1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
54 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55 ;; operand 0 is the memory address to scan.
56 ;; operand 1 is a register containing the value to scan for. The mode
57 ;; of the scas opcode will be the same as the mode of this operand.
58 ;; operand 2 is the known alignment of operand 0.
59 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60 ;; operand 0 is the argument for `sin'.
61 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62 ;; operand 0 is the argument for `cos'.
63 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64 ;; always SImode. operand 0 is the size of the stack allocation.
65 ;; 4 This is the source of a fake SET of the frame pointer which is used to
66 ;; prevent insns referencing it being scheduled across the initial
67 ;; decrement of the stack pointer.
68 ;; 5 This is a `bsf' operation.
69 ;; 6 This is the @GOT offset of a PIC address.
70 ;; 7 This is the @GOTOFF offset of a PIC address.
71 ;; 8 This is a reference to a symbol's @PLT address.
72 ;; 9 This is an `fnstsw' operation.
73 ;; 10 This is a `sahf' operation.
74 ;; 11 This is a `fstcw' operation
75 ;; 12 This is behaviour of add when setting carry flag.
76 ;; 13 This is a `eh_return' placeholder.
78 ;; For SSE/MMX support:
79 ;; 30 This is `fix', guaranteed to be truncating.
80 ;; 31 This is a `emms' operation.
81 ;; 32 This is a `maskmov' operation.
82 ;; 33 This is a `movmsk' operation.
83 ;; 34 This is a `non-temporal' move.
84 ;; 35 This is a `prefetch' operation.
85 ;; 36 This is used to distinguish COMISS from UCOMISS.
86 ;; 37 This is a `ldmxcsr' operation.
87 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
88 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
89 ;; 40 This is a `stmxcsr' operation.
90 ;; 41 This is a `shuffle' operation.
91 ;; 42 This is a `rcp' operation.
92 ;; 43 This is a `rsqsrt' operation.
93 ;; 44 This is a `sfence' operation.
94 ;; 45 This is a noop to prevent excessive combiner cleverness.
95 ;; 46 This is a `femms' operation.
96 ;; 47 This is a `prefetch' (3DNow) operation.
97 ;; 48 This is a `prefetchw' operation.
98 ;; 49 This is a 'pavgusb' operation.
99 ;; 50 This is a `pfrcp' operation.
100 ;; 51 This is a `pfrcpit1' operation.
101 ;; 52 This is a `pfrcpit2' operation.
102 ;; 53 This is a `pfrsqrt' operation.
103 ;; 54 This is a `pfrsqrit1' operation.
105 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
108 ;; In C guard expressions, put expressions which may be compile-time
109 ;; constants first. This allows for better optimization. For
110 ;; example, write "TARGET_64BIT && reload_completed", not
111 ;; "reload_completed && TARGET_64BIT".
114 ;; Processor type. This attribute must exactly match the processor_type
115 ;; enumeration in i386.h.
116 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
117 (const (symbol_ref "ix86_cpu")))
119 ;; A basic instruction type. Refinements due to arguments to be
120 ;; provided in other attributes.
122 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
123 (const_string "other"))
125 ;; Main data type used by the insn
126 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
127 (const_string "unknown"))
129 ;; Set for i387 operations.
130 (define_attr "i387" ""
131 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
135 ;; The (bounding maximum) length of an instruction immediate.
136 (define_attr "length_immediate" ""
137 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
141 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
142 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
143 (eq_attr "type" "imov,test")
144 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
145 (eq_attr "type" "call")
146 (if_then_else (match_operand 0 "constant_call_address_operand" "")
149 (eq_attr "type" "callv")
150 (if_then_else (match_operand 1 "constant_call_address_operand" "")
153 (eq_attr "type" "ibr")
154 (if_then_else (and (ge (minus (match_dup 0) (pc))
156 (lt (minus (match_dup 0) (pc))
161 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
163 ;; The (bounding maximum) length of an instruction address.
164 (define_attr "length_address" ""
165 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
167 (and (eq_attr "type" "call")
168 (match_operand 1 "constant_call_address_operand" ""))
170 (and (eq_attr "type" "callv")
171 (match_operand 1 "constant_call_address_operand" ""))
174 (symbol_ref "ix86_attr_length_address_default (insn)")))
176 ;; Set when length prefix is used.
177 (define_attr "prefix_data16" ""
178 (if_then_else (eq_attr "mode" "HI")
182 ;; Set when string REP prefix is used.
183 (define_attr "prefix_rep" "" (const_int 0))
185 ;; Set when 0f opcode prefix is used.
186 (define_attr "prefix_0f" ""
187 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
191 ;; Set when modrm byte is used.
192 (define_attr "modrm" ""
193 (cond [(eq_attr "type" "str,cld")
197 (and (eq_attr "type" "incdec")
198 (ior (match_operand:SI 1 "register_operand" "")
199 (match_operand:HI 1 "register_operand" "")))
201 (and (eq_attr "type" "push")
202 (not (match_operand 1 "memory_operand" "")))
204 (and (eq_attr "type" "pop")
205 (not (match_operand 0 "memory_operand" "")))
207 (and (eq_attr "type" "imov")
208 (and (match_operand 0 "register_operand" "")
209 (match_operand 1 "immediate_operand" "")))
214 ;; The (bounding maximum) length of an instruction in bytes.
215 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
216 ;; to split it and compute proper length as for other insns.
217 (define_attr "length" ""
218 (cond [(eq_attr "type" "other,multi,fistp")
221 (plus (plus (attr "modrm")
222 (plus (attr "prefix_0f")
225 (plus (attr "prefix_rep")
226 (plus (attr "prefix_data16")
227 (plus (attr "length_immediate")
228 (attr "length_address")))))))
230 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
231 ;; `store' if there is a simple memory reference therein, or `unknown'
232 ;; if the instruction is complex.
234 (define_attr "memory" "none,load,store,both,unknown"
235 (cond [(eq_attr "type" "other,multi,str")
236 (const_string "unknown")
237 (eq_attr "type" "lea,fcmov,fpspc,cld")
238 (const_string "none")
239 (eq_attr "type" "fistp")
240 (const_string "both")
241 (eq_attr "type" "push")
242 (if_then_else (match_operand 1 "memory_operand" "")
243 (const_string "both")
244 (const_string "store"))
245 (eq_attr "type" "pop,setcc")
246 (if_then_else (match_operand 0 "memory_operand" "")
247 (const_string "both")
248 (const_string "load"))
249 (eq_attr "type" "icmp,test")
250 (if_then_else (ior (match_operand 0 "memory_operand" "")
251 (match_operand 1 "memory_operand" ""))
252 (const_string "load")
253 (const_string "none"))
254 (eq_attr "type" "ibr")
255 (if_then_else (match_operand 0 "memory_operand" "")
256 (const_string "load")
257 (const_string "none"))
258 (eq_attr "type" "call")
259 (if_then_else (match_operand 0 "constant_call_address_operand" "")
260 (const_string "none")
261 (const_string "load"))
262 (eq_attr "type" "callv")
263 (if_then_else (match_operand 1 "constant_call_address_operand" "")
264 (const_string "none")
265 (const_string "load"))
266 (and (eq_attr "type" "alu1,negnot")
267 (match_operand 1 "memory_operand" ""))
268 (const_string "both")
269 (and (match_operand 0 "memory_operand" "")
270 (match_operand 1 "memory_operand" ""))
271 (const_string "both")
272 (match_operand 0 "memory_operand" "")
273 (const_string "store")
274 (match_operand 1 "memory_operand" "")
275 (const_string "load")
276 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
277 (match_operand 2 "memory_operand" ""))
278 (const_string "load")
279 (and (eq_attr "type" "icmov")
280 (match_operand 3 "memory_operand" ""))
281 (const_string "load")
283 (const_string "none")))
285 ;; Indicates if an instruction has both an immediate and a displacement.
287 (define_attr "imm_disp" "false,true,unknown"
288 (cond [(eq_attr "type" "other,multi")
289 (const_string "unknown")
290 (and (eq_attr "type" "icmp,test,imov")
291 (and (match_operand 0 "memory_displacement_operand" "")
292 (match_operand 1 "immediate_operand" "")))
293 (const_string "true")
294 (and (eq_attr "type" "alu,ishift,imul,idiv")
295 (and (match_operand 0 "memory_displacement_operand" "")
296 (match_operand 2 "immediate_operand" "")))
297 (const_string "true")
299 (const_string "false")))
301 ;; Indicates if an FP operation has an integer source.
303 (define_attr "fp_int_src" "false,true"
304 (const_string "false"))
306 ;; Describe a user's asm statement.
307 (define_asm_attributes
308 [(set_attr "length" "128")
309 (set_attr "type" "multi")])
311 ;; Pentium Scheduling
313 ;; The Pentium is an in-order core with two integer pipelines.
315 ;; True for insns that behave like prefixed insns on the Pentium.
316 (define_attr "pent_prefix" "false,true"
317 (if_then_else (ior (eq_attr "prefix_0f" "1")
318 (ior (eq_attr "prefix_data16" "1")
319 (eq_attr "prefix_rep" "1")))
320 (const_string "true")
321 (const_string "false")))
323 ;; Categorize how an instruction slots.
325 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
326 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
327 ;; rules, because it results in noticeably better code on non-MMX Pentium
328 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
329 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
331 (define_attr "pent_pair" "uv,pu,pv,np"
332 (cond [(eq_attr "imm_disp" "true")
334 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
335 (and (eq_attr "type" "pop,push")
336 (eq_attr "memory" "!both")))
337 (if_then_else (eq_attr "pent_prefix" "true")
340 (eq_attr "type" "ibr")
342 (and (eq_attr "type" "ishift")
343 (match_operand 2 "const_int_operand" ""))
345 (and (eq_attr "type" "call")
346 (match_operand 0 "constant_call_address_operand" ""))
348 (and (eq_attr "type" "callv")
349 (match_operand 1 "constant_call_address_operand" ""))
352 (const_string "np")))
354 ;; Rough readiness numbers. Fine tuning happens in i386.c.
356 ;; u describes pipe U
357 ;; v describes pipe V
358 ;; uv describes either pipe U or V for those that can issue to either
359 ;; np describes not paring
361 ;; fpm describes fp insns of different types are not pipelined.
363 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
365 (define_function_unit "pent_np" 1 0
366 (and (eq_attr "cpu" "pentium")
367 (eq_attr "type" "imul"))
370 (define_function_unit "pent_mul" 1 1
371 (and (eq_attr "cpu" "pentium")
372 (eq_attr "type" "imul"))
375 ;; Rep movs takes minimally 12 cycles.
376 (define_function_unit "pent_np" 1 0
377 (and (eq_attr "cpu" "pentium")
378 (eq_attr "type" "str"))
381 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
382 (define_function_unit "pent_np" 1 0
383 (and (eq_attr "cpu" "pentium")
384 (eq_attr "type" "idiv"))
387 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
388 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
389 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
390 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
391 ; like normal fp operation and fist takes 6 cycles.
393 (define_function_unit "fpu" 1 0
394 (and (eq_attr "cpu" "pentium")
395 (and (eq_attr "type" "fmov")
396 (and (eq_attr "memory" "load,store")
397 (eq_attr "mode" "XF"))))
400 (define_function_unit "pent_np" 1 0
401 (and (eq_attr "cpu" "pentium")
402 (and (eq_attr "type" "fmov")
403 (and (eq_attr "memory" "load,store")
404 (eq_attr "mode" "XF"))))
407 (define_function_unit "fpu" 1 0
408 (and (eq_attr "cpu" "pentium")
409 (and (eq_attr "type" "fmov")
410 (ior (match_operand 1 "immediate_operand" "")
411 (eq_attr "memory" "store"))))
414 (define_function_unit "pent_np" 1 0
415 (and (eq_attr "cpu" "pentium")
416 (and (eq_attr "type" "fmov")
417 (ior (match_operand 1 "immediate_operand" "")
418 (eq_attr "memory" "store"))))
421 (define_function_unit "pent_np" 1 0
422 (and (eq_attr "cpu" "pentium")
423 (eq_attr "type" "cld"))
426 (define_function_unit "fpu" 1 0
427 (and (eq_attr "cpu" "pentium")
428 (and (eq_attr "type" "fmov")
429 (eq_attr "memory" "none,load")))
432 ; Read/Modify/Write instructions usually take 3 cycles.
433 (define_function_unit "pent_u" 1 0
434 (and (eq_attr "cpu" "pentium")
435 (and (eq_attr "type" "alu,alu1,ishift")
436 (and (eq_attr "pent_pair" "pu")
437 (eq_attr "memory" "both"))))
440 (define_function_unit "pent_uv" 2 0
441 (and (eq_attr "cpu" "pentium")
442 (and (eq_attr "type" "alu,alu1,ishift")
443 (and (eq_attr "pent_pair" "!np")
444 (eq_attr "memory" "both"))))
447 (define_function_unit "pent_np" 1 0
448 (and (eq_attr "cpu" "pentium")
449 (and (eq_attr "type" "alu,alu1,negnot,ishift")
450 (and (eq_attr "pent_pair" "np")
451 (eq_attr "memory" "both"))))
454 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
455 (define_function_unit "pent_u" 1 0
456 (and (eq_attr "cpu" "pentium")
457 (and (eq_attr "type" "alu,ishift")
458 (and (eq_attr "pent_pair" "pu")
459 (eq_attr "memory" "load,store"))))
462 (define_function_unit "pent_uv" 2 0
463 (and (eq_attr "cpu" "pentium")
464 (and (eq_attr "type" "alu,ishift")
465 (and (eq_attr "pent_pair" "!np")
466 (eq_attr "memory" "load,store"))))
469 (define_function_unit "pent_np" 1 0
470 (and (eq_attr "cpu" "pentium")
471 (and (eq_attr "type" "alu,ishift")
472 (and (eq_attr "pent_pair" "np")
473 (eq_attr "memory" "load,store"))))
476 ; Insns w/o memory operands and move instructions usually take one cycle.
477 (define_function_unit "pent_u" 1 0
478 (and (eq_attr "cpu" "pentium")
479 (eq_attr "pent_pair" "pu"))
482 (define_function_unit "pent_v" 1 0
483 (and (eq_attr "cpu" "pentium")
484 (eq_attr "pent_pair" "pv"))
487 (define_function_unit "pent_uv" 2 0
488 (and (eq_attr "cpu" "pentium")
489 (eq_attr "pent_pair" "!np"))
492 (define_function_unit "pent_np" 1 0
493 (and (eq_attr "cpu" "pentium")
494 (eq_attr "pent_pair" "np"))
497 ; Pairable insns only conflict with other non-pairable insns.
498 (define_function_unit "pent_np" 1 0
499 (and (eq_attr "cpu" "pentium")
500 (and (eq_attr "type" "alu,alu1,ishift")
501 (and (eq_attr "pent_pair" "!np")
502 (eq_attr "memory" "both"))))
504 [(eq_attr "pent_pair" "np")])
506 (define_function_unit "pent_np" 1 0
507 (and (eq_attr "cpu" "pentium")
508 (and (eq_attr "type" "alu,alu1,ishift")
509 (and (eq_attr "pent_pair" "!np")
510 (eq_attr "memory" "load,store"))))
512 [(eq_attr "pent_pair" "np")])
514 (define_function_unit "pent_np" 1 0
515 (and (eq_attr "cpu" "pentium")
516 (eq_attr "pent_pair" "!np"))
518 [(eq_attr "pent_pair" "np")])
520 ; Floating point instructions usually blocks cycle longer when combined with
521 ; integer instructions, because of the inpaired fxch instruction.
522 (define_function_unit "pent_np" 1 0
523 (and (eq_attr "cpu" "pentium")
524 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp"))
526 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp")])
528 (define_function_unit "fpu" 1 0
529 (and (eq_attr "cpu" "pentium")
530 (eq_attr "type" "fcmp,fxch,fsgn"))
533 ; Addition takes 3 cycles; assume other random cruft does as well.
534 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
535 (define_function_unit "fpu" 1 0
536 (and (eq_attr "cpu" "pentium")
537 (eq_attr "type" "fop,fop1,fistp"))
540 ; Multiplication takes 3 cycles and is only half pipelined.
541 (define_function_unit "fpu" 1 0
542 (and (eq_attr "cpu" "pentium")
543 (eq_attr "type" "fmul"))
546 (define_function_unit "pent_mul" 1 1
547 (and (eq_attr "cpu" "pentium")
548 (eq_attr "type" "fmul"))
551 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
552 ; They can overlap with integer insns. Only the last two cycles can overlap
553 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
554 ; Only last two cycles of fsin/fcos can overlap with other instructions.
555 (define_function_unit "fpu" 1 0
556 (and (eq_attr "cpu" "pentium")
557 (eq_attr "type" "fdiv"))
560 (define_function_unit "pent_mul" 1 1
561 (and (eq_attr "cpu" "pentium")
562 (eq_attr "type" "fdiv"))
565 (define_function_unit "fpu" 1 0
566 (and (eq_attr "cpu" "pentium")
567 (eq_attr "type" "fpspc"))
570 (define_function_unit "pent_mul" 1 1
571 (and (eq_attr "cpu" "pentium")
572 (eq_attr "type" "fpspc"))
575 ;; Pentium Pro/PII Scheduling
577 ;; The PPro has an out-of-order core, but the instruction decoders are
578 ;; naturally in-order and asymmetric. We get best performance by scheduling
579 ;; for the decoders, for in doing so we give the oo execution unit the
582 ;; Categorize how many uops an ia32 instruction evaluates to:
583 ;; one -- an instruction with 1 uop can be decoded by any of the
585 ;; few -- an instruction with 1 to 4 uops can be decoded only by
587 ;; many -- a complex instruction may take an unspecified number of
588 ;; cycles to decode in decoder 0.
590 (define_attr "ppro_uops" "one,few,many"
591 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
592 (const_string "many")
593 (eq_attr "type" "icmov,fcmov,str,cld")
595 (eq_attr "type" "imov")
596 (if_then_else (eq_attr "memory" "store,both")
598 (const_string "one"))
599 (eq_attr "memory" "!none")
602 (const_string "one")))
604 ;; Rough readiness numbers. Fine tuning happens in i386.c.
606 ;; p0 describes port 0.
607 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
608 ;; p2 describes port 2 for loads.
609 ;; p34 describes ports 3 and 4 for stores.
610 ;; fpu describes the fpu accessed via port 0.
611 ;; ??? It is less than clear if there are separate fadd and fmul units
612 ;; that could operate in parallel.
614 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
616 (define_function_unit "ppro_p0" 1 0
617 (and (eq_attr "cpu" "pentiumpro")
618 (eq_attr "type" "ishift,lea,ibr,cld"))
621 (define_function_unit "ppro_p0" 1 0
622 (and (eq_attr "cpu" "pentiumpro")
623 (eq_attr "type" "imul"))
626 ;; ??? Does the divider lock out the pipe while it works,
627 ;; or is there a disconnected unit?
628 (define_function_unit "ppro_p0" 1 0
629 (and (eq_attr "cpu" "pentiumpro")
630 (eq_attr "type" "idiv"))
633 (define_function_unit "ppro_p0" 1 0
634 (and (eq_attr "cpu" "pentiumpro")
635 (eq_attr "type" "fop,fop1,fsgn,fistp"))
638 (define_function_unit "ppro_p0" 1 0
639 (and (eq_attr "cpu" "pentiumpro")
640 (eq_attr "type" "fcmov"))
643 (define_function_unit "ppro_p0" 1 0
644 (and (eq_attr "cpu" "pentiumpro")
645 (eq_attr "type" "fcmp"))
648 (define_function_unit "ppro_p0" 1 0
649 (and (eq_attr "cpu" "pentiumpro")
650 (eq_attr "type" "fmov"))
653 (define_function_unit "ppro_p0" 1 0
654 (and (eq_attr "cpu" "pentiumpro")
655 (eq_attr "type" "fmul"))
658 (define_function_unit "ppro_p0" 1 0
659 (and (eq_attr "cpu" "pentiumpro")
660 (eq_attr "type" "fdiv,fpspc"))
663 (define_function_unit "ppro_p01" 2 0
664 (and (eq_attr "cpu" "pentiumpro")
665 (eq_attr "type" "!imov,fmov"))
668 (define_function_unit "ppro_p01" 2 0
669 (and (and (eq_attr "cpu" "pentiumpro")
670 (eq_attr "type" "imov,fmov"))
671 (eq_attr "memory" "none"))
674 (define_function_unit "ppro_p2" 1 0
675 (and (eq_attr "cpu" "pentiumpro")
676 (ior (eq_attr "type" "pop")
677 (eq_attr "memory" "load,both")))
680 (define_function_unit "ppro_p34" 1 0
681 (and (eq_attr "cpu" "pentiumpro")
682 (ior (eq_attr "type" "push")
683 (eq_attr "memory" "store,both")))
686 (define_function_unit "fpu" 1 0
687 (and (eq_attr "cpu" "pentiumpro")
688 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov,fistp"))
691 (define_function_unit "fpu" 1 0
692 (and (eq_attr "cpu" "pentiumpro")
693 (eq_attr "type" "fmul"))
696 (define_function_unit "fpu" 1 0
697 (and (eq_attr "cpu" "pentiumpro")
698 (eq_attr "type" "fdiv,fpspc"))
701 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
702 (define_function_unit "fpu" 1 0
703 (and (eq_attr "cpu" "pentiumpro")
704 (eq_attr "type" "imul"))
707 ;; AMD K6/K6-2 Scheduling
709 ;; The K6 has similar architecture to PPro. Important difference is, that
710 ;; there are only two decoders and they seems to be much slower than execution
711 ;; units. So we have to pay much more attention to proper decoding for
712 ;; schedulers. We share most of scheduler code for PPro in i386.c
714 ;; The fp unit is not pipelined and do one operation per two cycles including
717 ;; alu describes both ALU units (ALU-X and ALU-Y).
718 ;; alux describes X alu unit
719 ;; fpu describes FPU unit
720 ;; load describes load unit.
721 ;; branch describes branch unit.
722 ;; store decsribes store unit. This unit is not modelled completely and only
723 ;; used to model lea operation. Otherwise it lie outside of the critical
726 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
728 ;; The decoder specification is in the PPro section above!
730 ;; Shift instructions and certain arithmetic are issued only to X pipe.
731 (define_function_unit "k6_alux" 1 0
732 (and (eq_attr "cpu" "k6")
733 (eq_attr "type" "ishift,alu1,negnot,cld"))
736 ;; The QI mode arithmetic is issued to X pipe only.
737 (define_function_unit "k6_alux" 1 0
738 (and (eq_attr "cpu" "k6")
739 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
740 (match_operand:QI 0 "general_operand" "")))
743 (define_function_unit "k6_alu" 2 0
744 (and (eq_attr "cpu" "k6")
745 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
748 (define_function_unit "k6_alu" 2 0
749 (and (eq_attr "cpu" "k6")
750 (and (eq_attr "type" "imov")
751 (eq_attr "memory" "none")))
754 (define_function_unit "k6_branch" 1 0
755 (and (eq_attr "cpu" "k6")
756 (eq_attr "type" "call,callv,ibr"))
759 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
760 (define_function_unit "k6_load" 1 0
761 (and (eq_attr "cpu" "k6")
762 (ior (eq_attr "type" "pop")
763 (eq_attr "memory" "load,both")))
766 (define_function_unit "k6_load" 1 0
767 (and (eq_attr "cpu" "k6")
768 (and (eq_attr "type" "str")
769 (eq_attr "memory" "load,both")))
772 ;; Lea have two instructions, so latency is probably 2
773 (define_function_unit "k6_store" 1 0
774 (and (eq_attr "cpu" "k6")
775 (eq_attr "type" "lea"))
778 (define_function_unit "k6_store" 1 0
779 (and (eq_attr "cpu" "k6")
780 (eq_attr "type" "str"))
783 (define_function_unit "k6_store" 1 0
784 (and (eq_attr "cpu" "k6")
785 (ior (eq_attr "type" "push")
786 (eq_attr "memory" "store,both")))
789 (define_function_unit "k6_fpu" 1 1
790 (and (eq_attr "cpu" "k6")
791 (eq_attr "type" "fop,fop1,fmov,fcmp,fistp"))
794 (define_function_unit "k6_fpu" 1 1
795 (and (eq_attr "cpu" "k6")
796 (eq_attr "type" "fmul"))
800 (define_function_unit "k6_fpu" 1 1
801 (and (eq_attr "cpu" "k6")
802 (eq_attr "type" "fdiv,fpspc"))
805 (define_function_unit "k6_alu" 2 0
806 (and (eq_attr "cpu" "k6")
807 (eq_attr "type" "imul"))
810 (define_function_unit "k6_alux" 1 0
811 (and (eq_attr "cpu" "k6")
812 (eq_attr "type" "imul"))
816 (define_function_unit "k6_alu" 2 0
817 (and (eq_attr "cpu" "k6")
818 (eq_attr "type" "idiv"))
821 (define_function_unit "k6_alux" 1 0
822 (and (eq_attr "cpu" "k6")
823 (eq_attr "type" "idiv"))
826 ;; AMD Athlon Scheduling
828 ;; The Athlon does contain three pipelined FP units, three integer units and
829 ;; three address generation units.
831 ;; The predecode logic is determining boundaries of instructions in the 64
832 ;; byte cache line. So the cache line straddling problem of K6 might be issue
833 ;; here as well, but it is not noted in the documentation.
835 ;; Three DirectPath instructions decoders and only one VectorPath decoder
836 ;; is available. They can decode three DirectPath instructions or one VectorPath
837 ;; instruction per cycle.
838 ;; Decoded macro instructions are then passed to 72 entry instruction control
840 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
842 ;; The load/store queue unit is not attached to the schedulers but
843 ;; communicates with all the execution units separately instead.
845 (define_attr "athlon_decode" "direct,vector"
846 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
847 (const_string "vector")
848 (and (eq_attr "type" "push")
849 (match_operand 1 "memory_operand" ""))
850 (const_string "vector")
851 (and (eq_attr "type" "fmov")
852 (and (eq_attr "memory" "load,store")
853 (eq_attr "mode" "XF")))
854 (const_string "vector")]
855 (const_string "direct")))
857 (define_function_unit "athlon_vectordec" 1 0
858 (and (eq_attr "cpu" "athlon")
859 (eq_attr "athlon_decode" "vector"))
862 (define_function_unit "athlon_directdec" 3 0
863 (and (eq_attr "cpu" "athlon")
864 (eq_attr "athlon_decode" "direct"))
867 (define_function_unit "athlon_vectordec" 1 0
868 (and (eq_attr "cpu" "athlon")
869 (eq_attr "athlon_decode" "direct"))
870 1 1 [(eq_attr "athlon_decode" "vector")])
872 (define_function_unit "athlon_ieu" 3 0
873 (and (eq_attr "cpu" "athlon")
874 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
877 (define_function_unit "athlon_ieu" 3 0
878 (and (eq_attr "cpu" "athlon")
879 (eq_attr "type" "str"))
882 (define_function_unit "athlon_ieu" 3 0
883 (and (eq_attr "cpu" "athlon")
884 (eq_attr "type" "imul"))
887 (define_function_unit "athlon_ieu" 3 0
888 (and (eq_attr "cpu" "athlon")
889 (eq_attr "type" "idiv"))
892 (define_function_unit "athlon_muldiv" 1 0
893 (and (eq_attr "cpu" "athlon")
894 (eq_attr "type" "imul"))
897 (define_function_unit "athlon_muldiv" 1 0
898 (and (eq_attr "cpu" "athlon")
899 (eq_attr "type" "idiv"))
902 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
903 (cond [(eq_attr "type" "fop,fop1,fcmp,fistp")
905 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
907 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
908 (const_string "store")
909 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
911 (and (eq_attr "type" "fmov")
912 (ior (match_operand:SI 1 "register_operand" "")
913 (match_operand 1 "immediate_operand" "")))
914 (const_string "store")
915 (eq_attr "type" "fmov")
916 (const_string "muladd")]
917 (const_string "none")))
919 ;; We use latencies 1 for definitions. This is OK to model colisions
920 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
922 ;; fsin, fcos: 96-192
924 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
925 (define_function_unit "athlon_fp" 3 0
926 (and (eq_attr "cpu" "athlon")
927 (eq_attr "type" "fpspc"))
930 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
931 (define_function_unit "athlon_fp" 3 0
932 (and (eq_attr "cpu" "athlon")
933 (eq_attr "type" "fdiv"))
936 (define_function_unit "athlon_fp" 3 0
937 (and (eq_attr "cpu" "athlon")
938 (eq_attr "type" "fop,fop1,fmul,fistp"))
941 ;; XFmode loads are slow.
942 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
943 ;; there are no dependent instructions.
945 (define_function_unit "athlon_fp" 3 0
946 (and (eq_attr "cpu" "athlon")
947 (and (eq_attr "type" "fmov")
948 (and (eq_attr "memory" "load")
949 (eq_attr "mode" "XF"))))
952 (define_function_unit "athlon_fp" 3 0
953 (and (eq_attr "cpu" "athlon")
954 (eq_attr "type" "fmov,fsgn"))
957 ;; fcmp and ftst instructions
958 (define_function_unit "athlon_fp" 3 0
959 (and (eq_attr "cpu" "athlon")
960 (and (eq_attr "type" "fcmp")
961 (eq_attr "athlon_decode" "direct")))
964 ;; fcmpi instructions.
965 (define_function_unit "athlon_fp" 3 0
966 (and (eq_attr "cpu" "athlon")
967 (and (eq_attr "type" "fcmp")
968 (eq_attr "athlon_decode" "vector")))
971 (define_function_unit "athlon_fp" 3 0
972 (and (eq_attr "cpu" "athlon")
973 (eq_attr "type" "fcmov"))
976 (define_function_unit "athlon_fp_mul" 1 0
977 (and (eq_attr "cpu" "athlon")
978 (eq_attr "athlon_fpunits" "mul"))
981 (define_function_unit "athlon_fp_add" 1 0
982 (and (eq_attr "cpu" "athlon")
983 (eq_attr "athlon_fpunits" "add"))
986 (define_function_unit "athlon_fp_muladd" 2 0
987 (and (eq_attr "cpu" "athlon")
988 (eq_attr "athlon_fpunits" "muladd,mul,add"))
991 (define_function_unit "athlon_fp_store" 1 0
992 (and (eq_attr "cpu" "athlon")
993 (eq_attr "athlon_fpunits" "store"))
996 ;; We don't need to model the Address Generation Unit, since we don't model
997 ;; the re-order buffer yet and thus we never schedule more than three operations
998 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
999 ;; decoders independently on the functional units.
1001 ;(define_function_unit "athlon_agu" 3 0
1002 ; (and (eq_attr "cpu" "athlon")
1003 ; (and (eq_attr "memory" "!none")
1004 ; (eq_attr "athlon_fpunits" "none")))
1007 ;; Model load unit to avoid too long sequences of loads. We don't need to
1008 ;; model store queue, since it is hardly going to be bottleneck.
1010 (define_function_unit "athlon_load" 2 0
1011 (and (eq_attr "cpu" "athlon")
1012 (eq_attr "memory" "load,both"))
1016 ;; Compare instructions.
1018 ;; All compare insns have expanders that save the operands away without
1019 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1020 ;; after the cmp) will actually emit the cmpM.
1022 (define_expand "cmpdi"
1024 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1025 (match_operand:DI 1 "x86_64_general_operand" "")))]
1028 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1029 operands[0] = force_reg (DImode, operands[0]);
1030 ix86_compare_op0 = operands[0];
1031 ix86_compare_op1 = operands[1];
1035 (define_expand "cmpsi"
1037 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1038 (match_operand:SI 1 "general_operand" "")))]
1041 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1042 operands[0] = force_reg (SImode, operands[0]);
1043 ix86_compare_op0 = operands[0];
1044 ix86_compare_op1 = operands[1];
1048 (define_expand "cmphi"
1050 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
1051 (match_operand:HI 1 "general_operand" "")))]
1054 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1055 operands[0] = force_reg (HImode, operands[0]);
1056 ix86_compare_op0 = operands[0];
1057 ix86_compare_op1 = operands[1];
1061 (define_expand "cmpqi"
1063 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
1064 (match_operand:QI 1 "general_operand" "")))]
1065 "TARGET_QIMODE_MATH"
1067 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1068 operands[0] = force_reg (QImode, operands[0]);
1069 ix86_compare_op0 = operands[0];
1070 ix86_compare_op1 = operands[1];
1074 (define_insn "cmpdi_ccno_1_rex64"
1076 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
1077 (match_operand:DI 1 "const0_operand" "n,n")))]
1078 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
1080 test{q}\t{%0, %0|%0, %0}
1081 cmp{q}\t{%1, %0|%0, %1}"
1082 [(set_attr "type" "test,icmp")
1083 (set_attr "length_immediate" "0,1")
1084 (set_attr "mode" "DI")])
1086 (define_insn "*cmpdi_minus_1_rex64"
1088 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
1089 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
1091 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
1092 "cmp{q}\t{%1, %0|%0, %1}"
1093 [(set_attr "type" "icmp")
1094 (set_attr "mode" "DI")])
1096 (define_expand "cmpdi_1_rex64"
1098 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1099 (match_operand:DI 1 "general_operand" "")))]
1103 (define_insn "cmpdi_1_insn_rex64"
1105 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
1106 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
1107 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1108 "cmp{q}\t{%1, %0|%0, %1}"
1109 [(set_attr "type" "icmp")
1110 (set_attr "mode" "DI")])
1113 (define_insn "*cmpsi_ccno_1"
1115 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1116 (match_operand:SI 1 "const0_operand" "n,n")))]
1117 "ix86_match_ccmode (insn, CCNOmode)"
1119 test{l}\t{%0, %0|%0, %0}
1120 cmp{l}\t{%1, %0|%0, %1}"
1121 [(set_attr "type" "test,icmp")
1122 (set_attr "length_immediate" "0,1")
1123 (set_attr "mode" "SI")])
1125 (define_insn "*cmpsi_minus_1"
1127 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1128 (match_operand:SI 1 "general_operand" "ri,mr"))
1130 "ix86_match_ccmode (insn, CCGOCmode)"
1131 "cmp{l}\t{%1, %0|%0, %1}"
1132 [(set_attr "type" "icmp")
1133 (set_attr "mode" "SI")])
1135 (define_expand "cmpsi_1"
1137 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1138 (match_operand:SI 1 "general_operand" "ri,mr")))]
1142 (define_insn "*cmpsi_1_insn"
1144 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1145 (match_operand:SI 1 "general_operand" "ri,mr")))]
1146 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1147 && ix86_match_ccmode (insn, CCmode)"
1148 "cmp{l}\t{%1, %0|%0, %1}"
1149 [(set_attr "type" "icmp")
1150 (set_attr "mode" "SI")])
1152 (define_insn "*cmphi_ccno_1"
1154 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1155 (match_operand:HI 1 "const0_operand" "n,n")))]
1156 "ix86_match_ccmode (insn, CCNOmode)"
1158 test{w}\t{%0, %0|%0, %0}
1159 cmp{w}\t{%1, %0|%0, %1}"
1160 [(set_attr "type" "test,icmp")
1161 (set_attr "length_immediate" "0,1")
1162 (set_attr "mode" "HI")])
1164 (define_insn "*cmphi_minus_1"
1166 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1167 (match_operand:HI 1 "general_operand" "ri,mr"))
1169 "ix86_match_ccmode (insn, CCGOCmode)"
1170 "cmp{w}\t{%1, %0|%0, %1}"
1171 [(set_attr "type" "icmp")
1172 (set_attr "mode" "HI")])
1174 (define_insn "*cmphi_1"
1176 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1177 (match_operand:HI 1 "general_operand" "ri,mr")))]
1178 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1179 && ix86_match_ccmode (insn, CCmode)"
1180 "cmp{w}\t{%1, %0|%0, %1}"
1181 [(set_attr "type" "icmp")
1182 (set_attr "mode" "HI")])
1184 (define_insn "*cmpqi_ccno_1"
1186 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1187 (match_operand:QI 1 "const0_operand" "n,n")))]
1188 "ix86_match_ccmode (insn, CCNOmode)"
1190 test{b}\t{%0, %0|%0, %0}
1191 cmp{b}\t{$0, %0|%0, 0}"
1192 [(set_attr "type" "test,icmp")
1193 (set_attr "length_immediate" "0,1")
1194 (set_attr "mode" "QI")])
1196 (define_insn "*cmpqi_1"
1198 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1199 (match_operand:QI 1 "general_operand" "qi,mq")))]
1200 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1201 && ix86_match_ccmode (insn, CCmode)"
1202 "cmp{b}\t{%1, %0|%0, %1}"
1203 [(set_attr "type" "icmp")
1204 (set_attr "mode" "QI")])
1206 (define_insn "*cmpqi_minus_1"
1208 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1209 (match_operand:QI 1 "general_operand" "qi,mq"))
1211 "ix86_match_ccmode (insn, CCGOCmode)"
1212 "cmp{b}\t{%1, %0|%0, %1}"
1213 [(set_attr "type" "icmp")
1214 (set_attr "mode" "QI")])
1216 (define_insn "*cmpqi_ext_1"
1219 (match_operand:QI 0 "general_operand" "Qm")
1222 (match_operand 1 "ext_register_operand" "Q")
1224 (const_int 8)) 0)))]
1225 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1226 "cmp{b}\t{%h1, %0|%0, %h1}"
1227 [(set_attr "type" "icmp")
1228 (set_attr "mode" "QI")])
1230 (define_insn "*cmpqi_ext_1_rex64"
1233 (match_operand:QI 0 "register_operand" "Q")
1236 (match_operand 1 "ext_register_operand" "Q")
1238 (const_int 8)) 0)))]
1239 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1240 "cmp{b}\t{%h1, %0|%0, %h1}"
1241 [(set_attr "type" "icmp")
1242 (set_attr "mode" "QI")])
1244 (define_insn "*cmpqi_ext_2"
1249 (match_operand 0 "ext_register_operand" "Q")
1252 (match_operand:QI 1 "const0_operand" "n")))]
1253 "ix86_match_ccmode (insn, CCNOmode)"
1255 [(set_attr "type" "test")
1256 (set_attr "length_immediate" "0")
1257 (set_attr "mode" "QI")])
1259 (define_expand "cmpqi_ext_3"
1264 (match_operand 0 "ext_register_operand" "")
1267 (match_operand:QI 1 "general_operand" "")))]
1271 (define_insn "cmpqi_ext_3_insn"
1276 (match_operand 0 "ext_register_operand" "Q")
1279 (match_operand:QI 1 "general_operand" "Qmn")))]
1280 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1281 "cmp{b}\t{%1, %h0|%h0, %1}"
1282 [(set_attr "type" "icmp")
1283 (set_attr "mode" "QI")])
1285 (define_insn "cmpqi_ext_3_insn_rex64"
1290 (match_operand 0 "ext_register_operand" "Q")
1293 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1294 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1295 "cmp{b}\t{%1, %h0|%h0, %1}"
1296 [(set_attr "type" "icmp")
1297 (set_attr "mode" "QI")])
1299 (define_insn "*cmpqi_ext_4"
1304 (match_operand 0 "ext_register_operand" "Q")
1309 (match_operand 1 "ext_register_operand" "Q")
1311 (const_int 8)) 0)))]
1312 "ix86_match_ccmode (insn, CCmode)"
1313 "cmp{b}\t{%h1, %h0|%h0, %h1}"
1314 [(set_attr "type" "icmp")
1315 (set_attr "mode" "QI")])
1317 ;; These implement float point compares.
1318 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1319 ;; which would allow mix and match FP modes on the compares. Which is what
1320 ;; the old patterns did, but with many more of them.
1322 (define_expand "cmpxf"
1324 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1325 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1326 "!TARGET_64BIT && TARGET_80387"
1328 ix86_compare_op0 = operands[0];
1329 ix86_compare_op1 = operands[1];
1333 (define_expand "cmptf"
1335 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1336 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1339 ix86_compare_op0 = operands[0];
1340 ix86_compare_op1 = operands[1];
1344 (define_expand "cmpdf"
1346 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1347 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1348 "TARGET_80387 || TARGET_SSE2"
1350 ix86_compare_op0 = operands[0];
1351 ix86_compare_op1 = operands[1];
1355 (define_expand "cmpsf"
1357 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1358 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1359 "TARGET_80387 || TARGET_SSE"
1361 ix86_compare_op0 = operands[0];
1362 ix86_compare_op1 = operands[1];
1366 ;; FP compares, step 1:
1367 ;; Set the FP condition codes.
1369 ;; CCFPmode compare with exceptions
1370 ;; CCFPUmode compare with no exceptions
1372 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1373 ;; and that fp moves clobber the condition codes, and that there is
1374 ;; currently no way to describe this fact to reg-stack. So there are
1375 ;; no splitters yet for this.
1377 ;; %%% YIKES! This scheme does not retain a strong connection between
1378 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1379 ;; work! Only allow tos/mem with tos in op 0.
1381 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1382 ;; things aren't as bad as they sound...
1384 (define_insn "*cmpfp_0"
1385 [(set (match_operand:HI 0 "register_operand" "=a")
1387 [(compare:CCFP (match_operand 1 "register_operand" "f")
1388 (match_operand 2 "const0_operand" "X"))] 9))]
1390 && FLOAT_MODE_P (GET_MODE (operands[1]))
1391 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1393 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1394 return "ftst\;fnstsw\t%0\;fstp\t%y0";
1396 return "ftst\;fnstsw\t%0";
1398 [(set_attr "type" "multi")
1399 (set_attr "mode" "unknownfp")])
1401 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1402 ;; used to manage the reg stack popping would not be preserved.
1404 (define_insn "*cmpfp_2_sf"
1407 (match_operand:SF 0 "register_operand" "f")
1408 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1410 "* return output_fp_compare (insn, operands, 0, 0);"
1411 [(set_attr "type" "fcmp")
1412 (set_attr "mode" "SF")])
1414 (define_insn "*cmpfp_2_sf_1"
1415 [(set (match_operand:HI 0 "register_operand" "=a")
1418 (match_operand:SF 1 "register_operand" "f")
1419 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1421 "* return output_fp_compare (insn, operands, 2, 0);"
1422 [(set_attr "type" "fcmp")
1423 (set_attr "mode" "SF")])
1425 (define_insn "*cmpfp_2_df"
1428 (match_operand:DF 0 "register_operand" "f")
1429 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1431 "* return output_fp_compare (insn, operands, 0, 0);"
1432 [(set_attr "type" "fcmp")
1433 (set_attr "mode" "DF")])
1435 (define_insn "*cmpfp_2_df_1"
1436 [(set (match_operand:HI 0 "register_operand" "=a")
1439 (match_operand:DF 1 "register_operand" "f")
1440 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1442 "* return output_fp_compare (insn, operands, 2, 0);"
1443 [(set_attr "type" "multi")
1444 (set_attr "mode" "DF")])
1446 (define_insn "*cmpfp_2_xf"
1449 (match_operand:XF 0 "register_operand" "f")
1450 (match_operand:XF 1 "register_operand" "f")))]
1451 "!TARGET_64BIT && TARGET_80387"
1452 "* return output_fp_compare (insn, operands, 0, 0);"
1453 [(set_attr "type" "fcmp")
1454 (set_attr "mode" "XF")])
1456 (define_insn "*cmpfp_2_tf"
1459 (match_operand:TF 0 "register_operand" "f")
1460 (match_operand:TF 1 "register_operand" "f")))]
1462 "* return output_fp_compare (insn, operands, 0, 0);"
1463 [(set_attr "type" "fcmp")
1464 (set_attr "mode" "XF")])
1466 (define_insn "*cmpfp_2_xf_1"
1467 [(set (match_operand:HI 0 "register_operand" "=a")
1470 (match_operand:XF 1 "register_operand" "f")
1471 (match_operand:XF 2 "register_operand" "f"))] 9))]
1472 "!TARGET_64BIT && TARGET_80387"
1473 "* return output_fp_compare (insn, operands, 2, 0);"
1474 [(set_attr "type" "multi")
1475 (set_attr "mode" "XF")])
1477 (define_insn "*cmpfp_2_tf_1"
1478 [(set (match_operand:HI 0 "register_operand" "=a")
1481 (match_operand:TF 1 "register_operand" "f")
1482 (match_operand:TF 2 "register_operand" "f"))] 9))]
1484 "* return output_fp_compare (insn, operands, 2, 0);"
1485 [(set_attr "type" "multi")
1486 (set_attr "mode" "XF")])
1488 (define_insn "*cmpfp_2u"
1489 [(set (reg:CCFPU 18)
1491 (match_operand 0 "register_operand" "f")
1492 (match_operand 1 "register_operand" "f")))]
1494 && FLOAT_MODE_P (GET_MODE (operands[0]))
1495 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1496 "* return output_fp_compare (insn, operands, 0, 1);"
1497 [(set_attr "type" "fcmp")
1498 (set_attr "mode" "unknownfp")])
1500 (define_insn "*cmpfp_2u_1"
1501 [(set (match_operand:HI 0 "register_operand" "=a")
1504 (match_operand 1 "register_operand" "f")
1505 (match_operand 2 "register_operand" "f"))] 9))]
1507 && FLOAT_MODE_P (GET_MODE (operands[1]))
1508 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1509 "* return output_fp_compare (insn, operands, 2, 1);"
1510 [(set_attr "type" "multi")
1511 (set_attr "mode" "unknownfp")])
1513 ;; Patterns to match the SImode-in-memory ficom instructions.
1515 ;; %%% Play games with accepting gp registers, as otherwise we have to
1516 ;; force them to memory during rtl generation, which is no good. We
1517 ;; can get rid of this once we teach reload to do memory input reloads
1520 (define_insn "*ficom_1"
1523 (match_operand 0 "register_operand" "f,f")
1524 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1525 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1526 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1529 ;; Split the not-really-implemented gp register case into a
1530 ;; push-op-pop sequence.
1532 ;; %%% This is most efficient, but am I gonna get in trouble
1533 ;; for separating cc0_setter and cc0_user?
1538 (match_operand:SF 0 "register_operand" "")
1539 (float (match_operand:SI 1 "register_operand" ""))))]
1540 "0 && TARGET_80387 && reload_completed"
1541 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1542 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1543 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1544 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1545 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1546 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1548 ;; FP compares, step 2
1549 ;; Move the fpsw to ax.
1551 (define_insn "x86_fnstsw_1"
1552 [(set (match_operand:HI 0 "register_operand" "=a")
1553 (unspec:HI [(reg 18)] 9))]
1556 [(set_attr "length" "2")
1557 (set_attr "mode" "SI")
1558 (set_attr "i387" "1")
1559 (set_attr "ppro_uops" "few")])
1561 ;; FP compares, step 3
1562 ;; Get ax into flags, general case.
1564 (define_insn "x86_sahf_1"
1566 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1569 [(set_attr "length" "1")
1570 (set_attr "athlon_decode" "vector")
1571 (set_attr "mode" "SI")
1572 (set_attr "ppro_uops" "one")])
1574 ;; Pentium Pro can do steps 1 through 3 in one go.
1576 (define_insn "*cmpfp_i"
1578 (compare:CCFP (match_operand 0 "register_operand" "f")
1579 (match_operand 1 "register_operand" "f")))]
1580 "TARGET_80387 && TARGET_CMOVE
1581 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1582 && FLOAT_MODE_P (GET_MODE (operands[0]))
1583 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1584 "* return output_fp_compare (insn, operands, 1, 0);"
1585 [(set_attr "type" "fcmp")
1586 (set_attr "mode" "unknownfp")
1587 (set_attr "athlon_decode" "vector")])
1589 (define_insn "*cmpfp_i_sse"
1591 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1592 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1594 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1595 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1596 "* return output_fp_compare (insn, operands, 1, 0);"
1597 [(set_attr "type" "fcmp,sse")
1598 (set_attr "mode" "unknownfp")
1599 (set_attr "athlon_decode" "vector")])
1601 (define_insn "*cmpfp_i_sse_only"
1603 (compare:CCFP (match_operand 0 "register_operand" "x")
1604 (match_operand 1 "nonimmediate_operand" "xm")))]
1605 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1606 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1607 "* return output_fp_compare (insn, operands, 1, 0);"
1608 [(set_attr "type" "sse")
1609 (set_attr "mode" "unknownfp")
1610 (set_attr "athlon_decode" "vector")])
1612 (define_insn "*cmpfp_iu"
1613 [(set (reg:CCFPU 17)
1614 (compare:CCFPU (match_operand 0 "register_operand" "f")
1615 (match_operand 1 "register_operand" "f")))]
1616 "TARGET_80387 && TARGET_CMOVE
1617 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1618 && FLOAT_MODE_P (GET_MODE (operands[0]))
1619 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1620 "* return output_fp_compare (insn, operands, 1, 1);"
1621 [(set_attr "type" "fcmp")
1622 (set_attr "mode" "unknownfp")
1623 (set_attr "athlon_decode" "vector")])
1625 (define_insn "*cmpfp_iu_sse"
1626 [(set (reg:CCFPU 17)
1627 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1628 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1630 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1631 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1632 "* return output_fp_compare (insn, operands, 1, 1);"
1633 [(set_attr "type" "fcmp,sse")
1634 (set_attr "mode" "unknownfp")
1635 (set_attr "athlon_decode" "vector")])
1637 (define_insn "*cmpfp_iu_sse_only"
1638 [(set (reg:CCFPU 17)
1639 (compare:CCFPU (match_operand 0 "register_operand" "x")
1640 (match_operand 1 "nonimmediate_operand" "xm")))]
1641 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1642 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1643 "* return output_fp_compare (insn, operands, 1, 1);"
1644 [(set_attr "type" "sse")
1645 (set_attr "mode" "unknownfp")
1646 (set_attr "athlon_decode" "vector")])
1648 ;; Move instructions.
1650 ;; General case of fullword move.
1652 (define_expand "movsi"
1653 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1654 (match_operand:SI 1 "general_operand" ""))]
1656 "ix86_expand_move (SImode, operands); DONE;")
1658 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1661 ;; %%% We don't use a post-inc memory reference because x86 is not a
1662 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1663 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1664 ;; targets without our curiosities, and it is just as easy to represent
1665 ;; this differently.
1667 (define_insn "*pushsi2"
1668 [(set (match_operand:SI 0 "push_operand" "=<")
1669 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1672 [(set_attr "type" "push")
1673 (set_attr "mode" "SI")])
1675 ;; For 64BIT abi we always round up to 8 bytes.
1676 (define_insn "*pushsi2_rex64"
1677 [(set (match_operand:SI 0 "push_operand" "=X")
1678 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1681 [(set_attr "type" "push")
1682 (set_attr "mode" "SI")])
1684 (define_insn "*pushsi2_prologue"
1685 [(set (match_operand:SI 0 "push_operand" "=<")
1686 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1687 (clobber (mem:BLK (scratch)))]
1690 [(set_attr "type" "push")
1691 (set_attr "mode" "SI")])
1693 (define_insn "*popsi1_epilogue"
1694 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1695 (mem:SI (reg:SI 7)))
1697 (plus:SI (reg:SI 7) (const_int 4)))
1698 (clobber (mem:BLK (scratch)))]
1701 [(set_attr "type" "pop")
1702 (set_attr "mode" "SI")])
1704 (define_insn "popsi1"
1705 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1706 (mem:SI (reg:SI 7)))
1708 (plus:SI (reg:SI 7) (const_int 4)))]
1711 [(set_attr "type" "pop")
1712 (set_attr "mode" "SI")])
1714 (define_insn "*movsi_xor"
1715 [(set (match_operand:SI 0 "register_operand" "=r")
1716 (match_operand:SI 1 "const0_operand" "i"))
1717 (clobber (reg:CC 17))]
1718 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1719 "xor{l}\t{%0, %0|%0, %0}"
1720 [(set_attr "type" "alu1")
1721 (set_attr "mode" "SI")
1722 (set_attr "length_immediate" "0")])
1724 (define_insn "*movsi_or"
1725 [(set (match_operand:SI 0 "register_operand" "=r")
1726 (match_operand:SI 1 "immediate_operand" "i"))
1727 (clobber (reg:CC 17))]
1728 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1729 && INTVAL (operands[1]) == -1
1730 && (TARGET_PENTIUM || optimize_size)"
1732 operands[1] = constm1_rtx;
1733 return "or{l}\t{%1, %0|%0, %1}";
1735 [(set_attr "type" "alu1")
1736 (set_attr "mode" "SI")
1737 (set_attr "length_immediate" "1")])
1739 (define_insn "*movsi_1"
1740 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1741 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1742 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1744 switch (get_attr_type (insn))
1747 if (get_attr_mode (insn) == TImode)
1748 return "movdqa\t{%1, %0|%0, %1}";
1749 return "movd\t{%1, %0|%0, %1}";
1752 return "movd\t{%1, %0|%0, %1}";
1755 return "lea{l}\t{%1, %0|%0, %1}";
1758 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1760 return "mov{l}\t{%1, %0|%0, %1}";
1764 (cond [(eq_attr "alternative" "4,5")
1765 (const_string "mmx")
1766 (eq_attr "alternative" "6,7,8")
1767 (const_string "sse")
1768 (and (ne (symbol_ref "flag_pic") (const_int 0))
1769 (match_operand:SI 1 "symbolic_operand" ""))
1770 (const_string "lea")
1772 (const_string "imov")))
1773 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1774 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1776 ;; Stores and loads of ax to arbitary constant address.
1777 ;; We fake an second form of instruction to force reload to load address
1778 ;; into register when rax is not available
1779 (define_insn "*movabssi_1_rex64"
1780 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1781 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1784 movabs{l}\t{%1, %P0|%P0, %1}
1785 mov{l}\t{%1, %a0|%a0, %1}
1786 movabs{l}\t{%1, %a0|%a0, %1}"
1787 [(set_attr "type" "imov")
1788 (set_attr "modrm" "0,*,*")
1789 (set_attr "length_address" "8,0,0")
1790 (set_attr "length_immediate" "0,*,*")
1791 (set_attr "memory" "store")
1792 (set_attr "mode" "SI")])
1794 (define_insn "*movabssi_2_rex64"
1795 [(set (match_operand:SI 0 "register_operand" "=a,r")
1796 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1799 movabs{l}\t{%P1, %0|%0, %P1}
1800 mov{l}\t{%a1, %0|%0, %a1}"
1801 [(set_attr "type" "imov")
1802 (set_attr "modrm" "0,*")
1803 (set_attr "length_address" "8,0")
1804 (set_attr "length_immediate" "0")
1805 (set_attr "memory" "load")
1806 (set_attr "mode" "SI")])
1808 (define_insn "*swapsi"
1809 [(set (match_operand:SI 0 "register_operand" "+r")
1810 (match_operand:SI 1 "register_operand" "+r"))
1815 [(set_attr "type" "imov")
1816 (set_attr "pent_pair" "np")
1817 (set_attr "athlon_decode" "vector")
1818 (set_attr "mode" "SI")
1819 (set_attr "modrm" "0")
1820 (set_attr "ppro_uops" "few")])
1822 (define_expand "movhi"
1823 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1824 (match_operand:HI 1 "general_operand" ""))]
1826 "ix86_expand_move (HImode, operands); DONE;")
1828 (define_insn "*pushhi2"
1829 [(set (match_operand:HI 0 "push_operand" "=<,<")
1830 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1833 push{w}\t{|WORD PTR }%1
1835 [(set_attr "type" "push")
1836 (set_attr "mode" "HI")])
1838 ;; For 64BIT abi we always round up to 8 bytes.
1839 (define_insn "*pushhi2_rex64"
1840 [(set (match_operand:HI 0 "push_operand" "=X")
1841 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1844 [(set_attr "type" "push")
1845 (set_attr "mode" "QI")])
1847 (define_insn "*movhi_1"
1848 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1849 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1850 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1852 switch (get_attr_type (insn))
1855 /* movzwl is faster than movw on p2 due to partial word stalls,
1856 though not as fast as an aligned movl. */
1857 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1859 if (get_attr_mode (insn) == MODE_SI)
1860 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1862 return "mov{w}\t{%1, %0|%0, %1}";
1866 (cond [(and (eq_attr "alternative" "0,1")
1867 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1869 (eq (symbol_ref "TARGET_HIMODE_MATH")
1871 (const_string "imov")
1872 (and (eq_attr "alternative" "2,3,4")
1873 (match_operand:HI 1 "aligned_operand" ""))
1874 (const_string "imov")
1875 (and (ne (symbol_ref "TARGET_MOVX")
1877 (eq_attr "alternative" "0,1,3,4"))
1878 (const_string "imovx")
1880 (const_string "imov")))
1882 (cond [(eq_attr "type" "imovx")
1884 (and (eq_attr "alternative" "2,3,4")
1885 (match_operand:HI 1 "aligned_operand" ""))
1887 (and (eq_attr "alternative" "0,1")
1888 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1890 (eq (symbol_ref "TARGET_HIMODE_MATH")
1894 (const_string "HI")))
1895 (set_attr "modrm" "0,*,*,0,*,*")])
1897 ;; Stores and loads of ax to arbitary constant address.
1898 ;; We fake an second form of instruction to force reload to load address
1899 ;; into register when rax is not available
1900 (define_insn "*movabshi_1_rex64"
1901 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1902 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1905 movabs{w}\t{%1, %P0|%P0, %1}
1906 mov{w}\t{%1, %a0|%a0, %1}
1907 movabs{w}\t{%1, %a0|%a0, %1}"
1908 [(set_attr "type" "imov")
1909 (set_attr "modrm" "0,*,*")
1910 (set_attr "length_address" "8,0,0")
1911 (set_attr "length_immediate" "0,*,*")
1912 (set_attr "memory" "store")
1913 (set_attr "mode" "HI")])
1915 (define_insn "*movabshi_2_rex64"
1916 [(set (match_operand:HI 0 "register_operand" "=a,r")
1917 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1920 movabs{w}\t{%P1, %0|%0, %P1}
1921 mov{w}\t{%a1, %0|%0, %a1}"
1922 [(set_attr "type" "imov")
1923 (set_attr "modrm" "0,*")
1924 (set_attr "length_address" "8,0")
1925 (set_attr "length_immediate" "0")
1926 (set_attr "memory" "load")
1927 (set_attr "mode" "HI")])
1929 (define_insn "*swaphi_1"
1930 [(set (match_operand:HI 0 "register_operand" "+r")
1931 (match_operand:HI 1 "register_operand" "+r"))
1934 "TARGET_PARTIAL_REG_STALL"
1936 [(set_attr "type" "imov")
1937 (set_attr "pent_pair" "np")
1938 (set_attr "mode" "HI")
1939 (set_attr "modrm" "0")
1940 (set_attr "ppro_uops" "few")])
1942 (define_insn "*swaphi_2"
1943 [(set (match_operand:HI 0 "register_operand" "+r")
1944 (match_operand:HI 1 "register_operand" "+r"))
1947 "! TARGET_PARTIAL_REG_STALL"
1949 [(set_attr "type" "imov")
1950 (set_attr "pent_pair" "np")
1951 (set_attr "mode" "SI")
1952 (set_attr "modrm" "0")
1953 (set_attr "ppro_uops" "few")])
1955 (define_expand "movstricthi"
1956 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1957 (match_operand:HI 1 "general_operand" ""))]
1958 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1960 /* Don't generate memory->memory moves, go through a register */
1961 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1962 operands[1] = force_reg (HImode, operands[1]);
1965 (define_insn "*movstricthi_1"
1966 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1967 (match_operand:HI 1 "general_operand" "rn,m"))]
1968 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1969 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1970 "mov{w}\t{%1, %0|%0, %1}"
1971 [(set_attr "type" "imov")
1972 (set_attr "mode" "HI")])
1974 (define_insn "*movstricthi_xor"
1975 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1976 (match_operand:HI 1 "const0_operand" "i"))
1977 (clobber (reg:CC 17))]
1979 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1980 "xor{w}\t{%0, %0|%0, %0}"
1981 [(set_attr "type" "alu1")
1982 (set_attr "mode" "HI")
1983 (set_attr "length_immediate" "0")])
1985 (define_expand "movqi"
1986 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1987 (match_operand:QI 1 "general_operand" ""))]
1989 "ix86_expand_move (QImode, operands); DONE;")
1991 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1992 ;; "push a byte". But actually we use pushw, which has the effect
1993 ;; of rounding the amount pushed up to a halfword.
1995 (define_insn "*pushqi2"
1996 [(set (match_operand:QI 0 "push_operand" "=X,X")
1997 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
2000 push{w}\t{|word ptr }%1
2002 [(set_attr "type" "push")
2003 (set_attr "mode" "HI")])
2005 ;; For 64BIT abi we always round up to 8 bytes.
2006 (define_insn "*pushqi2_rex64"
2007 [(set (match_operand:QI 0 "push_operand" "=X")
2008 (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
2011 [(set_attr "type" "push")
2012 (set_attr "mode" "QI")])
2014 ;; Situation is quite tricky about when to choose full sized (SImode) move
2015 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
2016 ;; partial register dependency machines (such as AMD Athlon), where QImode
2017 ;; moves issue extra dependency and for partial register stalls machines
2018 ;; that don't use QImode patterns (and QImode move cause stall on the next
2021 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
2022 ;; register stall machines with, where we use QImode instructions, since
2023 ;; partial register stall can be caused there. Then we use movzx.
2024 (define_insn "*movqi_1"
2025 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2026 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2027 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
2029 switch (get_attr_type (insn))
2032 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
2034 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
2036 if (get_attr_mode (insn) == MODE_SI)
2037 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2039 return "mov{b}\t{%1, %0|%0, %1}";
2043 (cond [(and (eq_attr "alternative" "3")
2044 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
2046 (eq (symbol_ref "TARGET_QIMODE_MATH")
2048 (const_string "imov")
2049 (eq_attr "alternative" "3,5")
2050 (const_string "imovx")
2051 (and (ne (symbol_ref "TARGET_MOVX")
2053 (eq_attr "alternative" "2"))
2054 (const_string "imovx")
2056 (const_string "imov")))
2058 (cond [(eq_attr "alternative" "3,4,5")
2060 (eq_attr "alternative" "6")
2062 (eq_attr "type" "imovx")
2064 (and (eq_attr "type" "imov")
2065 (and (eq_attr "alternative" "0,1,2")
2066 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
2069 ;; Avoid partial register stalls when not using QImode arithmetic
2070 (and (eq_attr "type" "imov")
2071 (and (eq_attr "alternative" "0,1,2")
2072 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
2074 (eq (symbol_ref "TARGET_QIMODE_MATH")
2078 (const_string "QI")))])
2080 (define_expand "reload_outqi"
2081 [(parallel [(match_operand:QI 0 "" "=m")
2082 (match_operand:QI 1 "register_operand" "r")
2083 (match_operand:QI 2 "register_operand" "=&q")])]
2087 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
2089 if (reg_overlap_mentioned_p (op2, op0))
2091 if (! q_regs_operand (op1, QImode))
2093 emit_insn (gen_movqi (op2, op1));
2096 emit_insn (gen_movqi (op0, op1));
2100 (define_insn "*swapqi"
2101 [(set (match_operand:QI 0 "register_operand" "+r")
2102 (match_operand:QI 1 "register_operand" "+r"))
2107 [(set_attr "type" "imov")
2108 (set_attr "pent_pair" "np")
2109 (set_attr "mode" "QI")
2110 (set_attr "modrm" "0")
2111 (set_attr "ppro_uops" "few")])
2113 (define_expand "movstrictqi"
2114 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
2115 (match_operand:QI 1 "general_operand" ""))]
2116 "! TARGET_PARTIAL_REG_STALL"
2118 /* Don't generate memory->memory moves, go through a register */
2119 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2120 operands[1] = force_reg (QImode, operands[1]);
2123 (define_insn "*movstrictqi_1"
2124 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
2125 (match_operand:QI 1 "general_operand" "*qn,m"))]
2126 "! TARGET_PARTIAL_REG_STALL
2127 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2128 "mov{b}\t{%1, %0|%0, %1}"
2129 [(set_attr "type" "imov")
2130 (set_attr "mode" "QI")])
2132 (define_insn "*movstrictqi_xor"
2133 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
2134 (match_operand:QI 1 "const0_operand" "i"))
2135 (clobber (reg:CC 17))]
2136 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
2137 "xor{b}\t{%0, %0|%0, %0}"
2138 [(set_attr "type" "alu1")
2139 (set_attr "mode" "QI")
2140 (set_attr "length_immediate" "0")])
2142 (define_insn "*movsi_extv_1"
2143 [(set (match_operand:SI 0 "register_operand" "=R")
2144 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
2148 "movs{bl|x}\t{%h1, %0|%0, %h1}"
2149 [(set_attr "type" "imovx")
2150 (set_attr "mode" "SI")])
2152 (define_insn "*movhi_extv_1"
2153 [(set (match_operand:HI 0 "register_operand" "=R")
2154 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
2158 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
2159 [(set_attr "type" "imovx")
2160 (set_attr "mode" "SI")])
2162 (define_insn "*movqi_extv_1"
2163 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2164 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2169 switch (get_attr_type (insn))
2172 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2174 return "mov{b}\t{%h1, %0|%0, %h1}";
2178 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2179 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2180 (ne (symbol_ref "TARGET_MOVX")
2182 (const_string "imovx")
2183 (const_string "imov")))
2185 (if_then_else (eq_attr "type" "imovx")
2187 (const_string "QI")))])
2189 (define_insn "*movqi_extv_1_rex64"
2190 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2191 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2196 switch (get_attr_type (insn))
2199 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2201 return "mov{b}\t{%h1, %0|%0, %h1}";
2205 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2206 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2207 (ne (symbol_ref "TARGET_MOVX")
2209 (const_string "imovx")
2210 (const_string "imov")))
2212 (if_then_else (eq_attr "type" "imovx")
2214 (const_string "QI")))])
2216 ;; Stores and loads of ax to arbitary constant address.
2217 ;; We fake an second form of instruction to force reload to load address
2218 ;; into register when rax is not available
2219 (define_insn "*movabsqi_1_rex64"
2220 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2221 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2224 movabs{q}\t{%1, %P0|%P0, %1}
2225 mov{q}\t{%1, %a0|%a0, %1}
2226 movabs{q}\t{%1, %a0|%a0, %1}"
2227 [(set_attr "type" "imov")
2228 (set_attr "modrm" "0,*,*")
2229 (set_attr "length_address" "8,0,0")
2230 (set_attr "length_immediate" "0,*,*")
2231 (set_attr "memory" "store")
2232 (set_attr "mode" "QI")])
2234 (define_insn "*movabsqi_2_rex64"
2235 [(set (match_operand:QI 0 "register_operand" "=a,r")
2236 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2239 movabs{q}\t{%P1, %0|%0, %P1}
2240 mov{q}\t{%a1, %0|%0, %a1}"
2241 [(set_attr "type" "imov")
2242 (set_attr "modrm" "0,*")
2243 (set_attr "length_address" "8,0")
2244 (set_attr "length_immediate" "0")
2245 (set_attr "memory" "load")
2246 (set_attr "mode" "QI")])
2248 (define_insn "*movsi_extzv_1"
2249 [(set (match_operand:SI 0 "register_operand" "=R")
2250 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
2254 "movz{bl|x}\t{%h1, %0|%0, %h1}"
2255 [(set_attr "type" "imovx")
2256 (set_attr "mode" "SI")])
2258 (define_insn "*movqi_extzv_2"
2259 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2260 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2265 switch (get_attr_type (insn))
2268 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2270 return "mov{b}\t{%h1, %0|%0, %h1}";
2274 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2275 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2276 (ne (symbol_ref "TARGET_MOVX")
2278 (const_string "imovx")
2279 (const_string "imov")))
2281 (if_then_else (eq_attr "type" "imovx")
2283 (const_string "QI")))])
2285 (define_insn "*movqi_extzv_2_rex64"
2286 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2287 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2292 switch (get_attr_type (insn))
2295 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2297 return "mov{b}\t{%h1, %0|%0, %h1}";
2301 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2302 (ne (symbol_ref "TARGET_MOVX")
2304 (const_string "imovx")
2305 (const_string "imov")))
2307 (if_then_else (eq_attr "type" "imovx")
2309 (const_string "QI")))])
2311 (define_insn "movsi_insv_1"
2312 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2315 (match_operand:SI 1 "general_operand" "Qmn"))]
2317 "mov{b}\t{%b1, %h0|%h0, %b1}"
2318 [(set_attr "type" "imov")
2319 (set_attr "mode" "QI")])
2321 (define_insn "*movsi_insv_1_rex64"
2322 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2325 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
2327 "mov{b}\t{%b1, %h0|%h0, %b1}"
2328 [(set_attr "type" "imov")
2329 (set_attr "mode" "QI")])
2331 (define_insn "*movqi_insv_2"
2332 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2335 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
2339 "mov{b}\t{%h1, %h0|%h0, %h1}"
2340 [(set_attr "type" "imov")
2341 (set_attr "mode" "QI")])
2343 (define_expand "movdi"
2344 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2345 (match_operand:DI 1 "general_operand" ""))]
2347 "ix86_expand_move (DImode, operands); DONE;")
2349 (define_insn "*pushdi"
2350 [(set (match_operand:DI 0 "push_operand" "=<")
2351 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2355 (define_insn "pushdi2_rex64"
2356 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2357 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2362 [(set_attr "type" "push,multi")
2363 (set_attr "mode" "DI")])
2365 ;; Convert impossible pushes of immediate to existing instructions.
2366 ;; First try to get scratch register and go through it. In case this
2367 ;; fails, push sign extended lower part first and then overwrite
2368 ;; upper part by 32bit move.
2370 [(match_scratch:DI 2 "r")
2371 (set (match_operand:DI 0 "push_operand" "")
2372 (match_operand:DI 1 "immediate_operand" ""))]
2373 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2374 && !x86_64_immediate_operand (operands[1], DImode)"
2375 [(set (match_dup 2) (match_dup 1))
2376 (set (match_dup 0) (match_dup 2))]
2379 ;; We need to define this as both peepholer and splitter for case
2380 ;; peephole2 pass is not run.
2382 [(set (match_operand:DI 0 "push_operand" "")
2383 (match_operand:DI 1 "immediate_operand" ""))]
2384 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2385 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2386 [(set (match_dup 0) (match_dup 1))
2387 (set (match_dup 2) (match_dup 3))]
2388 "split_di (operands + 1, 1, operands + 2, operands + 3);
2389 operands[1] = gen_lowpart (DImode, operands[2]);
2390 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2395 [(set (match_operand:DI 0 "push_operand" "")
2396 (match_operand:DI 1 "immediate_operand" ""))]
2397 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2398 && !symbolic_operand (operands[1], DImode)
2399 && !x86_64_immediate_operand (operands[1], DImode)"
2400 [(set (match_dup 0) (match_dup 1))
2401 (set (match_dup 2) (match_dup 3))]
2402 "split_di (operands + 1, 1, operands + 2, operands + 3);
2403 operands[1] = gen_lowpart (DImode, operands[2]);
2404 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2408 (define_insn "*pushdi2_prologue_rex64"
2409 [(set (match_operand:DI 0 "push_operand" "=<")
2410 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2411 (clobber (mem:BLK (scratch)))]
2414 [(set_attr "type" "push")
2415 (set_attr "mode" "DI")])
2417 (define_insn "*popdi1_epilogue_rex64"
2418 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2419 (mem:DI (reg:DI 7)))
2421 (plus:DI (reg:DI 7) (const_int 8)))
2422 (clobber (mem:BLK (scratch)))]
2425 [(set_attr "type" "pop")
2426 (set_attr "mode" "DI")])
2428 (define_insn "popdi1"
2429 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2430 (mem:DI (reg:DI 7)))
2432 (plus:DI (reg:DI 7) (const_int 8)))]
2435 [(set_attr "type" "pop")
2436 (set_attr "mode" "DI")])
2438 (define_insn "*movdi_xor_rex64"
2439 [(set (match_operand:DI 0 "register_operand" "=r")
2440 (match_operand:DI 1 "const0_operand" "i"))
2441 (clobber (reg:CC 17))]
2442 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
2443 && reload_completed"
2444 "xor{l}\t{%k0, %k0|%k0, %k0}"
2445 [(set_attr "type" "alu1")
2446 (set_attr "mode" "SI")
2447 (set_attr "length_immediate" "0")])
2449 (define_insn "*movdi_or_rex64"
2450 [(set (match_operand:DI 0 "register_operand" "=r")
2451 (match_operand:DI 1 "const_int_operand" "i"))
2452 (clobber (reg:CC 17))]
2453 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
2455 && GET_CODE (operands[1]) == CONST_INT
2456 && INTVAL (operands[1]) == -1"
2458 operands[1] = constm1_rtx;
2459 return "or{q}\t{%1, %0|%0, %1}";
2461 [(set_attr "type" "alu1")
2462 (set_attr "mode" "DI")
2463 (set_attr "length_immediate" "1")])
2465 (define_insn "*movdi_2"
2466 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2467 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2469 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2473 movq\t{%1, %0|%0, %1}
2474 movq\t{%1, %0|%0, %1}
2475 movq\t{%1, %0|%0, %1}
2476 movdqa\t{%1, %0|%0, %1}
2477 movq\t{%1, %0|%0, %1}"
2478 [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
2479 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
2482 [(set (match_operand:DI 0 "push_operand" "")
2483 (match_operand:DI 1 "general_operand" ""))]
2484 "!TARGET_64BIT && reload_completed
2485 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2487 "ix86_split_long_move (operands); DONE;")
2489 ;; %%% This multiword shite has got to go.
2491 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2492 (match_operand:DI 1 "general_operand" ""))]
2493 "!TARGET_64BIT && reload_completed
2494 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
2495 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2497 "ix86_split_long_move (operands); DONE;")
2499 (define_insn "*movdi_1_rex64"
2500 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
2501 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
2503 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2505 switch (get_attr_type (insn))
2508 if (register_operand (operands[0], DImode)
2509 && register_operand (operands[1], DImode))
2510 return "movdqa\t{%1, %0|%0, %1}";
2513 return "movq\t{%1, %0|%0, %1}";
2517 return "lea{q}\t{%a1, %0|%0, %a1}";
2519 if (flag_pic && SYMBOLIC_CONST (operands[1]))
2521 if (get_attr_mode (insn) == MODE_SI)
2522 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2523 else if (which_alternative == 2)
2524 return "movabs{q}\t{%1, %0|%0, %1}";
2526 return "mov{q}\t{%1, %0|%0, %1}";
2530 (cond [(eq_attr "alternative" "5,6")
2531 (const_string "mmx")
2532 (eq_attr "alternative" "7,8")
2533 (const_string "sse")
2534 (eq_attr "alternative" "4")
2535 (const_string "multi")
2536 (and (ne (symbol_ref "flag_pic") (const_int 0))
2537 (match_operand:DI 1 "symbolic_operand" ""))
2538 (const_string "lea")
2540 (const_string "imov")))
2541 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
2542 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
2543 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
2545 ;; Stores and loads of ax to arbitary constant address.
2546 ;; We fake an second form of instruction to force reload to load address
2547 ;; into register when rax is not available
2548 (define_insn "*movabsdi_1_rex64"
2549 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2550 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2553 movabs{q}\t{%1, %P0|%P0, %1}
2554 mov{q}\t{%1, %a0|%a0, %1}
2555 movabs{q}\t{%1, %a0|%a0, %1}"
2556 [(set_attr "type" "imov")
2557 (set_attr "modrm" "0,*,*")
2558 (set_attr "length_address" "8,0,0")
2559 (set_attr "length_immediate" "0,*,*")
2560 (set_attr "memory" "store")
2561 (set_attr "mode" "DI")])
2563 (define_insn "*movabsdi_2_rex64"
2564 [(set (match_operand:DI 0 "register_operand" "=a,r")
2565 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2568 movabs{q}\t{%P1, %0|%0, %P1}
2569 mov{q}\t{%a1, %0|%0, %a1}"
2570 [(set_attr "type" "imov")
2571 (set_attr "modrm" "0,*")
2572 (set_attr "length_address" "8,0")
2573 (set_attr "length_immediate" "0")
2574 (set_attr "memory" "load")
2575 (set_attr "mode" "DI")])
2577 ;; Convert impossible stores of immediate to existing instructions.
2578 ;; First try to get scratch register and go through it. In case this
2579 ;; fails, move by 32bit parts.
2581 [(match_scratch:DI 2 "r")
2582 (set (match_operand:DI 0 "memory_operand" "")
2583 (match_operand:DI 1 "immediate_operand" ""))]
2584 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2585 && !x86_64_immediate_operand (operands[1], DImode)"
2586 [(set (match_dup 2) (match_dup 1))
2587 (set (match_dup 0) (match_dup 2))]
2590 ;; We need to define this as both peepholer and splitter for case
2591 ;; peephole2 pass is not run.
2593 [(set (match_operand:DI 0 "memory_operand" "")
2594 (match_operand:DI 1 "immediate_operand" ""))]
2595 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2596 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2597 [(set (match_dup 2) (match_dup 3))
2598 (set (match_dup 4) (match_dup 5))]
2599 "split_di (operands, 2, operands + 2, operands + 4);")
2602 [(set (match_operand:DI 0 "memory_operand" "")
2603 (match_operand:DI 1 "immediate_operand" ""))]
2604 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2605 && !symbolic_operand (operands[1], DImode)
2606 && !x86_64_immediate_operand (operands[1], DImode)"
2607 [(set (match_dup 2) (match_dup 3))
2608 (set (match_dup 4) (match_dup 5))]
2609 "split_di (operands, 2, operands + 2, operands + 4);")
2611 (define_insn "*swapdi_rex64"
2612 [(set (match_operand:DI 0 "register_operand" "+r")
2613 (match_operand:DI 1 "register_operand" "+r"))
2618 [(set_attr "type" "imov")
2619 (set_attr "pent_pair" "np")
2620 (set_attr "athlon_decode" "vector")
2621 (set_attr "mode" "DI")
2622 (set_attr "modrm" "0")
2623 (set_attr "ppro_uops" "few")])
2626 (define_expand "movsf"
2627 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2628 (match_operand:SF 1 "general_operand" ""))]
2630 "ix86_expand_move (SFmode, operands); DONE;")
2632 (define_insn "*pushsf"
2633 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2634 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2637 switch (which_alternative)
2640 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2641 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2642 operands[2] = stack_pointer_rtx;
2643 operands[3] = GEN_INT (4);
2644 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2645 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2647 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2650 return "push{l}\t%1";
2658 [(set_attr "type" "multi,push,multi")
2659 (set_attr "mode" "SF,SI,SF")])
2661 (define_insn "*pushsf_rex64"
2662 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2663 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2666 switch (which_alternative)
2669 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2670 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2671 operands[2] = stack_pointer_rtx;
2672 operands[3] = GEN_INT (8);
2673 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2674 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2676 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2679 return "push{q}\t%q1";
2688 [(set_attr "type" "multi,push,multi")
2689 (set_attr "mode" "SF,DI,SF")])
2692 [(set (match_operand:SF 0 "push_operand" "")
2693 (match_operand:SF 1 "memory_operand" ""))]
2695 && GET_CODE (operands[1]) == MEM
2696 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2697 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2700 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2703 ;; %%% Kill this when call knows how to work this out.
2705 [(set (match_operand:SF 0 "push_operand" "")
2706 (match_operand:SF 1 "register_operand" ""))]
2707 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2708 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2709 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2712 [(set (match_operand:SF 0 "push_operand" "")
2713 (match_operand:SF 1 "register_operand" ""))]
2714 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2715 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2716 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2718 (define_insn "*movsf_1"
2719 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2720 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2721 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2722 && (reload_in_progress || reload_completed
2723 || GET_CODE (operands[1]) != CONST_DOUBLE
2724 || memory_operand (operands[0], SFmode))"
2726 switch (which_alternative)
2729 if (REG_P (operands[1])
2730 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2732 else if (STACK_TOP_P (operands[0]))
2733 return "fld%z1\t%y1";
2738 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2739 return "fstp%z0\t%y0";
2741 return "fst%z0\t%y0";
2744 switch (standard_80387_constant_p (operands[1]))
2755 return "mov{l}\t{%1, %0|%0, %1}";
2757 return "pxor\t%0, %0";
2759 if (TARGET_PARTIAL_REG_DEPENDENCY)
2760 return "movaps\t{%1, %0|%0, %1}";
2762 return "movss\t{%1, %0|%0, %1}";
2765 return "movss\t{%1, %0|%0, %1}";
2771 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2772 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2774 (define_insn "*swapsf"
2775 [(set (match_operand:SF 0 "register_operand" "+f")
2776 (match_operand:SF 1 "register_operand" "+f"))
2779 "reload_completed || !TARGET_SSE2"
2781 if (STACK_TOP_P (operands[0]))
2786 [(set_attr "type" "fxch")
2787 (set_attr "mode" "SF")])
2789 (define_expand "movdf"
2790 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2791 (match_operand:DF 1 "general_operand" ""))]
2793 "ix86_expand_move (DFmode, operands); DONE;")
2795 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2796 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2797 ;; On the average, pushdf using integers can be still shorter. Allow this
2798 ;; pattern for optimize_size too.
2800 (define_insn "*pushdf_nointeger"
2801 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2802 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2803 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2805 switch (which_alternative)
2808 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2809 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2810 operands[2] = stack_pointer_rtx;
2811 operands[3] = GEN_INT (8);
2812 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2813 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2815 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2826 [(set_attr "type" "multi")
2827 (set_attr "mode" "DF,SI,SI,DF")])
2829 (define_insn "*pushdf_integer"
2830 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2831 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2832 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2834 switch (which_alternative)
2837 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2838 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2839 operands[2] = stack_pointer_rtx;
2840 operands[3] = GEN_INT (8);
2842 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2843 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2845 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2847 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2848 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2850 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2861 [(set_attr "type" "multi")
2862 (set_attr "mode" "DF,SI,DF")])
2864 ;; %%% Kill this when call knows how to work this out.
2866 [(set (match_operand:DF 0 "push_operand" "")
2867 (match_operand:DF 1 "register_operand" ""))]
2868 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2869 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2870 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2874 [(set (match_operand:DF 0 "push_operand" "")
2875 (match_operand:DF 1 "register_operand" ""))]
2876 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2877 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2878 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2882 [(set (match_operand:DF 0 "push_operand" "")
2883 (match_operand:DF 1 "general_operand" ""))]
2886 "ix86_split_long_move (operands); DONE;")
2888 ;; Moving is usually shorter when only FP registers are used. This separate
2889 ;; movdf pattern avoids the use of integer registers for FP operations
2890 ;; when optimizing for size.
2892 (define_insn "*movdf_nointeger"
2893 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2894 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2895 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2896 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2897 && (reload_in_progress || reload_completed
2898 || GET_CODE (operands[1]) != CONST_DOUBLE
2899 || memory_operand (operands[0], DFmode))"
2901 switch (which_alternative)
2904 if (REG_P (operands[1])
2905 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2907 else if (STACK_TOP_P (operands[0]))
2908 return "fld%z1\t%y1";
2913 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2914 return "fstp%z0\t%y0";
2916 return "fst%z0\t%y0";
2919 switch (standard_80387_constant_p (operands[1]))
2932 return "pxor\t%0, %0";
2934 if (TARGET_PARTIAL_REG_DEPENDENCY)
2935 return "movapd\t{%1, %0|%0, %1}";
2937 return "movsd\t{%1, %0|%0, %1}";
2940 return "movsd\t{%1, %0|%0, %1}";
2946 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2947 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2949 (define_insn "*movdf_integer"
2950 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2951 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2952 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2953 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2954 && (reload_in_progress || reload_completed
2955 || GET_CODE (operands[1]) != CONST_DOUBLE
2956 || memory_operand (operands[0], DFmode))"
2958 switch (which_alternative)
2961 if (REG_P (operands[1])
2962 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2964 else if (STACK_TOP_P (operands[0]))
2965 return "fld%z1\t%y1";
2970 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2971 return "fstp%z0\t%y0";
2973 return "fst%z0\t%y0";
2976 switch (standard_80387_constant_p (operands[1]))
2990 return "pxor\t%0, %0";
2992 if (TARGET_PARTIAL_REG_DEPENDENCY)
2993 return "movapd\t{%1, %0|%0, %1}";
2995 return "movsd\t{%1, %0|%0, %1}";
2998 return "movsd\t{%1, %0|%0, %1}";
3004 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
3005 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
3008 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3009 (match_operand:DF 1 "general_operand" ""))]
3011 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3012 && ! (ANY_FP_REG_P (operands[0]) ||
3013 (GET_CODE (operands[0]) == SUBREG
3014 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3015 && ! (ANY_FP_REG_P (operands[1]) ||
3016 (GET_CODE (operands[1]) == SUBREG
3017 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3019 "ix86_split_long_move (operands); DONE;")
3021 (define_insn "*swapdf"
3022 [(set (match_operand:DF 0 "register_operand" "+f")
3023 (match_operand:DF 1 "register_operand" "+f"))
3026 "reload_completed || !TARGET_SSE2"
3028 if (STACK_TOP_P (operands[0]))
3033 [(set_attr "type" "fxch")
3034 (set_attr "mode" "DF")])
3036 (define_expand "movxf"
3037 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3038 (match_operand:XF 1 "general_operand" ""))]
3040 "ix86_expand_move (XFmode, operands); DONE;")
3042 (define_expand "movtf"
3043 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3044 (match_operand:TF 1 "general_operand" ""))]
3046 "ix86_expand_move (TFmode, operands); DONE;")
3048 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
3049 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
3050 ;; Pushing using integer instructions is longer except for constants
3051 ;; and direct memory references.
3052 ;; (assuming that any given constant is pushed only once, but this ought to be
3053 ;; handled elsewhere).
3055 (define_insn "*pushxf_nointeger"
3056 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3057 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3058 "!TARGET_64BIT && optimize_size"
3060 switch (which_alternative)
3063 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3064 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3065 operands[2] = stack_pointer_rtx;
3066 operands[3] = GEN_INT (12);
3067 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3068 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3070 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3080 [(set_attr "type" "multi")
3081 (set_attr "mode" "XF,SI,SI")])
3083 (define_insn "*pushtf_nointeger"
3084 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
3085 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
3088 switch (which_alternative)
3091 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3092 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3093 operands[2] = stack_pointer_rtx;
3094 operands[3] = GEN_INT (16);
3095 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3096 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3098 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3108 [(set_attr "type" "multi")
3109 (set_attr "mode" "XF,SI,SI")])
3111 (define_insn "*pushxf_integer"
3112 [(set (match_operand:XF 0 "push_operand" "=<,<")
3113 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
3114 "!TARGET_64BIT && !optimize_size"
3116 switch (which_alternative)
3119 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3120 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3121 operands[2] = stack_pointer_rtx;
3122 operands[3] = GEN_INT (12);
3123 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3124 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3126 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3135 [(set_attr "type" "multi")
3136 (set_attr "mode" "XF,SI")])
3138 (define_insn "*pushtf_integer"
3139 [(set (match_operand:TF 0 "push_operand" "=<,<")
3140 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
3143 switch (which_alternative)
3146 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3147 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3148 operands[2] = stack_pointer_rtx;
3149 operands[3] = GEN_INT (16);
3151 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3152 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3154 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3156 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3157 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3159 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3168 [(set_attr "type" "multi")
3169 (set_attr "mode" "XF,SI")])
3172 [(set (match_operand 0 "push_operand" "")
3173 (match_operand 1 "general_operand" ""))]
3175 && (GET_MODE (operands[0]) == XFmode
3176 || GET_MODE (operands[0]) == TFmode
3177 || GET_MODE (operands[0]) == DFmode)
3178 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
3180 "ix86_split_long_move (operands); DONE;")
3183 [(set (match_operand:XF 0 "push_operand" "")
3184 (match_operand:XF 1 "register_operand" ""))]
3185 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3186 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3187 (set (mem:XF (reg:SI 7)) (match_dup 1))])
3190 [(set (match_operand:TF 0 "push_operand" "")
3191 (match_operand:TF 1 "register_operand" ""))]
3192 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3193 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3194 (set (mem:TF (reg:SI 7)) (match_dup 1))])
3197 [(set (match_operand:TF 0 "push_operand" "")
3198 (match_operand:TF 1 "register_operand" ""))]
3199 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3200 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3201 (set (mem:TF (reg:DI 7)) (match_dup 1))])
3203 ;; Do not use integer registers when optimizing for size
3204 (define_insn "*movxf_nointeger"
3205 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3206 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3209 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3210 && (reload_in_progress || reload_completed
3211 || GET_CODE (operands[1]) != CONST_DOUBLE
3212 || memory_operand (operands[0], XFmode))"
3214 switch (which_alternative)
3217 if (REG_P (operands[1])
3218 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3220 else if (STACK_TOP_P (operands[0]))
3221 return "fld%z1\t%y1";
3226 /* There is no non-popping store to memory for XFmode. So if
3227 we need one, follow the store with a load. */
3228 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3229 return "fstp%z0\t%y0\;fld%z0\t%y0";
3231 return "fstp%z0\t%y0";
3234 switch (standard_80387_constant_p (operands[1]))
3248 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3249 (set_attr "mode" "XF,XF,XF,SI,SI")])
3251 (define_insn "*movtf_nointeger"
3252 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3253 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3254 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3256 && (reload_in_progress || reload_completed
3257 || GET_CODE (operands[1]) != CONST_DOUBLE
3258 || memory_operand (operands[0], TFmode))"
3260 switch (which_alternative)
3263 if (REG_P (operands[1])
3264 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3266 else if (STACK_TOP_P (operands[0]))
3267 return "fld%z1\t%y1";
3272 /* There is no non-popping store to memory for XFmode. So if
3273 we need one, follow the store with a load. */
3274 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3275 return "fstp%z0\t%y0\;fld%z0\t%y0";
3277 return "fstp%z0\t%y0";
3280 switch (standard_80387_constant_p (operands[1]))
3294 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3295 (set_attr "mode" "XF,XF,XF,SI,SI")])
3297 (define_insn "*movxf_integer"
3298 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3299 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3302 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3303 && (reload_in_progress || reload_completed
3304 || GET_CODE (operands[1]) != CONST_DOUBLE
3305 || memory_operand (operands[0], XFmode))"
3307 switch (which_alternative)
3310 if (REG_P (operands[1])
3311 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3313 else if (STACK_TOP_P (operands[0]))
3314 return "fld%z1\t%y1";
3319 /* There is no non-popping store to memory for XFmode. So if
3320 we need one, follow the store with a load. */
3321 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3322 return "fstp%z0\t%y0\;fld%z0\t%y0";
3324 return "fstp%z0\t%y0";
3327 switch (standard_80387_constant_p (operands[1]))
3341 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3342 (set_attr "mode" "XF,XF,XF,SI,SI")])
3344 (define_insn "*movtf_integer"
3345 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3346 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3347 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3349 && (reload_in_progress || reload_completed
3350 || GET_CODE (operands[1]) != CONST_DOUBLE
3351 || memory_operand (operands[0], TFmode))"
3353 switch (which_alternative)
3356 if (REG_P (operands[1])
3357 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3359 else if (STACK_TOP_P (operands[0]))
3360 return "fld%z1\t%y1";
3365 /* There is no non-popping store to memory for XFmode. So if
3366 we need one, follow the store with a load. */
3367 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3368 return "fstp%z0\t%y0\;fld%z0\t%y0";
3370 return "fstp%z0\t%y0";
3373 switch (standard_80387_constant_p (operands[1]))
3387 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3388 (set_attr "mode" "XF,XF,XF,SI,SI")])
3391 [(set (match_operand 0 "nonimmediate_operand" "")
3392 (match_operand 1 "general_operand" ""))]
3394 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3395 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3396 && ! (ANY_FP_REG_P (operands[0]) ||
3397 (GET_CODE (operands[0]) == SUBREG
3398 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3399 && ! (ANY_FP_REG_P (operands[1]) ||
3400 (GET_CODE (operands[1]) == SUBREG
3401 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3403 "ix86_split_long_move (operands); DONE;")
3406 [(set (match_operand 0 "register_operand" "")
3407 (match_operand 1 "memory_operand" ""))]
3409 && GET_CODE (operands[1]) == MEM
3410 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3411 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3412 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3413 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3414 && (!(SSE_REG_P (operands[0]) ||
3415 (GET_CODE (operands[0]) == SUBREG
3416 && SSE_REG_P (SUBREG_REG (operands[0]))))
3417 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3418 && (!(FP_REG_P (operands[0]) ||
3419 (GET_CODE (operands[0]) == SUBREG
3420 && FP_REG_P (SUBREG_REG (operands[0]))))
3421 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3424 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3426 (define_insn "swapxf"
3427 [(set (match_operand:XF 0 "register_operand" "+f")
3428 (match_operand:XF 1 "register_operand" "+f"))
3433 if (STACK_TOP_P (operands[0]))
3438 [(set_attr "type" "fxch")
3439 (set_attr "mode" "XF")])
3441 (define_insn "swaptf"
3442 [(set (match_operand:TF 0 "register_operand" "+f")
3443 (match_operand:TF 1 "register_operand" "+f"))
3448 if (STACK_TOP_P (operands[0]))
3453 [(set_attr "type" "fxch")
3454 (set_attr "mode" "XF")])
3456 ;; Zero extension instructions
3458 (define_expand "zero_extendhisi2"
3459 [(set (match_operand:SI 0 "register_operand" "")
3460 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3463 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3465 operands[1] = force_reg (HImode, operands[1]);
3466 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3471 (define_insn "zero_extendhisi2_and"
3472 [(set (match_operand:SI 0 "register_operand" "=r")
3473 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3474 (clobber (reg:CC 17))]
3475 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3477 [(set_attr "type" "alu1")
3478 (set_attr "mode" "SI")])
3481 [(set (match_operand:SI 0 "register_operand" "")
3482 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3483 (clobber (reg:CC 17))]
3484 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3485 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3486 (clobber (reg:CC 17))])]
3489 (define_insn "*zero_extendhisi2_movzwl"
3490 [(set (match_operand:SI 0 "register_operand" "=r")
3491 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3492 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3493 "movz{wl|x}\t{%1, %0|%0, %1}"
3494 [(set_attr "type" "imovx")
3495 (set_attr "mode" "SI")])
3497 (define_expand "zero_extendqihi2"
3499 [(set (match_operand:HI 0 "register_operand" "")
3500 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3501 (clobber (reg:CC 17))])]
3505 (define_insn "*zero_extendqihi2_and"
3506 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3507 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3508 (clobber (reg:CC 17))]
3509 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3511 [(set_attr "type" "alu1")
3512 (set_attr "mode" "HI")])
3514 (define_insn "*zero_extendqihi2_movzbw_and"
3515 [(set (match_operand:HI 0 "register_operand" "=r,r")
3516 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3517 (clobber (reg:CC 17))]
3518 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3520 [(set_attr "type" "imovx,alu1")
3521 (set_attr "mode" "HI")])
3523 (define_insn "*zero_extendqihi2_movzbw"
3524 [(set (match_operand:HI 0 "register_operand" "=r")
3525 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3526 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3527 "movz{bw|x}\t{%1, %0|%0, %1}"
3528 [(set_attr "type" "imovx")
3529 (set_attr "mode" "HI")])
3531 ;; For the movzbw case strip only the clobber
3533 [(set (match_operand:HI 0 "register_operand" "")
3534 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3535 (clobber (reg:CC 17))]
3537 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3538 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3539 [(set (match_operand:HI 0 "register_operand" "")
3540 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3542 ;; When source and destination does not overlap, clear destination
3543 ;; first and then do the movb
3545 [(set (match_operand:HI 0 "register_operand" "")
3546 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3547 (clobber (reg:CC 17))]
3549 && ANY_QI_REG_P (operands[0])
3550 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3551 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3552 [(set (match_dup 0) (const_int 0))
3553 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3554 "operands[2] = gen_lowpart (QImode, operands[0]);")
3556 ;; Rest is handled by single and.
3558 [(set (match_operand:HI 0 "register_operand" "")
3559 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3560 (clobber (reg:CC 17))]
3562 && true_regnum (operands[0]) == true_regnum (operands[1])"
3563 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3564 (clobber (reg:CC 17))])]
3567 (define_expand "zero_extendqisi2"
3569 [(set (match_operand:SI 0 "register_operand" "")
3570 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3571 (clobber (reg:CC 17))])]
3575 (define_insn "*zero_extendqisi2_and"
3576 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3577 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3578 (clobber (reg:CC 17))]
3579 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3581 [(set_attr "type" "alu1")
3582 (set_attr "mode" "SI")])
3584 (define_insn "*zero_extendqisi2_movzbw_and"
3585 [(set (match_operand:SI 0 "register_operand" "=r,r")
3586 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3587 (clobber (reg:CC 17))]
3588 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3590 [(set_attr "type" "imovx,alu1")
3591 (set_attr "mode" "SI")])
3593 (define_insn "*zero_extendqisi2_movzbw"
3594 [(set (match_operand:SI 0 "register_operand" "=r")
3595 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3596 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3597 "movz{bl|x}\t{%1, %0|%0, %1}"
3598 [(set_attr "type" "imovx")
3599 (set_attr "mode" "SI")])
3601 ;; For the movzbl case strip only the clobber
3603 [(set (match_operand:SI 0 "register_operand" "")
3604 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3605 (clobber (reg:CC 17))]
3607 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3608 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3610 (zero_extend:SI (match_dup 1)))])
3612 ;; When source and destination does not overlap, clear destination
3613 ;; first and then do the movb
3615 [(set (match_operand:SI 0 "register_operand" "")
3616 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3617 (clobber (reg:CC 17))]
3619 && ANY_QI_REG_P (operands[0])
3620 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3621 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3622 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3623 [(set (match_dup 0) (const_int 0))
3624 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3625 "operands[2] = gen_lowpart (QImode, operands[0]);")
3627 ;; Rest is handled by single and.
3629 [(set (match_operand:SI 0 "register_operand" "")
3630 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3631 (clobber (reg:CC 17))]
3633 && true_regnum (operands[0]) == true_regnum (operands[1])"
3634 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3635 (clobber (reg:CC 17))])]
3638 ;; %%% Kill me once multi-word ops are sane.
3639 (define_expand "zero_extendsidi2"
3640 [(set (match_operand:DI 0 "register_operand" "=r")
3641 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3645 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3650 (define_insn "zero_extendsidi2_32"
3651 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3652 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3653 (clobber (reg:CC 17))]
3656 [(set_attr "mode" "SI")])
3658 (define_insn "zero_extendsidi2_rex64"
3659 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3660 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3663 mov\t{%k1, %k0|%k0, %k1}
3665 [(set_attr "type" "imovx,imov")
3666 (set_attr "mode" "SI,DI")])
3669 [(set (match_operand:DI 0 "memory_operand" "")
3670 (zero_extend:DI (match_dup 0)))]
3672 [(set (match_dup 4) (const_int 0))]
3673 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3676 [(set (match_operand:DI 0 "register_operand" "")
3677 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3678 (clobber (reg:CC 17))]
3679 "!TARGET_64BIT && reload_completed
3680 && true_regnum (operands[0]) == true_regnum (operands[1])"
3681 [(set (match_dup 4) (const_int 0))]
3682 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3685 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3686 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3687 (clobber (reg:CC 17))]
3688 "!TARGET_64BIT && reload_completed"
3689 [(set (match_dup 3) (match_dup 1))
3690 (set (match_dup 4) (const_int 0))]
3691 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3693 (define_insn "zero_extendhidi2"
3694 [(set (match_operand:DI 0 "register_operand" "=r,r")
3695 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3698 movz{wl|x}\t{%1, %k0|%k0, %1}
3699 movz{wq|x}\t{%1, %0|%0, %1}"
3700 [(set_attr "type" "imovx")
3701 (set_attr "mode" "SI,DI")])
3703 (define_insn "zero_extendqidi2"
3704 [(set (match_operand:DI 0 "register_operand" "=r,r")
3705 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3708 movz{bl|x}\t{%1, %k0|%k0, %1}
3709 movz{bq|x}\t{%1, %0|%0, %1}"
3710 [(set_attr "type" "imovx")
3711 (set_attr "mode" "SI,DI")])
3713 ;; Sign extension instructions
3715 (define_expand "extendsidi2"
3716 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3717 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3718 (clobber (reg:CC 17))
3719 (clobber (match_scratch:SI 2 ""))])]
3724 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3729 (define_insn "*extendsidi2_1"
3730 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3731 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3732 (clobber (reg:CC 17))
3733 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3737 (define_insn "extendsidi2_rex64"
3738 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3739 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3743 movs{lq|x}\t{%1,%0|%0, %1}"
3744 [(set_attr "type" "imovx")
3745 (set_attr "mode" "DI")
3746 (set_attr "prefix_0f" "0")
3747 (set_attr "modrm" "0,1")])
3749 (define_insn "extendhidi2"
3750 [(set (match_operand:DI 0 "register_operand" "=r")
3751 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3753 "movs{wq|x}\t{%1,%0|%0, %1}"
3754 [(set_attr "type" "imovx")
3755 (set_attr "mode" "DI")])
3757 (define_insn "extendqidi2"
3758 [(set (match_operand:DI 0 "register_operand" "=r")
3759 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3761 "movs{bq|x}\t{%1,%0|%0, %1}"
3762 [(set_attr "type" "imovx")
3763 (set_attr "mode" "DI")])
3765 ;; Extend to memory case when source register does die.
3767 [(set (match_operand:DI 0 "memory_operand" "")
3768 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3769 (clobber (reg:CC 17))
3770 (clobber (match_operand:SI 2 "register_operand" ""))]
3772 && dead_or_set_p (insn, operands[1])
3773 && !reg_mentioned_p (operands[1], operands[0]))"
3774 [(set (match_dup 3) (match_dup 1))
3775 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3776 (clobber (reg:CC 17))])
3777 (set (match_dup 4) (match_dup 1))]
3778 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3780 ;; Extend to memory case when source register does not die.
3782 [(set (match_operand:DI 0 "memory_operand" "")
3783 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3784 (clobber (reg:CC 17))
3785 (clobber (match_operand:SI 2 "register_operand" ""))]
3789 split_di (&operands[0], 1, &operands[3], &operands[4]);
3791 emit_move_insn (operands[3], operands[1]);
3793 /* Generate a cltd if possible and doing so it profitable. */
3794 if (true_regnum (operands[1]) == 0
3795 && true_regnum (operands[2]) == 1
3796 && (optimize_size || TARGET_USE_CLTD))
3798 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3802 emit_move_insn (operands[2], operands[1]);
3803 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3805 emit_move_insn (operands[4], operands[2]);
3809 ;; Extend to register case. Optimize case where source and destination
3810 ;; registers match and cases where we can use cltd.
3812 [(set (match_operand:DI 0 "register_operand" "")
3813 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3814 (clobber (reg:CC 17))
3815 (clobber (match_scratch:SI 2 ""))]
3819 split_di (&operands[0], 1, &operands[3], &operands[4]);
3821 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3822 emit_move_insn (operands[3], operands[1]);
3824 /* Generate a cltd if possible and doing so it profitable. */
3825 if (true_regnum (operands[3]) == 0
3826 && (optimize_size || TARGET_USE_CLTD))
3828 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3832 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3833 emit_move_insn (operands[4], operands[1]);
3835 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3839 (define_insn "extendhisi2"
3840 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3841 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3844 switch (get_attr_prefix_0f (insn))
3847 return "{cwtl|cwde}";
3849 return "movs{wl|x}\t{%1,%0|%0, %1}";
3852 [(set_attr "type" "imovx")
3853 (set_attr "mode" "SI")
3854 (set (attr "prefix_0f")
3855 ;; movsx is short decodable while cwtl is vector decoded.
3856 (if_then_else (and (eq_attr "cpu" "!k6")
3857 (eq_attr "alternative" "0"))
3859 (const_string "1")))
3861 (if_then_else (eq_attr "prefix_0f" "0")
3863 (const_string "1")))])
3865 (define_insn "*extendhisi2_zext"
3866 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3868 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3871 switch (get_attr_prefix_0f (insn))
3874 return "{cwtl|cwde}";
3876 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3879 [(set_attr "type" "imovx")
3880 (set_attr "mode" "SI")
3881 (set (attr "prefix_0f")
3882 ;; movsx is short decodable while cwtl is vector decoded.
3883 (if_then_else (and (eq_attr "cpu" "!k6")
3884 (eq_attr "alternative" "0"))
3886 (const_string "1")))
3888 (if_then_else (eq_attr "prefix_0f" "0")
3890 (const_string "1")))])
3892 (define_insn "extendqihi2"
3893 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3894 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3897 switch (get_attr_prefix_0f (insn))
3900 return "{cbtw|cbw}";
3902 return "movs{bw|x}\t{%1,%0|%0, %1}";
3905 [(set_attr "type" "imovx")
3906 (set_attr "mode" "HI")
3907 (set (attr "prefix_0f")
3908 ;; movsx is short decodable while cwtl is vector decoded.
3909 (if_then_else (and (eq_attr "cpu" "!k6")
3910 (eq_attr "alternative" "0"))
3912 (const_string "1")))
3914 (if_then_else (eq_attr "prefix_0f" "0")
3916 (const_string "1")))])
3918 (define_insn "extendqisi2"
3919 [(set (match_operand:SI 0 "register_operand" "=r")
3920 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3922 "movs{bl|x}\t{%1,%0|%0, %1}"
3923 [(set_attr "type" "imovx")
3924 (set_attr "mode" "SI")])
3926 (define_insn "*extendqisi2_zext"
3927 [(set (match_operand:DI 0 "register_operand" "=r")
3929 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3931 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3932 [(set_attr "type" "imovx")
3933 (set_attr "mode" "SI")])
3935 ;; Conversions between float and double.
3937 ;; These are all no-ops in the model used for the 80387. So just
3940 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3941 (define_insn "*dummy_extendsfdf2"
3942 [(set (match_operand:DF 0 "push_operand" "=<")
3943 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3948 [(set (match_operand:DF 0 "push_operand" "")
3949 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3950 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3951 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3952 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3955 [(set (match_operand:DF 0 "push_operand" "")
3956 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3957 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3958 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3959 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3961 (define_insn "*dummy_extendsfxf2"
3962 [(set (match_operand:XF 0 "push_operand" "=<")
3963 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3968 [(set (match_operand:XF 0 "push_operand" "")
3969 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3970 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3971 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3972 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3974 (define_insn "*dummy_extendsftf2"
3975 [(set (match_operand:TF 0 "push_operand" "=<")
3976 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3981 [(set (match_operand:TF 0 "push_operand" "")
3982 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3983 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3984 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3985 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3988 [(set (match_operand:TF 0 "push_operand" "")
3989 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3990 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3991 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3992 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3994 (define_insn "*dummy_extenddfxf2"
3995 [(set (match_operand:XF 0 "push_operand" "=<")
3996 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4001 [(set (match_operand:XF 0 "push_operand" "")
4002 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
4003 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
4004 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4005 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4007 (define_insn "*dummy_extenddftf2"
4008 [(set (match_operand:TF 0 "push_operand" "=<")
4009 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4014 [(set (match_operand:TF 0 "push_operand" "")
4015 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4016 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
4017 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4018 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4021 [(set (match_operand:TF 0 "push_operand" "")
4022 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4023 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
4024 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4025 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
4027 (define_expand "extendsfdf2"
4028 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4029 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
4030 "TARGET_80387 || TARGET_SSE2"
4032 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4033 operands[1] = force_reg (SFmode, operands[1]);
4036 (define_insn "*extendsfdf2_1"
4037 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
4038 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
4039 "(TARGET_80387 || TARGET_SSE2)
4040 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4042 switch (which_alternative)
4045 if (REG_P (operands[1])
4046 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4048 else if (STACK_TOP_P (operands[0]))
4049 return "fld%z1\t%y1";
4054 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4055 return "fstp%z0\t%y0";
4058 return "fst%z0\t%y0";
4060 return "cvtss2sd\t{%1, %0|%0, %1}";
4066 [(set_attr "type" "fmov,fmov,sse")
4067 (set_attr "mode" "SF,XF,DF")])
4069 (define_insn "*extendsfdf2_1_sse_only"
4070 [(set (match_operand:DF 0 "register_operand" "=Y")
4071 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
4072 "!TARGET_80387 && TARGET_SSE2
4073 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4074 "cvtss2sd\t{%1, %0|%0, %1}"
4075 [(set_attr "type" "sse")
4076 (set_attr "mode" "DF")])
4078 (define_expand "extendsfxf2"
4079 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4080 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
4081 "!TARGET_64BIT && TARGET_80387"
4083 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4084 operands[1] = force_reg (SFmode, operands[1]);
4087 (define_insn "*extendsfxf2_1"
4088 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4089 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4090 "!TARGET_64BIT && TARGET_80387
4091 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4093 switch (which_alternative)
4096 if (REG_P (operands[1])
4097 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4099 else if (STACK_TOP_P (operands[0]))
4100 return "fld%z1\t%y1";
4105 /* There is no non-popping store to memory for XFmode. So if
4106 we need one, follow the store with a load. */
4107 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4108 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4110 return "fstp%z0\t%y0";
4116 [(set_attr "type" "fmov")
4117 (set_attr "mode" "SF,XF")])
4119 (define_expand "extendsftf2"
4120 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4121 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
4124 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4125 operands[1] = force_reg (SFmode, operands[1]);
4128 (define_insn "*extendsftf2_1"
4129 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4130 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4132 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4134 switch (which_alternative)
4137 if (REG_P (operands[1])
4138 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4140 else if (STACK_TOP_P (operands[0]))
4141 return "fld%z1\t%y1";
4146 /* There is no non-popping store to memory for XFmode. So if
4147 we need one, follow the store with a load. */
4148 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4149 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4151 return "fstp%z0\t%y0";
4157 [(set_attr "type" "fmov")
4158 (set_attr "mode" "SF,XF")])
4160 (define_expand "extenddfxf2"
4161 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4162 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
4163 "!TARGET_64BIT && TARGET_80387"
4165 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4166 operands[1] = force_reg (DFmode, operands[1]);
4169 (define_insn "*extenddfxf2_1"
4170 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4171 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4172 "!TARGET_64BIT && TARGET_80387
4173 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4175 switch (which_alternative)
4178 if (REG_P (operands[1])
4179 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4181 else if (STACK_TOP_P (operands[0]))
4182 return "fld%z1\t%y1";
4187 /* There is no non-popping store to memory for XFmode. So if
4188 we need one, follow the store with a load. */
4189 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4190 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4192 return "fstp%z0\t%y0";
4198 [(set_attr "type" "fmov")
4199 (set_attr "mode" "DF,XF")])
4201 (define_expand "extenddftf2"
4202 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4203 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
4206 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4207 operands[1] = force_reg (DFmode, operands[1]);
4210 (define_insn "*extenddftf2_1"
4211 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4212 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4214 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4216 switch (which_alternative)
4219 if (REG_P (operands[1])
4220 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4222 else if (STACK_TOP_P (operands[0]))
4223 return "fld%z1\t%y1";
4228 /* There is no non-popping store to memory for XFmode. So if
4229 we need one, follow the store with a load. */
4230 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4231 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4233 return "fstp%z0\t%y0";
4239 [(set_attr "type" "fmov")
4240 (set_attr "mode" "DF,XF")])
4242 ;; %%% This seems bad bad news.
4243 ;; This cannot output into an f-reg because there is no way to be sure
4244 ;; of truncating in that case. Otherwise this is just like a simple move
4245 ;; insn. So we pretend we can output to a reg in order to get better
4246 ;; register preferencing, but we really use a stack slot.
4248 (define_expand "truncdfsf2"
4249 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4251 (match_operand:DF 1 "register_operand" "")))
4252 (clobber (match_dup 2))])]
4253 "TARGET_80387 || TARGET_SSE2"
4256 operands[2] = assign_386_stack_local (SFmode, 0);
4259 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4264 (define_insn "*truncdfsf2_1"
4265 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4267 (match_operand:DF 1 "register_operand" "f,f,f,f")))
4268 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4269 "TARGET_80387 && !TARGET_SSE2"
4271 switch (which_alternative)
4274 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4275 return "fstp%z0\t%y0";
4277 return "fst%z0\t%y0";
4282 [(set_attr "type" "fmov,multi,multi,multi")
4283 (set_attr "mode" "SF,SF,SF,SF")])
4285 (define_insn "*truncdfsf2_1_sse"
4286 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
4288 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
4289 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
4290 "TARGET_80387 && TARGET_SSE2"
4292 switch (which_alternative)
4295 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4296 return "fstp%z0\t%y0";
4298 return "fst%z0\t%y0";
4300 return "cvtsd2ss\t{%1, %0|%0, %1}";
4305 [(set_attr "type" "fmov,multi,multi,multi,sse")
4306 (set_attr "mode" "SF,SF,SF,SF,DF")])
4308 (define_insn "*truncdfsf2_2"
4309 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
4311 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4312 "TARGET_80387 && TARGET_SSE2
4313 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4315 switch (which_alternative)
4318 return "cvtsd2ss\t{%1, %0|%0, %1}";
4320 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4321 return "fstp%z0\t%y0";
4323 return "fst%z0\t%y0";
4328 [(set_attr "type" "sse,fmov")
4329 (set_attr "mode" "DF,SF")])
4331 (define_insn "truncdfsf2_3"
4332 [(set (match_operand:SF 0 "memory_operand" "=m")
4334 (match_operand:DF 1 "register_operand" "f")))]
4337 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4338 return "fstp%z0\t%y0";
4340 return "fst%z0\t%y0";
4342 [(set_attr "type" "fmov")
4343 (set_attr "mode" "SF")])
4345 (define_insn "truncdfsf2_sse_only"
4346 [(set (match_operand:SF 0 "register_operand" "=Y")
4348 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4349 "!TARGET_80387 && TARGET_SSE2"
4350 "cvtsd2ss\t{%1, %0|%0, %1}"
4351 [(set_attr "type" "sse")
4352 (set_attr "mode" "DF")])
4355 [(set (match_operand:SF 0 "memory_operand" "")
4357 (match_operand:DF 1 "register_operand" "")))
4358 (clobber (match_operand:SF 2 "memory_operand" ""))]
4360 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4364 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4366 (match_operand:DF 1 "nonimmediate_operand" "")))
4367 (clobber (match_operand 2 "" ""))]
4368 "TARGET_80387 && reload_completed
4369 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
4370 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4374 [(set (match_operand:SF 0 "register_operand" "")
4376 (match_operand:DF 1 "register_operand" "")))
4377 (clobber (match_operand:SF 2 "memory_operand" ""))]
4378 "TARGET_80387 && reload_completed
4379 && FP_REG_P (operands[1])"
4380 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4381 (set (match_dup 0) (match_dup 2))]
4384 (define_expand "truncxfsf2"
4385 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4387 (match_operand:XF 1 "register_operand" "")))
4388 (clobber (match_dup 2))])]
4389 "!TARGET_64BIT && TARGET_80387"
4390 "operands[2] = assign_386_stack_local (SFmode, 0);")
4392 (define_insn "*truncxfsf2_1"
4393 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4395 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4396 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4397 "!TARGET_64BIT && TARGET_80387"
4399 switch (which_alternative)
4402 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4403 return "fstp%z0\t%y0";
4405 return "fst%z0\t%y0";
4410 [(set_attr "type" "fmov,multi,multi,multi")
4411 (set_attr "mode" "SF")])
4413 (define_insn "*truncxfsf2_2"
4414 [(set (match_operand:SF 0 "memory_operand" "=m")
4416 (match_operand:XF 1 "register_operand" "f")))]
4417 "!TARGET_64BIT && TARGET_80387"
4419 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4420 return "fstp%z0\t%y0";
4422 return "fst%z0\t%y0";
4424 [(set_attr "type" "fmov")
4425 (set_attr "mode" "SF")])
4428 [(set (match_operand:SF 0 "memory_operand" "")
4430 (match_operand:XF 1 "register_operand" "")))
4431 (clobber (match_operand:SF 2 "memory_operand" ""))]
4433 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4437 [(set (match_operand:SF 0 "register_operand" "")
4439 (match_operand:XF 1 "register_operand" "")))
4440 (clobber (match_operand:SF 2 "memory_operand" ""))]
4441 "TARGET_80387 && reload_completed"
4442 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4443 (set (match_dup 0) (match_dup 2))]
4446 (define_expand "trunctfsf2"
4447 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4449 (match_operand:TF 1 "register_operand" "")))
4450 (clobber (match_dup 2))])]
4452 "operands[2] = assign_386_stack_local (SFmode, 0);")
4454 (define_insn "*trunctfsf2_1"
4455 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4457 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4458 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4461 switch (which_alternative)
4464 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4465 return "fstp%z0\t%y0";
4467 return "fst%z0\t%y0";
4472 [(set_attr "type" "fmov,multi,multi,multi")
4473 (set_attr "mode" "SF")])
4475 (define_insn "*trunctfsf2_2"
4476 [(set (match_operand:SF 0 "memory_operand" "=m")
4478 (match_operand:TF 1 "register_operand" "f")))]
4481 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4482 return "fstp%z0\t%y0";
4484 return "fst%z0\t%y0";
4486 [(set_attr "type" "fmov")
4487 (set_attr "mode" "SF")])
4490 [(set (match_operand:SF 0 "memory_operand" "")
4492 (match_operand:TF 1 "register_operand" "")))
4493 (clobber (match_operand:SF 2 "memory_operand" ""))]
4495 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4499 [(set (match_operand:SF 0 "register_operand" "")
4501 (match_operand:TF 1 "register_operand" "")))
4502 (clobber (match_operand:SF 2 "memory_operand" ""))]
4503 "TARGET_80387 && reload_completed"
4504 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4505 (set (match_dup 0) (match_dup 2))]
4509 (define_expand "truncxfdf2"
4510 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4512 (match_operand:XF 1 "register_operand" "")))
4513 (clobber (match_dup 2))])]
4514 "!TARGET_64BIT && TARGET_80387"
4515 "operands[2] = assign_386_stack_local (DFmode, 0);")
4517 (define_insn "*truncxfdf2_1"
4518 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4520 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4521 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4522 "!TARGET_64BIT && TARGET_80387"
4524 switch (which_alternative)
4527 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4528 return "fstp%z0\t%y0";
4530 return "fst%z0\t%y0";
4536 [(set_attr "type" "fmov,multi,multi,multi")
4537 (set_attr "mode" "DF")])
4539 (define_insn "*truncxfdf2_2"
4540 [(set (match_operand:DF 0 "memory_operand" "=m")
4542 (match_operand:XF 1 "register_operand" "f")))]
4543 "!TARGET_64BIT && TARGET_80387"
4545 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4546 return "fstp%z0\t%y0";
4548 return "fst%z0\t%y0";
4550 [(set_attr "type" "fmov")
4551 (set_attr "mode" "DF")])
4554 [(set (match_operand:DF 0 "memory_operand" "")
4556 (match_operand:XF 1 "register_operand" "")))
4557 (clobber (match_operand:DF 2 "memory_operand" ""))]
4559 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4563 [(set (match_operand:DF 0 "register_operand" "")
4565 (match_operand:XF 1 "register_operand" "")))
4566 (clobber (match_operand:DF 2 "memory_operand" ""))]
4567 "TARGET_80387 && reload_completed"
4568 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4569 (set (match_dup 0) (match_dup 2))]
4572 (define_expand "trunctfdf2"
4573 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4575 (match_operand:TF 1 "register_operand" "")))
4576 (clobber (match_dup 2))])]
4578 "operands[2] = assign_386_stack_local (DFmode, 0);")
4580 (define_insn "*trunctfdf2_1"
4581 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4583 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4584 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4587 switch (which_alternative)
4590 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4591 return "fstp%z0\t%y0";
4593 return "fst%z0\t%y0";
4599 [(set_attr "type" "fmov,multi,multi,multi")
4600 (set_attr "mode" "DF")])
4602 (define_insn "*trunctfdf2_2"
4603 [(set (match_operand:DF 0 "memory_operand" "=m")
4605 (match_operand:TF 1 "register_operand" "f")))]
4608 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4609 return "fstp%z0\t%y0";
4611 return "fst%z0\t%y0";
4613 [(set_attr "type" "fmov")
4614 (set_attr "mode" "DF")])
4617 [(set (match_operand:DF 0 "memory_operand" "")
4619 (match_operand:TF 1 "register_operand" "")))
4620 (clobber (match_operand:DF 2 "memory_operand" ""))]
4622 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4626 [(set (match_operand:DF 0 "register_operand" "")
4628 (match_operand:TF 1 "register_operand" "")))
4629 (clobber (match_operand:DF 2 "memory_operand" ""))]
4630 "TARGET_80387 && reload_completed"
4631 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4632 (set (match_dup 0) (match_dup 2))]
4636 ;; %%% Break up all these bad boys.
4638 ;; Signed conversion to DImode.
4640 (define_expand "fix_truncxfdi2"
4641 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4642 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4643 "!TARGET_64BIT && TARGET_80387"
4646 (define_expand "fix_trunctfdi2"
4647 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4648 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4652 (define_expand "fix_truncdfdi2"
4653 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4654 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4655 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4657 if (TARGET_64BIT && TARGET_SSE2)
4659 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4660 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4661 if (out != operands[0])
4662 emit_move_insn (operands[0], out);
4667 (define_expand "fix_truncsfdi2"
4668 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4669 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4670 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4672 if (TARGET_SSE && TARGET_64BIT)
4674 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4675 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4676 if (out != operands[0])
4677 emit_move_insn (operands[0], out);
4682 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4683 ;; of the machinery.
4684 (define_insn_and_split "*fix_truncdi_1"
4685 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4686 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4687 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4688 && !reload_completed && !reload_in_progress
4689 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4694 operands[2] = assign_386_stack_local (HImode, 1);
4695 operands[3] = assign_386_stack_local (HImode, 2);
4696 if (memory_operand (operands[0], VOIDmode))
4697 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4698 operands[2], operands[3]));
4701 operands[4] = assign_386_stack_local (DImode, 0);
4702 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4703 operands[2], operands[3],
4708 [(set_attr "type" "fistp")])
4710 (define_insn "fix_truncdi_nomemory"
4711 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4712 (fix:DI (match_operand 1 "register_operand" "f,f")))
4713 (use (match_operand:HI 2 "memory_operand" "m,m"))
4714 (use (match_operand:HI 3 "memory_operand" "m,m"))
4715 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4716 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4717 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4718 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4720 [(set_attr "type" "fistp")])
4722 (define_insn "fix_truncdi_memory"
4723 [(set (match_operand:DI 0 "memory_operand" "=m")
4724 (fix:DI (match_operand 1 "register_operand" "f")))
4725 (use (match_operand:HI 2 "memory_operand" "m"))
4726 (use (match_operand:HI 3 "memory_operand" "m"))
4727 (clobber (match_scratch:DF 4 "=&1f"))]
4728 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4729 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4730 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4731 [(set_attr "type" "fistp")])
4734 [(set (match_operand:DI 0 "register_operand" "")
4735 (fix:DI (match_operand 1 "register_operand" "")))
4736 (use (match_operand:HI 2 "memory_operand" ""))
4737 (use (match_operand:HI 3 "memory_operand" ""))
4738 (clobber (match_operand:DI 4 "memory_operand" ""))
4739 (clobber (match_scratch 5 ""))]
4741 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4744 (clobber (match_dup 5))])
4745 (set (match_dup 0) (match_dup 4))]
4749 [(set (match_operand:DI 0 "memory_operand" "")
4750 (fix:DI (match_operand 1 "register_operand" "")))
4751 (use (match_operand:HI 2 "memory_operand" ""))
4752 (use (match_operand:HI 3 "memory_operand" ""))
4753 (clobber (match_operand:DI 4 "memory_operand" ""))
4754 (clobber (match_scratch 5 ""))]
4756 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4759 (clobber (match_dup 5))])]
4762 ;; When SSE available, it is always faster to use it!
4763 (define_insn "fix_truncsfdi_sse"
4764 [(set (match_operand:DI 0 "register_operand" "=r")
4765 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4766 "TARGET_64BIT && TARGET_SSE"
4767 "cvttss2si{q}\t{%1, %0|%0, %1}"
4768 [(set_attr "type" "sse")])
4770 (define_insn "fix_truncdfdi_sse"
4771 [(set (match_operand:DI 0 "register_operand" "=r")
4772 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4773 "TARGET_64BIT && TARGET_SSE2"
4774 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4775 [(set_attr "type" "sse")])
4777 ;; Signed conversion to SImode.
4779 (define_expand "fix_truncxfsi2"
4780 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4781 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4782 "!TARGET_64BIT && TARGET_80387"
4785 (define_expand "fix_trunctfsi2"
4786 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4787 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4791 (define_expand "fix_truncdfsi2"
4792 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4793 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4794 "TARGET_80387 || TARGET_SSE2"
4798 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4799 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4800 if (out != operands[0])
4801 emit_move_insn (operands[0], out);
4806 (define_expand "fix_truncsfsi2"
4807 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4808 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4809 "TARGET_80387 || TARGET_SSE"
4813 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4814 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4815 if (out != operands[0])
4816 emit_move_insn (operands[0], out);
4821 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4822 ;; of the machinery.
4823 (define_insn_and_split "*fix_truncsi_1"
4824 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4825 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4826 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4827 && !reload_completed && !reload_in_progress
4828 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4833 operands[2] = assign_386_stack_local (HImode, 1);
4834 operands[3] = assign_386_stack_local (HImode, 2);
4835 if (memory_operand (operands[0], VOIDmode))
4836 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4837 operands[2], operands[3]));
4840 operands[4] = assign_386_stack_local (SImode, 0);
4841 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4842 operands[2], operands[3],
4847 [(set_attr "type" "fistp")])
4849 (define_insn "fix_truncsi_nomemory"
4850 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4851 (fix:SI (match_operand 1 "register_operand" "f,f")))
4852 (use (match_operand:HI 2 "memory_operand" "m,m"))
4853 (use (match_operand:HI 3 "memory_operand" "m,m"))
4854 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4855 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4856 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4858 [(set_attr "type" "fistp")])
4860 (define_insn "fix_truncsi_memory"
4861 [(set (match_operand:SI 0 "memory_operand" "=m")
4862 (fix:SI (match_operand 1 "register_operand" "f")))
4863 (use (match_operand:HI 2 "memory_operand" "m"))
4864 (use (match_operand:HI 3 "memory_operand" "m"))]
4865 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4866 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4867 "* return output_fix_trunc (insn, operands);"
4868 [(set_attr "type" "fistp")])
4870 ;; When SSE available, it is always faster to use it!
4871 (define_insn "fix_truncsfsi_sse"
4872 [(set (match_operand:SI 0 "register_operand" "=r")
4873 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4875 "cvttss2si\t{%1, %0|%0, %1}"
4876 [(set_attr "type" "sse")])
4878 (define_insn "fix_truncdfsi_sse"
4879 [(set (match_operand:SI 0 "register_operand" "=r")
4880 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4882 "cvttsd2si\t{%1, %0|%0, %1}"
4883 [(set_attr "type" "sse")])
4886 [(set (match_operand:SI 0 "register_operand" "")
4887 (fix:SI (match_operand 1 "register_operand" "")))
4888 (use (match_operand:HI 2 "memory_operand" ""))
4889 (use (match_operand:HI 3 "memory_operand" ""))
4890 (clobber (match_operand:SI 4 "memory_operand" ""))]
4892 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4894 (use (match_dup 3))])
4895 (set (match_dup 0) (match_dup 4))]
4899 [(set (match_operand:SI 0 "memory_operand" "")
4900 (fix:SI (match_operand 1 "register_operand" "")))
4901 (use (match_operand:HI 2 "memory_operand" ""))
4902 (use (match_operand:HI 3 "memory_operand" ""))
4903 (clobber (match_operand:SI 4 "memory_operand" ""))]
4905 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4907 (use (match_dup 3))])]
4910 ;; Signed conversion to HImode.
4912 (define_expand "fix_truncxfhi2"
4913 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4914 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4915 "!TARGET_64BIT && TARGET_80387"
4918 (define_expand "fix_trunctfhi2"
4919 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4920 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4924 (define_expand "fix_truncdfhi2"
4925 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4926 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4927 "TARGET_80387 && !TARGET_SSE2"
4930 (define_expand "fix_truncsfhi2"
4931 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4932 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4933 "TARGET_80387 && !TARGET_SSE"
4936 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4937 ;; of the machinery.
4938 (define_insn_and_split "*fix_trunchi_1"
4939 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4940 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4941 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4942 && !reload_completed && !reload_in_progress
4943 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4948 operands[2] = assign_386_stack_local (HImode, 1);
4949 operands[3] = assign_386_stack_local (HImode, 2);
4950 if (memory_operand (operands[0], VOIDmode))
4951 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4952 operands[2], operands[3]));
4955 operands[4] = assign_386_stack_local (HImode, 0);
4956 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4957 operands[2], operands[3],
4962 [(set_attr "type" "fistp")])
4964 (define_insn "fix_trunchi_nomemory"
4965 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4966 (fix:HI (match_operand 1 "register_operand" "f,f")))
4967 (use (match_operand:HI 2 "memory_operand" "m,m"))
4968 (use (match_operand:HI 3 "memory_operand" "m,m"))
4969 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4970 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4971 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4973 [(set_attr "type" "fistp")])
4975 (define_insn "fix_trunchi_memory"
4976 [(set (match_operand:HI 0 "memory_operand" "=m")
4977 (fix:HI (match_operand 1 "register_operand" "f")))
4978 (use (match_operand:HI 2 "memory_operand" "m"))
4979 (use (match_operand:HI 3 "memory_operand" "m"))]
4980 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4981 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4982 "* return output_fix_trunc (insn, operands);"
4983 [(set_attr "type" "fistp")])
4986 [(set (match_operand:HI 0 "memory_operand" "")
4987 (fix:HI (match_operand 1 "register_operand" "")))
4988 (use (match_operand:HI 2 "memory_operand" ""))
4989 (use (match_operand:HI 3 "memory_operand" ""))
4990 (clobber (match_operand:HI 4 "memory_operand" ""))]
4992 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4994 (use (match_dup 3))])]
4998 [(set (match_operand:HI 0 "register_operand" "")
4999 (fix:HI (match_operand 1 "register_operand" "")))
5000 (use (match_operand:HI 2 "memory_operand" ""))
5001 (use (match_operand:HI 3 "memory_operand" ""))
5002 (clobber (match_operand:HI 4 "memory_operand" ""))]
5004 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
5007 (clobber (match_dup 4))])
5008 (set (match_dup 0) (match_dup 4))]
5012 (define_insn "x86_fnstcw_1"
5013 [(set (match_operand:HI 0 "memory_operand" "=m")
5014 (unspec:HI [(reg:HI 18)] 11))]
5017 [(set_attr "length" "2")
5018 (set_attr "mode" "HI")
5019 (set_attr "i387" "1")
5020 (set_attr "ppro_uops" "few")])
5022 (define_insn "x86_fldcw_1"
5024 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
5027 [(set_attr "length" "2")
5028 (set_attr "mode" "HI")
5029 (set_attr "i387" "1")
5030 (set_attr "athlon_decode" "vector")
5031 (set_attr "ppro_uops" "few")])
5033 ;; Conversion between fixed point and floating point.
5035 ;; Even though we only accept memory inputs, the backend _really_
5036 ;; wants to be able to do this between registers.
5038 (define_insn "floathisf2"
5039 [(set (match_operand:SF 0 "register_operand" "=f,f")
5040 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5041 "TARGET_80387 && !TARGET_SSE"
5045 [(set_attr "type" "fmov,multi")
5046 (set_attr "mode" "SF")
5047 (set_attr "fp_int_src" "true")])
5049 (define_expand "floatsisf2"
5050 [(set (match_operand:SF 0 "register_operand" "")
5051 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5052 "TARGET_SSE || TARGET_80387"
5055 (define_insn "*floatsisf2_i387"
5056 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5057 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5058 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5062 cvtsi2ss\t{%1, %0|%0, %1}"
5063 [(set_attr "type" "fmov,multi,sse")
5064 (set_attr "mode" "SF")
5065 (set_attr "fp_int_src" "true")])
5067 (define_insn "*floatsisf2_sse"
5068 [(set (match_operand:SF 0 "register_operand" "=x")
5069 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5071 "cvtsi2ss\t{%1, %0|%0, %1}"
5072 [(set_attr "type" "sse")
5073 (set_attr "mode" "SF")
5074 (set_attr "fp_int_src" "true")])
5076 (define_expand "floatdisf2"
5077 [(set (match_operand:SF 0 "register_operand" "")
5078 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
5079 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
5082 (define_insn "*floatdisf2_i387_only"
5083 [(set (match_operand:SF 0 "register_operand" "=f,?f")
5084 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5085 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
5089 [(set_attr "type" "fmov,multi")
5090 (set_attr "mode" "SF")
5091 (set_attr "fp_int_src" "true")])
5093 (define_insn "*floatdisf2_i387"
5094 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5095 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5096 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5100 cvtsi2ss{q}\t{%1, %0|%0, %1}"
5101 [(set_attr "type" "fmov,multi,sse")
5102 (set_attr "mode" "SF")
5103 (set_attr "fp_int_src" "true")])
5105 (define_insn "*floatdisf2_sse"
5106 [(set (match_operand:SF 0 "register_operand" "=x")
5107 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5108 "TARGET_64BIT && TARGET_SSE"
5109 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
5110 [(set_attr "type" "sse")
5111 (set_attr "mode" "SF")
5112 (set_attr "fp_int_src" "true")])
5114 (define_insn "floathidf2"
5115 [(set (match_operand:DF 0 "register_operand" "=f,f")
5116 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5117 "TARGET_80387 && !TARGET_SSE2"
5121 [(set_attr "type" "fmov,multi")
5122 (set_attr "mode" "DF")
5123 (set_attr "fp_int_src" "true")])
5125 (define_expand "floatsidf2"
5126 [(set (match_operand:DF 0 "register_operand" "")
5127 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5131 (define_insn "*floatsidf2_i387"
5132 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5133 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5134 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5138 cvtsi2sd\t{%1, %0|%0, %1}"
5139 [(set_attr "type" "fmov,multi,sse")
5140 (set_attr "mode" "DF")
5141 (set_attr "fp_int_src" "true")])
5143 (define_insn "*floatsidf2_sse"
5144 [(set (match_operand:DF 0 "register_operand" "=Y")
5145 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5147 "cvtsi2sd\t{%1, %0|%0, %1}"
5148 [(set_attr "type" "sse")
5149 (set_attr "mode" "DF")
5150 (set_attr "fp_int_src" "true")])
5152 (define_expand "floatdidf2"
5153 [(set (match_operand:DF 0 "register_operand" "")
5154 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5155 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
5158 (define_insn "*floatdidf2_i387_only"
5159 [(set (match_operand:DF 0 "register_operand" "=f,?f")
5160 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5161 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
5165 [(set_attr "type" "fmov,multi")
5166 (set_attr "mode" "DF")
5167 (set_attr "fp_int_src" "true")])
5169 (define_insn "*floatdidf2_i387"
5170 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5171 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5172 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5176 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5177 [(set_attr "type" "fmov,multi,sse")
5178 (set_attr "mode" "DF")
5179 (set_attr "fp_int_src" "true")])
5181 (define_insn "*floatdidf2_sse"
5182 [(set (match_operand:DF 0 "register_operand" "=Y")
5183 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5185 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5186 [(set_attr "type" "sse")
5187 (set_attr "mode" "DF")
5188 (set_attr "fp_int_src" "true")])
5190 (define_insn "floathixf2"
5191 [(set (match_operand:XF 0 "register_operand" "=f,f")
5192 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5193 "!TARGET_64BIT && TARGET_80387"
5197 [(set_attr "type" "fmov,multi")
5198 (set_attr "mode" "XF")
5199 (set_attr "fp_int_src" "true")])
5201 (define_insn "floathitf2"
5202 [(set (match_operand:TF 0 "register_operand" "=f,f")
5203 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5208 [(set_attr "type" "fmov,multi")
5209 (set_attr "mode" "XF")
5210 (set_attr "fp_int_src" "true")])
5212 (define_insn "floatsixf2"
5213 [(set (match_operand:XF 0 "register_operand" "=f,f")
5214 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5215 "!TARGET_64BIT && TARGET_80387"
5219 [(set_attr "type" "fmov,multi")
5220 (set_attr "mode" "XF")
5221 (set_attr "fp_int_src" "true")])
5223 (define_insn "floatsitf2"
5224 [(set (match_operand:TF 0 "register_operand" "=f,f")
5225 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5230 [(set_attr "type" "fmov,multi")
5231 (set_attr "mode" "XF")
5232 (set_attr "fp_int_src" "true")])
5234 (define_insn "floatdixf2"
5235 [(set (match_operand:XF 0 "register_operand" "=f,f")
5236 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5237 "!TARGET_64BIT && TARGET_80387"
5241 [(set_attr "type" "fmov,multi")
5242 (set_attr "mode" "XF")
5243 (set_attr "fp_int_src" "true")])
5245 (define_insn "floatditf2"
5246 [(set (match_operand:TF 0 "register_operand" "=f,f")
5247 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5252 [(set_attr "type" "fmov,multi")
5253 (set_attr "mode" "XF")
5254 (set_attr "fp_int_src" "true")])
5256 ;; %%% Kill these when reload knows how to do it.
5258 [(set (match_operand 0 "register_operand" "")
5259 (float (match_operand 1 "register_operand" "")))]
5260 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5261 && FP_REG_P (operands[0])"
5264 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5265 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5266 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5267 ix86_free_from_memory (GET_MODE (operands[1]));
5273 ;; %%% splits for addsidi3
5274 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5275 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5276 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5278 (define_expand "adddi3"
5279 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5280 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5281 (match_operand:DI 2 "x86_64_general_operand" "")))
5282 (clobber (reg:CC 17))]
5284 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5286 (define_insn "*adddi3_1"
5287 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5288 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5289 (match_operand:DI 2 "general_operand" "roiF,riF")))
5290 (clobber (reg:CC 17))]
5295 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5296 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5297 (match_operand:DI 2 "general_operand" "")))
5298 (clobber (reg:CC 17))]
5299 "!TARGET_64BIT && reload_completed"
5300 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
5301 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5302 (parallel [(set (match_dup 3)
5303 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5306 (clobber (reg:CC 17))])]
5307 "split_di (operands+0, 1, operands+0, operands+3);
5308 split_di (operands+1, 1, operands+1, operands+4);
5309 split_di (operands+2, 1, operands+2, operands+5);")
5311 (define_insn "*adddi3_carry_rex64"
5312 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5313 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
5314 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5315 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5316 (clobber (reg:CC 17))]
5317 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5318 "adc{q}\t{%2, %0|%0, %2}"
5319 [(set_attr "type" "alu")
5320 (set_attr "pent_pair" "pu")
5321 (set_attr "mode" "DI")
5322 (set_attr "ppro_uops" "few")])
5324 (define_insn "*adddi3_cc_rex64"
5325 [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5326 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
5327 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5328 (plus:DI (match_dup 1) (match_dup 2)))]
5329 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5330 "add{q}\t{%2, %0|%0, %2}"
5331 [(set_attr "type" "alu")
5332 (set_attr "mode" "DI")])
5334 (define_insn "*addsi3_carry"
5335 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5336 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5337 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5338 (match_operand:SI 2 "general_operand" "ri,rm")))
5339 (clobber (reg:CC 17))]
5340 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5341 "adc{l}\t{%2, %0|%0, %2}"
5342 [(set_attr "type" "alu")
5343 (set_attr "pent_pair" "pu")
5344 (set_attr "mode" "SI")
5345 (set_attr "ppro_uops" "few")])
5347 (define_insn "*addsi3_carry_zext"
5348 [(set (match_operand:DI 0 "register_operand" "=r")
5350 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5351 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5352 (match_operand:SI 2 "general_operand" "rim"))))
5353 (clobber (reg:CC 17))]
5354 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5355 "adc{l}\t{%2, %k0|%k0, %2}"
5356 [(set_attr "type" "alu")
5357 (set_attr "pent_pair" "pu")
5358 (set_attr "mode" "SI")
5359 (set_attr "ppro_uops" "few")])
5361 (define_insn "*addsi3_cc"
5362 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5363 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
5364 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5365 (plus:SI (match_dup 1) (match_dup 2)))]
5366 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5367 "add{l}\t{%2, %0|%0, %2}"
5368 [(set_attr "type" "alu")
5369 (set_attr "mode" "SI")])
5371 (define_insn "addqi3_cc"
5372 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5373 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
5374 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5375 (plus:QI (match_dup 1) (match_dup 2)))]
5376 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5377 "add{b}\t{%2, %0|%0, %2}"
5378 [(set_attr "type" "alu")
5379 (set_attr "mode" "QI")])
5381 (define_expand "addsi3"
5382 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5383 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5384 (match_operand:SI 2 "general_operand" "")))
5385 (clobber (reg:CC 17))])]
5387 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5389 (define_insn "*lea_1"
5390 [(set (match_operand:SI 0 "register_operand" "=r")
5391 (match_operand:SI 1 "address_operand" "p"))]
5393 "lea{l}\t{%a1, %0|%0, %a1}"
5394 [(set_attr "type" "lea")
5395 (set_attr "mode" "SI")])
5397 (define_insn "*lea_1_rex64"
5398 [(set (match_operand:SI 0 "register_operand" "=r")
5399 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5401 "lea{l}\t{%a1, %0|%0, %a1}"
5402 [(set_attr "type" "lea")
5403 (set_attr "mode" "SI")])
5405 (define_insn "*lea_1_zext"
5406 [(set (match_operand:DI 0 "register_operand" "=r")
5407 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5409 "lea{l}\t{%a1, %k0|%k0, %a1}"
5410 [(set_attr "type" "lea")
5411 (set_attr "mode" "SI")])
5413 (define_insn "*lea_2_rex64"
5414 [(set (match_operand:DI 0 "register_operand" "=r")
5415 (match_operand:DI 1 "address_operand" "p"))]
5417 "lea{q}\t{%a1, %0|%0, %a1}"
5418 [(set_attr "type" "lea")
5419 (set_attr "mode" "DI")])
5421 ;; The lea patterns for non-Pmodes needs to be matched by several
5422 ;; insns converted to real lea by splitters.
5424 (define_insn_and_split "*lea_general_1"
5425 [(set (match_operand 0 "register_operand" "=r")
5426 (plus (plus (match_operand 1 "register_operand" "r")
5427 (match_operand 2 "register_operand" "r"))
5428 (match_operand 3 "immediate_operand" "i")))]
5429 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5430 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5431 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5432 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5433 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5434 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5435 || GET_MODE (operands[3]) == VOIDmode)"
5437 "&& reload_completed"
5441 operands[0] = gen_lowpart (SImode, operands[0]);
5442 operands[1] = gen_lowpart (Pmode, operands[1]);
5443 operands[2] = gen_lowpart (Pmode, operands[2]);
5444 operands[3] = gen_lowpart (Pmode, operands[3]);
5445 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5447 if (Pmode != SImode)
5448 pat = gen_rtx_SUBREG (SImode, pat, 0);
5449 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5452 [(set_attr "type" "lea")
5453 (set_attr "mode" "SI")])
5455 (define_insn_and_split "*lea_general_1_zext"
5456 [(set (match_operand:DI 0 "register_operand" "=r")
5458 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
5459 (match_operand:SI 2 "register_operand" "r"))
5460 (match_operand:SI 3 "immediate_operand" "i"))))]
5463 "&& reload_completed"
5465 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5467 (match_dup 3)) 0)))]
5469 operands[1] = gen_lowpart (Pmode, operands[1]);
5470 operands[2] = gen_lowpart (Pmode, operands[2]);
5471 operands[3] = gen_lowpart (Pmode, operands[3]);
5473 [(set_attr "type" "lea")
5474 (set_attr "mode" "SI")])
5476 (define_insn_and_split "*lea_general_2"
5477 [(set (match_operand 0 "register_operand" "=r")
5478 (plus (mult (match_operand 1 "register_operand" "r")
5479 (match_operand 2 "const248_operand" "i"))
5480 (match_operand 3 "nonmemory_operand" "ri")))]
5481 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5482 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5483 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5484 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5485 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5486 || GET_MODE (operands[3]) == VOIDmode)"
5488 "&& reload_completed"
5492 operands[0] = gen_lowpart (SImode, operands[0]);
5493 operands[1] = gen_lowpart (Pmode, operands[1]);
5494 operands[3] = gen_lowpart (Pmode, operands[3]);
5495 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5497 if (Pmode != SImode)
5498 pat = gen_rtx_SUBREG (SImode, pat, 0);
5499 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5502 [(set_attr "type" "lea")
5503 (set_attr "mode" "SI")])
5505 (define_insn_and_split "*lea_general_2_zext"
5506 [(set (match_operand:DI 0 "register_operand" "=r")
5508 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5509 (match_operand:SI 2 "const248_operand" "n"))
5510 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5513 "&& reload_completed"
5515 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5517 (match_dup 3)) 0)))]
5519 operands[1] = gen_lowpart (Pmode, operands[1]);
5520 operands[3] = gen_lowpart (Pmode, operands[3]);
5522 [(set_attr "type" "lea")
5523 (set_attr "mode" "SI")])
5525 (define_insn_and_split "*lea_general_3"
5526 [(set (match_operand 0 "register_operand" "=r")
5527 (plus (plus (mult (match_operand 1 "register_operand" "r")
5528 (match_operand 2 "const248_operand" "i"))
5529 (match_operand 3 "register_operand" "r"))
5530 (match_operand 4 "immediate_operand" "i")))]
5531 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5532 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5533 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5534 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5535 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5537 "&& reload_completed"
5541 operands[0] = gen_lowpart (SImode, operands[0]);
5542 operands[1] = gen_lowpart (Pmode, operands[1]);
5543 operands[3] = gen_lowpart (Pmode, operands[3]);
5544 operands[4] = gen_lowpart (Pmode, operands[4]);
5545 pat = gen_rtx_PLUS (Pmode,
5546 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5550 if (Pmode != SImode)
5551 pat = gen_rtx_SUBREG (SImode, pat, 0);
5552 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5555 [(set_attr "type" "lea")
5556 (set_attr "mode" "SI")])
5558 (define_insn_and_split "*lea_general_3_zext"
5559 [(set (match_operand:DI 0 "register_operand" "=r")
5561 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5562 (match_operand:SI 2 "const248_operand" "n"))
5563 (match_operand:SI 3 "register_operand" "r"))
5564 (match_operand:SI 4 "immediate_operand" "i"))))]
5567 "&& reload_completed"
5569 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5572 (match_dup 4)) 0)))]
5574 operands[1] = gen_lowpart (Pmode, operands[1]);
5575 operands[3] = gen_lowpart (Pmode, operands[3]);
5576 operands[4] = gen_lowpart (Pmode, operands[4]);
5578 [(set_attr "type" "lea")
5579 (set_attr "mode" "SI")])
5581 (define_insn "*adddi_1_rex64"
5582 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5583 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5584 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5585 (clobber (reg:CC 17))]
5586 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5588 switch (get_attr_type (insn))
5591 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5592 return "lea{q}\t{%a2, %0|%0, %a2}";
5595 if (! rtx_equal_p (operands[0], operands[1]))
5597 if (operands[2] == const1_rtx)
5598 return "inc{q}\t%0";
5599 else if (operands[2] == constm1_rtx)
5600 return "dec{q}\t%0";
5605 if (! rtx_equal_p (operands[0], operands[1]))
5608 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5609 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5610 if (GET_CODE (operands[2]) == CONST_INT
5611 /* Avoid overflows. */
5612 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5613 && (INTVAL (operands[2]) == 128
5614 || (INTVAL (operands[2]) < 0
5615 && INTVAL (operands[2]) != -128)))
5617 operands[2] = GEN_INT (-INTVAL (operands[2]));
5618 return "sub{q}\t{%2, %0|%0, %2}";
5620 return "add{q}\t{%2, %0|%0, %2}";
5624 (cond [(eq_attr "alternative" "2")
5625 (const_string "lea")
5626 ; Current assemblers are broken and do not allow @GOTOFF in
5627 ; ought but a memory context.
5628 (match_operand:DI 2 "pic_symbolic_operand" "")
5629 (const_string "lea")
5630 (match_operand:DI 2 "incdec_operand" "")
5631 (const_string "incdec")
5633 (const_string "alu")))
5634 (set_attr "mode" "DI")])
5636 ;; Convert lea to the lea pattern to avoid flags dependency.
5638 [(set (match_operand:DI 0 "register_operand" "")
5639 (plus:DI (match_operand:DI 1 "register_operand" "")
5640 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5641 (clobber (reg:CC 17))]
5642 "TARGET_64BIT && reload_completed
5643 && true_regnum (operands[0]) != true_regnum (operands[1])"
5645 (plus:DI (match_dup 1)
5649 (define_insn "*adddi_2_rex64"
5652 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5653 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5655 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5656 (plus:DI (match_dup 1) (match_dup 2)))]
5657 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5658 && ix86_binary_operator_ok (PLUS, DImode, operands)
5659 /* Current assemblers are broken and do not allow @GOTOFF in
5660 ought but a memory context. */
5661 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5663 switch (get_attr_type (insn))
5666 if (! rtx_equal_p (operands[0], operands[1]))
5668 if (operands[2] == const1_rtx)
5669 return "inc{q}\t%0";
5670 else if (operands[2] == constm1_rtx)
5671 return "dec{q}\t%0";
5676 if (! rtx_equal_p (operands[0], operands[1]))
5678 /* ???? We ought to handle there the 32bit case too
5679 - do we need new constrant? */
5680 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5681 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5682 if (GET_CODE (operands[2]) == CONST_INT
5683 /* Avoid overflows. */
5684 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5685 && (INTVAL (operands[2]) == 128
5686 || (INTVAL (operands[2]) < 0
5687 && INTVAL (operands[2]) != -128)))
5689 operands[2] = GEN_INT (-INTVAL (operands[2]));
5690 return "sub{q}\t{%2, %0|%0, %2}";
5692 return "add{q}\t{%2, %0|%0, %2}";
5696 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5697 (const_string "incdec")
5698 (const_string "alu")))
5699 (set_attr "mode" "DI")])
5701 (define_insn "*adddi_3_rex64"
5703 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5704 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5705 (clobber (match_scratch:DI 0 "=r"))]
5707 && ix86_match_ccmode (insn, CCZmode)
5708 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5709 /* Current assemblers are broken and do not allow @GOTOFF in
5710 ought but a memory context. */
5711 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5713 switch (get_attr_type (insn))
5716 if (! rtx_equal_p (operands[0], operands[1]))
5718 if (operands[2] == const1_rtx)
5719 return "inc{q}\t%0";
5720 else if (operands[2] == constm1_rtx)
5721 return "dec{q}\t%0";
5726 if (! rtx_equal_p (operands[0], operands[1]))
5728 /* ???? We ought to handle there the 32bit case too
5729 - do we need new constrant? */
5730 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5731 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5732 if (GET_CODE (operands[2]) == CONST_INT
5733 /* Avoid overflows. */
5734 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5735 && (INTVAL (operands[2]) == 128
5736 || (INTVAL (operands[2]) < 0
5737 && INTVAL (operands[2]) != -128)))
5739 operands[2] = GEN_INT (-INTVAL (operands[2]));
5740 return "sub{q}\t{%2, %0|%0, %2}";
5742 return "add{q}\t{%2, %0|%0, %2}";
5746 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5747 (const_string "incdec")
5748 (const_string "alu")))
5749 (set_attr "mode" "DI")])
5751 ; For comparisons against 1, -1 and 128, we may generate better code
5752 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5753 ; is matched then. We can't accept general immediate, because for
5754 ; case of overflows, the result is messed up.
5755 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5757 ; Also carry flag is reversed compared to cmp, so this converison is valid
5758 ; only for comparisons not depending on it.
5759 (define_insn "*adddi_4_rex64"
5761 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5762 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5763 (clobber (match_scratch:DI 0 "=rm"))]
5765 && ix86_match_ccmode (insn, CCGCmode)"
5767 switch (get_attr_type (insn))
5770 if (operands[2] == constm1_rtx)
5771 return "inc{q}\t%0";
5772 else if (operands[2] == const1_rtx)
5773 return "dec{q}\t%0";
5778 if (! rtx_equal_p (operands[0], operands[1]))
5780 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5781 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5782 if ((INTVAL (operands[2]) == -128
5783 || (INTVAL (operands[2]) > 0
5784 && INTVAL (operands[2]) != 128))
5785 /* Avoid overflows. */
5786 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5787 return "sub{q}\t{%2, %0|%0, %2}";
5788 operands[2] = GEN_INT (-INTVAL (operands[2]));
5789 return "add{q}\t{%2, %0|%0, %2}";
5793 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5794 (const_string "incdec")
5795 (const_string "alu")))
5796 (set_attr "mode" "DI")])
5798 (define_insn "*adddi_5_rex64"
5801 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5802 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5804 (clobber (match_scratch:DI 0 "=r"))]
5806 && ix86_match_ccmode (insn, CCGOCmode)
5807 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5808 /* Current assemblers are broken and do not allow @GOTOFF in
5809 ought but a memory context. */
5810 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5812 switch (get_attr_type (insn))
5815 if (! rtx_equal_p (operands[0], operands[1]))
5817 if (operands[2] == const1_rtx)
5818 return "inc{q}\t%0";
5819 else if (operands[2] == constm1_rtx)
5820 return "dec{q}\t%0";
5825 if (! rtx_equal_p (operands[0], operands[1]))
5827 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5828 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5829 if (GET_CODE (operands[2]) == CONST_INT
5830 /* Avoid overflows. */
5831 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5832 && (INTVAL (operands[2]) == 128
5833 || (INTVAL (operands[2]) < 0
5834 && INTVAL (operands[2]) != -128)))
5836 operands[2] = GEN_INT (-INTVAL (operands[2]));
5837 return "sub{q}\t{%2, %0|%0, %2}";
5839 return "add{q}\t{%2, %0|%0, %2}";
5843 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5844 (const_string "incdec")
5845 (const_string "alu")))
5846 (set_attr "mode" "DI")])
5849 (define_insn "*addsi_1"
5850 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5851 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5852 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5853 (clobber (reg:CC 17))]
5854 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5856 switch (get_attr_type (insn))
5859 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5860 return "lea{l}\t{%a2, %0|%0, %a2}";
5863 if (! rtx_equal_p (operands[0], operands[1]))
5865 if (operands[2] == const1_rtx)
5866 return "inc{l}\t%0";
5867 else if (operands[2] == constm1_rtx)
5868 return "dec{l}\t%0";
5873 if (! rtx_equal_p (operands[0], operands[1]))
5876 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5877 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5878 if (GET_CODE (operands[2]) == CONST_INT
5879 && (INTVAL (operands[2]) == 128
5880 || (INTVAL (operands[2]) < 0
5881 && INTVAL (operands[2]) != -128)))
5883 operands[2] = GEN_INT (-INTVAL (operands[2]));
5884 return "sub{l}\t{%2, %0|%0, %2}";
5886 return "add{l}\t{%2, %0|%0, %2}";
5890 (cond [(eq_attr "alternative" "2")
5891 (const_string "lea")
5892 ; Current assemblers are broken and do not allow @GOTOFF in
5893 ; ought but a memory context.
5894 (match_operand:SI 2 "pic_symbolic_operand" "")
5895 (const_string "lea")
5896 (match_operand:SI 2 "incdec_operand" "")
5897 (const_string "incdec")
5899 (const_string "alu")))
5900 (set_attr "mode" "SI")])
5902 ;; Convert lea to the lea pattern to avoid flags dependency.
5904 [(set (match_operand 0 "register_operand" "")
5905 (plus (match_operand 1 "register_operand" "")
5906 (match_operand 2 "nonmemory_operand" "")))
5907 (clobber (reg:CC 17))]
5909 && true_regnum (operands[0]) != true_regnum (operands[1])"
5913 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5914 may confuse gen_lowpart. */
5915 if (GET_MODE (operands[0]) != Pmode)
5917 operands[1] = gen_lowpart (Pmode, operands[1]);
5918 operands[2] = gen_lowpart (Pmode, operands[2]);
5920 operands[0] = gen_lowpart (SImode, operands[0]);
5921 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5922 if (Pmode != SImode)
5923 pat = gen_rtx_SUBREG (SImode, pat, 0);
5924 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5928 ;; It may seem that nonimmediate operand is proper one for operand 1.
5929 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5930 ;; we take care in ix86_binary_operator_ok to not allow two memory
5931 ;; operands so proper swapping will be done in reload. This allow
5932 ;; patterns constructed from addsi_1 to match.
5933 (define_insn "addsi_1_zext"
5934 [(set (match_operand:DI 0 "register_operand" "=r,r")
5936 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5937 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5938 (clobber (reg:CC 17))]
5939 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5941 switch (get_attr_type (insn))
5944 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5945 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5948 if (operands[2] == const1_rtx)
5949 return "inc{l}\t%k0";
5950 else if (operands[2] == constm1_rtx)
5951 return "dec{l}\t%k0";
5956 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5957 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5958 if (GET_CODE (operands[2]) == CONST_INT
5959 && (INTVAL (operands[2]) == 128
5960 || (INTVAL (operands[2]) < 0
5961 && INTVAL (operands[2]) != -128)))
5963 operands[2] = GEN_INT (-INTVAL (operands[2]));
5964 return "sub{l}\t{%2, %k0|%k0, %2}";
5966 return "add{l}\t{%2, %k0|%k0, %2}";
5970 (cond [(eq_attr "alternative" "1")
5971 (const_string "lea")
5972 ; Current assemblers are broken and do not allow @GOTOFF in
5973 ; ought but a memory context.
5974 (match_operand:SI 2 "pic_symbolic_operand" "")
5975 (const_string "lea")
5976 (match_operand:SI 2 "incdec_operand" "")
5977 (const_string "incdec")
5979 (const_string "alu")))
5980 (set_attr "mode" "SI")])
5982 ;; Convert lea to the lea pattern to avoid flags dependency.
5984 [(set (match_operand:DI 0 "register_operand" "")
5986 (plus:SI (match_operand:SI 1 "register_operand" "")
5987 (match_operand:SI 2 "nonmemory_operand" ""))))
5988 (clobber (reg:CC 17))]
5990 && true_regnum (operands[0]) != true_regnum (operands[1])"
5992 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5994 operands[1] = gen_lowpart (Pmode, operands[1]);
5995 operands[2] = gen_lowpart (Pmode, operands[2]);
5998 (define_insn "*addsi_2"
6001 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6002 (match_operand:SI 2 "general_operand" "rmni,rni"))
6004 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
6005 (plus:SI (match_dup 1) (match_dup 2)))]
6006 "ix86_match_ccmode (insn, CCGOCmode)
6007 && ix86_binary_operator_ok (PLUS, SImode, operands)
6008 /* Current assemblers are broken and do not allow @GOTOFF in
6009 ought but a memory context. */
6010 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6012 switch (get_attr_type (insn))
6015 if (! rtx_equal_p (operands[0], operands[1]))
6017 if (operands[2] == const1_rtx)
6018 return "inc{l}\t%0";
6019 else if (operands[2] == constm1_rtx)
6020 return "dec{l}\t%0";
6025 if (! rtx_equal_p (operands[0], operands[1]))
6027 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6028 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6029 if (GET_CODE (operands[2]) == CONST_INT
6030 && (INTVAL (operands[2]) == 128
6031 || (INTVAL (operands[2]) < 0
6032 && INTVAL (operands[2]) != -128)))
6034 operands[2] = GEN_INT (-INTVAL (operands[2]));
6035 return "sub{l}\t{%2, %0|%0, %2}";
6037 return "add{l}\t{%2, %0|%0, %2}";
6041 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6042 (const_string "incdec")
6043 (const_string "alu")))
6044 (set_attr "mode" "SI")])
6046 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6047 (define_insn "*addsi_2_zext"
6050 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6051 (match_operand:SI 2 "general_operand" "rmni"))
6053 (set (match_operand:DI 0 "register_operand" "=r")
6054 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6055 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6056 && ix86_binary_operator_ok (PLUS, SImode, operands)
6057 /* Current assemblers are broken and do not allow @GOTOFF in
6058 ought but a memory context. */
6059 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6061 switch (get_attr_type (insn))
6064 if (operands[2] == const1_rtx)
6065 return "inc{l}\t%k0";
6066 else if (operands[2] == constm1_rtx)
6067 return "dec{l}\t%k0";
6072 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6073 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6074 if (GET_CODE (operands[2]) == CONST_INT
6075 && (INTVAL (operands[2]) == 128
6076 || (INTVAL (operands[2]) < 0
6077 && INTVAL (operands[2]) != -128)))
6079 operands[2] = GEN_INT (-INTVAL (operands[2]));
6080 return "sub{l}\t{%2, %k0|%k0, %2}";
6082 return "add{l}\t{%2, %k0|%k0, %2}";
6086 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6087 (const_string "incdec")
6088 (const_string "alu")))
6089 (set_attr "mode" "SI")])
6091 (define_insn "*addsi_3"
6093 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6094 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6095 (clobber (match_scratch:SI 0 "=r"))]
6096 "ix86_match_ccmode (insn, CCZmode)
6097 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6098 /* Current assemblers are broken and do not allow @GOTOFF in
6099 ought but a memory context. */
6100 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6102 switch (get_attr_type (insn))
6105 if (! rtx_equal_p (operands[0], operands[1]))
6107 if (operands[2] == const1_rtx)
6108 return "inc{l}\t%0";
6109 else if (operands[2] == constm1_rtx)
6110 return "dec{l}\t%0";
6115 if (! rtx_equal_p (operands[0], operands[1]))
6117 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6118 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6119 if (GET_CODE (operands[2]) == CONST_INT
6120 && (INTVAL (operands[2]) == 128
6121 || (INTVAL (operands[2]) < 0
6122 && INTVAL (operands[2]) != -128)))
6124 operands[2] = GEN_INT (-INTVAL (operands[2]));
6125 return "sub{l}\t{%2, %0|%0, %2}";
6127 return "add{l}\t{%2, %0|%0, %2}";
6131 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6132 (const_string "incdec")
6133 (const_string "alu")))
6134 (set_attr "mode" "SI")])
6136 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6137 (define_insn "*addsi_3_zext"
6139 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6140 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6141 (set (match_operand:DI 0 "register_operand" "=r")
6142 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6143 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6144 && ix86_binary_operator_ok (PLUS, SImode, operands)
6145 /* Current assemblers are broken and do not allow @GOTOFF in
6146 ought but a memory context. */
6147 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6149 switch (get_attr_type (insn))
6152 if (operands[2] == const1_rtx)
6153 return "inc{l}\t%k0";
6154 else if (operands[2] == constm1_rtx)
6155 return "dec{l}\t%k0";
6160 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6161 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6162 if (GET_CODE (operands[2]) == CONST_INT
6163 && (INTVAL (operands[2]) == 128
6164 || (INTVAL (operands[2]) < 0
6165 && INTVAL (operands[2]) != -128)))
6167 operands[2] = GEN_INT (-INTVAL (operands[2]));
6168 return "sub{l}\t{%2, %k0|%k0, %2}";
6170 return "add{l}\t{%2, %k0|%k0, %2}";
6174 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6175 (const_string "incdec")
6176 (const_string "alu")))
6177 (set_attr "mode" "SI")])
6179 ; For comparisons agains 1, -1 and 128, we may generate better code
6180 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6181 ; is matched then. We can't accept general immediate, because for
6182 ; case of overflows, the result is messed up.
6183 ; This pattern also don't hold of 0x80000000, since the value overflows
6185 ; Also carry flag is reversed compared to cmp, so this converison is valid
6186 ; only for comparisons not depending on it.
6187 (define_insn "*addsi_4"
6189 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6190 (match_operand:SI 2 "const_int_operand" "n")))
6191 (clobber (match_scratch:SI 0 "=rm"))]
6192 "ix86_match_ccmode (insn, CCGCmode)
6193 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6195 switch (get_attr_type (insn))
6198 if (operands[2] == constm1_rtx)
6199 return "inc{l}\t%0";
6200 else if (operands[2] == const1_rtx)
6201 return "dec{l}\t%0";
6206 if (! rtx_equal_p (operands[0], operands[1]))
6208 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6209 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6210 if ((INTVAL (operands[2]) == -128
6211 || (INTVAL (operands[2]) > 0
6212 && INTVAL (operands[2]) != 128)))
6213 return "sub{l}\t{%2, %0|%0, %2}";
6214 operands[2] = GEN_INT (-INTVAL (operands[2]));
6215 return "add{l}\t{%2, %0|%0, %2}";
6219 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6220 (const_string "incdec")
6221 (const_string "alu")))
6222 (set_attr "mode" "SI")])
6224 (define_insn "*addsi_5"
6227 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6228 (match_operand:SI 2 "general_operand" "rmni"))
6230 (clobber (match_scratch:SI 0 "=r"))]
6231 "ix86_match_ccmode (insn, CCGOCmode)
6232 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6233 /* Current assemblers are broken and do not allow @GOTOFF in
6234 ought but a memory context. */
6235 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6237 switch (get_attr_type (insn))
6240 if (! rtx_equal_p (operands[0], operands[1]))
6242 if (operands[2] == const1_rtx)
6243 return "inc{l}\t%0";
6244 else if (operands[2] == constm1_rtx)
6245 return "dec{l}\t%0";
6250 if (! rtx_equal_p (operands[0], operands[1]))
6252 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6253 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6254 if (GET_CODE (operands[2]) == CONST_INT
6255 && (INTVAL (operands[2]) == 128
6256 || (INTVAL (operands[2]) < 0
6257 && INTVAL (operands[2]) != -128)))
6259 operands[2] = GEN_INT (-INTVAL (operands[2]));
6260 return "sub{l}\t{%2, %0|%0, %2}";
6262 return "add{l}\t{%2, %0|%0, %2}";
6266 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6267 (const_string "incdec")
6268 (const_string "alu")))
6269 (set_attr "mode" "SI")])
6271 (define_expand "addhi3"
6272 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6273 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6274 (match_operand:HI 2 "general_operand" "")))
6275 (clobber (reg:CC 17))])]
6276 "TARGET_HIMODE_MATH"
6277 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6279 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6280 ;; type optimizations enabled by define-splits. This is not important
6281 ;; for PII, and in fact harmful because of partial register stalls.
6283 (define_insn "*addhi_1_lea"
6284 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6285 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6286 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6287 (clobber (reg:CC 17))]
6288 "!TARGET_PARTIAL_REG_STALL
6289 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6291 switch (get_attr_type (insn))
6296 if (operands[2] == const1_rtx)
6297 return "inc{w}\t%0";
6298 else if (operands[2] == constm1_rtx
6299 || (GET_CODE (operands[2]) == CONST_INT
6300 && INTVAL (operands[2]) == 65535))
6301 return "dec{w}\t%0";
6305 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6306 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6307 if (GET_CODE (operands[2]) == CONST_INT
6308 && (INTVAL (operands[2]) == 128
6309 || (INTVAL (operands[2]) < 0
6310 && INTVAL (operands[2]) != -128)))
6312 operands[2] = GEN_INT (-INTVAL (operands[2]));
6313 return "sub{w}\t{%2, %0|%0, %2}";
6315 return "add{w}\t{%2, %0|%0, %2}";
6319 (if_then_else (eq_attr "alternative" "2")
6320 (const_string "lea")
6321 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6322 (const_string "incdec")
6323 (const_string "alu"))))
6324 (set_attr "mode" "HI,HI,SI")])
6326 (define_insn "*addhi_1"
6327 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6328 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6329 (match_operand:HI 2 "general_operand" "ri,rm")))
6330 (clobber (reg:CC 17))]
6331 "TARGET_PARTIAL_REG_STALL
6332 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6334 switch (get_attr_type (insn))
6337 if (operands[2] == const1_rtx)
6338 return "inc{w}\t%0";
6339 else if (operands[2] == constm1_rtx
6340 || (GET_CODE (operands[2]) == CONST_INT
6341 && INTVAL (operands[2]) == 65535))
6342 return "dec{w}\t%0";
6346 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6347 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6348 if (GET_CODE (operands[2]) == CONST_INT
6349 && (INTVAL (operands[2]) == 128
6350 || (INTVAL (operands[2]) < 0
6351 && INTVAL (operands[2]) != -128)))
6353 operands[2] = GEN_INT (-INTVAL (operands[2]));
6354 return "sub{w}\t{%2, %0|%0, %2}";
6356 return "add{w}\t{%2, %0|%0, %2}";
6360 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6361 (const_string "incdec")
6362 (const_string "alu")))
6363 (set_attr "mode" "HI")])
6365 (define_insn "*addhi_2"
6368 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6369 (match_operand:HI 2 "general_operand" "rmni,rni"))
6371 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6372 (plus:HI (match_dup 1) (match_dup 2)))]
6373 "ix86_match_ccmode (insn, CCGOCmode)
6374 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6376 switch (get_attr_type (insn))
6379 if (operands[2] == const1_rtx)
6380 return "inc{w}\t%0";
6381 else if (operands[2] == constm1_rtx
6382 || (GET_CODE (operands[2]) == CONST_INT
6383 && INTVAL (operands[2]) == 65535))
6384 return "dec{w}\t%0";
6388 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6389 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6390 if (GET_CODE (operands[2]) == CONST_INT
6391 && (INTVAL (operands[2]) == 128
6392 || (INTVAL (operands[2]) < 0
6393 && INTVAL (operands[2]) != -128)))
6395 operands[2] = GEN_INT (-INTVAL (operands[2]));
6396 return "sub{w}\t{%2, %0|%0, %2}";
6398 return "add{w}\t{%2, %0|%0, %2}";
6402 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6403 (const_string "incdec")
6404 (const_string "alu")))
6405 (set_attr "mode" "HI")])
6407 (define_insn "*addhi_3"
6409 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6410 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6411 (clobber (match_scratch:HI 0 "=r"))]
6412 "ix86_match_ccmode (insn, CCZmode)
6413 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6415 switch (get_attr_type (insn))
6418 if (operands[2] == const1_rtx)
6419 return "inc{w}\t%0";
6420 else if (operands[2] == constm1_rtx
6421 || (GET_CODE (operands[2]) == CONST_INT
6422 && INTVAL (operands[2]) == 65535))
6423 return "dec{w}\t%0";
6427 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6428 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6429 if (GET_CODE (operands[2]) == CONST_INT
6430 && (INTVAL (operands[2]) == 128
6431 || (INTVAL (operands[2]) < 0
6432 && INTVAL (operands[2]) != -128)))
6434 operands[2] = GEN_INT (-INTVAL (operands[2]));
6435 return "sub{w}\t{%2, %0|%0, %2}";
6437 return "add{w}\t{%2, %0|%0, %2}";
6441 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6442 (const_string "incdec")
6443 (const_string "alu")))
6444 (set_attr "mode" "HI")])
6446 ; See comments above addsi_3_imm for details.
6447 (define_insn "*addhi_4"
6449 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6450 (match_operand:HI 2 "const_int_operand" "n")))
6451 (clobber (match_scratch:HI 0 "=rm"))]
6452 "ix86_match_ccmode (insn, CCGCmode)
6453 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6455 switch (get_attr_type (insn))
6458 if (operands[2] == constm1_rtx
6459 || (GET_CODE (operands[2]) == CONST_INT
6460 && INTVAL (operands[2]) == 65535))
6461 return "inc{w}\t%0";
6462 else if (operands[2] == const1_rtx)
6463 return "dec{w}\t%0";
6468 if (! rtx_equal_p (operands[0], operands[1]))
6470 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6471 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6472 if ((INTVAL (operands[2]) == -128
6473 || (INTVAL (operands[2]) > 0
6474 && INTVAL (operands[2]) != 128)))
6475 return "sub{w}\t{%2, %0|%0, %2}";
6476 operands[2] = GEN_INT (-INTVAL (operands[2]));
6477 return "add{w}\t{%2, %0|%0, %2}";
6481 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6482 (const_string "incdec")
6483 (const_string "alu")))
6484 (set_attr "mode" "SI")])
6487 (define_insn "*addhi_5"
6490 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6491 (match_operand:HI 2 "general_operand" "rmni"))
6493 (clobber (match_scratch:HI 0 "=r"))]
6494 "ix86_match_ccmode (insn, CCGOCmode)
6495 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6497 switch (get_attr_type (insn))
6500 if (operands[2] == const1_rtx)
6501 return "inc{w}\t%0";
6502 else if (operands[2] == constm1_rtx
6503 || (GET_CODE (operands[2]) == CONST_INT
6504 && INTVAL (operands[2]) == 65535))
6505 return "dec{w}\t%0";
6509 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6510 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6511 if (GET_CODE (operands[2]) == CONST_INT
6512 && (INTVAL (operands[2]) == 128
6513 || (INTVAL (operands[2]) < 0
6514 && INTVAL (operands[2]) != -128)))
6516 operands[2] = GEN_INT (-INTVAL (operands[2]));
6517 return "sub{w}\t{%2, %0|%0, %2}";
6519 return "add{w}\t{%2, %0|%0, %2}";
6523 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6524 (const_string "incdec")
6525 (const_string "alu")))
6526 (set_attr "mode" "HI")])
6528 (define_expand "addqi3"
6529 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6530 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6531 (match_operand:QI 2 "general_operand" "")))
6532 (clobber (reg:CC 17))])]
6533 "TARGET_QIMODE_MATH"
6534 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6536 ;; %%% Potential partial reg stall on alternative 2. What to do?
6537 (define_insn "*addqi_1_lea"
6538 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6539 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6540 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6541 (clobber (reg:CC 17))]
6542 "!TARGET_PARTIAL_REG_STALL
6543 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6545 int widen = (which_alternative == 2);
6546 switch (get_attr_type (insn))
6551 if (operands[2] == const1_rtx)
6552 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6553 else if (operands[2] == constm1_rtx
6554 || (GET_CODE (operands[2]) == CONST_INT
6555 && INTVAL (operands[2]) == 255))
6556 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6560 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6561 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6562 if (GET_CODE (operands[2]) == CONST_INT
6563 && (INTVAL (operands[2]) == 128
6564 || (INTVAL (operands[2]) < 0
6565 && INTVAL (operands[2]) != -128)))
6567 operands[2] = GEN_INT (-INTVAL (operands[2]));
6569 return "sub{l}\t{%2, %k0|%k0, %2}";
6571 return "sub{b}\t{%2, %0|%0, %2}";
6574 return "add{l}\t{%k2, %k0|%k0, %k2}";
6576 return "add{b}\t{%2, %0|%0, %2}";
6580 (if_then_else (eq_attr "alternative" "3")
6581 (const_string "lea")
6582 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6583 (const_string "incdec")
6584 (const_string "alu"))))
6585 (set_attr "mode" "QI,QI,SI,SI")])
6587 (define_insn "*addqi_1"
6588 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6589 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6590 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6591 (clobber (reg:CC 17))]
6592 "TARGET_PARTIAL_REG_STALL
6593 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6595 int widen = (which_alternative == 2);
6596 switch (get_attr_type (insn))
6599 if (operands[2] == const1_rtx)
6600 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6601 else if (operands[2] == constm1_rtx
6602 || (GET_CODE (operands[2]) == CONST_INT
6603 && INTVAL (operands[2]) == 255))
6604 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6608 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6609 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6610 if (GET_CODE (operands[2]) == CONST_INT
6611 && (INTVAL (operands[2]) == 128
6612 || (INTVAL (operands[2]) < 0
6613 && INTVAL (operands[2]) != -128)))
6615 operands[2] = GEN_INT (-INTVAL (operands[2]));
6617 return "sub{l}\t{%2, %k0|%k0, %2}";
6619 return "sub{b}\t{%2, %0|%0, %2}";
6622 return "add{l}\t{%k2, %k0|%k0, %k2}";
6624 return "add{b}\t{%2, %0|%0, %2}";
6628 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6629 (const_string "incdec")
6630 (const_string "alu")))
6631 (set_attr "mode" "QI,QI,SI")])
6633 (define_insn "*addqi_2"
6636 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6637 (match_operand:QI 2 "general_operand" "qmni,qni"))
6639 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6640 (plus:QI (match_dup 1) (match_dup 2)))]
6641 "ix86_match_ccmode (insn, CCGOCmode)
6642 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6644 switch (get_attr_type (insn))
6647 if (operands[2] == const1_rtx)
6648 return "inc{b}\t%0";
6649 else if (operands[2] == constm1_rtx
6650 || (GET_CODE (operands[2]) == CONST_INT
6651 && INTVAL (operands[2]) == 255))
6652 return "dec{b}\t%0";
6656 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6657 if (GET_CODE (operands[2]) == CONST_INT
6658 && INTVAL (operands[2]) < 0)
6660 operands[2] = GEN_INT (-INTVAL (operands[2]));
6661 return "sub{b}\t{%2, %0|%0, %2}";
6663 return "add{b}\t{%2, %0|%0, %2}";
6667 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6668 (const_string "incdec")
6669 (const_string "alu")))
6670 (set_attr "mode" "QI")])
6672 (define_insn "*addqi_3"
6674 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6675 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6676 (clobber (match_scratch:QI 0 "=q"))]
6677 "ix86_match_ccmode (insn, CCZmode)
6678 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6680 switch (get_attr_type (insn))
6683 if (operands[2] == const1_rtx)
6684 return "inc{b}\t%0";
6685 else if (operands[2] == constm1_rtx
6686 || (GET_CODE (operands[2]) == CONST_INT
6687 && INTVAL (operands[2]) == 255))
6688 return "dec{b}\t%0";
6692 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6693 if (GET_CODE (operands[2]) == CONST_INT
6694 && INTVAL (operands[2]) < 0)
6696 operands[2] = GEN_INT (-INTVAL (operands[2]));
6697 return "sub{b}\t{%2, %0|%0, %2}";
6699 return "add{b}\t{%2, %0|%0, %2}";
6703 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6704 (const_string "incdec")
6705 (const_string "alu")))
6706 (set_attr "mode" "QI")])
6708 ; See comments above addsi_3_imm for details.
6709 (define_insn "*addqi_4"
6711 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6712 (match_operand:QI 2 "const_int_operand" "n")))
6713 (clobber (match_scratch:QI 0 "=qm"))]
6714 "ix86_match_ccmode (insn, CCGCmode)
6715 && (INTVAL (operands[2]) & 0xff) != 0x80"
6717 switch (get_attr_type (insn))
6720 if (operands[2] == constm1_rtx
6721 || (GET_CODE (operands[2]) == CONST_INT
6722 && INTVAL (operands[2]) == 255))
6723 return "inc{b}\t%0";
6724 else if (operands[2] == const1_rtx)
6725 return "dec{b}\t%0";
6730 if (! rtx_equal_p (operands[0], operands[1]))
6732 if (INTVAL (operands[2]) < 0)
6734 operands[2] = GEN_INT (-INTVAL (operands[2]));
6735 return "add{b}\t{%2, %0|%0, %2}";
6737 return "sub{b}\t{%2, %0|%0, %2}";
6741 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6742 (const_string "incdec")
6743 (const_string "alu")))
6744 (set_attr "mode" "QI")])
6747 (define_insn "*addqi_5"
6750 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6751 (match_operand:QI 2 "general_operand" "qmni"))
6753 (clobber (match_scratch:QI 0 "=q"))]
6754 "ix86_match_ccmode (insn, CCGOCmode)
6755 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6757 switch (get_attr_type (insn))
6760 if (operands[2] == const1_rtx)
6761 return "inc{b}\t%0";
6762 else if (operands[2] == constm1_rtx
6763 || (GET_CODE (operands[2]) == CONST_INT
6764 && INTVAL (operands[2]) == 255))
6765 return "dec{b}\t%0";
6769 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6770 if (GET_CODE (operands[2]) == CONST_INT
6771 && INTVAL (operands[2]) < 0)
6773 operands[2] = GEN_INT (-INTVAL (operands[2]));
6774 return "sub{b}\t{%2, %0|%0, %2}";
6776 return "add{b}\t{%2, %0|%0, %2}";
6780 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6781 (const_string "incdec")
6782 (const_string "alu")))
6783 (set_attr "mode" "QI")])
6786 (define_insn "addqi_ext_1"
6787 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6792 (match_operand 1 "ext_register_operand" "0")
6795 (match_operand:QI 2 "general_operand" "Qmn")))
6796 (clobber (reg:CC 17))]
6799 switch (get_attr_type (insn))
6802 if (operands[2] == const1_rtx)
6803 return "inc{b}\t%h0";
6804 else if (operands[2] == constm1_rtx
6805 || (GET_CODE (operands[2]) == CONST_INT
6806 && INTVAL (operands[2]) == 255))
6807 return "dec{b}\t%h0";
6811 return "add{b}\t{%2, %h0|%h0, %2}";
6815 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6816 (const_string "incdec")
6817 (const_string "alu")))
6818 (set_attr "mode" "QI")])
6820 (define_insn "*addqi_ext_1_rex64"
6821 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6826 (match_operand 1 "ext_register_operand" "0")
6829 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6830 (clobber (reg:CC 17))]
6833 switch (get_attr_type (insn))
6836 if (operands[2] == const1_rtx)
6837 return "inc{b}\t%h0";
6838 else if (operands[2] == constm1_rtx
6839 || (GET_CODE (operands[2]) == CONST_INT
6840 && INTVAL (operands[2]) == 255))
6841 return "dec{b}\t%h0";
6845 return "add{b}\t{%2, %h0|%h0, %2}";
6849 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6850 (const_string "incdec")
6851 (const_string "alu")))
6852 (set_attr "mode" "QI")])
6854 (define_insn "*addqi_ext_2"
6855 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6860 (match_operand 1 "ext_register_operand" "%0")
6864 (match_operand 2 "ext_register_operand" "Q")
6867 (clobber (reg:CC 17))]
6869 "add{b}\t{%h2, %h0|%h0, %h2}"
6870 [(set_attr "type" "alu")
6871 (set_attr "mode" "QI")])
6873 ;; The patterns that match these are at the end of this file.
6875 (define_expand "addxf3"
6876 [(set (match_operand:XF 0 "register_operand" "")
6877 (plus:XF (match_operand:XF 1 "register_operand" "")
6878 (match_operand:XF 2 "register_operand" "")))]
6879 "!TARGET_64BIT && TARGET_80387"
6882 (define_expand "addtf3"
6883 [(set (match_operand:TF 0 "register_operand" "")
6884 (plus:TF (match_operand:TF 1 "register_operand" "")
6885 (match_operand:TF 2 "register_operand" "")))]
6889 (define_expand "adddf3"
6890 [(set (match_operand:DF 0 "register_operand" "")
6891 (plus:DF (match_operand:DF 1 "register_operand" "")
6892 (match_operand:DF 2 "nonimmediate_operand" "")))]
6893 "TARGET_80387 || TARGET_SSE2"
6896 (define_expand "addsf3"
6897 [(set (match_operand:SF 0 "register_operand" "")
6898 (plus:SF (match_operand:SF 1 "register_operand" "")
6899 (match_operand:SF 2 "nonimmediate_operand" "")))]
6900 "TARGET_80387 || TARGET_SSE"
6903 ;; Subtract instructions
6905 ;; %%% splits for subsidi3
6907 (define_expand "subdi3"
6908 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6909 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6910 (match_operand:DI 2 "x86_64_general_operand" "")))
6911 (clobber (reg:CC 17))])]
6913 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6915 (define_insn "*subdi3_1"
6916 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6917 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6918 (match_operand:DI 2 "general_operand" "roiF,riF")))
6919 (clobber (reg:CC 17))]
6924 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6925 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6926 (match_operand:DI 2 "general_operand" "")))
6927 (clobber (reg:CC 17))]
6928 "!TARGET_64BIT && reload_completed"
6929 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6930 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6931 (parallel [(set (match_dup 3)
6932 (minus:SI (match_dup 4)
6933 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6935 (clobber (reg:CC 17))])]
6936 "split_di (operands+0, 1, operands+0, operands+3);
6937 split_di (operands+1, 1, operands+1, operands+4);
6938 split_di (operands+2, 1, operands+2, operands+5);")
6940 (define_insn "subdi3_carry_rex64"
6941 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6942 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6943 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6944 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6945 (clobber (reg:CC 17))]
6946 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6947 "sbb{q}\t{%2, %0|%0, %2}"
6948 [(set_attr "type" "alu")
6949 (set_attr "pent_pair" "pu")
6950 (set_attr "ppro_uops" "few")
6951 (set_attr "mode" "DI")])
6953 (define_insn "*subdi_1_rex64"
6954 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6955 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6956 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6957 (clobber (reg:CC 17))]
6958 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6959 "sub{q}\t{%2, %0|%0, %2}"
6960 [(set_attr "type" "alu")
6961 (set_attr "mode" "DI")])
6963 (define_insn "*subdi_2_rex64"
6966 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6967 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6969 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6970 (minus:DI (match_dup 1) (match_dup 2)))]
6971 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6972 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6973 "sub{q}\t{%2, %0|%0, %2}"
6974 [(set_attr "type" "alu")
6975 (set_attr "mode" "DI")])
6977 (define_insn "*subdi_3_rex63"
6979 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6980 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6981 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6982 (minus:DI (match_dup 1) (match_dup 2)))]
6983 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6984 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6985 "sub{q}\t{%2, %0|%0, %2}"
6986 [(set_attr "type" "alu")
6987 (set_attr "mode" "DI")])
6990 (define_insn "subsi3_carry"
6991 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6992 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6993 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6994 (match_operand:SI 2 "general_operand" "ri,rm"))))
6995 (clobber (reg:CC 17))]
6996 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6997 "sbb{l}\t{%2, %0|%0, %2}"
6998 [(set_attr "type" "alu")
6999 (set_attr "pent_pair" "pu")
7000 (set_attr "ppro_uops" "few")
7001 (set_attr "mode" "SI")])
7003 (define_insn "subsi3_carry_zext"
7004 [(set (match_operand:DI 0 "register_operand" "=rm,r")
7006 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
7007 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
7008 (match_operand:SI 2 "general_operand" "ri,rm")))))
7009 (clobber (reg:CC 17))]
7010 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7011 "sbb{l}\t{%2, %k0|%k0, %2}"
7012 [(set_attr "type" "alu")
7013 (set_attr "pent_pair" "pu")
7014 (set_attr "ppro_uops" "few")
7015 (set_attr "mode" "SI")])
7017 (define_expand "subsi3"
7018 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7019 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
7020 (match_operand:SI 2 "general_operand" "")))
7021 (clobber (reg:CC 17))])]
7023 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
7025 (define_insn "*subsi_1"
7026 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7027 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7028 (match_operand:SI 2 "general_operand" "ri,rm")))
7029 (clobber (reg:CC 17))]
7030 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7031 "sub{l}\t{%2, %0|%0, %2}"
7032 [(set_attr "type" "alu")
7033 (set_attr "mode" "SI")])
7035 (define_insn "*subsi_1_zext"
7036 [(set (match_operand:DI 0 "register_operand" "=r")
7038 (minus:SI (match_operand:SI 1 "register_operand" "0")
7039 (match_operand:SI 2 "general_operand" "rim"))))
7040 (clobber (reg:CC 17))]
7041 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7042 "sub{l}\t{%2, %k0|%k0, %2}"
7043 [(set_attr "type" "alu")
7044 (set_attr "mode" "SI")])
7046 (define_insn "*subsi_2"
7049 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7050 (match_operand:SI 2 "general_operand" "ri,rm"))
7052 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7053 (minus:SI (match_dup 1) (match_dup 2)))]
7054 "ix86_match_ccmode (insn, CCGOCmode)
7055 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7056 "sub{l}\t{%2, %0|%0, %2}"
7057 [(set_attr "type" "alu")
7058 (set_attr "mode" "SI")])
7060 (define_insn "*subsi_2_zext"
7063 (minus:SI (match_operand:SI 1 "register_operand" "0")
7064 (match_operand:SI 2 "general_operand" "rim"))
7066 (set (match_operand:DI 0 "register_operand" "=r")
7068 (minus:SI (match_dup 1)
7070 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7071 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7072 "sub{l}\t{%2, %k0|%k0, %2}"
7073 [(set_attr "type" "alu")
7074 (set_attr "mode" "SI")])
7076 (define_insn "*subsi_3"
7078 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7079 (match_operand:SI 2 "general_operand" "ri,rm")))
7080 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7081 (minus:SI (match_dup 1) (match_dup 2)))]
7082 "ix86_match_ccmode (insn, CCmode)
7083 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7084 "sub{l}\t{%2, %0|%0, %2}"
7085 [(set_attr "type" "alu")
7086 (set_attr "mode" "SI")])
7088 (define_insn "*subsi_3_zext"
7090 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7091 (match_operand:SI 2 "general_operand" "rim")))
7092 (set (match_operand:DI 0 "register_operand" "=r")
7094 (minus:SI (match_dup 1)
7096 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7097 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7098 "sub{q}\t{%2, %0|%0, %2}"
7099 [(set_attr "type" "alu")
7100 (set_attr "mode" "DI")])
7102 (define_expand "subhi3"
7103 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7104 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7105 (match_operand:HI 2 "general_operand" "")))
7106 (clobber (reg:CC 17))])]
7107 "TARGET_HIMODE_MATH"
7108 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7110 (define_insn "*subhi_1"
7111 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7112 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7113 (match_operand:HI 2 "general_operand" "ri,rm")))
7114 (clobber (reg:CC 17))]
7115 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7116 "sub{w}\t{%2, %0|%0, %2}"
7117 [(set_attr "type" "alu")
7118 (set_attr "mode" "HI")])
7120 (define_insn "*subhi_2"
7123 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7124 (match_operand:HI 2 "general_operand" "ri,rm"))
7126 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7127 (minus:HI (match_dup 1) (match_dup 2)))]
7128 "ix86_match_ccmode (insn, CCGOCmode)
7129 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7130 "sub{w}\t{%2, %0|%0, %2}"
7131 [(set_attr "type" "alu")
7132 (set_attr "mode" "HI")])
7134 (define_insn "*subhi_3"
7136 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7137 (match_operand:HI 2 "general_operand" "ri,rm")))
7138 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7139 (minus:HI (match_dup 1) (match_dup 2)))]
7140 "ix86_match_ccmode (insn, CCmode)
7141 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7142 "sub{w}\t{%2, %0|%0, %2}"
7143 [(set_attr "type" "alu")
7144 (set_attr "mode" "HI")])
7146 (define_expand "subqi3"
7147 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7148 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7149 (match_operand:QI 2 "general_operand" "")))
7150 (clobber (reg:CC 17))])]
7151 "TARGET_QIMODE_MATH"
7152 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7154 (define_insn "*subqi_1"
7155 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7156 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7157 (match_operand:QI 2 "general_operand" "qn,qmn")))
7158 (clobber (reg:CC 17))]
7159 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7160 "sub{b}\t{%2, %0|%0, %2}"
7161 [(set_attr "type" "alu")
7162 (set_attr "mode" "QI")])
7164 (define_insn "*subqi_2"
7167 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7168 (match_operand:QI 2 "general_operand" "qi,qm"))
7170 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7171 (minus:HI (match_dup 1) (match_dup 2)))]
7172 "ix86_match_ccmode (insn, CCGOCmode)
7173 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7174 "sub{b}\t{%2, %0|%0, %2}"
7175 [(set_attr "type" "alu")
7176 (set_attr "mode" "QI")])
7178 (define_insn "*subqi_3"
7180 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7181 (match_operand:QI 2 "general_operand" "qi,qm")))
7182 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7183 (minus:HI (match_dup 1) (match_dup 2)))]
7184 "ix86_match_ccmode (insn, CCmode)
7185 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7186 "sub{b}\t{%2, %0|%0, %2}"
7187 [(set_attr "type" "alu")
7188 (set_attr "mode" "QI")])
7190 ;; The patterns that match these are at the end of this file.
7192 (define_expand "subxf3"
7193 [(set (match_operand:XF 0 "register_operand" "")
7194 (minus:XF (match_operand:XF 1 "register_operand" "")
7195 (match_operand:XF 2 "register_operand" "")))]
7196 "!TARGET_64BIT && TARGET_80387"
7199 (define_expand "subtf3"
7200 [(set (match_operand:TF 0 "register_operand" "")
7201 (minus:TF (match_operand:TF 1 "register_operand" "")
7202 (match_operand:TF 2 "register_operand" "")))]
7206 (define_expand "subdf3"
7207 [(set (match_operand:DF 0 "register_operand" "")
7208 (minus:DF (match_operand:DF 1 "register_operand" "")
7209 (match_operand:DF 2 "nonimmediate_operand" "")))]
7210 "TARGET_80387 || TARGET_SSE2"
7213 (define_expand "subsf3"
7214 [(set (match_operand:SF 0 "register_operand" "")
7215 (minus:SF (match_operand:SF 1 "register_operand" "")
7216 (match_operand:SF 2 "nonimmediate_operand" "")))]
7217 "TARGET_80387 || TARGET_SSE"
7220 ;; Multiply instructions
7222 (define_expand "muldi3"
7223 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7224 (mult:DI (match_operand:DI 1 "register_operand" "")
7225 (match_operand:DI 2 "x86_64_general_operand" "")))
7226 (clobber (reg:CC 17))])]
7230 (define_insn "*muldi3_1_rex64"
7231 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7232 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
7233 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7234 (clobber (reg:CC 17))]
7236 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7238 imul{q}\t{%2, %1, %0|%0, %1, %2}
7239 imul{q}\t{%2, %1, %0|%0, %1, %2}
7240 imul{q}\t{%2, %0|%0, %2}"
7241 [(set_attr "type" "imul")
7242 (set_attr "prefix_0f" "0,0,1")
7243 (set_attr "mode" "DI")])
7245 (define_expand "mulsi3"
7246 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7247 (mult:SI (match_operand:SI 1 "register_operand" "")
7248 (match_operand:SI 2 "general_operand" "")))
7249 (clobber (reg:CC 17))])]
7253 (define_insn "*mulsi3_1"
7254 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7255 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7256 (match_operand:SI 2 "general_operand" "K,i,mr")))
7257 (clobber (reg:CC 17))]
7258 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7259 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7260 ; there are two ways of writing the exact same machine instruction
7261 ; in assembly language. One, for example, is:
7265 ; while the other is:
7267 ; imul $12, %eax, %eax
7269 ; The first is simply short-hand for the latter. But, some assemblers,
7270 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7272 imul{l}\t{%2, %1, %0|%0, %1, %2}
7273 imul{l}\t{%2, %1, %0|%0, %1, %2}
7274 imul{l}\t{%2, %0|%0, %2}"
7275 [(set_attr "type" "imul")
7276 (set_attr "prefix_0f" "0,0,1")
7277 (set_attr "mode" "SI")])
7279 (define_insn "*mulsi3_1_zext"
7280 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7282 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7283 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7284 (clobber (reg:CC 17))]
7286 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7287 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7288 ; there are two ways of writing the exact same machine instruction
7289 ; in assembly language. One, for example, is:
7293 ; while the other is:
7295 ; imul $12, %eax, %eax
7297 ; The first is simply short-hand for the latter. But, some assemblers,
7298 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7300 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7301 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7302 imul{l}\t{%2, %k0|%k0, %2}"
7303 [(set_attr "type" "imul")
7304 (set_attr "prefix_0f" "0,0,1")
7305 (set_attr "mode" "SI")])
7307 (define_expand "mulhi3"
7308 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7309 (mult:HI (match_operand:HI 1 "register_operand" "")
7310 (match_operand:HI 2 "general_operand" "")))
7311 (clobber (reg:CC 17))])]
7312 "TARGET_HIMODE_MATH"
7315 (define_insn "*mulhi3_1"
7316 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7317 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
7318 (match_operand:HI 2 "general_operand" "K,i,mr")))
7319 (clobber (reg:CC 17))]
7320 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7321 ; %%% There was a note about "Assembler has weird restrictions",
7322 ; concerning alternative 1 when op1 == op0. True?
7324 imul{w}\t{%2, %1, %0|%0, %1, %2}
7325 imul{w}\t{%2, %1, %0|%0, %1, %2}
7326 imul{w}\t{%2, %0|%0, %2}"
7327 [(set_attr "type" "imul")
7328 (set_attr "prefix_0f" "0,0,1")
7329 (set_attr "mode" "HI")])
7331 (define_insn "mulqi3"
7332 [(set (match_operand:QI 0 "register_operand" "=a")
7333 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7334 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7335 (clobber (reg:CC 17))]
7336 "TARGET_QIMODE_MATH"
7338 [(set_attr "type" "imul")
7339 (set_attr "length_immediate" "0")
7340 (set_attr "mode" "QI")])
7342 (define_insn "umulqihi3"
7343 [(set (match_operand:HI 0 "register_operand" "=a")
7344 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7345 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7346 (clobber (reg:CC 17))]
7347 "TARGET_QIMODE_MATH"
7349 [(set_attr "type" "imul")
7350 (set_attr "length_immediate" "0")
7351 (set_attr "mode" "QI")])
7353 (define_insn "mulqihi3"
7354 [(set (match_operand:HI 0 "register_operand" "=a")
7355 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7356 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7357 (clobber (reg:CC 17))]
7358 "TARGET_QIMODE_MATH"
7360 [(set_attr "type" "imul")
7361 (set_attr "length_immediate" "0")
7362 (set_attr "mode" "QI")])
7364 (define_insn "umulditi3"
7365 [(set (match_operand:TI 0 "register_operand" "=A")
7366 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7367 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7368 (clobber (reg:CC 17))]
7371 [(set_attr "type" "imul")
7372 (set_attr "ppro_uops" "few")
7373 (set_attr "length_immediate" "0")
7374 (set_attr "mode" "DI")])
7376 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7377 (define_insn "umulsidi3"
7378 [(set (match_operand:DI 0 "register_operand" "=A")
7379 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7380 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7381 (clobber (reg:CC 17))]
7384 [(set_attr "type" "imul")
7385 (set_attr "ppro_uops" "few")
7386 (set_attr "length_immediate" "0")
7387 (set_attr "mode" "SI")])
7389 (define_insn "mulditi3"
7390 [(set (match_operand:TI 0 "register_operand" "=A")
7391 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7392 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7393 (clobber (reg:CC 17))]
7396 [(set_attr "type" "imul")
7397 (set_attr "length_immediate" "0")
7398 (set_attr "mode" "DI")])
7400 (define_insn "mulsidi3"
7401 [(set (match_operand:DI 0 "register_operand" "=A")
7402 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7403 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7404 (clobber (reg:CC 17))]
7407 [(set_attr "type" "imul")
7408 (set_attr "length_immediate" "0")
7409 (set_attr "mode" "SI")])
7411 (define_insn "*umuldi3_highpart_rex64"
7412 [(set (match_operand:DI 0 "register_operand" "=d")
7415 (mult:TI (zero_extend:TI
7416 (match_operand:DI 1 "register_operand" "%a"))
7418 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7420 (clobber (match_scratch:DI 3 "=a"))
7421 (clobber (reg:CC 17))]
7424 [(set_attr "type" "imul")
7425 (set_attr "ppro_uops" "few")
7426 (set_attr "length_immediate" "0")
7427 (set_attr "mode" "DI")])
7429 (define_insn "umulsi3_highpart"
7430 [(set (match_operand:SI 0 "register_operand" "=d")
7433 (mult:DI (zero_extend:DI
7434 (match_operand:SI 1 "register_operand" "%a"))
7436 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7438 (clobber (match_scratch:SI 3 "=a"))
7439 (clobber (reg:CC 17))]
7442 [(set_attr "type" "imul")
7443 (set_attr "ppro_uops" "few")
7444 (set_attr "length_immediate" "0")
7445 (set_attr "mode" "SI")])
7447 (define_insn "*umulsi3_highpart_zext"
7448 [(set (match_operand:DI 0 "register_operand" "=d")
7449 (zero_extend:DI (truncate:SI
7451 (mult:DI (zero_extend:DI
7452 (match_operand:SI 1 "register_operand" "%a"))
7454 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7456 (clobber (match_scratch:SI 3 "=a"))
7457 (clobber (reg:CC 17))]
7460 [(set_attr "type" "imul")
7461 (set_attr "ppro_uops" "few")
7462 (set_attr "length_immediate" "0")
7463 (set_attr "mode" "SI")])
7465 (define_insn "*smuldi3_highpart_rex64"
7466 [(set (match_operand:DI 0 "register_operand" "=d")
7469 (mult:TI (sign_extend:TI
7470 (match_operand:DI 1 "register_operand" "%a"))
7472 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7474 (clobber (match_scratch:DI 3 "=a"))
7475 (clobber (reg:CC 17))]
7478 [(set_attr "type" "imul")
7479 (set_attr "ppro_uops" "few")
7480 (set_attr "mode" "DI")])
7482 (define_insn "smulsi3_highpart"
7483 [(set (match_operand:SI 0 "register_operand" "=d")
7486 (mult:DI (sign_extend:DI
7487 (match_operand:SI 1 "register_operand" "%a"))
7489 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7491 (clobber (match_scratch:SI 3 "=a"))
7492 (clobber (reg:CC 17))]
7495 [(set_attr "type" "imul")
7496 (set_attr "ppro_uops" "few")
7497 (set_attr "mode" "SI")])
7499 (define_insn "*smulsi3_highpart_zext"
7500 [(set (match_operand:DI 0 "register_operand" "=d")
7501 (zero_extend:DI (truncate:SI
7503 (mult:DI (sign_extend:DI
7504 (match_operand:SI 1 "register_operand" "%a"))
7506 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7508 (clobber (match_scratch:SI 3 "=a"))
7509 (clobber (reg:CC 17))]
7512 [(set_attr "type" "imul")
7513 (set_attr "ppro_uops" "few")
7514 (set_attr "mode" "SI")])
7516 ;; The patterns that match these are at the end of this file.
7518 (define_expand "mulxf3"
7519 [(set (match_operand:XF 0 "register_operand" "")
7520 (mult:XF (match_operand:XF 1 "register_operand" "")
7521 (match_operand:XF 2 "register_operand" "")))]
7522 "!TARGET_64BIT && TARGET_80387"
7525 (define_expand "multf3"
7526 [(set (match_operand:TF 0 "register_operand" "")
7527 (mult:TF (match_operand:TF 1 "register_operand" "")
7528 (match_operand:TF 2 "register_operand" "")))]
7532 (define_expand "muldf3"
7533 [(set (match_operand:DF 0 "register_operand" "")
7534 (mult:DF (match_operand:DF 1 "register_operand" "")
7535 (match_operand:DF 2 "nonimmediate_operand" "")))]
7536 "TARGET_80387 || TARGET_SSE2"
7539 (define_expand "mulsf3"
7540 [(set (match_operand:SF 0 "register_operand" "")
7541 (mult:SF (match_operand:SF 1 "register_operand" "")
7542 (match_operand:SF 2 "nonimmediate_operand" "")))]
7543 "TARGET_80387 || TARGET_SSE"
7546 ;; Divide instructions
7548 (define_insn "divqi3"
7549 [(set (match_operand:QI 0 "register_operand" "=a")
7550 (div:QI (match_operand:HI 1 "register_operand" "0")
7551 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7552 (clobber (reg:CC 17))]
7553 "TARGET_QIMODE_MATH"
7555 [(set_attr "type" "idiv")
7556 (set_attr "mode" "QI")
7557 (set_attr "ppro_uops" "few")])
7559 (define_insn "udivqi3"
7560 [(set (match_operand:QI 0 "register_operand" "=a")
7561 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7562 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7563 (clobber (reg:CC 17))]
7564 "TARGET_QIMODE_MATH"
7566 [(set_attr "type" "idiv")
7567 (set_attr "mode" "QI")
7568 (set_attr "ppro_uops" "few")])
7570 ;; The patterns that match these are at the end of this file.
7572 (define_expand "divxf3"
7573 [(set (match_operand:XF 0 "register_operand" "")
7574 (div:XF (match_operand:XF 1 "register_operand" "")
7575 (match_operand:XF 2 "register_operand" "")))]
7576 "!TARGET_64BIT && TARGET_80387"
7579 (define_expand "divtf3"
7580 [(set (match_operand:TF 0 "register_operand" "")
7581 (div:TF (match_operand:TF 1 "register_operand" "")
7582 (match_operand:TF 2 "register_operand" "")))]
7586 (define_expand "divdf3"
7587 [(set (match_operand:DF 0 "register_operand" "")
7588 (div:DF (match_operand:DF 1 "register_operand" "")
7589 (match_operand:DF 2 "nonimmediate_operand" "")))]
7590 "TARGET_80387 || TARGET_SSE2"
7593 (define_expand "divsf3"
7594 [(set (match_operand:SF 0 "register_operand" "")
7595 (div:SF (match_operand:SF 1 "register_operand" "")
7596 (match_operand:SF 2 "nonimmediate_operand" "")))]
7597 "TARGET_80387 || TARGET_SSE"
7600 ;; Remainder instructions.
7602 (define_expand "divmoddi4"
7603 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7604 (div:DI (match_operand:DI 1 "register_operand" "")
7605 (match_operand:DI 2 "nonimmediate_operand" "")))
7606 (set (match_operand:DI 3 "register_operand" "")
7607 (mod:DI (match_dup 1) (match_dup 2)))
7608 (clobber (reg:CC 17))])]
7612 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7613 ;; Penalize eax case sligthly because it results in worse scheduling
7615 (define_insn "*divmoddi4_nocltd_rex64"
7616 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7617 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7618 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7619 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7620 (mod:DI (match_dup 2) (match_dup 3)))
7621 (clobber (reg:CC 17))]
7622 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7624 [(set_attr "type" "multi")])
7626 (define_insn "*divmoddi4_cltd_rex64"
7627 [(set (match_operand:DI 0 "register_operand" "=a")
7628 (div:DI (match_operand:DI 2 "register_operand" "a")
7629 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7630 (set (match_operand:DI 1 "register_operand" "=&d")
7631 (mod:DI (match_dup 2) (match_dup 3)))
7632 (clobber (reg:CC 17))]
7633 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7635 [(set_attr "type" "multi")])
7637 (define_insn "*divmoddi_noext_rex64"
7638 [(set (match_operand:DI 0 "register_operand" "=a")
7639 (div:DI (match_operand:DI 1 "register_operand" "0")
7640 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7641 (set (match_operand:DI 3 "register_operand" "=d")
7642 (mod:DI (match_dup 1) (match_dup 2)))
7643 (use (match_operand:DI 4 "register_operand" "3"))
7644 (clobber (reg:CC 17))]
7647 [(set_attr "type" "idiv")
7648 (set_attr "mode" "DI")
7649 (set_attr "ppro_uops" "few")])
7652 [(set (match_operand:DI 0 "register_operand" "")
7653 (div:DI (match_operand:DI 1 "register_operand" "")
7654 (match_operand:DI 2 "nonimmediate_operand" "")))
7655 (set (match_operand:DI 3 "register_operand" "")
7656 (mod:DI (match_dup 1) (match_dup 2)))
7657 (clobber (reg:CC 17))]
7658 "TARGET_64BIT && reload_completed"
7659 [(parallel [(set (match_dup 3)
7660 (ashiftrt:DI (match_dup 4) (const_int 63)))
7661 (clobber (reg:CC 17))])
7662 (parallel [(set (match_dup 0)
7663 (div:DI (reg:DI 0) (match_dup 2)))
7665 (mod:DI (reg:DI 0) (match_dup 2)))
7667 (clobber (reg:CC 17))])]
7669 /* Avoid use of cltd in favour of a mov+shift. */
7670 if (!TARGET_USE_CLTD && !optimize_size)
7672 if (true_regnum (operands[1]))
7673 emit_move_insn (operands[0], operands[1]);
7675 emit_move_insn (operands[3], operands[1]);
7676 operands[4] = operands[3];
7680 if (true_regnum (operands[1]))
7682 operands[4] = operands[1];
7687 (define_expand "divmodsi4"
7688 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7689 (div:SI (match_operand:SI 1 "register_operand" "")
7690 (match_operand:SI 2 "nonimmediate_operand" "")))
7691 (set (match_operand:SI 3 "register_operand" "")
7692 (mod:SI (match_dup 1) (match_dup 2)))
7693 (clobber (reg:CC 17))])]
7697 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7698 ;; Penalize eax case sligthly because it results in worse scheduling
7700 (define_insn "*divmodsi4_nocltd"
7701 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7702 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7703 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7704 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7705 (mod:SI (match_dup 2) (match_dup 3)))
7706 (clobber (reg:CC 17))]
7707 "!optimize_size && !TARGET_USE_CLTD"
7709 [(set_attr "type" "multi")])
7711 (define_insn "*divmodsi4_cltd"
7712 [(set (match_operand:SI 0 "register_operand" "=a")
7713 (div:SI (match_operand:SI 2 "register_operand" "a")
7714 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7715 (set (match_operand:SI 1 "register_operand" "=&d")
7716 (mod:SI (match_dup 2) (match_dup 3)))
7717 (clobber (reg:CC 17))]
7718 "optimize_size || TARGET_USE_CLTD"
7720 [(set_attr "type" "multi")])
7722 (define_insn "*divmodsi_noext"
7723 [(set (match_operand:SI 0 "register_operand" "=a")
7724 (div:SI (match_operand:SI 1 "register_operand" "0")
7725 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7726 (set (match_operand:SI 3 "register_operand" "=d")
7727 (mod:SI (match_dup 1) (match_dup 2)))
7728 (use (match_operand:SI 4 "register_operand" "3"))
7729 (clobber (reg:CC 17))]
7732 [(set_attr "type" "idiv")
7733 (set_attr "mode" "SI")
7734 (set_attr "ppro_uops" "few")])
7737 [(set (match_operand:SI 0 "register_operand" "")
7738 (div:SI (match_operand:SI 1 "register_operand" "")
7739 (match_operand:SI 2 "nonimmediate_operand" "")))
7740 (set (match_operand:SI 3 "register_operand" "")
7741 (mod:SI (match_dup 1) (match_dup 2)))
7742 (clobber (reg:CC 17))]
7744 [(parallel [(set (match_dup 3)
7745 (ashiftrt:SI (match_dup 4) (const_int 31)))
7746 (clobber (reg:CC 17))])
7747 (parallel [(set (match_dup 0)
7748 (div:SI (reg:SI 0) (match_dup 2)))
7750 (mod:SI (reg:SI 0) (match_dup 2)))
7752 (clobber (reg:CC 17))])]
7754 /* Avoid use of cltd in favour of a mov+shift. */
7755 if (!TARGET_USE_CLTD && !optimize_size)
7757 if (true_regnum (operands[1]))
7758 emit_move_insn (operands[0], operands[1]);
7760 emit_move_insn (operands[3], operands[1]);
7761 operands[4] = operands[3];
7765 if (true_regnum (operands[1]))
7767 operands[4] = operands[1];
7771 (define_insn "divmodhi4"
7772 [(set (match_operand:HI 0 "register_operand" "=a")
7773 (div:HI (match_operand:HI 1 "register_operand" "0")
7774 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7775 (set (match_operand:HI 3 "register_operand" "=&d")
7776 (mod:HI (match_dup 1) (match_dup 2)))
7777 (clobber (reg:CC 17))]
7778 "TARGET_HIMODE_MATH"
7780 [(set_attr "type" "multi")
7781 (set_attr "length_immediate" "0")
7782 (set_attr "mode" "SI")])
7784 (define_insn "udivmoddi4"
7785 [(set (match_operand:DI 0 "register_operand" "=a")
7786 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7787 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7788 (set (match_operand:DI 3 "register_operand" "=&d")
7789 (umod:DI (match_dup 1) (match_dup 2)))
7790 (clobber (reg:CC 17))]
7792 "xor{q}\t%3, %3\;div{q}\t%2"
7793 [(set_attr "type" "multi")
7794 (set_attr "length_immediate" "0")
7795 (set_attr "mode" "DI")])
7797 (define_insn "*udivmoddi4_noext"
7798 [(set (match_operand:DI 0 "register_operand" "=a")
7799 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7800 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7801 (set (match_operand:DI 3 "register_operand" "=d")
7802 (umod:DI (match_dup 1) (match_dup 2)))
7804 (clobber (reg:CC 17))]
7807 [(set_attr "type" "idiv")
7808 (set_attr "ppro_uops" "few")
7809 (set_attr "mode" "DI")])
7812 [(set (match_operand:DI 0 "register_operand" "")
7813 (udiv:DI (match_operand:DI 1 "register_operand" "")
7814 (match_operand:DI 2 "nonimmediate_operand" "")))
7815 (set (match_operand:DI 3 "register_operand" "")
7816 (umod:DI (match_dup 1) (match_dup 2)))
7817 (clobber (reg:CC 17))]
7818 "TARGET_64BIT && reload_completed"
7819 [(set (match_dup 3) (const_int 0))
7820 (parallel [(set (match_dup 0)
7821 (udiv:DI (match_dup 1) (match_dup 2)))
7823 (umod:DI (match_dup 1) (match_dup 2)))
7825 (clobber (reg:CC 17))])]
7828 (define_insn "udivmodsi4"
7829 [(set (match_operand:SI 0 "register_operand" "=a")
7830 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7831 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7832 (set (match_operand:SI 3 "register_operand" "=&d")
7833 (umod:SI (match_dup 1) (match_dup 2)))
7834 (clobber (reg:CC 17))]
7836 "xor{l}\t%3, %3\;div{l}\t%2"
7837 [(set_attr "type" "multi")
7838 (set_attr "length_immediate" "0")
7839 (set_attr "mode" "SI")])
7841 (define_insn "*udivmodsi4_noext"
7842 [(set (match_operand:SI 0 "register_operand" "=a")
7843 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7844 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7845 (set (match_operand:SI 3 "register_operand" "=d")
7846 (umod:SI (match_dup 1) (match_dup 2)))
7848 (clobber (reg:CC 17))]
7851 [(set_attr "type" "idiv")
7852 (set_attr "ppro_uops" "few")
7853 (set_attr "mode" "SI")])
7856 [(set (match_operand:SI 0 "register_operand" "")
7857 (udiv:SI (match_operand:SI 1 "register_operand" "")
7858 (match_operand:SI 2 "nonimmediate_operand" "")))
7859 (set (match_operand:SI 3 "register_operand" "")
7860 (umod:SI (match_dup 1) (match_dup 2)))
7861 (clobber (reg:CC 17))]
7863 [(set (match_dup 3) (const_int 0))
7864 (parallel [(set (match_dup 0)
7865 (udiv:SI (match_dup 1) (match_dup 2)))
7867 (umod:SI (match_dup 1) (match_dup 2)))
7869 (clobber (reg:CC 17))])]
7872 (define_expand "udivmodhi4"
7873 [(set (match_dup 4) (const_int 0))
7874 (parallel [(set (match_operand:HI 0 "register_operand" "")
7875 (udiv:HI (match_operand:HI 1 "register_operand" "")
7876 (match_operand:HI 2 "nonimmediate_operand" "")))
7877 (set (match_operand:HI 3 "register_operand" "")
7878 (umod:HI (match_dup 1) (match_dup 2)))
7880 (clobber (reg:CC 17))])]
7881 "TARGET_HIMODE_MATH"
7882 "operands[4] = gen_reg_rtx (HImode);")
7884 (define_insn "*udivmodhi_noext"
7885 [(set (match_operand:HI 0 "register_operand" "=a")
7886 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7887 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7888 (set (match_operand:HI 3 "register_operand" "=d")
7889 (umod:HI (match_dup 1) (match_dup 2)))
7890 (use (match_operand:HI 4 "register_operand" "3"))
7891 (clobber (reg:CC 17))]
7894 [(set_attr "type" "idiv")
7895 (set_attr "mode" "HI")
7896 (set_attr "ppro_uops" "few")])
7898 ;; We can not use div/idiv for double division, because it causes
7899 ;; "division by zero" on the overflow and that's not what we expect
7900 ;; from truncate. Because true (non truncating) double division is
7901 ;; never generated, we can't create this insn anyway.
7904 ; [(set (match_operand:SI 0 "register_operand" "=a")
7906 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7908 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7909 ; (set (match_operand:SI 3 "register_operand" "=d")
7911 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7912 ; (clobber (reg:CC 17))]
7914 ; "div{l}\t{%2, %0|%0, %2}"
7915 ; [(set_attr "type" "idiv")
7916 ; (set_attr "ppro_uops" "few")])
7918 ;;- Logical AND instructions
7920 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7921 ;; Note that this excludes ah.
7923 (define_insn "*testdi_1_rex64"
7926 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7927 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7929 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7931 test{l}\t{%k1, %k0|%k0, %k1}
7932 test{l}\t{%k1, %k0|%k0, %k1}
7933 test{q}\t{%1, %0|%0, %1}
7934 test{q}\t{%1, %0|%0, %1}
7935 test{q}\t{%1, %0|%0, %1}"
7936 [(set_attr "type" "test")
7937 (set_attr "modrm" "0,1,0,1,1")
7938 (set_attr "mode" "SI,SI,DI,DI,DI")
7939 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7941 (define_insn "testsi_1"
7944 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7945 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7947 "ix86_match_ccmode (insn, CCNOmode)"
7948 "test{l}\t{%1, %0|%0, %1}"
7949 [(set_attr "type" "test")
7950 (set_attr "modrm" "0,1,1")
7951 (set_attr "mode" "SI")
7952 (set_attr "pent_pair" "uv,np,uv")])
7954 (define_expand "testsi_ccno_1"
7957 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7958 (match_operand:SI 1 "nonmemory_operand" ""))
7963 (define_insn "*testhi_1"
7965 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7966 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7968 "ix86_match_ccmode (insn, CCNOmode)"
7969 "test{w}\t{%1, %0|%0, %1}"
7970 [(set_attr "type" "test")
7971 (set_attr "modrm" "0,1,1")
7972 (set_attr "mode" "HI")
7973 (set_attr "pent_pair" "uv,np,uv")])
7975 (define_expand "testqi_ccz_1"
7977 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7978 (match_operand:QI 1 "nonmemory_operand" ""))
7983 (define_insn "*testqi_1"
7985 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7986 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7988 "ix86_match_ccmode (insn, CCNOmode)"
7990 if (which_alternative == 3)
7992 if (GET_CODE (operands[1]) == CONST_INT
7993 && (INTVAL (operands[1]) & 0xffffff00))
7994 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7995 return "test{l}\t{%1, %k0|%k0, %1}";
7997 return "test{b}\t{%1, %0|%0, %1}";
7999 [(set_attr "type" "test")
8000 (set_attr "modrm" "0,1,1,1")
8001 (set_attr "mode" "QI,QI,QI,SI")
8002 (set_attr "pent_pair" "uv,np,uv,np")])
8004 (define_expand "testqi_ext_ccno_0"
8009 (match_operand 0 "ext_register_operand" "")
8012 (match_operand 1 "const_int_operand" ""))
8017 (define_insn "*testqi_ext_0"
8022 (match_operand 0 "ext_register_operand" "Q")
8025 (match_operand 1 "const_int_operand" "n"))
8027 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
8028 && ix86_match_ccmode (insn, CCNOmode)"
8029 "test{b}\t{%1, %h0|%h0, %1}"
8030 [(set_attr "type" "test")
8031 (set_attr "mode" "QI")
8032 (set_attr "length_immediate" "1")
8033 (set_attr "pent_pair" "np")])
8035 (define_insn "*testqi_ext_1"
8040 (match_operand 0 "ext_register_operand" "Q")
8044 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
8046 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8047 "test{b}\t{%1, %h0|%h0, %1}"
8048 [(set_attr "type" "test")
8049 (set_attr "mode" "QI")])
8051 (define_insn "*testqi_ext_1_rex64"
8056 (match_operand 0 "ext_register_operand" "Q")
8060 (match_operand:QI 1 "register_operand" "Q")))
8062 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8063 "test{b}\t{%1, %h0|%h0, %1}"
8064 [(set_attr "type" "test")
8065 (set_attr "mode" "QI")])
8067 (define_insn "*testqi_ext_2"
8072 (match_operand 0 "ext_register_operand" "Q")
8076 (match_operand 1 "ext_register_operand" "Q")
8080 "ix86_match_ccmode (insn, CCNOmode)"
8081 "test{b}\t{%h1, %h0|%h0, %h1}"
8082 [(set_attr "type" "test")
8083 (set_attr "mode" "QI")])
8085 ;; Combine likes to form bit extractions for some tests. Humor it.
8086 (define_insn "*testqi_ext_3"
8088 (compare (zero_extract:SI
8089 (match_operand 0 "nonimmediate_operand" "rm")
8090 (match_operand:SI 1 "const_int_operand" "")
8091 (match_operand:SI 2 "const_int_operand" ""))
8093 "ix86_match_ccmode (insn, CCNOmode)
8094 && (GET_MODE (operands[0]) == SImode
8095 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8096 || GET_MODE (operands[0]) == HImode
8097 || GET_MODE (operands[0]) == QImode)"
8100 (define_insn "*testqi_ext_3_rex64"
8102 (compare (zero_extract:DI
8103 (match_operand 0 "nonimmediate_operand" "rm")
8104 (match_operand:DI 1 "const_int_operand" "")
8105 (match_operand:DI 2 "const_int_operand" ""))
8108 && ix86_match_ccmode (insn, CCNOmode)
8109 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8110 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8111 /* Ensure that resulting mask is zero or sign extended operand. */
8112 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8113 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8114 && INTVAL (operands[1]) > 32))
8115 && (GET_MODE (operands[0]) == SImode
8116 || GET_MODE (operands[0]) == DImode
8117 || GET_MODE (operands[0]) == HImode
8118 || GET_MODE (operands[0]) == QImode)"
8123 (compare (zero_extract
8124 (match_operand 0 "nonimmediate_operand" "")
8125 (match_operand 1 "const_int_operand" "")
8126 (match_operand 2 "const_int_operand" ""))
8128 "ix86_match_ccmode (insn, CCNOmode)"
8129 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8131 HOST_WIDE_INT len = INTVAL (operands[1]);
8132 HOST_WIDE_INT pos = INTVAL (operands[2]);
8134 enum machine_mode mode, submode;
8136 mode = GET_MODE (operands[0]);
8137 if (GET_CODE (operands[0]) == MEM)
8139 /* ??? Combine likes to put non-volatile mem extractions in QImode
8140 no matter the size of the test. So find a mode that works. */
8141 if (! MEM_VOLATILE_P (operands[0]))
8143 mode = smallest_mode_for_size (pos + len, MODE_INT);
8144 operands[0] = adjust_address (operands[0], mode, 0);
8147 else if (GET_CODE (operands[0]) == SUBREG
8148 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8149 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8150 && pos + len <= GET_MODE_BITSIZE (submode))
8152 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8154 operands[0] = SUBREG_REG (operands[0]);
8156 else if (mode == HImode && pos + len <= 8)
8158 /* Small HImode tests can be converted to QImode. */
8160 operands[0] = gen_lowpart (QImode, operands[0]);
8163 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8164 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8166 operands[3] = gen_rtx_AND (mode, operands[0],
8167 GEN_INT (trunc_int_for_mode (mask, mode)));
8170 ;; %%% This used to optimize known byte-wide and operations to memory,
8171 ;; and sometimes to QImode registers. If this is considered useful,
8172 ;; it should be done with splitters.
8174 (define_expand "anddi3"
8175 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8176 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8177 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8178 (clobber (reg:CC 17))]
8180 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8182 (define_insn "*anddi_1_rex64"
8183 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8184 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8185 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8186 (clobber (reg:CC 17))]
8187 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8189 switch (get_attr_type (insn))
8193 enum machine_mode mode;
8195 if (GET_CODE (operands[2]) != CONST_INT)
8197 if (INTVAL (operands[2]) == 0xff)
8199 else if (INTVAL (operands[2]) == 0xffff)
8204 operands[1] = gen_lowpart (mode, operands[1]);
8206 return "movz{bq|x}\t{%1,%0|%0, %1}";
8208 return "movz{wq|x}\t{%1,%0|%0, %1}";
8212 if (! rtx_equal_p (operands[0], operands[1]))
8214 if (get_attr_mode (insn) == MODE_SI)
8215 return "and{l}\t{%k2, %k0|%k0, %k2}";
8217 return "and{q}\t{%2, %0|%0, %2}";
8220 [(set_attr "type" "alu,alu,alu,imovx")
8221 (set_attr "length_immediate" "*,*,*,0")
8222 (set_attr "mode" "SI,DI,DI,DI")])
8224 (define_insn "*anddi_2"
8226 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8227 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8229 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8230 (and:DI (match_dup 1) (match_dup 2)))]
8231 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8232 && ix86_binary_operator_ok (AND, DImode, operands)"
8234 and{l}\t{%k2, %k0|%k0, %k2}
8235 and{q}\t{%2, %0|%0, %2}
8236 and{q}\t{%2, %0|%0, %2}"
8237 [(set_attr "type" "alu")
8238 (set_attr "mode" "SI,DI,DI")])
8240 (define_expand "andsi3"
8241 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8242 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8243 (match_operand:SI 2 "general_operand" "")))
8244 (clobber (reg:CC 17))]
8246 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8248 (define_insn "*andsi_1"
8249 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8250 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8251 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8252 (clobber (reg:CC 17))]
8253 "ix86_binary_operator_ok (AND, SImode, operands)"
8255 switch (get_attr_type (insn))
8259 enum machine_mode mode;
8261 if (GET_CODE (operands[2]) != CONST_INT)
8263 if (INTVAL (operands[2]) == 0xff)
8265 else if (INTVAL (operands[2]) == 0xffff)
8270 operands[1] = gen_lowpart (mode, operands[1]);
8272 return "movz{bl|x}\t{%1,%0|%0, %1}";
8274 return "movz{wl|x}\t{%1,%0|%0, %1}";
8278 if (! rtx_equal_p (operands[0], operands[1]))
8280 return "and{l}\t{%2, %0|%0, %2}";
8283 [(set_attr "type" "alu,alu,imovx")
8284 (set_attr "length_immediate" "*,*,0")
8285 (set_attr "mode" "SI")])
8288 [(set (match_operand 0 "register_operand" "")
8290 (const_int -65536)))
8291 (clobber (reg:CC 17))]
8293 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8294 "operands[1] = gen_lowpart (HImode, operands[0]);")
8297 [(set (match_operand 0 "ext_register_operand" "")
8300 (clobber (reg:CC 17))]
8301 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8302 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8303 "operands[1] = gen_lowpart (QImode, operands[0]);")
8306 [(set (match_operand 0 "ext_register_operand" "")
8308 (const_int -65281)))
8309 (clobber (reg:CC 17))]
8310 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8311 [(parallel [(set (zero_extract:SI (match_dup 0)
8315 (zero_extract:SI (match_dup 0)
8318 (zero_extract:SI (match_dup 0)
8321 (clobber (reg:CC 17))])]
8322 "operands[0] = gen_lowpart (SImode, operands[0]);")
8324 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8325 (define_insn "*andsi_1_zext"
8326 [(set (match_operand:DI 0 "register_operand" "=r")
8328 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8329 (match_operand:SI 2 "general_operand" "rim"))))
8330 (clobber (reg:CC 17))]
8331 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8332 "and{l}\t{%2, %k0|%k0, %2}"
8333 [(set_attr "type" "alu")
8334 (set_attr "mode" "SI")])
8336 (define_insn "*andsi_2"
8338 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8339 (match_operand:SI 2 "general_operand" "rim,ri"))
8341 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8342 (and:SI (match_dup 1) (match_dup 2)))]
8343 "ix86_match_ccmode (insn, CCNOmode)
8344 && ix86_binary_operator_ok (AND, SImode, operands)"
8345 "and{l}\t{%2, %0|%0, %2}"
8346 [(set_attr "type" "alu")
8347 (set_attr "mode" "SI")])
8349 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8350 (define_insn "*andsi_2_zext"
8352 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8353 (match_operand:SI 2 "general_operand" "rim"))
8355 (set (match_operand:DI 0 "register_operand" "=r")
8356 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8357 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8358 && ix86_binary_operator_ok (AND, SImode, operands)"
8359 "and{l}\t{%2, %k0|%k0, %2}"
8360 [(set_attr "type" "alu")
8361 (set_attr "mode" "SI")])
8363 (define_expand "andhi3"
8364 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8365 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8366 (match_operand:HI 2 "general_operand" "")))
8367 (clobber (reg:CC 17))]
8368 "TARGET_HIMODE_MATH"
8369 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8371 (define_insn "*andhi_1"
8372 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8373 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8374 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8375 (clobber (reg:CC 17))]
8376 "ix86_binary_operator_ok (AND, HImode, operands)"
8378 switch (get_attr_type (insn))
8381 if (GET_CODE (operands[2]) != CONST_INT)
8383 if (INTVAL (operands[2]) == 0xff)
8384 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8388 if (! rtx_equal_p (operands[0], operands[1]))
8391 return "and{w}\t{%2, %0|%0, %2}";
8394 [(set_attr "type" "alu,alu,imovx")
8395 (set_attr "length_immediate" "*,*,0")
8396 (set_attr "mode" "HI,HI,SI")])
8398 (define_insn "*andhi_2"
8400 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8401 (match_operand:HI 2 "general_operand" "rim,ri"))
8403 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8404 (and:HI (match_dup 1) (match_dup 2)))]
8405 "ix86_match_ccmode (insn, CCNOmode)
8406 && ix86_binary_operator_ok (AND, HImode, operands)"
8407 "and{w}\t{%2, %0|%0, %2}"
8408 [(set_attr "type" "alu")
8409 (set_attr "mode" "HI")])
8411 (define_expand "andqi3"
8412 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8413 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8414 (match_operand:QI 2 "general_operand" "")))
8415 (clobber (reg:CC 17))]
8416 "TARGET_QIMODE_MATH"
8417 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8419 ;; %%% Potential partial reg stall on alternative 2. What to do?
8420 (define_insn "*andqi_1"
8421 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8422 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8423 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8424 (clobber (reg:CC 17))]
8425 "ix86_binary_operator_ok (AND, QImode, operands)"
8427 and{b}\t{%2, %0|%0, %2}
8428 and{b}\t{%2, %0|%0, %2}
8429 and{l}\t{%k2, %k0|%k0, %k2}"
8430 [(set_attr "type" "alu")
8431 (set_attr "mode" "QI,QI,SI")])
8433 (define_insn "*andqi_1_slp"
8434 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8435 (and:QI (match_dup 0)
8436 (match_operand:QI 1 "general_operand" "qi,qmi")))
8437 (clobber (reg:CC 17))]
8439 "and{b}\t{%1, %0|%0, %1}"
8440 [(set_attr "type" "alu1")
8441 (set_attr "mode" "QI")])
8443 (define_insn "*andqi_2"
8446 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8447 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8449 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8450 (and:QI (match_dup 1) (match_dup 2)))]
8451 "ix86_match_ccmode (insn, CCNOmode)
8452 && ix86_binary_operator_ok (AND, QImode, operands)"
8454 if (which_alternative == 2)
8456 if (GET_CODE (operands[2]) == CONST_INT
8457 && (INTVAL (operands[2]) & 0xffffff00))
8458 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8459 return "and{l}\t{%2, %k0|%k0, %2}";
8461 return "and{b}\t{%2, %0|%0, %2}";
8463 [(set_attr "type" "alu")
8464 (set_attr "mode" "QI,QI,SI")])
8466 (define_insn "*andqi_2_slp"
8469 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8470 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8472 (set (strict_low_part (match_dup 0))
8473 (and:QI (match_dup 0) (match_dup 1)))]
8474 "ix86_match_ccmode (insn, CCNOmode)"
8475 "and{b}\t{%1, %0|%0, %1}"
8476 [(set_attr "type" "alu1")
8477 (set_attr "mode" "QI")])
8479 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8480 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8481 ;; for a QImode operand, which of course failed.
8483 (define_insn "andqi_ext_0"
8484 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8489 (match_operand 1 "ext_register_operand" "0")
8492 (match_operand 2 "const_int_operand" "n")))
8493 (clobber (reg:CC 17))]
8494 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8495 "and{b}\t{%2, %h0|%h0, %2}"
8496 [(set_attr "type" "alu")
8497 (set_attr "length_immediate" "1")
8498 (set_attr "mode" "QI")])
8500 ;; Generated by peephole translating test to and. This shows up
8501 ;; often in fp comparisons.
8503 (define_insn "*andqi_ext_0_cc"
8508 (match_operand 1 "ext_register_operand" "0")
8511 (match_operand 2 "const_int_operand" "n"))
8513 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8522 "ix86_match_ccmode (insn, CCNOmode)
8523 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8524 "and{b}\t{%2, %h0|%h0, %2}"
8525 [(set_attr "type" "alu")
8526 (set_attr "length_immediate" "1")
8527 (set_attr "mode" "QI")])
8529 (define_insn "*andqi_ext_1"
8530 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8535 (match_operand 1 "ext_register_operand" "0")
8539 (match_operand:QI 2 "general_operand" "Qm"))))
8540 (clobber (reg:CC 17))]
8542 "and{b}\t{%2, %h0|%h0, %2}"
8543 [(set_attr "type" "alu")
8544 (set_attr "length_immediate" "0")
8545 (set_attr "mode" "QI")])
8547 (define_insn "*andqi_ext_1_rex64"
8548 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8553 (match_operand 1 "ext_register_operand" "0")
8557 (match_operand 2 "ext_register_operand" "Q"))))
8558 (clobber (reg:CC 17))]
8560 "and{b}\t{%2, %h0|%h0, %2}"
8561 [(set_attr "type" "alu")
8562 (set_attr "length_immediate" "0")
8563 (set_attr "mode" "QI")])
8565 (define_insn "*andqi_ext_2"
8566 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8571 (match_operand 1 "ext_register_operand" "%0")
8575 (match_operand 2 "ext_register_operand" "Q")
8578 (clobber (reg:CC 17))]
8580 "and{b}\t{%h2, %h0|%h0, %h2}"
8581 [(set_attr "type" "alu")
8582 (set_attr "length_immediate" "0")
8583 (set_attr "mode" "QI")])
8585 ;; Logical inclusive OR instructions
8587 ;; %%% This used to optimize known byte-wide and operations to memory.
8588 ;; If this is considered useful, it should be done with splitters.
8590 (define_expand "iordi3"
8591 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8592 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8593 (match_operand:DI 2 "x86_64_general_operand" "")))
8594 (clobber (reg:CC 17))]
8596 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8598 (define_insn "*iordi_1_rex64"
8599 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8600 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8601 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8602 (clobber (reg:CC 17))]
8604 && ix86_binary_operator_ok (IOR, DImode, operands)"
8605 "or{q}\t{%2, %0|%0, %2}"
8606 [(set_attr "type" "alu")
8607 (set_attr "mode" "DI")])
8609 (define_insn "*iordi_2_rex64"
8611 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8612 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8614 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8615 (ior:DI (match_dup 1) (match_dup 2)))]
8617 && ix86_match_ccmode (insn, CCNOmode)
8618 && ix86_binary_operator_ok (IOR, DImode, operands)"
8619 "or{q}\t{%2, %0|%0, %2}"
8620 [(set_attr "type" "alu")
8621 (set_attr "mode" "DI")])
8623 (define_insn "*iordi_3_rex64"
8625 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8626 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8628 (clobber (match_scratch:DI 0 "=r"))]
8630 && ix86_match_ccmode (insn, CCNOmode)
8631 && ix86_binary_operator_ok (IOR, DImode, operands)"
8632 "or{q}\t{%2, %0|%0, %2}"
8633 [(set_attr "type" "alu")
8634 (set_attr "mode" "DI")])
8637 (define_expand "iorsi3"
8638 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8639 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8640 (match_operand:SI 2 "general_operand" "")))
8641 (clobber (reg:CC 17))]
8643 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8645 (define_insn "*iorsi_1"
8646 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8647 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8648 (match_operand:SI 2 "general_operand" "ri,rmi")))
8649 (clobber (reg:CC 17))]
8650 "ix86_binary_operator_ok (IOR, SImode, operands)"
8651 "or{l}\t{%2, %0|%0, %2}"
8652 [(set_attr "type" "alu")
8653 (set_attr "mode" "SI")])
8655 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8656 (define_insn "*iorsi_1_zext"
8657 [(set (match_operand:DI 0 "register_operand" "=rm")
8659 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8660 (match_operand:SI 2 "general_operand" "rim"))))
8661 (clobber (reg:CC 17))]
8662 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8663 "or{l}\t{%2, %k0|%k0, %2}"
8664 [(set_attr "type" "alu")
8665 (set_attr "mode" "SI")])
8667 (define_insn "*iorsi_1_zext_imm"
8668 [(set (match_operand:DI 0 "register_operand" "=rm")
8669 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8670 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8671 (clobber (reg:CC 17))]
8673 "or{l}\t{%2, %k0|%k0, %2}"
8674 [(set_attr "type" "alu")
8675 (set_attr "mode" "SI")])
8677 (define_insn "*iorsi_2"
8679 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8680 (match_operand:SI 2 "general_operand" "rim,ri"))
8682 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8683 (ior:SI (match_dup 1) (match_dup 2)))]
8684 "ix86_match_ccmode (insn, CCNOmode)
8685 && ix86_binary_operator_ok (IOR, SImode, operands)"
8686 "or{l}\t{%2, %0|%0, %2}"
8687 [(set_attr "type" "alu")
8688 (set_attr "mode" "SI")])
8690 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8691 ;; ??? Special case for immediate operand is missing - it is tricky.
8692 (define_insn "*iorsi_2_zext"
8694 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8695 (match_operand:SI 2 "general_operand" "rim"))
8697 (set (match_operand:DI 0 "register_operand" "=r")
8698 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8699 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8700 && ix86_binary_operator_ok (IOR, SImode, operands)"
8701 "or{l}\t{%2, %k0|%k0, %2}"
8702 [(set_attr "type" "alu")
8703 (set_attr "mode" "SI")])
8705 (define_insn "*iorsi_2_zext_imm"
8707 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8708 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8710 (set (match_operand:DI 0 "register_operand" "=r")
8711 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8712 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8713 && ix86_binary_operator_ok (IOR, SImode, operands)"
8714 "or{l}\t{%2, %k0|%k0, %2}"
8715 [(set_attr "type" "alu")
8716 (set_attr "mode" "SI")])
8718 (define_insn "*iorsi_3"
8720 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8721 (match_operand:SI 2 "general_operand" "rim"))
8723 (clobber (match_scratch:SI 0 "=r"))]
8724 "ix86_match_ccmode (insn, CCNOmode)
8725 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8726 "or{l}\t{%2, %0|%0, %2}"
8727 [(set_attr "type" "alu")
8728 (set_attr "mode" "SI")])
8730 (define_expand "iorhi3"
8731 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8732 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8733 (match_operand:HI 2 "general_operand" "")))
8734 (clobber (reg:CC 17))]
8735 "TARGET_HIMODE_MATH"
8736 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8738 (define_insn "*iorhi_1"
8739 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8740 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8741 (match_operand:HI 2 "general_operand" "rmi,ri")))
8742 (clobber (reg:CC 17))]
8743 "ix86_binary_operator_ok (IOR, HImode, operands)"
8744 "or{w}\t{%2, %0|%0, %2}"
8745 [(set_attr "type" "alu")
8746 (set_attr "mode" "HI")])
8748 (define_insn "*iorhi_2"
8750 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8751 (match_operand:HI 2 "general_operand" "rim,ri"))
8753 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8754 (ior:HI (match_dup 1) (match_dup 2)))]
8755 "ix86_match_ccmode (insn, CCNOmode)
8756 && ix86_binary_operator_ok (IOR, HImode, operands)"
8757 "or{w}\t{%2, %0|%0, %2}"
8758 [(set_attr "type" "alu")
8759 (set_attr "mode" "HI")])
8761 (define_insn "*iorhi_3"
8763 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8764 (match_operand:HI 2 "general_operand" "rim"))
8766 (clobber (match_scratch:HI 0 "=r"))]
8767 "ix86_match_ccmode (insn, CCNOmode)
8768 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8769 "or{w}\t{%2, %0|%0, %2}"
8770 [(set_attr "type" "alu")
8771 (set_attr "mode" "HI")])
8773 (define_expand "iorqi3"
8774 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8775 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8776 (match_operand:QI 2 "general_operand" "")))
8777 (clobber (reg:CC 17))]
8778 "TARGET_QIMODE_MATH"
8779 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8781 ;; %%% Potential partial reg stall on alternative 2. What to do?
8782 (define_insn "*iorqi_1"
8783 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8784 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8785 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8786 (clobber (reg:CC 17))]
8787 "ix86_binary_operator_ok (IOR, QImode, operands)"
8789 or{b}\t{%2, %0|%0, %2}
8790 or{b}\t{%2, %0|%0, %2}
8791 or{l}\t{%k2, %k0|%k0, %k2}"
8792 [(set_attr "type" "alu")
8793 (set_attr "mode" "QI,QI,SI")])
8795 (define_insn "*iorqi_1_slp"
8796 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8797 (ior:QI (match_dup 0)
8798 (match_operand:QI 1 "general_operand" "qmi,qi")))
8799 (clobber (reg:CC 17))]
8801 "or{b}\t{%1, %0|%0, %1}"
8802 [(set_attr "type" "alu1")
8803 (set_attr "mode" "QI")])
8805 (define_insn "*iorqi_2"
8807 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8808 (match_operand:QI 2 "general_operand" "qim,qi"))
8810 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8811 (ior:QI (match_dup 1) (match_dup 2)))]
8812 "ix86_match_ccmode (insn, CCNOmode)
8813 && ix86_binary_operator_ok (IOR, QImode, operands)"
8814 "or{b}\t{%2, %0|%0, %2}"
8815 [(set_attr "type" "alu")
8816 (set_attr "mode" "QI")])
8818 (define_insn "*iorqi_2_slp"
8820 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8821 (match_operand:QI 1 "general_operand" "qim,qi"))
8823 (set (strict_low_part (match_dup 0))
8824 (ior:QI (match_dup 0) (match_dup 1)))]
8825 "ix86_match_ccmode (insn, CCNOmode)"
8826 "or{b}\t{%1, %0|%0, %1}"
8827 [(set_attr "type" "alu1")
8828 (set_attr "mode" "QI")])
8830 (define_insn "*iorqi_3"
8832 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8833 (match_operand:QI 2 "general_operand" "qim"))
8835 (clobber (match_scratch:QI 0 "=q"))]
8836 "ix86_match_ccmode (insn, CCNOmode)
8837 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8838 "or{b}\t{%2, %0|%0, %2}"
8839 [(set_attr "type" "alu")
8840 (set_attr "mode" "QI")])
8843 ;; Logical XOR instructions
8845 ;; %%% This used to optimize known byte-wide and operations to memory.
8846 ;; If this is considered useful, it should be done with splitters.
8848 (define_expand "xordi3"
8849 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8850 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8851 (match_operand:DI 2 "x86_64_general_operand" "")))
8852 (clobber (reg:CC 17))]
8854 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8856 (define_insn "*xordi_1_rex64"
8857 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8858 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8859 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8860 (clobber (reg:CC 17))]
8862 && ix86_binary_operator_ok (XOR, DImode, operands)"
8864 xor{q}\t{%2, %0|%0, %2}
8865 xor{q}\t{%2, %0|%0, %2}"
8866 [(set_attr "type" "alu")
8867 (set_attr "mode" "DI,DI")])
8869 (define_insn "*xordi_2_rex64"
8871 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8872 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8874 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8875 (xor:DI (match_dup 1) (match_dup 2)))]
8877 && ix86_match_ccmode (insn, CCNOmode)
8878 && ix86_binary_operator_ok (XOR, DImode, operands)"
8880 xor{q}\t{%2, %0|%0, %2}
8881 xor{q}\t{%2, %0|%0, %2}"
8882 [(set_attr "type" "alu")
8883 (set_attr "mode" "DI,DI")])
8885 (define_insn "*xordi_3_rex64"
8887 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8888 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8890 (clobber (match_scratch:DI 0 "=r"))]
8892 && ix86_match_ccmode (insn, CCNOmode)
8893 && ix86_binary_operator_ok (XOR, DImode, operands)"
8894 "xor{q}\t{%2, %0|%0, %2}"
8895 [(set_attr "type" "alu")
8896 (set_attr "mode" "DI")])
8898 (define_expand "xorsi3"
8899 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8900 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8901 (match_operand:SI 2 "general_operand" "")))
8902 (clobber (reg:CC 17))]
8904 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8906 (define_insn "*xorsi_1"
8907 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8908 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8909 (match_operand:SI 2 "general_operand" "ri,rm")))
8910 (clobber (reg:CC 17))]
8911 "ix86_binary_operator_ok (XOR, SImode, operands)"
8912 "xor{l}\t{%2, %0|%0, %2}"
8913 [(set_attr "type" "alu")
8914 (set_attr "mode" "SI")])
8916 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8917 ;; Add speccase for immediates
8918 (define_insn "*xorsi_1_zext"
8919 [(set (match_operand:DI 0 "register_operand" "=r")
8921 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8922 (match_operand:SI 2 "general_operand" "rim"))))
8923 (clobber (reg:CC 17))]
8924 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8925 "xor{l}\t{%2, %k0|%k0, %2}"
8926 [(set_attr "type" "alu")
8927 (set_attr "mode" "SI")])
8929 (define_insn "*xorsi_1_zext_imm"
8930 [(set (match_operand:DI 0 "register_operand" "=r")
8931 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8932 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8933 (clobber (reg:CC 17))]
8934 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8935 "xor{l}\t{%2, %k0|%k0, %2}"
8936 [(set_attr "type" "alu")
8937 (set_attr "mode" "SI")])
8939 (define_insn "*xorsi_2"
8941 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8942 (match_operand:SI 2 "general_operand" "rim,ri"))
8944 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8945 (xor:SI (match_dup 1) (match_dup 2)))]
8946 "ix86_match_ccmode (insn, CCNOmode)
8947 && ix86_binary_operator_ok (XOR, SImode, operands)"
8948 "xor{l}\t{%2, %0|%0, %2}"
8949 [(set_attr "type" "alu")
8950 (set_attr "mode" "SI")])
8952 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8953 ;; ??? Special case for immediate operand is missing - it is tricky.
8954 (define_insn "*xorsi_2_zext"
8956 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8957 (match_operand:SI 2 "general_operand" "rim"))
8959 (set (match_operand:DI 0 "register_operand" "=r")
8960 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8961 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8962 && ix86_binary_operator_ok (XOR, SImode, operands)"
8963 "xor{l}\t{%2, %k0|%k0, %2}"
8964 [(set_attr "type" "alu")
8965 (set_attr "mode" "SI")])
8967 (define_insn "*xorsi_2_zext_imm"
8969 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8970 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8972 (set (match_operand:DI 0 "register_operand" "=r")
8973 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8974 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8975 && ix86_binary_operator_ok (XOR, SImode, operands)"
8976 "xor{l}\t{%2, %k0|%k0, %2}"
8977 [(set_attr "type" "alu")
8978 (set_attr "mode" "SI")])
8980 (define_insn "*xorsi_3"
8982 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8983 (match_operand:SI 2 "general_operand" "rim"))
8985 (clobber (match_scratch:SI 0 "=r"))]
8986 "ix86_match_ccmode (insn, CCNOmode)
8987 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8988 "xor{l}\t{%2, %0|%0, %2}"
8989 [(set_attr "type" "alu")
8990 (set_attr "mode" "SI")])
8992 (define_expand "xorhi3"
8993 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8994 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8995 (match_operand:HI 2 "general_operand" "")))
8996 (clobber (reg:CC 17))]
8997 "TARGET_HIMODE_MATH"
8998 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9000 (define_insn "*xorhi_1"
9001 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9002 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9003 (match_operand:HI 2 "general_operand" "rmi,ri")))
9004 (clobber (reg:CC 17))]
9005 "ix86_binary_operator_ok (XOR, HImode, operands)"
9006 "xor{w}\t{%2, %0|%0, %2}"
9007 [(set_attr "type" "alu")
9008 (set_attr "mode" "HI")])
9010 (define_insn "*xorhi_2"
9012 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9013 (match_operand:HI 2 "general_operand" "rim,ri"))
9015 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9016 (xor:HI (match_dup 1) (match_dup 2)))]
9017 "ix86_match_ccmode (insn, CCNOmode)
9018 && ix86_binary_operator_ok (XOR, HImode, operands)"
9019 "xor{w}\t{%2, %0|%0, %2}"
9020 [(set_attr "type" "alu")
9021 (set_attr "mode" "HI")])
9023 (define_insn "*xorhi_3"
9025 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9026 (match_operand:HI 2 "general_operand" "rim"))
9028 (clobber (match_scratch:HI 0 "=r"))]
9029 "ix86_match_ccmode (insn, CCNOmode)
9030 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9031 "xor{w}\t{%2, %0|%0, %2}"
9032 [(set_attr "type" "alu")
9033 (set_attr "mode" "HI")])
9035 (define_expand "xorqi3"
9036 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9037 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9038 (match_operand:QI 2 "general_operand" "")))
9039 (clobber (reg:CC 17))]
9040 "TARGET_QIMODE_MATH"
9041 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9043 ;; %%% Potential partial reg stall on alternative 2. What to do?
9044 (define_insn "*xorqi_1"
9045 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9046 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9047 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9048 (clobber (reg:CC 17))]
9049 "ix86_binary_operator_ok (XOR, QImode, operands)"
9051 xor{b}\t{%2, %0|%0, %2}
9052 xor{b}\t{%2, %0|%0, %2}
9053 xor{l}\t{%k2, %k0|%k0, %k2}"
9054 [(set_attr "type" "alu")
9055 (set_attr "mode" "QI,QI,SI")])
9057 (define_insn "*xorqi_ext_1"
9058 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9062 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9065 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9068 (clobber (reg:CC 17))]
9070 "xor{b}\t{%h2, %h0|%h0, %h2}"
9071 [(set_attr "type" "alu")
9072 (set_attr "length_immediate" "0")
9073 (set_attr "mode" "QI")])
9075 (define_insn "*xorqi_cc_1"
9078 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9079 (match_operand:QI 2 "general_operand" "qim,qi"))
9081 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9082 (xor:QI (match_dup 1) (match_dup 2)))]
9083 "ix86_match_ccmode (insn, CCNOmode)
9084 && ix86_binary_operator_ok (XOR, QImode, operands)"
9085 "xor{b}\t{%2, %0|%0, %2}"
9086 [(set_attr "type" "alu")
9087 (set_attr "mode" "QI")])
9089 (define_insn "*xorqi_cc_2"
9092 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9093 (match_operand:QI 2 "general_operand" "qim"))
9095 (clobber (match_scratch:QI 0 "=q"))]
9096 "ix86_match_ccmode (insn, CCNOmode)
9097 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9098 "xor{b}\t{%2, %0|%0, %2}"
9099 [(set_attr "type" "alu")
9100 (set_attr "mode" "QI")])
9102 (define_insn "*xorqi_cc_ext_1"
9107 (match_operand 1 "ext_register_operand" "0")
9110 (match_operand:QI 2 "general_operand" "qmn"))
9112 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9116 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9118 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9119 "xor{b}\t{%2, %h0|%h0, %2}"
9120 [(set_attr "type" "alu")
9121 (set_attr "mode" "QI")])
9123 (define_insn "*xorqi_cc_ext_1_rex64"
9128 (match_operand 1 "ext_register_operand" "0")
9131 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9133 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9137 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9139 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9140 "xor{b}\t{%2, %h0|%h0, %2}"
9141 [(set_attr "type" "alu")
9142 (set_attr "mode" "QI")])
9144 (define_expand "xorqi_cc_ext_1"
9150 (match_operand 1 "ext_register_operand" "")
9153 (match_operand:QI 2 "general_operand" ""))
9155 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9159 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9164 ;; Negation instructions
9166 (define_expand "negdi2"
9167 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9168 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9169 (clobber (reg:CC 17))])]
9171 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9173 (define_insn "*negdi2_1"
9174 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9175 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9176 (clobber (reg:CC 17))]
9178 && ix86_unary_operator_ok (NEG, DImode, operands)"
9182 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9183 (neg:DI (match_operand:DI 1 "general_operand" "")))
9184 (clobber (reg:CC 17))]
9185 "!TARGET_64BIT && reload_completed"
9188 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9189 (set (match_dup 0) (neg:SI (match_dup 2)))])
9192 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9195 (clobber (reg:CC 17))])
9198 (neg:SI (match_dup 1)))
9199 (clobber (reg:CC 17))])]
9200 "split_di (operands+1, 1, operands+2, operands+3);
9201 split_di (operands+0, 1, operands+0, operands+1);")
9203 (define_insn "*negdi2_1_rex64"
9204 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9205 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9206 (clobber (reg:CC 17))]
9207 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9209 [(set_attr "type" "negnot")
9210 (set_attr "mode" "DI")])
9212 ;; The problem with neg is that it does not perform (compare x 0),
9213 ;; it really performs (compare 0 x), which leaves us with the zero
9214 ;; flag being the only useful item.
9216 (define_insn "*negdi2_cmpz_rex64"
9218 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9220 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9221 (neg:DI (match_dup 1)))]
9222 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9224 [(set_attr "type" "negnot")
9225 (set_attr "mode" "DI")])
9228 (define_expand "negsi2"
9229 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9230 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9231 (clobber (reg:CC 17))])]
9233 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9235 (define_insn "*negsi2_1"
9236 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9237 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9238 (clobber (reg:CC 17))]
9239 "ix86_unary_operator_ok (NEG, SImode, operands)"
9241 [(set_attr "type" "negnot")
9242 (set_attr "mode" "SI")])
9244 ;; Combine is quite creative about this pattern.
9245 (define_insn "*negsi2_1_zext"
9246 [(set (match_operand:DI 0 "register_operand" "=r")
9247 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9250 (clobber (reg:CC 17))]
9251 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9253 [(set_attr "type" "negnot")
9254 (set_attr "mode" "SI")])
9256 ;; The problem with neg is that it does not perform (compare x 0),
9257 ;; it really performs (compare 0 x), which leaves us with the zero
9258 ;; flag being the only useful item.
9260 (define_insn "*negsi2_cmpz"
9262 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9264 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9265 (neg:SI (match_dup 1)))]
9266 "ix86_unary_operator_ok (NEG, SImode, operands)"
9268 [(set_attr "type" "negnot")
9269 (set_attr "mode" "SI")])
9271 (define_insn "*negsi2_cmpz_zext"
9273 (compare:CCZ (lshiftrt:DI
9275 (match_operand:DI 1 "register_operand" "0")
9279 (set (match_operand:DI 0 "register_operand" "=r")
9280 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9283 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9285 [(set_attr "type" "negnot")
9286 (set_attr "mode" "SI")])
9288 (define_expand "neghi2"
9289 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9290 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9291 (clobber (reg:CC 17))])]
9292 "TARGET_HIMODE_MATH"
9293 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9295 (define_insn "*neghi2_1"
9296 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9297 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9298 (clobber (reg:CC 17))]
9299 "ix86_unary_operator_ok (NEG, HImode, operands)"
9301 [(set_attr "type" "negnot")
9302 (set_attr "mode" "HI")])
9304 (define_insn "*neghi2_cmpz"
9306 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9308 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9309 (neg:HI (match_dup 1)))]
9310 "ix86_unary_operator_ok (NEG, HImode, operands)"
9312 [(set_attr "type" "negnot")
9313 (set_attr "mode" "HI")])
9315 (define_expand "negqi2"
9316 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9317 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9318 (clobber (reg:CC 17))])]
9319 "TARGET_QIMODE_MATH"
9320 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9322 (define_insn "*negqi2_1"
9323 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9324 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9325 (clobber (reg:CC 17))]
9326 "ix86_unary_operator_ok (NEG, QImode, operands)"
9328 [(set_attr "type" "negnot")
9329 (set_attr "mode" "QI")])
9331 (define_insn "*negqi2_cmpz"
9333 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9335 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9336 (neg:QI (match_dup 1)))]
9337 "ix86_unary_operator_ok (NEG, QImode, operands)"
9339 [(set_attr "type" "negnot")
9340 (set_attr "mode" "QI")])
9342 ;; Changing of sign for FP values is doable using integer unit too.
9344 (define_expand "negsf2"
9345 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9346 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9347 (clobber (reg:CC 17))])]
9351 /* In case operand is in memory, we will not use SSE. */
9352 if (memory_operand (operands[0], VOIDmode)
9353 && rtx_equal_p (operands[0], operands[1]))
9354 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9357 /* Using SSE is tricky, since we need bitwise negation of -0
9359 rtx reg = gen_reg_rtx (SFmode);
9360 rtx dest = operands[0];
9362 operands[1] = force_reg (SFmode, operands[1]);
9363 operands[0] = force_reg (SFmode, operands[0]);
9364 emit_move_insn (reg,
9365 gen_lowpart (SFmode,
9366 GEN_INT (trunc_int_for_mode (0x80000000,
9368 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9369 if (dest != operands[0])
9370 emit_move_insn (dest, operands[0]);
9374 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9376 (define_insn "negsf2_memory"
9377 [(set (match_operand:SF 0 "memory_operand" "=m")
9378 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9379 (clobber (reg:CC 17))]
9380 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9383 (define_insn "negsf2_ifs"
9384 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9385 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9386 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
9387 (clobber (reg:CC 17))]
9389 && (reload_in_progress || reload_completed
9390 || (register_operand (operands[0], VOIDmode)
9391 && register_operand (operands[1], VOIDmode)))"
9395 [(set (match_operand:SF 0 "memory_operand" "")
9396 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9397 (use (match_operand:SF 2 "" ""))
9398 (clobber (reg:CC 17))]
9400 [(parallel [(set (match_dup 0)
9401 (neg:SF (match_dup 1)))
9402 (clobber (reg:CC 17))])])
9405 [(set (match_operand:SF 0 "register_operand" "")
9406 (neg:SF (match_operand:SF 1 "register_operand" "")))
9407 (use (match_operand:SF 2 "" ""))
9408 (clobber (reg:CC 17))]
9409 "reload_completed && !SSE_REG_P (operands[0])"
9410 [(parallel [(set (match_dup 0)
9411 (neg:SF (match_dup 1)))
9412 (clobber (reg:CC 17))])])
9415 [(set (match_operand:SF 0 "register_operand" "")
9416 (neg:SF (match_operand:SF 1 "register_operand" "")))
9417 (use (match_operand:SF 2 "register_operand" ""))
9418 (clobber (reg:CC 17))]
9419 "reload_completed && SSE_REG_P (operands[0])"
9420 [(set (subreg:TI (match_dup 0) 0)
9421 (xor:TI (subreg:TI (match_dup 1) 0)
9422 (subreg:TI (match_dup 2) 0)))]
9424 if (operands_match_p (operands[0], operands[2]))
9428 operands[1] = operands[2];
9434 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9435 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9437 (define_insn "*negsf2_if"
9438 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9439 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9440 (clobber (reg:CC 17))]
9441 "TARGET_80387 && !TARGET_SSE
9442 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9446 [(set (match_operand:SF 0 "register_operand" "")
9447 (neg:SF (match_operand:SF 1 "register_operand" "")))
9448 (clobber (reg:CC 17))]
9449 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9451 (neg:SF (match_dup 1)))]
9455 [(set (match_operand:SF 0 "register_operand" "")
9456 (neg:SF (match_operand:SF 1 "register_operand" "")))
9457 (clobber (reg:CC 17))]
9458 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9459 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9460 (clobber (reg:CC 17))])]
9461 "operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9462 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9465 [(set (match_operand 0 "memory_operand" "")
9466 (neg (match_operand 1 "memory_operand" "")))
9467 (clobber (reg:CC 17))]
9468 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9469 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9470 (clobber (reg:CC 17))])]
9472 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9474 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9477 operands[0] = adjust_address (operands[0], QImode, size - 1);
9478 operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
9481 (define_expand "negdf2"
9482 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9483 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9484 (clobber (reg:CC 17))])]
9488 /* In case operand is in memory, we will not use SSE. */
9489 if (memory_operand (operands[0], VOIDmode)
9490 && rtx_equal_p (operands[0], operands[1]))
9491 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9494 /* Using SSE is tricky, since we need bitwise negation of -0
9496 rtx reg = gen_reg_rtx (DFmode);
9497 #if HOST_BITS_PER_WIDE_INT >= 64
9498 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9501 rtx imm = immed_double_const (0, 0x80000000, DImode);
9503 rtx dest = operands[0];
9505 operands[1] = force_reg (DFmode, operands[1]);
9506 operands[0] = force_reg (DFmode, operands[0]);
9507 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9508 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9509 if (dest != operands[0])
9510 emit_move_insn (dest, operands[0]);
9514 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9516 (define_insn "negdf2_memory"
9517 [(set (match_operand:DF 0 "memory_operand" "=m")
9518 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9519 (clobber (reg:CC 17))]
9520 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9523 (define_insn "negdf2_ifs"
9524 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9525 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9526 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9527 (clobber (reg:CC 17))]
9528 "!TARGET_64BIT && TARGET_SSE2
9529 && (reload_in_progress || reload_completed
9530 || (register_operand (operands[0], VOIDmode)
9531 && register_operand (operands[1], VOIDmode)))"
9534 (define_insn "*negdf2_ifs_rex64"
9535 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9536 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9537 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9538 (clobber (reg:CC 17))]
9539 "TARGET_64BIT && TARGET_SSE2
9540 && (reload_in_progress || reload_completed
9541 || (register_operand (operands[0], VOIDmode)
9542 && register_operand (operands[1], VOIDmode)))"
9546 [(set (match_operand:DF 0 "memory_operand" "")
9547 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9548 (use (match_operand:DF 2 "" ""))
9549 (clobber (reg:CC 17))]
9551 [(parallel [(set (match_dup 0)
9552 (neg:DF (match_dup 1)))
9553 (clobber (reg:CC 17))])])
9556 [(set (match_operand:DF 0 "register_operand" "")
9557 (neg:DF (match_operand:DF 1 "register_operand" "")))
9558 (use (match_operand:DF 2 "" ""))
9559 (clobber (reg:CC 17))]
9560 "reload_completed && !SSE_REG_P (operands[0])
9561 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9562 [(parallel [(set (match_dup 0)
9563 (neg:DF (match_dup 1)))
9564 (clobber (reg:CC 17))])])
9567 [(set (match_operand:DF 0 "register_operand" "")
9568 (neg:DF (match_operand:DF 1 "register_operand" "")))
9569 (use (match_operand:DF 2 "" ""))
9570 (clobber (reg:CC 17))]
9571 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9572 [(parallel [(set (match_dup 0)
9573 (xor:DI (match_dup 1) (match_dup 2)))
9574 (clobber (reg:CC 17))])]
9575 "operands[0] = gen_lowpart (DImode, operands[0]);
9576 operands[1] = gen_lowpart (DImode, operands[1]);
9577 operands[2] = gen_lowpart (DImode, operands[2]);")
9580 [(set (match_operand:DF 0 "register_operand" "")
9581 (neg:DF (match_operand:DF 1 "register_operand" "")))
9582 (use (match_operand:DF 2 "register_operand" ""))
9583 (clobber (reg:CC 17))]
9584 "reload_completed && SSE_REG_P (operands[0])"
9585 [(set (subreg:TI (match_dup 0) 0)
9586 (xor:TI (subreg:TI (match_dup 1) 0)
9587 (subreg:TI (match_dup 2) 0)))]
9589 if (operands_match_p (operands[0], operands[2]))
9593 operands[1] = operands[2];
9598 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9599 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9601 (define_insn "*negdf2_if"
9602 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9603 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9604 (clobber (reg:CC 17))]
9605 "!TARGET_64BIT && TARGET_80387
9606 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9609 ;; FIXME: We should to allow integer registers here. Problem is that
9610 ;; we need another scratch register to get constant from.
9611 ;; Forcing constant to mem if no register available in peep2 should be
9612 ;; safe even for PIC mode, because of RIP relative addressing.
9613 (define_insn "*negdf2_if_rex64"
9614 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9615 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9616 (clobber (reg:CC 17))]
9617 "TARGET_64BIT && TARGET_80387
9618 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9622 [(set (match_operand:DF 0 "register_operand" "")
9623 (neg:DF (match_operand:DF 1 "register_operand" "")))
9624 (clobber (reg:CC 17))]
9625 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9627 (neg:DF (match_dup 1)))]
9631 [(set (match_operand:DF 0 "register_operand" "")
9632 (neg:DF (match_operand:DF 1 "register_operand" "")))
9633 (clobber (reg:CC 17))]
9634 "!TARGET_64BIT && TARGET_80387 && reload_completed
9635 && !FP_REGNO_P (REGNO (operands[0]))"
9636 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9637 (clobber (reg:CC 17))])]
9638 "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9639 split_di (operands+0, 1, operands+2, operands+3);")
9641 (define_expand "negxf2"
9642 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9643 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9644 (clobber (reg:CC 17))])]
9645 "!TARGET_64BIT && TARGET_80387"
9646 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9648 (define_expand "negtf2"
9649 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9650 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9651 (clobber (reg:CC 17))])]
9653 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9655 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9656 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9658 (define_insn "*negxf2_if"
9659 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9660 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9661 (clobber (reg:CC 17))]
9662 "!TARGET_64BIT && TARGET_80387
9663 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9667 [(set (match_operand:XF 0 "register_operand" "")
9668 (neg:XF (match_operand:XF 1 "register_operand" "")))
9669 (clobber (reg:CC 17))]
9670 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9672 (neg:XF (match_dup 1)))]
9676 [(set (match_operand:XF 0 "register_operand" "")
9677 (neg:XF (match_operand:XF 1 "register_operand" "")))
9678 (clobber (reg:CC 17))]
9679 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9680 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9681 (clobber (reg:CC 17))])]
9682 "operands[1] = GEN_INT (0x8000);
9683 operands[0] = gen_rtx_REG (SImode,
9684 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9686 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9687 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9689 (define_insn "*negtf2_if"
9690 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9691 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9692 (clobber (reg:CC 17))]
9693 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9697 [(set (match_operand:TF 0 "register_operand" "")
9698 (neg:TF (match_operand:TF 1 "register_operand" "")))
9699 (clobber (reg:CC 17))]
9700 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9702 (neg:TF (match_dup 1)))]
9706 [(set (match_operand:TF 0 "register_operand" "")
9707 (neg:TF (match_operand:TF 1 "register_operand" "")))
9708 (clobber (reg:CC 17))]
9709 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9710 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9711 (clobber (reg:CC 17))])]
9712 "operands[1] = GEN_INT (0x8000);
9713 operands[0] = gen_rtx_REG (SImode,
9714 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9716 ;; Conditionize these after reload. If they matches before reload, we
9717 ;; lose the clobber and ability to use integer instructions.
9719 (define_insn "*negsf2_1"
9720 [(set (match_operand:SF 0 "register_operand" "=f")
9721 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9722 "TARGET_80387 && reload_completed"
9724 [(set_attr "type" "fsgn")
9725 (set_attr "mode" "SF")
9726 (set_attr "ppro_uops" "few")])
9728 (define_insn "*negdf2_1"
9729 [(set (match_operand:DF 0 "register_operand" "=f")
9730 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9731 "TARGET_80387 && reload_completed"
9733 [(set_attr "type" "fsgn")
9734 (set_attr "mode" "DF")
9735 (set_attr "ppro_uops" "few")])
9737 (define_insn "*negextendsfdf2"
9738 [(set (match_operand:DF 0 "register_operand" "=f")
9739 (neg:DF (float_extend:DF
9740 (match_operand:SF 1 "register_operand" "0"))))]
9743 [(set_attr "type" "fsgn")
9744 (set_attr "mode" "DF")
9745 (set_attr "ppro_uops" "few")])
9747 (define_insn "*negxf2_1"
9748 [(set (match_operand:XF 0 "register_operand" "=f")
9749 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9750 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9752 [(set_attr "type" "fsgn")
9753 (set_attr "mode" "XF")
9754 (set_attr "ppro_uops" "few")])
9756 (define_insn "*negextenddfxf2"
9757 [(set (match_operand:XF 0 "register_operand" "=f")
9758 (neg:XF (float_extend:XF
9759 (match_operand:DF 1 "register_operand" "0"))))]
9760 "!TARGET_64BIT && TARGET_80387"
9762 [(set_attr "type" "fsgn")
9763 (set_attr "mode" "XF")
9764 (set_attr "ppro_uops" "few")])
9766 (define_insn "*negextendsfxf2"
9767 [(set (match_operand:XF 0 "register_operand" "=f")
9768 (neg:XF (float_extend:XF
9769 (match_operand:SF 1 "register_operand" "0"))))]
9770 "!TARGET_64BIT && TARGET_80387"
9772 [(set_attr "type" "fsgn")
9773 (set_attr "mode" "XF")
9774 (set_attr "ppro_uops" "few")])
9776 (define_insn "*negtf2_1"
9777 [(set (match_operand:TF 0 "register_operand" "=f")
9778 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9779 "TARGET_80387 && reload_completed"
9781 [(set_attr "type" "fsgn")
9782 (set_attr "mode" "XF")
9783 (set_attr "ppro_uops" "few")])
9785 (define_insn "*negextenddftf2"
9786 [(set (match_operand:TF 0 "register_operand" "=f")
9787 (neg:TF (float_extend:TF
9788 (match_operand:DF 1 "register_operand" "0"))))]
9791 [(set_attr "type" "fsgn")
9792 (set_attr "mode" "XF")
9793 (set_attr "ppro_uops" "few")])
9795 (define_insn "*negextendsftf2"
9796 [(set (match_operand:TF 0 "register_operand" "=f")
9797 (neg:TF (float_extend:TF
9798 (match_operand:SF 1 "register_operand" "0"))))]
9801 [(set_attr "type" "fsgn")
9802 (set_attr "mode" "XF")
9803 (set_attr "ppro_uops" "few")])
9805 ;; Absolute value instructions
9807 (define_expand "abssf2"
9808 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9809 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9810 (clobber (reg:CC 17))])]
9814 /* In case operand is in memory, we will not use SSE. */
9815 if (memory_operand (operands[0], VOIDmode)
9816 && rtx_equal_p (operands[0], operands[1]))
9817 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9820 /* Using SSE is tricky, since we need bitwise negation of -0
9822 rtx reg = gen_reg_rtx (SFmode);
9823 rtx dest = operands[0];
9825 operands[1] = force_reg (SFmode, operands[1]);
9826 operands[0] = force_reg (SFmode, operands[0]);
9827 emit_move_insn (reg,
9828 gen_lowpart (SFmode,
9829 GEN_INT (trunc_int_for_mode (0x80000000,
9831 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9832 if (dest != operands[0])
9833 emit_move_insn (dest, operands[0]);
9837 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9839 (define_insn "abssf2_memory"
9840 [(set (match_operand:SF 0 "memory_operand" "=m")
9841 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9842 (clobber (reg:CC 17))]
9843 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9846 (define_insn "abssf2_ifs"
9847 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9848 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9849 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9850 (clobber (reg:CC 17))]
9852 && (reload_in_progress || reload_completed
9853 || (register_operand (operands[0], VOIDmode)
9854 && register_operand (operands[1], VOIDmode)))"
9858 [(set (match_operand:SF 0 "memory_operand" "")
9859 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9860 (use (match_operand:SF 2 "" ""))
9861 (clobber (reg:CC 17))]
9863 [(parallel [(set (match_dup 0)
9864 (abs:SF (match_dup 1)))
9865 (clobber (reg:CC 17))])])
9868 [(set (match_operand:SF 0 "register_operand" "")
9869 (abs:SF (match_operand:SF 1 "register_operand" "")))
9870 (use (match_operand:SF 2 "" ""))
9871 (clobber (reg:CC 17))]
9872 "reload_completed && !SSE_REG_P (operands[0])"
9873 [(parallel [(set (match_dup 0)
9874 (abs:SF (match_dup 1)))
9875 (clobber (reg:CC 17))])])
9878 [(set (match_operand:SF 0 "register_operand" "")
9879 (abs:SF (match_operand:SF 1 "register_operand" "")))
9880 (use (match_operand:SF 2 "register_operand" ""))
9881 (clobber (reg:CC 17))]
9882 "reload_completed && SSE_REG_P (operands[0])"
9883 [(set (subreg:TI (match_dup 0) 0)
9884 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9885 (subreg:TI (match_dup 1) 0)))])
9887 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9888 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9890 (define_insn "*abssf2_if"
9891 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9892 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9893 (clobber (reg:CC 17))]
9894 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9898 [(set (match_operand:SF 0 "register_operand" "")
9899 (abs:SF (match_operand:SF 1 "register_operand" "")))
9900 (clobber (reg:CC 17))]
9901 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9903 (abs:SF (match_dup 1)))]
9907 [(set (match_operand:SF 0 "register_operand" "")
9908 (abs:SF (match_operand:SF 1 "register_operand" "")))
9909 (clobber (reg:CC 17))]
9910 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9911 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9912 (clobber (reg:CC 17))])]
9913 "operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
9914 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9917 [(set (match_operand 0 "memory_operand" "")
9918 (abs (match_operand 1 "memory_operand" "")))
9919 (clobber (reg:CC 17))]
9920 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9921 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9922 (clobber (reg:CC 17))])]
9924 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9926 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9929 operands[0] = adjust_address (operands[0], QImode, size - 1);
9930 operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
9933 (define_expand "absdf2"
9934 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9935 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9936 (clobber (reg:CC 17))])]
9940 /* In case operand is in memory, we will not use SSE. */
9941 if (memory_operand (operands[0], VOIDmode)
9942 && rtx_equal_p (operands[0], operands[1]))
9943 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9946 /* Using SSE is tricky, since we need bitwise negation of -0
9948 rtx reg = gen_reg_rtx (DFmode);
9949 #if HOST_BITS_PER_WIDE_INT >= 64
9950 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9953 rtx imm = immed_double_const (0, 0x80000000, DImode);
9955 rtx dest = operands[0];
9957 operands[1] = force_reg (DFmode, operands[1]);
9958 operands[0] = force_reg (DFmode, operands[0]);
9959 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9960 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9961 if (dest != operands[0])
9962 emit_move_insn (dest, operands[0]);
9966 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9968 (define_insn "absdf2_memory"
9969 [(set (match_operand:DF 0 "memory_operand" "=m")
9970 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9971 (clobber (reg:CC 17))]
9972 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9975 (define_insn "absdf2_ifs"
9976 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
9977 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9978 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
9979 (clobber (reg:CC 17))]
9980 "!TARGET_64BIT && TARGET_SSE2
9981 && (reload_in_progress || reload_completed
9982 || (register_operand (operands[0], VOIDmode)
9983 && register_operand (operands[1], VOIDmode)))"
9986 (define_insn "*absdf2_ifs_rex64"
9987 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
9988 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
9989 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
9990 (clobber (reg:CC 17))]
9991 "TARGET_64BIT && TARGET_SSE2
9992 && (reload_in_progress || reload_completed
9993 || (register_operand (operands[0], VOIDmode)
9994 && register_operand (operands[1], VOIDmode)))"
9998 [(set (match_operand:DF 0 "memory_operand" "")
9999 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10000 (use (match_operand:DF 2 "" ""))
10001 (clobber (reg:CC 17))]
10003 [(parallel [(set (match_dup 0)
10004 (abs:DF (match_dup 1)))
10005 (clobber (reg:CC 17))])])
10008 [(set (match_operand:DF 0 "register_operand" "")
10009 (abs:DF (match_operand:DF 1 "register_operand" "")))
10010 (use (match_operand:DF 2 "" ""))
10011 (clobber (reg:CC 17))]
10012 "reload_completed && !SSE_REG_P (operands[0])"
10013 [(parallel [(set (match_dup 0)
10014 (abs:DF (match_dup 1)))
10015 (clobber (reg:CC 17))])])
10018 [(set (match_operand:DF 0 "register_operand" "")
10019 (abs:DF (match_operand:DF 1 "register_operand" "")))
10020 (use (match_operand:DF 2 "register_operand" ""))
10021 (clobber (reg:CC 17))]
10022 "reload_completed && SSE_REG_P (operands[0])"
10023 [(set (subreg:TI (match_dup 0) 0)
10024 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
10025 (subreg:TI (match_dup 1) 0)))])
10028 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10029 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10031 (define_insn "*absdf2_if"
10032 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10033 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10034 (clobber (reg:CC 17))]
10035 "!TARGET_64BIT && TARGET_80387
10036 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10039 ;; FIXME: We should to allow integer registers here. Problem is that
10040 ;; we need another scratch register to get constant from.
10041 ;; Forcing constant to mem if no register available in peep2 should be
10042 ;; safe even for PIC mode, because of RIP relative addressing.
10043 (define_insn "*absdf2_if_rex64"
10044 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10045 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10046 (clobber (reg:CC 17))]
10047 "TARGET_64BIT && TARGET_80387
10048 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10052 [(set (match_operand:DF 0 "register_operand" "")
10053 (abs:DF (match_operand:DF 1 "register_operand" "")))
10054 (clobber (reg:CC 17))]
10055 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10056 [(set (match_dup 0)
10057 (abs:DF (match_dup 1)))]
10061 [(set (match_operand:DF 0 "register_operand" "")
10062 (abs:DF (match_operand:DF 1 "register_operand" "")))
10063 (clobber (reg:CC 17))]
10064 "!TARGET_64BIT && TARGET_80387 && reload_completed &&
10065 !FP_REGNO_P (REGNO (operands[0]))"
10066 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10067 (clobber (reg:CC 17))])]
10068 "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
10069 split_di (operands+0, 1, operands+2, operands+3);")
10071 (define_expand "absxf2"
10072 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10073 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10074 (clobber (reg:CC 17))])]
10075 "!TARGET_64BIT && TARGET_80387"
10076 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10078 (define_expand "abstf2"
10079 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10080 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10081 (clobber (reg:CC 17))])]
10083 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10085 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10086 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10088 (define_insn "*absxf2_if"
10089 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10090 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10091 (clobber (reg:CC 17))]
10092 "!TARGET_64BIT && TARGET_80387
10093 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10097 [(set (match_operand:XF 0 "register_operand" "")
10098 (abs:XF (match_operand:XF 1 "register_operand" "")))
10099 (clobber (reg:CC 17))]
10100 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10101 [(set (match_dup 0)
10102 (abs:XF (match_dup 1)))]
10106 [(set (match_operand:XF 0 "register_operand" "")
10107 (abs:XF (match_operand:XF 1 "register_operand" "")))
10108 (clobber (reg:CC 17))]
10109 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10110 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10111 (clobber (reg:CC 17))])]
10112 "operands[1] = GEN_INT (~0x8000);
10113 operands[0] = gen_rtx_REG (SImode,
10114 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10116 (define_insn "*abstf2_if"
10117 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10118 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10119 (clobber (reg:CC 17))]
10120 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10124 [(set (match_operand:TF 0 "register_operand" "")
10125 (abs:TF (match_operand:TF 1 "register_operand" "")))
10126 (clobber (reg:CC 17))]
10127 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10128 [(set (match_dup 0)
10129 (abs:TF (match_dup 1)))]
10133 [(set (match_operand:TF 0 "register_operand" "")
10134 (abs:TF (match_operand:TF 1 "register_operand" "")))
10135 (clobber (reg:CC 17))]
10136 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10137 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10138 (clobber (reg:CC 17))])]
10139 "operands[1] = GEN_INT (~0x8000);
10140 operands[0] = gen_rtx_REG (SImode,
10141 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10143 (define_insn "*abssf2_1"
10144 [(set (match_operand:SF 0 "register_operand" "=f")
10145 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10146 "TARGET_80387 && reload_completed"
10148 [(set_attr "type" "fsgn")
10149 (set_attr "mode" "SF")])
10151 (define_insn "*absdf2_1"
10152 [(set (match_operand:DF 0 "register_operand" "=f")
10153 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10154 "TARGET_80387 && reload_completed"
10156 [(set_attr "type" "fsgn")
10157 (set_attr "mode" "DF")])
10159 (define_insn "*absextendsfdf2"
10160 [(set (match_operand:DF 0 "register_operand" "=f")
10161 (abs:DF (float_extend:DF
10162 (match_operand:SF 1 "register_operand" "0"))))]
10165 [(set_attr "type" "fsgn")
10166 (set_attr "mode" "DF")])
10168 (define_insn "*absxf2_1"
10169 [(set (match_operand:XF 0 "register_operand" "=f")
10170 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10171 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10173 [(set_attr "type" "fsgn")
10174 (set_attr "mode" "DF")])
10176 (define_insn "*absextenddfxf2"
10177 [(set (match_operand:XF 0 "register_operand" "=f")
10178 (abs:XF (float_extend:XF
10179 (match_operand:DF 1 "register_operand" "0"))))]
10180 "!TARGET_64BIT && TARGET_80387"
10182 [(set_attr "type" "fsgn")
10183 (set_attr "mode" "XF")])
10185 (define_insn "*absextendsfxf2"
10186 [(set (match_operand:XF 0 "register_operand" "=f")
10187 (abs:XF (float_extend:XF
10188 (match_operand:SF 1 "register_operand" "0"))))]
10189 "!TARGET_64BIT && TARGET_80387"
10191 [(set_attr "type" "fsgn")
10192 (set_attr "mode" "XF")])
10194 (define_insn "*abstf2_1"
10195 [(set (match_operand:TF 0 "register_operand" "=f")
10196 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10197 "TARGET_80387 && reload_completed"
10199 [(set_attr "type" "fsgn")
10200 (set_attr "mode" "DF")])
10202 (define_insn "*absextenddftf2"
10203 [(set (match_operand:TF 0 "register_operand" "=f")
10204 (abs:TF (float_extend:TF
10205 (match_operand:DF 1 "register_operand" "0"))))]
10208 [(set_attr "type" "fsgn")
10209 (set_attr "mode" "XF")])
10211 (define_insn "*absextendsftf2"
10212 [(set (match_operand:TF 0 "register_operand" "=f")
10213 (abs:TF (float_extend:TF
10214 (match_operand:SF 1 "register_operand" "0"))))]
10217 [(set_attr "type" "fsgn")
10218 (set_attr "mode" "XF")])
10220 ;; One complement instructions
10222 (define_expand "one_cmpldi2"
10223 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10224 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10226 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10228 (define_insn "*one_cmpldi2_1_rex64"
10229 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10230 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10231 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10233 [(set_attr "type" "negnot")
10234 (set_attr "mode" "DI")])
10236 (define_insn "*one_cmpldi2_2_rex64"
10238 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10240 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10241 (not:DI (match_dup 1)))]
10242 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10243 && ix86_unary_operator_ok (NOT, DImode, operands)"
10245 [(set_attr "type" "alu1")
10246 (set_attr "mode" "DI")])
10250 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10252 (set (match_operand:DI 0 "nonimmediate_operand" "")
10253 (not:DI (match_dup 1)))]
10254 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10255 [(parallel [(set (reg:CCNO 17)
10256 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10259 (xor:DI (match_dup 1) (const_int -1)))])]
10262 (define_expand "one_cmplsi2"
10263 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10264 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10266 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10268 (define_insn "*one_cmplsi2_1"
10269 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10270 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10271 "ix86_unary_operator_ok (NOT, SImode, operands)"
10273 [(set_attr "type" "negnot")
10274 (set_attr "mode" "SI")])
10276 ;; ??? Currently never generated - xor is used instead.
10277 (define_insn "*one_cmplsi2_1_zext"
10278 [(set (match_operand:DI 0 "register_operand" "=r")
10279 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10280 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10282 [(set_attr "type" "negnot")
10283 (set_attr "mode" "SI")])
10285 (define_insn "*one_cmplsi2_2"
10287 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10289 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10290 (not:SI (match_dup 1)))]
10291 "ix86_match_ccmode (insn, CCNOmode)
10292 && ix86_unary_operator_ok (NOT, SImode, operands)"
10294 [(set_attr "type" "alu1")
10295 (set_attr "mode" "SI")])
10299 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10301 (set (match_operand:SI 0 "nonimmediate_operand" "")
10302 (not:SI (match_dup 1)))]
10303 "ix86_match_ccmode (insn, CCNOmode)"
10304 [(parallel [(set (reg:CCNO 17)
10305 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10308 (xor:SI (match_dup 1) (const_int -1)))])]
10311 ;; ??? Currently never generated - xor is used instead.
10312 (define_insn "*one_cmplsi2_2_zext"
10314 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10316 (set (match_operand:DI 0 "register_operand" "=r")
10317 (zero_extend:DI (not:SI (match_dup 1))))]
10318 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10319 && ix86_unary_operator_ok (NOT, SImode, operands)"
10321 [(set_attr "type" "alu1")
10322 (set_attr "mode" "SI")])
10326 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10328 (set (match_operand:DI 0 "register_operand" "")
10329 (zero_extend:DI (not:SI (match_dup 1))))]
10330 "ix86_match_ccmode (insn, CCNOmode)"
10331 [(parallel [(set (reg:CCNO 17)
10332 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10335 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10338 (define_expand "one_cmplhi2"
10339 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10340 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10341 "TARGET_HIMODE_MATH"
10342 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10344 (define_insn "*one_cmplhi2_1"
10345 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10346 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10347 "ix86_unary_operator_ok (NOT, HImode, operands)"
10349 [(set_attr "type" "negnot")
10350 (set_attr "mode" "HI")])
10352 (define_insn "*one_cmplhi2_2"
10354 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10356 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10357 (not:HI (match_dup 1)))]
10358 "ix86_match_ccmode (insn, CCNOmode)
10359 && ix86_unary_operator_ok (NEG, HImode, operands)"
10361 [(set_attr "type" "alu1")
10362 (set_attr "mode" "HI")])
10366 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10368 (set (match_operand:HI 0 "nonimmediate_operand" "")
10369 (not:HI (match_dup 1)))]
10370 "ix86_match_ccmode (insn, CCNOmode)"
10371 [(parallel [(set (reg:CCNO 17)
10372 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10375 (xor:HI (match_dup 1) (const_int -1)))])]
10378 ;; %%% Potential partial reg stall on alternative 1. What to do?
10379 (define_expand "one_cmplqi2"
10380 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10381 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10382 "TARGET_QIMODE_MATH"
10383 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10385 (define_insn "*one_cmplqi2_1"
10386 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10387 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10388 "ix86_unary_operator_ok (NOT, QImode, operands)"
10392 [(set_attr "type" "negnot")
10393 (set_attr "mode" "QI,SI")])
10395 (define_insn "*one_cmplqi2_2"
10397 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10399 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10400 (not:QI (match_dup 1)))]
10401 "ix86_match_ccmode (insn, CCNOmode)
10402 && ix86_unary_operator_ok (NOT, QImode, operands)"
10404 [(set_attr "type" "alu1")
10405 (set_attr "mode" "QI")])
10409 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10411 (set (match_operand:QI 0 "nonimmediate_operand" "")
10412 (not:QI (match_dup 1)))]
10413 "ix86_match_ccmode (insn, CCNOmode)"
10414 [(parallel [(set (reg:CCNO 17)
10415 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10418 (xor:QI (match_dup 1) (const_int -1)))])]
10421 ;; Arithmetic shift instructions
10423 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10424 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10425 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10426 ;; from the assembler input.
10428 ;; This instruction shifts the target reg/mem as usual, but instead of
10429 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10430 ;; is a left shift double, bits are taken from the high order bits of
10431 ;; reg, else if the insn is a shift right double, bits are taken from the
10432 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10433 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10435 ;; Since sh[lr]d does not change the `reg' operand, that is done
10436 ;; separately, making all shifts emit pairs of shift double and normal
10437 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10438 ;; support a 63 bit shift, each shift where the count is in a reg expands
10439 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10441 ;; If the shift count is a constant, we need never emit more than one
10442 ;; shift pair, instead using moves and sign extension for counts greater
10445 (define_expand "ashldi3"
10446 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10447 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10448 (match_operand:QI 2 "nonmemory_operand" "")))
10449 (clobber (reg:CC 17))])]
10452 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10454 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10457 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10461 (define_insn "*ashldi3_1_rex64"
10462 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10463 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10464 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10465 (clobber (reg:CC 17))]
10466 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10468 switch (get_attr_type (insn))
10471 if (operands[2] != const1_rtx)
10473 if (!rtx_equal_p (operands[0], operands[1]))
10475 return "add{q}\t{%0, %0|%0, %0}";
10478 if (GET_CODE (operands[2]) != CONST_INT
10479 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10481 operands[1] = gen_rtx_MULT (DImode, operands[1],
10482 GEN_INT (1 << INTVAL (operands[2])));
10483 return "lea{q}\t{%a1, %0|%0, %a1}";
10486 if (REG_P (operands[2]))
10487 return "sal{q}\t{%b2, %0|%0, %b2}";
10488 else if (GET_CODE (operands[2]) == CONST_INT
10489 && INTVAL (operands[2]) == 1
10490 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10491 return "sal{q}\t%0";
10493 return "sal{q}\t{%2, %0|%0, %2}";
10496 [(set (attr "type")
10497 (cond [(eq_attr "alternative" "1")
10498 (const_string "lea")
10499 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10501 (match_operand 0 "register_operand" ""))
10502 (match_operand 2 "const1_operand" ""))
10503 (const_string "alu")
10505 (const_string "ishift")))
10506 (set_attr "mode" "DI")])
10508 ;; Convert lea to the lea pattern to avoid flags dependency.
10510 [(set (match_operand:DI 0 "register_operand" "")
10511 (ashift:DI (match_operand:DI 1 "register_operand" "")
10512 (match_operand:QI 2 "immediate_operand" "")))
10513 (clobber (reg:CC 17))]
10514 "TARGET_64BIT && reload_completed
10515 && true_regnum (operands[0]) != true_regnum (operands[1])"
10516 [(set (match_dup 0)
10517 (mult:DI (match_dup 1)
10519 "operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10522 ;; This pattern can't accept a variable shift count, since shifts by
10523 ;; zero don't affect the flags. We assume that shifts by constant
10524 ;; zero are optimized away.
10525 (define_insn "*ashldi3_cmp_rex64"
10528 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10529 (match_operand:QI 2 "immediate_operand" "e"))
10531 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10532 (ashift:DI (match_dup 1) (match_dup 2)))]
10533 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10534 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10536 switch (get_attr_type (insn))
10539 if (operands[2] != const1_rtx)
10541 return "add{q}\t{%0, %0|%0, %0}";
10544 if (REG_P (operands[2]))
10545 return "sal{q}\t{%b2, %0|%0, %b2}";
10546 else if (GET_CODE (operands[2]) == CONST_INT
10547 && INTVAL (operands[2]) == 1
10548 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10549 return "sal{q}\t%0";
10551 return "sal{q}\t{%2, %0|%0, %2}";
10554 [(set (attr "type")
10555 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10557 (match_operand 0 "register_operand" ""))
10558 (match_operand 2 "const1_operand" ""))
10559 (const_string "alu")
10561 (const_string "ishift")))
10562 (set_attr "mode" "DI")])
10564 (define_insn "ashldi3_1"
10565 [(set (match_operand:DI 0 "register_operand" "=r")
10566 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10567 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10568 (clobber (match_scratch:SI 3 "=&r"))
10569 (clobber (reg:CC 17))]
10570 "!TARGET_64BIT && TARGET_CMOVE"
10572 [(set_attr "type" "multi")])
10574 (define_insn "*ashldi3_2"
10575 [(set (match_operand:DI 0 "register_operand" "=r")
10576 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10577 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10578 (clobber (reg:CC 17))]
10581 [(set_attr "type" "multi")])
10584 [(set (match_operand:DI 0 "register_operand" "")
10585 (ashift:DI (match_operand:DI 1 "register_operand" "")
10586 (match_operand:QI 2 "nonmemory_operand" "")))
10587 (clobber (match_scratch:SI 3 ""))
10588 (clobber (reg:CC 17))]
10589 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10591 "ix86_split_ashldi (operands, operands[3]); DONE;")
10594 [(set (match_operand:DI 0 "register_operand" "")
10595 (ashift:DI (match_operand:DI 1 "register_operand" "")
10596 (match_operand:QI 2 "nonmemory_operand" "")))
10597 (clobber (reg:CC 17))]
10598 "!TARGET_64BIT && reload_completed"
10600 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10602 (define_insn "x86_shld_1"
10603 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10604 (ior:SI (ashift:SI (match_dup 0)
10605 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10606 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10607 (minus:QI (const_int 32) (match_dup 2)))))
10608 (clobber (reg:CC 17))]
10611 shld{l}\t{%2, %1, %0|%0, %1, %2}
10612 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10613 [(set_attr "type" "ishift")
10614 (set_attr "prefix_0f" "1")
10615 (set_attr "mode" "SI")
10616 (set_attr "pent_pair" "np")
10617 (set_attr "athlon_decode" "vector")
10618 (set_attr "ppro_uops" "few")])
10620 (define_expand "x86_shift_adj_1"
10622 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10625 (set (match_operand:SI 0 "register_operand" "")
10626 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10627 (match_operand:SI 1 "register_operand" "")
10630 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10631 (match_operand:SI 3 "register_operand" "r")
10636 (define_expand "x86_shift_adj_2"
10637 [(use (match_operand:SI 0 "register_operand" ""))
10638 (use (match_operand:SI 1 "register_operand" ""))
10639 (use (match_operand:QI 2 "register_operand" ""))]
10642 rtx label = gen_label_rtx ();
10645 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10647 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10648 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10649 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10650 gen_rtx_LABEL_REF (VOIDmode, label),
10652 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10653 JUMP_LABEL (tmp) = label;
10655 emit_move_insn (operands[0], operands[1]);
10656 emit_move_insn (operands[1], const0_rtx);
10658 emit_label (label);
10659 LABEL_NUSES (label) = 1;
10664 (define_expand "ashlsi3"
10665 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10666 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10667 (match_operand:QI 2 "nonmemory_operand" "")))
10668 (clobber (reg:CC 17))]
10670 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10672 (define_insn "*ashlsi3_1"
10673 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10674 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10675 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10676 (clobber (reg:CC 17))]
10677 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10679 switch (get_attr_type (insn))
10682 if (operands[2] != const1_rtx)
10684 if (!rtx_equal_p (operands[0], operands[1]))
10686 return "add{l}\t{%0, %0|%0, %0}";
10692 if (REG_P (operands[2]))
10693 return "sal{l}\t{%b2, %0|%0, %b2}";
10694 else if (GET_CODE (operands[2]) == CONST_INT
10695 && INTVAL (operands[2]) == 1
10696 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10697 return "sal{l}\t%0";
10699 return "sal{l}\t{%2, %0|%0, %2}";
10702 [(set (attr "type")
10703 (cond [(eq_attr "alternative" "1")
10704 (const_string "lea")
10705 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10707 (match_operand 0 "register_operand" ""))
10708 (match_operand 2 "const1_operand" ""))
10709 (const_string "alu")
10711 (const_string "ishift")))
10712 (set_attr "mode" "SI")])
10714 ;; Convert lea to the lea pattern to avoid flags dependency.
10716 [(set (match_operand 0 "register_operand" "")
10717 (ashift (match_operand 1 "register_operand" "")
10718 (match_operand:QI 2 "const_int_operand" "")))
10719 (clobber (reg:CC 17))]
10721 && true_regnum (operands[0]) != true_regnum (operands[1])"
10725 operands[0] = gen_lowpart (SImode, operands[0]);
10726 operands[1] = gen_lowpart (Pmode, operands[1]);
10727 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10729 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10730 if (Pmode != SImode)
10731 pat = gen_rtx_SUBREG (SImode, pat, 0);
10732 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10736 (define_insn "*ashlsi3_1_zext"
10737 [(set (match_operand:DI 0 "register_operand" "=r,r")
10738 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10739 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10740 (clobber (reg:CC 17))]
10741 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10743 switch (get_attr_type (insn))
10746 if (operands[2] != const1_rtx)
10748 return "add{l}\t{%k0, %k0|%k0, %k0}";
10754 if (REG_P (operands[2]))
10755 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10756 else if (GET_CODE (operands[2]) == CONST_INT
10757 && INTVAL (operands[2]) == 1
10758 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10759 return "sal{l}\t%k0";
10761 return "sal{l}\t{%2, %k0|%k0, %2}";
10764 [(set (attr "type")
10765 (cond [(eq_attr "alternative" "1")
10766 (const_string "lea")
10767 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10769 (match_operand 2 "const1_operand" ""))
10770 (const_string "alu")
10772 (const_string "ishift")))
10773 (set_attr "mode" "SI")])
10775 ;; Convert lea to the lea pattern to avoid flags dependency.
10777 [(set (match_operand:DI 0 "register_operand" "")
10778 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10779 (match_operand:QI 2 "const_int_operand" ""))))
10780 (clobber (reg:CC 17))]
10782 && true_regnum (operands[0]) != true_regnum (operands[1])"
10783 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10785 operands[1] = gen_lowpart (Pmode, operands[1]);
10786 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10790 ;; This pattern can't accept a variable shift count, since shifts by
10791 ;; zero don't affect the flags. We assume that shifts by constant
10792 ;; zero are optimized away.
10793 (define_insn "*ashlsi3_cmp"
10796 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10797 (match_operand:QI 2 "immediate_operand" "I"))
10799 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10800 (ashift:SI (match_dup 1) (match_dup 2)))]
10801 "ix86_match_ccmode (insn, CCGOCmode)
10802 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10804 switch (get_attr_type (insn))
10807 if (operands[2] != const1_rtx)
10809 return "add{l}\t{%0, %0|%0, %0}";
10812 if (REG_P (operands[2]))
10813 return "sal{l}\t{%b2, %0|%0, %b2}";
10814 else if (GET_CODE (operands[2]) == CONST_INT
10815 && INTVAL (operands[2]) == 1
10816 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10817 return "sal{l}\t%0";
10819 return "sal{l}\t{%2, %0|%0, %2}";
10822 [(set (attr "type")
10823 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10825 (match_operand 0 "register_operand" ""))
10826 (match_operand 2 "const1_operand" ""))
10827 (const_string "alu")
10829 (const_string "ishift")))
10830 (set_attr "mode" "SI")])
10832 (define_insn "*ashlsi3_cmp_zext"
10835 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10836 (match_operand:QI 2 "immediate_operand" "I"))
10838 (set (match_operand:DI 0 "register_operand" "=r")
10839 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10840 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10841 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10843 switch (get_attr_type (insn))
10846 if (operands[2] != const1_rtx)
10848 return "add{l}\t{%k0, %k0|%k0, %k0}";
10851 if (REG_P (operands[2]))
10852 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10853 else if (GET_CODE (operands[2]) == CONST_INT
10854 && INTVAL (operands[2]) == 1
10855 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10856 return "sal{l}\t%k0";
10858 return "sal{l}\t{%2, %k0|%k0, %2}";
10861 [(set (attr "type")
10862 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10864 (match_operand 2 "const1_operand" ""))
10865 (const_string "alu")
10867 (const_string "ishift")))
10868 (set_attr "mode" "SI")])
10870 (define_expand "ashlhi3"
10871 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10872 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10873 (match_operand:QI 2 "nonmemory_operand" "")))
10874 (clobber (reg:CC 17))]
10875 "TARGET_HIMODE_MATH"
10876 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10878 (define_insn "*ashlhi3_1_lea"
10879 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10880 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10881 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10882 (clobber (reg:CC 17))]
10883 "!TARGET_PARTIAL_REG_STALL
10884 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10886 switch (get_attr_type (insn))
10891 if (operands[2] != const1_rtx)
10893 return "add{w}\t{%0, %0|%0, %0}";
10896 if (REG_P (operands[2]))
10897 return "sal{w}\t{%b2, %0|%0, %b2}";
10898 else if (GET_CODE (operands[2]) == CONST_INT
10899 && INTVAL (operands[2]) == 1
10900 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10901 return "sal{w}\t%0";
10903 return "sal{w}\t{%2, %0|%0, %2}";
10906 [(set (attr "type")
10907 (cond [(eq_attr "alternative" "1")
10908 (const_string "lea")
10909 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10911 (match_operand 0 "register_operand" ""))
10912 (match_operand 2 "const1_operand" ""))
10913 (const_string "alu")
10915 (const_string "ishift")))
10916 (set_attr "mode" "HI,SI")])
10918 (define_insn "*ashlhi3_1"
10919 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10920 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10921 (match_operand:QI 2 "nonmemory_operand" "cI")))
10922 (clobber (reg:CC 17))]
10923 "TARGET_PARTIAL_REG_STALL
10924 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10926 switch (get_attr_type (insn))
10929 if (operands[2] != const1_rtx)
10931 return "add{w}\t{%0, %0|%0, %0}";
10934 if (REG_P (operands[2]))
10935 return "sal{w}\t{%b2, %0|%0, %b2}";
10936 else if (GET_CODE (operands[2]) == CONST_INT
10937 && INTVAL (operands[2]) == 1
10938 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10939 return "sal{w}\t%0";
10941 return "sal{w}\t{%2, %0|%0, %2}";
10944 [(set (attr "type")
10945 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10947 (match_operand 0 "register_operand" ""))
10948 (match_operand 2 "const1_operand" ""))
10949 (const_string "alu")
10951 (const_string "ishift")))
10952 (set_attr "mode" "HI")])
10954 ;; This pattern can't accept a variable shift count, since shifts by
10955 ;; zero don't affect the flags. We assume that shifts by constant
10956 ;; zero are optimized away.
10957 (define_insn "*ashlhi3_cmp"
10960 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10961 (match_operand:QI 2 "immediate_operand" "I"))
10963 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10964 (ashift:HI (match_dup 1) (match_dup 2)))]
10965 "ix86_match_ccmode (insn, CCGOCmode)
10966 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10968 switch (get_attr_type (insn))
10971 if (operands[2] != const1_rtx)
10973 return "add{w}\t{%0, %0|%0, %0}";
10976 if (REG_P (operands[2]))
10977 return "sal{w}\t{%b2, %0|%0, %b2}";
10978 else if (GET_CODE (operands[2]) == CONST_INT
10979 && INTVAL (operands[2]) == 1
10980 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10981 return "sal{w}\t%0";
10983 return "sal{w}\t{%2, %0|%0, %2}";
10986 [(set (attr "type")
10987 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10989 (match_operand 0 "register_operand" ""))
10990 (match_operand 2 "const1_operand" ""))
10991 (const_string "alu")
10993 (const_string "ishift")))
10994 (set_attr "mode" "HI")])
10996 (define_expand "ashlqi3"
10997 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10998 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10999 (match_operand:QI 2 "nonmemory_operand" "")))
11000 (clobber (reg:CC 17))]
11001 "TARGET_QIMODE_MATH"
11002 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11004 ;; %%% Potential partial reg stall on alternative 2. What to do?
11006 (define_insn "*ashlqi3_1_lea"
11007 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11008 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11009 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11010 (clobber (reg:CC 17))]
11011 "!TARGET_PARTIAL_REG_STALL
11012 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11014 switch (get_attr_type (insn))
11019 if (operands[2] != const1_rtx)
11021 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11022 return "add{l}\t{%k0, %k0|%k0, %k0}";
11024 return "add{b}\t{%0, %0|%0, %0}";
11027 if (REG_P (operands[2]))
11029 if (get_attr_mode (insn) == MODE_SI)
11030 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11032 return "sal{b}\t{%b2, %0|%0, %b2}";
11034 else if (GET_CODE (operands[2]) == CONST_INT
11035 && INTVAL (operands[2]) == 1
11036 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11038 if (get_attr_mode (insn) == MODE_SI)
11039 return "sal{l}\t%0";
11041 return "sal{b}\t%0";
11045 if (get_attr_mode (insn) == MODE_SI)
11046 return "sal{l}\t{%2, %k0|%k0, %2}";
11048 return "sal{b}\t{%2, %0|%0, %2}";
11052 [(set (attr "type")
11053 (cond [(eq_attr "alternative" "2")
11054 (const_string "lea")
11055 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11057 (match_operand 0 "register_operand" ""))
11058 (match_operand 2 "const1_operand" ""))
11059 (const_string "alu")
11061 (const_string "ishift")))
11062 (set_attr "mode" "QI,SI,SI")])
11064 (define_insn "*ashlqi3_1"
11065 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11066 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11067 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11068 (clobber (reg:CC 17))]
11069 "TARGET_PARTIAL_REG_STALL
11070 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11072 switch (get_attr_type (insn))
11075 if (operands[2] != const1_rtx)
11077 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11078 return "add{l}\t{%k0, %k0|%k0, %k0}";
11080 return "add{b}\t{%0, %0|%0, %0}";
11083 if (REG_P (operands[2]))
11085 if (get_attr_mode (insn) == MODE_SI)
11086 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11088 return "sal{b}\t{%b2, %0|%0, %b2}";
11090 else if (GET_CODE (operands[2]) == CONST_INT
11091 && INTVAL (operands[2]) == 1
11092 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11094 if (get_attr_mode (insn) == MODE_SI)
11095 return "sal{l}\t%0";
11097 return "sal{b}\t%0";
11101 if (get_attr_mode (insn) == MODE_SI)
11102 return "sal{l}\t{%2, %k0|%k0, %2}";
11104 return "sal{b}\t{%2, %0|%0, %2}";
11108 [(set (attr "type")
11109 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11111 (match_operand 0 "register_operand" ""))
11112 (match_operand 2 "const1_operand" ""))
11113 (const_string "alu")
11115 (const_string "ishift")))
11116 (set_attr "mode" "QI,SI")])
11118 ;; This pattern can't accept a variable shift count, since shifts by
11119 ;; zero don't affect the flags. We assume that shifts by constant
11120 ;; zero are optimized away.
11121 (define_insn "*ashlqi3_cmp"
11124 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11125 (match_operand:QI 2 "immediate_operand" "I"))
11127 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11128 (ashift:QI (match_dup 1) (match_dup 2)))]
11129 "ix86_match_ccmode (insn, CCGOCmode)
11130 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11132 switch (get_attr_type (insn))
11135 if (operands[2] != const1_rtx)
11137 return "add{b}\t{%0, %0|%0, %0}";
11140 if (REG_P (operands[2]))
11141 return "sal{b}\t{%b2, %0|%0, %b2}";
11142 else if (GET_CODE (operands[2]) == CONST_INT
11143 && INTVAL (operands[2]) == 1
11144 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11145 return "sal{b}\t%0";
11147 return "sal{b}\t{%2, %0|%0, %2}";
11150 [(set (attr "type")
11151 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11153 (match_operand 0 "register_operand" ""))
11154 (match_operand 2 "const1_operand" ""))
11155 (const_string "alu")
11157 (const_string "ishift")))
11158 (set_attr "mode" "QI")])
11160 ;; See comment above `ashldi3' about how this works.
11162 (define_expand "ashrdi3"
11163 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11164 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11165 (match_operand:QI 2 "nonmemory_operand" "")))
11166 (clobber (reg:CC 17))])]
11169 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11171 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11174 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11178 (define_insn "ashrdi3_63_rex64"
11179 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11180 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11181 (match_operand:DI 2 "const_int_operand" "i,i")))
11182 (clobber (reg:CC 17))]
11183 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11184 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11187 sar{q}\t{%2, %0|%0, %2}"
11188 [(set_attr "type" "imovx,ishift")
11189 (set_attr "prefix_0f" "0,*")
11190 (set_attr "length_immediate" "0,*")
11191 (set_attr "modrm" "0,1")
11192 (set_attr "mode" "DI")])
11194 (define_insn "*ashrdi3_1_one_bit_rex64"
11195 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11196 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11197 (match_operand:QI 2 "const_int_1_operand" "")))
11198 (clobber (reg:CC 17))]
11199 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11200 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11202 [(set_attr "type" "ishift")
11203 (set (attr "length")
11204 (if_then_else (match_operand:DI 0 "register_operand" "")
11206 (const_string "*")))])
11208 (define_insn "*ashrdi3_1_rex64"
11209 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11210 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11211 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11212 (clobber (reg:CC 17))]
11213 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11215 sar{q}\t{%2, %0|%0, %2}
11216 sar{q}\t{%b2, %0|%0, %b2}"
11217 [(set_attr "type" "ishift")
11218 (set_attr "mode" "DI")])
11220 ;; This pattern can't accept a variable shift count, since shifts by
11221 ;; zero don't affect the flags. We assume that shifts by constant
11222 ;; zero are optimized away.
11223 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11226 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11227 (match_operand:QI 2 "const_int_1_operand" ""))
11229 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11230 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11231 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11232 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11233 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11235 [(set_attr "type" "ishift")
11236 (set (attr "length")
11237 (if_then_else (match_operand:DI 0 "register_operand" "")
11239 (const_string "*")))])
11241 ;; This pattern can't accept a variable shift count, since shifts by
11242 ;; zero don't affect the flags. We assume that shifts by constant
11243 ;; zero are optimized away.
11244 (define_insn "*ashrdi3_cmp_rex64"
11247 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11248 (match_operand:QI 2 "const_int_operand" "n"))
11250 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11251 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11252 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11253 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11254 "sar{q}\t{%2, %0|%0, %2}"
11255 [(set_attr "type" "ishift")
11256 (set_attr "mode" "DI")])
11259 (define_insn "ashrdi3_1"
11260 [(set (match_operand:DI 0 "register_operand" "=r")
11261 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11262 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11263 (clobber (match_scratch:SI 3 "=&r"))
11264 (clobber (reg:CC 17))]
11265 "!TARGET_64BIT && TARGET_CMOVE"
11267 [(set_attr "type" "multi")])
11269 (define_insn "*ashrdi3_2"
11270 [(set (match_operand:DI 0 "register_operand" "=r")
11271 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11272 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11273 (clobber (reg:CC 17))]
11276 [(set_attr "type" "multi")])
11279 [(set (match_operand:DI 0 "register_operand" "")
11280 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11281 (match_operand:QI 2 "nonmemory_operand" "")))
11282 (clobber (match_scratch:SI 3 ""))
11283 (clobber (reg:CC 17))]
11284 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11286 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11289 [(set (match_operand:DI 0 "register_operand" "")
11290 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11291 (match_operand:QI 2 "nonmemory_operand" "")))
11292 (clobber (reg:CC 17))]
11293 "!TARGET_64BIT && reload_completed"
11295 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11297 (define_insn "x86_shrd_1"
11298 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11299 (ior:SI (ashiftrt:SI (match_dup 0)
11300 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11301 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11302 (minus:QI (const_int 32) (match_dup 2)))))
11303 (clobber (reg:CC 17))]
11306 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11307 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11308 [(set_attr "type" "ishift")
11309 (set_attr "prefix_0f" "1")
11310 (set_attr "pent_pair" "np")
11311 (set_attr "ppro_uops" "few")
11312 (set_attr "mode" "SI")])
11314 (define_expand "x86_shift_adj_3"
11315 [(use (match_operand:SI 0 "register_operand" ""))
11316 (use (match_operand:SI 1 "register_operand" ""))
11317 (use (match_operand:QI 2 "register_operand" ""))]
11320 rtx label = gen_label_rtx ();
11323 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11325 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11326 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11327 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11328 gen_rtx_LABEL_REF (VOIDmode, label),
11330 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11331 JUMP_LABEL (tmp) = label;
11333 emit_move_insn (operands[0], operands[1]);
11334 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11336 emit_label (label);
11337 LABEL_NUSES (label) = 1;
11342 (define_insn "ashrsi3_31"
11343 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11344 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11345 (match_operand:SI 2 "const_int_operand" "i,i")))
11346 (clobber (reg:CC 17))]
11347 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11348 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11351 sar{l}\t{%2, %0|%0, %2}"
11352 [(set_attr "type" "imovx,ishift")
11353 (set_attr "prefix_0f" "0,*")
11354 (set_attr "length_immediate" "0,*")
11355 (set_attr "modrm" "0,1")
11356 (set_attr "mode" "SI")])
11358 (define_insn "*ashrsi3_31_zext"
11359 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11360 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11361 (match_operand:SI 2 "const_int_operand" "i,i"))))
11362 (clobber (reg:CC 17))]
11363 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11364 && INTVAL (operands[2]) == 31
11365 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11368 sar{l}\t{%2, %k0|%k0, %2}"
11369 [(set_attr "type" "imovx,ishift")
11370 (set_attr "prefix_0f" "0,*")
11371 (set_attr "length_immediate" "0,*")
11372 (set_attr "modrm" "0,1")
11373 (set_attr "mode" "SI")])
11375 (define_expand "ashrsi3"
11376 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11377 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11378 (match_operand:QI 2 "nonmemory_operand" "")))
11379 (clobber (reg:CC 17))]
11381 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11383 (define_insn "*ashrsi3_1_one_bit"
11384 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11385 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11386 (match_operand:QI 2 "const_int_1_operand" "")))
11387 (clobber (reg:CC 17))]
11388 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11389 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11391 [(set_attr "type" "ishift")
11392 (set (attr "length")
11393 (if_then_else (match_operand:SI 0 "register_operand" "")
11395 (const_string "*")))])
11397 (define_insn "*ashrsi3_1_one_bit_zext"
11398 [(set (match_operand:DI 0 "register_operand" "=r")
11399 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11400 (match_operand:QI 2 "const_int_1_operand" ""))))
11401 (clobber (reg:CC 17))]
11402 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11403 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11405 [(set_attr "type" "ishift")
11406 (set_attr "length" "2")])
11408 (define_insn "*ashrsi3_1"
11409 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11410 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11411 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11412 (clobber (reg:CC 17))]
11413 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11415 sar{l}\t{%2, %0|%0, %2}
11416 sar{l}\t{%b2, %0|%0, %b2}"
11417 [(set_attr "type" "ishift")
11418 (set_attr "mode" "SI")])
11420 (define_insn "*ashrsi3_1_zext"
11421 [(set (match_operand:DI 0 "register_operand" "=r,r")
11422 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11423 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11424 (clobber (reg:CC 17))]
11425 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11427 sar{l}\t{%2, %k0|%k0, %2}
11428 sar{l}\t{%b2, %k0|%k0, %b2}"
11429 [(set_attr "type" "ishift")
11430 (set_attr "mode" "SI")])
11432 ;; This pattern can't accept a variable shift count, since shifts by
11433 ;; zero don't affect the flags. We assume that shifts by constant
11434 ;; zero are optimized away.
11435 (define_insn "*ashrsi3_one_bit_cmp"
11438 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11439 (match_operand:QI 2 "const_int_1_operand" ""))
11441 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11442 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11443 "ix86_match_ccmode (insn, CCGOCmode)
11444 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11445 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11447 [(set_attr "type" "ishift")
11448 (set (attr "length")
11449 (if_then_else (match_operand:SI 0 "register_operand" "")
11451 (const_string "*")))])
11453 (define_insn "*ashrsi3_one_bit_cmp_zext"
11456 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11457 (match_operand:QI 2 "const_int_1_operand" ""))
11459 (set (match_operand:DI 0 "register_operand" "=r")
11460 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11461 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11462 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11463 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11465 [(set_attr "type" "ishift")
11466 (set_attr "length" "2")])
11468 ;; This pattern can't accept a variable shift count, since shifts by
11469 ;; zero don't affect the flags. We assume that shifts by constant
11470 ;; zero are optimized away.
11471 (define_insn "*ashrsi3_cmp"
11474 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11475 (match_operand:QI 2 "immediate_operand" "I"))
11477 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11478 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11479 "ix86_match_ccmode (insn, CCGOCmode)
11480 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11481 "sar{l}\t{%2, %0|%0, %2}"
11482 [(set_attr "type" "ishift")
11483 (set_attr "mode" "SI")])
11485 (define_insn "*ashrsi3_cmp_zext"
11488 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11489 (match_operand:QI 2 "immediate_operand" "I"))
11491 (set (match_operand:DI 0 "register_operand" "=r")
11492 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11493 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11494 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11495 "sar{l}\t{%2, %k0|%k0, %2}"
11496 [(set_attr "type" "ishift")
11497 (set_attr "mode" "SI")])
11499 (define_expand "ashrhi3"
11500 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11501 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11502 (match_operand:QI 2 "nonmemory_operand" "")))
11503 (clobber (reg:CC 17))]
11504 "TARGET_HIMODE_MATH"
11505 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11507 (define_insn "*ashrhi3_1_one_bit"
11508 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11509 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11510 (match_operand:QI 2 "const_int_1_operand" "")))
11511 (clobber (reg:CC 17))]
11512 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11513 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11515 [(set_attr "type" "ishift")
11516 (set (attr "length")
11517 (if_then_else (match_operand 0 "register_operand" "")
11519 (const_string "*")))])
11521 (define_insn "*ashrhi3_1"
11522 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11523 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11524 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11525 (clobber (reg:CC 17))]
11526 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11528 sar{w}\t{%2, %0|%0, %2}
11529 sar{w}\t{%b2, %0|%0, %b2}"
11530 [(set_attr "type" "ishift")
11531 (set_attr "mode" "HI")])
11533 ;; This pattern can't accept a variable shift count, since shifts by
11534 ;; zero don't affect the flags. We assume that shifts by constant
11535 ;; zero are optimized away.
11536 (define_insn "*ashrhi3_one_bit_cmp"
11539 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11540 (match_operand:QI 2 "const_int_1_operand" ""))
11542 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11543 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11544 "ix86_match_ccmode (insn, CCGOCmode)
11545 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11546 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11548 [(set_attr "type" "ishift")
11549 (set (attr "length")
11550 (if_then_else (match_operand 0 "register_operand" "")
11552 (const_string "*")))])
11554 ;; This pattern can't accept a variable shift count, since shifts by
11555 ;; zero don't affect the flags. We assume that shifts by constant
11556 ;; zero are optimized away.
11557 (define_insn "*ashrhi3_cmp"
11560 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11561 (match_operand:QI 2 "immediate_operand" "I"))
11563 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11564 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11565 "ix86_match_ccmode (insn, CCGOCmode)
11566 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11567 "sar{w}\t{%2, %0|%0, %2}"
11568 [(set_attr "type" "ishift")
11569 (set_attr "mode" "HI")])
11571 (define_expand "ashrqi3"
11572 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11573 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11574 (match_operand:QI 2 "nonmemory_operand" "")))
11575 (clobber (reg:CC 17))]
11576 "TARGET_QIMODE_MATH"
11577 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11579 (define_insn "*ashrqi3_1_one_bit"
11580 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11581 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11582 (match_operand:QI 2 "const_int_1_operand" "")))
11583 (clobber (reg:CC 17))]
11584 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11585 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11587 [(set_attr "type" "ishift")
11588 (set (attr "length")
11589 (if_then_else (match_operand 0 "register_operand" "")
11591 (const_string "*")))])
11593 (define_insn "*ashrqi3_1"
11594 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11595 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11596 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11597 (clobber (reg:CC 17))]
11598 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11600 sar{b}\t{%2, %0|%0, %2}
11601 sar{b}\t{%b2, %0|%0, %b2}"
11602 [(set_attr "type" "ishift")
11603 (set_attr "mode" "QI")])
11605 ;; This pattern can't accept a variable shift count, since shifts by
11606 ;; zero don't affect the flags. We assume that shifts by constant
11607 ;; zero are optimized away.
11608 (define_insn "*ashrqi3_one_bit_cmp"
11611 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11612 (match_operand:QI 2 "const_int_1_operand" "I"))
11614 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11615 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11616 "ix86_match_ccmode (insn, CCGOCmode)
11617 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11618 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11620 [(set_attr "type" "ishift")
11621 (set (attr "length")
11622 (if_then_else (match_operand 0 "register_operand" "")
11624 (const_string "*")))])
11626 ;; This pattern can't accept a variable shift count, since shifts by
11627 ;; zero don't affect the flags. We assume that shifts by constant
11628 ;; zero are optimized away.
11629 (define_insn "*ashrqi3_cmp"
11632 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11633 (match_operand:QI 2 "immediate_operand" "I"))
11635 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11636 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11637 "ix86_match_ccmode (insn, CCGOCmode)
11638 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11639 "sar{b}\t{%2, %0|%0, %2}"
11640 [(set_attr "type" "ishift")
11641 (set_attr "mode" "QI")])
11643 ;; Logical shift instructions
11645 ;; See comment above `ashldi3' about how this works.
11647 (define_expand "lshrdi3"
11648 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11649 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11650 (match_operand:QI 2 "nonmemory_operand" "")))
11651 (clobber (reg:CC 17))])]
11654 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11656 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11659 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11663 (define_insn "*lshrdi3_1_one_bit_rex64"
11664 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11665 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11666 (match_operand:QI 2 "const_int_1_operand" "")))
11667 (clobber (reg:CC 17))]
11668 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11669 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11671 [(set_attr "type" "ishift")
11672 (set (attr "length")
11673 (if_then_else (match_operand:DI 0 "register_operand" "")
11675 (const_string "*")))])
11677 (define_insn "*lshrdi3_1_rex64"
11678 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11679 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11680 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11681 (clobber (reg:CC 17))]
11682 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11684 shr{q}\t{%2, %0|%0, %2}
11685 shr{q}\t{%b2, %0|%0, %b2}"
11686 [(set_attr "type" "ishift")
11687 (set_attr "mode" "DI")])
11689 ;; This pattern can't accept a variable shift count, since shifts by
11690 ;; zero don't affect the flags. We assume that shifts by constant
11691 ;; zero are optimized away.
11692 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11695 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11696 (match_operand:QI 2 "const_int_1_operand" ""))
11698 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11699 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11700 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11701 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11702 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11704 [(set_attr "type" "ishift")
11705 (set (attr "length")
11706 (if_then_else (match_operand:DI 0 "register_operand" "")
11708 (const_string "*")))])
11710 ;; This pattern can't accept a variable shift count, since shifts by
11711 ;; zero don't affect the flags. We assume that shifts by constant
11712 ;; zero are optimized away.
11713 (define_insn "*lshrdi3_cmp_rex64"
11716 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11717 (match_operand:QI 2 "const_int_operand" "e"))
11719 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11720 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11721 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11722 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11723 "shr{q}\t{%2, %0|%0, %2}"
11724 [(set_attr "type" "ishift")
11725 (set_attr "mode" "DI")])
11727 (define_insn "lshrdi3_1"
11728 [(set (match_operand:DI 0 "register_operand" "=r")
11729 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11730 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11731 (clobber (match_scratch:SI 3 "=&r"))
11732 (clobber (reg:CC 17))]
11733 "!TARGET_64BIT && TARGET_CMOVE"
11735 [(set_attr "type" "multi")])
11737 (define_insn "*lshrdi3_2"
11738 [(set (match_operand:DI 0 "register_operand" "=r")
11739 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11740 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11741 (clobber (reg:CC 17))]
11744 [(set_attr "type" "multi")])
11747 [(set (match_operand:DI 0 "register_operand" "")
11748 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11749 (match_operand:QI 2 "nonmemory_operand" "")))
11750 (clobber (match_scratch:SI 3 ""))
11751 (clobber (reg:CC 17))]
11752 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11754 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11757 [(set (match_operand:DI 0 "register_operand" "")
11758 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11759 (match_operand:QI 2 "nonmemory_operand" "")))
11760 (clobber (reg:CC 17))]
11761 "!TARGET_64BIT && reload_completed"
11763 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11765 (define_expand "lshrsi3"
11766 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11767 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11768 (match_operand:QI 2 "nonmemory_operand" "")))
11769 (clobber (reg:CC 17))]
11771 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11773 (define_insn "*lshrsi3_1_one_bit"
11774 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11775 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11776 (match_operand:QI 2 "const_int_1_operand" "")))
11777 (clobber (reg:CC 17))]
11778 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11779 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11781 [(set_attr "type" "ishift")
11782 (set (attr "length")
11783 (if_then_else (match_operand:SI 0 "register_operand" "")
11785 (const_string "*")))])
11787 (define_insn "*lshrsi3_1_one_bit_zext"
11788 [(set (match_operand:DI 0 "register_operand" "=r")
11789 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11790 (match_operand:QI 2 "const_int_1_operand" "")))
11791 (clobber (reg:CC 17))]
11792 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11793 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11795 [(set_attr "type" "ishift")
11796 (set_attr "length" "2")])
11798 (define_insn "*lshrsi3_1"
11799 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11800 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11801 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11802 (clobber (reg:CC 17))]
11803 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11805 shr{l}\t{%2, %0|%0, %2}
11806 shr{l}\t{%b2, %0|%0, %b2}"
11807 [(set_attr "type" "ishift")
11808 (set_attr "mode" "SI")])
11810 (define_insn "*lshrsi3_1_zext"
11811 [(set (match_operand:DI 0 "register_operand" "=r,r")
11813 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11814 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11815 (clobber (reg:CC 17))]
11816 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11818 shr{l}\t{%2, %k0|%k0, %2}
11819 shr{l}\t{%b2, %k0|%k0, %b2}"
11820 [(set_attr "type" "ishift")
11821 (set_attr "mode" "SI")])
11823 ;; This pattern can't accept a variable shift count, since shifts by
11824 ;; zero don't affect the flags. We assume that shifts by constant
11825 ;; zero are optimized away.
11826 (define_insn "*lshrsi3_one_bit_cmp"
11829 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11830 (match_operand:QI 2 "const_int_1_operand" ""))
11832 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11833 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11834 "ix86_match_ccmode (insn, CCGOCmode)
11835 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11836 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11838 [(set_attr "type" "ishift")
11839 (set (attr "length")
11840 (if_then_else (match_operand:SI 0 "register_operand" "")
11842 (const_string "*")))])
11844 (define_insn "*lshrsi3_cmp_one_bit_zext"
11847 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11848 (match_operand:QI 2 "const_int_1_operand" ""))
11850 (set (match_operand:DI 0 "register_operand" "=r")
11851 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11852 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11853 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11854 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11856 [(set_attr "type" "ishift")
11857 (set_attr "length" "2")])
11859 ;; This pattern can't accept a variable shift count, since shifts by
11860 ;; zero don't affect the flags. We assume that shifts by constant
11861 ;; zero are optimized away.
11862 (define_insn "*lshrsi3_cmp"
11865 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11866 (match_operand:QI 2 "immediate_operand" "I"))
11868 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11869 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11870 "ix86_match_ccmode (insn, CCGOCmode)
11871 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11872 "shr{l}\t{%2, %0|%0, %2}"
11873 [(set_attr "type" "ishift")
11874 (set_attr "mode" "SI")])
11876 (define_insn "*lshrsi3_cmp_zext"
11879 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11880 (match_operand:QI 2 "immediate_operand" "I"))
11882 (set (match_operand:DI 0 "register_operand" "=r")
11883 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11884 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11885 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11886 "shr{l}\t{%2, %k0|%k0, %2}"
11887 [(set_attr "type" "ishift")
11888 (set_attr "mode" "SI")])
11890 (define_expand "lshrhi3"
11891 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11892 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11893 (match_operand:QI 2 "nonmemory_operand" "")))
11894 (clobber (reg:CC 17))]
11895 "TARGET_HIMODE_MATH"
11896 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11898 (define_insn "*lshrhi3_1_one_bit"
11899 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11900 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11901 (match_operand:QI 2 "const_int_1_operand" "")))
11902 (clobber (reg:CC 17))]
11903 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11904 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11906 [(set_attr "type" "ishift")
11907 (set (attr "length")
11908 (if_then_else (match_operand 0 "register_operand" "")
11910 (const_string "*")))])
11912 (define_insn "*lshrhi3_1"
11913 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11914 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11915 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11916 (clobber (reg:CC 17))]
11917 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11919 shr{w}\t{%2, %0|%0, %2}
11920 shr{w}\t{%b2, %0|%0, %b2}"
11921 [(set_attr "type" "ishift")
11922 (set_attr "mode" "HI")])
11924 ;; This pattern can't accept a variable shift count, since shifts by
11925 ;; zero don't affect the flags. We assume that shifts by constant
11926 ;; zero are optimized away.
11927 (define_insn "*lshrhi3_one_bit_cmp"
11930 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11931 (match_operand:QI 2 "const_int_1_operand" ""))
11933 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11934 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11935 "ix86_match_ccmode (insn, CCGOCmode)
11936 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11937 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11939 [(set_attr "type" "ishift")
11940 (set (attr "length")
11941 (if_then_else (match_operand:SI 0 "register_operand" "")
11943 (const_string "*")))])
11945 ;; This pattern can't accept a variable shift count, since shifts by
11946 ;; zero don't affect the flags. We assume that shifts by constant
11947 ;; zero are optimized away.
11948 (define_insn "*lshrhi3_cmp"
11951 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11952 (match_operand:QI 2 "immediate_operand" "I"))
11954 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11955 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11956 "ix86_match_ccmode (insn, CCGOCmode)
11957 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11958 "shr{w}\t{%2, %0|%0, %2}"
11959 [(set_attr "type" "ishift")
11960 (set_attr "mode" "HI")])
11962 (define_expand "lshrqi3"
11963 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11964 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11965 (match_operand:QI 2 "nonmemory_operand" "")))
11966 (clobber (reg:CC 17))]
11967 "TARGET_QIMODE_MATH"
11968 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11970 (define_insn "*lshrqi3_1_one_bit"
11971 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11972 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11973 (match_operand:QI 2 "const_int_1_operand" "")))
11974 (clobber (reg:CC 17))]
11975 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11976 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11978 [(set_attr "type" "ishift")
11979 (set (attr "length")
11980 (if_then_else (match_operand 0 "register_operand" "")
11982 (const_string "*")))])
11984 (define_insn "*lshrqi3_1"
11985 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11986 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11987 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11988 (clobber (reg:CC 17))]
11989 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11991 shr{b}\t{%2, %0|%0, %2}
11992 shr{b}\t{%b2, %0|%0, %b2}"
11993 [(set_attr "type" "ishift")
11994 (set_attr "mode" "QI")])
11996 ;; This pattern can't accept a variable shift count, since shifts by
11997 ;; zero don't affect the flags. We assume that shifts by constant
11998 ;; zero are optimized away.
11999 (define_insn "*lshrqi2_one_bit_cmp"
12002 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12003 (match_operand:QI 2 "const_int_1_operand" ""))
12005 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12006 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12007 "ix86_match_ccmode (insn, CCGOCmode)
12008 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
12009 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12011 [(set_attr "type" "ishift")
12012 (set (attr "length")
12013 (if_then_else (match_operand:SI 0 "register_operand" "")
12015 (const_string "*")))])
12017 ;; This pattern can't accept a variable shift count, since shifts by
12018 ;; zero don't affect the flags. We assume that shifts by constant
12019 ;; zero are optimized away.
12020 (define_insn "*lshrqi2_cmp"
12023 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12024 (match_operand:QI 2 "immediate_operand" "I"))
12026 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12027 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12028 "ix86_match_ccmode (insn, CCGOCmode)
12029 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12030 "shr{b}\t{%2, %0|%0, %2}"
12031 [(set_attr "type" "ishift")
12032 (set_attr "mode" "QI")])
12034 ;; Rotate instructions
12036 (define_expand "rotldi3"
12037 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12038 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12039 (match_operand:QI 2 "nonmemory_operand" "")))
12040 (clobber (reg:CC 17))]
12042 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12044 (define_insn "*rotlsi3_1_one_bit_rex64"
12045 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12046 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12047 (match_operand:QI 2 "const_int_1_operand" "")))
12048 (clobber (reg:CC 17))]
12049 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12050 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12052 [(set_attr "type" "ishift")
12053 (set (attr "length")
12054 (if_then_else (match_operand:DI 0 "register_operand" "")
12056 (const_string "*")))])
12058 (define_insn "*rotldi3_1_rex64"
12059 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12060 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12061 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12062 (clobber (reg:CC 17))]
12063 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12065 rol{q}\t{%2, %0|%0, %2}
12066 rol{q}\t{%b2, %0|%0, %b2}"
12067 [(set_attr "type" "ishift")
12068 (set_attr "mode" "DI")])
12070 (define_expand "rotlsi3"
12071 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12072 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12073 (match_operand:QI 2 "nonmemory_operand" "")))
12074 (clobber (reg:CC 17))]
12076 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12078 (define_insn "*rotlsi3_1_one_bit"
12079 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12080 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12081 (match_operand:QI 2 "const_int_1_operand" "")))
12082 (clobber (reg:CC 17))]
12083 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12084 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12086 [(set_attr "type" "ishift")
12087 (set (attr "length")
12088 (if_then_else (match_operand:SI 0 "register_operand" "")
12090 (const_string "*")))])
12092 (define_insn "*rotlsi3_1_one_bit_zext"
12093 [(set (match_operand:DI 0 "register_operand" "=r")
12095 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12096 (match_operand:QI 2 "const_int_1_operand" ""))))
12097 (clobber (reg:CC 17))]
12098 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12099 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12101 [(set_attr "type" "ishift")
12102 (set_attr "length" "2")])
12104 (define_insn "*rotlsi3_1"
12105 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12106 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12107 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12108 (clobber (reg:CC 17))]
12109 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12111 rol{l}\t{%2, %0|%0, %2}
12112 rol{l}\t{%b2, %0|%0, %b2}"
12113 [(set_attr "type" "ishift")
12114 (set_attr "mode" "SI")])
12116 (define_insn "*rotlsi3_1_zext"
12117 [(set (match_operand:DI 0 "register_operand" "=r,r")
12119 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12120 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12121 (clobber (reg:CC 17))]
12122 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12124 rol{l}\t{%2, %k0|%k0, %2}
12125 rol{l}\t{%b2, %k0|%k0, %b2}"
12126 [(set_attr "type" "ishift")
12127 (set_attr "mode" "SI")])
12129 (define_expand "rotlhi3"
12130 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12131 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12132 (match_operand:QI 2 "nonmemory_operand" "")))
12133 (clobber (reg:CC 17))]
12134 "TARGET_HIMODE_MATH"
12135 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12137 (define_insn "*rotlhi3_1_one_bit"
12138 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12139 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12140 (match_operand:QI 2 "const_int_1_operand" "")))
12141 (clobber (reg:CC 17))]
12142 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12143 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12145 [(set_attr "type" "ishift")
12146 (set (attr "length")
12147 (if_then_else (match_operand 0 "register_operand" "")
12149 (const_string "*")))])
12151 (define_insn "*rotlhi3_1"
12152 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12153 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12154 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12155 (clobber (reg:CC 17))]
12156 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12158 rol{w}\t{%2, %0|%0, %2}
12159 rol{w}\t{%b2, %0|%0, %b2}"
12160 [(set_attr "type" "ishift")
12161 (set_attr "mode" "HI")])
12163 (define_expand "rotlqi3"
12164 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12165 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12166 (match_operand:QI 2 "nonmemory_operand" "")))
12167 (clobber (reg:CC 17))]
12168 "TARGET_QIMODE_MATH"
12169 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12171 (define_insn "*rotlqi3_1_one_bit"
12172 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12173 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12174 (match_operand:QI 2 "const_int_1_operand" "")))
12175 (clobber (reg:CC 17))]
12176 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12177 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12179 [(set_attr "type" "ishift")
12180 (set (attr "length")
12181 (if_then_else (match_operand 0 "register_operand" "")
12183 (const_string "*")))])
12185 (define_insn "*rotlqi3_1"
12186 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12187 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12188 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12189 (clobber (reg:CC 17))]
12190 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12192 rol{b}\t{%2, %0|%0, %2}
12193 rol{b}\t{%b2, %0|%0, %b2}"
12194 [(set_attr "type" "ishift")
12195 (set_attr "mode" "QI")])
12197 (define_expand "rotrdi3"
12198 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12199 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12200 (match_operand:QI 2 "nonmemory_operand" "")))
12201 (clobber (reg:CC 17))]
12203 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12205 (define_insn "*rotrdi3_1_one_bit_rex64"
12206 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12207 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12208 (match_operand:QI 2 "const_int_1_operand" "")))
12209 (clobber (reg:CC 17))]
12210 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12211 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12213 [(set_attr "type" "ishift")
12214 (set (attr "length")
12215 (if_then_else (match_operand:DI 0 "register_operand" "")
12217 (const_string "*")))])
12219 (define_insn "*rotrdi3_1_rex64"
12220 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12221 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12222 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12223 (clobber (reg:CC 17))]
12224 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12226 ror{q}\t{%2, %0|%0, %2}
12227 ror{q}\t{%b2, %0|%0, %b2}"
12228 [(set_attr "type" "ishift")
12229 (set_attr "mode" "DI")])
12231 (define_expand "rotrsi3"
12232 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12233 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12234 (match_operand:QI 2 "nonmemory_operand" "")))
12235 (clobber (reg:CC 17))]
12237 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12239 (define_insn "*rotrsi3_1_one_bit"
12240 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12241 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12242 (match_operand:QI 2 "const_int_1_operand" "")))
12243 (clobber (reg:CC 17))]
12244 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12245 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12247 [(set_attr "type" "ishift")
12248 (set (attr "length")
12249 (if_then_else (match_operand:SI 0 "register_operand" "")
12251 (const_string "*")))])
12253 (define_insn "*rotrsi3_1_one_bit_zext"
12254 [(set (match_operand:DI 0 "register_operand" "=r")
12256 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12257 (match_operand:QI 2 "const_int_1_operand" ""))))
12258 (clobber (reg:CC 17))]
12259 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12260 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12262 [(set_attr "type" "ishift")
12263 (set (attr "length")
12264 (if_then_else (match_operand:SI 0 "register_operand" "")
12266 (const_string "*")))])
12268 (define_insn "*rotrsi3_1"
12269 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12270 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12271 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12272 (clobber (reg:CC 17))]
12273 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12275 ror{l}\t{%2, %0|%0, %2}
12276 ror{l}\t{%b2, %0|%0, %b2}"
12277 [(set_attr "type" "ishift")
12278 (set_attr "mode" "SI")])
12280 (define_insn "*rotrsi3_1_zext"
12281 [(set (match_operand:DI 0 "register_operand" "=r,r")
12283 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12284 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12285 (clobber (reg:CC 17))]
12286 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12288 ror{l}\t{%2, %k0|%k0, %2}
12289 ror{l}\t{%b2, %k0|%k0, %b2}"
12290 [(set_attr "type" "ishift")
12291 (set_attr "mode" "SI")])
12293 (define_expand "rotrhi3"
12294 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12295 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12296 (match_operand:QI 2 "nonmemory_operand" "")))
12297 (clobber (reg:CC 17))]
12298 "TARGET_HIMODE_MATH"
12299 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12301 (define_insn "*rotrhi3_one_bit"
12302 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12303 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12304 (match_operand:QI 2 "const_int_1_operand" "")))
12305 (clobber (reg:CC 17))]
12306 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12307 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12309 [(set_attr "type" "ishift")
12310 (set (attr "length")
12311 (if_then_else (match_operand 0 "register_operand" "")
12313 (const_string "*")))])
12315 (define_insn "*rotrhi3"
12316 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12317 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12318 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12319 (clobber (reg:CC 17))]
12320 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12322 ror{w}\t{%2, %0|%0, %2}
12323 ror{w}\t{%b2, %0|%0, %b2}"
12324 [(set_attr "type" "ishift")
12325 (set_attr "mode" "HI")])
12327 (define_expand "rotrqi3"
12328 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12329 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12330 (match_operand:QI 2 "nonmemory_operand" "")))
12331 (clobber (reg:CC 17))]
12332 "TARGET_QIMODE_MATH"
12333 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12335 (define_insn "*rotrqi3_1_one_bit"
12336 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12337 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12338 (match_operand:QI 2 "const_int_1_operand" "")))
12339 (clobber (reg:CC 17))]
12340 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12341 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12343 [(set_attr "type" "ishift")
12344 (set (attr "length")
12345 (if_then_else (match_operand 0 "register_operand" "")
12347 (const_string "*")))])
12349 (define_insn "*rotrqi3_1"
12350 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12351 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12352 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12353 (clobber (reg:CC 17))]
12354 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12356 ror{b}\t{%2, %0|%0, %2}
12357 ror{b}\t{%b2, %0|%0, %b2}"
12358 [(set_attr "type" "ishift")
12359 (set_attr "mode" "QI")])
12361 ;; Bit set / bit test instructions
12363 (define_expand "extv"
12364 [(set (match_operand:SI 0 "register_operand" "")
12365 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12366 (match_operand:SI 2 "immediate_operand" "")
12367 (match_operand:SI 3 "immediate_operand" "")))]
12370 /* Handle extractions from %ah et al. */
12371 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12374 /* From mips.md: extract_bit_field doesn't verify that our source
12375 matches the predicate, so check it again here. */
12376 if (! register_operand (operands[1], VOIDmode))
12380 (define_expand "extzv"
12381 [(set (match_operand:SI 0 "register_operand" "")
12382 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12383 (match_operand:SI 2 "immediate_operand" "")
12384 (match_operand:SI 3 "immediate_operand" "")))]
12387 /* Handle extractions from %ah et al. */
12388 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12391 /* From mips.md: extract_bit_field doesn't verify that our source
12392 matches the predicate, so check it again here. */
12393 if (! register_operand (operands[1], VOIDmode))
12397 (define_expand "insv"
12398 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12399 (match_operand:SI 1 "immediate_operand" "")
12400 (match_operand:SI 2 "immediate_operand" ""))
12401 (match_operand:SI 3 "register_operand" ""))]
12404 /* Handle extractions from %ah et al. */
12405 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12408 /* From mips.md: insert_bit_field doesn't verify that our source
12409 matches the predicate, so check it again here. */
12410 if (! register_operand (operands[0], VOIDmode))
12414 ;; %%% bts, btr, btc, bt.
12416 ;; Store-flag instructions.
12418 ;; For all sCOND expanders, also expand the compare or test insn that
12419 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12421 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12422 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12423 ;; way, which can later delete the movzx if only QImode is needed.
12425 (define_expand "seq"
12426 [(set (match_operand:QI 0 "register_operand" "")
12427 (eq:QI (reg:CC 17) (const_int 0)))]
12429 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12431 (define_expand "sne"
12432 [(set (match_operand:QI 0 "register_operand" "")
12433 (ne:QI (reg:CC 17) (const_int 0)))]
12435 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12437 (define_expand "sgt"
12438 [(set (match_operand:QI 0 "register_operand" "")
12439 (gt:QI (reg:CC 17) (const_int 0)))]
12441 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12443 (define_expand "sgtu"
12444 [(set (match_operand:QI 0 "register_operand" "")
12445 (gtu:QI (reg:CC 17) (const_int 0)))]
12447 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12449 (define_expand "slt"
12450 [(set (match_operand:QI 0 "register_operand" "")
12451 (lt:QI (reg:CC 17) (const_int 0)))]
12453 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12455 (define_expand "sltu"
12456 [(set (match_operand:QI 0 "register_operand" "")
12457 (ltu:QI (reg:CC 17) (const_int 0)))]
12459 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12461 (define_expand "sge"
12462 [(set (match_operand:QI 0 "register_operand" "")
12463 (ge:QI (reg:CC 17) (const_int 0)))]
12465 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12467 (define_expand "sgeu"
12468 [(set (match_operand:QI 0 "register_operand" "")
12469 (geu:QI (reg:CC 17) (const_int 0)))]
12471 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12473 (define_expand "sle"
12474 [(set (match_operand:QI 0 "register_operand" "")
12475 (le:QI (reg:CC 17) (const_int 0)))]
12477 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12479 (define_expand "sleu"
12480 [(set (match_operand:QI 0 "register_operand" "")
12481 (leu:QI (reg:CC 17) (const_int 0)))]
12483 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12485 (define_expand "sunordered"
12486 [(set (match_operand:QI 0 "register_operand" "")
12487 (unordered:QI (reg:CC 17) (const_int 0)))]
12488 "TARGET_80387 || TARGET_SSE"
12489 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12491 (define_expand "sordered"
12492 [(set (match_operand:QI 0 "register_operand" "")
12493 (ordered:QI (reg:CC 17) (const_int 0)))]
12495 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12497 (define_expand "suneq"
12498 [(set (match_operand:QI 0 "register_operand" "")
12499 (uneq:QI (reg:CC 17) (const_int 0)))]
12500 "TARGET_80387 || TARGET_SSE"
12501 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12503 (define_expand "sunge"
12504 [(set (match_operand:QI 0 "register_operand" "")
12505 (unge:QI (reg:CC 17) (const_int 0)))]
12506 "TARGET_80387 || TARGET_SSE"
12507 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12509 (define_expand "sungt"
12510 [(set (match_operand:QI 0 "register_operand" "")
12511 (ungt:QI (reg:CC 17) (const_int 0)))]
12512 "TARGET_80387 || TARGET_SSE"
12513 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12515 (define_expand "sunle"
12516 [(set (match_operand:QI 0 "register_operand" "")
12517 (unle:QI (reg:CC 17) (const_int 0)))]
12518 "TARGET_80387 || TARGET_SSE"
12519 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12521 (define_expand "sunlt"
12522 [(set (match_operand:QI 0 "register_operand" "")
12523 (unlt:QI (reg:CC 17) (const_int 0)))]
12524 "TARGET_80387 || TARGET_SSE"
12525 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12527 (define_expand "sltgt"
12528 [(set (match_operand:QI 0 "register_operand" "")
12529 (ltgt:QI (reg:CC 17) (const_int 0)))]
12530 "TARGET_80387 || TARGET_SSE"
12531 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12533 (define_insn "*setcc_1"
12534 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12535 (match_operator:QI 1 "ix86_comparison_operator"
12536 [(reg 17) (const_int 0)]))]
12539 [(set_attr "type" "setcc")
12540 (set_attr "mode" "QI")])
12542 (define_insn "setcc_2"
12543 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12544 (match_operator:QI 1 "ix86_comparison_operator"
12545 [(reg 17) (const_int 0)]))]
12548 [(set_attr "type" "setcc")
12549 (set_attr "mode" "QI")])
12551 ;; In general it is not safe to assume too much about CCmode registers,
12552 ;; so simplify-rtx stops when it sees a second one. Under certain
12553 ;; conditions this is safe on x86, so help combine not create
12560 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12561 (ne:QI (match_operator 1 "ix86_comparison_operator"
12562 [(reg 17) (const_int 0)])
12565 [(set (match_dup 0) (match_dup 1))]
12567 PUT_MODE (operands[1], QImode);
12571 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12572 (ne:QI (match_operator 1 "ix86_comparison_operator"
12573 [(reg 17) (const_int 0)])
12576 [(set (match_dup 0) (match_dup 1))]
12578 PUT_MODE (operands[1], QImode);
12582 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12583 (eq:QI (match_operator 1 "ix86_comparison_operator"
12584 [(reg 17) (const_int 0)])
12587 [(set (match_dup 0) (match_dup 1))]
12589 rtx new_op1 = copy_rtx (operands[1]);
12590 operands[1] = new_op1;
12591 PUT_MODE (new_op1, QImode);
12592 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12593 GET_MODE (XEXP (new_op1, 0))));
12595 /* Make sure that (a) the CCmode we have for the flags is strong
12596 enough for the reversed compare or (b) we have a valid FP compare. */
12597 if (! ix86_comparison_operator (new_op1, VOIDmode))
12602 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12603 (eq:QI (match_operator 1 "ix86_comparison_operator"
12604 [(reg 17) (const_int 0)])
12607 [(set (match_dup 0) (match_dup 1))]
12609 rtx new_op1 = copy_rtx (operands[1]);
12610 operands[1] = new_op1;
12611 PUT_MODE (new_op1, QImode);
12612 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12613 GET_MODE (XEXP (new_op1, 0))));
12615 /* Make sure that (a) the CCmode we have for the flags is strong
12616 enough for the reversed compare or (b) we have a valid FP compare. */
12617 if (! ix86_comparison_operator (new_op1, VOIDmode))
12621 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12622 ;; subsequent logical operations are used to imitate conditional moves.
12623 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12624 ;; it directly. Futher holding this value in pseudo register might bring
12625 ;; problem in implicit normalization in spill code.
12626 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12627 ;; instructions after reload by splitting the conditional move patterns.
12629 (define_insn "*sse_setccsf"
12630 [(set (match_operand:SF 0 "register_operand" "=x")
12631 (match_operator:SF 1 "sse_comparison_operator"
12632 [(match_operand:SF 2 "register_operand" "0")
12633 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12634 "TARGET_SSE && reload_completed"
12635 "cmp%D1ss\t{%3, %0|%0, %3}"
12636 [(set_attr "type" "sse")
12637 (set_attr "mode" "SF")])
12639 (define_insn "*sse_setccdf"
12640 [(set (match_operand:DF 0 "register_operand" "=Y")
12641 (match_operator:DF 1 "sse_comparison_operator"
12642 [(match_operand:DF 2 "register_operand" "0")
12643 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12644 "TARGET_SSE2 && reload_completed"
12645 "cmp%D1sd\t{%3, %0|%0, %3}"
12646 [(set_attr "type" "sse")
12647 (set_attr "mode" "DF")])
12649 ;; Basic conditional jump instructions.
12650 ;; We ignore the overflow flag for signed branch instructions.
12652 ;; For all bCOND expanders, also expand the compare or test insn that
12653 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12655 (define_expand "beq"
12657 (if_then_else (match_dup 1)
12658 (label_ref (match_operand 0 "" ""))
12661 "ix86_expand_branch (EQ, operands[0]); DONE;")
12663 (define_expand "bne"
12665 (if_then_else (match_dup 1)
12666 (label_ref (match_operand 0 "" ""))
12669 "ix86_expand_branch (NE, operands[0]); DONE;")
12671 (define_expand "bgt"
12673 (if_then_else (match_dup 1)
12674 (label_ref (match_operand 0 "" ""))
12677 "ix86_expand_branch (GT, operands[0]); DONE;")
12679 (define_expand "bgtu"
12681 (if_then_else (match_dup 1)
12682 (label_ref (match_operand 0 "" ""))
12685 "ix86_expand_branch (GTU, operands[0]); DONE;")
12687 (define_expand "blt"
12689 (if_then_else (match_dup 1)
12690 (label_ref (match_operand 0 "" ""))
12693 "ix86_expand_branch (LT, operands[0]); DONE;")
12695 (define_expand "bltu"
12697 (if_then_else (match_dup 1)
12698 (label_ref (match_operand 0 "" ""))
12701 "ix86_expand_branch (LTU, operands[0]); DONE;")
12703 (define_expand "bge"
12705 (if_then_else (match_dup 1)
12706 (label_ref (match_operand 0 "" ""))
12709 "ix86_expand_branch (GE, operands[0]); DONE;")
12711 (define_expand "bgeu"
12713 (if_then_else (match_dup 1)
12714 (label_ref (match_operand 0 "" ""))
12717 "ix86_expand_branch (GEU, operands[0]); DONE;")
12719 (define_expand "ble"
12721 (if_then_else (match_dup 1)
12722 (label_ref (match_operand 0 "" ""))
12725 "ix86_expand_branch (LE, operands[0]); DONE;")
12727 (define_expand "bleu"
12729 (if_then_else (match_dup 1)
12730 (label_ref (match_operand 0 "" ""))
12733 "ix86_expand_branch (LEU, operands[0]); DONE;")
12735 (define_expand "bunordered"
12737 (if_then_else (match_dup 1)
12738 (label_ref (match_operand 0 "" ""))
12740 "TARGET_80387 || TARGET_SSE"
12741 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12743 (define_expand "bordered"
12745 (if_then_else (match_dup 1)
12746 (label_ref (match_operand 0 "" ""))
12748 "TARGET_80387 || TARGET_SSE"
12749 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12751 (define_expand "buneq"
12753 (if_then_else (match_dup 1)
12754 (label_ref (match_operand 0 "" ""))
12756 "TARGET_80387 || TARGET_SSE"
12757 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12759 (define_expand "bunge"
12761 (if_then_else (match_dup 1)
12762 (label_ref (match_operand 0 "" ""))
12764 "TARGET_80387 || TARGET_SSE"
12765 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12767 (define_expand "bungt"
12769 (if_then_else (match_dup 1)
12770 (label_ref (match_operand 0 "" ""))
12772 "TARGET_80387 || TARGET_SSE"
12773 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12775 (define_expand "bunle"
12777 (if_then_else (match_dup 1)
12778 (label_ref (match_operand 0 "" ""))
12780 "TARGET_80387 || TARGET_SSE"
12781 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12783 (define_expand "bunlt"
12785 (if_then_else (match_dup 1)
12786 (label_ref (match_operand 0 "" ""))
12788 "TARGET_80387 || TARGET_SSE"
12789 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12791 (define_expand "bltgt"
12793 (if_then_else (match_dup 1)
12794 (label_ref (match_operand 0 "" ""))
12796 "TARGET_80387 || TARGET_SSE"
12797 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12799 (define_insn "*jcc_1"
12801 (if_then_else (match_operator 1 "ix86_comparison_operator"
12802 [(reg 17) (const_int 0)])
12803 (label_ref (match_operand 0 "" ""))
12807 [(set_attr "type" "ibr")
12808 (set (attr "prefix_0f")
12809 (if_then_else (and (ge (minus (match_dup 0) (pc))
12811 (lt (minus (match_dup 0) (pc))
12816 (define_insn "*jcc_2"
12818 (if_then_else (match_operator 1 "ix86_comparison_operator"
12819 [(reg 17) (const_int 0)])
12821 (label_ref (match_operand 0 "" ""))))]
12824 [(set_attr "type" "ibr")
12825 (set (attr "prefix_0f")
12826 (if_then_else (and (ge (minus (match_dup 0) (pc))
12828 (lt (minus (match_dup 0) (pc))
12833 ;; In general it is not safe to assume too much about CCmode registers,
12834 ;; so simplify-rtx stops when it sees a second one. Under certain
12835 ;; conditions this is safe on x86, so help combine not create
12843 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
12844 [(reg 17) (const_int 0)])
12846 (label_ref (match_operand 1 "" ""))
12850 (if_then_else (match_dup 0)
12851 (label_ref (match_dup 1))
12854 PUT_MODE (operands[0], VOIDmode);
12859 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
12860 [(reg 17) (const_int 0)])
12862 (label_ref (match_operand 1 "" ""))
12866 (if_then_else (match_dup 0)
12867 (label_ref (match_dup 1))
12870 rtx new_op0 = copy_rtx (operands[0]);
12871 operands[0] = new_op0;
12872 PUT_MODE (new_op0, VOIDmode);
12873 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
12874 GET_MODE (XEXP (new_op0, 0))));
12876 /* Make sure that (a) the CCmode we have for the flags is strong
12877 enough for the reversed compare or (b) we have a valid FP compare. */
12878 if (! ix86_comparison_operator (new_op0, VOIDmode))
12882 ;; Define combination compare-and-branch fp compare instructions to use
12883 ;; during early optimization. Splitting the operation apart early makes
12884 ;; for bad code when we want to reverse the operation.
12886 (define_insn "*fp_jcc_1"
12888 (if_then_else (match_operator 0 "comparison_operator"
12889 [(match_operand 1 "register_operand" "f")
12890 (match_operand 2 "register_operand" "f")])
12891 (label_ref (match_operand 3 "" ""))
12893 (clobber (reg:CCFP 18))
12894 (clobber (reg:CCFP 17))]
12895 "TARGET_CMOVE && TARGET_80387
12896 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12897 && FLOAT_MODE_P (GET_MODE (operands[1]))
12898 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12899 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12902 (define_insn "*fp_jcc_1_sse"
12904 (if_then_else (match_operator 0 "comparison_operator"
12905 [(match_operand 1 "register_operand" "f#x,x#f")
12906 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12907 (label_ref (match_operand 3 "" ""))
12909 (clobber (reg:CCFP 18))
12910 (clobber (reg:CCFP 17))]
12912 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12913 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12914 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12917 (define_insn "*fp_jcc_1_sse_only"
12919 (if_then_else (match_operator 0 "comparison_operator"
12920 [(match_operand 1 "register_operand" "x")
12921 (match_operand 2 "nonimmediate_operand" "xm")])
12922 (label_ref (match_operand 3 "" ""))
12924 (clobber (reg:CCFP 18))
12925 (clobber (reg:CCFP 17))]
12926 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12927 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12928 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12931 (define_insn "*fp_jcc_2"
12933 (if_then_else (match_operator 0 "comparison_operator"
12934 [(match_operand 1 "register_operand" "f")
12935 (match_operand 2 "register_operand" "f")])
12937 (label_ref (match_operand 3 "" ""))))
12938 (clobber (reg:CCFP 18))
12939 (clobber (reg:CCFP 17))]
12940 "TARGET_CMOVE && TARGET_80387
12941 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12942 && FLOAT_MODE_P (GET_MODE (operands[1]))
12943 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12944 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12947 (define_insn "*fp_jcc_2_sse"
12949 (if_then_else (match_operator 0 "comparison_operator"
12950 [(match_operand 1 "register_operand" "f#x,x#f")
12951 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12953 (label_ref (match_operand 3 "" ""))))
12954 (clobber (reg:CCFP 18))
12955 (clobber (reg:CCFP 17))]
12957 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12958 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12959 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12962 (define_insn "*fp_jcc_2_sse_only"
12964 (if_then_else (match_operator 0 "comparison_operator"
12965 [(match_operand 1 "register_operand" "x")
12966 (match_operand 2 "nonimmediate_operand" "xm")])
12968 (label_ref (match_operand 3 "" ""))))
12969 (clobber (reg:CCFP 18))
12970 (clobber (reg:CCFP 17))]
12971 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12972 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12973 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12976 (define_insn "*fp_jcc_3"
12978 (if_then_else (match_operator 0 "comparison_operator"
12979 [(match_operand 1 "register_operand" "f")
12980 (match_operand 2 "nonimmediate_operand" "fm")])
12981 (label_ref (match_operand 3 "" ""))
12983 (clobber (reg:CCFP 18))
12984 (clobber (reg:CCFP 17))
12985 (clobber (match_scratch:HI 4 "=a"))]
12987 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12988 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12989 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12990 && SELECT_CC_MODE (GET_CODE (operands[0]),
12991 operands[1], operands[2]) == CCFPmode
12992 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12995 (define_insn "*fp_jcc_4"
12997 (if_then_else (match_operator 0 "comparison_operator"
12998 [(match_operand 1 "register_operand" "f")
12999 (match_operand 2 "nonimmediate_operand" "fm")])
13001 (label_ref (match_operand 3 "" ""))))
13002 (clobber (reg:CCFP 18))
13003 (clobber (reg:CCFP 17))
13004 (clobber (match_scratch:HI 4 "=a"))]
13006 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13007 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13008 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13009 && SELECT_CC_MODE (GET_CODE (operands[0]),
13010 operands[1], operands[2]) == CCFPmode
13011 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13014 (define_insn "*fp_jcc_5"
13016 (if_then_else (match_operator 0 "comparison_operator"
13017 [(match_operand 1 "register_operand" "f")
13018 (match_operand 2 "register_operand" "f")])
13019 (label_ref (match_operand 3 "" ""))
13021 (clobber (reg:CCFP 18))
13022 (clobber (reg:CCFP 17))
13023 (clobber (match_scratch:HI 4 "=a"))]
13025 && FLOAT_MODE_P (GET_MODE (operands[1]))
13026 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13027 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13030 (define_insn "*fp_jcc_6"
13032 (if_then_else (match_operator 0 "comparison_operator"
13033 [(match_operand 1 "register_operand" "f")
13034 (match_operand 2 "register_operand" "f")])
13036 (label_ref (match_operand 3 "" ""))))
13037 (clobber (reg:CCFP 18))
13038 (clobber (reg:CCFP 17))
13039 (clobber (match_scratch:HI 4 "=a"))]
13041 && FLOAT_MODE_P (GET_MODE (operands[1]))
13042 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13043 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13048 (if_then_else (match_operator 0 "comparison_operator"
13049 [(match_operand 1 "register_operand" "")
13050 (match_operand 2 "nonimmediate_operand" "")])
13051 (match_operand 3 "" "")
13052 (match_operand 4 "" "")))
13053 (clobber (reg:CCFP 18))
13054 (clobber (reg:CCFP 17))]
13058 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13059 operands[3], operands[4], NULL_RTX);
13065 (if_then_else (match_operator 0 "comparison_operator"
13066 [(match_operand 1 "register_operand" "")
13067 (match_operand 2 "nonimmediate_operand" "")])
13068 (match_operand 3 "" "")
13069 (match_operand 4 "" "")))
13070 (clobber (reg:CCFP 18))
13071 (clobber (reg:CCFP 17))
13072 (clobber (match_scratch:HI 5 "=a"))]
13075 (if_then_else (match_dup 6)
13079 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13080 operands[3], operands[4], operands[5]);
13084 ;; Unconditional and other jump instructions
13086 (define_insn "jump"
13088 (label_ref (match_operand 0 "" "")))]
13091 [(set_attr "type" "ibr")])
13093 (define_expand "indirect_jump"
13094 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13098 (define_insn "*indirect_jump"
13099 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13102 [(set_attr "type" "ibr")
13103 (set_attr "length_immediate" "0")])
13105 (define_insn "*indirect_jump_rtx64"
13106 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13109 [(set_attr "type" "ibr")
13110 (set_attr "length_immediate" "0")])
13112 (define_expand "tablejump"
13113 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13114 (use (label_ref (match_operand 1 "" "")))])]
13117 /* In PIC mode, the table entries are stored GOT-relative. Convert
13118 the relative address to an absolute address. */
13122 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
13123 gen_rtx_LABEL_REF (Pmode, operands[1]),
13126 else if (HAVE_AS_GOTOFF_IN_DATA)
13128 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
13129 pic_offset_table_rtx, NULL_RTX,
13131 current_function_uses_pic_offset_table = 1;
13135 operands[0] = expand_simple_binop (Pmode, MINUS, pic_offset_table_rtx,
13136 operands[0], NULL_RTX, 1,
13138 current_function_uses_pic_offset_table = 1;
13143 (define_insn "*tablejump_1"
13144 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13145 (use (label_ref (match_operand 1 "" "")))]
13148 [(set_attr "type" "ibr")
13149 (set_attr "length_immediate" "0")])
13151 (define_insn "*tablejump_1_rtx64"
13152 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13153 (use (label_ref (match_operand 1 "" "")))]
13156 [(set_attr "type" "ibr")
13157 (set_attr "length_immediate" "0")])
13159 ;; Loop instruction
13161 ;; This is all complicated by the fact that since this is a jump insn
13162 ;; we must handle our own reloads.
13164 (define_expand "doloop_end"
13165 [(use (match_operand 0 "" "")) ; loop pseudo
13166 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13167 (use (match_operand 2 "" "")) ; max iterations
13168 (use (match_operand 3 "" "")) ; loop level
13169 (use (match_operand 4 "" ""))] ; label
13170 "!TARGET_64BIT && TARGET_USE_LOOP"
13173 /* Only use cloop on innermost loops. */
13174 if (INTVAL (operands[3]) > 1)
13176 if (GET_MODE (operands[0]) != SImode)
13178 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13183 (define_insn "doloop_end_internal"
13185 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13187 (label_ref (match_operand 0 "" ""))
13189 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13190 (plus:SI (match_dup 1)
13192 (clobber (match_scratch:SI 3 "=X,X,r"))
13193 (clobber (reg:CC 17))]
13194 "!TARGET_64BIT && TARGET_USE_LOOP"
13196 if (which_alternative != 0)
13198 if (get_attr_length (insn) == 2)
13199 return "%+loop\t%l0";
13201 return "dec{l}\t%1\;%+jne\t%l0";
13203 [(set_attr "ppro_uops" "many")
13205 (if_then_else (and (eq_attr "alternative" "0")
13206 (and (ge (minus (match_dup 0) (pc))
13208 (lt (minus (match_dup 0) (pc))
13210 (const_string "ibr")
13211 (const_string "multi")))])
13215 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13217 (match_operand 0 "" "")
13220 (plus:SI (match_dup 1)
13222 (clobber (match_scratch:SI 2 ""))
13223 (clobber (reg:CC 17))]
13224 "!TARGET_64BIT && TARGET_USE_LOOP
13225 && reload_completed
13226 && REGNO (operands[1]) != 2"
13227 [(parallel [(set (reg:CCZ 17)
13228 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13230 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13231 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13238 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13240 (match_operand 0 "" "")
13242 (set (match_operand:SI 2 "nonimmediate_operand" "")
13243 (plus:SI (match_dup 1)
13245 (clobber (match_scratch:SI 3 ""))
13246 (clobber (reg:CC 17))]
13247 "!TARGET_64BIT && TARGET_USE_LOOP
13248 && reload_completed
13249 && (! REG_P (operands[2])
13250 || ! rtx_equal_p (operands[1], operands[2]))"
13251 [(set (match_dup 3) (match_dup 1))
13252 (parallel [(set (reg:CCZ 17)
13253 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13255 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13256 (set (match_dup 2) (match_dup 3))
13257 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13262 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13265 [(set (reg 17) (match_operand 0 "" ""))
13266 (set (match_operand:QI 1 "register_operand" "")
13267 (match_operator:QI 2 "ix86_comparison_operator"
13268 [(reg 17) (const_int 0)]))
13269 (set (match_operand 3 "q_regs_operand" "")
13270 (zero_extend (match_dup 1)))]
13271 "(peep2_reg_dead_p (3, operands[1])
13272 || operands_match_p (operands[1], operands[3]))
13273 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13274 [(set (match_dup 4) (match_dup 0))
13275 (set (strict_low_part (match_dup 5))
13278 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13279 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13280 ix86_expand_clear (operands[3]);
13283 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13286 [(set (reg 17) (match_operand 0 "" ""))
13287 (set (match_operand:QI 1 "register_operand" "")
13288 (match_operator:QI 2 "ix86_comparison_operator"
13289 [(reg 17) (const_int 0)]))
13290 (parallel [(set (match_operand 3 "q_regs_operand" "")
13291 (zero_extend (match_dup 1)))
13292 (clobber (reg:CC 17))])]
13293 "(peep2_reg_dead_p (3, operands[1])
13294 || operands_match_p (operands[1], operands[3]))
13295 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13296 [(set (match_dup 4) (match_dup 0))
13297 (set (strict_low_part (match_dup 5))
13300 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13301 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13302 ix86_expand_clear (operands[3]);
13305 ;; Call instructions.
13307 ;; The predicates normally associated with named expanders are not properly
13308 ;; checked for calls. This is a bug in the generic code, but it isn't that
13309 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13311 ;; Call subroutine returning no value.
13313 (define_expand "call_pop"
13314 [(parallel [(call (match_operand:QI 0 "" "")
13315 (match_operand:SI 1 "" ""))
13317 (plus:SI (reg:SI 7)
13318 (match_operand:SI 3 "" "")))])]
13321 if (operands[3] == const0_rtx)
13323 emit_insn (gen_call (operands[0], operands[1], constm1_rtx));
13326 /* Static functions and indirect calls don't need
13327 current_function_uses_pic_offset_table. */
13329 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13330 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13331 current_function_uses_pic_offset_table = 1;
13332 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13333 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13338 (define_insn "*call_pop_0"
13339 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13340 (match_operand:SI 1 "" ""))
13341 (set (reg:SI 7) (plus:SI (reg:SI 7)
13342 (match_operand:SI 2 "immediate_operand" "")))]
13345 if (SIBLING_CALL_P (insn))
13348 return "call\t%P0";
13350 [(set_attr "type" "call")])
13352 (define_insn "*call_pop_1"
13353 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13354 (match_operand:SI 1 "" ""))
13355 (set (reg:SI 7) (plus:SI (reg:SI 7)
13356 (match_operand:SI 2 "immediate_operand" "i")))]
13359 if (constant_call_address_operand (operands[0], Pmode))
13361 if (SIBLING_CALL_P (insn))
13364 return "call\t%P0";
13366 if (SIBLING_CALL_P (insn))
13369 return "call\t%A0";
13371 [(set_attr "type" "call")])
13373 (define_expand "call"
13374 [(call (match_operand:QI 0 "" "")
13375 (match_operand 1 "" ""))
13376 (use (match_operand 2 "" ""))]
13377 ;; Operand 1 not used on the i386.
13381 /* Static functions and indirect calls don't need
13382 current_function_uses_pic_offset_table. */
13384 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13385 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13386 current_function_uses_pic_offset_table = 1;
13388 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13389 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13390 if (TARGET_64BIT && INTVAL (operands[2]) >= 0)
13392 rtx reg = gen_rtx_REG (QImode, 0);
13393 emit_move_insn (reg, operands[2]);
13394 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13395 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13398 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13402 (define_expand "call_exp"
13403 [(call (match_operand:QI 0 "" "")
13404 (match_operand 1 "" ""))]
13408 (define_insn "*call_0"
13409 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13410 (match_operand 1 "" ""))]
13413 if (SIBLING_CALL_P (insn))
13416 return "call\t%P0";
13418 [(set_attr "type" "call")])
13420 (define_insn "*call_1"
13421 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13422 (match_operand 1 "" ""))]
13425 if (constant_call_address_operand (operands[0], QImode))
13427 if (SIBLING_CALL_P (insn))
13430 return "call\t%P0";
13432 if (SIBLING_CALL_P (insn))
13435 return "call\t%A0";
13437 [(set_attr "type" "call")])
13439 (define_insn "*call_1_rex64"
13440 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13441 (match_operand 1 "" ""))]
13444 if (constant_call_address_operand (operands[0], QImode))
13446 if (SIBLING_CALL_P (insn))
13449 return "call\t%P0";
13451 if (SIBLING_CALL_P (insn))
13454 return "call\t%A0";
13456 [(set_attr "type" "call")])
13458 ;; Call subroutine, returning value in operand 0
13459 ;; (which must be a hard register).
13461 (define_expand "call_value_pop"
13462 [(parallel [(set (match_operand 0 "" "")
13463 (call (match_operand:QI 1 "" "")
13464 (match_operand:SI 2 "" "")))
13466 (plus:SI (reg:SI 7)
13467 (match_operand:SI 4 "" "")))])]
13470 if (operands[4] == const0_rtx)
13472 emit_insn (gen_call_value (operands[0], operands[1], operands[2],
13476 /* Static functions and indirect calls don't need
13477 current_function_uses_pic_offset_table. */
13479 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13480 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13481 current_function_uses_pic_offset_table = 1;
13482 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13483 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13486 (define_expand "call_value"
13487 [(set (match_operand 0 "" "")
13488 (call (match_operand:QI 1 "" "")
13489 (match_operand:SI 2 "" "")))
13490 (use (match_operand:SI 3 "" ""))]
13491 ;; Operand 2 not used on the i386.
13495 /* Static functions and indirect calls don't need
13496 current_function_uses_pic_offset_table. */
13498 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13499 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13500 current_function_uses_pic_offset_table = 1;
13501 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13502 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13503 if (TARGET_64BIT && INTVAL (operands[3]) >= 0)
13505 rtx reg = gen_rtx_REG (QImode, 0);
13506 emit_move_insn (reg, operands[3]);
13507 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13509 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13512 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13517 (define_expand "call_value_exp"
13518 [(set (match_operand 0 "" "")
13519 (call (match_operand:QI 1 "" "")
13520 (match_operand:SI 2 "" "")))]
13524 ;; Call subroutine returning any type.
13526 (define_expand "untyped_call"
13527 [(parallel [(call (match_operand 0 "" "")
13529 (match_operand 1 "" "")
13530 (match_operand 2 "" "")])]
13535 /* In order to give reg-stack an easier job in validating two
13536 coprocessor registers as containing a possible return value,
13537 simply pretend the untyped call returns a complex long double
13540 emit_call_insn (TARGET_80387
13541 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13542 operands[0], const0_rtx,
13543 GEN_INT (SSE_REGPARM_MAX - 1))
13544 : gen_call (operands[0], const0_rtx,
13545 GEN_INT (SSE_REGPARM_MAX - 1)));
13547 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13549 rtx set = XVECEXP (operands[2], 0, i);
13550 emit_move_insn (SET_DEST (set), SET_SRC (set));
13553 /* The optimizer does not know that the call sets the function value
13554 registers we stored in the result block. We avoid problems by
13555 claiming that all hard registers are used and clobbered at this
13557 emit_insn (gen_blockage ());
13562 ;; Prologue and epilogue instructions
13564 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13565 ;; all of memory. This blocks insns from being moved across this point.
13567 (define_insn "blockage"
13568 [(unspec_volatile [(const_int 0)] 0)]
13571 [(set_attr "length" "0")])
13573 ;; Insn emitted into the body of a function to return from a function.
13574 ;; This is only done if the function's epilogue is known to be simple.
13575 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13577 (define_expand "return"
13579 "ix86_can_use_return_insn_p ()"
13581 if (current_function_pops_args)
13583 rtx popc = GEN_INT (current_function_pops_args);
13584 emit_jump_insn (gen_return_pop_internal (popc));
13589 (define_insn "return_internal"
13593 [(set_attr "length" "1")
13594 (set_attr "length_immediate" "0")
13595 (set_attr "modrm" "0")])
13597 (define_insn "return_pop_internal"
13599 (use (match_operand:SI 0 "const_int_operand" ""))]
13602 [(set_attr "length" "3")
13603 (set_attr "length_immediate" "2")
13604 (set_attr "modrm" "0")])
13606 (define_insn "return_indirect_internal"
13608 (use (match_operand:SI 0 "register_operand" "r"))]
13611 [(set_attr "type" "ibr")
13612 (set_attr "length_immediate" "0")])
13618 [(set_attr "length" "1")
13619 (set_attr "length_immediate" "0")
13620 (set_attr "modrm" "0")
13621 (set_attr "ppro_uops" "one")])
13623 (define_expand "prologue"
13626 "ix86_expand_prologue (); DONE;")
13628 (define_insn "prologue_set_got"
13629 [(set (match_operand:SI 0 "register_operand" "=r")
13630 (unspec_volatile:SI
13631 [(plus:SI (match_dup 0)
13632 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
13633 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
13634 (clobber (reg:CC 17))]
13637 if (GET_CODE (operands[2]) == LABEL_REF)
13638 operands[2] = XEXP (operands[2], 0);
13639 if (TARGET_DEEP_BRANCH_PREDICTION)
13640 return "add{l}\t{%1, %0|%0, %1}";
13642 return "add{l}\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}";
13644 [(set_attr "type" "alu")
13645 ; Since this insn may have two constant operands, we must set the
13647 (set_attr "length_immediate" "4")
13648 (set_attr "mode" "SI")])
13650 (define_insn "prologue_get_pc"
13651 [(set (match_operand:SI 0 "register_operand" "=r")
13652 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
13655 if (GET_CODE (operands[1]) == LABEL_REF)
13656 operands[1] = XEXP (operands[1], 0);
13657 output_asm_insn ("call\t%X1", operands);
13658 if (! TARGET_DEEP_BRANCH_PREDICTION)
13660 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
13661 CODE_LABEL_NUMBER (operands[1]));
13665 [(set_attr "type" "multi")])
13667 (define_expand "epilogue"
13670 "ix86_expand_epilogue (1); DONE;")
13672 (define_expand "sibcall_epilogue"
13675 "ix86_expand_epilogue (0); DONE;")
13677 (define_expand "eh_return"
13678 [(use (match_operand 0 "register_operand" ""))
13679 (use (match_operand 1 "register_operand" ""))]
13682 rtx tmp, sa = operands[0], ra = operands[1];
13684 /* Tricky bit: we write the address of the handler to which we will
13685 be returning into someone else's stack frame, one word below the
13686 stack address we wish to restore. */
13687 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13688 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13689 tmp = gen_rtx_MEM (Pmode, tmp);
13690 emit_move_insn (tmp, ra);
13692 if (Pmode == SImode)
13693 emit_insn (gen_eh_return_si (sa));
13695 emit_insn (gen_eh_return_di (sa));
13700 (define_insn_and_split "eh_return_si"
13701 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13)]
13706 "ix86_expand_epilogue (2); DONE;")
13708 (define_insn_and_split "eh_return_di"
13709 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13)]
13714 "ix86_expand_epilogue (2); DONE;")
13716 (define_insn "leave"
13717 [(set (reg:SI 7) (reg:SI 6))
13718 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))
13719 (clobber (mem:BLK (scratch)))]
13722 [(set_attr "length_immediate" "0")
13723 (set_attr "length" "1")
13724 (set_attr "modrm" "0")
13725 (set_attr "modrm" "0")
13726 (set_attr "athlon_decode" "vector")
13727 (set_attr "ppro_uops" "few")])
13729 (define_insn "leave_rex64"
13730 [(set (reg:DI 7) (reg:DI 6))
13731 (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7))))
13732 (clobber (mem:BLK (scratch)))]
13735 [(set_attr "length_immediate" "0")
13736 (set_attr "length" "1")
13737 (set_attr "modrm" "0")
13738 (set_attr "modrm" "0")
13739 (set_attr "athlon_decode" "vector")
13740 (set_attr "ppro_uops" "few")])
13742 (define_expand "ffssi2"
13743 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13744 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13747 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13748 rtx in = operands[1];
13752 emit_move_insn (tmp, constm1_rtx);
13753 emit_insn (gen_ffssi_1 (out, in));
13754 emit_insn (gen_rtx_SET (VOIDmode, out,
13755 gen_rtx_IF_THEN_ELSE (SImode,
13756 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13760 emit_insn (gen_addsi3 (out, out, const1_rtx));
13761 emit_move_insn (operands[0], out);
13764 /* Pentium bsf instruction is extremly slow. The following code is
13765 recommended by the Intel Optimizing Manual as a reasonable replacement:
13769 MOV DWORD PTR [TEMP+4],ECX
13772 MOV DWORD PTR [TEMP],EAX
13773 FILD QWORD PTR [TEMP]
13774 FSTP QWORD PTR [TEMP]
13775 WAIT ; WAIT only needed for compatibility with
13776 ; earlier processors
13777 MOV ECX, DWORD PTR [TEMP+4]
13780 TEST EAX,EAX ; clear zero flag
13782 Following piece of code expand ffs to similar beast.
13785 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13787 rtx label = gen_label_rtx ();
13789 rtx mem = assign_386_stack_local (DImode, 0);
13790 rtx fptmp = gen_reg_rtx (DFmode);
13791 split_di (&mem, 1, &lo, &hi);
13793 emit_move_insn (out, const0_rtx);
13795 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label);
13797 emit_move_insn (hi, out);
13798 emit_insn (gen_subsi3 (out, out, in));
13799 emit_insn (gen_andsi3 (out, out, in));
13800 emit_move_insn (lo, out);
13801 emit_insn (gen_floatdidf2 (fptmp,mem));
13802 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13803 emit_move_insn (out, hi);
13804 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13805 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13807 emit_label (label);
13808 LABEL_NUSES (label) = 1;
13810 emit_move_insn (operands[0], out);
13814 emit_move_insn (tmp, const0_rtx);
13815 emit_insn (gen_ffssi_1 (out, in));
13816 emit_insn (gen_rtx_SET (VOIDmode,
13817 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13818 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13820 emit_insn (gen_negsi2 (tmp, tmp));
13821 emit_insn (gen_iorsi3 (out, out, tmp));
13822 emit_insn (gen_addsi3 (out, out, const1_rtx));
13823 emit_move_insn (operands[0], out);
13828 (define_insn "ffssi_1"
13830 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13832 (set (match_operand:SI 0 "register_operand" "=r")
13833 (unspec:SI [(match_dup 1)] 5))]
13835 "bsf{l}\t{%1, %0|%0, %1}"
13836 [(set_attr "prefix_0f" "1")
13837 (set_attr "ppro_uops" "few")])
13839 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13840 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13842 ;; These patterns match the binary 387 instructions for addM3, subM3,
13843 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13844 ;; SFmode. The first is the normal insn, the second the same insn but
13845 ;; with one operand a conversion, and the third the same insn but with
13846 ;; the other operand a conversion. The conversion may be SFmode or
13847 ;; SImode if the target mode DFmode, but only SImode if the target mode
13850 ;; Gcc is slightly more smart about handling normal two address instructions
13851 ;; so use special patterns for add and mull.
13852 (define_insn "*fop_sf_comm"
13853 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13854 (match_operator:SF 3 "binary_fp_operator"
13855 [(match_operand:SF 1 "register_operand" "%0,0")
13856 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13857 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13858 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13859 "* return output_387_binary_op (insn, operands);"
13860 [(set (attr "type")
13861 (if_then_else (eq_attr "alternative" "1")
13862 (const_string "sse")
13863 (if_then_else (match_operand:SF 3 "mult_operator" "")
13864 (const_string "fmul")
13865 (const_string "fop"))))
13866 (set_attr "mode" "SF")])
13868 (define_insn "*fop_sf_comm_sse"
13869 [(set (match_operand:SF 0 "register_operand" "=x")
13870 (match_operator:SF 3 "binary_fp_operator"
13871 [(match_operand:SF 1 "register_operand" "%0")
13872 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13873 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13874 "* return output_387_binary_op (insn, operands);"
13875 [(set_attr "type" "sse")
13876 (set_attr "mode" "SF")])
13878 (define_insn "*fop_df_comm"
13879 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13880 (match_operator:DF 3 "binary_fp_operator"
13881 [(match_operand:DF 1 "register_operand" "%0,0")
13882 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13883 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13884 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13885 "* return output_387_binary_op (insn, operands);"
13886 [(set (attr "type")
13887 (if_then_else (eq_attr "alternative" "1")
13888 (const_string "sse")
13889 (if_then_else (match_operand:SF 3 "mult_operator" "")
13890 (const_string "fmul")
13891 (const_string "fop"))))
13892 (set_attr "mode" "DF")])
13894 (define_insn "*fop_df_comm_sse"
13895 [(set (match_operand:DF 0 "register_operand" "=Y")
13896 (match_operator:DF 3 "binary_fp_operator"
13897 [(match_operand:DF 1 "register_operand" "%0")
13898 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13900 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13901 "* return output_387_binary_op (insn, operands);"
13902 [(set_attr "type" "sse")
13903 (set_attr "mode" "DF")])
13905 (define_insn "*fop_xf_comm"
13906 [(set (match_operand:XF 0 "register_operand" "=f")
13907 (match_operator:XF 3 "binary_fp_operator"
13908 [(match_operand:XF 1 "register_operand" "%0")
13909 (match_operand:XF 2 "register_operand" "f")]))]
13910 "!TARGET_64BIT && TARGET_80387
13911 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13912 "* return output_387_binary_op (insn, operands);"
13913 [(set (attr "type")
13914 (if_then_else (match_operand:XF 3 "mult_operator" "")
13915 (const_string "fmul")
13916 (const_string "fop")))
13917 (set_attr "mode" "XF")])
13919 (define_insn "*fop_tf_comm"
13920 [(set (match_operand:TF 0 "register_operand" "=f")
13921 (match_operator:TF 3 "binary_fp_operator"
13922 [(match_operand:TF 1 "register_operand" "%0")
13923 (match_operand:TF 2 "register_operand" "f")]))]
13924 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13925 "* return output_387_binary_op (insn, operands);"
13926 [(set (attr "type")
13927 (if_then_else (match_operand:TF 3 "mult_operator" "")
13928 (const_string "fmul")
13929 (const_string "fop")))
13930 (set_attr "mode" "XF")])
13932 (define_insn "*fop_sf_1"
13933 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
13934 (match_operator:SF 3 "binary_fp_operator"
13935 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
13936 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
13937 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13938 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13939 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13940 "* return output_387_binary_op (insn, operands);"
13941 [(set (attr "type")
13942 (cond [(eq_attr "alternative" "2")
13943 (const_string "sse")
13944 (match_operand:SF 3 "mult_operator" "")
13945 (const_string "fmul")
13946 (match_operand:SF 3 "div_operator" "")
13947 (const_string "fdiv")
13949 (const_string "fop")))
13950 (set_attr "mode" "SF")])
13952 (define_insn "*fop_sf_1_sse"
13953 [(set (match_operand:SF 0 "register_operand" "=x")
13954 (match_operator:SF 3 "binary_fp_operator"
13955 [(match_operand:SF 1 "register_operand" "0")
13956 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13958 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13959 "* return output_387_binary_op (insn, operands);"
13960 [(set_attr "type" "sse")
13961 (set_attr "mode" "SF")])
13963 ;; ??? Add SSE splitters for these!
13964 (define_insn "*fop_sf_2"
13965 [(set (match_operand:SF 0 "register_operand" "=f,f")
13966 (match_operator:SF 3 "binary_fp_operator"
13967 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13968 (match_operand:SF 2 "register_operand" "0,0")]))]
13969 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13970 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13971 [(set (attr "type")
13972 (cond [(match_operand:SF 3 "mult_operator" "")
13973 (const_string "fmul")
13974 (match_operand:SF 3 "div_operator" "")
13975 (const_string "fdiv")
13977 (const_string "fop")))
13978 (set_attr "fp_int_src" "true")
13979 (set_attr "ppro_uops" "many")
13980 (set_attr "mode" "SI")])
13982 (define_insn "*fop_sf_3"
13983 [(set (match_operand:SF 0 "register_operand" "=f,f")
13984 (match_operator:SF 3 "binary_fp_operator"
13985 [(match_operand:SF 1 "register_operand" "0,0")
13986 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13987 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13988 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13989 [(set (attr "type")
13990 (cond [(match_operand:SF 3 "mult_operator" "")
13991 (const_string "fmul")
13992 (match_operand:SF 3 "div_operator" "")
13993 (const_string "fdiv")
13995 (const_string "fop")))
13996 (set_attr "fp_int_src" "true")
13997 (set_attr "ppro_uops" "many")
13998 (set_attr "mode" "SI")])
14000 (define_insn "*fop_df_1"
14001 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14002 (match_operator:DF 3 "binary_fp_operator"
14003 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14004 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14005 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
14006 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14007 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14008 "* return output_387_binary_op (insn, operands);"
14009 [(set (attr "type")
14010 (cond [(eq_attr "alternative" "2")
14011 (const_string "sse")
14012 (match_operand:DF 3 "mult_operator" "")
14013 (const_string "fmul")
14014 (match_operand:DF 3 "div_operator" "")
14015 (const_string "fdiv")
14017 (const_string "fop")))
14018 (set_attr "mode" "DF")])
14020 (define_insn "*fop_df_1_sse"
14021 [(set (match_operand:DF 0 "register_operand" "=Y")
14022 (match_operator:DF 3 "binary_fp_operator"
14023 [(match_operand:DF 1 "register_operand" "0")
14024 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14026 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14027 "* return output_387_binary_op (insn, operands);"
14028 [(set_attr "type" "sse")])
14030 ;; ??? Add SSE splitters for these!
14031 (define_insn "*fop_df_2"
14032 [(set (match_operand:DF 0 "register_operand" "=f,f")
14033 (match_operator:DF 3 "binary_fp_operator"
14034 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14035 (match_operand:DF 2 "register_operand" "0,0")]))]
14036 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
14037 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14038 [(set (attr "type")
14039 (cond [(match_operand:DF 3 "mult_operator" "")
14040 (const_string "fmul")
14041 (match_operand:DF 3 "div_operator" "")
14042 (const_string "fdiv")
14044 (const_string "fop")))
14045 (set_attr "fp_int_src" "true")
14046 (set_attr "ppro_uops" "many")
14047 (set_attr "mode" "SI")])
14049 (define_insn "*fop_df_3"
14050 [(set (match_operand:DF 0 "register_operand" "=f,f")
14051 (match_operator:DF 3 "binary_fp_operator"
14052 [(match_operand:DF 1 "register_operand" "0,0")
14053 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14054 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
14055 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14056 [(set (attr "type")
14057 (cond [(match_operand:DF 3 "mult_operator" "")
14058 (const_string "fmul")
14059 (match_operand:DF 3 "div_operator" "")
14060 (const_string "fdiv")
14062 (const_string "fop")))
14063 (set_attr "fp_int_src" "true")
14064 (set_attr "ppro_uops" "many")
14065 (set_attr "mode" "SI")])
14067 (define_insn "*fop_df_4"
14068 [(set (match_operand:DF 0 "register_operand" "=f,f")
14069 (match_operator:DF 3 "binary_fp_operator"
14070 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14071 (match_operand:DF 2 "register_operand" "0,f")]))]
14073 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14074 "* return output_387_binary_op (insn, operands);"
14075 [(set (attr "type")
14076 (cond [(match_operand:DF 3 "mult_operator" "")
14077 (const_string "fmul")
14078 (match_operand:DF 3 "div_operator" "")
14079 (const_string "fdiv")
14081 (const_string "fop")))
14082 (set_attr "mode" "SF")])
14084 (define_insn "*fop_df_5"
14085 [(set (match_operand:DF 0 "register_operand" "=f,f")
14086 (match_operator:DF 3 "binary_fp_operator"
14087 [(match_operand:DF 1 "register_operand" "0,f")
14089 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14090 "TARGET_80387 && !TARGET_SSE2"
14091 "* return output_387_binary_op (insn, operands);"
14092 [(set (attr "type")
14093 (cond [(match_operand:DF 3 "mult_operator" "")
14094 (const_string "fmul")
14095 (match_operand:DF 3 "div_operator" "")
14096 (const_string "fdiv")
14098 (const_string "fop")))
14099 (set_attr "mode" "SF")])
14101 (define_insn "*fop_xf_1"
14102 [(set (match_operand:XF 0 "register_operand" "=f,f")
14103 (match_operator:XF 3 "binary_fp_operator"
14104 [(match_operand:XF 1 "register_operand" "0,f")
14105 (match_operand:XF 2 "register_operand" "f,0")]))]
14106 "!TARGET_64BIT && TARGET_80387
14107 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14108 "* return output_387_binary_op (insn, operands);"
14109 [(set (attr "type")
14110 (cond [(match_operand:XF 3 "mult_operator" "")
14111 (const_string "fmul")
14112 (match_operand:XF 3 "div_operator" "")
14113 (const_string "fdiv")
14115 (const_string "fop")))
14116 (set_attr "mode" "XF")])
14118 (define_insn "*fop_tf_1"
14119 [(set (match_operand:TF 0 "register_operand" "=f,f")
14120 (match_operator:TF 3 "binary_fp_operator"
14121 [(match_operand:TF 1 "register_operand" "0,f")
14122 (match_operand:TF 2 "register_operand" "f,0")]))]
14124 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14125 "* return output_387_binary_op (insn, operands);"
14126 [(set (attr "type")
14127 (cond [(match_operand:TF 3 "mult_operator" "")
14128 (const_string "fmul")
14129 (match_operand:TF 3 "div_operator" "")
14130 (const_string "fdiv")
14132 (const_string "fop")))
14133 (set_attr "mode" "XF")])
14135 (define_insn "*fop_xf_2"
14136 [(set (match_operand:XF 0 "register_operand" "=f,f")
14137 (match_operator:XF 3 "binary_fp_operator"
14138 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14139 (match_operand:XF 2 "register_operand" "0,0")]))]
14140 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14141 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14142 [(set (attr "type")
14143 (cond [(match_operand:XF 3 "mult_operator" "")
14144 (const_string "fmul")
14145 (match_operand:XF 3 "div_operator" "")
14146 (const_string "fdiv")
14148 (const_string "fop")))
14149 (set_attr "fp_int_src" "true")
14150 (set_attr "mode" "SI")
14151 (set_attr "ppro_uops" "many")])
14153 (define_insn "*fop_tf_2"
14154 [(set (match_operand:TF 0 "register_operand" "=f,f")
14155 (match_operator:TF 3 "binary_fp_operator"
14156 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14157 (match_operand:TF 2 "register_operand" "0,0")]))]
14158 "TARGET_80387 && TARGET_USE_FIOP"
14159 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14160 [(set (attr "type")
14161 (cond [(match_operand:TF 3 "mult_operator" "")
14162 (const_string "fmul")
14163 (match_operand:TF 3 "div_operator" "")
14164 (const_string "fdiv")
14166 (const_string "fop")))
14167 (set_attr "fp_int_src" "true")
14168 (set_attr "mode" "SI")
14169 (set_attr "ppro_uops" "many")])
14171 (define_insn "*fop_xf_3"
14172 [(set (match_operand:XF 0 "register_operand" "=f,f")
14173 (match_operator:XF 3 "binary_fp_operator"
14174 [(match_operand:XF 1 "register_operand" "0,0")
14175 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14176 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14177 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14178 [(set (attr "type")
14179 (cond [(match_operand:XF 3 "mult_operator" "")
14180 (const_string "fmul")
14181 (match_operand:XF 3 "div_operator" "")
14182 (const_string "fdiv")
14184 (const_string "fop")))
14185 (set_attr "fp_int_src" "true")
14186 (set_attr "mode" "SI")
14187 (set_attr "ppro_uops" "many")])
14189 (define_insn "*fop_tf_3"
14190 [(set (match_operand:TF 0 "register_operand" "=f,f")
14191 (match_operator:TF 3 "binary_fp_operator"
14192 [(match_operand:TF 1 "register_operand" "0,0")
14193 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14194 "TARGET_80387 && TARGET_USE_FIOP"
14195 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14196 [(set (attr "type")
14197 (cond [(match_operand:TF 3 "mult_operator" "")
14198 (const_string "fmul")
14199 (match_operand:TF 3 "div_operator" "")
14200 (const_string "fdiv")
14202 (const_string "fop")))
14203 (set_attr "fp_int_src" "true")
14204 (set_attr "mode" "SI")
14205 (set_attr "ppro_uops" "many")])
14207 (define_insn "*fop_xf_4"
14208 [(set (match_operand:XF 0 "register_operand" "=f,f")
14209 (match_operator:XF 3 "binary_fp_operator"
14210 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14211 (match_operand:XF 2 "register_operand" "0,f")]))]
14212 "!TARGET_64BIT && TARGET_80387"
14213 "* return output_387_binary_op (insn, operands);"
14214 [(set (attr "type")
14215 (cond [(match_operand:XF 3 "mult_operator" "")
14216 (const_string "fmul")
14217 (match_operand:XF 3 "div_operator" "")
14218 (const_string "fdiv")
14220 (const_string "fop")))
14221 (set_attr "mode" "SF")])
14223 (define_insn "*fop_tf_4"
14224 [(set (match_operand:TF 0 "register_operand" "=f,f")
14225 (match_operator:TF 3 "binary_fp_operator"
14226 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14227 (match_operand:TF 2 "register_operand" "0,f")]))]
14229 "* return output_387_binary_op (insn, operands);"
14230 [(set (attr "type")
14231 (cond [(match_operand:TF 3 "mult_operator" "")
14232 (const_string "fmul")
14233 (match_operand:TF 3 "div_operator" "")
14234 (const_string "fdiv")
14236 (const_string "fop")))
14237 (set_attr "mode" "SF")])
14239 (define_insn "*fop_xf_5"
14240 [(set (match_operand:XF 0 "register_operand" "=f,f")
14241 (match_operator:XF 3 "binary_fp_operator"
14242 [(match_operand:XF 1 "register_operand" "0,f")
14244 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14245 "!TARGET_64BIT && TARGET_80387"
14246 "* return output_387_binary_op (insn, operands);"
14247 [(set (attr "type")
14248 (cond [(match_operand:XF 3 "mult_operator" "")
14249 (const_string "fmul")
14250 (match_operand:XF 3 "div_operator" "")
14251 (const_string "fdiv")
14253 (const_string "fop")))
14254 (set_attr "mode" "SF")])
14256 (define_insn "*fop_tf_5"
14257 [(set (match_operand:TF 0 "register_operand" "=f,f")
14258 (match_operator:TF 3 "binary_fp_operator"
14259 [(match_operand:TF 1 "register_operand" "0,f")
14261 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14263 "* return output_387_binary_op (insn, operands);"
14264 [(set (attr "type")
14265 (cond [(match_operand:TF 3 "mult_operator" "")
14266 (const_string "fmul")
14267 (match_operand:TF 3 "div_operator" "")
14268 (const_string "fdiv")
14270 (const_string "fop")))
14271 (set_attr "mode" "SF")])
14273 (define_insn "*fop_xf_6"
14274 [(set (match_operand:XF 0 "register_operand" "=f,f")
14275 (match_operator:XF 3 "binary_fp_operator"
14276 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14277 (match_operand:XF 2 "register_operand" "0,f")]))]
14278 "!TARGET_64BIT && TARGET_80387"
14279 "* return output_387_binary_op (insn, operands);"
14280 [(set (attr "type")
14281 (cond [(match_operand:XF 3 "mult_operator" "")
14282 (const_string "fmul")
14283 (match_operand:XF 3 "div_operator" "")
14284 (const_string "fdiv")
14286 (const_string "fop")))
14287 (set_attr "mode" "DF")])
14289 (define_insn "*fop_tf_6"
14290 [(set (match_operand:TF 0 "register_operand" "=f,f")
14291 (match_operator:TF 3 "binary_fp_operator"
14292 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14293 (match_operand:TF 2 "register_operand" "0,f")]))]
14295 "* return output_387_binary_op (insn, operands);"
14296 [(set (attr "type")
14297 (cond [(match_operand:TF 3 "mult_operator" "")
14298 (const_string "fmul")
14299 (match_operand:TF 3 "div_operator" "")
14300 (const_string "fdiv")
14302 (const_string "fop")))
14303 (set_attr "mode" "DF")])
14305 (define_insn "*fop_xf_7"
14306 [(set (match_operand:XF 0 "register_operand" "=f,f")
14307 (match_operator:XF 3 "binary_fp_operator"
14308 [(match_operand:XF 1 "register_operand" "0,f")
14310 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14311 "!TARGET_64BIT && TARGET_80387"
14312 "* return output_387_binary_op (insn, operands);"
14313 [(set (attr "type")
14314 (cond [(match_operand:XF 3 "mult_operator" "")
14315 (const_string "fmul")
14316 (match_operand:XF 3 "div_operator" "")
14317 (const_string "fdiv")
14319 (const_string "fop")))
14320 (set_attr "mode" "DF")])
14322 (define_insn "*fop_tf_7"
14323 [(set (match_operand:TF 0 "register_operand" "=f,f")
14324 (match_operator:TF 3 "binary_fp_operator"
14325 [(match_operand:TF 1 "register_operand" "0,f")
14327 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14329 "* return output_387_binary_op (insn, operands);"
14330 [(set (attr "type")
14331 (cond [(match_operand:TF 3 "mult_operator" "")
14332 (const_string "fmul")
14333 (match_operand:TF 3 "div_operator" "")
14334 (const_string "fdiv")
14336 (const_string "fop")))
14337 (set_attr "mode" "DF")])
14340 [(set (match_operand 0 "register_operand" "")
14341 (match_operator 3 "binary_fp_operator"
14342 [(float (match_operand:SI 1 "register_operand" ""))
14343 (match_operand 2 "register_operand" "")]))]
14344 "TARGET_80387 && reload_completed
14345 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14348 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14349 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14350 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14351 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14352 GET_MODE (operands[3]),
14355 ix86_free_from_memory (GET_MODE (operands[1]));
14360 [(set (match_operand 0 "register_operand" "")
14361 (match_operator 3 "binary_fp_operator"
14362 [(match_operand 1 "register_operand" "")
14363 (float (match_operand:SI 2 "register_operand" ""))]))]
14364 "TARGET_80387 && reload_completed
14365 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14368 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14369 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14370 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14371 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14372 GET_MODE (operands[3]),
14375 ix86_free_from_memory (GET_MODE (operands[2]));
14379 ;; FPU special functions.
14381 (define_expand "sqrtsf2"
14382 [(set (match_operand:SF 0 "register_operand" "")
14383 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14384 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
14387 operands[1] = force_reg (SFmode, operands[1]);
14390 (define_insn "sqrtsf2_1"
14391 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14392 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14393 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14394 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
14397 sqrtss\t{%1, %0|%0, %1}"
14398 [(set_attr "type" "fpspc,sse")
14399 (set_attr "mode" "SF,SF")
14400 (set_attr "athlon_decode" "direct,*")])
14402 (define_insn "sqrtsf2_1_sse_only"
14403 [(set (match_operand:SF 0 "register_operand" "=x")
14404 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14405 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14406 "sqrtss\t{%1, %0|%0, %1}"
14407 [(set_attr "type" "sse")
14408 (set_attr "mode" "SF")
14409 (set_attr "athlon_decode" "*")])
14411 (define_insn "sqrtsf2_i387"
14412 [(set (match_operand:SF 0 "register_operand" "=f")
14413 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14414 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14415 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
14417 [(set_attr "type" "fpspc")
14418 (set_attr "mode" "SF")
14419 (set_attr "athlon_decode" "direct")])
14421 (define_expand "sqrtdf2"
14422 [(set (match_operand:DF 0 "register_operand" "")
14423 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14424 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
14427 operands[1] = force_reg (DFmode, operands[1]);
14430 (define_insn "sqrtdf2_1"
14431 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14432 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14433 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14434 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
14437 sqrtsd\t{%1, %0|%0, %1}"
14438 [(set_attr "type" "fpspc,sse")
14439 (set_attr "mode" "DF,DF")
14440 (set_attr "athlon_decode" "direct,*")])
14442 (define_insn "sqrtdf2_1_sse_only"
14443 [(set (match_operand:DF 0 "register_operand" "=Y")
14444 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14445 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14446 "sqrtsd\t{%1, %0|%0, %1}"
14447 [(set_attr "type" "sse")
14448 (set_attr "mode" "DF")
14449 (set_attr "athlon_decode" "*")])
14451 (define_insn "sqrtdf2_i387"
14452 [(set (match_operand:DF 0 "register_operand" "=f")
14453 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14454 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14455 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
14457 [(set_attr "type" "fpspc")
14458 (set_attr "mode" "DF")
14459 (set_attr "athlon_decode" "direct")])
14461 (define_insn "*sqrtextendsfdf2"
14462 [(set (match_operand:DF 0 "register_operand" "=f")
14463 (sqrt:DF (float_extend:DF
14464 (match_operand:SF 1 "register_operand" "0"))))]
14465 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
14467 [(set_attr "type" "fpspc")
14468 (set_attr "mode" "DF")
14469 (set_attr "athlon_decode" "direct")])
14471 (define_insn "sqrtxf2"
14472 [(set (match_operand:XF 0 "register_operand" "=f")
14473 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14474 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14475 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14477 [(set_attr "type" "fpspc")
14478 (set_attr "mode" "XF")
14479 (set_attr "athlon_decode" "direct")])
14481 (define_insn "sqrttf2"
14482 [(set (match_operand:TF 0 "register_operand" "=f")
14483 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14484 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14485 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14487 [(set_attr "type" "fpspc")
14488 (set_attr "mode" "XF")
14489 (set_attr "athlon_decode" "direct")])
14491 (define_insn "*sqrtextenddfxf2"
14492 [(set (match_operand:XF 0 "register_operand" "=f")
14493 (sqrt:XF (float_extend:XF
14494 (match_operand:DF 1 "register_operand" "0"))))]
14495 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14497 [(set_attr "type" "fpspc")
14498 (set_attr "mode" "XF")
14499 (set_attr "athlon_decode" "direct")])
14501 (define_insn "*sqrtextenddftf2"
14502 [(set (match_operand:TF 0 "register_operand" "=f")
14503 (sqrt:TF (float_extend:TF
14504 (match_operand:DF 1 "register_operand" "0"))))]
14505 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14507 [(set_attr "type" "fpspc")
14508 (set_attr "mode" "XF")
14509 (set_attr "athlon_decode" "direct")])
14511 (define_insn "*sqrtextendsfxf2"
14512 [(set (match_operand:XF 0 "register_operand" "=f")
14513 (sqrt:XF (float_extend:XF
14514 (match_operand:SF 1 "register_operand" "0"))))]
14515 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
14517 [(set_attr "type" "fpspc")
14518 (set_attr "mode" "XF")
14519 (set_attr "athlon_decode" "direct")])
14521 (define_insn "*sqrtextendsftf2"
14522 [(set (match_operand:TF 0 "register_operand" "=f")
14523 (sqrt:TF (float_extend:TF
14524 (match_operand:SF 1 "register_operand" "0"))))]
14525 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14527 [(set_attr "type" "fpspc")
14528 (set_attr "mode" "XF")
14529 (set_attr "athlon_decode" "direct")])
14531 (define_insn "sindf2"
14532 [(set (match_operand:DF 0 "register_operand" "=f")
14533 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
14534 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14535 && flag_unsafe_math_optimizations"
14537 [(set_attr "type" "fpspc")
14538 (set_attr "mode" "DF")])
14540 (define_insn "sinsf2"
14541 [(set (match_operand:SF 0 "register_operand" "=f")
14542 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
14543 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14544 && flag_unsafe_math_optimizations"
14546 [(set_attr "type" "fpspc")
14547 (set_attr "mode" "SF")])
14549 (define_insn "*sinextendsfdf2"
14550 [(set (match_operand:DF 0 "register_operand" "=f")
14551 (unspec:DF [(float_extend:DF
14552 (match_operand:SF 1 "register_operand" "0"))] 1))]
14553 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14554 && flag_unsafe_math_optimizations"
14556 [(set_attr "type" "fpspc")
14557 (set_attr "mode" "DF")])
14559 (define_insn "sinxf2"
14560 [(set (match_operand:XF 0 "register_operand" "=f")
14561 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14562 "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
14563 && flag_unsafe_math_optimizations"
14565 [(set_attr "type" "fpspc")
14566 (set_attr "mode" "XF")])
14568 (define_insn "sintf2"
14569 [(set (match_operand:TF 0 "register_operand" "=f")
14570 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
14571 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14572 && flag_unsafe_math_optimizations"
14574 [(set_attr "type" "fpspc")
14575 (set_attr "mode" "XF")])
14577 (define_insn "cosdf2"
14578 [(set (match_operand:DF 0 "register_operand" "=f")
14579 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
14580 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14581 && flag_unsafe_math_optimizations"
14583 [(set_attr "type" "fpspc")
14584 (set_attr "mode" "DF")])
14586 (define_insn "cossf2"
14587 [(set (match_operand:SF 0 "register_operand" "=f")
14588 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
14589 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14590 && flag_unsafe_math_optimizations"
14592 [(set_attr "type" "fpspc")
14593 (set_attr "mode" "SF")])
14595 (define_insn "*cosextendsfdf2"
14596 [(set (match_operand:DF 0 "register_operand" "=f")
14597 (unspec:DF [(float_extend:DF
14598 (match_operand:SF 1 "register_operand" "0"))] 2))]
14599 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14600 && flag_unsafe_math_optimizations"
14602 [(set_attr "type" "fpspc")
14603 (set_attr "mode" "DF")])
14605 (define_insn "cosxf2"
14606 [(set (match_operand:XF 0 "register_operand" "=f")
14607 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
14608 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14609 && flag_unsafe_math_optimizations"
14611 [(set_attr "type" "fpspc")
14612 (set_attr "mode" "XF")])
14614 (define_insn "costf2"
14615 [(set (match_operand:TF 0 "register_operand" "=f")
14616 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
14617 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14618 && flag_unsafe_math_optimizations"
14620 [(set_attr "type" "fpspc")
14621 (set_attr "mode" "XF")])
14623 ;; Block operation instructions
14626 [(set (reg:SI 19) (const_int 0))]
14629 [(set_attr "type" "cld")])
14631 (define_expand "movstrsi"
14632 [(use (match_operand:BLK 0 "memory_operand" ""))
14633 (use (match_operand:BLK 1 "memory_operand" ""))
14634 (use (match_operand:SI 2 "nonmemory_operand" ""))
14635 (use (match_operand:SI 3 "const_int_operand" ""))]
14638 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14644 (define_expand "movstrdi"
14645 [(use (match_operand:BLK 0 "memory_operand" ""))
14646 (use (match_operand:BLK 1 "memory_operand" ""))
14647 (use (match_operand:DI 2 "nonmemory_operand" ""))
14648 (use (match_operand:DI 3 "const_int_operand" ""))]
14651 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14657 ;; Most CPUs don't like single string operations
14658 ;; Handle this case here to simplify previous expander.
14660 (define_expand "strmovdi_rex64"
14661 [(set (match_dup 2)
14662 (mem:DI (match_operand:DI 1 "register_operand" "")))
14663 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14665 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14666 (clobber (reg:CC 17))])
14667 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14668 (clobber (reg:CC 17))])]
14671 if (TARGET_SINGLE_STRINGOP || optimize_size)
14673 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14678 operands[2] = gen_reg_rtx (DImode);
14682 (define_expand "strmovsi"
14683 [(set (match_dup 2)
14684 (mem:SI (match_operand:SI 1 "register_operand" "")))
14685 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14687 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14688 (clobber (reg:CC 17))])
14689 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14690 (clobber (reg:CC 17))])]
14695 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14698 if (TARGET_SINGLE_STRINGOP || optimize_size)
14700 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14705 operands[2] = gen_reg_rtx (SImode);
14708 (define_expand "strmovsi_rex64"
14709 [(set (match_dup 2)
14710 (mem:SI (match_operand:DI 1 "register_operand" "")))
14711 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14713 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14714 (clobber (reg:CC 17))])
14715 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14716 (clobber (reg:CC 17))])]
14719 if (TARGET_SINGLE_STRINGOP || optimize_size)
14721 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14726 operands[2] = gen_reg_rtx (SImode);
14729 (define_expand "strmovhi"
14730 [(set (match_dup 2)
14731 (mem:HI (match_operand:SI 1 "register_operand" "")))
14732 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14734 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14735 (clobber (reg:CC 17))])
14736 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14737 (clobber (reg:CC 17))])]
14742 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14745 if (TARGET_SINGLE_STRINGOP || optimize_size)
14747 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14752 operands[2] = gen_reg_rtx (HImode);
14755 (define_expand "strmovhi_rex64"
14756 [(set (match_dup 2)
14757 (mem:HI (match_operand:DI 1 "register_operand" "")))
14758 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14760 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14761 (clobber (reg:CC 17))])
14762 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14763 (clobber (reg:CC 17))])]
14766 if (TARGET_SINGLE_STRINGOP || optimize_size)
14768 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14773 operands[2] = gen_reg_rtx (HImode);
14776 (define_expand "strmovqi"
14777 [(set (match_dup 2)
14778 (mem:QI (match_operand:SI 1 "register_operand" "")))
14779 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14781 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14782 (clobber (reg:CC 17))])
14783 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14784 (clobber (reg:CC 17))])]
14789 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14792 if (TARGET_SINGLE_STRINGOP || optimize_size)
14794 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14799 operands[2] = gen_reg_rtx (QImode);
14802 (define_expand "strmovqi_rex64"
14803 [(set (match_dup 2)
14804 (mem:QI (match_operand:DI 1 "register_operand" "")))
14805 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14807 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14808 (clobber (reg:CC 17))])
14809 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14810 (clobber (reg:CC 17))])]
14813 if (TARGET_SINGLE_STRINGOP || optimize_size)
14815 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14820 operands[2] = gen_reg_rtx (QImode);
14823 (define_insn "strmovdi_rex_1"
14824 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14825 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14826 (set (match_operand:DI 0 "register_operand" "=D")
14827 (plus:DI (match_dup 2)
14829 (set (match_operand:DI 1 "register_operand" "=S")
14830 (plus:DI (match_dup 3)
14833 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14835 [(set_attr "type" "str")
14836 (set_attr "mode" "DI")
14837 (set_attr "memory" "both")])
14839 (define_insn "strmovsi_1"
14840 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14841 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14842 (set (match_operand:SI 0 "register_operand" "=D")
14843 (plus:SI (match_dup 2)
14845 (set (match_operand:SI 1 "register_operand" "=S")
14846 (plus:SI (match_dup 3)
14849 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14851 [(set_attr "type" "str")
14852 (set_attr "mode" "SI")
14853 (set_attr "memory" "both")])
14855 (define_insn "strmovsi_rex_1"
14856 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
14857 (mem:SI (match_operand:DI 3 "register_operand" "1")))
14858 (set (match_operand:DI 0 "register_operand" "=D")
14859 (plus:DI (match_dup 2)
14861 (set (match_operand:DI 1 "register_operand" "=S")
14862 (plus:DI (match_dup 3)
14865 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14867 [(set_attr "type" "str")
14868 (set_attr "mode" "SI")
14869 (set_attr "memory" "both")])
14871 (define_insn "strmovhi_1"
14872 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
14873 (mem:HI (match_operand:SI 3 "register_operand" "1")))
14874 (set (match_operand:SI 0 "register_operand" "=D")
14875 (plus:SI (match_dup 2)
14877 (set (match_operand:SI 1 "register_operand" "=S")
14878 (plus:SI (match_dup 3)
14881 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14883 [(set_attr "type" "str")
14884 (set_attr "memory" "both")
14885 (set_attr "mode" "HI")])
14887 (define_insn "strmovhi_rex_1"
14888 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
14889 (mem:HI (match_operand:DI 3 "register_operand" "1")))
14890 (set (match_operand:DI 0 "register_operand" "=D")
14891 (plus:DI (match_dup 2)
14893 (set (match_operand:DI 1 "register_operand" "=S")
14894 (plus:DI (match_dup 3)
14897 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14899 [(set_attr "type" "str")
14900 (set_attr "memory" "both")
14901 (set_attr "mode" "HI")])
14903 (define_insn "strmovqi_1"
14904 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
14905 (mem:QI (match_operand:SI 3 "register_operand" "1")))
14906 (set (match_operand:SI 0 "register_operand" "=D")
14907 (plus:SI (match_dup 2)
14909 (set (match_operand:SI 1 "register_operand" "=S")
14910 (plus:SI (match_dup 3)
14913 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14915 [(set_attr "type" "str")
14916 (set_attr "memory" "both")
14917 (set_attr "mode" "QI")])
14919 (define_insn "strmovqi_rex_1"
14920 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
14921 (mem:QI (match_operand:DI 3 "register_operand" "1")))
14922 (set (match_operand:DI 0 "register_operand" "=D")
14923 (plus:DI (match_dup 2)
14925 (set (match_operand:DI 1 "register_operand" "=S")
14926 (plus:DI (match_dup 3)
14929 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14931 [(set_attr "type" "str")
14932 (set_attr "memory" "both")
14933 (set_attr "mode" "QI")])
14935 (define_insn "rep_movdi_rex64"
14936 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14937 (set (match_operand:DI 0 "register_operand" "=D")
14938 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14940 (match_operand:DI 3 "register_operand" "0")))
14941 (set (match_operand:DI 1 "register_operand" "=S")
14942 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
14943 (match_operand:DI 4 "register_operand" "1")))
14944 (set (mem:BLK (match_dup 3))
14945 (mem:BLK (match_dup 4)))
14946 (use (match_dup 5))
14949 "{rep\;movsq|rep movsq}"
14950 [(set_attr "type" "str")
14951 (set_attr "prefix_rep" "1")
14952 (set_attr "memory" "both")
14953 (set_attr "mode" "DI")])
14955 (define_insn "rep_movsi"
14956 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14957 (set (match_operand:SI 0 "register_operand" "=D")
14958 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
14960 (match_operand:SI 3 "register_operand" "0")))
14961 (set (match_operand:SI 1 "register_operand" "=S")
14962 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
14963 (match_operand:SI 4 "register_operand" "1")))
14964 (set (mem:BLK (match_dup 3))
14965 (mem:BLK (match_dup 4)))
14966 (use (match_dup 5))
14969 "{rep\;movsl|rep movsd}"
14970 [(set_attr "type" "str")
14971 (set_attr "prefix_rep" "1")
14972 (set_attr "memory" "both")
14973 (set_attr "mode" "SI")])
14975 (define_insn "rep_movsi_rex64"
14976 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14977 (set (match_operand:DI 0 "register_operand" "=D")
14978 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14980 (match_operand:DI 3 "register_operand" "0")))
14981 (set (match_operand:DI 1 "register_operand" "=S")
14982 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
14983 (match_operand:DI 4 "register_operand" "1")))
14984 (set (mem:BLK (match_dup 3))
14985 (mem:BLK (match_dup 4)))
14986 (use (match_dup 5))
14989 "{rep\;movsl|rep movsd}"
14990 [(set_attr "type" "str")
14991 (set_attr "prefix_rep" "1")
14992 (set_attr "memory" "both")
14993 (set_attr "mode" "SI")])
14995 (define_insn "rep_movqi"
14996 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14997 (set (match_operand:SI 0 "register_operand" "=D")
14998 (plus:SI (match_operand:SI 3 "register_operand" "0")
14999 (match_operand:SI 5 "register_operand" "2")))
15000 (set (match_operand:SI 1 "register_operand" "=S")
15001 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
15002 (set (mem:BLK (match_dup 3))
15003 (mem:BLK (match_dup 4)))
15004 (use (match_dup 5))
15007 "{rep\;movsb|rep movsb}"
15008 [(set_attr "type" "str")
15009 (set_attr "prefix_rep" "1")
15010 (set_attr "memory" "both")
15011 (set_attr "mode" "SI")])
15013 (define_insn "rep_movqi_rex64"
15014 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15015 (set (match_operand:DI 0 "register_operand" "=D")
15016 (plus:DI (match_operand:DI 3 "register_operand" "0")
15017 (match_operand:DI 5 "register_operand" "2")))
15018 (set (match_operand:DI 1 "register_operand" "=S")
15019 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
15020 (set (mem:BLK (match_dup 3))
15021 (mem:BLK (match_dup 4)))
15022 (use (match_dup 5))
15025 "{rep\;movsb|rep movsb}"
15026 [(set_attr "type" "str")
15027 (set_attr "prefix_rep" "1")
15028 (set_attr "memory" "both")
15029 (set_attr "mode" "SI")])
15031 (define_expand "clrstrsi"
15032 [(use (match_operand:BLK 0 "memory_operand" ""))
15033 (use (match_operand:SI 1 "nonmemory_operand" ""))
15034 (use (match_operand 2 "const_int_operand" ""))]
15037 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15043 (define_expand "clrstrdi"
15044 [(use (match_operand:BLK 0 "memory_operand" ""))
15045 (use (match_operand:DI 1 "nonmemory_operand" ""))
15046 (use (match_operand 2 "const_int_operand" ""))]
15049 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15055 ;; Most CPUs don't like single string operations
15056 ;; Handle this case here to simplify previous expander.
15058 (define_expand "strsetdi_rex64"
15059 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
15060 (match_operand:DI 1 "register_operand" ""))
15061 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15062 (clobber (reg:CC 17))])]
15065 if (TARGET_SINGLE_STRINGOP || optimize_size)
15067 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
15072 (define_expand "strsetsi"
15073 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
15074 (match_operand:SI 1 "register_operand" ""))
15075 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15076 (clobber (reg:CC 17))])]
15081 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
15084 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15086 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
15091 (define_expand "strsetsi_rex64"
15092 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
15093 (match_operand:SI 1 "register_operand" ""))
15094 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15095 (clobber (reg:CC 17))])]
15098 if (TARGET_SINGLE_STRINGOP || optimize_size)
15100 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
15105 (define_expand "strsethi"
15106 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
15107 (match_operand:HI 1 "register_operand" ""))
15108 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15109 (clobber (reg:CC 17))])]
15114 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
15117 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15119 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
15124 (define_expand "strsethi_rex64"
15125 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
15126 (match_operand:HI 1 "register_operand" ""))
15127 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15128 (clobber (reg:CC 17))])]
15131 if (TARGET_SINGLE_STRINGOP || optimize_size)
15133 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
15138 (define_expand "strsetqi"
15139 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
15140 (match_operand:QI 1 "register_operand" ""))
15141 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15142 (clobber (reg:CC 17))])]
15147 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15150 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15152 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15157 (define_expand "strsetqi_rex64"
15158 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15159 (match_operand:QI 1 "register_operand" ""))
15160 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15161 (clobber (reg:CC 17))])]
15164 if (TARGET_SINGLE_STRINGOP || optimize_size)
15166 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15171 (define_insn "strsetdi_rex_1"
15172 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15173 (match_operand:SI 2 "register_operand" "a"))
15174 (set (match_operand:DI 0 "register_operand" "=D")
15175 (plus:DI (match_dup 1)
15178 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15180 [(set_attr "type" "str")
15181 (set_attr "memory" "store")
15182 (set_attr "mode" "DI")])
15184 (define_insn "strsetsi_1"
15185 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15186 (match_operand:SI 2 "register_operand" "a"))
15187 (set (match_operand:SI 0 "register_operand" "=D")
15188 (plus:SI (match_dup 1)
15191 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15193 [(set_attr "type" "str")
15194 (set_attr "memory" "store")
15195 (set_attr "mode" "SI")])
15197 (define_insn "strsetsi_rex_1"
15198 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15199 (match_operand:SI 2 "register_operand" "a"))
15200 (set (match_operand:DI 0 "register_operand" "=D")
15201 (plus:DI (match_dup 1)
15204 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15206 [(set_attr "type" "str")
15207 (set_attr "memory" "store")
15208 (set_attr "mode" "SI")])
15210 (define_insn "strsethi_1"
15211 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15212 (match_operand:HI 2 "register_operand" "a"))
15213 (set (match_operand:SI 0 "register_operand" "=D")
15214 (plus:SI (match_dup 1)
15217 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15219 [(set_attr "type" "str")
15220 (set_attr "memory" "store")
15221 (set_attr "mode" "HI")])
15223 (define_insn "strsethi_rex_1"
15224 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15225 (match_operand:HI 2 "register_operand" "a"))
15226 (set (match_operand:DI 0 "register_operand" "=D")
15227 (plus:DI (match_dup 1)
15230 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15232 [(set_attr "type" "str")
15233 (set_attr "memory" "store")
15234 (set_attr "mode" "HI")])
15236 (define_insn "strsetqi_1"
15237 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15238 (match_operand:QI 2 "register_operand" "a"))
15239 (set (match_operand:SI 0 "register_operand" "=D")
15240 (plus:SI (match_dup 1)
15243 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15245 [(set_attr "type" "str")
15246 (set_attr "memory" "store")
15247 (set_attr "mode" "QI")])
15249 (define_insn "strsetqi_rex_1"
15250 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15251 (match_operand:QI 2 "register_operand" "a"))
15252 (set (match_operand:DI 0 "register_operand" "=D")
15253 (plus:DI (match_dup 1)
15256 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15258 [(set_attr "type" "str")
15259 (set_attr "memory" "store")
15260 (set_attr "mode" "QI")])
15262 (define_insn "rep_stosdi_rex64"
15263 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15264 (set (match_operand:DI 0 "register_operand" "=D")
15265 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15267 (match_operand:DI 3 "register_operand" "0")))
15268 (set (mem:BLK (match_dup 3))
15270 (use (match_operand:DI 2 "register_operand" "a"))
15271 (use (match_dup 4))
15274 "{rep\;stosq|rep stosq}"
15275 [(set_attr "type" "str")
15276 (set_attr "prefix_rep" "1")
15277 (set_attr "memory" "store")
15278 (set_attr "mode" "DI")])
15280 (define_insn "rep_stossi"
15281 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15282 (set (match_operand:SI 0 "register_operand" "=D")
15283 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15285 (match_operand:SI 3 "register_operand" "0")))
15286 (set (mem:BLK (match_dup 3))
15288 (use (match_operand:SI 2 "register_operand" "a"))
15289 (use (match_dup 4))
15292 "{rep\;stosl|rep stosd}"
15293 [(set_attr "type" "str")
15294 (set_attr "prefix_rep" "1")
15295 (set_attr "memory" "store")
15296 (set_attr "mode" "SI")])
15298 (define_insn "rep_stossi_rex64"
15299 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15300 (set (match_operand:DI 0 "register_operand" "=D")
15301 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15303 (match_operand:DI 3 "register_operand" "0")))
15304 (set (mem:BLK (match_dup 3))
15306 (use (match_operand:SI 2 "register_operand" "a"))
15307 (use (match_dup 4))
15310 "{rep\;stosl|rep stosd}"
15311 [(set_attr "type" "str")
15312 (set_attr "prefix_rep" "1")
15313 (set_attr "memory" "store")
15314 (set_attr "mode" "SI")])
15316 (define_insn "rep_stosqi"
15317 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15318 (set (match_operand:SI 0 "register_operand" "=D")
15319 (plus:SI (match_operand:SI 3 "register_operand" "0")
15320 (match_operand:SI 4 "register_operand" "1")))
15321 (set (mem:BLK (match_dup 3))
15323 (use (match_operand:QI 2 "register_operand" "a"))
15324 (use (match_dup 4))
15327 "{rep\;stosb|rep stosb}"
15328 [(set_attr "type" "str")
15329 (set_attr "prefix_rep" "1")
15330 (set_attr "memory" "store")
15331 (set_attr "mode" "QI")])
15333 (define_insn "rep_stosqi_rex64"
15334 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15335 (set (match_operand:DI 0 "register_operand" "=D")
15336 (plus:DI (match_operand:DI 3 "register_operand" "0")
15337 (match_operand:DI 4 "register_operand" "1")))
15338 (set (mem:BLK (match_dup 3))
15340 (use (match_operand:QI 2 "register_operand" "a"))
15341 (use (match_dup 4))
15344 "{rep\;stosb|rep stosb}"
15345 [(set_attr "type" "str")
15346 (set_attr "prefix_rep" "1")
15347 (set_attr "memory" "store")
15348 (set_attr "mode" "QI")])
15350 (define_expand "cmpstrsi"
15351 [(set (match_operand:SI 0 "register_operand" "")
15352 (compare:SI (match_operand:BLK 1 "general_operand" "")
15353 (match_operand:BLK 2 "general_operand" "")))
15354 (use (match_operand 3 "general_operand" ""))
15355 (use (match_operand 4 "immediate_operand" ""))]
15358 rtx addr1, addr2, out, outlow, count, countreg, align;
15361 if (GET_CODE (out) != REG)
15362 out = gen_reg_rtx (SImode);
15364 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15365 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15367 count = operands[3];
15368 countreg = ix86_zero_extend_to_Pmode (count);
15370 /* %%% Iff we are testing strict equality, we can use known alignment
15371 to good advantage. This may be possible with combine, particularly
15372 once cc0 is dead. */
15373 align = operands[4];
15375 emit_insn (gen_cld ());
15376 if (GET_CODE (count) == CONST_INT)
15378 if (INTVAL (count) == 0)
15380 emit_move_insn (operands[0], const0_rtx);
15384 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15385 addr1, addr2, countreg));
15387 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15388 addr1, addr2, countreg));
15394 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15395 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15396 addr1, addr2, countreg));
15400 emit_insn (gen_cmpsi_1 (countreg, countreg));
15401 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15402 addr1, addr2, countreg));
15406 outlow = gen_lowpart (QImode, out);
15407 emit_insn (gen_cmpintqi (outlow));
15408 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15410 if (operands[0] != out)
15411 emit_move_insn (operands[0], out);
15416 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15418 (define_expand "cmpintqi"
15419 [(set (match_dup 1)
15420 (gtu:QI (reg:CC 17) (const_int 0)))
15422 (ltu:QI (reg:CC 17) (const_int 0)))
15423 (parallel [(set (match_operand:QI 0 "register_operand" "")
15424 (minus:QI (match_dup 1)
15426 (clobber (reg:CC 17))])]
15428 "operands[1] = gen_reg_rtx (QImode);
15429 operands[2] = gen_reg_rtx (QImode);")
15431 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15432 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15434 (define_insn "cmpstrqi_nz_1"
15436 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15437 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15438 (use (match_operand:SI 6 "register_operand" "2"))
15439 (use (match_operand:SI 3 "immediate_operand" "i"))
15441 (clobber (match_operand:SI 0 "register_operand" "=S"))
15442 (clobber (match_operand:SI 1 "register_operand" "=D"))
15443 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15446 [(set_attr "type" "str")
15447 (set_attr "mode" "QI")
15448 (set_attr "prefix_rep" "1")])
15450 (define_insn "cmpstrqi_nz_rex_1"
15452 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15453 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15454 (use (match_operand:DI 6 "register_operand" "2"))
15455 (use (match_operand:SI 3 "immediate_operand" "i"))
15457 (clobber (match_operand:DI 0 "register_operand" "=S"))
15458 (clobber (match_operand:DI 1 "register_operand" "=D"))
15459 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15462 [(set_attr "type" "str")
15463 (set_attr "mode" "QI")
15464 (set_attr "prefix_rep" "1")])
15466 ;; The same, but the count is not known to not be zero.
15468 (define_insn "cmpstrqi_1"
15470 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15472 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15473 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15475 (use (match_operand:SI 3 "immediate_operand" "i"))
15478 (clobber (match_operand:SI 0 "register_operand" "=S"))
15479 (clobber (match_operand:SI 1 "register_operand" "=D"))
15480 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15483 [(set_attr "type" "str")
15484 (set_attr "mode" "QI")
15485 (set_attr "prefix_rep" "1")])
15487 (define_insn "cmpstrqi_rex_1"
15489 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15491 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15492 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15494 (use (match_operand:SI 3 "immediate_operand" "i"))
15497 (clobber (match_operand:DI 0 "register_operand" "=S"))
15498 (clobber (match_operand:DI 1 "register_operand" "=D"))
15499 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15502 [(set_attr "type" "str")
15503 (set_attr "mode" "QI")
15504 (set_attr "prefix_rep" "1")])
15506 (define_expand "strlensi"
15507 [(set (match_operand:SI 0 "register_operand" "")
15508 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15509 (match_operand:QI 2 "immediate_operand" "")
15510 (match_operand 3 "immediate_operand" "")] 0))]
15513 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15519 (define_expand "strlendi"
15520 [(set (match_operand:DI 0 "register_operand" "")
15521 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15522 (match_operand:QI 2 "immediate_operand" "")
15523 (match_operand 3 "immediate_operand" "")] 0))]
15526 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15532 (define_insn "strlenqi_1"
15533 [(set (match_operand:SI 0 "register_operand" "=&c")
15534 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15535 (match_operand:QI 2 "register_operand" "a")
15536 (match_operand:SI 3 "immediate_operand" "i")
15537 (match_operand:SI 4 "register_operand" "0")] 0))
15539 (clobber (match_operand:SI 1 "register_operand" "=D"))
15540 (clobber (reg:CC 17))]
15543 [(set_attr "type" "str")
15544 (set_attr "mode" "QI")
15545 (set_attr "prefix_rep" "1")])
15547 (define_insn "strlenqi_rex_1"
15548 [(set (match_operand:DI 0 "register_operand" "=&c")
15549 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15550 (match_operand:QI 2 "register_operand" "a")
15551 (match_operand:DI 3 "immediate_operand" "i")
15552 (match_operand:DI 4 "register_operand" "0")] 0))
15554 (clobber (match_operand:DI 1 "register_operand" "=D"))
15555 (clobber (reg:CC 17))]
15558 [(set_attr "type" "str")
15559 (set_attr "mode" "QI")
15560 (set_attr "prefix_rep" "1")])
15562 ;; Peephole optimizations to clean up after cmpstr*. This should be
15563 ;; handled in combine, but it is not currently up to the task.
15564 ;; When used for their truth value, the cmpstr* expanders generate
15573 ;; The intermediate three instructions are unnecessary.
15575 ;; This one handles cmpstr*_nz_1...
15579 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15580 (mem:BLK (match_operand 5 "register_operand" ""))))
15581 (use (match_operand 6 "register_operand" ""))
15582 (use (match_operand:SI 3 "immediate_operand" ""))
15584 (clobber (match_operand 0 "register_operand" ""))
15585 (clobber (match_operand 1 "register_operand" ""))
15586 (clobber (match_operand 2 "register_operand" ""))])
15587 (set (match_operand:QI 7 "register_operand" "")
15588 (gtu:QI (reg:CC 17) (const_int 0)))
15589 (set (match_operand:QI 8 "register_operand" "")
15590 (ltu:QI (reg:CC 17) (const_int 0)))
15592 (compare (match_dup 7) (match_dup 8)))
15594 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15597 (compare:CC (mem:BLK (match_dup 4))
15598 (mem:BLK (match_dup 5))))
15599 (use (match_dup 6))
15600 (use (match_dup 3))
15602 (clobber (match_dup 0))
15603 (clobber (match_dup 1))
15604 (clobber (match_dup 2))])]
15607 ;; ...and this one handles cmpstr*_1.
15611 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
15613 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15614 (mem:BLK (match_operand 5 "register_operand" "")))
15616 (use (match_operand:SI 3 "immediate_operand" ""))
15619 (clobber (match_operand 0 "register_operand" ""))
15620 (clobber (match_operand 1 "register_operand" ""))
15621 (clobber (match_operand 2 "register_operand" ""))])
15622 (set (match_operand:QI 7 "register_operand" "")
15623 (gtu:QI (reg:CC 17) (const_int 0)))
15624 (set (match_operand:QI 8 "register_operand" "")
15625 (ltu:QI (reg:CC 17) (const_int 0)))
15627 (compare (match_dup 7) (match_dup 8)))
15629 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15632 (if_then_else:CC (ne (match_dup 6)
15634 (compare:CC (mem:BLK (match_dup 4))
15635 (mem:BLK (match_dup 5)))
15637 (use (match_dup 3))
15640 (clobber (match_dup 0))
15641 (clobber (match_dup 1))
15642 (clobber (match_dup 2))])]
15647 ;; Conditional move instructions.
15649 (define_expand "movdicc"
15650 [(set (match_operand:DI 0 "register_operand" "")
15651 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15652 (match_operand:DI 2 "general_operand" "")
15653 (match_operand:DI 3 "general_operand" "")))]
15655 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15657 (define_insn "x86_movdicc_0_m1_rex64"
15658 [(set (match_operand:DI 0 "register_operand" "=r")
15659 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15662 (clobber (reg:CC 17))]
15665 ; Since we don't have the proper number of operands for an alu insn,
15666 ; fill in all the blanks.
15667 [(set_attr "type" "alu")
15668 (set_attr "memory" "none")
15669 (set_attr "imm_disp" "false")
15670 (set_attr "mode" "DI")
15671 (set_attr "length_immediate" "0")])
15673 (define_insn "*movdicc_c_rex64"
15674 [(set (match_operand:DI 0 "register_operand" "=r,r")
15675 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15676 [(reg 17) (const_int 0)])
15677 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15678 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15679 "TARGET_64BIT && TARGET_CMOVE
15680 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15682 cmov%C1\t{%2, %0|%0, %2}
15683 cmov%c1\t{%3, %0|%0, %3}"
15684 [(set_attr "type" "icmov")
15685 (set_attr "mode" "DI")])
15687 (define_expand "movsicc"
15688 [(set (match_operand:SI 0 "register_operand" "")
15689 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15690 (match_operand:SI 2 "general_operand" "")
15691 (match_operand:SI 3 "general_operand" "")))]
15693 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15695 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15696 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15697 ;; So just document what we're doing explicitly.
15699 (define_insn "x86_movsicc_0_m1"
15700 [(set (match_operand:SI 0 "register_operand" "=r")
15701 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15704 (clobber (reg:CC 17))]
15707 ; Since we don't have the proper number of operands for an alu insn,
15708 ; fill in all the blanks.
15709 [(set_attr "type" "alu")
15710 (set_attr "memory" "none")
15711 (set_attr "imm_disp" "false")
15712 (set_attr "mode" "SI")
15713 (set_attr "length_immediate" "0")])
15715 (define_insn "*movsicc_noc"
15716 [(set (match_operand:SI 0 "register_operand" "=r,r")
15717 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15718 [(reg 17) (const_int 0)])
15719 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15720 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15722 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15724 cmov%C1\t{%2, %0|%0, %2}
15725 cmov%c1\t{%3, %0|%0, %3}"
15726 [(set_attr "type" "icmov")
15727 (set_attr "mode" "SI")])
15729 (define_expand "movhicc"
15730 [(set (match_operand:HI 0 "register_operand" "")
15731 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15732 (match_operand:HI 2 "nonimmediate_operand" "")
15733 (match_operand:HI 3 "nonimmediate_operand" "")))]
15734 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15735 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15737 (define_insn "*movhicc_noc"
15738 [(set (match_operand:HI 0 "register_operand" "=r,r")
15739 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15740 [(reg 17) (const_int 0)])
15741 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15742 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15744 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15746 cmov%C1\t{%2, %0|%0, %2}
15747 cmov%c1\t{%3, %0|%0, %3}"
15748 [(set_attr "type" "icmov")
15749 (set_attr "mode" "HI")])
15751 (define_expand "movsfcc"
15752 [(set (match_operand:SF 0 "register_operand" "")
15753 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15754 (match_operand:SF 2 "register_operand" "")
15755 (match_operand:SF 3 "register_operand" "")))]
15757 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15759 (define_insn "*movsfcc_1"
15760 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15761 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15762 [(reg 17) (const_int 0)])
15763 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15764 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15766 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15768 fcmov%F1\t{%2, %0|%0, %2}
15769 fcmov%f1\t{%3, %0|%0, %3}
15770 cmov%C1\t{%2, %0|%0, %2}
15771 cmov%c1\t{%3, %0|%0, %3}"
15772 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15773 (set_attr "mode" "SF,SF,SI,SI")])
15775 (define_expand "movdfcc"
15776 [(set (match_operand:DF 0 "register_operand" "")
15777 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15778 (match_operand:DF 2 "register_operand" "")
15779 (match_operand:DF 3 "register_operand" "")))]
15781 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15783 (define_insn "*movdfcc_1"
15784 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15785 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15786 [(reg 17) (const_int 0)])
15787 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15788 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15789 "!TARGET_64BIT && TARGET_CMOVE
15790 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15792 fcmov%F1\t{%2, %0|%0, %2}
15793 fcmov%f1\t{%3, %0|%0, %3}
15796 [(set_attr "type" "fcmov,fcmov,multi,multi")
15797 (set_attr "mode" "DF")])
15799 (define_insn "*movdfcc_1_rex64"
15800 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15801 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15802 [(reg 17) (const_int 0)])
15803 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15804 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15805 "TARGET_64BIT && TARGET_CMOVE
15806 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15808 fcmov%F1\t{%2, %0|%0, %2}
15809 fcmov%f1\t{%3, %0|%0, %3}
15810 cmov%C1\t{%2, %0|%0, %2}
15811 cmov%c1\t{%3, %0|%0, %3}"
15812 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15813 (set_attr "mode" "DF")])
15816 [(set (match_operand:DF 0 "register_operand" "")
15817 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15818 [(match_operand 4 "" "") (const_int 0)])
15819 (match_operand:DF 2 "nonimmediate_operand" "")
15820 (match_operand:DF 3 "nonimmediate_operand" "")))]
15821 "!TARGET_64BIT && !ANY_FP_REG_P (operands[0]) && reload_completed"
15822 [(set (match_dup 2)
15823 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15827 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15830 "split_di (operands+2, 1, operands+5, operands+6);
15831 split_di (operands+3, 1, operands+7, operands+8);
15832 split_di (operands, 1, operands+2, operands+3);")
15834 (define_expand "movxfcc"
15835 [(set (match_operand:XF 0 "register_operand" "")
15836 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15837 (match_operand:XF 2 "register_operand" "")
15838 (match_operand:XF 3 "register_operand" "")))]
15839 "!TARGET_64BIT && TARGET_CMOVE"
15840 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15842 (define_expand "movtfcc"
15843 [(set (match_operand:TF 0 "register_operand" "")
15844 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15845 (match_operand:TF 2 "register_operand" "")
15846 (match_operand:TF 3 "register_operand" "")))]
15848 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15850 (define_insn "*movxfcc_1"
15851 [(set (match_operand:XF 0 "register_operand" "=f,f")
15852 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
15853 [(reg 17) (const_int 0)])
15854 (match_operand:XF 2 "register_operand" "f,0")
15855 (match_operand:XF 3 "register_operand" "0,f")))]
15856 "!TARGET_64BIT && TARGET_CMOVE"
15858 fcmov%F1\t{%2, %0|%0, %2}
15859 fcmov%f1\t{%3, %0|%0, %3}"
15860 [(set_attr "type" "fcmov")
15861 (set_attr "mode" "XF")])
15863 (define_insn "*movtfcc_1"
15864 [(set (match_operand:TF 0 "register_operand" "=f,f")
15865 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
15866 [(reg 17) (const_int 0)])
15867 (match_operand:TF 2 "register_operand" "f,0")
15868 (match_operand:TF 3 "register_operand" "0,f")))]
15871 fcmov%F1\t{%2, %0|%0, %2}
15872 fcmov%f1\t{%3, %0|%0, %3}"
15873 [(set_attr "type" "fcmov")
15874 (set_attr "mode" "XF")])
15876 (define_expand "minsf3"
15878 (set (match_operand:SF 0 "register_operand" "")
15879 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15880 (match_operand:SF 2 "nonimmediate_operand" ""))
15883 (clobber (reg:CC 17))])]
15887 (define_insn "*minsf"
15888 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15889 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
15890 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15893 (clobber (reg:CC 17))]
15894 "TARGET_SSE && TARGET_IEEE_FP"
15897 (define_insn "*minsf_nonieee"
15898 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15899 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15900 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15903 (clobber (reg:CC 17))]
15904 "TARGET_SSE && !TARGET_IEEE_FP"
15908 [(set (match_operand:SF 0 "register_operand" "")
15909 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15910 (match_operand:SF 2 "nonimmediate_operand" ""))
15911 (match_operand:SF 3 "register_operand" "")
15912 (match_operand:SF 4 "nonimmediate_operand" "")))
15913 (clobber (reg:CC 17))]
15914 "SSE_REG_P (operands[0]) && reload_completed
15915 && ((operands_match_p (operands[1], operands[3])
15916 && operands_match_p (operands[2], operands[4]))
15917 || (operands_match_p (operands[1], operands[4])
15918 && operands_match_p (operands[2], operands[3])))"
15919 [(set (match_dup 0)
15920 (if_then_else:SF (lt (match_dup 1)
15925 ;; We can't represent the LT test directly. Do this by swapping the operands.
15928 [(set (match_operand:SF 0 "register_operand" "")
15929 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15930 (match_operand:SF 2 "register_operand" ""))
15931 (match_operand:DF 3 "register_operand" "")
15932 (match_operand:DF 4 "register_operand" "")))
15933 (clobber (reg:CC 17))]
15934 "FP_REG_P (operands[0]) && reload_completed
15935 && ((operands_match_p (operands[1], operands[3])
15936 && operands_match_p (operands[2], operands[4]))
15937 || (operands_match_p (operands[1], operands[4])
15938 && operands_match_p (operands[2], operands[3])))"
15939 [(set (reg:CCFP 17)
15940 (compare:CCFP (match_dup 2)
15943 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
15947 (define_insn "*minsf_sse"
15948 [(set (match_operand:SF 0 "register_operand" "=x")
15949 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
15950 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15953 "TARGET_SSE && reload_completed"
15954 "minss\t{%2, %0|%0, %2}"
15955 [(set_attr "type" "sse")
15956 (set_attr "mode" "SF")])
15958 (define_expand "mindf3"
15960 (set (match_operand:DF 0 "register_operand" "")
15961 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15962 (match_operand:DF 2 "nonimmediate_operand" ""))
15965 (clobber (reg:CC 17))])]
15969 (define_insn "*mindf"
15970 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15971 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15972 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15975 (clobber (reg:CC 17))]
15976 "TARGET_SSE2 && TARGET_IEEE_FP"
15979 (define_insn "*mindf_nonieee"
15980 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15981 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
15982 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15985 (clobber (reg:CC 17))]
15986 "TARGET_SSE2 && !TARGET_IEEE_FP"
15990 [(set (match_operand:DF 0 "register_operand" "")
15991 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15992 (match_operand:DF 2 "nonimmediate_operand" ""))
15993 (match_operand:DF 3 "register_operand" "")
15994 (match_operand:DF 4 "nonimmediate_operand" "")))
15995 (clobber (reg:CC 17))]
15996 "SSE_REG_P (operands[0]) && reload_completed
15997 && ((operands_match_p (operands[1], operands[3])
15998 && operands_match_p (operands[2], operands[4]))
15999 || (operands_match_p (operands[1], operands[4])
16000 && operands_match_p (operands[2], operands[3])))"
16001 [(set (match_dup 0)
16002 (if_then_else:DF (lt (match_dup 1)
16007 ;; We can't represent the LT test directly. Do this by swapping the operands.
16009 [(set (match_operand:DF 0 "register_operand" "")
16010 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16011 (match_operand:DF 2 "register_operand" ""))
16012 (match_operand:DF 3 "register_operand" "")
16013 (match_operand:DF 4 "register_operand" "")))
16014 (clobber (reg:CC 17))]
16015 "FP_REG_P (operands[0]) && reload_completed
16016 && ((operands_match_p (operands[1], operands[3])
16017 && operands_match_p (operands[2], operands[4]))
16018 || (operands_match_p (operands[1], operands[4])
16019 && operands_match_p (operands[2], operands[3])))"
16020 [(set (reg:CCFP 17)
16021 (compare:CCFP (match_dup 2)
16024 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
16028 (define_insn "*mindf_sse"
16029 [(set (match_operand:DF 0 "register_operand" "=Y")
16030 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
16031 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16034 "TARGET_SSE2 && reload_completed"
16035 "minsd\t{%2, %0|%0, %2}"
16036 [(set_attr "type" "sse")
16037 (set_attr "mode" "DF")])
16039 (define_expand "maxsf3"
16041 (set (match_operand:SF 0 "register_operand" "")
16042 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16043 (match_operand:SF 2 "nonimmediate_operand" ""))
16046 (clobber (reg:CC 17))])]
16050 (define_insn "*maxsf"
16051 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16052 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
16053 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
16056 (clobber (reg:CC 17))]
16057 "TARGET_SSE && TARGET_IEEE_FP"
16060 (define_insn "*maxsf_nonieee"
16061 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16062 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
16063 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
16066 (clobber (reg:CC 17))]
16067 "TARGET_SSE && !TARGET_IEEE_FP"
16071 [(set (match_operand:SF 0 "register_operand" "")
16072 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16073 (match_operand:SF 2 "nonimmediate_operand" ""))
16074 (match_operand:SF 3 "register_operand" "")
16075 (match_operand:SF 4 "nonimmediate_operand" "")))
16076 (clobber (reg:CC 17))]
16077 "SSE_REG_P (operands[0]) && reload_completed
16078 && ((operands_match_p (operands[1], operands[3])
16079 && operands_match_p (operands[2], operands[4]))
16080 || (operands_match_p (operands[1], operands[4])
16081 && operands_match_p (operands[2], operands[3])))"
16082 [(set (match_dup 0)
16083 (if_then_else:SF (gt (match_dup 1)
16089 [(set (match_operand:SF 0 "register_operand" "")
16090 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16091 (match_operand:SF 2 "register_operand" ""))
16092 (match_operand:SF 3 "register_operand" "")
16093 (match_operand:SF 4 "register_operand" "")))
16094 (clobber (reg:CC 17))]
16095 "FP_REG_P (operands[0]) && reload_completed
16096 && ((operands_match_p (operands[1], operands[3])
16097 && operands_match_p (operands[2], operands[4]))
16098 || (operands_match_p (operands[1], operands[4])
16099 && operands_match_p (operands[2], operands[3])))"
16100 [(set (reg:CCFP 17)
16101 (compare:CCFP (match_dup 1)
16104 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
16108 (define_insn "*maxsf_sse"
16109 [(set (match_operand:SF 0 "register_operand" "=x")
16110 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
16111 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16114 "TARGET_SSE && reload_completed"
16115 "maxss\t{%2, %0|%0, %2}"
16116 [(set_attr "type" "sse")
16117 (set_attr "mode" "SF")])
16119 (define_expand "maxdf3"
16121 (set (match_operand:DF 0 "register_operand" "")
16122 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16123 (match_operand:DF 2 "nonimmediate_operand" ""))
16126 (clobber (reg:CC 17))])]
16130 (define_insn "*maxdf"
16131 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16132 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16133 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
16136 (clobber (reg:CC 17))]
16137 "TARGET_SSE2 && TARGET_IEEE_FP"
16140 (define_insn "*maxdf_nonieee"
16141 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16142 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
16143 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
16146 (clobber (reg:CC 17))]
16147 "TARGET_SSE2 && !TARGET_IEEE_FP"
16151 [(set (match_operand:DF 0 "register_operand" "")
16152 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16153 (match_operand:DF 2 "nonimmediate_operand" ""))
16154 (match_operand:DF 3 "register_operand" "")
16155 (match_operand:DF 4 "nonimmediate_operand" "")))
16156 (clobber (reg:CC 17))]
16157 "SSE_REG_P (operands[0]) && reload_completed
16158 && ((operands_match_p (operands[1], operands[3])
16159 && operands_match_p (operands[2], operands[4]))
16160 || (operands_match_p (operands[1], operands[4])
16161 && operands_match_p (operands[2], operands[3])))"
16162 [(set (match_dup 0)
16163 (if_then_else:DF (gt (match_dup 1)
16169 [(set (match_operand:DF 0 "register_operand" "")
16170 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16171 (match_operand:DF 2 "register_operand" ""))
16172 (match_operand:DF 3 "register_operand" "")
16173 (match_operand:DF 4 "register_operand" "")))
16174 (clobber (reg:CC 17))]
16175 "FP_REG_P (operands[0]) && reload_completed
16176 && ((operands_match_p (operands[1], operands[3])
16177 && operands_match_p (operands[2], operands[4]))
16178 || (operands_match_p (operands[1], operands[4])
16179 && operands_match_p (operands[2], operands[3])))"
16180 [(set (reg:CCFP 17)
16181 (compare:CCFP (match_dup 1)
16184 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16188 (define_insn "*maxdf_sse"
16189 [(set (match_operand:DF 0 "register_operand" "=Y")
16190 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16191 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16194 "TARGET_SSE2 && reload_completed"
16195 "maxsd\t{%2, %0|%0, %2}"
16196 [(set_attr "type" "sse")
16197 (set_attr "mode" "DF")])
16199 ;; Misc patterns (?)
16201 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
16202 ;; Otherwise there will be nothing to keep
16204 ;; [(set (reg ebp) (reg esp))]
16205 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16206 ;; (clobber (eflags)]
16207 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16209 ;; in proper program order.
16210 (define_expand "pro_epilogue_adjust_stack"
16211 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
16212 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16213 (match_operand:SI 2 "immediate_operand" "i,i")))
16214 (clobber (reg:CC 17))
16215 (clobber (mem:BLK (scratch)))])]
16220 emit_insn (gen_pro_epilogue_adjust_stack_rex64
16221 (operands[0], operands[1], operands[2]));
16226 (define_insn "*pro_epilogue_adjust_stack_1"
16227 [(set (match_operand:SI 0 "register_operand" "=r,r")
16228 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16229 (match_operand:SI 2 "immediate_operand" "i,i")))
16230 (clobber (reg:CC 17))
16231 (clobber (mem:BLK (scratch)))]
16234 switch (get_attr_type (insn))
16237 return "mov{l}\t{%1, %0|%0, %1}";
16240 if (GET_CODE (operands[2]) == CONST_INT
16241 && (INTVAL (operands[2]) == 128
16242 || (INTVAL (operands[2]) < 0
16243 && INTVAL (operands[2]) != -128)))
16245 operands[2] = GEN_INT (-INTVAL (operands[2]));
16246 return "sub{l}\t{%2, %0|%0, %2}";
16248 return "add{l}\t{%2, %0|%0, %2}";
16251 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16252 return "lea{l}\t{%a2, %0|%0, %a2}";
16258 [(set (attr "type")
16259 (cond [(eq_attr "alternative" "0")
16260 (const_string "alu")
16261 (match_operand:SI 2 "const0_operand" "")
16262 (const_string "imov")
16264 (const_string "lea")))
16265 (set_attr "mode" "SI")])
16267 (define_insn "pro_epilogue_adjust_stack_rex64"
16268 [(set (match_operand:DI 0 "register_operand" "=r,r")
16269 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16270 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16271 (clobber (reg:CC 17))
16272 (clobber (mem:BLK (scratch)))]
16275 switch (get_attr_type (insn))
16278 return "mov{q}\t{%1, %0|%0, %1}";
16281 if (GET_CODE (operands[2]) == CONST_INT
16282 && (INTVAL (operands[2]) == 128
16283 || (INTVAL (operands[2]) < 0
16284 && INTVAL (operands[2]) != -128)))
16286 operands[2] = GEN_INT (-INTVAL (operands[2]));
16287 return "sub{q}\t{%2, %0|%0, %2}";
16289 return "add{q}\t{%2, %0|%0, %2}";
16292 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16293 return "lea{q}\t{%a2, %0|%0, %a2}";
16299 [(set (attr "type")
16300 (cond [(eq_attr "alternative" "0")
16301 (const_string "alu")
16302 (match_operand:DI 2 "const0_operand" "")
16303 (const_string "imov")
16305 (const_string "lea")))
16306 (set_attr "mode" "DI")])
16309 ;; Placeholder for the conditional moves. This one is split eighter to SSE
16310 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16311 ;; fact is that compares supported by the cmp??ss instructions are exactly
16312 ;; swapped of those supported by cmove sequence.
16313 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16314 ;; supported by i387 comparisons and we do need to emit two conditional moves
16317 (define_insn "sse_movsfcc"
16318 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16319 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16320 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16321 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16322 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16323 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16324 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16325 (clobber (reg:CC 17))]
16327 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16328 && (!TARGET_IEEE_FP
16329 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16332 (define_insn "sse_movsfcc_eq"
16333 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16334 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16335 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16336 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16337 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16338 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16339 (clobber (reg:CC 17))]
16341 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16344 (define_insn "sse_movdfcc"
16345 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16346 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16347 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16348 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16349 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16350 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16351 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16352 (clobber (reg:CC 17))]
16354 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16355 && (!TARGET_IEEE_FP
16356 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16359 (define_insn "sse_movdfcc_eq"
16360 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16361 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16362 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16363 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16364 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16365 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16366 (clobber (reg:CC 17))]
16368 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16371 ;; For non-sse moves just expand the usual cmove sequence.
16373 [(set (match_operand 0 "register_operand" "")
16374 (if_then_else (match_operator 1 "comparison_operator"
16375 [(match_operand 4 "nonimmediate_operand" "")
16376 (match_operand 5 "register_operand" "")])
16377 (match_operand 2 "nonimmediate_operand" "")
16378 (match_operand 3 "nonimmediate_operand" "")))
16379 (clobber (match_operand 6 "" ""))
16380 (clobber (reg:CC 17))]
16381 "!SSE_REG_P (operands[0]) && reload_completed
16382 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16385 ix86_compare_op0 = operands[5];
16386 ix86_compare_op1 = operands[4];
16387 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16388 VOIDmode, operands[5], operands[4]);
16389 ix86_expand_fp_movcc (operands);
16393 ;; Split SSE based conditional move into seqence:
16394 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16395 ;; and op2, op0 - zero op2 if comparison was false
16396 ;; nand op0, op3 - load op3 to op0 if comparison was false
16397 ;; or op2, op0 - get the non-zero one into the result.
16399 [(set (match_operand 0 "register_operand" "")
16400 (if_then_else (match_operator 1 "sse_comparison_operator"
16401 [(match_operand 4 "register_operand" "")
16402 (match_operand 5 "nonimmediate_operand" "")])
16403 (match_operand 2 "register_operand" "")
16404 (match_operand 3 "register_operand" "")))
16405 (clobber (match_operand 6 "" ""))
16406 (clobber (reg:CC 17))]
16407 "SSE_REG_P (operands[0]) && reload_completed"
16408 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16409 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16410 (subreg:TI (match_dup 4) 0)))
16411 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16412 (subreg:TI (match_dup 3) 0)))
16413 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16414 (subreg:TI (match_dup 7) 0)))]
16416 PUT_MODE (operands[1], GET_MODE (operands[0]));
16417 if (operands_match_p (operands[0], operands[4]))
16418 operands[6] = operands[4], operands[7] = operands[2];
16420 operands[6] = operands[2], operands[7] = operands[4];
16423 ;; Special case of conditional move we can handle effectivly.
16424 ;; Do not brother with the integer/floating point case, since these are
16425 ;; bot considerably slower, unlike in the generic case.
16426 (define_insn "*sse_movsfcc_const0_1"
16427 [(set (match_operand:SF 0 "register_operand" "=x")
16428 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16429 [(match_operand:SF 4 "register_operand" "0")
16430 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16431 (match_operand:SF 2 "register_operand" "x")
16432 (match_operand:SF 3 "const0_operand" "X")))]
16436 (define_insn "*sse_movsfcc_const0_2"
16437 [(set (match_operand:SF 0 "register_operand" "=x")
16438 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16439 [(match_operand:SF 4 "register_operand" "0")
16440 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16441 (match_operand:SF 2 "const0_operand" "x")
16442 (match_operand:SF 3 "register_operand" "X")))]
16446 (define_insn "*sse_movsfcc_const0_3"
16447 [(set (match_operand:SF 0 "register_operand" "=x")
16448 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16449 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16450 (match_operand:SF 5 "register_operand" "0")])
16451 (match_operand:SF 2 "register_operand" "x")
16452 (match_operand:SF 3 "const0_operand" "X")))]
16456 (define_insn "*sse_movsfcc_const0_4"
16457 [(set (match_operand:SF 0 "register_operand" "=x")
16458 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16459 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16460 (match_operand:SF 5 "register_operand" "0")])
16461 (match_operand:SF 2 "const0_operand" "x")
16462 (match_operand:SF 3 "register_operand" "X")))]
16466 (define_insn "*sse_movdfcc_const0_1"
16467 [(set (match_operand:SF 0 "register_operand" "=x")
16468 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16469 [(match_operand:SF 4 "register_operand" "0")
16470 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16471 (match_operand:SF 2 "register_operand" "x")
16472 (match_operand:SF 3 "const0_operand" "X")))]
16476 (define_insn "*sse_movdfcc_const0_2"
16477 [(set (match_operand:SF 0 "register_operand" "=x")
16478 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16479 [(match_operand:SF 4 "register_operand" "0")
16480 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16481 (match_operand:SF 2 "const0_operand" "x")
16482 (match_operand:SF 3 "register_operand" "X")))]
16486 (define_insn "*sse_movdfcc_const0_3"
16487 [(set (match_operand:SF 0 "register_operand" "=x")
16488 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16489 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16490 (match_operand:SF 5 "register_operand" "0")])
16491 (match_operand:SF 2 "register_operand" "x")
16492 (match_operand:SF 3 "const0_operand" "X")))]
16496 (define_insn "*sse_movdfcc_const0_4"
16497 [(set (match_operand:SF 0 "register_operand" "=x")
16498 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16499 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16500 (match_operand:SF 5 "register_operand" "0")])
16501 (match_operand:SF 2 "const0_operand" "x")
16502 (match_operand:SF 3 "register_operand" "X")))]
16507 [(set (match_operand 0 "register_operand" "")
16508 (if_then_else (match_operator 1 "comparison_operator"
16509 [(match_operand 4 "register_operand" "")
16510 (match_operand 5 "nonimmediate_operand" "")])
16511 (match_operand 2 "nonmemory_operand" "")
16512 (match_operand 3 "nonmemory_operand" "")))]
16513 "SSE_REG_P (operands[0]) && reload_completed
16514 && (const0_operand (operands[2], GET_MODE (operands[0]))
16515 || const0_operand (operands[3], GET_MODE (operands[0])))"
16516 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16517 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16518 (subreg:TI (match_dup 7) 0)))]
16520 PUT_MODE (operands[1], GET_MODE (operands[0]));
16521 if (!sse_comparison_operator (operands[1], VOIDmode))
16523 rtx tmp = operands[5];
16524 operands[5] = operands[4];
16526 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16528 if (const0_operand (operands[2], GET_MODE (operands[0])))
16530 operands[7] = operands[3];
16531 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16536 operands[7] = operands[2];
16537 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16541 (define_expand "allocate_stack_worker"
16542 [(match_operand:SI 0 "register_operand" "")]
16543 "TARGET_STACK_PROBE"
16546 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16548 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16552 (define_insn "allocate_stack_worker_1"
16553 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
16554 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16555 (clobber (match_dup 0))
16556 (clobber (reg:CC 17))]
16557 "!TARGET_64BIT && TARGET_STACK_PROBE"
16559 [(set_attr "type" "multi")
16560 (set_attr "length" "5")])
16562 (define_insn "allocate_stack_worker_rex64"
16563 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
16564 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16565 (clobber (match_dup 0))
16566 (clobber (reg:CC 17))]
16567 "TARGET_64BIT && TARGET_STACK_PROBE"
16569 [(set_attr "type" "multi")
16570 (set_attr "length" "5")])
16572 (define_expand "allocate_stack"
16573 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16574 (minus:SI (reg:SI 7)
16575 (match_operand:SI 1 "general_operand" "")))
16576 (clobber (reg:CC 17))])
16577 (parallel [(set (reg:SI 7)
16578 (minus:SI (reg:SI 7) (match_dup 1)))
16579 (clobber (reg:CC 17))])]
16580 "TARGET_STACK_PROBE"
16582 #ifdef CHECK_STACK_LIMIT
16583 if (GET_CODE (operands[1]) == CONST_INT
16584 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16585 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16589 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16592 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16596 (define_expand "builtin_setjmp_receiver"
16597 [(label_ref (match_operand 0 "" ""))]
16598 "!TARGET_64BIT && flag_pic"
16600 load_pic_register ();
16604 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16607 [(set (match_operand 0 "register_operand" "")
16608 (match_operator 3 "promotable_binary_operator"
16609 [(match_operand 1 "register_operand" "")
16610 (match_operand 2 "aligned_operand" "")]))
16611 (clobber (reg:CC 17))]
16612 "! TARGET_PARTIAL_REG_STALL && reload_completed
16613 && ((GET_MODE (operands[0]) == HImode
16614 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
16615 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16616 || (GET_MODE (operands[0]) == QImode
16617 && (TARGET_PROMOTE_QImode || optimize_size)))"
16618 [(parallel [(set (match_dup 0)
16619 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16620 (clobber (reg:CC 17))])]
16621 "operands[0] = gen_lowpart (SImode, operands[0]);
16622 operands[1] = gen_lowpart (SImode, operands[1]);
16623 if (GET_CODE (operands[3]) != ASHIFT)
16624 operands[2] = gen_lowpart (SImode, operands[2]);
16625 PUT_MODE (operands[3], SImode);")
16629 (compare (and (match_operand 1 "aligned_operand" "")
16630 (match_operand 2 "const_int_operand" ""))
16632 (set (match_operand 0 "register_operand" "")
16633 (and (match_dup 1) (match_dup 2)))]
16634 "! TARGET_PARTIAL_REG_STALL && reload_completed
16635 && ix86_match_ccmode (insn, CCNOmode)
16636 && (GET_MODE (operands[0]) == HImode
16637 || (GET_MODE (operands[0]) == QImode
16638 && (TARGET_PROMOTE_QImode || optimize_size)))"
16639 [(parallel [(set (reg:CCNO 17)
16640 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16643 (and:SI (match_dup 1) (match_dup 2)))])]
16645 = GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
16646 & GET_MODE_MASK (GET_MODE (operands[0])),
16648 operands[0] = gen_lowpart (SImode, operands[0]);
16649 operands[1] = gen_lowpart (SImode, operands[1]);")
16653 (compare (and (match_operand 0 "aligned_operand" "")
16654 (match_operand 1 "const_int_operand" ""))
16656 "! TARGET_PARTIAL_REG_STALL && reload_completed
16657 && ix86_match_ccmode (insn, CCNOmode)
16658 && (GET_MODE (operands[0]) == HImode
16659 || (GET_MODE (operands[0]) == QImode
16660 && (TARGET_PROMOTE_QImode || optimize_size)))"
16661 [(set (reg:CCNO 17)
16662 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16665 = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
16666 & GET_MODE_MASK (GET_MODE (operands[0])),
16668 operands[0] = gen_lowpart (SImode, operands[0]);")
16671 [(set (match_operand 0 "register_operand" "")
16672 (neg (match_operand 1 "register_operand" "")))
16673 (clobber (reg:CC 17))]
16674 "! TARGET_PARTIAL_REG_STALL && reload_completed
16675 && (GET_MODE (operands[0]) == HImode
16676 || (GET_MODE (operands[0]) == QImode
16677 && (TARGET_PROMOTE_QImode || optimize_size)))"
16678 [(parallel [(set (match_dup 0)
16679 (neg:SI (match_dup 1)))
16680 (clobber (reg:CC 17))])]
16681 "operands[0] = gen_lowpart (SImode, operands[0]);
16682 operands[1] = gen_lowpart (SImode, operands[1]);")
16685 [(set (match_operand 0 "register_operand" "")
16686 (not (match_operand 1 "register_operand" "")))]
16687 "! TARGET_PARTIAL_REG_STALL && reload_completed
16688 && (GET_MODE (operands[0]) == HImode
16689 || (GET_MODE (operands[0]) == QImode
16690 && (TARGET_PROMOTE_QImode || optimize_size)))"
16691 [(set (match_dup 0)
16692 (not:SI (match_dup 1)))]
16693 "operands[0] = gen_lowpart (SImode, operands[0]);
16694 operands[1] = gen_lowpart (SImode, operands[1]);")
16697 [(set (match_operand 0 "register_operand" "")
16698 (if_then_else (match_operator 1 "comparison_operator"
16699 [(reg 17) (const_int 0)])
16700 (match_operand 2 "register_operand" "")
16701 (match_operand 3 "register_operand" "")))]
16702 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16703 && (GET_MODE (operands[0]) == HImode
16704 || (GET_MODE (operands[0]) == QImode
16705 && (TARGET_PROMOTE_QImode || optimize_size)))"
16706 [(set (match_dup 0)
16707 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16708 "operands[0] = gen_lowpart (SImode, operands[0]);
16709 operands[2] = gen_lowpart (SImode, operands[2]);
16710 operands[3] = gen_lowpart (SImode, operands[3]);")
16713 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16714 ;; transform a complex memory operation into two memory to register operations.
16716 ;; Don't push memory operands
16718 [(set (match_operand:SI 0 "push_operand" "")
16719 (match_operand:SI 1 "memory_operand" ""))
16720 (match_scratch:SI 2 "r")]
16721 "! optimize_size && ! TARGET_PUSH_MEMORY"
16722 [(set (match_dup 2) (match_dup 1))
16723 (set (match_dup 0) (match_dup 2))]
16727 [(set (match_operand:DI 0 "push_operand" "")
16728 (match_operand:DI 1 "memory_operand" ""))
16729 (match_scratch:DI 2 "r")]
16730 "! optimize_size && ! TARGET_PUSH_MEMORY"
16731 [(set (match_dup 2) (match_dup 1))
16732 (set (match_dup 0) (match_dup 2))]
16735 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16738 [(set (match_operand:SF 0 "push_operand" "")
16739 (match_operand:SF 1 "memory_operand" ""))
16740 (match_scratch:SF 2 "r")]
16741 "! optimize_size && ! TARGET_PUSH_MEMORY"
16742 [(set (match_dup 2) (match_dup 1))
16743 (set (match_dup 0) (match_dup 2))]
16747 [(set (match_operand:HI 0 "push_operand" "")
16748 (match_operand:HI 1 "memory_operand" ""))
16749 (match_scratch:HI 2 "r")]
16750 "! optimize_size && ! TARGET_PUSH_MEMORY"
16751 [(set (match_dup 2) (match_dup 1))
16752 (set (match_dup 0) (match_dup 2))]
16756 [(set (match_operand:QI 0 "push_operand" "")
16757 (match_operand:QI 1 "memory_operand" ""))
16758 (match_scratch:QI 2 "q")]
16759 "! optimize_size && ! TARGET_PUSH_MEMORY"
16760 [(set (match_dup 2) (match_dup 1))
16761 (set (match_dup 0) (match_dup 2))]
16764 ;; Don't move an immediate directly to memory when the instruction
16767 [(match_scratch:SI 1 "r")
16768 (set (match_operand:SI 0 "memory_operand" "")
16771 && ! TARGET_USE_MOV0
16772 && TARGET_SPLIT_LONG_MOVES
16773 && get_attr_length (insn) >= ix86_cost->large_insn
16774 && peep2_regno_dead_p (0, FLAGS_REG)"
16775 [(parallel [(set (match_dup 1) (const_int 0))
16776 (clobber (reg:CC 17))])
16777 (set (match_dup 0) (match_dup 1))]
16781 [(match_scratch:HI 1 "r")
16782 (set (match_operand:HI 0 "memory_operand" "")
16785 && ! TARGET_USE_MOV0
16786 && TARGET_SPLIT_LONG_MOVES
16787 && get_attr_length (insn) >= ix86_cost->large_insn
16788 && peep2_regno_dead_p (0, FLAGS_REG)"
16789 [(parallel [(set (match_dup 2) (const_int 0))
16790 (clobber (reg:CC 17))])
16791 (set (match_dup 0) (match_dup 1))]
16792 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16795 [(match_scratch:QI 1 "q")
16796 (set (match_operand:QI 0 "memory_operand" "")
16799 && ! TARGET_USE_MOV0
16800 && TARGET_SPLIT_LONG_MOVES
16801 && get_attr_length (insn) >= ix86_cost->large_insn
16802 && peep2_regno_dead_p (0, FLAGS_REG)"
16803 [(parallel [(set (match_dup 2) (const_int 0))
16804 (clobber (reg:CC 17))])
16805 (set (match_dup 0) (match_dup 1))]
16806 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16809 [(match_scratch:SI 2 "r")
16810 (set (match_operand:SI 0 "memory_operand" "")
16811 (match_operand:SI 1 "immediate_operand" ""))]
16813 && get_attr_length (insn) >= ix86_cost->large_insn
16814 && TARGET_SPLIT_LONG_MOVES"
16815 [(set (match_dup 2) (match_dup 1))
16816 (set (match_dup 0) (match_dup 2))]
16820 [(match_scratch:HI 2 "r")
16821 (set (match_operand:HI 0 "memory_operand" "")
16822 (match_operand:HI 1 "immediate_operand" ""))]
16823 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16824 && TARGET_SPLIT_LONG_MOVES"
16825 [(set (match_dup 2) (match_dup 1))
16826 (set (match_dup 0) (match_dup 2))]
16830 [(match_scratch:QI 2 "q")
16831 (set (match_operand:QI 0 "memory_operand" "")
16832 (match_operand:QI 1 "immediate_operand" ""))]
16833 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16834 && TARGET_SPLIT_LONG_MOVES"
16835 [(set (match_dup 2) (match_dup 1))
16836 (set (match_dup 0) (match_dup 2))]
16839 ;; Don't compare memory with zero, load and use a test instead.
16842 (compare (match_operand:SI 0 "memory_operand" "")
16844 (match_scratch:SI 3 "r")]
16845 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
16846 [(set (match_dup 3) (match_dup 0))
16847 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
16850 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16851 ;; Don't split NOTs with a displacement operand, because resulting XOR
16852 ;; will not be pariable anyway.
16854 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
16855 ;; represented using a modRM byte. The XOR replacement is long decoded,
16856 ;; so this split helps here as well.
16858 ;; Note: Can't do this as a regular split because we can't get proper
16859 ;; lifetime information then.
16862 [(set (match_operand:SI 0 "nonimmediate_operand" "")
16863 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
16865 && peep2_regno_dead_p (0, FLAGS_REG)
16866 && ((TARGET_PENTIUM
16867 && (GET_CODE (operands[0]) != MEM
16868 || !memory_displacement_operand (operands[0], SImode)))
16869 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
16870 [(parallel [(set (match_dup 0)
16871 (xor:SI (match_dup 1) (const_int -1)))
16872 (clobber (reg:CC 17))])]
16876 [(set (match_operand:HI 0 "nonimmediate_operand" "")
16877 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
16879 && peep2_regno_dead_p (0, FLAGS_REG)
16880 && ((TARGET_PENTIUM
16881 && (GET_CODE (operands[0]) != MEM
16882 || !memory_displacement_operand (operands[0], HImode)))
16883 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
16884 [(parallel [(set (match_dup 0)
16885 (xor:HI (match_dup 1) (const_int -1)))
16886 (clobber (reg:CC 17))])]
16890 [(set (match_operand:QI 0 "nonimmediate_operand" "")
16891 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
16893 && peep2_regno_dead_p (0, FLAGS_REG)
16894 && ((TARGET_PENTIUM
16895 && (GET_CODE (operands[0]) != MEM
16896 || !memory_displacement_operand (operands[0], QImode)))
16897 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
16898 [(parallel [(set (match_dup 0)
16899 (xor:QI (match_dup 1) (const_int -1)))
16900 (clobber (reg:CC 17))])]
16903 ;; Non pairable "test imm, reg" instructions can be translated to
16904 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
16905 ;; byte opcode instead of two, have a short form for byte operands),
16906 ;; so do it for other CPUs as well. Given that the value was dead,
16907 ;; this should not create any new dependencies. Pass on the sub-word
16908 ;; versions if we're concerned about partial register stalls.
16912 (compare (and:SI (match_operand:SI 0 "register_operand" "")
16913 (match_operand:SI 1 "immediate_operand" ""))
16915 "ix86_match_ccmode (insn, CCNOmode)
16916 && (true_regnum (operands[0]) != 0
16917 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
16918 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16920 [(set (reg:CCNO 17)
16921 (compare:CCNO (and:SI (match_dup 0)
16925 (and:SI (match_dup 0) (match_dup 1)))])]
16928 ;; We don't need to handle HImode case, because it will be promoted to SImode
16929 ;; on ! TARGET_PARTIAL_REG_STALL
16933 (compare (and:QI (match_operand:QI 0 "register_operand" "")
16934 (match_operand:QI 1 "immediate_operand" ""))
16936 "! TARGET_PARTIAL_REG_STALL
16937 && ix86_match_ccmode (insn, CCNOmode)
16938 && true_regnum (operands[0]) != 0
16939 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16941 [(set (reg:CCNO 17)
16942 (compare:CCNO (and:QI (match_dup 0)
16946 (and:QI (match_dup 0) (match_dup 1)))])]
16954 (match_operand 0 "ext_register_operand" "")
16957 (match_operand 1 "const_int_operand" ""))
16959 "! TARGET_PARTIAL_REG_STALL
16960 && ix86_match_ccmode (insn, CCNOmode)
16961 && true_regnum (operands[0]) != 0
16962 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16963 [(parallel [(set (reg:CCNO 17)
16972 (set (zero_extract:SI (match_dup 0)
16983 ;; Don't do logical operations with memory inputs.
16985 [(match_scratch:SI 2 "r")
16986 (parallel [(set (match_operand:SI 0 "register_operand" "")
16987 (match_operator:SI 3 "arith_or_logical_operator"
16989 (match_operand:SI 1 "memory_operand" "")]))
16990 (clobber (reg:CC 17))])]
16991 "! optimize_size && ! TARGET_READ_MODIFY"
16992 [(set (match_dup 2) (match_dup 1))
16993 (parallel [(set (match_dup 0)
16994 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
16995 (clobber (reg:CC 17))])]
16999 [(match_scratch:SI 2 "r")
17000 (parallel [(set (match_operand:SI 0 "register_operand" "")
17001 (match_operator:SI 3 "arith_or_logical_operator"
17002 [(match_operand:SI 1 "memory_operand" "")
17004 (clobber (reg:CC 17))])]
17005 "! optimize_size && ! TARGET_READ_MODIFY"
17006 [(set (match_dup 2) (match_dup 1))
17007 (parallel [(set (match_dup 0)
17008 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
17009 (clobber (reg:CC 17))])]
17012 ; Don't do logical operations with memory outputs
17014 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
17015 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
17016 ; the same decoder scheduling characteristics as the original.
17019 [(match_scratch:SI 2 "r")
17020 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17021 (match_operator:SI 3 "arith_or_logical_operator"
17023 (match_operand:SI 1 "nonmemory_operand" "")]))
17024 (clobber (reg:CC 17))])]
17025 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17026 [(set (match_dup 2) (match_dup 0))
17027 (parallel [(set (match_dup 2)
17028 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
17029 (clobber (reg:CC 17))])
17030 (set (match_dup 0) (match_dup 2))]
17034 [(match_scratch:SI 2 "r")
17035 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17036 (match_operator:SI 3 "arith_or_logical_operator"
17037 [(match_operand:SI 1 "nonmemory_operand" "")
17039 (clobber (reg:CC 17))])]
17040 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17041 [(set (match_dup 2) (match_dup 0))
17042 (parallel [(set (match_dup 2)
17043 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17044 (clobber (reg:CC 17))])
17045 (set (match_dup 0) (match_dup 2))]
17048 ;; Attempt to always use XOR for zeroing registers.
17050 [(set (match_operand 0 "register_operand" "")
17052 "(GET_MODE (operands[0]) == QImode
17053 || GET_MODE (operands[0]) == HImode
17054 || GET_MODE (operands[0]) == SImode
17055 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17056 && (! TARGET_USE_MOV0 || optimize_size)
17057 && peep2_regno_dead_p (0, FLAGS_REG)"
17058 [(parallel [(set (match_dup 0) (const_int 0))
17059 (clobber (reg:CC 17))])]
17060 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17061 true_regnum (operands[0]));")
17064 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17066 "(GET_MODE (operands[0]) == QImode
17067 || GET_MODE (operands[0]) == HImode)
17068 && (! TARGET_USE_MOV0 || optimize_size)
17069 && peep2_regno_dead_p (0, FLAGS_REG)"
17070 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17071 (clobber (reg:CC 17))])])
17073 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
17075 [(set (match_operand 0 "register_operand" "")
17077 "(GET_MODE (operands[0]) == HImode
17078 || GET_MODE (operands[0]) == SImode
17079 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17080 && (optimize_size || TARGET_PENTIUM)
17081 && peep2_regno_dead_p (0, FLAGS_REG)"
17082 [(parallel [(set (match_dup 0) (const_int -1))
17083 (clobber (reg:CC 17))])]
17084 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17085 true_regnum (operands[0]));")
17087 ;; Attempt to convert simple leas to adds. These can be created by
17090 [(set (match_operand:SI 0 "register_operand" "")
17091 (plus:SI (match_dup 0)
17092 (match_operand:SI 1 "nonmemory_operand" "")))]
17093 "peep2_regno_dead_p (0, FLAGS_REG)"
17094 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
17095 (clobber (reg:CC 17))])]
17099 [(set (match_operand:SI 0 "register_operand" "")
17100 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17101 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17102 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
17103 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17104 (clobber (reg:CC 17))])]
17105 "operands[2] = gen_lowpart (SImode, operands[2]);")
17108 [(set (match_operand:DI 0 "register_operand" "")
17109 (plus:DI (match_dup 0)
17110 (match_operand:DI 1 "x86_64_general_operand" "")))]
17111 "peep2_regno_dead_p (0, FLAGS_REG)"
17112 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
17113 (clobber (reg:CC 17))])]
17117 [(set (match_operand:SI 0 "register_operand" "")
17118 (mult:SI (match_dup 0)
17119 (match_operand:SI 1 "const_int_operand" "")))]
17120 "exact_log2 (INTVAL (operands[1])) >= 0
17121 && peep2_regno_dead_p (0, FLAGS_REG)"
17122 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17123 (clobber (reg:CC 17))])]
17124 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17127 [(set (match_operand:DI 0 "register_operand" "")
17128 (mult:DI (match_dup 0)
17129 (match_operand:DI 1 "const_int_operand" "")))]
17130 "exact_log2 (INTVAL (operands[1])) >= 0
17131 && peep2_regno_dead_p (0, FLAGS_REG)"
17132 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17133 (clobber (reg:CC 17))])]
17134 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17137 [(set (match_operand:SI 0 "register_operand" "")
17138 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17139 (match_operand:DI 2 "const_int_operand" "")) 0))]
17140 "exact_log2 (INTVAL (operands[1])) >= 0
17141 && REGNO (operands[0]) == REGNO (operands[1])
17142 && peep2_regno_dead_p (0, FLAGS_REG)"
17143 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17144 (clobber (reg:CC 17))])]
17145 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17147 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17148 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17149 ;; many CPUs it is also faster, since special hardware to avoid esp
17150 ;; dependencies is present.
17152 ;; While some of these converisons may be done using splitters, we use peepholes
17153 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17155 ;; Convert prologue esp subtractions to push.
17156 ;; We need register to push. In order to keep verify_flow_info happy we have
17158 ;; - use scratch and clobber it in order to avoid dependencies
17159 ;; - use already live register
17160 ;; We can't use the second way right now, since there is no reliable way how to
17161 ;; verify that given register is live. First choice will also most likely in
17162 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17163 ;; call clobbered registers are dead. We may want to use base pointer as an
17164 ;; alternative when no register is available later.
17167 [(match_scratch:SI 0 "r")
17168 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17169 (clobber (reg:CC 17))
17170 (clobber (mem:BLK (scratch)))])]
17171 "optimize_size || !TARGET_SUB_ESP_4"
17172 [(clobber (match_dup 0))
17173 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17174 (clobber (mem:BLK (scratch)))])])
17177 [(match_scratch:SI 0 "r")
17178 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17179 (clobber (reg:CC 17))
17180 (clobber (mem:BLK (scratch)))])]
17181 "optimize_size || !TARGET_SUB_ESP_8"
17182 [(clobber (match_dup 0))
17183 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17184 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17185 (clobber (mem:BLK (scratch)))])])
17187 ;; Convert esp subtractions to push.
17189 [(match_scratch:SI 0 "r")
17190 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17191 (clobber (reg:CC 17))])]
17192 "optimize_size || !TARGET_SUB_ESP_4"
17193 [(clobber (match_dup 0))
17194 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17197 [(match_scratch:SI 0 "r")
17198 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17199 (clobber (reg:CC 17))])]
17200 "optimize_size || !TARGET_SUB_ESP_8"
17201 [(clobber (match_dup 0))
17202 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17203 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17205 ;; Convert epilogue deallocator to pop.
17207 [(match_scratch:SI 0 "r")
17208 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17209 (clobber (reg:CC 17))
17210 (clobber (mem:BLK (scratch)))])]
17211 "optimize_size || !TARGET_ADD_ESP_4"
17212 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17213 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17214 (clobber (mem:BLK (scratch)))])]
17217 ;; Two pops case is tricky, since pop causes dependency on destination register.
17218 ;; We use two registers if available.
17220 [(match_scratch:SI 0 "r")
17221 (match_scratch:SI 1 "r")
17222 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17223 (clobber (reg:CC 17))
17224 (clobber (mem:BLK (scratch)))])]
17225 "optimize_size || !TARGET_ADD_ESP_8"
17226 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17227 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17228 (clobber (mem:BLK (scratch)))])
17229 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17230 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17234 [(match_scratch:SI 0 "r")
17235 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17236 (clobber (reg:CC 17))
17237 (clobber (mem:BLK (scratch)))])]
17239 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17240 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17241 (clobber (mem:BLK (scratch)))])
17242 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17243 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17246 ;; Convert esp additions to pop.
17248 [(match_scratch:SI 0 "r")
17249 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17250 (clobber (reg:CC 17))])]
17252 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17253 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17256 ;; Two pops case is tricky, since pop causes dependency on destination register.
17257 ;; We use two registers if available.
17259 [(match_scratch:SI 0 "r")
17260 (match_scratch:SI 1 "r")
17261 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17262 (clobber (reg:CC 17))])]
17264 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17265 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17266 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17267 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17271 [(match_scratch:SI 0 "r")
17272 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17273 (clobber (reg:CC 17))])]
17275 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17276 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17277 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17278 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17281 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17282 ;; required and register dies.
17285 (compare (match_operand:SI 0 "register_operand" "")
17286 (match_operand:SI 1 "incdec_operand" "")))]
17287 "ix86_match_ccmode (insn, CCGCmode)
17288 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17289 [(parallel [(set (reg:CCGC 17)
17290 (compare:CCGC (match_dup 0)
17292 (clobber (match_dup 0))])]
17297 (compare (match_operand:HI 0 "register_operand" "")
17298 (match_operand:HI 1 "incdec_operand" "")))]
17299 "ix86_match_ccmode (insn, CCGCmode)
17300 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17301 [(parallel [(set (reg:CCGC 17)
17302 (compare:CCGC (match_dup 0)
17304 (clobber (match_dup 0))])]
17309 (compare (match_operand:QI 0 "register_operand" "")
17310 (match_operand:QI 1 "incdec_operand" "")))]
17311 "ix86_match_ccmode (insn, CCGCmode)
17312 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17313 [(parallel [(set (reg:CCGC 17)
17314 (compare:CCGC (match_dup 0)
17316 (clobber (match_dup 0))])]
17319 ;; Convert compares with 128 to shorter add -128
17322 (compare (match_operand:SI 0 "register_operand" "")
17324 "ix86_match_ccmode (insn, CCGCmode)
17325 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17326 [(parallel [(set (reg:CCGC 17)
17327 (compare:CCGC (match_dup 0)
17329 (clobber (match_dup 0))])]
17334 (compare (match_operand:HI 0 "register_operand" "")
17336 "ix86_match_ccmode (insn, CCGCmode)
17337 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17338 [(parallel [(set (reg:CCGC 17)
17339 (compare:CCGC (match_dup 0)
17341 (clobber (match_dup 0))])]
17345 [(match_scratch:DI 0 "r")
17346 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17347 (clobber (reg:CC 17))
17348 (clobber (mem:BLK (scratch)))])]
17349 "optimize_size || !TARGET_SUB_ESP_4"
17350 [(clobber (match_dup 0))
17351 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17352 (clobber (mem:BLK (scratch)))])])
17355 [(match_scratch:DI 0 "r")
17356 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17357 (clobber (reg:CC 17))
17358 (clobber (mem:BLK (scratch)))])]
17359 "optimize_size || !TARGET_SUB_ESP_8"
17360 [(clobber (match_dup 0))
17361 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17362 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17363 (clobber (mem:BLK (scratch)))])])
17365 ;; Convert esp subtractions to push.
17367 [(match_scratch:DI 0 "r")
17368 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17369 (clobber (reg:CC 17))])]
17370 "optimize_size || !TARGET_SUB_ESP_4"
17371 [(clobber (match_dup 0))
17372 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17375 [(match_scratch:DI 0 "r")
17376 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17377 (clobber (reg:CC 17))])]
17378 "optimize_size || !TARGET_SUB_ESP_8"
17379 [(clobber (match_dup 0))
17380 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17381 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17383 ;; Convert epilogue deallocator to pop.
17385 [(match_scratch:DI 0 "r")
17386 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17387 (clobber (reg:CC 17))
17388 (clobber (mem:BLK (scratch)))])]
17389 "optimize_size || !TARGET_ADD_ESP_4"
17390 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17391 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17392 (clobber (mem:BLK (scratch)))])]
17395 ;; Two pops case is tricky, since pop causes dependency on destination register.
17396 ;; We use two registers if available.
17398 [(match_scratch:DI 0 "r")
17399 (match_scratch:DI 1 "r")
17400 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17401 (clobber (reg:CC 17))
17402 (clobber (mem:BLK (scratch)))])]
17403 "optimize_size || !TARGET_ADD_ESP_8"
17404 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17405 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17406 (clobber (mem:BLK (scratch)))])
17407 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17408 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17412 [(match_scratch:DI 0 "r")
17413 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17414 (clobber (reg:CC 17))
17415 (clobber (mem:BLK (scratch)))])]
17417 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17418 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17419 (clobber (mem:BLK (scratch)))])
17420 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17421 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17424 ;; Convert esp additions to pop.
17426 [(match_scratch:DI 0 "r")
17427 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17428 (clobber (reg:CC 17))])]
17430 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17431 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17434 ;; Two pops case is tricky, since pop causes dependency on destination register.
17435 ;; We use two registers if available.
17437 [(match_scratch:DI 0 "r")
17438 (match_scratch:DI 1 "r")
17439 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17440 (clobber (reg:CC 17))])]
17442 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17443 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17444 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17445 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17449 [(match_scratch:DI 0 "r")
17450 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17451 (clobber (reg:CC 17))])]
17453 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17454 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17455 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17456 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17459 ;; Call-value patterns last so that the wildcard operand does not
17460 ;; disrupt insn-recog's switch tables.
17462 (define_insn "*call_value_pop_0"
17463 [(set (match_operand 0 "" "")
17464 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17465 (match_operand:SI 2 "" "")))
17466 (set (reg:SI 7) (plus:SI (reg:SI 7)
17467 (match_operand:SI 3 "immediate_operand" "")))]
17470 if (SIBLING_CALL_P (insn))
17473 return "call\t%P1";
17475 [(set_attr "type" "callv")])
17477 (define_insn "*call_value_pop_1"
17478 [(set (match_operand 0 "" "")
17479 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17480 (match_operand:SI 2 "" "")))
17481 (set (reg:SI 7) (plus:SI (reg:SI 7)
17482 (match_operand:SI 3 "immediate_operand" "i")))]
17485 if (constant_call_address_operand (operands[1], QImode))
17487 if (SIBLING_CALL_P (insn))
17490 return "call\t%P1";
17492 if (SIBLING_CALL_P (insn))
17495 return "call\t%A1";
17497 [(set_attr "type" "callv")])
17499 (define_insn "*call_value_0"
17500 [(set (match_operand 0 "" "")
17501 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17502 (match_operand:SI 2 "" "")))]
17505 if (SIBLING_CALL_P (insn))
17508 return "call\t%P1";
17510 [(set_attr "type" "callv")])
17512 (define_insn "*call_value_0_rex64"
17513 [(set (match_operand 0 "" "")
17514 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17515 (match_operand:DI 2 "const_int_operand" "")))]
17518 if (SIBLING_CALL_P (insn))
17521 return "call\t%P1";
17523 [(set_attr "type" "callv")])
17525 (define_insn "*call_value_1"
17526 [(set (match_operand 0 "" "")
17527 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17528 (match_operand:SI 2 "" "")))]
17531 if (constant_call_address_operand (operands[1], QImode))
17533 if (SIBLING_CALL_P (insn))
17536 return "call\t%P1";
17538 if (SIBLING_CALL_P (insn))
17539 return "jmp\t%*%1";
17541 return "call\t%*%1";
17543 [(set_attr "type" "callv")])
17545 (define_insn "*call_value_1_rex64"
17546 [(set (match_operand 0 "" "")
17547 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17548 (match_operand:DI 2 "" "")))]
17551 if (constant_call_address_operand (operands[1], QImode))
17553 if (SIBLING_CALL_P (insn))
17556 return "call\t%P1";
17558 if (SIBLING_CALL_P (insn))
17561 return "call\t%A1";
17563 [(set_attr "type" "callv")])
17565 (define_insn "trap"
17566 [(trap_if (const_int 1) (const_int 5))]
17570 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17571 ;;; for the sake of bounds checking. By emitting bounds checks as
17572 ;;; conditional traps rather than as conditional jumps around
17573 ;;; unconditional traps we avoid introducing spurious basic-block
17574 ;;; boundaries and facilitate elimination of redundant checks. In
17575 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17578 ;;; FIXME: Static branch prediction rules for ix86 are such that
17579 ;;; forward conditional branches predict as untaken. As implemented
17580 ;;; below, pseudo conditional traps violate that rule. We should use
17581 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17582 ;;; section loaded at the end of the text segment and branch forward
17583 ;;; there on bounds-failure, and then jump back immediately (in case
17584 ;;; the system chooses to ignore bounds violations, or to report
17585 ;;; violations and continue execution).
17587 (define_expand "conditional_trap"
17588 [(trap_if (match_operator 0 "comparison_operator"
17589 [(match_dup 2) (const_int 0)])
17590 (match_operand 1 "const_int_operand" ""))]
17593 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17594 ix86_expand_compare (GET_CODE (operands[0]),
17600 (define_insn "*conditional_trap_1"
17601 [(trap_if (match_operator 0 "comparison_operator"
17602 [(reg 17) (const_int 0)])
17603 (match_operand 1 "const_int_operand" ""))]
17606 operands[2] = gen_label_rtx ();
17607 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
17608 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
17609 CODE_LABEL_NUMBER (operands[2]));
17613 ;; Pentium III SIMD instructions.
17615 ;; Moves for SSE/MMX regs.
17617 (define_insn "movv4sf_internal"
17618 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17619 (match_operand:V4SF 1 "general_operand" "xm,x"))]
17621 ;; @@@ let's try to use movaps here.
17622 "movaps\t{%1, %0|%0, %1}"
17623 [(set_attr "type" "sse")])
17625 (define_insn "movv4si_internal"
17626 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17627 (match_operand:V4SI 1 "general_operand" "xm,x"))]
17629 ;; @@@ let's try to use movaps here.
17630 "movaps\t{%1, %0|%0, %1}"
17631 [(set_attr "type" "sse")])
17633 (define_insn "movv8qi_internal"
17634 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17635 (match_operand:V8QI 1 "general_operand" "ym,y"))]
17637 "movq\t{%1, %0|%0, %1}"
17638 [(set_attr "type" "mmx")])
17640 (define_insn "movv4hi_internal"
17641 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17642 (match_operand:V4HI 1 "general_operand" "ym,y"))]
17644 "movq\t{%1, %0|%0, %1}"
17645 [(set_attr "type" "mmx")])
17647 (define_insn "movv2si_internal"
17648 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17649 (match_operand:V2SI 1 "general_operand" "ym,y"))]
17651 "movq\t{%1, %0|%0, %1}"
17652 [(set_attr "type" "mmx")])
17654 (define_insn "movv2sf_internal"
17655 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
17656 (match_operand:V2SF 1 "general_operand" "ym,y"))]
17658 "movq\\t{%1, %0|%0, %1}"
17659 [(set_attr "type" "mmx")])
17661 (define_expand "movti"
17662 [(set (match_operand:TI 0 "general_operand" "")
17663 (match_operand:TI 1 "general_operand" ""))]
17664 "TARGET_SSE || TARGET_64BIT"
17668 ix86_expand_move (TImode, operands);
17671 /* For constants other than zero into memory. We do not know how the
17672 instructions used to build constants modify the upper 64 bits
17673 of the register, once we have that information we may be able
17674 to handle some of them more efficiently. */
17675 if ((reload_in_progress | reload_completed) == 0
17676 && register_operand (operands[0], TImode)
17677 && CONSTANT_P (operands[1]))
17679 rtx addr = gen_reg_rtx (Pmode);
17681 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
17682 operands[1] = gen_rtx_MEM (TImode, addr);
17685 /* Make operand1 a register if it isn't already. */
17686 if ((reload_in_progress | reload_completed) == 0
17687 && !register_operand (operands[0], TImode)
17688 && !register_operand (operands[1], TImode)
17689 && operands[1] != CONST0_RTX (TImode))
17691 rtx temp = force_reg (TImode, operands[1]);
17692 emit_move_insn (operands[0], temp);
17697 (define_expand "movv4sf"
17698 [(set (match_operand:V4SF 0 "general_operand" "")
17699 (match_operand:V4SF 1 "general_operand" ""))]
17702 /* For constants other than zero into memory. We do not know how the
17703 instructions used to build constants modify the upper 64 bits
17704 of the register, once we have that information we may be able
17705 to handle some of them more efficiently. */
17706 if ((reload_in_progress | reload_completed) == 0
17707 && register_operand (operands[0], V4SFmode)
17708 && CONSTANT_P (operands[1]))
17710 rtx addr = gen_reg_rtx (Pmode);
17712 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
17713 operands[1] = gen_rtx_MEM (V4SFmode, addr);
17716 /* Make operand1 a register if it isn't already. */
17717 if ((reload_in_progress | reload_completed) == 0
17718 && !register_operand (operands[0], V4SFmode)
17719 && !register_operand (operands[1], V4SFmode)
17720 && operands[1] != CONST0_RTX (V4SFmode))
17722 rtx temp = force_reg (V4SFmode, operands[1]);
17723 emit_move_insn (operands[0], temp);
17728 (define_expand "movv4si"
17729 [(set (match_operand:V4SI 0 "general_operand" "")
17730 (match_operand:V4SI 1 "general_operand" ""))]
17733 /* For constants other than zero into memory. We do not know how the
17734 instructions used to build constants modify the upper 64 bits
17735 of the register, once we have that information we may be able
17736 to handle some of them more efficiently. */
17737 if ((reload_in_progress | reload_completed) == 0
17738 && register_operand (operands[0], V4SImode)
17739 && CONSTANT_P (operands[1]))
17741 rtx addr = gen_reg_rtx (Pmode);
17743 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
17744 operands[1] = gen_rtx_MEM (V4SImode, addr);
17747 /* Make operand1 a register if it isn't already. */
17748 if ((reload_in_progress | reload_completed) == 0
17749 && !register_operand (operands[0], V4SImode)
17750 && !register_operand (operands[1], V4SImode)
17751 && operands[1] != CONST0_RTX (V4SImode))
17753 rtx temp = force_reg (V4SImode, operands[1]);
17754 emit_move_insn (operands[0], temp);
17759 (define_expand "movv2si"
17760 [(set (match_operand:V2SI 0 "general_operand" "")
17761 (match_operand:V2SI 1 "general_operand" ""))]
17764 /* For constants other than zero into memory. We do not know how the
17765 instructions used to build constants modify the upper 64 bits
17766 of the register, once we have that information we may be able
17767 to handle some of them more efficiently. */
17768 if ((reload_in_progress | reload_completed) == 0
17769 && register_operand (operands[0], V2SImode)
17770 && CONSTANT_P (operands[1]))
17772 rtx addr = gen_reg_rtx (Pmode);
17774 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
17775 operands[1] = gen_rtx_MEM (V2SImode, addr);
17778 /* Make operand1 a register if it isn't already. */
17779 if ((reload_in_progress | reload_completed) == 0
17780 && !register_operand (operands[0], V2SImode)
17781 && !register_operand (operands[1], V2SImode)
17782 && operands[1] != CONST0_RTX (V2SImode))
17784 rtx temp = force_reg (V2SImode, operands[1]);
17785 emit_move_insn (operands[0], temp);
17790 (define_expand "movv4hi"
17791 [(set (match_operand:V4HI 0 "general_operand" "")
17792 (match_operand:V4HI 1 "general_operand" ""))]
17795 /* For constants other than zero into memory. We do not know how the
17796 instructions used to build constants modify the upper 64 bits
17797 of the register, once we have that information we may be able
17798 to handle some of them more efficiently. */
17799 if ((reload_in_progress | reload_completed) == 0
17800 && register_operand (operands[0], V4HImode)
17801 && CONSTANT_P (operands[1]))
17803 rtx addr = gen_reg_rtx (Pmode);
17805 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
17806 operands[1] = gen_rtx_MEM (V4HImode, addr);
17809 /* Make operand1 a register if it isn't already. */
17810 if ((reload_in_progress | reload_completed) == 0
17811 && !register_operand (operands[0], V4HImode)
17812 && !register_operand (operands[1], V4HImode)
17813 && operands[1] != CONST0_RTX (V4HImode))
17815 rtx temp = force_reg (V4HImode, operands[1]);
17816 emit_move_insn (operands[0], temp);
17821 (define_expand "movv8qi"
17822 [(set (match_operand:V8QI 0 "general_operand" "")
17823 (match_operand:V8QI 1 "general_operand" ""))]
17826 /* For constants other than zero into memory. We do not know how the
17827 instructions used to build constants modify the upper 64 bits
17828 of the register, once we have that information we may be able
17829 to handle some of them more efficiently. */
17830 if ((reload_in_progress | reload_completed) == 0
17831 && register_operand (operands[0], V8QImode)
17832 && CONSTANT_P (operands[1]))
17834 rtx addr = gen_reg_rtx (Pmode);
17836 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
17837 operands[1] = gen_rtx_MEM (V8QImode, addr);
17840 /* Make operand1 a register if it isn't already. */
17841 if ((reload_in_progress | reload_completed) == 0
17842 && !register_operand (operands[0], V8QImode)
17843 && !register_operand (operands[1], V8QImode)
17844 && operands[1] != CONST0_RTX (V8QImode))
17846 rtx temp = force_reg (V8QImode, operands[1]);
17847 emit_move_insn (operands[0], temp);
17852 (define_expand "movv2sf"
17853 [(set (match_operand:V2SF 0 "general_operand" "")
17854 (match_operand:V2SF 1 "general_operand" ""))]
17858 /* For constants other than zero into memory. We do not know how the
17859 instructions used to build constants modify the upper 64 bits
17860 of the register, once we have that information we may be able
17861 to handle some of them more efficiently. */
17862 if ((reload_in_progress | reload_completed) == 0
17863 && register_operand (operands[0], V2SFmode)
17864 && CONSTANT_P (operands[1]))
17866 rtx addr = gen_reg_rtx (Pmode);
17868 emit_move_insn (addr,
17869 XEXP (force_const_mem (V2SFmode, operands[1]), 0));
17870 operands[1] = gen_rtx_MEM (V2SFmode, addr);
17873 /* Make operand1 a register is it isn't already. */
17874 if ((reload_in_progress | reload_completed) == 0
17875 && !register_operand (operands[0], V2SFmode)
17876 && !register_operand (operands[1], V2SFmode)
17877 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
17878 && operands[1] != CONST0_RTX (V2SFmode))
17880 rtx temp = force_reg (V2SFmode, operands[1]);
17881 emit_move_insn (operands[0], temp);
17886 (define_insn_and_split "*pushti"
17887 [(set (match_operand:TI 0 "push_operand" "=<")
17888 (match_operand:TI 1 "nonmemory_operand" "x"))]
17892 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17893 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17895 [(set_attr "type" "sse")])
17897 (define_insn_and_split "*pushv4sf"
17898 [(set (match_operand:V4SF 0 "push_operand" "=<")
17899 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
17903 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17904 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
17906 [(set_attr "type" "sse")])
17908 (define_insn_and_split "*pushv4si"
17909 [(set (match_operand:V4SI 0 "push_operand" "=<")
17910 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
17914 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17915 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
17917 [(set_attr "type" "sse")])
17919 (define_insn_and_split "*pushv2si"
17920 [(set (match_operand:V2SI 0 "push_operand" "=<")
17921 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
17925 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17926 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
17928 [(set_attr "type" "mmx")])
17930 (define_insn_and_split "*pushv4hi"
17931 [(set (match_operand:V4HI 0 "push_operand" "=<")
17932 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
17936 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17937 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
17939 [(set_attr "type" "mmx")])
17941 (define_insn_and_split "*pushv8qi"
17942 [(set (match_operand:V8QI 0 "push_operand" "=<")
17943 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
17947 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17948 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
17950 [(set_attr "type" "mmx")])
17952 (define_insn_and_split "*pushv2sf"
17953 [(set (match_operand:V2SF 0 "push_operand" "=<")
17954 (match_operand:V2SF 1 "nonmemory_operand" "y"))]
17958 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17959 (set (mem:V2SF (reg:SI 7)) (match_dup 1))]
17961 [(set_attr "type" "mmx")])
17963 (define_insn "movti_internal"
17964 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
17965 (match_operand:TI 1 "general_operand" "xm,x"))]
17966 "TARGET_SSE && !TARGET_64BIT"
17968 movaps\t{%1, %0|%0, %1}
17969 movaps\t{%1, %0|%0, %1}"
17970 [(set_attr "type" "sse")])
17972 (define_insn "*movti_rex64"
17973 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,mx,x")
17974 (match_operand:TI 1 "general_operand" "riFo,riF,x,m"))]
17976 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
17980 movaps\\t{%1, %0|%0, %1}
17981 movaps\\t{%1, %0|%0, %1}"
17982 [(set_attr "type" "*,*,sse,sse")
17983 (set_attr "mode" "TI")])
17986 [(set (match_operand:TI 0 "nonimmediate_operand" "")
17987 (match_operand:TI 1 "general_operand" ""))]
17988 "reload_completed && !SSE_REG_P (operands[0])
17989 && !SSE_REG_P (operands[1])"
17991 "ix86_split_long_move (operands); DONE;")
17993 ;; These two patterns are useful for specifying exactly whether to use
17994 ;; movaps or movups
17995 (define_insn "sse_movaps"
17996 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17997 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
18000 movaps\t{%1, %0|%0, %1}
18001 movaps\t{%1, %0|%0, %1}"
18002 [(set_attr "type" "sse")])
18004 (define_insn "sse_movups"
18005 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18006 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
18009 movups\t{%1, %0|%0, %1}
18010 movups\t{%1, %0|%0, %1}"
18011 [(set_attr "type" "sse")])
18014 ;; SSE Strange Moves.
18016 (define_insn "sse_movmskps"
18017 [(set (match_operand:SI 0 "register_operand" "=r")
18018 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
18020 "movmskps\t{%1, %0|%0, %1}"
18021 [(set_attr "type" "sse")])
18023 (define_insn "mmx_pmovmskb"
18024 [(set (match_operand:SI 0 "register_operand" "=r")
18025 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
18026 "TARGET_SSE || TARGET_3DNOW_A"
18027 "pmovmskb\t{%1, %0|%0, %1}"
18028 [(set_attr "type" "sse")])
18030 (define_insn "mmx_maskmovq"
18031 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
18032 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18033 (match_operand:V8QI 2 "register_operand" "y")] 32))]
18034 "TARGET_SSE || TARGET_3DNOW_A"
18035 ;; @@@ check ordering of operands in intel/nonintel syntax
18036 "maskmovq\t{%2, %1|%1, %2}"
18037 [(set_attr "type" "sse")])
18039 (define_insn "sse_movntv4sf"
18040 [(set (match_operand:V4SF 0 "memory_operand" "=m")
18041 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
18043 "movntps\t{%1, %0|%0, %1}"
18044 [(set_attr "type" "sse")])
18046 (define_insn "sse_movntdi"
18047 [(set (match_operand:DI 0 "memory_operand" "=m")
18048 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
18049 "TARGET_SSE || TARGET_3DNOW_A"
18050 "movntq\t{%1, %0|%0, %1}"
18051 [(set_attr "type" "sse")])
18053 (define_insn "sse_movhlps"
18054 [(set (match_operand:V4SF 0 "register_operand" "=x")
18056 (match_operand:V4SF 1 "register_operand" "0")
18057 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18058 (parallel [(const_int 2)
18064 "movhlps\t{%2, %0|%0, %2}"
18065 [(set_attr "type" "sse")])
18067 (define_insn "sse_movlhps"
18068 [(set (match_operand:V4SF 0 "register_operand" "=x")
18070 (match_operand:V4SF 1 "register_operand" "0")
18071 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18072 (parallel [(const_int 2)
18078 "movlhps\t{%2, %0|%0, %2}"
18079 [(set_attr "type" "sse")])
18081 (define_insn "sse_movhps"
18082 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18084 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18085 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18087 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18088 "movhps\t{%2, %0|%0, %2}"
18089 [(set_attr "type" "sse")])
18091 (define_insn "sse_movlps"
18092 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18094 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18095 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18097 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18098 "movlps\t{%2, %0|%0, %2}"
18099 [(set_attr "type" "sse")])
18101 (define_insn "sse_loadss"
18102 [(set (match_operand:V4SF 0 "register_operand" "=x")
18104 (match_operand:V4SF 1 "memory_operand" "m")
18105 (vec_duplicate:V4SF (float:SF (const_int 0)))
18108 "movss\t{%1, %0|%0, %1}"
18109 [(set_attr "type" "sse")])
18111 (define_insn "sse_movss"
18112 [(set (match_operand:V4SF 0 "register_operand" "=x")
18114 (match_operand:V4SF 1 "register_operand" "0")
18115 (match_operand:V4SF 2 "register_operand" "x")
18118 "movss\t{%2, %0|%0, %2}"
18119 [(set_attr "type" "sse")])
18121 (define_insn "sse_storess"
18122 [(set (match_operand:SF 0 "memory_operand" "=m")
18124 (match_operand:V4SF 1 "register_operand" "x")
18125 (parallel [(const_int 0)])))]
18127 "movss\t{%1, %0|%0, %1}"
18128 [(set_attr "type" "sse")])
18130 (define_insn "sse_shufps"
18131 [(set (match_operand:V4SF 0 "register_operand" "=x")
18132 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
18133 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
18134 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18136 ;; @@@ check operand order for intel/nonintel syntax
18137 "shufps\t{%3, %2, %0|%0, %2, %3}"
18138 [(set_attr "type" "sse")])
18143 (define_insn "addv4sf3"
18144 [(set (match_operand:V4SF 0 "register_operand" "=x")
18145 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18146 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18148 "addps\t{%2, %0|%0, %2}"
18149 [(set_attr "type" "sse")])
18151 (define_insn "vmaddv4sf3"
18152 [(set (match_operand:V4SF 0 "register_operand" "=x")
18153 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18154 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18158 "addss\t{%2, %0|%0, %2}"
18159 [(set_attr "type" "sse")])
18161 (define_insn "subv4sf3"
18162 [(set (match_operand:V4SF 0 "register_operand" "=x")
18163 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18164 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18166 "subps\t{%2, %0|%0, %2}"
18167 [(set_attr "type" "sse")])
18169 (define_insn "vmsubv4sf3"
18170 [(set (match_operand:V4SF 0 "register_operand" "=x")
18171 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18172 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18176 "subss\t{%2, %0|%0, %2}"
18177 [(set_attr "type" "sse")])
18179 (define_insn "mulv4sf3"
18180 [(set (match_operand:V4SF 0 "register_operand" "=x")
18181 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18182 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18184 "mulps\t{%2, %0|%0, %2}"
18185 [(set_attr "type" "sse")])
18187 (define_insn "vmmulv4sf3"
18188 [(set (match_operand:V4SF 0 "register_operand" "=x")
18189 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18190 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18194 "mulss\t{%2, %0|%0, %2}"
18195 [(set_attr "type" "sse")])
18197 (define_insn "divv4sf3"
18198 [(set (match_operand:V4SF 0 "register_operand" "=x")
18199 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18200 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18202 "divps\t{%2, %0|%0, %2}"
18203 [(set_attr "type" "sse")])
18205 (define_insn "vmdivv4sf3"
18206 [(set (match_operand:V4SF 0 "register_operand" "=x")
18207 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18208 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18212 "divss\t{%2, %0|%0, %2}"
18213 [(set_attr "type" "sse")])
18216 ;; SSE square root/reciprocal
18218 (define_insn "rcpv4sf2"
18219 [(set (match_operand:V4SF 0 "register_operand" "=x")
18220 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
18222 "rcpps\t{%1, %0|%0, %1}"
18223 [(set_attr "type" "sse")])
18225 (define_insn "vmrcpv4sf2"
18226 [(set (match_operand:V4SF 0 "register_operand" "=x")
18227 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
18228 (match_operand:V4SF 2 "register_operand" "0")
18231 "rcpss\t{%1, %0|%0, %1}"
18232 [(set_attr "type" "sse")])
18234 (define_insn "rsqrtv4sf2"
18235 [(set (match_operand:V4SF 0 "register_operand" "=x")
18236 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
18238 "rsqrtps\t{%1, %0|%0, %1}"
18239 [(set_attr "type" "sse")])
18241 (define_insn "vmrsqrtv4sf2"
18242 [(set (match_operand:V4SF 0 "register_operand" "=x")
18243 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
18244 (match_operand:V4SF 2 "register_operand" "0")
18247 "rsqrtss\t{%1, %0|%0, %1}"
18248 [(set_attr "type" "sse")])
18250 (define_insn "sqrtv4sf2"
18251 [(set (match_operand:V4SF 0 "register_operand" "=x")
18252 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
18254 "sqrtps\t{%1, %0|%0, %1}"
18255 [(set_attr "type" "sse")])
18257 (define_insn "vmsqrtv4sf2"
18258 [(set (match_operand:V4SF 0 "register_operand" "=x")
18259 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
18260 (match_operand:V4SF 2 "register_operand" "0")
18263 "sqrtss\t{%1, %0|%0, %1}"
18264 [(set_attr "type" "sse")])
18267 ;; SSE logical operations.
18269 ;; These are not called andti3 etc. because we really really don't want
18270 ;; the compiler to widen DImode ands to TImode ands and then try to move
18271 ;; into DImode subregs of SSE registers, and them together, and move out
18272 ;; of DImode subregs again!
18274 (define_insn "*sse_andti3_df_1"
18275 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18276 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18277 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18279 "andpd\t{%2, %0|%0, %2}"
18280 [(set_attr "type" "sse")])
18282 (define_insn "*sse_andti3_df_2"
18283 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18284 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18285 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18287 "andpd\t{%2, %0|%0, %2}"
18288 [(set_attr "type" "sse")])
18290 (define_insn "*sse_andti3_sf_1"
18291 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18292 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18293 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18295 "andps\t{%2, %0|%0, %2}"
18296 [(set_attr "type" "sse")])
18298 (define_insn "*sse_andti3_sf_2"
18299 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18300 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18301 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18303 "andps\t{%2, %0|%0, %2}"
18304 [(set_attr "type" "sse")])
18306 (define_insn "sse_andti3"
18307 [(set (match_operand:TI 0 "register_operand" "=x")
18308 (and:TI (match_operand:TI 1 "register_operand" "%0")
18309 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18310 "TARGET_SSE && !TARGET_SSE2"
18311 "andps\t{%2, %0|%0, %2}"
18312 [(set_attr "type" "sse")])
18314 (define_insn "*sse_andti3_sse2"
18315 [(set (match_operand:TI 0 "register_operand" "=x")
18316 (and:TI (match_operand:TI 1 "register_operand" "%0")
18317 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18319 "pand\t{%2, %0|%0, %2}"
18320 [(set_attr "type" "sse")])
18322 (define_insn "*sse_nandti3_df"
18323 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18324 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18325 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18327 "andnpd\t{%2, %0|%0, %2}"
18328 [(set_attr "type" "sse")])
18330 (define_insn "*sse_nandti3_sf"
18331 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18332 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18333 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18335 "andnps\t{%2, %0|%0, %2}"
18336 [(set_attr "type" "sse")])
18338 (define_insn "sse_nandti3"
18339 [(set (match_operand:TI 0 "register_operand" "=x")
18340 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18341 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18342 "TARGET_SSE && !TARGET_SSE2"
18343 "andnps\t{%2, %0|%0, %2}"
18344 [(set_attr "type" "sse")])
18346 (define_insn "*sse_nandti3_sse2"
18347 [(set (match_operand:TI 0 "register_operand" "=x")
18348 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18349 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18351 "pnand\t{%2, %0|%0, %2}"
18352 [(set_attr "type" "sse")])
18354 (define_insn "*sse_iorti3_df_1"
18355 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18356 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18357 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18359 "orpd\t{%2, %0|%0, %2}"
18360 [(set_attr "type" "sse")])
18362 (define_insn "*sse_iorti3_df_2"
18363 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18364 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18365 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18367 "orpd\t{%2, %0|%0, %2}"
18368 [(set_attr "type" "sse")])
18370 (define_insn "*sse_iorti3_sf_1"
18371 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18372 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18373 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18375 "orps\t{%2, %0|%0, %2}"
18376 [(set_attr "type" "sse")])
18378 (define_insn "*sse_iorti3_sf_2"
18379 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18380 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18381 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18383 "orps\t{%2, %0|%0, %2}"
18384 [(set_attr "type" "sse")])
18386 (define_insn "sse_iorti3"
18387 [(set (match_operand:TI 0 "register_operand" "=x")
18388 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18389 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18390 "TARGET_SSE && !TARGET_SSE2"
18391 "orps\t{%2, %0|%0, %2}"
18392 [(set_attr "type" "sse")])
18394 (define_insn "*sse_iorti3_sse2"
18395 [(set (match_operand:TI 0 "register_operand" "=x")
18396 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18397 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18399 "por\t{%2, %0|%0, %2}"
18400 [(set_attr "type" "sse")])
18402 (define_insn "*sse_xorti3_df_1"
18403 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18404 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18405 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18407 "xorpd\t{%2, %0|%0, %2}"
18408 [(set_attr "type" "sse")])
18410 (define_insn "*sse_xorti3_df_2"
18411 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18412 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18413 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18415 "xorpd\t{%2, %0|%0, %2}"
18416 [(set_attr "type" "sse")])
18418 (define_insn "*sse_xorti3_sf_1"
18419 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18420 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18421 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18423 "xorps\t{%2, %0|%0, %2}"
18424 [(set_attr "type" "sse")])
18426 (define_insn "*sse_xorti3_sf_2"
18427 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18428 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18429 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18431 "xorps\t{%2, %0|%0, %2}"
18432 [(set_attr "type" "sse")])
18434 (define_insn "sse_xorti3"
18435 [(set (match_operand:TI 0 "register_operand" "=x")
18436 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18437 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18438 "TARGET_SSE && !TARGET_SSE2"
18439 "xorps\t{%2, %0|%0, %2}"
18440 [(set_attr "type" "sse")])
18442 (define_insn "*sse_xorti3_sse2"
18443 [(set (match_operand:TI 0 "register_operand" "=x")
18444 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18445 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18447 "pxor\t{%2, %0|%0, %2}"
18448 [(set_attr "type" "sse")])
18450 ;; Use xor, but don't show input operands so they aren't live before
18452 (define_insn "sse_clrti"
18453 [(set (match_operand:TI 0 "register_operand" "=x")
18454 (unspec:TI [(const_int 0)] 45))]
18456 "xorps\t{%0, %0|%0, %0}"
18457 [(set_attr "type" "sse")
18458 (set_attr "memory" "none")])
18460 ;; SSE mask-generating compares
18462 (define_insn "maskcmpv4sf3"
18463 [(set (match_operand:V4SI 0 "register_operand" "=x")
18464 (match_operator:V4SI 3 "sse_comparison_operator"
18465 [(match_operand:V4SF 1 "register_operand" "0")
18466 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
18468 "cmp%D3ps\t{%2, %0|%0, %2}"
18469 [(set_attr "type" "sse")])
18471 (define_insn "maskncmpv4sf3"
18472 [(set (match_operand:V4SI 0 "register_operand" "=x")
18474 (match_operator:V4SI 3 "sse_comparison_operator"
18475 [(match_operand:V4SF 1 "register_operand" "0")
18476 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
18480 if (GET_CODE (operands[3]) == UNORDERED)
18481 return \"cmpordps\t{%2, %0|%0, %2}\";
18483 return \"cmpn%D3ps\t{%2, %0|%0, %2}\";
18485 [(set_attr "type" "sse")])
18487 (define_insn "vmmaskcmpv4sf3"
18488 [(set (match_operand:V4SI 0 "register_operand" "=x")
18490 (match_operator:V4SI 3 "sse_comparison_operator"
18491 [(match_operand:V4SF 1 "register_operand" "0")
18492 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
18496 "cmp%D3ss\t{%2, %0|%0, %2}"
18497 [(set_attr "type" "sse")])
18499 (define_insn "vmmaskncmpv4sf3"
18500 [(set (match_operand:V4SI 0 "register_operand" "=x")
18503 (match_operator:V4SI 3 "sse_comparison_operator"
18504 [(match_operand:V4SF 1 "register_operand" "0")
18505 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
18506 (subreg:V4SI (match_dup 1) 0)
18511 if (GET_CODE (operands[3]) == UNORDERED)
18512 return \"cmpordss\t{%2, %0|%0, %2}\";
18514 return \"cmpn%D3ss\t{%2, %0|%0, %2}\";
18516 [(set_attr "type" "sse")])
18518 (define_insn "sse_comi"
18519 [(set (reg:CCFP 17)
18520 (match_operator:CCFP 2 "sse_comparison_operator"
18522 (match_operand:V4SF 0 "register_operand" "x")
18523 (parallel [(const_int 0)]))
18525 (match_operand:V4SF 1 "register_operand" "x")
18526 (parallel [(const_int 0)]))]))]
18528 "comiss\t{%1, %0|%0, %1}"
18529 [(set_attr "type" "sse")])
18531 (define_insn "sse_ucomi"
18532 [(set (reg:CCFPU 17)
18533 (match_operator:CCFPU 2 "sse_comparison_operator"
18535 (match_operand:V4SF 0 "register_operand" "x")
18536 (parallel [(const_int 0)]))
18538 (match_operand:V4SF 1 "register_operand" "x")
18539 (parallel [(const_int 0)]))]))]
18541 "ucomiss\t{%1, %0|%0, %1}"
18542 [(set_attr "type" "sse")])
18547 (define_insn "sse_unpckhps"
18548 [(set (match_operand:V4SF 0 "register_operand" "=x")
18550 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18551 (parallel [(const_int 2)
18555 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18556 (parallel [(const_int 0)
18562 "unpckhps\t{%2, %0|%0, %2}"
18563 [(set_attr "type" "sse")])
18565 (define_insn "sse_unpcklps"
18566 [(set (match_operand:V4SF 0 "register_operand" "=x")
18568 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18569 (parallel [(const_int 0)
18573 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18574 (parallel [(const_int 2)
18580 "unpcklps\t{%2, %0|%0, %2}"
18581 [(set_attr "type" "sse")])
18586 (define_insn "smaxv4sf3"
18587 [(set (match_operand:V4SF 0 "register_operand" "=x")
18588 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18589 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18591 "maxps\t{%2, %0|%0, %2}"
18592 [(set_attr "type" "sse")])
18594 (define_insn "vmsmaxv4sf3"
18595 [(set (match_operand:V4SF 0 "register_operand" "=x")
18596 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18597 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18601 "maxss\t{%2, %0|%0, %2}"
18602 [(set_attr "type" "sse")])
18604 (define_insn "sminv4sf3"
18605 [(set (match_operand:V4SF 0 "register_operand" "=x")
18606 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18607 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18609 "minps\t{%2, %0|%0, %2}"
18610 [(set_attr "type" "sse")])
18612 (define_insn "vmsminv4sf3"
18613 [(set (match_operand:V4SF 0 "register_operand" "=x")
18614 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18615 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18619 "minss\t{%2, %0|%0, %2}"
18620 [(set_attr "type" "sse")])
18623 ;; SSE <-> integer/MMX conversions
18625 (define_insn "cvtpi2ps"
18626 [(set (match_operand:V4SF 0 "register_operand" "=x")
18627 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18628 (vec_duplicate:V4SF
18629 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
18632 "cvtpi2ps\t{%2, %0|%0, %2}"
18633 [(set_attr "type" "sse")])
18635 (define_insn "cvtps2pi"
18636 [(set (match_operand:V2SI 0 "register_operand" "=y")
18637 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18642 "cvtps2pi\t{%1, %0|%0, %1}"
18643 [(set_attr "type" "sse")])
18645 (define_insn "cvttps2pi"
18646 [(set (match_operand:V2SI 0 "register_operand" "=y")
18647 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18652 "cvttps2pi\t{%1, %0|%0, %1}"
18653 [(set_attr "type" "sse")])
18655 (define_insn "cvtsi2ss"
18656 [(set (match_operand:V4SF 0 "register_operand" "=x")
18657 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18658 (vec_duplicate:V4SF
18659 (float:SF (match_operand:SI 2 "register_operand" "rm")))
18662 "cvtsi2ss\t{%2, %0|%0, %2}"
18663 [(set_attr "type" "sse")])
18665 (define_insn "cvtss2si"
18666 [(set (match_operand:SI 0 "register_operand" "=r")
18667 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18668 (parallel [(const_int 0)])))]
18670 "cvtss2si\t{%1, %0|%0, %1}"
18671 [(set_attr "type" "sse")])
18673 (define_insn "cvttss2si"
18674 [(set (match_operand:SI 0 "register_operand" "=r")
18675 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18676 (parallel [(const_int 0)])))]
18678 "cvttss2si\t{%1, %0|%0, %1}"
18679 [(set_attr "type" "sse")])
18686 (define_insn "addv8qi3"
18687 [(set (match_operand:V8QI 0 "register_operand" "=y")
18688 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18689 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18691 "paddb\t{%2, %0|%0, %2}"
18692 [(set_attr "type" "mmx")])
18694 (define_insn "addv4hi3"
18695 [(set (match_operand:V4HI 0 "register_operand" "=y")
18696 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18697 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18699 "paddw\t{%2, %0|%0, %2}"
18700 [(set_attr "type" "mmx")])
18702 (define_insn "addv2si3"
18703 [(set (match_operand:V2SI 0 "register_operand" "=y")
18704 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18705 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18707 "paddd\t{%2, %0|%0, %2}"
18708 [(set_attr "type" "mmx")])
18710 (define_insn "ssaddv8qi3"
18711 [(set (match_operand:V8QI 0 "register_operand" "=y")
18712 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18713 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18715 "paddsb\t{%2, %0|%0, %2}"
18716 [(set_attr "type" "mmx")])
18718 (define_insn "ssaddv4hi3"
18719 [(set (match_operand:V4HI 0 "register_operand" "=y")
18720 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18721 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18723 "paddsw\t{%2, %0|%0, %2}"
18724 [(set_attr "type" "mmx")])
18726 (define_insn "usaddv8qi3"
18727 [(set (match_operand:V8QI 0 "register_operand" "=y")
18728 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18729 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18731 "paddusb\t{%2, %0|%0, %2}"
18732 [(set_attr "type" "mmx")])
18734 (define_insn "usaddv4hi3"
18735 [(set (match_operand:V4HI 0 "register_operand" "=y")
18736 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18737 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18739 "paddusw\t{%2, %0|%0, %2}"
18740 [(set_attr "type" "mmx")])
18742 (define_insn "subv8qi3"
18743 [(set (match_operand:V8QI 0 "register_operand" "=y")
18744 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18745 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18747 "psubb\t{%2, %0|%0, %2}"
18748 [(set_attr "type" "mmx")])
18750 (define_insn "subv4hi3"
18751 [(set (match_operand:V4HI 0 "register_operand" "=y")
18752 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18753 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18755 "psubw\t{%2, %0|%0, %2}"
18756 [(set_attr "type" "mmx")])
18758 (define_insn "subv2si3"
18759 [(set (match_operand:V2SI 0 "register_operand" "=y")
18760 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18761 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18763 "psubd\t{%2, %0|%0, %2}"
18764 [(set_attr "type" "mmx")])
18766 (define_insn "sssubv8qi3"
18767 [(set (match_operand:V8QI 0 "register_operand" "=y")
18768 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18769 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18771 "psubsb\t{%2, %0|%0, %2}"
18772 [(set_attr "type" "mmx")])
18774 (define_insn "sssubv4hi3"
18775 [(set (match_operand:V4HI 0 "register_operand" "=y")
18776 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18777 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18779 "psubsw\t{%2, %0|%0, %2}"
18780 [(set_attr "type" "mmx")])
18782 (define_insn "ussubv8qi3"
18783 [(set (match_operand:V8QI 0 "register_operand" "=y")
18784 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18785 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18787 "psubusb\t{%2, %0|%0, %2}"
18788 [(set_attr "type" "mmx")])
18790 (define_insn "ussubv4hi3"
18791 [(set (match_operand:V4HI 0 "register_operand" "=y")
18792 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18793 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18795 "psubusw\t{%2, %0|%0, %2}"
18796 [(set_attr "type" "mmx")])
18798 (define_insn "mulv4hi3"
18799 [(set (match_operand:V4HI 0 "register_operand" "=y")
18800 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
18801 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18803 "pmullw\t{%2, %0|%0, %2}"
18804 [(set_attr "type" "mmx")])
18806 (define_insn "smulv4hi3_highpart"
18807 [(set (match_operand:V4HI 0 "register_operand" "=y")
18810 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18811 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18814 "pmulhw\t{%2, %0|%0, %2}"
18815 [(set_attr "type" "mmx")])
18817 (define_insn "umulv4hi3_highpart"
18818 [(set (match_operand:V4HI 0 "register_operand" "=y")
18821 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18822 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18824 "TARGET_SSE || TARGET_3DNOW_A"
18825 "pmulhuw\t{%2, %0|%0, %2}"
18826 [(set_attr "type" "mmx")])
18828 (define_insn "mmx_pmaddwd"
18829 [(set (match_operand:V2SI 0 "register_operand" "=y")
18832 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
18833 (parallel [(const_int 0)
18835 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18836 (parallel [(const_int 0)
18839 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
18840 (parallel [(const_int 1)
18842 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
18843 (parallel [(const_int 1)
18844 (const_int 3)]))))))]
18846 "pmaddwd\t{%2, %0|%0, %2}"
18847 [(set_attr "type" "mmx")])
18850 ;; MMX logical operations
18851 ;; Note we don't want to declare these as regular iordi3 insns to prevent
18852 ;; normal code that also wants to use the FPU from getting broken.
18853 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
18854 (define_insn "mmx_iordi3"
18855 [(set (match_operand:DI 0 "register_operand" "=y")
18857 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18858 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18860 "por\t{%2, %0|%0, %2}"
18861 [(set_attr "type" "mmx")])
18863 (define_insn "mmx_xordi3"
18864 [(set (match_operand:DI 0 "register_operand" "=y")
18866 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18867 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18869 "pxor\t{%2, %0|%0, %2}"
18870 [(set_attr "type" "mmx")
18871 (set_attr "memory" "none")])
18873 ;; Same as pxor, but don't show input operands so that we don't think
18875 (define_insn "mmx_clrdi"
18876 [(set (match_operand:DI 0 "register_operand" "=y")
18877 (unspec:DI [(const_int 0)] 45))]
18879 "pxor\t{%0, %0|%0, %0}"
18880 [(set_attr "type" "mmx")])
18882 (define_insn "mmx_anddi3"
18883 [(set (match_operand:DI 0 "register_operand" "=y")
18885 [(and:DI (match_operand:DI 1 "register_operand" "0")
18886 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18888 "pand\t{%2, %0|%0, %2}"
18889 [(set_attr "type" "mmx")])
18891 (define_insn "mmx_nanddi3"
18892 [(set (match_operand:DI 0 "register_operand" "=y")
18894 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
18895 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18897 "pandn\t{%2, %0|%0, %2}"
18898 [(set_attr "type" "mmx")])
18901 ;; MMX unsigned averages/sum of absolute differences
18903 (define_insn "mmx_uavgv8qi3"
18904 [(set (match_operand:V8QI 0 "register_operand" "=y")
18906 (plus:V8QI (plus:V8QI
18907 (match_operand:V8QI 1 "register_operand" "0")
18908 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18909 (vec_const:V8QI (parallel [(const_int 1)
18918 "TARGET_SSE || TARGET_3DNOW_A"
18919 "pavgb\t{%2, %0|%0, %2}"
18920 [(set_attr "type" "sse")])
18922 (define_insn "mmx_uavgv4hi3"
18923 [(set (match_operand:V4HI 0 "register_operand" "=y")
18925 (plus:V4HI (plus:V4HI
18926 (match_operand:V4HI 1 "register_operand" "0")
18927 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18928 (vec_const:V4HI (parallel [(const_int 1)
18933 "TARGET_SSE || TARGET_3DNOW_A"
18934 "pavgw\t{%2, %0|%0, %2}"
18935 [(set_attr "type" "sse")])
18937 (define_insn "mmx_psadbw"
18938 [(set (match_operand:V8QI 0 "register_operand" "=y")
18939 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18940 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
18941 "TARGET_SSE || TARGET_3DNOW_A"
18942 "psadbw\t{%2, %0|%0, %2}"
18943 [(set_attr "type" "sse")])
18946 ;; MMX insert/extract/shuffle
18948 (define_insn "mmx_pinsrw"
18949 [(set (match_operand:V4HI 0 "register_operand" "=y")
18950 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
18951 (vec_duplicate:V4HI
18952 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
18953 (match_operand:SI 3 "immediate_operand" "i")))]
18954 "TARGET_SSE || TARGET_3DNOW_A"
18955 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
18956 [(set_attr "type" "sse")])
18958 (define_insn "mmx_pextrw"
18959 [(set (match_operand:SI 0 "register_operand" "=r")
18960 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
18962 [(match_operand:SI 2 "immediate_operand" "i")]))))]
18963 "TARGET_SSE || TARGET_3DNOW_A"
18964 "pextrw\t{%2, %1, %0|%0, %1, %2}"
18965 [(set_attr "type" "sse")])
18967 (define_insn "mmx_pshufw"
18968 [(set (match_operand:V4HI 0 "register_operand" "=y")
18969 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
18970 (match_operand:SI 2 "immediate_operand" "i")] 41))]
18971 "TARGET_SSE || TARGET_3DNOW_A"
18972 "pshufw\t{%2, %1, %0|%0, %1, %2}"
18973 [(set_attr "type" "sse")])
18976 ;; MMX mask-generating comparisons
18978 (define_insn "eqv8qi3"
18979 [(set (match_operand:V8QI 0 "register_operand" "=y")
18980 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
18981 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18983 "pcmpeqb\t{%2, %0|%0, %2}"
18984 [(set_attr "type" "mmx")])
18986 (define_insn "eqv4hi3"
18987 [(set (match_operand:V4HI 0 "register_operand" "=y")
18988 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
18989 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18991 "pcmpeqw\t{%2, %0|%0, %2}"
18992 [(set_attr "type" "mmx")])
18994 (define_insn "eqv2si3"
18995 [(set (match_operand:V2SI 0 "register_operand" "=y")
18996 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
18997 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18999 "pcmpeqd\t{%2, %0|%0, %2}"
19000 [(set_attr "type" "mmx")])
19002 (define_insn "gtv8qi3"
19003 [(set (match_operand:V8QI 0 "register_operand" "=y")
19004 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
19005 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19007 "pcmpgtb\t{%2, %0|%0, %2}"
19008 [(set_attr "type" "mmx")])
19010 (define_insn "gtv4hi3"
19011 [(set (match_operand:V4HI 0 "register_operand" "=y")
19012 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19013 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19015 "pcmpgtw\t{%2, %0|%0, %2}"
19016 [(set_attr "type" "mmx")])
19018 (define_insn "gtv2si3"
19019 [(set (match_operand:V2SI 0 "register_operand" "=y")
19020 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19021 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19023 "pcmpgtd\t{%2, %0|%0, %2}"
19024 [(set_attr "type" "mmx")])
19027 ;; MMX max/min insns
19029 (define_insn "umaxv8qi3"
19030 [(set (match_operand:V8QI 0 "register_operand" "=y")
19031 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
19032 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19033 "TARGET_SSE || TARGET_3DNOW_A"
19034 "pmaxub\t{%2, %0|%0, %2}"
19035 [(set_attr "type" "sse")])
19037 (define_insn "smaxv4hi3"
19038 [(set (match_operand:V4HI 0 "register_operand" "=y")
19039 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
19040 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19041 "TARGET_SSE || TARGET_3DNOW_A"
19042 "pmaxsw\t{%2, %0|%0, %2}"
19043 [(set_attr "type" "sse")])
19045 (define_insn "uminv8qi3"
19046 [(set (match_operand:V8QI 0 "register_operand" "=y")
19047 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
19048 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19049 "TARGET_SSE || TARGET_3DNOW_A"
19050 "pminub\t{%2, %0|%0, %2}"
19051 [(set_attr "type" "sse")])
19053 (define_insn "sminv4hi3"
19054 [(set (match_operand:V4HI 0 "register_operand" "=y")
19055 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
19056 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19057 "TARGET_SSE || TARGET_3DNOW_A"
19058 "pminsw\t{%2, %0|%0, %2}"
19059 [(set_attr "type" "sse")])
19064 (define_insn "ashrv4hi3"
19065 [(set (match_operand:V4HI 0 "register_operand" "=y")
19066 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19067 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19069 "psraw\t{%2, %0|%0, %2}"
19070 [(set_attr "type" "mmx")])
19072 (define_insn "ashrv2si3"
19073 [(set (match_operand:V2SI 0 "register_operand" "=y")
19074 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19075 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19077 "psrad\t{%2, %0|%0, %2}"
19078 [(set_attr "type" "mmx")])
19080 (define_insn "lshrv4hi3"
19081 [(set (match_operand:V4HI 0 "register_operand" "=y")
19082 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19083 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19085 "psrlw\t{%2, %0|%0, %2}"
19086 [(set_attr "type" "mmx")])
19088 (define_insn "lshrv2si3"
19089 [(set (match_operand:V2SI 0 "register_operand" "=y")
19090 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19091 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19093 "psrld\t{%2, %0|%0, %2}"
19094 [(set_attr "type" "mmx")])
19096 ;; See logical MMX insns.
19097 (define_insn "mmx_lshrdi3"
19098 [(set (match_operand:DI 0 "register_operand" "=y")
19100 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
19101 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
19103 "psrlq\t{%2, %0|%0, %2}"
19104 [(set_attr "type" "mmx")])
19106 (define_insn "ashlv4hi3"
19107 [(set (match_operand:V4HI 0 "register_operand" "=y")
19108 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
19109 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19111 "psllw\t{%2, %0|%0, %2}"
19112 [(set_attr "type" "mmx")])
19114 (define_insn "ashlv2si3"
19115 [(set (match_operand:V2SI 0 "register_operand" "=y")
19116 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
19117 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19119 "pslld\t{%2, %0|%0, %2}"
19120 [(set_attr "type" "mmx")])
19122 ;; See logical MMX insns.
19123 (define_insn "mmx_ashldi3"
19124 [(set (match_operand:DI 0 "register_operand" "=y")
19126 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
19127 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
19129 "psllq\t{%2, %0|%0, %2}"
19130 [(set_attr "type" "mmx")])
19133 ;; MMX pack/unpack insns.
19135 (define_insn "mmx_packsswb"
19136 [(set (match_operand:V8QI 0 "register_operand" "=y")
19138 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19139 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19141 "packsswb\t{%2, %0|%0, %2}"
19142 [(set_attr "type" "mmx")])
19144 (define_insn "mmx_packssdw"
19145 [(set (match_operand:V4HI 0 "register_operand" "=y")
19147 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
19148 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
19150 "packssdw\t{%2, %0|%0, %2}"
19151 [(set_attr "type" "mmx")])
19153 (define_insn "mmx_packuswb"
19154 [(set (match_operand:V8QI 0 "register_operand" "=y")
19156 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19157 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19159 "packuswb\t{%2, %0|%0, %2}"
19160 [(set_attr "type" "mmx")])
19162 (define_insn "mmx_punpckhbw"
19163 [(set (match_operand:V8QI 0 "register_operand" "=y")
19165 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19166 (parallel [(const_int 4)
19174 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19175 (parallel [(const_int 0)
19185 "punpckhbw\t{%2, %0|%0, %2}"
19186 [(set_attr "type" "mmx")])
19188 (define_insn "mmx_punpckhwd"
19189 [(set (match_operand:V4HI 0 "register_operand" "=y")
19191 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19192 (parallel [(const_int 0)
19196 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19197 (parallel [(const_int 2)
19203 "punpckhwd\t{%2, %0|%0, %2}"
19204 [(set_attr "type" "mmx")])
19206 (define_insn "mmx_punpckhdq"
19207 [(set (match_operand:V2SI 0 "register_operand" "=y")
19209 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19210 (parallel [(const_int 0)
19212 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19213 (parallel [(const_int 1)
19217 "punpckhdq\t{%2, %0|%0, %2}"
19218 [(set_attr "type" "mmx")])
19220 (define_insn "mmx_punpcklbw"
19221 [(set (match_operand:V8QI 0 "register_operand" "=y")
19223 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19224 (parallel [(const_int 0)
19232 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19233 (parallel [(const_int 4)
19243 "punpcklbw\t{%2, %0|%0, %2}"
19244 [(set_attr "type" "mmx")])
19246 (define_insn "mmx_punpcklwd"
19247 [(set (match_operand:V4HI 0 "register_operand" "=y")
19249 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19250 (parallel [(const_int 2)
19254 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19255 (parallel [(const_int 0)
19261 "punpcklwd\t{%2, %0|%0, %2}"
19262 [(set_attr "type" "mmx")])
19264 (define_insn "mmx_punpckldq"
19265 [(set (match_operand:V2SI 0 "register_operand" "=y")
19267 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19268 (parallel [(const_int 1)
19270 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19271 (parallel [(const_int 0)
19275 "punpckldq\t{%2, %0|%0, %2}"
19276 [(set_attr "type" "mmx")])
19279 ;; Miscellaneous stuff
19281 (define_insn "emms"
19282 [(unspec_volatile [(const_int 0)] 31)
19283 (clobber (reg:XF 8))
19284 (clobber (reg:XF 9))
19285 (clobber (reg:XF 10))
19286 (clobber (reg:XF 11))
19287 (clobber (reg:XF 12))
19288 (clobber (reg:XF 13))
19289 (clobber (reg:XF 14))
19290 (clobber (reg:XF 15))
19291 (clobber (reg:DI 29))
19292 (clobber (reg:DI 30))
19293 (clobber (reg:DI 31))
19294 (clobber (reg:DI 32))
19295 (clobber (reg:DI 33))
19296 (clobber (reg:DI 34))
19297 (clobber (reg:DI 35))
19298 (clobber (reg:DI 36))]
19301 [(set_attr "type" "mmx")
19302 (set_attr "memory" "unknown")])
19304 (define_insn "ldmxcsr"
19305 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
19308 [(set_attr "type" "mmx")
19309 (set_attr "memory" "load")])
19311 (define_insn "stmxcsr"
19312 [(set (match_operand:SI 0 "memory_operand" "=m")
19313 (unspec_volatile:SI [(const_int 0)] 40))]
19316 [(set_attr "type" "mmx")
19317 (set_attr "memory" "store")])
19319 (define_expand "sfence"
19320 [(set (match_dup 0)
19321 (unspec:BLK [(match_dup 0)] 44))]
19322 "TARGET_SSE || TARGET_3DNOW_A"
19324 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19325 MEM_VOLATILE_P (operands[0]) = 1;
19328 (define_insn "*sfence_insn"
19329 [(set (match_operand:BLK 0 "" "")
19330 (unspec:BLK [(match_dup 0)] 44))]
19331 "TARGET_SSE || TARGET_3DNOW_A"
19333 [(set_attr "type" "sse")
19334 (set_attr "memory" "unknown")])
19336 (define_insn "prefetch"
19337 [(unspec [(match_operand:SI 0 "address_operand" "p")
19338 (match_operand:SI 1 "immediate_operand" "n")] 35)]
19339 "TARGET_SSE || TARGET_3DNOW_A"
19341 switch (INTVAL (operands[1]))
19344 return "prefetchnta\t%a0";
19346 return "prefetcht0\t%a0";
19348 return "prefetcht1\t%a0";
19350 return "prefetcht2\t%a0";
19355 [(set_attr "type" "sse")])
19357 (define_expand "sse_prologue_save"
19358 [(parallel [(set (match_operand:BLK 0 "" "")
19359 (unspec:BLK [(reg:DI 21)
19367 (use (match_operand:DI 1 "register_operand" ""))
19368 (use (match_operand:DI 2 "immediate_operand" ""))
19369 (use (label_ref:DI (match_operand 3 "" "")))])]
19373 (define_insn "*sse_prologue_save_insn"
19374 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
19375 (match_operand:DI 4 "const_int_operand" "n")))
19376 (unspec:BLK [(reg:DI 21)
19384 (use (match_operand:DI 1 "register_operand" "r"))
19385 (use (match_operand:DI 2 "const_int_operand" "i"))
19386 (use (label_ref:DI (match_operand 3 "" "X")))]
19388 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
19389 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
19393 operands[0] = gen_rtx_MEM (Pmode,
19394 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
19395 output_asm_insn (\"jmp\\t%A1\", operands);
19396 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
19398 operands[4] = adjust_address (operands[0], DImode, i*16);
19399 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
19400 PUT_MODE (operands[4], TImode);
19401 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
19402 output_asm_insn (\"rex\", operands);
19403 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
19405 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
19406 CODE_LABEL_NUMBER (operands[3]));
19410 [(set_attr "type" "other")
19411 (set_attr "length_immediate" "0")
19412 (set_attr "length_address" "0")
19413 (set_attr "length" "135")
19414 (set_attr "memory" "store")
19415 (set_attr "modrm" "0")
19416 (set_attr "mode" "DI")])
19418 ;; 3Dnow! instructions
19420 (define_insn "addv2sf3"
19421 [(set (match_operand:V2SF 0 "register_operand" "=y")
19422 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19423 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19425 "pfadd\\t{%2, %0|%0, %2}"
19426 [(set_attr "type" "mmx")])
19428 (define_insn "subv2sf3"
19429 [(set (match_operand:V2SF 0 "register_operand" "=y")
19430 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19431 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19433 "pfsub\\t{%2, %0|%0, %2}"
19434 [(set_attr "type" "mmx")])
19436 (define_insn "subrv2sf3"
19437 [(set (match_operand:V2SF 0 "register_operand" "=y")
19438 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
19439 (match_operand:V2SF 1 "register_operand" "0")))]
19441 "pfsubr\\t{%2, %0|%0, %2}"
19442 [(set_attr "type" "mmx")])
19444 (define_insn "gtv2sf3"
19445 [(set (match_operand:V2SI 0 "register_operand" "=y")
19446 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
19447 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19449 "pfcmpgt\\t{%2, %0|%0, %2}"
19450 [(set_attr "type" "mmx")])
19452 (define_insn "gev2sf3"
19453 [(set (match_operand:V2SI 0 "register_operand" "=y")
19454 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
19455 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19457 "pfcmpge\\t{%2, %0|%0, %2}"
19458 [(set_attr "type" "mmx")])
19460 (define_insn "eqv2sf3"
19461 [(set (match_operand:V2SI 0 "register_operand" "=y")
19462 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
19463 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19465 "pfcmpeq\\t{%2, %0|%0, %2}"
19466 [(set_attr "type" "mmx")])
19468 (define_insn "pfmaxv2sf3"
19469 [(set (match_operand:V2SF 0 "register_operand" "=y")
19470 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
19471 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19473 "pfmax\\t{%2, %0|%0, %2}"
19474 [(set_attr "type" "mmx")])
19476 (define_insn "pfminv2sf3"
19477 [(set (match_operand:V2SF 0 "register_operand" "=y")
19478 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
19479 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19481 "pfmin\\t{%2, %0|%0, %2}"
19482 [(set_attr "type" "mmx")])
19484 (define_insn "mulv2sf3"
19485 [(set (match_operand:V2SF 0 "register_operand" "=y")
19486 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
19487 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19489 "pfmul\\t{%2, %0|%0, %2}"
19490 [(set_attr "type" "mmx")])
19492 (define_insn "femms"
19493 [(unspec_volatile [(const_int 0)] 46)
19494 (clobber (reg:XF 8))
19495 (clobber (reg:XF 9))
19496 (clobber (reg:XF 10))
19497 (clobber (reg:XF 11))
19498 (clobber (reg:XF 12))
19499 (clobber (reg:XF 13))
19500 (clobber (reg:XF 14))
19501 (clobber (reg:XF 15))
19502 (clobber (reg:DI 29))
19503 (clobber (reg:DI 30))
19504 (clobber (reg:DI 31))
19505 (clobber (reg:DI 32))
19506 (clobber (reg:DI 33))
19507 (clobber (reg:DI 34))
19508 (clobber (reg:DI 35))
19509 (clobber (reg:DI 36))]
19512 [(set_attr "type" "mmx")])
19514 (define_insn "prefetch_3dnow"
19515 [(unspec [(match_operand:SI 0 "address_operand" "p")] 47)]
19518 [(set_attr "type" "mmx")])
19520 (define_insn "prefetchw"
19521 [(unspec [(match_operand:SI 0 "address_operand" "p")] 48)]
19524 [(set_attr "type" "mmx")])
19526 (define_insn "pf2id"
19527 [(set (match_operand:V2SI 0 "register_operand" "=y")
19528 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
19530 "pf2id\\t{%1, %0|%0, %1}"
19531 [(set_attr "type" "mmx")])
19533 (define_insn "pf2iw"
19534 [(set (match_operand:V2SI 0 "register_operand" "=y")
19537 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
19539 "pf2iw\\t{%1, %0|%0, %1}"
19540 [(set_attr "type" "mmx")])
19542 (define_insn "pfacc"
19543 [(set (match_operand:V2SF 0 "register_operand" "=y")
19546 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19547 (parallel [(const_int 0)]))
19548 (vec_select:SF (match_dup 1)
19549 (parallel [(const_int 1)])))
19551 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19552 (parallel [(const_int 0)]))
19553 (vec_select:SF (match_dup 2)
19554 (parallel [(const_int 1)])))))]
19556 "pfacc\\t{%2, %0|%0, %2}"
19557 [(set_attr "type" "mmx")])
19559 (define_insn "pfnacc"
19560 [(set (match_operand:V2SF 0 "register_operand" "=y")
19563 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19564 (parallel [(const_int 0)]))
19565 (vec_select:SF (match_dup 1)
19566 (parallel [(const_int 1)])))
19568 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19569 (parallel [(const_int 0)]))
19570 (vec_select:SF (match_dup 2)
19571 (parallel [(const_int 1)])))))]
19573 "pfnacc\\t{%2, %0|%0, %2}"
19574 [(set_attr "type" "mmx")])
19576 (define_insn "pfpnacc"
19577 [(set (match_operand:V2SF 0 "register_operand" "=y")
19580 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19581 (parallel [(const_int 0)]))
19582 (vec_select:SF (match_dup 1)
19583 (parallel [(const_int 1)])))
19585 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19586 (parallel [(const_int 0)]))
19587 (vec_select:SF (match_dup 2)
19588 (parallel [(const_int 1)])))))]
19590 "pfpnacc\\t{%2, %0|%0, %2}"
19591 [(set_attr "type" "mmx")])
19593 (define_insn "pi2fw"
19594 [(set (match_operand:V2SF 0 "register_operand" "=y")
19599 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19600 (parallel [(const_int 0)]))))
19603 (vec_select:SI (match_dup 1)
19604 (parallel [(const_int 1)])))))))]
19606 "pi2fw\\t{%1, %0|%0, %1}"
19607 [(set_attr "type" "mmx")])
19609 (define_insn "floatv2si2"
19610 [(set (match_operand:V2SF 0 "register_operand" "=y")
19611 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
19613 "pi2fd\\t{%1, %0|%0, %1}"
19614 [(set_attr "type" "mmx")])
19616 ;; This insn is identical to pavgb in operation, but the opcode is
19617 ;; different. To avoid accidentally matching pavgb, use an unspec.
19619 (define_insn "pavgusb"
19620 [(set (match_operand:V8QI 0 "register_operand" "=y")
19622 [(match_operand:V8QI 1 "register_operand" "0")
19623 (match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))]
19625 "pavgusb\\t{%2, %0|%0, %2}"
19626 [(set_attr "type" "mmx")])
19628 ;; 3DNow reciprical and sqrt
19630 (define_insn "pfrcpv2sf2"
19631 [(set (match_operand:V2SF 0 "register_operand" "=y")
19632 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))]
19634 "pfrcp\\t{%1, %0|%0, %1}"
19635 [(set_attr "type" "mmx")])
19637 (define_insn "pfrcpit1v2sf3"
19638 [(set (match_operand:V2SF 0 "register_operand" "=y")
19639 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19640 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))]
19642 "pfrcpit1\\t{%2, %0|%0, %2}"
19643 [(set_attr "type" "mmx")])
19645 (define_insn "pfrcpit2v2sf3"
19646 [(set (match_operand:V2SF 0 "register_operand" "=y")
19647 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19648 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))]
19650 "pfrcpit2\\t{%2, %0|%0, %2}"
19651 [(set_attr "type" "mmx")])
19653 (define_insn "pfrsqrtv2sf2"
19654 [(set (match_operand:V2SF 0 "register_operand" "=y")
19655 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))]
19657 "pfrsqrt\\t{%1, %0|%0, %1}"
19658 [(set_attr "type" "mmx")])
19660 (define_insn "pfrsqit1v2sf3"
19661 [(set (match_operand:V2SF 0 "register_operand" "=y")
19662 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19663 (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))]
19665 "pfrsqit1\\t{%2, %0|%0, %2}"
19666 [(set_attr "type" "mmx")])
19668 (define_insn "pmulhrwv4hi3"
19669 [(set (match_operand:V4HI 0 "register_operand" "=y")
19675 (match_operand:V4HI 1 "register_operand" "0"))
19677 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19679 (parallel [(const_int 32768)
19682 (const_int 32768)])))
19685 "pmulhrw\\t{%2, %0|%0, %2}"
19686 [(set_attr "type" "mmx")])
19688 (define_insn "pswapdv2si2"
19689 [(set (match_operand:V2SI 0 "register_operand" "=y")
19690 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19691 (parallel [(const_int 1) (const_int 0)])))]
19693 "pswapd\\t{%1, %0|%0, %1}"
19694 [(set_attr "type" "mmx")])
19696 (define_insn "pswapdv2sf2"
19697 [(set (match_operand:V2SF 0 "register_operand" "=y")
19698 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
19699 (parallel [(const_int 1) (const_int 0)])))]
19701 "pswapd\\t{%1, %0|%0, %1}"
19702 [(set_attr "type" "mmx")])