1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
54 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55 ;; operand 0 is the memory address to scan.
56 ;; operand 1 is a register containing the value to scan for. The mode
57 ;; of the scas opcode will be the same as the mode of this operand.
58 ;; operand 2 is the known alignment of operand 0.
59 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60 ;; operand 0 is the argument for `sin'.
61 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62 ;; operand 0 is the argument for `cos'.
63 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64 ;; always SImode. operand 0 is the size of the stack allocation.
65 ;; 4 This is the source of a fake SET of the frame pointer which is used to
66 ;; prevent insns referencing it being scheduled across the initial
67 ;; decrement of the stack pointer.
68 ;; 5 This is a `bsf' operation.
69 ;; 6 This is the @GOT offset of a PIC address.
70 ;; 7 This is the @GOTOFF offset of a PIC address.
71 ;; 8 This is a reference to a symbol's @PLT address.
72 ;; 9 This is an `fnstsw' operation.
73 ;; 10 This is a `sahf' operation.
74 ;; 11 This is a `fstcw' operation
75 ;; 12 This is behaviour of add when setting carry flag.
76 ;; 13 This is a `eh_return' placeholder.
78 ;; For SSE/MMX support:
79 ;; 30 This is `fix', guaranteed to be truncating.
80 ;; 31 This is a `emms' operation.
81 ;; 32 This is a `maskmov' operation.
82 ;; 33 This is a `movmsk' operation.
83 ;; 34 This is a `non-temporal' move.
84 ;; 35 This is a `prefetch' operation.
85 ;; 36 This is used to distinguish COMISS from UCOMISS.
86 ;; 37 This is a `ldmxcsr' operation.
87 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
88 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
89 ;; 40 This is a `stmxcsr' operation.
90 ;; 41 This is a `shuffle' operation.
91 ;; 42 This is a `rcp' operation.
92 ;; 43 This is a `rsqsrt' operation.
93 ;; 44 This is a `sfence' operation.
94 ;; 45 This is a noop to prevent excessive combiner cleverness.
96 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
100 ;; Processor type. This attribute must exactly match the processor_type
101 ;; enumeration in i386.h.
102 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
103 (const (symbol_ref "ix86_cpu")))
105 ;; A basic instruction type. Refinements due to arguments to be
106 ;; provided in other attributes.
108 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
109 (const_string "other"))
111 ;; Main data type used by the insn
112 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
113 (const_string "unknown"))
115 ;; Set for i387 operations.
116 (define_attr "i387" ""
117 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
121 ;; The (bounding maximum) length of an instruction immediate.
122 (define_attr "length_immediate" ""
123 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
127 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
128 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
129 (eq_attr "type" "imov,test")
130 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
131 (eq_attr "type" "call")
132 (if_then_else (match_operand 0 "constant_call_address_operand" "")
135 (eq_attr "type" "callv")
136 (if_then_else (match_operand 1 "constant_call_address_operand" "")
139 (eq_attr "type" "ibr")
140 (if_then_else (and (ge (minus (match_dup 0) (pc))
142 (lt (minus (match_dup 0) (pc))
147 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
149 ;; The (bounding maximum) length of an instruction address.
150 (define_attr "length_address" ""
151 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
153 (and (eq_attr "type" "call")
154 (match_operand 1 "constant_call_address_operand" ""))
156 (and (eq_attr "type" "callv")
157 (match_operand 1 "constant_call_address_operand" ""))
160 (symbol_ref "ix86_attr_length_address_default (insn)")))
162 ;; Set when length prefix is used.
163 (define_attr "prefix_data16" ""
164 (if_then_else (eq_attr "mode" "HI")
168 ;; Set when string REP prefix is used.
169 (define_attr "prefix_rep" "" (const_int 0))
171 ;; Set when 0f opcode prefix is used.
172 (define_attr "prefix_0f" ""
173 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
177 ;; Set when modrm byte is used.
178 (define_attr "modrm" ""
179 (cond [(eq_attr "type" "str,cld")
183 (and (eq_attr "type" "incdec")
184 (ior (match_operand:SI 1 "register_operand" "")
185 (match_operand:HI 1 "register_operand" "")))
187 (and (eq_attr "type" "push")
188 (not (match_operand 1 "memory_operand" "")))
190 (and (eq_attr "type" "pop")
191 (not (match_operand 0 "memory_operand" "")))
193 (and (eq_attr "type" "imov")
194 (and (match_operand 0 "register_operand" "")
195 (match_operand 1 "immediate_operand" "")))
200 ;; The (bounding maximum) length of an instruction in bytes.
201 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
202 ;; to split it and compute proper length as for other insns.
203 (define_attr "length" ""
204 (cond [(eq_attr "type" "other,multi,fistp")
207 (plus (plus (attr "modrm")
208 (plus (attr "prefix_0f")
211 (plus (attr "prefix_rep")
212 (plus (attr "prefix_data16")
213 (plus (attr "length_immediate")
214 (attr "length_address")))))))
216 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
217 ;; `store' if there is a simple memory reference therein, or `unknown'
218 ;; if the instruction is complex.
220 (define_attr "memory" "none,load,store,both,unknown"
221 (cond [(eq_attr "type" "other,multi,str")
222 (const_string "unknown")
223 (eq_attr "type" "lea,fcmov,fpspc,cld")
224 (const_string "none")
225 (eq_attr "type" "fistp")
226 (const_string "both")
227 (eq_attr "type" "push")
228 (if_then_else (match_operand 1 "memory_operand" "")
229 (const_string "both")
230 (const_string "store"))
231 (eq_attr "type" "pop,setcc")
232 (if_then_else (match_operand 0 "memory_operand" "")
233 (const_string "both")
234 (const_string "load"))
235 (eq_attr "type" "icmp,test")
236 (if_then_else (ior (match_operand 0 "memory_operand" "")
237 (match_operand 1 "memory_operand" ""))
238 (const_string "load")
239 (const_string "none"))
240 (eq_attr "type" "ibr")
241 (if_then_else (match_operand 0 "memory_operand" "")
242 (const_string "load")
243 (const_string "none"))
244 (eq_attr "type" "call")
245 (if_then_else (match_operand 0 "constant_call_address_operand" "")
246 (const_string "none")
247 (const_string "load"))
248 (eq_attr "type" "callv")
249 (if_then_else (match_operand 1 "constant_call_address_operand" "")
250 (const_string "none")
251 (const_string "load"))
252 (and (eq_attr "type" "alu1,negnot")
253 (match_operand 1 "memory_operand" ""))
254 (const_string "both")
255 (and (match_operand 0 "memory_operand" "")
256 (match_operand 1 "memory_operand" ""))
257 (const_string "both")
258 (match_operand 0 "memory_operand" "")
259 (const_string "store")
260 (match_operand 1 "memory_operand" "")
261 (const_string "load")
262 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
263 (match_operand 2 "memory_operand" ""))
264 (const_string "load")
265 (and (eq_attr "type" "icmov")
266 (match_operand 3 "memory_operand" ""))
267 (const_string "load")
269 (const_string "none")))
271 ;; Indicates if an instruction has both an immediate and a displacement.
273 (define_attr "imm_disp" "false,true,unknown"
274 (cond [(eq_attr "type" "other,multi")
275 (const_string "unknown")
276 (and (eq_attr "type" "icmp,test,imov")
277 (and (match_operand 0 "memory_displacement_operand" "")
278 (match_operand 1 "immediate_operand" "")))
279 (const_string "true")
280 (and (eq_attr "type" "alu,ishift,imul,idiv")
281 (and (match_operand 0 "memory_displacement_operand" "")
282 (match_operand 2 "immediate_operand" "")))
283 (const_string "true")
285 (const_string "false")))
287 ;; Indicates if an FP operation has an integer source.
289 (define_attr "fp_int_src" "false,true"
290 (const_string "false"))
292 ;; Describe a user's asm statement.
293 (define_asm_attributes
294 [(set_attr "length" "128")
295 (set_attr "type" "multi")])
297 ;; Pentium Scheduling
299 ;; The Pentium is an in-order core with two integer pipelines.
301 ;; True for insns that behave like prefixed insns on the Pentium.
302 (define_attr "pent_prefix" "false,true"
303 (if_then_else (ior (eq_attr "prefix_0f" "1")
304 (ior (eq_attr "prefix_data16" "1")
305 (eq_attr "prefix_rep" "1")))
306 (const_string "true")
307 (const_string "false")))
309 ;; Categorize how an instruction slots.
311 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
312 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
313 ;; rules, because it results in noticeably better code on non-MMX Pentium
314 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
315 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
317 (define_attr "pent_pair" "uv,pu,pv,np"
318 (cond [(eq_attr "imm_disp" "true")
320 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
321 (and (eq_attr "type" "pop,push")
322 (eq_attr "memory" "!both")))
323 (if_then_else (eq_attr "pent_prefix" "true")
326 (eq_attr "type" "ibr")
328 (and (eq_attr "type" "ishift")
329 (match_operand 2 "const_int_operand" ""))
331 (and (eq_attr "type" "call")
332 (match_operand 0 "constant_call_address_operand" ""))
334 (and (eq_attr "type" "callv")
335 (match_operand 1 "constant_call_address_operand" ""))
338 (const_string "np")))
340 ;; Rough readiness numbers. Fine tuning happens in i386.c.
342 ;; u describes pipe U
343 ;; v describes pipe V
344 ;; uv describes either pipe U or V for those that can issue to either
345 ;; np describes not paring
347 ;; fpm describes fp insns of different types are not pipelined.
349 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
351 (define_function_unit "pent_np" 1 0
352 (and (eq_attr "cpu" "pentium")
353 (eq_attr "type" "imul"))
356 (define_function_unit "pent_mul" 1 1
357 (and (eq_attr "cpu" "pentium")
358 (eq_attr "type" "imul"))
361 ;; Rep movs takes minimally 12 cycles.
362 (define_function_unit "pent_np" 1 0
363 (and (eq_attr "cpu" "pentium")
364 (eq_attr "type" "str"))
367 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
368 (define_function_unit "pent_np" 1 0
369 (and (eq_attr "cpu" "pentium")
370 (eq_attr "type" "idiv"))
373 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
374 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
375 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
376 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
377 ; like normal fp operation and fist takes 6 cycles.
379 (define_function_unit "fpu" 1 0
380 (and (eq_attr "cpu" "pentium")
381 (and (eq_attr "type" "fmov")
382 (and (eq_attr "memory" "load,store")
383 (eq_attr "mode" "XF"))))
386 (define_function_unit "pent_np" 1 0
387 (and (eq_attr "cpu" "pentium")
388 (and (eq_attr "type" "fmov")
389 (and (eq_attr "memory" "load,store")
390 (eq_attr "mode" "XF"))))
393 (define_function_unit "fpu" 1 0
394 (and (eq_attr "cpu" "pentium")
395 (and (eq_attr "type" "fmov")
396 (ior (match_operand 1 "immediate_operand" "")
397 (eq_attr "memory" "store"))))
400 (define_function_unit "pent_np" 1 0
401 (and (eq_attr "cpu" "pentium")
402 (and (eq_attr "type" "fmov")
403 (ior (match_operand 1 "immediate_operand" "")
404 (eq_attr "memory" "store"))))
407 (define_function_unit "pent_np" 1 0
408 (and (eq_attr "cpu" "pentium")
409 (eq_attr "type" "cld"))
412 (define_function_unit "fpu" 1 0
413 (and (eq_attr "cpu" "pentium")
414 (and (eq_attr "type" "fmov")
415 (eq_attr "memory" "none,load")))
418 ; Read/Modify/Write instructions usually take 3 cycles.
419 (define_function_unit "pent_u" 1 0
420 (and (eq_attr "cpu" "pentium")
421 (and (eq_attr "type" "alu,alu1,ishift")
422 (and (eq_attr "pent_pair" "pu")
423 (eq_attr "memory" "both"))))
426 (define_function_unit "pent_uv" 2 0
427 (and (eq_attr "cpu" "pentium")
428 (and (eq_attr "type" "alu,alu1,ishift")
429 (and (eq_attr "pent_pair" "!np")
430 (eq_attr "memory" "both"))))
433 (define_function_unit "pent_np" 1 0
434 (and (eq_attr "cpu" "pentium")
435 (and (eq_attr "type" "alu,alu1,negnot,ishift")
436 (and (eq_attr "pent_pair" "np")
437 (eq_attr "memory" "both"))))
440 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
441 (define_function_unit "pent_u" 1 0
442 (and (eq_attr "cpu" "pentium")
443 (and (eq_attr "type" "alu,ishift")
444 (and (eq_attr "pent_pair" "pu")
445 (eq_attr "memory" "load,store"))))
448 (define_function_unit "pent_uv" 2 0
449 (and (eq_attr "cpu" "pentium")
450 (and (eq_attr "type" "alu,ishift")
451 (and (eq_attr "pent_pair" "!np")
452 (eq_attr "memory" "load,store"))))
455 (define_function_unit "pent_np" 1 0
456 (and (eq_attr "cpu" "pentium")
457 (and (eq_attr "type" "alu,ishift")
458 (and (eq_attr "pent_pair" "np")
459 (eq_attr "memory" "load,store"))))
462 ; Insns w/o memory operands and move instructions usually take one cycle.
463 (define_function_unit "pent_u" 1 0
464 (and (eq_attr "cpu" "pentium")
465 (eq_attr "pent_pair" "pu"))
468 (define_function_unit "pent_v" 1 0
469 (and (eq_attr "cpu" "pentium")
470 (eq_attr "pent_pair" "pv"))
473 (define_function_unit "pent_uv" 2 0
474 (and (eq_attr "cpu" "pentium")
475 (eq_attr "pent_pair" "!np"))
478 (define_function_unit "pent_np" 1 0
479 (and (eq_attr "cpu" "pentium")
480 (eq_attr "pent_pair" "np"))
483 ; Pairable insns only conflict with other non-pairable insns.
484 (define_function_unit "pent_np" 1 0
485 (and (eq_attr "cpu" "pentium")
486 (and (eq_attr "type" "alu,alu1,ishift")
487 (and (eq_attr "pent_pair" "!np")
488 (eq_attr "memory" "both"))))
490 [(eq_attr "pent_pair" "np")])
492 (define_function_unit "pent_np" 1 0
493 (and (eq_attr "cpu" "pentium")
494 (and (eq_attr "type" "alu,alu1,ishift")
495 (and (eq_attr "pent_pair" "!np")
496 (eq_attr "memory" "load,store"))))
498 [(eq_attr "pent_pair" "np")])
500 (define_function_unit "pent_np" 1 0
501 (and (eq_attr "cpu" "pentium")
502 (eq_attr "pent_pair" "!np"))
504 [(eq_attr "pent_pair" "np")])
506 ; Floating point instructions usually blocks cycle longer when combined with
507 ; integer instructions, because of the inpaired fxch instruction.
508 (define_function_unit "pent_np" 1 0
509 (and (eq_attr "cpu" "pentium")
510 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp"))
512 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp")])
514 (define_function_unit "fpu" 1 0
515 (and (eq_attr "cpu" "pentium")
516 (eq_attr "type" "fcmp,fxch,fsgn"))
519 ; Addition takes 3 cycles; assume other random cruft does as well.
520 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
521 (define_function_unit "fpu" 1 0
522 (and (eq_attr "cpu" "pentium")
523 (eq_attr "type" "fop,fop1,fistp"))
526 ; Multiplication takes 3 cycles and is only half pipelined.
527 (define_function_unit "fpu" 1 0
528 (and (eq_attr "cpu" "pentium")
529 (eq_attr "type" "fmul"))
532 (define_function_unit "pent_mul" 1 1
533 (and (eq_attr "cpu" "pentium")
534 (eq_attr "type" "fmul"))
537 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
538 ; They can overlap with integer insns. Only the last two cycles can overlap
539 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
540 ; Only last two cycles of fsin/fcos can overlap with other instructions.
541 (define_function_unit "fpu" 1 0
542 (and (eq_attr "cpu" "pentium")
543 (eq_attr "type" "fdiv"))
546 (define_function_unit "pent_mul" 1 1
547 (and (eq_attr "cpu" "pentium")
548 (eq_attr "type" "fdiv"))
551 (define_function_unit "fpu" 1 0
552 (and (eq_attr "cpu" "pentium")
553 (eq_attr "type" "fpspc"))
556 (define_function_unit "pent_mul" 1 1
557 (and (eq_attr "cpu" "pentium")
558 (eq_attr "type" "fpspc"))
561 ;; Pentium Pro/PII Scheduling
563 ;; The PPro has an out-of-order core, but the instruction decoders are
564 ;; naturally in-order and asymmetric. We get best performance by scheduling
565 ;; for the decoders, for in doing so we give the oo execution unit the
568 ;; Categorize how many uops an ia32 instruction evaluates to:
569 ;; one -- an instruction with 1 uop can be decoded by any of the
571 ;; few -- an instruction with 1 to 4 uops can be decoded only by
573 ;; many -- a complex instruction may take an unspecified number of
574 ;; cycles to decode in decoder 0.
576 (define_attr "ppro_uops" "one,few,many"
577 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
578 (const_string "many")
579 (eq_attr "type" "icmov,fcmov,str,cld")
581 (eq_attr "type" "imov")
582 (if_then_else (eq_attr "memory" "store,both")
584 (const_string "one"))
585 (eq_attr "memory" "!none")
588 (const_string "one")))
590 ;; Rough readiness numbers. Fine tuning happens in i386.c.
592 ;; p0 describes port 0.
593 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
594 ;; p2 describes port 2 for loads.
595 ;; p34 describes ports 3 and 4 for stores.
596 ;; fpu describes the fpu accessed via port 0.
597 ;; ??? It is less than clear if there are separate fadd and fmul units
598 ;; that could operate in parallel.
600 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
602 (define_function_unit "ppro_p0" 1 0
603 (and (eq_attr "cpu" "pentiumpro")
604 (eq_attr "type" "ishift,lea,ibr,cld"))
607 (define_function_unit "ppro_p0" 1 0
608 (and (eq_attr "cpu" "pentiumpro")
609 (eq_attr "type" "imul"))
612 ;; ??? Does the divider lock out the pipe while it works,
613 ;; or is there a disconnected unit?
614 (define_function_unit "ppro_p0" 1 0
615 (and (eq_attr "cpu" "pentiumpro")
616 (eq_attr "type" "idiv"))
619 (define_function_unit "ppro_p0" 1 0
620 (and (eq_attr "cpu" "pentiumpro")
621 (eq_attr "type" "fop,fop1,fsgn,fistp"))
624 (define_function_unit "ppro_p0" 1 0
625 (and (eq_attr "cpu" "pentiumpro")
626 (eq_attr "type" "fcmov"))
629 (define_function_unit "ppro_p0" 1 0
630 (and (eq_attr "cpu" "pentiumpro")
631 (eq_attr "type" "fcmp"))
634 (define_function_unit "ppro_p0" 1 0
635 (and (eq_attr "cpu" "pentiumpro")
636 (eq_attr "type" "fmov"))
639 (define_function_unit "ppro_p0" 1 0
640 (and (eq_attr "cpu" "pentiumpro")
641 (eq_attr "type" "fmul"))
644 (define_function_unit "ppro_p0" 1 0
645 (and (eq_attr "cpu" "pentiumpro")
646 (eq_attr "type" "fdiv,fpspc"))
649 (define_function_unit "ppro_p01" 2 0
650 (and (eq_attr "cpu" "pentiumpro")
651 (eq_attr "type" "!imov,fmov"))
654 (define_function_unit "ppro_p01" 2 0
655 (and (and (eq_attr "cpu" "pentiumpro")
656 (eq_attr "type" "imov,fmov"))
657 (eq_attr "memory" "none"))
660 (define_function_unit "ppro_p2" 1 0
661 (and (eq_attr "cpu" "pentiumpro")
662 (ior (eq_attr "type" "pop")
663 (eq_attr "memory" "load,both")))
666 (define_function_unit "ppro_p34" 1 0
667 (and (eq_attr "cpu" "pentiumpro")
668 (ior (eq_attr "type" "push")
669 (eq_attr "memory" "store,both")))
672 (define_function_unit "fpu" 1 0
673 (and (eq_attr "cpu" "pentiumpro")
674 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov,fistp"))
677 (define_function_unit "fpu" 1 0
678 (and (eq_attr "cpu" "pentiumpro")
679 (eq_attr "type" "fmul"))
682 (define_function_unit "fpu" 1 0
683 (and (eq_attr "cpu" "pentiumpro")
684 (eq_attr "type" "fdiv,fpspc"))
687 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
688 (define_function_unit "fpu" 1 0
689 (and (eq_attr "cpu" "pentiumpro")
690 (eq_attr "type" "imul"))
693 ;; AMD K6/K6-2 Scheduling
695 ;; The K6 has similar architecture to PPro. Important difference is, that
696 ;; there are only two decoders and they seems to be much slower than execution
697 ;; units. So we have to pay much more attention to proper decoding for
698 ;; schedulers. We share most of scheduler code for PPro in i386.c
700 ;; The fp unit is not pipelined and do one operation per two cycles including
703 ;; alu describes both ALU units (ALU-X and ALU-Y).
704 ;; alux describes X alu unit
705 ;; fpu describes FPU unit
706 ;; load describes load unit.
707 ;; branch describes branch unit.
708 ;; store decsribes store unit. This unit is not modelled completely and only
709 ;; used to model lea operation. Otherwise it lie outside of the critical
712 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
714 ;; The decoder specification is in the PPro section above!
716 ;; Shift instructions and certain arithmetic are issued only to X pipe.
717 (define_function_unit "k6_alux" 1 0
718 (and (eq_attr "cpu" "k6")
719 (eq_attr "type" "ishift,alu1,negnot,cld"))
722 ;; The QI mode arithmetic is issued to X pipe only.
723 (define_function_unit "k6_alux" 1 0
724 (and (eq_attr "cpu" "k6")
725 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
726 (match_operand:QI 0 "general_operand" "")))
729 (define_function_unit "k6_alu" 2 0
730 (and (eq_attr "cpu" "k6")
731 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
734 (define_function_unit "k6_alu" 2 0
735 (and (eq_attr "cpu" "k6")
736 (and (eq_attr "type" "imov")
737 (eq_attr "memory" "none")))
740 (define_function_unit "k6_branch" 1 0
741 (and (eq_attr "cpu" "k6")
742 (eq_attr "type" "call,callv,ibr"))
745 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
746 (define_function_unit "k6_load" 1 0
747 (and (eq_attr "cpu" "k6")
748 (ior (eq_attr "type" "pop")
749 (eq_attr "memory" "load,both")))
752 (define_function_unit "k6_load" 1 0
753 (and (eq_attr "cpu" "k6")
754 (and (eq_attr "type" "str")
755 (eq_attr "memory" "load,both")))
758 ;; Lea have two instructions, so latency is probably 2
759 (define_function_unit "k6_store" 1 0
760 (and (eq_attr "cpu" "k6")
761 (eq_attr "type" "lea"))
764 (define_function_unit "k6_store" 1 0
765 (and (eq_attr "cpu" "k6")
766 (eq_attr "type" "str"))
769 (define_function_unit "k6_store" 1 0
770 (and (eq_attr "cpu" "k6")
771 (ior (eq_attr "type" "push")
772 (eq_attr "memory" "store,both")))
775 (define_function_unit "k6_fpu" 1 1
776 (and (eq_attr "cpu" "k6")
777 (eq_attr "type" "fop,fop1,fmov,fcmp,fistp"))
780 (define_function_unit "k6_fpu" 1 1
781 (and (eq_attr "cpu" "k6")
782 (eq_attr "type" "fmul"))
786 (define_function_unit "k6_fpu" 1 1
787 (and (eq_attr "cpu" "k6")
788 (eq_attr "type" "fdiv,fpspc"))
791 (define_function_unit "k6_alu" 2 0
792 (and (eq_attr "cpu" "k6")
793 (eq_attr "type" "imul"))
796 (define_function_unit "k6_alux" 1 0
797 (and (eq_attr "cpu" "k6")
798 (eq_attr "type" "imul"))
802 (define_function_unit "k6_alu" 2 0
803 (and (eq_attr "cpu" "k6")
804 (eq_attr "type" "idiv"))
807 (define_function_unit "k6_alux" 1 0
808 (and (eq_attr "cpu" "k6")
809 (eq_attr "type" "idiv"))
812 ;; AMD Athlon Scheduling
814 ;; The Athlon does contain three pipelined FP units, three integer units and
815 ;; three address generation units.
817 ;; The predecode logic is determining boundaries of instructions in the 64
818 ;; byte cache line. So the cache line straddling problem of K6 might be issue
819 ;; here as well, but it is not noted in the documentation.
821 ;; Three DirectPath instructions decoders and only one VectorPath decoder
822 ;; is available. They can decode three DirectPath instructions or one VectorPath
823 ;; instruction per cycle.
824 ;; Decoded macro instructions are then passed to 72 entry instruction control
826 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
828 ;; The load/store queue unit is not attached to the schedulers but
829 ;; communicates with all the execution units seperately instead.
831 (define_attr "athlon_decode" "direct,vector"
832 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
833 (const_string "vector")
834 (and (eq_attr "type" "push")
835 (match_operand 1 "memory_operand" ""))
836 (const_string "vector")
837 (and (eq_attr "type" "fmov")
838 (and (eq_attr "memory" "load,store")
839 (eq_attr "mode" "XF")))
840 (const_string "vector")]
841 (const_string "direct")))
843 (define_function_unit "athlon_vectordec" 1 0
844 (and (eq_attr "cpu" "athlon")
845 (eq_attr "athlon_decode" "vector"))
848 (define_function_unit "athlon_directdec" 3 0
849 (and (eq_attr "cpu" "athlon")
850 (eq_attr "athlon_decode" "direct"))
853 (define_function_unit "athlon_vectordec" 1 0
854 (and (eq_attr "cpu" "athlon")
855 (eq_attr "athlon_decode" "direct"))
856 1 1 [(eq_attr "athlon_decode" "vector")])
858 (define_function_unit "athlon_ieu" 3 0
859 (and (eq_attr "cpu" "athlon")
860 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
863 (define_function_unit "athlon_ieu" 3 0
864 (and (eq_attr "cpu" "athlon")
865 (eq_attr "type" "str"))
868 (define_function_unit "athlon_ieu" 3 0
869 (and (eq_attr "cpu" "athlon")
870 (eq_attr "type" "imul"))
873 (define_function_unit "athlon_ieu" 3 0
874 (and (eq_attr "cpu" "athlon")
875 (eq_attr "type" "idiv"))
878 (define_function_unit "athlon_muldiv" 1 0
879 (and (eq_attr "cpu" "athlon")
880 (eq_attr "type" "imul"))
883 (define_function_unit "athlon_muldiv" 1 0
884 (and (eq_attr "cpu" "athlon")
885 (eq_attr "type" "idiv"))
888 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
889 (cond [(eq_attr "type" "fop,fop1,fcmp,fistp")
891 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
893 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
894 (const_string "store")
895 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
897 (and (eq_attr "type" "fmov")
898 (ior (match_operand:SI 1 "register_operand" "")
899 (match_operand 1 "immediate_operand" "")))
900 (const_string "store")
901 (eq_attr "type" "fmov")
902 (const_string "muladd")]
903 (const_string "none")))
905 ;; We use latencies 1 for definitions. This is OK to model colisions
906 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
908 ;; fsin, fcos: 96-192
910 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
911 (define_function_unit "athlon_fp" 3 0
912 (and (eq_attr "cpu" "athlon")
913 (eq_attr "type" "fpspc"))
916 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
917 (define_function_unit "athlon_fp" 3 0
918 (and (eq_attr "cpu" "athlon")
919 (eq_attr "type" "fdiv"))
922 (define_function_unit "athlon_fp" 3 0
923 (and (eq_attr "cpu" "athlon")
924 (eq_attr "type" "fop,fop1,fmul,fistp"))
927 ;; XFmode loads are slow.
928 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
929 ;; there are no dependent instructions.
931 (define_function_unit "athlon_fp" 3 0
932 (and (eq_attr "cpu" "athlon")
933 (and (eq_attr "type" "fmov")
934 (and (eq_attr "memory" "load")
935 (eq_attr "mode" "XF"))))
938 (define_function_unit "athlon_fp" 3 0
939 (and (eq_attr "cpu" "athlon")
940 (eq_attr "type" "fmov,fsgn"))
943 ;; fcmp and ftst instructions
944 (define_function_unit "athlon_fp" 3 0
945 (and (eq_attr "cpu" "athlon")
946 (and (eq_attr "type" "fcmp")
947 (eq_attr "athlon_decode" "direct")))
950 ;; fcmpi instructions.
951 (define_function_unit "athlon_fp" 3 0
952 (and (eq_attr "cpu" "athlon")
953 (and (eq_attr "type" "fcmp")
954 (eq_attr "athlon_decode" "vector")))
957 (define_function_unit "athlon_fp" 3 0
958 (and (eq_attr "cpu" "athlon")
959 (eq_attr "type" "fcmov"))
962 (define_function_unit "athlon_fp_mul" 1 0
963 (and (eq_attr "cpu" "athlon")
964 (eq_attr "athlon_fpunits" "mul"))
967 (define_function_unit "athlon_fp_add" 1 0
968 (and (eq_attr "cpu" "athlon")
969 (eq_attr "athlon_fpunits" "add"))
972 (define_function_unit "athlon_fp_muladd" 2 0
973 (and (eq_attr "cpu" "athlon")
974 (eq_attr "athlon_fpunits" "muladd,mul,add"))
977 (define_function_unit "athlon_fp_store" 1 0
978 (and (eq_attr "cpu" "athlon")
979 (eq_attr "athlon_fpunits" "store"))
982 ;; We don't need to model the Adress Generation Unit, since we don't model
983 ;; the re-order buffer yet and thus we never schedule more than three operations
984 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
985 ;; decoders independently on the functional units.
987 ;(define_function_unit "athlon_agu" 3 0
988 ; (and (eq_attr "cpu" "athlon")
989 ; (and (eq_attr "memory" "!none")
990 ; (eq_attr "athlon_fpunits" "none")))
993 ;; Model load unit to avoid too long sequences of loads. We don't need to
994 ;; model store queue, since it is hardly going to be bottleneck.
996 (define_function_unit "athlon_load" 2 0
997 (and (eq_attr "cpu" "athlon")
998 (eq_attr "memory" "load,both"))
1002 ;; Compare instructions.
1004 ;; All compare insns have expanders that save the operands away without
1005 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1006 ;; after the cmp) will actually emit the cmpM.
1008 (define_expand "cmpdi"
1010 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1011 (match_operand:DI 1 "x86_64_general_operand" "")))]
1014 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1015 operands[0] = force_reg (DImode, operands[0]);
1016 ix86_compare_op0 = operands[0];
1017 ix86_compare_op1 = operands[1];
1021 (define_expand "cmpsi"
1023 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1024 (match_operand:SI 1 "general_operand" "")))]
1027 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1028 operands[0] = force_reg (SImode, operands[0]);
1029 ix86_compare_op0 = operands[0];
1030 ix86_compare_op1 = operands[1];
1034 (define_expand "cmphi"
1036 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
1037 (match_operand:HI 1 "general_operand" "")))]
1040 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1041 operands[0] = force_reg (HImode, operands[0]);
1042 ix86_compare_op0 = operands[0];
1043 ix86_compare_op1 = operands[1];
1047 (define_expand "cmpqi"
1049 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
1050 (match_operand:QI 1 "general_operand" "")))]
1051 "TARGET_QIMODE_MATH"
1053 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1054 operands[0] = force_reg (QImode, operands[0]);
1055 ix86_compare_op0 = operands[0];
1056 ix86_compare_op1 = operands[1];
1060 (define_insn "cmpdi_ccno_1_rex64"
1062 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
1063 (match_operand:DI 1 "const0_operand" "n,n")))]
1064 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
1066 test{q}\t{%0, %0|%0, %0}
1067 cmp{q}\t{%1, %0|%0, %1}"
1068 [(set_attr "type" "test,icmp")
1069 (set_attr "length_immediate" "0,1")
1070 (set_attr "mode" "DI")])
1072 (define_insn "*cmpdi_minus_1_rex64"
1074 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
1075 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
1077 "ix86_match_ccmode (insn, CCGOCmode)"
1078 "cmp{q}\t{%1, %0|%0, %1}"
1079 [(set_attr "type" "icmp")
1080 (set_attr "mode" "DI")])
1082 (define_expand "cmpdi_1_rex64"
1084 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1085 (match_operand:DI 1 "general_operand" "")))]
1089 (define_insn "cmpdi_1_insn_rex64"
1091 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
1092 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
1093 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1094 "cmp{q}\t{%1, %0|%0, %1}"
1095 [(set_attr "type" "icmp")
1096 (set_attr "mode" "DI")])
1099 (define_insn "*cmpsi_ccno_1"
1101 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1102 (match_operand:SI 1 "const0_operand" "n,n")))]
1103 "ix86_match_ccmode (insn, CCNOmode)"
1105 test{l}\t{%0, %0|%0, %0}
1106 cmp{l}\t{%1, %0|%0, %1}"
1107 [(set_attr "type" "test,icmp")
1108 (set_attr "length_immediate" "0,1")
1109 (set_attr "mode" "SI")])
1111 (define_insn "*cmpsi_minus_1"
1113 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1114 (match_operand:SI 1 "general_operand" "ri,mr"))
1116 "ix86_match_ccmode (insn, CCGOCmode)"
1117 "cmp{l}\t{%1, %0|%0, %1}"
1118 [(set_attr "type" "icmp")
1119 (set_attr "mode" "SI")])
1121 (define_expand "cmpsi_1"
1123 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1124 (match_operand:SI 1 "general_operand" "ri,mr")))]
1128 (define_insn "*cmpsi_1_insn"
1130 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1131 (match_operand:SI 1 "general_operand" "ri,mr")))]
1132 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1133 && ix86_match_ccmode (insn, CCmode)"
1134 "cmp{l}\t{%1, %0|%0, %1}"
1135 [(set_attr "type" "icmp")
1136 (set_attr "mode" "SI")])
1138 (define_insn "*cmphi_ccno_1"
1140 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1141 (match_operand:HI 1 "const0_operand" "n,n")))]
1142 "ix86_match_ccmode (insn, CCNOmode)"
1144 test{w}\t{%0, %0|%0, %0}
1145 cmp{w}\t{%1, %0|%0, %1}"
1146 [(set_attr "type" "test,icmp")
1147 (set_attr "length_immediate" "0,1")
1148 (set_attr "mode" "HI")])
1150 (define_insn "*cmphi_minus_1"
1152 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1153 (match_operand:HI 1 "general_operand" "ri,mr"))
1155 "ix86_match_ccmode (insn, CCGOCmode)"
1156 "cmp{w}\t{%1, %0|%0, %1}"
1157 [(set_attr "type" "icmp")
1158 (set_attr "mode" "HI")])
1160 (define_insn "*cmphi_1"
1162 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1163 (match_operand:HI 1 "general_operand" "ri,mr")))]
1164 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1165 && ix86_match_ccmode (insn, CCmode)"
1166 "cmp{w}\t{%1, %0|%0, %1}"
1167 [(set_attr "type" "icmp")
1168 (set_attr "mode" "HI")])
1170 (define_insn "*cmpqi_ccno_1"
1172 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1173 (match_operand:QI 1 "const0_operand" "n,n")))]
1174 "ix86_match_ccmode (insn, CCNOmode)"
1176 test{b}\t{%0, %0|%0, %0}
1177 cmp{b}\t{$0, %0|%0, 0}"
1178 [(set_attr "type" "test,icmp")
1179 (set_attr "length_immediate" "0,1")
1180 (set_attr "mode" "QI")])
1182 (define_insn "*cmpqi_1"
1184 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1185 (match_operand:QI 1 "general_operand" "qi,mq")))]
1186 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1187 && ix86_match_ccmode (insn, CCmode)"
1188 "cmp{b}\t{%1, %0|%0, %1}"
1189 [(set_attr "type" "icmp")
1190 (set_attr "mode" "QI")])
1192 (define_insn "*cmpqi_minus_1"
1194 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1195 (match_operand:QI 1 "general_operand" "qi,mq"))
1197 "ix86_match_ccmode (insn, CCGOCmode)"
1198 "cmp{b}\t{%1, %0|%0, %1}"
1199 [(set_attr "type" "icmp")
1200 (set_attr "mode" "QI")])
1202 (define_insn "*cmpqi_ext_1"
1205 (match_operand:QI 0 "general_operand" "Qm")
1208 (match_operand 1 "ext_register_operand" "Q")
1210 (const_int 8)) 0)))]
1211 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1212 "cmp{b}\t{%h1, %0|%0, %h1}"
1213 [(set_attr "type" "icmp")
1214 (set_attr "mode" "QI")])
1216 (define_insn "*cmpqi_ext_1_rex64"
1219 (match_operand:QI 0 "register_operand" "Q")
1222 (match_operand 1 "ext_register_operand" "Q")
1224 (const_int 8)) 0)))]
1225 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1226 "cmp{b}\t{%h1, %0|%0, %h1}"
1227 [(set_attr "type" "icmp")
1228 (set_attr "mode" "QI")])
1230 (define_insn "*cmpqi_ext_2"
1235 (match_operand 0 "ext_register_operand" "Q")
1238 (match_operand:QI 1 "const0_operand" "n")))]
1239 "ix86_match_ccmode (insn, CCNOmode)"
1241 [(set_attr "type" "test")
1242 (set_attr "length_immediate" "0")
1243 (set_attr "mode" "QI")])
1245 (define_expand "cmpqi_ext_3"
1250 (match_operand 0 "ext_register_operand" "")
1253 (match_operand:QI 1 "general_operand" "")))]
1257 (define_insn "cmpqi_ext_3_insn"
1262 (match_operand 0 "ext_register_operand" "Q")
1265 (match_operand:QI 1 "general_operand" "Qmn")))]
1266 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1267 "cmp{b}\t{%1, %h0|%h0, %1}"
1268 [(set_attr "type" "icmp")
1269 (set_attr "mode" "QI")])
1271 (define_insn "cmpqi_ext_3_insn_rex64"
1276 (match_operand 0 "ext_register_operand" "Q")
1279 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1280 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1281 "cmp{b}\t{%1, %h0|%h0, %1}"
1282 [(set_attr "type" "icmp")
1283 (set_attr "mode" "QI")])
1285 (define_insn "*cmpqi_ext_4"
1290 (match_operand 0 "ext_register_operand" "Q")
1295 (match_operand 1 "ext_register_operand" "Q")
1297 (const_int 8)) 0)))]
1298 "ix86_match_ccmode (insn, CCmode)"
1299 "cmp{b}\t{%h1, %h0|%h0, %h1}"
1300 [(set_attr "type" "icmp")
1301 (set_attr "mode" "QI")])
1303 ;; These implement float point compares.
1304 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1305 ;; which would allow mix and match FP modes on the compares. Which is what
1306 ;; the old patterns did, but with many more of them.
1308 (define_expand "cmpxf"
1310 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1311 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1312 "TARGET_80387 && !TARGET_64BIT"
1314 ix86_compare_op0 = operands[0];
1315 ix86_compare_op1 = operands[1];
1319 (define_expand "cmptf"
1321 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1322 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1325 ix86_compare_op0 = operands[0];
1326 ix86_compare_op1 = operands[1];
1330 (define_expand "cmpdf"
1332 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1333 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1334 "TARGET_80387 || TARGET_SSE2"
1336 ix86_compare_op0 = operands[0];
1337 ix86_compare_op1 = operands[1];
1341 (define_expand "cmpsf"
1343 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1344 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1345 "TARGET_80387 || TARGET_SSE"
1347 ix86_compare_op0 = operands[0];
1348 ix86_compare_op1 = operands[1];
1352 ;; FP compares, step 1:
1353 ;; Set the FP condition codes.
1355 ;; CCFPmode compare with exceptions
1356 ;; CCFPUmode compare with no exceptions
1358 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1359 ;; and that fp moves clobber the condition codes, and that there is
1360 ;; currently no way to describe this fact to reg-stack. So there are
1361 ;; no splitters yet for this.
1363 ;; %%% YIKES! This scheme does not retain a strong connection between
1364 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1365 ;; work! Only allow tos/mem with tos in op 0.
1367 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1368 ;; things aren't as bad as they sound...
1370 (define_insn "*cmpfp_0"
1371 [(set (match_operand:HI 0 "register_operand" "=a")
1373 [(compare:CCFP (match_operand 1 "register_operand" "f")
1374 (match_operand 2 "const0_operand" "X"))] 9))]
1376 && FLOAT_MODE_P (GET_MODE (operands[1]))
1377 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1379 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1380 return "ftst\;fnstsw\t%0\;fstp\t%y0";
1382 return "ftst\;fnstsw\t%0";
1384 [(set_attr "type" "multi")
1385 (set_attr "mode" "unknownfp")])
1387 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1388 ;; used to manage the reg stack popping would not be preserved.
1390 (define_insn "*cmpfp_2_sf"
1393 (match_operand:SF 0 "register_operand" "f")
1394 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1396 "* return output_fp_compare (insn, operands, 0, 0);"
1397 [(set_attr "type" "fcmp")
1398 (set_attr "mode" "SF")])
1400 (define_insn "*cmpfp_2_sf_1"
1401 [(set (match_operand:HI 0 "register_operand" "=a")
1404 (match_operand:SF 1 "register_operand" "f")
1405 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1407 "* return output_fp_compare (insn, operands, 2, 0);"
1408 [(set_attr "type" "fcmp")
1409 (set_attr "mode" "SF")])
1411 (define_insn "*cmpfp_2_df"
1414 (match_operand:DF 0 "register_operand" "f")
1415 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1417 "* return output_fp_compare (insn, operands, 0, 0);"
1418 [(set_attr "type" "fcmp")
1419 (set_attr "mode" "DF")])
1421 (define_insn "*cmpfp_2_df_1"
1422 [(set (match_operand:HI 0 "register_operand" "=a")
1425 (match_operand:DF 1 "register_operand" "f")
1426 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1428 "* return output_fp_compare (insn, operands, 2, 0);"
1429 [(set_attr "type" "multi")
1430 (set_attr "mode" "DF")])
1432 (define_insn "*cmpfp_2_xf"
1435 (match_operand:XF 0 "register_operand" "f")
1436 (match_operand:XF 1 "register_operand" "f")))]
1437 "TARGET_80387 && !TARGET_64BIT"
1438 "* return output_fp_compare (insn, operands, 0, 0);"
1439 [(set_attr "type" "fcmp")
1440 (set_attr "mode" "XF")])
1442 (define_insn "*cmpfp_2_tf"
1445 (match_operand:TF 0 "register_operand" "f")
1446 (match_operand:TF 1 "register_operand" "f")))]
1448 "* return output_fp_compare (insn, operands, 0, 0);"
1449 [(set_attr "type" "fcmp")
1450 (set_attr "mode" "XF")])
1452 (define_insn "*cmpfp_2_xf_1"
1453 [(set (match_operand:HI 0 "register_operand" "=a")
1456 (match_operand:XF 1 "register_operand" "f")
1457 (match_operand:XF 2 "register_operand" "f"))] 9))]
1458 "TARGET_80387 && !TARGET_64BIT"
1459 "* return output_fp_compare (insn, operands, 2, 0);"
1460 [(set_attr "type" "multi")
1461 (set_attr "mode" "XF")])
1463 (define_insn "*cmpfp_2_tf_1"
1464 [(set (match_operand:HI 0 "register_operand" "=a")
1467 (match_operand:TF 1 "register_operand" "f")
1468 (match_operand:TF 2 "register_operand" "f"))] 9))]
1470 "* return output_fp_compare (insn, operands, 2, 0);"
1471 [(set_attr "type" "multi")
1472 (set_attr "mode" "XF")])
1474 (define_insn "*cmpfp_2u"
1475 [(set (reg:CCFPU 18)
1477 (match_operand 0 "register_operand" "f")
1478 (match_operand 1 "register_operand" "f")))]
1480 && FLOAT_MODE_P (GET_MODE (operands[0]))
1481 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1482 "* return output_fp_compare (insn, operands, 0, 1);"
1483 [(set_attr "type" "fcmp")
1484 (set_attr "mode" "unknownfp")])
1486 (define_insn "*cmpfp_2u_1"
1487 [(set (match_operand:HI 0 "register_operand" "=a")
1490 (match_operand 1 "register_operand" "f")
1491 (match_operand 2 "register_operand" "f"))] 9))]
1493 && FLOAT_MODE_P (GET_MODE (operands[1]))
1494 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1495 "* return output_fp_compare (insn, operands, 2, 1);"
1496 [(set_attr "type" "multi")
1497 (set_attr "mode" "unknownfp")])
1499 ;; Patterns to match the SImode-in-memory ficom instructions.
1501 ;; %%% Play games with accepting gp registers, as otherwise we have to
1502 ;; force them to memory during rtl generation, which is no good. We
1503 ;; can get rid of this once we teach reload to do memory input reloads
1506 (define_insn "*ficom_1"
1509 (match_operand 0 "register_operand" "f,f")
1510 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1511 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1512 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1515 ;; Split the not-really-implemented gp register case into a
1516 ;; push-op-pop sequence.
1518 ;; %%% This is most efficient, but am I gonna get in trouble
1519 ;; for separating cc0_setter and cc0_user?
1524 (match_operand:SF 0 "register_operand" "")
1525 (float (match_operand:SI 1 "register_operand" ""))))]
1526 "0 && TARGET_80387 && reload_completed"
1527 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1528 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1529 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1530 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1531 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1532 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1534 ;; FP compares, step 2
1535 ;; Move the fpsw to ax.
1537 (define_insn "x86_fnstsw_1"
1538 [(set (match_operand:HI 0 "register_operand" "=a")
1539 (unspec:HI [(reg 18)] 9))]
1542 [(set_attr "length" "2")
1543 (set_attr "mode" "SI")
1544 (set_attr "i387" "1")
1545 (set_attr "ppro_uops" "few")])
1547 ;; FP compares, step 3
1548 ;; Get ax into flags, general case.
1550 (define_insn "x86_sahf_1"
1552 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1555 [(set_attr "length" "1")
1556 (set_attr "athlon_decode" "vector")
1557 (set_attr "mode" "SI")
1558 (set_attr "ppro_uops" "one")])
1560 ;; Pentium Pro can do steps 1 through 3 in one go.
1562 (define_insn "*cmpfp_i"
1564 (compare:CCFP (match_operand 0 "register_operand" "f")
1565 (match_operand 1 "register_operand" "f")))]
1566 "TARGET_80387 && TARGET_CMOVE
1567 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1568 && FLOAT_MODE_P (GET_MODE (operands[0]))
1569 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1570 "* return output_fp_compare (insn, operands, 1, 0);"
1571 [(set_attr "type" "fcmp")
1572 (set_attr "mode" "unknownfp")
1573 (set_attr "athlon_decode" "vector")])
1575 (define_insn "*cmpfp_i_sse"
1577 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1578 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1580 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1581 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1582 "* return output_fp_compare (insn, operands, 1, 0);"
1583 [(set_attr "type" "fcmp,sse")
1584 (set_attr "mode" "unknownfp")
1585 (set_attr "athlon_decode" "vector")])
1587 (define_insn "*cmpfp_i_sse_only"
1589 (compare:CCFP (match_operand 0 "register_operand" "x")
1590 (match_operand 1 "nonimmediate_operand" "xm")))]
1591 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1592 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1593 "* return output_fp_compare (insn, operands, 1, 0);"
1594 [(set_attr "type" "sse")
1595 (set_attr "mode" "unknownfp")
1596 (set_attr "athlon_decode" "vector")])
1598 (define_insn "*cmpfp_iu"
1599 [(set (reg:CCFPU 17)
1600 (compare:CCFPU (match_operand 0 "register_operand" "f")
1601 (match_operand 1 "register_operand" "f")))]
1602 "TARGET_80387 && TARGET_CMOVE
1603 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1604 && FLOAT_MODE_P (GET_MODE (operands[0]))
1605 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1606 "* return output_fp_compare (insn, operands, 1, 1);"
1607 [(set_attr "type" "fcmp")
1608 (set_attr "mode" "unknownfp")
1609 (set_attr "athlon_decode" "vector")])
1611 (define_insn "*cmpfp_iu_sse"
1612 [(set (reg:CCFPU 17)
1613 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1614 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1616 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1617 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1618 "* return output_fp_compare (insn, operands, 1, 1);"
1619 [(set_attr "type" "fcmp,sse")
1620 (set_attr "mode" "unknownfp")
1621 (set_attr "athlon_decode" "vector")])
1623 (define_insn "*cmpfp_iu_sse_only"
1624 [(set (reg:CCFPU 17)
1625 (compare:CCFPU (match_operand 0 "register_operand" "x")
1626 (match_operand 1 "nonimmediate_operand" "xm")))]
1627 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1628 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1629 "* return output_fp_compare (insn, operands, 1, 1);"
1630 [(set_attr "type" "sse")
1631 (set_attr "mode" "unknownfp")
1632 (set_attr "athlon_decode" "vector")])
1634 ;; Move instructions.
1636 ;; General case of fullword move.
1638 (define_expand "movsi"
1639 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1640 (match_operand:SI 1 "general_operand" ""))]
1642 "ix86_expand_move (SImode, operands); DONE;")
1644 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1647 ;; %%% We don't use a post-inc memory reference because x86 is not a
1648 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1649 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1650 ;; targets without our curiosities, and it is just as easy to represent
1651 ;; this differently.
1653 (define_insn "*pushsi2"
1654 [(set (match_operand:SI 0 "push_operand" "=<")
1655 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1658 [(set_attr "type" "push")
1659 (set_attr "mode" "SI")])
1661 ;; For 64BIT abi we always round up to 8 bytes.
1662 (define_insn "*pushsi2_rex64"
1663 [(set (match_operand:SI 0 "push_operand" "=X")
1664 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1667 [(set_attr "type" "push")
1668 (set_attr "mode" "SI")])
1670 (define_insn "*pushsi2_prologue"
1671 [(set (match_operand:SI 0 "push_operand" "=<")
1672 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1673 (clobber (mem:BLK (scratch)))]
1676 [(set_attr "type" "push")
1677 (set_attr "mode" "SI")])
1679 (define_insn "*popsi1_epilogue"
1680 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1681 (mem:SI (reg:SI 7)))
1683 (plus:SI (reg:SI 7) (const_int 4)))
1684 (clobber (mem:BLK (scratch)))]
1687 [(set_attr "type" "pop")
1688 (set_attr "mode" "SI")])
1690 (define_insn "popsi1"
1691 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1692 (mem:SI (reg:SI 7)))
1694 (plus:SI (reg:SI 7) (const_int 4)))]
1697 [(set_attr "type" "pop")
1698 (set_attr "mode" "SI")])
1700 (define_insn "*movsi_xor"
1701 [(set (match_operand:SI 0 "register_operand" "=r")
1702 (match_operand:SI 1 "const0_operand" "i"))
1703 (clobber (reg:CC 17))]
1704 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1705 "xor{l}\t{%0, %0|%0, %0}"
1706 [(set_attr "type" "alu1")
1707 (set_attr "mode" "SI")
1708 (set_attr "length_immediate" "0")])
1710 (define_insn "*movsi_or"
1711 [(set (match_operand:SI 0 "register_operand" "=r")
1712 (match_operand:SI 1 "immediate_operand" "i"))
1713 (clobber (reg:CC 17))]
1714 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1715 && INTVAL (operands[1]) == -1
1716 && (TARGET_PENTIUM || optimize_size)"
1718 operands[1] = constm1_rtx;
1719 return "or{l}\t{%1, %0|%0, %1}";
1721 [(set_attr "type" "alu1")
1722 (set_attr "mode" "SI")
1723 (set_attr "length_immediate" "1")])
1725 (define_insn "*movsi_1"
1726 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1727 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1728 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1730 switch (get_attr_type (insn))
1733 if (get_attr_mode (insn) == TImode)
1734 return "movdqa\t{%1, %0|%0, %1}";
1735 return "movd\t{%1, %0|%0, %1}";
1738 return "movd\t{%1, %0|%0, %1}";
1741 return "lea{l}\t{%1, %0|%0, %1}";
1744 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1746 return "mov{l}\t{%1, %0|%0, %1}";
1750 (cond [(eq_attr "alternative" "4,5")
1751 (const_string "mmx")
1752 (eq_attr "alternative" "6,7,8")
1753 (const_string "sse")
1754 (and (ne (symbol_ref "flag_pic") (const_int 0))
1755 (match_operand:SI 1 "symbolic_operand" ""))
1756 (const_string "lea")
1758 (const_string "imov")))
1759 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1760 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1762 ;; Stores and loads of ax to arbitary constant address.
1763 ;; We fake an second form of instruction to force reload to load address
1764 ;; into register when rax is not available
1765 (define_insn "*movabssi_1_rex64"
1766 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1767 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1770 movabs{l}\t{%1, %P0|%P0, %1}
1771 mov{l}\t{%1, %a0|%a0, %1}
1772 movabs{l}\t{%1, %a0|%a0, %1}"
1773 [(set_attr "type" "imov")
1774 (set_attr "modrm" "0,*,*")
1775 (set_attr "length_address" "8,0,0")
1776 (set_attr "length_immediate" "0,*,*")
1777 (set_attr "memory" "store")
1778 (set_attr "mode" "SI")])
1780 (define_insn "*movabssi_2_rex64"
1781 [(set (match_operand:SI 0 "register_operand" "=a,r")
1782 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1785 movabs{l}\t{%P1, %0|%0, %P1}
1786 mov{l}\t{%a1, %0|%0, %a1}"
1787 [(set_attr "type" "imov")
1788 (set_attr "modrm" "0,*")
1789 (set_attr "length_address" "8,0")
1790 (set_attr "length_immediate" "0")
1791 (set_attr "memory" "load")
1792 (set_attr "mode" "SI")])
1794 (define_insn "*swapsi"
1795 [(set (match_operand:SI 0 "register_operand" "+r")
1796 (match_operand:SI 1 "register_operand" "+r"))
1801 [(set_attr "type" "imov")
1802 (set_attr "pent_pair" "np")
1803 (set_attr "athlon_decode" "vector")
1804 (set_attr "mode" "SI")
1805 (set_attr "modrm" "0")
1806 (set_attr "ppro_uops" "few")])
1808 (define_expand "movhi"
1809 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1810 (match_operand:HI 1 "general_operand" ""))]
1812 "ix86_expand_move (HImode, operands); DONE;")
1814 (define_insn "*pushhi2"
1815 [(set (match_operand:HI 0 "push_operand" "=<,<")
1816 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1819 push{w}\t{|WORD PTR }%1
1821 [(set_attr "type" "push")
1822 (set_attr "mode" "HI")])
1824 ;; For 64BIT abi we always round up to 8 bytes.
1825 (define_insn "*pushhi2_rex64"
1826 [(set (match_operand:HI 0 "push_operand" "=X")
1827 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1830 [(set_attr "type" "push")
1831 (set_attr "mode" "QI")])
1833 (define_insn "*movhi_1"
1834 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1835 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1836 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1838 switch (get_attr_type (insn))
1841 /* movzwl is faster than movw on p2 due to partial word stalls,
1842 though not as fast as an aligned movl. */
1843 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1845 if (get_attr_mode (insn) == MODE_SI)
1846 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1848 return "mov{w}\t{%1, %0|%0, %1}";
1852 (cond [(and (eq_attr "alternative" "0,1")
1853 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1855 (eq (symbol_ref "TARGET_HIMODE_MATH")
1857 (const_string "imov")
1858 (and (eq_attr "alternative" "2,3,4")
1859 (match_operand:HI 1 "aligned_operand" ""))
1860 (const_string "imov")
1861 (and (ne (symbol_ref "TARGET_MOVX")
1863 (eq_attr "alternative" "0,1,3,4"))
1864 (const_string "imovx")
1866 (const_string "imov")))
1868 (cond [(eq_attr "type" "imovx")
1870 (and (eq_attr "alternative" "2,3,4")
1871 (match_operand:HI 1 "aligned_operand" ""))
1873 (and (eq_attr "alternative" "0,1")
1874 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1876 (eq (symbol_ref "TARGET_HIMODE_MATH")
1880 (const_string "HI")))
1881 (set_attr "modrm" "0,*,*,0,*,*")])
1883 ;; Stores and loads of ax to arbitary constant address.
1884 ;; We fake an second form of instruction to force reload to load address
1885 ;; into register when rax is not available
1886 (define_insn "*movabshi_1_rex64"
1887 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1888 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1891 movabs{w}\t{%1, %P0|%P0, %1}
1892 mov{w}\t{%1, %a0|%a0, %1}
1893 movabs{w}\t{%1, %a0|%a0, %1}"
1894 [(set_attr "type" "imov")
1895 (set_attr "modrm" "0,*,*")
1896 (set_attr "length_address" "8,0,0")
1897 (set_attr "length_immediate" "0,*,*")
1898 (set_attr "memory" "store")
1899 (set_attr "mode" "HI")])
1901 (define_insn "*movabshi_2_rex64"
1902 [(set (match_operand:HI 0 "register_operand" "=a,r")
1903 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1906 movabs{w}\t{%P1, %0|%0, %P1}
1907 mov{w}\t{%a1, %0|%0, %a1}"
1908 [(set_attr "type" "imov")
1909 (set_attr "modrm" "0,*")
1910 (set_attr "length_address" "8,0")
1911 (set_attr "length_immediate" "0")
1912 (set_attr "memory" "load")
1913 (set_attr "mode" "HI")])
1915 (define_insn "*swaphi_1"
1916 [(set (match_operand:HI 0 "register_operand" "+r")
1917 (match_operand:HI 1 "register_operand" "+r"))
1920 "TARGET_PARTIAL_REG_STALL"
1922 [(set_attr "type" "imov")
1923 (set_attr "pent_pair" "np")
1924 (set_attr "mode" "HI")
1925 (set_attr "modrm" "0")
1926 (set_attr "ppro_uops" "few")])
1928 (define_insn "*swaphi_2"
1929 [(set (match_operand:HI 0 "register_operand" "+r")
1930 (match_operand:HI 1 "register_operand" "+r"))
1933 "! TARGET_PARTIAL_REG_STALL"
1935 [(set_attr "type" "imov")
1936 (set_attr "pent_pair" "np")
1937 (set_attr "mode" "SI")
1938 (set_attr "modrm" "0")
1939 (set_attr "ppro_uops" "few")])
1941 (define_expand "movstricthi"
1942 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1943 (match_operand:HI 1 "general_operand" ""))]
1944 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1946 /* Don't generate memory->memory moves, go through a register */
1947 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1948 operands[1] = force_reg (HImode, operands[1]);
1951 (define_insn "*movstricthi_1"
1952 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1953 (match_operand:HI 1 "general_operand" "rn,m"))]
1954 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1955 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1956 "mov{w}\t{%1, %0|%0, %1}"
1957 [(set_attr "type" "imov")
1958 (set_attr "mode" "HI")])
1960 (define_insn "*movstricthi_xor"
1961 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1962 (match_operand:HI 1 "const0_operand" "i"))
1963 (clobber (reg:CC 17))]
1965 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1966 "xor{w}\t{%0, %0|%0, %0}"
1967 [(set_attr "type" "alu1")
1968 (set_attr "mode" "HI")
1969 (set_attr "length_immediate" "0")])
1971 (define_expand "movqi"
1972 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1973 (match_operand:QI 1 "general_operand" ""))]
1975 "ix86_expand_move (QImode, operands); DONE;")
1977 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1978 ;; "push a byte". But actually we use pushw, which has the effect
1979 ;; of rounding the amount pushed up to a halfword.
1981 (define_insn "*pushqi2"
1982 [(set (match_operand:QI 0 "push_operand" "=X,X")
1983 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1986 push{w}\t{|word ptr }%1
1988 [(set_attr "type" "push")
1989 (set_attr "mode" "HI")])
1991 ;; For 64BIT abi we always round up to 8 bytes.
1992 (define_insn "*pushqi2_rex64"
1993 [(set (match_operand:QI 0 "push_operand" "=X")
1994 (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
1997 [(set_attr "type" "push")
1998 (set_attr "mode" "QI")])
2000 ;; Situation is quite tricky about when to choose full sized (SImode) move
2001 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
2002 ;; partial register dependency machines (such as AMD Athlon), where QImode
2003 ;; moves issue extra dependency and for partial register stalls machines
2004 ;; that don't use QImode patterns (and QImode move cause stall on the next
2007 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
2008 ;; register stall machines with, where we use QImode instructions, since
2009 ;; partial register stall can be caused there. Then we use movzx.
2010 (define_insn "*movqi_1"
2011 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2012 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2013 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
2015 switch (get_attr_type (insn))
2018 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
2020 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
2022 if (get_attr_mode (insn) == MODE_SI)
2023 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2025 return "mov{b}\t{%1, %0|%0, %1}";
2029 (cond [(and (eq_attr "alternative" "3")
2030 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
2032 (eq (symbol_ref "TARGET_QIMODE_MATH")
2034 (const_string "imov")
2035 (eq_attr "alternative" "3,5")
2036 (const_string "imovx")
2037 (and (ne (symbol_ref "TARGET_MOVX")
2039 (eq_attr "alternative" "2"))
2040 (const_string "imovx")
2042 (const_string "imov")))
2044 (cond [(eq_attr "alternative" "3,4,5")
2046 (eq_attr "alternative" "6")
2048 (eq_attr "type" "imovx")
2050 (and (eq_attr "type" "imov")
2051 (and (eq_attr "alternative" "0,1,2")
2052 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
2055 ;; Avoid partial register stalls when not using QImode arithmetic
2056 (and (eq_attr "type" "imov")
2057 (and (eq_attr "alternative" "0,1,2")
2058 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
2060 (eq (symbol_ref "TARGET_QIMODE_MATH")
2064 (const_string "QI")))])
2066 (define_expand "reload_outqi"
2067 [(parallel [(match_operand:QI 0 "" "=m")
2068 (match_operand:QI 1 "register_operand" "r")
2069 (match_operand:QI 2 "register_operand" "=&q")])]
2073 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
2075 if (reg_overlap_mentioned_p (op2, op0))
2077 if (! q_regs_operand (op1, QImode))
2079 emit_insn (gen_movqi (op2, op1));
2082 emit_insn (gen_movqi (op0, op1));
2086 (define_insn "*swapqi"
2087 [(set (match_operand:QI 0 "register_operand" "+r")
2088 (match_operand:QI 1 "register_operand" "+r"))
2093 [(set_attr "type" "imov")
2094 (set_attr "pent_pair" "np")
2095 (set_attr "mode" "QI")
2096 (set_attr "modrm" "0")
2097 (set_attr "ppro_uops" "few")])
2099 (define_expand "movstrictqi"
2100 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
2101 (match_operand:QI 1 "general_operand" ""))]
2102 "! TARGET_PARTIAL_REG_STALL"
2104 /* Don't generate memory->memory moves, go through a register */
2105 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2106 operands[1] = force_reg (QImode, operands[1]);
2109 (define_insn "*movstrictqi_1"
2110 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
2111 (match_operand:QI 1 "general_operand" "*qn,m"))]
2112 "! TARGET_PARTIAL_REG_STALL
2113 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2114 "mov{b}\t{%1, %0|%0, %1}"
2115 [(set_attr "type" "imov")
2116 (set_attr "mode" "QI")])
2118 (define_insn "*movstrictqi_xor"
2119 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
2120 (match_operand:QI 1 "const0_operand" "i"))
2121 (clobber (reg:CC 17))]
2122 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
2123 "xor{b}\t{%0, %0|%0, %0}"
2124 [(set_attr "type" "alu1")
2125 (set_attr "mode" "QI")
2126 (set_attr "length_immediate" "0")])
2128 (define_insn "*movsi_extv_1"
2129 [(set (match_operand:SI 0 "register_operand" "=R")
2130 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
2134 "movs{bl|x}\t{%h1, %0|%0, %h1}"
2135 [(set_attr "type" "imovx")
2136 (set_attr "mode" "SI")])
2138 (define_insn "*movhi_extv_1"
2139 [(set (match_operand:HI 0 "register_operand" "=R")
2140 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
2144 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
2145 [(set_attr "type" "imovx")
2146 (set_attr "mode" "SI")])
2148 (define_insn "*movqi_extv_1"
2149 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2150 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2155 switch (get_attr_type (insn))
2158 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2160 return "mov{b}\t{%h1, %0|%0, %h1}";
2164 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2165 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2166 (ne (symbol_ref "TARGET_MOVX")
2168 (const_string "imovx")
2169 (const_string "imov")))
2171 (if_then_else (eq_attr "type" "imovx")
2173 (const_string "QI")))])
2175 (define_insn "*movqi_extv_1_rex64"
2176 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2177 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2182 switch (get_attr_type (insn))
2185 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2187 return "mov{b}\t{%h1, %0|%0, %h1}";
2191 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2192 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2193 (ne (symbol_ref "TARGET_MOVX")
2195 (const_string "imovx")
2196 (const_string "imov")))
2198 (if_then_else (eq_attr "type" "imovx")
2200 (const_string "QI")))])
2202 ;; Stores and loads of ax to arbitary constant address.
2203 ;; We fake an second form of instruction to force reload to load address
2204 ;; into register when rax is not available
2205 (define_insn "*movabsqi_1_rex64"
2206 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2207 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2210 movabs{q}\t{%1, %P0|%P0, %1}
2211 mov{q}\t{%1, %a0|%a0, %1}
2212 movabs{q}\t{%1, %a0|%a0, %1}"
2213 [(set_attr "type" "imov")
2214 (set_attr "modrm" "0,*,*")
2215 (set_attr "length_address" "8,0,0")
2216 (set_attr "length_immediate" "0,*,*")
2217 (set_attr "memory" "store")
2218 (set_attr "mode" "QI")])
2220 (define_insn "*movabsqi_2_rex64"
2221 [(set (match_operand:QI 0 "register_operand" "=a,r")
2222 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2225 movabs{q}\t{%P1, %0|%0, %P1}
2226 mov{q}\t{%a1, %0|%0, %a1}"
2227 [(set_attr "type" "imov")
2228 (set_attr "modrm" "0,*")
2229 (set_attr "length_address" "8,0")
2230 (set_attr "length_immediate" "0")
2231 (set_attr "memory" "load")
2232 (set_attr "mode" "QI")])
2234 (define_insn "*movsi_extzv_1"
2235 [(set (match_operand:SI 0 "register_operand" "=R")
2236 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
2240 "movz{bl|x}\t{%h1, %0|%0, %h1}"
2241 [(set_attr "type" "imovx")
2242 (set_attr "mode" "SI")])
2244 (define_insn "*movqi_extzv_2"
2245 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2246 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2251 switch (get_attr_type (insn))
2254 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2256 return "mov{b}\t{%h1, %0|%0, %h1}";
2260 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2261 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2262 (ne (symbol_ref "TARGET_MOVX")
2264 (const_string "imovx")
2265 (const_string "imov")))
2267 (if_then_else (eq_attr "type" "imovx")
2269 (const_string "QI")))])
2271 (define_insn "*movqi_extzv_2_rex64"
2272 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2273 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2278 switch (get_attr_type (insn))
2281 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2283 return "mov{b}\t{%h1, %0|%0, %h1}";
2287 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2288 (ne (symbol_ref "TARGET_MOVX")
2290 (const_string "imovx")
2291 (const_string "imov")))
2293 (if_then_else (eq_attr "type" "imovx")
2295 (const_string "QI")))])
2297 (define_insn "movsi_insv_1"
2298 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2301 (match_operand:SI 1 "general_operand" "Qmn"))]
2303 "mov{b}\t{%b1, %h0|%h0, %b1}"
2304 [(set_attr "type" "imov")
2305 (set_attr "mode" "QI")])
2307 (define_insn "*movsi_insv_1_rex64"
2308 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2311 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
2313 "mov{b}\t{%b1, %h0|%h0, %b1}"
2314 [(set_attr "type" "imov")
2315 (set_attr "mode" "QI")])
2317 (define_insn "*movqi_insv_2"
2318 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2321 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
2325 "mov{b}\t{%h1, %h0|%h0, %h1}"
2326 [(set_attr "type" "imov")
2327 (set_attr "mode" "QI")])
2329 (define_expand "movdi"
2330 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2331 (match_operand:DI 1 "general_operand" ""))]
2333 "ix86_expand_move (DImode, operands); DONE;")
2335 (define_insn "*pushdi"
2336 [(set (match_operand:DI 0 "push_operand" "=<")
2337 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2341 (define_insn "pushdi2_rex64"
2342 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2343 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2348 [(set_attr "type" "push,multi")
2349 (set_attr "mode" "DI")])
2351 ;; Convert impossible pushes of immediate to existing instructions.
2352 ;; First try to get scratch register and go trought it. In case this
2353 ;; fails, push sign extended lower part first and then overwrite
2354 ;; upper part by 32bit move.
2356 [(match_scratch:DI 2 "r")
2357 (set (match_operand:DI 0 "push_operand" "")
2358 (match_operand:DI 1 "immediate_operand" ""))]
2359 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2360 && !x86_64_immediate_operand (operands[1], DImode)"
2361 [(set (match_dup 2) (match_dup 1))
2362 (set (match_dup 0) (match_dup 2))]
2365 ;; We need to define this as both peepholer and splitter for case
2366 ;; peephole2 pass is not run.
2368 [(set (match_operand:DI 0 "push_operand" "")
2369 (match_operand:DI 1 "immediate_operand" ""))]
2370 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2371 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2372 [(set (match_dup 0) (match_dup 1))
2373 (set (match_dup 2) (match_dup 3))]
2374 "split_di (operands + 1, 1, operands + 2, operands + 3);
2375 operands[1] = gen_lowpart (DImode, operands[2]);
2376 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2381 [(set (match_operand:DI 0 "push_operand" "")
2382 (match_operand:DI 1 "immediate_operand" ""))]
2383 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2384 && !symbolic_operand (operands[1], DImode)
2385 && !x86_64_immediate_operand (operands[1], DImode)"
2386 [(set (match_dup 0) (match_dup 1))
2387 (set (match_dup 2) (match_dup 3))]
2388 "split_di (operands + 1, 1, operands + 2, operands + 3);
2389 operands[1] = gen_lowpart (DImode, operands[2]);
2390 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2394 (define_insn "*pushdi2_prologue_rex64"
2395 [(set (match_operand:DI 0 "push_operand" "=<")
2396 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2397 (clobber (mem:BLK (scratch)))]
2400 [(set_attr "type" "push")
2401 (set_attr "mode" "DI")])
2403 (define_insn "*popdi1_epilogue_rex64"
2404 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2405 (mem:DI (reg:DI 7)))
2407 (plus:DI (reg:DI 7) (const_int 8)))
2408 (clobber (mem:BLK (scratch)))]
2411 [(set_attr "type" "pop")
2412 (set_attr "mode" "DI")])
2414 (define_insn "popdi1"
2415 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2416 (mem:DI (reg:DI 7)))
2418 (plus:DI (reg:DI 7) (const_int 8)))]
2421 [(set_attr "type" "pop")
2422 (set_attr "mode" "DI")])
2424 (define_insn "*movdi_xor_rex64"
2425 [(set (match_operand:DI 0 "register_operand" "=r")
2426 (match_operand:DI 1 "const0_operand" "i"))
2427 (clobber (reg:CC 17))]
2428 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)
2430 "xor{l}\t{%k0, %k0|%k0, %k0}"
2431 [(set_attr "type" "alu1")
2432 (set_attr "mode" "SI")
2433 (set_attr "length_immediate" "0")])
2435 (define_insn "*movdi_or_rex64"
2436 [(set (match_operand:DI 0 "register_operand" "=r")
2437 (match_operand:DI 1 "const_int_operand" "i"))
2438 (clobber (reg:CC 17))]
2439 "reload_completed && GET_CODE (operands[1]) == CONST_INT
2441 && INTVAL (operands[1]) == -1
2442 && (TARGET_PENTIUM || optimize_size)"
2444 operands[1] = constm1_rtx;
2445 return "or{q}\t{%1, %0|%0, %1}";
2447 [(set_attr "type" "alu1")
2448 (set_attr "mode" "DI")
2449 (set_attr "length_immediate" "1")])
2451 (define_insn "*movdi_2"
2452 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2453 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2455 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2459 movq\t{%1, %0|%0, %1}
2460 movq\t{%1, %0|%0, %1}
2461 movq\t{%1, %0|%0, %1}
2462 movdqa\t{%1, %0|%0, %1}
2463 movq\t{%1, %0|%0, %1}"
2464 [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
2465 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
2468 [(set (match_operand:DI 0 "push_operand" "")
2469 (match_operand:DI 1 "general_operand" ""))]
2470 "!TARGET_64BIT && reload_completed
2471 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2473 "ix86_split_long_move (operands); DONE;")
2475 ;; %%% This multiword shite has got to go.
2477 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2478 (match_operand:DI 1 "general_operand" ""))]
2479 "!TARGET_64BIT && reload_completed
2480 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
2481 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2483 "ix86_split_long_move (operands); DONE;")
2485 (define_insn "*movdi_1_rex64"
2486 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
2487 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
2488 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2491 switch (get_attr_type (insn))
2494 if (register_operand (operands[0], DImode)
2495 && register_operand (operands[1], DImode))
2496 return "movdqa\t{%1, %0|%0, %1}";
2499 return "movq\t{%1, %0|%0, %1}";
2503 return "lea{q}\t{%a1, %0|%0, %a1}";
2505 if (flag_pic && SYMBOLIC_CONST (operands[1]))
2507 if (get_attr_mode (insn) == MODE_SI)
2508 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2509 else if (which_alternative == 2)
2510 return "movabs{q}\t{%1, %0|%0, %1}";
2512 return "mov{q}\t{%1, %0|%0, %1}";
2516 (cond [(eq_attr "alternative" "5,6")
2517 (const_string "mmx")
2518 (eq_attr "alternative" "7,8")
2519 (const_string "sse")
2520 (eq_attr "alternative" "4")
2521 (const_string "multi")
2522 (and (ne (symbol_ref "flag_pic") (const_int 0))
2523 (match_operand:DI 1 "symbolic_operand" ""))
2524 (const_string "lea")
2526 (const_string "imov")))
2527 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
2528 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
2529 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
2531 ;; Stores and loads of ax to arbitary constant address.
2532 ;; We fake an second form of instruction to force reload to load address
2533 ;; into register when rax is not available
2534 (define_insn "*movabsdi_1_rex64"
2535 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2536 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2539 movabs{q}\t{%1, %P0|%P0, %1}
2540 mov{q}\t{%1, %a0|%a0, %1}
2541 movabs{q}\t{%1, %a0|%a0, %1}"
2542 [(set_attr "type" "imov")
2543 (set_attr "modrm" "0,*,*")
2544 (set_attr "length_address" "8,0,0")
2545 (set_attr "length_immediate" "0,*,*")
2546 (set_attr "memory" "store")
2547 (set_attr "mode" "DI")])
2549 (define_insn "*movabsdi_2_rex64"
2550 [(set (match_operand:DI 0 "register_operand" "=a,r")
2551 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2554 movabs{q}\t{%P1, %0|%0, %P1}
2555 mov{q}\t{%a1, %0|%0, %a1}"
2556 [(set_attr "type" "imov")
2557 (set_attr "modrm" "0,*")
2558 (set_attr "length_address" "8,0")
2559 (set_attr "length_immediate" "0")
2560 (set_attr "memory" "load")
2561 (set_attr "mode" "DI")])
2563 ;; Convert impossible stores of immediate to existing instructions.
2564 ;; First try to get scratch register and go trought it. In case this
2565 ;; fails, move by 32bit parts.
2567 [(match_scratch:DI 2 "r")
2568 (set (match_operand:DI 0 "memory_operand" "")
2569 (match_operand:DI 1 "immediate_operand" ""))]
2570 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2571 && !x86_64_immediate_operand (operands[1], DImode)"
2572 [(set (match_dup 2) (match_dup 1))
2573 (set (match_dup 0) (match_dup 2))]
2576 ;; We need to define this as both peepholer and splitter for case
2577 ;; peephole2 pass is not run.
2579 [(set (match_operand:DI 0 "memory_operand" "")
2580 (match_operand:DI 1 "immediate_operand" ""))]
2581 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2582 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2583 [(set (match_dup 2) (match_dup 3))
2584 (set (match_dup 4) (match_dup 5))]
2585 "split_di (operands, 2, operands + 2, operands + 4);")
2588 [(set (match_operand:DI 0 "memory_operand" "")
2589 (match_operand:DI 1 "immediate_operand" ""))]
2590 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2591 && !symbolic_operand (operands[1], DImode)
2592 && !x86_64_immediate_operand (operands[1], DImode)"
2593 [(set (match_dup 2) (match_dup 3))
2594 (set (match_dup 4) (match_dup 5))]
2595 "split_di (operands, 2, operands + 2, operands + 4);")
2597 (define_insn "*swapdi_rex64"
2598 [(set (match_operand:DI 0 "register_operand" "+r")
2599 (match_operand:DI 1 "register_operand" "+r"))
2604 [(set_attr "type" "imov")
2605 (set_attr "pent_pair" "np")
2606 (set_attr "athlon_decode" "vector")
2607 (set_attr "mode" "DI")
2608 (set_attr "modrm" "0")
2609 (set_attr "ppro_uops" "few")])
2612 (define_expand "movsf"
2613 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2614 (match_operand:SF 1 "general_operand" ""))]
2616 "ix86_expand_move (SFmode, operands); DONE;")
2618 (define_insn "*pushsf"
2619 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2620 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2623 switch (which_alternative)
2626 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2627 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2628 operands[2] = stack_pointer_rtx;
2629 operands[3] = GEN_INT (4);
2630 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2631 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2633 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2636 return "push{l}\t%1";
2644 [(set_attr "type" "multi,push,multi")
2645 (set_attr "mode" "SF,SI,SF")])
2647 (define_insn "*pushsf_rex64"
2648 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2649 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2652 switch (which_alternative)
2655 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2656 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2657 operands[2] = stack_pointer_rtx;
2658 operands[3] = GEN_INT (8);
2659 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2660 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2662 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2665 return "push{q}\t%q1";
2674 [(set_attr "type" "multi,push,multi")
2675 (set_attr "mode" "SF,DI,SF")])
2678 [(set (match_operand:SF 0 "push_operand" "")
2679 (match_operand:SF 1 "memory_operand" ""))]
2681 && GET_CODE (operands[1]) == MEM
2682 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2683 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2686 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2689 ;; %%% Kill this when call knows how to work this out.
2691 [(set (match_operand:SF 0 "push_operand" "")
2692 (match_operand:SF 1 "register_operand" ""))]
2693 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2694 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2695 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2698 [(set (match_operand:SF 0 "push_operand" "")
2699 (match_operand:SF 1 "register_operand" ""))]
2700 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2701 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2702 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2704 (define_insn "*movsf_1"
2705 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2706 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2707 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2708 && (reload_in_progress || reload_completed
2709 || GET_CODE (operands[1]) != CONST_DOUBLE
2710 || memory_operand (operands[0], SFmode))"
2712 switch (which_alternative)
2715 if (REG_P (operands[1])
2716 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2718 else if (STACK_TOP_P (operands[0]))
2719 return "fld%z1\t%y1";
2724 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2725 return "fstp%z0\t%y0";
2727 return "fst%z0\t%y0";
2730 switch (standard_80387_constant_p (operands[1]))
2741 return "mov{l}\t{%1, %0|%0, %1}";
2743 return "pxor\t%0, %0";
2745 if (TARGET_PARTIAL_REG_DEPENDENCY)
2746 return "movaps\t{%1, %0|%0, %1}";
2748 return "movss\t{%1, %0|%0, %1}";
2751 return "movss\t{%1, %0|%0, %1}";
2757 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2758 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2760 (define_insn "*swapsf"
2761 [(set (match_operand:SF 0 "register_operand" "+f")
2762 (match_operand:SF 1 "register_operand" "+f"))
2765 "reload_completed || !TARGET_SSE2"
2767 if (STACK_TOP_P (operands[0]))
2772 [(set_attr "type" "fxch")
2773 (set_attr "mode" "SF")])
2775 (define_expand "movdf"
2776 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2777 (match_operand:DF 1 "general_operand" ""))]
2779 "ix86_expand_move (DFmode, operands); DONE;")
2781 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2782 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2783 ;; On the average, pushdf using integers can be still shorter. Allow this
2784 ;; pattern for optimize_size too.
2786 (define_insn "*pushdf_nointeger"
2787 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2788 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2789 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2791 switch (which_alternative)
2794 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2795 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2796 operands[2] = stack_pointer_rtx;
2797 operands[3] = GEN_INT (8);
2798 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2799 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2801 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2812 [(set_attr "type" "multi")
2813 (set_attr "mode" "DF,SI,SI,DF")])
2815 (define_insn "*pushdf_integer"
2816 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2817 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2818 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2820 switch (which_alternative)
2823 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2824 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2825 operands[2] = stack_pointer_rtx;
2826 operands[3] = GEN_INT (8);
2828 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2829 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2831 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2833 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2834 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2836 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2847 [(set_attr "type" "multi")
2848 (set_attr "mode" "DF,SI,DF")])
2850 ;; %%% Kill this when call knows how to work this out.
2852 [(set (match_operand:DF 0 "push_operand" "")
2853 (match_operand:DF 1 "register_operand" ""))]
2854 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2855 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2856 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2860 [(set (match_operand:DF 0 "push_operand" "")
2861 (match_operand:DF 1 "register_operand" ""))]
2862 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2863 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2864 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2868 [(set (match_operand:DF 0 "push_operand" "")
2869 (match_operand:DF 1 "general_operand" ""))]
2872 "ix86_split_long_move (operands); DONE;")
2874 ;; Moving is usually shorter when only FP registers are used. This separate
2875 ;; movdf pattern avoids the use of integer registers for FP operations
2876 ;; when optimizing for size.
2878 (define_insn "*movdf_nointeger"
2879 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2880 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2881 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2882 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2883 && (reload_in_progress || reload_completed
2884 || GET_CODE (operands[1]) != CONST_DOUBLE
2885 || memory_operand (operands[0], DFmode))"
2887 switch (which_alternative)
2890 if (REG_P (operands[1])
2891 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2893 else if (STACK_TOP_P (operands[0]))
2894 return "fld%z1\t%y1";
2899 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2900 return "fstp%z0\t%y0";
2902 return "fst%z0\t%y0";
2905 switch (standard_80387_constant_p (operands[1]))
2918 return "pxor\t%0, %0";
2920 if (TARGET_PARTIAL_REG_DEPENDENCY)
2921 return "movapd\t{%1, %0|%0, %1}";
2923 return "movsd\t{%1, %0|%0, %1}";
2926 return "movsd\t{%1, %0|%0, %1}";
2932 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2933 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2935 (define_insn "*movdf_integer"
2936 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2937 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2938 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2939 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2940 && (reload_in_progress || reload_completed
2941 || GET_CODE (operands[1]) != CONST_DOUBLE
2942 || memory_operand (operands[0], DFmode))"
2944 switch (which_alternative)
2947 if (REG_P (operands[1])
2948 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2950 else if (STACK_TOP_P (operands[0]))
2951 return "fld%z1\t%y1";
2956 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2957 return "fstp%z0\t%y0";
2959 return "fst%z0\t%y0";
2962 switch (standard_80387_constant_p (operands[1]))
2976 return "pxor\t%0, %0";
2978 if (TARGET_PARTIAL_REG_DEPENDENCY)
2979 return "movapd\t{%1, %0|%0, %1}";
2981 return "movsd\t{%1, %0|%0, %1}";
2984 return "movsd\t{%1, %0|%0, %1}";
2990 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2991 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2994 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2995 (match_operand:DF 1 "general_operand" ""))]
2997 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2998 && ! (ANY_FP_REG_P (operands[0]) ||
2999 (GET_CODE (operands[0]) == SUBREG
3000 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3001 && ! (ANY_FP_REG_P (operands[1]) ||
3002 (GET_CODE (operands[1]) == SUBREG
3003 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3005 "ix86_split_long_move (operands); DONE;")
3007 (define_insn "*swapdf"
3008 [(set (match_operand:DF 0 "register_operand" "+f")
3009 (match_operand:DF 1 "register_operand" "+f"))
3012 "reload_completed || !TARGET_SSE2"
3014 if (STACK_TOP_P (operands[0]))
3019 [(set_attr "type" "fxch")
3020 (set_attr "mode" "DF")])
3022 (define_expand "movxf"
3023 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3024 (match_operand:XF 1 "general_operand" ""))]
3026 "ix86_expand_move (XFmode, operands); DONE;")
3028 (define_expand "movtf"
3029 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3030 (match_operand:TF 1 "general_operand" ""))]
3032 "ix86_expand_move (TFmode, operands); DONE;")
3034 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
3035 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
3036 ;; Pushing using integer instructions is longer except for constants
3037 ;; and direct memory references.
3038 ;; (assuming that any given constant is pushed only once, but this ought to be
3039 ;; handled elsewhere).
3041 (define_insn "*pushxf_nointeger"
3042 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3043 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3044 "optimize_size && !TARGET_64BIT"
3046 switch (which_alternative)
3049 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3050 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3051 operands[2] = stack_pointer_rtx;
3052 operands[3] = GEN_INT (12);
3053 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3054 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3056 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3066 [(set_attr "type" "multi")
3067 (set_attr "mode" "XF,SI,SI")])
3069 (define_insn "*pushtf_nointeger"
3070 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
3071 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
3074 switch (which_alternative)
3077 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3078 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3079 operands[2] = stack_pointer_rtx;
3080 operands[3] = GEN_INT (16);
3081 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3082 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3084 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3094 [(set_attr "type" "multi")
3095 (set_attr "mode" "XF,SI,SI")])
3097 (define_insn "*pushxf_integer"
3098 [(set (match_operand:XF 0 "push_operand" "=<,<")
3099 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
3100 "!optimize_size && !TARGET_64BIT"
3102 switch (which_alternative)
3105 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3106 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3107 operands[2] = stack_pointer_rtx;
3108 operands[3] = GEN_INT (12);
3109 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3110 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3112 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3121 [(set_attr "type" "multi")
3122 (set_attr "mode" "XF,SI")])
3124 (define_insn "*pushtf_integer"
3125 [(set (match_operand:TF 0 "push_operand" "=<,<")
3126 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
3129 switch (which_alternative)
3132 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3133 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3134 operands[2] = stack_pointer_rtx;
3135 operands[3] = GEN_INT (16);
3137 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3138 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3140 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3142 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3143 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
3145 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
3154 [(set_attr "type" "multi")
3155 (set_attr "mode" "XF,SI")])
3158 [(set (match_operand 0 "push_operand" "")
3159 (match_operand 1 "general_operand" ""))]
3161 && (GET_MODE (operands[0]) == XFmode
3162 || GET_MODE (operands[0]) == TFmode
3163 || GET_MODE (operands[0]) == DFmode)
3164 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
3166 "ix86_split_long_move (operands); DONE;")
3169 [(set (match_operand:XF 0 "push_operand" "")
3170 (match_operand:XF 1 "register_operand" ""))]
3171 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3172 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3173 (set (mem:XF (reg:SI 7)) (match_dup 1))])
3176 [(set (match_operand:TF 0 "push_operand" "")
3177 (match_operand:TF 1 "register_operand" ""))]
3178 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3179 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3180 (set (mem:TF (reg:SI 7)) (match_dup 1))])
3183 [(set (match_operand:TF 0 "push_operand" "")
3184 (match_operand:TF 1 "register_operand" ""))]
3185 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3186 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3187 (set (mem:TF (reg:DI 7)) (match_dup 1))])
3189 ;; Do not use integer registers when optimizing for size
3190 (define_insn "*movxf_nointeger"
3191 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3192 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3193 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3196 && (reload_in_progress || reload_completed
3197 || GET_CODE (operands[1]) != CONST_DOUBLE
3198 || memory_operand (operands[0], XFmode))"
3200 switch (which_alternative)
3203 if (REG_P (operands[1])
3204 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3206 else if (STACK_TOP_P (operands[0]))
3207 return "fld%z1\t%y1";
3212 /* There is no non-popping store to memory for XFmode. So if
3213 we need one, follow the store with a load. */
3214 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3215 return "fstp%z0\t%y0\;fld%z0\t%y0";
3217 return "fstp%z0\t%y0";
3220 switch (standard_80387_constant_p (operands[1]))
3234 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3235 (set_attr "mode" "XF,XF,XF,SI,SI")])
3237 (define_insn "*movtf_nointeger"
3238 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3239 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3240 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3242 && (reload_in_progress || reload_completed
3243 || GET_CODE (operands[1]) != CONST_DOUBLE
3244 || memory_operand (operands[0], TFmode))"
3246 switch (which_alternative)
3249 if (REG_P (operands[1])
3250 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3252 else if (STACK_TOP_P (operands[0]))
3253 return "fld%z1\t%y1";
3258 /* There is no non-popping store to memory for XFmode. So if
3259 we need one, follow the store with a load. */
3260 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3261 return "fstp%z0\t%y0\;fld%z0\t%y0";
3263 return "fstp%z0\t%y0";
3266 switch (standard_80387_constant_p (operands[1]))
3280 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3281 (set_attr "mode" "XF,XF,XF,SI,SI")])
3283 (define_insn "*movxf_integer"
3284 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3285 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3286 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3289 && (reload_in_progress || reload_completed
3290 || GET_CODE (operands[1]) != CONST_DOUBLE
3291 || memory_operand (operands[0], XFmode))"
3293 switch (which_alternative)
3296 if (REG_P (operands[1])
3297 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3299 else if (STACK_TOP_P (operands[0]))
3300 return "fld%z1\t%y1";
3305 /* There is no non-popping store to memory for XFmode. So if
3306 we need one, follow the store with a load. */
3307 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3308 return "fstp%z0\t%y0\;fld%z0\t%y0";
3310 return "fstp%z0\t%y0";
3313 switch (standard_80387_constant_p (operands[1]))
3327 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3328 (set_attr "mode" "XF,XF,XF,SI,SI")])
3330 (define_insn "*movtf_integer"
3331 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3332 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3333 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3335 && (reload_in_progress || reload_completed
3336 || GET_CODE (operands[1]) != CONST_DOUBLE
3337 || memory_operand (operands[0], TFmode))"
3339 switch (which_alternative)
3342 if (REG_P (operands[1])
3343 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3345 else if (STACK_TOP_P (operands[0]))
3346 return "fld%z1\t%y1";
3351 /* There is no non-popping store to memory for XFmode. So if
3352 we need one, follow the store with a load. */
3353 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3354 return "fstp%z0\t%y0\;fld%z0\t%y0";
3356 return "fstp%z0\t%y0";
3359 switch (standard_80387_constant_p (operands[1]))
3373 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3374 (set_attr "mode" "XF,XF,XF,SI,SI")])
3377 [(set (match_operand 0 "nonimmediate_operand" "")
3378 (match_operand 1 "general_operand" ""))]
3380 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3381 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3382 && ! (ANY_FP_REG_P (operands[0]) ||
3383 (GET_CODE (operands[0]) == SUBREG
3384 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3385 && ! (ANY_FP_REG_P (operands[1]) ||
3386 (GET_CODE (operands[1]) == SUBREG
3387 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3389 "ix86_split_long_move (operands); DONE;")
3392 [(set (match_operand 0 "register_operand" "")
3393 (match_operand 1 "memory_operand" ""))]
3395 && GET_CODE (operands[1]) == MEM
3396 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3397 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3398 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3399 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3400 && (!(SSE_REG_P (operands[0]) ||
3401 (GET_CODE (operands[0]) == SUBREG
3402 && SSE_REG_P (SUBREG_REG (operands[0]))))
3403 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3404 && (!(FP_REG_P (operands[0]) ||
3405 (GET_CODE (operands[0]) == SUBREG
3406 && FP_REG_P (SUBREG_REG (operands[0]))))
3407 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3410 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3412 (define_insn "swapxf"
3413 [(set (match_operand:XF 0 "register_operand" "+f")
3414 (match_operand:XF 1 "register_operand" "+f"))
3419 if (STACK_TOP_P (operands[0]))
3424 [(set_attr "type" "fxch")
3425 (set_attr "mode" "XF")])
3427 (define_insn "swaptf"
3428 [(set (match_operand:TF 0 "register_operand" "+f")
3429 (match_operand:TF 1 "register_operand" "+f"))
3434 if (STACK_TOP_P (operands[0]))
3439 [(set_attr "type" "fxch")
3440 (set_attr "mode" "XF")])
3442 ;; Zero extension instructions
3444 (define_expand "zero_extendhisi2"
3445 [(set (match_operand:SI 0 "register_operand" "")
3446 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3449 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3451 operands[1] = force_reg (HImode, operands[1]);
3452 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3457 (define_insn "zero_extendhisi2_and"
3458 [(set (match_operand:SI 0 "register_operand" "=r")
3459 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3460 (clobber (reg:CC 17))]
3461 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3463 [(set_attr "type" "alu1")
3464 (set_attr "mode" "SI")])
3467 [(set (match_operand:SI 0 "register_operand" "")
3468 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3469 (clobber (reg:CC 17))]
3470 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3471 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3472 (clobber (reg:CC 17))])]
3475 (define_insn "*zero_extendhisi2_movzwl"
3476 [(set (match_operand:SI 0 "register_operand" "=r")
3477 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3478 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3479 "movz{wl|x}\t{%1, %0|%0, %1}"
3480 [(set_attr "type" "imovx")
3481 (set_attr "mode" "SI")])
3483 (define_expand "zero_extendqihi2"
3485 [(set (match_operand:HI 0 "register_operand" "")
3486 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3487 (clobber (reg:CC 17))])]
3491 (define_insn "*zero_extendqihi2_and"
3492 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3493 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3494 (clobber (reg:CC 17))]
3495 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3497 [(set_attr "type" "alu1")
3498 (set_attr "mode" "HI")])
3500 (define_insn "*zero_extendqihi2_movzbw_and"
3501 [(set (match_operand:HI 0 "register_operand" "=r,r")
3502 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3503 (clobber (reg:CC 17))]
3504 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3506 [(set_attr "type" "imovx,alu1")
3507 (set_attr "mode" "HI")])
3509 (define_insn "*zero_extendqihi2_movzbw"
3510 [(set (match_operand:HI 0 "register_operand" "=r")
3511 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3512 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3513 "movz{bw|x}\t{%1, %0|%0, %1}"
3514 [(set_attr "type" "imovx")
3515 (set_attr "mode" "HI")])
3517 ;; For the movzbw case strip only the clobber
3519 [(set (match_operand:HI 0 "register_operand" "")
3520 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3521 (clobber (reg:CC 17))]
3523 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3524 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3525 [(set (match_operand:HI 0 "register_operand" "")
3526 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3528 ;; When source and destination does not overlap, clear destination
3529 ;; first and then do the movb
3531 [(set (match_operand:HI 0 "register_operand" "")
3532 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3533 (clobber (reg:CC 17))]
3535 && ANY_QI_REG_P (operands[0])
3536 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3537 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3538 [(set (match_dup 0) (const_int 0))
3539 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3540 "operands[2] = gen_lowpart (QImode, operands[0]);")
3542 ;; Rest is handled by single and.
3544 [(set (match_operand:HI 0 "register_operand" "")
3545 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3546 (clobber (reg:CC 17))]
3548 && true_regnum (operands[0]) == true_regnum (operands[1])"
3549 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3550 (clobber (reg:CC 17))])]
3553 (define_expand "zero_extendqisi2"
3555 [(set (match_operand:SI 0 "register_operand" "")
3556 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3557 (clobber (reg:CC 17))])]
3561 (define_insn "*zero_extendqisi2_and"
3562 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3563 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3564 (clobber (reg:CC 17))]
3565 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3567 [(set_attr "type" "alu1")
3568 (set_attr "mode" "SI")])
3570 (define_insn "*zero_extendqisi2_movzbw_and"
3571 [(set (match_operand:SI 0 "register_operand" "=r,r")
3572 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3573 (clobber (reg:CC 17))]
3574 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3576 [(set_attr "type" "imovx,alu1")
3577 (set_attr "mode" "SI")])
3579 (define_insn "*zero_extendqisi2_movzbw"
3580 [(set (match_operand:SI 0 "register_operand" "=r")
3581 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3582 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3583 "movz{bl|x}\t{%1, %0|%0, %1}"
3584 [(set_attr "type" "imovx")
3585 (set_attr "mode" "SI")])
3587 ;; For the movzbl case strip only the clobber
3589 [(set (match_operand:SI 0 "register_operand" "")
3590 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3591 (clobber (reg:CC 17))]
3593 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3594 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3596 (zero_extend:SI (match_dup 1)))])
3598 ;; When source and destination does not overlap, clear destination
3599 ;; first and then do the movb
3601 [(set (match_operand:SI 0 "register_operand" "")
3602 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3603 (clobber (reg:CC 17))]
3605 && ANY_QI_REG_P (operands[0])
3606 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3607 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3608 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3609 [(set (match_dup 0) (const_int 0))
3610 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3611 "operands[2] = gen_lowpart (QImode, operands[0]);")
3613 ;; Rest is handled by single and.
3615 [(set (match_operand:SI 0 "register_operand" "")
3616 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3617 (clobber (reg:CC 17))]
3619 && true_regnum (operands[0]) == true_regnum (operands[1])"
3620 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3621 (clobber (reg:CC 17))])]
3624 ;; %%% Kill me once multi-word ops are sane.
3625 (define_expand "zero_extendsidi2"
3626 [(set (match_operand:DI 0 "register_operand" "=r")
3627 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3631 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3636 (define_insn "zero_extendsidi2_32"
3637 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3638 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3639 (clobber (reg:CC 17))]
3642 [(set_attr "mode" "SI")])
3644 (define_insn "zero_extendsidi2_rex64"
3645 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3646 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3649 mov\t{%k1, %k0|%k0, %k1}
3651 [(set_attr "type" "imovx,imov")
3652 (set_attr "mode" "SI,DI")])
3655 [(set (match_operand:DI 0 "memory_operand" "")
3656 (zero_extend:DI (match_dup 0)))]
3658 [(set (match_dup 4) (const_int 0))]
3659 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3662 [(set (match_operand:DI 0 "register_operand" "")
3663 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3664 (clobber (reg:CC 17))]
3665 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
3667 [(set (match_dup 4) (const_int 0))]
3668 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3671 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3672 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3673 (clobber (reg:CC 17))]
3674 "reload_completed && !TARGET_64BIT"
3675 [(set (match_dup 3) (match_dup 1))
3676 (set (match_dup 4) (const_int 0))]
3677 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3679 (define_insn "zero_extendhidi2"
3680 [(set (match_operand:DI 0 "register_operand" "=r,r")
3681 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3684 movz{wl|x}\t{%1, %k0|%k0, %1}
3685 movz{wq|x}\t{%1, %0|%0, %1}"
3686 [(set_attr "type" "imovx")
3687 (set_attr "mode" "SI,DI")])
3689 (define_insn "zero_extendqidi2"
3690 [(set (match_operand:DI 0 "register_operand" "=r,r")
3691 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3694 movz{bl|x}\t{%1, %k0|%k0, %1}
3695 movz{bq|x}\t{%1, %0|%0, %1}"
3696 [(set_attr "type" "imovx")
3697 (set_attr "mode" "SI,DI")])
3699 ;; Sign extension instructions
3701 (define_expand "extendsidi2"
3702 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3703 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3704 (clobber (reg:CC 17))
3705 (clobber (match_scratch:SI 2 ""))])]
3710 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3715 (define_insn "*extendsidi2_1"
3716 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3717 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3718 (clobber (reg:CC 17))
3719 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3723 (define_insn "extendsidi2_rex64"
3724 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3725 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3729 movs{lq|x}\t{%1,%0|%0, %1}"
3730 [(set_attr "type" "imovx")
3731 (set_attr "mode" "DI")
3732 (set_attr "prefix_0f" "0")
3733 (set_attr "modrm" "0,1")])
3735 (define_insn "extendhidi2"
3736 [(set (match_operand:DI 0 "register_operand" "=r")
3737 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3739 "movs{wq|x}\t{%1,%0|%0, %1}"
3740 [(set_attr "type" "imovx")
3741 (set_attr "mode" "DI")])
3743 (define_insn "extendqidi2"
3744 [(set (match_operand:DI 0 "register_operand" "=r")
3745 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3747 "movs{bq|x}\t{%1,%0|%0, %1}"
3748 [(set_attr "type" "imovx")
3749 (set_attr "mode" "DI")])
3751 ;; Extend to memory case when source register does die.
3753 [(set (match_operand:DI 0 "memory_operand" "")
3754 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3755 (clobber (reg:CC 17))
3756 (clobber (match_operand:SI 2 "register_operand" ""))]
3758 && dead_or_set_p (insn, operands[1])
3759 && !reg_mentioned_p (operands[1], operands[0]))"
3760 [(set (match_dup 3) (match_dup 1))
3761 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3762 (clobber (reg:CC 17))])
3763 (set (match_dup 4) (match_dup 1))]
3764 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3766 ;; Extend to memory case when source register does not die.
3768 [(set (match_operand:DI 0 "memory_operand" "")
3769 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3770 (clobber (reg:CC 17))
3771 (clobber (match_operand:SI 2 "register_operand" ""))]
3775 split_di (&operands[0], 1, &operands[3], &operands[4]);
3777 emit_move_insn (operands[3], operands[1]);
3779 /* Generate a cltd if possible and doing so it profitable. */
3780 if (true_regnum (operands[1]) == 0
3781 && true_regnum (operands[2]) == 1
3782 && (optimize_size || TARGET_USE_CLTD))
3784 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3788 emit_move_insn (operands[2], operands[1]);
3789 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3791 emit_move_insn (operands[4], operands[2]);
3795 ;; Extend to register case. Optimize case where source and destination
3796 ;; registers match and cases where we can use cltd.
3798 [(set (match_operand:DI 0 "register_operand" "")
3799 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3800 (clobber (reg:CC 17))
3801 (clobber (match_scratch:SI 2 ""))]
3805 split_di (&operands[0], 1, &operands[3], &operands[4]);
3807 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3808 emit_move_insn (operands[3], operands[1]);
3810 /* Generate a cltd if possible and doing so it profitable. */
3811 if (true_regnum (operands[3]) == 0
3812 && (optimize_size || TARGET_USE_CLTD))
3814 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3818 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3819 emit_move_insn (operands[4], operands[1]);
3821 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3825 (define_insn "extendhisi2"
3826 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3827 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3830 switch (get_attr_prefix_0f (insn))
3833 return "{cwtl|cwde}";
3835 return "movs{wl|x}\t{%1,%0|%0, %1}";
3838 [(set_attr "type" "imovx")
3839 (set_attr "mode" "SI")
3840 (set (attr "prefix_0f")
3841 ;; movsx is short decodable while cwtl is vector decoded.
3842 (if_then_else (and (eq_attr "cpu" "!k6")
3843 (eq_attr "alternative" "0"))
3845 (const_string "1")))
3847 (if_then_else (eq_attr "prefix_0f" "0")
3849 (const_string "1")))])
3851 (define_insn "*extendhisi2_zext"
3852 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3854 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3857 switch (get_attr_prefix_0f (insn))
3860 return "{cwtl|cwde}";
3862 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3865 [(set_attr "type" "imovx")
3866 (set_attr "mode" "SI")
3867 (set (attr "prefix_0f")
3868 ;; movsx is short decodable while cwtl is vector decoded.
3869 (if_then_else (and (eq_attr "cpu" "!k6")
3870 (eq_attr "alternative" "0"))
3872 (const_string "1")))
3874 (if_then_else (eq_attr "prefix_0f" "0")
3876 (const_string "1")))])
3878 (define_insn "extendqihi2"
3879 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3880 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3883 switch (get_attr_prefix_0f (insn))
3886 return "{cbtw|cbw}";
3888 return "movs{bw|x}\t{%1,%0|%0, %1}";
3891 [(set_attr "type" "imovx")
3892 (set_attr "mode" "HI")
3893 (set (attr "prefix_0f")
3894 ;; movsx is short decodable while cwtl is vector decoded.
3895 (if_then_else (and (eq_attr "cpu" "!k6")
3896 (eq_attr "alternative" "0"))
3898 (const_string "1")))
3900 (if_then_else (eq_attr "prefix_0f" "0")
3902 (const_string "1")))])
3904 (define_insn "extendqisi2"
3905 [(set (match_operand:SI 0 "register_operand" "=r")
3906 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3908 "movs{bl|x}\t{%1,%0|%0, %1}"
3909 [(set_attr "type" "imovx")
3910 (set_attr "mode" "SI")])
3912 (define_insn "*extendqisi2_zext"
3913 [(set (match_operand:DI 0 "register_operand" "=r")
3915 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3917 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3918 [(set_attr "type" "imovx")
3919 (set_attr "mode" "SI")])
3921 ;; Conversions between float and double.
3923 ;; These are all no-ops in the model used for the 80387. So just
3926 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3927 (define_insn "*dummy_extendsfdf2"
3928 [(set (match_operand:DF 0 "push_operand" "=<")
3929 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3934 [(set (match_operand:DF 0 "push_operand" "")
3935 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3936 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3937 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3938 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3941 [(set (match_operand:DF 0 "push_operand" "")
3942 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3943 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3944 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3945 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3947 (define_insn "*dummy_extendsfxf2"
3948 [(set (match_operand:XF 0 "push_operand" "=<")
3949 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3954 [(set (match_operand:XF 0 "push_operand" "")
3955 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3956 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3957 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3958 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3960 (define_insn "*dummy_extendsftf2"
3961 [(set (match_operand:TF 0 "push_operand" "=<")
3962 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3967 [(set (match_operand:TF 0 "push_operand" "")
3968 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3969 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3970 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3971 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3974 [(set (match_operand:TF 0 "push_operand" "")
3975 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3976 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3977 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3978 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3980 (define_insn "*dummy_extenddfxf2"
3981 [(set (match_operand:XF 0 "push_operand" "=<")
3982 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3987 [(set (match_operand:XF 0 "push_operand" "")
3988 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
3989 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3990 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3991 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3993 (define_insn "*dummy_extenddftf2"
3994 [(set (match_operand:TF 0 "push_operand" "=<")
3995 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4000 [(set (match_operand:TF 0 "push_operand" "")
4001 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4002 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4003 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4004 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4007 [(set (match_operand:TF 0 "push_operand" "")
4008 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4009 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4010 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4011 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
4013 (define_expand "extendsfdf2"
4014 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4015 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
4016 "TARGET_80387 || TARGET_SSE2"
4018 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4019 operands[1] = force_reg (SFmode, operands[1]);
4022 (define_insn "*extendsfdf2_1"
4023 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
4024 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
4025 "(TARGET_80387 || TARGET_SSE2)
4026 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4028 switch (which_alternative)
4031 if (REG_P (operands[1])
4032 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4034 else if (STACK_TOP_P (operands[0]))
4035 return "fld%z1\t%y1";
4040 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4041 return "fstp%z0\t%y0";
4044 return "fst%z0\t%y0";
4046 return "cvtss2sd\t{%1, %0|%0, %1}";
4052 [(set_attr "type" "fmov,fmov,sse")
4053 (set_attr "mode" "SF,XF,DF")])
4055 (define_insn "*extendsfdf2_1_sse_only"
4056 [(set (match_operand:DF 0 "register_operand" "=Y")
4057 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
4058 "!TARGET_80387 && TARGET_SSE2
4059 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4060 "cvtss2sd\t{%1, %0|%0, %1}"
4061 [(set_attr "type" "sse")
4062 (set_attr "mode" "DF")])
4064 (define_expand "extendsfxf2"
4065 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4066 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
4067 "TARGET_80387 && !TARGET_64BIT"
4069 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4070 operands[1] = force_reg (SFmode, operands[1]);
4073 (define_insn "*extendsfxf2_1"
4074 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4075 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4076 "TARGET_80387 && !TARGET_64BIT
4077 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4079 switch (which_alternative)
4082 if (REG_P (operands[1])
4083 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4085 else if (STACK_TOP_P (operands[0]))
4086 return "fld%z1\t%y1";
4091 /* There is no non-popping store to memory for XFmode. So if
4092 we need one, follow the store with a load. */
4093 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4094 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4096 return "fstp%z0\t%y0";
4102 [(set_attr "type" "fmov")
4103 (set_attr "mode" "SF,XF")])
4105 (define_expand "extendsftf2"
4106 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4107 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
4110 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4111 operands[1] = force_reg (SFmode, operands[1]);
4114 (define_insn "*extendsftf2_1"
4115 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4116 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4118 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4120 switch (which_alternative)
4123 if (REG_P (operands[1])
4124 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4126 else if (STACK_TOP_P (operands[0]))
4127 return "fld%z1\t%y1";
4132 /* There is no non-popping store to memory for XFmode. So if
4133 we need one, follow the store with a load. */
4134 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4135 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4137 return "fstp%z0\t%y0";
4143 [(set_attr "type" "fmov")
4144 (set_attr "mode" "SF,XF")])
4146 (define_expand "extenddfxf2"
4147 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4148 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
4149 "TARGET_80387 && !TARGET_64BIT"
4151 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4152 operands[1] = force_reg (DFmode, operands[1]);
4155 (define_insn "*extenddfxf2_1"
4156 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4157 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4158 "TARGET_80387 && !TARGET_64BIT
4159 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4161 switch (which_alternative)
4164 if (REG_P (operands[1])
4165 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4167 else if (STACK_TOP_P (operands[0]))
4168 return "fld%z1\t%y1";
4173 /* There is no non-popping store to memory for XFmode. So if
4174 we need one, follow the store with a load. */
4175 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4176 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4178 return "fstp%z0\t%y0";
4184 [(set_attr "type" "fmov")
4185 (set_attr "mode" "DF,XF")])
4187 (define_expand "extenddftf2"
4188 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4189 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
4192 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4193 operands[1] = force_reg (DFmode, operands[1]);
4196 (define_insn "*extenddftf2_1"
4197 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4198 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4200 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4202 switch (which_alternative)
4205 if (REG_P (operands[1])
4206 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4208 else if (STACK_TOP_P (operands[0]))
4209 return "fld%z1\t%y1";
4214 /* There is no non-popping store to memory for XFmode. So if
4215 we need one, follow the store with a load. */
4216 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4217 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
4219 return "fstp%z0\t%y0";
4225 [(set_attr "type" "fmov")
4226 (set_attr "mode" "DF,XF")])
4228 ;; %%% This seems bad bad news.
4229 ;; This cannot output into an f-reg because there is no way to be sure
4230 ;; of truncating in that case. Otherwise this is just like a simple move
4231 ;; insn. So we pretend we can output to a reg in order to get better
4232 ;; register preferencing, but we really use a stack slot.
4234 (define_expand "truncdfsf2"
4235 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4237 (match_operand:DF 1 "register_operand" "")))
4238 (clobber (match_dup 2))])]
4239 "TARGET_80387 || TARGET_SSE2"
4242 operands[2] = assign_386_stack_local (SFmode, 0);
4245 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4250 (define_insn "*truncdfsf2_1"
4251 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4253 (match_operand:DF 1 "register_operand" "f,f,f,f")))
4254 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4255 "TARGET_80387 && !TARGET_SSE2"
4257 switch (which_alternative)
4260 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4261 return "fstp%z0\t%y0";
4263 return "fst%z0\t%y0";
4268 [(set_attr "type" "fmov,multi,multi,multi")
4269 (set_attr "mode" "SF,SF,SF,SF")])
4271 (define_insn "*truncdfsf2_1_sse"
4272 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
4274 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
4275 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
4276 "TARGET_80387 && TARGET_SSE2"
4278 switch (which_alternative)
4281 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4282 return "fstp%z0\t%y0";
4284 return "fst%z0\t%y0";
4286 return "cvtsd2ss\t{%1, %0|%0, %1}";
4291 [(set_attr "type" "fmov,multi,multi,multi,sse")
4292 (set_attr "mode" "SF,SF,SF,SF,DF")])
4294 (define_insn "*truncdfsf2_2"
4295 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
4297 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4298 "TARGET_80387 && TARGET_SSE2
4299 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4301 switch (which_alternative)
4304 return "cvtsd2ss\t{%1, %0|%0, %1}";
4306 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4307 return "fstp%z0\t%y0";
4309 return "fst%z0\t%y0";
4314 [(set_attr "type" "sse,fmov")
4315 (set_attr "mode" "DF,SF")])
4317 (define_insn "truncdfsf2_3"
4318 [(set (match_operand:SF 0 "memory_operand" "=m")
4320 (match_operand:DF 1 "register_operand" "f")))]
4323 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4324 return "fstp%z0\t%y0";
4326 return "fst%z0\t%y0";
4328 [(set_attr "type" "fmov")
4329 (set_attr "mode" "SF")])
4331 (define_insn "truncdfsf2_sse_only"
4332 [(set (match_operand:SF 0 "register_operand" "=Y")
4334 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4335 "!TARGET_80387 && TARGET_SSE2"
4336 "cvtsd2ss\t{%1, %0|%0, %1}"
4337 [(set_attr "type" "sse")
4338 (set_attr "mode" "DF")])
4341 [(set (match_operand:SF 0 "memory_operand" "")
4343 (match_operand:DF 1 "register_operand" "")))
4344 (clobber (match_operand:SF 2 "memory_operand" ""))]
4346 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4350 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4352 (match_operand:DF 1 "nonimmediate_operand" "")))
4353 (clobber (match_operand 2 "" ""))]
4354 "TARGET_80387 && reload_completed
4355 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
4356 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4360 [(set (match_operand:SF 0 "register_operand" "")
4362 (match_operand:DF 1 "register_operand" "")))
4363 (clobber (match_operand:SF 2 "memory_operand" ""))]
4364 "TARGET_80387 && reload_completed
4365 && FP_REG_P (operands[1])"
4366 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4367 (set (match_dup 0) (match_dup 2))]
4370 (define_expand "truncxfsf2"
4371 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4373 (match_operand:XF 1 "register_operand" "")))
4374 (clobber (match_dup 2))])]
4375 "TARGET_80387 && !TARGET_64BIT"
4376 "operands[2] = assign_386_stack_local (SFmode, 0);")
4378 (define_insn "*truncxfsf2_1"
4379 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4381 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4382 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4383 "TARGET_80387 && !TARGET_64BIT"
4385 switch (which_alternative)
4388 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4389 return "fstp%z0\t%y0";
4391 return "fst%z0\t%y0";
4396 [(set_attr "type" "fmov,multi,multi,multi")
4397 (set_attr "mode" "SF")])
4399 (define_insn "*truncxfsf2_2"
4400 [(set (match_operand:SF 0 "memory_operand" "=m")
4402 (match_operand:XF 1 "register_operand" "f")))]
4403 "TARGET_80387 && !TARGET_64BIT"
4405 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4406 return "fstp%z0\t%y0";
4408 return "fst%z0\t%y0";
4410 [(set_attr "type" "fmov")
4411 (set_attr "mode" "SF")])
4414 [(set (match_operand:SF 0 "memory_operand" "")
4416 (match_operand:XF 1 "register_operand" "")))
4417 (clobber (match_operand:SF 2 "memory_operand" ""))]
4419 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4423 [(set (match_operand:SF 0 "register_operand" "")
4425 (match_operand:XF 1 "register_operand" "")))
4426 (clobber (match_operand:SF 2 "memory_operand" ""))]
4427 "TARGET_80387 && reload_completed"
4428 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4429 (set (match_dup 0) (match_dup 2))]
4432 (define_expand "trunctfsf2"
4433 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4435 (match_operand:TF 1 "register_operand" "")))
4436 (clobber (match_dup 2))])]
4438 "operands[2] = assign_386_stack_local (SFmode, 0);")
4440 (define_insn "*trunctfsf2_1"
4441 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4443 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4444 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4447 switch (which_alternative)
4450 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4451 return "fstp%z0\t%y0";
4453 return "fst%z0\t%y0";
4458 [(set_attr "type" "fmov,multi,multi,multi")
4459 (set_attr "mode" "SF")])
4461 (define_insn "*trunctfsf2_2"
4462 [(set (match_operand:SF 0 "memory_operand" "=m")
4464 (match_operand:TF 1 "register_operand" "f")))]
4467 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4468 return "fstp%z0\t%y0";
4470 return "fst%z0\t%y0";
4472 [(set_attr "type" "fmov")
4473 (set_attr "mode" "SF")])
4476 [(set (match_operand:SF 0 "memory_operand" "")
4478 (match_operand:TF 1 "register_operand" "")))
4479 (clobber (match_operand:SF 2 "memory_operand" ""))]
4481 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4485 [(set (match_operand:SF 0 "register_operand" "")
4487 (match_operand:TF 1 "register_operand" "")))
4488 (clobber (match_operand:SF 2 "memory_operand" ""))]
4489 "TARGET_80387 && reload_completed"
4490 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4491 (set (match_dup 0) (match_dup 2))]
4495 (define_expand "truncxfdf2"
4496 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4498 (match_operand:XF 1 "register_operand" "")))
4499 (clobber (match_dup 2))])]
4500 "TARGET_80387 && !TARGET_64BIT"
4501 "operands[2] = assign_386_stack_local (DFmode, 0);")
4503 (define_insn "*truncxfdf2_1"
4504 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4506 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4507 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4508 "TARGET_80387 && !TARGET_64BIT"
4510 switch (which_alternative)
4513 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4514 return "fstp%z0\t%y0";
4516 return "fst%z0\t%y0";
4522 [(set_attr "type" "fmov,multi,multi,multi")
4523 (set_attr "mode" "DF")])
4525 (define_insn "*truncxfdf2_2"
4526 [(set (match_operand:DF 0 "memory_operand" "=m")
4528 (match_operand:XF 1 "register_operand" "f")))]
4529 "TARGET_80387 && !TARGET_64BIT"
4531 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4532 return "fstp%z0\t%y0";
4534 return "fst%z0\t%y0";
4536 [(set_attr "type" "fmov")
4537 (set_attr "mode" "DF")])
4540 [(set (match_operand:DF 0 "memory_operand" "")
4542 (match_operand:XF 1 "register_operand" "")))
4543 (clobber (match_operand:DF 2 "memory_operand" ""))]
4545 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4549 [(set (match_operand:DF 0 "register_operand" "")
4551 (match_operand:XF 1 "register_operand" "")))
4552 (clobber (match_operand:DF 2 "memory_operand" ""))]
4553 "TARGET_80387 && reload_completed"
4554 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4555 (set (match_dup 0) (match_dup 2))]
4558 (define_expand "trunctfdf2"
4559 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4561 (match_operand:TF 1 "register_operand" "")))
4562 (clobber (match_dup 2))])]
4564 "operands[2] = assign_386_stack_local (DFmode, 0);")
4566 (define_insn "*trunctfdf2_1"
4567 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4569 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4570 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4573 switch (which_alternative)
4576 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4577 return "fstp%z0\t%y0";
4579 return "fst%z0\t%y0";
4585 [(set_attr "type" "fmov,multi,multi,multi")
4586 (set_attr "mode" "DF")])
4588 (define_insn "*trunctfdf2_2"
4589 [(set (match_operand:DF 0 "memory_operand" "=m")
4591 (match_operand:TF 1 "register_operand" "f")))]
4594 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4595 return "fstp%z0\t%y0";
4597 return "fst%z0\t%y0";
4599 [(set_attr "type" "fmov")
4600 (set_attr "mode" "DF")])
4603 [(set (match_operand:DF 0 "memory_operand" "")
4605 (match_operand:TF 1 "register_operand" "")))
4606 (clobber (match_operand:DF 2 "memory_operand" ""))]
4608 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4612 [(set (match_operand:DF 0 "register_operand" "")
4614 (match_operand:TF 1 "register_operand" "")))
4615 (clobber (match_operand:DF 2 "memory_operand" ""))]
4616 "TARGET_80387 && reload_completed"
4617 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4618 (set (match_dup 0) (match_dup 2))]
4622 ;; %%% Break up all these bad boys.
4624 ;; Signed conversion to DImode.
4626 (define_expand "fix_truncxfdi2"
4627 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4628 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4629 "TARGET_80387 && !TARGET_64BIT"
4632 (define_expand "fix_trunctfdi2"
4633 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4634 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4638 (define_expand "fix_truncdfdi2"
4639 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4640 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4641 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4643 if (TARGET_SSE2 && TARGET_64BIT)
4645 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4646 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4647 if (out != operands[0])
4648 emit_move_insn (operands[0], out);
4653 (define_expand "fix_truncsfdi2"
4654 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4655 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4656 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4658 if (TARGET_SSE && TARGET_64BIT)
4660 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4661 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4662 if (out != operands[0])
4663 emit_move_insn (operands[0], out);
4668 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4669 ;; of the machinery.
4670 (define_insn_and_split "*fix_truncdi_1"
4671 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4672 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4673 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4674 && !reload_completed && !reload_in_progress
4675 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4680 operands[2] = assign_386_stack_local (HImode, 1);
4681 operands[3] = assign_386_stack_local (HImode, 2);
4682 if (memory_operand (operands[0], VOIDmode))
4683 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4684 operands[2], operands[3]));
4687 operands[4] = assign_386_stack_local (DImode, 0);
4688 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4689 operands[2], operands[3],
4694 [(set_attr "type" "fistp")])
4696 (define_insn "fix_truncdi_nomemory"
4697 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4698 (fix:DI (match_operand 1 "register_operand" "f,f")))
4699 (use (match_operand:HI 2 "memory_operand" "m,m"))
4700 (use (match_operand:HI 3 "memory_operand" "m,m"))
4701 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4702 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4703 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4704 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4706 [(set_attr "type" "fistp")])
4708 (define_insn "fix_truncdi_memory"
4709 [(set (match_operand:DI 0 "memory_operand" "=m")
4710 (fix:DI (match_operand 1 "register_operand" "f")))
4711 (use (match_operand:HI 2 "memory_operand" "m"))
4712 (use (match_operand:HI 3 "memory_operand" "m"))
4713 (clobber (match_scratch:DF 4 "=&1f"))]
4714 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4715 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4716 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4717 [(set_attr "type" "fistp")])
4720 [(set (match_operand:DI 0 "register_operand" "")
4721 (fix:DI (match_operand 1 "register_operand" "")))
4722 (use (match_operand:HI 2 "memory_operand" ""))
4723 (use (match_operand:HI 3 "memory_operand" ""))
4724 (clobber (match_operand:DI 4 "memory_operand" ""))
4725 (clobber (match_scratch 5 ""))]
4727 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4730 (clobber (match_dup 5))])
4731 (set (match_dup 0) (match_dup 4))]
4735 [(set (match_operand:DI 0 "memory_operand" "")
4736 (fix:DI (match_operand 1 "register_operand" "")))
4737 (use (match_operand:HI 2 "memory_operand" ""))
4738 (use (match_operand:HI 3 "memory_operand" ""))
4739 (clobber (match_operand:DI 4 "memory_operand" ""))
4740 (clobber (match_scratch 5 ""))]
4742 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4745 (clobber (match_dup 5))])]
4748 ;; When SSE available, it is always faster to use it!
4749 (define_insn "fix_truncsfdi_sse"
4750 [(set (match_operand:DI 0 "register_operand" "=r")
4751 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4752 "TARGET_SSE && TARGET_64BIT"
4753 "cvttss2si{q}\t{%1, %0|%0, %1}"
4754 [(set_attr "type" "sse")])
4756 (define_insn "fix_truncdfdi_sse"
4757 [(set (match_operand:DI 0 "register_operand" "=r")
4758 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4759 "TARGET_SSE2 && TARGET_64BIT"
4760 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4761 [(set_attr "type" "sse")])
4763 ;; Signed conversion to SImode.
4765 (define_expand "fix_truncxfsi2"
4766 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4767 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4768 "TARGET_80387 && !TARGET_64BIT"
4771 (define_expand "fix_trunctfsi2"
4772 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4773 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4777 (define_expand "fix_truncdfsi2"
4778 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4779 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4780 "TARGET_80387 || TARGET_SSE2"
4784 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4785 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4786 if (out != operands[0])
4787 emit_move_insn (operands[0], out);
4792 (define_expand "fix_truncsfsi2"
4793 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4794 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4795 "TARGET_80387 || TARGET_SSE"
4799 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4800 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4801 if (out != operands[0])
4802 emit_move_insn (operands[0], out);
4807 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4808 ;; of the machinery.
4809 (define_insn_and_split "*fix_truncsi_1"
4810 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4811 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4812 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4813 && !reload_completed && !reload_in_progress
4814 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4819 operands[2] = assign_386_stack_local (HImode, 1);
4820 operands[3] = assign_386_stack_local (HImode, 2);
4821 if (memory_operand (operands[0], VOIDmode))
4822 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4823 operands[2], operands[3]));
4826 operands[4] = assign_386_stack_local (SImode, 0);
4827 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4828 operands[2], operands[3],
4833 [(set_attr "type" "fistp")])
4835 (define_insn "fix_truncsi_nomemory"
4836 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4837 (fix:SI (match_operand 1 "register_operand" "f,f")))
4838 (use (match_operand:HI 2 "memory_operand" "m,m"))
4839 (use (match_operand:HI 3 "memory_operand" "m,m"))
4840 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4841 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4842 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4844 [(set_attr "type" "fistp")])
4846 (define_insn "fix_truncsi_memory"
4847 [(set (match_operand:SI 0 "memory_operand" "=m")
4848 (fix:SI (match_operand 1 "register_operand" "f")))
4849 (use (match_operand:HI 2 "memory_operand" "m"))
4850 (use (match_operand:HI 3 "memory_operand" "m"))]
4851 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4852 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4853 "* return output_fix_trunc (insn, operands);"
4854 [(set_attr "type" "fistp")])
4856 ;; When SSE available, it is always faster to use it!
4857 (define_insn "fix_truncsfsi_sse"
4858 [(set (match_operand:SI 0 "register_operand" "=r")
4859 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4861 "cvttss2si\t{%1, %0|%0, %1}"
4862 [(set_attr "type" "sse")])
4864 (define_insn "fix_truncdfsi_sse"
4865 [(set (match_operand:SI 0 "register_operand" "=r")
4866 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4868 "cvttsd2si\t{%1, %0|%0, %1}"
4869 [(set_attr "type" "sse")])
4872 [(set (match_operand:SI 0 "register_operand" "")
4873 (fix:SI (match_operand 1 "register_operand" "")))
4874 (use (match_operand:HI 2 "memory_operand" ""))
4875 (use (match_operand:HI 3 "memory_operand" ""))
4876 (clobber (match_operand:SI 4 "memory_operand" ""))]
4878 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4880 (use (match_dup 3))])
4881 (set (match_dup 0) (match_dup 4))]
4885 [(set (match_operand:SI 0 "memory_operand" "")
4886 (fix:SI (match_operand 1 "register_operand" "")))
4887 (use (match_operand:HI 2 "memory_operand" ""))
4888 (use (match_operand:HI 3 "memory_operand" ""))
4889 (clobber (match_operand:SI 4 "memory_operand" ""))]
4891 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4893 (use (match_dup 3))])]
4896 ;; Signed conversion to HImode.
4898 (define_expand "fix_truncxfhi2"
4899 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4900 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4901 "TARGET_80387 && !TARGET_64BIT"
4904 (define_expand "fix_trunctfhi2"
4905 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4906 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4910 (define_expand "fix_truncdfhi2"
4911 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4912 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4913 "TARGET_80387 && !TARGET_SSE2"
4916 (define_expand "fix_truncsfhi2"
4917 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4918 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4919 "TARGET_80387 && !TARGET_SSE"
4922 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4923 ;; of the machinery.
4924 (define_insn_and_split "*fix_trunchi_1"
4925 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4926 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4927 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4928 && !reload_completed && !reload_in_progress
4929 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4934 operands[2] = assign_386_stack_local (HImode, 1);
4935 operands[3] = assign_386_stack_local (HImode, 2);
4936 if (memory_operand (operands[0], VOIDmode))
4937 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4938 operands[2], operands[3]));
4941 operands[4] = assign_386_stack_local (HImode, 0);
4942 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4943 operands[2], operands[3],
4948 [(set_attr "type" "fistp")])
4950 (define_insn "fix_trunchi_nomemory"
4951 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4952 (fix:HI (match_operand 1 "register_operand" "f,f")))
4953 (use (match_operand:HI 2 "memory_operand" "m,m"))
4954 (use (match_operand:HI 3 "memory_operand" "m,m"))
4955 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4956 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4957 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4959 [(set_attr "type" "fistp")])
4961 (define_insn "fix_trunchi_memory"
4962 [(set (match_operand:HI 0 "memory_operand" "=m")
4963 (fix:HI (match_operand 1 "register_operand" "f")))
4964 (use (match_operand:HI 2 "memory_operand" "m"))
4965 (use (match_operand:HI 3 "memory_operand" "m"))]
4966 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4967 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4968 "* return output_fix_trunc (insn, operands);"
4969 [(set_attr "type" "fistp")])
4972 [(set (match_operand:HI 0 "memory_operand" "")
4973 (fix:HI (match_operand 1 "register_operand" "")))
4974 (use (match_operand:HI 2 "memory_operand" ""))
4975 (use (match_operand:HI 3 "memory_operand" ""))
4976 (clobber (match_operand:HI 4 "memory_operand" ""))]
4978 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4980 (use (match_dup 3))])]
4984 [(set (match_operand:HI 0 "register_operand" "")
4985 (fix:HI (match_operand 1 "register_operand" "")))
4986 (use (match_operand:HI 2 "memory_operand" ""))
4987 (use (match_operand:HI 3 "memory_operand" ""))
4988 (clobber (match_operand:HI 4 "memory_operand" ""))]
4990 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4993 (clobber (match_dup 4))])
4994 (set (match_dup 0) (match_dup 4))]
4998 (define_insn "x86_fnstcw_1"
4999 [(set (match_operand:HI 0 "memory_operand" "=m")
5000 (unspec:HI [(reg:HI 18)] 11))]
5003 [(set_attr "length" "2")
5004 (set_attr "mode" "HI")
5005 (set_attr "i387" "1")
5006 (set_attr "ppro_uops" "few")])
5008 (define_insn "x86_fldcw_1"
5010 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
5013 [(set_attr "length" "2")
5014 (set_attr "mode" "HI")
5015 (set_attr "i387" "1")
5016 (set_attr "athlon_decode" "vector")
5017 (set_attr "ppro_uops" "few")])
5019 ;; Conversion between fixed point and floating point.
5021 ;; Even though we only accept memory inputs, the backend _really_
5022 ;; wants to be able to do this between registers.
5024 (define_insn "floathisf2"
5025 [(set (match_operand:SF 0 "register_operand" "=f,f")
5026 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5027 "TARGET_80387 && !TARGET_SSE"
5031 [(set_attr "type" "fmov,multi")
5032 (set_attr "mode" "SF")
5033 (set_attr "fp_int_src" "true")])
5035 (define_expand "floatsisf2"
5036 [(set (match_operand:SF 0 "register_operand" "")
5037 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5038 "TARGET_SSE || TARGET_80387"
5041 (define_insn "*floatsisf2_i387"
5042 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5043 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5044 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5048 cvtsi2ss\t{%1, %0|%0, %1}"
5049 [(set_attr "type" "fmov,multi,sse")
5050 (set_attr "mode" "SF")
5051 (set_attr "fp_int_src" "true")])
5053 (define_insn "*floatsisf2_sse"
5054 [(set (match_operand:SF 0 "register_operand" "=x")
5055 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5057 "cvtsi2ss\t{%1, %0|%0, %1}"
5058 [(set_attr "type" "sse")
5059 (set_attr "mode" "SF")
5060 (set_attr "fp_int_src" "true")])
5062 (define_expand "floatdisf2"
5063 [(set (match_operand:SF 0 "register_operand" "")
5064 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
5065 "(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
5068 (define_insn "*floatdisf2_i387_only"
5069 [(set (match_operand:SF 0 "register_operand" "=f,?f")
5070 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5071 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
5075 [(set_attr "type" "fmov,multi")
5076 (set_attr "mode" "SF")
5077 (set_attr "fp_int_src" "true")])
5079 (define_insn "*floatdisf2_i387"
5080 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5081 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5082 "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5086 cvtsi2ss{q}\t{%1, %0|%0, %1}"
5087 [(set_attr "type" "fmov,multi,sse")
5088 (set_attr "mode" "SF")
5089 (set_attr "fp_int_src" "true")])
5091 (define_insn "*floatdisf2_sse"
5092 [(set (match_operand:SF 0 "register_operand" "=x")
5093 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5094 "TARGET_SSE && TARGET_64BIT"
5095 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
5096 [(set_attr "type" "sse")
5097 (set_attr "mode" "SF")
5098 (set_attr "fp_int_src" "true")])
5100 (define_insn "floathidf2"
5101 [(set (match_operand:DF 0 "register_operand" "=f,f")
5102 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5103 "TARGET_80387 && !TARGET_SSE2"
5107 [(set_attr "type" "fmov,multi")
5108 (set_attr "mode" "DF")
5109 (set_attr "fp_int_src" "true")])
5111 (define_expand "floatsidf2"
5112 [(set (match_operand:DF 0 "register_operand" "")
5113 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5117 (define_insn "*floatsidf2_i387"
5118 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5119 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5120 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5124 cvtsi2sd\t{%1, %0|%0, %1}"
5125 [(set_attr "type" "fmov,multi,sse")
5126 (set_attr "mode" "DF")
5127 (set_attr "fp_int_src" "true")])
5129 (define_insn "*floatsidf2_sse"
5130 [(set (match_operand:DF 0 "register_operand" "=Y")
5131 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5133 "cvtsi2sd\t{%1, %0|%0, %1}"
5134 [(set_attr "type" "sse")
5135 (set_attr "mode" "DF")
5136 (set_attr "fp_int_src" "true")])
5138 (define_expand "floatdidf2"
5139 [(set (match_operand:DF 0 "register_operand" "")
5140 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5141 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
5144 (define_insn "*floatdidf2_i387_only"
5145 [(set (match_operand:DF 0 "register_operand" "=f,?f")
5146 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5147 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
5151 [(set_attr "type" "fmov,multi")
5152 (set_attr "mode" "DF")
5153 (set_attr "fp_int_src" "true")])
5155 (define_insn "*floatdidf2_i387"
5156 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5157 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5158 "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5162 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5163 [(set_attr "type" "fmov,multi,sse")
5164 (set_attr "mode" "DF")
5165 (set_attr "fp_int_src" "true")])
5167 (define_insn "*floatdidf2_sse"
5168 [(set (match_operand:DF 0 "register_operand" "=Y")
5169 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5171 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5172 [(set_attr "type" "sse")
5173 (set_attr "mode" "DF")
5174 (set_attr "fp_int_src" "true")])
5176 (define_insn "floathixf2"
5177 [(set (match_operand:XF 0 "register_operand" "=f,f")
5178 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5179 "TARGET_80387 && !TARGET_64BIT"
5183 [(set_attr "type" "fmov,multi")
5184 (set_attr "mode" "XF")
5185 (set_attr "fp_int_src" "true")])
5187 (define_insn "floathitf2"
5188 [(set (match_operand:TF 0 "register_operand" "=f,f")
5189 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5194 [(set_attr "type" "fmov,multi")
5195 (set_attr "mode" "XF")
5196 (set_attr "fp_int_src" "true")])
5198 (define_insn "floatsixf2"
5199 [(set (match_operand:XF 0 "register_operand" "=f,f")
5200 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5201 "TARGET_80387 && !TARGET_64BIT"
5205 [(set_attr "type" "fmov,multi")
5206 (set_attr "mode" "XF")
5207 (set_attr "fp_int_src" "true")])
5209 (define_insn "floatsitf2"
5210 [(set (match_operand:TF 0 "register_operand" "=f,f")
5211 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5216 [(set_attr "type" "fmov,multi")
5217 (set_attr "mode" "XF")
5218 (set_attr "fp_int_src" "true")])
5220 (define_insn "floatdixf2"
5221 [(set (match_operand:XF 0 "register_operand" "=f,f")
5222 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5223 "TARGET_80387 && !TARGET_64BIT"
5227 [(set_attr "type" "fmov,multi")
5228 (set_attr "mode" "XF")
5229 (set_attr "fp_int_src" "true")])
5231 (define_insn "floatditf2"
5232 [(set (match_operand:TF 0 "register_operand" "=f,f")
5233 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5238 [(set_attr "type" "fmov,multi")
5239 (set_attr "mode" "XF")
5240 (set_attr "fp_int_src" "true")])
5242 ;; %%% Kill these when reload knows how to do it.
5244 [(set (match_operand 0 "register_operand" "")
5245 (float (match_operand 1 "register_operand" "")))]
5246 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5247 && FP_REG_P (operands[0])"
5250 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5251 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5252 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5253 ix86_free_from_memory (GET_MODE (operands[1]));
5259 ;; %%% splits for addsidi3
5260 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5261 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5262 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5264 (define_expand "adddi3"
5265 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5266 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5267 (match_operand:DI 2 "x86_64_general_operand" "")))
5268 (clobber (reg:CC 17))]
5270 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5272 (define_insn "*adddi3_1"
5273 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5274 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5275 (match_operand:DI 2 "general_operand" "roiF,riF")))
5276 (clobber (reg:CC 17))]
5281 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5282 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5283 (match_operand:DI 2 "general_operand" "")))
5284 (clobber (reg:CC 17))]
5285 "reload_completed && !TARGET_64BIT"
5286 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
5287 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5288 (parallel [(set (match_dup 3)
5289 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5292 (clobber (reg:CC 17))])]
5293 "split_di (operands+0, 1, operands+0, operands+3);
5294 split_di (operands+1, 1, operands+1, operands+4);
5295 split_di (operands+2, 1, operands+2, operands+5);")
5297 (define_insn "*adddi3_carry_rex64"
5298 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5299 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
5300 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5301 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5302 (clobber (reg:CC 17))]
5303 "ix86_binary_operator_ok (PLUS, DImode, operands)"
5304 "adc{q}\t{%2, %0|%0, %2}"
5305 [(set_attr "type" "alu")
5306 (set_attr "pent_pair" "pu")
5307 (set_attr "mode" "DI")
5308 (set_attr "ppro_uops" "few")])
5310 (define_insn "*adddi3_cc_rex64"
5311 [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5312 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
5313 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5314 (plus:DI (match_dup 1) (match_dup 2)))]
5315 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5316 "add{q}\t{%2, %0|%0, %2}"
5317 [(set_attr "type" "alu")
5318 (set_attr "mode" "DI")])
5320 (define_insn "*addsi3_carry"
5321 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5322 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5323 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5324 (match_operand:SI 2 "general_operand" "ri,rm")))
5325 (clobber (reg:CC 17))]
5326 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5327 "adc{l}\t{%2, %0|%0, %2}"
5328 [(set_attr "type" "alu")
5329 (set_attr "pent_pair" "pu")
5330 (set_attr "mode" "SI")
5331 (set_attr "ppro_uops" "few")])
5333 (define_insn "*addsi3_carry_zext"
5334 [(set (match_operand:DI 0 "register_operand" "=r")
5336 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5337 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5338 (match_operand:SI 2 "general_operand" "rim"))))
5339 (clobber (reg:CC 17))]
5340 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5341 "adc{l}\t{%2, %k0|%k0, %2}"
5342 [(set_attr "type" "alu")
5343 (set_attr "pent_pair" "pu")
5344 (set_attr "mode" "SI")
5345 (set_attr "ppro_uops" "few")])
5347 (define_insn "*addsi3_cc"
5348 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5349 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
5350 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5351 (plus:SI (match_dup 1) (match_dup 2)))]
5352 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5353 "add{l}\t{%2, %0|%0, %2}"
5354 [(set_attr "type" "alu")
5355 (set_attr "mode" "SI")])
5357 (define_insn "addqi3_cc"
5358 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5359 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
5360 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5361 (plus:QI (match_dup 1) (match_dup 2)))]
5362 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5363 "add{b}\t{%2, %0|%0, %2}"
5364 [(set_attr "type" "alu")
5365 (set_attr "mode" "QI")])
5367 (define_expand "addsi3"
5368 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5369 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5370 (match_operand:SI 2 "general_operand" "")))
5371 (clobber (reg:CC 17))])]
5373 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5375 (define_insn "*lea_1"
5376 [(set (match_operand:SI 0 "register_operand" "=r")
5377 (match_operand:SI 1 "address_operand" "p"))]
5379 "lea{l}\t{%a1, %0|%0, %a1}"
5380 [(set_attr "type" "lea")
5381 (set_attr "mode" "SI")])
5383 (define_insn "*lea_1_rex64"
5384 [(set (match_operand:SI 0 "register_operand" "=r")
5385 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5387 "lea{l}\t{%a1, %0|%0, %a1}"
5388 [(set_attr "type" "lea")
5389 (set_attr "mode" "SI")])
5391 (define_insn "*lea_1_zext"
5392 [(set (match_operand:DI 0 "register_operand" "=r")
5393 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5395 "lea{l}\t{%a1, %k0|%k0, %a1}"
5396 [(set_attr "type" "lea")
5397 (set_attr "mode" "SI")])
5399 (define_insn "*lea_2_rex64"
5400 [(set (match_operand:DI 0 "register_operand" "=r")
5401 (match_operand:DI 1 "address_operand" "p"))]
5403 "lea{q}\t{%a1, %0|%0, %a1}"
5404 [(set_attr "type" "lea")
5405 (set_attr "mode" "DI")])
5407 ;; The lea patterns for non-Pmodes needs to be matched by several
5408 ;; insns converted to real lea by splitters.
5410 (define_insn_and_split "*lea_general_1"
5411 [(set (match_operand 0 "register_operand" "=r")
5412 (plus (plus (match_operand 1 "register_operand" "r")
5413 (match_operand 2 "register_operand" "r"))
5414 (match_operand 3 "immediate_operand" "i")))]
5415 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5416 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5417 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5418 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5419 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5420 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5421 || GET_MODE (operands[3]) == VOIDmode)"
5423 "&& reload_completed"
5427 operands[0] = gen_lowpart (SImode, operands[0]);
5428 operands[1] = gen_lowpart (Pmode, operands[1]);
5429 operands[2] = gen_lowpart (Pmode, operands[2]);
5430 operands[3] = gen_lowpart (Pmode, operands[3]);
5431 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5433 if (Pmode != SImode)
5434 pat = gen_rtx_SUBREG (SImode, pat, 0);
5435 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5438 [(set_attr "type" "lea")
5439 (set_attr "mode" "SI")])
5441 (define_insn_and_split "*lea_general_1_zext"
5442 [(set (match_operand:DI 0 "register_operand" "=r")
5444 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
5445 (match_operand:SI 2 "register_operand" "r"))
5446 (match_operand:SI 3 "immediate_operand" "i"))))]
5449 "&& reload_completed"
5451 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5453 (match_dup 3)) 0)))]
5455 operands[1] = gen_lowpart (Pmode, operands[1]);
5456 operands[2] = gen_lowpart (Pmode, operands[2]);
5457 operands[3] = gen_lowpart (Pmode, operands[3]);
5459 [(set_attr "type" "lea")
5460 (set_attr "mode" "SI")])
5462 (define_insn_and_split "*lea_general_2"
5463 [(set (match_operand 0 "register_operand" "=r")
5464 (plus (mult (match_operand 1 "register_operand" "r")
5465 (match_operand 2 "const248_operand" "i"))
5466 (match_operand 3 "nonmemory_operand" "ri")))]
5467 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5468 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5469 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5470 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5471 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5472 || GET_MODE (operands[3]) == VOIDmode)"
5474 "&& reload_completed"
5478 operands[0] = gen_lowpart (SImode, operands[0]);
5479 operands[1] = gen_lowpart (Pmode, operands[1]);
5480 operands[3] = gen_lowpart (Pmode, operands[3]);
5481 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5483 if (Pmode != SImode)
5484 pat = gen_rtx_SUBREG (SImode, pat, 0);
5485 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5488 [(set_attr "type" "lea")
5489 (set_attr "mode" "SI")])
5491 (define_insn_and_split "*lea_general_2_zext"
5492 [(set (match_operand:DI 0 "register_operand" "=r")
5494 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5495 (match_operand:SI 2 "const248_operand" "n"))
5496 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5499 "&& reload_completed"
5501 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5503 (match_dup 3)) 0)))]
5505 operands[1] = gen_lowpart (Pmode, operands[1]);
5506 operands[3] = gen_lowpart (Pmode, operands[3]);
5508 [(set_attr "type" "lea")
5509 (set_attr "mode" "SI")])
5511 (define_insn_and_split "*lea_general_3"
5512 [(set (match_operand 0 "register_operand" "=r")
5513 (plus (plus (mult (match_operand 1 "register_operand" "r")
5514 (match_operand 2 "const248_operand" "i"))
5515 (match_operand 3 "register_operand" "r"))
5516 (match_operand 4 "immediate_operand" "i")))]
5517 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5518 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5519 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5520 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5521 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5523 "&& reload_completed"
5527 operands[0] = gen_lowpart (SImode, operands[0]);
5528 operands[1] = gen_lowpart (Pmode, operands[1]);
5529 operands[3] = gen_lowpart (Pmode, operands[3]);
5530 operands[4] = gen_lowpart (Pmode, operands[4]);
5531 pat = gen_rtx_PLUS (Pmode,
5532 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5536 if (Pmode != SImode)
5537 pat = gen_rtx_SUBREG (SImode, pat, 0);
5538 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5541 [(set_attr "type" "lea")
5542 (set_attr "mode" "SI")])
5544 (define_insn_and_split "*lea_general_3_zext"
5545 [(set (match_operand:DI 0 "register_operand" "=r")
5547 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5548 (match_operand:SI 2 "const248_operand" "n"))
5549 (match_operand:SI 3 "register_operand" "r"))
5550 (match_operand:SI 4 "immediate_operand" "i"))))]
5553 "&& reload_completed"
5555 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5558 (match_dup 4)) 0)))]
5560 operands[1] = gen_lowpart (Pmode, operands[1]);
5561 operands[3] = gen_lowpart (Pmode, operands[3]);
5562 operands[4] = gen_lowpart (Pmode, operands[4]);
5564 [(set_attr "type" "lea")
5565 (set_attr "mode" "SI")])
5567 (define_insn "*adddi_1_rex64"
5568 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5569 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5570 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5571 (clobber (reg:CC 17))]
5572 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5574 switch (get_attr_type (insn))
5577 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5578 return "lea{q}\t{%a2, %0|%0, %a2}";
5581 if (! rtx_equal_p (operands[0], operands[1]))
5583 if (operands[2] == const1_rtx)
5584 return "inc{q}\t%0";
5585 else if (operands[2] == constm1_rtx)
5586 return "dec{q}\t%0";
5591 if (! rtx_equal_p (operands[0], operands[1]))
5594 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5595 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5596 if (GET_CODE (operands[2]) == CONST_INT
5597 /* Avoid overflows. */
5598 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5599 && (INTVAL (operands[2]) == 128
5600 || (INTVAL (operands[2]) < 0
5601 && INTVAL (operands[2]) != -128)))
5603 operands[2] = GEN_INT (-INTVAL (operands[2]));
5604 return "sub{q}\t{%2, %0|%0, %2}";
5606 return "add{q}\t{%2, %0|%0, %2}";
5610 (cond [(eq_attr "alternative" "2")
5611 (const_string "lea")
5612 ; Current assemblers are broken and do not allow @GOTOFF in
5613 ; ought but a memory context.
5614 (match_operand:DI 2 "pic_symbolic_operand" "")
5615 (const_string "lea")
5616 (match_operand:DI 2 "incdec_operand" "")
5617 (const_string "incdec")
5619 (const_string "alu")))
5620 (set_attr "mode" "DI")])
5622 ;; Convert lea to the lea pattern to avoid flags dependency.
5624 [(set (match_operand:DI 0 "register_operand" "")
5625 (plus:DI (match_operand:DI 1 "register_operand" "")
5626 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5627 (clobber (reg:CC 17))]
5628 "reload_completed && TARGET_64BIT
5629 && true_regnum (operands[0]) != true_regnum (operands[1])"
5631 (plus:DI (match_dup 1)
5635 (define_insn "*adddi_2_rex64"
5638 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5639 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5641 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5642 (plus:DI (match_dup 1) (match_dup 2)))]
5643 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5644 && ix86_binary_operator_ok (PLUS, DImode, operands)
5645 /* Current assemblers are broken and do not allow @GOTOFF in
5646 ought but a memory context. */
5647 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5649 switch (get_attr_type (insn))
5652 if (! rtx_equal_p (operands[0], operands[1]))
5654 if (operands[2] == const1_rtx)
5655 return "inc{q}\t%0";
5656 else if (operands[2] == constm1_rtx)
5657 return "dec{q}\t%0";
5662 if (! rtx_equal_p (operands[0], operands[1]))
5664 /* ???? We ought to handle there the 32bit case too
5665 - do we need new constrant? */
5666 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5667 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5668 if (GET_CODE (operands[2]) == CONST_INT
5669 /* Avoid overflows. */
5670 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5671 && (INTVAL (operands[2]) == 128
5672 || (INTVAL (operands[2]) < 0
5673 && INTVAL (operands[2]) != -128)))
5675 operands[2] = GEN_INT (-INTVAL (operands[2]));
5676 return "sub{q}\t{%2, %0|%0, %2}";
5678 return "add{q}\t{%2, %0|%0, %2}";
5682 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5683 (const_string "incdec")
5684 (const_string "alu")))
5685 (set_attr "mode" "DI")])
5687 (define_insn "*adddi_3_rex64"
5689 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5690 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5691 (clobber (match_scratch:DI 0 "=r"))]
5693 && ix86_match_ccmode (insn, CCZmode)
5694 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5695 /* Current assemblers are broken and do not allow @GOTOFF in
5696 ought but a memory context. */
5697 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5699 switch (get_attr_type (insn))
5702 if (! rtx_equal_p (operands[0], operands[1]))
5704 if (operands[2] == const1_rtx)
5705 return "inc{q}\t%0";
5706 else if (operands[2] == constm1_rtx)
5707 return "dec{q}\t%0";
5712 if (! rtx_equal_p (operands[0], operands[1]))
5714 /* ???? We ought to handle there the 32bit case too
5715 - do we need new constrant? */
5716 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5717 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5718 if (GET_CODE (operands[2]) == CONST_INT
5719 /* Avoid overflows. */
5720 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5721 && (INTVAL (operands[2]) == 128
5722 || (INTVAL (operands[2]) < 0
5723 && INTVAL (operands[2]) != -128)))
5725 operands[2] = GEN_INT (-INTVAL (operands[2]));
5726 return "sub{q}\t{%2, %0|%0, %2}";
5728 return "add{q}\t{%2, %0|%0, %2}";
5732 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5733 (const_string "incdec")
5734 (const_string "alu")))
5735 (set_attr "mode" "DI")])
5737 ; For comparisons against 1, -1 and 128, we may generate better code
5738 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5739 ; is matched then. We can't accept general immediate, because for
5740 ; case of overflows, the result is messed up.
5741 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5743 ; Also carry flag is reversed compared to cmp, so this converison is valid
5744 ; only for comparisons not depending on it.
5745 (define_insn "*adddi_4_rex64"
5747 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5748 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5749 (clobber (match_scratch:DI 0 "=rm"))]
5751 && ix86_match_ccmode (insn, CCGCmode)"
5753 switch (get_attr_type (insn))
5756 if (operands[2] == constm1_rtx)
5757 return "inc{q}\t%0";
5758 else if (operands[2] == const1_rtx)
5759 return "dec{q}\t%0";
5764 if (! rtx_equal_p (operands[0], operands[1]))
5766 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5767 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5768 if ((INTVAL (operands[2]) == -128
5769 || (INTVAL (operands[2]) > 0
5770 && INTVAL (operands[2]) != 128))
5771 /* Avoid overflows. */
5772 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5773 return "sub{q}\t{%2, %0|%0, %2}";
5774 operands[2] = GEN_INT (-INTVAL (operands[2]));
5775 return "add{q}\t{%2, %0|%0, %2}";
5779 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5780 (const_string "incdec")
5781 (const_string "alu")))
5782 (set_attr "mode" "DI")])
5784 (define_insn "*adddi_5_rex64"
5787 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5788 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5790 (clobber (match_scratch:DI 0 "=r"))]
5792 && ix86_match_ccmode (insn, CCGOCmode)
5793 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5794 /* Current assemblers are broken and do not allow @GOTOFF in
5795 ought but a memory context. */
5796 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5798 switch (get_attr_type (insn))
5801 if (! rtx_equal_p (operands[0], operands[1]))
5803 if (operands[2] == const1_rtx)
5804 return "inc{q}\t%0";
5805 else if (operands[2] == constm1_rtx)
5806 return "dec{q}\t%0";
5811 if (! rtx_equal_p (operands[0], operands[1]))
5813 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5814 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5815 if (GET_CODE (operands[2]) == CONST_INT
5816 /* Avoid overflows. */
5817 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5818 && (INTVAL (operands[2]) == 128
5819 || (INTVAL (operands[2]) < 0
5820 && INTVAL (operands[2]) != -128)))
5822 operands[2] = GEN_INT (-INTVAL (operands[2]));
5823 return "sub{q}\t{%2, %0|%0, %2}";
5825 return "add{q}\t{%2, %0|%0, %2}";
5829 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5830 (const_string "incdec")
5831 (const_string "alu")))
5832 (set_attr "mode" "DI")])
5835 (define_insn "*addsi_1"
5836 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5837 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5838 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5839 (clobber (reg:CC 17))]
5840 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5842 switch (get_attr_type (insn))
5845 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5846 return "lea{l}\t{%a2, %0|%0, %a2}";
5849 if (! rtx_equal_p (operands[0], operands[1]))
5851 if (operands[2] == const1_rtx)
5852 return "inc{l}\t%0";
5853 else if (operands[2] == constm1_rtx)
5854 return "dec{l}\t%0";
5859 if (! rtx_equal_p (operands[0], operands[1]))
5862 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5863 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5864 if (GET_CODE (operands[2]) == CONST_INT
5865 && (INTVAL (operands[2]) == 128
5866 || (INTVAL (operands[2]) < 0
5867 && INTVAL (operands[2]) != -128)))
5869 operands[2] = GEN_INT (-INTVAL (operands[2]));
5870 return "sub{l}\t{%2, %0|%0, %2}";
5872 return "add{l}\t{%2, %0|%0, %2}";
5876 (cond [(eq_attr "alternative" "2")
5877 (const_string "lea")
5878 ; Current assemblers are broken and do not allow @GOTOFF in
5879 ; ought but a memory context.
5880 (match_operand:SI 2 "pic_symbolic_operand" "")
5881 (const_string "lea")
5882 (match_operand:SI 2 "incdec_operand" "")
5883 (const_string "incdec")
5885 (const_string "alu")))
5886 (set_attr "mode" "SI")])
5888 ;; Convert lea to the lea pattern to avoid flags dependency.
5890 [(set (match_operand 0 "register_operand" "")
5891 (plus (match_operand 1 "register_operand" "")
5892 (match_operand 2 "nonmemory_operand" "")))
5893 (clobber (reg:CC 17))]
5895 && true_regnum (operands[0]) != true_regnum (operands[1])"
5899 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5900 may confuse gen_lowpart. */
5901 if (GET_MODE (operands[0]) != Pmode)
5903 operands[1] = gen_lowpart (Pmode, operands[1]);
5904 operands[2] = gen_lowpart (Pmode, operands[2]);
5906 operands[0] = gen_lowpart (SImode, operands[0]);
5907 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5908 if (Pmode != SImode)
5909 pat = gen_rtx_SUBREG (SImode, pat, 0);
5910 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5914 ;; It may seem that nonimmediate operand is proper one for operand 1.
5915 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5916 ;; we take care in ix86_binary_operator_ok to not allow two memory
5917 ;; operands so proper swapping will be done in reload. This allow
5918 ;; patterns constructed from addsi_1 to match.
5919 (define_insn "addsi_1_zext"
5920 [(set (match_operand:DI 0 "register_operand" "=r,r")
5922 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5923 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5924 (clobber (reg:CC 17))]
5925 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5927 switch (get_attr_type (insn))
5930 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5931 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5934 if (operands[2] == const1_rtx)
5935 return "inc{l}\t%k0";
5936 else if (operands[2] == constm1_rtx)
5937 return "dec{l}\t%k0";
5942 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5943 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5944 if (GET_CODE (operands[2]) == CONST_INT
5945 && (INTVAL (operands[2]) == 128
5946 || (INTVAL (operands[2]) < 0
5947 && INTVAL (operands[2]) != -128)))
5949 operands[2] = GEN_INT (-INTVAL (operands[2]));
5950 return "sub{l}\t{%2, %k0|%k0, %2}";
5952 return "add{l}\t{%2, %k0|%k0, %2}";
5956 (cond [(eq_attr "alternative" "1")
5957 (const_string "lea")
5958 ; Current assemblers are broken and do not allow @GOTOFF in
5959 ; ought but a memory context.
5960 (match_operand:SI 2 "pic_symbolic_operand" "")
5961 (const_string "lea")
5962 (match_operand:SI 2 "incdec_operand" "")
5963 (const_string "incdec")
5965 (const_string "alu")))
5966 (set_attr "mode" "SI")])
5968 ;; Convert lea to the lea pattern to avoid flags dependency.
5970 [(set (match_operand:DI 0 "register_operand" "")
5972 (plus:SI (match_operand:SI 1 "register_operand" "")
5973 (match_operand:SI 2 "nonmemory_operand" ""))))
5974 (clobber (reg:CC 17))]
5976 && true_regnum (operands[0]) != true_regnum (operands[1])"
5978 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5980 operands[1] = gen_lowpart (Pmode, operands[1]);
5981 operands[2] = gen_lowpart (Pmode, operands[2]);
5984 (define_insn "*addsi_2"
5987 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5988 (match_operand:SI 2 "general_operand" "rmni,rni"))
5990 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5991 (plus:SI (match_dup 1) (match_dup 2)))]
5992 "ix86_match_ccmode (insn, CCGOCmode)
5993 && ix86_binary_operator_ok (PLUS, SImode, operands)
5994 /* Current assemblers are broken and do not allow @GOTOFF in
5995 ought but a memory context. */
5996 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5998 switch (get_attr_type (insn))
6001 if (! rtx_equal_p (operands[0], operands[1]))
6003 if (operands[2] == const1_rtx)
6004 return "inc{l}\t%0";
6005 else if (operands[2] == constm1_rtx)
6006 return "dec{l}\t%0";
6011 if (! rtx_equal_p (operands[0], operands[1]))
6013 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6014 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6015 if (GET_CODE (operands[2]) == CONST_INT
6016 && (INTVAL (operands[2]) == 128
6017 || (INTVAL (operands[2]) < 0
6018 && INTVAL (operands[2]) != -128)))
6020 operands[2] = GEN_INT (-INTVAL (operands[2]));
6021 return "sub{l}\t{%2, %0|%0, %2}";
6023 return "add{l}\t{%2, %0|%0, %2}";
6027 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6028 (const_string "incdec")
6029 (const_string "alu")))
6030 (set_attr "mode" "SI")])
6032 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6033 (define_insn "*addsi_2_zext"
6036 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6037 (match_operand:SI 2 "general_operand" "rmni"))
6039 (set (match_operand:DI 0 "register_operand" "=r")
6040 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6041 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6042 && ix86_binary_operator_ok (PLUS, SImode, operands)
6043 /* Current assemblers are broken and do not allow @GOTOFF in
6044 ought but a memory context. */
6045 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6047 switch (get_attr_type (insn))
6050 if (operands[2] == const1_rtx)
6051 return "inc{l}\t%k0";
6052 else if (operands[2] == constm1_rtx)
6053 return "dec{l}\t%k0";
6058 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6059 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6060 if (GET_CODE (operands[2]) == CONST_INT
6061 && (INTVAL (operands[2]) == 128
6062 || (INTVAL (operands[2]) < 0
6063 && INTVAL (operands[2]) != -128)))
6065 operands[2] = GEN_INT (-INTVAL (operands[2]));
6066 return "sub{l}\t{%2, %k0|%k0, %2}";
6068 return "add{l}\t{%2, %k0|%k0, %2}";
6072 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6073 (const_string "incdec")
6074 (const_string "alu")))
6075 (set_attr "mode" "SI")])
6077 (define_insn "*addsi_3"
6079 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6080 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6081 (clobber (match_scratch:SI 0 "=r"))]
6082 "ix86_match_ccmode (insn, CCZmode)
6083 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6084 /* Current assemblers are broken and do not allow @GOTOFF in
6085 ought but a memory context. */
6086 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6088 switch (get_attr_type (insn))
6091 if (! rtx_equal_p (operands[0], operands[1]))
6093 if (operands[2] == const1_rtx)
6094 return "inc{l}\t%0";
6095 else if (operands[2] == constm1_rtx)
6096 return "dec{l}\t%0";
6101 if (! rtx_equal_p (operands[0], operands[1]))
6103 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6104 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6105 if (GET_CODE (operands[2]) == CONST_INT
6106 && (INTVAL (operands[2]) == 128
6107 || (INTVAL (operands[2]) < 0
6108 && INTVAL (operands[2]) != -128)))
6110 operands[2] = GEN_INT (-INTVAL (operands[2]));
6111 return "sub{l}\t{%2, %0|%0, %2}";
6113 return "add{l}\t{%2, %0|%0, %2}";
6117 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6118 (const_string "incdec")
6119 (const_string "alu")))
6120 (set_attr "mode" "SI")])
6122 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6123 (define_insn "*addsi_3_zext"
6125 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6126 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6127 (set (match_operand:DI 0 "register_operand" "=r")
6128 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6129 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6130 && ix86_binary_operator_ok (PLUS, SImode, operands)
6131 /* Current assemblers are broken and do not allow @GOTOFF in
6132 ought but a memory context. */
6133 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6135 switch (get_attr_type (insn))
6138 if (operands[2] == const1_rtx)
6139 return "inc{l}\t%k0";
6140 else if (operands[2] == constm1_rtx)
6141 return "dec{l}\t%k0";
6146 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6147 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6148 if (GET_CODE (operands[2]) == CONST_INT
6149 && (INTVAL (operands[2]) == 128
6150 || (INTVAL (operands[2]) < 0
6151 && INTVAL (operands[2]) != -128)))
6153 operands[2] = GEN_INT (-INTVAL (operands[2]));
6154 return "sub{l}\t{%2, %k0|%k0, %2}";
6156 return "add{l}\t{%2, %k0|%k0, %2}";
6160 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6161 (const_string "incdec")
6162 (const_string "alu")))
6163 (set_attr "mode" "SI")])
6165 ; For comparisons agains 1, -1 and 128, we may generate better code
6166 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6167 ; is matched then. We can't accept general immediate, because for
6168 ; case of overflows, the result is messed up.
6169 ; This pattern also don't hold of 0x80000000, since the value overflows
6171 ; Also carry flag is reversed compared to cmp, so this converison is valid
6172 ; only for comparisons not depending on it.
6173 (define_insn "*addsi_4"
6175 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6176 (match_operand:SI 2 "const_int_operand" "n")))
6177 (clobber (match_scratch:SI 0 "=rm"))]
6178 "ix86_match_ccmode (insn, CCGCmode)
6179 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6181 switch (get_attr_type (insn))
6184 if (operands[2] == constm1_rtx)
6185 return "inc{l}\t%0";
6186 else if (operands[2] == const1_rtx)
6187 return "dec{l}\t%0";
6192 if (! rtx_equal_p (operands[0], operands[1]))
6194 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6195 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6196 if ((INTVAL (operands[2]) == -128
6197 || (INTVAL (operands[2]) > 0
6198 && INTVAL (operands[2]) != 128)))
6199 return "sub{l}\t{%2, %0|%0, %2}";
6200 operands[2] = GEN_INT (-INTVAL (operands[2]));
6201 return "add{l}\t{%2, %0|%0, %2}";
6205 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6206 (const_string "incdec")
6207 (const_string "alu")))
6208 (set_attr "mode" "SI")])
6210 (define_insn "*addsi_5"
6213 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6214 (match_operand:SI 2 "general_operand" "rmni"))
6216 (clobber (match_scratch:SI 0 "=r"))]
6217 "ix86_match_ccmode (insn, CCGOCmode)
6218 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6219 /* Current assemblers are broken and do not allow @GOTOFF in
6220 ought but a memory context. */
6221 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6223 switch (get_attr_type (insn))
6226 if (! rtx_equal_p (operands[0], operands[1]))
6228 if (operands[2] == const1_rtx)
6229 return "inc{l}\t%0";
6230 else if (operands[2] == constm1_rtx)
6231 return "dec{l}\t%0";
6236 if (! rtx_equal_p (operands[0], operands[1]))
6238 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6239 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6240 if (GET_CODE (operands[2]) == CONST_INT
6241 && (INTVAL (operands[2]) == 128
6242 || (INTVAL (operands[2]) < 0
6243 && INTVAL (operands[2]) != -128)))
6245 operands[2] = GEN_INT (-INTVAL (operands[2]));
6246 return "sub{l}\t{%2, %0|%0, %2}";
6248 return "add{l}\t{%2, %0|%0, %2}";
6252 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6253 (const_string "incdec")
6254 (const_string "alu")))
6255 (set_attr "mode" "SI")])
6257 (define_expand "addhi3"
6258 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6259 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6260 (match_operand:HI 2 "general_operand" "")))
6261 (clobber (reg:CC 17))])]
6262 "TARGET_HIMODE_MATH"
6263 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6265 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6266 ;; type optimizations enabled by define-splits. This is not important
6267 ;; for PII, and in fact harmful because of partial register stalls.
6269 (define_insn "*addhi_1_lea"
6270 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6271 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6272 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6273 (clobber (reg:CC 17))]
6274 "!TARGET_PARTIAL_REG_STALL
6275 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6277 switch (get_attr_type (insn))
6282 if (operands[2] == const1_rtx)
6283 return "inc{w}\t%0";
6284 else if (operands[2] == constm1_rtx
6285 || (GET_CODE (operands[2]) == CONST_INT
6286 && INTVAL (operands[2]) == 65535))
6287 return "dec{w}\t%0";
6291 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6292 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6293 if (GET_CODE (operands[2]) == CONST_INT
6294 && (INTVAL (operands[2]) == 128
6295 || (INTVAL (operands[2]) < 0
6296 && INTVAL (operands[2]) != -128)))
6298 operands[2] = GEN_INT (-INTVAL (operands[2]));
6299 return "sub{w}\t{%2, %0|%0, %2}";
6301 return "add{w}\t{%2, %0|%0, %2}";
6305 (if_then_else (eq_attr "alternative" "2")
6306 (const_string "lea")
6307 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6308 (const_string "incdec")
6309 (const_string "alu"))))
6310 (set_attr "mode" "HI,HI,SI")])
6312 (define_insn "*addhi_1"
6313 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6314 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6315 (match_operand:HI 2 "general_operand" "ri,rm")))
6316 (clobber (reg:CC 17))]
6317 "TARGET_PARTIAL_REG_STALL
6318 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6320 switch (get_attr_type (insn))
6323 if (operands[2] == const1_rtx)
6324 return "inc{w}\t%0";
6325 else if (operands[2] == constm1_rtx
6326 || (GET_CODE (operands[2]) == CONST_INT
6327 && INTVAL (operands[2]) == 65535))
6328 return "dec{w}\t%0";
6332 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6333 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6334 if (GET_CODE (operands[2]) == CONST_INT
6335 && (INTVAL (operands[2]) == 128
6336 || (INTVAL (operands[2]) < 0
6337 && INTVAL (operands[2]) != -128)))
6339 operands[2] = GEN_INT (-INTVAL (operands[2]));
6340 return "sub{w}\t{%2, %0|%0, %2}";
6342 return "add{w}\t{%2, %0|%0, %2}";
6346 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6347 (const_string "incdec")
6348 (const_string "alu")))
6349 (set_attr "mode" "HI")])
6351 (define_insn "*addhi_2"
6354 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6355 (match_operand:HI 2 "general_operand" "rmni,rni"))
6357 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6358 (plus:HI (match_dup 1) (match_dup 2)))]
6359 "ix86_match_ccmode (insn, CCGOCmode)
6360 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6362 switch (get_attr_type (insn))
6365 if (operands[2] == const1_rtx)
6366 return "inc{w}\t%0";
6367 else if (operands[2] == constm1_rtx
6368 || (GET_CODE (operands[2]) == CONST_INT
6369 && INTVAL (operands[2]) == 65535))
6370 return "dec{w}\t%0";
6374 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6375 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6376 if (GET_CODE (operands[2]) == CONST_INT
6377 && (INTVAL (operands[2]) == 128
6378 || (INTVAL (operands[2]) < 0
6379 && INTVAL (operands[2]) != -128)))
6381 operands[2] = GEN_INT (-INTVAL (operands[2]));
6382 return "sub{w}\t{%2, %0|%0, %2}";
6384 return "add{w}\t{%2, %0|%0, %2}";
6388 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6389 (const_string "incdec")
6390 (const_string "alu")))
6391 (set_attr "mode" "HI")])
6393 (define_insn "*addhi_3"
6395 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6396 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6397 (clobber (match_scratch:HI 0 "=r"))]
6398 "ix86_match_ccmode (insn, CCZmode)
6399 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6401 switch (get_attr_type (insn))
6404 if (operands[2] == const1_rtx)
6405 return "inc{w}\t%0";
6406 else if (operands[2] == constm1_rtx
6407 || (GET_CODE (operands[2]) == CONST_INT
6408 && INTVAL (operands[2]) == 65535))
6409 return "dec{w}\t%0";
6413 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6414 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6415 if (GET_CODE (operands[2]) == CONST_INT
6416 && (INTVAL (operands[2]) == 128
6417 || (INTVAL (operands[2]) < 0
6418 && INTVAL (operands[2]) != -128)))
6420 operands[2] = GEN_INT (-INTVAL (operands[2]));
6421 return "sub{w}\t{%2, %0|%0, %2}";
6423 return "add{w}\t{%2, %0|%0, %2}";
6427 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6428 (const_string "incdec")
6429 (const_string "alu")))
6430 (set_attr "mode" "HI")])
6432 ; See comments above addsi_3_imm for details.
6433 (define_insn "*addhi_4"
6435 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6436 (match_operand:HI 2 "const_int_operand" "n")))
6437 (clobber (match_scratch:HI 0 "=rm"))]
6438 "ix86_match_ccmode (insn, CCGCmode)
6439 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6441 switch (get_attr_type (insn))
6444 if (operands[2] == constm1_rtx
6445 || (GET_CODE (operands[2]) == CONST_INT
6446 && INTVAL (operands[2]) == 65535))
6447 return "inc{w}\t%0";
6448 else if (operands[2] == const1_rtx)
6449 return "dec{w}\t%0";
6454 if (! rtx_equal_p (operands[0], operands[1]))
6456 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6457 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6458 if ((INTVAL (operands[2]) == -128
6459 || (INTVAL (operands[2]) > 0
6460 && INTVAL (operands[2]) != 128)))
6461 return "sub{w}\t{%2, %0|%0, %2}";
6462 operands[2] = GEN_INT (-INTVAL (operands[2]));
6463 return "add{w}\t{%2, %0|%0, %2}";
6467 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6468 (const_string "incdec")
6469 (const_string "alu")))
6470 (set_attr "mode" "SI")])
6473 (define_insn "*addhi_5"
6476 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6477 (match_operand:HI 2 "general_operand" "rmni"))
6479 (clobber (match_scratch:HI 0 "=r"))]
6480 "ix86_match_ccmode (insn, CCGOCmode)
6481 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6483 switch (get_attr_type (insn))
6486 if (operands[2] == const1_rtx)
6487 return "inc{w}\t%0";
6488 else if (operands[2] == constm1_rtx
6489 || (GET_CODE (operands[2]) == CONST_INT
6490 && INTVAL (operands[2]) == 65535))
6491 return "dec{w}\t%0";
6495 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6496 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6497 if (GET_CODE (operands[2]) == CONST_INT
6498 && (INTVAL (operands[2]) == 128
6499 || (INTVAL (operands[2]) < 0
6500 && INTVAL (operands[2]) != -128)))
6502 operands[2] = GEN_INT (-INTVAL (operands[2]));
6503 return "sub{w}\t{%2, %0|%0, %2}";
6505 return "add{w}\t{%2, %0|%0, %2}";
6509 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6510 (const_string "incdec")
6511 (const_string "alu")))
6512 (set_attr "mode" "HI")])
6514 (define_expand "addqi3"
6515 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6516 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6517 (match_operand:QI 2 "general_operand" "")))
6518 (clobber (reg:CC 17))])]
6519 "TARGET_QIMODE_MATH"
6520 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6522 ;; %%% Potential partial reg stall on alternative 2. What to do?
6523 (define_insn "*addqi_1_lea"
6524 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6525 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6526 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6527 (clobber (reg:CC 17))]
6528 "!TARGET_PARTIAL_REG_STALL
6529 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6531 int widen = (which_alternative == 2);
6532 switch (get_attr_type (insn))
6537 if (operands[2] == const1_rtx)
6538 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6539 else if (operands[2] == constm1_rtx
6540 || (GET_CODE (operands[2]) == CONST_INT
6541 && INTVAL (operands[2]) == 255))
6542 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6546 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6547 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6548 if (GET_CODE (operands[2]) == CONST_INT
6549 && (INTVAL (operands[2]) == 128
6550 || (INTVAL (operands[2]) < 0
6551 && INTVAL (operands[2]) != -128)))
6553 operands[2] = GEN_INT (-INTVAL (operands[2]));
6555 return "sub{l}\t{%2, %k0|%k0, %2}";
6557 return "sub{b}\t{%2, %0|%0, %2}";
6560 return "add{l}\t{%k2, %k0|%k0, %k2}";
6562 return "add{b}\t{%2, %0|%0, %2}";
6566 (if_then_else (eq_attr "alternative" "3")
6567 (const_string "lea")
6568 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6569 (const_string "incdec")
6570 (const_string "alu"))))
6571 (set_attr "mode" "QI,QI,SI,SI")])
6573 (define_insn "*addqi_1"
6574 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6575 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6576 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6577 (clobber (reg:CC 17))]
6578 "TARGET_PARTIAL_REG_STALL
6579 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6581 int widen = (which_alternative == 2);
6582 switch (get_attr_type (insn))
6585 if (operands[2] == const1_rtx)
6586 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6587 else if (operands[2] == constm1_rtx
6588 || (GET_CODE (operands[2]) == CONST_INT
6589 && INTVAL (operands[2]) == 255))
6590 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6594 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6595 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6596 if (GET_CODE (operands[2]) == CONST_INT
6597 && (INTVAL (operands[2]) == 128
6598 || (INTVAL (operands[2]) < 0
6599 && INTVAL (operands[2]) != -128)))
6601 operands[2] = GEN_INT (-INTVAL (operands[2]));
6603 return "sub{l}\t{%2, %k0|%k0, %2}";
6605 return "sub{b}\t{%2, %0|%0, %2}";
6608 return "add{l}\t{%k2, %k0|%k0, %k2}";
6610 return "add{b}\t{%2, %0|%0, %2}";
6614 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6615 (const_string "incdec")
6616 (const_string "alu")))
6617 (set_attr "mode" "QI,QI,SI")])
6619 (define_insn "*addqi_2"
6622 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6623 (match_operand:QI 2 "general_operand" "qmni,qni"))
6625 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6626 (plus:QI (match_dup 1) (match_dup 2)))]
6627 "ix86_match_ccmode (insn, CCGOCmode)
6628 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6630 switch (get_attr_type (insn))
6633 if (operands[2] == const1_rtx)
6634 return "inc{b}\t%0";
6635 else if (operands[2] == constm1_rtx
6636 || (GET_CODE (operands[2]) == CONST_INT
6637 && INTVAL (operands[2]) == 255))
6638 return "dec{b}\t%0";
6642 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6643 if (GET_CODE (operands[2]) == CONST_INT
6644 && INTVAL (operands[2]) < 0)
6646 operands[2] = GEN_INT (-INTVAL (operands[2]));
6647 return "sub{b}\t{%2, %0|%0, %2}";
6649 return "add{b}\t{%2, %0|%0, %2}";
6653 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6654 (const_string "incdec")
6655 (const_string "alu")))
6656 (set_attr "mode" "QI")])
6658 (define_insn "*addqi_3"
6660 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6661 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6662 (clobber (match_scratch:QI 0 "=q"))]
6663 "ix86_match_ccmode (insn, CCZmode)
6664 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6666 switch (get_attr_type (insn))
6669 if (operands[2] == const1_rtx)
6670 return "inc{b}\t%0";
6671 else if (operands[2] == constm1_rtx
6672 || (GET_CODE (operands[2]) == CONST_INT
6673 && INTVAL (operands[2]) == 255))
6674 return "dec{b}\t%0";
6678 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6679 if (GET_CODE (operands[2]) == CONST_INT
6680 && INTVAL (operands[2]) < 0)
6682 operands[2] = GEN_INT (-INTVAL (operands[2]));
6683 return "sub{b}\t{%2, %0|%0, %2}";
6685 return "add{b}\t{%2, %0|%0, %2}";
6689 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6690 (const_string "incdec")
6691 (const_string "alu")))
6692 (set_attr "mode" "QI")])
6694 ; See comments above addsi_3_imm for details.
6695 (define_insn "*addqi_4"
6697 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6698 (match_operand:QI 2 "const_int_operand" "n")))
6699 (clobber (match_scratch:QI 0 "=qm"))]
6700 "ix86_match_ccmode (insn, CCGCmode)
6701 && (INTVAL (operands[2]) & 0xff) != 0x80"
6703 switch (get_attr_type (insn))
6706 if (operands[2] == constm1_rtx
6707 || (GET_CODE (operands[2]) == CONST_INT
6708 && INTVAL (operands[2]) == 255))
6709 return "inc{b}\t%0";
6710 else if (operands[2] == const1_rtx)
6711 return "dec{b}\t%0";
6716 if (! rtx_equal_p (operands[0], operands[1]))
6718 if (INTVAL (operands[2]) < 0)
6720 operands[2] = GEN_INT (-INTVAL (operands[2]));
6721 return "add{b}\t{%2, %0|%0, %2}";
6723 return "sub{b}\t{%2, %0|%0, %2}";
6727 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6728 (const_string "incdec")
6729 (const_string "alu")))
6730 (set_attr "mode" "QI")])
6733 (define_insn "*addqi_5"
6736 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6737 (match_operand:QI 2 "general_operand" "qmni"))
6739 (clobber (match_scratch:QI 0 "=q"))]
6740 "ix86_match_ccmode (insn, CCGOCmode)
6741 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6743 switch (get_attr_type (insn))
6746 if (operands[2] == const1_rtx)
6747 return "inc{b}\t%0";
6748 else if (operands[2] == constm1_rtx
6749 || (GET_CODE (operands[2]) == CONST_INT
6750 && INTVAL (operands[2]) == 255))
6751 return "dec{b}\t%0";
6755 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6756 if (GET_CODE (operands[2]) == CONST_INT
6757 && INTVAL (operands[2]) < 0)
6759 operands[2] = GEN_INT (-INTVAL (operands[2]));
6760 return "sub{b}\t{%2, %0|%0, %2}";
6762 return "add{b}\t{%2, %0|%0, %2}";
6766 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6767 (const_string "incdec")
6768 (const_string "alu")))
6769 (set_attr "mode" "QI")])
6772 (define_insn "addqi_ext_1"
6773 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6778 (match_operand 1 "ext_register_operand" "0")
6781 (match_operand:QI 2 "general_operand" "Qmn")))
6782 (clobber (reg:CC 17))]
6785 switch (get_attr_type (insn))
6788 if (operands[2] == const1_rtx)
6789 return "inc{b}\t%h0";
6790 else if (operands[2] == constm1_rtx
6791 || (GET_CODE (operands[2]) == CONST_INT
6792 && INTVAL (operands[2]) == 255))
6793 return "dec{b}\t%h0";
6797 return "add{b}\t{%2, %h0|%h0, %2}";
6801 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6802 (const_string "incdec")
6803 (const_string "alu")))
6804 (set_attr "mode" "QI")])
6806 (define_insn "*addqi_ext_1_rex64"
6807 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6812 (match_operand 1 "ext_register_operand" "0")
6815 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6816 (clobber (reg:CC 17))]
6819 switch (get_attr_type (insn))
6822 if (operands[2] == const1_rtx)
6823 return "inc{b}\t%h0";
6824 else if (operands[2] == constm1_rtx
6825 || (GET_CODE (operands[2]) == CONST_INT
6826 && INTVAL (operands[2]) == 255))
6827 return "dec{b}\t%h0";
6831 return "add{b}\t{%2, %h0|%h0, %2}";
6835 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6836 (const_string "incdec")
6837 (const_string "alu")))
6838 (set_attr "mode" "QI")])
6840 (define_insn "*addqi_ext_2"
6841 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6846 (match_operand 1 "ext_register_operand" "%0")
6850 (match_operand 2 "ext_register_operand" "Q")
6853 (clobber (reg:CC 17))]
6855 "add{b}\t{%h2, %h0|%h0, %h2}"
6856 [(set_attr "type" "alu")
6857 (set_attr "mode" "QI")])
6859 ;; The patterns that match these are at the end of this file.
6861 (define_expand "addxf3"
6862 [(set (match_operand:XF 0 "register_operand" "")
6863 (plus:XF (match_operand:XF 1 "register_operand" "")
6864 (match_operand:XF 2 "register_operand" "")))]
6865 "TARGET_80387 && !TARGET_64BIT"
6868 (define_expand "addtf3"
6869 [(set (match_operand:TF 0 "register_operand" "")
6870 (plus:TF (match_operand:TF 1 "register_operand" "")
6871 (match_operand:TF 2 "register_operand" "")))]
6875 (define_expand "adddf3"
6876 [(set (match_operand:DF 0 "register_operand" "")
6877 (plus:DF (match_operand:DF 1 "register_operand" "")
6878 (match_operand:DF 2 "nonimmediate_operand" "")))]
6879 "TARGET_80387 || TARGET_SSE2"
6882 (define_expand "addsf3"
6883 [(set (match_operand:SF 0 "register_operand" "")
6884 (plus:SF (match_operand:SF 1 "register_operand" "")
6885 (match_operand:SF 2 "nonimmediate_operand" "")))]
6886 "TARGET_80387 || TARGET_SSE"
6889 ;; Subtract instructions
6891 ;; %%% splits for subsidi3
6893 (define_expand "subdi3"
6894 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6895 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6896 (match_operand:DI 2 "x86_64_general_operand" "")))
6897 (clobber (reg:CC 17))])]
6899 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6901 (define_insn "*subdi3_1"
6902 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6903 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6904 (match_operand:DI 2 "general_operand" "roiF,riF")))
6905 (clobber (reg:CC 17))]
6910 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6911 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6912 (match_operand:DI 2 "general_operand" "")))
6913 (clobber (reg:CC 17))]
6914 "reload_completed && !TARGET_64BIT"
6915 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6916 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6917 (parallel [(set (match_dup 3)
6918 (minus:SI (match_dup 4)
6919 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6921 (clobber (reg:CC 17))])]
6922 "split_di (operands+0, 1, operands+0, operands+3);
6923 split_di (operands+1, 1, operands+1, operands+4);
6924 split_di (operands+2, 1, operands+2, operands+5);")
6926 (define_insn "subdi3_carry_rex64"
6927 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6928 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6929 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6930 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6931 (clobber (reg:CC 17))]
6932 "ix86_binary_operator_ok (MINUS, DImode, operands)"
6933 "sbb{q}\t{%2, %0|%0, %2}"
6934 [(set_attr "type" "alu")
6935 (set_attr "pent_pair" "pu")
6936 (set_attr "ppro_uops" "few")
6937 (set_attr "mode" "DI")])
6939 (define_insn "*subdi_1_rex64"
6940 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6941 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6942 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6943 (clobber (reg:CC 17))]
6944 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6945 "sub{q}\t{%2, %0|%0, %2}"
6946 [(set_attr "type" "alu")
6947 (set_attr "mode" "DI")])
6949 (define_insn "*subdi_2_rex64"
6952 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6953 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6955 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6956 (minus:DI (match_dup 1) (match_dup 2)))]
6957 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6958 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6959 "sub{q}\t{%2, %0|%0, %2}"
6960 [(set_attr "type" "alu")
6961 (set_attr "mode" "DI")])
6963 (define_insn "*subdi_3_rex63"
6965 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6966 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6967 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6968 (minus:DI (match_dup 1) (match_dup 2)))]
6969 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6970 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6971 "sub{q}\t{%2, %0|%0, %2}"
6972 [(set_attr "type" "alu")
6973 (set_attr "mode" "DI")])
6976 (define_insn "subsi3_carry"
6977 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6978 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6979 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6980 (match_operand:SI 2 "general_operand" "ri,rm"))))
6981 (clobber (reg:CC 17))]
6982 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6983 "sbb{l}\t{%2, %0|%0, %2}"
6984 [(set_attr "type" "alu")
6985 (set_attr "pent_pair" "pu")
6986 (set_attr "ppro_uops" "few")
6987 (set_attr "mode" "SI")])
6989 (define_insn "subsi3_carry_zext"
6990 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6992 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6993 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6994 (match_operand:SI 2 "general_operand" "ri,rm")))))
6995 (clobber (reg:CC 17))]
6996 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6997 "sbb{l}\t{%2, %k0|%k0, %2}"
6998 [(set_attr "type" "alu")
6999 (set_attr "pent_pair" "pu")
7000 (set_attr "ppro_uops" "few")
7001 (set_attr "mode" "SI")])
7003 (define_expand "subsi3"
7004 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7005 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
7006 (match_operand:SI 2 "general_operand" "")))
7007 (clobber (reg:CC 17))])]
7009 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
7011 (define_insn "*subsi_1"
7012 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7013 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7014 (match_operand:SI 2 "general_operand" "ri,rm")))
7015 (clobber (reg:CC 17))]
7016 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7017 "sub{l}\t{%2, %0|%0, %2}"
7018 [(set_attr "type" "alu")
7019 (set_attr "mode" "SI")])
7021 (define_insn "*subsi_1_zext"
7022 [(set (match_operand:DI 0 "register_operand" "=r")
7024 (minus:SI (match_operand:SI 1 "register_operand" "0")
7025 (match_operand:SI 2 "general_operand" "rim"))))
7026 (clobber (reg:CC 17))]
7027 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7028 "sub{l}\t{%2, %k0|%k0, %2}"
7029 [(set_attr "type" "alu")
7030 (set_attr "mode" "SI")])
7032 (define_insn "*subsi_2"
7035 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7036 (match_operand:SI 2 "general_operand" "ri,rm"))
7038 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7039 (minus:SI (match_dup 1) (match_dup 2)))]
7040 "ix86_match_ccmode (insn, CCGOCmode)
7041 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7042 "sub{l}\t{%2, %0|%0, %2}"
7043 [(set_attr "type" "alu")
7044 (set_attr "mode" "SI")])
7046 (define_insn "*subsi_2_zext"
7049 (minus:SI (match_operand:SI 1 "register_operand" "0")
7050 (match_operand:SI 2 "general_operand" "rim"))
7052 (set (match_operand:DI 0 "register_operand" "=r")
7054 (minus:SI (match_dup 1)
7056 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7057 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7058 "sub{l}\t{%2, %k0|%k0, %2}"
7059 [(set_attr "type" "alu")
7060 (set_attr "mode" "SI")])
7062 (define_insn "*subsi_3"
7064 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7065 (match_operand:SI 2 "general_operand" "ri,rm")))
7066 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7067 (minus:SI (match_dup 1) (match_dup 2)))]
7068 "ix86_match_ccmode (insn, CCmode)
7069 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7070 "sub{l}\t{%2, %0|%0, %2}"
7071 [(set_attr "type" "alu")
7072 (set_attr "mode" "SI")])
7074 (define_insn "*subsi_3_zext"
7076 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7077 (match_operand:SI 2 "general_operand" "rim")))
7078 (set (match_operand:DI 0 "register_operand" "=r")
7080 (minus:SI (match_dup 1)
7082 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7083 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7084 "sub{q}\t{%2, %0|%0, %2}"
7085 [(set_attr "type" "alu")
7086 (set_attr "mode" "DI")])
7088 (define_expand "subhi3"
7089 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7090 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7091 (match_operand:HI 2 "general_operand" "")))
7092 (clobber (reg:CC 17))])]
7093 "TARGET_HIMODE_MATH"
7094 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7096 (define_insn "*subhi_1"
7097 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7098 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7099 (match_operand:HI 2 "general_operand" "ri,rm")))
7100 (clobber (reg:CC 17))]
7101 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7102 "sub{w}\t{%2, %0|%0, %2}"
7103 [(set_attr "type" "alu")
7104 (set_attr "mode" "HI")])
7106 (define_insn "*subhi_2"
7109 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7110 (match_operand:HI 2 "general_operand" "ri,rm"))
7112 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7113 (minus:HI (match_dup 1) (match_dup 2)))]
7114 "ix86_match_ccmode (insn, CCGOCmode)
7115 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7116 "sub{w}\t{%2, %0|%0, %2}"
7117 [(set_attr "type" "alu")
7118 (set_attr "mode" "HI")])
7120 (define_insn "*subhi_3"
7122 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7123 (match_operand:HI 2 "general_operand" "ri,rm")))
7124 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7125 (minus:HI (match_dup 1) (match_dup 2)))]
7126 "ix86_match_ccmode (insn, CCmode)
7127 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7128 "sub{w}\t{%2, %0|%0, %2}"
7129 [(set_attr "type" "alu")
7130 (set_attr "mode" "HI")])
7132 (define_expand "subqi3"
7133 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7134 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7135 (match_operand:QI 2 "general_operand" "")))
7136 (clobber (reg:CC 17))])]
7137 "TARGET_QIMODE_MATH"
7138 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7140 (define_insn "*subqi_1"
7141 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7142 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7143 (match_operand:QI 2 "general_operand" "qn,qmn")))
7144 (clobber (reg:CC 17))]
7145 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7146 "sub{b}\t{%2, %0|%0, %2}"
7147 [(set_attr "type" "alu")
7148 (set_attr "mode" "QI")])
7150 (define_insn "*subqi_2"
7153 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7154 (match_operand:QI 2 "general_operand" "qi,qm"))
7156 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7157 (minus:HI (match_dup 1) (match_dup 2)))]
7158 "ix86_match_ccmode (insn, CCGOCmode)
7159 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7160 "sub{b}\t{%2, %0|%0, %2}"
7161 [(set_attr "type" "alu")
7162 (set_attr "mode" "QI")])
7164 (define_insn "*subqi_3"
7166 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7167 (match_operand:QI 2 "general_operand" "qi,qm")))
7168 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7169 (minus:HI (match_dup 1) (match_dup 2)))]
7170 "ix86_match_ccmode (insn, CCmode)
7171 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7172 "sub{b}\t{%2, %0|%0, %2}"
7173 [(set_attr "type" "alu")
7174 (set_attr "mode" "QI")])
7176 ;; The patterns that match these are at the end of this file.
7178 (define_expand "subxf3"
7179 [(set (match_operand:XF 0 "register_operand" "")
7180 (minus:XF (match_operand:XF 1 "register_operand" "")
7181 (match_operand:XF 2 "register_operand" "")))]
7182 "TARGET_80387 && !TARGET_64BIT"
7185 (define_expand "subtf3"
7186 [(set (match_operand:TF 0 "register_operand" "")
7187 (minus:TF (match_operand:TF 1 "register_operand" "")
7188 (match_operand:TF 2 "register_operand" "")))]
7192 (define_expand "subdf3"
7193 [(set (match_operand:DF 0 "register_operand" "")
7194 (minus:DF (match_operand:DF 1 "register_operand" "")
7195 (match_operand:DF 2 "nonimmediate_operand" "")))]
7196 "TARGET_80387 || TARGET_SSE2"
7199 (define_expand "subsf3"
7200 [(set (match_operand:SF 0 "register_operand" "")
7201 (minus:SF (match_operand:SF 1 "register_operand" "")
7202 (match_operand:SF 2 "nonimmediate_operand" "")))]
7203 "TARGET_80387 || TARGET_SSE"
7206 ;; Multiply instructions
7208 (define_expand "muldi3"
7209 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7210 (mult:DI (match_operand:DI 1 "register_operand" "")
7211 (match_operand:DI 2 "x86_64_general_operand" "")))
7212 (clobber (reg:CC 17))])]
7216 (define_insn "*muldi3_1_rex64"
7217 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7218 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
7219 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7220 (clobber (reg:CC 17))]
7221 "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
7224 imul{q}\t{%2, %1, %0|%0, %1, %2}
7225 imul{q}\t{%2, %1, %0|%0, %1, %2}
7226 imul{q}\t{%2, %0|%0, %2}"
7227 [(set_attr "type" "imul")
7228 (set_attr "prefix_0f" "0,0,1")
7229 (set_attr "mode" "DI")])
7231 (define_expand "mulsi3"
7232 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7233 (mult:SI (match_operand:SI 1 "register_operand" "")
7234 (match_operand:SI 2 "general_operand" "")))
7235 (clobber (reg:CC 17))])]
7239 (define_insn "*mulsi3_1"
7240 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7241 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7242 (match_operand:SI 2 "general_operand" "K,i,mr")))
7243 (clobber (reg:CC 17))]
7244 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7245 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7246 ; there are two ways of writing the exact same machine instruction
7247 ; in assembly language. One, for example, is:
7251 ; while the other is:
7253 ; imul $12, %eax, %eax
7255 ; The first is simply short-hand for the latter. But, some assemblers,
7256 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7258 imul{l}\t{%2, %1, %0|%0, %1, %2}
7259 imul{l}\t{%2, %1, %0|%0, %1, %2}
7260 imul{l}\t{%2, %0|%0, %2}"
7261 [(set_attr "type" "imul")
7262 (set_attr "prefix_0f" "0,0,1")
7263 (set_attr "mode" "SI")])
7265 (define_insn "*mulsi3_1_zext"
7266 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7268 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7269 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7270 (clobber (reg:CC 17))]
7272 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7273 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7274 ; there are two ways of writing the exact same machine instruction
7275 ; in assembly language. One, for example, is:
7279 ; while the other is:
7281 ; imul $12, %eax, %eax
7283 ; The first is simply short-hand for the latter. But, some assemblers,
7284 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7286 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7287 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7288 imul{l}\t{%2, %k0|%k0, %2}"
7289 [(set_attr "type" "imul")
7290 (set_attr "prefix_0f" "0,0,1")
7291 (set_attr "mode" "SI")])
7293 (define_expand "mulhi3"
7294 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7295 (mult:HI (match_operand:HI 1 "register_operand" "")
7296 (match_operand:HI 2 "general_operand" "")))
7297 (clobber (reg:CC 17))])]
7298 "TARGET_HIMODE_MATH"
7301 (define_insn "*mulhi3_1"
7302 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7303 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
7304 (match_operand:HI 2 "general_operand" "K,i,mr")))
7305 (clobber (reg:CC 17))]
7306 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7307 ; %%% There was a note about "Assembler has weird restrictions",
7308 ; concerning alternative 1 when op1 == op0. True?
7310 imul{w}\t{%2, %1, %0|%0, %1, %2}
7311 imul{w}\t{%2, %1, %0|%0, %1, %2}
7312 imul{w}\t{%2, %0|%0, %2}"
7313 [(set_attr "type" "imul")
7314 (set_attr "prefix_0f" "0,0,1")
7315 (set_attr "mode" "HI")])
7317 (define_insn "mulqi3"
7318 [(set (match_operand:QI 0 "register_operand" "=a")
7319 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7320 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7321 (clobber (reg:CC 17))]
7322 "TARGET_QIMODE_MATH"
7324 [(set_attr "type" "imul")
7325 (set_attr "length_immediate" "0")
7326 (set_attr "mode" "QI")])
7328 (define_insn "umulqihi3"
7329 [(set (match_operand:HI 0 "register_operand" "=a")
7330 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7331 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7332 (clobber (reg:CC 17))]
7333 "TARGET_QIMODE_MATH"
7335 [(set_attr "type" "imul")
7336 (set_attr "length_immediate" "0")
7337 (set_attr "mode" "QI")])
7339 (define_insn "mulqihi3"
7340 [(set (match_operand:HI 0 "register_operand" "=a")
7341 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7342 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7343 (clobber (reg:CC 17))]
7344 "TARGET_QIMODE_MATH"
7346 [(set_attr "type" "imul")
7347 (set_attr "length_immediate" "0")
7348 (set_attr "mode" "QI")])
7350 (define_insn "umulditi3"
7351 [(set (match_operand:TI 0 "register_operand" "=A")
7352 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7353 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7354 (clobber (reg:CC 17))]
7357 [(set_attr "type" "imul")
7358 (set_attr "ppro_uops" "few")
7359 (set_attr "length_immediate" "0")
7360 (set_attr "mode" "DI")])
7362 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7363 (define_insn "umulsidi3"
7364 [(set (match_operand:DI 0 "register_operand" "=A")
7365 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7366 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7367 (clobber (reg:CC 17))]
7370 [(set_attr "type" "imul")
7371 (set_attr "ppro_uops" "few")
7372 (set_attr "length_immediate" "0")
7373 (set_attr "mode" "SI")])
7375 (define_insn "mulditi3"
7376 [(set (match_operand:TI 0 "register_operand" "=A")
7377 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7378 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7379 (clobber (reg:CC 17))]
7382 [(set_attr "type" "imul")
7383 (set_attr "length_immediate" "0")
7384 (set_attr "mode" "DI")])
7386 (define_insn "mulsidi3"
7387 [(set (match_operand:DI 0 "register_operand" "=A")
7388 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7389 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7390 (clobber (reg:CC 17))]
7393 [(set_attr "type" "imul")
7394 (set_attr "length_immediate" "0")
7395 (set_attr "mode" "SI")])
7397 (define_insn "*umuldi3_highpart_rex64"
7398 [(set (match_operand:DI 0 "register_operand" "=d")
7401 (mult:TI (zero_extend:TI
7402 (match_operand:DI 1 "register_operand" "%a"))
7404 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7406 (clobber (match_scratch:DI 3 "=a"))
7407 (clobber (reg:CC 17))]
7410 [(set_attr "type" "imul")
7411 (set_attr "ppro_uops" "few")
7412 (set_attr "length_immediate" "0")
7413 (set_attr "mode" "DI")])
7415 (define_insn "umulsi3_highpart"
7416 [(set (match_operand:SI 0 "register_operand" "=d")
7419 (mult:DI (zero_extend:DI
7420 (match_operand:SI 1 "register_operand" "%a"))
7422 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7424 (clobber (match_scratch:SI 3 "=a"))
7425 (clobber (reg:CC 17))]
7428 [(set_attr "type" "imul")
7429 (set_attr "ppro_uops" "few")
7430 (set_attr "length_immediate" "0")
7431 (set_attr "mode" "SI")])
7433 (define_insn "*umulsi3_highpart_zext"
7434 [(set (match_operand:DI 0 "register_operand" "=d")
7435 (zero_extend:DI (truncate:SI
7437 (mult:DI (zero_extend:DI
7438 (match_operand:SI 1 "register_operand" "%a"))
7440 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7442 (clobber (match_scratch:SI 3 "=a"))
7443 (clobber (reg:CC 17))]
7446 [(set_attr "type" "imul")
7447 (set_attr "ppro_uops" "few")
7448 (set_attr "length_immediate" "0")
7449 (set_attr "mode" "SI")])
7451 (define_insn "*smuldi3_highpart_rex64"
7452 [(set (match_operand:DI 0 "register_operand" "=d")
7455 (mult:TI (sign_extend:TI
7456 (match_operand:DI 1 "register_operand" "%a"))
7458 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7460 (clobber (match_scratch:DI 3 "=a"))
7461 (clobber (reg:CC 17))]
7464 [(set_attr "type" "imul")
7465 (set_attr "ppro_uops" "few")
7466 (set_attr "mode" "DI")])
7468 (define_insn "smulsi3_highpart"
7469 [(set (match_operand:SI 0 "register_operand" "=d")
7472 (mult:DI (sign_extend:DI
7473 (match_operand:SI 1 "register_operand" "%a"))
7475 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7477 (clobber (match_scratch:SI 3 "=a"))
7478 (clobber (reg:CC 17))]
7481 [(set_attr "type" "imul")
7482 (set_attr "ppro_uops" "few")
7483 (set_attr "mode" "SI")])
7485 (define_insn "*smulsi3_highpart_zext"
7486 [(set (match_operand:DI 0 "register_operand" "=d")
7487 (zero_extend:DI (truncate:SI
7489 (mult:DI (sign_extend:DI
7490 (match_operand:SI 1 "register_operand" "%a"))
7492 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7494 (clobber (match_scratch:SI 3 "=a"))
7495 (clobber (reg:CC 17))]
7498 [(set_attr "type" "imul")
7499 (set_attr "ppro_uops" "few")
7500 (set_attr "mode" "SI")])
7502 ;; The patterns that match these are at the end of this file.
7504 (define_expand "mulxf3"
7505 [(set (match_operand:XF 0 "register_operand" "")
7506 (mult:XF (match_operand:XF 1 "register_operand" "")
7507 (match_operand:XF 2 "register_operand" "")))]
7508 "TARGET_80387 && !TARGET_64BIT"
7511 (define_expand "multf3"
7512 [(set (match_operand:TF 0 "register_operand" "")
7513 (mult:TF (match_operand:TF 1 "register_operand" "")
7514 (match_operand:TF 2 "register_operand" "")))]
7518 (define_expand "muldf3"
7519 [(set (match_operand:DF 0 "register_operand" "")
7520 (mult:DF (match_operand:DF 1 "register_operand" "")
7521 (match_operand:DF 2 "nonimmediate_operand" "")))]
7522 "TARGET_80387 || TARGET_SSE2"
7525 (define_expand "mulsf3"
7526 [(set (match_operand:SF 0 "register_operand" "")
7527 (mult:SF (match_operand:SF 1 "register_operand" "")
7528 (match_operand:SF 2 "nonimmediate_operand" "")))]
7529 "TARGET_80387 || TARGET_SSE"
7532 ;; Divide instructions
7534 (define_insn "divqi3"
7535 [(set (match_operand:QI 0 "register_operand" "=a")
7536 (div:QI (match_operand:HI 1 "register_operand" "0")
7537 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7538 (clobber (reg:CC 17))]
7539 "TARGET_QIMODE_MATH"
7541 [(set_attr "type" "idiv")
7542 (set_attr "mode" "QI")
7543 (set_attr "ppro_uops" "few")])
7545 (define_insn "udivqi3"
7546 [(set (match_operand:QI 0 "register_operand" "=a")
7547 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7548 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7549 (clobber (reg:CC 17))]
7550 "TARGET_QIMODE_MATH"
7552 [(set_attr "type" "idiv")
7553 (set_attr "mode" "QI")
7554 (set_attr "ppro_uops" "few")])
7556 ;; The patterns that match these are at the end of this file.
7558 (define_expand "divxf3"
7559 [(set (match_operand:XF 0 "register_operand" "")
7560 (div:XF (match_operand:XF 1 "register_operand" "")
7561 (match_operand:XF 2 "register_operand" "")))]
7562 "TARGET_80387 && !TARGET_64BIT"
7565 (define_expand "divtf3"
7566 [(set (match_operand:TF 0 "register_operand" "")
7567 (div:TF (match_operand:TF 1 "register_operand" "")
7568 (match_operand:TF 2 "register_operand" "")))]
7572 (define_expand "divdf3"
7573 [(set (match_operand:DF 0 "register_operand" "")
7574 (div:DF (match_operand:DF 1 "register_operand" "")
7575 (match_operand:DF 2 "nonimmediate_operand" "")))]
7576 "TARGET_80387 || TARGET_SSE2"
7579 (define_expand "divsf3"
7580 [(set (match_operand:SF 0 "register_operand" "")
7581 (div:SF (match_operand:SF 1 "register_operand" "")
7582 (match_operand:SF 2 "nonimmediate_operand" "")))]
7583 "TARGET_80387 || TARGET_SSE"
7586 ;; Remainder instructions.
7588 (define_expand "divmoddi4"
7589 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7590 (div:DI (match_operand:DI 1 "register_operand" "")
7591 (match_operand:DI 2 "nonimmediate_operand" "")))
7592 (set (match_operand:DI 3 "register_operand" "")
7593 (mod:DI (match_dup 1) (match_dup 2)))
7594 (clobber (reg:CC 17))])]
7598 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7599 ;; Penalize eax case sligthly because it results in worse scheduling
7601 (define_insn "*divmoddi4_nocltd_rex64"
7602 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7603 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7604 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7605 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7606 (mod:DI (match_dup 2) (match_dup 3)))
7607 (clobber (reg:CC 17))]
7608 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7610 [(set_attr "type" "multi")])
7612 (define_insn "*divmoddi4_cltd_rex64"
7613 [(set (match_operand:DI 0 "register_operand" "=a")
7614 (div:DI (match_operand:DI 2 "register_operand" "a")
7615 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7616 (set (match_operand:DI 1 "register_operand" "=&d")
7617 (mod:DI (match_dup 2) (match_dup 3)))
7618 (clobber (reg:CC 17))]
7619 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7621 [(set_attr "type" "multi")])
7623 (define_insn "*divmoddi_noext_rex64"
7624 [(set (match_operand:DI 0 "register_operand" "=a")
7625 (div:DI (match_operand:DI 1 "register_operand" "0")
7626 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7627 (set (match_operand:DI 3 "register_operand" "=d")
7628 (mod:DI (match_dup 1) (match_dup 2)))
7629 (use (match_operand:DI 4 "register_operand" "3"))
7630 (clobber (reg:CC 17))]
7633 [(set_attr "type" "idiv")
7634 (set_attr "mode" "DI")
7635 (set_attr "ppro_uops" "few")])
7638 [(set (match_operand:DI 0 "register_operand" "")
7639 (div:DI (match_operand:DI 1 "register_operand" "")
7640 (match_operand:DI 2 "nonimmediate_operand" "")))
7641 (set (match_operand:DI 3 "register_operand" "")
7642 (mod:DI (match_dup 1) (match_dup 2)))
7643 (clobber (reg:CC 17))]
7644 "TARGET_64BIT && reload_completed"
7645 [(parallel [(set (match_dup 3)
7646 (ashiftrt:DI (match_dup 4) (const_int 63)))
7647 (clobber (reg:CC 17))])
7648 (parallel [(set (match_dup 0)
7649 (div:DI (reg:DI 0) (match_dup 2)))
7651 (mod:DI (reg:DI 0) (match_dup 2)))
7653 (clobber (reg:CC 17))])]
7655 /* Avoid use of cltd in favour of a mov+shift. */
7656 if (!TARGET_USE_CLTD && !optimize_size)
7658 if (true_regnum (operands[1]))
7659 emit_move_insn (operands[0], operands[1]);
7661 emit_move_insn (operands[3], operands[1]);
7662 operands[4] = operands[3];
7666 if (true_regnum (operands[1]))
7668 operands[4] = operands[1];
7673 (define_expand "divmodsi4"
7674 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7675 (div:SI (match_operand:SI 1 "register_operand" "")
7676 (match_operand:SI 2 "nonimmediate_operand" "")))
7677 (set (match_operand:SI 3 "register_operand" "")
7678 (mod:SI (match_dup 1) (match_dup 2)))
7679 (clobber (reg:CC 17))])]
7683 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7684 ;; Penalize eax case sligthly because it results in worse scheduling
7686 (define_insn "*divmodsi4_nocltd"
7687 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7688 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7689 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7690 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7691 (mod:SI (match_dup 2) (match_dup 3)))
7692 (clobber (reg:CC 17))]
7693 "!optimize_size && !TARGET_USE_CLTD"
7695 [(set_attr "type" "multi")])
7697 (define_insn "*divmodsi4_cltd"
7698 [(set (match_operand:SI 0 "register_operand" "=a")
7699 (div:SI (match_operand:SI 2 "register_operand" "a")
7700 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7701 (set (match_operand:SI 1 "register_operand" "=&d")
7702 (mod:SI (match_dup 2) (match_dup 3)))
7703 (clobber (reg:CC 17))]
7704 "optimize_size || TARGET_USE_CLTD"
7706 [(set_attr "type" "multi")])
7708 (define_insn "*divmodsi_noext"
7709 [(set (match_operand:SI 0 "register_operand" "=a")
7710 (div:SI (match_operand:SI 1 "register_operand" "0")
7711 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7712 (set (match_operand:SI 3 "register_operand" "=d")
7713 (mod:SI (match_dup 1) (match_dup 2)))
7714 (use (match_operand:SI 4 "register_operand" "3"))
7715 (clobber (reg:CC 17))]
7718 [(set_attr "type" "idiv")
7719 (set_attr "mode" "SI")
7720 (set_attr "ppro_uops" "few")])
7723 [(set (match_operand:SI 0 "register_operand" "")
7724 (div:SI (match_operand:SI 1 "register_operand" "")
7725 (match_operand:SI 2 "nonimmediate_operand" "")))
7726 (set (match_operand:SI 3 "register_operand" "")
7727 (mod:SI (match_dup 1) (match_dup 2)))
7728 (clobber (reg:CC 17))]
7730 [(parallel [(set (match_dup 3)
7731 (ashiftrt:SI (match_dup 4) (const_int 31)))
7732 (clobber (reg:CC 17))])
7733 (parallel [(set (match_dup 0)
7734 (div:SI (reg:SI 0) (match_dup 2)))
7736 (mod:SI (reg:SI 0) (match_dup 2)))
7738 (clobber (reg:CC 17))])]
7740 /* Avoid use of cltd in favour of a mov+shift. */
7741 if (!TARGET_USE_CLTD && !optimize_size)
7743 if (true_regnum (operands[1]))
7744 emit_move_insn (operands[0], operands[1]);
7746 emit_move_insn (operands[3], operands[1]);
7747 operands[4] = operands[3];
7751 if (true_regnum (operands[1]))
7753 operands[4] = operands[1];
7757 (define_insn "divmodhi4"
7758 [(set (match_operand:HI 0 "register_operand" "=a")
7759 (div:HI (match_operand:HI 1 "register_operand" "0")
7760 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7761 (set (match_operand:HI 3 "register_operand" "=&d")
7762 (mod:HI (match_dup 1) (match_dup 2)))
7763 (clobber (reg:CC 17))]
7764 "TARGET_HIMODE_MATH"
7766 [(set_attr "type" "multi")
7767 (set_attr "length_immediate" "0")
7768 (set_attr "mode" "SI")])
7770 (define_insn "udivmoddi4"
7771 [(set (match_operand:DI 0 "register_operand" "=a")
7772 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7773 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7774 (set (match_operand:DI 3 "register_operand" "=&d")
7775 (umod:DI (match_dup 1) (match_dup 2)))
7776 (clobber (reg:CC 17))]
7778 "xor{q}\t%3, %3\;div{q}\t%2"
7779 [(set_attr "type" "multi")
7780 (set_attr "length_immediate" "0")
7781 (set_attr "mode" "DI")])
7783 (define_insn "*udivmoddi4_noext"
7784 [(set (match_operand:DI 0 "register_operand" "=a")
7785 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7786 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7787 (set (match_operand:DI 3 "register_operand" "=d")
7788 (umod:DI (match_dup 1) (match_dup 2)))
7790 (clobber (reg:CC 17))]
7793 [(set_attr "type" "idiv")
7794 (set_attr "ppro_uops" "few")
7795 (set_attr "mode" "DI")])
7798 [(set (match_operand:DI 0 "register_operand" "")
7799 (udiv:DI (match_operand:DI 1 "register_operand" "")
7800 (match_operand:DI 2 "nonimmediate_operand" "")))
7801 (set (match_operand:DI 3 "register_operand" "")
7802 (umod:DI (match_dup 1) (match_dup 2)))
7803 (clobber (reg:CC 17))]
7804 "reload_completed && TARGET_64BIT"
7805 [(set (match_dup 3) (const_int 0))
7806 (parallel [(set (match_dup 0)
7807 (udiv:DI (match_dup 1) (match_dup 2)))
7809 (umod:DI (match_dup 1) (match_dup 2)))
7811 (clobber (reg:CC 17))])]
7814 (define_insn "udivmodsi4"
7815 [(set (match_operand:SI 0 "register_operand" "=a")
7816 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7817 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7818 (set (match_operand:SI 3 "register_operand" "=&d")
7819 (umod:SI (match_dup 1) (match_dup 2)))
7820 (clobber (reg:CC 17))]
7822 "xor{l}\t%3, %3\;div{l}\t%2"
7823 [(set_attr "type" "multi")
7824 (set_attr "length_immediate" "0")
7825 (set_attr "mode" "SI")])
7827 (define_insn "*udivmodsi4_noext"
7828 [(set (match_operand:SI 0 "register_operand" "=a")
7829 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7830 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7831 (set (match_operand:SI 3 "register_operand" "=d")
7832 (umod:SI (match_dup 1) (match_dup 2)))
7834 (clobber (reg:CC 17))]
7837 [(set_attr "type" "idiv")
7838 (set_attr "ppro_uops" "few")
7839 (set_attr "mode" "SI")])
7842 [(set (match_operand:SI 0 "register_operand" "")
7843 (udiv:SI (match_operand:SI 1 "register_operand" "")
7844 (match_operand:SI 2 "nonimmediate_operand" "")))
7845 (set (match_operand:SI 3 "register_operand" "")
7846 (umod:SI (match_dup 1) (match_dup 2)))
7847 (clobber (reg:CC 17))]
7849 [(set (match_dup 3) (const_int 0))
7850 (parallel [(set (match_dup 0)
7851 (udiv:SI (match_dup 1) (match_dup 2)))
7853 (umod:SI (match_dup 1) (match_dup 2)))
7855 (clobber (reg:CC 17))])]
7858 (define_expand "udivmodhi4"
7859 [(set (match_dup 4) (const_int 0))
7860 (parallel [(set (match_operand:HI 0 "register_operand" "")
7861 (udiv:HI (match_operand:HI 1 "register_operand" "")
7862 (match_operand:HI 2 "nonimmediate_operand" "")))
7863 (set (match_operand:HI 3 "register_operand" "")
7864 (umod:HI (match_dup 1) (match_dup 2)))
7866 (clobber (reg:CC 17))])]
7867 "TARGET_HIMODE_MATH"
7868 "operands[4] = gen_reg_rtx (HImode);")
7870 (define_insn "*udivmodhi_noext"
7871 [(set (match_operand:HI 0 "register_operand" "=a")
7872 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7873 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7874 (set (match_operand:HI 3 "register_operand" "=d")
7875 (umod:HI (match_dup 1) (match_dup 2)))
7876 (use (match_operand:HI 4 "register_operand" "3"))
7877 (clobber (reg:CC 17))]
7880 [(set_attr "type" "idiv")
7881 (set_attr "mode" "HI")
7882 (set_attr "ppro_uops" "few")])
7884 ;; We can not use div/idiv for double division, because it causes
7885 ;; "division by zero" on the overflow and that's not what we expect
7886 ;; from truncate. Because true (non truncating) double division is
7887 ;; never generated, we can't create this insn anyway.
7890 ; [(set (match_operand:SI 0 "register_operand" "=a")
7892 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7894 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7895 ; (set (match_operand:SI 3 "register_operand" "=d")
7897 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7898 ; (clobber (reg:CC 17))]
7900 ; "div{l}\t{%2, %0|%0, %2}"
7901 ; [(set_attr "type" "idiv")
7902 ; (set_attr "ppro_uops" "few")])
7904 ;;- Logical AND instructions
7906 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7907 ;; Note that this excludes ah.
7909 (define_insn "*testdi_1_rex64"
7912 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7913 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7915 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7917 test{l}\t{%k1, %k0|%k0, %k1}
7918 test{l}\t{%k1, %k0|%k0, %k1}
7919 test{q}\t{%1, %0|%0, %1}
7920 test{q}\t{%1, %0|%0, %1}
7921 test{q}\t{%1, %0|%0, %1}"
7922 [(set_attr "type" "test")
7923 (set_attr "modrm" "0,1,0,1,1")
7924 (set_attr "mode" "SI,SI,DI,DI,DI")
7925 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7927 (define_insn "testsi_1"
7930 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7931 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7933 "ix86_match_ccmode (insn, CCNOmode)"
7934 "test{l}\t{%1, %0|%0, %1}"
7935 [(set_attr "type" "test")
7936 (set_attr "modrm" "0,1,1")
7937 (set_attr "mode" "SI")
7938 (set_attr "pent_pair" "uv,np,uv")])
7940 (define_expand "testsi_ccno_1"
7943 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7944 (match_operand:SI 1 "nonmemory_operand" ""))
7949 (define_insn "*testhi_1"
7951 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7952 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7954 "ix86_match_ccmode (insn, CCNOmode)"
7955 "test{w}\t{%1, %0|%0, %1}"
7956 [(set_attr "type" "test")
7957 (set_attr "modrm" "0,1,1")
7958 (set_attr "mode" "HI")
7959 (set_attr "pent_pair" "uv,np,uv")])
7961 (define_expand "testqi_ccz_1"
7963 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7964 (match_operand:QI 1 "nonmemory_operand" ""))
7969 (define_insn "*testqi_1"
7971 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7972 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7974 "ix86_match_ccmode (insn, CCNOmode)"
7976 if (which_alternative == 3)
7978 if (GET_CODE (operands[1]) == CONST_INT
7979 && (INTVAL (operands[1]) & 0xffffff00))
7980 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7981 return "test{l}\t{%1, %k0|%k0, %1}";
7983 return "test{b}\t{%1, %0|%0, %1}";
7985 [(set_attr "type" "test")
7986 (set_attr "modrm" "0,1,1,1")
7987 (set_attr "mode" "QI,QI,QI,SI")
7988 (set_attr "pent_pair" "uv,np,uv,np")])
7990 (define_expand "testqi_ext_ccno_0"
7995 (match_operand 0 "ext_register_operand" "")
7998 (match_operand 1 "const_int_operand" ""))
8003 (define_insn "*testqi_ext_0"
8008 (match_operand 0 "ext_register_operand" "Q")
8011 (match_operand 1 "const_int_operand" "n"))
8013 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
8014 && ix86_match_ccmode (insn, CCNOmode)"
8015 "test{b}\t{%1, %h0|%h0, %1}"
8016 [(set_attr "type" "test")
8017 (set_attr "mode" "QI")
8018 (set_attr "length_immediate" "1")
8019 (set_attr "pent_pair" "np")])
8021 (define_insn "*testqi_ext_1"
8026 (match_operand 0 "ext_register_operand" "Q")
8030 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
8032 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8033 "test{b}\t{%1, %h0|%h0, %1}"
8034 [(set_attr "type" "test")
8035 (set_attr "mode" "QI")])
8037 (define_insn "*testqi_ext_1_rex64"
8042 (match_operand 0 "ext_register_operand" "Q")
8046 (match_operand:QI 1 "register_operand" "Q")))
8048 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8049 "test{b}\t{%1, %h0|%h0, %1}"
8050 [(set_attr "type" "test")
8051 (set_attr "mode" "QI")])
8053 (define_insn "*testqi_ext_2"
8058 (match_operand 0 "ext_register_operand" "Q")
8062 (match_operand 1 "ext_register_operand" "Q")
8066 "ix86_match_ccmode (insn, CCNOmode)"
8067 "test{b}\t{%h1, %h0|%h0, %h1}"
8068 [(set_attr "type" "test")
8069 (set_attr "mode" "QI")])
8071 ;; Combine likes to form bit extractions for some tests. Humor it.
8072 (define_insn "*testqi_ext_3"
8074 (compare (zero_extract:SI
8075 (match_operand 0 "nonimmediate_operand" "rm")
8076 (match_operand:SI 1 "const_int_operand" "")
8077 (match_operand:SI 2 "const_int_operand" ""))
8079 "ix86_match_ccmode (insn, CCNOmode)
8080 && (GET_MODE (operands[0]) == SImode
8081 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8082 || GET_MODE (operands[0]) == HImode
8083 || GET_MODE (operands[0]) == QImode)"
8086 (define_insn "*testqi_ext_3_rex64"
8088 (compare (zero_extract:DI
8089 (match_operand 0 "nonimmediate_operand" "rm")
8090 (match_operand:DI 1 "const_int_operand" "")
8091 (match_operand:DI 2 "const_int_operand" ""))
8093 "ix86_match_ccmode (insn, CCNOmode)
8095 && (GET_MODE (operands[0]) == SImode
8096 || GET_MODE (operands[0]) == DImode
8097 || GET_MODE (operands[0]) == HImode
8098 || GET_MODE (operands[0]) == QImode)"
8103 (compare (zero_extract
8104 (match_operand 0 "nonimmediate_operand" "")
8105 (match_operand 1 "const_int_operand" "")
8106 (match_operand 2 "const_int_operand" ""))
8108 "ix86_match_ccmode (insn, CCNOmode)"
8109 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8111 HOST_WIDE_INT len = INTVAL (operands[1]);
8112 HOST_WIDE_INT pos = INTVAL (operands[2]);
8114 enum machine_mode mode;
8116 mode = GET_MODE (operands[0]);
8117 if (GET_CODE (operands[0]) == MEM)
8119 /* ??? Combine likes to put non-volatile mem extractions in QImode
8120 no matter the size of the test. So find a mode that works. */
8121 if (! MEM_VOLATILE_P (operands[0]))
8123 mode = smallest_mode_for_size (pos + len, MODE_INT);
8124 operands[0] = adjust_address (operands[0], mode, 0);
8127 else if (mode == HImode && pos + len <= 8)
8129 /* Small HImode tests can be converted to QImode. */
8131 operands[0] = gen_lowpart (QImode, operands[0]);
8134 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8135 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8137 operands[3] = gen_rtx_AND (mode, operands[0],
8138 GEN_INT (trunc_int_for_mode (mask, mode)));
8141 ;; %%% This used to optimize known byte-wide and operations to memory,
8142 ;; and sometimes to QImode registers. If this is considered useful,
8143 ;; it should be done with splitters.
8145 (define_expand "anddi3"
8146 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8147 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8148 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8149 (clobber (reg:CC 17))]
8151 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8153 (define_insn "*anddi_1_rex64"
8154 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8155 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8156 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8157 (clobber (reg:CC 17))]
8158 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8160 switch (get_attr_type (insn))
8164 enum machine_mode mode;
8166 if (GET_CODE (operands[2]) != CONST_INT)
8168 if (INTVAL (operands[2]) == 0xff)
8170 else if (INTVAL (operands[2]) == 0xffff)
8175 operands[1] = gen_lowpart (mode, operands[1]);
8177 return "movz{bq|x}\t{%1,%0|%0, %1}";
8179 return "movz{wq|x}\t{%1,%0|%0, %1}";
8183 if (! rtx_equal_p (operands[0], operands[1]))
8185 if (get_attr_mode (insn) == MODE_SI)
8186 return "and{l}\t{%k2, %k0|%k0, %k2}";
8188 return "and{q}\t{%2, %0|%0, %2}";
8191 [(set_attr "type" "alu,alu,alu,imovx")
8192 (set_attr "length_immediate" "*,*,*,0")
8193 (set_attr "mode" "SI,DI,DI,DI")])
8195 (define_insn "*anddi_2"
8197 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8198 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8200 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8201 (and:DI (match_dup 1) (match_dup 2)))]
8202 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8203 && ix86_binary_operator_ok (AND, DImode, operands)"
8205 and{l}\t{%k2, %k0|%k0, %k2}
8206 and{q}\t{%2, %0|%0, %2}
8207 and{q}\t{%2, %0|%0, %2}"
8208 [(set_attr "type" "alu")
8209 (set_attr "mode" "SI,DI,DI")])
8211 (define_expand "andsi3"
8212 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8213 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8214 (match_operand:SI 2 "general_operand" "")))
8215 (clobber (reg:CC 17))]
8217 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8219 (define_insn "*andsi_1"
8220 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8221 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8222 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8223 (clobber (reg:CC 17))]
8224 "ix86_binary_operator_ok (AND, SImode, operands)"
8226 switch (get_attr_type (insn))
8230 enum machine_mode mode;
8232 if (GET_CODE (operands[2]) != CONST_INT)
8234 if (INTVAL (operands[2]) == 0xff)
8236 else if (INTVAL (operands[2]) == 0xffff)
8241 operands[1] = gen_lowpart (mode, operands[1]);
8243 return "movz{bl|x}\t{%1,%0|%0, %1}";
8245 return "movz{wl|x}\t{%1,%0|%0, %1}";
8249 if (! rtx_equal_p (operands[0], operands[1]))
8251 return "and{l}\t{%2, %0|%0, %2}";
8254 [(set_attr "type" "alu,alu,imovx")
8255 (set_attr "length_immediate" "*,*,0")
8256 (set_attr "mode" "SI")])
8259 [(set (match_operand 0 "register_operand" "")
8261 (const_int -65536)))
8262 (clobber (reg:CC 17))]
8264 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8265 "operands[1] = gen_lowpart (HImode, operands[0]);")
8268 [(set (match_operand 0 "ext_register_operand" "")
8271 (clobber (reg:CC 17))]
8272 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8273 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8274 "operands[1] = gen_lowpart (QImode, operands[0]);")
8277 [(set (match_operand 0 "ext_register_operand" "")
8279 (const_int -65281)))
8280 (clobber (reg:CC 17))]
8281 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8282 [(parallel [(set (zero_extract:SI (match_dup 0)
8286 (zero_extract:SI (match_dup 0)
8289 (zero_extract:SI (match_dup 0)
8292 (clobber (reg:CC 17))])]
8293 "operands[0] = gen_lowpart (SImode, operands[0]);")
8295 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8296 (define_insn "*andsi_1_zext"
8297 [(set (match_operand:DI 0 "register_operand" "=r")
8299 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8300 (match_operand:SI 2 "general_operand" "rim"))))
8301 (clobber (reg:CC 17))]
8302 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8303 "and{l}\t{%2, %k0|%k0, %2}"
8304 [(set_attr "type" "alu")
8305 (set_attr "mode" "SI")])
8307 (define_insn "*andsi_2"
8309 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8310 (match_operand:SI 2 "general_operand" "rim,ri"))
8312 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8313 (and:SI (match_dup 1) (match_dup 2)))]
8314 "ix86_match_ccmode (insn, CCNOmode)
8315 && ix86_binary_operator_ok (AND, SImode, operands)"
8316 "and{l}\t{%2, %0|%0, %2}"
8317 [(set_attr "type" "alu")
8318 (set_attr "mode" "SI")])
8320 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8321 (define_insn "*andsi_2_zext"
8323 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8324 (match_operand:SI 2 "general_operand" "rim"))
8326 (set (match_operand:DI 0 "register_operand" "=r")
8327 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8328 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8329 && ix86_binary_operator_ok (AND, SImode, operands)"
8330 "and{l}\t{%2, %k0|%k0, %2}"
8331 [(set_attr "type" "alu")
8332 (set_attr "mode" "SI")])
8334 (define_expand "andhi3"
8335 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8336 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8337 (match_operand:HI 2 "general_operand" "")))
8338 (clobber (reg:CC 17))]
8339 "TARGET_HIMODE_MATH"
8340 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8342 (define_insn "*andhi_1"
8343 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8344 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8345 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8346 (clobber (reg:CC 17))]
8347 "ix86_binary_operator_ok (AND, HImode, operands)"
8349 switch (get_attr_type (insn))
8352 if (GET_CODE (operands[2]) != CONST_INT)
8354 if (INTVAL (operands[2]) == 0xff)
8355 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8359 if (! rtx_equal_p (operands[0], operands[1]))
8362 return "and{w}\t{%2, %0|%0, %2}";
8365 [(set_attr "type" "alu,alu,imovx")
8366 (set_attr "length_immediate" "*,*,0")
8367 (set_attr "mode" "HI,HI,SI")])
8369 (define_insn "*andhi_2"
8371 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8372 (match_operand:HI 2 "general_operand" "rim,ri"))
8374 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8375 (and:HI (match_dup 1) (match_dup 2)))]
8376 "ix86_match_ccmode (insn, CCNOmode)
8377 && ix86_binary_operator_ok (AND, HImode, operands)"
8378 "and{w}\t{%2, %0|%0, %2}"
8379 [(set_attr "type" "alu")
8380 (set_attr "mode" "HI")])
8382 (define_expand "andqi3"
8383 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8384 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8385 (match_operand:QI 2 "general_operand" "")))
8386 (clobber (reg:CC 17))]
8387 "TARGET_QIMODE_MATH"
8388 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8390 ;; %%% Potential partial reg stall on alternative 2. What to do?
8391 (define_insn "*andqi_1"
8392 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8393 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8394 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8395 (clobber (reg:CC 17))]
8396 "ix86_binary_operator_ok (AND, QImode, operands)"
8398 and{b}\t{%2, %0|%0, %2}
8399 and{b}\t{%2, %0|%0, %2}
8400 and{l}\t{%k2, %k0|%k0, %k2}"
8401 [(set_attr "type" "alu")
8402 (set_attr "mode" "QI,QI,SI")])
8404 (define_insn "*andqi_1_slp"
8405 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8406 (and:QI (match_dup 0)
8407 (match_operand:QI 1 "general_operand" "qi,qmi")))
8408 (clobber (reg:CC 17))]
8410 "and{b}\t{%1, %0|%0, %1}"
8411 [(set_attr "type" "alu1")
8412 (set_attr "mode" "QI")])
8414 (define_insn "*andqi_2"
8417 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8418 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8420 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8421 (and:QI (match_dup 1) (match_dup 2)))]
8422 "ix86_match_ccmode (insn, CCNOmode)
8423 && ix86_binary_operator_ok (AND, QImode, operands)"
8425 if (which_alternative == 2)
8427 if (GET_CODE (operands[2]) == CONST_INT
8428 && (INTVAL (operands[2]) & 0xffffff00))
8429 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8430 return "and{l}\t{%2, %k0|%k0, %2}";
8432 return "and{b}\t{%2, %0|%0, %2}";
8434 [(set_attr "type" "alu")
8435 (set_attr "mode" "QI,QI,SI")])
8437 (define_insn "*andqi_2_slp"
8440 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8441 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8443 (set (strict_low_part (match_dup 0))
8444 (and:QI (match_dup 0) (match_dup 1)))]
8445 "ix86_match_ccmode (insn, CCNOmode)"
8446 "and{b}\t{%1, %0|%0, %1}"
8447 [(set_attr "type" "alu1")
8448 (set_attr "mode" "QI")])
8450 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8451 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8452 ;; for a QImode operand, which of course failed.
8454 (define_insn "andqi_ext_0"
8455 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8460 (match_operand 1 "ext_register_operand" "0")
8463 (match_operand 2 "const_int_operand" "n")))
8464 (clobber (reg:CC 17))]
8465 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8466 "and{b}\t{%2, %h0|%h0, %2}"
8467 [(set_attr "type" "alu")
8468 (set_attr "length_immediate" "1")
8469 (set_attr "mode" "QI")])
8471 ;; Generated by peephole translating test to and. This shows up
8472 ;; often in fp comparisons.
8474 (define_insn "*andqi_ext_0_cc"
8479 (match_operand 1 "ext_register_operand" "0")
8482 (match_operand 2 "const_int_operand" "n"))
8484 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8493 "ix86_match_ccmode (insn, CCNOmode)
8494 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8495 "and{b}\t{%2, %h0|%h0, %2}"
8496 [(set_attr "type" "alu")
8497 (set_attr "length_immediate" "1")
8498 (set_attr "mode" "QI")])
8500 (define_insn "*andqi_ext_1"
8501 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8506 (match_operand 1 "ext_register_operand" "0")
8510 (match_operand:QI 2 "general_operand" "Qm"))))
8511 (clobber (reg:CC 17))]
8513 "and{b}\t{%2, %h0|%h0, %2}"
8514 [(set_attr "type" "alu")
8515 (set_attr "length_immediate" "0")
8516 (set_attr "mode" "QI")])
8518 (define_insn "*andqi_ext_1_rex64"
8519 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8524 (match_operand 1 "ext_register_operand" "0")
8528 (match_operand 2 "ext_register_operand" "Q"))))
8529 (clobber (reg:CC 17))]
8531 "and{b}\t{%2, %h0|%h0, %2}"
8532 [(set_attr "type" "alu")
8533 (set_attr "length_immediate" "0")
8534 (set_attr "mode" "QI")])
8536 (define_insn "*andqi_ext_2"
8537 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8542 (match_operand 1 "ext_register_operand" "%0")
8546 (match_operand 2 "ext_register_operand" "Q")
8549 (clobber (reg:CC 17))]
8551 "and{b}\t{%h2, %h0|%h0, %h2}"
8552 [(set_attr "type" "alu")
8553 (set_attr "length_immediate" "0")
8554 (set_attr "mode" "QI")])
8556 ;; Logical inclusive OR instructions
8558 ;; %%% This used to optimize known byte-wide and operations to memory.
8559 ;; If this is considered useful, it should be done with splitters.
8561 (define_expand "iordi3"
8562 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8563 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8564 (match_operand:DI 2 "x86_64_general_operand" "")))
8565 (clobber (reg:CC 17))]
8567 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8569 (define_insn "*iordi_1_rex64"
8570 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8571 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8572 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8573 (clobber (reg:CC 17))]
8575 && ix86_binary_operator_ok (IOR, DImode, operands)"
8576 "or{q}\t{%2, %0|%0, %2}"
8577 [(set_attr "type" "alu")
8578 (set_attr "mode" "DI")])
8580 (define_insn "*iordi_2_rex64"
8582 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8583 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8585 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8586 (ior:DI (match_dup 1) (match_dup 2)))]
8588 && ix86_match_ccmode (insn, CCNOmode)
8589 && ix86_binary_operator_ok (IOR, DImode, operands)"
8590 "or{q}\t{%2, %0|%0, %2}"
8591 [(set_attr "type" "alu")
8592 (set_attr "mode" "DI")])
8594 (define_insn "*iordi_3_rex64"
8596 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8597 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8599 (clobber (match_scratch:DI 0 "=r"))]
8601 && ix86_match_ccmode (insn, CCNOmode)
8602 && ix86_binary_operator_ok (IOR, DImode, operands)"
8603 "or{q}\t{%2, %0|%0, %2}"
8604 [(set_attr "type" "alu")
8605 (set_attr "mode" "DI")])
8608 (define_expand "iorsi3"
8609 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8610 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8611 (match_operand:SI 2 "general_operand" "")))
8612 (clobber (reg:CC 17))]
8614 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8616 (define_insn "*iorsi_1"
8617 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8618 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8619 (match_operand:SI 2 "general_operand" "ri,rmi")))
8620 (clobber (reg:CC 17))]
8621 "ix86_binary_operator_ok (IOR, SImode, operands)"
8622 "or{l}\t{%2, %0|%0, %2}"
8623 [(set_attr "type" "alu")
8624 (set_attr "mode" "SI")])
8626 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8627 (define_insn "*iorsi_1_zext"
8628 [(set (match_operand:DI 0 "register_operand" "=rm")
8630 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8631 (match_operand:SI 2 "general_operand" "rim"))))
8632 (clobber (reg:CC 17))]
8633 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8634 "or{l}\t{%2, %k0|%k0, %2}"
8635 [(set_attr "type" "alu")
8636 (set_attr "mode" "SI")])
8638 (define_insn "*iorsi_1_zext_imm"
8639 [(set (match_operand:DI 0 "register_operand" "=rm")
8640 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8641 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8642 (clobber (reg:CC 17))]
8644 "or{l}\t{%2, %k0|%k0, %2}"
8645 [(set_attr "type" "alu")
8646 (set_attr "mode" "SI")])
8648 (define_insn "*iorsi_2"
8650 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8651 (match_operand:SI 2 "general_operand" "rim,ri"))
8653 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8654 (ior:SI (match_dup 1) (match_dup 2)))]
8655 "ix86_match_ccmode (insn, CCNOmode)
8656 && ix86_binary_operator_ok (IOR, SImode, operands)"
8657 "or{l}\t{%2, %0|%0, %2}"
8658 [(set_attr "type" "alu")
8659 (set_attr "mode" "SI")])
8661 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8662 ;; ??? Special case for immediate operand is missing - it is tricky.
8663 (define_insn "*iorsi_2_zext"
8665 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8666 (match_operand:SI 2 "general_operand" "rim"))
8668 (set (match_operand:DI 0 "register_operand" "=r")
8669 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8670 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8671 && ix86_binary_operator_ok (IOR, SImode, operands)"
8672 "or{l}\t{%2, %k0|%k0, %2}"
8673 [(set_attr "type" "alu")
8674 (set_attr "mode" "SI")])
8676 (define_insn "*iorsi_2_zext_imm"
8678 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8679 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8681 (set (match_operand:DI 0 "register_operand" "=r")
8682 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8683 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8684 && ix86_binary_operator_ok (IOR, SImode, operands)"
8685 "or{l}\t{%2, %k0|%k0, %2}"
8686 [(set_attr "type" "alu")
8687 (set_attr "mode" "SI")])
8689 (define_insn "*iorsi_3"
8691 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8692 (match_operand:SI 2 "general_operand" "rim"))
8694 (clobber (match_scratch:SI 0 "=r"))]
8695 "ix86_match_ccmode (insn, CCNOmode)
8696 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8697 "or{l}\t{%2, %0|%0, %2}"
8698 [(set_attr "type" "alu")
8699 (set_attr "mode" "SI")])
8701 (define_expand "iorhi3"
8702 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8703 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8704 (match_operand:HI 2 "general_operand" "")))
8705 (clobber (reg:CC 17))]
8706 "TARGET_HIMODE_MATH"
8707 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8709 (define_insn "*iorhi_1"
8710 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8711 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8712 (match_operand:HI 2 "general_operand" "rmi,ri")))
8713 (clobber (reg:CC 17))]
8714 "ix86_binary_operator_ok (IOR, HImode, operands)"
8715 "or{w}\t{%2, %0|%0, %2}"
8716 [(set_attr "type" "alu")
8717 (set_attr "mode" "HI")])
8719 (define_insn "*iorhi_2"
8721 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8722 (match_operand:HI 2 "general_operand" "rim,ri"))
8724 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8725 (ior:HI (match_dup 1) (match_dup 2)))]
8726 "ix86_match_ccmode (insn, CCNOmode)
8727 && ix86_binary_operator_ok (IOR, HImode, operands)"
8728 "or{w}\t{%2, %0|%0, %2}"
8729 [(set_attr "type" "alu")
8730 (set_attr "mode" "HI")])
8732 (define_insn "*iorhi_3"
8734 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8735 (match_operand:HI 2 "general_operand" "rim"))
8737 (clobber (match_scratch:HI 0 "=r"))]
8738 "ix86_match_ccmode (insn, CCNOmode)
8739 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8740 "or{w}\t{%2, %0|%0, %2}"
8741 [(set_attr "type" "alu")
8742 (set_attr "mode" "HI")])
8744 (define_expand "iorqi3"
8745 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8746 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8747 (match_operand:QI 2 "general_operand" "")))
8748 (clobber (reg:CC 17))]
8749 "TARGET_QIMODE_MATH"
8750 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8752 ;; %%% Potential partial reg stall on alternative 2. What to do?
8753 (define_insn "*iorqi_1"
8754 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8755 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8756 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8757 (clobber (reg:CC 17))]
8758 "ix86_binary_operator_ok (IOR, QImode, operands)"
8760 or{b}\t{%2, %0|%0, %2}
8761 or{b}\t{%2, %0|%0, %2}
8762 or{l}\t{%k2, %k0|%k0, %k2}"
8763 [(set_attr "type" "alu")
8764 (set_attr "mode" "QI,QI,SI")])
8766 (define_insn "*iorqi_1_slp"
8767 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8768 (ior:QI (match_dup 0)
8769 (match_operand:QI 1 "general_operand" "qmi,qi")))
8770 (clobber (reg:CC 17))]
8772 "or{b}\t{%1, %0|%0, %1}"
8773 [(set_attr "type" "alu1")
8774 (set_attr "mode" "QI")])
8776 (define_insn "*iorqi_2"
8778 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8779 (match_operand:QI 2 "general_operand" "qim,qi"))
8781 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8782 (ior:QI (match_dup 1) (match_dup 2)))]
8783 "ix86_match_ccmode (insn, CCNOmode)
8784 && ix86_binary_operator_ok (IOR, QImode, operands)"
8785 "or{b}\t{%2, %0|%0, %2}"
8786 [(set_attr "type" "alu")
8787 (set_attr "mode" "QI")])
8789 (define_insn "*iorqi_2_slp"
8791 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8792 (match_operand:QI 1 "general_operand" "qim,qi"))
8794 (set (strict_low_part (match_dup 0))
8795 (ior:QI (match_dup 0) (match_dup 1)))]
8796 "ix86_match_ccmode (insn, CCNOmode)"
8797 "or{b}\t{%1, %0|%0, %1}"
8798 [(set_attr "type" "alu1")
8799 (set_attr "mode" "QI")])
8801 (define_insn "*iorqi_3"
8803 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8804 (match_operand:QI 2 "general_operand" "qim"))
8806 (clobber (match_scratch:QI 0 "=q"))]
8807 "ix86_match_ccmode (insn, CCNOmode)
8808 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8809 "or{b}\t{%2, %0|%0, %2}"
8810 [(set_attr "type" "alu")
8811 (set_attr "mode" "QI")])
8814 ;; Logical XOR instructions
8816 ;; %%% This used to optimize known byte-wide and operations to memory.
8817 ;; If this is considered useful, it should be done with splitters.
8819 (define_expand "xordi3"
8820 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8821 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8822 (match_operand:DI 2 "x86_64_general_operand" "")))
8823 (clobber (reg:CC 17))]
8825 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8827 (define_insn "*xordi_1_rex64"
8828 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8829 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8830 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8831 (clobber (reg:CC 17))]
8833 && ix86_binary_operator_ok (XOR, DImode, operands)"
8835 xor{q}\t{%2, %0|%0, %2}
8836 xor{q}\t{%2, %0|%0, %2}"
8837 [(set_attr "type" "alu")
8838 (set_attr "mode" "DI,DI")])
8840 (define_insn "*xordi_2_rex64"
8842 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8843 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8845 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8846 (xor:DI (match_dup 1) (match_dup 2)))]
8848 && ix86_match_ccmode (insn, CCNOmode)
8849 && ix86_binary_operator_ok (XOR, DImode, operands)"
8851 xor{q}\t{%2, %0|%0, %2}
8852 xor{q}\t{%2, %0|%0, %2}"
8853 [(set_attr "type" "alu")
8854 (set_attr "mode" "DI,DI")])
8856 (define_insn "*xordi_3_rex64"
8858 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8859 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8861 (clobber (match_scratch:DI 0 "=r"))]
8863 && ix86_match_ccmode (insn, CCNOmode)
8864 && ix86_binary_operator_ok (XOR, DImode, operands)"
8865 "xor{q}\t{%2, %0|%0, %2}"
8866 [(set_attr "type" "alu")
8867 (set_attr "mode" "DI")])
8869 (define_expand "xorsi3"
8870 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8871 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8872 (match_operand:SI 2 "general_operand" "")))
8873 (clobber (reg:CC 17))]
8875 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8877 (define_insn "*xorsi_1"
8878 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8879 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8880 (match_operand:SI 2 "general_operand" "ri,rm")))
8881 (clobber (reg:CC 17))]
8882 "ix86_binary_operator_ok (XOR, SImode, operands)"
8883 "xor{l}\t{%2, %0|%0, %2}"
8884 [(set_attr "type" "alu")
8885 (set_attr "mode" "SI")])
8887 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8888 ;; Add speccase for immediates
8889 (define_insn "*xorsi_1_zext"
8890 [(set (match_operand:DI 0 "register_operand" "=r")
8892 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8893 (match_operand:SI 2 "general_operand" "rim"))))
8894 (clobber (reg:CC 17))]
8895 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8896 "xor{l}\t{%2, %k0|%k0, %2}"
8897 [(set_attr "type" "alu")
8898 (set_attr "mode" "SI")])
8900 (define_insn "*xorsi_1_zext_imm"
8901 [(set (match_operand:DI 0 "register_operand" "=r")
8902 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8903 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8904 (clobber (reg:CC 17))]
8905 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8906 "xor{l}\t{%2, %k0|%k0, %2}"
8907 [(set_attr "type" "alu")
8908 (set_attr "mode" "SI")])
8910 (define_insn "*xorsi_2"
8912 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8913 (match_operand:SI 2 "general_operand" "rim,ri"))
8915 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8916 (xor:SI (match_dup 1) (match_dup 2)))]
8917 "ix86_match_ccmode (insn, CCNOmode)
8918 && ix86_binary_operator_ok (XOR, SImode, operands)"
8919 "xor{l}\t{%2, %0|%0, %2}"
8920 [(set_attr "type" "alu")
8921 (set_attr "mode" "SI")])
8923 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8924 ;; ??? Special case for immediate operand is missing - it is tricky.
8925 (define_insn "*xorsi_2_zext"
8927 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8928 (match_operand:SI 2 "general_operand" "rim"))
8930 (set (match_operand:DI 0 "register_operand" "=r")
8931 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8932 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8933 && ix86_binary_operator_ok (XOR, SImode, operands)"
8934 "xor{l}\t{%2, %k0|%k0, %2}"
8935 [(set_attr "type" "alu")
8936 (set_attr "mode" "SI")])
8938 (define_insn "*xorsi_2_zext_imm"
8940 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8941 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8943 (set (match_operand:DI 0 "register_operand" "=r")
8944 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8945 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8946 && ix86_binary_operator_ok (XOR, SImode, operands)"
8947 "xor{l}\t{%2, %k0|%k0, %2}"
8948 [(set_attr "type" "alu")
8949 (set_attr "mode" "SI")])
8951 (define_insn "*xorsi_3"
8953 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8954 (match_operand:SI 2 "general_operand" "rim"))
8956 (clobber (match_scratch:SI 0 "=r"))]
8957 "ix86_match_ccmode (insn, CCNOmode)
8958 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8959 "xor{l}\t{%2, %0|%0, %2}"
8960 [(set_attr "type" "alu")
8961 (set_attr "mode" "SI")])
8963 (define_expand "xorhi3"
8964 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8965 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8966 (match_operand:HI 2 "general_operand" "")))
8967 (clobber (reg:CC 17))]
8968 "TARGET_HIMODE_MATH"
8969 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
8971 (define_insn "*xorhi_1"
8972 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8973 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8974 (match_operand:HI 2 "general_operand" "rmi,ri")))
8975 (clobber (reg:CC 17))]
8976 "ix86_binary_operator_ok (XOR, HImode, operands)"
8977 "xor{w}\t{%2, %0|%0, %2}"
8978 [(set_attr "type" "alu")
8979 (set_attr "mode" "HI")])
8981 (define_insn "*xorhi_2"
8983 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8984 (match_operand:HI 2 "general_operand" "rim,ri"))
8986 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8987 (xor:HI (match_dup 1) (match_dup 2)))]
8988 "ix86_match_ccmode (insn, CCNOmode)
8989 && ix86_binary_operator_ok (XOR, HImode, operands)"
8990 "xor{w}\t{%2, %0|%0, %2}"
8991 [(set_attr "type" "alu")
8992 (set_attr "mode" "HI")])
8994 (define_insn "*xorhi_3"
8996 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8997 (match_operand:HI 2 "general_operand" "rim"))
8999 (clobber (match_scratch:HI 0 "=r"))]
9000 "ix86_match_ccmode (insn, CCNOmode)
9001 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9002 "xor{w}\t{%2, %0|%0, %2}"
9003 [(set_attr "type" "alu")
9004 (set_attr "mode" "HI")])
9006 (define_expand "xorqi3"
9007 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9008 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9009 (match_operand:QI 2 "general_operand" "")))
9010 (clobber (reg:CC 17))]
9011 "TARGET_QIMODE_MATH"
9012 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9014 ;; %%% Potential partial reg stall on alternative 2. What to do?
9015 (define_insn "*xorqi_1"
9016 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9017 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9018 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9019 (clobber (reg:CC 17))]
9020 "ix86_binary_operator_ok (XOR, QImode, operands)"
9022 xor{b}\t{%2, %0|%0, %2}
9023 xor{b}\t{%2, %0|%0, %2}
9024 xor{l}\t{%k2, %k0|%k0, %k2}"
9025 [(set_attr "type" "alu")
9026 (set_attr "mode" "QI,QI,SI")])
9028 (define_insn "*xorqi_ext_1"
9029 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9033 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9036 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9039 (clobber (reg:CC 17))]
9041 "xor{b}\t{%h2, %h0|%h0, %h2}"
9042 [(set_attr "type" "alu")
9043 (set_attr "length_immediate" "0")
9044 (set_attr "mode" "QI")])
9046 (define_insn "*xorqi_cc_1"
9049 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9050 (match_operand:QI 2 "general_operand" "qim,qi"))
9052 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9053 (xor:QI (match_dup 1) (match_dup 2)))]
9054 "ix86_match_ccmode (insn, CCNOmode)
9055 && ix86_binary_operator_ok (XOR, QImode, operands)"
9056 "xor{b}\t{%2, %0|%0, %2}"
9057 [(set_attr "type" "alu")
9058 (set_attr "mode" "QI")])
9060 (define_insn "*xorqi_cc_2"
9063 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9064 (match_operand:QI 2 "general_operand" "qim"))
9066 (clobber (match_scratch:QI 0 "=q"))]
9067 "ix86_match_ccmode (insn, CCNOmode)
9068 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9069 "xor{b}\t{%2, %0|%0, %2}"
9070 [(set_attr "type" "alu")
9071 (set_attr "mode" "QI")])
9073 (define_insn "*xorqi_cc_ext_1"
9078 (match_operand 1 "ext_register_operand" "0")
9081 (match_operand:QI 2 "general_operand" "qmn"))
9083 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9087 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9089 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9090 "xor{b}\t{%2, %h0|%h0, %2}"
9091 [(set_attr "type" "alu")
9092 (set_attr "mode" "QI")])
9094 (define_insn "*xorqi_cc_ext_1_rex64"
9099 (match_operand 1 "ext_register_operand" "0")
9102 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9104 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9108 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9110 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9111 "xor{b}\t{%2, %h0|%h0, %2}"
9112 [(set_attr "type" "alu")
9113 (set_attr "mode" "QI")])
9115 (define_expand "xorqi_cc_ext_1"
9121 (match_operand 1 "ext_register_operand" "")
9124 (match_operand:QI 2 "general_operand" ""))
9126 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9130 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9135 ;; Negation instructions
9137 (define_expand "negdi2"
9138 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9139 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9140 (clobber (reg:CC 17))])]
9142 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9144 (define_insn "*negdi2_1"
9145 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9146 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9147 (clobber (reg:CC 17))]
9149 && ix86_unary_operator_ok (NEG, DImode, operands)"
9153 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9154 (neg:DI (match_operand:DI 1 "general_operand" "")))
9155 (clobber (reg:CC 17))]
9160 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9161 (set (match_dup 0) (neg:SI (match_dup 2)))])
9164 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9167 (clobber (reg:CC 17))])
9170 (neg:SI (match_dup 1)))
9171 (clobber (reg:CC 17))])]
9172 "split_di (operands+1, 1, operands+2, operands+3);
9173 split_di (operands+0, 1, operands+0, operands+1);")
9175 (define_insn "*negdi2_1_rex64"
9176 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9177 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9178 (clobber (reg:CC 17))]
9179 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9181 [(set_attr "type" "negnot")
9182 (set_attr "mode" "DI")])
9184 ;; The problem with neg is that it does not perform (compare x 0),
9185 ;; it really performs (compare 0 x), which leaves us with the zero
9186 ;; flag being the only useful item.
9188 (define_insn "*negdi2_cmpz_rex64"
9190 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9192 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9193 (neg:DI (match_dup 1)))]
9194 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9196 [(set_attr "type" "negnot")
9197 (set_attr "mode" "DI")])
9200 (define_expand "negsi2"
9201 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9202 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9203 (clobber (reg:CC 17))])]
9205 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9207 (define_insn "*negsi2_1"
9208 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9209 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9210 (clobber (reg:CC 17))]
9211 "ix86_unary_operator_ok (NEG, SImode, operands)"
9213 [(set_attr "type" "negnot")
9214 (set_attr "mode" "SI")])
9216 ;; Combine is quite creative about this pattern.
9217 (define_insn "*negsi2_1_zext"
9218 [(set (match_operand:DI 0 "register_operand" "=r")
9219 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9222 (clobber (reg:CC 17))]
9223 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9225 [(set_attr "type" "negnot")
9226 (set_attr "mode" "SI")])
9228 ;; The problem with neg is that it does not perform (compare x 0),
9229 ;; it really performs (compare 0 x), which leaves us with the zero
9230 ;; flag being the only useful item.
9232 (define_insn "*negsi2_cmpz"
9234 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9236 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9237 (neg:SI (match_dup 1)))]
9238 "ix86_unary_operator_ok (NEG, SImode, operands)"
9240 [(set_attr "type" "negnot")
9241 (set_attr "mode" "SI")])
9243 (define_insn "*negsi2_cmpz_zext"
9245 (compare:CCZ (lshiftrt:DI
9247 (match_operand:DI 1 "register_operand" "0")
9251 (set (match_operand:DI 0 "register_operand" "=r")
9252 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9255 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9257 [(set_attr "type" "negnot")
9258 (set_attr "mode" "SI")])
9260 (define_expand "neghi2"
9261 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9262 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9263 (clobber (reg:CC 17))])]
9264 "TARGET_HIMODE_MATH"
9265 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9267 (define_insn "*neghi2_1"
9268 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9269 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9270 (clobber (reg:CC 17))]
9271 "ix86_unary_operator_ok (NEG, HImode, operands)"
9273 [(set_attr "type" "negnot")
9274 (set_attr "mode" "HI")])
9276 (define_insn "*neghi2_cmpz"
9278 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9280 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9281 (neg:HI (match_dup 1)))]
9282 "ix86_unary_operator_ok (NEG, HImode, operands)"
9284 [(set_attr "type" "negnot")
9285 (set_attr "mode" "HI")])
9287 (define_expand "negqi2"
9288 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9289 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9290 (clobber (reg:CC 17))])]
9291 "TARGET_QIMODE_MATH"
9292 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9294 (define_insn "*negqi2_1"
9295 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9296 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9297 (clobber (reg:CC 17))]
9298 "ix86_unary_operator_ok (NEG, QImode, operands)"
9300 [(set_attr "type" "negnot")
9301 (set_attr "mode" "QI")])
9303 (define_insn "*negqi2_cmpz"
9305 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9307 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9308 (neg:QI (match_dup 1)))]
9309 "ix86_unary_operator_ok (NEG, QImode, operands)"
9311 [(set_attr "type" "negnot")
9312 (set_attr "mode" "QI")])
9314 ;; Changing of sign for FP values is doable using integer unit too.
9316 (define_expand "negsf2"
9317 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9318 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9319 (clobber (reg:CC 17))])]
9323 /* In case operand is in memory, we will not use SSE. */
9324 if (memory_operand (operands[0], VOIDmode)
9325 && rtx_equal_p (operands[0], operands[1]))
9326 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9329 /* Using SSE is tricky, since we need bitwise negation of -0
9331 rtx reg = gen_reg_rtx (SFmode);
9332 rtx dest = operands[0];
9334 operands[1] = force_reg (SFmode, operands[1]);
9335 operands[0] = force_reg (SFmode, operands[0]);
9336 emit_move_insn (reg,
9337 gen_lowpart (SFmode,
9338 GEN_INT (trunc_int_for_mode (0x80000000,
9340 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9341 if (dest != operands[0])
9342 emit_move_insn (dest, operands[0]);
9346 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9348 (define_insn "negsf2_memory"
9349 [(set (match_operand:SF 0 "memory_operand" "=m")
9350 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9351 (clobber (reg:CC 17))]
9352 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9355 (define_insn "negsf2_ifs"
9356 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9357 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9358 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
9359 (clobber (reg:CC 17))]
9361 && (reload_in_progress || reload_completed
9362 || (register_operand (operands[0], VOIDmode)
9363 && register_operand (operands[1], VOIDmode)))"
9367 [(set (match_operand:SF 0 "memory_operand" "")
9368 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9369 (use (match_operand:SF 2 "" ""))
9370 (clobber (reg:CC 17))]
9372 [(parallel [(set (match_dup 0)
9373 (neg:SF (match_dup 1)))
9374 (clobber (reg:CC 17))])])
9377 [(set (match_operand:SF 0 "register_operand" "")
9378 (neg:SF (match_operand:SF 1 "register_operand" "")))
9379 (use (match_operand:SF 2 "" ""))
9380 (clobber (reg:CC 17))]
9381 "reload_completed && !SSE_REG_P (operands[0])"
9382 [(parallel [(set (match_dup 0)
9383 (neg:SF (match_dup 1)))
9384 (clobber (reg:CC 17))])])
9387 [(set (match_operand:SF 0 "register_operand" "")
9388 (neg:SF (match_operand:SF 1 "register_operand" "")))
9389 (use (match_operand:SF 2 "register_operand" ""))
9390 (clobber (reg:CC 17))]
9391 "reload_completed && SSE_REG_P (operands[0])"
9392 [(set (subreg:TI (match_dup 0) 0)
9393 (xor:TI (subreg:TI (match_dup 1) 0)
9394 (subreg:TI (match_dup 2) 0)))]
9396 if (operands_match_p (operands[0], operands[2]))
9400 operands[1] = operands[2];
9406 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9407 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9409 (define_insn "*negsf2_if"
9410 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9411 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9412 (clobber (reg:CC 17))]
9413 "TARGET_80387 && !TARGET_SSE
9414 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9418 [(set (match_operand:SF 0 "register_operand" "")
9419 (neg:SF (match_operand:SF 1 "register_operand" "")))
9420 (clobber (reg:CC 17))]
9421 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9423 (neg:SF (match_dup 1)))]
9427 [(set (match_operand:SF 0 "register_operand" "")
9428 (neg:SF (match_operand:SF 1 "register_operand" "")))
9429 (clobber (reg:CC 17))]
9430 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9431 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9432 (clobber (reg:CC 17))])]
9433 "operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9434 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9437 [(set (match_operand 0 "memory_operand" "")
9438 (neg (match_operand 1 "memory_operand" "")))
9439 (clobber (reg:CC 17))]
9440 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9441 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9442 (clobber (reg:CC 17))])]
9444 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9446 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9449 operands[0] = adjust_address (operands[0], QImode, size - 1);
9450 operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
9453 (define_expand "negdf2"
9454 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9455 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9456 (clobber (reg:CC 17))])]
9460 /* In case operand is in memory, we will not use SSE. */
9461 if (memory_operand (operands[0], VOIDmode)
9462 && rtx_equal_p (operands[0], operands[1]))
9463 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9466 /* Using SSE is tricky, since we need bitwise negation of -0
9468 rtx reg = gen_reg_rtx (DFmode);
9469 #if HOST_BITS_PER_WIDE_INT >= 64
9470 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9473 rtx imm = immed_double_const (0, 0x80000000, DImode);
9475 rtx dest = operands[0];
9477 operands[1] = force_reg (DFmode, operands[1]);
9478 operands[0] = force_reg (DFmode, operands[0]);
9479 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9480 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9481 if (dest != operands[0])
9482 emit_move_insn (dest, operands[0]);
9486 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9488 (define_insn "negdf2_memory"
9489 [(set (match_operand:DF 0 "memory_operand" "=m")
9490 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9491 (clobber (reg:CC 17))]
9492 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9495 (define_insn "negdf2_ifs"
9496 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9497 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9498 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9499 (clobber (reg:CC 17))]
9500 "TARGET_SSE2 && !TARGET_64BIT
9501 && (reload_in_progress || reload_completed
9502 || (register_operand (operands[0], VOIDmode)
9503 && register_operand (operands[1], VOIDmode)))"
9506 (define_insn "*negdf2_ifs_rex64"
9507 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9508 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9509 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9510 (clobber (reg:CC 17))]
9511 "TARGET_SSE2 && TARGET_64BIT
9512 && (reload_in_progress || reload_completed
9513 || (register_operand (operands[0], VOIDmode)
9514 && register_operand (operands[1], VOIDmode)))"
9518 [(set (match_operand:DF 0 "memory_operand" "")
9519 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9520 (use (match_operand:DF 2 "" ""))
9521 (clobber (reg:CC 17))]
9523 [(parallel [(set (match_dup 0)
9524 (neg:DF (match_dup 1)))
9525 (clobber (reg:CC 17))])])
9528 [(set (match_operand:DF 0 "register_operand" "")
9529 (neg:DF (match_operand:DF 1 "register_operand" "")))
9530 (use (match_operand:DF 2 "" ""))
9531 (clobber (reg:CC 17))]
9532 "reload_completed && !SSE_REG_P (operands[0])
9533 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9534 [(parallel [(set (match_dup 0)
9535 (neg:DF (match_dup 1)))
9536 (clobber (reg:CC 17))])])
9539 [(set (match_operand:DF 0 "register_operand" "")
9540 (neg:DF (match_operand:DF 1 "register_operand" "")))
9541 (use (match_operand:DF 2 "" ""))
9542 (clobber (reg:CC 17))]
9543 "reload_completed && GENERAL_REG_P (operands[0]) && TARGET_64BIT"
9544 [(parallel [(set (match_dup 0)
9545 (xor:DI (match_dup 1) (match_dup 2)))
9546 (clobber (reg:CC 17))])]
9547 "operands[0] = gen_lowpart (DImode, operands[0]);
9548 operands[1] = gen_lowpart (DImode, operands[1]);
9549 operands[2] = gen_lowpart (DImode, operands[2]);")
9552 [(set (match_operand:DF 0 "register_operand" "")
9553 (neg:DF (match_operand:DF 1 "register_operand" "")))
9554 (use (match_operand:DF 2 "register_operand" ""))
9555 (clobber (reg:CC 17))]
9556 "reload_completed && SSE_REG_P (operands[0])"
9557 [(set (subreg:TI (match_dup 0) 0)
9558 (xor:TI (subreg:TI (match_dup 1) 0)
9559 (subreg:TI (match_dup 2) 0)))]
9561 if (operands_match_p (operands[0], operands[2]))
9565 operands[1] = operands[2];
9570 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9571 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9573 (define_insn "*negdf2_if"
9574 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9575 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9576 (clobber (reg:CC 17))]
9577 "TARGET_80387 && !TARGET_64BIT
9578 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9581 ;; FIXME: We should to allow integer registers here. Problem is that
9582 ;; we need another scratch register to get constant from.
9583 ;; Forcing constant to mem if no register available in peep2 should be
9584 ;; safe even for PIC mode, because of RIP relative addressing.
9585 (define_insn "*negdf2_if_rex64"
9586 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9587 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9588 (clobber (reg:CC 17))]
9589 "TARGET_80387 && TARGET_64BIT
9590 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9594 [(set (match_operand:DF 0 "register_operand" "")
9595 (neg:DF (match_operand:DF 1 "register_operand" "")))
9596 (clobber (reg:CC 17))]
9597 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9599 (neg:DF (match_dup 1)))]
9603 [(set (match_operand:DF 0 "register_operand" "")
9604 (neg:DF (match_operand:DF 1 "register_operand" "")))
9605 (clobber (reg:CC 17))]
9606 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
9608 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9609 (clobber (reg:CC 17))])]
9610 "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9611 split_di (operands+0, 1, operands+2, operands+3);")
9613 (define_expand "negxf2"
9614 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9615 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9616 (clobber (reg:CC 17))])]
9617 "TARGET_80387 && !TARGET_64BIT"
9618 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9620 (define_expand "negtf2"
9621 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9622 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9623 (clobber (reg:CC 17))])]
9625 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9627 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9628 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9630 (define_insn "*negxf2_if"
9631 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9632 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9633 (clobber (reg:CC 17))]
9634 "TARGET_80387 && !TARGET_64BIT
9635 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9639 [(set (match_operand:XF 0 "register_operand" "")
9640 (neg:XF (match_operand:XF 1 "register_operand" "")))
9641 (clobber (reg:CC 17))]
9642 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9644 (neg:XF (match_dup 1)))]
9648 [(set (match_operand:XF 0 "register_operand" "")
9649 (neg:XF (match_operand:XF 1 "register_operand" "")))
9650 (clobber (reg:CC 17))]
9651 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9652 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9653 (clobber (reg:CC 17))])]
9654 "operands[1] = GEN_INT (0x8000);
9655 operands[0] = gen_rtx_REG (SImode,
9656 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9658 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9659 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9661 (define_insn "*negtf2_if"
9662 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9663 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9664 (clobber (reg:CC 17))]
9665 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9669 [(set (match_operand:TF 0 "register_operand" "")
9670 (neg:TF (match_operand:TF 1 "register_operand" "")))
9671 (clobber (reg:CC 17))]
9672 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9674 (neg:TF (match_dup 1)))]
9678 [(set (match_operand:TF 0 "register_operand" "")
9679 (neg:TF (match_operand:TF 1 "register_operand" "")))
9680 (clobber (reg:CC 17))]
9681 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9682 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9683 (clobber (reg:CC 17))])]
9684 "operands[1] = GEN_INT (0x8000);
9685 operands[0] = gen_rtx_REG (SImode,
9686 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9688 ;; Conditionize these after reload. If they matches before reload, we
9689 ;; lose the clobber and ability to use integer instructions.
9691 (define_insn "*negsf2_1"
9692 [(set (match_operand:SF 0 "register_operand" "=f")
9693 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9694 "TARGET_80387 && reload_completed"
9696 [(set_attr "type" "fsgn")
9697 (set_attr "mode" "SF")
9698 (set_attr "ppro_uops" "few")])
9700 (define_insn "*negdf2_1"
9701 [(set (match_operand:DF 0 "register_operand" "=f")
9702 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9703 "TARGET_80387 && reload_completed"
9705 [(set_attr "type" "fsgn")
9706 (set_attr "mode" "DF")
9707 (set_attr "ppro_uops" "few")])
9709 (define_insn "*negextendsfdf2"
9710 [(set (match_operand:DF 0 "register_operand" "=f")
9711 (neg:DF (float_extend:DF
9712 (match_operand:SF 1 "register_operand" "0"))))]
9715 [(set_attr "type" "fsgn")
9716 (set_attr "mode" "DF")
9717 (set_attr "ppro_uops" "few")])
9719 (define_insn "*negxf2_1"
9720 [(set (match_operand:XF 0 "register_operand" "=f")
9721 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9722 "TARGET_80387 && !TARGET_64BIT && reload_completed"
9724 [(set_attr "type" "fsgn")
9725 (set_attr "mode" "XF")
9726 (set_attr "ppro_uops" "few")])
9728 (define_insn "*negextenddfxf2"
9729 [(set (match_operand:XF 0 "register_operand" "=f")
9730 (neg:XF (float_extend:XF
9731 (match_operand:DF 1 "register_operand" "0"))))]
9732 "TARGET_80387 && !TARGET_64BIT"
9734 [(set_attr "type" "fsgn")
9735 (set_attr "mode" "XF")
9736 (set_attr "ppro_uops" "few")])
9738 (define_insn "*negextendsfxf2"
9739 [(set (match_operand:XF 0 "register_operand" "=f")
9740 (neg:XF (float_extend:XF
9741 (match_operand:SF 1 "register_operand" "0"))))]
9742 "TARGET_80387 && !TARGET_64BIT"
9744 [(set_attr "type" "fsgn")
9745 (set_attr "mode" "XF")
9746 (set_attr "ppro_uops" "few")])
9748 (define_insn "*negtf2_1"
9749 [(set (match_operand:TF 0 "register_operand" "=f")
9750 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9751 "TARGET_80387 && reload_completed"
9753 [(set_attr "type" "fsgn")
9754 (set_attr "mode" "XF")
9755 (set_attr "ppro_uops" "few")])
9757 (define_insn "*negextenddftf2"
9758 [(set (match_operand:TF 0 "register_operand" "=f")
9759 (neg:TF (float_extend:TF
9760 (match_operand:DF 1 "register_operand" "0"))))]
9763 [(set_attr "type" "fsgn")
9764 (set_attr "mode" "XF")
9765 (set_attr "ppro_uops" "few")])
9767 (define_insn "*negextendsftf2"
9768 [(set (match_operand:TF 0 "register_operand" "=f")
9769 (neg:TF (float_extend:TF
9770 (match_operand:SF 1 "register_operand" "0"))))]
9773 [(set_attr "type" "fsgn")
9774 (set_attr "mode" "XF")
9775 (set_attr "ppro_uops" "few")])
9777 ;; Absolute value instructions
9779 (define_expand "abssf2"
9780 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9781 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9782 (clobber (reg:CC 17))])]
9786 /* In case operand is in memory, we will not use SSE. */
9787 if (memory_operand (operands[0], VOIDmode)
9788 && rtx_equal_p (operands[0], operands[1]))
9789 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9792 /* Using SSE is tricky, since we need bitwise negation of -0
9794 rtx reg = gen_reg_rtx (SFmode);
9795 rtx dest = operands[0];
9797 operands[1] = force_reg (SFmode, operands[1]);
9798 operands[0] = force_reg (SFmode, operands[0]);
9799 emit_move_insn (reg,
9800 gen_lowpart (SFmode,
9801 GEN_INT (trunc_int_for_mode (0x80000000,
9803 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9804 if (dest != operands[0])
9805 emit_move_insn (dest, operands[0]);
9809 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9811 (define_insn "abssf2_memory"
9812 [(set (match_operand:SF 0 "memory_operand" "=m")
9813 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9814 (clobber (reg:CC 17))]
9815 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9818 (define_insn "abssf2_ifs"
9819 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9820 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9821 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9822 (clobber (reg:CC 17))]
9824 && (reload_in_progress || reload_completed
9825 || (register_operand (operands[0], VOIDmode)
9826 && register_operand (operands[1], VOIDmode)))"
9830 [(set (match_operand:SF 0 "memory_operand" "")
9831 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9832 (use (match_operand:SF 2 "" ""))
9833 (clobber (reg:CC 17))]
9835 [(parallel [(set (match_dup 0)
9836 (abs:SF (match_dup 1)))
9837 (clobber (reg:CC 17))])])
9840 [(set (match_operand:SF 0 "register_operand" "")
9841 (abs:SF (match_operand:SF 1 "register_operand" "")))
9842 (use (match_operand:SF 2 "" ""))
9843 (clobber (reg:CC 17))]
9844 "reload_completed && !SSE_REG_P (operands[0])"
9845 [(parallel [(set (match_dup 0)
9846 (abs:SF (match_dup 1)))
9847 (clobber (reg:CC 17))])])
9850 [(set (match_operand:SF 0 "register_operand" "")
9851 (abs:SF (match_operand:SF 1 "register_operand" "")))
9852 (use (match_operand:SF 2 "register_operand" ""))
9853 (clobber (reg:CC 17))]
9854 "reload_completed && SSE_REG_P (operands[0])"
9855 [(set (subreg:TI (match_dup 0) 0)
9856 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9857 (subreg:TI (match_dup 1) 0)))])
9859 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9860 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9862 (define_insn "*abssf2_if"
9863 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9864 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9865 (clobber (reg:CC 17))]
9866 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9870 [(set (match_operand:SF 0 "register_operand" "")
9871 (abs:SF (match_operand:SF 1 "register_operand" "")))
9872 (clobber (reg:CC 17))]
9873 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9875 (abs:SF (match_dup 1)))]
9879 [(set (match_operand:SF 0 "register_operand" "")
9880 (abs:SF (match_operand:SF 1 "register_operand" "")))
9881 (clobber (reg:CC 17))]
9882 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9883 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9884 (clobber (reg:CC 17))])]
9885 "operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
9886 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9889 [(set (match_operand 0 "memory_operand" "")
9890 (abs (match_operand 1 "memory_operand" "")))
9891 (clobber (reg:CC 17))]
9892 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9893 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9894 (clobber (reg:CC 17))])]
9896 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9898 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9901 operands[0] = adjust_address (operands[0], QImode, size - 1);
9902 operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
9905 (define_expand "absdf2"
9906 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9907 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9908 (clobber (reg:CC 17))])]
9912 /* In case operand is in memory, we will not use SSE. */
9913 if (memory_operand (operands[0], VOIDmode)
9914 && rtx_equal_p (operands[0], operands[1]))
9915 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9918 /* Using SSE is tricky, since we need bitwise negation of -0
9920 rtx reg = gen_reg_rtx (DFmode);
9921 #if HOST_BITS_PER_WIDE_INT >= 64
9922 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9925 rtx imm = immed_double_const (0, 0x80000000, DImode);
9927 rtx dest = operands[0];
9929 operands[1] = force_reg (DFmode, operands[1]);
9930 operands[0] = force_reg (DFmode, operands[0]);
9931 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9932 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9933 if (dest != operands[0])
9934 emit_move_insn (dest, operands[0]);
9938 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9940 (define_insn "absdf2_memory"
9941 [(set (match_operand:DF 0 "memory_operand" "=m")
9942 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9943 (clobber (reg:CC 17))]
9944 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9947 (define_insn "absdf2_ifs"
9948 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
9949 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9950 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
9951 (clobber (reg:CC 17))]
9952 "TARGET_SSE2 && !TARGET_64BIT
9953 && (reload_in_progress || reload_completed
9954 || (register_operand (operands[0], VOIDmode)
9955 && register_operand (operands[1], VOIDmode)))"
9958 (define_insn "*absdf2_ifs_rex64"
9959 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
9960 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
9961 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
9962 (clobber (reg:CC 17))]
9963 "TARGET_SSE2 && TARGET_64BIT
9964 && (reload_in_progress || reload_completed
9965 || (register_operand (operands[0], VOIDmode)
9966 && register_operand (operands[1], VOIDmode)))"
9970 [(set (match_operand:DF 0 "memory_operand" "")
9971 (abs:DF (match_operand:DF 1 "memory_operand" "")))
9972 (use (match_operand:DF 2 "" ""))
9973 (clobber (reg:CC 17))]
9975 [(parallel [(set (match_dup 0)
9976 (abs:DF (match_dup 1)))
9977 (clobber (reg:CC 17))])])
9980 [(set (match_operand:DF 0 "register_operand" "")
9981 (abs:DF (match_operand:DF 1 "register_operand" "")))
9982 (use (match_operand:DF 2 "" ""))
9983 (clobber (reg:CC 17))]
9984 "reload_completed && !SSE_REG_P (operands[0])"
9985 [(parallel [(set (match_dup 0)
9986 (abs:DF (match_dup 1)))
9987 (clobber (reg:CC 17))])])
9990 [(set (match_operand:DF 0 "register_operand" "")
9991 (abs:DF (match_operand:DF 1 "register_operand" "")))
9992 (use (match_operand:DF 2 "register_operand" ""))
9993 (clobber (reg:CC 17))]
9994 "reload_completed && SSE_REG_P (operands[0])"
9995 [(set (subreg:TI (match_dup 0) 0)
9996 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9997 (subreg:TI (match_dup 1) 0)))])
10000 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10001 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10003 (define_insn "*absdf2_if"
10004 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10005 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10006 (clobber (reg:CC 17))]
10007 "TARGET_80387 && !TARGET_64BIT
10008 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10011 ;; FIXME: We should to allow integer registers here. Problem is that
10012 ;; we need another scratch register to get constant from.
10013 ;; Forcing constant to mem if no register available in peep2 should be
10014 ;; safe even for PIC mode, because of RIP relative addressing.
10015 (define_insn "*absdf2_if_rex64"
10016 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10017 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10018 (clobber (reg:CC 17))]
10019 "TARGET_80387 && TARGET_64BIT
10020 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10024 [(set (match_operand:DF 0 "register_operand" "")
10025 (abs:DF (match_operand:DF 1 "register_operand" "")))
10026 (clobber (reg:CC 17))]
10027 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10028 [(set (match_dup 0)
10029 (abs:DF (match_dup 1)))]
10033 [(set (match_operand:DF 0 "register_operand" "")
10034 (abs:DF (match_operand:DF 1 "register_operand" "")))
10035 (clobber (reg:CC 17))]
10036 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
10038 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10039 (clobber (reg:CC 17))])]
10040 "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
10041 split_di (operands+0, 1, operands+2, operands+3);")
10043 (define_expand "absxf2"
10044 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10045 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10046 (clobber (reg:CC 17))])]
10047 "TARGET_80387 && !TARGET_64BIT"
10048 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10050 (define_expand "abstf2"
10051 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10052 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10053 (clobber (reg:CC 17))])]
10055 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10057 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10058 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10060 (define_insn "*absxf2_if"
10061 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10062 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10063 (clobber (reg:CC 17))]
10064 "TARGET_80387 && !TARGET_64BIT
10065 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10069 [(set (match_operand:XF 0 "register_operand" "")
10070 (abs:XF (match_operand:XF 1 "register_operand" "")))
10071 (clobber (reg:CC 17))]
10072 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10073 [(set (match_dup 0)
10074 (abs:XF (match_dup 1)))]
10078 [(set (match_operand:XF 0 "register_operand" "")
10079 (abs:XF (match_operand:XF 1 "register_operand" "")))
10080 (clobber (reg:CC 17))]
10081 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10082 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10083 (clobber (reg:CC 17))])]
10084 "operands[1] = GEN_INT (~0x8000);
10085 operands[0] = gen_rtx_REG (SImode,
10086 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10088 (define_insn "*abstf2_if"
10089 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10090 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10091 (clobber (reg:CC 17))]
10092 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10096 [(set (match_operand:TF 0 "register_operand" "")
10097 (abs:TF (match_operand:TF 1 "register_operand" "")))
10098 (clobber (reg:CC 17))]
10099 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10100 [(set (match_dup 0)
10101 (abs:TF (match_dup 1)))]
10105 [(set (match_operand:TF 0 "register_operand" "")
10106 (abs:TF (match_operand:TF 1 "register_operand" "")))
10107 (clobber (reg:CC 17))]
10108 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10109 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10110 (clobber (reg:CC 17))])]
10111 "operands[1] = GEN_INT (~0x8000);
10112 operands[0] = gen_rtx_REG (SImode,
10113 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10115 (define_insn "*abssf2_1"
10116 [(set (match_operand:SF 0 "register_operand" "=f")
10117 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10118 "TARGET_80387 && reload_completed"
10120 [(set_attr "type" "fsgn")
10121 (set_attr "mode" "SF")])
10123 (define_insn "*absdf2_1"
10124 [(set (match_operand:DF 0 "register_operand" "=f")
10125 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10126 "TARGET_80387 && reload_completed"
10128 [(set_attr "type" "fsgn")
10129 (set_attr "mode" "DF")])
10131 (define_insn "*absextendsfdf2"
10132 [(set (match_operand:DF 0 "register_operand" "=f")
10133 (abs:DF (float_extend:DF
10134 (match_operand:SF 1 "register_operand" "0"))))]
10137 [(set_attr "type" "fsgn")
10138 (set_attr "mode" "DF")])
10140 (define_insn "*absxf2_1"
10141 [(set (match_operand:XF 0 "register_operand" "=f")
10142 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10143 "TARGET_80387 && !TARGET_64BIT && reload_completed"
10145 [(set_attr "type" "fsgn")
10146 (set_attr "mode" "DF")])
10148 (define_insn "*absextenddfxf2"
10149 [(set (match_operand:XF 0 "register_operand" "=f")
10150 (abs:XF (float_extend:XF
10151 (match_operand:DF 1 "register_operand" "0"))))]
10152 "TARGET_80387 && !TARGET_64BIT"
10154 [(set_attr "type" "fsgn")
10155 (set_attr "mode" "XF")])
10157 (define_insn "*absextendsfxf2"
10158 [(set (match_operand:XF 0 "register_operand" "=f")
10159 (abs:XF (float_extend:XF
10160 (match_operand:SF 1 "register_operand" "0"))))]
10161 "TARGET_80387 && !TARGET_64BIT"
10163 [(set_attr "type" "fsgn")
10164 (set_attr "mode" "XF")])
10166 (define_insn "*abstf2_1"
10167 [(set (match_operand:TF 0 "register_operand" "=f")
10168 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10169 "TARGET_80387 && reload_completed"
10171 [(set_attr "type" "fsgn")
10172 (set_attr "mode" "DF")])
10174 (define_insn "*absextenddftf2"
10175 [(set (match_operand:TF 0 "register_operand" "=f")
10176 (abs:TF (float_extend:TF
10177 (match_operand:DF 1 "register_operand" "0"))))]
10180 [(set_attr "type" "fsgn")
10181 (set_attr "mode" "XF")])
10183 (define_insn "*absextendsftf2"
10184 [(set (match_operand:TF 0 "register_operand" "=f")
10185 (abs:TF (float_extend:TF
10186 (match_operand:SF 1 "register_operand" "0"))))]
10189 [(set_attr "type" "fsgn")
10190 (set_attr "mode" "XF")])
10192 ;; One complement instructions
10194 (define_expand "one_cmpldi2"
10195 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10196 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10198 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10200 (define_insn "*one_cmpldi2_1_rex64"
10201 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10202 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10203 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10205 [(set_attr "type" "negnot")
10206 (set_attr "mode" "DI")])
10208 (define_insn "*one_cmpldi2_2_rex64"
10210 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10212 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10213 (not:DI (match_dup 1)))]
10214 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10215 && ix86_unary_operator_ok (NOT, DImode, operands)"
10217 [(set_attr "type" "alu1")
10218 (set_attr "mode" "DI")])
10222 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10224 (set (match_operand:DI 0 "nonimmediate_operand" "")
10225 (not:DI (match_dup 1)))]
10226 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10227 [(parallel [(set (reg:CCNO 17)
10228 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10231 (xor:DI (match_dup 1) (const_int -1)))])]
10234 (define_expand "one_cmplsi2"
10235 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10236 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10238 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10240 (define_insn "*one_cmplsi2_1"
10241 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10242 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10243 "ix86_unary_operator_ok (NOT, SImode, operands)"
10245 [(set_attr "type" "negnot")
10246 (set_attr "mode" "SI")])
10248 ;; ??? Currently never generated - xor is used instead.
10249 (define_insn "*one_cmplsi2_1_zext"
10250 [(set (match_operand:DI 0 "register_operand" "=r")
10251 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10252 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10254 [(set_attr "type" "negnot")
10255 (set_attr "mode" "SI")])
10257 (define_insn "*one_cmplsi2_2"
10259 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10261 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10262 (not:SI (match_dup 1)))]
10263 "ix86_match_ccmode (insn, CCNOmode)
10264 && ix86_unary_operator_ok (NOT, SImode, operands)"
10266 [(set_attr "type" "alu1")
10267 (set_attr "mode" "SI")])
10271 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10273 (set (match_operand:SI 0 "nonimmediate_operand" "")
10274 (not:SI (match_dup 1)))]
10275 "ix86_match_ccmode (insn, CCNOmode)"
10276 [(parallel [(set (reg:CCNO 17)
10277 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10280 (xor:SI (match_dup 1) (const_int -1)))])]
10283 ;; ??? Currently never generated - xor is used instead.
10284 (define_insn "*one_cmplsi2_2_zext"
10286 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10288 (set (match_operand:DI 0 "register_operand" "=r")
10289 (zero_extend:DI (not:SI (match_dup 1))))]
10290 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10291 && ix86_unary_operator_ok (NOT, SImode, operands)"
10293 [(set_attr "type" "alu1")
10294 (set_attr "mode" "SI")])
10298 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10300 (set (match_operand:DI 0 "register_operand" "")
10301 (zero_extend:DI (not:SI (match_dup 1))))]
10302 "ix86_match_ccmode (insn, CCNOmode)"
10303 [(parallel [(set (reg:CCNO 17)
10304 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10307 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10310 (define_expand "one_cmplhi2"
10311 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10312 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10313 "TARGET_HIMODE_MATH"
10314 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10316 (define_insn "*one_cmplhi2_1"
10317 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10318 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10319 "ix86_unary_operator_ok (NOT, HImode, operands)"
10321 [(set_attr "type" "negnot")
10322 (set_attr "mode" "HI")])
10324 (define_insn "*one_cmplhi2_2"
10326 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10328 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10329 (not:HI (match_dup 1)))]
10330 "ix86_match_ccmode (insn, CCNOmode)
10331 && ix86_unary_operator_ok (NEG, HImode, operands)"
10333 [(set_attr "type" "alu1")
10334 (set_attr "mode" "HI")])
10338 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10340 (set (match_operand:HI 0 "nonimmediate_operand" "")
10341 (not:HI (match_dup 1)))]
10342 "ix86_match_ccmode (insn, CCNOmode)"
10343 [(parallel [(set (reg:CCNO 17)
10344 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10347 (xor:HI (match_dup 1) (const_int -1)))])]
10350 ;; %%% Potential partial reg stall on alternative 1. What to do?
10351 (define_expand "one_cmplqi2"
10352 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10353 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10354 "TARGET_QIMODE_MATH"
10355 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10357 (define_insn "*one_cmplqi2_1"
10358 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10359 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10360 "ix86_unary_operator_ok (NOT, QImode, operands)"
10364 [(set_attr "type" "negnot")
10365 (set_attr "mode" "QI,SI")])
10367 (define_insn "*one_cmplqi2_2"
10369 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10371 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10372 (not:QI (match_dup 1)))]
10373 "ix86_match_ccmode (insn, CCNOmode)
10374 && ix86_unary_operator_ok (NOT, QImode, operands)"
10376 [(set_attr "type" "alu1")
10377 (set_attr "mode" "QI")])
10381 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10383 (set (match_operand:QI 0 "nonimmediate_operand" "")
10384 (not:QI (match_dup 1)))]
10385 "ix86_match_ccmode (insn, CCNOmode)"
10386 [(parallel [(set (reg:CCNO 17)
10387 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10390 (xor:QI (match_dup 1) (const_int -1)))])]
10393 ;; Arithmetic shift instructions
10395 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10396 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10397 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10398 ;; from the assembler input.
10400 ;; This instruction shifts the target reg/mem as usual, but instead of
10401 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10402 ;; is a left shift double, bits are taken from the high order bits of
10403 ;; reg, else if the insn is a shift right double, bits are taken from the
10404 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10405 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10407 ;; Since sh[lr]d does not change the `reg' operand, that is done
10408 ;; separately, making all shifts emit pairs of shift double and normal
10409 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10410 ;; support a 63 bit shift, each shift where the count is in a reg expands
10411 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10413 ;; If the shift count is a constant, we need never emit more than one
10414 ;; shift pair, instead using moves and sign extension for counts greater
10417 (define_expand "ashldi3"
10418 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10419 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10420 (match_operand:QI 2 "nonmemory_operand" "")))
10421 (clobber (reg:CC 17))])]
10424 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10426 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10429 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10433 (define_insn "*ashldi3_1_rex64"
10434 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10435 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10436 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10437 (clobber (reg:CC 17))]
10438 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10440 switch (get_attr_type (insn))
10443 if (operands[2] != const1_rtx)
10445 if (!rtx_equal_p (operands[0], operands[1]))
10447 return "add{q}\t{%0, %0|%0, %0}";
10450 if (GET_CODE (operands[2]) != CONST_INT
10451 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10453 operands[1] = gen_rtx_MULT (DImode, operands[1],
10454 GEN_INT (1 << INTVAL (operands[2])));
10455 return "lea{q}\t{%a1, %0|%0, %a1}";
10458 if (REG_P (operands[2]))
10459 return "sal{q}\t{%b2, %0|%0, %b2}";
10460 else if (GET_CODE (operands[2]) == CONST_INT
10461 && INTVAL (operands[2]) == 1
10462 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10463 return "sal{q}\t%0";
10465 return "sal{q}\t{%2, %0|%0, %2}";
10468 [(set (attr "type")
10469 (cond [(eq_attr "alternative" "1")
10470 (const_string "lea")
10471 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10473 (match_operand 0 "register_operand" ""))
10474 (match_operand 2 "const1_operand" ""))
10475 (const_string "alu")
10477 (const_string "ishift")))
10478 (set_attr "mode" "DI")])
10480 ;; Convert lea to the lea pattern to avoid flags dependency.
10482 [(set (match_operand:DI 0 "register_operand" "")
10483 (ashift:DI (match_operand:DI 1 "register_operand" "")
10484 (match_operand:QI 2 "immediate_operand" "")))
10485 (clobber (reg:CC 17))]
10488 && true_regnum (operands[0]) != true_regnum (operands[1])"
10489 [(set (match_dup 0)
10490 (mult:DI (match_dup 1)
10492 "operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10495 ;; This pattern can't accept a variable shift count, since shifts by
10496 ;; zero don't affect the flags. We assume that shifts by constant
10497 ;; zero are optimized away.
10498 (define_insn "*ashldi3_cmp_rex64"
10501 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10502 (match_operand:QI 2 "immediate_operand" "e"))
10504 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10505 (ashift:DI (match_dup 1) (match_dup 2)))]
10506 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10507 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10509 switch (get_attr_type (insn))
10512 if (operands[2] != const1_rtx)
10514 return "add{q}\t{%0, %0|%0, %0}";
10517 if (REG_P (operands[2]))
10518 return "sal{q}\t{%b2, %0|%0, %b2}";
10519 else if (GET_CODE (operands[2]) == CONST_INT
10520 && INTVAL (operands[2]) == 1
10521 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10522 return "sal{q}\t%0";
10524 return "sal{q}\t{%2, %0|%0, %2}";
10527 [(set (attr "type")
10528 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10530 (match_operand 0 "register_operand" ""))
10531 (match_operand 2 "const1_operand" ""))
10532 (const_string "alu")
10534 (const_string "ishift")))
10535 (set_attr "mode" "DI")])
10537 (define_insn "ashldi3_1"
10538 [(set (match_operand:DI 0 "register_operand" "=r")
10539 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10540 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10541 (clobber (match_scratch:SI 3 "=&r"))
10542 (clobber (reg:CC 17))]
10543 "!TARGET_64BIT && TARGET_CMOVE"
10545 [(set_attr "type" "multi")])
10547 (define_insn "*ashldi3_2"
10548 [(set (match_operand:DI 0 "register_operand" "=r")
10549 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10550 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10551 (clobber (reg:CC 17))]
10554 [(set_attr "type" "multi")])
10557 [(set (match_operand:DI 0 "register_operand" "")
10558 (ashift:DI (match_operand:DI 1 "register_operand" "")
10559 (match_operand:QI 2 "nonmemory_operand" "")))
10560 (clobber (match_scratch:SI 3 ""))
10561 (clobber (reg:CC 17))]
10562 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10564 "ix86_split_ashldi (operands, operands[3]); DONE;")
10567 [(set (match_operand:DI 0 "register_operand" "")
10568 (ashift:DI (match_operand:DI 1 "register_operand" "")
10569 (match_operand:QI 2 "nonmemory_operand" "")))
10570 (clobber (reg:CC 17))]
10571 "!TARGET_64BIT && reload_completed"
10573 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10575 (define_insn "x86_shld_1"
10576 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10577 (ior:SI (ashift:SI (match_dup 0)
10578 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10579 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10580 (minus:QI (const_int 32) (match_dup 2)))))
10581 (clobber (reg:CC 17))]
10584 shld{l}\t{%2, %1, %0|%0, %1, %2}
10585 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10586 [(set_attr "type" "ishift")
10587 (set_attr "prefix_0f" "1")
10588 (set_attr "mode" "SI")
10589 (set_attr "pent_pair" "np")
10590 (set_attr "athlon_decode" "vector")
10591 (set_attr "ppro_uops" "few")])
10593 (define_expand "x86_shift_adj_1"
10595 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10598 (set (match_operand:SI 0 "register_operand" "")
10599 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10600 (match_operand:SI 1 "register_operand" "")
10603 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10604 (match_operand:SI 3 "register_operand" "r")
10609 (define_expand "x86_shift_adj_2"
10610 [(use (match_operand:SI 0 "register_operand" ""))
10611 (use (match_operand:SI 1 "register_operand" ""))
10612 (use (match_operand:QI 2 "register_operand" ""))]
10615 rtx label = gen_label_rtx ();
10618 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10620 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10621 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10622 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10623 gen_rtx_LABEL_REF (VOIDmode, label),
10625 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10626 JUMP_LABEL (tmp) = label;
10628 emit_move_insn (operands[0], operands[1]);
10629 emit_move_insn (operands[1], const0_rtx);
10631 emit_label (label);
10632 LABEL_NUSES (label) = 1;
10637 (define_expand "ashlsi3"
10638 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10639 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10640 (match_operand:QI 2 "nonmemory_operand" "")))
10641 (clobber (reg:CC 17))]
10643 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10645 (define_insn "*ashlsi3_1"
10646 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10647 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10648 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10649 (clobber (reg:CC 17))]
10650 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10652 switch (get_attr_type (insn))
10655 if (operands[2] != const1_rtx)
10657 if (!rtx_equal_p (operands[0], operands[1]))
10659 return "add{l}\t{%0, %0|%0, %0}";
10665 if (REG_P (operands[2]))
10666 return "sal{l}\t{%b2, %0|%0, %b2}";
10667 else if (GET_CODE (operands[2]) == CONST_INT
10668 && INTVAL (operands[2]) == 1
10669 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10670 return "sal{l}\t%0";
10672 return "sal{l}\t{%2, %0|%0, %2}";
10675 [(set (attr "type")
10676 (cond [(eq_attr "alternative" "1")
10677 (const_string "lea")
10678 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10680 (match_operand 0 "register_operand" ""))
10681 (match_operand 2 "const1_operand" ""))
10682 (const_string "alu")
10684 (const_string "ishift")))
10685 (set_attr "mode" "SI")])
10687 ;; Convert lea to the lea pattern to avoid flags dependency.
10689 [(set (match_operand 0 "register_operand" "")
10690 (ashift (match_operand 1 "register_operand" "")
10691 (match_operand:QI 2 "const_int_operand" "")))
10692 (clobber (reg:CC 17))]
10694 && true_regnum (operands[0]) != true_regnum (operands[1])"
10698 operands[0] = gen_lowpart (SImode, operands[0]);
10699 operands[1] = gen_lowpart (Pmode, operands[1]);
10700 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10702 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10703 if (Pmode != SImode)
10704 pat = gen_rtx_SUBREG (SImode, pat, 0);
10705 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10709 (define_insn "*ashlsi3_1_zext"
10710 [(set (match_operand:DI 0 "register_operand" "=r,r")
10711 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10712 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10713 (clobber (reg:CC 17))]
10714 "ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
10716 switch (get_attr_type (insn))
10719 if (operands[2] != const1_rtx)
10721 return "add{l}\t{%k0, %k0|%k0, %k0}";
10727 if (REG_P (operands[2]))
10728 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10729 else if (GET_CODE (operands[2]) == CONST_INT
10730 && INTVAL (operands[2]) == 1
10731 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10732 return "sal{l}\t%k0";
10734 return "sal{l}\t{%2, %k0|%k0, %2}";
10737 [(set (attr "type")
10738 (cond [(eq_attr "alternative" "1")
10739 (const_string "lea")
10740 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10742 (match_operand 2 "const1_operand" ""))
10743 (const_string "alu")
10745 (const_string "ishift")))
10746 (set_attr "mode" "SI")])
10748 ;; Convert lea to the lea pattern to avoid flags dependency.
10750 [(set (match_operand:DI 0 "register_operand" "")
10751 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10752 (match_operand:QI 2 "const_int_operand" ""))))
10753 (clobber (reg:CC 17))]
10755 && true_regnum (operands[0]) != true_regnum (operands[1])"
10756 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10758 operands[1] = gen_lowpart (Pmode, operands[1]);
10759 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10763 ;; This pattern can't accept a variable shift count, since shifts by
10764 ;; zero don't affect the flags. We assume that shifts by constant
10765 ;; zero are optimized away.
10766 (define_insn "*ashlsi3_cmp"
10769 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10770 (match_operand:QI 2 "immediate_operand" "I"))
10772 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10773 (ashift:SI (match_dup 1) (match_dup 2)))]
10774 "ix86_match_ccmode (insn, CCGOCmode)
10775 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10777 switch (get_attr_type (insn))
10780 if (operands[2] != const1_rtx)
10782 return "add{l}\t{%0, %0|%0, %0}";
10785 if (REG_P (operands[2]))
10786 return "sal{l}\t{%b2, %0|%0, %b2}";
10787 else if (GET_CODE (operands[2]) == CONST_INT
10788 && INTVAL (operands[2]) == 1
10789 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10790 return "sal{l}\t%0";
10792 return "sal{l}\t{%2, %0|%0, %2}";
10795 [(set (attr "type")
10796 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10798 (match_operand 0 "register_operand" ""))
10799 (match_operand 2 "const1_operand" ""))
10800 (const_string "alu")
10802 (const_string "ishift")))
10803 (set_attr "mode" "SI")])
10805 (define_insn "*ashlsi3_cmp_zext"
10808 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10809 (match_operand:QI 2 "immediate_operand" "I"))
10811 (set (match_operand:DI 0 "register_operand" "=r")
10812 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10813 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10814 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10816 switch (get_attr_type (insn))
10819 if (operands[2] != const1_rtx)
10821 return "add{l}\t{%k0, %k0|%k0, %k0}";
10824 if (REG_P (operands[2]))
10825 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10826 else if (GET_CODE (operands[2]) == CONST_INT
10827 && INTVAL (operands[2]) == 1
10828 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10829 return "sal{l}\t%k0";
10831 return "sal{l}\t{%2, %k0|%k0, %2}";
10834 [(set (attr "type")
10835 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10837 (match_operand 2 "const1_operand" ""))
10838 (const_string "alu")
10840 (const_string "ishift")))
10841 (set_attr "mode" "SI")])
10843 (define_expand "ashlhi3"
10844 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10845 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10846 (match_operand:QI 2 "nonmemory_operand" "")))
10847 (clobber (reg:CC 17))]
10848 "TARGET_HIMODE_MATH"
10849 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10851 (define_insn "*ashlhi3_1_lea"
10852 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10853 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10854 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10855 (clobber (reg:CC 17))]
10856 "!TARGET_PARTIAL_REG_STALL
10857 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10859 switch (get_attr_type (insn))
10864 if (operands[2] != const1_rtx)
10866 return "add{w}\t{%0, %0|%0, %0}";
10869 if (REG_P (operands[2]))
10870 return "sal{w}\t{%b2, %0|%0, %b2}";
10871 else if (GET_CODE (operands[2]) == CONST_INT
10872 && INTVAL (operands[2]) == 1
10873 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10874 return "sal{w}\t%0";
10876 return "sal{w}\t{%2, %0|%0, %2}";
10879 [(set (attr "type")
10880 (cond [(eq_attr "alternative" "1")
10881 (const_string "lea")
10882 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10884 (match_operand 0 "register_operand" ""))
10885 (match_operand 2 "const1_operand" ""))
10886 (const_string "alu")
10888 (const_string "ishift")))
10889 (set_attr "mode" "HI,SI")])
10891 (define_insn "*ashlhi3_1"
10892 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10893 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10894 (match_operand:QI 2 "nonmemory_operand" "cI")))
10895 (clobber (reg:CC 17))]
10896 "TARGET_PARTIAL_REG_STALL
10897 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10899 switch (get_attr_type (insn))
10902 if (operands[2] != const1_rtx)
10904 return "add{w}\t{%0, %0|%0, %0}";
10907 if (REG_P (operands[2]))
10908 return "sal{w}\t{%b2, %0|%0, %b2}";
10909 else if (GET_CODE (operands[2]) == CONST_INT
10910 && INTVAL (operands[2]) == 1
10911 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10912 return "sal{w}\t%0";
10914 return "sal{w}\t{%2, %0|%0, %2}";
10917 [(set (attr "type")
10918 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10920 (match_operand 0 "register_operand" ""))
10921 (match_operand 2 "const1_operand" ""))
10922 (const_string "alu")
10924 (const_string "ishift")))
10925 (set_attr "mode" "HI")])
10927 ;; This pattern can't accept a variable shift count, since shifts by
10928 ;; zero don't affect the flags. We assume that shifts by constant
10929 ;; zero are optimized away.
10930 (define_insn "*ashlhi3_cmp"
10933 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10934 (match_operand:QI 2 "immediate_operand" "I"))
10936 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10937 (ashift:HI (match_dup 1) (match_dup 2)))]
10938 "ix86_match_ccmode (insn, CCGOCmode)
10939 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10941 switch (get_attr_type (insn))
10944 if (operands[2] != const1_rtx)
10946 return "add{w}\t{%0, %0|%0, %0}";
10949 if (REG_P (operands[2]))
10950 return "sal{w}\t{%b2, %0|%0, %b2}";
10951 else if (GET_CODE (operands[2]) == CONST_INT
10952 && INTVAL (operands[2]) == 1
10953 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10954 return "sal{w}\t%0";
10956 return "sal{w}\t{%2, %0|%0, %2}";
10959 [(set (attr "type")
10960 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10962 (match_operand 0 "register_operand" ""))
10963 (match_operand 2 "const1_operand" ""))
10964 (const_string "alu")
10966 (const_string "ishift")))
10967 (set_attr "mode" "HI")])
10969 (define_expand "ashlqi3"
10970 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10971 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10972 (match_operand:QI 2 "nonmemory_operand" "")))
10973 (clobber (reg:CC 17))]
10974 "TARGET_QIMODE_MATH"
10975 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10977 ;; %%% Potential partial reg stall on alternative 2. What to do?
10979 (define_insn "*ashlqi3_1_lea"
10980 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10981 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
10982 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10983 (clobber (reg:CC 17))]
10984 "!TARGET_PARTIAL_REG_STALL
10985 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10987 switch (get_attr_type (insn))
10992 if (operands[2] != const1_rtx)
10994 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10995 return "add{l}\t{%k0, %k0|%k0, %k0}";
10997 return "add{b}\t{%0, %0|%0, %0}";
11000 if (REG_P (operands[2]))
11002 if (get_attr_mode (insn) == MODE_SI)
11003 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11005 return "sal{b}\t{%b2, %0|%0, %b2}";
11007 else if (GET_CODE (operands[2]) == CONST_INT
11008 && INTVAL (operands[2]) == 1
11009 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11011 if (get_attr_mode (insn) == MODE_SI)
11012 return "sal{l}\t%0";
11014 return "sal{b}\t%0";
11018 if (get_attr_mode (insn) == MODE_SI)
11019 return "sal{l}\t{%2, %k0|%k0, %2}";
11021 return "sal{b}\t{%2, %0|%0, %2}";
11025 [(set (attr "type")
11026 (cond [(eq_attr "alternative" "2")
11027 (const_string "lea")
11028 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11030 (match_operand 0 "register_operand" ""))
11031 (match_operand 2 "const1_operand" ""))
11032 (const_string "alu")
11034 (const_string "ishift")))
11035 (set_attr "mode" "QI,SI,SI")])
11037 (define_insn "*ashlqi3_1"
11038 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11039 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11040 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11041 (clobber (reg:CC 17))]
11042 "TARGET_PARTIAL_REG_STALL
11043 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11045 switch (get_attr_type (insn))
11048 if (operands[2] != const1_rtx)
11050 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11051 return "add{l}\t{%k0, %k0|%k0, %k0}";
11053 return "add{b}\t{%0, %0|%0, %0}";
11056 if (REG_P (operands[2]))
11058 if (get_attr_mode (insn) == MODE_SI)
11059 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11061 return "sal{b}\t{%b2, %0|%0, %b2}";
11063 else if (GET_CODE (operands[2]) == CONST_INT
11064 && INTVAL (operands[2]) == 1
11065 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11067 if (get_attr_mode (insn) == MODE_SI)
11068 return "sal{l}\t%0";
11070 return "sal{b}\t%0";
11074 if (get_attr_mode (insn) == MODE_SI)
11075 return "sal{l}\t{%2, %k0|%k0, %2}";
11077 return "sal{b}\t{%2, %0|%0, %2}";
11081 [(set (attr "type")
11082 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11084 (match_operand 0 "register_operand" ""))
11085 (match_operand 2 "const1_operand" ""))
11086 (const_string "alu")
11088 (const_string "ishift")))
11089 (set_attr "mode" "QI,SI")])
11091 ;; This pattern can't accept a variable shift count, since shifts by
11092 ;; zero don't affect the flags. We assume that shifts by constant
11093 ;; zero are optimized away.
11094 (define_insn "*ashlqi3_cmp"
11097 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11098 (match_operand:QI 2 "immediate_operand" "I"))
11100 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11101 (ashift:QI (match_dup 1) (match_dup 2)))]
11102 "ix86_match_ccmode (insn, CCGOCmode)
11103 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11105 switch (get_attr_type (insn))
11108 if (operands[2] != const1_rtx)
11110 return "add{b}\t{%0, %0|%0, %0}";
11113 if (REG_P (operands[2]))
11114 return "sal{b}\t{%b2, %0|%0, %b2}";
11115 else if (GET_CODE (operands[2]) == CONST_INT
11116 && INTVAL (operands[2]) == 1
11117 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11118 return "sal{b}\t%0";
11120 return "sal{b}\t{%2, %0|%0, %2}";
11123 [(set (attr "type")
11124 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11126 (match_operand 0 "register_operand" ""))
11127 (match_operand 2 "const1_operand" ""))
11128 (const_string "alu")
11130 (const_string "ishift")))
11131 (set_attr "mode" "QI")])
11133 ;; See comment above `ashldi3' about how this works.
11135 (define_expand "ashrdi3"
11136 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11137 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11138 (match_operand:QI 2 "nonmemory_operand" "")))
11139 (clobber (reg:CC 17))])]
11142 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11144 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11147 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11151 (define_insn "ashrdi3_63_rex64"
11152 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11153 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11154 (match_operand:DI 2 "const_int_operand" "i,i")))
11155 (clobber (reg:CC 17))]
11156 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11157 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11160 sar{q}\t{%2, %0|%0, %2}"
11161 [(set_attr "type" "imovx,ishift")
11162 (set_attr "prefix_0f" "0,*")
11163 (set_attr "length_immediate" "0,*")
11164 (set_attr "modrm" "0,1")
11165 (set_attr "mode" "DI")])
11167 (define_insn "*ashrdi3_1_one_bit_rex64"
11168 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11169 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11170 (match_operand:QI 2 "const_int_1_operand" "")))
11171 (clobber (reg:CC 17))]
11172 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11173 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11175 [(set_attr "type" "ishift")
11176 (set (attr "length")
11177 (if_then_else (match_operand:DI 0 "register_operand" "")
11179 (const_string "*")))])
11181 (define_insn "*ashrdi3_1_rex64"
11182 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11183 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11184 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11185 (clobber (reg:CC 17))]
11186 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11188 sar{q}\t{%2, %0|%0, %2}
11189 sar{q}\t{%b2, %0|%0, %b2}"
11190 [(set_attr "type" "ishift")
11191 (set_attr "mode" "DI")])
11193 ;; This pattern can't accept a variable shift count, since shifts by
11194 ;; zero don't affect the flags. We assume that shifts by constant
11195 ;; zero are optimized away.
11196 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11199 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11200 (match_operand:QI 2 "const_int_1_operand" ""))
11202 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11203 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11204 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11205 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11206 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11208 [(set_attr "type" "ishift")
11209 (set (attr "length")
11210 (if_then_else (match_operand:DI 0 "register_operand" "")
11212 (const_string "*")))])
11214 ;; This pattern can't accept a variable shift count, since shifts by
11215 ;; zero don't affect the flags. We assume that shifts by constant
11216 ;; zero are optimized away.
11217 (define_insn "*ashrdi3_cmp_rex64"
11220 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11221 (match_operand:QI 2 "const_int_operand" "n"))
11223 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11224 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11225 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11226 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11227 "sar{q}\t{%2, %0|%0, %2}"
11228 [(set_attr "type" "ishift")
11229 (set_attr "mode" "DI")])
11232 (define_insn "ashrdi3_1"
11233 [(set (match_operand:DI 0 "register_operand" "=r")
11234 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11235 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11236 (clobber (match_scratch:SI 3 "=&r"))
11237 (clobber (reg:CC 17))]
11238 "!TARGET_64BIT && TARGET_CMOVE"
11240 [(set_attr "type" "multi")])
11242 (define_insn "*ashrdi3_2"
11243 [(set (match_operand:DI 0 "register_operand" "=r")
11244 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11245 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11246 (clobber (reg:CC 17))]
11249 [(set_attr "type" "multi")])
11252 [(set (match_operand:DI 0 "register_operand" "")
11253 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11254 (match_operand:QI 2 "nonmemory_operand" "")))
11255 (clobber (match_scratch:SI 3 ""))
11256 (clobber (reg:CC 17))]
11257 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11259 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11262 [(set (match_operand:DI 0 "register_operand" "")
11263 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11264 (match_operand:QI 2 "nonmemory_operand" "")))
11265 (clobber (reg:CC 17))]
11266 "!TARGET_64BIT && reload_completed"
11268 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11270 (define_insn "x86_shrd_1"
11271 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11272 (ior:SI (ashiftrt:SI (match_dup 0)
11273 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11274 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11275 (minus:QI (const_int 32) (match_dup 2)))))
11276 (clobber (reg:CC 17))]
11279 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11280 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11281 [(set_attr "type" "ishift")
11282 (set_attr "prefix_0f" "1")
11283 (set_attr "pent_pair" "np")
11284 (set_attr "ppro_uops" "few")
11285 (set_attr "mode" "SI")])
11287 (define_expand "x86_shift_adj_3"
11288 [(use (match_operand:SI 0 "register_operand" ""))
11289 (use (match_operand:SI 1 "register_operand" ""))
11290 (use (match_operand:QI 2 "register_operand" ""))]
11293 rtx label = gen_label_rtx ();
11296 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11298 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11299 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11300 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11301 gen_rtx_LABEL_REF (VOIDmode, label),
11303 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11304 JUMP_LABEL (tmp) = label;
11306 emit_move_insn (operands[0], operands[1]);
11307 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11309 emit_label (label);
11310 LABEL_NUSES (label) = 1;
11315 (define_insn "ashrsi3_31"
11316 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11317 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11318 (match_operand:SI 2 "const_int_operand" "i,i")))
11319 (clobber (reg:CC 17))]
11320 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11321 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11324 sar{l}\t{%2, %0|%0, %2}"
11325 [(set_attr "type" "imovx,ishift")
11326 (set_attr "prefix_0f" "0,*")
11327 (set_attr "length_immediate" "0,*")
11328 (set_attr "modrm" "0,1")
11329 (set_attr "mode" "SI")])
11331 (define_insn "*ashrsi3_31_zext"
11332 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11333 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11334 (match_operand:SI 2 "const_int_operand" "i,i"))))
11335 (clobber (reg:CC 17))]
11336 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11337 && TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11340 sar{l}\t{%2, %k0|%k0, %2}"
11341 [(set_attr "type" "imovx,ishift")
11342 (set_attr "prefix_0f" "0,*")
11343 (set_attr "length_immediate" "0,*")
11344 (set_attr "modrm" "0,1")
11345 (set_attr "mode" "SI")])
11347 (define_expand "ashrsi3"
11348 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11349 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11350 (match_operand:QI 2 "nonmemory_operand" "")))
11351 (clobber (reg:CC 17))]
11353 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11355 (define_insn "*ashrsi3_1_one_bit"
11356 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11357 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11358 (match_operand:QI 2 "const_int_1_operand" "")))
11359 (clobber (reg:CC 17))]
11360 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11361 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11363 [(set_attr "type" "ishift")
11364 (set (attr "length")
11365 (if_then_else (match_operand:SI 0 "register_operand" "")
11367 (const_string "*")))])
11369 (define_insn "*ashrsi3_1_one_bit_zext"
11370 [(set (match_operand:DI 0 "register_operand" "=r")
11371 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11372 (match_operand:QI 2 "const_int_1_operand" ""))))
11373 (clobber (reg:CC 17))]
11374 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11375 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11377 [(set_attr "type" "ishift")
11378 (set_attr "length" "2")])
11380 (define_insn "*ashrsi3_1"
11381 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11382 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11383 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11384 (clobber (reg:CC 17))]
11385 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11387 sar{l}\t{%2, %0|%0, %2}
11388 sar{l}\t{%b2, %0|%0, %b2}"
11389 [(set_attr "type" "ishift")
11390 (set_attr "mode" "SI")])
11392 (define_insn "*ashrsi3_1_zext"
11393 [(set (match_operand:DI 0 "register_operand" "=r,r")
11394 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11395 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11396 (clobber (reg:CC 17))]
11397 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11399 sar{l}\t{%2, %k0|%k0, %2}
11400 sar{l}\t{%b2, %k0|%k0, %b2}"
11401 [(set_attr "type" "ishift")
11402 (set_attr "mode" "SI")])
11404 ;; This pattern can't accept a variable shift count, since shifts by
11405 ;; zero don't affect the flags. We assume that shifts by constant
11406 ;; zero are optimized away.
11407 (define_insn "*ashrsi3_one_bit_cmp"
11410 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11411 (match_operand:QI 2 "const_int_1_operand" ""))
11413 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11414 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11415 "ix86_match_ccmode (insn, CCGOCmode)
11416 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11417 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11419 [(set_attr "type" "ishift")
11420 (set (attr "length")
11421 (if_then_else (match_operand:SI 0 "register_operand" "")
11423 (const_string "*")))])
11425 (define_insn "*ashrsi3_one_bit_cmp_zext"
11428 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11429 (match_operand:QI 2 "const_int_1_operand" ""))
11431 (set (match_operand:DI 0 "register_operand" "=r")
11432 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11433 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11434 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11435 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11437 [(set_attr "type" "ishift")
11438 (set_attr "length" "2")])
11440 ;; This pattern can't accept a variable shift count, since shifts by
11441 ;; zero don't affect the flags. We assume that shifts by constant
11442 ;; zero are optimized away.
11443 (define_insn "*ashrsi3_cmp"
11446 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11447 (match_operand:QI 2 "immediate_operand" "I"))
11449 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11450 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11451 "ix86_match_ccmode (insn, CCGOCmode)
11452 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11453 "sar{l}\t{%2, %0|%0, %2}"
11454 [(set_attr "type" "ishift")
11455 (set_attr "mode" "SI")])
11457 (define_insn "*ashrsi3_cmp_zext"
11460 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11461 (match_operand:QI 2 "immediate_operand" "I"))
11463 (set (match_operand:DI 0 "register_operand" "=r")
11464 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11465 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11466 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11467 "sar{l}\t{%2, %k0|%k0, %2}"
11468 [(set_attr "type" "ishift")
11469 (set_attr "mode" "SI")])
11471 (define_expand "ashrhi3"
11472 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11473 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11474 (match_operand:QI 2 "nonmemory_operand" "")))
11475 (clobber (reg:CC 17))]
11476 "TARGET_HIMODE_MATH"
11477 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11479 (define_insn "*ashrhi3_1_one_bit"
11480 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11481 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11482 (match_operand:QI 2 "const_int_1_operand" "")))
11483 (clobber (reg:CC 17))]
11484 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11485 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11487 [(set_attr "type" "ishift")
11488 (set (attr "length")
11489 (if_then_else (match_operand 0 "register_operand" "")
11491 (const_string "*")))])
11493 (define_insn "*ashrhi3_1"
11494 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11495 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11496 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11497 (clobber (reg:CC 17))]
11498 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11500 sar{w}\t{%2, %0|%0, %2}
11501 sar{w}\t{%b2, %0|%0, %b2}"
11502 [(set_attr "type" "ishift")
11503 (set_attr "mode" "HI")])
11505 ;; This pattern can't accept a variable shift count, since shifts by
11506 ;; zero don't affect the flags. We assume that shifts by constant
11507 ;; zero are optimized away.
11508 (define_insn "*ashrhi3_one_bit_cmp"
11511 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11512 (match_operand:QI 2 "const_int_1_operand" ""))
11514 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11515 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11516 "ix86_match_ccmode (insn, CCGOCmode)
11517 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11518 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11520 [(set_attr "type" "ishift")
11521 (set (attr "length")
11522 (if_then_else (match_operand 0 "register_operand" "")
11524 (const_string "*")))])
11526 ;; This pattern can't accept a variable shift count, since shifts by
11527 ;; zero don't affect the flags. We assume that shifts by constant
11528 ;; zero are optimized away.
11529 (define_insn "*ashrhi3_cmp"
11532 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11533 (match_operand:QI 2 "immediate_operand" "I"))
11535 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11536 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11537 "ix86_match_ccmode (insn, CCGOCmode)
11538 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11539 "sar{w}\t{%2, %0|%0, %2}"
11540 [(set_attr "type" "ishift")
11541 (set_attr "mode" "HI")])
11543 (define_expand "ashrqi3"
11544 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11545 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11546 (match_operand:QI 2 "nonmemory_operand" "")))
11547 (clobber (reg:CC 17))]
11548 "TARGET_QIMODE_MATH"
11549 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11551 (define_insn "*ashrqi3_1_one_bit"
11552 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11553 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11554 (match_operand:QI 2 "const_int_1_operand" "")))
11555 (clobber (reg:CC 17))]
11556 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11557 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11559 [(set_attr "type" "ishift")
11560 (set (attr "length")
11561 (if_then_else (match_operand 0 "register_operand" "")
11563 (const_string "*")))])
11565 (define_insn "*ashrqi3_1"
11566 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11567 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11568 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11569 (clobber (reg:CC 17))]
11570 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11572 sar{b}\t{%2, %0|%0, %2}
11573 sar{b}\t{%b2, %0|%0, %b2}"
11574 [(set_attr "type" "ishift")
11575 (set_attr "mode" "QI")])
11577 ;; This pattern can't accept a variable shift count, since shifts by
11578 ;; zero don't affect the flags. We assume that shifts by constant
11579 ;; zero are optimized away.
11580 (define_insn "*ashrqi3_one_bit_cmp"
11583 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11584 (match_operand:QI 2 "const_int_1_operand" "I"))
11586 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11587 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11588 "ix86_match_ccmode (insn, CCGOCmode)
11589 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11590 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11592 [(set_attr "type" "ishift")
11593 (set (attr "length")
11594 (if_then_else (match_operand 0 "register_operand" "")
11596 (const_string "*")))])
11598 ;; This pattern can't accept a variable shift count, since shifts by
11599 ;; zero don't affect the flags. We assume that shifts by constant
11600 ;; zero are optimized away.
11601 (define_insn "*ashrqi3_cmp"
11604 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11605 (match_operand:QI 2 "immediate_operand" "I"))
11607 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11608 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11609 "ix86_match_ccmode (insn, CCGOCmode)
11610 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11611 "sar{b}\t{%2, %0|%0, %2}"
11612 [(set_attr "type" "ishift")
11613 (set_attr "mode" "QI")])
11615 ;; Logical shift instructions
11617 ;; See comment above `ashldi3' about how this works.
11619 (define_expand "lshrdi3"
11620 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11621 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11622 (match_operand:QI 2 "nonmemory_operand" "")))
11623 (clobber (reg:CC 17))])]
11626 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11628 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11631 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11635 (define_insn "*lshrdi3_1_one_bit_rex64"
11636 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11637 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11638 (match_operand:QI 2 "const_int_1_operand" "")))
11639 (clobber (reg:CC 17))]
11640 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11641 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11643 [(set_attr "type" "ishift")
11644 (set (attr "length")
11645 (if_then_else (match_operand:DI 0 "register_operand" "")
11647 (const_string "*")))])
11649 (define_insn "*lshrdi3_1_rex64"
11650 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11651 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11652 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11653 (clobber (reg:CC 17))]
11654 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11656 shr{q}\t{%2, %0|%0, %2}
11657 shr{q}\t{%b2, %0|%0, %b2}"
11658 [(set_attr "type" "ishift")
11659 (set_attr "mode" "DI")])
11661 ;; This pattern can't accept a variable shift count, since shifts by
11662 ;; zero don't affect the flags. We assume that shifts by constant
11663 ;; zero are optimized away.
11664 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11667 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11668 (match_operand:QI 2 "const_int_1_operand" ""))
11670 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11671 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11672 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11673 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11674 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11676 [(set_attr "type" "ishift")
11677 (set (attr "length")
11678 (if_then_else (match_operand:DI 0 "register_operand" "")
11680 (const_string "*")))])
11682 ;; This pattern can't accept a variable shift count, since shifts by
11683 ;; zero don't affect the flags. We assume that shifts by constant
11684 ;; zero are optimized away.
11685 (define_insn "*lshrdi3_cmp_rex64"
11688 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11689 (match_operand:QI 2 "const_int_operand" "e"))
11691 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11692 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11693 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11694 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11695 "shr{q}\t{%2, %0|%0, %2}"
11696 [(set_attr "type" "ishift")
11697 (set_attr "mode" "DI")])
11699 (define_insn "lshrdi3_1"
11700 [(set (match_operand:DI 0 "register_operand" "=r")
11701 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11702 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11703 (clobber (match_scratch:SI 3 "=&r"))
11704 (clobber (reg:CC 17))]
11705 "!TARGET_64BIT && TARGET_CMOVE"
11707 [(set_attr "type" "multi")])
11709 (define_insn "*lshrdi3_2"
11710 [(set (match_operand:DI 0 "register_operand" "=r")
11711 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11712 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11713 (clobber (reg:CC 17))]
11716 [(set_attr "type" "multi")])
11719 [(set (match_operand:DI 0 "register_operand" "")
11720 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11721 (match_operand:QI 2 "nonmemory_operand" "")))
11722 (clobber (match_scratch:SI 3 ""))
11723 (clobber (reg:CC 17))]
11724 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11726 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11729 [(set (match_operand:DI 0 "register_operand" "")
11730 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11731 (match_operand:QI 2 "nonmemory_operand" "")))
11732 (clobber (reg:CC 17))]
11733 "!TARGET_64BIT && reload_completed"
11735 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11737 (define_expand "lshrsi3"
11738 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11739 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11740 (match_operand:QI 2 "nonmemory_operand" "")))
11741 (clobber (reg:CC 17))]
11743 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11745 (define_insn "*lshrsi3_1_one_bit"
11746 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11747 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11748 (match_operand:QI 2 "const_int_1_operand" "")))
11749 (clobber (reg:CC 17))]
11750 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11751 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11753 [(set_attr "type" "ishift")
11754 (set (attr "length")
11755 (if_then_else (match_operand:SI 0 "register_operand" "")
11757 (const_string "*")))])
11759 (define_insn "*lshrsi3_1_one_bit_zext"
11760 [(set (match_operand:DI 0 "register_operand" "=r")
11761 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11762 (match_operand:QI 2 "const_int_1_operand" "")))
11763 (clobber (reg:CC 17))]
11764 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11765 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11767 [(set_attr "type" "ishift")
11768 (set_attr "length" "2")])
11770 (define_insn "*lshrsi3_1"
11771 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11772 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11773 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11774 (clobber (reg:CC 17))]
11775 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11777 shr{l}\t{%2, %0|%0, %2}
11778 shr{l}\t{%b2, %0|%0, %b2}"
11779 [(set_attr "type" "ishift")
11780 (set_attr "mode" "SI")])
11782 (define_insn "*lshrsi3_1_zext"
11783 [(set (match_operand:DI 0 "register_operand" "=r,r")
11785 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11786 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11787 (clobber (reg:CC 17))]
11788 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11790 shr{l}\t{%2, %k0|%k0, %2}
11791 shr{l}\t{%b2, %k0|%k0, %b2}"
11792 [(set_attr "type" "ishift")
11793 (set_attr "mode" "SI")])
11795 ;; This pattern can't accept a variable shift count, since shifts by
11796 ;; zero don't affect the flags. We assume that shifts by constant
11797 ;; zero are optimized away.
11798 (define_insn "*lshrsi3_one_bit_cmp"
11801 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11802 (match_operand:QI 2 "const_int_1_operand" ""))
11804 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11805 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11806 "ix86_match_ccmode (insn, CCGOCmode)
11807 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11808 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11810 [(set_attr "type" "ishift")
11811 (set (attr "length")
11812 (if_then_else (match_operand:SI 0 "register_operand" "")
11814 (const_string "*")))])
11816 (define_insn "*lshrsi3_cmp_one_bit_zext"
11819 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11820 (match_operand:QI 2 "const_int_1_operand" ""))
11822 (set (match_operand:DI 0 "register_operand" "=r")
11823 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11824 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11825 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11826 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11828 [(set_attr "type" "ishift")
11829 (set_attr "length" "2")])
11831 ;; This pattern can't accept a variable shift count, since shifts by
11832 ;; zero don't affect the flags. We assume that shifts by constant
11833 ;; zero are optimized away.
11834 (define_insn "*lshrsi3_cmp"
11837 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11838 (match_operand:QI 2 "immediate_operand" "I"))
11840 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11841 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11842 "ix86_match_ccmode (insn, CCGOCmode)
11843 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11844 "shr{l}\t{%2, %0|%0, %2}"
11845 [(set_attr "type" "ishift")
11846 (set_attr "mode" "SI")])
11848 (define_insn "*lshrsi3_cmp_zext"
11851 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11852 (match_operand:QI 2 "immediate_operand" "I"))
11854 (set (match_operand:DI 0 "register_operand" "=r")
11855 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11856 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11857 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11858 "shr{l}\t{%2, %k0|%k0, %2}"
11859 [(set_attr "type" "ishift")
11860 (set_attr "mode" "SI")])
11862 (define_expand "lshrhi3"
11863 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11864 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11865 (match_operand:QI 2 "nonmemory_operand" "")))
11866 (clobber (reg:CC 17))]
11867 "TARGET_HIMODE_MATH"
11868 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11870 (define_insn "*lshrhi3_1_one_bit"
11871 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11872 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11873 (match_operand:QI 2 "const_int_1_operand" "")))
11874 (clobber (reg:CC 17))]
11875 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11876 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11878 [(set_attr "type" "ishift")
11879 (set (attr "length")
11880 (if_then_else (match_operand 0 "register_operand" "")
11882 (const_string "*")))])
11884 (define_insn "*lshrhi3_1"
11885 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11886 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11887 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11888 (clobber (reg:CC 17))]
11889 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11891 shr{w}\t{%2, %0|%0, %2}
11892 shr{w}\t{%b2, %0|%0, %b2}"
11893 [(set_attr "type" "ishift")
11894 (set_attr "mode" "HI")])
11896 ;; This pattern can't accept a variable shift count, since shifts by
11897 ;; zero don't affect the flags. We assume that shifts by constant
11898 ;; zero are optimized away.
11899 (define_insn "*lshrhi3_one_bit_cmp"
11902 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11903 (match_operand:QI 2 "const_int_1_operand" ""))
11905 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11906 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11907 "ix86_match_ccmode (insn, CCGOCmode)
11908 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11909 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11911 [(set_attr "type" "ishift")
11912 (set (attr "length")
11913 (if_then_else (match_operand:SI 0 "register_operand" "")
11915 (const_string "*")))])
11917 ;; This pattern can't accept a variable shift count, since shifts by
11918 ;; zero don't affect the flags. We assume that shifts by constant
11919 ;; zero are optimized away.
11920 (define_insn "*lshrhi3_cmp"
11923 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11924 (match_operand:QI 2 "immediate_operand" "I"))
11926 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11927 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11928 "ix86_match_ccmode (insn, CCGOCmode)
11929 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11930 "shr{w}\t{%2, %0|%0, %2}"
11931 [(set_attr "type" "ishift")
11932 (set_attr "mode" "HI")])
11934 (define_expand "lshrqi3"
11935 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11936 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11937 (match_operand:QI 2 "nonmemory_operand" "")))
11938 (clobber (reg:CC 17))]
11939 "TARGET_QIMODE_MATH"
11940 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11942 (define_insn "*lshrqi3_1_one_bit"
11943 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11944 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11945 (match_operand:QI 2 "const_int_1_operand" "")))
11946 (clobber (reg:CC 17))]
11947 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11948 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11950 [(set_attr "type" "ishift")
11951 (set (attr "length")
11952 (if_then_else (match_operand 0 "register_operand" "")
11954 (const_string "*")))])
11956 (define_insn "*lshrqi3_1"
11957 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11958 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11959 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11960 (clobber (reg:CC 17))]
11961 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11963 shr{b}\t{%2, %0|%0, %2}
11964 shr{b}\t{%b2, %0|%0, %b2}"
11965 [(set_attr "type" "ishift")
11966 (set_attr "mode" "QI")])
11968 ;; This pattern can't accept a variable shift count, since shifts by
11969 ;; zero don't affect the flags. We assume that shifts by constant
11970 ;; zero are optimized away.
11971 (define_insn "*lshrqi2_one_bit_cmp"
11974 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11975 (match_operand:QI 2 "const_int_1_operand" ""))
11977 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11978 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11979 "ix86_match_ccmode (insn, CCGOCmode)
11980 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11981 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11983 [(set_attr "type" "ishift")
11984 (set (attr "length")
11985 (if_then_else (match_operand:SI 0 "register_operand" "")
11987 (const_string "*")))])
11989 ;; This pattern can't accept a variable shift count, since shifts by
11990 ;; zero don't affect the flags. We assume that shifts by constant
11991 ;; zero are optimized away.
11992 (define_insn "*lshrqi2_cmp"
11995 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11996 (match_operand:QI 2 "immediate_operand" "I"))
11998 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11999 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12000 "ix86_match_ccmode (insn, CCGOCmode)
12001 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12002 "shr{b}\t{%2, %0|%0, %2}"
12003 [(set_attr "type" "ishift")
12004 (set_attr "mode" "QI")])
12006 ;; Rotate instructions
12008 (define_expand "rotldi3"
12009 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12010 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12011 (match_operand:QI 2 "nonmemory_operand" "")))
12012 (clobber (reg:CC 17))]
12014 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12016 (define_insn "*rotlsi3_1_one_bit_rex64"
12017 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12018 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12019 (match_operand:QI 2 "const_int_1_operand" "")))
12020 (clobber (reg:CC 17))]
12021 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12022 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12024 [(set_attr "type" "ishift")
12025 (set (attr "length")
12026 (if_then_else (match_operand:DI 0 "register_operand" "")
12028 (const_string "*")))])
12030 (define_insn "*rotldi3_1_rex64"
12031 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12032 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12033 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12034 (clobber (reg:CC 17))]
12035 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12037 rol{q}\t{%2, %0|%0, %2}
12038 rol{q}\t{%b2, %0|%0, %b2}"
12039 [(set_attr "type" "ishift")
12040 (set_attr "mode" "DI")])
12042 (define_expand "rotlsi3"
12043 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12044 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12045 (match_operand:QI 2 "nonmemory_operand" "")))
12046 (clobber (reg:CC 17))]
12048 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12050 (define_insn "*rotlsi3_1_one_bit"
12051 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12052 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12053 (match_operand:QI 2 "const_int_1_operand" "")))
12054 (clobber (reg:CC 17))]
12055 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12056 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12058 [(set_attr "type" "ishift")
12059 (set (attr "length")
12060 (if_then_else (match_operand:SI 0 "register_operand" "")
12062 (const_string "*")))])
12064 (define_insn "*rotlsi3_1_one_bit_zext"
12065 [(set (match_operand:DI 0 "register_operand" "=r")
12067 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12068 (match_operand:QI 2 "const_int_1_operand" ""))))
12069 (clobber (reg:CC 17))]
12070 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12071 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12073 [(set_attr "type" "ishift")
12074 (set_attr "length" "2")])
12076 (define_insn "*rotlsi3_1"
12077 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12078 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12079 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12080 (clobber (reg:CC 17))]
12081 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12083 rol{l}\t{%2, %0|%0, %2}
12084 rol{l}\t{%b2, %0|%0, %b2}"
12085 [(set_attr "type" "ishift")
12086 (set_attr "mode" "SI")])
12088 (define_insn "*rotlsi3_1_zext"
12089 [(set (match_operand:DI 0 "register_operand" "=r,r")
12091 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12092 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12093 (clobber (reg:CC 17))]
12094 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12096 rol{l}\t{%2, %k0|%k0, %2}
12097 rol{l}\t{%b2, %k0|%k0, %b2}"
12098 [(set_attr "type" "ishift")
12099 (set_attr "mode" "SI")])
12101 (define_expand "rotlhi3"
12102 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12103 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12104 (match_operand:QI 2 "nonmemory_operand" "")))
12105 (clobber (reg:CC 17))]
12106 "TARGET_HIMODE_MATH"
12107 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12109 (define_insn "*rotlhi3_1_one_bit"
12110 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12111 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12112 (match_operand:QI 2 "const_int_1_operand" "")))
12113 (clobber (reg:CC 17))]
12114 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12115 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12117 [(set_attr "type" "ishift")
12118 (set (attr "length")
12119 (if_then_else (match_operand 0 "register_operand" "")
12121 (const_string "*")))])
12123 (define_insn "*rotlhi3_1"
12124 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12125 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12126 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12127 (clobber (reg:CC 17))]
12128 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12130 rol{w}\t{%2, %0|%0, %2}
12131 rol{w}\t{%b2, %0|%0, %b2}"
12132 [(set_attr "type" "ishift")
12133 (set_attr "mode" "HI")])
12135 (define_expand "rotlqi3"
12136 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12137 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12138 (match_operand:QI 2 "nonmemory_operand" "")))
12139 (clobber (reg:CC 17))]
12140 "TARGET_QIMODE_MATH"
12141 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12143 (define_insn "*rotlqi3_1_one_bit"
12144 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12145 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12146 (match_operand:QI 2 "const_int_1_operand" "")))
12147 (clobber (reg:CC 17))]
12148 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12149 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12151 [(set_attr "type" "ishift")
12152 (set (attr "length")
12153 (if_then_else (match_operand 0 "register_operand" "")
12155 (const_string "*")))])
12157 (define_insn "*rotlqi3_1"
12158 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12159 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12160 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12161 (clobber (reg:CC 17))]
12162 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12164 rol{b}\t{%2, %0|%0, %2}
12165 rol{b}\t{%b2, %0|%0, %b2}"
12166 [(set_attr "type" "ishift")
12167 (set_attr "mode" "QI")])
12169 (define_expand "rotrdi3"
12170 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12171 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12172 (match_operand:QI 2 "nonmemory_operand" "")))
12173 (clobber (reg:CC 17))]
12175 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12177 (define_insn "*rotrdi3_1_one_bit_rex64"
12178 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12179 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12180 (match_operand:QI 2 "const_int_1_operand" "")))
12181 (clobber (reg:CC 17))]
12182 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12183 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12185 [(set_attr "type" "ishift")
12186 (set (attr "length")
12187 (if_then_else (match_operand:DI 0 "register_operand" "")
12189 (const_string "*")))])
12191 (define_insn "*rotrdi3_1_rex64"
12192 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12193 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12194 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12195 (clobber (reg:CC 17))]
12196 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12198 ror{q}\t{%2, %0|%0, %2}
12199 ror{q}\t{%b2, %0|%0, %b2}"
12200 [(set_attr "type" "ishift")
12201 (set_attr "mode" "DI")])
12203 (define_expand "rotrsi3"
12204 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12205 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12206 (match_operand:QI 2 "nonmemory_operand" "")))
12207 (clobber (reg:CC 17))]
12209 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12211 (define_insn "*rotrsi3_1_one_bit"
12212 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12213 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12214 (match_operand:QI 2 "const_int_1_operand" "")))
12215 (clobber (reg:CC 17))]
12216 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12217 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12219 [(set_attr "type" "ishift")
12220 (set (attr "length")
12221 (if_then_else (match_operand:SI 0 "register_operand" "")
12223 (const_string "*")))])
12225 (define_insn "*rotrsi3_1_one_bit_zext"
12226 [(set (match_operand:DI 0 "register_operand" "=r")
12228 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12229 (match_operand:QI 2 "const_int_1_operand" ""))))
12230 (clobber (reg:CC 17))]
12231 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12232 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12234 [(set_attr "type" "ishift")
12235 (set (attr "length")
12236 (if_then_else (match_operand:SI 0 "register_operand" "")
12238 (const_string "*")))])
12240 (define_insn "*rotrsi3_1"
12241 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12242 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12243 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12244 (clobber (reg:CC 17))]
12245 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12247 ror{l}\t{%2, %0|%0, %2}
12248 ror{l}\t{%b2, %0|%0, %b2}"
12249 [(set_attr "type" "ishift")
12250 (set_attr "mode" "SI")])
12252 (define_insn "*rotrsi3_1_zext"
12253 [(set (match_operand:DI 0 "register_operand" "=r,r")
12255 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12256 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12257 (clobber (reg:CC 17))]
12258 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12260 ror{l}\t{%2, %k0|%k0, %2}
12261 ror{l}\t{%b2, %k0|%k0, %b2}"
12262 [(set_attr "type" "ishift")
12263 (set_attr "mode" "SI")])
12265 (define_expand "rotrhi3"
12266 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12267 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12268 (match_operand:QI 2 "nonmemory_operand" "")))
12269 (clobber (reg:CC 17))]
12270 "TARGET_HIMODE_MATH"
12271 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12273 (define_insn "*rotrhi3_one_bit"
12274 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12275 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12276 (match_operand:QI 2 "const_int_1_operand" "")))
12277 (clobber (reg:CC 17))]
12278 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12279 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12281 [(set_attr "type" "ishift")
12282 (set (attr "length")
12283 (if_then_else (match_operand 0 "register_operand" "")
12285 (const_string "*")))])
12287 (define_insn "*rotrhi3"
12288 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12289 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12290 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12291 (clobber (reg:CC 17))]
12292 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12294 ror{w}\t{%2, %0|%0, %2}
12295 ror{w}\t{%b2, %0|%0, %b2}"
12296 [(set_attr "type" "ishift")
12297 (set_attr "mode" "HI")])
12299 (define_expand "rotrqi3"
12300 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12301 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12302 (match_operand:QI 2 "nonmemory_operand" "")))
12303 (clobber (reg:CC 17))]
12304 "TARGET_QIMODE_MATH"
12305 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12307 (define_insn "*rotrqi3_1_one_bit"
12308 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12309 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12310 (match_operand:QI 2 "const_int_1_operand" "")))
12311 (clobber (reg:CC 17))]
12312 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12313 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12315 [(set_attr "type" "ishift")
12316 (set (attr "length")
12317 (if_then_else (match_operand 0 "register_operand" "")
12319 (const_string "*")))])
12321 (define_insn "*rotrqi3_1"
12322 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12323 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12324 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12325 (clobber (reg:CC 17))]
12326 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12328 ror{b}\t{%2, %0|%0, %2}
12329 ror{b}\t{%b2, %0|%0, %b2}"
12330 [(set_attr "type" "ishift")
12331 (set_attr "mode" "QI")])
12333 ;; Bit set / bit test instructions
12335 (define_expand "extv"
12336 [(set (match_operand:SI 0 "register_operand" "")
12337 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12338 (match_operand:SI 2 "immediate_operand" "")
12339 (match_operand:SI 3 "immediate_operand" "")))]
12342 /* Handle extractions from %ah et al. */
12343 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12346 /* From mips.md: extract_bit_field doesn't verify that our source
12347 matches the predicate, so check it again here. */
12348 if (! register_operand (operands[1], VOIDmode))
12352 (define_expand "extzv"
12353 [(set (match_operand:SI 0 "register_operand" "")
12354 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12355 (match_operand:SI 2 "immediate_operand" "")
12356 (match_operand:SI 3 "immediate_operand" "")))]
12359 /* Handle extractions from %ah et al. */
12360 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12363 /* From mips.md: extract_bit_field doesn't verify that our source
12364 matches the predicate, so check it again here. */
12365 if (! register_operand (operands[1], VOIDmode))
12369 (define_expand "insv"
12370 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12371 (match_operand:SI 1 "immediate_operand" "")
12372 (match_operand:SI 2 "immediate_operand" ""))
12373 (match_operand:SI 3 "register_operand" ""))]
12376 /* Handle extractions from %ah et al. */
12377 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12380 /* From mips.md: insert_bit_field doesn't verify that our source
12381 matches the predicate, so check it again here. */
12382 if (! register_operand (operands[0], VOIDmode))
12386 ;; %%% bts, btr, btc, bt.
12388 ;; Store-flag instructions.
12390 ;; For all sCOND expanders, also expand the compare or test insn that
12391 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12393 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12394 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12395 ;; way, which can later delete the movzx if only QImode is needed.
12397 (define_expand "seq"
12398 [(set (match_operand:SI 0 "register_operand" "")
12399 (eq:SI (reg:CC 17) (const_int 0)))]
12401 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12403 (define_expand "sne"
12404 [(set (match_operand:SI 0 "register_operand" "")
12405 (ne:SI (reg:CC 17) (const_int 0)))]
12407 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12409 (define_expand "sgt"
12410 [(set (match_operand:SI 0 "register_operand" "")
12411 (gt:SI (reg:CC 17) (const_int 0)))]
12413 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12415 (define_expand "sgtu"
12416 [(set (match_operand:SI 0 "register_operand" "")
12417 (gtu:SI (reg:CC 17) (const_int 0)))]
12419 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12421 (define_expand "slt"
12422 [(set (match_operand:SI 0 "register_operand" "")
12423 (lt:SI (reg:CC 17) (const_int 0)))]
12425 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12427 (define_expand "sltu"
12428 [(set (match_operand:SI 0 "register_operand" "")
12429 (ltu:SI (reg:CC 17) (const_int 0)))]
12431 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12433 (define_expand "sge"
12434 [(set (match_operand:SI 0 "register_operand" "")
12435 (ge:SI (reg:CC 17) (const_int 0)))]
12437 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12439 (define_expand "sgeu"
12440 [(set (match_operand:SI 0 "register_operand" "")
12441 (geu:SI (reg:CC 17) (const_int 0)))]
12443 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12445 (define_expand "sle"
12446 [(set (match_operand:SI 0 "register_operand" "")
12447 (le:SI (reg:CC 17) (const_int 0)))]
12449 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12451 (define_expand "sleu"
12452 [(set (match_operand:SI 0 "register_operand" "")
12453 (leu:SI (reg:CC 17) (const_int 0)))]
12455 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12457 (define_expand "sunordered"
12458 [(set (match_operand:SI 0 "register_operand" "")
12459 (unordered:SI (reg:CC 17) (const_int 0)))]
12460 "TARGET_80387 || TARGET_SSE"
12461 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12463 (define_expand "sordered"
12464 [(set (match_operand:SI 0 "register_operand" "")
12465 (ordered:SI (reg:CC 17) (const_int 0)))]
12467 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12469 (define_expand "suneq"
12470 [(set (match_operand:SI 0 "register_operand" "")
12471 (uneq:SI (reg:CC 17) (const_int 0)))]
12472 "TARGET_80387 || TARGET_SSE"
12473 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12475 (define_expand "sunge"
12476 [(set (match_operand:SI 0 "register_operand" "")
12477 (unge:SI (reg:CC 17) (const_int 0)))]
12478 "TARGET_80387 || TARGET_SSE"
12479 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12481 (define_expand "sungt"
12482 [(set (match_operand:SI 0 "register_operand" "")
12483 (ungt:SI (reg:CC 17) (const_int 0)))]
12484 "TARGET_80387 || TARGET_SSE"
12485 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12487 (define_expand "sunle"
12488 [(set (match_operand:SI 0 "register_operand" "")
12489 (unle:SI (reg:CC 17) (const_int 0)))]
12490 "TARGET_80387 || TARGET_SSE"
12491 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12493 (define_expand "sunlt"
12494 [(set (match_operand:SI 0 "register_operand" "")
12495 (unlt:SI (reg:CC 17) (const_int 0)))]
12496 "TARGET_80387 || TARGET_SSE"
12497 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12499 (define_expand "sltgt"
12500 [(set (match_operand:SI 0 "register_operand" "")
12501 (ltgt:SI (reg:CC 17) (const_int 0)))]
12502 "TARGET_80387 || TARGET_SSE"
12503 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12505 (define_insn "*setcc_1"
12506 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12507 (match_operator:QI 1 "ix86_comparison_operator"
12508 [(reg 17) (const_int 0)]))]
12511 [(set_attr "type" "setcc")
12512 (set_attr "mode" "QI")])
12514 (define_insn "setcc_2"
12515 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12516 (match_operator:QI 1 "ix86_comparison_operator"
12517 [(reg 17) (const_int 0)]))]
12520 [(set_attr "type" "setcc")
12521 (set_attr "mode" "QI")])
12523 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12524 ;; subsequent logical operations are used to imitate conditional moves.
12525 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12526 ;; it directly. Futher holding this value in pseudo register might bring
12527 ;; problem in implicit normalization in spill code.
12528 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12529 ;; instructions after reload by splitting the conditional move patterns.
12531 (define_insn "*sse_setccsf"
12532 [(set (match_operand:SF 0 "register_operand" "=x")
12533 (match_operator:SF 1 "sse_comparison_operator"
12534 [(match_operand:SF 2 "register_operand" "0")
12535 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12536 "TARGET_SSE && reload_completed"
12537 "cmp%D1ss\t{%3, %0|%0, %3}"
12538 [(set_attr "type" "sse")
12539 (set_attr "mode" "SF")])
12541 (define_insn "*sse_setccdf"
12542 [(set (match_operand:DF 0 "register_operand" "=Y")
12543 (match_operator:DF 1 "sse_comparison_operator"
12544 [(match_operand:DF 2 "register_operand" "0")
12545 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12546 "TARGET_SSE2 && reload_completed"
12547 "cmp%D1sd\t{%3, %0|%0, %3}"
12548 [(set_attr "type" "sse")
12549 (set_attr "mode" "DF")])
12551 ;; Basic conditional jump instructions.
12552 ;; We ignore the overflow flag for signed branch instructions.
12554 ;; For all bCOND expanders, also expand the compare or test insn that
12555 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12557 (define_expand "beq"
12559 (if_then_else (match_dup 1)
12560 (label_ref (match_operand 0 "" ""))
12563 "ix86_expand_branch (EQ, operands[0]); DONE;")
12565 (define_expand "bne"
12567 (if_then_else (match_dup 1)
12568 (label_ref (match_operand 0 "" ""))
12571 "ix86_expand_branch (NE, operands[0]); DONE;")
12573 (define_expand "bgt"
12575 (if_then_else (match_dup 1)
12576 (label_ref (match_operand 0 "" ""))
12579 "ix86_expand_branch (GT, operands[0]); DONE;")
12581 (define_expand "bgtu"
12583 (if_then_else (match_dup 1)
12584 (label_ref (match_operand 0 "" ""))
12587 "ix86_expand_branch (GTU, operands[0]); DONE;")
12589 (define_expand "blt"
12591 (if_then_else (match_dup 1)
12592 (label_ref (match_operand 0 "" ""))
12595 "ix86_expand_branch (LT, operands[0]); DONE;")
12597 (define_expand "bltu"
12599 (if_then_else (match_dup 1)
12600 (label_ref (match_operand 0 "" ""))
12603 "ix86_expand_branch (LTU, operands[0]); DONE;")
12605 (define_expand "bge"
12607 (if_then_else (match_dup 1)
12608 (label_ref (match_operand 0 "" ""))
12611 "ix86_expand_branch (GE, operands[0]); DONE;")
12613 (define_expand "bgeu"
12615 (if_then_else (match_dup 1)
12616 (label_ref (match_operand 0 "" ""))
12619 "ix86_expand_branch (GEU, operands[0]); DONE;")
12621 (define_expand "ble"
12623 (if_then_else (match_dup 1)
12624 (label_ref (match_operand 0 "" ""))
12627 "ix86_expand_branch (LE, operands[0]); DONE;")
12629 (define_expand "bleu"
12631 (if_then_else (match_dup 1)
12632 (label_ref (match_operand 0 "" ""))
12635 "ix86_expand_branch (LEU, operands[0]); DONE;")
12637 (define_expand "bunordered"
12639 (if_then_else (match_dup 1)
12640 (label_ref (match_operand 0 "" ""))
12642 "TARGET_80387 || TARGET_SSE"
12643 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12645 (define_expand "bordered"
12647 (if_then_else (match_dup 1)
12648 (label_ref (match_operand 0 "" ""))
12650 "TARGET_80387 || TARGET_SSE"
12651 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12653 (define_expand "buneq"
12655 (if_then_else (match_dup 1)
12656 (label_ref (match_operand 0 "" ""))
12658 "TARGET_80387 || TARGET_SSE"
12659 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12661 (define_expand "bunge"
12663 (if_then_else (match_dup 1)
12664 (label_ref (match_operand 0 "" ""))
12666 "TARGET_80387 || TARGET_SSE"
12667 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12669 (define_expand "bungt"
12671 (if_then_else (match_dup 1)
12672 (label_ref (match_operand 0 "" ""))
12674 "TARGET_80387 || TARGET_SSE"
12675 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12677 (define_expand "bunle"
12679 (if_then_else (match_dup 1)
12680 (label_ref (match_operand 0 "" ""))
12682 "TARGET_80387 || TARGET_SSE"
12683 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12685 (define_expand "bunlt"
12687 (if_then_else (match_dup 1)
12688 (label_ref (match_operand 0 "" ""))
12690 "TARGET_80387 || TARGET_SSE"
12691 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12693 (define_expand "bltgt"
12695 (if_then_else (match_dup 1)
12696 (label_ref (match_operand 0 "" ""))
12698 "TARGET_80387 || TARGET_SSE"
12699 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12701 (define_insn "*jcc_1"
12703 (if_then_else (match_operator 1 "ix86_comparison_operator"
12704 [(reg 17) (const_int 0)])
12705 (label_ref (match_operand 0 "" ""))
12709 [(set_attr "type" "ibr")
12710 (set (attr "prefix_0f")
12711 (if_then_else (and (ge (minus (match_dup 0) (pc))
12713 (lt (minus (match_dup 0) (pc))
12718 (define_insn "*jcc_2"
12720 (if_then_else (match_operator 1 "ix86_comparison_operator"
12721 [(reg 17) (const_int 0)])
12723 (label_ref (match_operand 0 "" ""))))]
12726 [(set_attr "type" "ibr")
12727 (set (attr "prefix_0f")
12728 (if_then_else (and (ge (minus (match_dup 0) (pc))
12730 (lt (minus (match_dup 0) (pc))
12735 ;; Define combination compare-and-branch fp compare instructions to use
12736 ;; during early optimization. Splitting the operation apart early makes
12737 ;; for bad code when we want to reverse the operation.
12739 (define_insn "*fp_jcc_1"
12741 (if_then_else (match_operator 0 "comparison_operator"
12742 [(match_operand 1 "register_operand" "f")
12743 (match_operand 2 "register_operand" "f")])
12744 (label_ref (match_operand 3 "" ""))
12746 (clobber (reg:CCFP 18))
12747 (clobber (reg:CCFP 17))]
12748 "TARGET_CMOVE && TARGET_80387
12749 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12750 && FLOAT_MODE_P (GET_MODE (operands[1]))
12751 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12752 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12755 (define_insn "*fp_jcc_1_sse"
12757 (if_then_else (match_operator 0 "comparison_operator"
12758 [(match_operand 1 "register_operand" "f#x,x#f")
12759 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12760 (label_ref (match_operand 3 "" ""))
12762 (clobber (reg:CCFP 18))
12763 (clobber (reg:CCFP 17))]
12765 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12766 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12767 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12770 (define_insn "*fp_jcc_1_sse_only"
12772 (if_then_else (match_operator 0 "comparison_operator"
12773 [(match_operand 1 "register_operand" "x")
12774 (match_operand 2 "nonimmediate_operand" "xm")])
12775 (label_ref (match_operand 3 "" ""))
12777 (clobber (reg:CCFP 18))
12778 (clobber (reg:CCFP 17))]
12779 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12780 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12781 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12784 (define_insn "*fp_jcc_2"
12786 (if_then_else (match_operator 0 "comparison_operator"
12787 [(match_operand 1 "register_operand" "f")
12788 (match_operand 2 "register_operand" "f")])
12790 (label_ref (match_operand 3 "" ""))))
12791 (clobber (reg:CCFP 18))
12792 (clobber (reg:CCFP 17))]
12793 "TARGET_CMOVE && TARGET_80387
12794 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12795 && FLOAT_MODE_P (GET_MODE (operands[1]))
12796 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12797 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12800 (define_insn "*fp_jcc_2_sse"
12802 (if_then_else (match_operator 0 "comparison_operator"
12803 [(match_operand 1 "register_operand" "f#x,x#f")
12804 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12806 (label_ref (match_operand 3 "" ""))))
12807 (clobber (reg:CCFP 18))
12808 (clobber (reg:CCFP 17))]
12810 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12811 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12812 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12815 (define_insn "*fp_jcc_2_sse_only"
12817 (if_then_else (match_operator 0 "comparison_operator"
12818 [(match_operand 1 "register_operand" "x")
12819 (match_operand 2 "nonimmediate_operand" "xm")])
12821 (label_ref (match_operand 3 "" ""))))
12822 (clobber (reg:CCFP 18))
12823 (clobber (reg:CCFP 17))]
12824 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12825 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12826 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12829 (define_insn "*fp_jcc_3"
12831 (if_then_else (match_operator 0 "comparison_operator"
12832 [(match_operand 1 "register_operand" "f")
12833 (match_operand 2 "nonimmediate_operand" "fm")])
12834 (label_ref (match_operand 3 "" ""))
12836 (clobber (reg:CCFP 18))
12837 (clobber (reg:CCFP 17))
12838 (clobber (match_scratch:HI 4 "=a"))]
12840 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12841 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12842 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12843 && SELECT_CC_MODE (GET_CODE (operands[0]),
12844 operands[1], operands[2]) == CCFPmode
12845 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12848 (define_insn "*fp_jcc_4"
12850 (if_then_else (match_operator 0 "comparison_operator"
12851 [(match_operand 1 "register_operand" "f")
12852 (match_operand 2 "nonimmediate_operand" "fm")])
12854 (label_ref (match_operand 3 "" ""))))
12855 (clobber (reg:CCFP 18))
12856 (clobber (reg:CCFP 17))
12857 (clobber (match_scratch:HI 4 "=a"))]
12859 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12860 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12861 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12862 && SELECT_CC_MODE (GET_CODE (operands[0]),
12863 operands[1], operands[2]) == CCFPmode
12864 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12867 (define_insn "*fp_jcc_5"
12869 (if_then_else (match_operator 0 "comparison_operator"
12870 [(match_operand 1 "register_operand" "f")
12871 (match_operand 2 "register_operand" "f")])
12872 (label_ref (match_operand 3 "" ""))
12874 (clobber (reg:CCFP 18))
12875 (clobber (reg:CCFP 17))
12876 (clobber (match_scratch:HI 4 "=a"))]
12878 && FLOAT_MODE_P (GET_MODE (operands[1]))
12879 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12880 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12883 (define_insn "*fp_jcc_6"
12885 (if_then_else (match_operator 0 "comparison_operator"
12886 [(match_operand 1 "register_operand" "f")
12887 (match_operand 2 "register_operand" "f")])
12889 (label_ref (match_operand 3 "" ""))))
12890 (clobber (reg:CCFP 18))
12891 (clobber (reg:CCFP 17))
12892 (clobber (match_scratch:HI 4 "=a"))]
12894 && FLOAT_MODE_P (GET_MODE (operands[1]))
12895 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12896 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12901 (if_then_else (match_operator 0 "comparison_operator"
12902 [(match_operand 1 "register_operand" "")
12903 (match_operand 2 "nonimmediate_operand" "")])
12904 (match_operand 3 "" "")
12905 (match_operand 4 "" "")))
12906 (clobber (reg:CCFP 18))
12907 (clobber (reg:CCFP 17))]
12911 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
12912 operands[3], operands[4], NULL_RTX);
12918 (if_then_else (match_operator 0 "comparison_operator"
12919 [(match_operand 1 "register_operand" "")
12920 (match_operand 2 "nonimmediate_operand" "")])
12921 (match_operand 3 "" "")
12922 (match_operand 4 "" "")))
12923 (clobber (reg:CCFP 18))
12924 (clobber (reg:CCFP 17))
12925 (clobber (match_scratch:HI 5 "=a"))]
12928 (if_then_else (match_dup 6)
12932 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
12933 operands[3], operands[4], operands[5]);
12937 ;; Unconditional and other jump instructions
12939 (define_insn "jump"
12941 (label_ref (match_operand 0 "" "")))]
12944 [(set_attr "type" "ibr")])
12946 (define_insn "indirect_jump"
12947 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
12950 [(set_attr "type" "ibr")
12951 (set_attr "length_immediate" "0")])
12953 (define_insn "tablejump"
12954 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
12955 (use (label_ref (match_operand 1 "" "")))]
12958 [(set_attr "type" "ibr")
12959 (set_attr "length_immediate" "0")])
12961 ;; Implement switch statements when generating PIC code. Switches are
12962 ;; implemented by `tablejump' when not using -fpic.
12964 ;; Emit code here to do the range checking and make the index zero based.
12966 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
12967 ;; two rules below:
12969 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
12971 ;; 1. An expression involving an external reference may only use the
12972 ;; addition operator, and only with an assembly-time constant.
12973 ;; The example above satisfies this because ".-.L2" is a constant.
12975 ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
12976 ;; given the value of "GOT - .", where GOT is the actual address of
12977 ;; the Global Offset Table. Therefore, the .long above actually
12978 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
12979 ;; expression "GOT - .L2" by itself would generate an error from as(1).
12981 ;; The pattern below emits code that looks like this:
12984 ;; subl TABLE@GOTOFF(%ebx,index,4),reg
12987 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
12988 ;; the addr_diff_vec is known to be part of this module.
12990 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
12991 ;; evaluates to just ".L2".
12993 (define_expand "casesi"
12994 [(set (match_dup 5)
12995 (match_operand:SI 0 "general_operand" ""))
12996 (parallel [(set (match_dup 6)
12997 (minus:SI (match_dup 5)
12998 (match_operand:SI 1 "general_operand" "")))
12999 (clobber (reg:CC 17))])
13001 (compare:CC (match_dup 6)
13002 (match_operand:SI 2 "general_operand" "")))
13004 (if_then_else (gtu (reg:CC 17)
13006 (label_ref (match_operand 4 "" ""))
13009 [(set (match_dup 7)
13010 (minus:SI (match_dup 8)
13011 (mem:SI (plus:SI (plus:SI (mult:SI (match_dup 6) (const_int 4))
13013 (const (unspec [(label_ref (match_operand 3 "" ""))] 7))))))
13014 (clobber (reg:CC 17))])
13015 (parallel [(set (pc) (match_dup 7))
13016 (use (label_ref (match_dup 3)))])]
13019 operands[5] = gen_reg_rtx (SImode);
13020 operands[6] = gen_reg_rtx (SImode);
13021 operands[7] = gen_reg_rtx (SImode);
13022 operands[8] = pic_offset_table_rtx;
13023 current_function_uses_pic_offset_table = 1;
13026 (define_insn "*tablejump_pic"
13027 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13028 (use (label_ref (match_operand 1 "" "")))]
13031 [(set_attr "type" "ibr")
13032 (set_attr "length_immediate" "0")])
13034 ;; Loop instruction
13036 ;; This is all complicated by the fact that since this is a jump insn
13037 ;; we must handle our own reloads.
13039 (define_expand "doloop_end"
13040 [(use (match_operand 0 "" "")) ; loop pseudo
13041 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13042 (use (match_operand 2 "" "")) ; max iterations
13043 (use (match_operand 3 "" "")) ; loop level
13044 (use (match_operand 4 "" ""))] ; label
13045 "TARGET_USE_LOOP && !TARGET_64BIT"
13048 /* Only use cloop on innermost loops. */
13049 if (INTVAL (operands[3]) > 1)
13051 if (GET_MODE (operands[0]) != SImode)
13053 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13058 (define_insn "doloop_end_internal"
13060 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13062 (label_ref (match_operand 0 "" ""))
13064 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13065 (plus:SI (match_dup 1)
13067 (clobber (match_scratch:SI 3 "=X,X,r"))
13068 (clobber (reg:CC 17))]
13069 "TARGET_USE_LOOP && !TARGET_64BIT"
13071 if (which_alternative != 0)
13073 if (get_attr_length (insn) == 2)
13074 return "%+loop\t%l0";
13076 return "dec{l}\t%1\;%+jne\t%l0";
13078 [(set_attr "ppro_uops" "many")
13080 (if_then_else (and (eq_attr "alternative" "0")
13081 (and (ge (minus (match_dup 0) (pc))
13083 (lt (minus (match_dup 0) (pc))
13085 (const_string "ibr")
13086 (const_string "multi")))])
13090 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13092 (match_operand 0 "" "")
13095 (plus:SI (match_dup 1)
13097 (clobber (match_scratch:SI 2 ""))
13098 (clobber (reg:CC 17))]
13099 "TARGET_USE_LOOP && !TARGET_64BIT
13100 && reload_completed
13101 && REGNO (operands[1]) != 2"
13102 [(parallel [(set (reg:CCZ 17)
13103 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13105 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13106 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13113 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13115 (match_operand 0 "" "")
13117 (set (match_operand:SI 2 "nonimmediate_operand" "")
13118 (plus:SI (match_dup 1)
13120 (clobber (match_scratch:SI 3 ""))
13121 (clobber (reg:CC 17))]
13122 "TARGET_USE_LOOP && !TARGET_64BIT
13123 && reload_completed
13124 && (! REG_P (operands[2])
13125 || ! rtx_equal_p (operands[1], operands[2]))"
13126 [(set (match_dup 3) (match_dup 1))
13127 (parallel [(set (reg:CCZ 17)
13128 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13130 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13131 (set (match_dup 2) (match_dup 3))
13132 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13137 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13140 [(set (reg 17) (match_operand 0 "" ""))
13141 (set (match_operand:QI 1 "register_operand" "")
13142 (match_operator:QI 2 "ix86_comparison_operator"
13143 [(reg 17) (const_int 0)]))
13144 (set (match_operand 3 "q_regs_operand" "")
13145 (zero_extend (match_dup 1)))]
13146 "peep2_reg_dead_p (3, operands[1])
13147 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13148 [(parallel [(set (match_dup 3) (const_int 0))
13149 (clobber (reg:CC 17))])
13150 (set (match_dup 4) (match_dup 0))
13151 (set (strict_low_part (match_dup 5))
13153 "operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13154 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));")
13156 ;; Call instructions.
13158 ;; The predicates normally associated with named expanders are not properly
13159 ;; checked for calls. This is a bug in the generic code, but it isn't that
13160 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13162 ;; Call subroutine returning no value.
13164 (define_expand "call_pop"
13165 [(parallel [(call (match_operand:QI 0 "" "")
13166 (match_operand:SI 1 "" ""))
13168 (plus:SI (reg:SI 7)
13169 (match_operand:SI 3 "" "")))])]
13172 if (operands[3] == const0_rtx)
13174 emit_insn (gen_call (operands[0], operands[1], constm1_rtx));
13177 /* Static functions and indirect calls don't need
13178 current_function_uses_pic_offset_table. */
13180 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13181 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13182 current_function_uses_pic_offset_table = 1;
13183 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13184 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13189 (define_insn "*call_pop_0"
13190 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13191 (match_operand:SI 1 "" ""))
13192 (set (reg:SI 7) (plus:SI (reg:SI 7)
13193 (match_operand:SI 2 "immediate_operand" "")))]
13196 if (SIBLING_CALL_P (insn))
13199 return "call\t%P0";
13201 [(set_attr "type" "call")])
13203 (define_insn "*call_pop_1"
13204 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13205 (match_operand:SI 1 "" ""))
13206 (set (reg:SI 7) (plus:SI (reg:SI 7)
13207 (match_operand:SI 2 "immediate_operand" "i")))]
13210 if (constant_call_address_operand (operands[0], Pmode))
13212 if (SIBLING_CALL_P (insn))
13215 return "call\t%P0";
13217 if (SIBLING_CALL_P (insn))
13220 return "call\t%A0";
13222 [(set_attr "type" "call")])
13224 (define_expand "call"
13225 [(call (match_operand:QI 0 "" "")
13226 (match_operand 1 "" ""))
13227 (use (match_operand 2 "" ""))]
13228 ;; Operand 1 not used on the i386.
13232 /* Static functions and indirect calls don't need
13233 current_function_uses_pic_offset_table. */
13235 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13236 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13237 current_function_uses_pic_offset_table = 1;
13239 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13240 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13241 if (TARGET_64BIT && INTVAL (operands[2]) >= 0)
13243 rtx reg = gen_rtx_REG (QImode, 0);
13244 emit_move_insn (reg, operands[2]);
13245 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13246 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13249 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13253 (define_expand "call_exp"
13254 [(call (match_operand:QI 0 "" "")
13255 (match_operand 1 "" ""))]
13259 (define_insn "*call_0"
13260 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13261 (match_operand 1 "" ""))]
13264 if (SIBLING_CALL_P (insn))
13267 return "call\t%P0";
13269 [(set_attr "type" "call")])
13271 (define_insn "*call_1"
13272 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13273 (match_operand 1 "" ""))]
13276 if (constant_call_address_operand (operands[0], QImode))
13278 if (SIBLING_CALL_P (insn))
13281 return "call\t%P0";
13283 if (SIBLING_CALL_P (insn))
13286 return "call\t%A0";
13288 [(set_attr "type" "call")])
13290 (define_insn "*call_1_rex64"
13291 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13292 (match_operand 1 "" ""))]
13295 if (constant_call_address_operand (operands[0], QImode))
13297 if (SIBLING_CALL_P (insn))
13300 return "call\t%P0";
13302 if (SIBLING_CALL_P (insn))
13305 return "call\t%A0";
13307 [(set_attr "type" "call")])
13309 ;; Call subroutine, returning value in operand 0
13310 ;; (which must be a hard register).
13312 (define_expand "call_value_pop"
13313 [(parallel [(set (match_operand 0 "" "")
13314 (call (match_operand:QI 1 "" "")
13315 (match_operand:SI 2 "" "")))
13317 (plus:SI (reg:SI 7)
13318 (match_operand:SI 4 "" "")))])]
13321 if (operands[4] == const0_rtx)
13323 emit_insn (gen_call_value (operands[0], operands[1], operands[2],
13327 /* Static functions and indirect calls don't need
13328 current_function_uses_pic_offset_table. */
13330 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13331 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13332 current_function_uses_pic_offset_table = 1;
13333 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13334 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13337 (define_expand "call_value"
13338 [(set (match_operand 0 "" "")
13339 (call (match_operand:QI 1 "" "")
13340 (match_operand:SI 2 "" "")))
13341 (use (match_operand:SI 3 "" ""))]
13342 ;; Operand 2 not used on the i386.
13346 /* Static functions and indirect calls don't need
13347 current_function_uses_pic_offset_table. */
13349 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13350 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13351 current_function_uses_pic_offset_table = 1;
13352 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13353 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13354 if (TARGET_64BIT && INTVAL (operands[3]) >= 0)
13356 rtx reg = gen_rtx_REG (QImode, 0);
13357 emit_move_insn (reg, operands[3]);
13358 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13360 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13363 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13368 (define_expand "call_value_exp"
13369 [(set (match_operand 0 "" "")
13370 (call (match_operand:QI 1 "" "")
13371 (match_operand:SI 2 "" "")))]
13375 ;; Call subroutine returning any type.
13377 (define_expand "untyped_call"
13378 [(parallel [(call (match_operand 0 "" "")
13380 (match_operand 1 "" "")
13381 (match_operand 2 "" "")])]
13386 /* In order to give reg-stack an easier job in validating two
13387 coprocessor registers as containing a possible return value,
13388 simply pretend the untyped call returns a complex long double
13391 emit_call_insn (TARGET_80387
13392 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13393 operands[0], const0_rtx,
13394 GEN_INT (SSE_REGPARM_MAX - 1))
13395 : gen_call (operands[0], const0_rtx,
13396 GEN_INT (SSE_REGPARM_MAX - 1)));
13398 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13400 rtx set = XVECEXP (operands[2], 0, i);
13401 emit_move_insn (SET_DEST (set), SET_SRC (set));
13404 /* The optimizer does not know that the call sets the function value
13405 registers we stored in the result block. We avoid problems by
13406 claiming that all hard registers are used and clobbered at this
13408 emit_insn (gen_blockage ());
13413 ;; Prologue and epilogue instructions
13415 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13416 ;; all of memory. This blocks insns from being moved across this point.
13418 (define_insn "blockage"
13419 [(unspec_volatile [(const_int 0)] 0)]
13422 [(set_attr "length" "0")])
13424 ;; Insn emitted into the body of a function to return from a function.
13425 ;; This is only done if the function's epilogue is known to be simple.
13426 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13428 (define_expand "return"
13430 "ix86_can_use_return_insn_p ()"
13432 if (current_function_pops_args)
13434 rtx popc = GEN_INT (current_function_pops_args);
13435 emit_jump_insn (gen_return_pop_internal (popc));
13440 (define_insn "return_internal"
13444 [(set_attr "length" "1")
13445 (set_attr "length_immediate" "0")
13446 (set_attr "modrm" "0")])
13448 (define_insn "return_pop_internal"
13450 (use (match_operand:SI 0 "const_int_operand" ""))]
13453 [(set_attr "length" "3")
13454 (set_attr "length_immediate" "2")
13455 (set_attr "modrm" "0")])
13457 (define_insn "return_indirect_internal"
13459 (use (match_operand:SI 0 "register_operand" "r"))]
13462 [(set_attr "type" "ibr")
13463 (set_attr "length_immediate" "0")])
13469 [(set_attr "length" "1")
13470 (set_attr "length_immediate" "0")
13471 (set_attr "modrm" "0")
13472 (set_attr "ppro_uops" "one")])
13474 (define_expand "prologue"
13477 "ix86_expand_prologue (); DONE;")
13479 (define_insn "prologue_set_got"
13480 [(set (match_operand:SI 0 "register_operand" "=r")
13481 (unspec_volatile:SI
13482 [(plus:SI (match_dup 0)
13483 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
13484 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
13485 (clobber (reg:CC 17))]
13488 if (GET_CODE (operands[2]) == LABEL_REF)
13489 operands[2] = XEXP (operands[2], 0);
13490 if (TARGET_DEEP_BRANCH_PREDICTION)
13491 return "add{l}\t{%1, %0|%0, %1}";
13493 return "add{l}\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}";
13495 [(set_attr "type" "alu")
13496 ; Since this insn may have two constant operands, we must set the
13498 (set_attr "length_immediate" "4")
13499 (set_attr "mode" "SI")])
13501 (define_insn "prologue_get_pc"
13502 [(set (match_operand:SI 0 "register_operand" "=r")
13503 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
13506 if (GET_CODE (operands[1]) == LABEL_REF)
13507 operands[1] = XEXP (operands[1], 0);
13508 output_asm_insn ("call\t%X1", operands);
13509 if (! TARGET_DEEP_BRANCH_PREDICTION)
13511 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
13512 CODE_LABEL_NUMBER (operands[1]));
13516 [(set_attr "type" "multi")])
13518 (define_expand "epilogue"
13521 "ix86_expand_epilogue (1); DONE;")
13523 (define_expand "sibcall_epilogue"
13526 "ix86_expand_epilogue (0); DONE;")
13528 (define_expand "eh_return"
13529 [(use (match_operand 0 "register_operand" ""))
13530 (use (match_operand 1 "register_operand" ""))]
13533 rtx tmp, sa = operands[0], ra = operands[1];
13535 /* Tricky bit: we write the address of the handler to which we will
13536 be returning into someone else's stack frame, one word below the
13537 stack address we wish to restore. */
13538 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13539 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13540 tmp = gen_rtx_MEM (Pmode, tmp);
13541 emit_move_insn (tmp, ra);
13543 if (Pmode == SImode)
13544 emit_insn (gen_eh_return_si (sa));
13546 emit_insn (gen_eh_return_di (sa));
13551 (define_insn_and_split "eh_return_si"
13552 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13)]
13557 "ix86_expand_epilogue (2); DONE;")
13559 (define_insn_and_split "eh_return_di"
13560 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13)]
13565 "ix86_expand_epilogue (2); DONE;")
13567 (define_insn "leave"
13568 [(set (reg:SI 7) (reg:SI 6))
13569 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))
13570 (clobber (mem:BLK (scratch)))]
13573 [(set_attr "length_immediate" "0")
13574 (set_attr "length" "1")
13575 (set_attr "modrm" "0")
13576 (set_attr "modrm" "0")
13577 (set_attr "athlon_decode" "vector")
13578 (set_attr "ppro_uops" "few")])
13580 (define_insn "leave_rex64"
13581 [(set (reg:DI 7) (reg:DI 6))
13582 (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7))))
13583 (clobber (mem:BLK (scratch)))]
13586 [(set_attr "length_immediate" "0")
13587 (set_attr "length" "1")
13588 (set_attr "modrm" "0")
13589 (set_attr "modrm" "0")
13590 (set_attr "athlon_decode" "vector")
13591 (set_attr "ppro_uops" "few")])
13593 (define_expand "ffssi2"
13594 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13595 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13598 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13599 rtx in = operands[1];
13603 emit_move_insn (tmp, constm1_rtx);
13604 emit_insn (gen_ffssi_1 (out, in));
13605 emit_insn (gen_rtx_SET (VOIDmode, out,
13606 gen_rtx_IF_THEN_ELSE (SImode,
13607 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13611 emit_insn (gen_addsi3 (out, out, const1_rtx));
13612 emit_move_insn (operands[0], out);
13615 /* Pentium bsf instruction is extremly slow. The following code is
13616 recommended by the Intel Optimizing Manual as a reasonable replacement:
13620 MOV DWORD PTR [TEMP+4],ECX
13623 MOV DWORD PTR [TEMP],EAX
13624 FILD QWORD PTR [TEMP]
13625 FSTP QWORD PTR [TEMP]
13626 WAIT ; WAIT only needed for compatibility with
13627 ; earlier processors
13628 MOV ECX, DWORD PTR [TEMP+4]
13631 TEST EAX,EAX ; clear zero flag
13633 Following piece of code expand ffs to similar beast.
13636 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13638 rtx label = gen_label_rtx ();
13640 rtx mem = assign_386_stack_local (DImode, 0);
13641 rtx fptmp = gen_reg_rtx (DFmode);
13642 split_di (&mem, 1, &lo, &hi);
13644 emit_move_insn (out, const0_rtx);
13646 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, 0, label);
13648 emit_move_insn (hi, out);
13649 emit_insn (gen_subsi3 (out, out, in));
13650 emit_insn (gen_andsi3 (out, out, in));
13651 emit_move_insn (lo, out);
13652 emit_insn (gen_floatdidf2 (fptmp,mem));
13653 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13654 emit_move_insn (out, hi);
13655 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13656 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13658 emit_label (label);
13659 LABEL_NUSES (label) = 1;
13661 emit_move_insn (operands[0], out);
13665 emit_move_insn (tmp, const0_rtx);
13666 emit_insn (gen_ffssi_1 (out, in));
13667 emit_insn (gen_rtx_SET (VOIDmode,
13668 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13669 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13671 emit_insn (gen_negsi2 (tmp, tmp));
13672 emit_insn (gen_iorsi3 (out, out, tmp));
13673 emit_insn (gen_addsi3 (out, out, const1_rtx));
13674 emit_move_insn (operands[0], out);
13679 (define_insn "ffssi_1"
13681 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13683 (set (match_operand:SI 0 "register_operand" "=r")
13684 (unspec:SI [(match_dup 1)] 5))]
13686 "bsf{l}\t{%1, %0|%0, %1}"
13687 [(set_attr "prefix_0f" "1")
13688 (set_attr "ppro_uops" "few")])
13690 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13691 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13693 ;; These patterns match the binary 387 instructions for addM3, subM3,
13694 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13695 ;; SFmode. The first is the normal insn, the second the same insn but
13696 ;; with one operand a conversion, and the third the same insn but with
13697 ;; the other operand a conversion. The conversion may be SFmode or
13698 ;; SImode if the target mode DFmode, but only SImode if the target mode
13701 ;; Gcc is slightly more smart about handling normal two address instructions
13702 ;; so use special patterns for add and mull.
13703 (define_insn "*fop_sf_comm"
13704 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13705 (match_operator:SF 3 "binary_fp_operator"
13706 [(match_operand:SF 1 "register_operand" "%0,0")
13707 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13708 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13709 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13710 "* return output_387_binary_op (insn, operands);"
13711 [(set (attr "type")
13712 (if_then_else (eq_attr "alternative" "1")
13713 (const_string "sse")
13714 (if_then_else (match_operand:SF 3 "mult_operator" "")
13715 (const_string "fmul")
13716 (const_string "fop"))))
13717 (set_attr "mode" "SF")])
13719 (define_insn "*fop_sf_comm_sse"
13720 [(set (match_operand:SF 0 "register_operand" "=x")
13721 (match_operator:SF 3 "binary_fp_operator"
13722 [(match_operand:SF 1 "register_operand" "%0")
13723 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13724 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13725 "* return output_387_binary_op (insn, operands);"
13726 [(set_attr "type" "sse")
13727 (set_attr "mode" "SF")])
13729 (define_insn "*fop_df_comm"
13730 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13731 (match_operator:DF 3 "binary_fp_operator"
13732 [(match_operand:DF 1 "register_operand" "%0,0")
13733 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13734 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13735 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13736 "* return output_387_binary_op (insn, operands);"
13737 [(set (attr "type")
13738 (if_then_else (eq_attr "alternative" "1")
13739 (const_string "sse")
13740 (if_then_else (match_operand:SF 3 "mult_operator" "")
13741 (const_string "fmul")
13742 (const_string "fop"))))
13743 (set_attr "mode" "DF")])
13745 (define_insn "*fop_df_comm_sse"
13746 [(set (match_operand:DF 0 "register_operand" "=Y")
13747 (match_operator:DF 3 "binary_fp_operator"
13748 [(match_operand:DF 1 "register_operand" "%0")
13749 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13751 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13752 "* return output_387_binary_op (insn, operands);"
13753 [(set_attr "type" "sse")
13754 (set_attr "mode" "DF")])
13756 (define_insn "*fop_xf_comm"
13757 [(set (match_operand:XF 0 "register_operand" "=f")
13758 (match_operator:XF 3 "binary_fp_operator"
13759 [(match_operand:XF 1 "register_operand" "%0")
13760 (match_operand:XF 2 "register_operand" "f")]))]
13761 "TARGET_80387 && !TARGET_64BIT
13762 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13763 "* return output_387_binary_op (insn, operands);"
13764 [(set (attr "type")
13765 (if_then_else (match_operand:XF 3 "mult_operator" "")
13766 (const_string "fmul")
13767 (const_string "fop")))
13768 (set_attr "mode" "XF")])
13770 (define_insn "*fop_tf_comm"
13771 [(set (match_operand:TF 0 "register_operand" "=f")
13772 (match_operator:TF 3 "binary_fp_operator"
13773 [(match_operand:TF 1 "register_operand" "%0")
13774 (match_operand:TF 2 "register_operand" "f")]))]
13775 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13776 "* return output_387_binary_op (insn, operands);"
13777 [(set (attr "type")
13778 (if_then_else (match_operand:TF 3 "mult_operator" "")
13779 (const_string "fmul")
13780 (const_string "fop")))
13781 (set_attr "mode" "XF")])
13783 (define_insn "*fop_sf_1"
13784 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
13785 (match_operator:SF 3 "binary_fp_operator"
13786 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
13787 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
13788 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13789 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13790 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13791 "* return output_387_binary_op (insn, operands);"
13792 [(set (attr "type")
13793 (cond [(eq_attr "alternative" "2")
13794 (const_string "sse")
13795 (match_operand:SF 3 "mult_operator" "")
13796 (const_string "fmul")
13797 (match_operand:SF 3 "div_operator" "")
13798 (const_string "fdiv")
13800 (const_string "fop")))
13801 (set_attr "mode" "SF")])
13803 (define_insn "*fop_sf_1_sse"
13804 [(set (match_operand:SF 0 "register_operand" "=x")
13805 (match_operator:SF 3 "binary_fp_operator"
13806 [(match_operand:SF 1 "register_operand" "0")
13807 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13809 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13810 "* return output_387_binary_op (insn, operands);"
13811 [(set_attr "type" "sse")
13812 (set_attr "mode" "SF")])
13814 ;; ??? Add SSE splitters for these!
13815 (define_insn "*fop_sf_2"
13816 [(set (match_operand:SF 0 "register_operand" "=f,f")
13817 (match_operator:SF 3 "binary_fp_operator"
13818 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13819 (match_operand:SF 2 "register_operand" "0,0")]))]
13820 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13821 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13822 [(set (attr "type")
13823 (cond [(match_operand:SF 3 "mult_operator" "")
13824 (const_string "fmul")
13825 (match_operand:SF 3 "div_operator" "")
13826 (const_string "fdiv")
13828 (const_string "fop")))
13829 (set_attr "fp_int_src" "true")
13830 (set_attr "ppro_uops" "many")
13831 (set_attr "mode" "SI")])
13833 (define_insn "*fop_sf_3"
13834 [(set (match_operand:SF 0 "register_operand" "=f,f")
13835 (match_operator:SF 3 "binary_fp_operator"
13836 [(match_operand:SF 1 "register_operand" "0,0")
13837 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13838 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13839 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13840 [(set (attr "type")
13841 (cond [(match_operand:SF 3 "mult_operator" "")
13842 (const_string "fmul")
13843 (match_operand:SF 3 "div_operator" "")
13844 (const_string "fdiv")
13846 (const_string "fop")))
13847 (set_attr "fp_int_src" "true")
13848 (set_attr "ppro_uops" "many")
13849 (set_attr "mode" "SI")])
13851 (define_insn "*fop_df_1"
13852 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
13853 (match_operator:DF 3 "binary_fp_operator"
13854 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
13855 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
13856 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13857 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13858 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13859 "* return output_387_binary_op (insn, operands);"
13860 [(set (attr "type")
13861 (cond [(eq_attr "alternative" "2")
13862 (const_string "sse")
13863 (match_operand:DF 3 "mult_operator" "")
13864 (const_string "fmul")
13865 (match_operand:DF 3 "div_operator" "")
13866 (const_string "fdiv")
13868 (const_string "fop")))
13869 (set_attr "mode" "DF")])
13871 (define_insn "*fop_df_1_sse"
13872 [(set (match_operand:DF 0 "register_operand" "=Y")
13873 (match_operator:DF 3 "binary_fp_operator"
13874 [(match_operand:DF 1 "register_operand" "0")
13875 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13877 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13878 "* return output_387_binary_op (insn, operands);"
13879 [(set_attr "type" "sse")])
13881 ;; ??? Add SSE splitters for these!
13882 (define_insn "*fop_df_2"
13883 [(set (match_operand:DF 0 "register_operand" "=f,f")
13884 (match_operator:DF 3 "binary_fp_operator"
13885 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13886 (match_operand:DF 2 "register_operand" "0,0")]))]
13887 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13888 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13889 [(set (attr "type")
13890 (cond [(match_operand:DF 3 "mult_operator" "")
13891 (const_string "fmul")
13892 (match_operand:DF 3 "div_operator" "")
13893 (const_string "fdiv")
13895 (const_string "fop")))
13896 (set_attr "fp_int_src" "true")
13897 (set_attr "ppro_uops" "many")
13898 (set_attr "mode" "SI")])
13900 (define_insn "*fop_df_3"
13901 [(set (match_operand:DF 0 "register_operand" "=f,f")
13902 (match_operator:DF 3 "binary_fp_operator"
13903 [(match_operand:DF 1 "register_operand" "0,0")
13904 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13905 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13906 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13907 [(set (attr "type")
13908 (cond [(match_operand:DF 3 "mult_operator" "")
13909 (const_string "fmul")
13910 (match_operand:DF 3 "div_operator" "")
13911 (const_string "fdiv")
13913 (const_string "fop")))
13914 (set_attr "fp_int_src" "true")
13915 (set_attr "ppro_uops" "many")
13916 (set_attr "mode" "SI")])
13918 (define_insn "*fop_df_4"
13919 [(set (match_operand:DF 0 "register_operand" "=f,f")
13920 (match_operator:DF 3 "binary_fp_operator"
13921 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13922 (match_operand:DF 2 "register_operand" "0,f")]))]
13924 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13925 "* return output_387_binary_op (insn, operands);"
13926 [(set (attr "type")
13927 (cond [(match_operand:DF 3 "mult_operator" "")
13928 (const_string "fmul")
13929 (match_operand:DF 3 "div_operator" "")
13930 (const_string "fdiv")
13932 (const_string "fop")))
13933 (set_attr "mode" "SF")])
13935 (define_insn "*fop_df_5"
13936 [(set (match_operand:DF 0 "register_operand" "=f,f")
13937 (match_operator:DF 3 "binary_fp_operator"
13938 [(match_operand:DF 1 "register_operand" "0,f")
13940 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13941 "TARGET_80387 && !TARGET_SSE2"
13942 "* return output_387_binary_op (insn, operands);"
13943 [(set (attr "type")
13944 (cond [(match_operand:DF 3 "mult_operator" "")
13945 (const_string "fmul")
13946 (match_operand:DF 3 "div_operator" "")
13947 (const_string "fdiv")
13949 (const_string "fop")))
13950 (set_attr "mode" "SF")])
13952 (define_insn "*fop_xf_1"
13953 [(set (match_operand:XF 0 "register_operand" "=f,f")
13954 (match_operator:XF 3 "binary_fp_operator"
13955 [(match_operand:XF 1 "register_operand" "0,f")
13956 (match_operand:XF 2 "register_operand" "f,0")]))]
13957 "TARGET_80387 && !TARGET_64BIT
13958 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13959 "* return output_387_binary_op (insn, operands);"
13960 [(set (attr "type")
13961 (cond [(match_operand:XF 3 "mult_operator" "")
13962 (const_string "fmul")
13963 (match_operand:XF 3 "div_operator" "")
13964 (const_string "fdiv")
13966 (const_string "fop")))
13967 (set_attr "mode" "XF")])
13969 (define_insn "*fop_tf_1"
13970 [(set (match_operand:TF 0 "register_operand" "=f,f")
13971 (match_operator:TF 3 "binary_fp_operator"
13972 [(match_operand:TF 1 "register_operand" "0,f")
13973 (match_operand:TF 2 "register_operand" "f,0")]))]
13975 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13976 "* return output_387_binary_op (insn, operands);"
13977 [(set (attr "type")
13978 (cond [(match_operand:TF 3 "mult_operator" "")
13979 (const_string "fmul")
13980 (match_operand:TF 3 "div_operator" "")
13981 (const_string "fdiv")
13983 (const_string "fop")))
13984 (set_attr "mode" "XF")])
13986 (define_insn "*fop_xf_2"
13987 [(set (match_operand:XF 0 "register_operand" "=f,f")
13988 (match_operator:XF 3 "binary_fp_operator"
13989 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13990 (match_operand:XF 2 "register_operand" "0,0")]))]
13991 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
13992 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13993 [(set (attr "type")
13994 (cond [(match_operand:XF 3 "mult_operator" "")
13995 (const_string "fmul")
13996 (match_operand:XF 3 "div_operator" "")
13997 (const_string "fdiv")
13999 (const_string "fop")))
14000 (set_attr "fp_int_src" "true")
14001 (set_attr "mode" "SI")
14002 (set_attr "ppro_uops" "many")])
14004 (define_insn "*fop_tf_2"
14005 [(set (match_operand:TF 0 "register_operand" "=f,f")
14006 (match_operator:TF 3 "binary_fp_operator"
14007 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14008 (match_operand:TF 2 "register_operand" "0,0")]))]
14009 "TARGET_80387 && TARGET_USE_FIOP"
14010 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14011 [(set (attr "type")
14012 (cond [(match_operand:TF 3 "mult_operator" "")
14013 (const_string "fmul")
14014 (match_operand:TF 3 "div_operator" "")
14015 (const_string "fdiv")
14017 (const_string "fop")))
14018 (set_attr "fp_int_src" "true")
14019 (set_attr "mode" "SI")
14020 (set_attr "ppro_uops" "many")])
14022 (define_insn "*fop_xf_3"
14023 [(set (match_operand:XF 0 "register_operand" "=f,f")
14024 (match_operator:XF 3 "binary_fp_operator"
14025 [(match_operand:XF 1 "register_operand" "0,0")
14026 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14027 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
14028 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14029 [(set (attr "type")
14030 (cond [(match_operand:XF 3 "mult_operator" "")
14031 (const_string "fmul")
14032 (match_operand:XF 3 "div_operator" "")
14033 (const_string "fdiv")
14035 (const_string "fop")))
14036 (set_attr "fp_int_src" "true")
14037 (set_attr "mode" "SI")
14038 (set_attr "ppro_uops" "many")])
14040 (define_insn "*fop_tf_3"
14041 [(set (match_operand:TF 0 "register_operand" "=f,f")
14042 (match_operator:TF 3 "binary_fp_operator"
14043 [(match_operand:TF 1 "register_operand" "0,0")
14044 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14045 "TARGET_80387 && TARGET_USE_FIOP"
14046 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14047 [(set (attr "type")
14048 (cond [(match_operand:TF 3 "mult_operator" "")
14049 (const_string "fmul")
14050 (match_operand:TF 3 "div_operator" "")
14051 (const_string "fdiv")
14053 (const_string "fop")))
14054 (set_attr "fp_int_src" "true")
14055 (set_attr "mode" "SI")
14056 (set_attr "ppro_uops" "many")])
14058 (define_insn "*fop_xf_4"
14059 [(set (match_operand:XF 0 "register_operand" "=f,f")
14060 (match_operator:XF 3 "binary_fp_operator"
14061 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14062 (match_operand:XF 2 "register_operand" "0,f")]))]
14063 "TARGET_80387 && !TARGET_64BIT"
14064 "* return output_387_binary_op (insn, operands);"
14065 [(set (attr "type")
14066 (cond [(match_operand:XF 3 "mult_operator" "")
14067 (const_string "fmul")
14068 (match_operand:XF 3 "div_operator" "")
14069 (const_string "fdiv")
14071 (const_string "fop")))
14072 (set_attr "mode" "SF")])
14074 (define_insn "*fop_tf_4"
14075 [(set (match_operand:TF 0 "register_operand" "=f,f")
14076 (match_operator:TF 3 "binary_fp_operator"
14077 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14078 (match_operand:TF 2 "register_operand" "0,f")]))]
14080 "* return output_387_binary_op (insn, operands);"
14081 [(set (attr "type")
14082 (cond [(match_operand:TF 3 "mult_operator" "")
14083 (const_string "fmul")
14084 (match_operand:TF 3 "div_operator" "")
14085 (const_string "fdiv")
14087 (const_string "fop")))
14088 (set_attr "mode" "SF")])
14090 (define_insn "*fop_xf_5"
14091 [(set (match_operand:XF 0 "register_operand" "=f,f")
14092 (match_operator:XF 3 "binary_fp_operator"
14093 [(match_operand:XF 1 "register_operand" "0,f")
14095 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14096 "TARGET_80387 && !TARGET_64BIT"
14097 "* return output_387_binary_op (insn, operands);"
14098 [(set (attr "type")
14099 (cond [(match_operand:XF 3 "mult_operator" "")
14100 (const_string "fmul")
14101 (match_operand:XF 3 "div_operator" "")
14102 (const_string "fdiv")
14104 (const_string "fop")))
14105 (set_attr "mode" "SF")])
14107 (define_insn "*fop_tf_5"
14108 [(set (match_operand:TF 0 "register_operand" "=f,f")
14109 (match_operator:TF 3 "binary_fp_operator"
14110 [(match_operand:TF 1 "register_operand" "0,f")
14112 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14114 "* return output_387_binary_op (insn, operands);"
14115 [(set (attr "type")
14116 (cond [(match_operand:TF 3 "mult_operator" "")
14117 (const_string "fmul")
14118 (match_operand:TF 3 "div_operator" "")
14119 (const_string "fdiv")
14121 (const_string "fop")))
14122 (set_attr "mode" "SF")])
14124 (define_insn "*fop_xf_6"
14125 [(set (match_operand:XF 0 "register_operand" "=f,f")
14126 (match_operator:XF 3 "binary_fp_operator"
14127 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14128 (match_operand:XF 2 "register_operand" "0,f")]))]
14129 "TARGET_80387 && !TARGET_64BIT"
14130 "* return output_387_binary_op (insn, operands);"
14131 [(set (attr "type")
14132 (cond [(match_operand:XF 3 "mult_operator" "")
14133 (const_string "fmul")
14134 (match_operand:XF 3 "div_operator" "")
14135 (const_string "fdiv")
14137 (const_string "fop")))
14138 (set_attr "mode" "DF")])
14140 (define_insn "*fop_tf_6"
14141 [(set (match_operand:TF 0 "register_operand" "=f,f")
14142 (match_operator:TF 3 "binary_fp_operator"
14143 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14144 (match_operand:TF 2 "register_operand" "0,f")]))]
14146 "* return output_387_binary_op (insn, operands);"
14147 [(set (attr "type")
14148 (cond [(match_operand:TF 3 "mult_operator" "")
14149 (const_string "fmul")
14150 (match_operand:TF 3 "div_operator" "")
14151 (const_string "fdiv")
14153 (const_string "fop")))
14154 (set_attr "mode" "DF")])
14156 (define_insn "*fop_xf_7"
14157 [(set (match_operand:XF 0 "register_operand" "=f,f")
14158 (match_operator:XF 3 "binary_fp_operator"
14159 [(match_operand:XF 1 "register_operand" "0,f")
14161 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14162 "TARGET_80387 && !TARGET_64BIT"
14163 "* return output_387_binary_op (insn, operands);"
14164 [(set (attr "type")
14165 (cond [(match_operand:XF 3 "mult_operator" "")
14166 (const_string "fmul")
14167 (match_operand:XF 3 "div_operator" "")
14168 (const_string "fdiv")
14170 (const_string "fop")))
14171 (set_attr "mode" "DF")])
14173 (define_insn "*fop_tf_7"
14174 [(set (match_operand:TF 0 "register_operand" "=f,f")
14175 (match_operator:TF 3 "binary_fp_operator"
14176 [(match_operand:TF 1 "register_operand" "0,f")
14178 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14180 "* return output_387_binary_op (insn, operands);"
14181 [(set (attr "type")
14182 (cond [(match_operand:TF 3 "mult_operator" "")
14183 (const_string "fmul")
14184 (match_operand:TF 3 "div_operator" "")
14185 (const_string "fdiv")
14187 (const_string "fop")))
14188 (set_attr "mode" "DF")])
14191 [(set (match_operand 0 "register_operand" "")
14192 (match_operator 3 "binary_fp_operator"
14193 [(float (match_operand:SI 1 "register_operand" ""))
14194 (match_operand 2 "register_operand" "")]))]
14195 "TARGET_80387 && reload_completed
14196 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14199 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14200 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14201 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14202 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14203 GET_MODE (operands[3]),
14206 ix86_free_from_memory (GET_MODE (operands[1]));
14211 [(set (match_operand 0 "register_operand" "")
14212 (match_operator 3 "binary_fp_operator"
14213 [(match_operand 1 "register_operand" "")
14214 (float (match_operand:SI 2 "register_operand" ""))]))]
14215 "TARGET_80387 && reload_completed
14216 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14219 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14220 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14221 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14222 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14223 GET_MODE (operands[3]),
14226 ix86_free_from_memory (GET_MODE (operands[2]));
14230 ;; FPU special functions.
14232 (define_expand "sqrtsf2"
14233 [(set (match_operand:SF 0 "register_operand" "")
14234 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14235 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
14238 operands[1] = force_reg (SFmode, operands[1]);
14241 (define_insn "sqrtsf2_1"
14242 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14243 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14244 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14245 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
14248 sqrtss\t{%1, %0|%0, %1}"
14249 [(set_attr "type" "fpspc,sse")
14250 (set_attr "mode" "SF,SF")
14251 (set_attr "athlon_decode" "direct,*")])
14253 (define_insn "sqrtsf2_1_sse_only"
14254 [(set (match_operand:SF 0 "register_operand" "=x")
14255 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14256 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14257 "sqrtss\t{%1, %0|%0, %1}"
14258 [(set_attr "type" "sse")
14259 (set_attr "mode" "SF")
14260 (set_attr "athlon_decode" "*")])
14262 (define_insn "sqrtsf2_i387"
14263 [(set (match_operand:SF 0 "register_operand" "=f")
14264 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14265 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14266 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
14268 [(set_attr "type" "fpspc")
14269 (set_attr "mode" "SF")
14270 (set_attr "athlon_decode" "direct")])
14272 (define_expand "sqrtdf2"
14273 [(set (match_operand:DF 0 "register_operand" "")
14274 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14275 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
14278 operands[1] = force_reg (DFmode, operands[1]);
14281 (define_insn "sqrtdf2_1"
14282 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14283 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14284 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14285 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
14288 sqrtsd\t{%1, %0|%0, %1}"
14289 [(set_attr "type" "fpspc,sse")
14290 (set_attr "mode" "DF,DF")
14291 (set_attr "athlon_decode" "direct,*")])
14293 (define_insn "sqrtdf2_1_sse_only"
14294 [(set (match_operand:DF 0 "register_operand" "=Y")
14295 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14296 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14297 "sqrtsd\t{%1, %0|%0, %1}"
14298 [(set_attr "type" "sse")
14299 (set_attr "mode" "DF")
14300 (set_attr "athlon_decode" "*")])
14302 (define_insn "sqrtdf2_i387"
14303 [(set (match_operand:DF 0 "register_operand" "=f")
14304 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14305 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14306 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
14308 [(set_attr "type" "fpspc")
14309 (set_attr "mode" "DF")
14310 (set_attr "athlon_decode" "direct")])
14312 (define_insn "*sqrtextendsfdf2"
14313 [(set (match_operand:DF 0 "register_operand" "=f")
14314 (sqrt:DF (float_extend:DF
14315 (match_operand:SF 1 "register_operand" "0"))))]
14316 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
14318 [(set_attr "type" "fpspc")
14319 (set_attr "mode" "DF")
14320 (set_attr "athlon_decode" "direct")])
14322 (define_insn "sqrtxf2"
14323 [(set (match_operand:XF 0 "register_operand" "=f")
14324 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14325 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14326 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14328 [(set_attr "type" "fpspc")
14329 (set_attr "mode" "XF")
14330 (set_attr "athlon_decode" "direct")])
14332 (define_insn "sqrttf2"
14333 [(set (match_operand:TF 0 "register_operand" "=f")
14334 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14335 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14336 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14338 [(set_attr "type" "fpspc")
14339 (set_attr "mode" "XF")
14340 (set_attr "athlon_decode" "direct")])
14342 (define_insn "*sqrtextenddfxf2"
14343 [(set (match_operand:XF 0 "register_operand" "=f")
14344 (sqrt:XF (float_extend:XF
14345 (match_operand:DF 1 "register_operand" "0"))))]
14346 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14348 [(set_attr "type" "fpspc")
14349 (set_attr "mode" "XF")
14350 (set_attr "athlon_decode" "direct")])
14352 (define_insn "*sqrtextenddftf2"
14353 [(set (match_operand:TF 0 "register_operand" "=f")
14354 (sqrt:TF (float_extend:TF
14355 (match_operand:DF 1 "register_operand" "0"))))]
14356 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14358 [(set_attr "type" "fpspc")
14359 (set_attr "mode" "XF")
14360 (set_attr "athlon_decode" "direct")])
14362 (define_insn "*sqrtextendsfxf2"
14363 [(set (match_operand:XF 0 "register_operand" "=f")
14364 (sqrt:XF (float_extend:XF
14365 (match_operand:SF 1 "register_operand" "0"))))]
14366 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14368 [(set_attr "type" "fpspc")
14369 (set_attr "mode" "XF")
14370 (set_attr "athlon_decode" "direct")])
14372 (define_insn "*sqrtextendsftf2"
14373 [(set (match_operand:TF 0 "register_operand" "=f")
14374 (sqrt:TF (float_extend:TF
14375 (match_operand:SF 1 "register_operand" "0"))))]
14376 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14378 [(set_attr "type" "fpspc")
14379 (set_attr "mode" "XF")
14380 (set_attr "athlon_decode" "direct")])
14382 (define_insn "sindf2"
14383 [(set (match_operand:DF 0 "register_operand" "=f")
14384 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
14385 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14386 && flag_unsafe_math_optimizations"
14388 [(set_attr "type" "fpspc")
14389 (set_attr "mode" "DF")])
14391 (define_insn "sinsf2"
14392 [(set (match_operand:SF 0 "register_operand" "=f")
14393 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
14394 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14395 && flag_unsafe_math_optimizations"
14397 [(set_attr "type" "fpspc")
14398 (set_attr "mode" "SF")])
14400 (define_insn "*sinextendsfdf2"
14401 [(set (match_operand:DF 0 "register_operand" "=f")
14402 (unspec:DF [(float_extend:DF
14403 (match_operand:SF 1 "register_operand" "0"))] 1))]
14404 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14405 && flag_unsafe_math_optimizations"
14407 [(set_attr "type" "fpspc")
14408 (set_attr "mode" "DF")])
14410 (define_insn "sinxf2"
14411 [(set (match_operand:XF 0 "register_operand" "=f")
14412 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14413 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14414 && flag_unsafe_math_optimizations"
14416 [(set_attr "type" "fpspc")
14417 (set_attr "mode" "XF")])
14419 (define_insn "sintf2"
14420 [(set (match_operand:TF 0 "register_operand" "=f")
14421 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
14422 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14423 && flag_unsafe_math_optimizations"
14425 [(set_attr "type" "fpspc")
14426 (set_attr "mode" "XF")])
14428 (define_insn "cosdf2"
14429 [(set (match_operand:DF 0 "register_operand" "=f")
14430 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
14431 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14432 && flag_unsafe_math_optimizations"
14434 [(set_attr "type" "fpspc")
14435 (set_attr "mode" "DF")])
14437 (define_insn "cossf2"
14438 [(set (match_operand:SF 0 "register_operand" "=f")
14439 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
14440 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14441 && flag_unsafe_math_optimizations"
14443 [(set_attr "type" "fpspc")
14444 (set_attr "mode" "SF")])
14446 (define_insn "*cosextendsfdf2"
14447 [(set (match_operand:DF 0 "register_operand" "=f")
14448 (unspec:DF [(float_extend:DF
14449 (match_operand:SF 1 "register_operand" "0"))] 2))]
14450 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14451 && flag_unsafe_math_optimizations"
14453 [(set_attr "type" "fpspc")
14454 (set_attr "mode" "DF")])
14456 (define_insn "cosxf2"
14457 [(set (match_operand:XF 0 "register_operand" "=f")
14458 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
14459 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14460 && flag_unsafe_math_optimizations"
14462 [(set_attr "type" "fpspc")
14463 (set_attr "mode" "XF")])
14465 (define_insn "costf2"
14466 [(set (match_operand:TF 0 "register_operand" "=f")
14467 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
14468 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14469 && flag_unsafe_math_optimizations"
14471 [(set_attr "type" "fpspc")
14472 (set_attr "mode" "XF")])
14474 ;; Block operation instructions
14477 [(set (reg:SI 19) (const_int 0))]
14480 [(set_attr "type" "cld")])
14482 (define_expand "movstrsi"
14483 [(use (match_operand:BLK 0 "memory_operand" ""))
14484 (use (match_operand:BLK 1 "memory_operand" ""))
14485 (use (match_operand:SI 2 "nonmemory_operand" ""))
14486 (use (match_operand:SI 3 "const_int_operand" ""))]
14489 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14495 (define_expand "movstrdi"
14496 [(use (match_operand:BLK 0 "memory_operand" ""))
14497 (use (match_operand:BLK 1 "memory_operand" ""))
14498 (use (match_operand:DI 2 "nonmemory_operand" ""))
14499 (use (match_operand:DI 3 "const_int_operand" ""))]
14502 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14508 ;; Most CPUs don't like single string operations
14509 ;; Handle this case here to simplify previous expander.
14511 (define_expand "strmovdi_rex64"
14512 [(set (match_dup 2)
14513 (mem:DI (match_operand:DI 1 "register_operand" "")))
14514 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14516 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14517 (clobber (reg:CC 17))])
14518 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14519 (clobber (reg:CC 17))])]
14522 if (TARGET_SINGLE_STRINGOP || optimize_size)
14524 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14529 operands[2] = gen_reg_rtx (DImode);
14533 (define_expand "strmovsi"
14534 [(set (match_dup 2)
14535 (mem:SI (match_operand:SI 1 "register_operand" "")))
14536 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14538 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14539 (clobber (reg:CC 17))])
14540 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14541 (clobber (reg:CC 17))])]
14546 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14549 if (TARGET_SINGLE_STRINGOP || optimize_size)
14551 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14556 operands[2] = gen_reg_rtx (SImode);
14559 (define_expand "strmovsi_rex64"
14560 [(set (match_dup 2)
14561 (mem:SI (match_operand:DI 1 "register_operand" "")))
14562 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14564 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14565 (clobber (reg:CC 17))])
14566 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14567 (clobber (reg:CC 17))])]
14570 if (TARGET_SINGLE_STRINGOP || optimize_size)
14572 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14577 operands[2] = gen_reg_rtx (SImode);
14580 (define_expand "strmovhi"
14581 [(set (match_dup 2)
14582 (mem:HI (match_operand:SI 1 "register_operand" "")))
14583 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14585 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14586 (clobber (reg:CC 17))])
14587 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14588 (clobber (reg:CC 17))])]
14593 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14596 if (TARGET_SINGLE_STRINGOP || optimize_size)
14598 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14603 operands[2] = gen_reg_rtx (HImode);
14606 (define_expand "strmovhi_rex64"
14607 [(set (match_dup 2)
14608 (mem:HI (match_operand:DI 1 "register_operand" "")))
14609 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14611 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14612 (clobber (reg:CC 17))])
14613 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14614 (clobber (reg:CC 17))])]
14617 if (TARGET_SINGLE_STRINGOP || optimize_size)
14619 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14624 operands[2] = gen_reg_rtx (HImode);
14627 (define_expand "strmovqi"
14628 [(set (match_dup 2)
14629 (mem:QI (match_operand:SI 1 "register_operand" "")))
14630 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14632 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14633 (clobber (reg:CC 17))])
14634 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14635 (clobber (reg:CC 17))])]
14640 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14643 if (TARGET_SINGLE_STRINGOP || optimize_size)
14645 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14650 operands[2] = gen_reg_rtx (QImode);
14653 (define_expand "strmovqi_rex64"
14654 [(set (match_dup 2)
14655 (mem:QI (match_operand:DI 1 "register_operand" "")))
14656 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14658 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14659 (clobber (reg:CC 17))])
14660 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14661 (clobber (reg:CC 17))])]
14664 if (TARGET_SINGLE_STRINGOP || optimize_size)
14666 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14671 operands[2] = gen_reg_rtx (QImode);
14674 (define_insn "strmovdi_rex_1"
14675 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14676 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14677 (set (match_operand:DI 0 "register_operand" "=D")
14678 (plus:DI (match_dup 2)
14680 (set (match_operand:DI 1 "register_operand" "=S")
14681 (plus:DI (match_dup 3)
14684 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14686 [(set_attr "type" "str")
14687 (set_attr "mode" "DI")
14688 (set_attr "memory" "both")])
14690 (define_insn "strmovsi_1"
14691 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14692 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14693 (set (match_operand:SI 0 "register_operand" "=D")
14694 (plus:SI (match_dup 2)
14696 (set (match_operand:SI 1 "register_operand" "=S")
14697 (plus:SI (match_dup 3)
14700 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14702 [(set_attr "type" "str")
14703 (set_attr "mode" "SI")
14704 (set_attr "memory" "both")])
14706 (define_insn "strmovsi_rex_1"
14707 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
14708 (mem:SI (match_operand:DI 3 "register_operand" "1")))
14709 (set (match_operand:DI 0 "register_operand" "=D")
14710 (plus:DI (match_dup 2)
14712 (set (match_operand:DI 1 "register_operand" "=S")
14713 (plus:DI (match_dup 3)
14716 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14718 [(set_attr "type" "str")
14719 (set_attr "mode" "SI")
14720 (set_attr "memory" "both")])
14722 (define_insn "strmovhi_1"
14723 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
14724 (mem:HI (match_operand:SI 3 "register_operand" "1")))
14725 (set (match_operand:SI 0 "register_operand" "=D")
14726 (plus:SI (match_dup 2)
14728 (set (match_operand:SI 1 "register_operand" "=S")
14729 (plus:SI (match_dup 3)
14732 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14734 [(set_attr "type" "str")
14735 (set_attr "memory" "both")
14736 (set_attr "mode" "HI")])
14738 (define_insn "strmovhi_rex_1"
14739 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
14740 (mem:HI (match_operand:DI 3 "register_operand" "1")))
14741 (set (match_operand:DI 0 "register_operand" "=D")
14742 (plus:DI (match_dup 2)
14744 (set (match_operand:DI 1 "register_operand" "=S")
14745 (plus:DI (match_dup 3)
14748 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14750 [(set_attr "type" "str")
14751 (set_attr "memory" "both")
14752 (set_attr "mode" "HI")])
14754 (define_insn "strmovqi_1"
14755 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
14756 (mem:QI (match_operand:SI 3 "register_operand" "1")))
14757 (set (match_operand:SI 0 "register_operand" "=D")
14758 (plus:SI (match_dup 2)
14760 (set (match_operand:SI 1 "register_operand" "=S")
14761 (plus:SI (match_dup 3)
14764 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14766 [(set_attr "type" "str")
14767 (set_attr "memory" "both")
14768 (set_attr "mode" "QI")])
14770 (define_insn "strmovqi_rex_1"
14771 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
14772 (mem:QI (match_operand:DI 3 "register_operand" "1")))
14773 (set (match_operand:DI 0 "register_operand" "=D")
14774 (plus:DI (match_dup 2)
14776 (set (match_operand:DI 1 "register_operand" "=S")
14777 (plus:DI (match_dup 3)
14780 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14782 [(set_attr "type" "str")
14783 (set_attr "memory" "both")
14784 (set_attr "mode" "QI")])
14786 (define_insn "rep_movdi_rex64"
14787 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14788 (set (match_operand:DI 0 "register_operand" "=D")
14789 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14791 (match_operand:DI 3 "register_operand" "0")))
14792 (set (match_operand:DI 1 "register_operand" "=S")
14793 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
14794 (match_operand:DI 4 "register_operand" "1")))
14795 (set (mem:BLK (match_dup 3))
14796 (mem:BLK (match_dup 4)))
14797 (use (match_dup 5))
14800 "rep\;movsq|rep movsq"
14801 [(set_attr "type" "str")
14802 (set_attr "prefix_rep" "1")
14803 (set_attr "memory" "both")
14804 (set_attr "mode" "DI")])
14806 (define_insn "rep_movsi"
14807 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14808 (set (match_operand:SI 0 "register_operand" "=D")
14809 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
14811 (match_operand:SI 3 "register_operand" "0")))
14812 (set (match_operand:SI 1 "register_operand" "=S")
14813 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
14814 (match_operand:SI 4 "register_operand" "1")))
14815 (set (mem:BLK (match_dup 3))
14816 (mem:BLK (match_dup 4)))
14817 (use (match_dup 5))
14820 "rep\;movsl|rep movsd"
14821 [(set_attr "type" "str")
14822 (set_attr "prefix_rep" "1")
14823 (set_attr "memory" "both")
14824 (set_attr "mode" "SI")])
14826 (define_insn "rep_movsi_rex64"
14827 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14828 (set (match_operand:DI 0 "register_operand" "=D")
14829 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14831 (match_operand:DI 3 "register_operand" "0")))
14832 (set (match_operand:DI 1 "register_operand" "=S")
14833 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
14834 (match_operand:DI 4 "register_operand" "1")))
14835 (set (mem:BLK (match_dup 3))
14836 (mem:BLK (match_dup 4)))
14837 (use (match_dup 5))
14840 "rep\;movsl|rep movsd"
14841 [(set_attr "type" "str")
14842 (set_attr "prefix_rep" "1")
14843 (set_attr "memory" "both")
14844 (set_attr "mode" "SI")])
14846 (define_insn "rep_movqi"
14847 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14848 (set (match_operand:SI 0 "register_operand" "=D")
14849 (plus:SI (match_operand:SI 3 "register_operand" "0")
14850 (match_operand:SI 5 "register_operand" "2")))
14851 (set (match_operand:SI 1 "register_operand" "=S")
14852 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
14853 (set (mem:BLK (match_dup 3))
14854 (mem:BLK (match_dup 4)))
14855 (use (match_dup 5))
14858 "rep\;movsb|rep movsb"
14859 [(set_attr "type" "str")
14860 (set_attr "prefix_rep" "1")
14861 (set_attr "memory" "both")
14862 (set_attr "mode" "SI")])
14864 (define_insn "rep_movqi_rex64"
14865 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14866 (set (match_operand:DI 0 "register_operand" "=D")
14867 (plus:DI (match_operand:DI 3 "register_operand" "0")
14868 (match_operand:DI 5 "register_operand" "2")))
14869 (set (match_operand:DI 1 "register_operand" "=S")
14870 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
14871 (set (mem:BLK (match_dup 3))
14872 (mem:BLK (match_dup 4)))
14873 (use (match_dup 5))
14876 "rep\;movsb|rep movsb"
14877 [(set_attr "type" "str")
14878 (set_attr "prefix_rep" "1")
14879 (set_attr "memory" "both")
14880 (set_attr "mode" "SI")])
14882 (define_expand "clrstrsi"
14883 [(use (match_operand:BLK 0 "memory_operand" ""))
14884 (use (match_operand:SI 1 "nonmemory_operand" ""))
14885 (use (match_operand 2 "const_int_operand" ""))]
14888 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14894 (define_expand "clrstrdi"
14895 [(use (match_operand:BLK 0 "memory_operand" ""))
14896 (use (match_operand:DI 1 "nonmemory_operand" ""))
14897 (use (match_operand 2 "const_int_operand" ""))]
14900 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14906 ;; Most CPUs don't like single string operations
14907 ;; Handle this case here to simplify previous expander.
14909 (define_expand "strsetdi_rex64"
14910 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
14911 (match_operand:DI 1 "register_operand" ""))
14912 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14913 (clobber (reg:CC 17))])]
14916 if (TARGET_SINGLE_STRINGOP || optimize_size)
14918 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
14923 (define_expand "strsetsi"
14924 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
14925 (match_operand:SI 1 "register_operand" ""))
14926 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14927 (clobber (reg:CC 17))])]
14932 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
14935 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14937 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
14942 (define_expand "strsetsi_rex64"
14943 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
14944 (match_operand:SI 1 "register_operand" ""))
14945 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14946 (clobber (reg:CC 17))])]
14949 if (TARGET_SINGLE_STRINGOP || optimize_size)
14951 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
14956 (define_expand "strsethi"
14957 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
14958 (match_operand:HI 1 "register_operand" ""))
14959 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14960 (clobber (reg:CC 17))])]
14965 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
14968 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14970 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
14975 (define_expand "strsethi_rex64"
14976 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
14977 (match_operand:HI 1 "register_operand" ""))
14978 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14979 (clobber (reg:CC 17))])]
14982 if (TARGET_SINGLE_STRINGOP || optimize_size)
14984 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
14989 (define_expand "strsetqi"
14990 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
14991 (match_operand:QI 1 "register_operand" ""))
14992 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14993 (clobber (reg:CC 17))])]
14998 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15001 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15003 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15008 (define_expand "strsetqi_rex64"
15009 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15010 (match_operand:QI 1 "register_operand" ""))
15011 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15012 (clobber (reg:CC 17))])]
15015 if (TARGET_SINGLE_STRINGOP || optimize_size)
15017 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15022 (define_insn "strsetdi_rex_1"
15023 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15024 (match_operand:SI 2 "register_operand" "a"))
15025 (set (match_operand:DI 0 "register_operand" "=D")
15026 (plus:DI (match_dup 1)
15029 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15031 [(set_attr "type" "str")
15032 (set_attr "memory" "store")
15033 (set_attr "mode" "DI")])
15035 (define_insn "strsetsi_1"
15036 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15037 (match_operand:SI 2 "register_operand" "a"))
15038 (set (match_operand:SI 0 "register_operand" "=D")
15039 (plus:SI (match_dup 1)
15042 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15044 [(set_attr "type" "str")
15045 (set_attr "memory" "store")
15046 (set_attr "mode" "SI")])
15048 (define_insn "strsetsi_rex_1"
15049 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15050 (match_operand:SI 2 "register_operand" "a"))
15051 (set (match_operand:DI 0 "register_operand" "=D")
15052 (plus:DI (match_dup 1)
15055 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15057 [(set_attr "type" "str")
15058 (set_attr "memory" "store")
15059 (set_attr "mode" "SI")])
15061 (define_insn "strsethi_1"
15062 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15063 (match_operand:HI 2 "register_operand" "a"))
15064 (set (match_operand:SI 0 "register_operand" "=D")
15065 (plus:SI (match_dup 1)
15068 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15070 [(set_attr "type" "str")
15071 (set_attr "memory" "store")
15072 (set_attr "mode" "HI")])
15074 (define_insn "strsethi_rex_1"
15075 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15076 (match_operand:HI 2 "register_operand" "a"))
15077 (set (match_operand:DI 0 "register_operand" "=D")
15078 (plus:DI (match_dup 1)
15081 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15083 [(set_attr "type" "str")
15084 (set_attr "memory" "store")
15085 (set_attr "mode" "HI")])
15087 (define_insn "strsetqi_1"
15088 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15089 (match_operand:QI 2 "register_operand" "a"))
15090 (set (match_operand:SI 0 "register_operand" "=D")
15091 (plus:SI (match_dup 1)
15094 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15096 [(set_attr "type" "str")
15097 (set_attr "memory" "store")
15098 (set_attr "mode" "QI")])
15100 (define_insn "strsetqi_rex_1"
15101 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15102 (match_operand:QI 2 "register_operand" "a"))
15103 (set (match_operand:DI 0 "register_operand" "=D")
15104 (plus:DI (match_dup 1)
15107 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15109 [(set_attr "type" "str")
15110 (set_attr "memory" "store")
15111 (set_attr "mode" "QI")])
15113 (define_insn "rep_stosdi_rex64"
15114 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15115 (set (match_operand:DI 0 "register_operand" "=D")
15116 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15118 (match_operand:DI 3 "register_operand" "0")))
15119 (set (mem:BLK (match_dup 3))
15121 (use (match_operand:DI 2 "register_operand" "a"))
15122 (use (match_dup 4))
15125 "rep\;stosq|rep stosq"
15126 [(set_attr "type" "str")
15127 (set_attr "prefix_rep" "1")
15128 (set_attr "memory" "store")
15129 (set_attr "mode" "DI")])
15131 (define_insn "rep_stossi"
15132 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15133 (set (match_operand:SI 0 "register_operand" "=D")
15134 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15136 (match_operand:SI 3 "register_operand" "0")))
15137 (set (mem:BLK (match_dup 3))
15139 (use (match_operand:SI 2 "register_operand" "a"))
15140 (use (match_dup 4))
15143 "rep\;stosl|rep stosd"
15144 [(set_attr "type" "str")
15145 (set_attr "prefix_rep" "1")
15146 (set_attr "memory" "store")
15147 (set_attr "mode" "SI")])
15149 (define_insn "rep_stossi_rex64"
15150 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15151 (set (match_operand:DI 0 "register_operand" "=D")
15152 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15154 (match_operand:DI 3 "register_operand" "0")))
15155 (set (mem:BLK (match_dup 3))
15157 (use (match_operand:SI 2 "register_operand" "a"))
15158 (use (match_dup 4))
15161 "rep\;stosl|rep stosd"
15162 [(set_attr "type" "str")
15163 (set_attr "prefix_rep" "1")
15164 (set_attr "memory" "store")
15165 (set_attr "mode" "SI")])
15167 (define_insn "rep_stosqi"
15168 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15169 (set (match_operand:SI 0 "register_operand" "=D")
15170 (plus:SI (match_operand:SI 3 "register_operand" "0")
15171 (match_operand:SI 4 "register_operand" "1")))
15172 (set (mem:BLK (match_dup 3))
15174 (use (match_operand:QI 2 "register_operand" "a"))
15175 (use (match_dup 4))
15178 "rep\;stosb|rep stosb"
15179 [(set_attr "type" "str")
15180 (set_attr "prefix_rep" "1")
15181 (set_attr "memory" "store")
15182 (set_attr "mode" "QI")])
15184 (define_insn "rep_stosqi_rex64"
15185 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15186 (set (match_operand:DI 0 "register_operand" "=D")
15187 (plus:DI (match_operand:DI 3 "register_operand" "0")
15188 (match_operand:DI 4 "register_operand" "1")))
15189 (set (mem:BLK (match_dup 3))
15191 (use (match_operand:QI 2 "register_operand" "a"))
15192 (use (match_dup 4))
15195 "rep\;stosb|rep stosb"
15196 [(set_attr "type" "str")
15197 (set_attr "prefix_rep" "1")
15198 (set_attr "memory" "store")
15199 (set_attr "mode" "QI")])
15201 (define_expand "cmpstrsi"
15202 [(set (match_operand:SI 0 "register_operand" "")
15203 (compare:SI (match_operand:BLK 1 "general_operand" "")
15204 (match_operand:BLK 2 "general_operand" "")))
15205 (use (match_operand 3 "general_operand" ""))
15206 (use (match_operand 4 "immediate_operand" ""))]
15209 rtx addr1, addr2, out, outlow, count, countreg, align;
15212 if (GET_CODE (out) != REG)
15213 out = gen_reg_rtx (SImode);
15215 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15216 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15218 count = operands[3];
15219 countreg = ix86_zero_extend_to_Pmode (count);
15221 /* %%% Iff we are testing strict equality, we can use known alignment
15222 to good advantage. This may be possible with combine, particularly
15223 once cc0 is dead. */
15224 align = operands[4];
15226 emit_insn (gen_cld ());
15227 if (GET_CODE (count) == CONST_INT)
15229 if (INTVAL (count) == 0)
15231 emit_move_insn (operands[0], const0_rtx);
15235 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15236 addr1, addr2, countreg));
15238 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15239 addr1, addr2, countreg));
15245 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15246 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15247 addr1, addr2, countreg));
15251 emit_insn (gen_cmpsi_1 (countreg, countreg));
15252 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15253 addr1, addr2, countreg));
15257 outlow = gen_lowpart (QImode, out);
15258 emit_insn (gen_cmpintqi (outlow));
15259 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15261 if (operands[0] != out)
15262 emit_move_insn (operands[0], out);
15267 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15269 (define_expand "cmpintqi"
15270 [(set (match_dup 1)
15271 (gtu:QI (reg:CC 17) (const_int 0)))
15273 (ltu:QI (reg:CC 17) (const_int 0)))
15274 (parallel [(set (match_operand:QI 0 "register_operand" "")
15275 (minus:QI (match_dup 1)
15277 (clobber (reg:CC 17))])]
15279 "operands[1] = gen_reg_rtx (QImode);
15280 operands[2] = gen_reg_rtx (QImode);")
15282 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15283 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15285 (define_insn "cmpstrqi_nz_1"
15287 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15288 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15289 (use (match_operand:SI 6 "register_operand" "2"))
15290 (use (match_operand:SI 3 "immediate_operand" "i"))
15292 (clobber (match_operand:SI 0 "register_operand" "=S"))
15293 (clobber (match_operand:SI 1 "register_operand" "=D"))
15294 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15297 [(set_attr "type" "str")
15298 (set_attr "mode" "QI")
15299 (set_attr "prefix_rep" "1")])
15301 (define_insn "cmpstrqi_nz_rex_1"
15303 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15304 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15305 (use (match_operand:DI 6 "register_operand" "2"))
15306 (use (match_operand:SI 3 "immediate_operand" "i"))
15308 (clobber (match_operand:DI 0 "register_operand" "=S"))
15309 (clobber (match_operand:DI 1 "register_operand" "=D"))
15310 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15313 [(set_attr "type" "str")
15314 (set_attr "mode" "QI")
15315 (set_attr "prefix_rep" "1")])
15317 ;; The same, but the count is not known to not be zero.
15319 (define_insn "cmpstrqi_1"
15321 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15323 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15324 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15326 (use (match_operand:SI 3 "immediate_operand" "i"))
15329 (clobber (match_operand:SI 0 "register_operand" "=S"))
15330 (clobber (match_operand:SI 1 "register_operand" "=D"))
15331 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15334 [(set_attr "type" "str")
15335 (set_attr "mode" "QI")
15336 (set_attr "prefix_rep" "1")])
15338 (define_insn "cmpstrqi_rex_1"
15340 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15342 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15343 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15345 (use (match_operand:SI 3 "immediate_operand" "i"))
15348 (clobber (match_operand:DI 0 "register_operand" "=S"))
15349 (clobber (match_operand:DI 1 "register_operand" "=D"))
15350 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15353 [(set_attr "type" "str")
15354 (set_attr "mode" "QI")
15355 (set_attr "prefix_rep" "1")])
15357 (define_expand "strlensi"
15358 [(set (match_operand:SI 0 "register_operand" "")
15359 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15360 (match_operand:QI 2 "immediate_operand" "")
15361 (match_operand 3 "immediate_operand" "")] 0))]
15364 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15370 (define_expand "strlendi"
15371 [(set (match_operand:DI 0 "register_operand" "")
15372 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15373 (match_operand:QI 2 "immediate_operand" "")
15374 (match_operand 3 "immediate_operand" "")] 0))]
15377 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15383 (define_insn "strlenqi_1"
15384 [(set (match_operand:SI 0 "register_operand" "=&c")
15385 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15386 (match_operand:QI 2 "register_operand" "a")
15387 (match_operand:SI 3 "immediate_operand" "i")
15388 (match_operand:SI 4 "register_operand" "0")] 0))
15390 (clobber (match_operand:SI 1 "register_operand" "=D"))
15391 (clobber (reg:CC 17))]
15394 [(set_attr "type" "str")
15395 (set_attr "mode" "QI")
15396 (set_attr "prefix_rep" "1")])
15398 (define_insn "strlenqi_rex_1"
15399 [(set (match_operand:DI 0 "register_operand" "=&c")
15400 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15401 (match_operand:QI 2 "register_operand" "a")
15402 (match_operand:DI 3 "immediate_operand" "i")
15403 (match_operand:DI 4 "register_operand" "0")] 0))
15405 (clobber (match_operand:DI 1 "register_operand" "=D"))
15406 (clobber (reg:CC 17))]
15409 [(set_attr "type" "str")
15410 (set_attr "mode" "QI")
15411 (set_attr "prefix_rep" "1")])
15413 ;; Peephole optimizations to clean up after cmpstr*. This should be
15414 ;; handled in combine, but it is not currently up to the task.
15415 ;; When used for their truth value, the cmpstr* expanders generate
15424 ;; The intermediate three instructions are unnecessary.
15426 ;; This one handles cmpstr*_nz_1...
15430 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15431 (mem:BLK (match_operand 5 "register_operand" ""))))
15432 (use (match_operand 6 "register_operand" ""))
15433 (use (match_operand:SI 3 "immediate_operand" ""))
15435 (clobber (match_operand 0 "register_operand" ""))
15436 (clobber (match_operand 1 "register_operand" ""))
15437 (clobber (match_operand 2 "register_operand" ""))])
15438 (set (match_operand:QI 7 "register_operand" "")
15439 (gtu:QI (reg:CC 17) (const_int 0)))
15440 (set (match_operand:QI 8 "register_operand" "")
15441 (ltu:QI (reg:CC 17) (const_int 0)))
15443 (compare (match_dup 7) (match_dup 8)))
15445 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15448 (compare:CC (mem:BLK (match_dup 4))
15449 (mem:BLK (match_dup 5))))
15450 (use (match_dup 6))
15451 (use (match_dup 3))
15453 (clobber (match_dup 0))
15454 (clobber (match_dup 1))
15455 (clobber (match_dup 2))])]
15458 ;; ...and this one handles cmpstr*_1.
15462 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
15464 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15465 (mem:BLK (match_operand 5 "register_operand" "")))
15467 (use (match_operand:SI 3 "immediate_operand" ""))
15470 (clobber (match_operand 0 "register_operand" ""))
15471 (clobber (match_operand 1 "register_operand" ""))
15472 (clobber (match_operand 2 "register_operand" ""))])
15473 (set (match_operand:QI 7 "register_operand" "")
15474 (gtu:QI (reg:CC 17) (const_int 0)))
15475 (set (match_operand:QI 8 "register_operand" "")
15476 (ltu:QI (reg:CC 17) (const_int 0)))
15478 (compare (match_dup 7) (match_dup 8)))
15480 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15483 (if_then_else:CC (ne (match_dup 6)
15485 (compare:CC (mem:BLK (match_dup 4))
15486 (mem:BLK (match_dup 5)))
15488 (use (match_dup 3))
15491 (clobber (match_dup 0))
15492 (clobber (match_dup 1))
15493 (clobber (match_dup 2))])]
15498 ;; Conditional move instructions.
15500 (define_expand "movdicc_rex64"
15501 [(set (match_operand:DI 0 "register_operand" "")
15502 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15503 (match_operand:DI 2 "x86_64_general_operand" "")
15504 (match_operand:DI 3 "x86_64_general_operand" "")))]
15506 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15508 (define_insn "x86_movdicc_0_m1_rex64"
15509 [(set (match_operand:DI 0 "register_operand" "=r")
15510 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15513 (clobber (reg:CC 17))]
15516 ; Since we don't have the proper number of operands for an alu insn,
15517 ; fill in all the blanks.
15518 [(set_attr "type" "alu")
15519 (set_attr "memory" "none")
15520 (set_attr "imm_disp" "false")
15521 (set_attr "mode" "DI")
15522 (set_attr "length_immediate" "0")])
15524 (define_insn "*movdicc_c_rex64"
15525 [(set (match_operand:DI 0 "register_operand" "=r,r")
15526 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15527 [(reg 17) (const_int 0)])
15528 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15529 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15530 "TARGET_64BIT && TARGET_CMOVE
15531 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15533 cmov%C1\t{%2, %0|%0, %2}
15534 cmov%c1\t{%3, %0|%0, %3}"
15535 [(set_attr "type" "icmov")
15536 (set_attr "mode" "DI")])
15538 (define_expand "movsicc"
15539 [(set (match_operand:SI 0 "register_operand" "")
15540 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15541 (match_operand:SI 2 "general_operand" "")
15542 (match_operand:SI 3 "general_operand" "")))]
15544 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15546 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15547 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15548 ;; So just document what we're doing explicitly.
15550 (define_insn "x86_movsicc_0_m1"
15551 [(set (match_operand:SI 0 "register_operand" "=r")
15552 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15555 (clobber (reg:CC 17))]
15558 ; Since we don't have the proper number of operands for an alu insn,
15559 ; fill in all the blanks.
15560 [(set_attr "type" "alu")
15561 (set_attr "memory" "none")
15562 (set_attr "imm_disp" "false")
15563 (set_attr "mode" "SI")
15564 (set_attr "length_immediate" "0")])
15566 (define_insn "*movsicc_noc"
15567 [(set (match_operand:SI 0 "register_operand" "=r,r")
15568 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15569 [(reg 17) (const_int 0)])
15570 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15571 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15573 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15575 cmov%C1\t{%2, %0|%0, %2}
15576 cmov%c1\t{%3, %0|%0, %3}"
15577 [(set_attr "type" "icmov")
15578 (set_attr "mode" "SI")])
15580 (define_expand "movhicc"
15581 [(set (match_operand:HI 0 "register_operand" "")
15582 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15583 (match_operand:HI 2 "nonimmediate_operand" "")
15584 (match_operand:HI 3 "nonimmediate_operand" "")))]
15585 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15586 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15588 (define_insn "*movhicc_noc"
15589 [(set (match_operand:HI 0 "register_operand" "=r,r")
15590 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15591 [(reg 17) (const_int 0)])
15592 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15593 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15595 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15597 cmov%C1\t{%2, %0|%0, %2}
15598 cmov%c1\t{%3, %0|%0, %3}"
15599 [(set_attr "type" "icmov")
15600 (set_attr "mode" "HI")])
15602 (define_expand "movsfcc"
15603 [(set (match_operand:SF 0 "register_operand" "")
15604 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15605 (match_operand:SF 2 "register_operand" "")
15606 (match_operand:SF 3 "register_operand" "")))]
15608 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15610 (define_insn "*movsfcc_1"
15611 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15612 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15613 [(reg 17) (const_int 0)])
15614 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15615 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15617 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15619 fcmov%F1\t{%2, %0|%0, %2}
15620 fcmov%f1\t{%3, %0|%0, %3}
15621 cmov%C1\t{%2, %0|%0, %2}
15622 cmov%c1\t{%3, %0|%0, %3}"
15623 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15624 (set_attr "mode" "SF,SF,SI,SI")])
15626 (define_expand "movdfcc"
15627 [(set (match_operand:DF 0 "register_operand" "")
15628 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15629 (match_operand:DF 2 "register_operand" "")
15630 (match_operand:DF 3 "register_operand" "")))]
15632 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15634 (define_insn "*movdfcc_1"
15635 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15636 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15637 [(reg 17) (const_int 0)])
15638 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15639 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15640 "TARGET_CMOVE && !TARGET_64BIT
15641 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15643 fcmov%F1\t{%2, %0|%0, %2}
15644 fcmov%f1\t{%3, %0|%0, %3}
15647 [(set_attr "type" "fcmov,fcmov,multi,multi")
15648 (set_attr "mode" "DF")])
15650 (define_insn "*movdfcc_1_rex64"
15651 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15652 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15653 [(reg 17) (const_int 0)])
15654 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15655 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15656 "TARGET_CMOVE && TARGET_64BIT
15657 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15659 fcmov%F1\t{%2, %0|%0, %2}
15660 fcmov%f1\t{%3, %0|%0, %3}
15661 cmov%C1\t{%2, %0|%0, %2}
15662 cmov%c1\t{%3, %0|%0, %3}"
15663 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15664 (set_attr "mode" "DF")])
15667 [(set (match_operand:DF 0 "register_operand" "")
15668 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15669 [(match_operand 4 "" "") (const_int 0)])
15670 (match_operand:DF 2 "nonimmediate_operand" "")
15671 (match_operand:DF 3 "nonimmediate_operand" "")))]
15672 "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
15673 [(set (match_dup 2)
15674 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15678 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15681 "split_di (operands+2, 1, operands+5, operands+6);
15682 split_di (operands+3, 1, operands+7, operands+8);
15683 split_di (operands, 1, operands+2, operands+3);")
15685 (define_expand "movxfcc"
15686 [(set (match_operand:XF 0 "register_operand" "")
15687 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15688 (match_operand:XF 2 "register_operand" "")
15689 (match_operand:XF 3 "register_operand" "")))]
15690 "TARGET_CMOVE && !TARGET_64BIT"
15691 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15693 (define_expand "movtfcc"
15694 [(set (match_operand:TF 0 "register_operand" "")
15695 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15696 (match_operand:TF 2 "register_operand" "")
15697 (match_operand:TF 3 "register_operand" "")))]
15699 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15701 (define_insn "*movxfcc_1"
15702 [(set (match_operand:XF 0 "register_operand" "=f,f")
15703 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
15704 [(reg 17) (const_int 0)])
15705 (match_operand:XF 2 "register_operand" "f,0")
15706 (match_operand:XF 3 "register_operand" "0,f")))]
15707 "TARGET_CMOVE && !TARGET_64BIT"
15709 fcmov%F1\t{%2, %0|%0, %2}
15710 fcmov%f1\t{%3, %0|%0, %3}"
15711 [(set_attr "type" "fcmov")
15712 (set_attr "mode" "XF")])
15714 (define_insn "*movtfcc_1"
15715 [(set (match_operand:TF 0 "register_operand" "=f,f")
15716 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
15717 [(reg 17) (const_int 0)])
15718 (match_operand:TF 2 "register_operand" "f,0")
15719 (match_operand:TF 3 "register_operand" "0,f")))]
15722 fcmov%F1\t{%2, %0|%0, %2}
15723 fcmov%f1\t{%3, %0|%0, %3}"
15724 [(set_attr "type" "fcmov")
15725 (set_attr "mode" "XF")])
15727 (define_expand "minsf3"
15729 (set (match_operand:SF 0 "register_operand" "")
15730 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15731 (match_operand:SF 2 "nonimmediate_operand" ""))
15734 (clobber (reg:CC 17))])]
15738 (define_insn "*minsf"
15739 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15740 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
15741 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15744 (clobber (reg:CC 17))]
15745 "TARGET_SSE && TARGET_IEEE_FP"
15748 (define_insn "*minsf_nonieee"
15749 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15750 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15751 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15754 (clobber (reg:CC 17))]
15755 "TARGET_SSE && !TARGET_IEEE_FP"
15759 [(set (match_operand:SF 0 "register_operand" "")
15760 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15761 (match_operand:SF 2 "nonimmediate_operand" ""))
15762 (match_operand:SF 3 "register_operand" "")
15763 (match_operand:SF 4 "nonimmediate_operand" "")))
15764 (clobber (reg:CC 17))]
15765 "SSE_REG_P (operands[0]) && reload_completed
15766 && ((operands_match_p (operands[1], operands[3])
15767 && operands_match_p (operands[2], operands[4]))
15768 || (operands_match_p (operands[1], operands[4])
15769 && operands_match_p (operands[2], operands[3])))"
15770 [(set (match_dup 0)
15771 (if_then_else:SF (lt (match_dup 1)
15776 ;; We can't represent the LT test directly. Do this by swapping the operands.
15779 [(set (match_operand:SF 0 "register_operand" "")
15780 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15781 (match_operand:SF 2 "register_operand" ""))
15782 (match_operand:DF 3 "register_operand" "")
15783 (match_operand:DF 4 "register_operand" "")))
15784 (clobber (reg:CC 17))]
15785 "FP_REG_P (operands[0]) && reload_completed
15786 && ((operands_match_p (operands[1], operands[3])
15787 && operands_match_p (operands[2], operands[4]))
15788 || (operands_match_p (operands[1], operands[4])
15789 && operands_match_p (operands[2], operands[3])))"
15790 [(set (reg:CCFP 17)
15791 (compare:CCFP (match_dup 2)
15794 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
15798 (define_insn "*minsf_sse"
15799 [(set (match_operand:SF 0 "register_operand" "=x")
15800 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
15801 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15804 "TARGET_SSE && reload_completed"
15805 "minss\t{%2, %0|%0, %2}"
15806 [(set_attr "type" "sse")
15807 (set_attr "mode" "SF")])
15809 (define_expand "mindf3"
15811 (set (match_operand:DF 0 "register_operand" "")
15812 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15813 (match_operand:DF 2 "nonimmediate_operand" ""))
15816 (clobber (reg:CC 17))])]
15820 (define_insn "*mindf"
15821 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15822 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15823 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15826 (clobber (reg:CC 17))]
15827 "TARGET_SSE2 && TARGET_IEEE_FP"
15830 (define_insn "*mindf_nonieee"
15831 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15832 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
15833 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15836 (clobber (reg:CC 17))]
15837 "TARGET_SSE2 && !TARGET_IEEE_FP"
15841 [(set (match_operand:DF 0 "register_operand" "")
15842 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15843 (match_operand:DF 2 "nonimmediate_operand" ""))
15844 (match_operand:DF 3 "register_operand" "")
15845 (match_operand:DF 4 "nonimmediate_operand" "")))
15846 (clobber (reg:CC 17))]
15847 "SSE_REG_P (operands[0]) && reload_completed
15848 && ((operands_match_p (operands[1], operands[3])
15849 && operands_match_p (operands[2], operands[4]))
15850 || (operands_match_p (operands[1], operands[4])
15851 && operands_match_p (operands[2], operands[3])))"
15852 [(set (match_dup 0)
15853 (if_then_else:DF (lt (match_dup 1)
15858 ;; We can't represent the LT test directly. Do this by swapping the operands.
15860 [(set (match_operand:DF 0 "register_operand" "")
15861 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15862 (match_operand:DF 2 "register_operand" ""))
15863 (match_operand:DF 3 "register_operand" "")
15864 (match_operand:DF 4 "register_operand" "")))
15865 (clobber (reg:CC 17))]
15866 "FP_REG_P (operands[0]) && reload_completed
15867 && ((operands_match_p (operands[1], operands[3])
15868 && operands_match_p (operands[2], operands[4]))
15869 || (operands_match_p (operands[1], operands[4])
15870 && operands_match_p (operands[2], operands[3])))"
15871 [(set (reg:CCFP 17)
15872 (compare:CCFP (match_dup 2)
15875 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
15879 (define_insn "*mindf_sse"
15880 [(set (match_operand:DF 0 "register_operand" "=Y")
15881 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
15882 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15885 "TARGET_SSE2 && reload_completed"
15886 "minsd\t{%2, %0|%0, %2}"
15887 [(set_attr "type" "sse")
15888 (set_attr "mode" "DF")])
15890 (define_expand "maxsf3"
15892 (set (match_operand:SF 0 "register_operand" "")
15893 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15894 (match_operand:SF 2 "nonimmediate_operand" ""))
15897 (clobber (reg:CC 17))])]
15901 (define_insn "*maxsf"
15902 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15903 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
15904 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
15907 (clobber (reg:CC 17))]
15908 "TARGET_SSE && TARGET_IEEE_FP"
15911 (define_insn "*maxsf_nonieee"
15912 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15913 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
15914 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15917 (clobber (reg:CC 17))]
15918 "TARGET_SSE && !TARGET_IEEE_FP"
15922 [(set (match_operand:SF 0 "register_operand" "")
15923 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15924 (match_operand:SF 2 "nonimmediate_operand" ""))
15925 (match_operand:SF 3 "register_operand" "")
15926 (match_operand:SF 4 "nonimmediate_operand" "")))
15927 (clobber (reg:CC 17))]
15928 "SSE_REG_P (operands[0]) && reload_completed
15929 && ((operands_match_p (operands[1], operands[3])
15930 && operands_match_p (operands[2], operands[4]))
15931 || (operands_match_p (operands[1], operands[4])
15932 && operands_match_p (operands[2], operands[3])))"
15933 [(set (match_dup 0)
15934 (if_then_else:SF (gt (match_dup 1)
15940 [(set (match_operand:SF 0 "register_operand" "")
15941 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15942 (match_operand:SF 2 "register_operand" ""))
15943 (match_operand:SF 3 "register_operand" "")
15944 (match_operand:SF 4 "register_operand" "")))
15945 (clobber (reg:CC 17))]
15946 "FP_REG_P (operands[0]) && reload_completed
15947 && ((operands_match_p (operands[1], operands[3])
15948 && operands_match_p (operands[2], operands[4]))
15949 || (operands_match_p (operands[1], operands[4])
15950 && operands_match_p (operands[2], operands[3])))"
15951 [(set (reg:CCFP 17)
15952 (compare:CCFP (match_dup 1)
15955 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
15959 (define_insn "*maxsf_sse"
15960 [(set (match_operand:SF 0 "register_operand" "=x")
15961 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
15962 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15965 "TARGET_SSE && reload_completed"
15966 "maxss\t{%2, %0|%0, %2}"
15967 [(set_attr "type" "sse")
15968 (set_attr "mode" "SF")])
15970 (define_expand "maxdf3"
15972 (set (match_operand:DF 0 "register_operand" "")
15973 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15974 (match_operand:DF 2 "nonimmediate_operand" ""))
15977 (clobber (reg:CC 17))])]
15981 (define_insn "*maxdf"
15982 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15983 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15984 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
15987 (clobber (reg:CC 17))]
15988 "TARGET_SSE2 && TARGET_IEEE_FP"
15991 (define_insn "*maxdf_nonieee"
15992 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15993 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
15994 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15997 (clobber (reg:CC 17))]
15998 "TARGET_SSE2 && !TARGET_IEEE_FP"
16002 [(set (match_operand:DF 0 "register_operand" "")
16003 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16004 (match_operand:DF 2 "nonimmediate_operand" ""))
16005 (match_operand:DF 3 "register_operand" "")
16006 (match_operand:DF 4 "nonimmediate_operand" "")))
16007 (clobber (reg:CC 17))]
16008 "SSE_REG_P (operands[0]) && reload_completed
16009 && ((operands_match_p (operands[1], operands[3])
16010 && operands_match_p (operands[2], operands[4]))
16011 || (operands_match_p (operands[1], operands[4])
16012 && operands_match_p (operands[2], operands[3])))"
16013 [(set (match_dup 0)
16014 (if_then_else:DF (gt (match_dup 1)
16020 [(set (match_operand:DF 0 "register_operand" "")
16021 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16022 (match_operand:DF 2 "register_operand" ""))
16023 (match_operand:DF 3 "register_operand" "")
16024 (match_operand:DF 4 "register_operand" "")))
16025 (clobber (reg:CC 17))]
16026 "FP_REG_P (operands[0]) && reload_completed
16027 && ((operands_match_p (operands[1], operands[3])
16028 && operands_match_p (operands[2], operands[4]))
16029 || (operands_match_p (operands[1], operands[4])
16030 && operands_match_p (operands[2], operands[3])))"
16031 [(set (reg:CCFP 17)
16032 (compare:CCFP (match_dup 1)
16035 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16039 (define_insn "*maxdf_sse"
16040 [(set (match_operand:DF 0 "register_operand" "=Y")
16041 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16042 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16045 "TARGET_SSE2 && reload_completed"
16046 "maxsd\t{%2, %0|%0, %2}"
16047 [(set_attr "type" "sse")
16048 (set_attr "mode" "DF")])
16050 ;; Misc patterns (?)
16052 ;; This pattern exists to put a dependancy on all ebp-based memory accesses.
16053 ;; Otherwise there will be nothing to keep
16055 ;; [(set (reg ebp) (reg esp))]
16056 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16057 ;; (clobber (eflags)]
16058 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16060 ;; in proper program order.
16061 (define_expand "pro_epilogue_adjust_stack"
16062 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
16063 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16064 (match_operand:SI 2 "immediate_operand" "i,i")))
16065 (clobber (reg:CC 17))
16066 (clobber (mem:BLK (scratch)))])]
16071 emit_insn (gen_pro_epilogue_adjust_stack_rex64
16072 (operands[0], operands[1], operands[2]));
16077 (define_insn "*pro_epilogue_adjust_stack_1"
16078 [(set (match_operand:SI 0 "register_operand" "=r,r")
16079 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16080 (match_operand:SI 2 "immediate_operand" "i,i")))
16081 (clobber (reg:CC 17))
16082 (clobber (mem:BLK (scratch)))]
16085 switch (get_attr_type (insn))
16088 return "mov{l}\t{%1, %0|%0, %1}";
16091 if (GET_CODE (operands[2]) == CONST_INT
16092 && (INTVAL (operands[2]) == 128
16093 || (INTVAL (operands[2]) < 0
16094 && INTVAL (operands[2]) != -128)))
16096 operands[2] = GEN_INT (-INTVAL (operands[2]));
16097 return "sub{l}\t{%2, %0|%0, %2}";
16099 return "add{l}\t{%2, %0|%0, %2}";
16102 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16103 return "lea{l}\t{%a2, %0|%0, %a2}";
16109 [(set (attr "type")
16110 (cond [(eq_attr "alternative" "0")
16111 (const_string "alu")
16112 (match_operand:SI 2 "const0_operand" "")
16113 (const_string "imov")
16115 (const_string "lea")))
16116 (set_attr "mode" "SI")])
16118 (define_insn "pro_epilogue_adjust_stack_rex64"
16119 [(set (match_operand:DI 0 "register_operand" "=r,r")
16120 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16121 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16122 (clobber (reg:CC 17))
16123 (clobber (mem:BLK (scratch)))]
16126 switch (get_attr_type (insn))
16129 return "mov{q}\t{%1, %0|%0, %1}";
16132 if (GET_CODE (operands[2]) == CONST_INT
16133 && (INTVAL (operands[2]) == 128
16134 || (INTVAL (operands[2]) < 0
16135 && INTVAL (operands[2]) != -128)))
16137 operands[2] = GEN_INT (-INTVAL (operands[2]));
16138 return "sub{q}\t{%2, %0|%0, %2}";
16140 return "add{q}\t{%2, %0|%0, %2}";
16143 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16144 return "lea{q}\t{%a2, %0|%0, %a2}";
16150 [(set (attr "type")
16151 (cond [(eq_attr "alternative" "0")
16152 (const_string "alu")
16153 (match_operand:DI 2 "const0_operand" "")
16154 (const_string "imov")
16156 (const_string "lea")))
16157 (set_attr "mode" "DI")])
16160 ;; Placeholder for the conditional moves. This one is split eighter to SSE
16161 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16162 ;; fact is that compares supported by the cmp??ss instructions are exactly
16163 ;; swapped of those supported by cmove sequence.
16164 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16165 ;; supported by i387 comparisons and we do need to emit two conditional moves
16168 (define_insn "sse_movsfcc"
16169 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16170 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16171 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16172 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16173 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16174 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16175 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16176 (clobber (reg:CC 17))]
16178 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16179 && (!TARGET_IEEE_FP
16180 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16183 (define_insn "sse_movsfcc_eq"
16184 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16185 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16186 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16187 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16188 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16189 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16190 (clobber (reg:CC 17))]
16192 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16195 (define_insn "sse_movdfcc"
16196 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16197 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16198 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16199 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16200 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16201 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16202 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16203 (clobber (reg:CC 17))]
16205 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16206 && (!TARGET_IEEE_FP
16207 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16210 (define_insn "sse_movdfcc_eq"
16211 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16212 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16213 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16214 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16215 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16216 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16217 (clobber (reg:CC 17))]
16219 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16222 ;; For non-sse moves just expand the usual cmove sequence.
16224 [(set (match_operand 0 "register_operand" "")
16225 (if_then_else (match_operator 1 "comparison_operator"
16226 [(match_operand 4 "nonimmediate_operand" "")
16227 (match_operand 5 "register_operand" "")])
16228 (match_operand 2 "nonimmediate_operand" "")
16229 (match_operand 3 "nonimmediate_operand" "")))
16230 (clobber (match_operand 6 "" ""))
16231 (clobber (reg:CC 17))]
16232 "!SSE_REG_P (operands[0]) && reload_completed
16233 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16236 ix86_compare_op0 = operands[5];
16237 ix86_compare_op1 = operands[4];
16238 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16239 VOIDmode, operands[5], operands[4]);
16240 ix86_expand_fp_movcc (operands);
16244 ;; Split SSE based conditional move into seqence:
16245 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16246 ;; and op2, op0 - zero op2 if comparison was false
16247 ;; nand op0, op3 - load op3 to op0 if comparison was false
16248 ;; or op2, op0 - get the non-zero one into the result.
16250 [(set (match_operand 0 "register_operand" "")
16251 (if_then_else (match_operator 1 "sse_comparison_operator"
16252 [(match_operand 4 "register_operand" "")
16253 (match_operand 5 "nonimmediate_operand" "")])
16254 (match_operand 2 "register_operand" "")
16255 (match_operand 3 "register_operand" "")))
16256 (clobber (match_operand 6 "" ""))
16257 (clobber (reg:CC 17))]
16258 "SSE_REG_P (operands[0]) && reload_completed"
16259 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16260 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16261 (subreg:TI (match_dup 4) 0)))
16262 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16263 (subreg:TI (match_dup 3) 0)))
16264 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16265 (subreg:TI (match_dup 7) 0)))]
16267 PUT_MODE (operands[1], GET_MODE (operands[0]));
16268 if (operands_match_p (operands[0], operands[4]))
16269 operands[6] = operands[4], operands[7] = operands[2];
16271 operands[6] = operands[2], operands[7] = operands[4];
16274 ;; Special case of conditional move we can handle effectivly.
16275 ;; Do not brother with the integer/floating point case, since these are
16276 ;; bot considerably slower, unlike in the generic case.
16277 (define_insn "*sse_movsfcc_const0_1"
16278 [(set (match_operand:SF 0 "register_operand" "=x")
16279 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16280 [(match_operand:SF 4 "register_operand" "0")
16281 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16282 (match_operand:SF 2 "register_operand" "x")
16283 (match_operand:SF 3 "const0_operand" "X")))]
16287 (define_insn "*sse_movsfcc_const0_2"
16288 [(set (match_operand:SF 0 "register_operand" "=x")
16289 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16290 [(match_operand:SF 4 "register_operand" "0")
16291 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16292 (match_operand:SF 2 "const0_operand" "x")
16293 (match_operand:SF 3 "register_operand" "X")))]
16297 (define_insn "*sse_movsfcc_const0_3"
16298 [(set (match_operand:SF 0 "register_operand" "=x")
16299 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16300 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16301 (match_operand:SF 5 "register_operand" "0")])
16302 (match_operand:SF 2 "register_operand" "x")
16303 (match_operand:SF 3 "const0_operand" "X")))]
16307 (define_insn "*sse_movsfcc_const0_4"
16308 [(set (match_operand:SF 0 "register_operand" "=x")
16309 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16310 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16311 (match_operand:SF 5 "register_operand" "0")])
16312 (match_operand:SF 2 "const0_operand" "x")
16313 (match_operand:SF 3 "register_operand" "X")))]
16317 (define_insn "*sse_movdfcc_const0_1"
16318 [(set (match_operand:SF 0 "register_operand" "=x")
16319 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16320 [(match_operand:SF 4 "register_operand" "0")
16321 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16322 (match_operand:SF 2 "register_operand" "x")
16323 (match_operand:SF 3 "const0_operand" "X")))]
16327 (define_insn "*sse_movdfcc_const0_2"
16328 [(set (match_operand:SF 0 "register_operand" "=x")
16329 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16330 [(match_operand:SF 4 "register_operand" "0")
16331 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16332 (match_operand:SF 2 "const0_operand" "x")
16333 (match_operand:SF 3 "register_operand" "X")))]
16337 (define_insn "*sse_movdfcc_const0_3"
16338 [(set (match_operand:SF 0 "register_operand" "=x")
16339 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16340 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16341 (match_operand:SF 5 "register_operand" "0")])
16342 (match_operand:SF 2 "register_operand" "x")
16343 (match_operand:SF 3 "const0_operand" "X")))]
16347 (define_insn "*sse_movdfcc_const0_4"
16348 [(set (match_operand:SF 0 "register_operand" "=x")
16349 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16350 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16351 (match_operand:SF 5 "register_operand" "0")])
16352 (match_operand:SF 2 "const0_operand" "x")
16353 (match_operand:SF 3 "register_operand" "X")))]
16358 [(set (match_operand 0 "register_operand" "")
16359 (if_then_else (match_operator 1 "comparison_operator"
16360 [(match_operand 4 "register_operand" "")
16361 (match_operand 5 "nonimmediate_operand" "")])
16362 (match_operand 2 "nonmemory_operand" "")
16363 (match_operand 3 "nonmemory_operand" "")))]
16364 "SSE_REG_P (operands[0]) && reload_completed
16365 && (const0_operand (operands[2], GET_MODE (operands[0]))
16366 || const0_operand (operands[3], GET_MODE (operands[0])))"
16367 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16368 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16369 (subreg:TI (match_dup 7) 0)))]
16371 PUT_MODE (operands[1], GET_MODE (operands[0]));
16372 if (!sse_comparison_operator (operands[1], VOIDmode))
16374 rtx tmp = operands[5];
16375 operands[5] = operands[4];
16377 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16379 if (const0_operand (operands[2], GET_MODE (operands[0])))
16381 operands[7] = operands[3];
16382 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16387 operands[7] = operands[2];
16388 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16392 (define_expand "allocate_stack_worker"
16393 [(match_operand:SI 0 "register_operand" "")]
16394 "TARGET_STACK_PROBE"
16397 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16399 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16403 (define_insn "allocate_stack_worker_1"
16404 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
16405 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16406 (clobber (match_dup 0))
16407 (clobber (reg:CC 17))]
16408 "TARGET_STACK_PROBE && !TARGET_64BIT"
16410 [(set_attr "type" "multi")
16411 (set_attr "length" "5")])
16413 (define_insn "allocate_stack_worker_rex64"
16414 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
16415 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16416 (clobber (match_dup 0))
16417 (clobber (reg:CC 17))]
16418 "TARGET_STACK_PROBE && TARGET_64BIT"
16420 [(set_attr "type" "multi")
16421 (set_attr "length" "5")])
16423 (define_expand "allocate_stack"
16424 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16425 (minus:SI (reg:SI 7)
16426 (match_operand:SI 1 "general_operand" "")))
16427 (clobber (reg:CC 17))])
16428 (parallel [(set (reg:SI 7)
16429 (minus:SI (reg:SI 7) (match_dup 1)))
16430 (clobber (reg:CC 17))])]
16431 "TARGET_STACK_PROBE"
16433 #ifdef CHECK_STACK_LIMIT
16434 if (GET_CODE (operands[1]) == CONST_INT
16435 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16436 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16440 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16443 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16447 (define_expand "builtin_setjmp_receiver"
16448 [(label_ref (match_operand 0 "" ""))]
16449 "flag_pic && !TARGET_64BIT"
16451 load_pic_register ();
16455 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16458 [(set (match_operand 0 "register_operand" "")
16459 (match_operator 3 "promotable_binary_operator"
16460 [(match_operand 1 "register_operand" "")
16461 (match_operand 2 "aligned_operand" "")]))
16462 (clobber (reg:CC 17))]
16463 "! TARGET_PARTIAL_REG_STALL && reload_completed
16464 && ((GET_MODE (operands[0]) == HImode
16465 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
16466 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16467 || (GET_MODE (operands[0]) == QImode
16468 && (TARGET_PROMOTE_QImode || optimize_size)))"
16469 [(parallel [(set (match_dup 0)
16470 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16471 (clobber (reg:CC 17))])]
16472 "operands[0] = gen_lowpart (SImode, operands[0]);
16473 operands[1] = gen_lowpart (SImode, operands[1]);
16474 if (GET_CODE (operands[3]) != ASHIFT)
16475 operands[2] = gen_lowpart (SImode, operands[2]);
16476 PUT_MODE (operands[3], SImode);")
16480 (compare (and (match_operand 1 "aligned_operand" "")
16481 (match_operand 2 "const_int_operand" ""))
16483 (set (match_operand 0 "register_operand" "")
16484 (and (match_dup 1) (match_dup 2)))]
16485 "! TARGET_PARTIAL_REG_STALL && reload_completed
16486 && ix86_match_ccmode (insn, CCNOmode)
16487 && (GET_MODE (operands[0]) == HImode
16488 || (GET_MODE (operands[0]) == QImode
16489 && (TARGET_PROMOTE_QImode || optimize_size)))"
16490 [(parallel [(set (reg:CCNO 17)
16491 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16494 (and:SI (match_dup 1) (match_dup 2)))])]
16496 = GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
16497 & GET_MODE_MASK (GET_MODE (operands[0])),
16499 operands[0] = gen_lowpart (SImode, operands[0]);
16500 operands[1] = gen_lowpart (SImode, operands[1]);")
16504 (compare (and (match_operand 0 "aligned_operand" "")
16505 (match_operand 1 "const_int_operand" ""))
16507 "! TARGET_PARTIAL_REG_STALL && reload_completed
16508 && ix86_match_ccmode (insn, CCNOmode)
16509 && (GET_MODE (operands[0]) == HImode
16510 || (GET_MODE (operands[0]) == QImode
16511 && (TARGET_PROMOTE_QImode || optimize_size)))"
16512 [(set (reg:CCNO 17)
16513 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16516 = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
16517 & GET_MODE_MASK (GET_MODE (operands[0])),
16519 operands[0] = gen_lowpart (SImode, operands[0]);")
16522 [(set (match_operand 0 "register_operand" "")
16523 (neg (match_operand 1 "register_operand" "")))
16524 (clobber (reg:CC 17))]
16525 "! TARGET_PARTIAL_REG_STALL && reload_completed
16526 && (GET_MODE (operands[0]) == HImode
16527 || (GET_MODE (operands[0]) == QImode
16528 && (TARGET_PROMOTE_QImode || optimize_size)))"
16529 [(parallel [(set (match_dup 0)
16530 (neg:SI (match_dup 1)))
16531 (clobber (reg:CC 17))])]
16532 "operands[0] = gen_lowpart (SImode, operands[0]);
16533 operands[1] = gen_lowpart (SImode, operands[1]);")
16536 [(set (match_operand 0 "register_operand" "")
16537 (not (match_operand 1 "register_operand" "")))]
16538 "! TARGET_PARTIAL_REG_STALL && reload_completed
16539 && (GET_MODE (operands[0]) == HImode
16540 || (GET_MODE (operands[0]) == QImode
16541 && (TARGET_PROMOTE_QImode || optimize_size)))"
16542 [(set (match_dup 0)
16543 (not:SI (match_dup 1)))]
16544 "operands[0] = gen_lowpart (SImode, operands[0]);
16545 operands[1] = gen_lowpart (SImode, operands[1]);")
16548 [(set (match_operand 0 "register_operand" "")
16549 (if_then_else (match_operator 1 "comparison_operator"
16550 [(reg 17) (const_int 0)])
16551 (match_operand 2 "register_operand" "")
16552 (match_operand 3 "register_operand" "")))]
16553 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16554 && (GET_MODE (operands[0]) == HImode
16555 || (GET_MODE (operands[0]) == QImode
16556 && (TARGET_PROMOTE_QImode || optimize_size)))"
16557 [(set (match_dup 0)
16558 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16559 "operands[0] = gen_lowpart (SImode, operands[0]);
16560 operands[2] = gen_lowpart (SImode, operands[2]);
16561 operands[3] = gen_lowpart (SImode, operands[3]);")
16564 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16565 ;; transform a complex memory operation into two memory to register operations.
16567 ;; Don't push memory operands
16569 [(set (match_operand:SI 0 "push_operand" "")
16570 (match_operand:SI 1 "memory_operand" ""))
16571 (match_scratch:SI 2 "r")]
16572 "! optimize_size && ! TARGET_PUSH_MEMORY"
16573 [(set (match_dup 2) (match_dup 1))
16574 (set (match_dup 0) (match_dup 2))]
16578 [(set (match_operand:DI 0 "push_operand" "")
16579 (match_operand:DI 1 "memory_operand" ""))
16580 (match_scratch:DI 2 "r")]
16581 "! optimize_size && ! TARGET_PUSH_MEMORY"
16582 [(set (match_dup 2) (match_dup 1))
16583 (set (match_dup 0) (match_dup 2))]
16586 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16589 [(set (match_operand:SF 0 "push_operand" "")
16590 (match_operand:SF 1 "memory_operand" ""))
16591 (match_scratch:SF 2 "r")]
16592 "! optimize_size && ! TARGET_PUSH_MEMORY"
16593 [(set (match_dup 2) (match_dup 1))
16594 (set (match_dup 0) (match_dup 2))]
16598 [(set (match_operand:HI 0 "push_operand" "")
16599 (match_operand:HI 1 "memory_operand" ""))
16600 (match_scratch:HI 2 "r")]
16601 "! optimize_size && ! TARGET_PUSH_MEMORY"
16602 [(set (match_dup 2) (match_dup 1))
16603 (set (match_dup 0) (match_dup 2))]
16607 [(set (match_operand:QI 0 "push_operand" "")
16608 (match_operand:QI 1 "memory_operand" ""))
16609 (match_scratch:QI 2 "q")]
16610 "! optimize_size && ! TARGET_PUSH_MEMORY"
16611 [(set (match_dup 2) (match_dup 1))
16612 (set (match_dup 0) (match_dup 2))]
16615 ;; Don't move an immediate directly to memory when the instruction
16618 [(match_scratch:SI 1 "r")
16619 (set (match_operand:SI 0 "memory_operand" "")
16622 && ! TARGET_USE_MOV0
16623 && TARGET_SPLIT_LONG_MOVES
16624 && get_attr_length (insn) >= ix86_cost->large_insn
16625 && peep2_regno_dead_p (0, FLAGS_REG)"
16626 [(parallel [(set (match_dup 1) (const_int 0))
16627 (clobber (reg:CC 17))])
16628 (set (match_dup 0) (match_dup 1))]
16632 [(match_scratch:HI 1 "r")
16633 (set (match_operand:HI 0 "memory_operand" "")
16636 && ! TARGET_USE_MOV0
16637 && TARGET_SPLIT_LONG_MOVES
16638 && get_attr_length (insn) >= ix86_cost->large_insn
16639 && peep2_regno_dead_p (0, FLAGS_REG)"
16640 [(parallel [(set (match_dup 2) (const_int 0))
16641 (clobber (reg:CC 17))])
16642 (set (match_dup 0) (match_dup 1))]
16643 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16646 [(match_scratch:QI 1 "q")
16647 (set (match_operand:QI 0 "memory_operand" "")
16650 && ! TARGET_USE_MOV0
16651 && TARGET_SPLIT_LONG_MOVES
16652 && get_attr_length (insn) >= ix86_cost->large_insn
16653 && peep2_regno_dead_p (0, FLAGS_REG)"
16654 [(parallel [(set (match_dup 2) (const_int 0))
16655 (clobber (reg:CC 17))])
16656 (set (match_dup 0) (match_dup 1))]
16657 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16660 [(match_scratch:SI 2 "r")
16661 (set (match_operand:SI 0 "memory_operand" "")
16662 (match_operand:SI 1 "immediate_operand" ""))]
16664 && get_attr_length (insn) >= ix86_cost->large_insn
16665 && TARGET_SPLIT_LONG_MOVES"
16666 [(set (match_dup 2) (match_dup 1))
16667 (set (match_dup 0) (match_dup 2))]
16671 [(match_scratch:HI 2 "r")
16672 (set (match_operand:HI 0 "memory_operand" "")
16673 (match_operand:HI 1 "immediate_operand" ""))]
16674 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16675 && TARGET_SPLIT_LONG_MOVES"
16676 [(set (match_dup 2) (match_dup 1))
16677 (set (match_dup 0) (match_dup 2))]
16681 [(match_scratch:QI 2 "q")
16682 (set (match_operand:QI 0 "memory_operand" "")
16683 (match_operand:QI 1 "immediate_operand" ""))]
16684 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16685 && TARGET_SPLIT_LONG_MOVES"
16686 [(set (match_dup 2) (match_dup 1))
16687 (set (match_dup 0) (match_dup 2))]
16690 ;; Don't compare memory with zero, load and use a test instead.
16693 (compare (match_operand:SI 0 "memory_operand" "")
16695 (match_scratch:SI 3 "r")]
16696 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
16697 [(set (match_dup 3) (match_dup 0))
16698 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
16701 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16702 ;; Don't split NOTs with a displacement operand, because resulting XOR
16703 ;; will not be pariable anyway.
16705 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
16706 ;; represented using a modRM byte. The XOR replacement is long decoded,
16707 ;; so this split helps here as well.
16709 ;; Note: Can't do this as a regular split because we can't get proper
16710 ;; lifetime information then.
16713 [(set (match_operand:SI 0 "nonimmediate_operand" "")
16714 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
16716 && peep2_regno_dead_p (0, FLAGS_REG)
16717 && ((TARGET_PENTIUM
16718 && (GET_CODE (operands[0]) != MEM
16719 || !memory_displacement_operand (operands[0], SImode)))
16720 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
16721 [(parallel [(set (match_dup 0)
16722 (xor:SI (match_dup 1) (const_int -1)))
16723 (clobber (reg:CC 17))])]
16727 [(set (match_operand:HI 0 "nonimmediate_operand" "")
16728 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
16730 && peep2_regno_dead_p (0, FLAGS_REG)
16731 && ((TARGET_PENTIUM
16732 && (GET_CODE (operands[0]) != MEM
16733 || !memory_displacement_operand (operands[0], HImode)))
16734 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
16735 [(parallel [(set (match_dup 0)
16736 (xor:HI (match_dup 1) (const_int -1)))
16737 (clobber (reg:CC 17))])]
16741 [(set (match_operand:QI 0 "nonimmediate_operand" "")
16742 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
16744 && peep2_regno_dead_p (0, FLAGS_REG)
16745 && ((TARGET_PENTIUM
16746 && (GET_CODE (operands[0]) != MEM
16747 || !memory_displacement_operand (operands[0], QImode)))
16748 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
16749 [(parallel [(set (match_dup 0)
16750 (xor:QI (match_dup 1) (const_int -1)))
16751 (clobber (reg:CC 17))])]
16754 ;; Non pairable "test imm, reg" instructions can be translated to
16755 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
16756 ;; byte opcode instead of two, have a short form for byte operands),
16757 ;; so do it for other CPUs as well. Given that the value was dead,
16758 ;; this should not create any new dependancies. Pass on the sub-word
16759 ;; versions if we're concerned about partial register stalls.
16763 (compare (and:SI (match_operand:SI 0 "register_operand" "")
16764 (match_operand:SI 1 "immediate_operand" ""))
16766 "ix86_match_ccmode (insn, CCNOmode)
16767 && (true_regnum (operands[0]) != 0
16768 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
16769 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16771 [(set (reg:CCNO 17)
16772 (compare:CCNO (and:SI (match_dup 0)
16776 (and:SI (match_dup 0) (match_dup 1)))])]
16779 ;; We don't need to handle HImode case, because it will be promoted to SImode
16780 ;; on ! TARGET_PARTIAL_REG_STALL
16784 (compare (and:QI (match_operand:QI 0 "register_operand" "")
16785 (match_operand:QI 1 "immediate_operand" ""))
16787 "! TARGET_PARTIAL_REG_STALL
16788 && ix86_match_ccmode (insn, CCNOmode)
16789 && true_regnum (operands[0]) != 0
16790 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16792 [(set (reg:CCNO 17)
16793 (compare:CCNO (and:QI (match_dup 0)
16797 (and:QI (match_dup 0) (match_dup 1)))])]
16805 (match_operand 0 "ext_register_operand" "")
16808 (match_operand 1 "const_int_operand" ""))
16810 "! TARGET_PARTIAL_REG_STALL
16811 && ix86_match_ccmode (insn, CCNOmode)
16812 && true_regnum (operands[0]) != 0
16813 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16814 [(parallel [(set (reg:CCNO 17)
16823 (set (zero_extract:SI (match_dup 0)
16834 ;; Don't do logical operations with memory inputs.
16836 [(match_scratch:SI 2 "r")
16837 (parallel [(set (match_operand:SI 0 "register_operand" "")
16838 (match_operator:SI 3 "arith_or_logical_operator"
16840 (match_operand:SI 1 "memory_operand" "")]))
16841 (clobber (reg:CC 17))])]
16842 "! optimize_size && ! TARGET_READ_MODIFY"
16843 [(set (match_dup 2) (match_dup 1))
16844 (parallel [(set (match_dup 0)
16845 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
16846 (clobber (reg:CC 17))])]
16850 [(match_scratch:SI 2 "r")
16851 (parallel [(set (match_operand:SI 0 "register_operand" "")
16852 (match_operator:SI 3 "arith_or_logical_operator"
16853 [(match_operand:SI 1 "memory_operand" "")
16855 (clobber (reg:CC 17))])]
16856 "! optimize_size && ! TARGET_READ_MODIFY"
16857 [(set (match_dup 2) (match_dup 1))
16858 (parallel [(set (match_dup 0)
16859 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
16860 (clobber (reg:CC 17))])]
16863 ; Don't do logical operations with memory outputs
16865 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
16866 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
16867 ; the same decoder scheduling characteristics as the original.
16870 [(match_scratch:SI 2 "r")
16871 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16872 (match_operator:SI 3 "arith_or_logical_operator"
16874 (match_operand:SI 1 "nonmemory_operand" "")]))
16875 (clobber (reg:CC 17))])]
16876 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16877 [(set (match_dup 2) (match_dup 0))
16878 (parallel [(set (match_dup 2)
16879 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
16880 (clobber (reg:CC 17))])
16881 (set (match_dup 0) (match_dup 2))]
16885 [(match_scratch:SI 2 "r")
16886 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16887 (match_operator:SI 3 "arith_or_logical_operator"
16888 [(match_operand:SI 1 "nonmemory_operand" "")
16890 (clobber (reg:CC 17))])]
16891 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16892 [(set (match_dup 2) (match_dup 0))
16893 (parallel [(set (match_dup 2)
16894 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16895 (clobber (reg:CC 17))])
16896 (set (match_dup 0) (match_dup 2))]
16899 ;; Attempt to always use XOR for zeroing registers.
16901 [(set (match_operand 0 "register_operand" "")
16903 "(GET_MODE (operands[0]) == QImode
16904 || GET_MODE (operands[0]) == HImode
16905 || GET_MODE (operands[0]) == SImode
16906 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16907 && (! TARGET_USE_MOV0 || optimize_size)
16908 && peep2_regno_dead_p (0, FLAGS_REG)"
16909 [(parallel [(set (match_dup 0) (const_int 0))
16910 (clobber (reg:CC 17))])]
16911 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16912 true_regnum (operands[0]));")
16915 [(set (strict_low_part (match_operand 0 "register_operand" ""))
16917 "(GET_MODE (operands[0]) == QImode
16918 || GET_MODE (operands[0]) == HImode)
16919 && (! TARGET_USE_MOV0 || optimize_size)
16920 && peep2_regno_dead_p (0, FLAGS_REG)"
16921 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
16922 (clobber (reg:CC 17))])])
16924 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
16926 [(set (match_operand 0 "register_operand" "")
16928 "(GET_MODE (operands[0]) == HImode
16929 || GET_MODE (operands[0]) == SImode
16930 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16931 && (optimize_size || TARGET_PENTIUM)
16932 && peep2_regno_dead_p (0, FLAGS_REG)"
16933 [(parallel [(set (match_dup 0) (const_int -1))
16934 (clobber (reg:CC 17))])]
16935 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16936 true_regnum (operands[0]));")
16938 ;; Attempt to convert simple leas to adds. These can be created by
16941 [(set (match_operand:SI 0 "register_operand" "")
16942 (plus:SI (match_dup 0)
16943 (match_operand:SI 1 "nonmemory_operand" "")))]
16944 "peep2_regno_dead_p (0, FLAGS_REG)"
16945 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
16946 (clobber (reg:CC 17))])]
16950 [(set (match_operand:SI 0 "register_operand" "")
16951 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
16952 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
16953 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
16954 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
16955 (clobber (reg:CC 17))])]
16956 "operands[2] = gen_lowpart (SImode, operands[2]);")
16959 [(set (match_operand:DI 0 "register_operand" "")
16960 (plus:DI (match_dup 0)
16961 (match_operand:DI 1 "x86_64_general_operand" "")))]
16962 "peep2_regno_dead_p (0, FLAGS_REG)"
16963 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
16964 (clobber (reg:CC 17))])]
16968 [(set (match_operand:SI 0 "register_operand" "")
16969 (mult:SI (match_dup 0)
16970 (match_operand:SI 1 "const_int_operand" "")))]
16971 "exact_log2 (INTVAL (operands[1])) >= 0
16972 && peep2_regno_dead_p (0, FLAGS_REG)"
16973 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16974 (clobber (reg:CC 17))])]
16975 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16978 [(set (match_operand:DI 0 "register_operand" "")
16979 (mult:DI (match_dup 0)
16980 (match_operand:DI 1 "const_int_operand" "")))]
16981 "exact_log2 (INTVAL (operands[1])) >= 0
16982 && peep2_regno_dead_p (0, FLAGS_REG)"
16983 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
16984 (clobber (reg:CC 17))])]
16985 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16988 [(set (match_operand:SI 0 "register_operand" "")
16989 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
16990 (match_operand:DI 2 "const_int_operand" "")) 0))]
16991 "exact_log2 (INTVAL (operands[1])) >= 0
16992 && REGNO (operands[0]) == REGNO (operands[1])
16993 && peep2_regno_dead_p (0, FLAGS_REG)"
16994 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16995 (clobber (reg:CC 17))])]
16996 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
16998 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
16999 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17000 ;; many CPUs it is also faster, since special hardware to avoid esp
17001 ;; dependancies is present.
17003 ;; While some of these converisons may be done using splitters, we use peepholes
17004 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17006 ;; Convert prologue esp substractions to push.
17007 ;; We need register to push. In order to keep verify_flow_info happy we have
17009 ;; - use scratch and clobber it in order to avoid dependencies
17010 ;; - use already live register
17011 ;; We can't use the second way right now, since there is no reliable way how to
17012 ;; verify that given register is live. First choice will also most likely in
17013 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17014 ;; call clobbered registers are dead. We may want to use base pointer as an
17015 ;; alternative when no register is available later.
17018 [(match_scratch:SI 0 "r")
17019 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17020 (clobber (reg:CC 17))
17021 (clobber (mem:BLK (scratch)))])]
17022 "optimize_size || !TARGET_SUB_ESP_4"
17023 [(clobber (match_dup 0))
17024 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17025 (clobber (mem:BLK (scratch)))])])
17028 [(match_scratch:SI 0 "r")
17029 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17030 (clobber (reg:CC 17))
17031 (clobber (mem:BLK (scratch)))])]
17032 "optimize_size || !TARGET_SUB_ESP_8"
17033 [(clobber (match_dup 0))
17034 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17035 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17036 (clobber (mem:BLK (scratch)))])])
17038 ;; Convert esp substractions to push.
17040 [(match_scratch:SI 0 "r")
17041 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17042 (clobber (reg:CC 17))])]
17043 "optimize_size || !TARGET_SUB_ESP_4"
17044 [(clobber (match_dup 0))
17045 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17048 [(match_scratch:SI 0 "r")
17049 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17050 (clobber (reg:CC 17))])]
17051 "optimize_size || !TARGET_SUB_ESP_8"
17052 [(clobber (match_dup 0))
17053 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17054 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17056 ;; Convert epilogue deallocator to pop.
17058 [(match_scratch:SI 0 "r")
17059 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17060 (clobber (reg:CC 17))
17061 (clobber (mem:BLK (scratch)))])]
17062 "optimize_size || !TARGET_ADD_ESP_4"
17063 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17064 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17065 (clobber (mem:BLK (scratch)))])]
17068 ;; Two pops case is tricky, since pop causes dependency on destination register.
17069 ;; We use two registers if available.
17071 [(match_scratch:SI 0 "r")
17072 (match_scratch:SI 1 "r")
17073 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17074 (clobber (reg:CC 17))
17075 (clobber (mem:BLK (scratch)))])]
17076 "optimize_size || !TARGET_ADD_ESP_8"
17077 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17078 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17079 (clobber (mem:BLK (scratch)))])
17080 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17081 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17085 [(match_scratch:SI 0 "r")
17086 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17087 (clobber (reg:CC 17))
17088 (clobber (mem:BLK (scratch)))])]
17090 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17091 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17092 (clobber (mem:BLK (scratch)))])
17093 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17094 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17097 ;; Convert esp additions to pop.
17099 [(match_scratch:SI 0 "r")
17100 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17101 (clobber (reg:CC 17))])]
17103 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17104 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17107 ;; Two pops case is tricky, since pop causes dependency on destination register.
17108 ;; We use two registers if available.
17110 [(match_scratch:SI 0 "r")
17111 (match_scratch:SI 1 "r")
17112 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17113 (clobber (reg:CC 17))])]
17115 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17116 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17117 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17118 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17122 [(match_scratch:SI 0 "r")
17123 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17124 (clobber (reg:CC 17))])]
17126 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17127 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17128 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17129 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17132 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17133 ;; required and register dies.
17136 (compare (match_operand:SI 0 "register_operand" "")
17137 (match_operand:SI 1 "incdec_operand" "")))]
17138 "ix86_match_ccmode (insn, CCGCmode)
17139 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17140 [(parallel [(set (reg:CCGC 17)
17141 (compare:CCGC (match_dup 0)
17143 (clobber (match_dup 0))])]
17148 (compare (match_operand:HI 0 "register_operand" "")
17149 (match_operand:HI 1 "incdec_operand" "")))]
17150 "ix86_match_ccmode (insn, CCGCmode)
17151 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17152 [(parallel [(set (reg:CCGC 17)
17153 (compare:CCGC (match_dup 0)
17155 (clobber (match_dup 0))])]
17160 (compare (match_operand:QI 0 "register_operand" "")
17161 (match_operand:QI 1 "incdec_operand" "")))]
17162 "ix86_match_ccmode (insn, CCGCmode)
17163 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17164 [(parallel [(set (reg:CCGC 17)
17165 (compare:CCGC (match_dup 0)
17167 (clobber (match_dup 0))])]
17170 ;; Convert compares with 128 to shorter add -128
17173 (compare (match_operand:SI 0 "register_operand" "")
17175 "ix86_match_ccmode (insn, CCGCmode)
17176 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17177 [(parallel [(set (reg:CCGC 17)
17178 (compare:CCGC (match_dup 0)
17180 (clobber (match_dup 0))])]
17185 (compare (match_operand:HI 0 "register_operand" "")
17187 "ix86_match_ccmode (insn, CCGCmode)
17188 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17189 [(parallel [(set (reg:CCGC 17)
17190 (compare:CCGC (match_dup 0)
17192 (clobber (match_dup 0))])]
17196 [(match_scratch:DI 0 "r")
17197 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17198 (clobber (reg:CC 17))
17199 (clobber (mem:BLK (scratch)))])]
17200 "optimize_size || !TARGET_SUB_ESP_4"
17201 [(clobber (match_dup 0))
17202 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17203 (clobber (mem:BLK (scratch)))])])
17206 [(match_scratch:DI 0 "r")
17207 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17208 (clobber (reg:CC 17))
17209 (clobber (mem:BLK (scratch)))])]
17210 "optimize_size || !TARGET_SUB_ESP_8"
17211 [(clobber (match_dup 0))
17212 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17213 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17214 (clobber (mem:BLK (scratch)))])])
17216 ;; Convert esp substractions to push.
17218 [(match_scratch:DI 0 "r")
17219 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17220 (clobber (reg:CC 17))])]
17221 "optimize_size || !TARGET_SUB_ESP_4"
17222 [(clobber (match_dup 0))
17223 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17226 [(match_scratch:DI 0 "r")
17227 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17228 (clobber (reg:CC 17))])]
17229 "optimize_size || !TARGET_SUB_ESP_8"
17230 [(clobber (match_dup 0))
17231 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17232 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17234 ;; Convert epilogue deallocator to pop.
17236 [(match_scratch:DI 0 "r")
17237 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17238 (clobber (reg:CC 17))
17239 (clobber (mem:BLK (scratch)))])]
17240 "optimize_size || !TARGET_ADD_ESP_4"
17241 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17242 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17243 (clobber (mem:BLK (scratch)))])]
17246 ;; Two pops case is tricky, since pop causes dependency on destination register.
17247 ;; We use two registers if available.
17249 [(match_scratch:DI 0 "r")
17250 (match_scratch:DI 1 "r")
17251 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17252 (clobber (reg:CC 17))
17253 (clobber (mem:BLK (scratch)))])]
17254 "optimize_size || !TARGET_ADD_ESP_8"
17255 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17256 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17257 (clobber (mem:BLK (scratch)))])
17258 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17259 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17263 [(match_scratch:DI 0 "r")
17264 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17265 (clobber (reg:CC 17))
17266 (clobber (mem:BLK (scratch)))])]
17268 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17269 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17270 (clobber (mem:BLK (scratch)))])
17271 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17272 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17275 ;; Convert esp additions to pop.
17277 [(match_scratch:DI 0 "r")
17278 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17279 (clobber (reg:CC 17))])]
17281 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17282 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17285 ;; Two pops case is tricky, since pop causes dependency on destination register.
17286 ;; We use two registers if available.
17288 [(match_scratch:DI 0 "r")
17289 (match_scratch:DI 1 "r")
17290 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17291 (clobber (reg:CC 17))])]
17293 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17294 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17295 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17296 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17300 [(match_scratch:DI 0 "r")
17301 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17302 (clobber (reg:CC 17))])]
17304 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17305 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17306 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17307 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17310 ;; Call-value patterns last so that the wildcard operand does not
17311 ;; disrupt insn-recog's switch tables.
17313 (define_insn "*call_value_pop_0"
17314 [(set (match_operand 0 "" "")
17315 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17316 (match_operand:SI 2 "" "")))
17317 (set (reg:SI 7) (plus:SI (reg:SI 7)
17318 (match_operand:SI 3 "immediate_operand" "")))]
17321 if (SIBLING_CALL_P (insn))
17324 return "call\t%P1";
17326 [(set_attr "type" "callv")])
17328 (define_insn "*call_value_pop_1"
17329 [(set (match_operand 0 "" "")
17330 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17331 (match_operand:SI 2 "" "")))
17332 (set (reg:SI 7) (plus:SI (reg:SI 7)
17333 (match_operand:SI 3 "immediate_operand" "i")))]
17336 if (constant_call_address_operand (operands[1], QImode))
17338 if (SIBLING_CALL_P (insn))
17341 return "call\t%P1";
17343 if (SIBLING_CALL_P (insn))
17346 return "call\t%A1";
17348 [(set_attr "type" "callv")])
17350 (define_insn "*call_value_0"
17351 [(set (match_operand 0 "" "")
17352 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17353 (match_operand:SI 2 "" "")))]
17356 if (SIBLING_CALL_P (insn))
17359 return "call\t%P1";
17361 [(set_attr "type" "callv")])
17363 (define_insn "*call_value_0_rex64"
17364 [(set (match_operand 0 "" "")
17365 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17366 (match_operand:DI 2 "const_int_operand" "")))]
17369 if (SIBLING_CALL_P (insn))
17372 return "call\t%P1";
17374 [(set_attr "type" "callv")])
17376 (define_insn "*call_value_1"
17377 [(set (match_operand 0 "" "")
17378 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17379 (match_operand:SI 2 "" "")))]
17382 if (constant_call_address_operand (operands[1], QImode))
17384 if (SIBLING_CALL_P (insn))
17387 return "call\t%P1";
17389 if (SIBLING_CALL_P (insn))
17390 return "jmp\t%*%1";
17392 return "call\t%*%1";
17394 [(set_attr "type" "callv")])
17396 (define_insn "*call_value_1_rex64"
17397 [(set (match_operand 0 "" "")
17398 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17399 (match_operand:DI 2 "" "")))]
17402 if (constant_call_address_operand (operands[1], QImode))
17404 if (SIBLING_CALL_P (insn))
17407 return "call\t%P1";
17409 if (SIBLING_CALL_P (insn))
17412 return "call\t%A1";
17414 [(set_attr "type" "callv")])
17416 (define_insn "trap"
17417 [(trap_if (const_int 1) (const_int 5))]
17421 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17422 ;;; for the sake of bounds checking. By emitting bounds checks as
17423 ;;; conditional traps rather than as conditional jumps around
17424 ;;; unconditional traps we avoid introducing spurious basic-block
17425 ;;; boundaries and facilitate elimination of redundant checks. In
17426 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17429 ;;; FIXME: Static branch prediction rules for ix86 are such that
17430 ;;; forward conditional branches predict as untaken. As implemented
17431 ;;; below, pseudo conditional traps violate that rule. We should use
17432 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17433 ;;; section loaded at the end of the text segment and branch forward
17434 ;;; there on bounds-failure, and then jump back immediately (in case
17435 ;;; the system chooses to ignore bounds violations, or to report
17436 ;;; violations and continue execution).
17438 (define_expand "conditional_trap"
17439 [(trap_if (match_operator 0 "comparison_operator"
17440 [(match_dup 2) (const_int 0)])
17441 (match_operand 1 "const_int_operand" ""))]
17444 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17445 ix86_expand_compare (GET_CODE (operands[0]),
17451 (define_insn "*conditional_trap_1"
17452 [(trap_if (match_operator 0 "comparison_operator"
17453 [(reg 17) (const_int 0)])
17454 (match_operand 1 "const_int_operand" ""))]
17457 operands[2] = gen_label_rtx ();
17458 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
17459 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
17460 CODE_LABEL_NUMBER (operands[2]));
17464 ;; Pentium III SIMD instructions.
17466 ;; Moves for SSE/MMX regs.
17468 (define_insn "movv4sf_internal"
17469 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17470 (match_operand:V4SF 1 "general_operand" "xm,x"))]
17472 ;; @@@ let's try to use movaps here.
17473 "movaps\t{%1, %0|%0, %1}"
17474 [(set_attr "type" "sse")])
17476 (define_insn "movv4si_internal"
17477 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17478 (match_operand:V4SI 1 "general_operand" "xm,x"))]
17480 ;; @@@ let's try to use movaps here.
17481 "movaps\t{%1, %0|%0, %1}"
17482 [(set_attr "type" "sse")])
17484 (define_insn "movv8qi_internal"
17485 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17486 (match_operand:V8QI 1 "general_operand" "ym,y"))]
17488 "movq\t{%1, %0|%0, %1}"
17489 [(set_attr "type" "mmx")])
17491 (define_insn "movv4hi_internal"
17492 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17493 (match_operand:V4HI 1 "general_operand" "ym,y"))]
17495 "movq\t{%1, %0|%0, %1}"
17496 [(set_attr "type" "mmx")])
17498 (define_insn "movv2si_internal"
17499 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17500 (match_operand:V2SI 1 "general_operand" "ym,y"))]
17502 "movq\t{%1, %0|%0, %1}"
17503 [(set_attr "type" "mmx")])
17505 (define_expand "movti"
17506 [(set (match_operand:TI 0 "general_operand" "")
17507 (match_operand:TI 1 "general_operand" ""))]
17510 /* For constants other than zero into memory. We do not know how the
17511 instructions used to build constants modify the upper 64 bits
17512 of the register, once we have that information we may be able
17513 to handle some of them more efficiently. */
17514 if ((reload_in_progress | reload_completed) == 0
17515 && register_operand (operands[0], TImode)
17516 && CONSTANT_P (operands[1]))
17518 rtx addr = gen_reg_rtx (Pmode);
17520 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
17521 operands[1] = gen_rtx_MEM (TImode, addr);
17524 /* Make operand1 a register if it isn't already. */
17525 if ((reload_in_progress | reload_completed) == 0
17526 && !register_operand (operands[0], TImode)
17527 && !register_operand (operands[1], TImode)
17528 && operands[1] != CONST0_RTX (TImode))
17530 rtx temp = force_reg (TImode, operands[1]);
17531 emit_move_insn (operands[0], temp);
17536 (define_expand "movv4sf"
17537 [(set (match_operand:V4SF 0 "general_operand" "")
17538 (match_operand:V4SF 1 "general_operand" ""))]
17541 /* For constants other than zero into memory. We do not know how the
17542 instructions used to build constants modify the upper 64 bits
17543 of the register, once we have that information we may be able
17544 to handle some of them more efficiently. */
17545 if ((reload_in_progress | reload_completed) == 0
17546 && register_operand (operands[0], V4SFmode)
17547 && CONSTANT_P (operands[1]))
17549 rtx addr = gen_reg_rtx (Pmode);
17551 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
17552 operands[1] = gen_rtx_MEM (V4SFmode, addr);
17555 /* Make operand1 a register if it isn't already. */
17556 if ((reload_in_progress | reload_completed) == 0
17557 && !register_operand (operands[0], V4SFmode)
17558 && !register_operand (operands[1], V4SFmode)
17559 && operands[1] != CONST0_RTX (V4SFmode))
17561 rtx temp = force_reg (V4SFmode, operands[1]);
17562 emit_move_insn (operands[0], temp);
17567 (define_expand "movv4si"
17568 [(set (match_operand:V4SI 0 "general_operand" "")
17569 (match_operand:V4SI 1 "general_operand" ""))]
17572 /* For constants other than zero into memory. We do not know how the
17573 instructions used to build constants modify the upper 64 bits
17574 of the register, once we have that information we may be able
17575 to handle some of them more efficiently. */
17576 if ((reload_in_progress | reload_completed) == 0
17577 && register_operand (operands[0], V4SImode)
17578 && CONSTANT_P (operands[1]))
17580 rtx addr = gen_reg_rtx (Pmode);
17582 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
17583 operands[1] = gen_rtx_MEM (V4SImode, addr);
17586 /* Make operand1 a register if it isn't already. */
17587 if ((reload_in_progress | reload_completed) == 0
17588 && !register_operand (operands[0], V4SImode)
17589 && !register_operand (operands[1], V4SImode)
17590 && operands[1] != CONST0_RTX (V4SImode))
17592 rtx temp = force_reg (V4SImode, operands[1]);
17593 emit_move_insn (operands[0], temp);
17598 (define_expand "movv2si"
17599 [(set (match_operand:V2SI 0 "general_operand" "")
17600 (match_operand:V2SI 1 "general_operand" ""))]
17603 /* For constants other than zero into memory. We do not know how the
17604 instructions used to build constants modify the upper 64 bits
17605 of the register, once we have that information we may be able
17606 to handle some of them more efficiently. */
17607 if ((reload_in_progress | reload_completed) == 0
17608 && register_operand (operands[0], V2SImode)
17609 && CONSTANT_P (operands[1]))
17611 rtx addr = gen_reg_rtx (Pmode);
17613 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
17614 operands[1] = gen_rtx_MEM (V2SImode, addr);
17617 /* Make operand1 a register if it isn't already. */
17618 if ((reload_in_progress | reload_completed) == 0
17619 && !register_operand (operands[0], V2SImode)
17620 && !register_operand (operands[1], V2SImode)
17621 && operands[1] != CONST0_RTX (V2SImode))
17623 rtx temp = force_reg (V2SImode, operands[1]);
17624 emit_move_insn (operands[0], temp);
17629 (define_expand "movv4hi"
17630 [(set (match_operand:V4HI 0 "general_operand" "")
17631 (match_operand:V4HI 1 "general_operand" ""))]
17634 /* For constants other than zero into memory. We do not know how the
17635 instructions used to build constants modify the upper 64 bits
17636 of the register, once we have that information we may be able
17637 to handle some of them more efficiently. */
17638 if ((reload_in_progress | reload_completed) == 0
17639 && register_operand (operands[0], V4HImode)
17640 && CONSTANT_P (operands[1]))
17642 rtx addr = gen_reg_rtx (Pmode);
17644 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
17645 operands[1] = gen_rtx_MEM (V4HImode, addr);
17648 /* Make operand1 a register if it isn't already. */
17649 if ((reload_in_progress | reload_completed) == 0
17650 && !register_operand (operands[0], V4HImode)
17651 && !register_operand (operands[1], V4HImode)
17652 && operands[1] != CONST0_RTX (V4HImode))
17654 rtx temp = force_reg (V4HImode, operands[1]);
17655 emit_move_insn (operands[0], temp);
17660 (define_expand "movv8qi"
17661 [(set (match_operand:V8QI 0 "general_operand" "")
17662 (match_operand:V8QI 1 "general_operand" ""))]
17665 /* For constants other than zero into memory. We do not know how the
17666 instructions used to build constants modify the upper 64 bits
17667 of the register, once we have that information we may be able
17668 to handle some of them more efficiently. */
17669 if ((reload_in_progress | reload_completed) == 0
17670 && register_operand (operands[0], V8QImode)
17671 && CONSTANT_P (operands[1]))
17673 rtx addr = gen_reg_rtx (Pmode);
17675 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
17676 operands[1] = gen_rtx_MEM (V8QImode, addr);
17679 /* Make operand1 a register if it isn't already. */
17680 if ((reload_in_progress | reload_completed) == 0
17681 && !register_operand (operands[0], V8QImode)
17682 && !register_operand (operands[1], V8QImode)
17683 && operands[1] != CONST0_RTX (V8QImode))
17685 rtx temp = force_reg (V8QImode, operands[1]);
17686 emit_move_insn (operands[0], temp);
17691 (define_insn_and_split "*pushti"
17692 [(set (match_operand:TI 0 "push_operand" "=<")
17693 (match_operand:TI 1 "nonmemory_operand" "x"))]
17697 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17698 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17700 [(set_attr "type" "sse")])
17702 (define_insn_and_split "*pushv4sf"
17703 [(set (match_operand:V4SF 0 "push_operand" "=<")
17704 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
17708 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17709 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
17711 [(set_attr "type" "sse")])
17713 (define_insn_and_split "*pushv4si"
17714 [(set (match_operand:V4SI 0 "push_operand" "=<")
17715 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
17719 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17720 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
17722 [(set_attr "type" "sse")])
17724 (define_insn_and_split "*pushv2si"
17725 [(set (match_operand:V2SI 0 "push_operand" "=<")
17726 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
17730 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17731 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
17733 [(set_attr "type" "mmx")])
17735 (define_insn_and_split "*pushv4hi"
17736 [(set (match_operand:V4HI 0 "push_operand" "=<")
17737 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
17741 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17742 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
17744 [(set_attr "type" "mmx")])
17746 (define_insn_and_split "*pushv8qi"
17747 [(set (match_operand:V8QI 0 "push_operand" "=<")
17748 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
17752 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17753 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
17755 [(set_attr "type" "mmx")])
17757 (define_insn "movti_internal"
17758 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
17759 (match_operand:TI 1 "general_operand" "xm,x"))]
17762 movaps\t{%1, %0|%0, %1}
17763 movaps\t{%1, %0|%0, %1}"
17764 [(set_attr "type" "sse")])
17766 ;; These two patterns are useful for specifying exactly whether to use
17767 ;; movaps or movups
17768 (define_insn "sse_movaps"
17769 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17770 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
17773 movaps\t{%1, %0|%0, %1}
17774 movaps\t{%1, %0|%0, %1}"
17775 [(set_attr "type" "sse")])
17777 (define_insn "sse_movups"
17778 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17779 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
17782 movups\t{%1, %0|%0, %1}
17783 movups\t{%1, %0|%0, %1}"
17784 [(set_attr "type" "sse")])
17787 ;; SSE Strange Moves.
17789 (define_insn "sse_movmskps"
17790 [(set (match_operand:SI 0 "register_operand" "=r")
17791 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
17793 "movmskps\t{%1, %0|%0, %1}"
17794 [(set_attr "type" "sse")])
17796 (define_insn "mmx_pmovmskb"
17797 [(set (match_operand:SI 0 "register_operand" "=r")
17798 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
17800 "pmovmskb\t{%1, %0|%0, %1}"
17801 [(set_attr "type" "sse")])
17803 (define_insn "mmx_maskmovq"
17804 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17805 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17806 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17808 ;; @@@ check ordering of operands in intel/nonintel syntax
17809 "maskmovq\t{%2, %1|%1, %2}"
17810 [(set_attr "type" "sse")])
17812 (define_insn "sse_movntv4sf"
17813 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17814 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17816 "movntps\t{%1, %0|%0, %1}"
17817 [(set_attr "type" "sse")])
17819 (define_insn "sse_movntdi"
17820 [(set (match_operand:DI 0 "memory_operand" "=m")
17821 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
17823 "movntq\t{%1, %0|%0, %1}"
17824 [(set_attr "type" "sse")])
17826 (define_insn "sse_movhlps"
17827 [(set (match_operand:V4SF 0 "register_operand" "=x")
17829 (match_operand:V4SF 1 "register_operand" "0")
17830 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17831 (parallel [(const_int 2)
17837 "movhlps\t{%2, %0|%0, %2}"
17838 [(set_attr "type" "sse")])
17840 (define_insn "sse_movlhps"
17841 [(set (match_operand:V4SF 0 "register_operand" "=x")
17843 (match_operand:V4SF 1 "register_operand" "0")
17844 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17845 (parallel [(const_int 2)
17851 "movlhps\t{%2, %0|%0, %2}"
17852 [(set_attr "type" "sse")])
17854 (define_insn "sse_movhps"
17855 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17857 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17858 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17860 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17861 "movhps\t{%2, %0|%0, %2}"
17862 [(set_attr "type" "sse")])
17864 (define_insn "sse_movlps"
17865 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17867 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17868 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17870 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17871 "movlps\t{%2, %0|%0, %2}"
17872 [(set_attr "type" "sse")])
17874 (define_insn "sse_loadss"
17875 [(set (match_operand:V4SF 0 "register_operand" "=x")
17877 (match_operand:V4SF 1 "memory_operand" "m")
17878 (vec_duplicate:V4SF (float:SF (const_int 0)))
17881 "movss\t{%1, %0|%0, %1}"
17882 [(set_attr "type" "sse")])
17884 (define_insn "sse_movss"
17885 [(set (match_operand:V4SF 0 "register_operand" "=x")
17887 (match_operand:V4SF 1 "register_operand" "0")
17888 (match_operand:V4SF 2 "register_operand" "x")
17891 "movss\t{%2, %0|%0, %2}"
17892 [(set_attr "type" "sse")])
17894 (define_insn "sse_storess"
17895 [(set (match_operand:SF 0 "memory_operand" "=m")
17897 (match_operand:V4SF 1 "register_operand" "x")
17898 (parallel [(const_int 0)])))]
17900 "movss\t{%1, %0|%0, %1}"
17901 [(set_attr "type" "sse")])
17903 (define_insn "sse_shufps"
17904 [(set (match_operand:V4SF 0 "register_operand" "=x")
17905 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
17906 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
17907 (match_operand:SI 3 "immediate_operand" "i")] 41))]
17909 ;; @@@ check operand order for intel/nonintel syntax
17910 "shufps\t{%3, %2, %0|%0, %2, %3}"
17911 [(set_attr "type" "sse")])
17916 (define_insn "addv4sf3"
17917 [(set (match_operand:V4SF 0 "register_operand" "=x")
17918 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17919 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17921 "addps\t{%2, %0|%0, %2}"
17922 [(set_attr "type" "sse")])
17924 (define_insn "vmaddv4sf3"
17925 [(set (match_operand:V4SF 0 "register_operand" "=x")
17926 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17927 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17931 "addss\t{%2, %0|%0, %2}"
17932 [(set_attr "type" "sse")])
17934 (define_insn "subv4sf3"
17935 [(set (match_operand:V4SF 0 "register_operand" "=x")
17936 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17937 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17939 "subps\t{%2, %0|%0, %2}"
17940 [(set_attr "type" "sse")])
17942 (define_insn "vmsubv4sf3"
17943 [(set (match_operand:V4SF 0 "register_operand" "=x")
17944 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17945 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17949 "subss\t{%2, %0|%0, %2}"
17950 [(set_attr "type" "sse")])
17952 (define_insn "mulv4sf3"
17953 [(set (match_operand:V4SF 0 "register_operand" "=x")
17954 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17955 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17957 "mulps\t{%2, %0|%0, %2}"
17958 [(set_attr "type" "sse")])
17960 (define_insn "vmmulv4sf3"
17961 [(set (match_operand:V4SF 0 "register_operand" "=x")
17962 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17963 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17967 "mulss\t{%2, %0|%0, %2}"
17968 [(set_attr "type" "sse")])
17970 (define_insn "divv4sf3"
17971 [(set (match_operand:V4SF 0 "register_operand" "=x")
17972 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17973 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17975 "divps\t{%2, %0|%0, %2}"
17976 [(set_attr "type" "sse")])
17978 (define_insn "vmdivv4sf3"
17979 [(set (match_operand:V4SF 0 "register_operand" "=x")
17980 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17981 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17985 "divss\t{%2, %0|%0, %2}"
17986 [(set_attr "type" "sse")])
17989 ;; SSE square root/reciprocal
17991 (define_insn "rcpv4sf2"
17992 [(set (match_operand:V4SF 0 "register_operand" "=x")
17993 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
17995 "rcpps\t{%1, %0|%0, %1}"
17996 [(set_attr "type" "sse")])
17998 (define_insn "vmrcpv4sf2"
17999 [(set (match_operand:V4SF 0 "register_operand" "=x")
18000 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
18001 (match_operand:V4SF 2 "register_operand" "0")
18004 "rcpss\t{%1, %0|%0, %1}"
18005 [(set_attr "type" "sse")])
18007 (define_insn "rsqrtv4sf2"
18008 [(set (match_operand:V4SF 0 "register_operand" "=x")
18009 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
18011 "rsqrtps\t{%1, %0|%0, %1}"
18012 [(set_attr "type" "sse")])
18014 (define_insn "vmrsqrtv4sf2"
18015 [(set (match_operand:V4SF 0 "register_operand" "=x")
18016 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
18017 (match_operand:V4SF 2 "register_operand" "0")
18020 "rsqrtss\t{%1, %0|%0, %1}"
18021 [(set_attr "type" "sse")])
18023 (define_insn "sqrtv4sf2"
18024 [(set (match_operand:V4SF 0 "register_operand" "=x")
18025 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
18027 "sqrtps\t{%1, %0|%0, %1}"
18028 [(set_attr "type" "sse")])
18030 (define_insn "vmsqrtv4sf2"
18031 [(set (match_operand:V4SF 0 "register_operand" "=x")
18032 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
18033 (match_operand:V4SF 2 "register_operand" "0")
18036 "sqrtss\t{%1, %0|%0, %1}"
18037 [(set_attr "type" "sse")])
18040 ;; SSE logical operations.
18042 ;; These are not called andti3 etc. because we really really don't want
18043 ;; the compiler to widen DImode ands to TImode ands and then try to move
18044 ;; into DImode subregs of SSE registers, and them together, and move out
18045 ;; of DImode subregs again!
18047 (define_insn "*sse_andti3_df_1"
18048 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18049 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18050 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18052 "andpd\t{%2, %0|%0, %2}"
18053 [(set_attr "type" "sse")])
18055 (define_insn "*sse_andti3_df_2"
18056 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18057 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18058 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18060 "andpd\t{%2, %0|%0, %2}"
18061 [(set_attr "type" "sse")])
18063 (define_insn "*sse_andti3_sf_1"
18064 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18065 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18066 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18068 "andps\t{%2, %0|%0, %2}"
18069 [(set_attr "type" "sse")])
18071 (define_insn "*sse_andti3_sf_2"
18072 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18073 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18074 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18076 "andps\t{%2, %0|%0, %2}"
18077 [(set_attr "type" "sse")])
18079 (define_insn "sse_andti3"
18080 [(set (match_operand:TI 0 "register_operand" "=x")
18081 (and:TI (match_operand:TI 1 "register_operand" "%0")
18082 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18083 "TARGET_SSE && !TARGET_SSE2"
18084 "andps\t{%2, %0|%0, %2}"
18085 [(set_attr "type" "sse")])
18087 (define_insn "*sse_andti3_sse2"
18088 [(set (match_operand:TI 0 "register_operand" "=x")
18089 (and:TI (match_operand:TI 1 "register_operand" "%0")
18090 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18092 "pand\t{%2, %0|%0, %2}"
18093 [(set_attr "type" "sse")])
18095 (define_insn "*sse_nandti3_df"
18096 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18097 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18098 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18100 "andnpd\t{%2, %0|%0, %2}"
18101 [(set_attr "type" "sse")])
18103 (define_insn "*sse_nandti3_sf"
18104 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18105 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18106 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18108 "andnps\t{%2, %0|%0, %2}"
18109 [(set_attr "type" "sse")])
18111 (define_insn "sse_nandti3"
18112 [(set (match_operand:TI 0 "register_operand" "=x")
18113 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18114 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18115 "TARGET_SSE && !TARGET_SSE2"
18116 "andnps\t{%2, %0|%0, %2}"
18117 [(set_attr "type" "sse")])
18119 (define_insn "*sse_nandti3_sse2"
18120 [(set (match_operand:TI 0 "register_operand" "=x")
18121 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18122 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18124 "pnand\t{%2, %0|%0, %2}"
18125 [(set_attr "type" "sse")])
18127 (define_insn "*sse_iorti3_df_1"
18128 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18129 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18130 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18132 "orpd\t{%2, %0|%0, %2}"
18133 [(set_attr "type" "sse")])
18135 (define_insn "*sse_iorti3_df_2"
18136 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18137 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18138 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18140 "orpd\t{%2, %0|%0, %2}"
18141 [(set_attr "type" "sse")])
18143 (define_insn "*sse_iorti3_sf_1"
18144 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18145 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18146 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18148 "orps\t{%2, %0|%0, %2}"
18149 [(set_attr "type" "sse")])
18151 (define_insn "*sse_iorti3_sf_2"
18152 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18153 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18154 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18156 "orps\t{%2, %0|%0, %2}"
18157 [(set_attr "type" "sse")])
18159 (define_insn "sse_iorti3"
18160 [(set (match_operand:TI 0 "register_operand" "=x")
18161 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18162 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18163 "TARGET_SSE && !TARGET_SSE2"
18164 "orps\t{%2, %0|%0, %2}"
18165 [(set_attr "type" "sse")])
18167 (define_insn "*sse_iorti3_sse2"
18168 [(set (match_operand:TI 0 "register_operand" "=x")
18169 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18170 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18172 "por\t{%2, %0|%0, %2}"
18173 [(set_attr "type" "sse")])
18175 (define_insn "*sse_xorti3_df_1"
18176 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18177 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18178 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18180 "xorpd\t{%2, %0|%0, %2}"
18181 [(set_attr "type" "sse")])
18183 (define_insn "*sse_xorti3_df_2"
18184 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18185 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18186 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18188 "xorpd\t{%2, %0|%0, %2}"
18189 [(set_attr "type" "sse")])
18191 (define_insn "*sse_xorti3_sf_1"
18192 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18193 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18194 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18196 "xorps\t{%2, %0|%0, %2}"
18197 [(set_attr "type" "sse")])
18199 (define_insn "*sse_xorti3_sf_2"
18200 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18201 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18202 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18204 "xorps\t{%2, %0|%0, %2}"
18205 [(set_attr "type" "sse")])
18207 (define_insn "sse_xorti3"
18208 [(set (match_operand:TI 0 "register_operand" "=x")
18209 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18210 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18211 "TARGET_SSE && !TARGET_SSE2"
18212 "xorps\t{%2, %0|%0, %2}"
18213 [(set_attr "type" "sse")])
18215 (define_insn "*sse_xorti3_sse2"
18216 [(set (match_operand:TI 0 "register_operand" "=x")
18217 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18218 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18220 "pxor\t{%2, %0|%0, %2}"
18221 [(set_attr "type" "sse")])
18223 ;; Use xor, but don't show input operands so they aren't live before
18225 (define_insn "sse_clrti"
18226 [(set (match_operand:TI 0 "register_operand" "=x")
18227 (unspec:TI [(const_int 0)] 45))]
18229 "xorps\t{%0, %0|%0, %0}"
18230 [(set_attr "type" "sse")])
18233 ;; SSE mask-generating compares
18235 (define_insn "maskcmpv4sf3"
18236 [(set (match_operand:V4SI 0 "register_operand" "=x")
18237 (match_operator:V4SI 3 "sse_comparison_operator"
18238 [(match_operand:V4SF 1 "register_operand" "0")
18239 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
18241 "cmp%D3ps\t{%2, %0|%0, %2}"
18242 [(set_attr "type" "sse")])
18244 (define_insn "maskncmpv4sf3"
18245 [(set (match_operand:V4SI 0 "register_operand" "=x")
18247 (match_operator:V4SI 3 "sse_comparison_operator"
18248 [(match_operand:V4SF 1 "register_operand" "0")
18249 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
18251 "cmpn%D3ps\t{%2, %0|%0, %2}"
18252 [(set_attr "type" "sse")])
18254 (define_insn "vmmaskcmpv4sf3"
18255 [(set (match_operand:V4SI 0 "register_operand" "=x")
18257 (match_operator:V4SI 3 "sse_comparison_operator"
18258 [(match_operand:V4SF 1 "register_operand" "0")
18259 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
18263 "cmp%D3ss\t{%2, %0|%0, %2}"
18264 [(set_attr "type" "sse")])
18266 (define_insn "vmmaskncmpv4sf3"
18267 [(set (match_operand:V4SI 0 "register_operand" "=x")
18270 (match_operator:V4SI 3 "sse_comparison_operator"
18271 [(match_operand:V4SF 1 "register_operand" "0")
18272 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
18273 (subreg:V4SI (match_dup 1) 0)
18276 "cmp%D3ss\t{%2, %0|%0, %2}"
18277 [(set_attr "type" "sse")])
18279 (define_insn "sse_comi"
18280 [(set (reg:CCFP 17)
18281 (match_operator:CCFP 2 "sse_comparison_operator"
18283 (match_operand:V4SF 0 "register_operand" "x")
18284 (parallel [(const_int 0)]))
18286 (match_operand:V4SF 1 "register_operand" "x")
18287 (parallel [(const_int 0)]))]))]
18289 "comiss\t{%2, %0|%0, %2}"
18290 [(set_attr "type" "sse")])
18292 (define_insn "sse_ucomi"
18293 [(set (reg:CCFPU 17)
18294 (match_operator:CCFPU 2 "sse_comparison_operator"
18296 (match_operand:V4SF 0 "register_operand" "x")
18297 (parallel [(const_int 0)]))
18299 (match_operand:V4SF 1 "register_operand" "x")
18300 (parallel [(const_int 0)]))]))]
18302 "ucomiss\t{%2, %0|%0, %2}"
18303 [(set_attr "type" "sse")])
18308 (define_insn "sse_unpckhps"
18309 [(set (match_operand:V4SF 0 "register_operand" "=x")
18311 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18312 (parallel [(const_int 2)
18316 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18317 (parallel [(const_int 0)
18323 "unpckhps\t{%2, %0|%0, %2}"
18324 [(set_attr "type" "sse")])
18326 (define_insn "sse_unpcklps"
18327 [(set (match_operand:V4SF 0 "register_operand" "=x")
18329 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18330 (parallel [(const_int 0)
18334 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18335 (parallel [(const_int 2)
18341 "unpcklps\t{%2, %0|%0, %2}"
18342 [(set_attr "type" "sse")])
18347 (define_insn "smaxv4sf3"
18348 [(set (match_operand:V4SF 0 "register_operand" "=x")
18349 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18350 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18352 "maxps\t{%2, %0|%0, %2}"
18353 [(set_attr "type" "sse")])
18355 (define_insn "vmsmaxv4sf3"
18356 [(set (match_operand:V4SF 0 "register_operand" "=x")
18357 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18358 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18362 "maxss\t{%2, %0|%0, %2}"
18363 [(set_attr "type" "sse")])
18365 (define_insn "sminv4sf3"
18366 [(set (match_operand:V4SF 0 "register_operand" "=x")
18367 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18368 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18370 "minps\t{%2, %0|%0, %2}"
18371 [(set_attr "type" "sse")])
18373 (define_insn "vmsminv4sf3"
18374 [(set (match_operand:V4SF 0 "register_operand" "=x")
18375 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18376 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18380 "minss\t{%2, %0|%0, %2}"
18381 [(set_attr "type" "sse")])
18384 ;; SSE <-> integer/MMX conversions
18386 (define_insn "cvtpi2ps"
18387 [(set (match_operand:V4SF 0 "register_operand" "=x")
18388 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18389 (vec_duplicate:V4SF
18390 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
18393 "cvtpi2ps\t{%2, %0|%0, %2}"
18394 [(set_attr "type" "sse")])
18396 (define_insn "cvtps2pi"
18397 [(set (match_operand:V2SI 0 "register_operand" "=y")
18398 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18403 "cvtps2pi\t{%1, %0|%0, %1}"
18404 [(set_attr "type" "sse")])
18406 (define_insn "cvttps2pi"
18407 [(set (match_operand:V2SI 0 "register_operand" "=y")
18408 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18413 "cvttps2pi\t{%1, %0|%0, %1}"
18414 [(set_attr "type" "sse")])
18416 (define_insn "cvtsi2ss"
18417 [(set (match_operand:V4SF 0 "register_operand" "=x")
18418 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18419 (vec_duplicate:V4SF
18420 (float:SF (match_operand:SI 2 "register_operand" "rm")))
18423 "cvtsi2ss\t{%2, %0|%0, %2}"
18424 [(set_attr "type" "sse")])
18426 (define_insn "cvtss2si"
18427 [(set (match_operand:SI 0 "register_operand" "=y")
18428 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18429 (parallel [(const_int 0)])))]
18431 "cvtss2si\t{%1, %0|%0, %1}"
18432 [(set_attr "type" "sse")])
18434 (define_insn "cvttss2si"
18435 [(set (match_operand:SI 0 "register_operand" "=y")
18436 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18437 (parallel [(const_int 0)])))]
18439 "cvttss2si\t{%1, %0|%0, %1}"
18440 [(set_attr "type" "sse")])
18447 (define_insn "addv8qi3"
18448 [(set (match_operand:V8QI 0 "register_operand" "=y")
18449 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18450 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18452 "paddb\t{%2, %0|%0, %2}"
18453 [(set_attr "type" "mmx")])
18455 (define_insn "addv4hi3"
18456 [(set (match_operand:V4HI 0 "register_operand" "=y")
18457 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18458 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18460 "paddw\t{%2, %0|%0, %2}"
18461 [(set_attr "type" "mmx")])
18463 (define_insn "addv2si3"
18464 [(set (match_operand:V2SI 0 "register_operand" "=y")
18465 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18466 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18468 "paddd\t{%2, %0|%0, %2}"
18469 [(set_attr "type" "mmx")])
18471 (define_insn "ssaddv8qi3"
18472 [(set (match_operand:V8QI 0 "register_operand" "=y")
18473 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18474 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18476 "paddsb\t{%2, %0|%0, %2}"
18477 [(set_attr "type" "mmx")])
18479 (define_insn "ssaddv4hi3"
18480 [(set (match_operand:V4HI 0 "register_operand" "=y")
18481 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18482 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18484 "paddsw\t{%2, %0|%0, %2}"
18485 [(set_attr "type" "mmx")])
18487 (define_insn "usaddv8qi3"
18488 [(set (match_operand:V8QI 0 "register_operand" "=y")
18489 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18490 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18492 "paddusb\t{%2, %0|%0, %2}"
18493 [(set_attr "type" "mmx")])
18495 (define_insn "usaddv4hi3"
18496 [(set (match_operand:V4HI 0 "register_operand" "=y")
18497 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18498 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18500 "paddusw\t{%2, %0|%0, %2}"
18501 [(set_attr "type" "mmx")])
18503 (define_insn "subv8qi3"
18504 [(set (match_operand:V8QI 0 "register_operand" "=y")
18505 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18506 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18508 "psubb\t{%2, %0|%0, %2}"
18509 [(set_attr "type" "mmx")])
18511 (define_insn "subv4hi3"
18512 [(set (match_operand:V4HI 0 "register_operand" "=y")
18513 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18514 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18516 "psubw\t{%2, %0|%0, %2}"
18517 [(set_attr "type" "mmx")])
18519 (define_insn "subv2si3"
18520 [(set (match_operand:V2SI 0 "register_operand" "=y")
18521 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18522 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18524 "psubd\t{%2, %0|%0, %2}"
18525 [(set_attr "type" "mmx")])
18527 (define_insn "sssubv8qi3"
18528 [(set (match_operand:V8QI 0 "register_operand" "=y")
18529 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18530 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18532 "psubsb\t{%2, %0|%0, %2}"
18533 [(set_attr "type" "mmx")])
18535 (define_insn "sssubv4hi3"
18536 [(set (match_operand:V4HI 0 "register_operand" "=y")
18537 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18538 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18540 "psubsw\t{%2, %0|%0, %2}"
18541 [(set_attr "type" "mmx")])
18543 (define_insn "ussubv8qi3"
18544 [(set (match_operand:V8QI 0 "register_operand" "=y")
18545 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18546 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18548 "psubusb\t{%2, %0|%0, %2}"
18549 [(set_attr "type" "mmx")])
18551 (define_insn "ussubv4hi3"
18552 [(set (match_operand:V4HI 0 "register_operand" "=y")
18553 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18554 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18556 "psubusw\t{%2, %0|%0, %2}"
18557 [(set_attr "type" "mmx")])
18559 (define_insn "mulv4hi3"
18560 [(set (match_operand:V4HI 0 "register_operand" "=y")
18561 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
18562 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18564 "pmullw\t{%2, %0|%0, %2}"
18565 [(set_attr "type" "mmx")])
18567 (define_insn "smulv4hi3_highpart"
18568 [(set (match_operand:V4HI 0 "register_operand" "=y")
18571 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18572 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18575 "pmulhw\t{%2, %0|%0, %2}"
18576 [(set_attr "type" "mmx")])
18578 (define_insn "umulv4hi3_highpart"
18579 [(set (match_operand:V4HI 0 "register_operand" "=y")
18582 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18583 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18586 "pmulhuw\t{%2, %0|%0, %2}"
18587 [(set_attr "type" "mmx")])
18589 (define_insn "mmx_pmaddwd"
18590 [(set (match_operand:V2SI 0 "register_operand" "=y")
18593 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
18594 (parallel [(const_int 0)
18596 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18597 (parallel [(const_int 0)
18600 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
18601 (parallel [(const_int 1)
18603 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
18604 (parallel [(const_int 1)
18605 (const_int 3)]))))))]
18607 "pmaddwd\t{%2, %0|%0, %2}"
18608 [(set_attr "type" "mmx")])
18611 ;; MMX logical operations
18612 ;; Note we don't want to declare these as regular iordi3 insns to prevent
18613 ;; normal code that also wants to use the FPU from getting broken.
18614 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
18615 (define_insn "mmx_iordi3"
18616 [(set (match_operand:DI 0 "register_operand" "=y")
18618 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18619 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18621 "por\t{%2, %0|%0, %2}"
18622 [(set_attr "type" "mmx")])
18624 (define_insn "mmx_xordi3"
18625 [(set (match_operand:DI 0 "register_operand" "=y")
18627 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18628 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18630 "pxor\t{%2, %0|%0, %2}"
18631 [(set_attr "type" "mmx")])
18633 ;; Same as pxor, but don't show input operands so that we don't think
18635 (define_insn "mmx_clrdi"
18636 [(set (match_operand:DI 0 "register_operand" "=y")
18637 (unspec:DI [(const_int 0)] 45))]
18639 "pxor\t{%0, %0|%0, %0}"
18640 [(set_attr "type" "mmx")])
18642 (define_insn "mmx_anddi3"
18643 [(set (match_operand:DI 0 "register_operand" "=y")
18645 [(and:DI (match_operand:DI 1 "register_operand" "0")
18646 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18648 "pand\t{%2, %0|%0, %2}"
18649 [(set_attr "type" "mmx")])
18651 (define_insn "mmx_nanddi3"
18652 [(set (match_operand:DI 0 "register_operand" "=y")
18654 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
18655 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18657 "pandn\t{%2, %0|%0, %2}"
18658 [(set_attr "type" "mmx")])
18661 ;; MMX unsigned averages/sum of absolute differences
18663 (define_insn "mmx_uavgv8qi3"
18664 [(set (match_operand:V8QI 0 "register_operand" "=y")
18666 (plus:V8QI (plus:V8QI
18667 (match_operand:V8QI 1 "register_operand" "0")
18668 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18669 (vec_const:V8QI (parallel [(const_int 1)
18679 "pavgb\t{%2, %0|%0, %2}"
18680 [(set_attr "type" "sse")])
18682 (define_insn "mmx_uavgv4hi3"
18683 [(set (match_operand:V4HI 0 "register_operand" "=y")
18685 (plus:V4HI (plus:V4HI
18686 (match_operand:V4HI 1 "register_operand" "0")
18687 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18688 (vec_const:V4HI (parallel [(const_int 1)
18694 "pavgw\t{%2, %0|%0, %2}"
18695 [(set_attr "type" "sse")])
18697 (define_insn "mmx_psadbw"
18698 [(set (match_operand:V8QI 0 "register_operand" "=y")
18699 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18700 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
18702 "psadbw\t{%2, %0|%0, %2}"
18703 [(set_attr "type" "sse")])
18706 ;; MMX insert/extract/shuffle
18708 (define_insn "mmx_pinsrw"
18709 [(set (match_operand:V4HI 0 "register_operand" "=y")
18710 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
18711 (vec_duplicate:V4HI
18712 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
18713 (match_operand:SI 3 "immediate_operand" "i")))]
18715 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
18716 [(set_attr "type" "sse")])
18718 (define_insn "mmx_pextrw"
18719 [(set (match_operand:SI 0 "register_operand" "=r")
18720 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
18722 [(match_operand:SI 2 "immediate_operand" "i")]))))]
18724 "pextrw\t{%2, %1, %0|%0, %1, %2}"
18725 [(set_attr "type" "sse")])
18727 (define_insn "mmx_pshufw"
18728 [(set (match_operand:V4HI 0 "register_operand" "=y")
18729 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
18730 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18731 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18733 "pshufw\t{%3, %2, %0|%0, %2, %3}"
18734 [(set_attr "type" "sse")])
18737 ;; MMX mask-generating comparisons
18739 (define_insn "eqv8qi3"
18740 [(set (match_operand:V8QI 0 "register_operand" "=y")
18741 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
18742 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18744 "pcmpeqb\t{%2, %0|%0, %2}"
18745 [(set_attr "type" "mmx")])
18747 (define_insn "eqv4hi3"
18748 [(set (match_operand:V4HI 0 "register_operand" "=y")
18749 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
18750 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18752 "pcmpeqw\t{%2, %0|%0, %2}"
18753 [(set_attr "type" "mmx")])
18755 (define_insn "eqv2si3"
18756 [(set (match_operand:V2SI 0 "register_operand" "=y")
18757 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
18758 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18760 "pcmpeqd\t{%2, %0|%0, %2}"
18761 [(set_attr "type" "mmx")])
18763 (define_insn "gtv8qi3"
18764 [(set (match_operand:V8QI 0 "register_operand" "=y")
18765 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
18766 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18768 "pcmpgtb\t{%2, %0|%0, %2}"
18769 [(set_attr "type" "mmx")])
18771 (define_insn "gtv4hi3"
18772 [(set (match_operand:V4HI 0 "register_operand" "=y")
18773 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18774 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18776 "pcmpgtw\t{%2, %0|%0, %2}"
18777 [(set_attr "type" "mmx")])
18779 (define_insn "gtv2si3"
18780 [(set (match_operand:V2SI 0 "register_operand" "=y")
18781 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18782 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18784 "pcmpgtd\t{%2, %0|%0, %2}"
18785 [(set_attr "type" "mmx")])
18788 ;; MMX max/min insns
18790 (define_insn "umaxv8qi3"
18791 [(set (match_operand:V8QI 0 "register_operand" "=y")
18792 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
18793 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18795 "pmaxub\t{%2, %0|%0, %2}"
18796 [(set_attr "type" "sse")])
18798 (define_insn "smaxv4hi3"
18799 [(set (match_operand:V4HI 0 "register_operand" "=y")
18800 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
18801 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18803 "pmaxsw\t{%2, %0|%0, %2}"
18804 [(set_attr "type" "sse")])
18806 (define_insn "uminv8qi3"
18807 [(set (match_operand:V8QI 0 "register_operand" "=y")
18808 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
18809 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18811 "pminub\t{%2, %0|%0, %2}"
18812 [(set_attr "type" "sse")])
18814 (define_insn "sminv4hi3"
18815 [(set (match_operand:V4HI 0 "register_operand" "=y")
18816 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
18817 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18819 "pminsw\t{%2, %0|%0, %2}"
18820 [(set_attr "type" "sse")])
18825 (define_insn "ashrv4hi3"
18826 [(set (match_operand:V4HI 0 "register_operand" "=y")
18827 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18828 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18830 "psraw\t{%2, %0|%0, %2}"
18831 [(set_attr "type" "mmx")])
18833 (define_insn "ashrv2si3"
18834 [(set (match_operand:V2SI 0 "register_operand" "=y")
18835 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18836 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18838 "psrad\t{%2, %0|%0, %2}"
18839 [(set_attr "type" "mmx")])
18841 (define_insn "lshrv4hi3"
18842 [(set (match_operand:V4HI 0 "register_operand" "=y")
18843 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18844 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18846 "psrlw\t{%2, %0|%0, %2}"
18847 [(set_attr "type" "mmx")])
18849 (define_insn "lshrv2si3"
18850 [(set (match_operand:V2SI 0 "register_operand" "=y")
18851 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18852 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18854 "psrld\t{%2, %0|%0, %2}"
18855 [(set_attr "type" "mmx")])
18857 ;; See logical MMX insns.
18858 (define_insn "mmx_lshrdi3"
18859 [(set (match_operand:DI 0 "register_operand" "=y")
18861 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
18862 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18864 "psrlq\t{%2, %0|%0, %2}"
18865 [(set_attr "type" "mmx")])
18867 (define_insn "ashlv4hi3"
18868 [(set (match_operand:V4HI 0 "register_operand" "=y")
18869 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
18870 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18872 "psllw\t{%2, %0|%0, %2}"
18873 [(set_attr "type" "mmx")])
18875 (define_insn "ashlv2si3"
18876 [(set (match_operand:V2SI 0 "register_operand" "=y")
18877 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
18878 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18880 "pslld\t{%2, %0|%0, %2}"
18881 [(set_attr "type" "mmx")])
18883 ;; See logical MMX insns.
18884 (define_insn "mmx_ashldi3"
18885 [(set (match_operand:DI 0 "register_operand" "=y")
18887 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
18888 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18890 "psllq\t{%2, %0|%0, %2}"
18891 [(set_attr "type" "mmx")])
18894 ;; MMX pack/unpack insns.
18896 (define_insn "mmx_packsswb"
18897 [(set (match_operand:V8QI 0 "register_operand" "=y")
18899 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18900 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18902 "packsswb\t{%2, %0|%0, %2}"
18903 [(set_attr "type" "mmx")])
18905 (define_insn "mmx_packssdw"
18906 [(set (match_operand:V4HI 0 "register_operand" "=y")
18908 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
18909 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
18911 "packssdw\t{%2, %0|%0, %2}"
18912 [(set_attr "type" "mmx")])
18914 (define_insn "mmx_packuswb"
18915 [(set (match_operand:V8QI 0 "register_operand" "=y")
18917 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18918 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18920 "packuswb\t{%2, %0|%0, %2}"
18921 [(set_attr "type" "mmx")])
18923 (define_insn "mmx_punpckhbw"
18924 [(set (match_operand:V8QI 0 "register_operand" "=y")
18926 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
18927 (parallel [(const_int 4)
18935 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
18936 (parallel [(const_int 0)
18946 "punpckhbw\t{%2, %0|%0, %2}"
18947 [(set_attr "type" "mmx")])
18949 (define_insn "mmx_punpckhwd"
18950 [(set (match_operand:V4HI 0 "register_operand" "=y")
18952 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
18953 (parallel [(const_int 0)
18957 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
18958 (parallel [(const_int 2)
18964 "punpckhwd\t{%2, %0|%0, %2}"
18965 [(set_attr "type" "mmx")])
18967 (define_insn "mmx_punpckhdq"
18968 [(set (match_operand:V2SI 0 "register_operand" "=y")
18970 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
18971 (parallel [(const_int 0)
18973 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
18974 (parallel [(const_int 1)
18978 "punpckhdq\t{%2, %0|%0, %2}"
18979 [(set_attr "type" "mmx")])
18981 (define_insn "mmx_punpcklbw"
18982 [(set (match_operand:V8QI 0 "register_operand" "=y")
18984 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
18985 (parallel [(const_int 0)
18993 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
18994 (parallel [(const_int 4)
19004 "punpcklbw\t{%2, %0|%0, %2}"
19005 [(set_attr "type" "mmx")])
19007 (define_insn "mmx_punpcklwd"
19008 [(set (match_operand:V4HI 0 "register_operand" "=y")
19010 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19011 (parallel [(const_int 2)
19015 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19016 (parallel [(const_int 0)
19022 "punpcklwd\t{%2, %0|%0, %2}"
19023 [(set_attr "type" "mmx")])
19025 (define_insn "mmx_punpckldq"
19026 [(set (match_operand:V2SI 0 "register_operand" "=y")
19028 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19029 (parallel [(const_int 1)
19031 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19032 (parallel [(const_int 0)
19036 "punpckldq\t{%2, %0|%0, %2}"
19037 [(set_attr "type" "mmx")])
19040 ;; Miscellaneous stuff
19042 (define_insn "emms"
19043 [(unspec_volatile [(const_int 0)] 31)
19044 (clobber (reg:XF 8))
19045 (clobber (reg:XF 9))
19046 (clobber (reg:XF 10))
19047 (clobber (reg:XF 11))
19048 (clobber (reg:XF 12))
19049 (clobber (reg:XF 13))
19050 (clobber (reg:XF 14))
19051 (clobber (reg:XF 15))
19052 (clobber (reg:DI 29))
19053 (clobber (reg:DI 30))
19054 (clobber (reg:DI 31))
19055 (clobber (reg:DI 32))
19056 (clobber (reg:DI 33))
19057 (clobber (reg:DI 34))
19058 (clobber (reg:DI 35))
19059 (clobber (reg:DI 36))]
19062 [(set_attr "type" "mmx")
19063 (set_attr "memory" "unknown")])
19065 (define_insn "ldmxcsr"
19066 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
19069 [(set_attr "type" "mmx")])
19071 (define_insn "stmxcsr"
19072 [(set (match_operand:SI 0 "memory_operand" "=m")
19073 (unspec_volatile:SI [(const_int 0)] 40))]
19076 [(set_attr "type" "mmx")])
19078 (define_expand "sfence"
19079 [(set (match_dup 0)
19080 (unspec:BLK [(match_dup 0)] 44))]
19083 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19084 MEM_VOLATILE_P (operands[0]) = 1;
19087 (define_insn "*sfence_insn"
19088 [(set (match_operand:BLK 0 "" "")
19089 (unspec:BLK [(match_dup 0)] 44))]
19092 [(set_attr "type" "sse")
19093 (set_attr "memory" "unknown")])
19095 (define_insn "prefetch"
19096 [(unspec [(match_operand:SI 0 "address_operand" "p")
19097 (match_operand:SI 1 "immediate_operand" "n")] 35)]
19100 switch (INTVAL (operands[1]))
19103 return "prefetchnta\t%a0";
19105 return "prefetcht0\t%a0";
19107 return "prefetcht1\t%a0";
19109 return "prefetcht2\t%a0";
19114 [(set_attr "type" "sse")])