1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
54 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55 ;; operand 0 is the memory address to scan.
56 ;; operand 1 is a register containing the value to scan for. The mode
57 ;; of the scas opcode will be the same as the mode of this operand.
58 ;; operand 2 is the known alignment of operand 0.
59 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60 ;; operand 0 is the argument for `sin'.
61 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62 ;; operand 0 is the argument for `cos'.
63 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64 ;; always SImode. operand 0 is the size of the stack allocation.
65 ;; 4 This is the source of a fake SET of the frame pointer which is used to
66 ;; prevent insns referencing it being scheduled across the initial
67 ;; decrement of the stack pointer.
68 ;; 5 This is a `bsf' operation.
69 ;; 6 This is the @GOT offset of a PIC address.
70 ;; 7 This is the @GOTOFF offset of a PIC address.
71 ;; 8 This is a reference to a symbol's @PLT address.
72 ;; 9 This is an `fnstsw' operation.
73 ;; 10 This is a `sahf' operation.
74 ;; 11 This is a `fstcw' operation
75 ;; 12 This is behaviour of add when setting carry flag.
76 ;; 13 This is a `eh_return' placeholder.
78 ;; For SSE/MMX support:
79 ;; 30 This is `fix', guaranteed to be truncating.
80 ;; 31 This is a `emms' operation.
81 ;; 32 This is a `maskmov' operation.
82 ;; 33 This is a `movmsk' operation.
83 ;; 34 This is a `non-temporal' move.
84 ;; 35 This is a `prefetch' operation.
85 ;; 36 This is used to distinguish COMISS from UCOMISS.
86 ;; 37 This is a `ldmxcsr' operation.
87 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
88 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
89 ;; 40 This is a `stmxcsr' operation.
90 ;; 41 This is a `shuffle' operation.
91 ;; 42 This is a `rcp' operation.
92 ;; 43 This is a `rsqsrt' operation.
93 ;; 44 This is a `sfence' operation.
94 ;; 45 This is a noop to prevent excessive combiner cleverness.
96 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
100 ;; Processor type. This attribute must exactly match the processor_type
101 ;; enumeration in i386.h.
102 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
103 (const (symbol_ref "ix86_cpu")))
105 ;; A basic instruction type. Refinements due to arguments to be
106 ;; provided in other attributes.
108 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx"
109 (const_string "other"))
111 ;; Main data type used by the insn
112 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
113 (const_string "unknown"))
115 ;; Set for i387 operations.
116 (define_attr "i387" ""
117 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch")
121 ;; The (bounding maximum) length of an instruction immediate.
122 (define_attr "length_immediate" ""
123 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
127 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
128 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
129 (eq_attr "type" "imov,test")
130 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
131 (eq_attr "type" "call")
132 (if_then_else (match_operand 0 "constant_call_address_operand" "")
135 (eq_attr "type" "callv")
136 (if_then_else (match_operand 1 "constant_call_address_operand" "")
139 (eq_attr "type" "ibr")
140 (if_then_else (and (ge (minus (match_dup 0) (pc))
142 (lt (minus (match_dup 0) (pc))
147 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
149 ;; The (bounding maximum) length of an instruction address.
150 (define_attr "length_address" ""
151 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
153 (and (eq_attr "type" "call")
154 (match_operand 1 "constant_call_address_operand" ""))
156 (and (eq_attr "type" "callv")
157 (match_operand 1 "constant_call_address_operand" ""))
160 (symbol_ref "ix86_attr_length_address_default (insn)")))
162 ;; Set when length prefix is used.
163 (define_attr "prefix_data16" ""
164 (if_then_else (eq_attr "mode" "HI")
168 ;; Set when string REP prefix is used.
169 (define_attr "prefix_rep" "" (const_int 0))
171 ;; Set when 0f opcode prefix is used.
172 (define_attr "prefix_0f" ""
173 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
177 ;; Set when modrm byte is used.
178 (define_attr "modrm" ""
179 (cond [(eq_attr "type" "str,cld")
183 (and (eq_attr "type" "incdec")
184 (ior (match_operand:SI 1 "register_operand" "")
185 (match_operand:HI 1 "register_operand" "")))
187 (and (eq_attr "type" "push")
188 (not (match_operand 1 "memory_operand" "")))
190 (and (eq_attr "type" "pop")
191 (not (match_operand 0 "memory_operand" "")))
193 (and (eq_attr "type" "imov")
194 (and (match_operand 0 "register_operand" "")
195 (match_operand 1 "immediate_operand" "")))
200 ;; The (bounding maximum) length of an instruction in bytes.
201 (define_attr "length" ""
202 (cond [(eq_attr "type" "other,multi")
205 (plus (plus (attr "modrm")
206 (plus (attr "prefix_0f")
209 (plus (attr "prefix_rep")
210 (plus (attr "prefix_data16")
211 (plus (attr "length_immediate")
212 (attr "length_address")))))))
214 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
215 ;; `store' if there is a simple memory reference therein, or `unknown'
216 ;; if the instruction is complex.
218 (define_attr "memory" "none,load,store,both,unknown"
219 (cond [(eq_attr "type" "other,multi,str")
220 (const_string "unknown")
221 (eq_attr "type" "lea,fcmov,fpspc,cld")
222 (const_string "none")
223 (eq_attr "type" "push")
224 (if_then_else (match_operand 1 "memory_operand" "")
225 (const_string "both")
226 (const_string "store"))
227 (eq_attr "type" "pop,setcc")
228 (if_then_else (match_operand 0 "memory_operand" "")
229 (const_string "both")
230 (const_string "load"))
231 (eq_attr "type" "icmp,test")
232 (if_then_else (ior (match_operand 0 "memory_operand" "")
233 (match_operand 1 "memory_operand" ""))
234 (const_string "load")
235 (const_string "none"))
236 (eq_attr "type" "ibr")
237 (if_then_else (match_operand 0 "memory_operand" "")
238 (const_string "load")
239 (const_string "none"))
240 (eq_attr "type" "call")
241 (if_then_else (match_operand 0 "constant_call_address_operand" "")
242 (const_string "none")
243 (const_string "load"))
244 (eq_attr "type" "callv")
245 (if_then_else (match_operand 1 "constant_call_address_operand" "")
246 (const_string "none")
247 (const_string "load"))
248 (and (eq_attr "type" "alu1,negnot")
249 (match_operand 1 "memory_operand" ""))
250 (const_string "both")
251 (and (match_operand 0 "memory_operand" "")
252 (match_operand 1 "memory_operand" ""))
253 (const_string "both")
254 (match_operand 0 "memory_operand" "")
255 (const_string "store")
256 (match_operand 1 "memory_operand" "")
257 (const_string "load")
258 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
259 (match_operand 2 "memory_operand" ""))
260 (const_string "load")
261 (and (eq_attr "type" "icmov")
262 (match_operand 3 "memory_operand" ""))
263 (const_string "load")
265 (const_string "none")))
267 ;; Indicates if an instruction has both an immediate and a displacement.
269 (define_attr "imm_disp" "false,true,unknown"
270 (cond [(eq_attr "type" "other,multi")
271 (const_string "unknown")
272 (and (eq_attr "type" "icmp,test,imov")
273 (and (match_operand 0 "memory_displacement_operand" "")
274 (match_operand 1 "immediate_operand" "")))
275 (const_string "true")
276 (and (eq_attr "type" "alu,ishift,imul,idiv")
277 (and (match_operand 0 "memory_displacement_operand" "")
278 (match_operand 2 "immediate_operand" "")))
279 (const_string "true")
281 (const_string "false")))
283 ;; Indicates if an FP operation has an integer source.
285 (define_attr "fp_int_src" "false,true"
286 (const_string "false"))
288 ;; Describe a user's asm statement.
289 (define_asm_attributes
290 [(set_attr "length" "128")
291 (set_attr "type" "multi")])
293 ;; Pentium Scheduling
295 ;; The Pentium is an in-order core with two integer pipelines.
297 ;; True for insns that behave like prefixed insns on the Pentium.
298 (define_attr "pent_prefix" "false,true"
299 (if_then_else (ior (eq_attr "prefix_0f" "1")
300 (ior (eq_attr "prefix_data16" "1")
301 (eq_attr "prefix_rep" "1")))
302 (const_string "true")
303 (const_string "false")))
305 ;; Categorize how an instruction slots.
307 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
308 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
309 ;; rules, because it results in noticeably better code on non-MMX Pentium
310 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
311 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
313 (define_attr "pent_pair" "uv,pu,pv,np"
314 (cond [(eq_attr "imm_disp" "true")
316 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
317 (and (eq_attr "type" "pop,push")
318 (eq_attr "memory" "!both")))
319 (if_then_else (eq_attr "pent_prefix" "true")
322 (eq_attr "type" "ibr")
324 (and (eq_attr "type" "ishift")
325 (match_operand 2 "const_int_operand" ""))
327 (and (eq_attr "type" "call")
328 (match_operand 0 "constant_call_address_operand" ""))
330 (and (eq_attr "type" "callv")
331 (match_operand 1 "constant_call_address_operand" ""))
334 (const_string "np")))
336 ;; Rough readiness numbers. Fine tuning happens in i386.c.
338 ;; u describes pipe U
339 ;; v describes pipe V
340 ;; uv describes either pipe U or V for those that can issue to either
341 ;; np describes not paring
343 ;; fpm describes fp insns of different types are not pipelined.
345 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
347 (define_function_unit "pent_np" 1 0
348 (and (eq_attr "cpu" "pentium")
349 (eq_attr "type" "imul"))
352 (define_function_unit "pent_mul" 1 1
353 (and (eq_attr "cpu" "pentium")
354 (eq_attr "type" "imul"))
357 ;; Rep movs takes minimally 12 cycles.
358 (define_function_unit "pent_np" 1 0
359 (and (eq_attr "cpu" "pentium")
360 (eq_attr "type" "str"))
363 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
364 (define_function_unit "pent_np" 1 0
365 (and (eq_attr "cpu" "pentium")
366 (eq_attr "type" "idiv"))
369 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
370 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
371 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
372 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
373 ; like normal fp operation and fist takes 6 cycles.
375 (define_function_unit "fpu" 1 0
376 (and (eq_attr "cpu" "pentium")
377 (and (eq_attr "type" "fmov")
378 (and (eq_attr "memory" "load,store")
379 (eq_attr "mode" "XF"))))
382 (define_function_unit "pent_np" 1 0
383 (and (eq_attr "cpu" "pentium")
384 (and (eq_attr "type" "fmov")
385 (and (eq_attr "memory" "load,store")
386 (eq_attr "mode" "XF"))))
389 (define_function_unit "fpu" 1 0
390 (and (eq_attr "cpu" "pentium")
391 (and (eq_attr "type" "fmov")
392 (ior (match_operand 1 "immediate_operand" "")
393 (eq_attr "memory" "store"))))
396 (define_function_unit "pent_np" 1 0
397 (and (eq_attr "cpu" "pentium")
398 (and (eq_attr "type" "fmov")
399 (ior (match_operand 1 "immediate_operand" "")
400 (eq_attr "memory" "store"))))
403 (define_function_unit "pent_np" 1 0
404 (and (eq_attr "cpu" "pentium")
405 (eq_attr "type" "cld"))
408 (define_function_unit "fpu" 1 0
409 (and (eq_attr "cpu" "pentium")
410 (and (eq_attr "type" "fmov")
411 (eq_attr "memory" "none,load")))
414 ; Read/Modify/Write instructions usually take 3 cycles.
415 (define_function_unit "pent_u" 1 0
416 (and (eq_attr "cpu" "pentium")
417 (and (eq_attr "type" "alu,alu1,ishift")
418 (and (eq_attr "pent_pair" "pu")
419 (eq_attr "memory" "both"))))
422 (define_function_unit "pent_uv" 2 0
423 (and (eq_attr "cpu" "pentium")
424 (and (eq_attr "type" "alu,alu1,ishift")
425 (and (eq_attr "pent_pair" "!np")
426 (eq_attr "memory" "both"))))
429 (define_function_unit "pent_np" 1 0
430 (and (eq_attr "cpu" "pentium")
431 (and (eq_attr "type" "alu,alu1,negnot,ishift")
432 (and (eq_attr "pent_pair" "np")
433 (eq_attr "memory" "both"))))
436 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
437 (define_function_unit "pent_u" 1 0
438 (and (eq_attr "cpu" "pentium")
439 (and (eq_attr "type" "alu,ishift")
440 (and (eq_attr "pent_pair" "pu")
441 (eq_attr "memory" "load,store"))))
444 (define_function_unit "pent_uv" 2 0
445 (and (eq_attr "cpu" "pentium")
446 (and (eq_attr "type" "alu,ishift")
447 (and (eq_attr "pent_pair" "!np")
448 (eq_attr "memory" "load,store"))))
451 (define_function_unit "pent_np" 1 0
452 (and (eq_attr "cpu" "pentium")
453 (and (eq_attr "type" "alu,ishift")
454 (and (eq_attr "pent_pair" "np")
455 (eq_attr "memory" "load,store"))))
458 ; Insns w/o memory operands and move instructions usually take one cycle.
459 (define_function_unit "pent_u" 1 0
460 (and (eq_attr "cpu" "pentium")
461 (eq_attr "pent_pair" "pu"))
464 (define_function_unit "pent_v" 1 0
465 (and (eq_attr "cpu" "pentium")
466 (eq_attr "pent_pair" "pv"))
469 (define_function_unit "pent_uv" 2 0
470 (and (eq_attr "cpu" "pentium")
471 (eq_attr "pent_pair" "!np"))
474 (define_function_unit "pent_np" 1 0
475 (and (eq_attr "cpu" "pentium")
476 (eq_attr "pent_pair" "np"))
479 ; Pairable insns only conflict with other non-pairable insns.
480 (define_function_unit "pent_np" 1 0
481 (and (eq_attr "cpu" "pentium")
482 (and (eq_attr "type" "alu,alu1,ishift")
483 (and (eq_attr "pent_pair" "!np")
484 (eq_attr "memory" "both"))))
486 [(eq_attr "pent_pair" "np")])
488 (define_function_unit "pent_np" 1 0
489 (and (eq_attr "cpu" "pentium")
490 (and (eq_attr "type" "alu,alu1,ishift")
491 (and (eq_attr "pent_pair" "!np")
492 (eq_attr "memory" "load,store"))))
494 [(eq_attr "pent_pair" "np")])
496 (define_function_unit "pent_np" 1 0
497 (and (eq_attr "cpu" "pentium")
498 (eq_attr "pent_pair" "!np"))
500 [(eq_attr "pent_pair" "np")])
502 ; Floating point instructions usually blocks cycle longer when combined with
503 ; integer instructions, because of the inpaired fxch instruction.
504 (define_function_unit "pent_np" 1 0
505 (and (eq_attr "cpu" "pentium")
506 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp"))
508 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp")])
510 (define_function_unit "fpu" 1 0
511 (and (eq_attr "cpu" "pentium")
512 (eq_attr "type" "fcmp,fxch,fsgn"))
515 ; Addition takes 3 cycles; assume other random cruft does as well.
516 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
517 (define_function_unit "fpu" 1 0
518 (and (eq_attr "cpu" "pentium")
519 (eq_attr "type" "fop,fop1"))
522 ; Multiplication takes 3 cycles and is only half pipelined.
523 (define_function_unit "fpu" 1 0
524 (and (eq_attr "cpu" "pentium")
525 (eq_attr "type" "fmul"))
528 (define_function_unit "pent_mul" 1 1
529 (and (eq_attr "cpu" "pentium")
530 (eq_attr "type" "fmul"))
533 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
534 ; They can overlap with integer insns. Only the last two cycles can overlap
535 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
536 ; Only last two cycles of fsin/fcos can overlap with other instructions.
537 (define_function_unit "fpu" 1 0
538 (and (eq_attr "cpu" "pentium")
539 (eq_attr "type" "fdiv"))
542 (define_function_unit "pent_mul" 1 1
543 (and (eq_attr "cpu" "pentium")
544 (eq_attr "type" "fdiv"))
547 (define_function_unit "fpu" 1 0
548 (and (eq_attr "cpu" "pentium")
549 (eq_attr "type" "fpspc"))
552 (define_function_unit "pent_mul" 1 1
553 (and (eq_attr "cpu" "pentium")
554 (eq_attr "type" "fpspc"))
557 ;; Pentium Pro/PII Scheduling
559 ;; The PPro has an out-of-order core, but the instruction decoders are
560 ;; naturally in-order and asymmetric. We get best performance by scheduling
561 ;; for the decoders, for in doing so we give the oo execution unit the
564 ;; Categorize how many uops an ia32 instruction evaluates to:
565 ;; one -- an instruction with 1 uop can be decoded by any of the
567 ;; few -- an instruction with 1 to 4 uops can be decoded only by
569 ;; many -- a complex instruction may take an unspecified number of
570 ;; cycles to decode in decoder 0.
572 (define_attr "ppro_uops" "one,few,many"
573 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
574 (const_string "many")
575 (eq_attr "type" "icmov,fcmov,str,cld")
577 (eq_attr "type" "imov")
578 (if_then_else (eq_attr "memory" "store,both")
580 (const_string "one"))
581 (eq_attr "memory" "!none")
584 (const_string "one")))
586 ;; Rough readiness numbers. Fine tuning happens in i386.c.
588 ;; p0 describes port 0.
589 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
590 ;; p2 describes port 2 for loads.
591 ;; p34 describes ports 3 and 4 for stores.
592 ;; fpu describes the fpu accessed via port 0.
593 ;; ??? It is less than clear if there are separate fadd and fmul units
594 ;; that could operate in parallel.
596 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
598 (define_function_unit "ppro_p0" 1 0
599 (and (eq_attr "cpu" "pentiumpro")
600 (eq_attr "type" "ishift,lea,ibr,cld"))
603 (define_function_unit "ppro_p0" 1 0
604 (and (eq_attr "cpu" "pentiumpro")
605 (eq_attr "type" "imul"))
608 ;; ??? Does the divider lock out the pipe while it works,
609 ;; or is there a disconnected unit?
610 (define_function_unit "ppro_p0" 1 0
611 (and (eq_attr "cpu" "pentiumpro")
612 (eq_attr "type" "idiv"))
615 (define_function_unit "ppro_p0" 1 0
616 (and (eq_attr "cpu" "pentiumpro")
617 (eq_attr "type" "fop,fop1,fsgn"))
620 (define_function_unit "ppro_p0" 1 0
621 (and (eq_attr "cpu" "pentiumpro")
622 (eq_attr "type" "fcmov"))
625 (define_function_unit "ppro_p0" 1 0
626 (and (eq_attr "cpu" "pentiumpro")
627 (eq_attr "type" "fcmp"))
630 (define_function_unit "ppro_p0" 1 0
631 (and (eq_attr "cpu" "pentiumpro")
632 (eq_attr "type" "fmov"))
635 (define_function_unit "ppro_p0" 1 0
636 (and (eq_attr "cpu" "pentiumpro")
637 (eq_attr "type" "fmul"))
640 (define_function_unit "ppro_p0" 1 0
641 (and (eq_attr "cpu" "pentiumpro")
642 (eq_attr "type" "fdiv,fpspc"))
645 (define_function_unit "ppro_p01" 2 0
646 (and (eq_attr "cpu" "pentiumpro")
647 (eq_attr "type" "!imov,fmov"))
650 (define_function_unit "ppro_p01" 2 0
651 (and (and (eq_attr "cpu" "pentiumpro")
652 (eq_attr "type" "imov,fmov"))
653 (eq_attr "memory" "none"))
656 (define_function_unit "ppro_p2" 1 0
657 (and (eq_attr "cpu" "pentiumpro")
658 (ior (eq_attr "type" "pop")
659 (eq_attr "memory" "load,both")))
662 (define_function_unit "ppro_p34" 1 0
663 (and (eq_attr "cpu" "pentiumpro")
664 (ior (eq_attr "type" "push")
665 (eq_attr "memory" "store,both")))
668 (define_function_unit "fpu" 1 0
669 (and (eq_attr "cpu" "pentiumpro")
670 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov"))
673 (define_function_unit "fpu" 1 0
674 (and (eq_attr "cpu" "pentiumpro")
675 (eq_attr "type" "fmul"))
678 (define_function_unit "fpu" 1 0
679 (and (eq_attr "cpu" "pentiumpro")
680 (eq_attr "type" "fdiv,fpspc"))
683 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
684 (define_function_unit "fpu" 1 0
685 (and (eq_attr "cpu" "pentiumpro")
686 (eq_attr "type" "imul"))
689 ;; AMD K6/K6-2 Scheduling
691 ;; The K6 has similar architecture to PPro. Important difference is, that
692 ;; there are only two decoders and they seems to be much slower than execution
693 ;; units. So we have to pay much more attention to proper decoding for
694 ;; schedulers. We share most of scheduler code for PPro in i386.c
696 ;; The fp unit is not pipelined and do one operation per two cycles including
699 ;; alu describes both ALU units (ALU-X and ALU-Y).
700 ;; alux describes X alu unit
701 ;; fpu describes FPU unit
702 ;; load describes load unit.
703 ;; branch describes branch unit.
704 ;; store decsribes store unit. This unit is not modelled completely and only
705 ;; used to model lea operation. Otherwise it lie outside of the critical
708 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
710 ;; The decoder specification is in the PPro section above!
712 ;; Shift instructions and certain arithmetic are issued only to X pipe.
713 (define_function_unit "k6_alux" 1 0
714 (and (eq_attr "cpu" "k6")
715 (eq_attr "type" "ishift,alu1,negnot,cld"))
718 ;; The QI mode arithmetic is issued to X pipe only.
719 (define_function_unit "k6_alux" 1 0
720 (and (eq_attr "cpu" "k6")
721 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
722 (match_operand:QI 0 "general_operand" "")))
725 (define_function_unit "k6_alu" 2 0
726 (and (eq_attr "cpu" "k6")
727 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
730 (define_function_unit "k6_alu" 2 0
731 (and (eq_attr "cpu" "k6")
732 (and (eq_attr "type" "imov")
733 (eq_attr "memory" "none")))
736 (define_function_unit "k6_branch" 1 0
737 (and (eq_attr "cpu" "k6")
738 (eq_attr "type" "call,callv,ibr"))
741 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
742 (define_function_unit "k6_load" 1 0
743 (and (eq_attr "cpu" "k6")
744 (ior (eq_attr "type" "pop")
745 (eq_attr "memory" "load,both")))
748 (define_function_unit "k6_load" 1 0
749 (and (eq_attr "cpu" "k6")
750 (and (eq_attr "type" "str")
751 (eq_attr "memory" "load,both")))
754 ;; Lea have two instructions, so latency is probably 2
755 (define_function_unit "k6_store" 1 0
756 (and (eq_attr "cpu" "k6")
757 (eq_attr "type" "lea"))
760 (define_function_unit "k6_store" 1 0
761 (and (eq_attr "cpu" "k6")
762 (eq_attr "type" "str"))
765 (define_function_unit "k6_store" 1 0
766 (and (eq_attr "cpu" "k6")
767 (ior (eq_attr "type" "push")
768 (eq_attr "memory" "store,both")))
771 (define_function_unit "k6_fpu" 1 1
772 (and (eq_attr "cpu" "k6")
773 (eq_attr "type" "fop,fop1,fmov,fcmp"))
776 (define_function_unit "k6_fpu" 1 1
777 (and (eq_attr "cpu" "k6")
778 (eq_attr "type" "fmul"))
782 (define_function_unit "k6_fpu" 1 1
783 (and (eq_attr "cpu" "k6")
784 (eq_attr "type" "fdiv,fpspc"))
787 (define_function_unit "k6_alu" 2 0
788 (and (eq_attr "cpu" "k6")
789 (eq_attr "type" "imul"))
792 (define_function_unit "k6_alux" 1 0
793 (and (eq_attr "cpu" "k6")
794 (eq_attr "type" "imul"))
798 (define_function_unit "k6_alu" 2 0
799 (and (eq_attr "cpu" "k6")
800 (eq_attr "type" "idiv"))
803 (define_function_unit "k6_alux" 1 0
804 (and (eq_attr "cpu" "k6")
805 (eq_attr "type" "idiv"))
808 ;; AMD Athlon Scheduling
810 ;; The Athlon does contain three pipelined FP units, three integer units and
811 ;; three address generation units.
813 ;; The predecode logic is determining boundaries of instructions in the 64
814 ;; byte cache line. So the cache line straddling problem of K6 might be issue
815 ;; here as well, but it is not noted in the documentation.
817 ;; Three DirectPath instructions decoders and only one VectorPath decoder
818 ;; is available. They can decode three DirectPath instructions or one VectorPath
819 ;; instruction per cycle.
820 ;; Decoded macro instructions are then passed to 72 entry instruction control
822 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
824 ;; The load/store queue unit is not attached to the schedulers but
825 ;; communicates with all the execution units seperately instead.
827 (define_attr "athlon_decode" "direct,vector"
828 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
829 (const_string "vector")
830 (and (eq_attr "type" "push")
831 (match_operand 1 "memory_operand" ""))
832 (const_string "vector")
833 (and (eq_attr "type" "fmov")
834 (and (eq_attr "memory" "load,store")
835 (eq_attr "mode" "XF")))
836 (const_string "vector")]
837 (const_string "direct")))
839 (define_function_unit "athlon_vectordec" 1 0
840 (and (eq_attr "cpu" "athlon")
841 (eq_attr "athlon_decode" "vector"))
844 (define_function_unit "athlon_directdec" 3 0
845 (and (eq_attr "cpu" "athlon")
846 (eq_attr "athlon_decode" "direct"))
849 (define_function_unit "athlon_vectordec" 1 0
850 (and (eq_attr "cpu" "athlon")
851 (eq_attr "athlon_decode" "direct"))
852 1 1 [(eq_attr "athlon_decode" "vector")])
854 (define_function_unit "athlon_ieu" 3 0
855 (and (eq_attr "cpu" "athlon")
856 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
859 (define_function_unit "athlon_ieu" 3 0
860 (and (eq_attr "cpu" "athlon")
861 (eq_attr "type" "str"))
864 (define_function_unit "athlon_ieu" 3 0
865 (and (eq_attr "cpu" "athlon")
866 (eq_attr "type" "imul"))
869 (define_function_unit "athlon_ieu" 3 0
870 (and (eq_attr "cpu" "athlon")
871 (eq_attr "type" "idiv"))
874 (define_function_unit "athlon_muldiv" 1 0
875 (and (eq_attr "cpu" "athlon")
876 (eq_attr "type" "imul"))
879 (define_function_unit "athlon_muldiv" 1 0
880 (and (eq_attr "cpu" "athlon")
881 (eq_attr "type" "idiv"))
884 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
885 (cond [(eq_attr "type" "fop,fop1,fcmp")
887 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
889 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
890 (const_string "store")
891 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
893 (and (eq_attr "type" "fmov")
894 (ior (match_operand:SI 1 "register_operand" "")
895 (match_operand 1 "immediate_operand" "")))
896 (const_string "store")
897 (eq_attr "type" "fmov")
898 (const_string "muladd")]
899 (const_string "none")))
901 ;; We use latencies 1 for definitions. This is OK to model colisions
902 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
904 ;; fsin, fcos: 96-192
906 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
907 (define_function_unit "athlon_fp" 3 0
908 (and (eq_attr "cpu" "athlon")
909 (eq_attr "type" "fpspc"))
912 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
913 (define_function_unit "athlon_fp" 3 0
914 (and (eq_attr "cpu" "athlon")
915 (eq_attr "type" "fdiv"))
918 (define_function_unit "athlon_fp" 3 0
919 (and (eq_attr "cpu" "athlon")
920 (eq_attr "type" "fop,fop1,fmul"))
923 ;; XFmode loads are slow.
924 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
925 ;; there are no dependent instructions.
927 (define_function_unit "athlon_fp" 3 0
928 (and (eq_attr "cpu" "athlon")
929 (and (eq_attr "type" "fmov")
930 (and (eq_attr "memory" "load")
931 (eq_attr "mode" "XF"))))
934 (define_function_unit "athlon_fp" 3 0
935 (and (eq_attr "cpu" "athlon")
936 (eq_attr "type" "fmov,fsgn"))
939 ;; fcmp and ftst instructions
940 (define_function_unit "athlon_fp" 3 0
941 (and (eq_attr "cpu" "athlon")
942 (and (eq_attr "type" "fcmp")
943 (eq_attr "athlon_decode" "direct")))
946 ;; fcmpi instructions.
947 (define_function_unit "athlon_fp" 3 0
948 (and (eq_attr "cpu" "athlon")
949 (and (eq_attr "type" "fcmp")
950 (eq_attr "athlon_decode" "vector")))
953 (define_function_unit "athlon_fp" 3 0
954 (and (eq_attr "cpu" "athlon")
955 (eq_attr "type" "fcmov"))
958 (define_function_unit "athlon_fp_mul" 1 0
959 (and (eq_attr "cpu" "athlon")
960 (eq_attr "athlon_fpunits" "mul"))
963 (define_function_unit "athlon_fp_add" 1 0
964 (and (eq_attr "cpu" "athlon")
965 (eq_attr "athlon_fpunits" "add"))
968 (define_function_unit "athlon_fp_muladd" 2 0
969 (and (eq_attr "cpu" "athlon")
970 (eq_attr "athlon_fpunits" "muladd,mul,add"))
973 (define_function_unit "athlon_fp_store" 1 0
974 (and (eq_attr "cpu" "athlon")
975 (eq_attr "athlon_fpunits" "store"))
978 ;; We don't need to model the Adress Generation Unit, since we don't model
979 ;; the re-order buffer yet and thus we never schedule more than three operations
980 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
981 ;; decoders independently on the functional units.
983 ;(define_function_unit "athlon_agu" 3 0
984 ; (and (eq_attr "cpu" "athlon")
985 ; (and (eq_attr "memory" "!none")
986 ; (eq_attr "athlon_fpunits" "none")))
989 ;; Model load unit to avoid too long sequences of loads. We don't need to
990 ;; model store queue, since it is hardly going to be bottleneck.
992 (define_function_unit "athlon_load" 2 0
993 (and (eq_attr "cpu" "athlon")
994 (eq_attr "memory" "load,both"))
998 ;; Compare instructions.
1000 ;; All compare insns have expanders that save the operands away without
1001 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1002 ;; after the cmp) will actually emit the cmpM.
1004 (define_expand "cmpdi"
1006 (compare:CC (match_operand:DI 0 "x86_64_general_operand" "")
1007 (match_operand:DI 1 "x86_64_general_operand" "")))]
1011 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1012 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1013 operands[0] = force_reg (DImode, operands[0]);
1014 ix86_compare_op0 = operands[0];
1015 ix86_compare_op1 = operands[1];
1019 (define_expand "cmpsi"
1021 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1022 (match_operand:SI 1 "general_operand" "")))]
1026 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1027 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1028 operands[0] = force_reg (SImode, operands[0]);
1029 ix86_compare_op0 = operands[0];
1030 ix86_compare_op1 = operands[1];
1034 (define_expand "cmphi"
1036 (compare:CC (match_operand:HI 0 "general_operand" "")
1037 (match_operand:HI 1 "general_operand" "")))]
1041 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1042 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1043 operands[0] = force_reg (HImode, operands[0]);
1044 ix86_compare_op0 = operands[0];
1045 ix86_compare_op1 = operands[1];
1049 (define_expand "cmpqi"
1051 (compare:CC (match_operand:QI 0 "general_operand" "")
1052 (match_operand:QI 1 "general_operand" "")))]
1053 "TARGET_QIMODE_MATH"
1056 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1057 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1058 operands[0] = force_reg (QImode, operands[0]);
1059 ix86_compare_op0 = operands[0];
1060 ix86_compare_op1 = operands[1];
1064 (define_insn "cmpdi_ccno_1_rex64"
1066 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
1067 (match_operand:DI 1 "const0_operand" "n,n")))]
1068 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
1070 test{q}\\t{%0, %0|%0, %0}
1071 cmp{q}\\t{%1, %0|%0, %1}"
1072 [(set_attr "type" "test,icmp")
1073 (set_attr "length_immediate" "0,1")
1074 (set_attr "mode" "DI")])
1076 (define_insn "*cmpdi_minus_1_rex64"
1078 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
1079 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
1081 "ix86_match_ccmode (insn, CCGOCmode)"
1082 "cmp{q}\\t{%1, %0|%0, %1}"
1083 [(set_attr "type" "icmp")
1084 (set_attr "mode" "DI")])
1086 (define_expand "cmpdi_1_rex64"
1088 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1089 (match_operand:DI 1 "general_operand" "")))]
1093 (define_insn "cmpdi_1_insn_rex64"
1095 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
1096 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
1097 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1098 "cmp{q}\\t{%1, %0|%0, %1}"
1099 [(set_attr "type" "icmp")
1100 (set_attr "mode" "DI")])
1103 (define_insn "*cmpsi_ccno_1"
1105 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1106 (match_operand:SI 1 "const0_operand" "n,n")))]
1107 "ix86_match_ccmode (insn, CCNOmode)"
1109 test{l}\\t{%0, %0|%0, %0}
1110 cmp{l}\\t{%1, %0|%0, %1}"
1111 [(set_attr "type" "test,icmp")
1112 (set_attr "length_immediate" "0,1")
1113 (set_attr "mode" "SI")])
1115 (define_insn "*cmpsi_minus_1"
1117 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1118 (match_operand:SI 1 "general_operand" "ri,mr"))
1120 "ix86_match_ccmode (insn, CCGOCmode)"
1121 "cmp{l}\\t{%1, %0|%0, %1}"
1122 [(set_attr "type" "icmp")
1123 (set_attr "mode" "SI")])
1125 (define_expand "cmpsi_1"
1127 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1128 (match_operand:SI 1 "general_operand" "ri,mr")))]
1132 (define_insn "*cmpsi_1_insn"
1134 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1135 (match_operand:SI 1 "general_operand" "ri,mr")))]
1136 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1137 && ix86_match_ccmode (insn, CCmode)"
1138 "cmp{l}\\t{%1, %0|%0, %1}"
1139 [(set_attr "type" "icmp")
1140 (set_attr "mode" "SI")])
1142 (define_insn "*cmphi_ccno_1"
1144 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1145 (match_operand:HI 1 "const0_operand" "n,n")))]
1146 "ix86_match_ccmode (insn, CCNOmode)"
1148 test{w}\\t{%0, %0|%0, %0}
1149 cmp{w}\\t{%1, %0|%0, %1}"
1150 [(set_attr "type" "test,icmp")
1151 (set_attr "length_immediate" "0,1")
1152 (set_attr "mode" "HI")])
1154 (define_insn "*cmphi_minus_1"
1156 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1157 (match_operand:HI 1 "general_operand" "ri,mr"))
1159 "ix86_match_ccmode (insn, CCGOCmode)"
1160 "cmp{w}\\t{%1, %0|%0, %1}"
1161 [(set_attr "type" "icmp")
1162 (set_attr "mode" "HI")])
1164 (define_insn "*cmphi_1"
1166 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1167 (match_operand:HI 1 "general_operand" "ri,mr")))]
1168 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1169 && ix86_match_ccmode (insn, CCmode)"
1170 "cmp{w}\\t{%1, %0|%0, %1}"
1171 [(set_attr "type" "icmp")
1172 (set_attr "mode" "HI")])
1174 (define_insn "*cmpqi_ccno_1"
1176 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1177 (match_operand:QI 1 "const0_operand" "n,n")))]
1178 "ix86_match_ccmode (insn, CCNOmode)"
1180 test{b}\\t{%0, %0|%0, %0}
1181 cmp{b}\\t{$0, %0|%0, 0}"
1182 [(set_attr "type" "test,icmp")
1183 (set_attr "length_immediate" "0,1")
1184 (set_attr "mode" "QI")])
1186 (define_insn "*cmpqi_1"
1188 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1189 (match_operand:QI 1 "general_operand" "qi,mq")))]
1190 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1191 && ix86_match_ccmode (insn, CCmode)"
1192 "cmp{b}\\t{%1, %0|%0, %1}"
1193 [(set_attr "type" "icmp")
1194 (set_attr "mode" "QI")])
1196 (define_insn "*cmpqi_minus_1"
1198 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1199 (match_operand:QI 1 "general_operand" "qi,mq"))
1201 "ix86_match_ccmode (insn, CCGOCmode)"
1202 "cmp{b}\\t{%1, %0|%0, %1}"
1203 [(set_attr "type" "icmp")
1204 (set_attr "mode" "QI")])
1206 (define_insn "*cmpqi_ext_1"
1209 (match_operand:QI 0 "general_operand" "Qm")
1212 (match_operand 1 "ext_register_operand" "Q")
1214 (const_int 8)) 0)))]
1215 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1216 "cmp{b}\\t{%h1, %0|%0, %h1}"
1217 [(set_attr "type" "icmp")
1218 (set_attr "mode" "QI")])
1220 (define_insn "*cmpqi_ext_1_rex64"
1223 (match_operand:QI 0 "register_operand" "Q")
1226 (match_operand 1 "ext_register_operand" "Q")
1228 (const_int 8)) 0)))]
1229 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1230 "cmp{b}\\t{%h1, %0|%0, %h1}"
1231 [(set_attr "type" "icmp")
1232 (set_attr "mode" "QI")])
1234 (define_insn "*cmpqi_ext_2"
1239 (match_operand 0 "ext_register_operand" "Q")
1242 (match_operand:QI 1 "const0_operand" "n")))]
1243 "ix86_match_ccmode (insn, CCNOmode)"
1244 "test{b}\\t%h0, %h0"
1245 [(set_attr "type" "test")
1246 (set_attr "length_immediate" "0")
1247 (set_attr "mode" "QI")])
1249 (define_expand "cmpqi_ext_3"
1254 (match_operand 0 "ext_register_operand" "")
1257 (match_operand:QI 1 "general_operand" "")))]
1261 (define_insn "cmpqi_ext_3_insn"
1266 (match_operand 0 "ext_register_operand" "Q")
1269 (match_operand:QI 1 "general_operand" "Qmn")))]
1270 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1271 "cmp{b}\\t{%1, %h0|%h0, %1}"
1272 [(set_attr "type" "icmp")
1273 (set_attr "mode" "QI")])
1275 (define_insn "cmpqi_ext_3_insn_rex64"
1280 (match_operand 0 "ext_register_operand" "Q")
1283 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1284 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1285 "cmp{b}\\t{%1, %h0|%h0, %1}"
1286 [(set_attr "type" "icmp")
1287 (set_attr "mode" "QI")])
1289 (define_insn "*cmpqi_ext_4"
1294 (match_operand 0 "ext_register_operand" "Q")
1299 (match_operand 1 "ext_register_operand" "Q")
1301 (const_int 8)) 0)))]
1302 "ix86_match_ccmode (insn, CCmode)"
1303 "cmp{b}\\t{%h1, %h0|%h0, %h1}"
1304 [(set_attr "type" "icmp")
1305 (set_attr "mode" "QI")])
1307 ;; These implement float point compares.
1308 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1309 ;; which would allow mix and match FP modes on the compares. Which is what
1310 ;; the old patterns did, but with many more of them.
1312 (define_expand "cmpxf"
1314 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1315 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1316 "TARGET_80387 && !TARGET_64BIT"
1319 ix86_compare_op0 = operands[0];
1320 ix86_compare_op1 = operands[1];
1324 (define_expand "cmptf"
1326 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1327 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1331 ix86_compare_op0 = operands[0];
1332 ix86_compare_op1 = operands[1];
1336 (define_expand "cmpdf"
1338 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1339 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1340 "TARGET_80387 || TARGET_SSE2"
1343 ix86_compare_op0 = operands[0];
1344 ix86_compare_op1 = operands[1];
1348 (define_expand "cmpsf"
1350 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1351 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1352 "TARGET_80387 || TARGET_SSE"
1355 ix86_compare_op0 = operands[0];
1356 ix86_compare_op1 = operands[1];
1360 ;; FP compares, step 1:
1361 ;; Set the FP condition codes.
1363 ;; CCFPmode compare with exceptions
1364 ;; CCFPUmode compare with no exceptions
1366 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1367 ;; and that fp moves clobber the condition codes, and that there is
1368 ;; currently no way to describe this fact to reg-stack. So there are
1369 ;; no splitters yet for this.
1371 ;; %%% YIKES! This scheme does not retain a strong connection between
1372 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1373 ;; work! Only allow tos/mem with tos in op 0.
1375 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1376 ;; things aren't as bad as they sound...
1378 (define_insn "*cmpfp_0"
1379 [(set (match_operand:HI 0 "register_operand" "=a")
1381 [(compare:CCFP (match_operand 1 "register_operand" "f")
1382 (match_operand 2 "const0_operand" "X"))] 9))]
1384 && FLOAT_MODE_P (GET_MODE (operands[1]))
1385 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1388 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1389 return \"ftst\;fnstsw\\t%0\;fstp\\t%y0\";
1391 return \"ftst\;fnstsw\\t%0\";
1393 [(set_attr "type" "multi")
1394 (set_attr "mode" "unknownfp")])
1396 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1397 ;; used to manage the reg stack popping would not be preserved.
1399 (define_insn "*cmpfp_2_sf"
1402 (match_operand:SF 0 "register_operand" "f")
1403 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1405 "* return output_fp_compare (insn, operands, 0, 0);"
1406 [(set_attr "type" "fcmp")
1407 (set_attr "mode" "SF")])
1409 (define_insn "*cmpfp_2_sf_1"
1410 [(set (match_operand:HI 0 "register_operand" "=a")
1413 (match_operand:SF 1 "register_operand" "f")
1414 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1416 "* return output_fp_compare (insn, operands, 2, 0);"
1417 [(set_attr "type" "fcmp")
1418 (set_attr "mode" "SF")])
1420 (define_insn "*cmpfp_2_df"
1423 (match_operand:DF 0 "register_operand" "f")
1424 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1426 "* return output_fp_compare (insn, operands, 0, 0);"
1427 [(set_attr "type" "fcmp")
1428 (set_attr "mode" "DF")])
1430 (define_insn "*cmpfp_2_df_1"
1431 [(set (match_operand:HI 0 "register_operand" "=a")
1434 (match_operand:DF 1 "register_operand" "f")
1435 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1437 "* return output_fp_compare (insn, operands, 2, 0);"
1438 [(set_attr "type" "multi")
1439 (set_attr "mode" "DF")])
1441 (define_insn "*cmpfp_2_xf"
1444 (match_operand:XF 0 "register_operand" "f")
1445 (match_operand:XF 1 "register_operand" "f")))]
1446 "TARGET_80387 && !TARGET_64BIT"
1447 "* return output_fp_compare (insn, operands, 0, 0);"
1448 [(set_attr "type" "fcmp")
1449 (set_attr "mode" "XF")])
1451 (define_insn "*cmpfp_2_tf"
1454 (match_operand:TF 0 "register_operand" "f")
1455 (match_operand:TF 1 "register_operand" "f")))]
1457 "* return output_fp_compare (insn, operands, 0, 0);"
1458 [(set_attr "type" "fcmp")
1459 (set_attr "mode" "XF")])
1461 (define_insn "*cmpfp_2_xf_1"
1462 [(set (match_operand:HI 0 "register_operand" "=a")
1465 (match_operand:XF 1 "register_operand" "f")
1466 (match_operand:XF 2 "register_operand" "f"))] 9))]
1467 "TARGET_80387 && !TARGET_64BIT"
1468 "* return output_fp_compare (insn, operands, 2, 0);"
1469 [(set_attr "type" "multi")
1470 (set_attr "mode" "XF")])
1472 (define_insn "*cmpfp_2_tf_1"
1473 [(set (match_operand:HI 0 "register_operand" "=a")
1476 (match_operand:TF 1 "register_operand" "f")
1477 (match_operand:TF 2 "register_operand" "f"))] 9))]
1479 "* return output_fp_compare (insn, operands, 2, 0);"
1480 [(set_attr "type" "multi")
1481 (set_attr "mode" "XF")])
1483 (define_insn "*cmpfp_2u"
1484 [(set (reg:CCFPU 18)
1486 (match_operand 0 "register_operand" "f")
1487 (match_operand 1 "register_operand" "f")))]
1489 && FLOAT_MODE_P (GET_MODE (operands[0]))
1490 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1491 "* return output_fp_compare (insn, operands, 0, 1);"
1492 [(set_attr "type" "fcmp")
1493 (set_attr "mode" "unknownfp")])
1495 (define_insn "*cmpfp_2u_1"
1496 [(set (match_operand:HI 0 "register_operand" "=a")
1499 (match_operand 1 "register_operand" "f")
1500 (match_operand 2 "register_operand" "f"))] 9))]
1502 && FLOAT_MODE_P (GET_MODE (operands[1]))
1503 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1504 "* return output_fp_compare (insn, operands, 2, 1);"
1505 [(set_attr "type" "multi")
1506 (set_attr "mode" "unknownfp")])
1508 ;; Patterns to match the SImode-in-memory ficom instructions.
1510 ;; %%% Play games with accepting gp registers, as otherwise we have to
1511 ;; force them to memory during rtl generation, which is no good. We
1512 ;; can get rid of this once we teach reload to do memory input reloads
1515 (define_insn "*ficom_1"
1518 (match_operand 0 "register_operand" "f,f")
1519 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1520 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1521 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1524 ;; Split the not-really-implemented gp register case into a
1525 ;; push-op-pop sequence.
1527 ;; %%% This is most efficient, but am I gonna get in trouble
1528 ;; for separating cc0_setter and cc0_user?
1533 (match_operand:SF 0 "register_operand" "")
1534 (float (match_operand:SI 1 "register_operand" ""))))]
1535 "0 && TARGET_80387 && reload_completed"
1536 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1537 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1538 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1539 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1540 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1541 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1543 ;; FP compares, step 2
1544 ;; Move the fpsw to ax.
1546 (define_insn "x86_fnstsw_1"
1547 [(set (match_operand:HI 0 "register_operand" "=a")
1548 (unspec:HI [(reg 18)] 9))]
1551 [(set_attr "length" "2")
1552 (set_attr "mode" "SI")
1553 (set_attr "i387" "1")
1554 (set_attr "ppro_uops" "few")])
1556 ;; FP compares, step 3
1557 ;; Get ax into flags, general case.
1559 (define_insn "x86_sahf_1"
1561 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1564 [(set_attr "length" "1")
1565 (set_attr "athlon_decode" "vector")
1566 (set_attr "mode" "SI")
1567 (set_attr "ppro_uops" "one")])
1569 ;; Pentium Pro can do steps 1 through 3 in one go.
1571 (define_insn "*cmpfp_i"
1573 (compare:CCFP (match_operand 0 "register_operand" "f")
1574 (match_operand 1 "register_operand" "f")))]
1575 "TARGET_80387 && TARGET_CMOVE
1576 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1577 && FLOAT_MODE_P (GET_MODE (operands[0]))
1578 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1579 "* return output_fp_compare (insn, operands, 1, 0);"
1580 [(set_attr "type" "fcmp")
1581 (set_attr "mode" "unknownfp")
1582 (set_attr "athlon_decode" "vector")])
1584 (define_insn "*cmpfp_i_sse"
1586 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1587 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1589 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1590 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1591 "* return output_fp_compare (insn, operands, 1, 0);"
1592 [(set_attr "type" "fcmp,sse")
1593 (set_attr "mode" "unknownfp")
1594 (set_attr "athlon_decode" "vector")])
1596 (define_insn "*cmpfp_i_sse_only"
1598 (compare:CCFP (match_operand 0 "register_operand" "x")
1599 (match_operand 1 "nonimmediate_operand" "xm")))]
1600 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1601 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1602 "* return output_fp_compare (insn, operands, 1, 0);"
1603 [(set_attr "type" "sse")
1604 (set_attr "mode" "unknownfp")
1605 (set_attr "athlon_decode" "vector")])
1607 (define_insn "*cmpfp_iu"
1608 [(set (reg:CCFPU 17)
1609 (compare:CCFPU (match_operand 0 "register_operand" "f")
1610 (match_operand 1 "register_operand" "f")))]
1611 "TARGET_80387 && TARGET_CMOVE
1612 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1613 && FLOAT_MODE_P (GET_MODE (operands[0]))
1614 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1615 "* return output_fp_compare (insn, operands, 1, 1);"
1616 [(set_attr "type" "fcmp")
1617 (set_attr "mode" "unknownfp")
1618 (set_attr "athlon_decode" "vector")])
1620 (define_insn "*cmpfp_iu_sse"
1621 [(set (reg:CCFPU 17)
1622 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1623 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1625 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1626 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1627 "* return output_fp_compare (insn, operands, 1, 1);"
1628 [(set_attr "type" "fcmp,sse")
1629 (set_attr "mode" "unknownfp")
1630 (set_attr "athlon_decode" "vector")])
1632 (define_insn "*cmpfp_iu_sse_only"
1633 [(set (reg:CCFPU 17)
1634 (compare:CCFPU (match_operand 0 "register_operand" "x")
1635 (match_operand 1 "nonimmediate_operand" "xm")))]
1636 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1637 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1638 "* return output_fp_compare (insn, operands, 1, 1);"
1639 [(set_attr "type" "sse")
1640 (set_attr "mode" "unknownfp")
1641 (set_attr "athlon_decode" "vector")])
1643 ;; Move instructions.
1645 ;; General case of fullword move.
1647 (define_expand "movsi"
1648 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1649 (match_operand:SI 1 "general_operand" ""))]
1651 "ix86_expand_move (SImode, operands); DONE;")
1653 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1656 ;; %%% We don't use a post-inc memory reference because x86 is not a
1657 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1658 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1659 ;; targets without our curiosities, and it is just as easy to represent
1660 ;; this differently.
1662 (define_insn "*pushsi2"
1663 [(set (match_operand:SI 0 "push_operand" "=<")
1664 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1667 [(set_attr "type" "push")
1668 (set_attr "mode" "SI")])
1670 ;; For 64BIT abi we always round up to 8 bytes.
1671 (define_insn "*pushsi2_rex64"
1672 [(set (match_operand:SI 0 "push_operand" "=X")
1673 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1676 [(set_attr "type" "push")
1677 (set_attr "mode" "SI")])
1679 (define_insn "*pushsi2_prologue"
1680 [(set (match_operand:SI 0 "push_operand" "=<")
1681 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1682 (set (reg:SI 6) (reg:SI 6))]
1685 [(set_attr "type" "push")
1686 (set_attr "mode" "SI")])
1688 (define_insn "*popsi1_epilogue"
1689 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1690 (mem:SI (reg:SI 7)))
1692 (plus:SI (reg:SI 7) (const_int 4)))
1693 (set (reg:SI 6) (reg:SI 6))]
1696 [(set_attr "type" "pop")
1697 (set_attr "mode" "SI")])
1699 (define_insn "popsi1"
1700 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1701 (mem:SI (reg:SI 7)))
1703 (plus:SI (reg:SI 7) (const_int 4)))]
1706 [(set_attr "type" "pop")
1707 (set_attr "mode" "SI")])
1709 (define_insn "*movsi_xor"
1710 [(set (match_operand:SI 0 "register_operand" "=r")
1711 (match_operand:SI 1 "const0_operand" "i"))
1712 (clobber (reg:CC 17))]
1713 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1714 "xor{l}\\t{%0, %0|%0, %0}"
1715 [(set_attr "type" "alu1")
1716 (set_attr "mode" "SI")
1717 (set_attr "length_immediate" "0")])
1719 (define_insn "*movsi_or"
1720 [(set (match_operand:SI 0 "register_operand" "=r")
1721 (match_operand:SI 1 "immediate_operand" "i"))
1722 (clobber (reg:CC 17))]
1723 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1724 && INTVAL (operands[1]) == -1
1725 && (TARGET_PENTIUM || optimize_size)"
1728 operands[1] = constm1_rtx;
1729 return \"or{l}\\t{%1, %0|%0, %1}\";
1731 [(set_attr "type" "alu1")
1732 (set_attr "mode" "SI")
1733 (set_attr "length_immediate" "1")])
1735 (define_insn "*movsi_1"
1736 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1737 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1738 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1741 switch (get_attr_type (insn))
1744 if (get_attr_mode (insn) == TImode)
1745 return \"movdqa\\t{%1, %0|%0, %1}\";
1746 return \"movd\\t{%1, %0|%0, %1}\";
1749 return \"movd\\t{%1, %0|%0, %1}\";
1752 return \"lea{l}\\t{%1, %0|%0, %1}\";
1755 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1757 return \"mov{l}\\t{%1, %0|%0, %1}\";
1761 (cond [(eq_attr "alternative" "4,5")
1762 (const_string "mmx")
1763 (eq_attr "alternative" "6,7,8")
1764 (const_string "sse")
1765 (and (ne (symbol_ref "flag_pic") (const_int 0))
1766 (match_operand:SI 1 "symbolic_operand" ""))
1767 (const_string "lea")
1769 (const_string "imov")))
1770 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1771 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1773 ;; Stores and loads of ax to arbitary constant address.
1774 ;; We fake an second form of instruction to force reload to load address
1775 ;; into register when rax is not available
1776 (define_insn "*movabssi_1_rex64"
1777 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1778 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1781 movabs{l}\\t{%1, %P0|%P0, %1}
1782 mov{l}\\t{%1, %a0|%a0, %1}
1783 movabs{l}\\t{%1, %a0|%a0, %1}"
1784 [(set_attr "type" "imov")
1785 (set_attr "modrm" "0,*,*")
1786 (set_attr "length_address" "8,0,0")
1787 (set_attr "length_immediate" "0,*,*")
1788 (set_attr "memory" "store")
1789 (set_attr "mode" "SI")])
1791 (define_insn "*movabssi_2_rex64"
1792 [(set (match_operand:SI 0 "register_operand" "=a,r")
1793 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1796 movabs{l}\\t{%P1, %0|%0, %P1}
1797 mov{l}\\t{%a1, %0|%0, %a1}"
1798 [(set_attr "type" "imov")
1799 (set_attr "modrm" "0,*")
1800 (set_attr "length_address" "8,0")
1801 (set_attr "length_immediate" "0")
1802 (set_attr "memory" "load")
1803 (set_attr "mode" "SI")])
1805 (define_insn "*swapsi"
1806 [(set (match_operand:SI 0 "register_operand" "+r")
1807 (match_operand:SI 1 "register_operand" "+r"))
1812 [(set_attr "type" "imov")
1813 (set_attr "pent_pair" "np")
1814 (set_attr "athlon_decode" "vector")
1815 (set_attr "mode" "SI")
1816 (set_attr "modrm" "0")
1817 (set_attr "ppro_uops" "few")])
1819 (define_expand "movhi"
1820 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1821 (match_operand:HI 1 "general_operand" ""))]
1823 "ix86_expand_move (HImode, operands); DONE;")
1825 (define_insn "*pushhi2"
1826 [(set (match_operand:HI 0 "push_operand" "=<,<")
1827 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1830 push{w}\\t{|WORD PTR }%1
1832 [(set_attr "type" "push")
1833 (set_attr "mode" "HI")])
1835 ;; For 64BIT abi we always round up to 8 bytes.
1836 (define_insn "*pushhi2_rex64"
1837 [(set (match_operand:HI 0 "push_operand" "=X")
1838 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1841 [(set_attr "type" "push")
1842 (set_attr "mode" "QI")])
1844 (define_insn "*movhi_1"
1845 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1846 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1847 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1850 switch (get_attr_type (insn))
1853 /* movzwl is faster than movw on p2 due to partial word stalls,
1854 though not as fast as an aligned movl. */
1855 return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
1857 if (get_attr_mode (insn) == MODE_SI)
1858 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1860 return \"mov{w}\\t{%1, %0|%0, %1}\";
1864 (cond [(and (eq_attr "alternative" "0,1")
1865 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1867 (eq (symbol_ref "TARGET_HIMODE_MATH")
1869 (const_string "imov")
1870 (and (eq_attr "alternative" "2,3,4")
1871 (match_operand:HI 1 "aligned_operand" ""))
1872 (const_string "imov")
1873 (and (ne (symbol_ref "TARGET_MOVX")
1875 (eq_attr "alternative" "0,1,3,4"))
1876 (const_string "imovx")
1878 (const_string "imov")))
1880 (cond [(eq_attr "type" "imovx")
1882 (and (eq_attr "alternative" "2,3,4")
1883 (match_operand:HI 1 "aligned_operand" ""))
1885 (and (eq_attr "alternative" "0,1")
1886 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1888 (eq (symbol_ref "TARGET_HIMODE_MATH")
1892 (const_string "HI")))
1893 (set_attr "modrm" "0,*,*,0,*,*")])
1895 ;; Stores and loads of ax to arbitary constant address.
1896 ;; We fake an second form of instruction to force reload to load address
1897 ;; into register when rax is not available
1898 (define_insn "*movabshi_1_rex64"
1899 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1900 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1903 movabs{w}\\t{%1, %P0|%P0, %1}
1904 mov{w}\\t{%1, %a0|%a0, %1}
1905 movabs{w}\\t{%1, %a0|%a0, %1}"
1906 [(set_attr "type" "imov")
1907 (set_attr "modrm" "0,*,*")
1908 (set_attr "length_address" "8,0,0")
1909 (set_attr "length_immediate" "0,*,*")
1910 (set_attr "memory" "store")
1911 (set_attr "mode" "HI")])
1913 (define_insn "*movabshi_2_rex64"
1914 [(set (match_operand:HI 0 "register_operand" "=a,r")
1915 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1918 movabs{w}\\t{%P1, %0|%0, %P1}
1919 mov{w}\\t{%a1, %0|%0, %a1}"
1920 [(set_attr "type" "imov")
1921 (set_attr "modrm" "0,*")
1922 (set_attr "length_address" "8,0")
1923 (set_attr "length_immediate" "0")
1924 (set_attr "memory" "load")
1925 (set_attr "mode" "HI")])
1927 (define_insn "*swaphi_1"
1928 [(set (match_operand:HI 0 "register_operand" "+r")
1929 (match_operand:HI 1 "register_operand" "+r"))
1932 "TARGET_PARTIAL_REG_STALL"
1934 [(set_attr "type" "imov")
1935 (set_attr "pent_pair" "np")
1936 (set_attr "mode" "HI")
1937 (set_attr "modrm" "0")
1938 (set_attr "ppro_uops" "few")])
1940 (define_insn "*swaphi_2"
1941 [(set (match_operand:HI 0 "register_operand" "+r")
1942 (match_operand:HI 1 "register_operand" "+r"))
1945 "! TARGET_PARTIAL_REG_STALL"
1946 "xchg{l}\\t%k1, %k0"
1947 [(set_attr "type" "imov")
1948 (set_attr "pent_pair" "np")
1949 (set_attr "mode" "SI")
1950 (set_attr "modrm" "0")
1951 (set_attr "ppro_uops" "few")])
1953 (define_expand "movstricthi"
1954 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1955 (match_operand:HI 1 "general_operand" ""))]
1956 "! TARGET_PARTIAL_REG_STALL"
1959 /* Don't generate memory->memory moves, go through a register */
1960 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1961 operands[1] = force_reg (HImode, operands[1]);
1964 (define_insn "*movstricthi_1"
1965 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1966 (match_operand:HI 1 "general_operand" "rn,m"))]
1967 "! TARGET_PARTIAL_REG_STALL
1968 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1969 "mov{w}\\t{%1, %0|%0, %1}"
1970 [(set_attr "type" "imov")
1971 (set_attr "mode" "HI")])
1973 (define_insn "*movstricthi_xor"
1974 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1975 (match_operand:HI 1 "const0_operand" "i"))
1976 (clobber (reg:CC 17))]
1977 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1978 "xor{w}\\t{%0, %0|%0, %0}"
1979 [(set_attr "type" "alu1")
1980 (set_attr "mode" "HI")
1981 (set_attr "length_immediate" "0")])
1983 (define_expand "movqi"
1984 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1985 (match_operand:QI 1 "general_operand" ""))]
1987 "ix86_expand_move (QImode, operands); DONE;")
1989 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1990 ;; "push a byte". But actually we use pushw, which has the effect
1991 ;; of rounding the amount pushed up to a halfword.
1993 (define_insn "*pushqi2"
1994 [(set (match_operand:QI 0 "push_operand" "=X,X")
1995 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1998 push{w}\\t{|word ptr }%1
2000 [(set_attr "type" "push")
2001 (set_attr "mode" "HI")])
2003 ;; For 64BIT abi we always round up to 8 bytes.
2004 (define_insn "*pushqi2_rex64"
2005 [(set (match_operand:QI 0 "push_operand" "=X")
2006 (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
2009 [(set_attr "type" "push")
2010 (set_attr "mode" "QI")])
2012 ;; Situation is quite tricky about when to choose full sized (SImode) move
2013 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
2014 ;; partial register dependency machines (such as AMD Athlon), where QImode
2015 ;; moves issue extra dependency and for partial register stalls machines
2016 ;; that don't use QImode patterns (and QImode move cause stall on the next
2019 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
2020 ;; register stall machines with, where we use QImode instructions, since
2021 ;; partial register stall can be caused there. Then we use movzx.
2022 (define_insn "*movqi_1"
2023 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2024 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2025 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
2028 switch (get_attr_type (insn))
2031 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
2033 return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
2035 if (get_attr_mode (insn) == MODE_SI)
2036 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2038 return \"mov{b}\\t{%1, %0|%0, %1}\";
2042 (cond [(and (eq_attr "alternative" "3")
2043 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
2045 (eq (symbol_ref "TARGET_QIMODE_MATH")
2047 (const_string "imov")
2048 (eq_attr "alternative" "3,5")
2049 (const_string "imovx")
2050 (and (ne (symbol_ref "TARGET_MOVX")
2052 (eq_attr "alternative" "2"))
2053 (const_string "imovx")
2055 (const_string "imov")))
2057 (cond [(eq_attr "alternative" "3,4,5")
2059 (eq_attr "alternative" "6")
2061 (eq_attr "type" "imovx")
2063 (and (eq_attr "type" "imov")
2064 (and (eq_attr "alternative" "0,1,2")
2065 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
2068 ;; Avoid partial register stalls when not using QImode arithmetic
2069 (and (eq_attr "type" "imov")
2070 (and (eq_attr "alternative" "0,1,2")
2071 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
2073 (eq (symbol_ref "TARGET_QIMODE_MATH")
2077 (const_string "QI")))])
2079 (define_expand "reload_outqi"
2080 [(parallel [(match_operand:QI 0 "" "=m")
2081 (match_operand:QI 1 "register_operand" "r")
2082 (match_operand:QI 2 "register_operand" "=&q")])]
2087 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
2089 if (reg_overlap_mentioned_p (op2, op0))
2091 if (! q_regs_operand (op1, QImode))
2093 emit_insn (gen_movqi (op2, op1));
2096 emit_insn (gen_movqi (op0, op1));
2100 (define_insn "*swapqi"
2101 [(set (match_operand:QI 0 "register_operand" "+r")
2102 (match_operand:QI 1 "register_operand" "+r"))
2107 [(set_attr "type" "imov")
2108 (set_attr "pent_pair" "np")
2109 (set_attr "mode" "QI")
2110 (set_attr "modrm" "0")
2111 (set_attr "ppro_uops" "few")])
2113 (define_expand "movstrictqi"
2114 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
2115 (match_operand:QI 1 "general_operand" ""))]
2116 "! TARGET_PARTIAL_REG_STALL"
2119 /* Don't generate memory->memory moves, go through a register */
2120 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2121 operands[1] = force_reg (QImode, operands[1]);
2124 (define_insn "*movstrictqi_1"
2125 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
2126 (match_operand:QI 1 "general_operand" "*qn,m"))]
2127 "! TARGET_PARTIAL_REG_STALL
2128 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2129 "mov{b}\\t{%1, %0|%0, %1}"
2130 [(set_attr "type" "imov")
2131 (set_attr "mode" "QI")])
2133 (define_insn "*movstrictqi_xor"
2134 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
2135 (match_operand:QI 1 "const0_operand" "i"))
2136 (clobber (reg:CC 17))]
2137 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
2138 "xor{b}\\t{%0, %0|%0, %0}"
2139 [(set_attr "type" "alu1")
2140 (set_attr "mode" "QI")
2141 (set_attr "length_immediate" "0")])
2143 (define_insn "*movsi_extv_1"
2144 [(set (match_operand:SI 0 "register_operand" "=R")
2145 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
2149 "movs{bl|x}\\t{%h1, %0|%0, %h1}"
2150 [(set_attr "type" "imovx")
2151 (set_attr "mode" "SI")])
2153 (define_insn "*movhi_extv_1"
2154 [(set (match_operand:HI 0 "register_operand" "=R")
2155 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
2159 "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
2160 [(set_attr "type" "imovx")
2161 (set_attr "mode" "SI")])
2163 (define_insn "*movqi_extv_1"
2164 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2165 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2171 switch (get_attr_type (insn))
2174 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2176 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2180 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2181 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2182 (ne (symbol_ref "TARGET_MOVX")
2184 (const_string "imovx")
2185 (const_string "imov")))
2187 (if_then_else (eq_attr "type" "imovx")
2189 (const_string "QI")))])
2191 (define_insn "*movqi_extv_1_rex64"
2192 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2193 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2199 switch (get_attr_type (insn))
2202 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2204 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2208 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2209 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2210 (ne (symbol_ref "TARGET_MOVX")
2212 (const_string "imovx")
2213 (const_string "imov")))
2215 (if_then_else (eq_attr "type" "imovx")
2217 (const_string "QI")))])
2219 ;; Stores and loads of ax to arbitary constant address.
2220 ;; We fake an second form of instruction to force reload to load address
2221 ;; into register when rax is not available
2222 (define_insn "*movabsqi_1_rex64"
2223 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2224 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2227 movabs{q}\\t{%1, %P0|%P0, %1}
2228 mov{q}\\t{%1, %a0|%a0, %1}
2229 movabs{q}\\t{%1, %a0|%a0, %1}"
2230 [(set_attr "type" "imov")
2231 (set_attr "modrm" "0,*,*")
2232 (set_attr "length_address" "8,0,0")
2233 (set_attr "length_immediate" "0,*,*")
2234 (set_attr "memory" "store")
2235 (set_attr "mode" "QI")])
2237 (define_insn "*movabsqi_2_rex64"
2238 [(set (match_operand:QI 0 "register_operand" "=a,r")
2239 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2242 movabs{q}\\t{%P1, %0|%0, %P1}
2243 mov{q}\\t{%a1, %0|%0, %a1}"
2244 [(set_attr "type" "imov")
2245 (set_attr "modrm" "0,*")
2246 (set_attr "length_address" "8,0")
2247 (set_attr "length_immediate" "0")
2248 (set_attr "memory" "load")
2249 (set_attr "mode" "QI")])
2251 (define_insn "*movsi_extzv_1"
2252 [(set (match_operand:SI 0 "register_operand" "=R")
2253 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
2257 "movz{bl|x}\\t{%h1, %0|%0, %h1}"
2258 [(set_attr "type" "imovx")
2259 (set_attr "mode" "SI")])
2261 (define_insn "*movqi_extzv_2"
2262 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2263 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2269 switch (get_attr_type (insn))
2272 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2274 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2278 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2279 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2280 (ne (symbol_ref "TARGET_MOVX")
2282 (const_string "imovx")
2283 (const_string "imov")))
2285 (if_then_else (eq_attr "type" "imovx")
2287 (const_string "QI")))])
2289 (define_insn "*movqi_extzv_2_rex64"
2290 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2291 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2297 switch (get_attr_type (insn))
2300 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2302 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2306 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2307 (ne (symbol_ref "TARGET_MOVX")
2309 (const_string "imovx")
2310 (const_string "imov")))
2312 (if_then_else (eq_attr "type" "imovx")
2314 (const_string "QI")))])
2316 (define_insn "*movsi_insv_1"
2317 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2320 (match_operand:SI 1 "nonimmediate_operand" "Qm"))]
2322 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2323 [(set_attr "type" "imov")
2324 (set_attr "mode" "QI")])
2326 (define_insn "*movsi_insv_1_rex64"
2327 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2330 (match_operand:SI 1 "register_operand" "Q"))]
2332 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2333 [(set_attr "type" "imov")
2334 (set_attr "mode" "QI")])
2336 (define_insn "*movqi_insv_2"
2337 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2340 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
2344 "mov{b}\\t{%h1, %h0|%h0, %h1}"
2345 [(set_attr "type" "imov")
2346 (set_attr "mode" "QI")])
2348 (define_expand "movdi"
2349 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2350 (match_operand:DI 1 "general_operand" ""))]
2352 "ix86_expand_move (DImode, operands); DONE;")
2354 (define_insn "*pushdi"
2355 [(set (match_operand:DI 0 "push_operand" "=<")
2356 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2360 (define_insn "pushdi2_rex64"
2361 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2362 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2367 [(set_attr "type" "push,multi")
2368 (set_attr "mode" "DI")])
2370 ;; Convert impossible pushes of immediate to existing instructions.
2371 ;; First try to get scratch register and go trought it. In case this
2372 ;; fails, push sign extended lower part first and then overwrite
2373 ;; upper part by 32bit move.
2375 [(match_scratch:DI 2 "r")
2376 (set (match_operand:DI 0 "push_operand" "")
2377 (match_operand:DI 1 "immediate_operand" ""))]
2378 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2379 && !x86_64_immediate_operand (operands[1], DImode)"
2380 [(set (match_dup 2) (match_dup 1))
2381 (set (match_dup 0) (match_dup 2))]
2384 ;; We need to define this as both peepholer and splitter for case
2385 ;; peephole2 pass is not run.
2387 [(set (match_operand:DI 0 "push_operand" "")
2388 (match_operand:DI 1 "immediate_operand" ""))]
2389 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2390 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2391 [(set (match_dup 0) (match_dup 1))
2392 (set (match_dup 2) (match_dup 3))]
2393 "split_di (operands + 1, 1, operands + 2, operands + 3);
2394 operands[1] = gen_lowpart (DImode, operands[2]);
2395 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2400 [(set (match_operand:DI 0 "push_operand" "")
2401 (match_operand:DI 1 "immediate_operand" ""))]
2402 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2403 && !symbolic_operand (operands[1], DImode)
2404 && !x86_64_immediate_operand (operands[1], DImode)"
2405 [(set (match_dup 0) (match_dup 1))
2406 (set (match_dup 2) (match_dup 3))]
2407 "split_di (operands + 1, 1, operands + 2, operands + 3);
2408 operands[1] = gen_lowpart (DImode, operands[2]);
2409 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2413 (define_insn "*pushdi2_prologue_rex64"
2414 [(set (match_operand:DI 0 "push_operand" "=<")
2415 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2416 (set (reg:DI 6) (reg:DI 6))]
2419 [(set_attr "type" "push")
2420 (set_attr "mode" "DI")])
2422 (define_insn "*popdi1_epilogue_rex64"
2423 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2424 (mem:DI (reg:DI 7)))
2426 (plus:DI (reg:DI 7) (const_int 8)))
2427 (set (reg:DI 6) (reg:DI 6))]
2430 [(set_attr "type" "pop")
2431 (set_attr "mode" "DI")])
2433 (define_insn "popdi1"
2434 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2435 (mem:DI (reg:DI 7)))
2437 (plus:DI (reg:DI 7) (const_int 8)))]
2440 [(set_attr "type" "pop")
2441 (set_attr "mode" "DI")])
2443 (define_insn "*movdi_xor_rex64"
2444 [(set (match_operand:DI 0 "register_operand" "=r")
2445 (match_operand:DI 1 "const0_operand" "i"))
2446 (clobber (reg:CC 17))]
2447 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)
2449 "xor{l}\\t{%k0, %k0|%k0, %k0}"
2450 [(set_attr "type" "alu1")
2451 (set_attr "mode" "SI")
2452 (set_attr "length_immediate" "0")])
2454 (define_insn "*movdi_or_rex64"
2455 [(set (match_operand:DI 0 "register_operand" "=r")
2456 (match_operand:DI 1 "const_int_operand" "i"))
2457 (clobber (reg:CC 17))]
2458 "reload_completed && GET_CODE (operands[1]) == CONST_INT
2460 && INTVAL (operands[1]) == -1
2461 && (TARGET_PENTIUM || optimize_size)"
2464 operands[1] = constm1_rtx;
2465 return \"or{q}\\t{%1, %0|%0, %1}\";
2467 [(set_attr "type" "alu1")
2468 (set_attr "mode" "DI")
2469 (set_attr "length_immediate" "1")])
2471 (define_insn "*movdi_2"
2472 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2473 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2475 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2479 movq\\t{%1, %0|%0, %1}
2480 movq\\t{%1, %0|%0, %1}
2481 movq\\t{%1, %0|%0, %1}
2482 movdqa\\t{%1, %0|%0, %1}
2483 movq\\t{%1, %0|%0, %1}"
2484 [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
2485 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
2488 [(set (match_operand:DI 0 "push_operand" "")
2489 (match_operand:DI 1 "general_operand" ""))]
2490 "!TARGET_64BIT && reload_completed
2491 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2493 "ix86_split_long_move (operands); DONE;")
2495 ;; %%% This multiword shite has got to go.
2497 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2498 (match_operand:DI 1 "general_operand" ""))]
2499 "!TARGET_64BIT && reload_completed
2500 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
2501 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2503 "ix86_split_long_move (operands); DONE;")
2505 (define_insn "*movdi_1_rex64"
2506 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
2507 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
2508 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2512 switch (get_attr_type (insn))
2515 if (register_operand (operands[0], DImode)
2516 && register_operand (operands[1], DImode))
2517 return \"movdqa\\t{%1, %0|%0, %1}\";
2520 return \"movq\\t{%1, %0|%0, %1}\";
2524 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
2526 if (flag_pic && SYMBOLIC_CONST (operands[1]))
2528 if (get_attr_mode (insn) == MODE_SI)
2529 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2530 else if (which_alternative == 2)
2531 return \"movabs{q}\\t{%1, %0|%0, %1}\";
2533 return \"mov{q}\\t{%1, %0|%0, %1}\";
2537 (cond [(eq_attr "alternative" "5,6")
2538 (const_string "mmx")
2539 (eq_attr "alternative" "7,8")
2540 (const_string "sse")
2541 (eq_attr "alternative" "4")
2542 (const_string "multi")
2543 (and (ne (symbol_ref "flag_pic") (const_int 0))
2544 (match_operand:DI 1 "symbolic_operand" ""))
2545 (const_string "lea")
2547 (const_string "imov")))
2548 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
2549 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
2550 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
2552 ;; Stores and loads of ax to arbitary constant address.
2553 ;; We fake an second form of instruction to force reload to load address
2554 ;; into register when rax is not available
2555 (define_insn "*movabsdi_1_rex64"
2556 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2557 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2560 movabs{q}\\t{%1, %P0|%P0, %1}
2561 mov{q}\\t{%1, %a0|%a0, %1}
2562 movabs{q}\\t{%1, %a0|%a0, %1}"
2563 [(set_attr "type" "imov")
2564 (set_attr "modrm" "0,*,*")
2565 (set_attr "length_address" "8,0,0")
2566 (set_attr "length_immediate" "0,*,*")
2567 (set_attr "memory" "store")
2568 (set_attr "mode" "DI")])
2570 (define_insn "*movabsdi_2_rex64"
2571 [(set (match_operand:DI 0 "register_operand" "=a,r")
2572 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2575 movabs{q}\\t{%P1, %0|%0, %P1}
2576 mov{q}\\t{%a1, %0|%0, %a1}"
2577 [(set_attr "type" "imov")
2578 (set_attr "modrm" "0,*")
2579 (set_attr "length_address" "8,0")
2580 (set_attr "length_immediate" "0")
2581 (set_attr "memory" "load")
2582 (set_attr "mode" "DI")])
2584 ;; Convert impossible stores of immediate to existing instructions.
2585 ;; First try to get scratch register and go trought it. In case this
2586 ;; fails, move by 32bit parts.
2588 [(match_scratch:DI 2 "r")
2589 (set (match_operand:DI 0 "memory_operand" "")
2590 (match_operand:DI 1 "immediate_operand" ""))]
2591 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2592 && !x86_64_immediate_operand (operands[1], DImode)"
2593 [(set (match_dup 2) (match_dup 1))
2594 (set (match_dup 0) (match_dup 2))]
2597 ;; We need to define this as both peepholer and splitter for case
2598 ;; peephole2 pass is not run.
2600 [(set (match_operand:DI 0 "memory_operand" "")
2601 (match_operand:DI 1 "immediate_operand" ""))]
2602 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2603 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2604 [(set (match_dup 2) (match_dup 3))
2605 (set (match_dup 4) (match_dup 5))]
2606 "split_di (operands, 2, operands + 2, operands + 4);")
2609 [(set (match_operand:DI 0 "memory_operand" "")
2610 (match_operand:DI 1 "immediate_operand" ""))]
2611 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2612 && !symbolic_operand (operands[1], DImode)
2613 && !x86_64_immediate_operand (operands[1], DImode)"
2614 [(set (match_dup 2) (match_dup 3))
2615 (set (match_dup 4) (match_dup 5))]
2616 "split_di (operands, 2, operands + 2, operands + 4);")
2618 (define_insn "*swapdi_rex64"
2619 [(set (match_operand:DI 0 "register_operand" "+r")
2620 (match_operand:DI 1 "register_operand" "+r"))
2625 [(set_attr "type" "imov")
2626 (set_attr "pent_pair" "np")
2627 (set_attr "athlon_decode" "vector")
2628 (set_attr "mode" "DI")
2629 (set_attr "modrm" "0")
2630 (set_attr "ppro_uops" "few")])
2633 (define_expand "movsf"
2634 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2635 (match_operand:SF 1 "general_operand" ""))]
2637 "ix86_expand_move (SFmode, operands); DONE;")
2639 (define_insn "*pushsf"
2640 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2641 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2645 switch (which_alternative)
2648 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2649 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2650 operands[2] = stack_pointer_rtx;
2651 operands[3] = GEN_INT (4);
2652 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2653 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2655 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2658 return \"push{l}\\t%1\";
2666 [(set_attr "type" "multi,push,multi")
2667 (set_attr "mode" "SF,SI,SF")])
2669 (define_insn "*pushsf_rex64"
2670 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2671 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2675 switch (which_alternative)
2678 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2679 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2680 operands[2] = stack_pointer_rtx;
2681 operands[3] = GEN_INT (8);
2682 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2683 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2685 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2688 return \"push{q}\\t%q1\";
2697 [(set_attr "type" "multi,push,multi")
2698 (set_attr "mode" "SF,DI,SF")])
2701 [(set (match_operand:SF 0 "push_operand" "")
2702 (match_operand:SF 1 "memory_operand" ""))]
2704 && GET_CODE (operands[1]) == MEM
2705 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2706 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2709 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2712 ;; %%% Kill this when call knows how to work this out.
2714 [(set (match_operand:SF 0 "push_operand" "")
2715 (match_operand:SF 1 "register_operand" ""))]
2716 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2717 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2718 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2721 [(set (match_operand:SF 0 "push_operand" "")
2722 (match_operand:SF 1 "register_operand" ""))]
2723 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2724 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2725 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2727 (define_insn "*movsf_1"
2728 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2729 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2730 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2731 && (reload_in_progress || reload_completed
2732 || GET_CODE (operands[1]) != CONST_DOUBLE
2733 || memory_operand (operands[0], SFmode))"
2736 switch (which_alternative)
2739 if (REG_P (operands[1])
2740 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2741 return \"fstp\\t%y0\";
2742 else if (STACK_TOP_P (operands[0]))
2743 return \"fld%z1\\t%y1\";
2745 return \"fst\\t%y0\";
2748 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2749 return \"fstp%z0\\t%y0\";
2751 return \"fst%z0\\t%y0\";
2754 switch (standard_80387_constant_p (operands[1]))
2765 return \"mov{l}\\t{%1, %0|%0, %1}\";
2767 return \"pxor\\t%0, %0\";
2769 if (TARGET_PARTIAL_REG_DEPENDENCY)
2770 return \"movaps\\t{%1, %0|%0, %1}\";
2772 return \"movss\\t{%1, %0|%0, %1}\";
2775 return \"movss\\t{%1, %0|%0, %1}\";
2781 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2782 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2784 (define_insn "*swapsf"
2785 [(set (match_operand:SF 0 "register_operand" "+f")
2786 (match_operand:SF 1 "register_operand" "+f"))
2789 "reload_completed || !TARGET_SSE2"
2792 if (STACK_TOP_P (operands[0]))
2793 return \"fxch\\t%1\";
2795 return \"fxch\\t%0\";
2797 [(set_attr "type" "fxch")
2798 (set_attr "mode" "SF")])
2800 (define_expand "movdf"
2801 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2802 (match_operand:DF 1 "general_operand" ""))]
2804 "ix86_expand_move (DFmode, operands); DONE;")
2806 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2807 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2808 ;; On the average, pushdf using integers can be still shorter. Allow this
2809 ;; pattern for optimize_size too.
2811 (define_insn "*pushdf_nointeger"
2812 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2813 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2814 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2817 switch (which_alternative)
2820 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2821 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2822 operands[2] = stack_pointer_rtx;
2823 operands[3] = GEN_INT (8);
2824 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2825 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2827 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2838 [(set_attr "type" "multi")
2839 (set_attr "mode" "DF,SI,SI,DF")])
2841 (define_insn "*pushdf_integer"
2842 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2843 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2844 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2847 switch (which_alternative)
2850 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2851 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2852 operands[2] = stack_pointer_rtx;
2853 operands[3] = GEN_INT (8);
2855 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2856 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2858 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2860 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2861 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2863 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2874 [(set_attr "type" "multi")
2875 (set_attr "mode" "DF,SI,DF")])
2877 ;; %%% Kill this when call knows how to work this out.
2879 [(set (match_operand:DF 0 "push_operand" "")
2880 (match_operand:DF 1 "register_operand" ""))]
2881 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2882 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2883 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2887 [(set (match_operand:DF 0 "push_operand" "")
2888 (match_operand:DF 1 "register_operand" ""))]
2889 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2890 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2891 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2895 [(set (match_operand:DF 0 "push_operand" "")
2896 (match_operand:DF 1 "general_operand" ""))]
2899 "ix86_split_long_move (operands); DONE;")
2901 ;; Moving is usually shorter when only FP registers are used. This separate
2902 ;; movdf pattern avoids the use of integer registers for FP operations
2903 ;; when optimizing for size.
2905 (define_insn "*movdf_nointeger"
2906 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2907 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2908 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2909 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2910 && (reload_in_progress || reload_completed
2911 || GET_CODE (operands[1]) != CONST_DOUBLE
2912 || memory_operand (operands[0], DFmode))"
2915 switch (which_alternative)
2918 if (REG_P (operands[1])
2919 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2920 return \"fstp\\t%y0\";
2921 else if (STACK_TOP_P (operands[0]))
2922 return \"fld%z1\\t%y1\";
2924 return \"fst\\t%y0\";
2927 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2928 return \"fstp%z0\\t%y0\";
2930 return \"fst%z0\\t%y0\";
2933 switch (standard_80387_constant_p (operands[1]))
2946 return \"pxor\\t%0, %0\";
2948 if (TARGET_PARTIAL_REG_DEPENDENCY)
2949 return \"movapd\\t{%1, %0|%0, %1}\";
2951 return \"movsd\\t{%1, %0|%0, %1}\";
2954 return \"movsd\\t{%1, %0|%0, %1}\";
2960 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2961 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2963 (define_insn "*movdf_integer"
2964 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2965 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2966 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2967 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2968 && (reload_in_progress || reload_completed
2969 || GET_CODE (operands[1]) != CONST_DOUBLE
2970 || memory_operand (operands[0], DFmode))"
2973 switch (which_alternative)
2976 if (REG_P (operands[1])
2977 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2978 return \"fstp\\t%y0\";
2979 else if (STACK_TOP_P (operands[0]))
2980 return \"fld%z1\\t%y1\";
2982 return \"fst\\t%y0\";
2985 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2986 return \"fstp%z0\\t%y0\";
2988 return \"fst%z0\\t%y0\";
2991 switch (standard_80387_constant_p (operands[1]))
3005 return \"pxor\\t%0, %0\";
3007 if (TARGET_PARTIAL_REG_DEPENDENCY)
3008 return \"movapd\\t{%1, %0|%0, %1}\";
3010 return \"movsd\\t{%1, %0|%0, %1}\";
3013 return \"movsd\\t{%1, %0|%0, %1}\";
3019 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
3020 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
3023 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3024 (match_operand:DF 1 "general_operand" ""))]
3026 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3027 && ! (ANY_FP_REG_P (operands[0]) ||
3028 (GET_CODE (operands[0]) == SUBREG
3029 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3030 && ! (ANY_FP_REG_P (operands[1]) ||
3031 (GET_CODE (operands[1]) == SUBREG
3032 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3034 "ix86_split_long_move (operands); DONE;")
3036 (define_insn "*swapdf"
3037 [(set (match_operand:DF 0 "register_operand" "+f")
3038 (match_operand:DF 1 "register_operand" "+f"))
3041 "reload_completed || !TARGET_SSE2"
3044 if (STACK_TOP_P (operands[0]))
3045 return \"fxch\\t%1\";
3047 return \"fxch\\t%0\";
3049 [(set_attr "type" "fxch")
3050 (set_attr "mode" "DF")])
3052 (define_expand "movxf"
3053 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3054 (match_operand:XF 1 "general_operand" ""))]
3056 "ix86_expand_move (XFmode, operands); DONE;")
3058 (define_expand "movtf"
3059 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3060 (match_operand:TF 1 "general_operand" ""))]
3062 "ix86_expand_move (TFmode, operands); DONE;")
3064 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
3065 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
3066 ;; Pushing using integer instructions is longer except for constants
3067 ;; and direct memory references.
3068 ;; (assuming that any given constant is pushed only once, but this ought to be
3069 ;; handled elsewhere).
3071 (define_insn "*pushxf_nointeger"
3072 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3073 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3074 "optimize_size && !TARGET_64BIT"
3077 switch (which_alternative)
3080 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3081 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3082 operands[2] = stack_pointer_rtx;
3083 operands[3] = GEN_INT (12);
3084 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3085 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3087 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3097 [(set_attr "type" "multi")
3098 (set_attr "mode" "XF,SI,SI")])
3100 (define_insn "*pushtf_nointeger"
3101 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
3102 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
3106 switch (which_alternative)
3109 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3110 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3111 operands[2] = stack_pointer_rtx;
3112 operands[3] = GEN_INT (16);
3113 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3114 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3116 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3126 [(set_attr "type" "multi")
3127 (set_attr "mode" "XF,SI,SI")])
3129 (define_insn "*pushxf_integer"
3130 [(set (match_operand:XF 0 "push_operand" "=<,<")
3131 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
3132 "!optimize_size && !TARGET_64BIT"
3135 switch (which_alternative)
3138 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3139 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3140 operands[2] = stack_pointer_rtx;
3141 operands[3] = GEN_INT (12);
3142 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3143 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3145 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3154 [(set_attr "type" "multi")
3155 (set_attr "mode" "XF,SI")])
3157 (define_insn "*pushtf_integer"
3158 [(set (match_operand:TF 0 "push_operand" "=<,<")
3159 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
3163 switch (which_alternative)
3166 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3167 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3168 operands[2] = stack_pointer_rtx;
3169 operands[3] = GEN_INT (16);
3171 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3172 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3174 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3176 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3177 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3179 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3188 [(set_attr "type" "multi")
3189 (set_attr "mode" "XF,SI")])
3192 [(set (match_operand 0 "push_operand" "")
3193 (match_operand 1 "general_operand" ""))]
3195 && (GET_MODE (operands[0]) == XFmode
3196 || GET_MODE (operands[0]) == TFmode
3197 || GET_MODE (operands[0]) == DFmode)
3198 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
3200 "ix86_split_long_move (operands); DONE;")
3203 [(set (match_operand:XF 0 "push_operand" "")
3204 (match_operand:XF 1 "register_operand" ""))]
3205 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3206 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3207 (set (mem:XF (reg:SI 7)) (match_dup 1))])
3210 [(set (match_operand:TF 0 "push_operand" "")
3211 (match_operand:TF 1 "register_operand" ""))]
3212 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3213 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3214 (set (mem:TF (reg:SI 7)) (match_dup 1))])
3217 [(set (match_operand:TF 0 "push_operand" "")
3218 (match_operand:TF 1 "register_operand" ""))]
3219 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3220 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3221 (set (mem:TF (reg:DI 7)) (match_dup 1))])
3223 ;; Do not use integer registers when optimizing for size
3224 (define_insn "*movxf_nointeger"
3225 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3226 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3227 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3230 && (reload_in_progress || reload_completed
3231 || GET_CODE (operands[1]) != CONST_DOUBLE
3232 || memory_operand (operands[0], XFmode))"
3235 switch (which_alternative)
3238 if (REG_P (operands[1])
3239 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3240 return \"fstp\\t%y0\";
3241 else if (STACK_TOP_P (operands[0]))
3242 return \"fld%z1\\t%y1\";
3244 return \"fst\\t%y0\";
3247 /* There is no non-popping store to memory for XFmode. So if
3248 we need one, follow the store with a load. */
3249 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3250 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3252 return \"fstp%z0\\t%y0\";
3255 switch (standard_80387_constant_p (operands[1]))
3269 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3270 (set_attr "mode" "XF,XF,XF,SI,SI")])
3272 (define_insn "*movtf_nointeger"
3273 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3274 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3275 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3277 && (reload_in_progress || reload_completed
3278 || GET_CODE (operands[1]) != CONST_DOUBLE
3279 || memory_operand (operands[0], TFmode))"
3282 switch (which_alternative)
3285 if (REG_P (operands[1])
3286 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3287 return \"fstp\\t%y0\";
3288 else if (STACK_TOP_P (operands[0]))
3289 return \"fld%z1\\t%y1\";
3291 return \"fst\\t%y0\";
3294 /* There is no non-popping store to memory for XFmode. So if
3295 we need one, follow the store with a load. */
3296 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3297 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3299 return \"fstp%z0\\t%y0\";
3302 switch (standard_80387_constant_p (operands[1]))
3316 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3317 (set_attr "mode" "XF,XF,XF,SI,SI")])
3319 (define_insn "*movxf_integer"
3320 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3321 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3322 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3325 && (reload_in_progress || reload_completed
3326 || GET_CODE (operands[1]) != CONST_DOUBLE
3327 || memory_operand (operands[0], XFmode))"
3330 switch (which_alternative)
3333 if (REG_P (operands[1])
3334 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3335 return \"fstp\\t%y0\";
3336 else if (STACK_TOP_P (operands[0]))
3337 return \"fld%z1\\t%y1\";
3339 return \"fst\\t%y0\";
3342 /* There is no non-popping store to memory for XFmode. So if
3343 we need one, follow the store with a load. */
3344 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3345 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3347 return \"fstp%z0\\t%y0\";
3350 switch (standard_80387_constant_p (operands[1]))
3364 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3365 (set_attr "mode" "XF,XF,XF,SI,SI")])
3367 (define_insn "*movtf_integer"
3368 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3369 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3370 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3372 && (reload_in_progress || reload_completed
3373 || GET_CODE (operands[1]) != CONST_DOUBLE
3374 || memory_operand (operands[0], TFmode))"
3377 switch (which_alternative)
3380 if (REG_P (operands[1])
3381 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3382 return \"fstp\\t%y0\";
3383 else if (STACK_TOP_P (operands[0]))
3384 return \"fld%z1\\t%y1\";
3386 return \"fst\\t%y0\";
3389 /* There is no non-popping store to memory for XFmode. So if
3390 we need one, follow the store with a load. */
3391 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3392 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3394 return \"fstp%z0\\t%y0\";
3397 switch (standard_80387_constant_p (operands[1]))
3411 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3412 (set_attr "mode" "XF,XF,XF,SI,SI")])
3415 [(set (match_operand 0 "nonimmediate_operand" "")
3416 (match_operand 1 "general_operand" ""))]
3418 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3419 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3420 && ! (ANY_FP_REG_P (operands[0]) ||
3421 (GET_CODE (operands[0]) == SUBREG
3422 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3423 && ! (ANY_FP_REG_P (operands[1]) ||
3424 (GET_CODE (operands[1]) == SUBREG
3425 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3427 "ix86_split_long_move (operands); DONE;")
3430 [(set (match_operand 0 "register_operand" "")
3431 (match_operand 1 "memory_operand" ""))]
3433 && GET_CODE (operands[1]) == MEM
3434 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3435 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3436 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3437 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3438 && (!(SSE_REG_P (operands[0]) ||
3439 (GET_CODE (operands[0]) == SUBREG
3440 && SSE_REG_P (SUBREG_REG (operands[0]))))
3441 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3442 && (!(FP_REG_P (operands[0]) ||
3443 (GET_CODE (operands[0]) == SUBREG
3444 && FP_REG_P (SUBREG_REG (operands[0]))))
3445 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3448 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3450 (define_insn "swapxf"
3451 [(set (match_operand:XF 0 "register_operand" "+f")
3452 (match_operand:XF 1 "register_operand" "+f"))
3458 if (STACK_TOP_P (operands[0]))
3459 return \"fxch\\t%1\";
3461 return \"fxch\\t%0\";
3463 [(set_attr "type" "fxch")
3464 (set_attr "mode" "XF")])
3466 (define_insn "swaptf"
3467 [(set (match_operand:TF 0 "register_operand" "+f")
3468 (match_operand:TF 1 "register_operand" "+f"))
3474 if (STACK_TOP_P (operands[0]))
3475 return \"fxch\\t%1\";
3477 return \"fxch\\t%0\";
3479 [(set_attr "type" "fxch")
3480 (set_attr "mode" "XF")])
3482 ;; Zero extension instructions
3484 (define_expand "zero_extendhisi2"
3485 [(set (match_operand:SI 0 "register_operand" "")
3486 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3490 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3492 operands[1] = force_reg (HImode, operands[1]);
3493 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3498 (define_insn "zero_extendhisi2_and"
3499 [(set (match_operand:SI 0 "register_operand" "=r")
3500 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3501 (clobber (reg:CC 17))]
3502 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3504 [(set_attr "type" "alu1")
3505 (set_attr "mode" "SI")])
3508 [(set (match_operand:SI 0 "register_operand" "")
3509 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3510 (clobber (reg:CC 17))]
3511 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3512 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3513 (clobber (reg:CC 17))])]
3516 (define_insn "*zero_extendhisi2_movzwl"
3517 [(set (match_operand:SI 0 "register_operand" "=r")
3518 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3519 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3520 "movz{wl|x}\\t{%1, %0|%0, %1}"
3521 [(set_attr "type" "imovx")
3522 (set_attr "mode" "SI")])
3524 (define_expand "zero_extendqihi2"
3526 [(set (match_operand:HI 0 "register_operand" "")
3527 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3528 (clobber (reg:CC 17))])]
3532 (define_insn "*zero_extendqihi2_and"
3533 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3534 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3535 (clobber (reg:CC 17))]
3536 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3538 [(set_attr "type" "alu1")
3539 (set_attr "mode" "HI")])
3541 (define_insn "*zero_extendqihi2_movzbw_and"
3542 [(set (match_operand:HI 0 "register_operand" "=r,r")
3543 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3544 (clobber (reg:CC 17))]
3545 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3547 [(set_attr "type" "imovx,alu1")
3548 (set_attr "mode" "HI")])
3550 (define_insn "*zero_extendqihi2_movzbw"
3551 [(set (match_operand:HI 0 "register_operand" "=r")
3552 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3553 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3554 "movz{bw|x}\\t{%1, %0|%0, %1}"
3555 [(set_attr "type" "imovx")
3556 (set_attr "mode" "HI")])
3558 ;; For the movzbw case strip only the clobber
3560 [(set (match_operand:HI 0 "register_operand" "")
3561 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3562 (clobber (reg:CC 17))]
3564 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3565 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3566 [(set (match_operand:HI 0 "register_operand" "")
3567 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3569 ;; When source and destination does not overlap, clear destination
3570 ;; first and then do the movb
3572 [(set (match_operand:HI 0 "register_operand" "")
3573 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3574 (clobber (reg:CC 17))]
3576 && ANY_QI_REG_P (operands[0])
3577 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3578 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3579 [(set (match_dup 0) (const_int 0))
3580 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3581 "operands[2] = gen_lowpart (QImode, operands[0]);")
3583 ;; Rest is handled by single and.
3585 [(set (match_operand:HI 0 "register_operand" "")
3586 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3587 (clobber (reg:CC 17))]
3589 && true_regnum (operands[0]) == true_regnum (operands[1])"
3590 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3591 (clobber (reg:CC 17))])]
3594 (define_expand "zero_extendqisi2"
3596 [(set (match_operand:SI 0 "register_operand" "")
3597 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3598 (clobber (reg:CC 17))])]
3602 (define_insn "*zero_extendqisi2_and"
3603 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3604 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3605 (clobber (reg:CC 17))]
3606 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3608 [(set_attr "type" "alu1")
3609 (set_attr "mode" "SI")])
3611 (define_insn "*zero_extendqisi2_movzbw_and"
3612 [(set (match_operand:SI 0 "register_operand" "=r,r")
3613 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3614 (clobber (reg:CC 17))]
3615 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3617 [(set_attr "type" "imovx,alu1")
3618 (set_attr "mode" "SI")])
3620 (define_insn "*zero_extendqisi2_movzbw"
3621 [(set (match_operand:SI 0 "register_operand" "=r")
3622 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3623 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3624 "movz{bl|x}\\t{%1, %0|%0, %1}"
3625 [(set_attr "type" "imovx")
3626 (set_attr "mode" "SI")])
3628 ;; For the movzbl case strip only the clobber
3630 [(set (match_operand:SI 0 "register_operand" "")
3631 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3632 (clobber (reg:CC 17))]
3634 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3635 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3637 (zero_extend:SI (match_dup 1)))])
3639 ;; When source and destination does not overlap, clear destination
3640 ;; first and then do the movb
3642 [(set (match_operand:SI 0 "register_operand" "")
3643 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3644 (clobber (reg:CC 17))]
3646 && ANY_QI_REG_P (operands[0])
3647 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3648 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3649 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3650 [(set (match_dup 0) (const_int 0))
3651 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3652 "operands[2] = gen_lowpart (QImode, operands[0]);")
3654 ;; Rest is handled by single and.
3656 [(set (match_operand:SI 0 "register_operand" "")
3657 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3658 (clobber (reg:CC 17))]
3660 && true_regnum (operands[0]) == true_regnum (operands[1])"
3661 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3662 (clobber (reg:CC 17))])]
3665 ;; %%% Kill me once multi-word ops are sane.
3666 (define_expand "zero_extendsidi2"
3667 [(set (match_operand:DI 0 "register_operand" "=r")
3668 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3672 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3677 (define_insn "zero_extendsidi2_32"
3678 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3679 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3680 (clobber (reg:CC 17))]
3683 [(set_attr "mode" "SI")])
3685 (define_insn "zero_extendsidi2_rex64"
3686 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3687 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3690 mov\\t{%k1, %k0|%k0, %k1}
3692 [(set_attr "type" "imovx,imov")
3693 (set_attr "mode" "SI,DI")])
3696 [(set (match_operand:DI 0 "memory_operand" "")
3697 (zero_extend:DI (match_dup 0)))]
3699 [(set (match_dup 4) (const_int 0))]
3700 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3703 [(set (match_operand:DI 0 "register_operand" "")
3704 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3705 (clobber (reg:CC 17))]
3706 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
3708 [(set (match_dup 4) (const_int 0))]
3709 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3712 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3713 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3714 (clobber (reg:CC 17))]
3715 "reload_completed && !TARGET_64BIT"
3716 [(set (match_dup 3) (match_dup 1))
3717 (set (match_dup 4) (const_int 0))]
3718 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3720 (define_insn "zero_extendhidi2"
3721 [(set (match_operand:DI 0 "register_operand" "=r,r")
3722 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3725 movz{wl|x}\\t{%1, %k0|%k0, %1}
3726 movz{wq|x}\\t{%1, %0|%0, %1}"
3727 [(set_attr "type" "imovx")
3728 (set_attr "mode" "SI,DI")])
3730 (define_insn "zero_extendqidi2"
3731 [(set (match_operand:DI 0 "register_operand" "=r,r")
3732 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3735 movz{bl|x}\\t{%1, %k0|%k0, %1}
3736 movz{bq|x}\\t{%1, %0|%0, %1}"
3737 [(set_attr "type" "imovx")
3738 (set_attr "mode" "SI,DI")])
3740 ;; Sign extension instructions
3742 (define_expand "extendsidi2"
3743 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3744 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3745 (clobber (reg:CC 17))
3746 (clobber (match_scratch:SI 2 ""))])]
3752 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3757 (define_insn "*extendsidi2_1"
3758 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3759 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3760 (clobber (reg:CC 17))
3761 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3765 (define_insn "extendsidi2_rex64"
3766 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3767 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3771 movs{lq|x}\\t{%1,%0|%0, %1}"
3772 [(set_attr "type" "imovx")
3773 (set_attr "mode" "DI")
3774 (set_attr "prefix_0f" "0")
3775 (set_attr "modrm" "0,1")])
3777 (define_insn "extendhidi2"
3778 [(set (match_operand:DI 0 "register_operand" "=r")
3779 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3781 "movs{wq|x}\\t{%1,%0|%0, %1}"
3782 [(set_attr "type" "imovx")
3783 (set_attr "mode" "DI")])
3785 (define_insn "extendqidi2"
3786 [(set (match_operand:DI 0 "register_operand" "=r")
3787 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3789 "movs{bq|x}\\t{%1,%0|%0, %1}"
3790 [(set_attr "type" "imovx")
3791 (set_attr "mode" "DI")])
3793 ;; Extend to memory case when source register does die.
3795 [(set (match_operand:DI 0 "memory_operand" "")
3796 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3797 (clobber (reg:CC 17))
3798 (clobber (match_operand:SI 2 "register_operand" ""))]
3800 && dead_or_set_p (insn, operands[1])
3801 && !reg_mentioned_p (operands[1], operands[0]))"
3802 [(set (match_dup 3) (match_dup 1))
3803 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3804 (clobber (reg:CC 17))])
3805 (set (match_dup 4) (match_dup 1))]
3806 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3808 ;; Extend to memory case when source register does not die.
3810 [(set (match_operand:DI 0 "memory_operand" "")
3811 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3812 (clobber (reg:CC 17))
3813 (clobber (match_operand:SI 2 "register_operand" ""))]
3818 split_di (&operands[0], 1, &operands[3], &operands[4]);
3820 emit_move_insn (operands[3], operands[1]);
3822 /* Generate a cltd if possible and doing so it profitable. */
3823 if (true_regnum (operands[1]) == 0
3824 && true_regnum (operands[2]) == 1
3825 && (optimize_size || TARGET_USE_CLTD))
3827 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3831 emit_move_insn (operands[2], operands[1]);
3832 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3834 emit_move_insn (operands[4], operands[2]);
3838 ;; Extend to register case. Optimize case where source and destination
3839 ;; registers match and cases where we can use cltd.
3841 [(set (match_operand:DI 0 "register_operand" "")
3842 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3843 (clobber (reg:CC 17))
3844 (clobber (match_scratch:SI 2 ""))]
3849 split_di (&operands[0], 1, &operands[3], &operands[4]);
3851 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3852 emit_move_insn (operands[3], operands[1]);
3854 /* Generate a cltd if possible and doing so it profitable. */
3855 if (true_regnum (operands[3]) == 0
3856 && (optimize_size || TARGET_USE_CLTD))
3858 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3862 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3863 emit_move_insn (operands[4], operands[1]);
3865 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3869 (define_insn "extendhisi2"
3870 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3871 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3875 switch (get_attr_prefix_0f (insn))
3878 return \"{cwtl|cwde}\";
3880 return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
3883 [(set_attr "type" "imovx")
3884 (set_attr "mode" "SI")
3885 (set (attr "prefix_0f")
3886 ;; movsx is short decodable while cwtl is vector decoded.
3887 (if_then_else (and (eq_attr "cpu" "!k6")
3888 (eq_attr "alternative" "0"))
3890 (const_string "1")))
3892 (if_then_else (eq_attr "prefix_0f" "0")
3894 (const_string "1")))])
3896 (define_insn "*extendhisi2_zext"
3897 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3899 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3903 switch (get_attr_prefix_0f (insn))
3906 return \"{cwtl|cwde}\";
3908 return \"movs{wl|x}\\t{%1,%k0|%k0, %1}\";
3911 [(set_attr "type" "imovx")
3912 (set_attr "mode" "SI")
3913 (set (attr "prefix_0f")
3914 ;; movsx is short decodable while cwtl is vector decoded.
3915 (if_then_else (and (eq_attr "cpu" "!k6")
3916 (eq_attr "alternative" "0"))
3918 (const_string "1")))
3920 (if_then_else (eq_attr "prefix_0f" "0")
3922 (const_string "1")))])
3924 (define_insn "extendqihi2"
3925 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3926 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3930 switch (get_attr_prefix_0f (insn))
3933 return \"{cbtw|cbw}\";
3935 return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
3938 [(set_attr "type" "imovx")
3939 (set_attr "mode" "HI")
3940 (set (attr "prefix_0f")
3941 ;; movsx is short decodable while cwtl is vector decoded.
3942 (if_then_else (and (eq_attr "cpu" "!k6")
3943 (eq_attr "alternative" "0"))
3945 (const_string "1")))
3947 (if_then_else (eq_attr "prefix_0f" "0")
3949 (const_string "1")))])
3951 (define_insn "extendqisi2"
3952 [(set (match_operand:SI 0 "register_operand" "=r")
3953 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3955 "movs{bl|x}\\t{%1,%0|%0, %1}"
3956 [(set_attr "type" "imovx")
3957 (set_attr "mode" "SI")])
3959 (define_insn "*extendqisi2_zext"
3960 [(set (match_operand:DI 0 "register_operand" "=r")
3962 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3964 "movs{bl|x}\\t{%1,%k0|%k0, %1}"
3965 [(set_attr "type" "imovx")
3966 (set_attr "mode" "SI")])
3968 ;; Conversions between float and double.
3970 ;; These are all no-ops in the model used for the 80387. So just
3973 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3974 (define_insn "*dummy_extendsfdf2"
3975 [(set (match_operand:DF 0 "push_operand" "=<")
3976 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3981 [(set (match_operand:DF 0 "push_operand" "")
3982 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3983 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3984 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3985 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3988 [(set (match_operand:DF 0 "push_operand" "")
3989 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3990 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3991 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3992 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3994 (define_insn "*dummy_extendsfxf2"
3995 [(set (match_operand:XF 0 "push_operand" "=<")
3996 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
4001 [(set (match_operand:XF 0 "push_operand" "")
4002 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
4003 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4004 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4005 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4007 (define_insn "*dummy_extendsftf2"
4008 [(set (match_operand:TF 0 "push_operand" "=<")
4009 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
4014 [(set (match_operand:TF 0 "push_operand" "")
4015 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4016 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4017 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4018 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
4021 [(set (match_operand:TF 0 "push_operand" "")
4022 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4023 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4024 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4025 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
4027 (define_insn "*dummy_extenddfxf2"
4028 [(set (match_operand:XF 0 "push_operand" "=<")
4029 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4034 [(set (match_operand:XF 0 "push_operand" "")
4035 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
4036 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4037 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4038 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4040 (define_insn "*dummy_extenddftf2"
4041 [(set (match_operand:TF 0 "push_operand" "=<")
4042 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4047 [(set (match_operand:TF 0 "push_operand" "")
4048 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4049 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4050 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4051 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4054 [(set (match_operand:TF 0 "push_operand" "")
4055 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4056 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4057 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4058 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
4060 (define_expand "extendsfdf2"
4061 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4062 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
4063 "TARGET_80387 || TARGET_SSE2"
4066 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4067 operands[1] = force_reg (SFmode, operands[1]);
4070 (define_insn "*extendsfdf2_1"
4071 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
4072 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
4073 "(TARGET_80387 || TARGET_SSE2)
4074 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4077 switch (which_alternative)
4080 if (REG_P (operands[1])
4081 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4082 return \"fstp\\t%y0\";
4083 else if (STACK_TOP_P (operands[0]))
4084 return \"fld%z1\\t%y1\";
4086 return \"fst\\t%y0\";
4089 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4090 return \"fstp%z0\\t%y0\";
4093 return \"fst%z0\\t%y0\";
4095 return \"cvtss2sd\\t{%1, %0|%0, %1}\";
4101 [(set_attr "type" "fmov,fmov,sse")
4102 (set_attr "mode" "SF,XF,DF")])
4104 (define_insn "*extendsfdf2_1_sse_only"
4105 [(set (match_operand:DF 0 "register_operand" "=Y")
4106 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
4107 "!TARGET_80387 && TARGET_SSE2
4108 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4109 "cvtss2sd\\t{%1, %0|%0, %1}"
4110 [(set_attr "type" "sse")
4111 (set_attr "mode" "DF")])
4113 (define_expand "extendsfxf2"
4114 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4115 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
4116 "TARGET_80387 && !TARGET_64BIT"
4119 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4120 operands[1] = force_reg (SFmode, operands[1]);
4123 (define_insn "*extendsfxf2_1"
4124 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4125 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4126 "TARGET_80387 && !TARGET_64BIT
4127 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4130 switch (which_alternative)
4133 if (REG_P (operands[1])
4134 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4135 return \"fstp\\t%y0\";
4136 else if (STACK_TOP_P (operands[0]))
4137 return \"fld%z1\\t%y1\";
4139 return \"fst\\t%y0\";
4142 /* There is no non-popping store to memory for XFmode. So if
4143 we need one, follow the store with a load. */
4144 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4145 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4147 return \"fstp%z0\\t%y0\";
4153 [(set_attr "type" "fmov")
4154 (set_attr "mode" "SF,XF")])
4156 (define_expand "extendsftf2"
4157 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4158 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
4162 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4163 operands[1] = force_reg (SFmode, operands[1]);
4166 (define_insn "*extendsftf2_1"
4167 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4168 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4170 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4173 switch (which_alternative)
4176 if (REG_P (operands[1])
4177 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4178 return \"fstp\\t%y0\";
4179 else if (STACK_TOP_P (operands[0]))
4180 return \"fld%z1\\t%y1\";
4182 return \"fst\\t%y0\";
4185 /* There is no non-popping store to memory for XFmode. So if
4186 we need one, follow the store with a load. */
4187 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4188 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4190 return \"fstp%z0\\t%y0\";
4196 [(set_attr "type" "fmov")
4197 (set_attr "mode" "SF,XF")])
4199 (define_expand "extenddfxf2"
4200 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4201 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
4202 "TARGET_80387 && !TARGET_64BIT"
4205 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4206 operands[1] = force_reg (DFmode, operands[1]);
4209 (define_insn "*extenddfxf2_1"
4210 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4211 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4212 "TARGET_80387 && !TARGET_64BIT
4213 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4216 switch (which_alternative)
4219 if (REG_P (operands[1])
4220 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4221 return \"fstp\\t%y0\";
4222 else if (STACK_TOP_P (operands[0]))
4223 return \"fld%z1\\t%y1\";
4225 return \"fst\\t%y0\";
4228 /* There is no non-popping store to memory for XFmode. So if
4229 we need one, follow the store with a load. */
4230 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4231 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4233 return \"fstp%z0\\t%y0\";
4239 [(set_attr "type" "fmov")
4240 (set_attr "mode" "DF,XF")])
4242 (define_expand "extenddftf2"
4243 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4244 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
4248 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4249 operands[1] = force_reg (DFmode, operands[1]);
4252 (define_insn "*extenddftf2_1"
4253 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4254 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4256 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4259 switch (which_alternative)
4262 if (REG_P (operands[1])
4263 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4264 return \"fstp\\t%y0\";
4265 else if (STACK_TOP_P (operands[0]))
4266 return \"fld%z1\\t%y1\";
4268 return \"fst\\t%y0\";
4271 /* There is no non-popping store to memory for XFmode. So if
4272 we need one, follow the store with a load. */
4273 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4274 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4276 return \"fstp%z0\\t%y0\";
4282 [(set_attr "type" "fmov")
4283 (set_attr "mode" "DF,XF")])
4285 ;; %%% This seems bad bad news.
4286 ;; This cannot output into an f-reg because there is no way to be sure
4287 ;; of truncating in that case. Otherwise this is just like a simple move
4288 ;; insn. So we pretend we can output to a reg in order to get better
4289 ;; register preferencing, but we really use a stack slot.
4291 (define_expand "truncdfsf2"
4292 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4294 (match_operand:DF 1 "register_operand" "")))
4295 (clobber (match_dup 2))])]
4296 "TARGET_80387 || TARGET_SSE2"
4299 operands[2] = assign_386_stack_local (SFmode, 0);
4302 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4307 (define_insn "*truncdfsf2_1"
4308 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4310 (match_operand:DF 1 "register_operand" "f,f,f,f")))
4311 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4312 "TARGET_80387 && !TARGET_SSE2"
4315 switch (which_alternative)
4318 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4319 return \"fstp%z0\\t%y0\";
4321 return \"fst%z0\\t%y0\";
4326 [(set_attr "type" "fmov,multi,multi,multi")
4327 (set_attr "mode" "SF,SF,SF,SF")])
4329 (define_insn "*truncdfsf2_1_sse"
4330 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
4332 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
4333 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
4334 "TARGET_80387 && TARGET_SSE2"
4337 switch (which_alternative)
4340 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4341 return \"fstp%z0\\t%y0\";
4343 return \"fst%z0\\t%y0\";
4345 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4350 [(set_attr "type" "fmov,multi,multi,multi,sse")
4351 (set_attr "mode" "SF,SF,SF,SF,DF")])
4353 (define_insn "*truncdfsf2_2"
4354 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
4356 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4357 "TARGET_80387 && TARGET_SSE2
4358 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4361 switch (which_alternative)
4364 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4366 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4367 return \"fstp%z0\\t%y0\";
4369 return \"fst%z0\\t%y0\";
4372 [(set_attr "type" "sse,fmov")
4373 (set_attr "mode" "DF,SF")])
4375 (define_insn "truncdfsf2_3"
4376 [(set (match_operand:SF 0 "memory_operand" "=m")
4378 (match_operand:DF 1 "register_operand" "f")))]
4382 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4383 return \"fstp%z0\\t%y0\";
4385 return \"fst%z0\\t%y0\";
4387 [(set_attr "type" "fmov")
4388 (set_attr "mode" "SF")])
4390 (define_insn "truncdfsf2_sse_only"
4391 [(set (match_operand:SF 0 "register_operand" "=Y")
4393 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4394 "!TARGET_80387 && TARGET_SSE2"
4395 "cvtsd2ss\\t{%1, %0|%0, %1}"
4396 [(set_attr "type" "sse")
4397 (set_attr "mode" "DF")])
4400 [(set (match_operand:SF 0 "memory_operand" "")
4402 (match_operand:DF 1 "register_operand" "")))
4403 (clobber (match_operand:SF 2 "memory_operand" ""))]
4405 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4409 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4411 (match_operand:DF 1 "nonimmediate_operand" "")))
4412 (clobber (match_operand 2 "" ""))]
4413 "TARGET_80387 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
4414 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4418 [(set (match_operand:SF 0 "register_operand" "")
4420 (match_operand:DF 1 "register_operand" "")))
4421 (clobber (match_operand:SF 2 "memory_operand" ""))]
4422 "TARGET_80387 && reload_completed
4423 && FP_REG_P (operands[1])"
4424 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4425 (set (match_dup 0) (match_dup 2))]
4428 (define_expand "truncxfsf2"
4429 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4431 (match_operand:XF 1 "register_operand" "")))
4432 (clobber (match_dup 2))])]
4433 "TARGET_80387 && !TARGET_64BIT"
4434 "operands[2] = assign_386_stack_local (SFmode, 0);")
4436 (define_insn "*truncxfsf2_1"
4437 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4439 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4440 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4441 "TARGET_80387 && !TARGET_64BIT"
4444 switch (which_alternative)
4447 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4448 return \"fstp%z0\\t%y0\";
4450 return \"fst%z0\\t%y0\";
4455 [(set_attr "type" "fmov,multi,multi,multi")
4456 (set_attr "mode" "SF")])
4458 (define_insn "*truncxfsf2_2"
4459 [(set (match_operand:SF 0 "memory_operand" "=m")
4461 (match_operand:XF 1 "register_operand" "f")))]
4462 "TARGET_80387 && !TARGET_64BIT"
4465 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4466 return \"fstp%z0\\t%y0\";
4468 return \"fst%z0\\t%y0\";
4470 [(set_attr "type" "fmov")
4471 (set_attr "mode" "SF")])
4474 [(set (match_operand:SF 0 "memory_operand" "")
4476 (match_operand:XF 1 "register_operand" "")))
4477 (clobber (match_operand:SF 2 "memory_operand" ""))]
4479 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4483 [(set (match_operand:SF 0 "register_operand" "")
4485 (match_operand:XF 1 "register_operand" "")))
4486 (clobber (match_operand:SF 2 "memory_operand" ""))]
4487 "TARGET_80387 && reload_completed"
4488 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4489 (set (match_dup 0) (match_dup 2))]
4492 (define_expand "trunctfsf2"
4493 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4495 (match_operand:TF 1 "register_operand" "")))
4496 (clobber (match_dup 2))])]
4498 "operands[2] = assign_386_stack_local (SFmode, 0);")
4500 (define_insn "*trunctfsf2_1"
4501 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4503 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4504 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4508 switch (which_alternative)
4511 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4512 return \"fstp%z0\\t%y0\";
4514 return \"fst%z0\\t%y0\";
4519 [(set_attr "type" "fmov,multi,multi,multi")
4520 (set_attr "mode" "SF")])
4522 (define_insn "*trunctfsf2_2"
4523 [(set (match_operand:SF 0 "memory_operand" "=m")
4525 (match_operand:TF 1 "register_operand" "f")))]
4529 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4530 return \"fstp%z0\\t%y0\";
4532 return \"fst%z0\\t%y0\";
4534 [(set_attr "type" "fmov")
4535 (set_attr "mode" "SF")])
4538 [(set (match_operand:SF 0 "memory_operand" "")
4540 (match_operand:TF 1 "register_operand" "")))
4541 (clobber (match_operand:SF 2 "memory_operand" ""))]
4543 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4547 [(set (match_operand:SF 0 "register_operand" "")
4549 (match_operand:TF 1 "register_operand" "")))
4550 (clobber (match_operand:SF 2 "memory_operand" ""))]
4551 "TARGET_80387 && reload_completed"
4552 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4553 (set (match_dup 0) (match_dup 2))]
4557 (define_expand "truncxfdf2"
4558 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4560 (match_operand:XF 1 "register_operand" "")))
4561 (clobber (match_dup 2))])]
4562 "TARGET_80387 && !TARGET_64BIT"
4563 "operands[2] = assign_386_stack_local (DFmode, 0);")
4565 (define_insn "*truncxfdf2_1"
4566 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4568 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4569 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4570 "TARGET_80387 && !TARGET_64BIT"
4573 switch (which_alternative)
4576 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4577 return \"fstp%z0\\t%y0\";
4579 return \"fst%z0\\t%y0\";
4585 [(set_attr "type" "fmov,multi,multi,multi")
4586 (set_attr "mode" "DF")])
4588 (define_insn "*truncxfdf2_2"
4589 [(set (match_operand:DF 0 "memory_operand" "=m")
4591 (match_operand:XF 1 "register_operand" "f")))]
4592 "TARGET_80387 && !TARGET_64BIT"
4595 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4596 return \"fstp%z0\\t%y0\";
4598 return \"fst%z0\\t%y0\";
4600 [(set_attr "type" "fmov")
4601 (set_attr "mode" "DF")])
4604 [(set (match_operand:DF 0 "memory_operand" "")
4606 (match_operand:XF 1 "register_operand" "")))
4607 (clobber (match_operand:DF 2 "memory_operand" ""))]
4609 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4613 [(set (match_operand:DF 0 "register_operand" "")
4615 (match_operand:XF 1 "register_operand" "")))
4616 (clobber (match_operand:DF 2 "memory_operand" ""))]
4617 "TARGET_80387 && reload_completed"
4618 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4619 (set (match_dup 0) (match_dup 2))]
4622 (define_expand "trunctfdf2"
4623 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4625 (match_operand:TF 1 "register_operand" "")))
4626 (clobber (match_dup 2))])]
4628 "operands[2] = assign_386_stack_local (DFmode, 0);")
4630 (define_insn "*trunctfdf2_1"
4631 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4633 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4634 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4638 switch (which_alternative)
4641 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4642 return \"fstp%z0\\t%y0\";
4644 return \"fst%z0\\t%y0\";
4650 [(set_attr "type" "fmov,multi,multi,multi")
4651 (set_attr "mode" "DF")])
4653 (define_insn "*trunctfdf2_2"
4654 [(set (match_operand:DF 0 "memory_operand" "=m")
4656 (match_operand:TF 1 "register_operand" "f")))]
4660 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4661 return \"fstp%z0\\t%y0\";
4663 return \"fst%z0\\t%y0\";
4665 [(set_attr "type" "fmov")
4666 (set_attr "mode" "DF")])
4669 [(set (match_operand:DF 0 "memory_operand" "")
4671 (match_operand:TF 1 "register_operand" "")))
4672 (clobber (match_operand:DF 2 "memory_operand" ""))]
4674 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4678 [(set (match_operand:DF 0 "register_operand" "")
4680 (match_operand:TF 1 "register_operand" "")))
4681 (clobber (match_operand:DF 2 "memory_operand" ""))]
4682 "TARGET_80387 && reload_completed"
4683 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4684 (set (match_dup 0) (match_dup 2))]
4688 ;; %%% Break up all these bad boys.
4690 ;; Signed conversion to DImode.
4692 (define_expand "fix_truncxfdi2"
4693 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4694 (fix:DI (match_operand:XF 1 "register_operand" "")))
4695 (clobber (match_dup 2))
4696 (clobber (match_dup 3))
4697 (clobber (match_scratch:SI 4 ""))
4698 (clobber (match_scratch:XF 5 ""))])]
4699 "TARGET_80387 && !TARGET_64BIT"
4700 "operands[2] = assign_386_stack_local (SImode, 0);
4701 operands[3] = assign_386_stack_local (DImode, 1);")
4703 (define_expand "fix_trunctfdi2"
4704 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4705 (fix:DI (match_operand:TF 1 "register_operand" "")))
4706 (clobber (match_dup 2))
4707 (clobber (match_dup 3))
4708 (clobber (match_scratch:SI 4 ""))
4709 (clobber (match_scratch:TF 5 ""))])]
4711 "operands[2] = assign_386_stack_local (SImode, 0);
4712 operands[3] = assign_386_stack_local (DImode, 1);")
4714 (define_expand "fix_truncdfdi2"
4715 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4716 (fix:DI (match_operand:DF 1 "register_operand" "")))
4717 (clobber (match_dup 2))
4718 (clobber (match_dup 3))
4719 (clobber (match_scratch:SI 4 ""))
4720 (clobber (match_scratch:DF 5 ""))])]
4721 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4724 if (TARGET_SSE2 && TARGET_64BIT)
4726 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4727 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4728 if (out != operands[0])
4729 emit_move_insn (operands[0], out);
4734 operands[2] = assign_386_stack_local (SImode, 0);
4735 operands[3] = assign_386_stack_local (DImode, 1);
4739 (define_expand "fix_truncsfdi2"
4740 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4741 (fix:DI (match_operand:SF 1 "register_operand" "")))
4742 (clobber (match_dup 2))
4743 (clobber (match_dup 3))
4744 (clobber (match_scratch:SI 4 ""))
4745 (clobber (match_scratch:SF 5 ""))])]
4746 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4749 if (TARGET_SSE2 && TARGET_64BIT)
4751 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4752 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4753 if (out != operands[0])
4754 emit_move_insn (operands[0], out);
4759 operands[2] = assign_386_stack_local (SImode, 0);
4760 operands[3] = assign_386_stack_local (DImode, 1);
4764 (define_insn "*fix_truncdi_1"
4765 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4766 (fix:DI (match_operand 1 "register_operand" "f,f")))
4767 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4768 (clobber (match_operand:DI 3 "memory_operand" "=m,m"))
4769 (clobber (match_scratch:SI 4 "=&r,&r"))
4770 (clobber (match_scratch 5 "=&f,&f"))]
4771 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4772 && (!TARGET_SSE2 || !TARGET_64BIT
4773 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4774 "* return output_fix_trunc (insn, operands);"
4775 [(set_attr "type" "multi")])
4778 [(set (match_operand:DI 0 "register_operand" "")
4779 (fix:DI (match_operand 1 "register_operand" "")))
4780 (clobber (match_operand:SI 2 "memory_operand" ""))
4781 (clobber (match_operand:DI 3 "memory_operand" ""))
4782 (clobber (match_scratch:SI 4 ""))
4783 (clobber (match_scratch 5 ""))]
4784 "reload_completed && !reg_overlap_mentioned_p (operands[4], operands[3])"
4785 [(parallel [(set (match_dup 3) (fix:DI (match_dup 1)))
4786 (clobber (match_dup 2))
4787 (clobber (match_dup 3))
4788 (clobber (match_dup 4))
4789 (clobber (match_dup 5))])
4790 (set (match_dup 0) (match_dup 3))]
4793 ;; When SSE available, it is always faster to use it!
4794 (define_insn "fix_truncsfdi_sse"
4795 [(set (match_operand:DI 0 "register_operand" "=r")
4796 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4797 "TARGET_SSE && TARGET_64BIT"
4798 "cvttss2si{q}\\t{%1, %0|%0, %1}"
4799 [(set_attr "type" "sse")])
4801 (define_insn "fix_truncdfdi_sse"
4802 [(set (match_operand:DI 0 "register_operand" "=r")
4803 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4804 "TARGET_SSE2 && TARGET_64BIT"
4805 "cvttsd2si{q}\\t{%1, %0|%0, %1}"
4806 [(set_attr "type" "sse")])
4808 ;; Signed conversion to SImode.
4810 (define_expand "fix_truncxfsi2"
4811 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4812 (fix:SI (match_operand:XF 1 "register_operand" "")))
4813 (clobber (match_dup 2))
4814 (clobber (match_dup 3))
4815 (clobber (match_scratch:SI 4 ""))])]
4816 "TARGET_80387 && !TARGET_64BIT"
4817 "operands[2] = assign_386_stack_local (SImode, 0);
4818 operands[3] = assign_386_stack_local (SImode, 1);")
4820 (define_expand "fix_trunctfsi2"
4821 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4822 (fix:SI (match_operand:TF 1 "register_operand" "")))
4823 (clobber (match_dup 2))
4824 (clobber (match_dup 3))
4825 (clobber (match_scratch:SI 4 ""))])]
4827 "operands[2] = assign_386_stack_local (SImode, 0);
4828 operands[3] = assign_386_stack_local (SImode, 1);")
4830 (define_expand "fix_truncdfsi2"
4831 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4832 (fix:SI (match_operand:DF 1 "register_operand" "")))
4833 (clobber (match_dup 2))
4834 (clobber (match_dup 3))
4835 (clobber (match_scratch:SI 4 ""))])]
4836 "TARGET_80387 || TARGET_SSE2"
4841 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4842 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4843 if (out != operands[0])
4844 emit_move_insn (operands[0], out);
4849 operands[2] = assign_386_stack_local (SImode, 0);
4850 operands[3] = assign_386_stack_local (SImode, 1);
4854 (define_expand "fix_truncsfsi2"
4855 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4856 (fix:SI (match_operand:SF 1 "register_operand" "")))
4857 (clobber (match_dup 2))
4858 (clobber (match_dup 3))
4859 (clobber (match_scratch:SI 4 ""))])]
4860 "TARGET_80387 || TARGET_SSE"
4865 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4866 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4867 if (out != operands[0])
4868 emit_move_insn (operands[0], out);
4873 operands[2] = assign_386_stack_local (SImode, 0);
4874 operands[3] = assign_386_stack_local (SImode, 1);
4878 (define_insn "*fix_truncsi_1"
4879 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4880 (fix:SI (match_operand 1 "register_operand" "f,f")))
4881 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4882 (clobber (match_operand:SI 3 "memory_operand" "=m,m"))
4883 (clobber (match_scratch:SI 4 "=&r,r"))]
4884 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4885 && (!TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4886 "* return output_fix_trunc (insn, operands);"
4887 [(set_attr "type" "multi")])
4889 ;; When SSE available, it is always faster to use it!
4890 (define_insn "fix_truncsfsi_sse"
4891 [(set (match_operand:SI 0 "register_operand" "=r")
4892 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4894 "cvttss2si\\t{%1, %0|%0, %1}"
4895 [(set_attr "type" "sse")])
4897 (define_insn "fix_truncdfsi_sse"
4898 [(set (match_operand:SI 0 "register_operand" "=r")
4899 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4901 "cvttsd2si\\t{%1, %0|%0, %1}"
4902 [(set_attr "type" "sse")])
4905 [(set (match_operand:SI 0 "register_operand" "")
4906 (fix:SI (match_operand 1 "register_operand" "")))
4907 (clobber (match_operand:SI 2 "memory_operand" ""))
4908 (clobber (match_operand:SI 3 "memory_operand" ""))
4909 (clobber (match_scratch:SI 4 ""))]
4911 [(parallel [(set (match_dup 3) (fix:SI (match_dup 1)))
4912 (clobber (match_dup 2))
4913 (clobber (match_dup 3))
4914 (clobber (match_dup 4))])
4915 (set (match_dup 0) (match_dup 3))]
4918 ;; Signed conversion to HImode.
4920 (define_expand "fix_truncxfhi2"
4921 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4922 (fix:HI (match_operand:XF 1 "register_operand" "")))
4923 (clobber (match_dup 2))
4924 (clobber (match_dup 3))
4925 (clobber (match_scratch:SI 4 ""))])]
4926 "TARGET_80387 && !TARGET_64BIT"
4927 "operands[2] = assign_386_stack_local (SImode, 0);
4928 operands[3] = assign_386_stack_local (HImode, 1);")
4930 (define_expand "fix_trunctfhi2"
4931 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4932 (fix:HI (match_operand:TF 1 "register_operand" "")))
4933 (clobber (match_dup 2))
4934 (clobber (match_dup 3))
4935 (clobber (match_scratch:SI 4 ""))])]
4937 "operands[2] = assign_386_stack_local (SImode, 0);
4938 operands[3] = assign_386_stack_local (HImode, 1);")
4940 (define_expand "fix_truncdfhi2"
4941 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4942 (fix:HI (match_operand:DF 1 "register_operand" "")))
4943 (clobber (match_dup 2))
4944 (clobber (match_dup 3))
4945 (clobber (match_scratch:SI 4 ""))])]
4946 "TARGET_80387 && !TARGET_SSE2"
4947 "operands[2] = assign_386_stack_local (SImode, 0);
4948 operands[3] = assign_386_stack_local (HImode, 1);")
4950 (define_expand "fix_truncsfhi2"
4951 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4952 (fix:HI (match_operand:SF 1 "register_operand" "")))
4953 (clobber (match_dup 2))
4954 (clobber (match_dup 3))
4955 (clobber (match_scratch:SI 4 ""))])]
4956 "TARGET_80387 && !TARGET_SSE"
4957 "operands[2] = assign_386_stack_local (SImode, 0);
4958 operands[3] = assign_386_stack_local (HImode, 1);")
4960 (define_insn "*fix_trunchi_1"
4961 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4962 (fix:HI (match_operand 1 "register_operand" "f,f")))
4963 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4964 (clobber (match_operand:HI 3 "memory_operand" "=m,m"))
4965 (clobber (match_scratch:SI 4 "=&r,r"))]
4966 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4967 && (TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4968 "* return output_fix_trunc (insn, operands);"
4969 [(set_attr "type" "multi")])
4972 [(set (match_operand:HI 0 "register_operand" "")
4973 (fix:HI (match_operand 1 "register_operand" "")))
4974 (clobber (match_operand:SI 2 "memory_operand" ""))
4975 (clobber (match_operand:HI 3 "memory_operand" ""))
4976 (clobber (match_scratch:SI 4 ""))]
4978 [(parallel [(set (match_dup 3) (fix:HI (match_dup 1)))
4979 (clobber (match_dup 2))
4980 (clobber (match_dup 3))
4981 (clobber (match_dup 4))])
4982 (set (match_dup 0) (match_dup 3))]
4985 ;; %%% Kill these when reload knows how to do it.
4987 [(set (match_operand 0 "register_operand" "")
4988 (fix (match_operand 1 "register_operand" "")))]
4989 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[1]))
4990 && FP_REG_P (operands[1])"
4994 operands[2] = ix86_force_to_memory (GET_MODE (operands[0]), operands[0]);
4995 operands[2] = gen_rtx_FIX (GET_MODE (operands[2]), operands[1]);
4996 emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1]));
4997 emit_move_insn (operands[0], operands[2]);
4998 ix86_free_from_memory (GET_MODE (operands[0]));
5003 (define_insn "x86_fnstcw_1"
5004 [(set (match_operand:HI 0 "memory_operand" "=m")
5005 (unspec:HI [(reg:HI 18)] 11))]
5008 [(set_attr "length" "2")
5009 (set_attr "mode" "HI")
5010 (set_attr "i387" "1")
5011 (set_attr "ppro_uops" "few")])
5013 (define_insn "x86_fldcw_1"
5015 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
5018 [(set_attr "length" "2")
5019 (set_attr "mode" "HI")
5020 (set_attr "i387" "1")
5021 (set_attr "athlon_decode" "vector")
5022 (set_attr "ppro_uops" "few")])
5024 ;; Conversion between fixed point and floating point.
5026 ;; Even though we only accept memory inputs, the backend _really_
5027 ;; wants to be able to do this between registers.
5029 (define_insn "floathisf2"
5030 [(set (match_operand:SF 0 "register_operand" "=f,f")
5031 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5032 "TARGET_80387 && !TARGET_SSE"
5036 [(set_attr "type" "fmov,multi")
5037 (set_attr "mode" "SF")
5038 (set_attr "fp_int_src" "true")])
5040 (define_expand "floatsisf2"
5041 [(set (match_operand:SF 0 "register_operand" "")
5042 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5043 "TARGET_SSE || TARGET_80387"
5046 (define_insn "*floatsisf2_i387"
5047 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5048 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5049 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5053 cvtsi2ss\\t{%1, %0|%0, %1}"
5054 [(set_attr "type" "fmov,multi,sse")
5055 (set_attr "mode" "SF")
5056 (set_attr "fp_int_src" "true")])
5058 (define_insn "*floatsisf2_sse"
5059 [(set (match_operand:SF 0 "register_operand" "=x")
5060 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5062 "cvtsi2ss\\t{%1, %0|%0, %1}"
5063 [(set_attr "type" "sse")
5064 (set_attr "mode" "SF")
5065 (set_attr "fp_int_src" "true")])
5067 (define_expand "floatdisf2"
5068 [(set (match_operand:SF 0 "register_operand" "")
5069 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
5070 "(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
5073 (define_insn "*floatdisf2_i387_only"
5074 [(set (match_operand:SF 0 "register_operand" "=f,?f")
5075 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5076 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
5080 [(set_attr "type" "fmov,multi")
5081 (set_attr "mode" "SF")
5082 (set_attr "fp_int_src" "true")])
5084 (define_insn "*floatdisf2_i387"
5085 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5086 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5087 "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5091 cvtsi2ss{q}\\t{%1, %0|%0, %1}"
5092 [(set_attr "type" "fmov,multi,sse")
5093 (set_attr "mode" "SF")
5094 (set_attr "fp_int_src" "true")])
5096 (define_insn "*floatdisf2_sse"
5097 [(set (match_operand:SF 0 "register_operand" "=x")
5098 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5099 "TARGET_SSE && TARGET_64BIT"
5100 "cvtsi2ss{q}\\t{%1, %0|%0, %1}"
5101 [(set_attr "type" "sse")
5102 (set_attr "mode" "SF")
5103 (set_attr "fp_int_src" "true")])
5105 (define_insn "floathidf2"
5106 [(set (match_operand:DF 0 "register_operand" "=f,f")
5107 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5108 "TARGET_80387 && !TARGET_SSE2"
5112 [(set_attr "type" "fmov,multi")
5113 (set_attr "mode" "DF")
5114 (set_attr "fp_int_src" "true")])
5116 (define_expand "floatsidf2"
5117 [(set (match_operand:DF 0 "register_operand" "")
5118 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5122 (define_insn "*floatsidf2_i387"
5123 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5124 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5125 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5129 cvtsi2sd\\t{%1, %0|%0, %1}"
5130 [(set_attr "type" "fmov,multi,sse")
5131 (set_attr "mode" "DF")
5132 (set_attr "fp_int_src" "true")])
5134 (define_insn "*floatsidf2_sse"
5135 [(set (match_operand:DF 0 "register_operand" "=Y")
5136 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5138 "cvtsi2sd\\t{%1, %0|%0, %1}"
5139 [(set_attr "type" "sse")
5140 (set_attr "mode" "DF")
5141 (set_attr "fp_int_src" "true")])
5143 (define_expand "floatdidf2"
5144 [(set (match_operand:DF 0 "register_operand" "")
5145 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5146 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
5149 (define_insn "*floatdidf2_i387_only"
5150 [(set (match_operand:DF 0 "register_operand" "=f,?f")
5151 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5152 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
5156 [(set_attr "type" "fmov,multi")
5157 (set_attr "mode" "DF")
5158 (set_attr "fp_int_src" "true")])
5160 (define_insn "*floatdidf2_i387"
5161 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5162 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5163 "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5167 cvtsi2sd{q}\\t{%1, %0|%0, %1}"
5168 [(set_attr "type" "fmov,multi,sse")
5169 (set_attr "mode" "DF")
5170 (set_attr "fp_int_src" "true")])
5172 (define_insn "*floatdidf2_sse"
5173 [(set (match_operand:DF 0 "register_operand" "=Y")
5174 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5176 "cvtsi2sd{q}\\t{%1, %0|%0, %1}"
5177 [(set_attr "type" "sse")
5178 (set_attr "mode" "DF")
5179 (set_attr "fp_int_src" "true")])
5181 (define_insn "floathixf2"
5182 [(set (match_operand:XF 0 "register_operand" "=f,f")
5183 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5184 "TARGET_80387 && !TARGET_64BIT"
5188 [(set_attr "type" "fmov,multi")
5189 (set_attr "mode" "XF")
5190 (set_attr "fp_int_src" "true")])
5192 (define_insn "floathitf2"
5193 [(set (match_operand:TF 0 "register_operand" "=f,f")
5194 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5199 [(set_attr "type" "fmov,multi")
5200 (set_attr "mode" "XF")
5201 (set_attr "fp_int_src" "true")])
5203 (define_insn "floatsixf2"
5204 [(set (match_operand:XF 0 "register_operand" "=f,f")
5205 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5206 "TARGET_80387 && !TARGET_64BIT"
5210 [(set_attr "type" "fmov,multi")
5211 (set_attr "mode" "XF")
5212 (set_attr "fp_int_src" "true")])
5214 (define_insn "floatsitf2"
5215 [(set (match_operand:TF 0 "register_operand" "=f,f")
5216 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5221 [(set_attr "type" "fmov,multi")
5222 (set_attr "mode" "XF")
5223 (set_attr "fp_int_src" "true")])
5225 (define_insn "floatdixf2"
5226 [(set (match_operand:XF 0 "register_operand" "=f,f")
5227 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5228 "TARGET_80387 && !TARGET_64BIT"
5232 [(set_attr "type" "fmov,multi")
5233 (set_attr "mode" "XF")
5234 (set_attr "fp_int_src" "true")])
5236 (define_insn "floatditf2"
5237 [(set (match_operand:TF 0 "register_operand" "=f,f")
5238 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5243 [(set_attr "type" "fmov,multi")
5244 (set_attr "mode" "XF")
5245 (set_attr "fp_int_src" "true")])
5247 ;; %%% Kill these when reload knows how to do it.
5249 [(set (match_operand 0 "register_operand" "")
5250 (float (match_operand 1 "register_operand" "")))]
5251 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5252 && FP_REG_P (operands[0])"
5256 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5257 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5258 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5259 ix86_free_from_memory (GET_MODE (operands[1]));
5265 ;; %%% splits for addsidi3
5266 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5267 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5268 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5270 (define_expand "adddi3"
5271 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5272 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5273 (match_operand:DI 2 "x86_64_general_operand" "")))
5274 (clobber (reg:CC 17))]
5276 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5278 (define_insn "*adddi3_1"
5279 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5280 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5281 (match_operand:DI 2 "general_operand" "roiF,riF")))
5282 (clobber (reg:CC 17))]
5287 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5288 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5289 (match_operand:DI 2 "general_operand" "")))
5290 (clobber (reg:CC 17))]
5291 "reload_completed && !TARGET_64BIT"
5292 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
5293 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5294 (parallel [(set (match_dup 3)
5295 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5298 (clobber (reg:CC 17))])]
5299 "split_di (operands+0, 1, operands+0, operands+3);
5300 split_di (operands+1, 1, operands+1, operands+4);
5301 split_di (operands+2, 1, operands+2, operands+5);")
5303 (define_insn "*adddi3_carry_rex64"
5304 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5305 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
5306 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5307 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5308 (clobber (reg:CC 17))]
5309 "ix86_binary_operator_ok (PLUS, DImode, operands)"
5310 "adc{q}\\t{%2, %0|%0, %2}"
5311 [(set_attr "type" "alu")
5312 (set_attr "pent_pair" "pu")
5313 (set_attr "mode" "DI")
5314 (set_attr "ppro_uops" "few")])
5316 (define_insn "*adddi3_cc_rex64"
5317 [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5318 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
5319 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5320 (plus:DI (match_dup 1) (match_dup 2)))]
5321 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5322 "add{q}\\t{%2, %0|%0, %2}"
5323 [(set_attr "type" "alu")
5324 (set_attr "mode" "DI")])
5326 (define_insn "*addsi3_carry"
5327 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5328 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5329 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5330 (match_operand:SI 2 "general_operand" "ri,rm")))
5331 (clobber (reg:CC 17))]
5332 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5333 "adc{l}\\t{%2, %0|%0, %2}"
5334 [(set_attr "type" "alu")
5335 (set_attr "pent_pair" "pu")
5336 (set_attr "mode" "SI")
5337 (set_attr "ppro_uops" "few")])
5339 (define_insn "*addsi3_carry_zext"
5340 [(set (match_operand:DI 0 "register_operand" "=r")
5342 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5343 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5344 (match_operand:SI 2 "general_operand" "rim"))))
5345 (clobber (reg:CC 17))]
5346 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5347 "adc{l}\\t{%2, %k0|%k0, %2}"
5348 [(set_attr "type" "alu")
5349 (set_attr "pent_pair" "pu")
5350 (set_attr "mode" "SI")
5351 (set_attr "ppro_uops" "few")])
5353 (define_insn "*addsi3_cc"
5354 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5355 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
5356 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5357 (plus:SI (match_dup 1) (match_dup 2)))]
5358 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5359 "add{l}\\t{%2, %0|%0, %2}"
5360 [(set_attr "type" "alu")
5361 (set_attr "mode" "SI")])
5363 (define_insn "addqi3_cc"
5364 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5365 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
5366 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5367 (plus:QI (match_dup 1) (match_dup 2)))]
5368 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5369 "add{b}\\t{%2, %0|%0, %2}"
5370 [(set_attr "type" "alu")
5371 (set_attr "mode" "QI")])
5373 (define_expand "addsi3"
5374 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5375 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5376 (match_operand:SI 2 "general_operand" "")))
5377 (clobber (reg:CC 17))])]
5379 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5381 (define_insn "*lea_1"
5382 [(set (match_operand:SI 0 "register_operand" "=r")
5383 (match_operand:SI 1 "address_operand" "p"))]
5385 "lea{l}\\t{%a1, %0|%0, %a1}"
5386 [(set_attr "type" "lea")
5387 (set_attr "mode" "SI")])
5389 (define_insn "*lea_1_rex64"
5390 [(set (match_operand:SI 0 "register_operand" "=r")
5391 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5393 "lea{l}\\t{%a1, %0|%0, %a1}"
5394 [(set_attr "type" "lea")
5395 (set_attr "mode" "SI")])
5397 (define_insn "*lea_1_zext"
5398 [(set (match_operand:DI 0 "register_operand" "=r")
5399 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5401 "lea{l}\\t{%a1, %k0|%k0, %a1}"
5402 [(set_attr "type" "lea")
5403 (set_attr "mode" "SI")])
5405 (define_insn "*lea_2_rex64"
5406 [(set (match_operand:DI 0 "register_operand" "=r")
5407 (match_operand:DI 1 "address_operand" "p"))]
5409 "lea{q}\\t{%a1, %0|%0, %a1}"
5410 [(set_attr "type" "lea")
5411 (set_attr "mode" "DI")])
5413 ;; The lea patterns for non-Pmodes needs to be matched by several
5414 ;; insns converted to real lea by splitters.
5416 (define_insn_and_split "*lea_general_1"
5417 [(set (match_operand 0 "register_operand" "=r")
5418 (plus (plus (match_operand 1 "register_operand" "r")
5419 (match_operand 2 "register_operand" "r"))
5420 (match_operand 3 "immediate_operand" "i")))]
5421 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5422 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5423 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5424 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5425 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5426 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5427 || GET_MODE (operands[3]) == VOIDmode)"
5429 "&& reload_completed"
5434 operands[0] = gen_lowpart (SImode, operands[0]);
5435 operands[1] = gen_lowpart (Pmode, operands[1]);
5436 operands[2] = gen_lowpart (Pmode, operands[2]);
5437 operands[3] = gen_lowpart (Pmode, operands[3]);
5438 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5440 if (Pmode != SImode)
5441 pat = gen_rtx_SUBREG (SImode, pat, 0);
5442 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5445 [(set_attr "type" "lea")
5446 (set_attr "mode" "SI")])
5448 (define_insn_and_split "*lea_general_1_zext"
5449 [(set (match_operand:DI 0 "register_operand" "=r")
5451 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
5452 (match_operand:SI 2 "register_operand" "r"))
5453 (match_operand:SI 3 "immediate_operand" "i"))))]
5456 "&& reload_completed"
5458 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5460 (match_dup 3)) 0)))]
5463 operands[1] = gen_lowpart (Pmode, operands[1]);
5464 operands[2] = gen_lowpart (Pmode, operands[2]);
5465 operands[3] = gen_lowpart (Pmode, operands[3]);
5467 [(set_attr "type" "lea")
5468 (set_attr "mode" "SI")])
5470 (define_insn_and_split "*lea_general_2"
5471 [(set (match_operand 0 "register_operand" "=r")
5472 (plus (mult (match_operand 1 "register_operand" "r")
5473 (match_operand 2 "const248_operand" "i"))
5474 (match_operand 3 "nonmemory_operand" "ri")))]
5475 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5476 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5477 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5478 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5479 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5480 || GET_MODE (operands[3]) == VOIDmode)"
5482 "&& reload_completed"
5487 operands[0] = gen_lowpart (SImode, operands[0]);
5488 operands[1] = gen_lowpart (Pmode, operands[1]);
5489 operands[3] = gen_lowpart (Pmode, operands[3]);
5490 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5492 if (Pmode != SImode)
5493 pat = gen_rtx_SUBREG (SImode, pat, 0);
5494 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5497 [(set_attr "type" "lea")
5498 (set_attr "mode" "SI")])
5500 (define_insn_and_split "*lea_general_2_zext"
5501 [(set (match_operand:DI 0 "register_operand" "=r")
5503 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5504 (match_operand:SI 2 "const248_operand" "n"))
5505 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5508 "&& reload_completed"
5510 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5512 (match_dup 3)) 0)))]
5515 operands[1] = gen_lowpart (Pmode, operands[1]);
5516 operands[3] = gen_lowpart (Pmode, operands[3]);
5518 [(set_attr "type" "lea")
5519 (set_attr "mode" "SI")])
5521 (define_insn_and_split "*lea_general_3"
5522 [(set (match_operand 0 "register_operand" "=r")
5523 (plus (plus (mult (match_operand 1 "register_operand" "r")
5524 (match_operand 2 "const248_operand" "i"))
5525 (match_operand 3 "register_operand" "r"))
5526 (match_operand 4 "immediate_operand" "i")))]
5527 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5528 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5529 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5530 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5531 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5533 "&& reload_completed"
5538 operands[0] = gen_lowpart (SImode, operands[0]);
5539 operands[1] = gen_lowpart (Pmode, operands[1]);
5540 operands[3] = gen_lowpart (Pmode, operands[3]);
5541 operands[4] = gen_lowpart (Pmode, operands[4]);
5542 pat = gen_rtx_PLUS (Pmode,
5543 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5547 if (Pmode != SImode)
5548 pat = gen_rtx_SUBREG (SImode, pat, 0);
5549 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5552 [(set_attr "type" "lea")
5553 (set_attr "mode" "SI")])
5555 (define_insn_and_split "*lea_general_3_zext"
5556 [(set (match_operand:DI 0 "register_operand" "=r")
5558 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5559 (match_operand:SI 2 "const248_operand" "n"))
5560 (match_operand:SI 3 "register_operand" "r"))
5561 (match_operand:SI 4 "immediate_operand" "i"))))]
5564 "&& reload_completed"
5566 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5569 (match_dup 4)) 0)))]
5572 operands[1] = gen_lowpart (Pmode, operands[1]);
5573 operands[3] = gen_lowpart (Pmode, operands[3]);
5574 operands[4] = gen_lowpart (Pmode, operands[4]);
5576 [(set_attr "type" "lea")
5577 (set_attr "mode" "SI")])
5579 (define_insn "*adddi_1_rex64"
5580 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5581 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5582 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5583 (clobber (reg:CC 17))]
5584 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5587 switch (get_attr_type (insn))
5590 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5591 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
5594 if (! rtx_equal_p (operands[0], operands[1]))
5596 if (operands[2] == const1_rtx)
5597 return \"inc{q}\\t%0\";
5598 else if (operands[2] == constm1_rtx)
5599 return \"dec{q}\\t%0\";
5604 if (! rtx_equal_p (operands[0], operands[1]))
5607 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5608 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5609 if (GET_CODE (operands[2]) == CONST_INT
5610 /* Avoid overflows. */
5611 && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
5612 && (INTVAL (operands[2]) == 128
5613 || (INTVAL (operands[2]) < 0
5614 && INTVAL (operands[2]) != -128)))
5616 operands[2] = GEN_INT (-INTVAL (operands[2]));
5617 return \"sub{q}\\t{%2, %0|%0, %2}\";
5619 return \"add{q}\\t{%2, %0|%0, %2}\";
5623 (cond [(eq_attr "alternative" "2")
5624 (const_string "lea")
5625 ; Current assemblers are broken and do not allow @GOTOFF in
5626 ; ought but a memory context.
5627 (match_operand:DI 2 "pic_symbolic_operand" "")
5628 (const_string "lea")
5629 (match_operand:DI 2 "incdec_operand" "")
5630 (const_string "incdec")
5632 (const_string "alu")))
5633 (set_attr "mode" "DI")])
5635 ;; Convert lea to the lea pattern to avoid flags dependency.
5637 [(set (match_operand:DI 0 "register_operand" "")
5638 (plus:DI (match_operand:DI 1 "register_operand" "")
5639 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5640 (clobber (reg:CC 17))]
5641 "reload_completed && TARGET_64BIT
5642 && true_regnum (operands[0]) != true_regnum (operands[1])"
5644 (plus:DI (match_dup 1)
5648 (define_insn "*adddi_2_rex64"
5651 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5652 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5654 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5655 (plus:DI (match_dup 1) (match_dup 2)))]
5656 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5657 && ix86_binary_operator_ok (PLUS, DImode, operands)
5658 /* Current assemblers are broken and do not allow @GOTOFF in
5659 ought but a memory context. */
5660 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5663 switch (get_attr_type (insn))
5666 if (! rtx_equal_p (operands[0], operands[1]))
5668 if (operands[2] == const1_rtx)
5669 return \"inc{q}\\t%0\";
5670 else if (operands[2] == constm1_rtx)
5671 return \"dec{q}\\t%0\";
5676 if (! rtx_equal_p (operands[0], operands[1]))
5678 /* ???? We ought to handle there the 32bit case too
5679 - do we need new constrant? */
5680 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5681 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5682 if (GET_CODE (operands[2]) == CONST_INT
5683 /* Avoid overflows. */
5684 && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
5685 && (INTVAL (operands[2]) == 128
5686 || (INTVAL (operands[2]) < 0
5687 && INTVAL (operands[2]) != -128)))
5689 operands[2] = GEN_INT (-INTVAL (operands[2]));
5690 return \"sub{q}\\t{%2, %0|%0, %2}\";
5692 return \"add{q}\\t{%2, %0|%0, %2}\";
5696 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5697 (const_string "incdec")
5698 (const_string "alu")))
5699 (set_attr "mode" "DI")])
5701 (define_insn "*adddi_3_rex64"
5703 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5704 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5705 (clobber (match_scratch:DI 0 "=r"))]
5707 && ix86_match_ccmode (insn, CCZmode)
5708 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5709 /* Current assemblers are broken and do not allow @GOTOFF in
5710 ought but a memory context. */
5711 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5714 switch (get_attr_type (insn))
5717 if (! rtx_equal_p (operands[0], operands[1]))
5719 if (operands[2] == const1_rtx)
5720 return \"inc{q}\\t%0\";
5721 else if (operands[2] == constm1_rtx)
5722 return \"dec{q}\\t%0\";
5727 if (! rtx_equal_p (operands[0], operands[1]))
5729 /* ???? We ought to handle there the 32bit case too
5730 - do we need new constrant? */
5731 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5732 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5733 if (GET_CODE (operands[2]) == CONST_INT
5734 /* Avoid overflows. */
5735 && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
5736 && (INTVAL (operands[2]) == 128
5737 || (INTVAL (operands[2]) < 0
5738 && INTVAL (operands[2]) != -128)))
5740 operands[2] = GEN_INT (-INTVAL (operands[2]));
5741 return \"sub{q}\\t{%2, %0|%0, %2}\";
5743 return \"add{q}\\t{%2, %0|%0, %2}\";
5747 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5748 (const_string "incdec")
5749 (const_string "alu")))
5750 (set_attr "mode" "DI")])
5752 ; For comparisons against 1, -1 and 128, we may generate better code
5753 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5754 ; is matched then. We can't accept general immediate, because for
5755 ; case of overflows, the result is messed up.
5756 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5758 ; Also carry flag is reversed compared to cmp, so this converison is valid
5759 ; only for comparisons not depending on it.
5760 (define_insn "*adddi_4_rex64"
5762 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5763 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5764 (clobber (match_scratch:DI 0 "=rm"))]
5766 && ix86_match_ccmode (insn, CCGCmode)"
5769 switch (get_attr_type (insn))
5772 if (operands[2] == constm1_rtx)
5773 return \"inc{q}\\t%0\";
5774 else if (operands[2] == const1_rtx)
5775 return \"dec{q}\\t%0\";
5780 if (! rtx_equal_p (operands[0], operands[1]))
5782 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5783 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5784 if ((INTVAL (operands[2]) == -128
5785 || (INTVAL (operands[2]) > 0
5786 && INTVAL (operands[2]) != 128))
5787 /* Avoid overflows. */
5788 && ((INTVAL (operands[2]) & ((1 << 31) - 1))))
5789 return \"sub{q}\\t{%2, %0|%0, %2}\";
5790 operands[2] = GEN_INT (-INTVAL (operands[2]));
5791 return \"add{q}\\t{%2, %0|%0, %2}\";
5795 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5796 (const_string "incdec")
5797 (const_string "alu")))
5798 (set_attr "mode" "DI")])
5800 (define_insn "*adddi_5_rex64"
5803 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5804 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5806 (clobber (match_scratch:DI 0 "=r"))]
5808 && ix86_match_ccmode (insn, CCGOCmode)
5809 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5810 /* Current assemblers are broken and do not allow @GOTOFF in
5811 ought but a memory context. */
5812 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5815 switch (get_attr_type (insn))
5818 if (! rtx_equal_p (operands[0], operands[1]))
5820 if (operands[2] == const1_rtx)
5821 return \"inc{q}\\t%0\";
5822 else if (operands[2] == constm1_rtx)
5823 return \"dec{q}\\t%0\";
5828 if (! rtx_equal_p (operands[0], operands[1]))
5830 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5831 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5832 if (GET_CODE (operands[2]) == CONST_INT
5833 /* Avoid overflows. */
5834 && ((INTVAL (operands[2]) & ((1 << 31) - 1)))
5835 && (INTVAL (operands[2]) == 128
5836 || (INTVAL (operands[2]) < 0
5837 && INTVAL (operands[2]) != -128)))
5839 operands[2] = GEN_INT (-INTVAL (operands[2]));
5840 return \"sub{q}\\t{%2, %0|%0, %2}\";
5842 return \"add{q}\\t{%2, %0|%0, %2}\";
5846 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5847 (const_string "incdec")
5848 (const_string "alu")))
5849 (set_attr "mode" "DI")])
5852 (define_insn "*addsi_1"
5853 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5854 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5855 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5856 (clobber (reg:CC 17))]
5857 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5860 switch (get_attr_type (insn))
5863 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5864 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
5867 if (! rtx_equal_p (operands[0], operands[1]))
5869 if (operands[2] == const1_rtx)
5870 return \"inc{l}\\t%0\";
5871 else if (operands[2] == constm1_rtx)
5872 return \"dec{l}\\t%0\";
5877 if (! rtx_equal_p (operands[0], operands[1]))
5880 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5881 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5882 if (GET_CODE (operands[2]) == CONST_INT
5883 && (INTVAL (operands[2]) == 128
5884 || (INTVAL (operands[2]) < 0
5885 && INTVAL (operands[2]) != -128)))
5887 operands[2] = GEN_INT (-INTVAL (operands[2]));
5888 return \"sub{l}\\t{%2, %0|%0, %2}\";
5890 return \"add{l}\\t{%2, %0|%0, %2}\";
5894 (cond [(eq_attr "alternative" "2")
5895 (const_string "lea")
5896 ; Current assemblers are broken and do not allow @GOTOFF in
5897 ; ought but a memory context.
5898 (match_operand:SI 2 "pic_symbolic_operand" "")
5899 (const_string "lea")
5900 (match_operand:SI 2 "incdec_operand" "")
5901 (const_string "incdec")
5903 (const_string "alu")))
5904 (set_attr "mode" "SI")])
5906 ;; Convert lea to the lea pattern to avoid flags dependency.
5908 [(set (match_operand 0 "register_operand" "")
5909 (plus (match_operand 1 "register_operand" "")
5910 (match_operand 2 "nonmemory_operand" "")))
5911 (clobber (reg:CC 17))]
5913 && true_regnum (operands[0]) != true_regnum (operands[1])"
5918 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5919 may confuse gen_lowpart. */
5920 if (GET_MODE (operands[0]) != Pmode)
5922 operands[1] = gen_lowpart (Pmode, operands[1]);
5923 operands[2] = gen_lowpart (Pmode, operands[2]);
5925 operands[0] = gen_lowpart (SImode, operands[0]);
5926 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5927 if (Pmode != SImode)
5928 pat = gen_rtx_SUBREG (SImode, pat, 0);
5929 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5933 ;; It may seem that nonimmediate operand is proper one for operand 1.
5934 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5935 ;; we take care in ix86_binary_operator_ok to not allow two memory
5936 ;; operands so proper swapping will be done in reload. This allow
5937 ;; patterns constructed from addsi_1 to match.
5938 (define_insn "addsi_1_zext"
5939 [(set (match_operand:DI 0 "register_operand" "=r,r")
5941 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5942 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5943 (clobber (reg:CC 17))]
5944 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5947 switch (get_attr_type (insn))
5950 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5951 return \"lea{l}\\t{%a2, %k0|%k0, %a2}\";
5954 if (operands[2] == const1_rtx)
5955 return \"inc{l}\\t%k0\";
5956 else if (operands[2] == constm1_rtx)
5957 return \"dec{l}\\t%k0\";
5962 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5963 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5964 if (GET_CODE (operands[2]) == CONST_INT
5965 && (INTVAL (operands[2]) == 128
5966 || (INTVAL (operands[2]) < 0
5967 && INTVAL (operands[2]) != -128)))
5969 operands[2] = GEN_INT (-INTVAL (operands[2]));
5970 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5972 return \"add{l}\\t{%2, %k0|%k0, %2}\";
5976 (cond [(eq_attr "alternative" "1")
5977 (const_string "lea")
5978 ; Current assemblers are broken and do not allow @GOTOFF in
5979 ; ought but a memory context.
5980 (match_operand:SI 2 "pic_symbolic_operand" "")
5981 (const_string "lea")
5982 (match_operand:SI 2 "incdec_operand" "")
5983 (const_string "incdec")
5985 (const_string "alu")))
5986 (set_attr "mode" "SI")])
5988 ;; Convert lea to the lea pattern to avoid flags dependency.
5990 [(set (match_operand:DI 0 "register_operand" "")
5992 (plus:SI (match_operand:SI 1 "register_operand" "")
5993 (match_operand:SI 2 "nonmemory_operand" ""))))
5994 (clobber (reg:CC 17))]
5996 && true_regnum (operands[0]) != true_regnum (operands[1])"
5998 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
6001 operands[1] = gen_lowpart (Pmode, operands[1]);
6002 operands[2] = gen_lowpart (Pmode, operands[2]);
6005 (define_insn "*addsi_2"
6008 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6009 (match_operand:SI 2 "general_operand" "rmni,rni"))
6011 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
6012 (plus:SI (match_dup 1) (match_dup 2)))]
6013 "ix86_match_ccmode (insn, CCGOCmode)
6014 && ix86_binary_operator_ok (PLUS, SImode, operands)
6015 /* Current assemblers are broken and do not allow @GOTOFF in
6016 ought but a memory context. */
6017 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6020 switch (get_attr_type (insn))
6023 if (! rtx_equal_p (operands[0], operands[1]))
6025 if (operands[2] == const1_rtx)
6026 return \"inc{l}\\t%0\";
6027 else if (operands[2] == constm1_rtx)
6028 return \"dec{l}\\t%0\";
6033 if (! rtx_equal_p (operands[0], operands[1]))
6035 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6036 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6037 if (GET_CODE (operands[2]) == CONST_INT
6038 && (INTVAL (operands[2]) == 128
6039 || (INTVAL (operands[2]) < 0
6040 && INTVAL (operands[2]) != -128)))
6042 operands[2] = GEN_INT (-INTVAL (operands[2]));
6043 return \"sub{l}\\t{%2, %0|%0, %2}\";
6045 return \"add{l}\\t{%2, %0|%0, %2}\";
6049 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6050 (const_string "incdec")
6051 (const_string "alu")))
6052 (set_attr "mode" "SI")])
6054 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6055 (define_insn "*addsi_2_zext"
6058 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6059 (match_operand:SI 2 "general_operand" "rmni"))
6061 (set (match_operand:DI 0 "register_operand" "=r")
6062 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6063 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6064 && ix86_binary_operator_ok (PLUS, SImode, operands)
6065 /* Current assemblers are broken and do not allow @GOTOFF in
6066 ought but a memory context. */
6067 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6070 switch (get_attr_type (insn))
6073 if (operands[2] == const1_rtx)
6074 return \"inc{l}\\t%k0\";
6075 else if (operands[2] == constm1_rtx)
6076 return \"dec{l}\\t%k0\";
6081 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6082 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6083 if (GET_CODE (operands[2]) == CONST_INT
6084 && (INTVAL (operands[2]) == 128
6085 || (INTVAL (operands[2]) < 0
6086 && INTVAL (operands[2]) != -128)))
6088 operands[2] = GEN_INT (-INTVAL (operands[2]));
6089 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6091 return \"add{l}\\t{%2, %k0|%k0, %2}\";
6095 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6096 (const_string "incdec")
6097 (const_string "alu")))
6098 (set_attr "mode" "SI")])
6100 (define_insn "*addsi_3"
6102 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6103 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6104 (clobber (match_scratch:SI 0 "=r"))]
6105 "ix86_match_ccmode (insn, CCZmode)
6106 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6107 /* Current assemblers are broken and do not allow @GOTOFF in
6108 ought but a memory context. */
6109 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6112 switch (get_attr_type (insn))
6115 if (! rtx_equal_p (operands[0], operands[1]))
6117 if (operands[2] == const1_rtx)
6118 return \"inc{l}\\t%0\";
6119 else if (operands[2] == constm1_rtx)
6120 return \"dec{l}\\t%0\";
6125 if (! rtx_equal_p (operands[0], operands[1]))
6127 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6128 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6129 if (GET_CODE (operands[2]) == CONST_INT
6130 && (INTVAL (operands[2]) == 128
6131 || (INTVAL (operands[2]) < 0
6132 && INTVAL (operands[2]) != -128)))
6134 operands[2] = GEN_INT (-INTVAL (operands[2]));
6135 return \"sub{l}\\t{%2, %0|%0, %2}\";
6137 return \"add{l}\\t{%2, %0|%0, %2}\";
6141 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6142 (const_string "incdec")
6143 (const_string "alu")))
6144 (set_attr "mode" "SI")])
6146 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6147 (define_insn "*addsi_3_zext"
6149 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6150 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6151 (set (match_operand:DI 0 "register_operand" "=r")
6152 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6153 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6154 && ix86_binary_operator_ok (PLUS, SImode, operands)
6155 /* Current assemblers are broken and do not allow @GOTOFF in
6156 ought but a memory context. */
6157 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6160 switch (get_attr_type (insn))
6163 if (operands[2] == const1_rtx)
6164 return \"inc{l}\\t%k0\";
6165 else if (operands[2] == constm1_rtx)
6166 return \"dec{l}\\t%k0\";
6171 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6172 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6173 if (GET_CODE (operands[2]) == CONST_INT
6174 && (INTVAL (operands[2]) == 128
6175 || (INTVAL (operands[2]) < 0
6176 && INTVAL (operands[2]) != -128)))
6178 operands[2] = GEN_INT (-INTVAL (operands[2]));
6179 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6181 return \"add{l}\\t{%2, %k0|%k0, %2}\";
6185 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6186 (const_string "incdec")
6187 (const_string "alu")))
6188 (set_attr "mode" "SI")])
6190 ; For comparisons agains 1, -1 and 128, we may generate better code
6191 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6192 ; is matched then. We can't accept general immediate, because for
6193 ; case of overflows, the result is messed up.
6194 ; This pattern also don't hold of 0x80000000, since the value overflows
6196 ; Also carry flag is reversed compared to cmp, so this converison is valid
6197 ; only for comparisons not depending on it.
6198 (define_insn "*addsi_4"
6200 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6201 (match_operand:SI 2 "const_int_operand" "n")))
6202 (clobber (match_scratch:SI 0 "=rm"))]
6203 "ix86_match_ccmode (insn, CCGCmode)
6204 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6207 switch (get_attr_type (insn))
6210 if (operands[2] == constm1_rtx)
6211 return \"inc{l}\\t%0\";
6212 else if (operands[2] == const1_rtx)
6213 return \"dec{l}\\t%0\";
6218 if (! rtx_equal_p (operands[0], operands[1]))
6220 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6221 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6222 if ((INTVAL (operands[2]) == -128
6223 || (INTVAL (operands[2]) > 0
6224 && INTVAL (operands[2]) != 128)))
6225 return \"sub{l}\\t{%2, %0|%0, %2}\";
6226 operands[2] = GEN_INT (-INTVAL (operands[2]));
6227 return \"add{l}\\t{%2, %0|%0, %2}\";
6231 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6232 (const_string "incdec")
6233 (const_string "alu")))
6234 (set_attr "mode" "SI")])
6236 (define_insn "*addsi_5"
6239 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6240 (match_operand:SI 2 "general_operand" "rmni"))
6242 (clobber (match_scratch:SI 0 "=r"))]
6243 "ix86_match_ccmode (insn, CCGOCmode)
6244 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6245 /* Current assemblers are broken and do not allow @GOTOFF in
6246 ought but a memory context. */
6247 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6250 switch (get_attr_type (insn))
6253 if (! rtx_equal_p (operands[0], operands[1]))
6255 if (operands[2] == const1_rtx)
6256 return \"inc{l}\\t%0\";
6257 else if (operands[2] == constm1_rtx)
6258 return \"dec{l}\\t%0\";
6263 if (! rtx_equal_p (operands[0], operands[1]))
6265 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6266 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6267 if (GET_CODE (operands[2]) == CONST_INT
6268 && (INTVAL (operands[2]) == 128
6269 || (INTVAL (operands[2]) < 0
6270 && INTVAL (operands[2]) != -128)))
6272 operands[2] = GEN_INT (-INTVAL (operands[2]));
6273 return \"sub{l}\\t{%2, %0|%0, %2}\";
6275 return \"add{l}\\t{%2, %0|%0, %2}\";
6279 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6280 (const_string "incdec")
6281 (const_string "alu")))
6282 (set_attr "mode" "SI")])
6284 (define_expand "addhi3"
6285 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6286 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6287 (match_operand:HI 2 "general_operand" "")))
6288 (clobber (reg:CC 17))])]
6289 "TARGET_HIMODE_MATH"
6290 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6292 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6293 ;; type optimizations enabled by define-splits. This is not important
6294 ;; for PII, and in fact harmful because of partial register stalls.
6296 (define_insn "*addhi_1_lea"
6297 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6298 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6299 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6300 (clobber (reg:CC 17))]
6301 "!TARGET_PARTIAL_REG_STALL
6302 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6305 switch (get_attr_type (insn))
6310 if (operands[2] == const1_rtx)
6311 return \"inc{w}\\t%0\";
6312 else if (operands[2] == constm1_rtx
6313 || (GET_CODE (operands[2]) == CONST_INT
6314 && INTVAL (operands[2]) == 65535))
6315 return \"dec{w}\\t%0\";
6319 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6320 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6321 if (GET_CODE (operands[2]) == CONST_INT
6322 && (INTVAL (operands[2]) == 128
6323 || (INTVAL (operands[2]) < 0
6324 && INTVAL (operands[2]) != -128)))
6326 operands[2] = GEN_INT (-INTVAL (operands[2]));
6327 return \"sub{w}\\t{%2, %0|%0, %2}\";
6329 return \"add{w}\\t{%2, %0|%0, %2}\";
6333 (if_then_else (eq_attr "alternative" "2")
6334 (const_string "lea")
6335 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6336 (const_string "incdec")
6337 (const_string "alu"))))
6338 (set_attr "mode" "HI,HI,SI")])
6340 (define_insn "*addhi_1"
6341 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6342 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6343 (match_operand:HI 2 "general_operand" "ri,rm")))
6344 (clobber (reg:CC 17))]
6345 "TARGET_PARTIAL_REG_STALL
6346 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6349 switch (get_attr_type (insn))
6352 if (operands[2] == const1_rtx)
6353 return \"inc{w}\\t%0\";
6354 else if (operands[2] == constm1_rtx
6355 || (GET_CODE (operands[2]) == CONST_INT
6356 && INTVAL (operands[2]) == 65535))
6357 return \"dec{w}\\t%0\";
6361 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6362 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6363 if (GET_CODE (operands[2]) == CONST_INT
6364 && (INTVAL (operands[2]) == 128
6365 || (INTVAL (operands[2]) < 0
6366 && INTVAL (operands[2]) != -128)))
6368 operands[2] = GEN_INT (-INTVAL (operands[2]));
6369 return \"sub{w}\\t{%2, %0|%0, %2}\";
6371 return \"add{w}\\t{%2, %0|%0, %2}\";
6375 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6376 (const_string "incdec")
6377 (const_string "alu")))
6378 (set_attr "mode" "HI")])
6380 (define_insn "*addhi_2"
6383 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6384 (match_operand:HI 2 "general_operand" "rmni,rni"))
6386 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6387 (plus:HI (match_dup 1) (match_dup 2)))]
6388 "ix86_match_ccmode (insn, CCGOCmode)
6389 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6392 switch (get_attr_type (insn))
6395 if (operands[2] == const1_rtx)
6396 return \"inc{w}\\t%0\";
6397 else if (operands[2] == constm1_rtx
6398 || (GET_CODE (operands[2]) == CONST_INT
6399 && INTVAL (operands[2]) == 65535))
6400 return \"dec{w}\\t%0\";
6404 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6405 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6406 if (GET_CODE (operands[2]) == CONST_INT
6407 && (INTVAL (operands[2]) == 128
6408 || (INTVAL (operands[2]) < 0
6409 && INTVAL (operands[2]) != -128)))
6411 operands[2] = GEN_INT (-INTVAL (operands[2]));
6412 return \"sub{w}\\t{%2, %0|%0, %2}\";
6414 return \"add{w}\\t{%2, %0|%0, %2}\";
6418 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6419 (const_string "incdec")
6420 (const_string "alu")))
6421 (set_attr "mode" "HI")])
6423 (define_insn "*addhi_3"
6425 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6426 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6427 (clobber (match_scratch:HI 0 "=r"))]
6428 "ix86_match_ccmode (insn, CCZmode)
6429 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6432 switch (get_attr_type (insn))
6435 if (operands[2] == const1_rtx)
6436 return \"inc{w}\\t%0\";
6437 else if (operands[2] == constm1_rtx
6438 || (GET_CODE (operands[2]) == CONST_INT
6439 && INTVAL (operands[2]) == 65535))
6440 return \"dec{w}\\t%0\";
6444 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6445 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6446 if (GET_CODE (operands[2]) == CONST_INT
6447 && (INTVAL (operands[2]) == 128
6448 || (INTVAL (operands[2]) < 0
6449 && INTVAL (operands[2]) != -128)))
6451 operands[2] = GEN_INT (-INTVAL (operands[2]));
6452 return \"sub{w}\\t{%2, %0|%0, %2}\";
6454 return \"add{w}\\t{%2, %0|%0, %2}\";
6458 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6459 (const_string "incdec")
6460 (const_string "alu")))
6461 (set_attr "mode" "HI")])
6463 ; See comments above addsi_3_imm for details.
6464 (define_insn "*addhi_4"
6466 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6467 (match_operand:HI 2 "const_int_operand" "n")))
6468 (clobber (match_scratch:HI 0 "=rm"))]
6469 "ix86_match_ccmode (insn, CCGCmode)
6470 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6473 switch (get_attr_type (insn))
6476 if (operands[2] == constm1_rtx
6477 || (GET_CODE (operands[2]) == CONST_INT
6478 && INTVAL (operands[2]) == 65535))
6479 return \"inc{w}\\t%0\";
6480 else if (operands[2] == const1_rtx)
6481 return \"dec{w}\\t%0\";
6486 if (! rtx_equal_p (operands[0], operands[1]))
6488 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6489 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6490 if ((INTVAL (operands[2]) == -128
6491 || (INTVAL (operands[2]) > 0
6492 && INTVAL (operands[2]) != 128)))
6493 return \"sub{w}\\t{%2, %0|%0, %2}\";
6494 operands[2] = GEN_INT (-INTVAL (operands[2]));
6495 return \"add{w}\\t{%2, %0|%0, %2}\";
6499 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6500 (const_string "incdec")
6501 (const_string "alu")))
6502 (set_attr "mode" "SI")])
6505 (define_insn "*addhi_5"
6508 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6509 (match_operand:HI 2 "general_operand" "rmni"))
6511 (clobber (match_scratch:HI 0 "=r"))]
6512 "ix86_match_ccmode (insn, CCGOCmode)
6513 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6516 switch (get_attr_type (insn))
6519 if (operands[2] == const1_rtx)
6520 return \"inc{w}\\t%0\";
6521 else if (operands[2] == constm1_rtx
6522 || (GET_CODE (operands[2]) == CONST_INT
6523 && INTVAL (operands[2]) == 65535))
6524 return \"dec{w}\\t%0\";
6528 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6529 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6530 if (GET_CODE (operands[2]) == CONST_INT
6531 && (INTVAL (operands[2]) == 128
6532 || (INTVAL (operands[2]) < 0
6533 && INTVAL (operands[2]) != -128)))
6535 operands[2] = GEN_INT (-INTVAL (operands[2]));
6536 return \"sub{w}\\t{%2, %0|%0, %2}\";
6538 return \"add{w}\\t{%2, %0|%0, %2}\";
6542 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6543 (const_string "incdec")
6544 (const_string "alu")))
6545 (set_attr "mode" "HI")])
6547 (define_expand "addqi3"
6548 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6549 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6550 (match_operand:QI 2 "general_operand" "")))
6551 (clobber (reg:CC 17))])]
6552 "TARGET_QIMODE_MATH"
6553 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6555 ;; %%% Potential partial reg stall on alternative 2. What to do?
6556 (define_insn "*addqi_1_lea"
6557 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6558 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6559 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6560 (clobber (reg:CC 17))]
6561 "!TARGET_PARTIAL_REG_STALL
6562 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6565 int widen = (which_alternative == 2);
6566 switch (get_attr_type (insn))
6571 if (operands[2] == const1_rtx)
6572 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6573 else if (operands[2] == constm1_rtx
6574 || (GET_CODE (operands[2]) == CONST_INT
6575 && INTVAL (operands[2]) == 255))
6576 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6580 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6581 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6582 if (GET_CODE (operands[2]) == CONST_INT
6583 && (INTVAL (operands[2]) == 128
6584 || (INTVAL (operands[2]) < 0
6585 && INTVAL (operands[2]) != -128)))
6587 operands[2] = GEN_INT (-INTVAL (operands[2]));
6589 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6591 return \"sub{b}\\t{%2, %0|%0, %2}\";
6594 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6596 return \"add{b}\\t{%2, %0|%0, %2}\";
6600 (if_then_else (eq_attr "alternative" "3")
6601 (const_string "lea")
6602 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6603 (const_string "incdec")
6604 (const_string "alu"))))
6605 (set_attr "mode" "QI,QI,SI,SI")])
6607 (define_insn "*addqi_1"
6608 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6609 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6610 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6611 (clobber (reg:CC 17))]
6612 "TARGET_PARTIAL_REG_STALL
6613 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6616 int widen = (which_alternative == 2);
6617 switch (get_attr_type (insn))
6620 if (operands[2] == const1_rtx)
6621 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6622 else if (operands[2] == constm1_rtx
6623 || (GET_CODE (operands[2]) == CONST_INT
6624 && INTVAL (operands[2]) == 255))
6625 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6629 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6630 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6631 if (GET_CODE (operands[2]) == CONST_INT
6632 && (INTVAL (operands[2]) == 128
6633 || (INTVAL (operands[2]) < 0
6634 && INTVAL (operands[2]) != -128)))
6636 operands[2] = GEN_INT (-INTVAL (operands[2]));
6638 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6640 return \"sub{b}\\t{%2, %0|%0, %2}\";
6643 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6645 return \"add{b}\\t{%2, %0|%0, %2}\";
6649 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6650 (const_string "incdec")
6651 (const_string "alu")))
6652 (set_attr "mode" "QI,QI,SI")])
6654 (define_insn "*addqi_2"
6657 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6658 (match_operand:QI 2 "general_operand" "qmni,qni"))
6660 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6661 (plus:QI (match_dup 1) (match_dup 2)))]
6662 "ix86_match_ccmode (insn, CCGOCmode)
6663 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6666 switch (get_attr_type (insn))
6669 if (operands[2] == const1_rtx)
6670 return \"inc{b}\\t%0\";
6671 else if (operands[2] == constm1_rtx
6672 || (GET_CODE (operands[2]) == CONST_INT
6673 && INTVAL (operands[2]) == 255))
6674 return \"dec{b}\\t%0\";
6678 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6679 if (GET_CODE (operands[2]) == CONST_INT
6680 && INTVAL (operands[2]) < 0)
6682 operands[2] = GEN_INT (-INTVAL (operands[2]));
6683 return \"sub{b}\\t{%2, %0|%0, %2}\";
6685 return \"add{b}\\t{%2, %0|%0, %2}\";
6689 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6690 (const_string "incdec")
6691 (const_string "alu")))
6692 (set_attr "mode" "QI")])
6694 (define_insn "*addqi_3"
6696 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6697 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6698 (clobber (match_scratch:QI 0 "=q"))]
6699 "ix86_match_ccmode (insn, CCZmode)
6700 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6703 switch (get_attr_type (insn))
6706 if (operands[2] == const1_rtx)
6707 return \"inc{b}\\t%0\";
6708 else if (operands[2] == constm1_rtx
6709 || (GET_CODE (operands[2]) == CONST_INT
6710 && INTVAL (operands[2]) == 255))
6711 return \"dec{b}\\t%0\";
6715 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6716 if (GET_CODE (operands[2]) == CONST_INT
6717 && INTVAL (operands[2]) < 0)
6719 operands[2] = GEN_INT (-INTVAL (operands[2]));
6720 return \"sub{b}\\t{%2, %0|%0, %2}\";
6722 return \"add{b}\\t{%2, %0|%0, %2}\";
6726 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6727 (const_string "incdec")
6728 (const_string "alu")))
6729 (set_attr "mode" "QI")])
6731 ; See comments above addsi_3_imm for details.
6732 (define_insn "*addqi_4"
6734 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6735 (match_operand:QI 2 "const_int_operand" "n")))
6736 (clobber (match_scratch:QI 0 "=qm"))]
6737 "ix86_match_ccmode (insn, CCGCmode)
6738 && (INTVAL (operands[2]) & 0xff) != 0x80"
6741 switch (get_attr_type (insn))
6744 if (operands[2] == constm1_rtx
6745 || (GET_CODE (operands[2]) == CONST_INT
6746 && INTVAL (operands[2]) == 255))
6747 return \"inc{b}\\t%0\";
6748 else if (operands[2] == const1_rtx)
6749 return \"dec{b}\\t%0\";
6754 if (! rtx_equal_p (operands[0], operands[1]))
6756 if (INTVAL (operands[2]) < 0)
6758 operands[2] = GEN_INT (-INTVAL (operands[2]));
6759 return \"add{b}\\t{%2, %0|%0, %2}\";
6761 return \"sub{b}\\t{%2, %0|%0, %2}\";
6765 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6766 (const_string "incdec")
6767 (const_string "alu")))
6768 (set_attr "mode" "QI")])
6771 (define_insn "*addqi_5"
6774 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6775 (match_operand:QI 2 "general_operand" "qmni"))
6777 (clobber (match_scratch:QI 0 "=q"))]
6778 "ix86_match_ccmode (insn, CCGOCmode)
6779 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6782 switch (get_attr_type (insn))
6785 if (operands[2] == const1_rtx)
6786 return \"inc{b}\\t%0\";
6787 else if (operands[2] == constm1_rtx
6788 || (GET_CODE (operands[2]) == CONST_INT
6789 && INTVAL (operands[2]) == 255))
6790 return \"dec{b}\\t%0\";
6794 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6795 if (GET_CODE (operands[2]) == CONST_INT
6796 && INTVAL (operands[2]) < 0)
6798 operands[2] = GEN_INT (-INTVAL (operands[2]));
6799 return \"sub{b}\\t{%2, %0|%0, %2}\";
6801 return \"add{b}\\t{%2, %0|%0, %2}\";
6805 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6806 (const_string "incdec")
6807 (const_string "alu")))
6808 (set_attr "mode" "QI")])
6811 (define_insn "addqi_ext_1"
6812 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6817 (match_operand 1 "ext_register_operand" "0")
6820 (match_operand:QI 2 "general_operand" "Qmn")))
6821 (clobber (reg:CC 17))]
6825 switch (get_attr_type (insn))
6828 if (operands[2] == const1_rtx)
6829 return \"inc{b}\\t%h0\";
6830 else if (operands[2] == constm1_rtx
6831 || (GET_CODE (operands[2]) == CONST_INT
6832 && INTVAL (operands[2]) == 255))
6833 return \"dec{b}\\t%h0\";
6837 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6841 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6842 (const_string "incdec")
6843 (const_string "alu")))
6844 (set_attr "mode" "QI")])
6846 (define_insn "*addqi_ext_1_rex64"
6847 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6852 (match_operand 1 "ext_register_operand" "0")
6855 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6856 (clobber (reg:CC 17))]
6860 switch (get_attr_type (insn))
6863 if (operands[2] == const1_rtx)
6864 return \"inc{b}\\t%h0\";
6865 else if (operands[2] == constm1_rtx
6866 || (GET_CODE (operands[2]) == CONST_INT
6867 && INTVAL (operands[2]) == 255))
6868 return \"dec{b}\\t%h0\";
6872 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6876 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6877 (const_string "incdec")
6878 (const_string "alu")))
6879 (set_attr "mode" "QI")])
6881 (define_insn "*addqi_ext_2"
6882 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6887 (match_operand 1 "ext_register_operand" "%0")
6891 (match_operand 2 "ext_register_operand" "Q")
6894 (clobber (reg:CC 17))]
6896 "add{b}\\t{%h2, %h0|%h0, %h2}"
6897 [(set_attr "type" "alu")
6898 (set_attr "mode" "QI")])
6900 ;; The patterns that match these are at the end of this file.
6902 (define_expand "addxf3"
6903 [(set (match_operand:XF 0 "register_operand" "")
6904 (plus:XF (match_operand:XF 1 "register_operand" "")
6905 (match_operand:XF 2 "register_operand" "")))]
6906 "TARGET_80387 && !TARGET_64BIT"
6909 (define_expand "addtf3"
6910 [(set (match_operand:TF 0 "register_operand" "")
6911 (plus:TF (match_operand:TF 1 "register_operand" "")
6912 (match_operand:TF 2 "register_operand" "")))]
6916 (define_expand "adddf3"
6917 [(set (match_operand:DF 0 "register_operand" "")
6918 (plus:DF (match_operand:DF 1 "register_operand" "")
6919 (match_operand:DF 2 "nonimmediate_operand" "")))]
6920 "TARGET_80387 || TARGET_SSE2"
6923 (define_expand "addsf3"
6924 [(set (match_operand:SF 0 "register_operand" "")
6925 (plus:SF (match_operand:SF 1 "register_operand" "")
6926 (match_operand:SF 2 "nonimmediate_operand" "")))]
6927 "TARGET_80387 || TARGET_SSE"
6930 ;; Subtract instructions
6932 ;; %%% splits for subsidi3
6934 (define_expand "subdi3"
6935 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6936 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6937 (match_operand:DI 2 "x86_64_general_operand" "")))
6938 (clobber (reg:CC 17))])]
6940 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6942 (define_insn "*subdi3_1"
6943 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6944 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6945 (match_operand:DI 2 "general_operand" "roiF,riF")))
6946 (clobber (reg:CC 17))]
6951 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6952 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6953 (match_operand:DI 2 "general_operand" "")))
6954 (clobber (reg:CC 17))]
6955 "reload_completed && !TARGET_64BIT"
6956 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6957 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6958 (parallel [(set (match_dup 3)
6959 (minus:SI (match_dup 4)
6960 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6962 (clobber (reg:CC 17))])]
6963 "split_di (operands+0, 1, operands+0, operands+3);
6964 split_di (operands+1, 1, operands+1, operands+4);
6965 split_di (operands+2, 1, operands+2, operands+5);")
6967 (define_insn "subdi3_carry_rex64"
6968 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6969 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6970 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6971 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6972 (clobber (reg:CC 17))]
6973 "ix86_binary_operator_ok (MINUS, DImode, operands)"
6974 "sbb{q}\\t{%2, %0|%0, %2}"
6975 [(set_attr "type" "alu")
6976 (set_attr "pent_pair" "pu")
6977 (set_attr "ppro_uops" "few")
6978 (set_attr "mode" "DI")])
6980 (define_insn "*subdi_1_rex64"
6981 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6982 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6983 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6984 (clobber (reg:CC 17))]
6985 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6986 "sub{q}\\t{%2, %0|%0, %2}"
6987 [(set_attr "type" "alu")
6988 (set_attr "mode" "DI")])
6990 (define_insn "*subdi_2_rex64"
6993 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6994 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6996 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6997 (minus:DI (match_dup 1) (match_dup 2)))]
6998 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6999 && ix86_binary_operator_ok (MINUS, DImode, operands)"
7000 "sub{q}\\t{%2, %0|%0, %2}"
7001 [(set_attr "type" "alu")
7002 (set_attr "mode" "DI")])
7004 (define_insn "*subdi_3_rex63"
7006 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
7007 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
7008 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
7009 (minus:DI (match_dup 1) (match_dup 2)))]
7010 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7011 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7012 "sub{q}\\t{%2, %0|%0, %2}"
7013 [(set_attr "type" "alu")
7014 (set_attr "mode" "DI")])
7017 (define_insn "subsi3_carry"
7018 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7019 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7020 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
7021 (match_operand:SI 2 "general_operand" "ri,rm"))))
7022 (clobber (reg:CC 17))]
7023 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7024 "sbb{l}\\t{%2, %0|%0, %2}"
7025 [(set_attr "type" "alu")
7026 (set_attr "pent_pair" "pu")
7027 (set_attr "ppro_uops" "few")
7028 (set_attr "mode" "SI")])
7030 (define_insn "subsi3_carry_zext"
7031 [(set (match_operand:DI 0 "register_operand" "=rm,r")
7033 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
7034 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
7035 (match_operand:SI 2 "general_operand" "ri,rm")))))
7036 (clobber (reg:CC 17))]
7037 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7038 "sbb{l}\\t{%2, %k0|%k0, %2}"
7039 [(set_attr "type" "alu")
7040 (set_attr "pent_pair" "pu")
7041 (set_attr "ppro_uops" "few")
7042 (set_attr "mode" "SI")])
7044 (define_expand "subsi3"
7045 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7046 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
7047 (match_operand:SI 2 "general_operand" "")))
7048 (clobber (reg:CC 17))])]
7050 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
7052 (define_insn "*subsi_1"
7053 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7054 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7055 (match_operand:SI 2 "general_operand" "ri,rm")))
7056 (clobber (reg:CC 17))]
7057 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7058 "sub{l}\\t{%2, %0|%0, %2}"
7059 [(set_attr "type" "alu")
7060 (set_attr "mode" "SI")])
7062 (define_insn "*subsi_1_zext"
7063 [(set (match_operand:DI 0 "register_operand" "=r")
7065 (minus:SI (match_operand:SI 1 "register_operand" "0")
7066 (match_operand:SI 2 "general_operand" "rim"))))
7067 (clobber (reg:CC 17))]
7068 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7069 "sub{l}\\t{%2, %k0|%k0, %2}"
7070 [(set_attr "type" "alu")
7071 (set_attr "mode" "SI")])
7073 (define_insn "*subsi_2"
7076 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7077 (match_operand:SI 2 "general_operand" "ri,rm"))
7079 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7080 (minus:SI (match_dup 1) (match_dup 2)))]
7081 "ix86_match_ccmode (insn, CCGOCmode)
7082 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7083 "sub{l}\\t{%2, %0|%0, %2}"
7084 [(set_attr "type" "alu")
7085 (set_attr "mode" "SI")])
7087 (define_insn "*subsi_2_zext"
7090 (minus:SI (match_operand:SI 1 "register_operand" "0")
7091 (match_operand:SI 2 "general_operand" "rim"))
7093 (set (match_operand:DI 0 "register_operand" "=r")
7095 (minus:SI (match_dup 1)
7097 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7098 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7099 "sub{l}\\t{%2, %k0|%k0, %2}"
7100 [(set_attr "type" "alu")
7101 (set_attr "mode" "SI")])
7103 (define_insn "*subsi_3"
7105 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7106 (match_operand:SI 2 "general_operand" "ri,rm")))
7107 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7108 (minus:SI (match_dup 1) (match_dup 2)))]
7109 "ix86_match_ccmode (insn, CCmode)
7110 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7111 "sub{l}\\t{%2, %0|%0, %2}"
7112 [(set_attr "type" "alu")
7113 (set_attr "mode" "SI")])
7115 (define_insn "*subsi_3_zext"
7117 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7118 (match_operand:SI 2 "general_operand" "rim")))
7119 (set (match_operand:DI 0 "register_operand" "=r")
7121 (minus:SI (match_dup 1)
7123 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7124 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7125 "sub{q}\\t{%2, %0|%0, %2}"
7126 [(set_attr "type" "alu")
7127 (set_attr "mode" "DI")])
7129 (define_expand "subhi3"
7130 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7131 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7132 (match_operand:HI 2 "general_operand" "")))
7133 (clobber (reg:CC 17))])]
7134 "TARGET_HIMODE_MATH"
7135 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7137 (define_insn "*subhi_1"
7138 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7139 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7140 (match_operand:HI 2 "general_operand" "ri,rm")))
7141 (clobber (reg:CC 17))]
7142 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7143 "sub{w}\\t{%2, %0|%0, %2}"
7144 [(set_attr "type" "alu")
7145 (set_attr "mode" "HI")])
7147 (define_insn "*subhi_2"
7150 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7151 (match_operand:HI 2 "general_operand" "ri,rm"))
7153 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7154 (minus:HI (match_dup 1) (match_dup 2)))]
7155 "ix86_match_ccmode (insn, CCGOCmode)
7156 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7157 "sub{w}\\t{%2, %0|%0, %2}"
7158 [(set_attr "type" "alu")
7159 (set_attr "mode" "HI")])
7161 (define_insn "*subhi_3"
7163 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7164 (match_operand:HI 2 "general_operand" "ri,rm")))
7165 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7166 (minus:HI (match_dup 1) (match_dup 2)))]
7167 "ix86_match_ccmode (insn, CCmode)
7168 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7169 "sub{w}\\t{%2, %0|%0, %2}"
7170 [(set_attr "type" "alu")
7171 (set_attr "mode" "HI")])
7173 (define_expand "subqi3"
7174 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7175 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7176 (match_operand:QI 2 "general_operand" "")))
7177 (clobber (reg:CC 17))])]
7178 "TARGET_QIMODE_MATH"
7179 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7181 (define_insn "*subqi_1"
7182 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7183 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7184 (match_operand:QI 2 "general_operand" "qn,qmn")))
7185 (clobber (reg:CC 17))]
7186 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7187 "sub{b}\\t{%2, %0|%0, %2}"
7188 [(set_attr "type" "alu")
7189 (set_attr "mode" "QI")])
7191 (define_insn "*subqi_2"
7194 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7195 (match_operand:QI 2 "general_operand" "qi,qm"))
7197 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7198 (minus:HI (match_dup 1) (match_dup 2)))]
7199 "ix86_match_ccmode (insn, CCGOCmode)
7200 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7201 "sub{b}\\t{%2, %0|%0, %2}"
7202 [(set_attr "type" "alu")
7203 (set_attr "mode" "QI")])
7205 (define_insn "*subqi_3"
7207 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7208 (match_operand:QI 2 "general_operand" "qi,qm")))
7209 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7210 (minus:HI (match_dup 1) (match_dup 2)))]
7211 "ix86_match_ccmode (insn, CCmode)
7212 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7213 "sub{b}\\t{%2, %0|%0, %2}"
7214 [(set_attr "type" "alu")
7215 (set_attr "mode" "QI")])
7217 ;; The patterns that match these are at the end of this file.
7219 (define_expand "subxf3"
7220 [(set (match_operand:XF 0 "register_operand" "")
7221 (minus:XF (match_operand:XF 1 "register_operand" "")
7222 (match_operand:XF 2 "register_operand" "")))]
7223 "TARGET_80387 && !TARGET_64BIT"
7226 (define_expand "subtf3"
7227 [(set (match_operand:TF 0 "register_operand" "")
7228 (minus:TF (match_operand:TF 1 "register_operand" "")
7229 (match_operand:TF 2 "register_operand" "")))]
7233 (define_expand "subdf3"
7234 [(set (match_operand:DF 0 "register_operand" "")
7235 (minus:DF (match_operand:DF 1 "register_operand" "")
7236 (match_operand:DF 2 "nonimmediate_operand" "")))]
7237 "TARGET_80387 || TARGET_SSE2"
7240 (define_expand "subsf3"
7241 [(set (match_operand:SF 0 "register_operand" "")
7242 (minus:SF (match_operand:SF 1 "register_operand" "")
7243 (match_operand:SF 2 "nonimmediate_operand" "")))]
7244 "TARGET_80387 || TARGET_SSE"
7247 ;; Multiply instructions
7249 (define_expand "muldi3"
7250 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7251 (mult:DI (match_operand:DI 1 "register_operand" "")
7252 (match_operand:DI 2 "x86_64_general_operand" "")))
7253 (clobber (reg:CC 17))])]
7257 (define_insn "*muldi3_1_rex64"
7258 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7259 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
7260 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7261 (clobber (reg:CC 17))]
7262 "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
7265 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7266 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7267 imul{q}\\t{%2, %0|%0, %2}"
7268 [(set_attr "type" "imul")
7269 (set_attr "prefix_0f" "0,0,1")
7270 (set_attr "mode" "DI")])
7272 (define_expand "mulsi3"
7273 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7274 (mult:SI (match_operand:SI 1 "register_operand" "")
7275 (match_operand:SI 2 "general_operand" "")))
7276 (clobber (reg:CC 17))])]
7280 (define_insn "*mulsi3_1"
7281 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7282 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7283 (match_operand:SI 2 "general_operand" "K,i,mr")))
7284 (clobber (reg:CC 17))]
7285 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7286 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7287 ; there are two ways of writing the exact same machine instruction
7288 ; in assembly language. One, for example, is:
7292 ; while the other is:
7294 ; imul $12, %eax, %eax
7296 ; The first is simply short-hand for the latter. But, some assemblers,
7297 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7299 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7300 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7301 imul{l}\\t{%2, %0|%0, %2}"
7302 [(set_attr "type" "imul")
7303 (set_attr "prefix_0f" "0,0,1")
7304 (set_attr "mode" "SI")])
7306 (define_insn "*mulsi3_1_zext"
7307 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7309 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7310 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7311 (clobber (reg:CC 17))]
7313 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7314 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7315 ; there are two ways of writing the exact same machine instruction
7316 ; in assembly language. One, for example, is:
7320 ; while the other is:
7322 ; imul $12, %eax, %eax
7324 ; The first is simply short-hand for the latter. But, some assemblers,
7325 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7327 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7328 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7329 imul{l}\\t{%2, %k0|%k0, %2}"
7330 [(set_attr "type" "imul")
7331 (set_attr "prefix_0f" "0,0,1")
7332 (set_attr "mode" "SI")])
7334 (define_expand "mulhi3"
7335 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7336 (mult:HI (match_operand:HI 1 "register_operand" "")
7337 (match_operand:HI 2 "general_operand" "")))
7338 (clobber (reg:CC 17))])]
7339 "TARGET_HIMODE_MATH"
7342 (define_insn "*mulhi3_1"
7343 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7344 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
7345 (match_operand:HI 2 "general_operand" "K,i,mr")))
7346 (clobber (reg:CC 17))]
7347 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7348 ; %%% There was a note about "Assembler has weird restrictions",
7349 ; concerning alternative 1 when op1 == op0. True?
7351 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7352 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7353 imul{w}\\t{%2, %0|%0, %2}"
7354 [(set_attr "type" "imul")
7355 (set_attr "prefix_0f" "0,0,1")
7356 (set_attr "mode" "HI")])
7358 (define_insn "mulqi3"
7359 [(set (match_operand:QI 0 "register_operand" "=a")
7360 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7361 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7362 (clobber (reg:CC 17))]
7363 "TARGET_QIMODE_MATH"
7365 [(set_attr "type" "imul")
7366 (set_attr "length_immediate" "0")
7367 (set_attr "mode" "QI")])
7369 (define_insn "umulqihi3"
7370 [(set (match_operand:HI 0 "register_operand" "=a")
7371 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7372 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7373 (clobber (reg:CC 17))]
7374 "TARGET_QIMODE_MATH"
7376 [(set_attr "type" "imul")
7377 (set_attr "length_immediate" "0")
7378 (set_attr "mode" "QI")])
7380 (define_insn "mulqihi3"
7381 [(set (match_operand:HI 0 "register_operand" "=a")
7382 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7383 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7384 (clobber (reg:CC 17))]
7385 "TARGET_QIMODE_MATH"
7387 [(set_attr "type" "imul")
7388 (set_attr "length_immediate" "0")
7389 (set_attr "mode" "QI")])
7391 (define_insn "umulditi3"
7392 [(set (match_operand:TI 0 "register_operand" "=A")
7393 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7394 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7395 (clobber (reg:CC 17))]
7398 [(set_attr "type" "imul")
7399 (set_attr "ppro_uops" "few")
7400 (set_attr "length_immediate" "0")
7401 (set_attr "mode" "DI")])
7403 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7404 (define_insn "umulsidi3"
7405 [(set (match_operand:DI 0 "register_operand" "=A")
7406 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7407 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7408 (clobber (reg:CC 17))]
7411 [(set_attr "type" "imul")
7412 (set_attr "ppro_uops" "few")
7413 (set_attr "length_immediate" "0")
7414 (set_attr "mode" "SI")])
7416 (define_insn "mulditi3"
7417 [(set (match_operand:TI 0 "register_operand" "=A")
7418 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7419 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7420 (clobber (reg:CC 17))]
7423 [(set_attr "type" "imul")
7424 (set_attr "length_immediate" "0")
7425 (set_attr "mode" "DI")])
7427 (define_insn "mulsidi3"
7428 [(set (match_operand:DI 0 "register_operand" "=A")
7429 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7430 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7431 (clobber (reg:CC 17))]
7434 [(set_attr "type" "imul")
7435 (set_attr "length_immediate" "0")
7436 (set_attr "mode" "SI")])
7438 (define_insn "*umuldi3_highpart_rex64"
7439 [(set (match_operand:DI 0 "register_operand" "=d")
7442 (mult:TI (zero_extend:TI
7443 (match_operand:DI 1 "register_operand" "%a"))
7445 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7447 (clobber (match_scratch:DI 3 "=a"))
7448 (clobber (reg:CC 17))]
7451 [(set_attr "type" "imul")
7452 (set_attr "ppro_uops" "few")
7453 (set_attr "length_immediate" "0")
7454 (set_attr "mode" "DI")])
7456 (define_insn "umulsi3_highpart"
7457 [(set (match_operand:SI 0 "register_operand" "=d")
7460 (mult:DI (zero_extend:DI
7461 (match_operand:SI 1 "register_operand" "%a"))
7463 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7465 (clobber (match_scratch:SI 3 "=a"))
7466 (clobber (reg:CC 17))]
7469 [(set_attr "type" "imul")
7470 (set_attr "ppro_uops" "few")
7471 (set_attr "length_immediate" "0")
7472 (set_attr "mode" "SI")])
7474 (define_insn "*umulsi3_highpart_zext"
7475 [(set (match_operand:DI 0 "register_operand" "=d")
7476 (zero_extend:DI (truncate:SI
7478 (mult:DI (zero_extend:DI
7479 (match_operand:SI 1 "register_operand" "%a"))
7481 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7483 (clobber (match_scratch:SI 3 "=a"))
7484 (clobber (reg:CC 17))]
7487 [(set_attr "type" "imul")
7488 (set_attr "ppro_uops" "few")
7489 (set_attr "length_immediate" "0")
7490 (set_attr "mode" "SI")])
7492 (define_insn "*smuldi3_highpart_rex64"
7493 [(set (match_operand:DI 0 "register_operand" "=d")
7496 (mult:TI (sign_extend:TI
7497 (match_operand:DI 1 "register_operand" "%a"))
7499 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7501 (clobber (match_scratch:DI 3 "=a"))
7502 (clobber (reg:CC 17))]
7505 [(set_attr "type" "imul")
7506 (set_attr "ppro_uops" "few")
7507 (set_attr "mode" "DI")])
7509 (define_insn "smulsi3_highpart"
7510 [(set (match_operand:SI 0 "register_operand" "=d")
7513 (mult:DI (sign_extend:DI
7514 (match_operand:SI 1 "register_operand" "%a"))
7516 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7518 (clobber (match_scratch:SI 3 "=a"))
7519 (clobber (reg:CC 17))]
7522 [(set_attr "type" "imul")
7523 (set_attr "ppro_uops" "few")
7524 (set_attr "mode" "SI")])
7526 (define_insn "*smulsi3_highpart_zext"
7527 [(set (match_operand:DI 0 "register_operand" "=d")
7528 (zero_extend:DI (truncate:SI
7530 (mult:DI (sign_extend:DI
7531 (match_operand:SI 1 "register_operand" "%a"))
7533 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7535 (clobber (match_scratch:SI 3 "=a"))
7536 (clobber (reg:CC 17))]
7539 [(set_attr "type" "imul")
7540 (set_attr "ppro_uops" "few")
7541 (set_attr "mode" "SI")])
7543 ;; The patterns that match these are at the end of this file.
7545 (define_expand "mulxf3"
7546 [(set (match_operand:XF 0 "register_operand" "")
7547 (mult:XF (match_operand:XF 1 "register_operand" "")
7548 (match_operand:XF 2 "register_operand" "")))]
7549 "TARGET_80387 && !TARGET_64BIT"
7552 (define_expand "multf3"
7553 [(set (match_operand:TF 0 "register_operand" "")
7554 (mult:TF (match_operand:TF 1 "register_operand" "")
7555 (match_operand:TF 2 "register_operand" "")))]
7559 (define_expand "muldf3"
7560 [(set (match_operand:DF 0 "register_operand" "")
7561 (mult:DF (match_operand:DF 1 "register_operand" "")
7562 (match_operand:DF 2 "nonimmediate_operand" "")))]
7563 "TARGET_80387 || TARGET_SSE2"
7566 (define_expand "mulsf3"
7567 [(set (match_operand:SF 0 "register_operand" "")
7568 (mult:SF (match_operand:SF 1 "register_operand" "")
7569 (match_operand:SF 2 "nonimmediate_operand" "")))]
7570 "TARGET_80387 || TARGET_SSE"
7573 ;; Divide instructions
7575 (define_insn "divqi3"
7576 [(set (match_operand:QI 0 "register_operand" "=a")
7577 (div:QI (match_operand:HI 1 "register_operand" "0")
7578 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7579 (clobber (reg:CC 17))]
7580 "TARGET_QIMODE_MATH"
7582 [(set_attr "type" "idiv")
7583 (set_attr "mode" "QI")
7584 (set_attr "ppro_uops" "few")])
7586 (define_insn "udivqi3"
7587 [(set (match_operand:QI 0 "register_operand" "=a")
7588 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7589 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7590 (clobber (reg:CC 17))]
7591 "TARGET_QIMODE_MATH"
7593 [(set_attr "type" "idiv")
7594 (set_attr "mode" "QI")
7595 (set_attr "ppro_uops" "few")])
7597 ;; The patterns that match these are at the end of this file.
7599 (define_expand "divxf3"
7600 [(set (match_operand:XF 0 "register_operand" "")
7601 (div:XF (match_operand:XF 1 "register_operand" "")
7602 (match_operand:XF 2 "register_operand" "")))]
7603 "TARGET_80387 && !TARGET_64BIT"
7606 (define_expand "divtf3"
7607 [(set (match_operand:TF 0 "register_operand" "")
7608 (div:TF (match_operand:TF 1 "register_operand" "")
7609 (match_operand:TF 2 "register_operand" "")))]
7613 (define_expand "divdf3"
7614 [(set (match_operand:DF 0 "register_operand" "")
7615 (div:DF (match_operand:DF 1 "register_operand" "")
7616 (match_operand:DF 2 "nonimmediate_operand" "")))]
7617 "TARGET_80387 || TARGET_SSE2"
7620 (define_expand "divsf3"
7621 [(set (match_operand:SF 0 "register_operand" "")
7622 (div:SF (match_operand:SF 1 "register_operand" "")
7623 (match_operand:SF 2 "nonimmediate_operand" "")))]
7624 "TARGET_80387 || TARGET_SSE"
7627 ;; Remainder instructions.
7629 (define_expand "divmoddi4"
7630 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7631 (div:DI (match_operand:DI 1 "register_operand" "")
7632 (match_operand:DI 2 "nonimmediate_operand" "")))
7633 (set (match_operand:DI 3 "register_operand" "")
7634 (mod:DI (match_dup 1) (match_dup 2)))
7635 (clobber (reg:CC 17))])]
7639 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7640 ;; Penalize eax case sligthly because it results in worse scheduling
7642 (define_insn "*divmoddi4_nocltd_rex64"
7643 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7644 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7645 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7646 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7647 (mod:DI (match_dup 2) (match_dup 3)))
7648 (clobber (reg:CC 17))]
7649 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7651 [(set_attr "type" "multi")])
7653 (define_insn "*divmoddi4_cltd_rex64"
7654 [(set (match_operand:DI 0 "register_operand" "=a")
7655 (div:DI (match_operand:DI 2 "register_operand" "a")
7656 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7657 (set (match_operand:DI 1 "register_operand" "=&d")
7658 (mod:DI (match_dup 2) (match_dup 3)))
7659 (clobber (reg:CC 17))]
7660 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7662 [(set_attr "type" "multi")])
7664 (define_insn "*divmoddi_noext_rex64"
7665 [(set (match_operand:DI 0 "register_operand" "=a")
7666 (div:DI (match_operand:DI 1 "register_operand" "0")
7667 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7668 (set (match_operand:DI 3 "register_operand" "=d")
7669 (mod:DI (match_dup 1) (match_dup 2)))
7670 (use (match_operand:DI 4 "register_operand" "3"))
7671 (clobber (reg:CC 17))]
7674 [(set_attr "type" "idiv")
7675 (set_attr "mode" "DI")
7676 (set_attr "ppro_uops" "few")])
7679 [(set (match_operand:DI 0 "register_operand" "")
7680 (div:DI (match_operand:DI 1 "register_operand" "")
7681 (match_operand:DI 2 "nonimmediate_operand" "")))
7682 (set (match_operand:DI 3 "register_operand" "")
7683 (mod:DI (match_dup 1) (match_dup 2)))
7684 (clobber (reg:CC 17))]
7685 "TARGET_64BIT && reload_completed"
7686 [(parallel [(set (match_dup 3)
7687 (ashiftrt:DI (match_dup 4) (const_int 63)))
7688 (clobber (reg:CC 17))])
7689 (parallel [(set (match_dup 0)
7690 (div:DI (reg:DI 0) (match_dup 2)))
7692 (mod:DI (reg:DI 0) (match_dup 2)))
7694 (clobber (reg:CC 17))])]
7697 /* Avoid use of cltd in favour of a mov+shift. */
7698 if (!TARGET_USE_CLTD && !optimize_size)
7700 if (true_regnum (operands[1]))
7701 emit_move_insn (operands[0], operands[1]);
7703 emit_move_insn (operands[3], operands[1]);
7704 operands[4] = operands[3];
7708 if (true_regnum (operands[1]))
7710 operands[4] = operands[1];
7715 (define_expand "divmodsi4"
7716 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7717 (div:SI (match_operand:SI 1 "register_operand" "")
7718 (match_operand:SI 2 "nonimmediate_operand" "")))
7719 (set (match_operand:SI 3 "register_operand" "")
7720 (mod:SI (match_dup 1) (match_dup 2)))
7721 (clobber (reg:CC 17))])]
7725 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7726 ;; Penalize eax case sligthly because it results in worse scheduling
7728 (define_insn "*divmodsi4_nocltd"
7729 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7730 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7731 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7732 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7733 (mod:SI (match_dup 2) (match_dup 3)))
7734 (clobber (reg:CC 17))]
7735 "!optimize_size && !TARGET_USE_CLTD"
7737 [(set_attr "type" "multi")])
7739 (define_insn "*divmodsi4_cltd"
7740 [(set (match_operand:SI 0 "register_operand" "=a")
7741 (div:SI (match_operand:SI 2 "register_operand" "a")
7742 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7743 (set (match_operand:SI 1 "register_operand" "=&d")
7744 (mod:SI (match_dup 2) (match_dup 3)))
7745 (clobber (reg:CC 17))]
7746 "optimize_size || TARGET_USE_CLTD"
7748 [(set_attr "type" "multi")])
7750 (define_insn "*divmodsi_noext"
7751 [(set (match_operand:SI 0 "register_operand" "=a")
7752 (div:SI (match_operand:SI 1 "register_operand" "0")
7753 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7754 (set (match_operand:SI 3 "register_operand" "=d")
7755 (mod:SI (match_dup 1) (match_dup 2)))
7756 (use (match_operand:SI 4 "register_operand" "3"))
7757 (clobber (reg:CC 17))]
7760 [(set_attr "type" "idiv")
7761 (set_attr "mode" "SI")
7762 (set_attr "ppro_uops" "few")])
7765 [(set (match_operand:SI 0 "register_operand" "")
7766 (div:SI (match_operand:SI 1 "register_operand" "")
7767 (match_operand:SI 2 "nonimmediate_operand" "")))
7768 (set (match_operand:SI 3 "register_operand" "")
7769 (mod:SI (match_dup 1) (match_dup 2)))
7770 (clobber (reg:CC 17))]
7772 [(parallel [(set (match_dup 3)
7773 (ashiftrt:SI (match_dup 4) (const_int 31)))
7774 (clobber (reg:CC 17))])
7775 (parallel [(set (match_dup 0)
7776 (div:SI (reg:SI 0) (match_dup 2)))
7778 (mod:SI (reg:SI 0) (match_dup 2)))
7780 (clobber (reg:CC 17))])]
7783 /* Avoid use of cltd in favour of a mov+shift. */
7784 if (!TARGET_USE_CLTD && !optimize_size)
7786 if (true_regnum (operands[1]))
7787 emit_move_insn (operands[0], operands[1]);
7789 emit_move_insn (operands[3], operands[1]);
7790 operands[4] = operands[3];
7794 if (true_regnum (operands[1]))
7796 operands[4] = operands[1];
7800 (define_insn "divmodhi4"
7801 [(set (match_operand:HI 0 "register_operand" "=a")
7802 (div:HI (match_operand:HI 1 "register_operand" "0")
7803 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7804 (set (match_operand:HI 3 "register_operand" "=&d")
7805 (mod:HI (match_dup 1) (match_dup 2)))
7806 (clobber (reg:CC 17))]
7807 "TARGET_HIMODE_MATH"
7808 "cwtd\;idiv{w}\\t%2"
7809 [(set_attr "type" "multi")
7810 (set_attr "length_immediate" "0")
7811 (set_attr "mode" "SI")])
7813 (define_insn "udivmoddi4"
7814 [(set (match_operand:DI 0 "register_operand" "=a")
7815 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7816 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7817 (set (match_operand:DI 3 "register_operand" "=&d")
7818 (umod:DI (match_dup 1) (match_dup 2)))
7819 (clobber (reg:CC 17))]
7821 "xor{q}\\t%3, %3\;div{q}\\t%2"
7822 [(set_attr "type" "multi")
7823 (set_attr "length_immediate" "0")
7824 (set_attr "mode" "DI")])
7826 (define_insn "*udivmoddi4_noext"
7827 [(set (match_operand:DI 0 "register_operand" "=a")
7828 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7829 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7830 (set (match_operand:DI 3 "register_operand" "=d")
7831 (umod:DI (match_dup 1) (match_dup 2)))
7833 (clobber (reg:CC 17))]
7836 [(set_attr "type" "idiv")
7837 (set_attr "ppro_uops" "few")
7838 (set_attr "mode" "DI")])
7841 [(set (match_operand:DI 0 "register_operand" "")
7842 (udiv:DI (match_operand:DI 1 "register_operand" "")
7843 (match_operand:DI 2 "nonimmediate_operand" "")))
7844 (set (match_operand:DI 3 "register_operand" "")
7845 (umod:DI (match_dup 1) (match_dup 2)))
7846 (clobber (reg:CC 17))]
7847 "reload_completed && TARGET_64BIT"
7848 [(set (match_dup 3) (const_int 0))
7849 (parallel [(set (match_dup 0)
7850 (udiv:DI (match_dup 1) (match_dup 2)))
7852 (umod:DI (match_dup 1) (match_dup 2)))
7854 (clobber (reg:CC 17))])]
7857 (define_insn "udivmodsi4"
7858 [(set (match_operand:SI 0 "register_operand" "=a")
7859 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7860 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7861 (set (match_operand:SI 3 "register_operand" "=&d")
7862 (umod:SI (match_dup 1) (match_dup 2)))
7863 (clobber (reg:CC 17))]
7865 "xor{l}\\t%3, %3\;div{l}\\t%2"
7866 [(set_attr "type" "multi")
7867 (set_attr "length_immediate" "0")
7868 (set_attr "mode" "SI")])
7870 (define_insn "*udivmodsi4_noext"
7871 [(set (match_operand:SI 0 "register_operand" "=a")
7872 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7873 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7874 (set (match_operand:SI 3 "register_operand" "=d")
7875 (umod:SI (match_dup 1) (match_dup 2)))
7877 (clobber (reg:CC 17))]
7880 [(set_attr "type" "idiv")
7881 (set_attr "ppro_uops" "few")
7882 (set_attr "mode" "SI")])
7885 [(set (match_operand:SI 0 "register_operand" "")
7886 (udiv:SI (match_operand:SI 1 "register_operand" "")
7887 (match_operand:SI 2 "nonimmediate_operand" "")))
7888 (set (match_operand:SI 3 "register_operand" "")
7889 (umod:SI (match_dup 1) (match_dup 2)))
7890 (clobber (reg:CC 17))]
7892 [(set (match_dup 3) (const_int 0))
7893 (parallel [(set (match_dup 0)
7894 (udiv:SI (match_dup 1) (match_dup 2)))
7896 (umod:SI (match_dup 1) (match_dup 2)))
7898 (clobber (reg:CC 17))])]
7901 (define_expand "udivmodhi4"
7902 [(set (match_dup 4) (const_int 0))
7903 (parallel [(set (match_operand:HI 0 "register_operand" "")
7904 (udiv:HI (match_operand:HI 1 "register_operand" "")
7905 (match_operand:HI 2 "nonimmediate_operand" "")))
7906 (set (match_operand:HI 3 "register_operand" "")
7907 (umod:HI (match_dup 1) (match_dup 2)))
7909 (clobber (reg:CC 17))])]
7910 "TARGET_HIMODE_MATH"
7911 "operands[4] = gen_reg_rtx (HImode);")
7913 (define_insn "*udivmodhi_noext"
7914 [(set (match_operand:HI 0 "register_operand" "=a")
7915 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7916 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7917 (set (match_operand:HI 3 "register_operand" "=d")
7918 (umod:HI (match_dup 1) (match_dup 2)))
7919 (use (match_operand:HI 4 "register_operand" "3"))
7920 (clobber (reg:CC 17))]
7923 [(set_attr "type" "idiv")
7924 (set_attr "mode" "HI")
7925 (set_attr "ppro_uops" "few")])
7927 ;; We can not use div/idiv for double division, because it causes
7928 ;; "division by zero" on the overflow and that's not what we expect
7929 ;; from truncate. Because true (non truncating) double division is
7930 ;; never generated, we can't create this insn anyway.
7933 ; [(set (match_operand:SI 0 "register_operand" "=a")
7935 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7937 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7938 ; (set (match_operand:SI 3 "register_operand" "=d")
7940 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7941 ; (clobber (reg:CC 17))]
7943 ; "div{l}\\t{%2, %0|%0, %2}"
7944 ; [(set_attr "type" "idiv")
7945 ; (set_attr "ppro_uops" "few")])
7947 ;;- Logical AND instructions
7949 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7950 ;; Note that this excludes ah.
7952 (define_insn "*testdi_1_rex64"
7955 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7956 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7958 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7960 test{l}\\t{%k1, %k0|%k0, %k1}
7961 test{l}\\t{%k1, %k0|%k0, %k1}
7962 test{q}\\t{%1, %0|%0, %1}
7963 test{q}\\t{%1, %0|%0, %1}
7964 test{q}\\t{%1, %0|%0, %1}"
7965 [(set_attr "type" "test")
7966 (set_attr "modrm" "0,1,0,1,1")
7967 (set_attr "mode" "SI,SI,DI,DI,DI")
7968 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7970 (define_insn "testsi_1"
7973 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7974 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7976 "ix86_match_ccmode (insn, CCNOmode)"
7977 "test{l}\\t{%1, %0|%0, %1}"
7978 [(set_attr "type" "test")
7979 (set_attr "modrm" "0,1,1")
7980 (set_attr "mode" "SI")
7981 (set_attr "pent_pair" "uv,np,uv")])
7983 (define_expand "testsi_ccno_1"
7986 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7987 (match_operand:SI 1 "nonmemory_operand" ""))
7992 (define_insn "*testhi_1"
7994 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7995 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7997 "ix86_match_ccmode (insn, CCNOmode)"
7998 "test{w}\\t{%1, %0|%0, %1}"
7999 [(set_attr "type" "test")
8000 (set_attr "modrm" "0,1,1")
8001 (set_attr "mode" "HI")
8002 (set_attr "pent_pair" "uv,np,uv")])
8004 (define_expand "testqi_ccz_1"
8006 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
8007 (match_operand:QI 1 "nonmemory_operand" ""))
8012 (define_insn "*testqi_1"
8014 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
8015 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
8017 "ix86_match_ccmode (insn, CCNOmode)"
8020 if (which_alternative == 3)
8022 if (GET_CODE (operands[1]) == CONST_INT
8023 && (INTVAL (operands[1]) & 0xffffff00))
8024 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
8025 return \"test{l}\\t{%1, %k0|%k0, %1}\";
8027 return \"test{b}\\t{%1, %0|%0, %1}\";
8029 [(set_attr "type" "test")
8030 (set_attr "modrm" "0,1,1,1")
8031 (set_attr "mode" "QI,QI,QI,SI")
8032 (set_attr "pent_pair" "uv,np,uv,np")])
8034 (define_expand "testqi_ext_ccno_0"
8039 (match_operand 0 "ext_register_operand" "")
8042 (match_operand 1 "const_int_operand" ""))
8047 (define_insn "*testqi_ext_0"
8052 (match_operand 0 "ext_register_operand" "Q")
8055 (match_operand 1 "const_int_operand" "n"))
8057 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
8058 && ix86_match_ccmode (insn, CCNOmode)"
8059 "test{b}\\t{%1, %h0|%h0, %1}"
8060 [(set_attr "type" "test")
8061 (set_attr "mode" "QI")
8062 (set_attr "length_immediate" "1")
8063 (set_attr "pent_pair" "np")])
8065 (define_insn "*testqi_ext_1"
8070 (match_operand 0 "ext_register_operand" "Q")
8074 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
8076 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8077 "test{b}\\t{%1, %h0|%h0, %1}"
8078 [(set_attr "type" "test")
8079 (set_attr "mode" "QI")])
8081 (define_insn "*testqi_ext_1_rex64"
8086 (match_operand 0 "ext_register_operand" "Q")
8090 (match_operand:QI 1 "register_operand" "Q")))
8092 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8093 "test{b}\\t{%1, %h0|%h0, %1}"
8094 [(set_attr "type" "test")
8095 (set_attr "mode" "QI")])
8097 (define_insn "*testqi_ext_2"
8102 (match_operand 0 "ext_register_operand" "Q")
8106 (match_operand 1 "ext_register_operand" "Q")
8110 "ix86_match_ccmode (insn, CCNOmode)"
8111 "test{b}\\t{%h1, %h0|%h0, %h1}"
8112 [(set_attr "type" "test")
8113 (set_attr "mode" "QI")])
8115 ;; Combine likes to form bit extractions for some tests. Humor it.
8116 (define_insn "*testqi_ext_3"
8118 (compare (zero_extract:SI
8119 (match_operand 0 "nonimmediate_operand" "rm")
8120 (match_operand:SI 1 "const_int_operand" "")
8121 (match_operand:SI 2 "const_int_operand" ""))
8123 "ix86_match_ccmode (insn, CCNOmode)
8124 && (GET_MODE (operands[0]) == SImode
8125 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8126 || GET_MODE (operands[0]) == HImode
8127 || GET_MODE (operands[0]) == QImode)"
8130 (define_insn "*testqi_ext_3_rex64"
8132 (compare (zero_extract:DI
8133 (match_operand 0 "nonimmediate_operand" "rm")
8134 (match_operand:DI 1 "const_int_operand" "")
8135 (match_operand:DI 2 "const_int_operand" ""))
8137 "ix86_match_ccmode (insn, CCNOmode)
8139 && (GET_MODE (operands[0]) == SImode
8140 || GET_MODE (operands[0]) == DImode
8141 || GET_MODE (operands[0]) == HImode
8142 || GET_MODE (operands[0]) == QImode)"
8147 (compare (zero_extract
8148 (match_operand 0 "nonimmediate_operand" "rm")
8149 (match_operand 1 "const_int_operand" "")
8150 (match_operand 2 "const_int_operand" ""))
8152 "ix86_match_ccmode (insn, CCNOmode)"
8153 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8156 HOST_WIDE_INT len = INTVAL (operands[1]);
8157 HOST_WIDE_INT pos = INTVAL (operands[2]);
8159 enum machine_mode mode;
8161 mode = GET_MODE (operands[0]);
8162 if (GET_CODE (operands[0]) == MEM)
8164 /* ??? Combine likes to put non-volatile mem extractions in QImode
8165 no matter the size of the test. So find a mode that works. */
8166 if (! MEM_VOLATILE_P (operands[0]))
8168 mode = smallest_mode_for_size (pos + len, MODE_INT);
8169 operands[0] = change_address (operands[0], mode, NULL_RTX);
8172 else if (mode == HImode && pos + len <= 8)
8174 /* Small HImode tests can be converted to QImode. */
8176 operands[0] = gen_lowpart (QImode, operands[0]);
8179 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8180 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8182 operands[3] = gen_rtx_AND (mode, operands[0],
8183 GEN_INT (trunc_int_for_mode (mask, mode)));
8186 ;; %%% This used to optimize known byte-wide and operations to memory,
8187 ;; and sometimes to QImode registers. If this is considered useful,
8188 ;; it should be done with splitters.
8190 (define_expand "anddi3"
8191 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8192 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8193 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8194 (clobber (reg:CC 17))]
8196 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8198 (define_insn "*anddi_1_rex64"
8199 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8200 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8201 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8202 (clobber (reg:CC 17))]
8203 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8206 switch (get_attr_type (insn))
8210 enum machine_mode mode;
8212 if (GET_CODE (operands[2]) != CONST_INT)
8214 if (INTVAL (operands[2]) == 0xff)
8216 else if (INTVAL (operands[2]) == 0xffff)
8221 operands[1] = gen_lowpart (mode, operands[1]);
8223 return \"movz{bq|x}\\t{%1,%0|%0, %1}\";
8225 return \"movz{wq|x}\\t{%1,%0|%0, %1}\";
8229 if (! rtx_equal_p (operands[0], operands[1]))
8231 if (get_attr_mode (insn) == MODE_SI)
8232 return \"and{l}\\t{%k2, %k0|%k0, %k2}\";
8234 return \"and{q}\\t{%2, %0|%0, %2}\";
8237 [(set_attr "type" "alu,alu,alu,imovx")
8238 (set_attr "length_immediate" "*,*,*,0")
8239 (set_attr "mode" "SI,DI,DI,DI")])
8241 (define_insn "*anddi_2"
8243 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8244 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8246 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8247 (and:DI (match_dup 1) (match_dup 2)))]
8248 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8249 && ix86_binary_operator_ok (AND, DImode, operands)"
8251 and{l}\\t{%k2, %k0|%k0, %k2}
8252 and{q}\\t{%2, %0|%0, %2}
8253 and{q}\\t{%2, %0|%0, %2}"
8254 [(set_attr "type" "alu")
8255 (set_attr "mode" "SI,DI,DI")])
8257 (define_expand "andsi3"
8258 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8259 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8260 (match_operand:SI 2 "general_operand" "")))
8261 (clobber (reg:CC 17))]
8263 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8265 (define_insn "*andsi_1"
8266 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8267 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8268 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8269 (clobber (reg:CC 17))]
8270 "ix86_binary_operator_ok (AND, SImode, operands)"
8273 switch (get_attr_type (insn))
8277 enum machine_mode mode;
8279 if (GET_CODE (operands[2]) != CONST_INT)
8281 if (INTVAL (operands[2]) == 0xff)
8283 else if (INTVAL (operands[2]) == 0xffff)
8288 operands[1] = gen_lowpart (mode, operands[1]);
8290 return \"movz{bl|x}\\t{%1,%0|%0, %1}\";
8292 return \"movz{wl|x}\\t{%1,%0|%0, %1}\";
8296 if (! rtx_equal_p (operands[0], operands[1]))
8298 return \"and{l}\\t{%2, %0|%0, %2}\";
8301 [(set_attr "type" "alu,alu,imovx")
8302 (set_attr "length_immediate" "*,*,0")
8303 (set_attr "mode" "SI")])
8306 [(set (match_operand 0 "ext_register_operand" "")
8308 (const_int -65536)))
8309 (clobber (reg:CC 17))]
8311 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8312 "operands[1] = gen_lowpart (HImode, operands[0]);")
8315 [(set (match_operand 0 "ext_register_operand" "")
8318 (clobber (reg:CC 17))]
8319 "(optimize_size || !TARGET_PARTIAL_REG_STALL)"
8320 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8321 "operands[1] = gen_lowpart (QImode, operands[0]);")
8324 [(set (match_operand 0 "ext_register_operand" "")
8326 (const_int -65281)))
8327 (clobber (reg:CC 17))]
8328 "(optimize_size || !TARGET_PARTIAL_REG_STALL)"
8329 [(parallel [(set (zero_extract:SI (match_dup 0)
8333 (zero_extract:SI (match_dup 0)
8336 (zero_extract:SI (match_dup 0)
8339 (clobber (reg:CC 17))])]
8340 "operands[0] = gen_lowpart (SImode, operands[0]);")
8342 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8343 (define_insn "*andsi_1_zext"
8344 [(set (match_operand:DI 0 "register_operand" "=r")
8346 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8347 (match_operand:SI 2 "general_operand" "rim"))))
8348 (clobber (reg:CC 17))]
8349 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8350 "and{l}\\t{%2, %k0|%k0, %2}"
8351 [(set_attr "type" "alu")
8352 (set_attr "mode" "SI")])
8354 (define_insn "*andsi_2"
8356 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8357 (match_operand:SI 2 "general_operand" "rim,ri"))
8359 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8360 (and:SI (match_dup 1) (match_dup 2)))]
8361 "ix86_match_ccmode (insn, CCNOmode)
8362 && ix86_binary_operator_ok (AND, SImode, operands)"
8363 "and{l}\\t{%2, %0|%0, %2}"
8364 [(set_attr "type" "alu")
8365 (set_attr "mode" "SI")])
8367 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8368 (define_insn "*andsi_2_zext"
8370 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8371 (match_operand:SI 2 "general_operand" "rim"))
8373 (set (match_operand:DI 0 "register_operand" "=r")
8374 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8375 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8376 && ix86_binary_operator_ok (AND, SImode, operands)"
8377 "and{l}\\t{%2, %k0|%k0, %2}"
8378 [(set_attr "type" "alu")
8379 (set_attr "mode" "SI")])
8381 (define_expand "andhi3"
8382 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8383 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8384 (match_operand:HI 2 "general_operand" "")))
8385 (clobber (reg:CC 17))]
8386 "TARGET_HIMODE_MATH"
8387 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8389 (define_insn "*andhi_1"
8390 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8391 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8392 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8393 (clobber (reg:CC 17))]
8394 "ix86_binary_operator_ok (AND, HImode, operands)"
8397 switch (get_attr_type (insn))
8400 if (GET_CODE (operands[2]) != CONST_INT)
8402 if (INTVAL (operands[2]) == 0xff)
8403 return \"movz{bl|x}\\t{%b1, %k0|%k0, %b1}\";
8407 if (! rtx_equal_p (operands[0], operands[1]))
8410 return \"and{w}\\t{%2, %0|%0, %2}\";
8413 [(set_attr "type" "alu,alu,imovx")
8414 (set_attr "length_immediate" "*,*,0")
8415 (set_attr "mode" "HI,HI,SI")])
8417 (define_insn "*andhi_2"
8419 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8420 (match_operand:HI 2 "general_operand" "rim,ri"))
8422 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8423 (and:HI (match_dup 1) (match_dup 2)))]
8424 "ix86_match_ccmode (insn, CCNOmode)
8425 && ix86_binary_operator_ok (AND, HImode, operands)"
8426 "and{w}\\t{%2, %0|%0, %2}"
8427 [(set_attr "type" "alu")
8428 (set_attr "mode" "HI")])
8430 (define_expand "andqi3"
8431 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8432 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8433 (match_operand:QI 2 "general_operand" "")))
8434 (clobber (reg:CC 17))]
8435 "TARGET_QIMODE_MATH"
8436 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8438 ;; %%% Potential partial reg stall on alternative 2. What to do?
8439 (define_insn "*andqi_1"
8440 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8441 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8442 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8443 (clobber (reg:CC 17))]
8444 "ix86_binary_operator_ok (AND, QImode, operands)"
8446 and{b}\\t{%2, %0|%0, %2}
8447 and{b}\\t{%2, %0|%0, %2}
8448 and{l}\\t{%k2, %k0|%k0, %k2}"
8449 [(set_attr "type" "alu")
8450 (set_attr "mode" "QI,QI,SI")])
8452 (define_insn "*andqi_1_slp"
8453 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8454 (and:QI (match_dup 0)
8455 (match_operand:QI 1 "general_operand" "qi,qmi")))
8456 (clobber (reg:CC 17))]
8458 "and{b}\\t{%1, %0|%0, %1}"
8459 [(set_attr "type" "alu1")
8460 (set_attr "mode" "QI")])
8462 (define_insn "*andqi_2"
8465 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8466 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8468 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8469 (and:QI (match_dup 1) (match_dup 2)))]
8470 "ix86_match_ccmode (insn, CCNOmode)
8471 && ix86_binary_operator_ok (AND, QImode, operands)"
8474 if (which_alternative == 2)
8476 if (GET_CODE (operands[2]) == CONST_INT
8477 && (INTVAL (operands[2]) & 0xffffff00))
8478 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8479 return \"and{l}\\t{%2, %k0|%k0, %2}\";
8481 return \"and{b}\\t{%2, %0|%0, %2}\";
8483 [(set_attr "type" "alu")
8484 (set_attr "mode" "QI,QI,SI")])
8486 (define_insn "*andqi_2_slp"
8489 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8490 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8492 (set (strict_low_part (match_dup 0))
8493 (and:QI (match_dup 0) (match_dup 1)))]
8494 "ix86_match_ccmode (insn, CCNOmode)"
8495 "and{b}\\t{%1, %0|%0, %1}"
8496 [(set_attr "type" "alu1")
8497 (set_attr "mode" "QI")])
8499 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8500 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8501 ;; for a QImode operand, which of course failed.
8503 (define_insn "andqi_ext_0"
8504 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8509 (match_operand 1 "ext_register_operand" "0")
8512 (match_operand 2 "const_int_operand" "n")))
8513 (clobber (reg:CC 17))]
8514 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8515 "and{b}\\t{%2, %h0|%h0, %2}"
8516 [(set_attr "type" "alu")
8517 (set_attr "length_immediate" "1")
8518 (set_attr "mode" "QI")])
8520 ;; Generated by peephole translating test to and. This shows up
8521 ;; often in fp comparisons.
8523 (define_insn "*andqi_ext_0_cc"
8528 (match_operand 1 "ext_register_operand" "0")
8531 (match_operand 2 "const_int_operand" "n"))
8533 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8542 "ix86_match_ccmode (insn, CCNOmode)
8543 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8544 "and{b}\\t{%2, %h0|%h0, %2}"
8545 [(set_attr "type" "alu")
8546 (set_attr "length_immediate" "1")
8547 (set_attr "mode" "QI")])
8549 (define_insn "*andqi_ext_1"
8550 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8555 (match_operand 1 "ext_register_operand" "0")
8559 (match_operand:QI 2 "general_operand" "Qm"))))
8560 (clobber (reg:CC 17))]
8562 "and{b}\\t{%2, %h0|%h0, %2}"
8563 [(set_attr "type" "alu")
8564 (set_attr "length_immediate" "0")
8565 (set_attr "mode" "QI")])
8567 (define_insn "*andqi_ext_1_rex64"
8568 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8573 (match_operand 1 "ext_register_operand" "0")
8577 (match_operand 2 "ext_register_operand" "Q"))))
8578 (clobber (reg:CC 17))]
8580 "and{b}\\t{%2, %h0|%h0, %2}"
8581 [(set_attr "type" "alu")
8582 (set_attr "length_immediate" "0")
8583 (set_attr "mode" "QI")])
8585 (define_insn "*andqi_ext_2"
8586 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8591 (match_operand 1 "ext_register_operand" "%0")
8595 (match_operand 2 "ext_register_operand" "Q")
8598 (clobber (reg:CC 17))]
8600 "and{b}\\t{%h2, %h0|%h0, %h2}"
8601 [(set_attr "type" "alu")
8602 (set_attr "length_immediate" "0")
8603 (set_attr "mode" "QI")])
8605 ;; Logical inclusive OR instructions
8607 ;; %%% This used to optimize known byte-wide and operations to memory.
8608 ;; If this is considered useful, it should be done with splitters.
8610 (define_expand "iordi3"
8611 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8612 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8613 (match_operand:DI 2 "x86_64_general_operand" "")))
8614 (clobber (reg:CC 17))]
8616 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8618 (define_insn "*iordi_1_rex64"
8619 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8620 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8621 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8622 (clobber (reg:CC 17))]
8624 && ix86_binary_operator_ok (IOR, DImode, operands)"
8625 "or{q}\\t{%2, %0|%0, %2}"
8626 [(set_attr "type" "alu")
8627 (set_attr "mode" "DI")])
8629 (define_insn "*iordi_2_rex64"
8631 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8632 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8634 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8635 (ior:DI (match_dup 1) (match_dup 2)))]
8637 && ix86_match_ccmode (insn, CCNOmode)
8638 && ix86_binary_operator_ok (IOR, DImode, operands)"
8639 "or{q}\\t{%2, %0|%0, %2}"
8640 [(set_attr "type" "alu")
8641 (set_attr "mode" "DI")])
8643 (define_insn "*iordi_3_rex64"
8645 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8646 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8648 (clobber (match_scratch:DI 0 "=r"))]
8650 && ix86_match_ccmode (insn, CCNOmode)
8651 && ix86_binary_operator_ok (IOR, DImode, operands)"
8652 "or{q}\\t{%2, %0|%0, %2}"
8653 [(set_attr "type" "alu")
8654 (set_attr "mode" "DI")])
8657 (define_expand "iorsi3"
8658 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8659 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8660 (match_operand:SI 2 "general_operand" "")))
8661 (clobber (reg:CC 17))]
8663 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8665 (define_insn "*iorsi_1"
8666 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8667 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8668 (match_operand:SI 2 "general_operand" "ri,rmi")))
8669 (clobber (reg:CC 17))]
8670 "ix86_binary_operator_ok (IOR, SImode, operands)"
8671 "or{l}\\t{%2, %0|%0, %2}"
8672 [(set_attr "type" "alu")
8673 (set_attr "mode" "SI")])
8675 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8676 (define_insn "*iorsi_1_zext"
8677 [(set (match_operand:DI 0 "register_operand" "=rm")
8679 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8680 (match_operand:SI 2 "general_operand" "rim"))))
8681 (clobber (reg:CC 17))]
8682 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8683 "or{l}\\t{%2, %k0|%k0, %2}"
8684 [(set_attr "type" "alu")
8685 (set_attr "mode" "SI")])
8687 (define_insn "*iorsi_1_zext_imm"
8688 [(set (match_operand:DI 0 "register_operand" "=rm")
8689 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8690 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8691 (clobber (reg:CC 17))]
8693 "or{l}\\t{%2, %k0|%k0, %2}"
8694 [(set_attr "type" "alu")
8695 (set_attr "mode" "SI")])
8697 (define_insn "*iorsi_2"
8699 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8700 (match_operand:SI 2 "general_operand" "rim,ri"))
8702 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8703 (ior:SI (match_dup 1) (match_dup 2)))]
8704 "ix86_match_ccmode (insn, CCNOmode)
8705 && ix86_binary_operator_ok (IOR, SImode, operands)"
8706 "or{l}\\t{%2, %0|%0, %2}"
8707 [(set_attr "type" "alu")
8708 (set_attr "mode" "SI")])
8710 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8711 ;; ??? Special case for immediate operand is missing - it is tricky.
8712 (define_insn "*iorsi_2_zext"
8714 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8715 (match_operand:SI 2 "general_operand" "rim"))
8717 (set (match_operand:DI 0 "register_operand" "=r")
8718 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8719 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8720 && ix86_binary_operator_ok (IOR, SImode, operands)"
8721 "or{l}\\t{%2, %k0|%k0, %2}"
8722 [(set_attr "type" "alu")
8723 (set_attr "mode" "SI")])
8725 (define_insn "*iorsi_2_zext_imm"
8727 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8728 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8730 (set (match_operand:DI 0 "register_operand" "=r")
8731 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8732 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8733 && ix86_binary_operator_ok (IOR, SImode, operands)"
8734 "or{l}\\t{%2, %k0|%k0, %2}"
8735 [(set_attr "type" "alu")
8736 (set_attr "mode" "SI")])
8738 (define_insn "*iorsi_3"
8740 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8741 (match_operand:SI 2 "general_operand" "rim"))
8743 (clobber (match_scratch:SI 0 "=r"))]
8744 "ix86_match_ccmode (insn, CCNOmode)
8745 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8746 "or{l}\\t{%2, %0|%0, %2}"
8747 [(set_attr "type" "alu")
8748 (set_attr "mode" "SI")])
8750 (define_expand "iorhi3"
8751 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8752 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8753 (match_operand:HI 2 "general_operand" "")))
8754 (clobber (reg:CC 17))]
8755 "TARGET_HIMODE_MATH"
8756 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8758 (define_insn "*iorhi_1"
8759 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8760 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8761 (match_operand:HI 2 "general_operand" "rmi,ri")))
8762 (clobber (reg:CC 17))]
8763 "ix86_binary_operator_ok (IOR, HImode, operands)"
8764 "or{w}\\t{%2, %0|%0, %2}"
8765 [(set_attr "type" "alu")
8766 (set_attr "mode" "HI")])
8768 (define_insn "*iorhi_2"
8770 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8771 (match_operand:HI 2 "general_operand" "rim,ri"))
8773 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8774 (ior:HI (match_dup 1) (match_dup 2)))]
8775 "ix86_match_ccmode (insn, CCNOmode)
8776 && ix86_binary_operator_ok (IOR, HImode, operands)"
8777 "or{w}\\t{%2, %0|%0, %2}"
8778 [(set_attr "type" "alu")
8779 (set_attr "mode" "HI")])
8781 (define_insn "*iorhi_3"
8783 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8784 (match_operand:HI 2 "general_operand" "rim"))
8786 (clobber (match_scratch:HI 0 "=r"))]
8787 "ix86_match_ccmode (insn, CCNOmode)
8788 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8789 "or{w}\\t{%2, %0|%0, %2}"
8790 [(set_attr "type" "alu")
8791 (set_attr "mode" "HI")])
8793 (define_expand "iorqi3"
8794 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8795 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8796 (match_operand:QI 2 "general_operand" "")))
8797 (clobber (reg:CC 17))]
8798 "TARGET_QIMODE_MATH"
8799 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8801 ;; %%% Potential partial reg stall on alternative 2. What to do?
8802 (define_insn "*iorqi_1"
8803 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8804 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8805 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8806 (clobber (reg:CC 17))]
8807 "ix86_binary_operator_ok (IOR, QImode, operands)"
8809 or{b}\\t{%2, %0|%0, %2}
8810 or{b}\\t{%2, %0|%0, %2}
8811 or{l}\\t{%k2, %k0|%k0, %k2}"
8812 [(set_attr "type" "alu")
8813 (set_attr "mode" "QI,QI,SI")])
8815 (define_insn "*iorqi_1_slp"
8816 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8817 (ior:QI (match_dup 0)
8818 (match_operand:QI 1 "general_operand" "qmi,qi")))
8819 (clobber (reg:CC 17))]
8821 "or{b}\\t{%1, %0|%0, %1}"
8822 [(set_attr "type" "alu1")
8823 (set_attr "mode" "QI")])
8825 (define_insn "*iorqi_2"
8827 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8828 (match_operand:QI 2 "general_operand" "qim,qi"))
8830 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8831 (ior:QI (match_dup 1) (match_dup 2)))]
8832 "ix86_match_ccmode (insn, CCNOmode)
8833 && ix86_binary_operator_ok (IOR, QImode, operands)"
8834 "or{b}\\t{%2, %0|%0, %2}"
8835 [(set_attr "type" "alu")
8836 (set_attr "mode" "QI")])
8838 (define_insn "*iorqi_2_slp"
8840 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8841 (match_operand:QI 1 "general_operand" "qim,qi"))
8843 (set (strict_low_part (match_dup 0))
8844 (ior:QI (match_dup 0) (match_dup 1)))]
8845 "ix86_match_ccmode (insn, CCNOmode)"
8846 "or{b}\\t{%1, %0|%0, %1}"
8847 [(set_attr "type" "alu1")
8848 (set_attr "mode" "QI")])
8850 (define_insn "*iorqi_3"
8852 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8853 (match_operand:QI 2 "general_operand" "qim"))
8855 (clobber (match_scratch:QI 0 "=q"))]
8856 "ix86_match_ccmode (insn, CCNOmode)
8857 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8858 "or{b}\\t{%2, %0|%0, %2}"
8859 [(set_attr "type" "alu")
8860 (set_attr "mode" "QI")])
8863 ;; Logical XOR instructions
8865 ;; %%% This used to optimize known byte-wide and operations to memory.
8866 ;; If this is considered useful, it should be done with splitters.
8868 (define_expand "xordi3"
8869 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8870 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8871 (match_operand:DI 2 "x86_64_general_operand" "")))
8872 (clobber (reg:CC 17))]
8874 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8876 (define_insn "*xordi_1_rex64"
8877 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8878 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8879 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8880 (clobber (reg:CC 17))]
8882 && ix86_binary_operator_ok (XOR, DImode, operands)"
8884 xor{q}\\t{%2, %0|%0, %2}
8885 xor{q}\\t{%2, %0|%0, %2}"
8886 [(set_attr "type" "alu")
8887 (set_attr "mode" "DI,DI")])
8889 (define_insn "*xordi_2_rex64"
8891 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8892 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8894 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8895 (xor:DI (match_dup 1) (match_dup 2)))]
8897 && ix86_match_ccmode (insn, CCNOmode)
8898 && ix86_binary_operator_ok (XOR, DImode, operands)"
8900 xor{q}\\t{%2, %0|%0, %2}
8901 xor{q}\\t{%2, %0|%0, %2}"
8902 [(set_attr "type" "alu")
8903 (set_attr "mode" "DI,DI")])
8905 (define_insn "*xordi_3_rex64"
8907 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8908 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8910 (clobber (match_scratch:DI 0 "=r"))]
8912 && ix86_match_ccmode (insn, CCNOmode)
8913 && ix86_binary_operator_ok (XOR, DImode, operands)"
8914 "xor{q}\\t{%2, %0|%0, %2}"
8915 [(set_attr "type" "alu")
8916 (set_attr "mode" "DI")])
8918 (define_expand "xorsi3"
8919 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8920 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8921 (match_operand:SI 2 "general_operand" "")))
8922 (clobber (reg:CC 17))]
8924 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8926 (define_insn "*xorsi_1"
8927 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8928 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8929 (match_operand:SI 2 "general_operand" "ri,rm")))
8930 (clobber (reg:CC 17))]
8931 "ix86_binary_operator_ok (XOR, SImode, operands)"
8932 "xor{l}\\t{%2, %0|%0, %2}"
8933 [(set_attr "type" "alu")
8934 (set_attr "mode" "SI")])
8936 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8937 ;; Add speccase for immediates
8938 (define_insn "*xorsi_1_zext"
8939 [(set (match_operand:DI 0 "register_operand" "=r")
8941 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8942 (match_operand:SI 2 "general_operand" "rim"))))
8943 (clobber (reg:CC 17))]
8944 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8945 "xor{l}\\t{%2, %k0|%k0, %2}"
8946 [(set_attr "type" "alu")
8947 (set_attr "mode" "SI")])
8949 (define_insn "*xorsi_1_zext_imm"
8950 [(set (match_operand:DI 0 "register_operand" "=r")
8951 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8952 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8953 (clobber (reg:CC 17))]
8954 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8955 "xor{l}\\t{%2, %k0|%k0, %2}"
8956 [(set_attr "type" "alu")
8957 (set_attr "mode" "SI")])
8959 (define_insn "*xorsi_2"
8961 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8962 (match_operand:SI 2 "general_operand" "rim,ri"))
8964 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8965 (xor:SI (match_dup 1) (match_dup 2)))]
8966 "ix86_match_ccmode (insn, CCNOmode)
8967 && ix86_binary_operator_ok (XOR, SImode, operands)"
8968 "xor{l}\\t{%2, %0|%0, %2}"
8969 [(set_attr "type" "alu")
8970 (set_attr "mode" "SI")])
8972 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8973 ;; ??? Special case for immediate operand is missing - it is tricky.
8974 (define_insn "*xorsi_2_zext"
8976 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8977 (match_operand:SI 2 "general_operand" "rim"))
8979 (set (match_operand:DI 0 "register_operand" "=r")
8980 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8981 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8982 && ix86_binary_operator_ok (XOR, SImode, operands)"
8983 "xor{l}\\t{%2, %k0|%k0, %2}"
8984 [(set_attr "type" "alu")
8985 (set_attr "mode" "SI")])
8987 (define_insn "*xorsi_2_zext_imm"
8989 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8990 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8992 (set (match_operand:DI 0 "register_operand" "=r")
8993 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8994 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8995 && ix86_binary_operator_ok (XOR, SImode, operands)"
8996 "xor{l}\\t{%2, %k0|%k0, %2}"
8997 [(set_attr "type" "alu")
8998 (set_attr "mode" "SI")])
9000 (define_insn "*xorsi_3"
9002 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9003 (match_operand:SI 2 "general_operand" "rim"))
9005 (clobber (match_scratch:SI 0 "=r"))]
9006 "ix86_match_ccmode (insn, CCNOmode)
9007 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9008 "xor{l}\\t{%2, %0|%0, %2}"
9009 [(set_attr "type" "alu")
9010 (set_attr "mode" "SI")])
9012 (define_expand "xorhi3"
9013 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9014 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9015 (match_operand:HI 2 "general_operand" "")))
9016 (clobber (reg:CC 17))]
9017 "TARGET_HIMODE_MATH"
9018 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9020 (define_insn "*xorhi_1"
9021 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9022 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9023 (match_operand:HI 2 "general_operand" "rmi,ri")))
9024 (clobber (reg:CC 17))]
9025 "ix86_binary_operator_ok (XOR, HImode, operands)"
9026 "xor{w}\\t{%2, %0|%0, %2}"
9027 [(set_attr "type" "alu")
9028 (set_attr "mode" "HI")])
9030 (define_insn "*xorhi_2"
9032 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9033 (match_operand:HI 2 "general_operand" "rim,ri"))
9035 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9036 (xor:HI (match_dup 1) (match_dup 2)))]
9037 "ix86_match_ccmode (insn, CCNOmode)
9038 && ix86_binary_operator_ok (XOR, HImode, operands)"
9039 "xor{w}\\t{%2, %0|%0, %2}"
9040 [(set_attr "type" "alu")
9041 (set_attr "mode" "HI")])
9043 (define_insn "*xorhi_3"
9045 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9046 (match_operand:HI 2 "general_operand" "rim"))
9048 (clobber (match_scratch:HI 0 "=r"))]
9049 "ix86_match_ccmode (insn, CCNOmode)
9050 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9051 "xor{w}\\t{%2, %0|%0, %2}"
9052 [(set_attr "type" "alu")
9053 (set_attr "mode" "HI")])
9055 (define_expand "xorqi3"
9056 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9057 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9058 (match_operand:QI 2 "general_operand" "")))
9059 (clobber (reg:CC 17))]
9060 "TARGET_QIMODE_MATH"
9061 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9063 ;; %%% Potential partial reg stall on alternative 2. What to do?
9064 (define_insn "*xorqi_1"
9065 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9066 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9067 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9068 (clobber (reg:CC 17))]
9069 "ix86_binary_operator_ok (XOR, QImode, operands)"
9071 xor{b}\\t{%2, %0|%0, %2}
9072 xor{b}\\t{%2, %0|%0, %2}
9073 xor{l}\\t{%k2, %k0|%k0, %k2}"
9074 [(set_attr "type" "alu")
9075 (set_attr "mode" "QI,QI,SI")])
9077 (define_insn "*xorqi_ext_1"
9078 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9082 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9085 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9088 (clobber (reg:CC 17))]
9090 "xor{b}\\t{%h2, %h0|%h0, %h2}"
9091 [(set_attr "type" "alu")
9092 (set_attr "length_immediate" "0")
9093 (set_attr "mode" "QI")])
9095 (define_insn "*xorqi_cc_1"
9098 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9099 (match_operand:QI 2 "general_operand" "qim,qi"))
9101 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9102 (xor:QI (match_dup 1) (match_dup 2)))]
9103 "ix86_match_ccmode (insn, CCNOmode)
9104 && ix86_binary_operator_ok (XOR, QImode, operands)"
9105 "xor{b}\\t{%2, %0|%0, %2}"
9106 [(set_attr "type" "alu")
9107 (set_attr "mode" "QI")])
9109 (define_insn "*xorqi_cc_2"
9112 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9113 (match_operand:QI 2 "general_operand" "qim"))
9115 (clobber (match_scratch:QI 0 "=q"))]
9116 "ix86_match_ccmode (insn, CCNOmode)
9117 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9118 "xor{b}\\t{%2, %0|%0, %2}"
9119 [(set_attr "type" "alu")
9120 (set_attr "mode" "QI")])
9122 (define_insn "*xorqi_cc_ext_1"
9127 (match_operand 1 "ext_register_operand" "0")
9130 (match_operand:QI 2 "general_operand" "qmn"))
9132 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9136 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9138 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9139 "xor{b}\\t{%2, %h0|%h0, %2}"
9140 [(set_attr "type" "alu")
9141 (set_attr "mode" "QI")])
9143 (define_insn "*xorqi_cc_ext_1_rex64"
9148 (match_operand 1 "ext_register_operand" "0")
9151 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9153 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9157 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9159 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9160 "xor{b}\\t{%2, %h0|%h0, %2}"
9161 [(set_attr "type" "alu")
9162 (set_attr "mode" "QI")])
9164 (define_expand "xorqi_cc_ext_1"
9170 (match_operand 1 "ext_register_operand" "")
9173 (match_operand:QI 2 "general_operand" ""))
9175 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9179 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9184 ;; Negation instructions
9186 (define_expand "negdi2"
9187 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9188 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9189 (clobber (reg:CC 17))])]
9191 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9193 (define_insn "*negdi2_1"
9194 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9195 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9196 (clobber (reg:CC 17))]
9198 && ix86_unary_operator_ok (NEG, DImode, operands)"
9202 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9203 (neg:DI (match_operand:DI 1 "general_operand" "")))
9204 (clobber (reg:CC 17))]
9209 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9210 (set (match_dup 0) (neg:SI (match_dup 2)))])
9213 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9216 (clobber (reg:CC 17))])
9219 (neg:SI (match_dup 1)))
9220 (clobber (reg:CC 17))])]
9221 "split_di (operands+1, 1, operands+2, operands+3);
9222 split_di (operands+0, 1, operands+0, operands+1);")
9224 (define_insn "*negdi2_1_rex64"
9225 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9226 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9227 (clobber (reg:CC 17))]
9228 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9230 [(set_attr "type" "negnot")
9231 (set_attr "mode" "DI")])
9233 ;; The problem with neg is that it does not perform (compare x 0),
9234 ;; it really performs (compare 0 x), which leaves us with the zero
9235 ;; flag being the only useful item.
9237 (define_insn "*negdi2_cmpz_rex64"
9239 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9241 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9242 (neg:DI (match_dup 1)))]
9243 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9245 [(set_attr "type" "negnot")
9246 (set_attr "mode" "DI")])
9249 (define_expand "negsi2"
9250 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9251 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9252 (clobber (reg:CC 17))])]
9254 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9256 (define_insn "*negsi2_1"
9257 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9258 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9259 (clobber (reg:CC 17))]
9260 "ix86_unary_operator_ok (NEG, SImode, operands)"
9262 [(set_attr "type" "negnot")
9263 (set_attr "mode" "SI")])
9265 ;; Combine is quite creative about this pattern.
9266 (define_insn "*negsi2_1_zext"
9267 [(set (match_operand:DI 0 "register_operand" "=r")
9268 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9271 (clobber (reg:CC 17))]
9272 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9274 [(set_attr "type" "negnot")
9275 (set_attr "mode" "SI")])
9277 ;; The problem with neg is that it does not perform (compare x 0),
9278 ;; it really performs (compare 0 x), which leaves us with the zero
9279 ;; flag being the only useful item.
9281 (define_insn "*negsi2_cmpz"
9283 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9285 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9286 (neg:SI (match_dup 1)))]
9287 "ix86_unary_operator_ok (NEG, SImode, operands)"
9289 [(set_attr "type" "negnot")
9290 (set_attr "mode" "SI")])
9292 (define_insn "*negsi2_cmpz_zext"
9294 (compare:CCZ (lshiftrt:DI
9296 (match_operand:DI 1 "register_operand" "0")
9300 (set (match_operand:DI 0 "register_operand" "=r")
9301 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9304 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9306 [(set_attr "type" "negnot")
9307 (set_attr "mode" "SI")])
9309 (define_expand "neghi2"
9310 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9311 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9312 (clobber (reg:CC 17))])]
9313 "TARGET_HIMODE_MATH"
9314 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9316 (define_insn "*neghi2_1"
9317 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9318 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9319 (clobber (reg:CC 17))]
9320 "ix86_unary_operator_ok (NEG, HImode, operands)"
9322 [(set_attr "type" "negnot")
9323 (set_attr "mode" "HI")])
9325 (define_insn "*neghi2_cmpz"
9327 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9329 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9330 (neg:HI (match_dup 1)))]
9331 "ix86_unary_operator_ok (NEG, HImode, operands)"
9333 [(set_attr "type" "negnot")
9334 (set_attr "mode" "HI")])
9336 (define_expand "negqi2"
9337 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9338 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9339 (clobber (reg:CC 17))])]
9340 "TARGET_QIMODE_MATH"
9341 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9343 (define_insn "*negqi2_1"
9344 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9345 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9346 (clobber (reg:CC 17))]
9347 "ix86_unary_operator_ok (NEG, QImode, operands)"
9349 [(set_attr "type" "negnot")
9350 (set_attr "mode" "QI")])
9352 (define_insn "*negqi2_cmpz"
9354 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9356 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9357 (neg:QI (match_dup 1)))]
9358 "ix86_unary_operator_ok (NEG, QImode, operands)"
9360 [(set_attr "type" "negnot")
9361 (set_attr "mode" "QI")])
9363 ;; Changing of sign for FP values is doable using integer unit too.
9365 (define_expand "negsf2"
9366 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9367 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9368 (clobber (reg:CC 17))])]
9372 /* In case operand is in memory, we will not use SSE. */
9373 if (memory_operand (operands[0], VOIDmode)
9374 && rtx_equal_p (operands[0], operands[1]))
9375 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9378 /* Using SSE is tricky, since we need bitwise negation of -0
9380 rtx reg = gen_reg_rtx (SFmode);
9381 rtx dest = operands[0];
9383 operands[1] = force_reg (SFmode, operands[1]);
9384 operands[0] = force_reg (SFmode, operands[0]);
9385 emit_move_insn (reg,
9386 gen_lowpart (SFmode,
9387 GEN_INT (trunc_int_for_mode (0x80000000,
9389 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9390 if (dest != operands[0])
9391 emit_move_insn (dest, operands[0]);
9395 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9397 (define_insn "negsf2_memory"
9398 [(set (match_operand:SF 0 "memory_operand" "=m")
9399 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9400 (clobber (reg:CC 17))]
9401 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9404 (define_insn "negsf2_ifs"
9405 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9406 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9407 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
9408 (clobber (reg:CC 17))]
9410 && (reload_in_progress || reload_completed
9411 || (register_operand (operands[0], VOIDmode)
9412 && register_operand (operands[1], VOIDmode)))"
9416 [(set (match_operand:SF 0 "memory_operand" "")
9417 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9418 (use (match_operand:SF 2 "" ""))
9419 (clobber (reg:CC 17))]
9421 [(parallel [(set (match_dup 0)
9422 (neg:SF (match_dup 1)))
9423 (clobber (reg:CC 17))])])
9426 [(set (match_operand:SF 0 "register_operand" "")
9427 (neg:SF (match_operand:SF 1 "register_operand" "")))
9428 (use (match_operand:SF 2 "" ""))
9429 (clobber (reg:CC 17))]
9430 "reload_completed && !SSE_REG_P (operands[0])"
9431 [(parallel [(set (match_dup 0)
9432 (neg:SF (match_dup 1)))
9433 (clobber (reg:CC 17))])])
9436 [(set (match_operand:SF 0 "register_operand" "")
9437 (neg:SF (match_operand:SF 1 "register_operand" "")))
9438 (use (match_operand:SF 2 "register_operand" ""))
9439 (clobber (reg:CC 17))]
9440 "reload_completed && SSE_REG_P (operands[0])"
9441 [(set (subreg:TI (match_dup 0) 0)
9442 (xor:TI (subreg:TI (match_dup 1) 0)
9443 (subreg:TI (match_dup 2) 0)))]
9446 if (operands_match_p (operands[0], operands[2]))
9450 operands[1] = operands[2];
9456 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9457 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9459 (define_insn "*negsf2_if"
9460 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9461 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9462 (clobber (reg:CC 17))]
9463 "TARGET_80387 && !TARGET_SSE
9464 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9468 [(set (match_operand:SF 0 "register_operand" "")
9469 (neg:SF (match_operand:SF 1 "register_operand" "")))
9470 (clobber (reg:CC 17))]
9471 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9473 (neg:SF (match_dup 1)))]
9477 [(set (match_operand:SF 0 "register_operand" "")
9478 (neg:SF (match_operand:SF 1 "register_operand" "")))
9479 (clobber (reg:CC 17))]
9480 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9481 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9482 (clobber (reg:CC 17))])]
9483 "operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9484 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9487 [(set (match_operand 0 "memory_operand" "")
9488 (neg (match_operand 1 "memory_operand" "")))
9489 (clobber (reg:CC 17))]
9490 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9491 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9492 (clobber (reg:CC 17))])]
9495 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9497 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9500 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9501 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9502 operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
9505 (define_expand "negdf2"
9506 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9507 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9508 (clobber (reg:CC 17))])]
9512 /* In case operand is in memory, we will not use SSE. */
9513 if (memory_operand (operands[0], VOIDmode)
9514 && rtx_equal_p (operands[0], operands[1]))
9515 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9518 /* Using SSE is tricky, since we need bitwise negation of -0
9520 rtx reg = gen_reg_rtx (DFmode);
9521 #if HOST_BITS_PER_WIDE_INT >= 64
9522 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9525 rtx imm = immed_double_const (0, 0x80000000, DImode);
9527 rtx dest = operands[0];
9529 operands[1] = force_reg (DFmode, operands[1]);
9530 operands[0] = force_reg (DFmode, operands[0]);
9531 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9532 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9533 if (dest != operands[0])
9534 emit_move_insn (dest, operands[0]);
9538 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9540 (define_insn "negdf2_memory"
9541 [(set (match_operand:DF 0 "memory_operand" "=m")
9542 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9543 (clobber (reg:CC 17))]
9544 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9547 (define_insn "negdf2_ifs"
9548 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9549 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9550 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9551 (clobber (reg:CC 17))]
9552 "TARGET_SSE2 && !TARGET_64BIT
9553 && (reload_in_progress || reload_completed
9554 || (register_operand (operands[0], VOIDmode)
9555 && register_operand (operands[1], VOIDmode)))"
9558 (define_insn "*negdf2_ifs_rex64"
9559 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9560 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9561 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9562 (clobber (reg:CC 17))]
9563 "TARGET_SSE2 && TARGET_64BIT
9564 && (reload_in_progress || reload_completed
9565 || (register_operand (operands[0], VOIDmode)
9566 && register_operand (operands[1], VOIDmode)))"
9570 [(set (match_operand:DF 0 "memory_operand" "")
9571 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9572 (use (match_operand:DF 2 "" ""))
9573 (clobber (reg:CC 17))]
9575 [(parallel [(set (match_dup 0)
9576 (neg:DF (match_dup 1)))
9577 (clobber (reg:CC 17))])])
9580 [(set (match_operand:DF 0 "register_operand" "")
9581 (neg:DF (match_operand:DF 1 "register_operand" "")))
9582 (use (match_operand:DF 2 "" ""))
9583 (clobber (reg:CC 17))]
9584 "reload_completed && !SSE_REG_P (operands[0])
9585 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9586 [(parallel [(set (match_dup 0)
9587 (neg:DF (match_dup 1)))
9588 (clobber (reg:CC 17))])])
9591 [(set (match_operand:DF 0 "register_operand" "")
9592 (neg:DF (match_operand:DF 1 "register_operand" "")))
9593 (use (match_operand:DF 2 "" ""))
9594 (clobber (reg:CC 17))]
9595 "reload_completed && GENERAL_REG_P (operands[0]) && TARGET_64BIT"
9596 [(parallel [(set (match_dup 0)
9597 (xor:DI (match_dup 1) (match_dup 2)))
9598 (clobber (reg:CC 17))])]
9599 "operands[0] = gen_lowpart (DImode, operands[0]);
9600 operands[1] = gen_lowpart (DImode, operands[1]);
9601 operands[2] = gen_lowpart (DImode, operands[2]);")
9604 [(set (match_operand:DF 0 "register_operand" "")
9605 (neg:DF (match_operand:DF 1 "register_operand" "")))
9606 (use (match_operand:DF 2 "register_operand" ""))
9607 (clobber (reg:CC 17))]
9608 "reload_completed && SSE_REG_P (operands[0])"
9609 [(set (subreg:TI (match_dup 0) 0)
9610 (xor:TI (subreg:TI (match_dup 1) 0)
9611 (subreg:TI (match_dup 2) 0)))]
9614 if (operands_match_p (operands[0], operands[2]))
9618 operands[1] = operands[2];
9623 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9624 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9626 (define_insn "*negdf2_if"
9627 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9628 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9629 (clobber (reg:CC 17))]
9630 "TARGET_80387 && !TARGET_64BIT
9631 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9634 ;; FIXME: We should to allow integer registers here. Problem is that
9635 ;; we need another scratch register to get constant from.
9636 ;; Forcing constant to mem if no register available in peep2 should be
9637 ;; safe even for PIC mode, because of RIP relative addressing.
9638 (define_insn "*negdf2_if_rex64"
9639 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9640 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9641 (clobber (reg:CC 17))]
9642 "TARGET_80387 && TARGET_64BIT
9643 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9647 [(set (match_operand:DF 0 "register_operand" "")
9648 (neg:DF (match_operand:DF 1 "register_operand" "")))
9649 (clobber (reg:CC 17))]
9650 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9652 (neg:DF (match_dup 1)))]
9656 [(set (match_operand:DF 0 "register_operand" "")
9657 (neg:DF (match_operand:DF 1 "register_operand" "")))
9658 (clobber (reg:CC 17))]
9659 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
9661 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9662 (clobber (reg:CC 17))])]
9663 "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9664 split_di (operands+0, 1, operands+2, operands+3);")
9666 (define_expand "negxf2"
9667 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9668 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9669 (clobber (reg:CC 17))])]
9670 "TARGET_80387 && !TARGET_64BIT"
9671 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9673 (define_expand "negtf2"
9674 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9675 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9676 (clobber (reg:CC 17))])]
9678 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9680 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9681 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9683 (define_insn "*negxf2_if"
9684 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9685 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9686 (clobber (reg:CC 17))]
9687 "TARGET_80387 && !TARGET_64BIT
9688 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9692 [(set (match_operand:XF 0 "register_operand" "")
9693 (neg:XF (match_operand:XF 1 "register_operand" "")))
9694 (clobber (reg:CC 17))]
9695 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9697 (neg:XF (match_dup 1)))]
9701 [(set (match_operand:XF 0 "register_operand" "")
9702 (neg:XF (match_operand:XF 1 "register_operand" "")))
9703 (clobber (reg:CC 17))]
9704 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9705 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9706 (clobber (reg:CC 17))])]
9707 "operands[1] = GEN_INT (0x8000);
9708 operands[0] = gen_rtx_REG (SImode,
9709 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9711 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9712 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9714 (define_insn "*negtf2_if"
9715 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9716 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9717 (clobber (reg:CC 17))]
9718 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9722 [(set (match_operand:TF 0 "register_operand" "")
9723 (neg:TF (match_operand:TF 1 "register_operand" "")))
9724 (clobber (reg:CC 17))]
9725 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9727 (neg:TF (match_dup 1)))]
9731 [(set (match_operand:TF 0 "register_operand" "")
9732 (neg:TF (match_operand:TF 1 "register_operand" "")))
9733 (clobber (reg:CC 17))]
9734 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9735 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9736 (clobber (reg:CC 17))])]
9737 "operands[1] = GEN_INT (0x8000);
9738 operands[0] = gen_rtx_REG (SImode,
9739 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9741 ;; Conditionize these after reload. If they matches before reload, we
9742 ;; lose the clobber and ability to use integer instructions.
9744 (define_insn "*negsf2_1"
9745 [(set (match_operand:SF 0 "register_operand" "=f")
9746 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9747 "TARGET_80387 && reload_completed"
9749 [(set_attr "type" "fsgn")
9750 (set_attr "mode" "SF")
9751 (set_attr "ppro_uops" "few")])
9753 (define_insn "*negdf2_1"
9754 [(set (match_operand:DF 0 "register_operand" "=f")
9755 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9756 "TARGET_80387 && reload_completed"
9758 [(set_attr "type" "fsgn")
9759 (set_attr "mode" "DF")
9760 (set_attr "ppro_uops" "few")])
9762 (define_insn "*negextendsfdf2"
9763 [(set (match_operand:DF 0 "register_operand" "=f")
9764 (neg:DF (float_extend:DF
9765 (match_operand:SF 1 "register_operand" "0"))))]
9768 [(set_attr "type" "fsgn")
9769 (set_attr "mode" "DF")
9770 (set_attr "ppro_uops" "few")])
9772 (define_insn "*negxf2_1"
9773 [(set (match_operand:XF 0 "register_operand" "=f")
9774 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9775 "TARGET_80387 && !TARGET_64BIT && reload_completed"
9777 [(set_attr "type" "fsgn")
9778 (set_attr "mode" "XF")
9779 (set_attr "ppro_uops" "few")])
9781 (define_insn "*negextenddfxf2"
9782 [(set (match_operand:XF 0 "register_operand" "=f")
9783 (neg:XF (float_extend:XF
9784 (match_operand:DF 1 "register_operand" "0"))))]
9785 "TARGET_80387 && !TARGET_64BIT"
9787 [(set_attr "type" "fsgn")
9788 (set_attr "mode" "XF")
9789 (set_attr "ppro_uops" "few")])
9791 (define_insn "*negextendsfxf2"
9792 [(set (match_operand:XF 0 "register_operand" "=f")
9793 (neg:XF (float_extend:XF
9794 (match_operand:SF 1 "register_operand" "0"))))]
9795 "TARGET_80387 && !TARGET_64BIT"
9797 [(set_attr "type" "fsgn")
9798 (set_attr "mode" "XF")
9799 (set_attr "ppro_uops" "few")])
9801 (define_insn "*negtf2_1"
9802 [(set (match_operand:TF 0 "register_operand" "=f")
9803 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9804 "TARGET_80387 && reload_completed"
9806 [(set_attr "type" "fsgn")
9807 (set_attr "mode" "XF")
9808 (set_attr "ppro_uops" "few")])
9810 (define_insn "*negextenddftf2"
9811 [(set (match_operand:TF 0 "register_operand" "=f")
9812 (neg:TF (float_extend:TF
9813 (match_operand:DF 1 "register_operand" "0"))))]
9816 [(set_attr "type" "fsgn")
9817 (set_attr "mode" "XF")
9818 (set_attr "ppro_uops" "few")])
9820 (define_insn "*negextendsftf2"
9821 [(set (match_operand:TF 0 "register_operand" "=f")
9822 (neg:TF (float_extend:TF
9823 (match_operand:SF 1 "register_operand" "0"))))]
9826 [(set_attr "type" "fsgn")
9827 (set_attr "mode" "XF")
9828 (set_attr "ppro_uops" "few")])
9830 ;; Absolute value instructions
9832 (define_expand "abssf2"
9833 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9834 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9835 (clobber (reg:CC 17))])]
9839 /* In case operand is in memory, we will not use SSE. */
9840 if (memory_operand (operands[0], VOIDmode)
9841 && rtx_equal_p (operands[0], operands[1]))
9842 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9845 /* Using SSE is tricky, since we need bitwise negation of -0
9847 rtx reg = gen_reg_rtx (SFmode);
9848 rtx dest = operands[0];
9850 operands[1] = force_reg (SFmode, operands[1]);
9851 operands[0] = force_reg (SFmode, operands[0]);
9852 emit_move_insn (reg,
9853 gen_lowpart (SFmode,
9854 GEN_INT (trunc_int_for_mode (0x80000000,
9856 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9857 if (dest != operands[0])
9858 emit_move_insn (dest, operands[0]);
9862 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9864 (define_insn "abssf2_memory"
9865 [(set (match_operand:SF 0 "memory_operand" "=m")
9866 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9867 (clobber (reg:CC 17))]
9868 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9871 (define_insn "abssf2_ifs"
9872 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9873 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9874 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9875 (clobber (reg:CC 17))]
9877 && (reload_in_progress || reload_completed
9878 || (register_operand (operands[0], VOIDmode)
9879 && register_operand (operands[1], VOIDmode)))"
9883 [(set (match_operand:SF 0 "memory_operand" "")
9884 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9885 (use (match_operand:SF 2 "" ""))
9886 (clobber (reg:CC 17))]
9888 [(parallel [(set (match_dup 0)
9889 (abs:SF (match_dup 1)))
9890 (clobber (reg:CC 17))])])
9893 [(set (match_operand:SF 0 "register_operand" "")
9894 (abs:SF (match_operand:SF 1 "register_operand" "")))
9895 (use (match_operand:SF 2 "" ""))
9896 (clobber (reg:CC 17))]
9897 "reload_completed && !SSE_REG_P (operands[0])"
9898 [(parallel [(set (match_dup 0)
9899 (abs:SF (match_dup 1)))
9900 (clobber (reg:CC 17))])])
9903 [(set (match_operand:SF 0 "register_operand" "")
9904 (abs:SF (match_operand:SF 1 "register_operand" "")))
9905 (use (match_operand:SF 2 "register_operand" ""))
9906 (clobber (reg:CC 17))]
9907 "reload_completed && SSE_REG_P (operands[0])"
9908 [(set (subreg:TI (match_dup 0) 0)
9909 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9910 (subreg:TI (match_dup 1) 0)))])
9912 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9913 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9915 (define_insn "*abssf2_if"
9916 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9917 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9918 (clobber (reg:CC 17))]
9919 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9923 [(set (match_operand:SF 0 "register_operand" "")
9924 (abs:SF (match_operand:SF 1 "register_operand" "")))
9925 (clobber (reg:CC 17))]
9926 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9928 (abs:SF (match_dup 1)))]
9932 [(set (match_operand:SF 0 "register_operand" "")
9933 (abs:SF (match_operand:SF 1 "register_operand" "")))
9934 (clobber (reg:CC 17))]
9935 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9936 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9937 (clobber (reg:CC 17))])]
9938 "operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
9939 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9942 [(set (match_operand 0 "memory_operand" "")
9943 (abs (match_operand 1 "memory_operand" "")))
9944 (clobber (reg:CC 17))]
9945 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9946 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9947 (clobber (reg:CC 17))])]
9950 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9952 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9955 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9956 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9957 operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
9960 (define_expand "absdf2"
9961 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9962 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9963 (clobber (reg:CC 17))])]
9967 /* In case operand is in memory, we will not use SSE. */
9968 if (memory_operand (operands[0], VOIDmode)
9969 && rtx_equal_p (operands[0], operands[1]))
9970 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9973 /* Using SSE is tricky, since we need bitwise negation of -0
9975 rtx reg = gen_reg_rtx (DFmode);
9976 #if HOST_BITS_PER_WIDE_INT >= 64
9977 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9980 rtx imm = immed_double_const (0, 0x80000000, DImode);
9982 rtx dest = operands[0];
9984 operands[1] = force_reg (DFmode, operands[1]);
9985 operands[0] = force_reg (DFmode, operands[0]);
9986 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9987 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9988 if (dest != operands[0])
9989 emit_move_insn (dest, operands[0]);
9993 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9995 (define_insn "absdf2_memory"
9996 [(set (match_operand:DF 0 "memory_operand" "=m")
9997 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9998 (clobber (reg:CC 17))]
9999 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10002 (define_insn "absdf2_ifs"
10003 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
10004 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
10005 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
10006 (clobber (reg:CC 17))]
10007 "TARGET_SSE2 && !TARGET_64BIT
10008 && (reload_in_progress || reload_completed
10009 || (register_operand (operands[0], VOIDmode)
10010 && register_operand (operands[1], VOIDmode)))"
10013 (define_insn "*absdf2_ifs_rex64"
10014 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
10015 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
10016 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
10017 (clobber (reg:CC 17))]
10018 "TARGET_SSE2 && TARGET_64BIT
10019 && (reload_in_progress || reload_completed
10020 || (register_operand (operands[0], VOIDmode)
10021 && register_operand (operands[1], VOIDmode)))"
10025 [(set (match_operand:DF 0 "memory_operand" "")
10026 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10027 (use (match_operand:DF 2 "" ""))
10028 (clobber (reg:CC 17))]
10030 [(parallel [(set (match_dup 0)
10031 (abs:DF (match_dup 1)))
10032 (clobber (reg:CC 17))])])
10035 [(set (match_operand:DF 0 "register_operand" "")
10036 (abs:DF (match_operand:DF 1 "register_operand" "")))
10037 (use (match_operand:DF 2 "" ""))
10038 (clobber (reg:CC 17))]
10039 "reload_completed && !SSE_REG_P (operands[0])"
10040 [(parallel [(set (match_dup 0)
10041 (abs:DF (match_dup 1)))
10042 (clobber (reg:CC 17))])])
10045 [(set (match_operand:DF 0 "register_operand" "")
10046 (abs:DF (match_operand:DF 1 "register_operand" "")))
10047 (use (match_operand:DF 2 "register_operand" ""))
10048 (clobber (reg:CC 17))]
10049 "reload_completed && SSE_REG_P (operands[0])"
10050 [(set (subreg:TI (match_dup 0) 0)
10051 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
10052 (subreg:TI (match_dup 1) 0)))])
10055 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10056 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10058 (define_insn "*absdf2_if"
10059 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10060 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10061 (clobber (reg:CC 17))]
10062 "TARGET_80387 && !TARGET_64BIT
10063 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10066 ;; FIXME: We should to allow integer registers here. Problem is that
10067 ;; we need another scratch register to get constant from.
10068 ;; Forcing constant to mem if no register available in peep2 should be
10069 ;; safe even for PIC mode, because of RIP relative addressing.
10070 (define_insn "*absdf2_if_rex64"
10071 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10072 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10073 (clobber (reg:CC 17))]
10074 "TARGET_80387 && TARGET_64BIT
10075 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10079 [(set (match_operand:DF 0 "register_operand" "")
10080 (abs:DF (match_operand:DF 1 "register_operand" "")))
10081 (clobber (reg:CC 17))]
10082 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10083 [(set (match_dup 0)
10084 (abs:DF (match_dup 1)))]
10088 [(set (match_operand:DF 0 "register_operand" "")
10089 (abs:DF (match_operand:DF 1 "register_operand" "")))
10090 (clobber (reg:CC 17))]
10091 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
10093 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10094 (clobber (reg:CC 17))])]
10095 "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
10096 split_di (operands+0, 1, operands+2, operands+3);")
10098 (define_expand "absxf2"
10099 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10100 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10101 (clobber (reg:CC 17))])]
10102 "TARGET_80387 && !TARGET_64BIT"
10103 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10105 (define_expand "abstf2"
10106 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10107 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10108 (clobber (reg:CC 17))])]
10110 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10112 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10113 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10115 (define_insn "*absxf2_if"
10116 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10117 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10118 (clobber (reg:CC 17))]
10119 "TARGET_80387 && !TARGET_64BIT
10120 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10124 [(set (match_operand:XF 0 "register_operand" "")
10125 (abs:XF (match_operand:XF 1 "register_operand" "")))
10126 (clobber (reg:CC 17))]
10127 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10128 [(set (match_dup 0)
10129 (abs:XF (match_dup 1)))]
10133 [(set (match_operand:XF 0 "register_operand" "")
10134 (abs:XF (match_operand:XF 1 "register_operand" "")))
10135 (clobber (reg:CC 17))]
10136 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10137 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10138 (clobber (reg:CC 17))])]
10139 "operands[1] = GEN_INT (~0x8000);
10140 operands[0] = gen_rtx_REG (SImode,
10141 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10143 (define_insn "*abstf2_if"
10144 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10145 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10146 (clobber (reg:CC 17))]
10147 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10151 [(set (match_operand:TF 0 "register_operand" "")
10152 (abs:TF (match_operand:TF 1 "register_operand" "")))
10153 (clobber (reg:CC 17))]
10154 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10155 [(set (match_dup 0)
10156 (abs:TF (match_dup 1)))]
10160 [(set (match_operand:TF 0 "register_operand" "")
10161 (abs:TF (match_operand:TF 1 "register_operand" "")))
10162 (clobber (reg:CC 17))]
10163 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10164 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10165 (clobber (reg:CC 17))])]
10166 "operands[1] = GEN_INT (~0x8000);
10167 operands[0] = gen_rtx_REG (SImode,
10168 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10170 (define_insn "*abssf2_1"
10171 [(set (match_operand:SF 0 "register_operand" "=f")
10172 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10173 "TARGET_80387 && reload_completed"
10175 [(set_attr "type" "fsgn")
10176 (set_attr "mode" "SF")])
10178 (define_insn "*absdf2_1"
10179 [(set (match_operand:DF 0 "register_operand" "=f")
10180 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10181 "TARGET_80387 && reload_completed"
10183 [(set_attr "type" "fsgn")
10184 (set_attr "mode" "DF")])
10186 (define_insn "*absextendsfdf2"
10187 [(set (match_operand:DF 0 "register_operand" "=f")
10188 (abs:DF (float_extend:DF
10189 (match_operand:SF 1 "register_operand" "0"))))]
10192 [(set_attr "type" "fsgn")
10193 (set_attr "mode" "DF")])
10195 (define_insn "*absxf2_1"
10196 [(set (match_operand:XF 0 "register_operand" "=f")
10197 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10198 "TARGET_80387 && !TARGET_64BIT && reload_completed"
10200 [(set_attr "type" "fsgn")
10201 (set_attr "mode" "DF")])
10203 (define_insn "*absextenddfxf2"
10204 [(set (match_operand:XF 0 "register_operand" "=f")
10205 (abs:XF (float_extend:XF
10206 (match_operand:DF 1 "register_operand" "0"))))]
10207 "TARGET_80387 && !TARGET_64BIT"
10209 [(set_attr "type" "fsgn")
10210 (set_attr "mode" "XF")])
10212 (define_insn "*absextendsfxf2"
10213 [(set (match_operand:XF 0 "register_operand" "=f")
10214 (abs:XF (float_extend:XF
10215 (match_operand:SF 1 "register_operand" "0"))))]
10216 "TARGET_80387 && !TARGET_64BIT"
10218 [(set_attr "type" "fsgn")
10219 (set_attr "mode" "XF")])
10221 (define_insn "*abstf2_1"
10222 [(set (match_operand:TF 0 "register_operand" "=f")
10223 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10224 "TARGET_80387 && reload_completed"
10226 [(set_attr "type" "fsgn")
10227 (set_attr "mode" "DF")])
10229 (define_insn "*absextenddftf2"
10230 [(set (match_operand:TF 0 "register_operand" "=f")
10231 (abs:TF (float_extend:TF
10232 (match_operand:DF 1 "register_operand" "0"))))]
10235 [(set_attr "type" "fsgn")
10236 (set_attr "mode" "XF")])
10238 (define_insn "*absextendsftf2"
10239 [(set (match_operand:TF 0 "register_operand" "=f")
10240 (abs:TF (float_extend:TF
10241 (match_operand:SF 1 "register_operand" "0"))))]
10244 [(set_attr "type" "fsgn")
10245 (set_attr "mode" "XF")])
10247 ;; One complement instructions
10249 (define_expand "one_cmpldi2"
10250 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10251 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10253 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10255 (define_insn "*one_cmpldi2_1_rex64"
10256 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10257 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10258 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10260 [(set_attr "type" "negnot")
10261 (set_attr "mode" "DI")])
10263 (define_insn "*one_cmpldi2_2_rex64"
10265 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10267 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10268 (not:DI (match_dup 1)))]
10269 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10270 && ix86_unary_operator_ok (NOT, DImode, operands)"
10272 [(set_attr "type" "alu1")
10273 (set_attr "mode" "DI")])
10277 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10279 (set (match_operand:DI 0 "nonimmediate_operand" "")
10280 (not:DI (match_dup 1)))]
10281 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10282 [(parallel [(set (reg:CCNO 17)
10283 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10286 (xor:DI (match_dup 1) (const_int -1)))])]
10289 (define_expand "one_cmplsi2"
10290 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10291 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10293 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10295 (define_insn "*one_cmplsi2_1"
10296 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10297 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10298 "ix86_unary_operator_ok (NOT, SImode, operands)"
10300 [(set_attr "type" "negnot")
10301 (set_attr "mode" "SI")])
10303 ;; ??? Currently never generated - xor is used instead.
10304 (define_insn "*one_cmplsi2_1_zext"
10305 [(set (match_operand:DI 0 "register_operand" "=r")
10306 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10307 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10309 [(set_attr "type" "negnot")
10310 (set_attr "mode" "SI")])
10312 (define_insn "*one_cmplsi2_2"
10314 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10316 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10317 (not:SI (match_dup 1)))]
10318 "ix86_match_ccmode (insn, CCNOmode)
10319 && ix86_unary_operator_ok (NOT, SImode, operands)"
10321 [(set_attr "type" "alu1")
10322 (set_attr "mode" "SI")])
10326 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10328 (set (match_operand:SI 0 "nonimmediate_operand" "")
10329 (not:SI (match_dup 1)))]
10330 "ix86_match_ccmode (insn, CCNOmode)"
10331 [(parallel [(set (reg:CCNO 17)
10332 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10335 (xor:SI (match_dup 1) (const_int -1)))])]
10338 ;; ??? Currently never generated - xor is used instead.
10339 (define_insn "*one_cmplsi2_2_zext"
10341 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10343 (set (match_operand:DI 0 "register_operand" "=r")
10344 (zero_extend:DI (not:SI (match_dup 1))))]
10345 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10346 && ix86_unary_operator_ok (NOT, SImode, operands)"
10348 [(set_attr "type" "alu1")
10349 (set_attr "mode" "SI")])
10353 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10355 (set (match_operand:DI 0 "register_operand" "")
10356 (zero_extend:DI (not:SI (match_dup 1))))]
10357 "ix86_match_ccmode (insn, CCNOmode)"
10358 [(parallel [(set (reg:CCNO 17)
10359 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10362 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10365 (define_expand "one_cmplhi2"
10366 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10367 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10368 "TARGET_HIMODE_MATH"
10369 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10371 (define_insn "*one_cmplhi2_1"
10372 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10373 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10374 "ix86_unary_operator_ok (NOT, HImode, operands)"
10376 [(set_attr "type" "negnot")
10377 (set_attr "mode" "HI")])
10379 (define_insn "*one_cmplhi2_2"
10381 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10383 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10384 (not:HI (match_dup 1)))]
10385 "ix86_match_ccmode (insn, CCNOmode)
10386 && ix86_unary_operator_ok (NEG, HImode, operands)"
10388 [(set_attr "type" "alu1")
10389 (set_attr "mode" "HI")])
10393 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10395 (set (match_operand:HI 0 "nonimmediate_operand" "")
10396 (not:HI (match_dup 1)))]
10397 "ix86_match_ccmode (insn, CCNOmode)"
10398 [(parallel [(set (reg:CCNO 17)
10399 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10402 (xor:HI (match_dup 1) (const_int -1)))])]
10405 ;; %%% Potential partial reg stall on alternative 1. What to do?
10406 (define_expand "one_cmplqi2"
10407 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10408 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10409 "TARGET_QIMODE_MATH"
10410 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10412 (define_insn "*one_cmplqi2_1"
10413 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10414 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10415 "ix86_unary_operator_ok (NOT, QImode, operands)"
10419 [(set_attr "type" "negnot")
10420 (set_attr "mode" "QI,SI")])
10422 (define_insn "*one_cmplqi2_2"
10424 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10426 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10427 (not:QI (match_dup 1)))]
10428 "ix86_match_ccmode (insn, CCNOmode)
10429 && ix86_unary_operator_ok (NOT, QImode, operands)"
10431 [(set_attr "type" "alu1")
10432 (set_attr "mode" "QI")])
10436 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10438 (set (match_operand:QI 0 "nonimmediate_operand" "")
10439 (not:QI (match_dup 1)))]
10440 "ix86_match_ccmode (insn, CCNOmode)"
10441 [(parallel [(set (reg:CCNO 17)
10442 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10445 (xor:QI (match_dup 1) (const_int -1)))])]
10448 ;; Arithmetic shift instructions
10450 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10451 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10452 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10453 ;; from the assembler input.
10455 ;; This instruction shifts the target reg/mem as usual, but instead of
10456 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10457 ;; is a left shift double, bits are taken from the high order bits of
10458 ;; reg, else if the insn is a shift right double, bits are taken from the
10459 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10460 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10462 ;; Since sh[lr]d does not change the `reg' operand, that is done
10463 ;; separately, making all shifts emit pairs of shift double and normal
10464 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10465 ;; support a 63 bit shift, each shift where the count is in a reg expands
10466 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10468 ;; If the shift count is a constant, we need never emit more than one
10469 ;; shift pair, instead using moves and sign extension for counts greater
10472 (define_expand "ashldi3"
10473 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10474 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10475 (match_operand:QI 2 "nonmemory_operand" "")))
10476 (clobber (reg:CC 17))])]
10480 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10482 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10485 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10489 (define_insn "*ashldi3_1_rex64"
10490 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10491 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10492 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10493 (clobber (reg:CC 17))]
10494 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10497 switch (get_attr_type (insn))
10500 if (operands[2] != const1_rtx)
10502 if (!rtx_equal_p (operands[0], operands[1]))
10504 return \"add{q}\\t{%0, %0|%0, %0}\";
10507 if (GET_CODE (operands[2]) != CONST_INT
10508 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10510 operands[1] = gen_rtx_MULT (DImode, operands[1],
10511 GEN_INT (1 << INTVAL (operands[2])));
10512 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
10515 if (REG_P (operands[2]))
10516 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10517 else if (GET_CODE (operands[2]) == CONST_INT
10518 && INTVAL (operands[2]) == 1
10519 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10520 return \"sal{q}\\t%0\";
10522 return \"sal{q}\\t{%2, %0|%0, %2}\";
10525 [(set (attr "type")
10526 (cond [(eq_attr "alternative" "1")
10527 (const_string "lea")
10528 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10530 (match_operand 0 "register_operand" ""))
10531 (match_operand 2 "const1_operand" ""))
10532 (const_string "alu")
10534 (const_string "ishift")))
10535 (set_attr "mode" "DI")])
10537 ;; Convert lea to the lea pattern to avoid flags dependency.
10539 [(set (match_operand:DI 0 "register_operand" "")
10540 (ashift:DI (match_operand:DI 1 "register_operand" "")
10541 (match_operand:QI 2 "immediate_operand" "")))
10542 (clobber (reg:CC 17))]
10545 && true_regnum (operands[0]) != true_regnum (operands[1])"
10546 [(set (match_dup 0)
10547 (mult:DI (match_dup 1)
10549 "operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10552 ;; This pattern can't accept a variable shift count, since shifts by
10553 ;; zero don't affect the flags. We assume that shifts by constant
10554 ;; zero are optimized away.
10555 (define_insn "*ashldi3_cmp_rex64"
10558 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10559 (match_operand:QI 2 "immediate_operand" "e"))
10561 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10562 (ashift:DI (match_dup 1) (match_dup 2)))]
10563 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10564 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10567 switch (get_attr_type (insn))
10570 if (operands[2] != const1_rtx)
10572 return \"add{q}\\t{%0, %0|%0, %0}\";
10575 if (REG_P (operands[2]))
10576 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10577 else if (GET_CODE (operands[2]) == CONST_INT
10578 && INTVAL (operands[2]) == 1
10579 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10580 return \"sal{q}\\t%0\";
10582 return \"sal{q}\\t{%2, %0|%0, %2}\";
10585 [(set (attr "type")
10586 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10588 (match_operand 0 "register_operand" ""))
10589 (match_operand 2 "const1_operand" ""))
10590 (const_string "alu")
10592 (const_string "ishift")))
10593 (set_attr "mode" "DI")])
10595 (define_insn "ashldi3_1"
10596 [(set (match_operand:DI 0 "register_operand" "=r")
10597 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10598 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10599 (clobber (match_scratch:SI 3 "=&r"))
10600 (clobber (reg:CC 17))]
10601 "!TARGET_64BIT && TARGET_CMOVE"
10603 [(set_attr "type" "multi")])
10605 (define_insn "*ashldi3_2"
10606 [(set (match_operand:DI 0 "register_operand" "=r")
10607 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10608 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10609 (clobber (reg:CC 17))]
10612 [(set_attr "type" "multi")])
10615 [(set (match_operand:DI 0 "register_operand" "")
10616 (ashift:DI (match_operand:DI 1 "register_operand" "")
10617 (match_operand:QI 2 "nonmemory_operand" "")))
10618 (clobber (match_scratch:SI 3 ""))
10619 (clobber (reg:CC 17))]
10620 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10622 "ix86_split_ashldi (operands, operands[3]); DONE;")
10625 [(set (match_operand:DI 0 "register_operand" "")
10626 (ashift:DI (match_operand:DI 1 "register_operand" "")
10627 (match_operand:QI 2 "nonmemory_operand" "")))
10628 (clobber (reg:CC 17))]
10629 "!TARGET_64BIT && reload_completed"
10631 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10633 (define_insn "x86_shld_1"
10634 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10635 (ior:SI (ashift:SI (match_dup 0)
10636 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10637 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10638 (minus:QI (const_int 32) (match_dup 2)))))
10639 (clobber (reg:CC 17))]
10642 shld{l}\\t{%2, %1, %0|%0, %1, %2}
10643 shld{l}\\t{%s2%1, %0|%0, %1, %2}"
10644 [(set_attr "type" "ishift")
10645 (set_attr "prefix_0f" "1")
10646 (set_attr "mode" "SI")
10647 (set_attr "pent_pair" "np")
10648 (set_attr "athlon_decode" "vector")
10649 (set_attr "ppro_uops" "few")])
10651 (define_expand "x86_shift_adj_1"
10653 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10656 (set (match_operand:SI 0 "register_operand" "")
10657 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10658 (match_operand:SI 1 "register_operand" "")
10661 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10662 (match_operand:SI 3 "register_operand" "r")
10667 (define_expand "x86_shift_adj_2"
10668 [(use (match_operand:SI 0 "register_operand" ""))
10669 (use (match_operand:SI 1 "register_operand" ""))
10670 (use (match_operand:QI 2 "register_operand" ""))]
10674 rtx label = gen_label_rtx ();
10677 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10679 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10680 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10681 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10682 gen_rtx_LABEL_REF (VOIDmode, label),
10684 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10685 JUMP_LABEL (tmp) = label;
10687 emit_move_insn (operands[0], operands[1]);
10688 emit_move_insn (operands[1], const0_rtx);
10690 emit_label (label);
10691 LABEL_NUSES (label) = 1;
10696 (define_expand "ashlsi3"
10697 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10698 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10699 (match_operand:QI 2 "nonmemory_operand" "")))
10700 (clobber (reg:CC 17))]
10702 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10704 (define_insn "*ashlsi3_1"
10705 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10706 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10707 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10708 (clobber (reg:CC 17))]
10709 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10712 switch (get_attr_type (insn))
10715 if (operands[2] != const1_rtx)
10717 if (!rtx_equal_p (operands[0], operands[1]))
10719 return \"add{l}\\t{%0, %0|%0, %0}\";
10725 if (REG_P (operands[2]))
10726 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10727 else if (GET_CODE (operands[2]) == CONST_INT
10728 && INTVAL (operands[2]) == 1
10729 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10730 return \"sal{l}\\t%0\";
10732 return \"sal{l}\\t{%2, %0|%0, %2}\";
10735 [(set (attr "type")
10736 (cond [(eq_attr "alternative" "1")
10737 (const_string "lea")
10738 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10740 (match_operand 0 "register_operand" ""))
10741 (match_operand 2 "const1_operand" ""))
10742 (const_string "alu")
10744 (const_string "ishift")))
10745 (set_attr "mode" "SI")])
10747 ;; Convert lea to the lea pattern to avoid flags dependency.
10749 [(set (match_operand 0 "register_operand" "")
10750 (ashift (match_operand 1 "register_operand" "")
10751 (match_operand:QI 2 "const_int_operand" "")))
10752 (clobber (reg:CC 17))]
10754 && true_regnum (operands[0]) != true_regnum (operands[1])"
10759 operands[0] = gen_lowpart (SImode, operands[0]);
10760 operands[1] = gen_lowpart (Pmode, operands[1]);
10761 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10763 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10764 if (Pmode != SImode)
10765 pat = gen_rtx_SUBREG (SImode, pat, 0);
10766 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10770 (define_insn "*ashlsi3_1_zext"
10771 [(set (match_operand:DI 0 "register_operand" "=r,r")
10772 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10773 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10774 (clobber (reg:CC 17))]
10775 "ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
10778 switch (get_attr_type (insn))
10781 if (operands[2] != const1_rtx)
10783 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10789 if (REG_P (operands[2]))
10790 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10791 else if (GET_CODE (operands[2]) == CONST_INT
10792 && INTVAL (operands[2]) == 1
10793 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10794 return \"sal{l}\\t%k0\";
10796 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10799 [(set (attr "type")
10800 (cond [(eq_attr "alternative" "1")
10801 (const_string "lea")
10802 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10804 (match_operand 2 "const1_operand" ""))
10805 (const_string "alu")
10807 (const_string "ishift")))
10808 (set_attr "mode" "SI")])
10810 ;; Convert lea to the lea pattern to avoid flags dependency.
10812 [(set (match_operand:DI 0 "register_operand" "")
10813 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10814 (match_operand:QI 2 "const_int_operand" ""))))
10815 (clobber (reg:CC 17))]
10817 && true_regnum (operands[0]) != true_regnum (operands[1])"
10818 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10821 operands[1] = gen_lowpart (Pmode, operands[1]);
10822 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10826 ;; This pattern can't accept a variable shift count, since shifts by
10827 ;; zero don't affect the flags. We assume that shifts by constant
10828 ;; zero are optimized away.
10829 (define_insn "*ashlsi3_cmp"
10832 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10833 (match_operand:QI 2 "immediate_operand" "I"))
10835 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10836 (ashift:SI (match_dup 1) (match_dup 2)))]
10837 "ix86_match_ccmode (insn, CCGOCmode)
10838 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10841 switch (get_attr_type (insn))
10844 if (operands[2] != const1_rtx)
10846 return \"add{l}\\t{%0, %0|%0, %0}\";
10849 if (REG_P (operands[2]))
10850 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10851 else if (GET_CODE (operands[2]) == CONST_INT
10852 && INTVAL (operands[2]) == 1
10853 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10854 return \"sal{l}\\t%0\";
10856 return \"sal{l}\\t{%2, %0|%0, %2}\";
10859 [(set (attr "type")
10860 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10862 (match_operand 0 "register_operand" ""))
10863 (match_operand 2 "const1_operand" ""))
10864 (const_string "alu")
10866 (const_string "ishift")))
10867 (set_attr "mode" "SI")])
10869 (define_insn "*ashlsi3_cmp_zext"
10872 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10873 (match_operand:QI 2 "immediate_operand" "I"))
10875 (set (match_operand:DI 0 "register_operand" "=r")
10876 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10877 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10878 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10881 switch (get_attr_type (insn))
10884 if (operands[2] != const1_rtx)
10886 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10889 if (REG_P (operands[2]))
10890 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10891 else if (GET_CODE (operands[2]) == CONST_INT
10892 && INTVAL (operands[2]) == 1
10893 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10894 return \"sal{l}\\t%k0\";
10896 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10899 [(set (attr "type")
10900 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10902 (match_operand 2 "const1_operand" ""))
10903 (const_string "alu")
10905 (const_string "ishift")))
10906 (set_attr "mode" "SI")])
10908 (define_expand "ashlhi3"
10909 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10910 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10911 (match_operand:QI 2 "nonmemory_operand" "")))
10912 (clobber (reg:CC 17))]
10913 "TARGET_HIMODE_MATH"
10914 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10916 (define_insn "*ashlhi3_1_lea"
10917 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10918 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10919 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10920 (clobber (reg:CC 17))]
10921 "!TARGET_PARTIAL_REG_STALL
10922 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10925 switch (get_attr_type (insn))
10930 if (operands[2] != const1_rtx)
10932 return \"add{w}\\t{%0, %0|%0, %0}\";
10935 if (REG_P (operands[2]))
10936 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10937 else if (GET_CODE (operands[2]) == CONST_INT
10938 && INTVAL (operands[2]) == 1
10939 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10940 return \"sal{w}\\t%0\";
10942 return \"sal{w}\\t{%2, %0|%0, %2}\";
10945 [(set (attr "type")
10946 (cond [(eq_attr "alternative" "1")
10947 (const_string "lea")
10948 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10950 (match_operand 0 "register_operand" ""))
10951 (match_operand 2 "const1_operand" ""))
10952 (const_string "alu")
10954 (const_string "ishift")))
10955 (set_attr "mode" "HI,SI")])
10957 (define_insn "*ashlhi3_1"
10958 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10959 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10960 (match_operand:QI 2 "nonmemory_operand" "cI")))
10961 (clobber (reg:CC 17))]
10962 "TARGET_PARTIAL_REG_STALL
10963 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10966 switch (get_attr_type (insn))
10969 if (operands[2] != const1_rtx)
10971 return \"add{w}\\t{%0, %0|%0, %0}\";
10974 if (REG_P (operands[2]))
10975 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10976 else if (GET_CODE (operands[2]) == CONST_INT
10977 && INTVAL (operands[2]) == 1
10978 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10979 return \"sal{w}\\t%0\";
10981 return \"sal{w}\\t{%2, %0|%0, %2}\";
10984 [(set (attr "type")
10985 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10987 (match_operand 0 "register_operand" ""))
10988 (match_operand 2 "const1_operand" ""))
10989 (const_string "alu")
10991 (const_string "ishift")))
10992 (set_attr "mode" "HI")])
10994 ;; This pattern can't accept a variable shift count, since shifts by
10995 ;; zero don't affect the flags. We assume that shifts by constant
10996 ;; zero are optimized away.
10997 (define_insn "*ashlhi3_cmp"
11000 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11001 (match_operand:QI 2 "immediate_operand" "I"))
11003 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11004 (ashift:HI (match_dup 1) (match_dup 2)))]
11005 "ix86_match_ccmode (insn, CCGOCmode)
11006 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11009 switch (get_attr_type (insn))
11012 if (operands[2] != const1_rtx)
11014 return \"add{w}\\t{%0, %0|%0, %0}\";
11017 if (REG_P (operands[2]))
11018 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
11019 else if (GET_CODE (operands[2]) == CONST_INT
11020 && INTVAL (operands[2]) == 1
11021 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11022 return \"sal{w}\\t%0\";
11024 return \"sal{w}\\t{%2, %0|%0, %2}\";
11027 [(set (attr "type")
11028 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11030 (match_operand 0 "register_operand" ""))
11031 (match_operand 2 "const1_operand" ""))
11032 (const_string "alu")
11034 (const_string "ishift")))
11035 (set_attr "mode" "HI")])
11037 (define_expand "ashlqi3"
11038 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11039 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11040 (match_operand:QI 2 "nonmemory_operand" "")))
11041 (clobber (reg:CC 17))]
11042 "TARGET_QIMODE_MATH"
11043 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11045 ;; %%% Potential partial reg stall on alternative 2. What to do?
11047 (define_insn "*ashlqi3_1_lea"
11048 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11049 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11050 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11051 (clobber (reg:CC 17))]
11052 "!TARGET_PARTIAL_REG_STALL
11053 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11056 switch (get_attr_type (insn))
11061 if (operands[2] != const1_rtx)
11063 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11064 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
11066 return \"add{b}\\t{%0, %0|%0, %0}\";
11069 if (REG_P (operands[2]))
11071 if (get_attr_mode (insn) == MODE_SI)
11072 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
11074 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11076 else if (GET_CODE (operands[2]) == CONST_INT
11077 && INTVAL (operands[2]) == 1
11078 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11080 if (get_attr_mode (insn) == MODE_SI)
11081 return \"sal{l}\\t%0\";
11083 return \"sal{b}\\t%0\";
11087 if (get_attr_mode (insn) == MODE_SI)
11088 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
11090 return \"sal{b}\\t{%2, %0|%0, %2}\";
11094 [(set (attr "type")
11095 (cond [(eq_attr "alternative" "2")
11096 (const_string "lea")
11097 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11099 (match_operand 0 "register_operand" ""))
11100 (match_operand 2 "const1_operand" ""))
11101 (const_string "alu")
11103 (const_string "ishift")))
11104 (set_attr "mode" "QI,SI,SI")])
11106 (define_insn "*ashlqi3_1"
11107 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11108 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11109 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11110 (clobber (reg:CC 17))]
11111 "TARGET_PARTIAL_REG_STALL
11112 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11115 switch (get_attr_type (insn))
11118 if (operands[2] != const1_rtx)
11120 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11121 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
11123 return \"add{b}\\t{%0, %0|%0, %0}\";
11126 if (REG_P (operands[2]))
11128 if (get_attr_mode (insn) == MODE_SI)
11129 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
11131 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11133 else if (GET_CODE (operands[2]) == CONST_INT
11134 && INTVAL (operands[2]) == 1
11135 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11137 if (get_attr_mode (insn) == MODE_SI)
11138 return \"sal{l}\\t%0\";
11140 return \"sal{b}\\t%0\";
11144 if (get_attr_mode (insn) == MODE_SI)
11145 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
11147 return \"sal{b}\\t{%2, %0|%0, %2}\";
11151 [(set (attr "type")
11152 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11154 (match_operand 0 "register_operand" ""))
11155 (match_operand 2 "const1_operand" ""))
11156 (const_string "alu")
11158 (const_string "ishift")))
11159 (set_attr "mode" "QI,SI")])
11161 ;; This pattern can't accept a variable shift count, since shifts by
11162 ;; zero don't affect the flags. We assume that shifts by constant
11163 ;; zero are optimized away.
11164 (define_insn "*ashlqi3_cmp"
11167 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11168 (match_operand:QI 2 "immediate_operand" "I"))
11170 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11171 (ashift:QI (match_dup 1) (match_dup 2)))]
11172 "ix86_match_ccmode (insn, CCGOCmode)
11173 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11176 switch (get_attr_type (insn))
11179 if (operands[2] != const1_rtx)
11181 return \"add{b}\\t{%0, %0|%0, %0}\";
11184 if (REG_P (operands[2]))
11185 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11186 else if (GET_CODE (operands[2]) == CONST_INT
11187 && INTVAL (operands[2]) == 1
11188 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11189 return \"sal{b}\\t%0\";
11191 return \"sal{b}\\t{%2, %0|%0, %2}\";
11194 [(set (attr "type")
11195 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11197 (match_operand 0 "register_operand" ""))
11198 (match_operand 2 "const1_operand" ""))
11199 (const_string "alu")
11201 (const_string "ishift")))
11202 (set_attr "mode" "QI")])
11204 ;; See comment above `ashldi3' about how this works.
11206 (define_expand "ashrdi3"
11207 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11208 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11209 (match_operand:QI 2 "nonmemory_operand" "")))
11210 (clobber (reg:CC 17))])]
11214 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11216 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11219 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11223 (define_insn "ashrdi3_63_rex64"
11224 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11225 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11226 (match_operand:DI 2 "const_int_operand" "i,i")))
11227 (clobber (reg:CC 17))]
11228 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11229 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11232 sar{q}\\t{%2, %0|%0, %2}"
11233 [(set_attr "type" "imovx,ishift")
11234 (set_attr "prefix_0f" "0,*")
11235 (set_attr "length_immediate" "0,*")
11236 (set_attr "modrm" "0,1")
11237 (set_attr "mode" "DI")])
11239 (define_insn "*ashrdi3_1_one_bit_rex64"
11240 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11241 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11242 (match_operand:QI 2 "const_int_1_operand" "")))
11243 (clobber (reg:CC 17))]
11244 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11245 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11247 [(set_attr "type" "ishift")
11248 (set (attr "length")
11249 (if_then_else (match_operand:DI 0 "register_operand" "")
11251 (const_string "*")))])
11253 (define_insn "*ashrdi3_1_rex64"
11254 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11255 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11256 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11257 (clobber (reg:CC 17))]
11258 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11260 sar{q}\\t{%2, %0|%0, %2}
11261 sar{q}\\t{%b2, %0|%0, %b2}"
11262 [(set_attr "type" "ishift")
11263 (set_attr "mode" "DI")])
11265 ;; This pattern can't accept a variable shift count, since shifts by
11266 ;; zero don't affect the flags. We assume that shifts by constant
11267 ;; zero are optimized away.
11268 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11271 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11272 (match_operand:QI 2 "const_int_1_operand" ""))
11274 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11275 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11276 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11277 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11278 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11280 [(set_attr "type" "ishift")
11281 (set (attr "length")
11282 (if_then_else (match_operand:DI 0 "register_operand" "")
11284 (const_string "*")))])
11286 ;; This pattern can't accept a variable shift count, since shifts by
11287 ;; zero don't affect the flags. We assume that shifts by constant
11288 ;; zero are optimized away.
11289 (define_insn "*ashrdi3_cmp_rex64"
11292 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11293 (match_operand:QI 2 "const_int_operand" "n"))
11295 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11296 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11297 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11298 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11299 "sar{q}\\t{%2, %0|%0, %2}"
11300 [(set_attr "type" "ishift")
11301 (set_attr "mode" "DI")])
11304 (define_insn "ashrdi3_1"
11305 [(set (match_operand:DI 0 "register_operand" "=r")
11306 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11307 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11308 (clobber (match_scratch:SI 3 "=&r"))
11309 (clobber (reg:CC 17))]
11310 "!TARGET_64BIT && TARGET_CMOVE"
11312 [(set_attr "type" "multi")])
11314 (define_insn "*ashrdi3_2"
11315 [(set (match_operand:DI 0 "register_operand" "=r")
11316 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11317 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11318 (clobber (reg:CC 17))]
11321 [(set_attr "type" "multi")])
11324 [(set (match_operand:DI 0 "register_operand" "")
11325 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11326 (match_operand:QI 2 "nonmemory_operand" "")))
11327 (clobber (match_scratch:SI 3 ""))
11328 (clobber (reg:CC 17))]
11329 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11331 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11334 [(set (match_operand:DI 0 "register_operand" "")
11335 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11336 (match_operand:QI 2 "nonmemory_operand" "")))
11337 (clobber (reg:CC 17))]
11338 "!TARGET_64BIT && reload_completed"
11340 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11342 (define_insn "x86_shrd_1"
11343 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11344 (ior:SI (ashiftrt:SI (match_dup 0)
11345 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11346 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11347 (minus:QI (const_int 32) (match_dup 2)))))
11348 (clobber (reg:CC 17))]
11351 shrd{l}\\t{%2, %1, %0|%0, %1, %2}
11352 shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
11353 [(set_attr "type" "ishift")
11354 (set_attr "prefix_0f" "1")
11355 (set_attr "pent_pair" "np")
11356 (set_attr "ppro_uops" "few")
11357 (set_attr "mode" "SI")])
11359 (define_expand "x86_shift_adj_3"
11360 [(use (match_operand:SI 0 "register_operand" ""))
11361 (use (match_operand:SI 1 "register_operand" ""))
11362 (use (match_operand:QI 2 "register_operand" ""))]
11366 rtx label = gen_label_rtx ();
11369 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11371 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11372 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11373 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11374 gen_rtx_LABEL_REF (VOIDmode, label),
11376 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11377 JUMP_LABEL (tmp) = label;
11379 emit_move_insn (operands[0], operands[1]);
11380 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11382 emit_label (label);
11383 LABEL_NUSES (label) = 1;
11388 (define_insn "ashrsi3_31"
11389 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11390 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11391 (match_operand:SI 2 "const_int_operand" "i,i")))
11392 (clobber (reg:CC 17))]
11393 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11394 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11397 sar{l}\\t{%2, %0|%0, %2}"
11398 [(set_attr "type" "imovx,ishift")
11399 (set_attr "prefix_0f" "0,*")
11400 (set_attr "length_immediate" "0,*")
11401 (set_attr "modrm" "0,1")
11402 (set_attr "mode" "SI")])
11404 (define_insn "*ashrsi3_31_zext"
11405 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11406 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11407 (match_operand:SI 2 "const_int_operand" "i,i"))))
11408 (clobber (reg:CC 17))]
11409 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11410 && TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11413 sar{l}\\t{%2, %k0|%k0, %2}"
11414 [(set_attr "type" "imovx,ishift")
11415 (set_attr "prefix_0f" "0,*")
11416 (set_attr "length_immediate" "0,*")
11417 (set_attr "modrm" "0,1")
11418 (set_attr "mode" "SI")])
11420 (define_expand "ashrsi3"
11421 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11422 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11423 (match_operand:QI 2 "nonmemory_operand" "")))
11424 (clobber (reg:CC 17))]
11426 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11428 (define_insn "*ashrsi3_1_one_bit"
11429 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11430 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11431 (match_operand:QI 2 "const_int_1_operand" "")))
11432 (clobber (reg:CC 17))]
11433 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11434 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11436 [(set_attr "type" "ishift")
11437 (set (attr "length")
11438 (if_then_else (match_operand:SI 0 "register_operand" "")
11440 (const_string "*")))])
11442 (define_insn "*ashrsi3_1_one_bit_zext"
11443 [(set (match_operand:DI 0 "register_operand" "=r")
11444 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11445 (match_operand:QI 2 "const_int_1_operand" ""))))
11446 (clobber (reg:CC 17))]
11447 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11448 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11450 [(set_attr "type" "ishift")
11451 (set_attr "length" "2")])
11453 (define_insn "*ashrsi3_1"
11454 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11455 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11456 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11457 (clobber (reg:CC 17))]
11458 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11460 sar{l}\\t{%2, %0|%0, %2}
11461 sar{l}\\t{%b2, %0|%0, %b2}"
11462 [(set_attr "type" "ishift")
11463 (set_attr "mode" "SI")])
11465 (define_insn "*ashrsi3_1_zext"
11466 [(set (match_operand:DI 0 "register_operand" "=r,r")
11467 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11468 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11469 (clobber (reg:CC 17))]
11470 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11472 sar{l}\\t{%2, %k0|%k0, %2}
11473 sar{l}\\t{%b2, %k0|%k0, %b2}"
11474 [(set_attr "type" "ishift")
11475 (set_attr "mode" "SI")])
11477 ;; This pattern can't accept a variable shift count, since shifts by
11478 ;; zero don't affect the flags. We assume that shifts by constant
11479 ;; zero are optimized away.
11480 (define_insn "*ashrsi3_one_bit_cmp"
11483 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11484 (match_operand:QI 2 "const_int_1_operand" ""))
11486 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11487 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11488 "ix86_match_ccmode (insn, CCGOCmode)
11489 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11490 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11492 [(set_attr "type" "ishift")
11493 (set (attr "length")
11494 (if_then_else (match_operand:SI 0 "register_operand" "")
11496 (const_string "*")))])
11498 (define_insn "*ashrsi3_one_bit_cmp_zext"
11501 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11502 (match_operand:QI 2 "const_int_1_operand" ""))
11504 (set (match_operand:DI 0 "register_operand" "=r")
11505 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11506 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11507 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11508 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11510 [(set_attr "type" "ishift")
11511 (set_attr "length" "2")])
11513 ;; This pattern can't accept a variable shift count, since shifts by
11514 ;; zero don't affect the flags. We assume that shifts by constant
11515 ;; zero are optimized away.
11516 (define_insn "*ashrsi3_cmp"
11519 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11520 (match_operand:QI 2 "immediate_operand" "I"))
11522 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11523 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11524 "ix86_match_ccmode (insn, CCGOCmode)
11525 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11526 "sar{l}\\t{%2, %0|%0, %2}"
11527 [(set_attr "type" "ishift")
11528 (set_attr "mode" "SI")])
11530 (define_insn "*ashrsi3_cmp_zext"
11533 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11534 (match_operand:QI 2 "immediate_operand" "I"))
11536 (set (match_operand:DI 0 "register_operand" "=r")
11537 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11538 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11539 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11540 "sar{l}\\t{%2, %k0|%k0, %2}"
11541 [(set_attr "type" "ishift")
11542 (set_attr "mode" "SI")])
11544 (define_expand "ashrhi3"
11545 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11546 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11547 (match_operand:QI 2 "nonmemory_operand" "")))
11548 (clobber (reg:CC 17))]
11549 "TARGET_HIMODE_MATH"
11550 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11552 (define_insn "*ashrhi3_1_one_bit"
11553 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11554 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11555 (match_operand:QI 2 "const_int_1_operand" "")))
11556 (clobber (reg:CC 17))]
11557 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11558 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11560 [(set_attr "type" "ishift")
11561 (set (attr "length")
11562 (if_then_else (match_operand 0 "register_operand" "")
11564 (const_string "*")))])
11566 (define_insn "*ashrhi3_1"
11567 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11568 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11569 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11570 (clobber (reg:CC 17))]
11571 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11573 sar{w}\\t{%2, %0|%0, %2}
11574 sar{w}\\t{%b2, %0|%0, %b2}"
11575 [(set_attr "type" "ishift")
11576 (set_attr "mode" "HI")])
11578 ;; This pattern can't accept a variable shift count, since shifts by
11579 ;; zero don't affect the flags. We assume that shifts by constant
11580 ;; zero are optimized away.
11581 (define_insn "*ashrhi3_one_bit_cmp"
11584 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11585 (match_operand:QI 2 "const_int_1_operand" ""))
11587 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11588 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11589 "ix86_match_ccmode (insn, CCGOCmode)
11590 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11591 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11593 [(set_attr "type" "ishift")
11594 (set (attr "length")
11595 (if_then_else (match_operand 0 "register_operand" "")
11597 (const_string "*")))])
11599 ;; This pattern can't accept a variable shift count, since shifts by
11600 ;; zero don't affect the flags. We assume that shifts by constant
11601 ;; zero are optimized away.
11602 (define_insn "*ashrhi3_cmp"
11605 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11606 (match_operand:QI 2 "immediate_operand" "I"))
11608 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11609 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11610 "ix86_match_ccmode (insn, CCGOCmode)
11611 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11612 "sar{w}\\t{%2, %0|%0, %2}"
11613 [(set_attr "type" "ishift")
11614 (set_attr "mode" "HI")])
11616 (define_expand "ashrqi3"
11617 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11618 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11619 (match_operand:QI 2 "nonmemory_operand" "")))
11620 (clobber (reg:CC 17))]
11621 "TARGET_QIMODE_MATH"
11622 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11624 (define_insn "*ashrqi3_1_one_bit"
11625 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11626 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11627 (match_operand:QI 2 "const_int_1_operand" "")))
11628 (clobber (reg:CC 17))]
11629 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11630 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11632 [(set_attr "type" "ishift")
11633 (set (attr "length")
11634 (if_then_else (match_operand 0 "register_operand" "")
11636 (const_string "*")))])
11638 (define_insn "*ashrqi3_1"
11639 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11640 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11641 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11642 (clobber (reg:CC 17))]
11643 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11645 sar{b}\\t{%2, %0|%0, %2}
11646 sar{b}\\t{%b2, %0|%0, %b2}"
11647 [(set_attr "type" "ishift")
11648 (set_attr "mode" "QI")])
11650 ;; This pattern can't accept a variable shift count, since shifts by
11651 ;; zero don't affect the flags. We assume that shifts by constant
11652 ;; zero are optimized away.
11653 (define_insn "*ashrqi3_one_bit_cmp"
11656 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11657 (match_operand:QI 2 "const_int_1_operand" "I"))
11659 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11660 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11661 "ix86_match_ccmode (insn, CCGOCmode)
11662 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11663 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11665 [(set_attr "type" "ishift")
11666 (set (attr "length")
11667 (if_then_else (match_operand 0 "register_operand" "")
11669 (const_string "*")))])
11671 ;; This pattern can't accept a variable shift count, since shifts by
11672 ;; zero don't affect the flags. We assume that shifts by constant
11673 ;; zero are optimized away.
11674 (define_insn "*ashrqi3_cmp"
11677 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11678 (match_operand:QI 2 "immediate_operand" "I"))
11680 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11681 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11682 "ix86_match_ccmode (insn, CCGOCmode)
11683 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11684 "sar{b}\\t{%2, %0|%0, %2}"
11685 [(set_attr "type" "ishift")
11686 (set_attr "mode" "QI")])
11688 ;; Logical shift instructions
11690 ;; See comment above `ashldi3' about how this works.
11692 (define_expand "lshrdi3"
11693 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11694 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11695 (match_operand:QI 2 "nonmemory_operand" "")))
11696 (clobber (reg:CC 17))])]
11700 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11702 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11705 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11709 (define_insn "*lshrdi3_1_one_bit_rex64"
11710 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11711 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11712 (match_operand:QI 2 "const_int_1_operand" "")))
11713 (clobber (reg:CC 17))]
11714 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11715 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11717 [(set_attr "type" "ishift")
11718 (set (attr "length")
11719 (if_then_else (match_operand:DI 0 "register_operand" "")
11721 (const_string "*")))])
11723 (define_insn "*lshrdi3_1_rex64"
11724 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11725 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11726 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11727 (clobber (reg:CC 17))]
11728 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11730 shr{q}\\t{%2, %0|%0, %2}
11731 shr{q}\\t{%b2, %0|%0, %b2}"
11732 [(set_attr "type" "ishift")
11733 (set_attr "mode" "DI")])
11735 ;; This pattern can't accept a variable shift count, since shifts by
11736 ;; zero don't affect the flags. We assume that shifts by constant
11737 ;; zero are optimized away.
11738 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11741 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11742 (match_operand:QI 2 "const_int_1_operand" ""))
11744 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11745 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11746 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11747 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11748 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11750 [(set_attr "type" "ishift")
11751 (set (attr "length")
11752 (if_then_else (match_operand:DI 0 "register_operand" "")
11754 (const_string "*")))])
11756 ;; This pattern can't accept a variable shift count, since shifts by
11757 ;; zero don't affect the flags. We assume that shifts by constant
11758 ;; zero are optimized away.
11759 (define_insn "*lshrdi3_cmp_rex64"
11762 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11763 (match_operand:QI 2 "const_int_operand" "e"))
11765 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11766 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11767 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11768 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11769 "shr{q}\\t{%2, %0|%0, %2}"
11770 [(set_attr "type" "ishift")
11771 (set_attr "mode" "DI")])
11773 (define_insn "lshrdi3_1"
11774 [(set (match_operand:DI 0 "register_operand" "=r")
11775 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11776 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11777 (clobber (match_scratch:SI 3 "=&r"))
11778 (clobber (reg:CC 17))]
11779 "!TARGET_64BIT && TARGET_CMOVE"
11781 [(set_attr "type" "multi")])
11783 (define_insn "*lshrdi3_2"
11784 [(set (match_operand:DI 0 "register_operand" "=r")
11785 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11786 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11787 (clobber (reg:CC 17))]
11790 [(set_attr "type" "multi")])
11793 [(set (match_operand:DI 0 "register_operand" "")
11794 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11795 (match_operand:QI 2 "nonmemory_operand" "")))
11796 (clobber (match_scratch:SI 3 ""))
11797 (clobber (reg:CC 17))]
11798 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11800 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11803 [(set (match_operand:DI 0 "register_operand" "")
11804 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11805 (match_operand:QI 2 "nonmemory_operand" "")))
11806 (clobber (reg:CC 17))]
11807 "!TARGET_64BIT && reload_completed"
11809 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11811 (define_expand "lshrsi3"
11812 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11813 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11814 (match_operand:QI 2 "nonmemory_operand" "")))
11815 (clobber (reg:CC 17))]
11817 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11819 (define_insn "*lshrsi3_1_one_bit"
11820 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11821 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11822 (match_operand:QI 2 "const_int_1_operand" "")))
11823 (clobber (reg:CC 17))]
11824 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11825 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11827 [(set_attr "type" "ishift")
11828 (set (attr "length")
11829 (if_then_else (match_operand:SI 0 "register_operand" "")
11831 (const_string "*")))])
11833 (define_insn "*lshrsi3_1_one_bit_zext"
11834 [(set (match_operand:DI 0 "register_operand" "=r")
11835 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11836 (match_operand:QI 2 "const_int_1_operand" "")))
11837 (clobber (reg:CC 17))]
11838 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11839 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11841 [(set_attr "type" "ishift")
11842 (set_attr "length" "2")])
11844 (define_insn "*lshrsi3_1"
11845 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11846 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11847 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11848 (clobber (reg:CC 17))]
11849 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11851 shr{l}\\t{%2, %0|%0, %2}
11852 shr{l}\\t{%b2, %0|%0, %b2}"
11853 [(set_attr "type" "ishift")
11854 (set_attr "mode" "SI")])
11856 (define_insn "*lshrsi3_1_zext"
11857 [(set (match_operand:DI 0 "register_operand" "=r,r")
11859 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11860 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11861 (clobber (reg:CC 17))]
11862 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11864 shr{l}\\t{%2, %k0|%k0, %2}
11865 shr{l}\\t{%b2, %k0|%k0, %b2}"
11866 [(set_attr "type" "ishift")
11867 (set_attr "mode" "SI")])
11869 ;; This pattern can't accept a variable shift count, since shifts by
11870 ;; zero don't affect the flags. We assume that shifts by constant
11871 ;; zero are optimized away.
11872 (define_insn "*lshrsi3_one_bit_cmp"
11875 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11876 (match_operand:QI 2 "const_int_1_operand" ""))
11878 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11879 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11880 "ix86_match_ccmode (insn, CCGOCmode)
11881 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11882 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11884 [(set_attr "type" "ishift")
11885 (set (attr "length")
11886 (if_then_else (match_operand:SI 0 "register_operand" "")
11888 (const_string "*")))])
11890 (define_insn "*lshrsi3_cmp_one_bit_zext"
11893 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11894 (match_operand:QI 2 "const_int_1_operand" ""))
11896 (set (match_operand:DI 0 "register_operand" "=r")
11897 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11898 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11899 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11900 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11902 [(set_attr "type" "ishift")
11903 (set_attr "length" "2")])
11905 ;; This pattern can't accept a variable shift count, since shifts by
11906 ;; zero don't affect the flags. We assume that shifts by constant
11907 ;; zero are optimized away.
11908 (define_insn "*lshrsi3_cmp"
11911 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11912 (match_operand:QI 2 "immediate_operand" "I"))
11914 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11915 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11916 "ix86_match_ccmode (insn, CCGOCmode)
11917 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11918 "shr{l}\\t{%2, %0|%0, %2}"
11919 [(set_attr "type" "ishift")
11920 (set_attr "mode" "SI")])
11922 (define_insn "*lshrsi3_cmp_zext"
11925 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11926 (match_operand:QI 2 "immediate_operand" "I"))
11928 (set (match_operand:DI 0 "register_operand" "=r")
11929 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11930 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11931 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11932 "shr{l}\\t{%2, %k0|%k0, %2}"
11933 [(set_attr "type" "ishift")
11934 (set_attr "mode" "SI")])
11936 (define_expand "lshrhi3"
11937 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11938 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11939 (match_operand:QI 2 "nonmemory_operand" "")))
11940 (clobber (reg:CC 17))]
11941 "TARGET_HIMODE_MATH"
11942 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11944 (define_insn "*lshrhi3_1_one_bit"
11945 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11946 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11947 (match_operand:QI 2 "const_int_1_operand" "")))
11948 (clobber (reg:CC 17))]
11949 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11950 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11952 [(set_attr "type" "ishift")
11953 (set (attr "length")
11954 (if_then_else (match_operand 0 "register_operand" "")
11956 (const_string "*")))])
11958 (define_insn "*lshrhi3_1"
11959 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11960 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11961 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11962 (clobber (reg:CC 17))]
11963 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11965 shr{w}\\t{%2, %0|%0, %2}
11966 shr{w}\\t{%b2, %0|%0, %b2}"
11967 [(set_attr "type" "ishift")
11968 (set_attr "mode" "HI")])
11970 ;; This pattern can't accept a variable shift count, since shifts by
11971 ;; zero don't affect the flags. We assume that shifts by constant
11972 ;; zero are optimized away.
11973 (define_insn "*lshrhi3_one_bit_cmp"
11976 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11977 (match_operand:QI 2 "const_int_1_operand" ""))
11979 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11980 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11981 "ix86_match_ccmode (insn, CCGOCmode)
11982 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11983 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11985 [(set_attr "type" "ishift")
11986 (set (attr "length")
11987 (if_then_else (match_operand:SI 0 "register_operand" "")
11989 (const_string "*")))])
11991 ;; This pattern can't accept a variable shift count, since shifts by
11992 ;; zero don't affect the flags. We assume that shifts by constant
11993 ;; zero are optimized away.
11994 (define_insn "*lshrhi3_cmp"
11997 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11998 (match_operand:QI 2 "immediate_operand" "I"))
12000 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12001 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12002 "ix86_match_ccmode (insn, CCGOCmode)
12003 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12004 "shr{w}\\t{%2, %0|%0, %2}"
12005 [(set_attr "type" "ishift")
12006 (set_attr "mode" "HI")])
12008 (define_expand "lshrqi3"
12009 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12010 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12011 (match_operand:QI 2 "nonmemory_operand" "")))
12012 (clobber (reg:CC 17))]
12013 "TARGET_QIMODE_MATH"
12014 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12016 (define_insn "*lshrqi3_1_one_bit"
12017 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12018 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12019 (match_operand:QI 2 "const_int_1_operand" "")))
12020 (clobber (reg:CC 17))]
12021 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12022 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12024 [(set_attr "type" "ishift")
12025 (set (attr "length")
12026 (if_then_else (match_operand 0 "register_operand" "")
12028 (const_string "*")))])
12030 (define_insn "*lshrqi3_1"
12031 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12032 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12033 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12034 (clobber (reg:CC 17))]
12035 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12037 shr{b}\\t{%2, %0|%0, %2}
12038 shr{b}\\t{%b2, %0|%0, %b2}"
12039 [(set_attr "type" "ishift")
12040 (set_attr "mode" "QI")])
12042 ;; This pattern can't accept a variable shift count, since shifts by
12043 ;; zero don't affect the flags. We assume that shifts by constant
12044 ;; zero are optimized away.
12045 (define_insn "*lshrqi2_one_bit_cmp"
12048 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12049 (match_operand:QI 2 "const_int_1_operand" ""))
12051 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12052 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12053 "ix86_match_ccmode (insn, CCGOCmode)
12054 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
12055 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12057 [(set_attr "type" "ishift")
12058 (set (attr "length")
12059 (if_then_else (match_operand:SI 0 "register_operand" "")
12061 (const_string "*")))])
12063 ;; This pattern can't accept a variable shift count, since shifts by
12064 ;; zero don't affect the flags. We assume that shifts by constant
12065 ;; zero are optimized away.
12066 (define_insn "*lshrqi2_cmp"
12069 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12070 (match_operand:QI 2 "immediate_operand" "I"))
12072 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12073 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12074 "ix86_match_ccmode (insn, CCGOCmode)
12075 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12076 "shr{b}\\t{%2, %0|%0, %2}"
12077 [(set_attr "type" "ishift")
12078 (set_attr "mode" "QI")])
12080 ;; Rotate instructions
12082 (define_expand "rotldi3"
12083 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12084 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12085 (match_operand:QI 2 "nonmemory_operand" "")))
12086 (clobber (reg:CC 17))]
12088 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12090 (define_insn "*rotlsi3_1_one_bit_rex64"
12091 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12092 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12093 (match_operand:QI 2 "const_int_1_operand" "")))
12094 (clobber (reg:CC 17))]
12095 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12096 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12098 [(set_attr "type" "ishift")
12099 (set (attr "length")
12100 (if_then_else (match_operand:DI 0 "register_operand" "")
12102 (const_string "*")))])
12104 (define_insn "*rotldi3_1_rex64"
12105 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12106 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12107 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12108 (clobber (reg:CC 17))]
12109 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12111 rol{q}\\t{%2, %0|%0, %2}
12112 rol{q}\\t{%b2, %0|%0, %b2}"
12113 [(set_attr "type" "ishift")
12114 (set_attr "mode" "DI")])
12116 (define_expand "rotlsi3"
12117 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12118 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12119 (match_operand:QI 2 "nonmemory_operand" "")))
12120 (clobber (reg:CC 17))]
12122 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12124 (define_insn "*rotlsi3_1_one_bit"
12125 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12126 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12127 (match_operand:QI 2 "const_int_1_operand" "")))
12128 (clobber (reg:CC 17))]
12129 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12130 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12132 [(set_attr "type" "ishift")
12133 (set (attr "length")
12134 (if_then_else (match_operand:SI 0 "register_operand" "")
12136 (const_string "*")))])
12138 (define_insn "*rotlsi3_1_one_bit_zext"
12139 [(set (match_operand:DI 0 "register_operand" "=r")
12141 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12142 (match_operand:QI 2 "const_int_1_operand" ""))))
12143 (clobber (reg:CC 17))]
12144 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12145 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12147 [(set_attr "type" "ishift")
12148 (set_attr "length" "2")])
12150 (define_insn "*rotlsi3_1"
12151 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12152 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12153 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12154 (clobber (reg:CC 17))]
12155 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12157 rol{l}\\t{%2, %0|%0, %2}
12158 rol{l}\\t{%b2, %0|%0, %b2}"
12159 [(set_attr "type" "ishift")
12160 (set_attr "mode" "SI")])
12162 (define_insn "*rotlsi3_1_zext"
12163 [(set (match_operand:DI 0 "register_operand" "=r,r")
12165 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12166 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12167 (clobber (reg:CC 17))]
12168 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12170 rol{l}\\t{%2, %k0|%k0, %2}
12171 rol{l}\\t{%b2, %k0|%k0, %b2}"
12172 [(set_attr "type" "ishift")
12173 (set_attr "mode" "SI")])
12175 (define_expand "rotlhi3"
12176 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12177 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12178 (match_operand:QI 2 "nonmemory_operand" "")))
12179 (clobber (reg:CC 17))]
12180 "TARGET_HIMODE_MATH"
12181 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12183 (define_insn "*rotlhi3_1_one_bit"
12184 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12185 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12186 (match_operand:QI 2 "const_int_1_operand" "")))
12187 (clobber (reg:CC 17))]
12188 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12189 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12191 [(set_attr "type" "ishift")
12192 (set (attr "length")
12193 (if_then_else (match_operand 0 "register_operand" "")
12195 (const_string "*")))])
12197 (define_insn "*rotlhi3_1"
12198 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12199 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12200 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12201 (clobber (reg:CC 17))]
12202 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12204 rol{w}\\t{%2, %0|%0, %2}
12205 rol{w}\\t{%b2, %0|%0, %b2}"
12206 [(set_attr "type" "ishift")
12207 (set_attr "mode" "HI")])
12209 (define_expand "rotlqi3"
12210 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12211 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12212 (match_operand:QI 2 "nonmemory_operand" "")))
12213 (clobber (reg:CC 17))]
12214 "TARGET_QIMODE_MATH"
12215 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12217 (define_insn "*rotlqi3_1_one_bit"
12218 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12219 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12220 (match_operand:QI 2 "const_int_1_operand" "")))
12221 (clobber (reg:CC 17))]
12222 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12223 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12225 [(set_attr "type" "ishift")
12226 (set (attr "length")
12227 (if_then_else (match_operand 0 "register_operand" "")
12229 (const_string "*")))])
12231 (define_insn "*rotlqi3_1"
12232 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12233 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12234 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12235 (clobber (reg:CC 17))]
12236 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12238 rol{b}\\t{%2, %0|%0, %2}
12239 rol{b}\\t{%b2, %0|%0, %b2}"
12240 [(set_attr "type" "ishift")
12241 (set_attr "mode" "QI")])
12243 (define_expand "rotrdi3"
12244 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12245 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12246 (match_operand:QI 2 "nonmemory_operand" "")))
12247 (clobber (reg:CC 17))]
12249 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12251 (define_insn "*rotrdi3_1_one_bit_rex64"
12252 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12253 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12254 (match_operand:QI 2 "const_int_1_operand" "")))
12255 (clobber (reg:CC 17))]
12256 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12257 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12259 [(set_attr "type" "ishift")
12260 (set (attr "length")
12261 (if_then_else (match_operand:DI 0 "register_operand" "")
12263 (const_string "*")))])
12265 (define_insn "*rotrdi3_1_rex64"
12266 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12267 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12268 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12269 (clobber (reg:CC 17))]
12270 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12272 ror{q}\\t{%2, %0|%0, %2}
12273 ror{q}\\t{%b2, %0|%0, %b2}"
12274 [(set_attr "type" "ishift")
12275 (set_attr "mode" "DI")])
12277 (define_expand "rotrsi3"
12278 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12279 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12280 (match_operand:QI 2 "nonmemory_operand" "")))
12281 (clobber (reg:CC 17))]
12283 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12285 (define_insn "*rotrsi3_1_one_bit"
12286 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12287 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12288 (match_operand:QI 2 "const_int_1_operand" "")))
12289 (clobber (reg:CC 17))]
12290 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12291 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12293 [(set_attr "type" "ishift")
12294 (set (attr "length")
12295 (if_then_else (match_operand:SI 0 "register_operand" "")
12297 (const_string "*")))])
12299 (define_insn "*rotrsi3_1_one_bit_zext"
12300 [(set (match_operand:DI 0 "register_operand" "=r")
12302 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12303 (match_operand:QI 2 "const_int_1_operand" ""))))
12304 (clobber (reg:CC 17))]
12305 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12306 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12308 [(set_attr "type" "ishift")
12309 (set (attr "length")
12310 (if_then_else (match_operand:SI 0 "register_operand" "")
12312 (const_string "*")))])
12314 (define_insn "*rotrsi3_1"
12315 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12316 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12317 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12318 (clobber (reg:CC 17))]
12319 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12321 ror{l}\\t{%2, %0|%0, %2}
12322 ror{l}\\t{%b2, %0|%0, %b2}"
12323 [(set_attr "type" "ishift")
12324 (set_attr "mode" "SI")])
12326 (define_insn "*rotrsi3_1_zext"
12327 [(set (match_operand:DI 0 "register_operand" "=r,r")
12329 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12330 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12331 (clobber (reg:CC 17))]
12332 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12334 ror{l}\\t{%2, %k0|%k0, %2}
12335 ror{l}\\t{%b2, %k0|%k0, %b2}"
12336 [(set_attr "type" "ishift")
12337 (set_attr "mode" "SI")])
12339 (define_expand "rotrhi3"
12340 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12341 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12342 (match_operand:QI 2 "nonmemory_operand" "")))
12343 (clobber (reg:CC 17))]
12344 "TARGET_HIMODE_MATH"
12345 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12347 (define_insn "*rotrhi3_one_bit"
12348 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12349 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12350 (match_operand:QI 2 "const_int_1_operand" "")))
12351 (clobber (reg:CC 17))]
12352 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12353 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12355 [(set_attr "type" "ishift")
12356 (set (attr "length")
12357 (if_then_else (match_operand 0 "register_operand" "")
12359 (const_string "*")))])
12361 (define_insn "*rotrhi3"
12362 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12363 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12364 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12365 (clobber (reg:CC 17))]
12366 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12368 ror{w}\\t{%2, %0|%0, %2}
12369 ror{w}\\t{%b2, %0|%0, %b2}"
12370 [(set_attr "type" "ishift")
12371 (set_attr "mode" "HI")])
12373 (define_expand "rotrqi3"
12374 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12375 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12376 (match_operand:QI 2 "nonmemory_operand" "")))
12377 (clobber (reg:CC 17))]
12378 "TARGET_QIMODE_MATH"
12379 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12381 (define_insn "*rotrqi3_1_one_bit"
12382 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12383 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12384 (match_operand:QI 2 "const_int_1_operand" "")))
12385 (clobber (reg:CC 17))]
12386 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12387 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12389 [(set_attr "type" "ishift")
12390 (set (attr "length")
12391 (if_then_else (match_operand 0 "register_operand" "")
12393 (const_string "*")))])
12395 (define_insn "*rotrqi3_1"
12396 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12397 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12398 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12399 (clobber (reg:CC 17))]
12400 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12402 ror{b}\\t{%2, %0|%0, %2}
12403 ror{b}\\t{%b2, %0|%0, %b2}"
12404 [(set_attr "type" "ishift")
12405 (set_attr "mode" "QI")])
12407 ;; Bit set / bit test instructions
12409 (define_expand "extv"
12410 [(set (match_operand:SI 0 "register_operand" "")
12411 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12412 (match_operand:SI 2 "immediate_operand" "")
12413 (match_operand:SI 3 "immediate_operand" "")))]
12417 /* Handle extractions from %ah et al. */
12418 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12421 /* From mips.md: extract_bit_field doesn't verify that our source
12422 matches the predicate, so check it again here. */
12423 if (! register_operand (operands[1], VOIDmode))
12427 (define_expand "extzv"
12428 [(set (match_operand:SI 0 "register_operand" "")
12429 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12430 (match_operand:SI 2 "immediate_operand" "")
12431 (match_operand:SI 3 "immediate_operand" "")))]
12435 /* Handle extractions from %ah et al. */
12436 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12439 /* From mips.md: extract_bit_field doesn't verify that our source
12440 matches the predicate, so check it again here. */
12441 if (! register_operand (operands[1], VOIDmode))
12445 (define_expand "insv"
12446 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12447 (match_operand:SI 1 "immediate_operand" "")
12448 (match_operand:SI 2 "immediate_operand" ""))
12449 (match_operand:SI 3 "register_operand" ""))]
12453 /* Handle extractions from %ah et al. */
12454 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12457 /* From mips.md: insert_bit_field doesn't verify that our source
12458 matches the predicate, so check it again here. */
12459 if (! register_operand (operands[0], VOIDmode))
12463 ;; %%% bts, btr, btc, bt.
12465 ;; Store-flag instructions.
12467 ;; For all sCOND expanders, also expand the compare or test insn that
12468 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12470 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12471 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12472 ;; way, which can later delete the movzx if only QImode is needed.
12474 (define_expand "seq"
12475 [(set (match_operand:SI 0 "register_operand" "")
12476 (eq:SI (reg:CC 17) (const_int 0)))]
12478 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12480 (define_expand "sne"
12481 [(set (match_operand:SI 0 "register_operand" "")
12482 (ne:SI (reg:CC 17) (const_int 0)))]
12484 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12486 (define_expand "sgt"
12487 [(set (match_operand:SI 0 "register_operand" "")
12488 (gt:SI (reg:CC 17) (const_int 0)))]
12490 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12492 (define_expand "sgtu"
12493 [(set (match_operand:SI 0 "register_operand" "")
12494 (gtu:SI (reg:CC 17) (const_int 0)))]
12496 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12498 (define_expand "slt"
12499 [(set (match_operand:SI 0 "register_operand" "")
12500 (lt:SI (reg:CC 17) (const_int 0)))]
12502 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12504 (define_expand "sltu"
12505 [(set (match_operand:SI 0 "register_operand" "")
12506 (ltu:SI (reg:CC 17) (const_int 0)))]
12508 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12510 (define_expand "sge"
12511 [(set (match_operand:SI 0 "register_operand" "")
12512 (ge:SI (reg:CC 17) (const_int 0)))]
12514 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12516 (define_expand "sgeu"
12517 [(set (match_operand:SI 0 "register_operand" "")
12518 (geu:SI (reg:CC 17) (const_int 0)))]
12520 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12522 (define_expand "sle"
12523 [(set (match_operand:SI 0 "register_operand" "")
12524 (le:SI (reg:CC 17) (const_int 0)))]
12526 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12528 (define_expand "sleu"
12529 [(set (match_operand:SI 0 "register_operand" "")
12530 (leu:SI (reg:CC 17) (const_int 0)))]
12532 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12534 (define_expand "sunordered"
12535 [(set (match_operand:SI 0 "register_operand" "")
12536 (unordered:SI (reg:CC 17) (const_int 0)))]
12537 "TARGET_80387 || TARGET_SSE"
12538 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12540 (define_expand "sordered"
12541 [(set (match_operand:SI 0 "register_operand" "")
12542 (ordered:SI (reg:CC 17) (const_int 0)))]
12544 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12546 (define_expand "suneq"
12547 [(set (match_operand:SI 0 "register_operand" "")
12548 (uneq:SI (reg:CC 17) (const_int 0)))]
12549 "TARGET_80387 || TARGET_SSE"
12550 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12552 (define_expand "sunge"
12553 [(set (match_operand:SI 0 "register_operand" "")
12554 (unge:SI (reg:CC 17) (const_int 0)))]
12555 "TARGET_80387 || TARGET_SSE"
12556 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12558 (define_expand "sungt"
12559 [(set (match_operand:SI 0 "register_operand" "")
12560 (ungt:SI (reg:CC 17) (const_int 0)))]
12561 "TARGET_80387 || TARGET_SSE"
12562 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12564 (define_expand "sunle"
12565 [(set (match_operand:SI 0 "register_operand" "")
12566 (unle:SI (reg:CC 17) (const_int 0)))]
12567 "TARGET_80387 || TARGET_SSE"
12568 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12570 (define_expand "sunlt"
12571 [(set (match_operand:SI 0 "register_operand" "")
12572 (unlt:SI (reg:CC 17) (const_int 0)))]
12573 "TARGET_80387 || TARGET_SSE"
12574 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12576 (define_expand "sltgt"
12577 [(set (match_operand:SI 0 "register_operand" "")
12578 (ltgt:SI (reg:CC 17) (const_int 0)))]
12579 "TARGET_80387 || TARGET_SSE"
12580 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12582 (define_insn "*setcc_1"
12583 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12584 (match_operator:QI 1 "ix86_comparison_operator"
12585 [(reg 17) (const_int 0)]))]
12588 [(set_attr "type" "setcc")
12589 (set_attr "mode" "QI")])
12591 (define_insn "setcc_2"
12592 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12593 (match_operator:QI 1 "ix86_comparison_operator"
12594 [(reg 17) (const_int 0)]))]
12597 [(set_attr "type" "setcc")
12598 (set_attr "mode" "QI")])
12600 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12601 ;; subsequent logical operations are used to imitate conditional moves.
12602 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12603 ;; it directly. Futher holding this value in pseudo register might bring
12604 ;; problem in implicit normalization in spill code.
12605 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12606 ;; instructions after reload by splitting the conditional move patterns.
12608 (define_insn "*sse_setccsf"
12609 [(set (match_operand:SF 0 "register_operand" "=x")
12610 (match_operator:SF 1 "sse_comparison_operator"
12611 [(match_operand:SF 2 "register_operand" "0")
12612 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12613 "TARGET_SSE && reload_completed"
12614 "cmp%D1ss\\t{%3, %0|%0, %3}"
12615 [(set_attr "type" "sse")
12616 (set_attr "mode" "SF")])
12618 (define_insn "*sse_setccdf"
12619 [(set (match_operand:DF 0 "register_operand" "=Y")
12620 (match_operator:DF 1 "sse_comparison_operator"
12621 [(match_operand:DF 2 "register_operand" "0")
12622 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12623 "TARGET_SSE2 && reload_completed"
12624 "cmp%D1sd\\t{%3, %0|%0, %3}"
12625 [(set_attr "type" "sse")
12626 (set_attr "mode" "DF")])
12628 ;; Basic conditional jump instructions.
12629 ;; We ignore the overflow flag for signed branch instructions.
12631 ;; For all bCOND expanders, also expand the compare or test insn that
12632 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12634 (define_expand "beq"
12636 (if_then_else (match_dup 1)
12637 (label_ref (match_operand 0 "" ""))
12640 "ix86_expand_branch (EQ, operands[0]); DONE;")
12642 (define_expand "bne"
12644 (if_then_else (match_dup 1)
12645 (label_ref (match_operand 0 "" ""))
12648 "ix86_expand_branch (NE, operands[0]); DONE;")
12650 (define_expand "bgt"
12652 (if_then_else (match_dup 1)
12653 (label_ref (match_operand 0 "" ""))
12656 "ix86_expand_branch (GT, operands[0]); DONE;")
12658 (define_expand "bgtu"
12660 (if_then_else (match_dup 1)
12661 (label_ref (match_operand 0 "" ""))
12664 "ix86_expand_branch (GTU, operands[0]); DONE;")
12666 (define_expand "blt"
12668 (if_then_else (match_dup 1)
12669 (label_ref (match_operand 0 "" ""))
12672 "ix86_expand_branch (LT, operands[0]); DONE;")
12674 (define_expand "bltu"
12676 (if_then_else (match_dup 1)
12677 (label_ref (match_operand 0 "" ""))
12680 "ix86_expand_branch (LTU, operands[0]); DONE;")
12682 (define_expand "bge"
12684 (if_then_else (match_dup 1)
12685 (label_ref (match_operand 0 "" ""))
12688 "ix86_expand_branch (GE, operands[0]); DONE;")
12690 (define_expand "bgeu"
12692 (if_then_else (match_dup 1)
12693 (label_ref (match_operand 0 "" ""))
12696 "ix86_expand_branch (GEU, operands[0]); DONE;")
12698 (define_expand "ble"
12700 (if_then_else (match_dup 1)
12701 (label_ref (match_operand 0 "" ""))
12704 "ix86_expand_branch (LE, operands[0]); DONE;")
12706 (define_expand "bleu"
12708 (if_then_else (match_dup 1)
12709 (label_ref (match_operand 0 "" ""))
12712 "ix86_expand_branch (LEU, operands[0]); DONE;")
12714 (define_expand "bunordered"
12716 (if_then_else (match_dup 1)
12717 (label_ref (match_operand 0 "" ""))
12719 "TARGET_80387 || TARGET_SSE"
12720 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12722 (define_expand "bordered"
12724 (if_then_else (match_dup 1)
12725 (label_ref (match_operand 0 "" ""))
12727 "TARGET_80387 || TARGET_SSE"
12728 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12730 (define_expand "buneq"
12732 (if_then_else (match_dup 1)
12733 (label_ref (match_operand 0 "" ""))
12735 "TARGET_80387 || TARGET_SSE"
12736 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12738 (define_expand "bunge"
12740 (if_then_else (match_dup 1)
12741 (label_ref (match_operand 0 "" ""))
12743 "TARGET_80387 || TARGET_SSE"
12744 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12746 (define_expand "bungt"
12748 (if_then_else (match_dup 1)
12749 (label_ref (match_operand 0 "" ""))
12751 "TARGET_80387 || TARGET_SSE"
12752 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12754 (define_expand "bunle"
12756 (if_then_else (match_dup 1)
12757 (label_ref (match_operand 0 "" ""))
12759 "TARGET_80387 || TARGET_SSE"
12760 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12762 (define_expand "bunlt"
12764 (if_then_else (match_dup 1)
12765 (label_ref (match_operand 0 "" ""))
12767 "TARGET_80387 || TARGET_SSE"
12768 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12770 (define_expand "bltgt"
12772 (if_then_else (match_dup 1)
12773 (label_ref (match_operand 0 "" ""))
12775 "TARGET_80387 || TARGET_SSE"
12776 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12778 (define_insn "*jcc_1"
12780 (if_then_else (match_operator 1 "ix86_comparison_operator"
12781 [(reg 17) (const_int 0)])
12782 (label_ref (match_operand 0 "" ""))
12786 [(set_attr "type" "ibr")
12787 (set (attr "prefix_0f")
12788 (if_then_else (and (ge (minus (match_dup 0) (pc))
12790 (lt (minus (match_dup 0) (pc))
12795 (define_insn "*jcc_2"
12797 (if_then_else (match_operator 1 "ix86_comparison_operator"
12798 [(reg 17) (const_int 0)])
12800 (label_ref (match_operand 0 "" ""))))]
12803 [(set_attr "type" "ibr")
12804 (set (attr "prefix_0f")
12805 (if_then_else (and (ge (minus (match_dup 0) (pc))
12807 (lt (minus (match_dup 0) (pc))
12812 ;; Define combination compare-and-branch fp compare instructions to use
12813 ;; during early optimization. Splitting the operation apart early makes
12814 ;; for bad code when we want to reverse the operation.
12816 (define_insn "*fp_jcc_1"
12818 (if_then_else (match_operator 0 "comparison_operator"
12819 [(match_operand 1 "register_operand" "f")
12820 (match_operand 2 "register_operand" "f")])
12821 (label_ref (match_operand 3 "" ""))
12823 (clobber (reg:CCFP 18))
12824 (clobber (reg:CCFP 17))]
12825 "TARGET_CMOVE && TARGET_80387
12826 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12827 && FLOAT_MODE_P (GET_MODE (operands[1]))
12828 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12831 (define_insn "*fp_jcc_1_sse"
12833 (if_then_else (match_operator 0 "comparison_operator"
12834 [(match_operand 1 "register_operand" "f#x,x#f")
12835 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12836 (label_ref (match_operand 3 "" ""))
12838 (clobber (reg:CCFP 18))
12839 (clobber (reg:CCFP 17))]
12841 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12842 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12845 (define_insn "*fp_jcc_1_sse_only"
12847 (if_then_else (match_operator 0 "comparison_operator"
12848 [(match_operand 1 "register_operand" "x")
12849 (match_operand 2 "nonimmediate_operand" "xm")])
12850 (label_ref (match_operand 3 "" ""))
12852 (clobber (reg:CCFP 18))
12853 (clobber (reg:CCFP 17))]
12854 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12855 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12858 (define_insn "*fp_jcc_2"
12860 (if_then_else (match_operator 0 "comparison_operator"
12861 [(match_operand 1 "register_operand" "f")
12862 (match_operand 2 "register_operand" "f")])
12864 (label_ref (match_operand 3 "" ""))))
12865 (clobber (reg:CCFP 18))
12866 (clobber (reg:CCFP 17))]
12867 "TARGET_CMOVE && TARGET_80387
12868 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12869 && FLOAT_MODE_P (GET_MODE (operands[1]))
12870 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12873 (define_insn "*fp_jcc_2_sse"
12875 (if_then_else (match_operator 0 "comparison_operator"
12876 [(match_operand 1 "register_operand" "f#x,x#f")
12877 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12879 (label_ref (match_operand 3 "" ""))))
12880 (clobber (reg:CCFP 18))
12881 (clobber (reg:CCFP 17))]
12883 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12884 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12887 (define_insn "*fp_jcc_2_sse_only"
12889 (if_then_else (match_operator 0 "comparison_operator"
12890 [(match_operand 1 "register_operand" "x")
12891 (match_operand 2 "nonimmediate_operand" "xm")])
12893 (label_ref (match_operand 3 "" ""))))
12894 (clobber (reg:CCFP 18))
12895 (clobber (reg:CCFP 17))]
12896 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12897 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12900 (define_insn "*fp_jcc_3"
12902 (if_then_else (match_operator 0 "comparison_operator"
12903 [(match_operand 1 "register_operand" "f")
12904 (match_operand 2 "nonimmediate_operand" "fm")])
12905 (label_ref (match_operand 3 "" ""))
12907 (clobber (reg:CCFP 18))
12908 (clobber (reg:CCFP 17))
12909 (clobber (match_scratch:HI 4 "=a"))]
12911 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12912 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12913 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12914 && SELECT_CC_MODE (GET_CODE (operands[0]),
12915 operands[1], operands[2]) == CCFPmode"
12918 (define_insn "*fp_jcc_4"
12920 (if_then_else (match_operator 0 "comparison_operator"
12921 [(match_operand 1 "register_operand" "f")
12922 (match_operand 2 "nonimmediate_operand" "fm")])
12924 (label_ref (match_operand 3 "" ""))))
12925 (clobber (reg:CCFP 18))
12926 (clobber (reg:CCFP 17))
12927 (clobber (match_scratch:HI 4 "=a"))]
12929 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12930 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12931 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12932 && SELECT_CC_MODE (GET_CODE (operands[0]),
12933 operands[1], operands[2]) == CCFPmode"
12936 (define_insn "*fp_jcc_5"
12938 (if_then_else (match_operator 0 "comparison_operator"
12939 [(match_operand 1 "register_operand" "f")
12940 (match_operand 2 "register_operand" "f")])
12941 (label_ref (match_operand 3 "" ""))
12943 (clobber (reg:CCFP 18))
12944 (clobber (reg:CCFP 17))
12945 (clobber (match_scratch:HI 4 "=a"))]
12947 && FLOAT_MODE_P (GET_MODE (operands[1]))
12948 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12951 (define_insn "*fp_jcc_6"
12953 (if_then_else (match_operator 0 "comparison_operator"
12954 [(match_operand 1 "register_operand" "f")
12955 (match_operand 2 "register_operand" "f")])
12957 (label_ref (match_operand 3 "" ""))))
12958 (clobber (reg:CCFP 18))
12959 (clobber (reg:CCFP 17))
12960 (clobber (match_scratch:HI 4 "=a"))]
12962 && FLOAT_MODE_P (GET_MODE (operands[1]))
12963 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12968 (if_then_else (match_operator 0 "comparison_operator"
12969 [(match_operand 1 "register_operand" "")
12970 (match_operand 2 "nonimmediate_operand" "")])
12971 (match_operand 3 "" "")
12972 (match_operand 4 "" "")))
12973 (clobber (reg:CCFP 18))
12974 (clobber (reg:CCFP 17))]
12979 ix86_split_fp_branch (operands[0], operands[1], operands[2],
12980 operands[3], operands[4], NULL_RTX);
12986 (if_then_else (match_operator 0 "comparison_operator"
12987 [(match_operand 1 "register_operand" "")
12988 (match_operand 2 "nonimmediate_operand" "")])
12989 (match_operand 3 "" "")
12990 (match_operand 4 "" "")))
12991 (clobber (reg:CCFP 18))
12992 (clobber (reg:CCFP 17))
12993 (clobber (match_scratch:HI 5 "=a"))]
12996 (if_then_else (match_dup 6)
13001 ix86_split_fp_branch (operands[0], operands[1], operands[2],
13002 operands[3], operands[4], operands[5]);
13006 ;; Unconditional and other jump instructions
13008 (define_insn "jump"
13010 (label_ref (match_operand 0 "" "")))]
13013 [(set_attr "type" "ibr")])
13015 (define_insn "indirect_jump"
13016 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13019 [(set_attr "type" "ibr")
13020 (set_attr "length_immediate" "0")])
13022 (define_insn "tablejump"
13023 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13024 (use (label_ref (match_operand 1 "" "")))]
13027 [(set_attr "type" "ibr")
13028 (set_attr "length_immediate" "0")])
13030 ;; Implement switch statements when generating PIC code. Switches are
13031 ;; implemented by `tablejump' when not using -fpic.
13033 ;; Emit code here to do the range checking and make the index zero based.
13035 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
13036 ;; two rules below:
13038 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
13040 ;; 1. An expression involving an external reference may only use the
13041 ;; addition operator, and only with an assembly-time constant.
13042 ;; The example above satisfies this because ".-.L2" is a constant.
13044 ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
13045 ;; given the value of "GOT - .", where GOT is the actual address of
13046 ;; the Global Offset Table. Therefore, the .long above actually
13047 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
13048 ;; expression "GOT - .L2" by itself would generate an error from as(1).
13050 ;; The pattern below emits code that looks like this:
13053 ;; subl TABLE@GOTOFF(%ebx,index,4),reg
13056 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
13057 ;; the addr_diff_vec is known to be part of this module.
13059 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
13060 ;; evaluates to just ".L2".
13062 (define_expand "casesi"
13063 [(set (match_dup 5)
13064 (match_operand:SI 0 "general_operand" ""))
13065 (parallel [(set (match_dup 6)
13066 (minus:SI (match_dup 5)
13067 (match_operand:SI 1 "general_operand" "")))
13068 (clobber (reg:CC 17))])
13070 (compare:CC (match_dup 6)
13071 (match_operand:SI 2 "general_operand" "")))
13073 (if_then_else (gtu (reg:CC 17)
13075 (label_ref (match_operand 4 "" ""))
13078 [(set (match_dup 7)
13079 (minus:SI (match_dup 8)
13080 (mem:SI (plus:SI (plus:SI (mult:SI (match_dup 6) (const_int 4))
13082 (const (unspec [(label_ref (match_operand 3 "" ""))] 7))))))
13083 (clobber (reg:CC 17))])
13084 (parallel [(set (pc) (match_dup 7))
13085 (use (label_ref (match_dup 3)))])]
13089 operands[5] = gen_reg_rtx (SImode);
13090 operands[6] = gen_reg_rtx (SImode);
13091 operands[7] = gen_reg_rtx (SImode);
13092 operands[8] = pic_offset_table_rtx;
13093 current_function_uses_pic_offset_table = 1;
13096 (define_insn "*tablejump_pic"
13097 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13098 (use (label_ref (match_operand 1 "" "")))]
13101 [(set_attr "type" "ibr")
13102 (set_attr "length_immediate" "0")])
13104 ;; Loop instruction
13106 ;; This is all complicated by the fact that since this is a jump insn
13107 ;; we must handle our own reloads.
13109 (define_expand "doloop_end"
13110 [(use (match_operand 0 "" "")) ; loop pseudo
13111 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13112 (use (match_operand 2 "" "")) ; max iterations
13113 (use (match_operand 3 "" "")) ; loop level
13114 (use (match_operand 4 "" ""))] ; label
13115 "TARGET_USE_LOOP && !TARGET_64BIT"
13118 /* Only use cloop on innermost loops. */
13119 if (INTVAL (operands[3]) > 1)
13121 if (GET_MODE (operands[0]) != SImode)
13123 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13128 (define_insn "doloop_end_internal"
13130 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13132 (label_ref (match_operand 0 "" ""))
13134 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13135 (plus:SI (match_dup 1)
13137 (clobber (match_scratch:SI 3 "=X,X,r"))
13138 (clobber (reg:CC 17))]
13139 "TARGET_USE_LOOP && !TARGET_64BIT"
13142 if (which_alternative != 0)
13144 if (get_attr_length (insn) == 2)
13145 return \"%+loop\\t%l0\";
13147 return \"dec{l}\\t%1\;%+jne\\t%l0\";
13149 [(set_attr "ppro_uops" "many")
13151 (if_then_else (and (eq_attr "alternative" "0")
13152 (and (ge (minus (match_dup 0) (pc))
13154 (lt (minus (match_dup 0) (pc))
13156 (const_string "ibr")
13157 (const_string "multi")))])
13161 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13163 (match_operand 0 "" "")
13166 (plus:SI (match_dup 1)
13168 (clobber (match_scratch:SI 2 ""))
13169 (clobber (reg:CC 17))]
13170 "TARGET_USE_LOOP && !TARGET_64BIT
13171 && reload_completed
13172 && REGNO (operands[1]) != 2"
13173 [(parallel [(set (reg:CCZ 17)
13174 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13176 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13177 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13184 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13186 (match_operand 0 "" "")
13188 (set (match_operand:SI 2 "nonimmediate_operand" "")
13189 (plus:SI (match_dup 1)
13191 (clobber (match_scratch:SI 3 ""))
13192 (clobber (reg:CC 17))]
13193 "TARGET_USE_LOOP && !TARGET_64BIT
13194 && reload_completed
13195 && (! REG_P (operands[2])
13196 || ! rtx_equal_p (operands[1], operands[2]))"
13197 [(set (match_dup 3) (match_dup 1))
13198 (parallel [(set (reg:CCZ 17)
13199 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13201 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13202 (set (match_dup 2) (match_dup 3))
13203 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13208 ;; Call instructions.
13210 ;; The predicates normally associated with named expanders are not properly
13211 ;; checked for calls. This is a bug in the generic code, but it isn't that
13212 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13214 ;; Call subroutine returning no value.
13216 (define_expand "call_pop"
13217 [(parallel [(call (match_operand:QI 0 "" "")
13218 (match_operand:SI 1 "" ""))
13220 (plus:SI (reg:SI 7)
13221 (match_operand:SI 3 "" "")))])]
13225 if (operands[3] == const0_rtx)
13227 emit_insn (gen_call (operands[0], operands[1], constm1_rtx));
13230 /* Static functions and indirect calls don't need
13231 current_function_uses_pic_offset_table. */
13233 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13234 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13235 current_function_uses_pic_offset_table = 1;
13236 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13237 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13242 (define_insn "*call_pop_0"
13243 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13244 (match_operand:SI 1 "" ""))
13245 (set (reg:SI 7) (plus:SI (reg:SI 7)
13246 (match_operand:SI 2 "immediate_operand" "")))]
13250 if (SIBLING_CALL_P (insn))
13251 return \"jmp\\t%P0\";
13253 return \"call\\t%P0\";
13255 [(set_attr "type" "call")])
13257 (define_insn "*call_pop_1"
13258 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13259 (match_operand:SI 1 "" ""))
13260 (set (reg:SI 7) (plus:SI (reg:SI 7)
13261 (match_operand:SI 2 "immediate_operand" "i")))]
13265 if (constant_call_address_operand (operands[0], Pmode))
13267 if (SIBLING_CALL_P (insn))
13268 return \"jmp\\t%P0\";
13270 return \"call\\t%P0\";
13272 if (SIBLING_CALL_P (insn))
13273 return \"jmp\\t%A0\";
13275 return \"call\\t%A0\";
13277 [(set_attr "type" "call")])
13279 (define_expand "call"
13280 [(call (match_operand:QI 0 "" "")
13281 (match_operand 1 "" ""))
13282 (use (match_operand 2 "" ""))]
13283 ;; Operand 1 not used on the i386.
13288 /* Static functions and indirect calls don't need
13289 current_function_uses_pic_offset_table. */
13291 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13292 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13293 current_function_uses_pic_offset_table = 1;
13295 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13296 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13297 if (TARGET_64BIT && INTVAL (operands[2]) >= 0)
13299 rtx reg = gen_rtx_REG (QImode, 0);
13300 emit_move_insn (reg, operands[2]);
13301 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13302 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13305 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13309 (define_expand "call_exp"
13310 [(call (match_operand:QI 0 "" "")
13311 (match_operand 1 "" ""))]
13315 (define_insn "*call_0"
13316 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13317 (match_operand 1 "" ""))]
13321 if (SIBLING_CALL_P (insn))
13322 return \"jmp\\t%P0\";
13324 return \"call\\t%P0\";
13326 [(set_attr "type" "call")])
13328 (define_insn "*call_1"
13329 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13330 (match_operand 1 "" ""))]
13334 if (constant_call_address_operand (operands[0], QImode))
13336 if (SIBLING_CALL_P (insn))
13337 return \"jmp\\t%P0\";
13339 return \"call\\t%P0\";
13341 if (SIBLING_CALL_P (insn))
13342 return \"jmp\\t%A0\";
13344 return \"call\\t%A0\";
13346 [(set_attr "type" "call")])
13348 (define_insn "*call_1_rex64"
13349 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13350 (match_operand 1 "" ""))]
13354 if (constant_call_address_operand (operands[0], QImode))
13356 if (SIBLING_CALL_P (insn))
13357 return \"jmp\\t%P0\";
13359 return \"call\\t%P0\";
13361 if (SIBLING_CALL_P (insn))
13362 return \"jmp\\t%A0\";
13364 return \"call\\t%A0\";
13366 [(set_attr "type" "call")])
13368 ;; Call subroutine, returning value in operand 0
13369 ;; (which must be a hard register).
13371 (define_expand "call_value_pop"
13372 [(parallel [(set (match_operand 0 "" "")
13373 (call (match_operand:QI 1 "" "")
13374 (match_operand:SI 2 "" "")))
13376 (plus:SI (reg:SI 7)
13377 (match_operand:SI 4 "" "")))])]
13381 if (operands[4] == const0_rtx)
13383 emit_insn (gen_call_value (operands[0], operands[1], operands[2],
13387 /* Static functions and indirect calls don't need
13388 current_function_uses_pic_offset_table. */
13390 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13391 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13392 current_function_uses_pic_offset_table = 1;
13393 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13394 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13397 (define_expand "call_value"
13398 [(set (match_operand 0 "" "")
13399 (call (match_operand:QI 1 "" "")
13400 (match_operand:SI 2 "" "")))
13401 (use (match_operand:SI 3 "" ""))]
13402 ;; Operand 2 not used on the i386.
13407 /* Static functions and indirect calls don't need
13408 current_function_uses_pic_offset_table. */
13410 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13411 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13412 current_function_uses_pic_offset_table = 1;
13413 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13414 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13415 if (TARGET_64BIT && INTVAL (operands[3]) >= 0)
13417 rtx reg = gen_rtx_REG (QImode, 0);
13418 emit_move_insn (reg, operands[3]);
13419 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13421 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13424 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13429 (define_expand "call_value_exp"
13430 [(set (match_operand 0 "" "")
13431 (call (match_operand:QI 1 "" "")
13432 (match_operand:SI 2 "" "")))]
13436 ;; Call subroutine returning any type.
13438 (define_expand "untyped_call"
13439 [(parallel [(call (match_operand 0 "" "")
13441 (match_operand 1 "" "")
13442 (match_operand 2 "" "")])]
13448 /* In order to give reg-stack an easier job in validating two
13449 coprocessor registers as containing a possible return value,
13450 simply pretend the untyped call returns a complex long double
13453 emit_call_insn (TARGET_80387
13454 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13455 operands[0], const0_rtx,
13456 GEN_INT (SSE_REGPARM_MAX - 1))
13457 : gen_call (operands[0], const0_rtx,
13458 GEN_INT (SSE_REGPARM_MAX - 1)));
13460 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13462 rtx set = XVECEXP (operands[2], 0, i);
13463 emit_move_insn (SET_DEST (set), SET_SRC (set));
13466 /* The optimizer does not know that the call sets the function value
13467 registers we stored in the result block. We avoid problems by
13468 claiming that all hard registers are used and clobbered at this
13470 emit_insn (gen_blockage ());
13475 ;; Prologue and epilogue instructions
13477 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13478 ;; all of memory. This blocks insns from being moved across this point.
13480 (define_insn "blockage"
13481 [(unspec_volatile [(const_int 0)] 0)]
13484 [(set_attr "length" "0")])
13486 ;; Insn emitted into the body of a function to return from a function.
13487 ;; This is only done if the function's epilogue is known to be simple.
13488 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13490 (define_expand "return"
13492 "ix86_can_use_return_insn_p ()"
13495 if (current_function_pops_args)
13497 rtx popc = GEN_INT (current_function_pops_args);
13498 emit_jump_insn (gen_return_pop_internal (popc));
13503 (define_insn "return_internal"
13507 [(set_attr "length" "1")
13508 (set_attr "length_immediate" "0")
13509 (set_attr "modrm" "0")])
13511 (define_insn "return_pop_internal"
13513 (use (match_operand:SI 0 "const_int_operand" ""))]
13516 [(set_attr "length" "3")
13517 (set_attr "length_immediate" "2")
13518 (set_attr "modrm" "0")])
13520 (define_insn "return_indirect_internal"
13522 (use (match_operand:SI 0 "register_operand" "r"))]
13525 [(set_attr "type" "ibr")
13526 (set_attr "length_immediate" "0")])
13532 [(set_attr "length" "1")
13533 (set_attr "length_immediate" "0")
13534 (set_attr "modrm" "0")
13535 (set_attr "ppro_uops" "one")])
13537 (define_expand "prologue"
13540 "ix86_expand_prologue (); DONE;")
13542 (define_insn "prologue_set_got"
13543 [(set (match_operand:SI 0 "register_operand" "=r")
13544 (unspec_volatile:SI
13545 [(plus:SI (match_dup 0)
13546 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
13547 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
13548 (clobber (reg:CC 17))]
13552 if (GET_CODE (operands[2]) == LABEL_REF)
13553 operands[2] = XEXP (operands[2], 0);
13554 if (TARGET_DEEP_BRANCH_PREDICTION)
13555 return \"add{l}\\t{%1, %0|%0, %1}\";
13557 return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
13559 [(set_attr "type" "alu")
13560 ; Since this insn may have two constant operands, we must set the
13562 (set_attr "length_immediate" "4")
13563 (set_attr "mode" "SI")])
13565 (define_insn "prologue_get_pc"
13566 [(set (match_operand:SI 0 "register_operand" "=r")
13567 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
13571 if (GET_CODE (operands[1]) == LABEL_REF)
13572 operands[1] = XEXP (operands[1], 0);
13573 output_asm_insn (\"call\\t%X1\", operands);
13574 if (! TARGET_DEEP_BRANCH_PREDICTION)
13576 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
13577 CODE_LABEL_NUMBER (operands[1]));
13581 [(set_attr "type" "multi")])
13583 (define_expand "epilogue"
13586 "ix86_expand_epilogue (1); DONE;")
13588 (define_expand "sibcall_epilogue"
13591 "ix86_expand_epilogue (0); DONE;")
13593 (define_expand "eh_return"
13594 [(use (match_operand 0 "register_operand" ""))
13595 (use (match_operand 1 "register_operand" ""))]
13599 rtx tmp, sa = operands[0], ra = operands[1];
13601 /* Tricky bit: we write the address of the handler to which we will
13602 be returning into someone else's stack frame, one word below the
13603 stack address we wish to restore. */
13604 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13605 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13606 tmp = gen_rtx_MEM (Pmode, tmp);
13607 emit_move_insn (tmp, ra);
13609 emit_insn (gen_eh_return_1 (sa));
13614 (define_insn_and_split "eh_return_1"
13615 [(unspec_volatile [(match_operand 0 "register_operand" "c")] 13)]
13620 "ix86_expand_epilogue (2); DONE;")
13622 (define_insn "leave"
13623 [(set (reg:SI 7) (reg:SI 6))
13624 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
13627 [(set_attr "length_immediate" "0")
13628 (set_attr "length" "1")
13629 (set_attr "modrm" "0")
13630 (set_attr "modrm" "0")
13631 (set_attr "athlon_decode" "vector")
13632 (set_attr "ppro_uops" "few")])
13634 (define_insn "leave_rex64"
13635 [(set (reg:DI 7) (reg:DI 6))
13636 (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7))))]
13639 [(set_attr "length_immediate" "0")
13640 (set_attr "length" "1")
13641 (set_attr "modrm" "0")
13642 (set_attr "modrm" "0")
13643 (set_attr "athlon_decode" "vector")
13644 (set_attr "ppro_uops" "few")])
13646 (define_expand "ffssi2"
13647 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13648 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13652 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13653 rtx in = operands[1];
13657 emit_move_insn (tmp, constm1_rtx);
13658 emit_insn (gen_ffssi_1 (out, in));
13659 emit_insn (gen_rtx_SET (VOIDmode, out,
13660 gen_rtx_IF_THEN_ELSE (SImode,
13661 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13665 emit_insn (gen_addsi3 (out, out, const1_rtx));
13666 emit_move_insn (operands[0], out);
13669 /* Pentium bsf instruction is extremly slow. The following code is
13670 recommended by the Intel Optimizing Manual as a reasonable replacement:
13674 MOV DWORD PTR [TEMP+4],ECX
13677 MOV DWORD PTR [TEMP],EAX
13678 FILD QWORD PTR [TEMP]
13679 FSTP QWORD PTR [TEMP]
13680 WAIT ; WAIT only needed for compatibility with
13681 ; earlier processors
13682 MOV ECX, DWORD PTR [TEMP+4]
13685 TEST EAX,EAX ; clear zero flag
13687 Following piece of code expand ffs to similar beast.
13690 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13692 rtx label = gen_label_rtx ();
13694 rtx mem = assign_386_stack_local (DImode, 0);
13695 rtx fptmp = gen_reg_rtx (DFmode);
13696 split_di (&mem, 1, &lo, &hi);
13698 emit_move_insn (out, const0_rtx);
13700 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, 0, label);
13702 emit_move_insn (hi, out);
13703 emit_insn (gen_subsi3 (out, out, in));
13704 emit_insn (gen_andsi3 (out, out, in));
13705 emit_move_insn (lo, out);
13706 emit_insn (gen_floatdidf2 (fptmp,mem));
13707 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13708 emit_move_insn (out, hi);
13709 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13710 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13712 emit_label (label);
13713 LABEL_NUSES (label) = 1;
13715 emit_move_insn (operands[0], out);
13719 emit_move_insn (tmp, const0_rtx);
13720 emit_insn (gen_ffssi_1 (out, in));
13721 emit_insn (gen_rtx_SET (VOIDmode,
13722 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13723 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13725 emit_insn (gen_negsi2 (tmp, tmp));
13726 emit_insn (gen_iorsi3 (out, out, tmp));
13727 emit_insn (gen_addsi3 (out, out, const1_rtx));
13728 emit_move_insn (operands[0], out);
13733 (define_insn "ffssi_1"
13735 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13737 (set (match_operand:SI 0 "register_operand" "=r")
13738 (unspec:SI [(match_dup 1)] 5))]
13740 "bsf{l}\\t{%1, %0|%0, %1}"
13741 [(set_attr "prefix_0f" "1")
13742 (set_attr "ppro_uops" "few")])
13744 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13745 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13747 ;; These patterns match the binary 387 instructions for addM3, subM3,
13748 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13749 ;; SFmode. The first is the normal insn, the second the same insn but
13750 ;; with one operand a conversion, and the third the same insn but with
13751 ;; the other operand a conversion. The conversion may be SFmode or
13752 ;; SImode if the target mode DFmode, but only SImode if the target mode
13755 ;; Gcc is slightly more smart about handling normal two address instructions
13756 ;; so use special patterns for add and mull.
13757 (define_insn "*fop_sf_comm"
13758 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13759 (match_operator:SF 3 "binary_fp_operator"
13760 [(match_operand:SF 1 "register_operand" "%0,0")
13761 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13762 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13763 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13764 "* return output_387_binary_op (insn, operands);"
13765 [(set (attr "type")
13766 (if_then_else (eq_attr "alternative" "1")
13767 (const_string "sse")
13768 (if_then_else (match_operand:SF 3 "mult_operator" "")
13769 (const_string "fmul")
13770 (const_string "fop"))))
13771 (set_attr "mode" "SF")])
13773 (define_insn "*fop_sf_comm_sse"
13774 [(set (match_operand:SF 0 "register_operand" "=x")
13775 (match_operator:SF 3 "binary_fp_operator"
13776 [(match_operand:SF 1 "register_operand" "%0")
13777 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13778 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13779 "* return output_387_binary_op (insn, operands);"
13780 [(set_attr "type" "sse")
13781 (set_attr "mode" "SF")])
13783 (define_insn "*fop_df_comm"
13784 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13785 (match_operator:DF 3 "binary_fp_operator"
13786 [(match_operand:DF 1 "register_operand" "%0,0")
13787 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13788 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13789 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13790 "* return output_387_binary_op (insn, operands);"
13791 [(set (attr "type")
13792 (if_then_else (eq_attr "alternative" "1")
13793 (const_string "sse")
13794 (if_then_else (match_operand:SF 3 "mult_operator" "")
13795 (const_string "fmul")
13796 (const_string "fop"))))
13797 (set_attr "mode" "DF")])
13799 (define_insn "*fop_df_comm_sse"
13800 [(set (match_operand:DF 0 "register_operand" "=Y")
13801 (match_operator:DF 3 "binary_fp_operator"
13802 [(match_operand:DF 1 "register_operand" "%0")
13803 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13805 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13806 "* return output_387_binary_op (insn, operands);"
13807 [(set_attr "type" "sse")
13808 (set_attr "mode" "DF")])
13810 (define_insn "*fop_xf_comm"
13811 [(set (match_operand:XF 0 "register_operand" "=f")
13812 (match_operator:XF 3 "binary_fp_operator"
13813 [(match_operand:XF 1 "register_operand" "%0")
13814 (match_operand:XF 2 "register_operand" "f")]))]
13815 "TARGET_80387 && !TARGET_64BIT
13816 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13817 "* return output_387_binary_op (insn, operands);"
13818 [(set (attr "type")
13819 (if_then_else (match_operand:XF 3 "mult_operator" "")
13820 (const_string "fmul")
13821 (const_string "fop")))
13822 (set_attr "mode" "XF")])
13824 (define_insn "*fop_tf_comm"
13825 [(set (match_operand:TF 0 "register_operand" "=f")
13826 (match_operator:TF 3 "binary_fp_operator"
13827 [(match_operand:TF 1 "register_operand" "%0")
13828 (match_operand:TF 2 "register_operand" "f")]))]
13829 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13830 "* return output_387_binary_op (insn, operands);"
13831 [(set (attr "type")
13832 (if_then_else (match_operand:TF 3 "mult_operator" "")
13833 (const_string "fmul")
13834 (const_string "fop")))
13835 (set_attr "mode" "XF")])
13837 (define_insn "*fop_sf_1"
13838 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
13839 (match_operator:SF 3 "binary_fp_operator"
13840 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
13841 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
13842 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13843 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13844 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13845 "* return output_387_binary_op (insn, operands);"
13846 [(set (attr "type")
13847 (cond [(eq_attr "alternative" "2")
13848 (const_string "sse")
13849 (match_operand:SF 3 "mult_operator" "")
13850 (const_string "fmul")
13851 (match_operand:SF 3 "div_operator" "")
13852 (const_string "fdiv")
13854 (const_string "fop")))
13855 (set_attr "mode" "SF")])
13857 (define_insn "*fop_sf_1_sse"
13858 [(set (match_operand:SF 0 "register_operand" "=x")
13859 (match_operator:SF 3 "binary_fp_operator"
13860 [(match_operand:SF 1 "register_operand" "0")
13861 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13863 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13864 "* return output_387_binary_op (insn, operands);"
13865 [(set_attr "type" "sse")
13866 (set_attr "mode" "SF")])
13868 ;; ??? Add SSE splitters for these!
13869 (define_insn "*fop_sf_2"
13870 [(set (match_operand:SF 0 "register_operand" "=f,f")
13871 (match_operator:SF 3 "binary_fp_operator"
13872 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13873 (match_operand:SF 2 "register_operand" "0,0")]))]
13874 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13875 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13876 [(set (attr "type")
13877 (cond [(match_operand:SF 3 "mult_operator" "")
13878 (const_string "fmul")
13879 (match_operand:SF 3 "div_operator" "")
13880 (const_string "fdiv")
13882 (const_string "fop")))
13883 (set_attr "fp_int_src" "true")
13884 (set_attr "ppro_uops" "many")
13885 (set_attr "mode" "SI")])
13887 (define_insn "*fop_sf_3"
13888 [(set (match_operand:SF 0 "register_operand" "=f,f")
13889 (match_operator:SF 3 "binary_fp_operator"
13890 [(match_operand:SF 1 "register_operand" "0,0")
13891 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13892 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13893 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13894 [(set (attr "type")
13895 (cond [(match_operand:SF 3 "mult_operator" "")
13896 (const_string "fmul")
13897 (match_operand:SF 3 "div_operator" "")
13898 (const_string "fdiv")
13900 (const_string "fop")))
13901 (set_attr "fp_int_src" "true")
13902 (set_attr "ppro_uops" "many")
13903 (set_attr "mode" "SI")])
13905 (define_insn "*fop_df_1"
13906 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
13907 (match_operator:DF 3 "binary_fp_operator"
13908 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
13909 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
13910 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13911 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13912 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13913 "* return output_387_binary_op (insn, operands);"
13914 [(set (attr "type")
13915 (cond [(eq_attr "alternative" "2")
13916 (const_string "sse")
13917 (match_operand:DF 3 "mult_operator" "")
13918 (const_string "fmul")
13919 (match_operand:DF 3 "div_operator" "")
13920 (const_string "fdiv")
13922 (const_string "fop")))
13923 (set_attr "mode" "DF")])
13925 (define_insn "*fop_df_1_sse"
13926 [(set (match_operand:DF 0 "register_operand" "=Y")
13927 (match_operator:DF 3 "binary_fp_operator"
13928 [(match_operand:DF 1 "register_operand" "0")
13929 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13931 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13932 "* return output_387_binary_op (insn, operands);"
13933 [(set_attr "type" "sse")])
13935 ;; ??? Add SSE splitters for these!
13936 (define_insn "*fop_df_2"
13937 [(set (match_operand:DF 0 "register_operand" "=f,f")
13938 (match_operator:DF 3 "binary_fp_operator"
13939 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13940 (match_operand:DF 2 "register_operand" "0,0")]))]
13941 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13942 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13943 [(set (attr "type")
13944 (cond [(match_operand:DF 3 "mult_operator" "")
13945 (const_string "fmul")
13946 (match_operand:DF 3 "div_operator" "")
13947 (const_string "fdiv")
13949 (const_string "fop")))
13950 (set_attr "fp_int_src" "true")
13951 (set_attr "ppro_uops" "many")
13952 (set_attr "mode" "SI")])
13954 (define_insn "*fop_df_3"
13955 [(set (match_operand:DF 0 "register_operand" "=f,f")
13956 (match_operator:DF 3 "binary_fp_operator"
13957 [(match_operand:DF 1 "register_operand" "0,0")
13958 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13959 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13960 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13961 [(set (attr "type")
13962 (cond [(match_operand:DF 3 "mult_operator" "")
13963 (const_string "fmul")
13964 (match_operand:DF 3 "div_operator" "")
13965 (const_string "fdiv")
13967 (const_string "fop")))
13968 (set_attr "fp_int_src" "true")
13969 (set_attr "ppro_uops" "many")
13970 (set_attr "mode" "SI")])
13972 (define_insn "*fop_df_4"
13973 [(set (match_operand:DF 0 "register_operand" "=f,f")
13974 (match_operator:DF 3 "binary_fp_operator"
13975 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13976 (match_operand:DF 2 "register_operand" "0,f")]))]
13978 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13979 "* return output_387_binary_op (insn, operands);"
13980 [(set (attr "type")
13981 (cond [(match_operand:DF 3 "mult_operator" "")
13982 (const_string "fmul")
13983 (match_operand:DF 3 "div_operator" "")
13984 (const_string "fdiv")
13986 (const_string "fop")))
13987 (set_attr "mode" "SF")])
13989 (define_insn "*fop_df_5"
13990 [(set (match_operand:DF 0 "register_operand" "=f,f")
13991 (match_operator:DF 3 "binary_fp_operator"
13992 [(match_operand:DF 1 "register_operand" "0,f")
13994 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13995 "TARGET_80387 && !TARGET_SSE2"
13996 "* return output_387_binary_op (insn, operands);"
13997 [(set (attr "type")
13998 (cond [(match_operand:DF 3 "mult_operator" "")
13999 (const_string "fmul")
14000 (match_operand:DF 3 "div_operator" "")
14001 (const_string "fdiv")
14003 (const_string "fop")))
14004 (set_attr "mode" "SF")])
14006 (define_insn "*fop_xf_1"
14007 [(set (match_operand:XF 0 "register_operand" "=f,f")
14008 (match_operator:XF 3 "binary_fp_operator"
14009 [(match_operand:XF 1 "register_operand" "0,f")
14010 (match_operand:XF 2 "register_operand" "f,0")]))]
14011 "TARGET_80387 && !TARGET_64BIT
14012 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14013 "* return output_387_binary_op (insn, operands);"
14014 [(set (attr "type")
14015 (cond [(match_operand:XF 3 "mult_operator" "")
14016 (const_string "fmul")
14017 (match_operand:XF 3 "div_operator" "")
14018 (const_string "fdiv")
14020 (const_string "fop")))
14021 (set_attr "mode" "XF")])
14023 (define_insn "*fop_tf_1"
14024 [(set (match_operand:TF 0 "register_operand" "=f,f")
14025 (match_operator:TF 3 "binary_fp_operator"
14026 [(match_operand:TF 1 "register_operand" "0,f")
14027 (match_operand:TF 2 "register_operand" "f,0")]))]
14029 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14030 "* return output_387_binary_op (insn, operands);"
14031 [(set (attr "type")
14032 (cond [(match_operand:TF 3 "mult_operator" "")
14033 (const_string "fmul")
14034 (match_operand:TF 3 "div_operator" "")
14035 (const_string "fdiv")
14037 (const_string "fop")))
14038 (set_attr "mode" "XF")])
14040 (define_insn "*fop_xf_2"
14041 [(set (match_operand:XF 0 "register_operand" "=f,f")
14042 (match_operator:XF 3 "binary_fp_operator"
14043 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14044 (match_operand:XF 2 "register_operand" "0,0")]))]
14045 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
14046 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14047 [(set (attr "type")
14048 (cond [(match_operand:XF 3 "mult_operator" "")
14049 (const_string "fmul")
14050 (match_operand:XF 3 "div_operator" "")
14051 (const_string "fdiv")
14053 (const_string "fop")))
14054 (set_attr "fp_int_src" "true")
14055 (set_attr "mode" "SI")
14056 (set_attr "ppro_uops" "many")])
14058 (define_insn "*fop_tf_2"
14059 [(set (match_operand:TF 0 "register_operand" "=f,f")
14060 (match_operator:TF 3 "binary_fp_operator"
14061 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14062 (match_operand:TF 2 "register_operand" "0,0")]))]
14063 "TARGET_80387 && TARGET_USE_FIOP"
14064 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14065 [(set (attr "type")
14066 (cond [(match_operand:TF 3 "mult_operator" "")
14067 (const_string "fmul")
14068 (match_operand:TF 3 "div_operator" "")
14069 (const_string "fdiv")
14071 (const_string "fop")))
14072 (set_attr "fp_int_src" "true")
14073 (set_attr "mode" "SI")
14074 (set_attr "ppro_uops" "many")])
14076 (define_insn "*fop_xf_3"
14077 [(set (match_operand:XF 0 "register_operand" "=f,f")
14078 (match_operator:XF 3 "binary_fp_operator"
14079 [(match_operand:XF 1 "register_operand" "0,0")
14080 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14081 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
14082 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14083 [(set (attr "type")
14084 (cond [(match_operand:XF 3 "mult_operator" "")
14085 (const_string "fmul")
14086 (match_operand:XF 3 "div_operator" "")
14087 (const_string "fdiv")
14089 (const_string "fop")))
14090 (set_attr "fp_int_src" "true")
14091 (set_attr "mode" "SI")
14092 (set_attr "ppro_uops" "many")])
14094 (define_insn "*fop_tf_3"
14095 [(set (match_operand:TF 0 "register_operand" "=f,f")
14096 (match_operator:TF 3 "binary_fp_operator"
14097 [(match_operand:TF 1 "register_operand" "0,0")
14098 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14099 "TARGET_80387 && TARGET_USE_FIOP"
14100 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14101 [(set (attr "type")
14102 (cond [(match_operand:TF 3 "mult_operator" "")
14103 (const_string "fmul")
14104 (match_operand:TF 3 "div_operator" "")
14105 (const_string "fdiv")
14107 (const_string "fop")))
14108 (set_attr "fp_int_src" "true")
14109 (set_attr "mode" "SI")
14110 (set_attr "ppro_uops" "many")])
14112 (define_insn "*fop_xf_4"
14113 [(set (match_operand:XF 0 "register_operand" "=f,f")
14114 (match_operator:XF 3 "binary_fp_operator"
14115 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14116 (match_operand:XF 2 "register_operand" "0,f")]))]
14117 "TARGET_80387 && !TARGET_64BIT"
14118 "* return output_387_binary_op (insn, operands);"
14119 [(set (attr "type")
14120 (cond [(match_operand:XF 3 "mult_operator" "")
14121 (const_string "fmul")
14122 (match_operand:XF 3 "div_operator" "")
14123 (const_string "fdiv")
14125 (const_string "fop")))
14126 (set_attr "mode" "SF")])
14128 (define_insn "*fop_tf_4"
14129 [(set (match_operand:TF 0 "register_operand" "=f,f")
14130 (match_operator:TF 3 "binary_fp_operator"
14131 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14132 (match_operand:TF 2 "register_operand" "0,f")]))]
14134 "* return output_387_binary_op (insn, operands);"
14135 [(set (attr "type")
14136 (cond [(match_operand:TF 3 "mult_operator" "")
14137 (const_string "fmul")
14138 (match_operand:TF 3 "div_operator" "")
14139 (const_string "fdiv")
14141 (const_string "fop")))
14142 (set_attr "mode" "SF")])
14144 (define_insn "*fop_xf_5"
14145 [(set (match_operand:XF 0 "register_operand" "=f,f")
14146 (match_operator:XF 3 "binary_fp_operator"
14147 [(match_operand:XF 1 "register_operand" "0,f")
14149 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14150 "TARGET_80387 && !TARGET_64BIT"
14151 "* return output_387_binary_op (insn, operands);"
14152 [(set (attr "type")
14153 (cond [(match_operand:XF 3 "mult_operator" "")
14154 (const_string "fmul")
14155 (match_operand:XF 3 "div_operator" "")
14156 (const_string "fdiv")
14158 (const_string "fop")))
14159 (set_attr "mode" "SF")])
14161 (define_insn "*fop_tf_5"
14162 [(set (match_operand:TF 0 "register_operand" "=f,f")
14163 (match_operator:TF 3 "binary_fp_operator"
14164 [(match_operand:TF 1 "register_operand" "0,f")
14166 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14168 "* return output_387_binary_op (insn, operands);"
14169 [(set (attr "type")
14170 (cond [(match_operand:TF 3 "mult_operator" "")
14171 (const_string "fmul")
14172 (match_operand:TF 3 "div_operator" "")
14173 (const_string "fdiv")
14175 (const_string "fop")))
14176 (set_attr "mode" "SF")])
14178 (define_insn "*fop_xf_6"
14179 [(set (match_operand:XF 0 "register_operand" "=f,f")
14180 (match_operator:XF 3 "binary_fp_operator"
14181 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14182 (match_operand:XF 2 "register_operand" "0,f")]))]
14183 "TARGET_80387 && !TARGET_64BIT"
14184 "* return output_387_binary_op (insn, operands);"
14185 [(set (attr "type")
14186 (cond [(match_operand:XF 3 "mult_operator" "")
14187 (const_string "fmul")
14188 (match_operand:XF 3 "div_operator" "")
14189 (const_string "fdiv")
14191 (const_string "fop")))
14192 (set_attr "mode" "DF")])
14194 (define_insn "*fop_tf_6"
14195 [(set (match_operand:TF 0 "register_operand" "=f,f")
14196 (match_operator:TF 3 "binary_fp_operator"
14197 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14198 (match_operand:TF 2 "register_operand" "0,f")]))]
14200 "* return output_387_binary_op (insn, operands);"
14201 [(set (attr "type")
14202 (cond [(match_operand:TF 3 "mult_operator" "")
14203 (const_string "fmul")
14204 (match_operand:TF 3 "div_operator" "")
14205 (const_string "fdiv")
14207 (const_string "fop")))
14208 (set_attr "mode" "DF")])
14210 (define_insn "*fop_xf_7"
14211 [(set (match_operand:XF 0 "register_operand" "=f,f")
14212 (match_operator:XF 3 "binary_fp_operator"
14213 [(match_operand:XF 1 "register_operand" "0,f")
14215 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14216 "TARGET_80387 && !TARGET_64BIT"
14217 "* return output_387_binary_op (insn, operands);"
14218 [(set (attr "type")
14219 (cond [(match_operand:XF 3 "mult_operator" "")
14220 (const_string "fmul")
14221 (match_operand:XF 3 "div_operator" "")
14222 (const_string "fdiv")
14224 (const_string "fop")))
14225 (set_attr "mode" "DF")])
14227 (define_insn "*fop_tf_7"
14228 [(set (match_operand:TF 0 "register_operand" "=f,f")
14229 (match_operator:TF 3 "binary_fp_operator"
14230 [(match_operand:TF 1 "register_operand" "0,f")
14232 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14234 "* return output_387_binary_op (insn, operands);"
14235 [(set (attr "type")
14236 (cond [(match_operand:TF 3 "mult_operator" "")
14237 (const_string "fmul")
14238 (match_operand:TF 3 "div_operator" "")
14239 (const_string "fdiv")
14241 (const_string "fop")))
14242 (set_attr "mode" "DF")])
14245 [(set (match_operand 0 "register_operand" "")
14246 (match_operator 3 "binary_fp_operator"
14247 [(float (match_operand:SI 1 "register_operand" ""))
14248 (match_operand 2 "register_operand" "")]))]
14249 "TARGET_80387 && reload_completed
14250 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14254 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14255 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14256 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14257 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14258 GET_MODE (operands[3]),
14261 ix86_free_from_memory (GET_MODE (operands[1]));
14266 [(set (match_operand 0 "register_operand" "")
14267 (match_operator 3 "binary_fp_operator"
14268 [(match_operand 1 "register_operand" "")
14269 (float (match_operand:SI 2 "register_operand" ""))]))]
14270 "TARGET_80387 && reload_completed
14271 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14275 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14276 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14277 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14278 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14279 GET_MODE (operands[3]),
14282 ix86_free_from_memory (GET_MODE (operands[2]));
14286 ;; FPU special functions.
14288 (define_expand "sqrtsf2"
14289 [(set (match_operand:SF 0 "register_operand" "")
14290 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14291 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
14295 operands[1] = force_reg (SFmode, operands[1]);
14298 (define_insn "sqrtsf2_1"
14299 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14300 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14301 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14302 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
14305 sqrtss\\t{%1, %0|%0, %1}"
14306 [(set_attr "type" "fpspc,sse")
14307 (set_attr "mode" "SF,SF")
14308 (set_attr "athlon_decode" "direct,*")])
14310 (define_insn "sqrtsf2_1_sse_only"
14311 [(set (match_operand:SF 0 "register_operand" "=x")
14312 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14313 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14314 "sqrtss\\t{%1, %0|%0, %1}"
14315 [(set_attr "type" "sse")
14316 (set_attr "mode" "SF")
14317 (set_attr "athlon_decode" "*")])
14319 (define_insn "sqrtsf2_i387"
14320 [(set (match_operand:SF 0 "register_operand" "=f")
14321 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14322 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14323 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
14325 [(set_attr "type" "fpspc")
14326 (set_attr "mode" "SF")
14327 (set_attr "athlon_decode" "direct")])
14329 (define_expand "sqrtdf2"
14330 [(set (match_operand:DF 0 "register_operand" "")
14331 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14332 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
14336 operands[1] = force_reg (DFmode, operands[1]);
14339 (define_insn "sqrtdf2_1"
14340 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14341 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14342 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14343 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
14346 sqrtsd\\t{%1, %0|%0, %1}"
14347 [(set_attr "type" "fpspc,sse")
14348 (set_attr "mode" "DF,DF")
14349 (set_attr "athlon_decode" "direct,*")])
14351 (define_insn "sqrtdf2_1_sse_only"
14352 [(set (match_operand:DF 0 "register_operand" "=Y")
14353 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14354 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14355 "sqrtsd\\t{%1, %0|%0, %1}"
14356 [(set_attr "type" "sse")
14357 (set_attr "mode" "DF")
14358 (set_attr "athlon_decode" "*")])
14360 (define_insn "sqrtdf2_i387"
14361 [(set (match_operand:DF 0 "register_operand" "=f")
14362 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14363 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14364 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
14366 [(set_attr "type" "fpspc")
14367 (set_attr "mode" "DF")
14368 (set_attr "athlon_decode" "direct")])
14370 (define_insn "*sqrtextendsfdf2"
14371 [(set (match_operand:DF 0 "register_operand" "=f")
14372 (sqrt:DF (float_extend:DF
14373 (match_operand:SF 1 "register_operand" "0"))))]
14374 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
14376 [(set_attr "type" "fpspc")
14377 (set_attr "mode" "DF")
14378 (set_attr "athlon_decode" "direct")])
14380 (define_insn "sqrtxf2"
14381 [(set (match_operand:XF 0 "register_operand" "=f")
14382 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14383 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14384 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14386 [(set_attr "type" "fpspc")
14387 (set_attr "mode" "XF")
14388 (set_attr "athlon_decode" "direct")])
14390 (define_insn "sqrttf2"
14391 [(set (match_operand:TF 0 "register_operand" "=f")
14392 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14393 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14394 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14396 [(set_attr "type" "fpspc")
14397 (set_attr "mode" "XF")
14398 (set_attr "athlon_decode" "direct")])
14400 (define_insn "*sqrtextenddfxf2"
14401 [(set (match_operand:XF 0 "register_operand" "=f")
14402 (sqrt:XF (float_extend:XF
14403 (match_operand:DF 1 "register_operand" "0"))))]
14404 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14406 [(set_attr "type" "fpspc")
14407 (set_attr "mode" "XF")
14408 (set_attr "athlon_decode" "direct")])
14410 (define_insn "*sqrtextenddftf2"
14411 [(set (match_operand:TF 0 "register_operand" "=f")
14412 (sqrt:TF (float_extend:TF
14413 (match_operand:DF 1 "register_operand" "0"))))]
14414 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14416 [(set_attr "type" "fpspc")
14417 (set_attr "mode" "XF")
14418 (set_attr "athlon_decode" "direct")])
14420 (define_insn "*sqrtextendsfxf2"
14421 [(set (match_operand:XF 0 "register_operand" "=f")
14422 (sqrt:XF (float_extend:XF
14423 (match_operand:SF 1 "register_operand" "0"))))]
14424 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14426 [(set_attr "type" "fpspc")
14427 (set_attr "mode" "XF")
14428 (set_attr "athlon_decode" "direct")])
14430 (define_insn "*sqrtextendsftf2"
14431 [(set (match_operand:TF 0 "register_operand" "=f")
14432 (sqrt:TF (float_extend:TF
14433 (match_operand:SF 1 "register_operand" "0"))))]
14434 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14436 [(set_attr "type" "fpspc")
14437 (set_attr "mode" "XF")
14438 (set_attr "athlon_decode" "direct")])
14440 (define_insn "sindf2"
14441 [(set (match_operand:DF 0 "register_operand" "=f")
14442 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
14443 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14444 && flag_unsafe_math_optimizations"
14446 [(set_attr "type" "fpspc")
14447 (set_attr "mode" "DF")])
14449 (define_insn "sinsf2"
14450 [(set (match_operand:SF 0 "register_operand" "=f")
14451 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
14452 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14453 && flag_unsafe_math_optimizations"
14455 [(set_attr "type" "fpspc")
14456 (set_attr "mode" "SF")])
14458 (define_insn "*sinextendsfdf2"
14459 [(set (match_operand:DF 0 "register_operand" "=f")
14460 (unspec:DF [(float_extend:DF
14461 (match_operand:SF 1 "register_operand" "0"))] 1))]
14462 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14463 && flag_unsafe_math_optimizations"
14465 [(set_attr "type" "fpspc")
14466 (set_attr "mode" "DF")])
14468 (define_insn "sinxf2"
14469 [(set (match_operand:XF 0 "register_operand" "=f")
14470 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14471 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14472 && flag_unsafe_math_optimizations"
14474 [(set_attr "type" "fpspc")
14475 (set_attr "mode" "XF")])
14477 (define_insn "sintf2"
14478 [(set (match_operand:TF 0 "register_operand" "=f")
14479 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
14480 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14481 && flag_unsafe_math_optimizations"
14483 [(set_attr "type" "fpspc")
14484 (set_attr "mode" "XF")])
14486 (define_insn "cosdf2"
14487 [(set (match_operand:DF 0 "register_operand" "=f")
14488 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
14489 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14490 && flag_unsafe_math_optimizations"
14492 [(set_attr "type" "fpspc")
14493 (set_attr "mode" "DF")])
14495 (define_insn "cossf2"
14496 [(set (match_operand:SF 0 "register_operand" "=f")
14497 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
14498 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14499 && flag_unsafe_math_optimizations"
14501 [(set_attr "type" "fpspc")
14502 (set_attr "mode" "SF")])
14504 (define_insn "*cosextendsfdf2"
14505 [(set (match_operand:DF 0 "register_operand" "=f")
14506 (unspec:DF [(float_extend:DF
14507 (match_operand:SF 1 "register_operand" "0"))] 2))]
14508 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14509 && flag_unsafe_math_optimizations"
14511 [(set_attr "type" "fpspc")
14512 (set_attr "mode" "DF")])
14514 (define_insn "cosxf2"
14515 [(set (match_operand:XF 0 "register_operand" "=f")
14516 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
14517 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14518 && flag_unsafe_math_optimizations"
14520 [(set_attr "type" "fpspc")
14521 (set_attr "mode" "XF")])
14523 (define_insn "costf2"
14524 [(set (match_operand:TF 0 "register_operand" "=f")
14525 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
14526 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14527 && flag_unsafe_math_optimizations"
14529 [(set_attr "type" "fpspc")
14530 (set_attr "mode" "XF")])
14532 ;; Block operation instructions
14535 [(set (reg:SI 19) (const_int 0))]
14538 [(set_attr "type" "cld")])
14540 (define_expand "movstrsi"
14541 [(use (match_operand:BLK 0 "memory_operand" ""))
14542 (use (match_operand:BLK 1 "memory_operand" ""))
14543 (use (match_operand:SI 2 "nonmemory_operand" ""))
14544 (use (match_operand:SI 3 "const_int_operand" ""))]
14548 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14554 (define_expand "movstrdi"
14555 [(use (match_operand:BLK 0 "memory_operand" ""))
14556 (use (match_operand:BLK 1 "memory_operand" ""))
14557 (use (match_operand:DI 2 "nonmemory_operand" ""))
14558 (use (match_operand:DI 3 "const_int_operand" ""))]
14562 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14568 ;; Most CPUs don't like single string operations
14569 ;; Handle this case here to simplify previous expander.
14571 (define_expand "strmovdi_rex64"
14572 [(set (match_dup 2)
14573 (mem:DI (match_operand:DI 1 "register_operand" "")))
14574 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14576 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14577 (clobber (reg:CC 17))])
14578 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14579 (clobber (reg:CC 17))])]
14583 if (TARGET_SINGLE_STRINGOP || optimize_size)
14585 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14590 operands[2] = gen_reg_rtx (DImode);
14594 (define_expand "strmovsi"
14595 [(set (match_dup 2)
14596 (mem:SI (match_operand:SI 1 "register_operand" "")))
14597 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14599 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14600 (clobber (reg:CC 17))])
14601 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14602 (clobber (reg:CC 17))])]
14608 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14611 if (TARGET_SINGLE_STRINGOP || optimize_size)
14613 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14618 operands[2] = gen_reg_rtx (SImode);
14621 (define_expand "strmovsi_rex64"
14622 [(set (match_dup 2)
14623 (mem:SI (match_operand:DI 1 "register_operand" "")))
14624 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14626 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14627 (clobber (reg:CC 17))])
14628 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14629 (clobber (reg:CC 17))])]
14633 if (TARGET_SINGLE_STRINGOP || optimize_size)
14635 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14640 operands[2] = gen_reg_rtx (SImode);
14643 (define_expand "strmovhi"
14644 [(set (match_dup 2)
14645 (mem:HI (match_operand:SI 1 "register_operand" "")))
14646 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14648 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14649 (clobber (reg:CC 17))])
14650 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14651 (clobber (reg:CC 17))])]
14657 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14660 if (TARGET_SINGLE_STRINGOP || optimize_size)
14662 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14667 operands[2] = gen_reg_rtx (HImode);
14670 (define_expand "strmovhi_rex64"
14671 [(set (match_dup 2)
14672 (mem:HI (match_operand:DI 1 "register_operand" "")))
14673 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14675 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14676 (clobber (reg:CC 17))])
14677 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14678 (clobber (reg:CC 17))])]
14682 if (TARGET_SINGLE_STRINGOP || optimize_size)
14684 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14689 operands[2] = gen_reg_rtx (HImode);
14692 (define_expand "strmovqi"
14693 [(set (match_dup 2)
14694 (mem:QI (match_operand:SI 1 "register_operand" "")))
14695 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14697 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14698 (clobber (reg:CC 17))])
14699 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14700 (clobber (reg:CC 17))])]
14706 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14709 if (TARGET_SINGLE_STRINGOP || optimize_size)
14711 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14716 operands[2] = gen_reg_rtx (QImode);
14719 (define_expand "strmovqi_rex64"
14720 [(set (match_dup 2)
14721 (mem:QI (match_operand:DI 1 "register_operand" "")))
14722 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14724 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14725 (clobber (reg:CC 17))])
14726 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14727 (clobber (reg:CC 17))])]
14731 if (TARGET_SINGLE_STRINGOP || optimize_size)
14733 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14738 operands[2] = gen_reg_rtx (QImode);
14741 (define_insn "strmovdi_rex_1"
14742 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14743 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14744 (set (match_operand:DI 0 "register_operand" "=D")
14745 (plus:DI (match_dup 2)
14747 (set (match_operand:DI 1 "register_operand" "=S")
14748 (plus:DI (match_dup 3)
14751 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14753 [(set_attr "type" "str")
14754 (set_attr "mode" "DI")
14755 (set_attr "memory" "both")])
14757 (define_insn "strmovsi_1"
14758 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14759 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14760 (set (match_operand:SI 0 "register_operand" "=D")
14761 (plus:SI (match_dup 2)
14763 (set (match_operand:SI 1 "register_operand" "=S")
14764 (plus:SI (match_dup 3)
14767 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14769 [(set_attr "type" "str")
14770 (set_attr "mode" "SI")
14771 (set_attr "memory" "both")])
14773 (define_insn "strmovsi_rex_1"
14774 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
14775 (mem:SI (match_operand:DI 3 "register_operand" "1")))
14776 (set (match_operand:DI 0 "register_operand" "=D")
14777 (plus:DI (match_dup 2)
14779 (set (match_operand:DI 1 "register_operand" "=S")
14780 (plus:DI (match_dup 3)
14783 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14785 [(set_attr "type" "str")
14786 (set_attr "mode" "SI")
14787 (set_attr "memory" "both")])
14789 (define_insn "strmovhi_1"
14790 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
14791 (mem:HI (match_operand:SI 3 "register_operand" "1")))
14792 (set (match_operand:SI 0 "register_operand" "=D")
14793 (plus:SI (match_dup 2)
14795 (set (match_operand:SI 1 "register_operand" "=S")
14796 (plus:SI (match_dup 3)
14799 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14801 [(set_attr "type" "str")
14802 (set_attr "memory" "both")
14803 (set_attr "mode" "HI")])
14805 (define_insn "strmovhi_rex_1"
14806 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
14807 (mem:HI (match_operand:DI 3 "register_operand" "1")))
14808 (set (match_operand:DI 0 "register_operand" "=D")
14809 (plus:DI (match_dup 2)
14811 (set (match_operand:DI 1 "register_operand" "=S")
14812 (plus:DI (match_dup 3)
14815 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14817 [(set_attr "type" "str")
14818 (set_attr "memory" "both")
14819 (set_attr "mode" "HI")])
14821 (define_insn "strmovqi_1"
14822 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
14823 (mem:QI (match_operand:SI 3 "register_operand" "1")))
14824 (set (match_operand:SI 0 "register_operand" "=D")
14825 (plus:SI (match_dup 2)
14827 (set (match_operand:SI 1 "register_operand" "=S")
14828 (plus:SI (match_dup 3)
14831 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14833 [(set_attr "type" "str")
14834 (set_attr "memory" "both")
14835 (set_attr "mode" "QI")])
14837 (define_insn "strmovqi_rex_1"
14838 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
14839 (mem:QI (match_operand:DI 3 "register_operand" "1")))
14840 (set (match_operand:DI 0 "register_operand" "=D")
14841 (plus:DI (match_dup 2)
14843 (set (match_operand:DI 1 "register_operand" "=S")
14844 (plus:DI (match_dup 3)
14847 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14849 [(set_attr "type" "str")
14850 (set_attr "memory" "both")
14851 (set_attr "mode" "QI")])
14853 (define_insn "rep_movdi_rex64"
14854 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14855 (set (match_operand:DI 0 "register_operand" "=D")
14856 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14858 (match_operand:DI 3 "register_operand" "0")))
14859 (set (match_operand:DI 1 "register_operand" "=S")
14860 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
14861 (match_operand:DI 4 "register_operand" "1")))
14862 (set (mem:BLK (match_dup 3))
14863 (mem:BLK (match_dup 4)))
14864 (use (match_dup 5))
14867 "rep\;movsq|rep movsq"
14868 [(set_attr "type" "str")
14869 (set_attr "prefix_rep" "1")
14870 (set_attr "memory" "both")
14871 (set_attr "mode" "DI")])
14873 (define_insn "rep_movsi"
14874 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14875 (set (match_operand:SI 0 "register_operand" "=D")
14876 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
14878 (match_operand:SI 3 "register_operand" "0")))
14879 (set (match_operand:SI 1 "register_operand" "=S")
14880 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
14881 (match_operand:SI 4 "register_operand" "1")))
14882 (set (mem:BLK (match_dup 3))
14883 (mem:BLK (match_dup 4)))
14884 (use (match_dup 5))
14887 "rep\;movsl|rep movsd"
14888 [(set_attr "type" "str")
14889 (set_attr "prefix_rep" "1")
14890 (set_attr "memory" "both")
14891 (set_attr "mode" "SI")])
14893 (define_insn "rep_movsi_rex64"
14894 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14895 (set (match_operand:DI 0 "register_operand" "=D")
14896 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14898 (match_operand:DI 3 "register_operand" "0")))
14899 (set (match_operand:DI 1 "register_operand" "=S")
14900 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
14901 (match_operand:DI 4 "register_operand" "1")))
14902 (set (mem:BLK (match_dup 3))
14903 (mem:BLK (match_dup 4)))
14904 (use (match_dup 5))
14907 "rep\;movsl|rep movsd"
14908 [(set_attr "type" "str")
14909 (set_attr "prefix_rep" "1")
14910 (set_attr "memory" "both")
14911 (set_attr "mode" "SI")])
14913 (define_insn "rep_movqi"
14914 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14915 (set (match_operand:SI 0 "register_operand" "=D")
14916 (plus:SI (match_operand:SI 3 "register_operand" "0")
14917 (match_operand:SI 5 "register_operand" "2")))
14918 (set (match_operand:SI 1 "register_operand" "=S")
14919 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
14920 (set (mem:BLK (match_dup 3))
14921 (mem:BLK (match_dup 4)))
14922 (use (match_dup 5))
14925 "rep\;movsb|rep movsb"
14926 [(set_attr "type" "str")
14927 (set_attr "prefix_rep" "1")
14928 (set_attr "memory" "both")
14929 (set_attr "mode" "SI")])
14931 (define_insn "rep_movqi_rex64"
14932 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14933 (set (match_operand:DI 0 "register_operand" "=D")
14934 (plus:DI (match_operand:DI 3 "register_operand" "0")
14935 (match_operand:DI 5 "register_operand" "2")))
14936 (set (match_operand:DI 1 "register_operand" "=S")
14937 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
14938 (set (mem:BLK (match_dup 3))
14939 (mem:BLK (match_dup 4)))
14940 (use (match_dup 5))
14943 "rep\;movsb|rep movsb"
14944 [(set_attr "type" "str")
14945 (set_attr "prefix_rep" "1")
14946 (set_attr "memory" "both")
14947 (set_attr "mode" "SI")])
14949 (define_expand "clrstrsi"
14950 [(use (match_operand:BLK 0 "memory_operand" ""))
14951 (use (match_operand:SI 1 "nonmemory_operand" ""))
14952 (use (match_operand 2 "const_int_operand" ""))]
14956 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14962 (define_expand "clrstrdi"
14963 [(use (match_operand:BLK 0 "memory_operand" ""))
14964 (use (match_operand:DI 1 "nonmemory_operand" ""))
14965 (use (match_operand 2 "const_int_operand" ""))]
14969 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14975 ;; Most CPUs don't like single string operations
14976 ;; Handle this case here to simplify previous expander.
14978 (define_expand "strsetdi_rex64"
14979 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
14980 (match_operand:DI 1 "register_operand" ""))
14981 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14982 (clobber (reg:CC 17))])]
14986 if (TARGET_SINGLE_STRINGOP || optimize_size)
14988 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
14993 (define_expand "strsetsi"
14994 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
14995 (match_operand:SI 1 "register_operand" ""))
14996 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14997 (clobber (reg:CC 17))])]
15003 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
15006 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15008 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
15013 (define_expand "strsetsi_rex64"
15014 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
15015 (match_operand:SI 1 "register_operand" ""))
15016 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15017 (clobber (reg:CC 17))])]
15021 if (TARGET_SINGLE_STRINGOP || optimize_size)
15023 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
15028 (define_expand "strsethi"
15029 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
15030 (match_operand:HI 1 "register_operand" ""))
15031 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15032 (clobber (reg:CC 17))])]
15038 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
15041 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15043 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
15048 (define_expand "strsethi_rex64"
15049 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
15050 (match_operand:HI 1 "register_operand" ""))
15051 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15052 (clobber (reg:CC 17))])]
15056 if (TARGET_SINGLE_STRINGOP || optimize_size)
15058 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
15063 (define_expand "strsetqi"
15064 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
15065 (match_operand:QI 1 "register_operand" ""))
15066 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15067 (clobber (reg:CC 17))])]
15073 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15076 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15078 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15083 (define_expand "strsetqi_rex64"
15084 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15085 (match_operand:QI 1 "register_operand" ""))
15086 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15087 (clobber (reg:CC 17))])]
15091 if (TARGET_SINGLE_STRINGOP || optimize_size)
15093 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15098 (define_insn "strsetdi_rex_1"
15099 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15100 (match_operand:SI 2 "register_operand" "a"))
15101 (set (match_operand:DI 0 "register_operand" "=D")
15102 (plus:DI (match_dup 1)
15105 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15107 [(set_attr "type" "str")
15108 (set_attr "memory" "store")
15109 (set_attr "mode" "DI")])
15111 (define_insn "strsetsi_1"
15112 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15113 (match_operand:SI 2 "register_operand" "a"))
15114 (set (match_operand:SI 0 "register_operand" "=D")
15115 (plus:SI (match_dup 1)
15118 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15120 [(set_attr "type" "str")
15121 (set_attr "memory" "store")
15122 (set_attr "mode" "SI")])
15124 (define_insn "strsetsi_rex_1"
15125 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15126 (match_operand:SI 2 "register_operand" "a"))
15127 (set (match_operand:DI 0 "register_operand" "=D")
15128 (plus:DI (match_dup 1)
15131 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15133 [(set_attr "type" "str")
15134 (set_attr "memory" "store")
15135 (set_attr "mode" "SI")])
15137 (define_insn "strsethi_1"
15138 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15139 (match_operand:HI 2 "register_operand" "a"))
15140 (set (match_operand:SI 0 "register_operand" "=D")
15141 (plus:SI (match_dup 1)
15144 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15146 [(set_attr "type" "str")
15147 (set_attr "memory" "store")
15148 (set_attr "mode" "HI")])
15150 (define_insn "strsethi_rex_1"
15151 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15152 (match_operand:HI 2 "register_operand" "a"))
15153 (set (match_operand:DI 0 "register_operand" "=D")
15154 (plus:DI (match_dup 1)
15157 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15159 [(set_attr "type" "str")
15160 (set_attr "memory" "store")
15161 (set_attr "mode" "HI")])
15163 (define_insn "strsetqi_1"
15164 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15165 (match_operand:QI 2 "register_operand" "a"))
15166 (set (match_operand:SI 0 "register_operand" "=D")
15167 (plus:SI (match_dup 1)
15170 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15172 [(set_attr "type" "str")
15173 (set_attr "memory" "store")
15174 (set_attr "mode" "QI")])
15176 (define_insn "strsetqi_rex_1"
15177 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15178 (match_operand:QI 2 "register_operand" "a"))
15179 (set (match_operand:DI 0 "register_operand" "=D")
15180 (plus:DI (match_dup 1)
15183 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15185 [(set_attr "type" "str")
15186 (set_attr "memory" "store")
15187 (set_attr "mode" "QI")])
15189 (define_insn "rep_stosdi_rex64"
15190 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15191 (set (match_operand:DI 0 "register_operand" "=D")
15192 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15194 (match_operand:DI 3 "register_operand" "0")))
15195 (set (mem:BLK (match_dup 3))
15197 (use (match_operand:DI 2 "register_operand" "a"))
15198 (use (match_dup 4))
15201 "rep\;stosq|rep stosq"
15202 [(set_attr "type" "str")
15203 (set_attr "prefix_rep" "1")
15204 (set_attr "memory" "store")
15205 (set_attr "mode" "DI")])
15207 (define_insn "rep_stossi"
15208 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15209 (set (match_operand:SI 0 "register_operand" "=D")
15210 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15212 (match_operand:SI 3 "register_operand" "0")))
15213 (set (mem:BLK (match_dup 3))
15215 (use (match_operand:SI 2 "register_operand" "a"))
15216 (use (match_dup 4))
15219 "rep\;stosl|rep stosd"
15220 [(set_attr "type" "str")
15221 (set_attr "prefix_rep" "1")
15222 (set_attr "memory" "store")
15223 (set_attr "mode" "SI")])
15225 (define_insn "rep_stossi_rex64"
15226 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15227 (set (match_operand:DI 0 "register_operand" "=D")
15228 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15230 (match_operand:DI 3 "register_operand" "0")))
15231 (set (mem:BLK (match_dup 3))
15233 (use (match_operand:SI 2 "register_operand" "a"))
15234 (use (match_dup 4))
15237 "rep\;stosl|rep stosd"
15238 [(set_attr "type" "str")
15239 (set_attr "prefix_rep" "1")
15240 (set_attr "memory" "store")
15241 (set_attr "mode" "SI")])
15243 (define_insn "rep_stosqi"
15244 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15245 (set (match_operand:SI 0 "register_operand" "=D")
15246 (plus:SI (match_operand:SI 3 "register_operand" "0")
15247 (match_operand:SI 4 "register_operand" "1")))
15248 (set (mem:BLK (match_dup 3))
15250 (use (match_operand:QI 2 "register_operand" "a"))
15251 (use (match_dup 4))
15254 "rep\;stosb|rep stosb"
15255 [(set_attr "type" "str")
15256 (set_attr "prefix_rep" "1")
15257 (set_attr "memory" "store")
15258 (set_attr "mode" "QI")])
15260 (define_insn "rep_stosqi_rex64"
15261 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15262 (set (match_operand:DI 0 "register_operand" "=D")
15263 (plus:DI (match_operand:DI 3 "register_operand" "0")
15264 (match_operand:DI 4 "register_operand" "1")))
15265 (set (mem:BLK (match_dup 3))
15267 (use (match_operand:QI 2 "register_operand" "a"))
15268 (use (match_dup 4))
15271 "rep\;stosb|rep stosb"
15272 [(set_attr "type" "str")
15273 (set_attr "prefix_rep" "1")
15274 (set_attr "memory" "store")
15275 (set_attr "mode" "QI")])
15277 (define_expand "cmpstrsi"
15278 [(set (match_operand:SI 0 "register_operand" "")
15279 (compare:SI (match_operand:BLK 1 "general_operand" "")
15280 (match_operand:BLK 2 "general_operand" "")))
15281 (use (match_operand 3 "general_operand" ""))
15282 (use (match_operand 4 "immediate_operand" ""))]
15286 rtx addr1, addr2, out, outlow, count, countreg, align;
15289 if (GET_CODE (out) != REG)
15290 out = gen_reg_rtx (SImode);
15292 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15293 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15295 count = operands[3];
15296 countreg = copy_to_mode_reg (Pmode, count);
15298 /* %%% Iff we are testing strict equality, we can use known alignment
15299 to good advantage. This may be possible with combine, particularly
15300 once cc0 is dead. */
15301 align = operands[4];
15303 emit_insn (gen_cld ());
15304 if (GET_CODE (count) == CONST_INT)
15306 if (INTVAL (count) == 0)
15308 emit_move_insn (operands[0], const0_rtx);
15312 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15313 addr1, addr2, countreg));
15315 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15316 addr1, addr2, countreg));
15322 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15323 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15324 addr1, addr2, countreg));
15328 emit_insn (gen_cmpsi_1 (countreg, countreg));
15329 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15330 addr1, addr2, countreg));
15334 outlow = gen_lowpart (QImode, out);
15335 emit_insn (gen_cmpintqi (outlow));
15336 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15338 if (operands[0] != out)
15339 emit_move_insn (operands[0], out);
15344 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15346 (define_expand "cmpintqi"
15347 [(set (match_dup 1)
15348 (gtu:QI (reg:CC 17) (const_int 0)))
15350 (ltu:QI (reg:CC 17) (const_int 0)))
15351 (parallel [(set (match_operand:QI 0 "register_operand" "")
15352 (minus:QI (match_dup 1)
15354 (clobber (reg:CC 17))])]
15356 "operands[1] = gen_reg_rtx (QImode);
15357 operands[2] = gen_reg_rtx (QImode);")
15359 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15360 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15362 (define_insn "cmpstrqi_nz_1"
15364 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15365 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15366 (use (match_operand:SI 6 "register_operand" "2"))
15367 (use (match_operand:SI 3 "immediate_operand" "i"))
15369 (clobber (match_operand:SI 0 "register_operand" "=S"))
15370 (clobber (match_operand:SI 1 "register_operand" "=D"))
15371 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15374 [(set_attr "type" "str")
15375 (set_attr "mode" "QI")
15376 (set_attr "prefix_rep" "1")])
15378 (define_insn "cmpstrqi_nz_rex_1"
15380 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15381 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15382 (use (match_operand:DI 6 "register_operand" "2"))
15383 (use (match_operand:SI 3 "immediate_operand" "i"))
15385 (clobber (match_operand:DI 0 "register_operand" "=S"))
15386 (clobber (match_operand:DI 1 "register_operand" "=D"))
15387 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15390 [(set_attr "type" "str")
15391 (set_attr "mode" "QI")
15392 (set_attr "prefix_rep" "1")])
15394 ;; The same, but the count is not known to not be zero.
15396 (define_insn "cmpstrqi_1"
15398 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15400 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15401 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15403 (use (match_operand:SI 3 "immediate_operand" "i"))
15406 (clobber (match_operand:SI 0 "register_operand" "=S"))
15407 (clobber (match_operand:SI 1 "register_operand" "=D"))
15408 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15411 [(set_attr "type" "str")
15412 (set_attr "mode" "QI")
15413 (set_attr "prefix_rep" "1")])
15415 (define_insn "cmpstrqi_rex_1"
15417 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15419 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15420 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15422 (use (match_operand:SI 3 "immediate_operand" "i"))
15425 (clobber (match_operand:DI 0 "register_operand" "=S"))
15426 (clobber (match_operand:DI 1 "register_operand" "=D"))
15427 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15430 [(set_attr "type" "str")
15431 (set_attr "mode" "QI")
15432 (set_attr "prefix_rep" "1")])
15434 (define_expand "strlensi"
15435 [(set (match_operand:SI 0 "register_operand" "")
15436 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15437 (match_operand:QI 2 "immediate_operand" "")
15438 (match_operand 3 "immediate_operand" "")] 0))]
15442 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15448 (define_expand "strlendi"
15449 [(set (match_operand:DI 0 "register_operand" "")
15450 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15451 (match_operand:QI 2 "immediate_operand" "")
15452 (match_operand 3 "immediate_operand" "")] 0))]
15456 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15462 (define_insn "strlenqi_1"
15463 [(set (match_operand:SI 0 "register_operand" "=&c")
15464 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15465 (match_operand:QI 2 "register_operand" "a")
15466 (match_operand:SI 3 "immediate_operand" "i")
15467 (match_operand:SI 4 "register_operand" "0")] 0))
15469 (clobber (match_operand:SI 1 "register_operand" "=D"))
15470 (clobber (reg:CC 17))]
15473 [(set_attr "type" "str")
15474 (set_attr "mode" "QI")
15475 (set_attr "prefix_rep" "1")])
15477 (define_insn "strlenqi_rex_1"
15478 [(set (match_operand:DI 0 "register_operand" "=&c")
15479 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15480 (match_operand:QI 2 "register_operand" "a")
15481 (match_operand:DI 3 "immediate_operand" "i")
15482 (match_operand:DI 4 "register_operand" "0")] 0))
15484 (clobber (match_operand:DI 1 "register_operand" "=D"))
15485 (clobber (reg:CC 17))]
15488 [(set_attr "type" "str")
15489 (set_attr "mode" "QI")
15490 (set_attr "prefix_rep" "1")])
15492 ;; Peephole optimizations to clean up after cmpstr*. This should be
15493 ;; handled in combine, but it is not currently up to the task.
15494 ;; When used for their truth value, the cmpstr* expanders generate
15503 ;; The intermediate three instructions are unnecessary.
15505 ;; This one handles cmpstr*_nz_1...
15509 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15510 (mem:BLK (match_operand 5 "register_operand" ""))))
15511 (use (match_operand 6 "register_operand" ""))
15512 (use (match_operand:SI 3 "immediate_operand" ""))
15514 (clobber (match_operand 0 "register_operand" ""))
15515 (clobber (match_operand 1 "register_operand" ""))
15516 (clobber (match_operand 2 "register_operand" ""))])
15517 (set (match_operand:QI 7 "register_operand" "")
15518 (gtu:QI (reg:CC 17) (const_int 0)))
15519 (set (match_operand:QI 8 "register_operand" "")
15520 (ltu:QI (reg:CC 17) (const_int 0)))
15522 (compare (match_dup 7) (match_dup 8)))
15524 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15527 (compare:CC (mem:BLK (match_dup 4))
15528 (mem:BLK (match_dup 5))))
15529 (use (match_dup 6))
15530 (use (match_dup 3))
15532 (clobber (match_dup 0))
15533 (clobber (match_dup 1))
15534 (clobber (match_dup 2))])]
15537 ;; ...and this one handles cmpstr*_1.
15541 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
15543 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15544 (mem:BLK (match_operand 5 "register_operand" "")))
15546 (use (match_operand:SI 3 "immediate_operand" ""))
15549 (clobber (match_operand 0 "register_operand" ""))
15550 (clobber (match_operand 1 "register_operand" ""))
15551 (clobber (match_operand 2 "register_operand" ""))])
15552 (set (match_operand:QI 7 "register_operand" "")
15553 (gtu:QI (reg:CC 17) (const_int 0)))
15554 (set (match_operand:QI 8 "register_operand" "")
15555 (ltu:QI (reg:CC 17) (const_int 0)))
15557 (compare (match_dup 7) (match_dup 8)))
15559 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15562 (if_then_else:CC (ne (match_dup 6)
15564 (compare:CC (mem:BLK (match_dup 4))
15565 (mem:BLK (match_dup 5)))
15567 (use (match_dup 3))
15570 (clobber (match_dup 0))
15571 (clobber (match_dup 1))
15572 (clobber (match_dup 2))])]
15577 ;; Conditional move instructions.
15579 (define_expand "movdicc_rex64"
15580 [(set (match_operand:DI 0 "register_operand" "")
15581 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15582 (match_operand:DI 2 "x86_64_general_operand" "")
15583 (match_operand:DI 3 "x86_64_general_operand" "")))]
15585 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15587 (define_insn "x86_movdicc_0_m1_rex64"
15588 [(set (match_operand:DI 0 "register_operand" "=r")
15589 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15592 (clobber (reg:CC 17))]
15595 ; Since we don't have the proper number of operands for an alu insn,
15596 ; fill in all the blanks.
15597 [(set_attr "type" "alu")
15598 (set_attr "memory" "none")
15599 (set_attr "imm_disp" "false")
15600 (set_attr "mode" "DI")
15601 (set_attr "length_immediate" "0")])
15603 (define_insn "*movdicc_c_rex64"
15604 [(set (match_operand:DI 0 "register_operand" "=r,r")
15605 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15606 [(reg 17) (const_int 0)])
15607 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15608 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15609 "TARGET_64BIT && TARGET_CMOVE
15610 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15612 cmov%C1\\t{%2, %0|%0, %2}
15613 cmov%c1\\t{%3, %0|%0, %3}"
15614 [(set_attr "type" "icmov")
15615 (set_attr "mode" "DI")])
15617 (define_expand "movsicc"
15618 [(set (match_operand:SI 0 "register_operand" "")
15619 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15620 (match_operand:SI 2 "general_operand" "")
15621 (match_operand:SI 3 "general_operand" "")))]
15623 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15625 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15626 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15627 ;; So just document what we're doing explicitly.
15629 (define_insn "x86_movsicc_0_m1"
15630 [(set (match_operand:SI 0 "register_operand" "=r")
15631 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15634 (clobber (reg:CC 17))]
15637 ; Since we don't have the proper number of operands for an alu insn,
15638 ; fill in all the blanks.
15639 [(set_attr "type" "alu")
15640 (set_attr "memory" "none")
15641 (set_attr "imm_disp" "false")
15642 (set_attr "mode" "SI")
15643 (set_attr "length_immediate" "0")])
15645 (define_insn "*movsicc_noc"
15646 [(set (match_operand:SI 0 "register_operand" "=r,r")
15647 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15648 [(reg 17) (const_int 0)])
15649 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15650 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15652 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15654 cmov%C1\\t{%2, %0|%0, %2}
15655 cmov%c1\\t{%3, %0|%0, %3}"
15656 [(set_attr "type" "icmov")
15657 (set_attr "mode" "SI")])
15659 (define_expand "movhicc"
15660 [(set (match_operand:HI 0 "register_operand" "")
15661 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15662 (match_operand:HI 2 "nonimmediate_operand" "")
15663 (match_operand:HI 3 "nonimmediate_operand" "")))]
15664 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15665 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15667 (define_insn "*movhicc_noc"
15668 [(set (match_operand:HI 0 "register_operand" "=r,r")
15669 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15670 [(reg 17) (const_int 0)])
15671 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15672 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15674 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15676 cmov%C1\\t{%2, %0|%0, %2}
15677 cmov%c1\\t{%3, %0|%0, %3}"
15678 [(set_attr "type" "icmov")
15679 (set_attr "mode" "HI")])
15681 (define_expand "movsfcc"
15682 [(set (match_operand:SF 0 "register_operand" "")
15683 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15684 (match_operand:SF 2 "register_operand" "")
15685 (match_operand:SF 3 "register_operand" "")))]
15687 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15689 (define_insn "*movsfcc_1"
15690 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15691 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15692 [(reg 17) (const_int 0)])
15693 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15694 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15696 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15698 fcmov%F1\\t{%2, %0|%0, %2}
15699 fcmov%f1\\t{%3, %0|%0, %3}
15700 cmov%C1\\t{%2, %0|%0, %2}
15701 cmov%c1\\t{%3, %0|%0, %3}"
15702 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15703 (set_attr "mode" "SF,SF,SI,SI")])
15705 (define_expand "movdfcc"
15706 [(set (match_operand:DF 0 "register_operand" "")
15707 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15708 (match_operand:DF 2 "register_operand" "")
15709 (match_operand:DF 3 "register_operand" "")))]
15711 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15713 (define_insn "*movdfcc_1"
15714 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15715 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15716 [(reg 17) (const_int 0)])
15717 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15718 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15719 "TARGET_CMOVE && !TARGET_64BIT
15720 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15722 fcmov%F1\\t{%2, %0|%0, %2}
15723 fcmov%f1\\t{%3, %0|%0, %3}
15726 [(set_attr "type" "fcmov,fcmov,multi,multi")
15727 (set_attr "mode" "DF")])
15729 (define_insn "*movdfcc_1_rex64"
15730 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15731 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15732 [(reg 17) (const_int 0)])
15733 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15734 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15735 "TARGET_CMOVE && TARGET_64BIT
15736 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15738 fcmov%F1\\t{%2, %0|%0, %2}
15739 fcmov%f1\\t{%3, %0|%0, %3}
15740 cmov%C1\\t{%2, %0|%0, %2}
15741 cmov%c1\\t{%3, %0|%0, %3}"
15742 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15743 (set_attr "mode" "DF")])
15746 [(set (match_operand:DF 0 "register_operand" "")
15747 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15748 [(match_operand 4 "" "") (const_int 0)])
15749 (match_operand:DF 2 "nonimmediate_operand" "")
15750 (match_operand:DF 3 "nonimmediate_operand" "")))]
15751 "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
15752 [(set (match_dup 2)
15753 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15757 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15760 "split_di (operands+2, 1, operands+5, operands+6);
15761 split_di (operands+3, 1, operands+7, operands+8);
15762 split_di (operands, 1, operands+2, operands+3);")
15764 (define_expand "movxfcc"
15765 [(set (match_operand:XF 0 "register_operand" "")
15766 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15767 (match_operand:XF 2 "register_operand" "")
15768 (match_operand:XF 3 "register_operand" "")))]
15769 "TARGET_CMOVE && !TARGET_64BIT"
15770 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15772 (define_expand "movtfcc"
15773 [(set (match_operand:TF 0 "register_operand" "")
15774 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15775 (match_operand:TF 2 "register_operand" "")
15776 (match_operand:TF 3 "register_operand" "")))]
15778 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15780 (define_insn "*movxfcc_1"
15781 [(set (match_operand:XF 0 "register_operand" "=f,f")
15782 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
15783 [(reg 17) (const_int 0)])
15784 (match_operand:XF 2 "register_operand" "f,0")
15785 (match_operand:XF 3 "register_operand" "0,f")))]
15786 "TARGET_CMOVE && !TARGET_64BIT"
15788 fcmov%F1\\t{%2, %0|%0, %2}
15789 fcmov%f1\\t{%3, %0|%0, %3}"
15790 [(set_attr "type" "fcmov")
15791 (set_attr "mode" "XF")])
15793 (define_insn "*movtfcc_1"
15794 [(set (match_operand:TF 0 "register_operand" "=f,f")
15795 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
15796 [(reg 17) (const_int 0)])
15797 (match_operand:TF 2 "register_operand" "f,0")
15798 (match_operand:TF 3 "register_operand" "0,f")))]
15801 fcmov%F1\\t{%2, %0|%0, %2}
15802 fcmov%f1\\t{%3, %0|%0, %3}"
15803 [(set_attr "type" "fcmov")
15804 (set_attr "mode" "XF")])
15806 (define_expand "minsf3"
15808 (set (match_operand:SF 0 "register_operand" "")
15809 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15810 (match_operand:SF 2 "nonimmediate_operand" ""))
15813 (clobber (reg:CC 17))])]
15817 (define_insn "*minsf"
15818 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15819 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
15820 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15823 (clobber (reg:CC 17))]
15824 "TARGET_SSE && TARGET_IEEE_FP"
15827 (define_insn "*minsf_nonieee"
15828 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15829 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15830 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15833 (clobber (reg:CC 17))]
15834 "TARGET_SSE && !TARGET_IEEE_FP"
15838 [(set (match_operand:SF 0 "register_operand" "")
15839 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15840 (match_operand:SF 2 "nonimmediate_operand" ""))
15841 (match_operand:DF 3 "register_operand" "")
15842 (match_operand:DF 4 "nonimmediate_operand" "")))
15843 (clobber (reg:CC 17))]
15844 "SSE_REG_P (operands[0]) && reload_completed
15845 && ((operands_match_p (operands[1], operands[3])
15846 && operands_match_p (operands[2], operands[4]))
15847 || (operands_match_p (operands[1], operands[4])
15848 && operands_match_p (operands[2], operands[3])))"
15849 [(set (match_dup 0)
15850 (if_then_else:SF (lt (match_dup 1)
15855 ;; We can't represent the LT test directly. Do this by swapping the operands.
15858 [(set (match_operand:SF 0 "register_operand" "")
15859 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15860 (match_operand:SF 2 "register_operand" ""))
15861 (match_operand:DF 3 "register_operand" "")
15862 (match_operand:DF 4 "register_operand" "")))
15863 (clobber (reg:CC 17))]
15864 "FP_REG_P (operands[0]) && reload_completed
15865 && ((operands_match_p (operands[1], operands[3])
15866 && operands_match_p (operands[2], operands[4]))
15867 || (operands_match_p (operands[1], operands[4])
15868 && operands_match_p (operands[2], operands[3])))"
15869 [(set (reg:CCFP 17)
15870 (compare:CCFP (match_dup 2)
15873 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
15877 (define_insn "*minsf_sse"
15878 [(set (match_operand:SF 0 "register_operand" "=x")
15879 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
15880 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15883 "TARGET_SSE && reload_completed"
15884 "minss\\t{%2, %0|%0, %2}"
15885 [(set_attr "type" "sse")
15886 (set_attr "mode" "SF")])
15888 (define_expand "mindf3"
15890 (set (match_operand:DF 0 "register_operand" "")
15891 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15892 (match_operand:DF 2 "nonimmediate_operand" ""))
15895 (clobber (reg:CC 17))])]
15899 (define_insn "*mindf"
15900 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15901 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15902 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15905 (clobber (reg:CC 17))]
15906 "TARGET_SSE2 && TARGET_IEEE_FP"
15909 (define_insn "*mindf_nonieee"
15910 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15911 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
15912 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15915 (clobber (reg:CC 17))]
15916 "TARGET_SSE2 && !TARGET_IEEE_FP"
15920 [(set (match_operand:DF 0 "register_operand" "")
15921 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15922 (match_operand:DF 2 "nonimmediate_operand" ""))
15923 (match_operand:DF 3 "register_operand" "")
15924 (match_operand:DF 4 "nonimmediate_operand" "")))
15925 (clobber (reg:CC 17))]
15926 "SSE_REG_P (operands[0]) && reload_completed
15927 && ((operands_match_p (operands[1], operands[3])
15928 && operands_match_p (operands[2], operands[4]))
15929 || (operands_match_p (operands[1], operands[4])
15930 && operands_match_p (operands[2], operands[3])))"
15931 [(set (match_dup 0)
15932 (if_then_else:DF (lt (match_dup 1)
15937 ;; We can't represent the LT test directly. Do this by swapping the operands.
15939 [(set (match_operand:DF 0 "register_operand" "")
15940 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15941 (match_operand:DF 2 "register_operand" ""))
15942 (match_operand:DF 3 "register_operand" "")
15943 (match_operand:DF 4 "register_operand" "")))
15944 (clobber (reg:CC 17))]
15945 "FP_REG_P (operands[0]) && reload_completed
15946 && ((operands_match_p (operands[1], operands[3])
15947 && operands_match_p (operands[2], operands[4]))
15948 || (operands_match_p (operands[1], operands[4])
15949 && operands_match_p (operands[2], operands[3])))"
15950 [(set (reg:CCFP 17)
15951 (compare:CCFP (match_dup 2)
15954 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
15958 (define_insn "*mindf_sse"
15959 [(set (match_operand:DF 0 "register_operand" "=Y")
15960 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
15961 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15964 "TARGET_SSE2 && reload_completed"
15965 "minsd\\t{%2, %0|%0, %2}"
15966 [(set_attr "type" "sse")
15967 (set_attr "mode" "DF")])
15969 (define_expand "maxsf3"
15971 (set (match_operand:SF 0 "register_operand" "")
15972 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15973 (match_operand:SF 2 "nonimmediate_operand" ""))
15976 (clobber (reg:CC 17))])]
15980 (define_insn "*maxsf"
15981 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15982 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
15983 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
15986 (clobber (reg:CC 17))]
15987 "TARGET_SSE && TARGET_IEEE_FP"
15990 (define_insn "*maxsf_nonieee"
15991 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15992 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
15993 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15996 (clobber (reg:CC 17))]
15997 "TARGET_SSE && !TARGET_IEEE_FP"
16001 [(set (match_operand:SF 0 "register_operand" "")
16002 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16003 (match_operand:SF 2 "nonimmediate_operand" ""))
16004 (match_operand:SF 3 "register_operand" "")
16005 (match_operand:SF 4 "nonimmediate_operand" "")))
16006 (clobber (reg:CC 17))]
16007 "SSE_REG_P (operands[0]) && reload_completed
16008 && ((operands_match_p (operands[1], operands[3])
16009 && operands_match_p (operands[2], operands[4]))
16010 || (operands_match_p (operands[1], operands[4])
16011 && operands_match_p (operands[2], operands[3])))"
16012 [(set (match_dup 0)
16013 (if_then_else:SF (gt (match_dup 1)
16019 [(set (match_operand:SF 0 "register_operand" "")
16020 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16021 (match_operand:SF 2 "register_operand" ""))
16022 (match_operand:SF 3 "register_operand" "")
16023 (match_operand:SF 4 "register_operand" "")))
16024 (clobber (reg:CC 17))]
16025 "FP_REG_P (operands[0]) && reload_completed
16026 && ((operands_match_p (operands[1], operands[3])
16027 && operands_match_p (operands[2], operands[4]))
16028 || (operands_match_p (operands[1], operands[4])
16029 && operands_match_p (operands[2], operands[3])))"
16030 [(set (reg:CCFP 17)
16031 (compare:CCFP (match_dup 1)
16034 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
16038 (define_insn "*maxsf_sse"
16039 [(set (match_operand:SF 0 "register_operand" "=x")
16040 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
16041 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16044 "TARGET_SSE && reload_completed"
16045 "maxss\\t{%2, %0|%0, %2}"
16046 [(set_attr "type" "sse")
16047 (set_attr "mode" "SF")])
16049 (define_expand "maxdf3"
16051 (set (match_operand:DF 0 "register_operand" "")
16052 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16053 (match_operand:DF 2 "nonimmediate_operand" ""))
16056 (clobber (reg:CC 17))])]
16060 (define_insn "*maxdf"
16061 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16062 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16063 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
16066 (clobber (reg:CC 17))]
16067 "TARGET_SSE2 && TARGET_IEEE_FP"
16070 (define_insn "*maxdf_nonieee"
16071 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16072 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
16073 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
16076 (clobber (reg:CC 17))]
16077 "TARGET_SSE2 && !TARGET_IEEE_FP"
16081 [(set (match_operand:DF 0 "register_operand" "")
16082 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16083 (match_operand:DF 2 "nonimmediate_operand" ""))
16084 (match_operand:DF 3 "register_operand" "")
16085 (match_operand:DF 4 "nonimmediate_operand" "")))
16086 (clobber (reg:CC 17))]
16087 "SSE_REG_P (operands[0]) && reload_completed
16088 && ((operands_match_p (operands[1], operands[3])
16089 && operands_match_p (operands[2], operands[4]))
16090 || (operands_match_p (operands[1], operands[4])
16091 && operands_match_p (operands[2], operands[3])))"
16092 [(set (match_dup 0)
16093 (if_then_else:DF (gt (match_dup 1)
16099 [(set (match_operand:DF 0 "register_operand" "")
16100 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16101 (match_operand:DF 2 "register_operand" ""))
16102 (match_operand:DF 3 "register_operand" "")
16103 (match_operand:DF 4 "register_operand" "")))
16104 (clobber (reg:CC 17))]
16105 "FP_REG_P (operands[0]) && reload_completed
16106 && ((operands_match_p (operands[1], operands[3])
16107 && operands_match_p (operands[2], operands[4]))
16108 || (operands_match_p (operands[1], operands[4])
16109 && operands_match_p (operands[2], operands[3])))"
16110 [(set (reg:CCFP 17)
16111 (compare:CCFP (match_dup 1)
16114 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16118 (define_insn "*maxdf_sse"
16119 [(set (match_operand:DF 0 "register_operand" "=Y")
16120 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16121 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16124 "TARGET_SSE2 && reload_completed"
16125 "maxsd\\t{%2, %0|%0, %2}"
16126 [(set_attr "type" "sse")
16127 (set_attr "mode" "DF")])
16129 ;; Misc patterns (?)
16131 ;; This pattern exists to put a dependancy on all ebp-based memory accesses.
16132 ;; Otherwise there will be nothing to keep
16134 ;; [(set (reg ebp) (reg esp))]
16135 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16136 ;; (clobber (eflags)]
16137 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16139 ;; in proper program order.
16140 (define_expand "pro_epilogue_adjust_stack"
16141 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
16142 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16143 (match_operand:SI 2 "immediate_operand" "i,i")))
16144 (set (match_operand:SI 3 "register_operand" "+r,r")
16146 (clobber (reg:CC 17))])]
16152 emit_insn (gen_pro_epilogue_adjust_stack_rex64 (operands[0], operands[1],
16153 operands[2], operands[3]));
16158 (define_insn "*pro_epilogue_adjust_stack_1"
16159 [(set (match_operand:SI 0 "register_operand" "=r,r")
16160 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16161 (match_operand:SI 2 "immediate_operand" "i,i")))
16162 (set (match_operand:SI 3 "register_operand" "+r,r")
16164 (clobber (reg:CC 17))]
16168 switch (get_attr_type (insn))
16171 return \"mov{l}\\t{%1, %0|%0, %1}\";
16174 if (GET_CODE (operands[2]) == CONST_INT
16175 && (INTVAL (operands[2]) == 128
16176 || (INTVAL (operands[2]) < 0
16177 && INTVAL (operands[2]) != -128)))
16179 operands[2] = GEN_INT (-INTVAL (operands[2]));
16180 return \"sub{l}\\t{%2, %0|%0, %2}\";
16182 return \"add{l}\\t{%2, %0|%0, %2}\";
16185 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16186 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
16192 [(set (attr "type")
16193 (cond [(eq_attr "alternative" "0")
16194 (const_string "alu")
16195 (match_operand:SI 2 "const0_operand" "")
16196 (const_string "imov")
16198 (const_string "lea")))
16199 (set_attr "mode" "SI")])
16201 (define_insn "pro_epilogue_adjust_stack_rex64"
16202 [(set (match_operand:DI 0 "register_operand" "=r,r")
16203 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16204 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16205 (set (match_operand:DI 3 "register_operand" "+r,r")
16207 (clobber (reg:CC 17))]
16211 switch (get_attr_type (insn))
16214 return \"mov{q}\\t{%1, %0|%0, %1}\";
16217 if (GET_CODE (operands[2]) == CONST_INT
16218 && (INTVAL (operands[2]) == 128
16219 || (INTVAL (operands[2]) < 0
16220 && INTVAL (operands[2]) != -128)))
16222 operands[2] = GEN_INT (-INTVAL (operands[2]));
16223 return \"sub{q}\\t{%2, %0|%0, %2}\";
16225 return \"add{q}\\t{%2, %0|%0, %2}\";
16228 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16229 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
16235 [(set (attr "type")
16236 (cond [(eq_attr "alternative" "0")
16237 (const_string "alu")
16238 (match_operand:DI 2 "const0_operand" "")
16239 (const_string "imov")
16241 (const_string "lea")))
16242 (set_attr "mode" "DI")])
16245 ;; Placeholder for the conditional moves. This one is split eighter to SSE
16246 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16247 ;; fact is that compares supported by the cmp??ss instructions are exactly
16248 ;; swapped of those supported by cmove sequence.
16249 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16250 ;; supported by i387 comparisons and we do need to emit two conditional moves
16253 (define_insn "sse_movsfcc"
16254 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16255 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16256 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16257 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16258 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16259 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16260 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16261 (clobber (reg:CC 17))]
16263 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16264 && (!TARGET_IEEE_FP
16265 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16268 (define_insn "sse_movsfcc_eq"
16269 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16270 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16271 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16272 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16273 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16274 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16275 (clobber (reg:CC 17))]
16277 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16280 (define_insn "sse_movdfcc"
16281 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16282 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16283 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16284 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16285 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16286 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16287 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16288 (clobber (reg:CC 17))]
16290 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16291 && (!TARGET_IEEE_FP
16292 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16295 (define_insn "sse_movdfcc_eq"
16296 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16297 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16298 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16299 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16300 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16301 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16302 (clobber (reg:CC 17))]
16304 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16307 ;; For non-sse moves just expand the usual cmove sequence.
16309 [(set (match_operand 0 "register_operand" "")
16310 (if_then_else (match_operator 1 "comparison_operator"
16311 [(match_operand 4 "nonimmediate_operand" "")
16312 (match_operand 5 "register_operand" "")])
16313 (match_operand 2 "nonimmediate_operand" "")
16314 (match_operand 3 "nonimmediate_operand" "")))
16315 (clobber (match_operand 6 "" ""))
16316 (clobber (reg:CC 17))]
16317 "!SSE_REG_P (operands[0]) && reload_completed
16318 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16322 ix86_compare_op0 = operands[5];
16323 ix86_compare_op1 = operands[4];
16324 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16325 VOIDmode, operands[5], operands[4]);
16326 ix86_expand_fp_movcc (operands);
16330 ;; Split SSE based conditional move into seqence:
16331 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16332 ;; and op2, op0 - zero op2 if comparison was false
16333 ;; nand op0, op3 - load op3 to op0 if comparison was false
16334 ;; or op2, op0 - get the non-zero one into the result.
16336 [(set (match_operand 0 "register_operand" "")
16337 (if_then_else (match_operator 1 "sse_comparison_operator"
16338 [(match_operand 4 "register_operand" "")
16339 (match_operand 5 "nonimmediate_operand" "")])
16340 (match_operand 2 "register_operand" "")
16341 (match_operand 3 "register_operand" "")))
16342 (clobber (match_operand 6 "" ""))
16343 (clobber (reg:CC 17))]
16344 "SSE_REG_P (operands[0]) && reload_completed"
16345 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16346 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16347 (subreg:TI (match_dup 4) 0)))
16348 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16349 (subreg:TI (match_dup 3) 0)))
16350 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16351 (subreg:TI (match_dup 7) 0)))]
16354 PUT_MODE (operands[1], GET_MODE (operands[0]));
16355 if (operands_match_p (operands[0], operands[4]))
16356 operands[6] = operands[4], operands[7] = operands[2];
16358 operands[6] = operands[2], operands[7] = operands[4];
16361 ;; Special case of conditional move we can handle effectivly.
16362 ;; Do not brother with the integer/floating point case, since these are
16363 ;; bot considerably slower, unlike in the generic case.
16364 (define_insn "*sse_movsfcc_const0_1"
16365 [(set (match_operand:SF 0 "register_operand" "=x")
16366 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16367 [(match_operand:SF 4 "register_operand" "0")
16368 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16369 (match_operand:SF 2 "register_operand" "x")
16370 (match_operand:SF 3 "const0_operand" "X")))]
16374 (define_insn "*sse_movsfcc_const0_2"
16375 [(set (match_operand:SF 0 "register_operand" "=x")
16376 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16377 [(match_operand:SF 4 "register_operand" "0")
16378 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16379 (match_operand:SF 2 "const0_operand" "x")
16380 (match_operand:SF 3 "register_operand" "X")))]
16384 (define_insn "*sse_movsfcc_const0_3"
16385 [(set (match_operand:SF 0 "register_operand" "=x")
16386 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16387 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16388 (match_operand:SF 5 "register_operand" "0")])
16389 (match_operand:SF 2 "register_operand" "x")
16390 (match_operand:SF 3 "const0_operand" "X")))]
16394 (define_insn "*sse_movsfcc_const0_4"
16395 [(set (match_operand:SF 0 "register_operand" "=x")
16396 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16397 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16398 (match_operand:SF 5 "register_operand" "0")])
16399 (match_operand:SF 2 "const0_operand" "x")
16400 (match_operand:SF 3 "register_operand" "X")))]
16404 (define_insn "*sse_movdfcc_const0_1"
16405 [(set (match_operand:SF 0 "register_operand" "=x")
16406 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16407 [(match_operand:SF 4 "register_operand" "0")
16408 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16409 (match_operand:SF 2 "register_operand" "x")
16410 (match_operand:SF 3 "const0_operand" "X")))]
16414 (define_insn "*sse_movdfcc_const0_2"
16415 [(set (match_operand:SF 0 "register_operand" "=x")
16416 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16417 [(match_operand:SF 4 "register_operand" "0")
16418 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16419 (match_operand:SF 2 "const0_operand" "x")
16420 (match_operand:SF 3 "register_operand" "X")))]
16424 (define_insn "*sse_movdfcc_const0_3"
16425 [(set (match_operand:SF 0 "register_operand" "=x")
16426 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16427 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16428 (match_operand:SF 5 "register_operand" "0")])
16429 (match_operand:SF 2 "register_operand" "x")
16430 (match_operand:SF 3 "const0_operand" "X")))]
16434 (define_insn "*sse_movdfcc_const0_4"
16435 [(set (match_operand:SF 0 "register_operand" "=x")
16436 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16437 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16438 (match_operand:SF 5 "register_operand" "0")])
16439 (match_operand:SF 2 "const0_operand" "x")
16440 (match_operand:SF 3 "register_operand" "X")))]
16445 [(set (match_operand 0 "register_operand" "")
16446 (if_then_else (match_operator 1 "comparison_operator"
16447 [(match_operand 4 "register_operand" "")
16448 (match_operand 5 "nonimmediate_operand" "")])
16449 (match_operand 2 "nonmemory_operand" "")
16450 (match_operand 3 "nonmemory_operand" "")))]
16451 "SSE_REG_P (operands[0]) && reload_completed
16452 && (const0_operand (operands[2], GET_MODE (operands[0]))
16453 || const0_operand (operands[3], GET_MODE (operands[0])))"
16454 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16455 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16456 (subreg:TI (match_dup 7) 0)))]
16459 PUT_MODE (operands[1], GET_MODE (operands[0]));
16460 if (!sse_comparison_operator (operands[1], VOIDmode))
16462 rtx tmp = operands[5];
16463 operands[5] = operands[4];
16465 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16467 if (const0_operand (operands[2], GET_MODE (operands[0])))
16469 operands[7] = operands[3];
16470 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16475 operands[7] = operands[2];
16476 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16480 (define_expand "allocate_stack_worker"
16481 [(match_operand:SI 0 "register_operand" "")]
16482 "TARGET_STACK_PROBE"
16486 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16488 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16492 (define_insn "allocate_stack_worker_1"
16493 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
16494 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16495 (clobber (match_dup 0))
16496 (clobber (reg:CC 17))]
16497 "TARGET_STACK_PROBE && !TARGET_64BIT"
16499 [(set_attr "type" "multi")
16500 (set_attr "length" "5")])
16502 (define_insn "allocate_stack_worker_rex64"
16503 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
16504 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16505 (clobber (match_dup 0))
16506 (clobber (reg:CC 17))]
16507 "TARGET_STACK_PROBE && TARGET_64BIT"
16509 [(set_attr "type" "multi")
16510 (set_attr "length" "5")])
16512 (define_expand "allocate_stack"
16513 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16514 (minus:SI (reg:SI 7)
16515 (match_operand:SI 1 "general_operand" "")))
16516 (clobber (reg:CC 17))])
16517 (parallel [(set (reg:SI 7)
16518 (minus:SI (reg:SI 7) (match_dup 1)))
16519 (clobber (reg:CC 17))])]
16520 "TARGET_STACK_PROBE"
16523 #ifdef CHECK_STACK_LIMIT
16524 if (GET_CODE (operands[1]) == CONST_INT
16525 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16526 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16530 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16533 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16537 (define_expand "builtin_setjmp_receiver"
16538 [(label_ref (match_operand 0 "" ""))]
16539 "flag_pic && !TARGET_64BIT"
16542 load_pic_register ();
16546 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16549 [(set (match_operand 0 "register_operand" "")
16550 (match_operator 3 "promotable_binary_operator"
16551 [(match_operand 1 "register_operand" "")
16552 (match_operand 2 "aligned_operand" "")]))
16553 (clobber (reg:CC 17))]
16554 "! TARGET_PARTIAL_REG_STALL && reload_completed
16555 && ((GET_MODE (operands[0]) == HImode
16556 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
16557 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16558 || (GET_MODE (operands[0]) == QImode
16559 && (TARGET_PROMOTE_QImode || optimize_size)))"
16560 [(parallel [(set (match_dup 0)
16561 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16562 (clobber (reg:CC 17))])]
16563 "operands[0] = gen_lowpart (SImode, operands[0]);
16564 operands[1] = gen_lowpart (SImode, operands[1]);
16565 if (GET_CODE (operands[3]) != ASHIFT)
16566 operands[2] = gen_lowpart (SImode, operands[2]);
16567 PUT_MODE (operands[3], SImode);")
16571 (compare (and (match_operand 1 "aligned_operand" "")
16572 (match_operand 2 "const_int_operand" ""))
16574 (set (match_operand 0 "register_operand" "")
16575 (and (match_dup 1) (match_dup 2)))]
16576 "! TARGET_PARTIAL_REG_STALL && reload_completed
16577 && ix86_match_ccmode (insn, CCNOmode)
16578 && (GET_MODE (operands[0]) == HImode
16579 || (GET_MODE (operands[0]) == QImode
16580 && (TARGET_PROMOTE_QImode || optimize_size)))"
16581 [(parallel [(set (reg:CCNO 17)
16582 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16585 (and:SI (match_dup 1) (match_dup 2)))])]
16587 = GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
16588 & GET_MODE_MASK (GET_MODE (operands[0])),
16590 operands[0] = gen_lowpart (SImode, operands[0]);
16591 operands[1] = gen_lowpart (SImode, operands[1]);")
16595 (compare (and (match_operand 0 "aligned_operand" "")
16596 (match_operand 1 "const_int_operand" ""))
16598 "! TARGET_PARTIAL_REG_STALL && reload_completed
16599 && ix86_match_ccmode (insn, CCNOmode)
16600 && (GET_MODE (operands[0]) == HImode
16601 || (GET_MODE (operands[0]) == QImode
16602 && (TARGET_PROMOTE_QImode || optimize_size)))"
16603 [(set (reg:CCNO 17)
16604 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16607 = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
16608 & GET_MODE_MASK (GET_MODE (operands[0])),
16610 operands[0] = gen_lowpart (SImode, operands[0]);")
16613 [(set (match_operand 0 "register_operand" "")
16614 (neg (match_operand 1 "register_operand" "")))
16615 (clobber (reg:CC 17))]
16616 "! TARGET_PARTIAL_REG_STALL && reload_completed
16617 && (GET_MODE (operands[0]) == HImode
16618 || (GET_MODE (operands[0]) == QImode
16619 && (TARGET_PROMOTE_QImode || optimize_size)))"
16620 [(parallel [(set (match_dup 0)
16621 (neg:SI (match_dup 1)))
16622 (clobber (reg:CC 17))])]
16623 "operands[0] = gen_lowpart (SImode, operands[0]);
16624 operands[1] = gen_lowpart (SImode, operands[1]);")
16627 [(set (match_operand 0 "register_operand" "")
16628 (not (match_operand 1 "register_operand" "")))]
16629 "! TARGET_PARTIAL_REG_STALL && reload_completed
16630 && (GET_MODE (operands[0]) == HImode
16631 || (GET_MODE (operands[0]) == QImode
16632 && (TARGET_PROMOTE_QImode || optimize_size)))"
16633 [(set (match_dup 0)
16634 (not:SI (match_dup 1)))]
16635 "operands[0] = gen_lowpart (SImode, operands[0]);
16636 operands[1] = gen_lowpart (SImode, operands[1]);")
16639 [(set (match_operand 0 "register_operand" "")
16640 (if_then_else (match_operator 1 "comparison_operator"
16641 [(reg 17) (const_int 0)])
16642 (match_operand 2 "register_operand" "")
16643 (match_operand 3 "register_operand" "")))]
16644 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16645 && (GET_MODE (operands[0]) == HImode
16646 || (GET_MODE (operands[0]) == QImode
16647 && (TARGET_PROMOTE_QImode || optimize_size)))"
16648 [(set (match_dup 0)
16649 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16650 "operands[0] = gen_lowpart (SImode, operands[0]);
16651 operands[2] = gen_lowpart (SImode, operands[2]);
16652 operands[3] = gen_lowpart (SImode, operands[3]);")
16655 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16656 ;; transform a complex memory operation into two memory to register operations.
16658 ;; Don't push memory operands
16660 [(set (match_operand:SI 0 "push_operand" "")
16661 (match_operand:SI 1 "memory_operand" ""))
16662 (match_scratch:SI 2 "r")]
16663 "! optimize_size && ! TARGET_PUSH_MEMORY"
16664 [(set (match_dup 2) (match_dup 1))
16665 (set (match_dup 0) (match_dup 2))]
16669 [(set (match_operand:DI 0 "push_operand" "")
16670 (match_operand:DI 1 "memory_operand" ""))
16671 (match_scratch:DI 2 "r")]
16672 "! optimize_size && ! TARGET_PUSH_MEMORY"
16673 [(set (match_dup 2) (match_dup 1))
16674 (set (match_dup 0) (match_dup 2))]
16677 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16680 [(set (match_operand:SF 0 "push_operand" "")
16681 (match_operand:SF 1 "memory_operand" ""))
16682 (match_scratch:SF 2 "r")]
16683 "! optimize_size && ! TARGET_PUSH_MEMORY"
16684 [(set (match_dup 2) (match_dup 1))
16685 (set (match_dup 0) (match_dup 2))]
16689 [(set (match_operand:HI 0 "push_operand" "")
16690 (match_operand:HI 1 "memory_operand" ""))
16691 (match_scratch:HI 2 "r")]
16692 "! optimize_size && ! TARGET_PUSH_MEMORY"
16693 [(set (match_dup 2) (match_dup 1))
16694 (set (match_dup 0) (match_dup 2))]
16698 [(set (match_operand:QI 0 "push_operand" "")
16699 (match_operand:QI 1 "memory_operand" ""))
16700 (match_scratch:QI 2 "q")]
16701 "! optimize_size && ! TARGET_PUSH_MEMORY"
16702 [(set (match_dup 2) (match_dup 1))
16703 (set (match_dup 0) (match_dup 2))]
16706 ;; Don't move an immediate directly to memory when the instruction
16709 [(match_scratch:SI 1 "r")
16710 (set (match_operand:SI 0 "memory_operand" "")
16713 && ! TARGET_USE_MOV0
16714 && TARGET_SPLIT_LONG_MOVES
16715 && get_attr_length (insn) >= ix86_cost->large_insn
16716 && peep2_regno_dead_p (0, FLAGS_REG)"
16717 [(parallel [(set (match_dup 1) (const_int 0))
16718 (clobber (reg:CC 17))])
16719 (set (match_dup 0) (match_dup 1))]
16723 [(match_scratch:HI 1 "r")
16724 (set (match_operand:HI 0 "memory_operand" "")
16727 && ! TARGET_USE_MOV0
16728 && TARGET_SPLIT_LONG_MOVES
16729 && get_attr_length (insn) >= ix86_cost->large_insn
16730 && peep2_regno_dead_p (0, FLAGS_REG)"
16731 [(parallel [(set (match_dup 2) (const_int 0))
16732 (clobber (reg:CC 17))])
16733 (set (match_dup 0) (match_dup 1))]
16734 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16737 [(match_scratch:QI 1 "q")
16738 (set (match_operand:QI 0 "memory_operand" "")
16741 && ! TARGET_USE_MOV0
16742 && TARGET_SPLIT_LONG_MOVES
16743 && get_attr_length (insn) >= ix86_cost->large_insn
16744 && peep2_regno_dead_p (0, FLAGS_REG)"
16745 [(parallel [(set (match_dup 2) (const_int 0))
16746 (clobber (reg:CC 17))])
16747 (set (match_dup 0) (match_dup 1))]
16748 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16751 [(match_scratch:SI 2 "r")
16752 (set (match_operand:SI 0 "memory_operand" "")
16753 (match_operand:SI 1 "immediate_operand" ""))]
16755 && get_attr_length (insn) >= ix86_cost->large_insn
16756 && TARGET_SPLIT_LONG_MOVES"
16757 [(set (match_dup 2) (match_dup 1))
16758 (set (match_dup 0) (match_dup 2))]
16762 [(match_scratch:HI 2 "r")
16763 (set (match_operand:HI 0 "memory_operand" "")
16764 (match_operand:HI 1 "immediate_operand" ""))]
16765 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16766 && TARGET_SPLIT_LONG_MOVES"
16767 [(set (match_dup 2) (match_dup 1))
16768 (set (match_dup 0) (match_dup 2))]
16772 [(match_scratch:QI 2 "q")
16773 (set (match_operand:QI 0 "memory_operand" "")
16774 (match_operand:QI 1 "immediate_operand" ""))]
16775 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16776 && TARGET_SPLIT_LONG_MOVES"
16777 [(set (match_dup 2) (match_dup 1))
16778 (set (match_dup 0) (match_dup 2))]
16781 ;; Don't compare memory with zero, load and use a test instead.
16784 (compare (match_operand:SI 0 "memory_operand" "")
16786 (match_scratch:SI 3 "r")]
16787 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
16788 [(set (match_dup 3) (match_dup 0))
16789 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
16792 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16793 ;; Don't split NOTs with a displacement operand, because resulting XOR
16794 ;; will not be pariable anyway.
16796 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
16797 ;; represented using a modRM byte. The XOR replacement is long decoded,
16798 ;; so this split helps here as well.
16800 ;; Note: Can't do this as a regular split because we can't get proper
16801 ;; lifetime information then.
16804 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
16805 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
16807 && peep2_regno_dead_p (0, FLAGS_REG)
16808 && ((TARGET_PENTIUM
16809 && (GET_CODE (operands[0]) != MEM
16810 || !memory_displacement_operand (operands[0], SImode)))
16811 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
16812 [(parallel [(set (match_dup 0)
16813 (xor:SI (match_dup 1) (const_int -1)))
16814 (clobber (reg:CC 17))])]
16818 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
16819 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
16821 && peep2_regno_dead_p (0, FLAGS_REG)
16822 && ((TARGET_PENTIUM
16823 && (GET_CODE (operands[0]) != MEM
16824 || !memory_displacement_operand (operands[0], HImode)))
16825 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
16826 [(parallel [(set (match_dup 0)
16827 (xor:HI (match_dup 1) (const_int -1)))
16828 (clobber (reg:CC 17))])]
16832 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
16833 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
16835 && peep2_regno_dead_p (0, FLAGS_REG)
16836 && ((TARGET_PENTIUM
16837 && (GET_CODE (operands[0]) != MEM
16838 || !memory_displacement_operand (operands[0], QImode)))
16839 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
16840 [(parallel [(set (match_dup 0)
16841 (xor:QI (match_dup 1) (const_int -1)))
16842 (clobber (reg:CC 17))])]
16845 ;; Non pairable "test imm, reg" instructions can be translated to
16846 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
16847 ;; byte opcode instead of two, have a short form for byte operands),
16848 ;; so do it for other CPUs as well. Given that the value was dead,
16849 ;; this should not create any new dependancies. Pass on the sub-word
16850 ;; versions if we're concerned about partial register stalls.
16854 (compare (and:SI (match_operand:SI 0 "register_operand" "")
16855 (match_operand:SI 1 "immediate_operand" ""))
16857 "ix86_match_ccmode (insn, CCNOmode)
16858 && (true_regnum (operands[0]) != 0
16859 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
16860 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16862 [(set (reg:CCNO 17)
16863 (compare:CCNO (and:SI (match_dup 0)
16867 (and:SI (match_dup 0) (match_dup 1)))])]
16870 ;; We don't need to handle HImode case, because it will be promoted to SImode
16871 ;; on ! TARGET_PARTIAL_REG_STALL
16875 (compare (and:QI (match_operand:QI 0 "register_operand" "")
16876 (match_operand:QI 1 "immediate_operand" ""))
16878 "! TARGET_PARTIAL_REG_STALL
16879 && ix86_match_ccmode (insn, CCNOmode)
16880 && true_regnum (operands[0]) != 0
16881 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16883 [(set (reg:CCNO 17)
16884 (compare:CCNO (and:QI (match_dup 0)
16888 (and:QI (match_dup 0) (match_dup 1)))])]
16896 (match_operand 0 "ext_register_operand" "")
16899 (match_operand 1 "const_int_operand" ""))
16901 "! TARGET_PARTIAL_REG_STALL
16902 && ix86_match_ccmode (insn, CCNOmode)
16903 && true_regnum (operands[0]) != 0
16904 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16905 [(parallel [(set (reg:CCNO 17)
16914 (set (zero_extract:SI (match_dup 0)
16925 ;; Don't do logical operations with memory inputs.
16927 [(match_scratch:SI 2 "r")
16928 (parallel [(set (match_operand:SI 0 "register_operand" "")
16929 (match_operator:SI 3 "arith_or_logical_operator"
16931 (match_operand:SI 1 "memory_operand" "")]))
16932 (clobber (reg:CC 17))])]
16933 "! optimize_size && ! TARGET_READ_MODIFY"
16934 [(set (match_dup 2) (match_dup 1))
16935 (parallel [(set (match_dup 0)
16936 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
16937 (clobber (reg:CC 17))])]
16941 [(match_scratch:SI 2 "r")
16942 (parallel [(set (match_operand:SI 0 "register_operand" "")
16943 (match_operator:SI 3 "arith_or_logical_operator"
16944 [(match_operand:SI 1 "memory_operand" "")
16946 (clobber (reg:CC 17))])]
16947 "! optimize_size && ! TARGET_READ_MODIFY"
16948 [(set (match_dup 2) (match_dup 1))
16949 (parallel [(set (match_dup 0)
16950 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
16951 (clobber (reg:CC 17))])]
16954 ; Don't do logical operations with memory outputs
16956 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
16957 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
16958 ; the same decoder scheduling characteristics as the original.
16961 [(match_scratch:SI 2 "r")
16962 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16963 (match_operator:SI 3 "arith_or_logical_operator"
16965 (match_operand:SI 1 "nonmemory_operand" "")]))
16966 (clobber (reg:CC 17))])]
16967 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16968 [(set (match_dup 2) (match_dup 0))
16969 (parallel [(set (match_dup 2)
16970 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
16971 (clobber (reg:CC 17))])
16972 (set (match_dup 0) (match_dup 2))]
16976 [(match_scratch:SI 2 "r")
16977 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16978 (match_operator:SI 3 "arith_or_logical_operator"
16979 [(match_operand:SI 1 "nonmemory_operand" "")
16981 (clobber (reg:CC 17))])]
16982 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16983 [(set (match_dup 2) (match_dup 0))
16984 (parallel [(set (match_dup 2)
16985 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16986 (clobber (reg:CC 17))])
16987 (set (match_dup 0) (match_dup 2))]
16990 ;; Attempt to always use XOR for zeroing registers.
16992 [(set (match_operand 0 "register_operand" "")
16994 "(GET_MODE (operands[0]) == QImode
16995 || GET_MODE (operands[0]) == HImode
16996 || GET_MODE (operands[0]) == SImode
16997 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16998 && (! TARGET_USE_MOV0 || optimize_size)
16999 && peep2_regno_dead_p (0, FLAGS_REG)"
17000 [(parallel [(set (match_dup 0) (const_int 0))
17001 (clobber (reg:CC 17))])]
17002 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17003 true_regnum (operands[0]));")
17006 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17008 "(GET_MODE (operands[0]) == QImode
17009 || GET_MODE (operands[0]) == HImode)
17010 && (! TARGET_USE_MOV0 || optimize_size)
17011 && peep2_regno_dead_p (0, FLAGS_REG)"
17012 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17013 (clobber (reg:CC 17))])])
17015 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
17017 [(set (match_operand 0 "register_operand" "")
17019 "(GET_MODE (operands[0]) == HImode
17020 || GET_MODE (operands[0]) == SImode
17021 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17022 && (optimize_size || TARGET_PENTIUM)
17023 && peep2_regno_dead_p (0, FLAGS_REG)"
17024 [(parallel [(set (match_dup 0) (const_int -1))
17025 (clobber (reg:CC 17))])]
17026 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17027 true_regnum (operands[0]));")
17029 ;; Attempt to convert simple leas to adds. These can be created by
17032 [(set (match_operand:SI 0 "register_operand" "")
17033 (plus:SI (match_dup 0)
17034 (match_operand:SI 1 "nonmemory_operand" "")))]
17035 "peep2_regno_dead_p (0, FLAGS_REG)"
17036 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
17037 (clobber (reg:CC 17))])]
17041 [(set (match_operand:SI 0 "register_operand" "")
17042 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17043 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17044 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
17045 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17046 (clobber (reg:CC 17))])]
17047 "operands[2] = gen_lowpart (SImode, operands[2]);")
17050 [(set (match_operand:DI 0 "register_operand" "")
17051 (plus:DI (match_dup 0)
17052 (match_operand:DI 1 "x86_64_general_operand" "")))]
17053 "peep2_regno_dead_p (0, FLAGS_REG)"
17054 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
17055 (clobber (reg:CC 17))])]
17059 [(set (match_operand:SI 0 "register_operand" "")
17060 (mult:SI (match_dup 0)
17061 (match_operand:SI 1 "const_int_operand" "")))]
17062 "exact_log2 (INTVAL (operands[1])) >= 0
17063 && peep2_regno_dead_p (0, FLAGS_REG)"
17064 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17065 (clobber (reg:CC 17))])]
17066 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17069 [(set (match_operand:DI 0 "register_operand" "")
17070 (mult:DI (match_dup 0)
17071 (match_operand:DI 1 "const_int_operand" "")))]
17072 "exact_log2 (INTVAL (operands[1])) >= 0
17073 && peep2_regno_dead_p (0, FLAGS_REG)"
17074 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17075 (clobber (reg:CC 17))])]
17076 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17079 [(set (match_operand:SI 0 "register_operand" "")
17080 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17081 (match_operand:DI 2 "const_int_operand" "")) 0))]
17082 "exact_log2 (INTVAL (operands[1])) >= 0
17083 && REGNO (operands[0]) == REGNO (operands[1])
17084 && peep2_regno_dead_p (0, FLAGS_REG)"
17085 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17086 (clobber (reg:CC 17))])]
17087 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17089 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17090 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17091 ;; many CPUs it is also faster, since special hardware to avoid esp
17092 ;; dependancies is present.
17094 ;; While some of these converisons may be done using splitters, we use peepholes
17095 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17097 ;; Convert prologue esp substractions to push.
17098 ;; We need register to push. In order to keep verify_flow_info happy we have
17100 ;; - use scratch and clobber it in order to avoid dependencies
17101 ;; - use already live register
17102 ;; We can't use the second way right now, since there is no reliable way how to
17103 ;; verify that given register is live. First choice will also most likely in
17104 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17105 ;; call clobbered registers are dead. We may want to use base pointer as an
17106 ;; alternative when no register is available later.
17109 [(match_scratch:SI 0 "r")
17110 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17111 (set (reg:SI 6) (reg:SI 6))
17112 (clobber (reg:CC 17))])]
17113 "optimize_size || !TARGET_SUB_ESP_4"
17114 [(clobber (match_dup 0))
17115 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17116 (set (reg:SI 6) (reg:SI 6))])])
17119 [(match_scratch:SI 0 "r")
17120 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17121 (set (reg:SI 6) (reg:SI 6))
17122 (clobber (reg:CC 17))])]
17123 "optimize_size || !TARGET_SUB_ESP_8"
17124 [(clobber (match_dup 0))
17125 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17126 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17127 (set (reg:SI 6) (reg:SI 6))])])
17129 ;; Convert esp substractions to push.
17131 [(match_scratch:SI 0 "r")
17132 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17133 (clobber (reg:CC 17))])]
17134 "optimize_size || !TARGET_SUB_ESP_4"
17135 [(clobber (match_dup 0))
17136 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17139 [(match_scratch:SI 0 "r")
17140 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17141 (clobber (reg:CC 17))])]
17142 "optimize_size || !TARGET_SUB_ESP_8"
17143 [(clobber (match_dup 0))
17144 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17145 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17147 ;; Convert epilogue deallocator to pop.
17149 [(match_scratch:SI 0 "r")
17150 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17151 (set (reg:SI 6) (reg:SI 6))
17152 (clobber (reg:CC 17))])]
17153 "optimize_size || !TARGET_ADD_ESP_4"
17154 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17155 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17156 (set (reg:SI 6) (reg:SI 6))])]
17159 ;; Two pops case is tricky, since pop causes dependency on destination register.
17160 ;; We use two registers if available.
17162 [(match_scratch:SI 0 "r")
17163 (match_scratch:SI 1 "r")
17164 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17165 (set (reg:SI 6) (reg:SI 6))
17166 (clobber (reg:CC 17))])]
17167 "optimize_size || !TARGET_ADD_ESP_8"
17168 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17169 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17170 (set (reg:SI 6) (reg:SI 6))])
17171 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17172 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17176 [(match_scratch:SI 0 "r")
17177 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17178 (set (reg:SI 6) (reg:SI 6))
17179 (clobber (reg:CC 17))])]
17181 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17182 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17183 (set (reg:SI 6) (reg:SI 6))])
17184 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17185 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17188 ;; Convert esp additions to pop.
17190 [(match_scratch:SI 0 "r")
17191 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17192 (clobber (reg:CC 17))])]
17194 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17195 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17198 ;; Two pops case is tricky, since pop causes dependency on destination register.
17199 ;; We use two registers if available.
17201 [(match_scratch:SI 0 "r")
17202 (match_scratch:SI 1 "r")
17203 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17204 (clobber (reg:CC 17))])]
17206 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17207 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17208 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17209 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17213 [(match_scratch:SI 0 "r")
17214 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17215 (clobber (reg:CC 17))])]
17217 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17218 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17219 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17220 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17223 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17224 ;; required and register dies.
17227 (compare (match_operand:SI 0 "register_operand" "")
17228 (match_operand:SI 1 "incdec_operand" "")))]
17229 "ix86_match_ccmode (insn, CCGCmode)
17230 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17231 [(parallel [(set (reg:CCGC 17)
17232 (compare:CCGC (match_dup 0)
17234 (clobber (match_dup 0))])]
17239 (compare (match_operand:HI 0 "register_operand" "")
17240 (match_operand:HI 1 "incdec_operand" "")))]
17241 "ix86_match_ccmode (insn, CCGCmode)
17242 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17243 [(parallel [(set (reg:CCGC 17)
17244 (compare:CCGC (match_dup 0)
17246 (clobber (match_dup 0))])]
17251 (compare (match_operand:QI 0 "register_operand" "")
17252 (match_operand:QI 1 "incdec_operand" "")))]
17253 "ix86_match_ccmode (insn, CCGCmode)
17254 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17255 [(parallel [(set (reg:CCGC 17)
17256 (compare:CCGC (match_dup 0)
17258 (clobber (match_dup 0))])]
17261 ;; Convert compares with 128 to shorter add -128
17264 (compare (match_operand:SI 0 "register_operand" "")
17266 "ix86_match_ccmode (insn, CCGCmode)
17267 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17268 [(parallel [(set (reg:CCGC 17)
17269 (compare:CCGC (match_dup 0)
17271 (clobber (match_dup 0))])]
17276 (compare (match_operand:HI 0 "register_operand" "")
17278 "ix86_match_ccmode (insn, CCGCmode)
17279 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17280 [(parallel [(set (reg:CCGC 17)
17281 (compare:CCGC (match_dup 0)
17283 (clobber (match_dup 0))])]
17287 [(match_scratch:DI 0 "r")
17288 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17289 (set (reg:DI 6) (reg:DI 6))
17290 (clobber (reg:CC 17))])]
17291 "optimize_size || !TARGET_SUB_ESP_4"
17292 [(clobber (match_dup 0))
17293 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17294 (set (reg:DI 6) (reg:DI 6))])])
17297 [(match_scratch:DI 0 "r")
17298 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17299 (set (reg:DI 6) (reg:DI 6))
17300 (clobber (reg:CC 17))])]
17301 "optimize_size || !TARGET_SUB_ESP_8"
17302 [(clobber (match_dup 0))
17303 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17304 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17305 (set (reg:DI 6) (reg:DI 6))])])
17307 ;; Convert esp substractions to push.
17309 [(match_scratch:DI 0 "r")
17310 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17311 (clobber (reg:CC 17))])]
17312 "optimize_size || !TARGET_SUB_ESP_4"
17313 [(clobber (match_dup 0))
17314 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17317 [(match_scratch:DI 0 "r")
17318 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17319 (clobber (reg:CC 17))])]
17320 "optimize_size || !TARGET_SUB_ESP_8"
17321 [(clobber (match_dup 0))
17322 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17323 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17325 ;; Convert epilogue deallocator to pop.
17327 [(match_scratch:DI 0 "r")
17328 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17329 (set (reg:DI 6) (reg:DI 6))
17330 (clobber (reg:CC 17))])]
17331 "optimize_size || !TARGET_ADD_ESP_4"
17332 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17333 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17334 (set (reg:DI 6) (reg:DI 6))])]
17337 ;; Two pops case is tricky, since pop causes dependency on destination register.
17338 ;; We use two registers if available.
17340 [(match_scratch:DI 0 "r")
17341 (match_scratch:DI 1 "r")
17342 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17343 (set (reg:DI 6) (reg:DI 6))
17344 (clobber (reg:CC 17))])]
17345 "optimize_size || !TARGET_ADD_ESP_8"
17346 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17347 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17348 (set (reg:DI 6) (reg:DI 6))])
17349 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17350 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17354 [(match_scratch:DI 0 "r")
17355 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17356 (set (reg:DI 6) (reg:DI 6))
17357 (clobber (reg:CC 17))])]
17359 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17360 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17361 (set (reg:DI 6) (reg:DI 6))])
17362 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17363 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17366 ;; Convert esp additions to pop.
17368 [(match_scratch:DI 0 "r")
17369 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17370 (clobber (reg:CC 17))])]
17372 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17373 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17376 ;; Two pops case is tricky, since pop causes dependency on destination register.
17377 ;; We use two registers if available.
17379 [(match_scratch:DI 0 "r")
17380 (match_scratch:DI 1 "r")
17381 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17382 (clobber (reg:CC 17))])]
17384 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17385 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17386 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17387 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17391 [(match_scratch:DI 0 "r")
17392 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17393 (clobber (reg:CC 17))])]
17395 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17396 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17397 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17398 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17401 ;; Call-value patterns last so that the wildcard operand does not
17402 ;; disrupt insn-recog's switch tables.
17404 (define_insn "*call_value_pop_0"
17405 [(set (match_operand 0 "" "")
17406 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17407 (match_operand:SI 2 "" "")))
17408 (set (reg:SI 7) (plus:SI (reg:SI 7)
17409 (match_operand:SI 3 "immediate_operand" "")))]
17413 if (SIBLING_CALL_P (insn))
17414 return \"jmp\\t%P1\";
17416 return \"call\\t%P1\";
17418 [(set_attr "type" "callv")])
17420 (define_insn "*call_value_pop_1"
17421 [(set (match_operand 0 "" "")
17422 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17423 (match_operand:SI 2 "" "")))
17424 (set (reg:SI 7) (plus:SI (reg:SI 7)
17425 (match_operand:SI 3 "immediate_operand" "i")))]
17429 if (constant_call_address_operand (operands[1], QImode))
17431 if (SIBLING_CALL_P (insn))
17432 return \"jmp\\t%P1\";
17434 return \"call\\t%P1\";
17436 if (SIBLING_CALL_P (insn))
17437 return \"jmp\\t%A1\";
17439 return \"call\\t%A1\";
17441 [(set_attr "type" "callv")])
17443 (define_insn "*call_value_0"
17444 [(set (match_operand 0 "" "")
17445 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17446 (match_operand:SI 2 "" "")))]
17450 if (SIBLING_CALL_P (insn))
17451 return \"jmp\\t%P1\";
17453 return \"call\\t%P1\";
17455 [(set_attr "type" "callv")])
17457 (define_insn "*call_value_0_rex64"
17458 [(set (match_operand 0 "" "")
17459 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17460 (match_operand:DI 2 "const_int_operand" "")))]
17464 if (SIBLING_CALL_P (insn))
17465 return \"jmp\\t%P1\";
17467 return \"call\\t%P1\";
17469 [(set_attr "type" "callv")])
17471 (define_insn "*call_value_1"
17472 [(set (match_operand 0 "" "")
17473 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17474 (match_operand:SI 2 "" "")))]
17478 if (constant_call_address_operand (operands[1], QImode))
17480 if (SIBLING_CALL_P (insn))
17481 return \"jmp\\t%P1\";
17483 return \"call\\t%P1\";
17485 if (SIBLING_CALL_P (insn))
17486 return \"jmp\\t%*%1\";
17488 return \"call\\t%*%1\";
17490 [(set_attr "type" "callv")])
17492 (define_insn "*call_value_1_rex64"
17493 [(set (match_operand 0 "" "")
17494 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17495 (match_operand:DI 2 "" "")))]
17499 if (constant_call_address_operand (operands[1], QImode))
17501 if (SIBLING_CALL_P (insn))
17502 return \"jmp\\t%P1\";
17504 return \"call\\t%P1\";
17506 if (SIBLING_CALL_P (insn))
17507 return \"jmp\\t%A1\";
17509 return \"call\\t%A1\";
17511 [(set_attr "type" "callv")])
17513 (define_insn "trap"
17514 [(trap_if (const_int 1) (const_int 5))]
17518 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17519 ;;; for the sake of bounds checking. By emitting bounds checks as
17520 ;;; conditional traps rather than as conditional jumps around
17521 ;;; unconditional traps we avoid introducing spurious basic-block
17522 ;;; boundaries and facilitate elimination of redundant checks. In
17523 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17526 ;;; FIXME: Static branch prediction rules for ix86 are such that
17527 ;;; forward conditional branches predict as untaken. As implemented
17528 ;;; below, pseudo conditional traps violate that rule. We should use
17529 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17530 ;;; section loaded at the end of the text segment and branch forward
17531 ;;; there on bounds-failure, and then jump back immediately (in case
17532 ;;; the system chooses to ignore bounds violations, or to report
17533 ;;; violations and continue execution).
17535 (define_expand "conditional_trap"
17536 [(trap_if (match_operator 0 "comparison_operator"
17537 [(match_dup 2) (const_int 0)])
17538 (match_operand 1 "const_int_operand" ""))]
17542 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17543 ix86_expand_compare (GET_CODE (operands[0]),
17550 [(trap_if (match_operator 0 "comparison_operator"
17551 [(reg 17) (const_int 0)])
17552 (match_operand 1 "const_int_operand" ""))]
17556 operands[2] = gen_label_rtx ();
17557 output_asm_insn (\"j%c0\\t%l2\; int\\t%1\", operands);
17558 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
17559 CODE_LABEL_NUMBER (operands[2]));
17563 ;; Pentium III SIMD instructions.
17565 ;; Moves for SSE/MMX regs.
17567 (define_insn "movv4sf_internal"
17568 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17569 (match_operand:V4SF 1 "general_operand" "xm,x"))]
17571 ;; @@@ let's try to use movaps here.
17572 "movaps\\t{%1, %0|%0, %1}"
17573 [(set_attr "type" "sse")])
17575 (define_insn "movv4si_internal"
17576 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17577 (match_operand:V4SI 1 "general_operand" "xm,x"))]
17579 ;; @@@ let's try to use movaps here.
17580 "movaps\\t{%1, %0|%0, %1}"
17581 [(set_attr "type" "sse")])
17583 (define_insn "movv8qi_internal"
17584 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17585 (match_operand:V8QI 1 "general_operand" "ym,y"))]
17587 "movq\\t{%1, %0|%0, %1}"
17588 [(set_attr "type" "mmx")])
17590 (define_insn "movv4hi_internal"
17591 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17592 (match_operand:V4HI 1 "general_operand" "ym,y"))]
17594 "movq\\t{%1, %0|%0, %1}"
17595 [(set_attr "type" "mmx")])
17597 (define_insn "movv2si_internal"
17598 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17599 (match_operand:V2SI 1 "general_operand" "ym,y"))]
17601 "movq\\t{%1, %0|%0, %1}"
17602 [(set_attr "type" "mmx")])
17604 (define_expand "movti"
17605 [(set (match_operand:TI 0 "general_operand" "")
17606 (match_operand:TI 1 "general_operand" ""))]
17610 /* For constants other than zero into memory. We do not know how the
17611 instructions used to build constants modify the upper 64 bits
17612 of the register, once we have that information we may be able
17613 to handle some of them more efficiently. */
17614 if ((reload_in_progress | reload_completed) == 0
17615 && register_operand (operands[0], TImode)
17616 && CONSTANT_P (operands[1]))
17618 rtx addr = gen_reg_rtx (Pmode);
17620 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
17621 operands[1] = gen_rtx_MEM (TImode, addr);
17624 /* Make operand1 a register if it isn't already. */
17625 if ((reload_in_progress | reload_completed) == 0
17626 && !register_operand (operands[0], TImode)
17627 && !register_operand (operands[1], TImode)
17628 && operands[1] != CONST0_RTX (TImode))
17630 rtx temp = force_reg (TImode, operands[1]);
17631 emit_move_insn (operands[0], temp);
17636 (define_expand "movv4sf"
17637 [(set (match_operand:V4SF 0 "general_operand" "")
17638 (match_operand:V4SF 1 "general_operand" ""))]
17642 /* For constants other than zero into memory. We do not know how the
17643 instructions used to build constants modify the upper 64 bits
17644 of the register, once we have that information we may be able
17645 to handle some of them more efficiently. */
17646 if ((reload_in_progress | reload_completed) == 0
17647 && register_operand (operands[0], V4SFmode)
17648 && CONSTANT_P (operands[1]))
17650 rtx addr = gen_reg_rtx (Pmode);
17652 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
17653 operands[1] = gen_rtx_MEM (V4SFmode, addr);
17656 /* Make operand1 a register if it isn't already. */
17657 if ((reload_in_progress | reload_completed) == 0
17658 && !register_operand (operands[0], V4SFmode)
17659 && !register_operand (operands[1], V4SFmode)
17660 && operands[1] != CONST0_RTX (V4SFmode))
17662 rtx temp = force_reg (V4SFmode, operands[1]);
17663 emit_move_insn (operands[0], temp);
17668 (define_expand "movv4si"
17669 [(set (match_operand:V4SI 0 "general_operand" "")
17670 (match_operand:V4SI 1 "general_operand" ""))]
17674 /* For constants other than zero into memory. We do not know how the
17675 instructions used to build constants modify the upper 64 bits
17676 of the register, once we have that information we may be able
17677 to handle some of them more efficiently. */
17678 if ((reload_in_progress | reload_completed) == 0
17679 && register_operand (operands[0], V4SImode)
17680 && CONSTANT_P (operands[1]))
17682 rtx addr = gen_reg_rtx (Pmode);
17684 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
17685 operands[1] = gen_rtx_MEM (V4SImode, addr);
17688 /* Make operand1 a register if it isn't already. */
17689 if ((reload_in_progress | reload_completed) == 0
17690 && !register_operand (operands[0], V4SImode)
17691 && !register_operand (operands[1], V4SImode)
17692 && operands[1] != CONST0_RTX (V4SImode))
17694 rtx temp = force_reg (V4SImode, operands[1]);
17695 emit_move_insn (operands[0], temp);
17700 (define_expand "movv2si"
17701 [(set (match_operand:V2SI 0 "general_operand" "")
17702 (match_operand:V2SI 1 "general_operand" ""))]
17706 /* For constants other than zero into memory. We do not know how the
17707 instructions used to build constants modify the upper 64 bits
17708 of the register, once we have that information we may be able
17709 to handle some of them more efficiently. */
17710 if ((reload_in_progress | reload_completed) == 0
17711 && register_operand (operands[0], V2SImode)
17712 && CONSTANT_P (operands[1]))
17714 rtx addr = gen_reg_rtx (Pmode);
17716 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
17717 operands[1] = gen_rtx_MEM (V2SImode, addr);
17720 /* Make operand1 a register if it isn't already. */
17721 if ((reload_in_progress | reload_completed) == 0
17722 && !register_operand (operands[0], V2SImode)
17723 && !register_operand (operands[1], V2SImode)
17724 && operands[1] != CONST0_RTX (V2SImode))
17726 rtx temp = force_reg (V2SImode, operands[1]);
17727 emit_move_insn (operands[0], temp);
17732 (define_expand "movv4hi"
17733 [(set (match_operand:V4HI 0 "general_operand" "")
17734 (match_operand:V4HI 1 "general_operand" ""))]
17738 /* For constants other than zero into memory. We do not know how the
17739 instructions used to build constants modify the upper 64 bits
17740 of the register, once we have that information we may be able
17741 to handle some of them more efficiently. */
17742 if ((reload_in_progress | reload_completed) == 0
17743 && register_operand (operands[0], V4HImode)
17744 && CONSTANT_P (operands[1]))
17746 rtx addr = gen_reg_rtx (Pmode);
17748 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
17749 operands[1] = gen_rtx_MEM (V4HImode, addr);
17752 /* Make operand1 a register if it isn't already. */
17753 if ((reload_in_progress | reload_completed) == 0
17754 && !register_operand (operands[0], V4HImode)
17755 && !register_operand (operands[1], V4HImode)
17756 && operands[1] != CONST0_RTX (V4HImode))
17758 rtx temp = force_reg (V4HImode, operands[1]);
17759 emit_move_insn (operands[0], temp);
17764 (define_expand "movv8qi"
17765 [(set (match_operand:V8QI 0 "general_operand" "")
17766 (match_operand:V8QI 1 "general_operand" ""))]
17770 /* For constants other than zero into memory. We do not know how the
17771 instructions used to build constants modify the upper 64 bits
17772 of the register, once we have that information we may be able
17773 to handle some of them more efficiently. */
17774 if ((reload_in_progress | reload_completed) == 0
17775 && register_operand (operands[0], V8QImode)
17776 && CONSTANT_P (operands[1]))
17778 rtx addr = gen_reg_rtx (Pmode);
17780 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
17781 operands[1] = gen_rtx_MEM (V8QImode, addr);
17784 /* Make operand1 a register if it isn't already. */
17785 if ((reload_in_progress | reload_completed) == 0
17786 && !register_operand (operands[0], V8QImode)
17787 && !register_operand (operands[1], V8QImode)
17788 && operands[1] != CONST0_RTX (V8QImode))
17790 rtx temp = force_reg (V8QImode, operands[1]);
17791 emit_move_insn (operands[0], temp);
17796 (define_insn_and_split "*pushti"
17797 [(set (match_operand:TI 0 "push_operand" "=<")
17798 (match_operand:TI 1 "nonmemory_operand" "x"))]
17802 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17803 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17805 [(set_attr "type" "sse")])
17807 (define_insn_and_split "*pushv4sf"
17808 [(set (match_operand:V4SF 0 "push_operand" "=<")
17809 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
17813 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17814 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
17816 [(set_attr "type" "sse")])
17818 (define_insn_and_split "*pushv4si"
17819 [(set (match_operand:V4SI 0 "push_operand" "=<")
17820 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
17824 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17825 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
17827 [(set_attr "type" "sse")])
17829 (define_insn_and_split "*pushv2si"
17830 [(set (match_operand:V2SI 0 "push_operand" "=<")
17831 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
17835 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17836 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
17838 [(set_attr "type" "mmx")])
17840 (define_insn_and_split "*pushv4hi"
17841 [(set (match_operand:V4HI 0 "push_operand" "=<")
17842 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
17846 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17847 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
17849 [(set_attr "type" "mmx")])
17851 (define_insn_and_split "*pushv8qi"
17852 [(set (match_operand:V8QI 0 "push_operand" "=<")
17853 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
17857 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17858 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
17860 [(set_attr "type" "mmx")])
17862 (define_insn "movti_internal"
17863 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
17864 (match_operand:TI 1 "general_operand" "xm,x"))]
17867 movaps\\t{%1, %0|%0, %1}
17868 movaps\\t{%1, %0|%0, %1}"
17869 [(set_attr "type" "sse")])
17871 ;; These two patterns are useful for specifying exactly whether to use
17872 ;; movaps or movups
17873 (define_insn "sse_movaps"
17874 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17875 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
17878 movaps\\t{%1, %0|%0, %1}
17879 movaps\\t{%1, %0|%0, %1}"
17880 [(set_attr "type" "sse")])
17882 (define_insn "sse_movups"
17883 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17884 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
17887 movups\\t{%1, %0|%0, %1}
17888 movups\\t{%1, %0|%0, %1}"
17889 [(set_attr "type" "sse")])
17892 ;; SSE Strange Moves.
17894 (define_insn "sse_movmskps"
17895 [(set (match_operand:SI 0 "register_operand" "=r")
17896 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
17898 "movmskps\\t{%1, %0|%0, %1}"
17899 [(set_attr "type" "sse")])
17901 (define_insn "mmx_pmovmskb"
17902 [(set (match_operand:SI 0 "register_operand" "=r")
17903 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
17905 "pmovmskb\\t{%1, %0|%0, %1}"
17906 [(set_attr "type" "sse")])
17908 (define_insn "mmx_maskmovq"
17909 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17910 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17911 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17913 ;; @@@ check ordering of operands in intel/nonintel syntax
17914 "maskmovq\\t{%2, %1|%1, %2}"
17915 [(set_attr "type" "sse")])
17917 (define_insn "sse_movntv4sf"
17918 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17919 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17921 "movntps\\t{%1, %0|%0, %1}"
17922 [(set_attr "type" "sse")])
17924 (define_insn "sse_movntdi"
17925 [(set (match_operand:DI 0 "memory_operand" "=m")
17926 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
17928 "movntq\\t{%1, %0|%0, %1}"
17929 [(set_attr "type" "sse")])
17931 (define_insn "sse_movhlps"
17932 [(set (match_operand:V4SF 0 "register_operand" "=x")
17934 (match_operand:V4SF 1 "register_operand" "0")
17935 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17936 (parallel [(const_int 2)
17942 "movhlps\\t{%2, %0|%0, %2}"
17943 [(set_attr "type" "sse")])
17945 (define_insn "sse_movlhps"
17946 [(set (match_operand:V4SF 0 "register_operand" "=x")
17948 (match_operand:V4SF 1 "register_operand" "0")
17949 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17950 (parallel [(const_int 2)
17956 "movlhps\\t{%2, %0|%0, %2}"
17957 [(set_attr "type" "sse")])
17959 (define_insn "sse_movhps"
17960 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17962 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17963 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17965 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17966 "movhps\\t{%2, %0|%0, %2}"
17967 [(set_attr "type" "sse")])
17969 (define_insn "sse_movlps"
17970 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17972 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17973 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17975 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17976 "movlps\\t{%2, %0|%0, %2}"
17977 [(set_attr "type" "sse")])
17979 (define_insn "sse_loadss"
17980 [(set (match_operand:V4SF 0 "register_operand" "=x")
17982 (match_operand:V4SF 1 "memory_operand" "m")
17983 (vec_duplicate:V4SF (float:SF (const_int 0)))
17986 "movss\\t{%1, %0|%0, %1}"
17987 [(set_attr "type" "sse")])
17989 (define_insn "sse_movss"
17990 [(set (match_operand:V4SF 0 "register_operand" "=x")
17992 (match_operand:V4SF 1 "register_operand" "0")
17993 (match_operand:V4SF 2 "register_operand" "x")
17996 "movss\\t{%2, %0|%0, %2}"
17997 [(set_attr "type" "sse")])
17999 (define_insn "sse_storess"
18000 [(set (match_operand:SF 0 "memory_operand" "=m")
18002 (match_operand:V4SF 1 "register_operand" "x")
18003 (parallel [(const_int 0)])))]
18005 "movss\\t{%1, %0|%0, %1}"
18006 [(set_attr "type" "sse")])
18008 (define_insn "sse_shufps"
18009 [(set (match_operand:V4SF 0 "register_operand" "=x")
18010 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
18011 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
18012 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18014 ;; @@@ check operand order for intel/nonintel syntax
18015 "shufps\\t{%3, %2, %0|%0, %2, %3}"
18016 [(set_attr "type" "sse")])
18021 (define_insn "addv4sf3"
18022 [(set (match_operand:V4SF 0 "register_operand" "=x")
18023 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18024 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18026 "addps\\t{%2, %0|%0, %2}"
18027 [(set_attr "type" "sse")])
18029 (define_insn "vmaddv4sf3"
18030 [(set (match_operand:V4SF 0 "register_operand" "=x")
18031 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18032 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18036 "addss\\t{%2, %0|%0, %2}"
18037 [(set_attr "type" "sse")])
18039 (define_insn "subv4sf3"
18040 [(set (match_operand:V4SF 0 "register_operand" "=x")
18041 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18042 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18044 "subps\\t{%2, %0|%0, %2}"
18045 [(set_attr "type" "sse")])
18047 (define_insn "vmsubv4sf3"
18048 [(set (match_operand:V4SF 0 "register_operand" "=x")
18049 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18050 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18054 "subss\\t{%2, %0|%0, %2}"
18055 [(set_attr "type" "sse")])
18057 (define_insn "mulv4sf3"
18058 [(set (match_operand:V4SF 0 "register_operand" "=x")
18059 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18060 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18062 "mulps\\t{%2, %0|%0, %2}"
18063 [(set_attr "type" "sse")])
18065 (define_insn "vmmulv4sf3"
18066 [(set (match_operand:V4SF 0 "register_operand" "=x")
18067 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18068 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18072 "mulss\\t{%2, %0|%0, %2}"
18073 [(set_attr "type" "sse")])
18075 (define_insn "divv4sf3"
18076 [(set (match_operand:V4SF 0 "register_operand" "=x")
18077 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18078 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18080 "divps\\t{%2, %0|%0, %2}"
18081 [(set_attr "type" "sse")])
18083 (define_insn "vmdivv4sf3"
18084 [(set (match_operand:V4SF 0 "register_operand" "=x")
18085 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18086 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18090 "divss\\t{%2, %0|%0, %2}"
18091 [(set_attr "type" "sse")])
18094 ;; SSE square root/reciprocal
18096 (define_insn "rcpv4sf2"
18097 [(set (match_operand:V4SF 0 "register_operand" "=x")
18098 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
18100 "rcpps\\t{%1, %0|%0, %1}"
18101 [(set_attr "type" "sse")])
18103 (define_insn "vmrcpv4sf2"
18104 [(set (match_operand:V4SF 0 "register_operand" "=x")
18105 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
18106 (match_operand:V4SF 2 "register_operand" "0")
18109 "rcpss\\t{%1, %0|%0, %1}"
18110 [(set_attr "type" "sse")])
18112 (define_insn "rsqrtv4sf2"
18113 [(set (match_operand:V4SF 0 "register_operand" "=x")
18114 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
18116 "rsqrtps\\t{%1, %0|%0, %1}"
18117 [(set_attr "type" "sse")])
18119 (define_insn "vmrsqrtv4sf2"
18120 [(set (match_operand:V4SF 0 "register_operand" "=x")
18121 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
18122 (match_operand:V4SF 2 "register_operand" "0")
18125 "rsqrtss\\t{%1, %0|%0, %1}"
18126 [(set_attr "type" "sse")])
18128 (define_insn "sqrtv4sf2"
18129 [(set (match_operand:V4SF 0 "register_operand" "=x")
18130 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
18132 "sqrtps\\t{%1, %0|%0, %1}"
18133 [(set_attr "type" "sse")])
18135 (define_insn "vmsqrtv4sf2"
18136 [(set (match_operand:V4SF 0 "register_operand" "=x")
18137 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
18138 (match_operand:V4SF 2 "register_operand" "0")
18141 "sqrtss\\t{%1, %0|%0, %1}"
18142 [(set_attr "type" "sse")])
18145 ;; SSE logical operations.
18147 ;; These are not called andti3 etc. because we really really don't want
18148 ;; the compiler to widen DImode ands to TImode ands and then try to move
18149 ;; into DImode subregs of SSE registers, and them together, and move out
18150 ;; of DImode subregs again!
18152 (define_insn "*sse_andti3_df_1"
18153 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18154 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18155 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18157 "andpd\\t{%2, %0|%0, %2}"
18158 [(set_attr "type" "sse")])
18160 (define_insn "*sse_andti3_df_2"
18161 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18162 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18163 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18165 "andpd\\t{%2, %0|%0, %2}"
18166 [(set_attr "type" "sse")])
18168 (define_insn "*sse_andti3_sf_1"
18169 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18170 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18171 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18173 "andps\\t{%2, %0|%0, %2}"
18174 [(set_attr "type" "sse")])
18176 (define_insn "*sse_andti3_sf_2"
18177 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18178 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18179 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18181 "andps\\t{%2, %0|%0, %2}"
18182 [(set_attr "type" "sse")])
18184 (define_insn "sse_andti3"
18185 [(set (match_operand:TI 0 "register_operand" "=x")
18186 (and:TI (match_operand:TI 1 "register_operand" "%0")
18187 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18188 "TARGET_SSE && !TARGET_SSE2"
18189 "andps\\t{%2, %0|%0, %2}"
18190 [(set_attr "type" "sse")])
18192 (define_insn "*sse_andti3_sse2"
18193 [(set (match_operand:TI 0 "register_operand" "=x")
18194 (and:TI (match_operand:TI 1 "register_operand" "%0")
18195 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18197 "pand\\t{%2, %0|%0, %2}"
18198 [(set_attr "type" "sse")])
18200 (define_insn "*sse_nandti3_df"
18201 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18202 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18203 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18205 "andnpd\\t{%2, %0|%0, %2}"
18206 [(set_attr "type" "sse")])
18208 (define_insn "*sse_nandti3_sf"
18209 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18210 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18211 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18213 "andnps\\t{%2, %0|%0, %2}"
18214 [(set_attr "type" "sse")])
18216 (define_insn "sse_nandti3"
18217 [(set (match_operand:TI 0 "register_operand" "=x")
18218 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18219 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18220 "TARGET_SSE && !TARGET_SSE2"
18221 "andnps\\t{%2, %0|%0, %2}"
18222 [(set_attr "type" "sse")])
18224 (define_insn "*sse_nandti3_sse2"
18225 [(set (match_operand:TI 0 "register_operand" "=x")
18226 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18227 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18229 "pnand\\t{%2, %0|%0, %2}"
18230 [(set_attr "type" "sse")])
18232 (define_insn "*sse_iorti3_df_1"
18233 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18234 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18235 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18237 "orpd\\t{%2, %0|%0, %2}"
18238 [(set_attr "type" "sse")])
18240 (define_insn "*sse_iorti3_df_2"
18241 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18242 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18243 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18245 "orpd\\t{%2, %0|%0, %2}"
18246 [(set_attr "type" "sse")])
18248 (define_insn "*sse_iorti3_sf_1"
18249 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18250 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18251 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18253 "orps\\t{%2, %0|%0, %2}"
18254 [(set_attr "type" "sse")])
18256 (define_insn "*sse_iorti3_sf_2"
18257 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18258 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18259 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18261 "orps\\t{%2, %0|%0, %2}"
18262 [(set_attr "type" "sse")])
18264 (define_insn "sse_iorti3"
18265 [(set (match_operand:TI 0 "register_operand" "=x")
18266 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18267 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18268 "TARGET_SSE && !TARGET_SSE2"
18269 "orps\\t{%2, %0|%0, %2}"
18270 [(set_attr "type" "sse")])
18272 (define_insn "*sse_iorti3_sse2"
18273 [(set (match_operand:TI 0 "register_operand" "=x")
18274 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18275 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18277 "por\\t{%2, %0|%0, %2}"
18278 [(set_attr "type" "sse")])
18280 (define_insn "*sse_xorti3_df_1"
18281 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18282 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18283 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18285 "xorpd\\t{%2, %0|%0, %2}"
18286 [(set_attr "type" "sse")])
18288 (define_insn "*sse_xorti3_df_2"
18289 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18290 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18291 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18293 "xorpd\\t{%2, %0|%0, %2}"
18294 [(set_attr "type" "sse")])
18296 (define_insn "*sse_xorti3_sf_1"
18297 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18298 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18299 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18301 "xorps\\t{%2, %0|%0, %2}"
18302 [(set_attr "type" "sse")])
18304 (define_insn "*sse_xorti3_sf_2"
18305 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18306 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18307 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18309 "xorps\\t{%2, %0|%0, %2}"
18310 [(set_attr "type" "sse")])
18312 (define_insn "sse_xorti3"
18313 [(set (match_operand:TI 0 "register_operand" "=x")
18314 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18315 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18316 "TARGET_SSE && !TARGET_SSE2"
18317 "xorps\\t{%2, %0|%0, %2}"
18318 [(set_attr "type" "sse")])
18320 (define_insn "*sse_xorti3_sse2"
18321 [(set (match_operand:TI 0 "register_operand" "=x")
18322 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18323 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18325 "pxor\\t{%2, %0|%0, %2}"
18326 [(set_attr "type" "sse")])
18328 ;; Use xor, but don't show input operands so they aren't live before
18330 (define_insn "sse_clrti"
18331 [(set (match_operand:TI 0 "register_operand" "=x")
18332 (unspec:TI [(const_int 0)] 45))]
18334 "xorps\\t{%0, %0|%0, %0}"
18335 [(set_attr "type" "sse")])
18338 ;; SSE mask-generating compares
18340 (define_insn "maskcmpv4sf3"
18341 [(set (match_operand:V4SI 0 "register_operand" "=x")
18342 (match_operator:V4SI 3 "sse_comparison_operator"
18343 [(match_operand:V4SF 1 "register_operand" "0")
18344 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
18346 "cmp%D3ps\\t{%2, %0|%0, %2}"
18347 [(set_attr "type" "sse")])
18349 (define_insn "maskncmpv4sf3"
18350 [(set (match_operand:V4SI 0 "register_operand" "=x")
18352 (match_operator:V4SI 3 "sse_comparison_operator"
18353 [(match_operand:V4SF 1 "register_operand" "0")
18354 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
18356 "cmpn%D3ps\\t{%2, %0|%0, %2}"
18357 [(set_attr "type" "sse")])
18359 (define_insn "vmmaskcmpv4sf3"
18360 [(set (match_operand:V4SI 0 "register_operand" "=x")
18362 (match_operator:V4SI 3 "sse_comparison_operator"
18363 [(match_operand:V4SF 1 "register_operand" "0")
18364 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
18368 "cmp%D3ss\\t{%2, %0|%0, %2}"
18369 [(set_attr "type" "sse")])
18371 (define_insn "vmmaskncmpv4sf3"
18372 [(set (match_operand:V4SI 0 "register_operand" "=x")
18375 (match_operator:V4SI 3 "sse_comparison_operator"
18376 [(match_operand:V4SF 1 "register_operand" "0")
18377 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
18378 (subreg:V4SI (match_dup 1) 0)
18381 "cmp%D3ss\\t{%2, %0|%0, %2}"
18382 [(set_attr "type" "sse")])
18384 (define_insn "sse_comi"
18385 [(set (reg:CCFP 17)
18386 (match_operator:CCFP 2 "sse_comparison_operator"
18388 (match_operand:V4SF 0 "register_operand" "x")
18389 (parallel [(const_int 0)]))
18391 (match_operand:V4SF 1 "register_operand" "x")
18392 (parallel [(const_int 0)]))]))]
18394 "comiss\\t{%2, %0|%0, %2}"
18395 [(set_attr "type" "sse")])
18397 (define_insn "sse_ucomi"
18398 [(set (reg:CCFPU 17)
18399 (match_operator:CCFPU 2 "sse_comparison_operator"
18401 (match_operand:V4SF 0 "register_operand" "x")
18402 (parallel [(const_int 0)]))
18404 (match_operand:V4SF 1 "register_operand" "x")
18405 (parallel [(const_int 0)]))]))]
18407 "ucomiss\\t{%2, %0|%0, %2}"
18408 [(set_attr "type" "sse")])
18413 (define_insn "sse_unpckhps"
18414 [(set (match_operand:V4SF 0 "register_operand" "=x")
18416 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18417 (parallel [(const_int 2)
18421 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18422 (parallel [(const_int 0)
18428 "unpckhps\\t{%2, %0|%0, %2}"
18429 [(set_attr "type" "sse")])
18431 (define_insn "sse_unpcklps"
18432 [(set (match_operand:V4SF 0 "register_operand" "=x")
18434 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18435 (parallel [(const_int 0)
18439 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18440 (parallel [(const_int 2)
18446 "unpcklps\\t{%2, %0|%0, %2}"
18447 [(set_attr "type" "sse")])
18452 (define_insn "smaxv4sf3"
18453 [(set (match_operand:V4SF 0 "register_operand" "=x")
18454 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18455 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18457 "maxps\\t{%2, %0|%0, %2}"
18458 [(set_attr "type" "sse")])
18460 (define_insn "vmsmaxv4sf3"
18461 [(set (match_operand:V4SF 0 "register_operand" "=x")
18462 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18463 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18467 "maxss\\t{%2, %0|%0, %2}"
18468 [(set_attr "type" "sse")])
18470 (define_insn "sminv4sf3"
18471 [(set (match_operand:V4SF 0 "register_operand" "=x")
18472 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18473 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18475 "minps\\t{%2, %0|%0, %2}"
18476 [(set_attr "type" "sse")])
18478 (define_insn "vmsminv4sf3"
18479 [(set (match_operand:V4SF 0 "register_operand" "=x")
18480 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18481 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18485 "minss\\t{%2, %0|%0, %2}"
18486 [(set_attr "type" "sse")])
18489 ;; SSE <-> integer/MMX conversions
18491 (define_insn "cvtpi2ps"
18492 [(set (match_operand:V4SF 0 "register_operand" "=x")
18493 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18494 (vec_duplicate:V4SF
18495 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
18498 "cvtpi2ps\\t{%2, %0|%0, %2}"
18499 [(set_attr "type" "sse")])
18501 (define_insn "cvtps2pi"
18502 [(set (match_operand:V2SI 0 "register_operand" "=y")
18503 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18508 "cvtps2pi\\t{%1, %0|%0, %1}"
18509 [(set_attr "type" "sse")])
18511 (define_insn "cvttps2pi"
18512 [(set (match_operand:V2SI 0 "register_operand" "=y")
18513 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18518 "cvttps2pi\\t{%1, %0|%0, %1}"
18519 [(set_attr "type" "sse")])
18521 (define_insn "cvtsi2ss"
18522 [(set (match_operand:V4SF 0 "register_operand" "=x")
18523 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18524 (vec_duplicate:V4SF
18525 (float:SF (match_operand:SI 2 "register_operand" "rm")))
18528 "cvtsi2ss\\t{%2, %0|%0, %2}"
18529 [(set_attr "type" "sse")])
18531 (define_insn "cvtss2si"
18532 [(set (match_operand:SI 0 "register_operand" "=y")
18533 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18534 (parallel [(const_int 0)])))]
18536 "cvtss2si\\t{%1, %0|%0, %1}"
18537 [(set_attr "type" "sse")])
18539 (define_insn "cvttss2si"
18540 [(set (match_operand:SI 0 "register_operand" "=y")
18541 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18542 (parallel [(const_int 0)])))]
18544 "cvttss2si\\t{%1, %0|%0, %1}"
18545 [(set_attr "type" "sse")])
18552 (define_insn "addv8qi3"
18553 [(set (match_operand:V8QI 0 "register_operand" "=y")
18554 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18555 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18557 "paddb\\t{%2, %0|%0, %2}"
18558 [(set_attr "type" "mmx")])
18560 (define_insn "addv4hi3"
18561 [(set (match_operand:V4HI 0 "register_operand" "=y")
18562 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18563 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18565 "paddw\\t{%2, %0|%0, %2}"
18566 [(set_attr "type" "mmx")])
18568 (define_insn "addv2si3"
18569 [(set (match_operand:V2SI 0 "register_operand" "=y")
18570 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18571 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18573 "paddd\\t{%2, %0|%0, %2}"
18574 [(set_attr "type" "mmx")])
18576 (define_insn "ssaddv8qi3"
18577 [(set (match_operand:V8QI 0 "register_operand" "=y")
18578 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18579 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18581 "paddsb\\t{%2, %0|%0, %2}"
18582 [(set_attr "type" "mmx")])
18584 (define_insn "ssaddv4hi3"
18585 [(set (match_operand:V4HI 0 "register_operand" "=y")
18586 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18587 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18589 "paddsw\\t{%2, %0|%0, %2}"
18590 [(set_attr "type" "mmx")])
18592 (define_insn "usaddv8qi3"
18593 [(set (match_operand:V8QI 0 "register_operand" "=y")
18594 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18595 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18597 "paddusb\\t{%2, %0|%0, %2}"
18598 [(set_attr "type" "mmx")])
18600 (define_insn "usaddv4hi3"
18601 [(set (match_operand:V4HI 0 "register_operand" "=y")
18602 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18603 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18605 "paddusw\\t{%2, %0|%0, %2}"
18606 [(set_attr "type" "mmx")])
18608 (define_insn "subv8qi3"
18609 [(set (match_operand:V8QI 0 "register_operand" "=y")
18610 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18611 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18613 "psubb\\t{%2, %0|%0, %2}"
18614 [(set_attr "type" "mmx")])
18616 (define_insn "subv4hi3"
18617 [(set (match_operand:V4HI 0 "register_operand" "=y")
18618 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18619 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18621 "psubw\\t{%2, %0|%0, %2}"
18622 [(set_attr "type" "mmx")])
18624 (define_insn "subv2si3"
18625 [(set (match_operand:V2SI 0 "register_operand" "=y")
18626 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18627 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18629 "psubd\\t{%2, %0|%0, %2}"
18630 [(set_attr "type" "mmx")])
18632 (define_insn "sssubv8qi3"
18633 [(set (match_operand:V8QI 0 "register_operand" "=y")
18634 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18635 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18637 "psubsb\\t{%2, %0|%0, %2}"
18638 [(set_attr "type" "mmx")])
18640 (define_insn "sssubv4hi3"
18641 [(set (match_operand:V4HI 0 "register_operand" "=y")
18642 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18643 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18645 "psubsw\\t{%2, %0|%0, %2}"
18646 [(set_attr "type" "mmx")])
18648 (define_insn "ussubv8qi3"
18649 [(set (match_operand:V8QI 0 "register_operand" "=y")
18650 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18651 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18653 "psubusb\\t{%2, %0|%0, %2}"
18654 [(set_attr "type" "mmx")])
18656 (define_insn "ussubv4hi3"
18657 [(set (match_operand:V4HI 0 "register_operand" "=y")
18658 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18659 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18661 "psubusw\\t{%2, %0|%0, %2}"
18662 [(set_attr "type" "mmx")])
18664 (define_insn "mulv4hi3"
18665 [(set (match_operand:V4HI 0 "register_operand" "=y")
18666 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
18667 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18669 "pmullw\\t{%2, %0|%0, %2}"
18670 [(set_attr "type" "mmx")])
18672 (define_insn "smulv4hi3_highpart"
18673 [(set (match_operand:V4HI 0 "register_operand" "=y")
18676 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18677 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18680 "pmulhw\\t{%2, %0|%0, %2}"
18681 [(set_attr "type" "mmx")])
18683 (define_insn "umulv4hi3_highpart"
18684 [(set (match_operand:V4HI 0 "register_operand" "=y")
18687 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18688 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18691 "pmulhuw\\t{%2, %0|%0, %2}"
18692 [(set_attr "type" "mmx")])
18694 (define_insn "mmx_pmaddwd"
18695 [(set (match_operand:V2SI 0 "register_operand" "=y")
18698 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
18699 (parallel [(const_int 0)
18701 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18702 (parallel [(const_int 0)
18705 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
18706 (parallel [(const_int 1)
18708 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
18709 (parallel [(const_int 1)
18710 (const_int 3)]))))))]
18712 "pmaddwd\\t{%2, %0|%0, %2}"
18713 [(set_attr "type" "mmx")])
18716 ;; MMX logical operations
18717 ;; Note we don't want to declare these as regular iordi3 insns to prevent
18718 ;; normal code that also wants to use the FPU from getting broken.
18719 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
18720 (define_insn "mmx_iordi3"
18721 [(set (match_operand:DI 0 "register_operand" "=y")
18723 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18724 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18726 "por\\t{%2, %0|%0, %2}"
18727 [(set_attr "type" "mmx")])
18729 (define_insn "mmx_xordi3"
18730 [(set (match_operand:DI 0 "register_operand" "=y")
18732 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18733 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18735 "pxor\\t{%2, %0|%0, %2}"
18736 [(set_attr "type" "mmx")])
18738 ;; Same as pxor, but don't show input operands so that we don't think
18740 (define_insn "mmx_clrdi"
18741 [(set (match_operand:DI 0 "register_operand" "=y")
18742 (unspec:DI [(const_int 0)] 45))]
18744 "pxor\\t{%0, %0|%0, %0}"
18745 [(set_attr "type" "mmx")])
18747 (define_insn "mmx_anddi3"
18748 [(set (match_operand:DI 0 "register_operand" "=y")
18750 [(and:DI (match_operand:DI 1 "register_operand" "0")
18751 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18753 "pand\\t{%2, %0|%0, %2}"
18754 [(set_attr "type" "mmx")])
18756 (define_insn "mmx_nanddi3"
18757 [(set (match_operand:DI 0 "register_operand" "=y")
18759 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
18760 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18762 "pandn\\t{%2, %0|%0, %2}"
18763 [(set_attr "type" "mmx")])
18766 ;; MMX unsigned averages/sum of absolute differences
18768 (define_insn "mmx_uavgv8qi3"
18769 [(set (match_operand:V8QI 0 "register_operand" "=y")
18771 (plus:V8QI (plus:V8QI
18772 (match_operand:V8QI 1 "register_operand" "0")
18773 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18774 (vec_const:V8QI (parallel [(const_int 1)
18784 "pavgb\\t{%2, %0|%0, %2}"
18785 [(set_attr "type" "sse")])
18787 (define_insn "mmx_uavgv4hi3"
18788 [(set (match_operand:V4HI 0 "register_operand" "=y")
18790 (plus:V4HI (plus:V4HI
18791 (match_operand:V4HI 1 "register_operand" "0")
18792 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18793 (vec_const:V4HI (parallel [(const_int 1)
18799 "pavgw\\t{%2, %0|%0, %2}"
18800 [(set_attr "type" "sse")])
18802 (define_insn "mmx_psadbw"
18803 [(set (match_operand:V8QI 0 "register_operand" "=y")
18804 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18805 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
18807 "psadbw\\t{%2, %0|%0, %2}"
18808 [(set_attr "type" "sse")])
18811 ;; MMX insert/extract/shuffle
18813 (define_insn "mmx_pinsrw"
18814 [(set (match_operand:V4HI 0 "register_operand" "=y")
18815 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
18816 (vec_duplicate:V4HI
18817 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
18818 (match_operand:SI 3 "immediate_operand" "i")))]
18820 "pinsrw\\t{%3, %2, %0|%0, %2, %3}"
18821 [(set_attr "type" "sse")])
18823 (define_insn "mmx_pextrw"
18824 [(set (match_operand:SI 0 "register_operand" "=r")
18825 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
18827 [(match_operand:SI 2 "immediate_operand" "i")]))))]
18829 "pextrw\\t{%2, %1, %0|%0, %1, %2}"
18830 [(set_attr "type" "sse")])
18832 (define_insn "mmx_pshufw"
18833 [(set (match_operand:V4HI 0 "register_operand" "=y")
18834 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
18835 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18836 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18838 "pshufw\\t{%3, %2, %0|%0, %2, %3}"
18839 [(set_attr "type" "sse")])
18842 ;; MMX mask-generating comparisons
18844 (define_insn "eqv8qi3"
18845 [(set (match_operand:V8QI 0 "register_operand" "=y")
18846 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
18847 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18849 "pcmpeqb\\t{%2, %0|%0, %2}"
18850 [(set_attr "type" "mmx")])
18852 (define_insn "eqv4hi3"
18853 [(set (match_operand:V4HI 0 "register_operand" "=y")
18854 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
18855 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18857 "pcmpeqw\\t{%2, %0|%0, %2}"
18858 [(set_attr "type" "mmx")])
18860 (define_insn "eqv2si3"
18861 [(set (match_operand:V2SI 0 "register_operand" "=y")
18862 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
18863 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18865 "pcmpeqd\\t{%2, %0|%0, %2}"
18866 [(set_attr "type" "mmx")])
18868 (define_insn "gtv8qi3"
18869 [(set (match_operand:V8QI 0 "register_operand" "=y")
18870 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
18871 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18873 "pcmpgtb\\t{%2, %0|%0, %2}"
18874 [(set_attr "type" "mmx")])
18876 (define_insn "gtv4hi3"
18877 [(set (match_operand:V4HI 0 "register_operand" "=y")
18878 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18879 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18881 "pcmpgtw\\t{%2, %0|%0, %2}"
18882 [(set_attr "type" "mmx")])
18884 (define_insn "gtv2si3"
18885 [(set (match_operand:V2SI 0 "register_operand" "=y")
18886 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18887 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18889 "pcmpgtd\\t{%2, %0|%0, %2}"
18890 [(set_attr "type" "mmx")])
18893 ;; MMX max/min insns
18895 (define_insn "umaxv8qi3"
18896 [(set (match_operand:V8QI 0 "register_operand" "=y")
18897 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
18898 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18900 "pmaxub\\t{%2, %0|%0, %2}"
18901 [(set_attr "type" "sse")])
18903 (define_insn "smaxv4hi3"
18904 [(set (match_operand:V4HI 0 "register_operand" "=y")
18905 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
18906 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18908 "pmaxsw\\t{%2, %0|%0, %2}"
18909 [(set_attr "type" "sse")])
18911 (define_insn "uminv8qi3"
18912 [(set (match_operand:V8QI 0 "register_operand" "=y")
18913 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
18914 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18916 "pminub\\t{%2, %0|%0, %2}"
18917 [(set_attr "type" "sse")])
18919 (define_insn "sminv4hi3"
18920 [(set (match_operand:V4HI 0 "register_operand" "=y")
18921 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
18922 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18924 "pminsw\\t{%2, %0|%0, %2}"
18925 [(set_attr "type" "sse")])
18930 (define_insn "ashrv4hi3"
18931 [(set (match_operand:V4HI 0 "register_operand" "=y")
18932 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18933 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18935 "psraw\\t{%2, %0|%0, %2}"
18936 [(set_attr "type" "mmx")])
18938 (define_insn "ashrv2si3"
18939 [(set (match_operand:V2SI 0 "register_operand" "=y")
18940 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18941 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18943 "psrad\\t{%2, %0|%0, %2}"
18944 [(set_attr "type" "mmx")])
18946 (define_insn "lshrv4hi3"
18947 [(set (match_operand:V4HI 0 "register_operand" "=y")
18948 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18949 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18951 "psrlw\\t{%2, %0|%0, %2}"
18952 [(set_attr "type" "mmx")])
18954 (define_insn "lshrv2si3"
18955 [(set (match_operand:V2SI 0 "register_operand" "=y")
18956 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18957 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18959 "psrld\\t{%2, %0|%0, %2}"
18960 [(set_attr "type" "mmx")])
18962 ;; See logical MMX insns.
18963 (define_insn "mmx_lshrdi3"
18964 [(set (match_operand:DI 0 "register_operand" "=y")
18966 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
18967 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18969 "psrlq\\t{%2, %0|%0, %2}"
18970 [(set_attr "type" "mmx")])
18972 (define_insn "ashlv4hi3"
18973 [(set (match_operand:V4HI 0 "register_operand" "=y")
18974 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
18975 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18977 "psllw\\t{%2, %0|%0, %2}"
18978 [(set_attr "type" "mmx")])
18980 (define_insn "ashlv2si3"
18981 [(set (match_operand:V2SI 0 "register_operand" "=y")
18982 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
18983 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18985 "pslld\\t{%2, %0|%0, %2}"
18986 [(set_attr "type" "mmx")])
18988 ;; See logical MMX insns.
18989 (define_insn "mmx_ashldi3"
18990 [(set (match_operand:DI 0 "register_operand" "=y")
18992 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
18993 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18995 "psllq\\t{%2, %0|%0, %2}"
18996 [(set_attr "type" "mmx")])
18999 ;; MMX pack/unpack insns.
19001 (define_insn "mmx_packsswb"
19002 [(set (match_operand:V8QI 0 "register_operand" "=y")
19004 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19005 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19007 "packsswb\\t{%2, %0|%0, %2}"
19008 [(set_attr "type" "mmx")])
19010 (define_insn "mmx_packssdw"
19011 [(set (match_operand:V4HI 0 "register_operand" "=y")
19013 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
19014 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
19016 "packssdw\\t{%2, %0|%0, %2}"
19017 [(set_attr "type" "mmx")])
19019 (define_insn "mmx_packuswb"
19020 [(set (match_operand:V8QI 0 "register_operand" "=y")
19022 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19023 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19025 "packuswb\\t{%2, %0|%0, %2}"
19026 [(set_attr "type" "mmx")])
19028 (define_insn "mmx_punpckhbw"
19029 [(set (match_operand:V8QI 0 "register_operand" "=y")
19031 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19032 (parallel [(const_int 4)
19040 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19041 (parallel [(const_int 0)
19051 "punpckhbw\\t{%2, %0|%0, %2}"
19052 [(set_attr "type" "mmx")])
19054 (define_insn "mmx_punpckhwd"
19055 [(set (match_operand:V4HI 0 "register_operand" "=y")
19057 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19058 (parallel [(const_int 0)
19062 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19063 (parallel [(const_int 2)
19069 "punpckhwd\\t{%2, %0|%0, %2}"
19070 [(set_attr "type" "mmx")])
19072 (define_insn "mmx_punpckhdq"
19073 [(set (match_operand:V2SI 0 "register_operand" "=y")
19075 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19076 (parallel [(const_int 0)
19078 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19079 (parallel [(const_int 1)
19083 "punpckhdq\\t{%2, %0|%0, %2}"
19084 [(set_attr "type" "mmx")])
19086 (define_insn "mmx_punpcklbw"
19087 [(set (match_operand:V8QI 0 "register_operand" "=y")
19089 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19090 (parallel [(const_int 0)
19098 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19099 (parallel [(const_int 4)
19109 "punpcklbw\\t{%2, %0|%0, %2}"
19110 [(set_attr "type" "mmx")])
19112 (define_insn "mmx_punpcklwd"
19113 [(set (match_operand:V4HI 0 "register_operand" "=y")
19115 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19116 (parallel [(const_int 2)
19120 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19121 (parallel [(const_int 0)
19127 "punpcklwd\\t{%2, %0|%0, %2}"
19128 [(set_attr "type" "mmx")])
19130 (define_insn "mmx_punpckldq"
19131 [(set (match_operand:V2SI 0 "register_operand" "=y")
19133 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19134 (parallel [(const_int 1)
19136 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19137 (parallel [(const_int 0)
19141 "punpckldq\\t{%2, %0|%0, %2}"
19142 [(set_attr "type" "mmx")])
19145 ;; Miscellaneous stuff
19147 (define_insn "emms"
19148 [(unspec_volatile [(const_int 0)] 31)
19149 (clobber (reg:XF 8))
19150 (clobber (reg:XF 9))
19151 (clobber (reg:XF 10))
19152 (clobber (reg:XF 11))
19153 (clobber (reg:XF 12))
19154 (clobber (reg:XF 13))
19155 (clobber (reg:XF 14))
19156 (clobber (reg:XF 15))
19157 (clobber (reg:DI 29))
19158 (clobber (reg:DI 30))
19159 (clobber (reg:DI 31))
19160 (clobber (reg:DI 32))
19161 (clobber (reg:DI 33))
19162 (clobber (reg:DI 34))
19163 (clobber (reg:DI 35))
19164 (clobber (reg:DI 36))]
19167 [(set_attr "type" "mmx")
19168 (set_attr "memory" "unknown")])
19170 (define_insn "ldmxcsr"
19171 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
19174 [(set_attr "type" "mmx")])
19176 (define_insn "stmxcsr"
19177 [(set (match_operand:SI 0 "memory_operand" "=m")
19178 (unspec_volatile:SI [(const_int 0)] 40))]
19181 [(set_attr "type" "mmx")])
19183 (define_expand "sfence"
19184 [(set (match_dup 0)
19185 (unspec:BLK [(match_dup 0)] 44))]
19189 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19190 MEM_VOLATILE_P (operands[0]) = 1;
19193 (define_insn "*sfence_insn"
19194 [(set (match_operand:BLK 0 "" "")
19195 (unspec:BLK [(match_dup 0)] 44))]
19198 [(set_attr "type" "sse")
19199 (set_attr "memory" "unknown")])
19201 (define_insn "prefetch"
19202 [(unspec [(match_operand:SI 0 "address_operand" "p")
19203 (match_operand:SI 1 "immediate_operand" "n")] 35)]
19207 switch (INTVAL (operands[1]))
19210 return \"prefetchnta\\t%a0\";
19212 return \"prefetcht0\\t%a0\";
19214 return \"prefetcht1\\t%a0\";
19216 return \"prefetcht2\\t%a0\";
19221 [(set_attr "type" "sse")])