1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 /* The purpose of this file is to define the characteristics of the i386,
24 independent of assembler syntax or operating system.
26 Three other files build on this one to describe a specific assembler syntax:
27 bsd386.h, att386.h, and sun386.h.
29 The actual tm.h file for a particular system should include
30 this file, and then the file for the appropriate assembler syntax.
32 Many macros that specify assembler syntax are omitted entirely from
33 this file because they really belong in the files for particular
34 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
35 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
36 that start with ASM_ or end in ASM_OP. */
38 /* Redefines for option macros. */
40 #define TARGET_64BIT OPTION_ISA_64BIT
41 #define TARGET_MMX OPTION_ISA_MMX
42 #define TARGET_3DNOW OPTION_ISA_3DNOW
43 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
44 #define TARGET_SSE OPTION_ISA_SSE
45 #define TARGET_SSE2 OPTION_ISA_SSE2
46 #define TARGET_SSE3 OPTION_ISA_SSE3
47 #define TARGET_SSSE3 OPTION_ISA_SSSE3
48 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
49 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
50 #define TARGET_SSE4A OPTION_ISA_SSE4A
52 #include "config/vxworks-dummy.h"
54 /* Algorithm to expand string function with. */
67 #define NAX_STRINGOP_ALGS 4
69 /* Specify what algorithm to use for stringops on known size.
70 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
71 known at compile time or estimated via feedback, the SIZE array
72 is walked in order until MAX is greater then the estimate (or -1
73 means infinity). Corresponding ALG is used then.
74 For example initializer:
75 {{256, loop}, {-1, rep_prefix_4_byte}}
76 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
80 const enum stringop_alg unknown_size;
81 const struct stringop_strategy {
83 const enum stringop_alg alg;
84 } size [NAX_STRINGOP_ALGS];
87 /* Define the specific costs for a given cpu */
89 struct processor_costs {
90 const int add; /* cost of an add instruction */
91 const int lea; /* cost of a lea instruction */
92 const int shift_var; /* variable shift costs */
93 const int shift_const; /* constant shift costs */
94 const int mult_init[5]; /* cost of starting a multiply
95 in QImode, HImode, SImode, DImode, TImode*/
96 const int mult_bit; /* cost of multiply per each bit set */
97 const int divide[5]; /* cost of a divide/mod
98 in QImode, HImode, SImode, DImode, TImode*/
99 int movsx; /* The cost of movsx operation. */
100 int movzx; /* The cost of movzx operation. */
101 const int large_insn; /* insns larger than this cost more */
102 const int move_ratio; /* The threshold of number of scalar
103 memory-to-memory move insns. */
104 const int movzbl_load; /* cost of loading using movzbl */
105 const int int_load[3]; /* cost of loading integer registers
106 in QImode, HImode and SImode relative
107 to reg-reg move (2). */
108 const int int_store[3]; /* cost of storing integer register
109 in QImode, HImode and SImode */
110 const int fp_move; /* cost of reg,reg fld/fst */
111 const int fp_load[3]; /* cost of loading FP register
112 in SFmode, DFmode and XFmode */
113 const int fp_store[3]; /* cost of storing FP register
114 in SFmode, DFmode and XFmode */
115 const int mmx_move; /* cost of moving MMX register. */
116 const int mmx_load[2]; /* cost of loading MMX register
117 in SImode and DImode */
118 const int mmx_store[2]; /* cost of storing MMX register
119 in SImode and DImode */
120 const int sse_move; /* cost of moving SSE register. */
121 const int sse_load[3]; /* cost of loading SSE register
122 in SImode, DImode and TImode*/
123 const int sse_store[3]; /* cost of storing SSE register
124 in SImode, DImode and TImode*/
125 const int mmxsse_to_integer; /* cost of moving mmxsse register to
126 integer and vice versa. */
127 const int prefetch_block; /* bytes moved to cache for prefetch. */
128 const int simultaneous_prefetches; /* number of parallel prefetch
130 const int branch_cost; /* Default value for BRANCH_COST. */
131 const int fadd; /* cost of FADD and FSUB instructions. */
132 const int fmul; /* cost of FMUL instruction. */
133 const int fdiv; /* cost of FDIV instruction. */
134 const int fabs; /* cost of FABS instruction. */
135 const int fchs; /* cost of FCHS instruction. */
136 const int fsqrt; /* cost of FSQRT instruction. */
137 /* Specify what algorithm
138 to use for stringops on unknown size. */
139 struct stringop_algs memcpy[2], memset[2];
142 extern const struct processor_costs *ix86_cost;
144 /* Macros used in the machine description to test the flags. */
146 /* configure can arrange to make this 2, to force a 486. */
148 #ifndef TARGET_CPU_DEFAULT
149 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
152 #ifndef TARGET_FPMATH_DEFAULT
153 #define TARGET_FPMATH_DEFAULT \
154 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
157 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
159 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
160 compile-time constant. */
164 #define TARGET_64BIT 1
166 #define TARGET_64BIT 0
169 #ifndef TARGET_BI_ARCH
171 #if TARGET_64BIT_DEFAULT
172 #define TARGET_64BIT 1
174 #define TARGET_64BIT 0
179 #define HAS_LONG_COND_BRANCH 1
180 #define HAS_LONG_UNCOND_BRANCH 1
182 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
183 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
184 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
185 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
186 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
187 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
188 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
189 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
190 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
191 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
192 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
193 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
194 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
195 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
196 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
197 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
199 /* Feature tests against the various tunings. */
200 enum ix86_tune_indices {
202 X86_TUNE_PUSH_MEMORY,
203 X86_TUNE_ZERO_EXTEND_WITH_AND,
204 X86_TUNE_USE_BIT_TEST,
205 X86_TUNE_UNROLL_STRLEN,
206 X86_TUNE_DEEP_BRANCH_PREDICTION,
207 X86_TUNE_BRANCH_PREDICTION_HINTS,
208 X86_TUNE_DOUBLE_WITH_ADD,
211 X86_TUNE_PARTIAL_REG_STALL,
212 X86_TUNE_PARTIAL_FLAG_REG_STALL,
213 X86_TUNE_USE_HIMODE_FIOP,
214 X86_TUNE_USE_SIMODE_FIOP,
218 X86_TUNE_SPLIT_LONG_MOVES,
219 X86_TUNE_READ_MODIFY_WRITE,
220 X86_TUNE_READ_MODIFY,
221 X86_TUNE_PROMOTE_QIMODE,
222 X86_TUNE_FAST_PREFIX,
223 X86_TUNE_SINGLE_STRINGOP,
224 X86_TUNE_QIMODE_MATH,
225 X86_TUNE_HIMODE_MATH,
226 X86_TUNE_PROMOTE_QI_REGS,
227 X86_TUNE_PROMOTE_HI_REGS,
232 X86_TUNE_INTEGER_DFMODE_MOVES,
233 X86_TUNE_PARTIAL_REG_DEPENDENCY,
234 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
235 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
236 X86_TUNE_SSE_SPLIT_REGS,
237 X86_TUNE_SSE_TYPELESS_STORES,
238 X86_TUNE_SSE_LOAD0_BY_PXOR,
239 X86_TUNE_MEMORY_MISMATCH_STALL,
240 X86_TUNE_PROLOGUE_USING_MOVE,
241 X86_TUNE_EPILOGUE_USING_MOVE,
244 X86_TUNE_INTER_UNIT_MOVES,
245 X86_TUNE_FOUR_JUMP_LIMIT,
249 X86_TUNE_PAD_RETURNS,
250 X86_TUNE_EXT_80387_CONSTANTS,
251 X86_TUNE_SHORTEN_X87_SSE,
252 X86_TUNE_AVOID_VECTOR_DECODE,
253 X86_TUNE_PROMOTE_HIMODE_IMUL,
254 X86_TUNE_SLOW_IMUL_IMM32_MEM,
255 X86_TUNE_SLOW_IMUL_IMM8,
256 X86_TUNE_MOVE_M1_VIA_OR,
257 X86_TUNE_NOT_UNPAIRABLE,
258 X86_TUNE_NOT_VECTORMODE,
263 extern unsigned int ix86_tune_features[X86_TUNE_LAST];
265 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
266 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
267 #define TARGET_ZERO_EXTEND_WITH_AND \
268 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
269 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
270 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
271 #define TARGET_DEEP_BRANCH_PREDICTION \
272 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
273 #define TARGET_BRANCH_PREDICTION_HINTS \
274 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
275 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
276 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
277 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
278 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
279 #define TARGET_PARTIAL_FLAG_REG_STALL \
280 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
281 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
282 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
283 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
284 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
285 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
286 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
287 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
288 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
289 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
290 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
291 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
292 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
293 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
294 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
295 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
296 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
297 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
298 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
299 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
300 #define TARGET_INTEGER_DFMODE_MOVES \
301 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
302 #define TARGET_PARTIAL_REG_DEPENDENCY \
303 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
304 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
305 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
306 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
307 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
308 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
309 #define TARGET_SSE_TYPELESS_STORES \
310 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
311 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
312 #define TARGET_MEMORY_MISMATCH_STALL \
313 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
314 #define TARGET_PROLOGUE_USING_MOVE \
315 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
316 #define TARGET_EPILOGUE_USING_MOVE \
317 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
318 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
319 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
320 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
321 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
322 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
323 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
324 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
325 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
326 #define TARGET_EXT_80387_CONSTANTS \
327 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
328 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
329 #define TARGET_AVOID_VECTOR_DECODE \
330 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
331 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
332 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
333 #define TARGET_SLOW_IMUL_IMM32_MEM \
334 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
335 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
336 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
337 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
338 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
340 /* Feature tests against the various architecture variations. */
341 enum ix86_arch_indices {
342 X86_ARCH_CMOVE, /* || TARGET_SSE */
351 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
353 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
354 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
355 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
356 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
357 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
359 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
361 extern int x86_prefetch_sse;
363 #define TARGET_ABM x86_abm
364 #define TARGET_CMPXCHG16B x86_cmpxchg16b
365 #define TARGET_POPCNT x86_popcnt
366 #define TARGET_PREFETCH_SSE x86_prefetch_sse
367 #define TARGET_SAHF x86_sahf
369 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
371 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
372 #define TARGET_MIX_SSE_I387 \
373 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
375 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
376 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
377 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
378 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
380 extern int ix86_isa_flags;
382 #ifndef TARGET_64BIT_DEFAULT
383 #define TARGET_64BIT_DEFAULT 0
385 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
386 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
389 /* Once GDB has been enhanced to deal with functions without frame
390 pointers, we can change this to allow for elimination of
391 the frame pointer in leaf functions. */
392 #define TARGET_DEFAULT 0
394 /* Extra bits to force. */
395 #define TARGET_SUBTARGET_DEFAULT 0
396 #define TARGET_SUBTARGET_ISA_DEFAULT 0
398 /* Extra bits to force on w/ 32-bit mode. */
399 #define TARGET_SUBTARGET32_DEFAULT 0
400 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
402 /* Extra bits to force on w/ 64-bit mode. */
403 #define TARGET_SUBTARGET64_DEFAULT 0
404 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
406 /* This is not really a target flag, but is done this way so that
407 it's analogous to similar code for Mach-O on PowerPC. darwin.h
408 redefines this to 1. */
409 #define TARGET_MACHO 0
411 /* Likewise, for the Windows 64-bit ABI. */
412 #define TARGET_64BIT_MS_ABI 0
414 /* Subtargets may reset this to 1 in order to enable 96-bit long double
415 with the rounding mode forced to 53 bits. */
416 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
418 /* Sometimes certain combinations of command options do not make
419 sense on a particular target machine. You can define a macro
420 `OVERRIDE_OPTIONS' to take account of this. This macro, if
421 defined, is executed once just after all the command options have
424 Don't use this macro to turn on various extra optimizations for
425 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
427 #define OVERRIDE_OPTIONS override_options ()
429 /* Define this to change the optimizations performed by default. */
430 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
431 optimization_options ((LEVEL), (SIZE))
433 /* -march=native handling only makes sense with compiler running on
434 an x86 or x86_64 chip. If changing this condition, also change
435 the condition in driver-i386.c. */
436 #if defined(__i386__) || defined(__x86_64__)
437 /* In driver-i386.c. */
438 extern const char *host_detect_local_cpu (int argc, const char **argv);
439 #define EXTRA_SPEC_FUNCTIONS \
440 { "local_cpu_detect", host_detect_local_cpu },
441 #define HAVE_LOCAL_CPU_DETECT
444 /* Support for configure-time defaults of some command line options.
445 The order here is important so that -march doesn't squash the
446 tune or cpu values. */
447 #define OPTION_DEFAULT_SPECS \
448 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
449 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
450 {"arch", "%{!march=*:-march=%(VALUE)}"}
452 /* Specs for the compiler proper */
455 #define CC1_CPU_SPEC_1 "\
457 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
459 %{mintel-syntax:-masm=intel \
460 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
461 %{mno-intel-syntax:-masm=att \
462 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
464 #ifndef HAVE_LOCAL_CPU_DETECT
465 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
467 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
468 "%{march=native:%<march=native %:local_cpu_detect(arch) \
469 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
470 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
474 /* Target CPU builtins. */
475 #define TARGET_CPU_CPP_BUILTINS() \
478 size_t arch_len = strlen (ix86_arch_string); \
479 size_t tune_len = strlen (ix86_tune_string); \
480 int last_arch_char = ix86_arch_string[arch_len - 1]; \
481 int last_tune_char = ix86_tune_string[tune_len - 1]; \
485 builtin_assert ("cpu=x86_64"); \
486 builtin_assert ("machine=x86_64"); \
487 builtin_define ("__amd64"); \
488 builtin_define ("__amd64__"); \
489 builtin_define ("__x86_64"); \
490 builtin_define ("__x86_64__"); \
494 builtin_assert ("cpu=i386"); \
495 builtin_assert ("machine=i386"); \
496 builtin_define_std ("i386"); \
499 /* Built-ins based on -mtune= (or -march= if no \
502 builtin_define ("__tune_i386__"); \
503 else if (TARGET_486) \
504 builtin_define ("__tune_i486__"); \
505 else if (TARGET_PENTIUM) \
507 builtin_define ("__tune_i586__"); \
508 builtin_define ("__tune_pentium__"); \
509 if (last_tune_char == 'x') \
510 builtin_define ("__tune_pentium_mmx__"); \
512 else if (TARGET_PENTIUMPRO) \
514 builtin_define ("__tune_i686__"); \
515 builtin_define ("__tune_pentiumpro__"); \
516 switch (last_tune_char) \
519 builtin_define ("__tune_pentium3__"); \
522 builtin_define ("__tune_pentium2__"); \
526 else if (TARGET_GEODE) \
528 builtin_define ("__tune_geode__"); \
530 else if (TARGET_K6) \
532 builtin_define ("__tune_k6__"); \
533 if (last_tune_char == '2') \
534 builtin_define ("__tune_k6_2__"); \
535 else if (last_tune_char == '3') \
536 builtin_define ("__tune_k6_3__"); \
538 else if (TARGET_ATHLON) \
540 builtin_define ("__tune_athlon__"); \
541 /* Only plain "athlon" lacks SSE. */ \
542 if (last_tune_char != 'n') \
543 builtin_define ("__tune_athlon_sse__"); \
545 else if (TARGET_K8) \
546 builtin_define ("__tune_k8__"); \
547 else if (TARGET_AMDFAM10) \
548 builtin_define ("__tune_amdfam10__"); \
549 else if (TARGET_PENTIUM4) \
550 builtin_define ("__tune_pentium4__"); \
551 else if (TARGET_NOCONA) \
552 builtin_define ("__tune_nocona__"); \
553 else if (TARGET_CORE2) \
554 builtin_define ("__tune_core2__"); \
557 builtin_define ("__MMX__"); \
559 builtin_define ("__3dNOW__"); \
560 if (TARGET_3DNOW_A) \
561 builtin_define ("__3dNOW_A__"); \
563 builtin_define ("__SSE__"); \
565 builtin_define ("__SSE2__"); \
567 builtin_define ("__SSE3__"); \
569 builtin_define ("__SSSE3__"); \
571 builtin_define ("__SSE4_1__"); \
573 builtin_define ("__SSE4_2__"); \
575 builtin_define ("__SSE4A__"); \
576 if (TARGET_SSE_MATH && TARGET_SSE) \
577 builtin_define ("__SSE_MATH__"); \
578 if (TARGET_SSE_MATH && TARGET_SSE2) \
579 builtin_define ("__SSE2_MATH__"); \
581 /* Built-ins based on -march=. */ \
582 if (ix86_arch == PROCESSOR_I486) \
584 builtin_define ("__i486"); \
585 builtin_define ("__i486__"); \
587 else if (ix86_arch == PROCESSOR_PENTIUM) \
589 builtin_define ("__i586"); \
590 builtin_define ("__i586__"); \
591 builtin_define ("__pentium"); \
592 builtin_define ("__pentium__"); \
593 if (last_arch_char == 'x') \
594 builtin_define ("__pentium_mmx__"); \
596 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
598 builtin_define ("__i686"); \
599 builtin_define ("__i686__"); \
600 builtin_define ("__pentiumpro"); \
601 builtin_define ("__pentiumpro__"); \
603 else if (ix86_arch == PROCESSOR_GEODE) \
605 builtin_define ("__geode"); \
606 builtin_define ("__geode__"); \
608 else if (ix86_arch == PROCESSOR_K6) \
611 builtin_define ("__k6"); \
612 builtin_define ("__k6__"); \
613 if (last_arch_char == '2') \
614 builtin_define ("__k6_2__"); \
615 else if (last_arch_char == '3') \
616 builtin_define ("__k6_3__"); \
618 else if (ix86_arch == PROCESSOR_ATHLON) \
620 builtin_define ("__athlon"); \
621 builtin_define ("__athlon__"); \
622 /* Only plain "athlon" lacks SSE. */ \
623 if (last_arch_char != 'n') \
624 builtin_define ("__athlon_sse__"); \
626 else if (ix86_arch == PROCESSOR_K8) \
628 builtin_define ("__k8"); \
629 builtin_define ("__k8__"); \
631 else if (ix86_arch == PROCESSOR_AMDFAM10) \
633 builtin_define ("__amdfam10"); \
634 builtin_define ("__amdfam10__"); \
636 else if (ix86_arch == PROCESSOR_PENTIUM4) \
638 builtin_define ("__pentium4"); \
639 builtin_define ("__pentium4__"); \
641 else if (ix86_arch == PROCESSOR_NOCONA) \
643 builtin_define ("__nocona"); \
644 builtin_define ("__nocona__"); \
646 else if (ix86_arch == PROCESSOR_CORE2) \
648 builtin_define ("__core2"); \
649 builtin_define ("__core2__"); \
654 #define TARGET_CPU_DEFAULT_i386 0
655 #define TARGET_CPU_DEFAULT_i486 1
656 #define TARGET_CPU_DEFAULT_pentium 2
657 #define TARGET_CPU_DEFAULT_pentium_mmx 3
658 #define TARGET_CPU_DEFAULT_pentiumpro 4
659 #define TARGET_CPU_DEFAULT_pentium2 5
660 #define TARGET_CPU_DEFAULT_pentium3 6
661 #define TARGET_CPU_DEFAULT_pentium4 7
662 #define TARGET_CPU_DEFAULT_geode 8
663 #define TARGET_CPU_DEFAULT_k6 9
664 #define TARGET_CPU_DEFAULT_k6_2 10
665 #define TARGET_CPU_DEFAULT_k6_3 11
666 #define TARGET_CPU_DEFAULT_athlon 12
667 #define TARGET_CPU_DEFAULT_athlon_sse 13
668 #define TARGET_CPU_DEFAULT_k8 14
669 #define TARGET_CPU_DEFAULT_pentium_m 15
670 #define TARGET_CPU_DEFAULT_prescott 16
671 #define TARGET_CPU_DEFAULT_nocona 17
672 #define TARGET_CPU_DEFAULT_core2 18
673 #define TARGET_CPU_DEFAULT_generic 19
674 #define TARGET_CPU_DEFAULT_amdfam10 20
676 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
677 "pentiumpro", "pentium2", "pentium3", \
678 "pentium4", "geode", "k6", "k6-2", "k6-3", \
679 "athlon", "athlon-4", "k8", \
680 "pentium-m", "prescott", "nocona", \
681 "core2", "generic", "amdfam10"}
684 #define CC1_SPEC "%(cc1_cpu) "
687 /* This macro defines names of additional specifications to put in the
688 specs that can be used in various specifications like CC1_SPEC. Its
689 definition is an initializer with a subgrouping for each command option.
691 Each subgrouping contains a string constant, that defines the
692 specification name, and a string constant that used by the GCC driver
695 Do not define this macro if it does not need to do anything. */
697 #ifndef SUBTARGET_EXTRA_SPECS
698 #define SUBTARGET_EXTRA_SPECS
701 #define EXTRA_SPECS \
702 { "cc1_cpu", CC1_CPU_SPEC }, \
703 SUBTARGET_EXTRA_SPECS
705 /* target machine storage layout */
707 #define LONG_DOUBLE_TYPE_SIZE 80
709 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
710 FPU, assume that the fpcw is set to extended precision; when using
711 only SSE, rounding is correct; when using both SSE and the FPU,
712 the rounding precision is indeterminate, since either may be chosen
713 apparently at random. */
714 #define TARGET_FLT_EVAL_METHOD \
715 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
717 #define SHORT_TYPE_SIZE 16
718 #define INT_TYPE_SIZE 32
719 #define FLOAT_TYPE_SIZE 32
720 #define LONG_TYPE_SIZE BITS_PER_WORD
721 #define DOUBLE_TYPE_SIZE 64
722 #define LONG_LONG_TYPE_SIZE 64
724 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
725 #define MAX_BITS_PER_WORD 64
727 #define MAX_BITS_PER_WORD 32
730 /* Define this if most significant byte of a word is the lowest numbered. */
731 /* That is true on the 80386. */
733 #define BITS_BIG_ENDIAN 0
735 /* Define this if most significant byte of a word is the lowest numbered. */
736 /* That is not true on the 80386. */
737 #define BYTES_BIG_ENDIAN 0
739 /* Define this if most significant word of a multiword number is the lowest
741 /* Not true for 80386 */
742 #define WORDS_BIG_ENDIAN 0
744 /* Width of a word, in units (bytes). */
745 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
747 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
749 #define MIN_UNITS_PER_WORD 4
752 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
753 #define PARM_BOUNDARY BITS_PER_WORD
755 /* Boundary (in *bits*) on which stack pointer should be aligned. */
756 #define STACK_BOUNDARY BITS_PER_WORD
758 /* Boundary (in *bits*) on which the stack pointer prefers to be
759 aligned; the compiler cannot rely on having this alignment. */
760 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
762 /* As of July 2001, many runtimes do not align the stack properly when
763 entering main. This causes expand_main_function to forcibly align
764 the stack, which results in aligned frames for functions called from
765 main, though it does nothing for the alignment of main itself. */
766 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
767 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
769 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
770 mandatory for the 64-bit ABI, and may or may not be true for other
771 operating systems. */
772 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
774 /* Minimum allocation boundary for the code of a function. */
775 #define FUNCTION_BOUNDARY 8
777 /* C++ stores the virtual bit in the lowest bit of function pointers. */
778 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
780 /* Alignment of field after `int : 0' in a structure. */
782 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
784 /* Minimum size in bits of the largest boundary to which any
785 and all fundamental data types supported by the hardware
786 might need to be aligned. No data type wants to be aligned
789 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
790 and Pentium Pro XFmode values at 128 bit boundaries. */
792 #define BIGGEST_ALIGNMENT 128
794 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
795 #define ALIGN_MODE_128(MODE) \
796 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
798 /* The published ABIs say that doubles should be aligned on word
799 boundaries, so lower the alignment for structure fields unless
800 -malign-double is set. */
802 /* ??? Blah -- this macro is used directly by libobjc. Since it
803 supports no vector modes, cut out the complexity and fall back
804 on BIGGEST_FIELD_ALIGNMENT. */
805 #ifdef IN_TARGET_LIBS
807 #define BIGGEST_FIELD_ALIGNMENT 128
809 #define BIGGEST_FIELD_ALIGNMENT 32
812 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
813 x86_field_alignment (FIELD, COMPUTED)
816 /* If defined, a C expression to compute the alignment given to a
817 constant that is being placed in memory. EXP is the constant
818 and ALIGN is the alignment that the object would ordinarily have.
819 The value of this macro is used instead of that alignment to align
822 If this macro is not defined, then ALIGN is used.
824 The typical use of this macro is to increase alignment for string
825 constants to be word aligned so that `strcpy' calls that copy
826 constants can be done inline. */
828 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
830 /* If defined, a C expression to compute the alignment for a static
831 variable. TYPE is the data type, and ALIGN is the alignment that
832 the object would ordinarily have. The value of this macro is used
833 instead of that alignment to align the object.
835 If this macro is not defined, then ALIGN is used.
837 One use of this macro is to increase alignment of medium-size
838 data to make it all fit in fewer cache lines. Another is to
839 cause character arrays to be word-aligned so that `strcpy' calls
840 that copy constants to character arrays can be done inline. */
842 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
844 /* If defined, a C expression to compute the alignment for a local
845 variable. TYPE is the data type, and ALIGN is the alignment that
846 the object would ordinarily have. The value of this macro is used
847 instead of that alignment to align the object.
849 If this macro is not defined, then ALIGN is used.
851 One use of this macro is to increase alignment of medium-size
852 data to make it all fit in fewer cache lines. */
854 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
856 /* If defined, a C expression that gives the alignment boundary, in
857 bits, of an argument with the specified mode and type. If it is
858 not defined, `PARM_BOUNDARY' is used for all arguments. */
860 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
861 ix86_function_arg_boundary ((MODE), (TYPE))
863 /* Set this nonzero if move instructions will actually fail to work
864 when given unaligned data. */
865 #define STRICT_ALIGNMENT 0
867 /* If bit field type is int, don't let it cross an int,
868 and give entire struct the alignment of an int. */
869 /* Required on the 386 since it doesn't have bit-field insns. */
870 #define PCC_BITFIELD_TYPE_MATTERS 1
872 /* Standard register usage. */
874 /* This processor has special stack-like registers. See reg-stack.c
878 #define IS_STACK_MODE(MODE) \
879 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
880 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
883 /* Number of actual hardware registers.
884 The hardware registers are assigned numbers for the compiler
885 from 0 to just below FIRST_PSEUDO_REGISTER.
886 All registers that the compiler knows about must be given numbers,
887 even those that are not normally considered general registers.
889 In the 80386 we give the 8 general purpose registers the numbers 0-7.
890 We number the floating point registers 8-15.
891 Note that registers 0-7 can be accessed as a short or int,
892 while only 0-3 may be used with byte `mov' instructions.
894 Reg 16 does not correspond to any hardware register, but instead
895 appears in the RTL as an argument pointer prior to reload, and is
896 eliminated during reloading in favor of either the stack or frame
899 #define FIRST_PSEUDO_REGISTER 53
901 /* Number of hardware registers that go into the DWARF-2 unwind info.
902 If not defined, equals FIRST_PSEUDO_REGISTER. */
904 #define DWARF_FRAME_REGISTERS 17
906 /* 1 for registers that have pervasive standard uses
907 and are not available for the register allocator.
908 On the 80386, the stack pointer is such, as is the arg pointer.
910 The value is zero if the register is not fixed on either 32 or
911 64 bit targets, one if the register if fixed on both 32 and 64
912 bit targets, two if it is only fixed on 32bit targets and three
913 if its only fixed on 64bit targets.
914 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
916 #define FIXED_REGISTERS \
917 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
918 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
919 /*arg,flags,fpsr,fpcr,frame*/ \
921 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
922 0, 0, 0, 0, 0, 0, 0, 0, \
923 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
924 0, 0, 0, 0, 0, 0, 0, 0, \
925 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
926 2, 2, 2, 2, 2, 2, 2, 2, \
927 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
928 2, 2, 2, 2, 2, 2, 2, 2}
931 /* 1 for registers not available across function calls.
932 These must include the FIXED_REGISTERS and also any
933 registers that can be used without being saved.
934 The latter must include the registers where values are returned
935 and the register where structure-value addresses are passed.
936 Aside from that, you can include as many other registers as you like.
938 The value is zero if the register is not call used on either 32 or
939 64 bit targets, one if the register if call used on both 32 and 64
940 bit targets, two if it is only call used on 32bit targets and three
941 if its only call used on 64bit targets.
942 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
944 #define CALL_USED_REGISTERS \
945 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
946 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
947 /*arg,flags,fpsr,fpcr,frame*/ \
949 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
950 1, 1, 1, 1, 1, 1, 1, 1, \
951 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
952 1, 1, 1, 1, 1, 1, 1, 1, \
953 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
954 1, 1, 1, 1, 2, 2, 2, 2, \
955 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
956 1, 1, 1, 1, 1, 1, 1, 1} \
958 /* Order in which to allocate registers. Each register must be
959 listed once, even those in FIXED_REGISTERS. List frame pointer
960 late and fixed registers last. Note that, in general, we prefer
961 registers listed in CALL_USED_REGISTERS, keeping the others
962 available for storage of persistent values.
964 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
965 so this is just empty initializer for array. */
967 #define REG_ALLOC_ORDER \
968 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
969 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
970 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
973 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
974 to be rearranged based on a particular function. When using sse math,
975 we want to allocate SSE before x87 registers and vice versa. */
977 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
980 /* Macro to conditionally modify fixed_regs/call_used_regs. */
981 #define CONDITIONAL_REGISTER_USAGE \
985 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
987 if (fixed_regs[i] > 1) \
988 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
989 if (call_used_regs[i] > 1) \
990 call_used_regs[i] = (call_used_regs[i] \
991 == (TARGET_64BIT ? 3 : 2)); \
993 j = PIC_OFFSET_TABLE_REGNUM; \
994 if (j != INVALID_REGNUM) \
997 call_used_regs[j] = 1; \
1002 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1003 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1004 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1009 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1010 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1011 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1013 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1017 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1018 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1019 if (TEST_HARD_REG_BIT (x, i)) \
1020 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1022 if (! TARGET_64BIT) \
1025 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
1026 reg_names[i] = ""; \
1027 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
1028 reg_names[i] = ""; \
1030 if (TARGET_64BIT_MS_ABI) \
1032 call_used_regs[4 /*RSI*/] = 0; \
1033 call_used_regs[5 /*RDI*/] = 0; \
1037 /* Return number of consecutive hard regs needed starting at reg REGNO
1038 to hold something of mode MODE.
1039 This is ordinarily the length in words of a value of mode MODE
1040 but can be less for certain modes in special long registers.
1042 Actually there are no two word move instructions for consecutive
1043 registers. And only registers 0-3 may have mov byte instructions
1047 #define HARD_REGNO_NREGS(REGNO, MODE) \
1048 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1049 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1050 : ((MODE) == XFmode \
1051 ? (TARGET_64BIT ? 2 : 3) \
1052 : (MODE) == XCmode \
1053 ? (TARGET_64BIT ? 4 : 6) \
1054 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1056 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1057 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1058 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1060 : ((MODE) == XFmode || (MODE) == XCmode)) \
1063 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1065 #define VALID_SSE2_REG_MODE(MODE) \
1066 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1067 || (MODE) == V2DImode || (MODE) == DFmode)
1069 #define VALID_SSE_REG_MODE(MODE) \
1070 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1071 || (MODE) == SFmode || (MODE) == TFmode)
1073 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1074 ((MODE) == V2SFmode || (MODE) == SFmode)
1076 #define VALID_MMX_REG_MODE(MODE) \
1077 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1078 || (MODE) == V2SImode || (MODE) == SImode)
1080 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1081 place emms and femms instructions. */
1082 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
1084 #define VALID_FP_MODE_P(MODE) \
1085 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1086 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1088 #define VALID_INT_MODE_P(MODE) \
1089 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1090 || (MODE) == DImode \
1091 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1092 || (MODE) == CDImode \
1093 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1094 || (MODE) == TFmode || (MODE) == TCmode)))
1096 /* Return true for modes passed in SSE registers. */
1097 #define SSE_REG_MODE_P(MODE) \
1098 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1099 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1100 || (MODE) == V4SFmode || (MODE) == V4SImode)
1102 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1104 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1105 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1107 /* Value is 1 if it is a good idea to tie two pseudo registers
1108 when one has mode MODE1 and one has mode MODE2.
1109 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1110 for any hard reg, then this must be 0 for correct output. */
1112 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1114 /* It is possible to write patterns to move flags; but until someone
1116 #define AVOID_CCMODE_COPIES
1118 /* Specify the modes required to caller save a given hard regno.
1119 We do this on i386 to prevent flags from being saved at all.
1121 Kill any attempts to combine saving of modes. */
1123 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1124 (CC_REGNO_P (REGNO) ? VOIDmode \
1125 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1126 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1127 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1128 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1130 /* Specify the registers used for certain standard purposes.
1131 The values of these macros are register numbers. */
1133 /* on the 386 the pc register is %eip, and is not usable as a general
1134 register. The ordinary mov instructions won't work */
1135 /* #define PC_REGNUM */
1137 /* Register to use for pushing function arguments. */
1138 #define STACK_POINTER_REGNUM 7
1140 /* Base register for access to local variables of the function. */
1141 #define HARD_FRAME_POINTER_REGNUM 6
1143 /* Base register for access to local variables of the function. */
1144 #define FRAME_POINTER_REGNUM 20
1146 /* First floating point reg */
1147 #define FIRST_FLOAT_REG 8
1149 /* First & last stack-like regs */
1150 #define FIRST_STACK_REG FIRST_FLOAT_REG
1151 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1153 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1154 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1156 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1157 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1159 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1160 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1162 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1163 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1165 /* Value should be nonzero if functions must have frame pointers.
1166 Zero means the frame pointer need not be set up (and parms
1167 may be accessed via the stack pointer) in functions that seem suitable.
1168 This is computed in `reload', in reload1.c. */
1169 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1171 /* Override this in other tm.h files to cope with various OS lossage
1172 requiring a frame pointer. */
1173 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1174 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1177 /* Make sure we can access arbitrary call frames. */
1178 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1180 /* Base register for access to arguments of the function. */
1181 #define ARG_POINTER_REGNUM 16
1183 /* Register in which static-chain is passed to a function.
1184 We do use ECX as static chain register for 32 bit ABI. On the
1185 64bit ABI, ECX is an argument register, so we use R10 instead. */
1186 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1188 /* Register to hold the addressing base for position independent
1189 code access to data items. We don't use PIC pointer for 64bit
1190 mode. Define the regnum to dummy value to prevent gcc from
1191 pessimizing code dealing with EBX.
1193 To avoid clobbering a call-saved register unnecessarily, we renumber
1194 the pic register when possible. The change is visible after the
1195 prologue has been emitted. */
1197 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1199 #define PIC_OFFSET_TABLE_REGNUM \
1200 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1201 || !flag_pic ? INVALID_REGNUM \
1202 : reload_completed ? REGNO (pic_offset_table_rtx) \
1203 : REAL_PIC_OFFSET_TABLE_REGNUM)
1205 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1207 /* A C expression which can inhibit the returning of certain function
1208 values in registers, based on the type of value. A nonzero value
1209 says to return the function value in memory, just as large
1210 structures are always returned. Here TYPE will be a C expression
1211 of type `tree', representing the data type of the value.
1213 Note that values of mode `BLKmode' must be explicitly handled by
1214 this macro. Also, the option `-fpcc-struct-return' takes effect
1215 regardless of this macro. On most systems, it is possible to
1216 leave the macro undefined; this causes a default definition to be
1217 used, whose value is the constant 1 for `BLKmode' values, and 0
1220 Do not use this macro to indicate that structures and unions
1221 should always be returned in memory. You should instead use
1222 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1224 #define RETURN_IN_MEMORY(TYPE) \
1225 ix86_return_in_memory (TYPE)
1227 /* This is overridden by <cygwin.h>. */
1228 #define MS_AGGREGATE_RETURN 0
1230 /* This is overridden by <netware.h>. */
1231 #define KEEP_AGGREGATE_RETURN_POINTER 0
1233 /* Define the classes of registers for register constraints in the
1234 machine description. Also define ranges of constants.
1236 One of the classes must always be named ALL_REGS and include all hard regs.
1237 If there is more than one class, another class must be named NO_REGS
1238 and contain no registers.
1240 The name GENERAL_REGS must be the name of a class (or an alias for
1241 another name such as ALL_REGS). This is the class of registers
1242 that is allowed by "g" or "r" in a register constraint.
1243 Also, registers outside this class are allocated only when
1244 instructions express preferences for them.
1246 The classes must be numbered in nondecreasing order; that is,
1247 a larger-numbered class must never be contained completely
1248 in a smaller-numbered class.
1250 For any two classes, it is very desirable that there be another
1251 class that represents their union.
1253 It might seem that class BREG is unnecessary, since no useful 386
1254 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1255 and the "b" register constraint is useful in asms for syscalls.
1257 The flags, fpsr and fpcr registers are in no class. */
1262 AREG, DREG, CREG, BREG, SIREG, DIREG,
1263 AD_REGS, /* %eax/%edx for DImode */
1264 Q_REGS, /* %eax %ebx %ecx %edx */
1265 NON_Q_REGS, /* %esi %edi %ebp %esp */
1266 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1267 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1268 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1269 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1280 ALL_REGS, LIM_REG_CLASSES
1283 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1285 #define INTEGER_CLASS_P(CLASS) \
1286 reg_class_subset_p ((CLASS), GENERAL_REGS)
1287 #define FLOAT_CLASS_P(CLASS) \
1288 reg_class_subset_p ((CLASS), FLOAT_REGS)
1289 #define SSE_CLASS_P(CLASS) \
1290 reg_class_subset_p ((CLASS), SSE_REGS)
1291 #define MMX_CLASS_P(CLASS) \
1292 ((CLASS) == MMX_REGS)
1293 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1294 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1295 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1296 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1297 #define MAYBE_SSE_CLASS_P(CLASS) \
1298 reg_classes_intersect_p (SSE_REGS, (CLASS))
1299 #define MAYBE_MMX_CLASS_P(CLASS) \
1300 reg_classes_intersect_p (MMX_REGS, (CLASS))
1302 #define Q_CLASS_P(CLASS) \
1303 reg_class_subset_p ((CLASS), Q_REGS)
1305 /* Give names of register classes as strings for dump file. */
1307 #define REG_CLASS_NAMES \
1309 "AREG", "DREG", "CREG", "BREG", \
1312 "Q_REGS", "NON_Q_REGS", \
1316 "FP_TOP_REG", "FP_SECOND_REG", \
1321 "FP_TOP_SSE_REGS", \
1322 "FP_SECOND_SSE_REGS", \
1326 "FLOAT_INT_SSE_REGS", \
1329 /* Define which registers fit in which classes.
1330 This is an initializer for a vector of HARD_REG_SET
1331 of length N_REG_CLASSES. */
1333 #define REG_CLASS_CONTENTS \
1335 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1336 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1337 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1338 { 0x03, 0x0 }, /* AD_REGS */ \
1339 { 0x0f, 0x0 }, /* Q_REGS */ \
1340 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1341 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1342 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1343 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1344 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1345 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1346 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1347 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1348 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1349 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1350 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1351 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1352 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1353 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1354 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1355 { 0xffffffff,0x1fffff } \
1358 /* The same information, inverted:
1359 Return the class number of the smallest class containing
1360 reg number REGNO. This could be a conditional expression
1361 or could index an array. */
1363 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1365 /* When defined, the compiler allows registers explicitly used in the
1366 rtl to be used as spill registers but prevents the compiler from
1367 extending the lifetime of these registers. */
1369 #define SMALL_REGISTER_CLASSES 1
1371 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1373 #define GENERAL_REGNO_P(N) \
1374 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1376 #define GENERAL_REG_P(X) \
1377 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1379 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1381 #define REX_INT_REGNO_P(N) \
1382 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1383 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1385 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1386 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1387 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1388 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1390 #define X87_FLOAT_MODE_P(MODE) \
1391 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1393 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1394 #define SSE_REGNO_P(N) \
1395 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1396 || REX_SSE_REGNO_P (N))
1398 #define REX_SSE_REGNO_P(N) \
1399 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1401 #define SSE_REGNO(N) \
1402 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1404 #define SSE_FLOAT_MODE_P(MODE) \
1405 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1407 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1408 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1410 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1411 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1413 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1415 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1416 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1418 /* The class value for index registers, and the one for base regs. */
1420 #define INDEX_REG_CLASS INDEX_REGS
1421 #define BASE_REG_CLASS GENERAL_REGS
1423 /* Place additional restrictions on the register class to use when it
1424 is necessary to be able to hold a value of mode MODE in a reload
1425 register for which class CLASS would ordinarily be used. */
1427 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1428 ((MODE) == QImode && !TARGET_64BIT \
1429 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1430 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1433 /* Given an rtx X being reloaded into a reg required to be
1434 in class CLASS, return the class of reg to actually use.
1435 In general this is just CLASS; but on some machines
1436 in some cases it is preferable to use a more restrictive class.
1437 On the 80386 series, we prevent floating constants from being
1438 reloaded into floating registers (since no move-insn can do that)
1439 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1441 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1442 QImode must go into class Q_REGS.
1443 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1444 movdf to do mem-to-mem moves through integer regs. */
1446 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1447 ix86_preferred_reload_class ((X), (CLASS))
1449 /* Discourage putting floating-point values in SSE registers unless
1450 SSE math is being used, and likewise for the 387 registers. */
1452 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1453 ix86_preferred_output_reload_class ((X), (CLASS))
1455 /* If we are copying between general and FP registers, we need a memory
1456 location. The same is true for SSE and MMX registers. */
1457 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1458 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1460 /* QImode spills from non-QI registers need a scratch. This does not
1461 happen often -- the only example so far requires an uninitialized
1464 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1465 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1466 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1469 /* Return the maximum number of consecutive registers
1470 needed to represent mode MODE in a register of class CLASS. */
1471 /* On the 80386, this is the size of MODE in words,
1472 except in the FP regs, where a single reg is always enough. */
1473 #define CLASS_MAX_NREGS(CLASS, MODE) \
1474 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1475 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1476 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1477 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1479 /* A C expression whose value is nonzero if pseudos that have been
1480 assigned to registers of class CLASS would likely be spilled
1481 because registers of CLASS are needed for spill registers.
1483 The default value of this macro returns 1 if CLASS has exactly one
1484 register and zero otherwise. On most machines, this default
1485 should be used. Only define this macro to some other expression
1486 if pseudo allocated by `local-alloc.c' end up in memory because
1487 their hard registers were needed for spill registers. If this
1488 macro returns nonzero for those classes, those pseudos will only
1489 be allocated by `global.c', which knows how to reallocate the
1490 pseudo to another register. If there would not be another
1491 register available for reallocation, you should not change the
1492 definition of this macro since the only effect of such a
1493 definition would be to slow down register allocation. */
1495 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1496 (((CLASS) == AREG) \
1497 || ((CLASS) == DREG) \
1498 || ((CLASS) == CREG) \
1499 || ((CLASS) == BREG) \
1500 || ((CLASS) == AD_REGS) \
1501 || ((CLASS) == SIREG) \
1502 || ((CLASS) == DIREG) \
1503 || ((CLASS) == FP_TOP_REG) \
1504 || ((CLASS) == FP_SECOND_REG))
1506 /* Return a class of registers that cannot change FROM mode to TO mode. */
1508 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1509 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1511 /* Stack layout; function entry, exit and calling. */
1513 /* Define this if pushing a word on the stack
1514 makes the stack pointer a smaller address. */
1515 #define STACK_GROWS_DOWNWARD
1517 /* Define this to nonzero if the nominal address of the stack frame
1518 is at the high-address end of the local variables;
1519 that is, each additional local variable allocated
1520 goes at a more negative offset in the frame. */
1521 #define FRAME_GROWS_DOWNWARD 1
1523 /* Offset within stack frame to start allocating local variables at.
1524 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1525 first local allocated. Otherwise, it is the offset to the BEGINNING
1526 of the first local allocated. */
1527 #define STARTING_FRAME_OFFSET 0
1529 /* If we generate an insn to push BYTES bytes,
1530 this says how many the stack pointer really advances by.
1531 On 386, we have pushw instruction that decrements by exactly 2 no
1532 matter what the position was, there is no pushb.
1533 But as CIE data alignment factor on this arch is -4, we need to make
1534 sure all stack pointer adjustments are in multiple of 4.
1536 For 64bit ABI we round up to 8 bytes.
1539 #define PUSH_ROUNDING(BYTES) \
1541 ? (((BYTES) + 7) & (-8)) \
1542 : (((BYTES) + 3) & (-4)))
1544 /* If defined, the maximum amount of space required for outgoing arguments will
1545 be computed and placed into the variable
1546 `current_function_outgoing_args_size'. No space will be pushed onto the
1547 stack for each call; instead, the function prologue should increase the stack
1548 frame size by this amount. */
1550 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1552 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1553 instructions to pass outgoing arguments. */
1555 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1557 /* We want the stack and args grow in opposite directions, even if
1559 #define PUSH_ARGS_REVERSED 1
1561 /* Offset of first parameter from the argument pointer register value. */
1562 #define FIRST_PARM_OFFSET(FNDECL) 0
1564 /* Define this macro if functions should assume that stack space has been
1565 allocated for arguments even when their values are passed in registers.
1567 The value of this macro is the size, in bytes, of the area reserved for
1568 arguments passed in registers for the function represented by FNDECL.
1570 This space can be allocated by the caller, or be a part of the
1571 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1573 #define REG_PARM_STACK_SPACE(FNDECL) 0
1575 /* Value is the number of bytes of arguments automatically
1576 popped when returning from a subroutine call.
1577 FUNDECL is the declaration node of the function (as a tree),
1578 FUNTYPE is the data type of the function (as a tree),
1579 or for a library call it is an identifier node for the subroutine name.
1580 SIZE is the number of bytes of arguments passed on the stack.
1582 On the 80386, the RTD insn may be used to pop them if the number
1583 of args is fixed, but if the number is variable then the caller
1584 must pop them all. RTD can't be used for library calls now
1585 because the library is compiled with the Unix compiler.
1586 Use of RTD is a selectable option, since it is incompatible with
1587 standard Unix calling sequences. If the option is not selected,
1588 the caller must always pop the args.
1590 The attribute stdcall is equivalent to RTD on a per module basis. */
1592 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1593 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1595 #define FUNCTION_VALUE_REGNO_P(N) \
1596 ix86_function_value_regno_p (N)
1598 /* Define how to find the value returned by a library function
1599 assuming the value has mode MODE. */
1601 #define LIBCALL_VALUE(MODE) \
1602 ix86_libcall_value (MODE)
1604 /* Define the size of the result block used for communication between
1605 untyped_call and untyped_return. The block contains a DImode value
1606 followed by the block used by fnsave and frstor. */
1608 #define APPLY_RESULT_SIZE (8+108)
1610 /* 1 if N is a possible register number for function argument passing. */
1611 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1613 /* Define a data type for recording info about an argument list
1614 during the scan of that argument list. This data type should
1615 hold all necessary information about the function itself
1616 and about the args processed so far, enough to enable macros
1617 such as FUNCTION_ARG to determine where the next arg should go. */
1619 typedef struct ix86_args {
1620 int words; /* # words passed so far */
1621 int nregs; /* # registers available for passing */
1622 int regno; /* next available register number */
1623 int fastcall; /* fastcall calling convention is used */
1624 int sse_words; /* # sse words passed so far */
1625 int sse_nregs; /* # sse registers available for passing */
1626 int warn_sse; /* True when we want to warn about SSE ABI. */
1627 int warn_mmx; /* True when we want to warn about MMX ABI. */
1628 int sse_regno; /* next available sse register number */
1629 int mmx_words; /* # mmx words passed so far */
1630 int mmx_nregs; /* # mmx registers available for passing */
1631 int mmx_regno; /* next available mmx register number */
1632 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1633 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1634 be passed in SSE registers. Otherwise 0. */
1637 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1638 for a call to a function whose data type is FNTYPE.
1639 For a library call, FNTYPE is 0. */
1641 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1642 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1644 /* Update the data in CUM to advance over an argument
1645 of mode MODE and data type TYPE.
1646 (TYPE is null for libcalls where that information may not be available.) */
1648 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1649 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1651 /* Define where to put the arguments to a function.
1652 Value is zero to push the argument on the stack,
1653 or a hard register in which to store the argument.
1655 MODE is the argument's machine mode.
1656 TYPE is the data type of the argument (as a tree).
1657 This is null for libcalls where that information may
1659 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1660 the preceding args and about the function being called.
1661 NAMED is nonzero if this argument is a named parameter
1662 (otherwise it is an extra parameter matching an ellipsis). */
1664 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1665 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1667 /* Implement `va_start' for varargs and stdarg. */
1668 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1669 ix86_va_start (VALIST, NEXTARG)
1671 #define TARGET_ASM_FILE_END ix86_file_end
1672 #define NEED_INDICATE_EXEC_STACK 0
1674 /* Output assembler code to FILE to increment profiler label # LABELNO
1675 for profiling a function entry. */
1677 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1679 #define MCOUNT_NAME "_mcount"
1681 #define PROFILE_COUNT_REGISTER "edx"
1683 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1684 the stack pointer does not matter. The value is tested only in
1685 functions that have frame pointers.
1686 No definition is equivalent to always zero. */
1687 /* Note on the 386 it might be more efficient not to define this since
1688 we have to restore it ourselves from the frame pointer, in order to
1691 #define EXIT_IGNORE_STACK 1
1693 /* Output assembler code for a block containing the constant parts
1694 of a trampoline, leaving space for the variable parts. */
1696 /* On the 386, the trampoline contains two instructions:
1699 The trampoline is generated entirely at runtime. The operand of JMP
1700 is the address of FUNCTION relative to the instruction following the
1701 JMP (which is 5 bytes long). */
1703 /* Length in units of the trampoline for entering a nested function. */
1705 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1707 /* Emit RTL insns to initialize the variable parts of a trampoline.
1708 FNADDR is an RTX for the address of the function's pure code.
1709 CXT is an RTX for the static chain value for the function. */
1711 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1712 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1714 /* Definitions for register eliminations.
1716 This is an array of structures. Each structure initializes one pair
1717 of eliminable registers. The "from" register number is given first,
1718 followed by "to". Eliminations of the same "from" register are listed
1719 in order of preference.
1721 There are two registers that can always be eliminated on the i386.
1722 The frame pointer and the arg pointer can be replaced by either the
1723 hard frame pointer or to the stack pointer, depending upon the
1724 circumstances. The hard frame pointer is not used before reload and
1725 so it is not eligible for elimination. */
1727 #define ELIMINABLE_REGS \
1728 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1729 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1730 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1731 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1733 /* Given FROM and TO register numbers, say whether this elimination is
1734 allowed. Frame pointer elimination is automatically handled.
1736 All other eliminations are valid. */
1738 #define CAN_ELIMINATE(FROM, TO) \
1739 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1741 /* Define the offset between two registers, one to be eliminated, and the other
1742 its replacement, at the start of a routine. */
1744 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1745 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1747 /* Addressing modes, and classification of registers for them. */
1749 /* Macros to check register numbers against specific register classes. */
1751 /* These assume that REGNO is a hard or pseudo reg number.
1752 They give nonzero only if REGNO is a hard reg of the suitable class
1753 or a pseudo reg currently allocated to a suitable hard reg.
1754 Since they use reg_renumber, they are safe only once reg_renumber
1755 has been allocated, which happens in local-alloc.c. */
1757 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1758 ((REGNO) < STACK_POINTER_REGNUM \
1759 || REX_INT_REGNO_P (REGNO) \
1760 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1761 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1763 #define REGNO_OK_FOR_BASE_P(REGNO) \
1764 (GENERAL_REGNO_P (REGNO) \
1765 || (REGNO) == ARG_POINTER_REGNUM \
1766 || (REGNO) == FRAME_POINTER_REGNUM \
1767 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1769 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1770 and check its validity for a certain class.
1771 We have two alternate definitions for each of them.
1772 The usual definition accepts all pseudo regs; the other rejects
1773 them unless they have been allocated suitable hard regs.
1774 The symbol REG_OK_STRICT causes the latter definition to be used.
1776 Most source files want to accept pseudo regs in the hope that
1777 they will get allocated to the class that the insn wants them to be in.
1778 Source files for reload pass need to be strict.
1779 After reload, it makes no difference, since pseudo regs have
1780 been eliminated by then. */
1783 /* Non strict versions, pseudos are ok. */
1784 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1785 (REGNO (X) < STACK_POINTER_REGNUM \
1786 || REX_INT_REGNO_P (REGNO (X)) \
1787 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1789 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1790 (GENERAL_REGNO_P (REGNO (X)) \
1791 || REGNO (X) == ARG_POINTER_REGNUM \
1792 || REGNO (X) == FRAME_POINTER_REGNUM \
1793 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1795 /* Strict versions, hard registers only */
1796 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1797 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1799 #ifndef REG_OK_STRICT
1800 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1801 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1804 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1805 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1808 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1809 that is a valid memory address for an instruction.
1810 The MODE argument is the machine mode for the MEM expression
1811 that wants to use this address.
1813 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1814 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1816 See legitimize_pic_address in i386.c for details as to what
1817 constitutes a legitimate address when -fpic is used. */
1819 #define MAX_REGS_PER_ADDRESS 2
1821 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1823 /* Nonzero if the constant value X is a legitimate general operand.
1824 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1826 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1828 #ifdef REG_OK_STRICT
1829 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1831 if (legitimate_address_p ((MODE), (X), 1)) \
1836 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1838 if (legitimate_address_p ((MODE), (X), 0)) \
1844 /* If defined, a C expression to determine the base term of address X.
1845 This macro is used in only one place: `find_base_term' in alias.c.
1847 It is always safe for this macro to not be defined. It exists so
1848 that alias analysis can understand machine-dependent addresses.
1850 The typical use of this macro is to handle addresses containing
1851 a label_ref or symbol_ref within an UNSPEC. */
1853 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1855 /* Try machine-dependent ways of modifying an illegitimate address
1856 to be legitimate. If we find one, return the new, valid address.
1857 This macro is used in only one place: `memory_address' in explow.c.
1859 OLDX is the address as it was before break_out_memory_refs was called.
1860 In some cases it is useful to look at this to decide what needs to be done.
1862 MODE and WIN are passed so that this macro can use
1863 GO_IF_LEGITIMATE_ADDRESS.
1865 It is always safe for this macro to do nothing. It exists to recognize
1866 opportunities to optimize the output.
1868 For the 80386, we handle X+REG by loading X into a register R and
1869 using R+REG. R will go in a general reg and indexing will be used.
1870 However, if REG is a broken-out memory address or multiplication,
1871 nothing needs to be done because REG can certainly go in a general reg.
1873 When -fpic is used, special handling is needed for symbolic references.
1874 See comments by legitimize_pic_address in i386.c for details. */
1876 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1878 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1879 if (memory_address_p ((MODE), (X))) \
1883 /* Nonzero if the constant value X is a legitimate general operand
1884 when generating PIC code. It is given that flag_pic is on and
1885 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1887 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1889 #define SYMBOLIC_CONST(X) \
1890 (GET_CODE (X) == SYMBOL_REF \
1891 || GET_CODE (X) == LABEL_REF \
1892 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1894 /* Go to LABEL if ADDR (a legitimate address expression)
1895 has an effect that depends on the machine mode it is used for.
1896 On the 80386, only postdecrement and postincrement address depend thus
1897 (the amount of decrement or increment being the length of the operand).
1898 These are now caught in recog.c. */
1899 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1901 /* Max number of args passed in registers. If this is more than 3, we will
1902 have problems with ebx (register #4), since it is a caller save register and
1903 is also used as the pic register in ELF. So for now, don't allow more than
1904 3 registers to be passed in registers. */
1906 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1908 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1910 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1913 /* Specify the machine mode that this machine uses
1914 for the index in the tablejump instruction. */
1915 #define CASE_VECTOR_MODE \
1916 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1918 /* Define this as 1 if `char' should by default be signed; else as 0. */
1919 #define DEFAULT_SIGNED_CHAR 1
1921 /* Max number of bytes we can move from memory to memory
1922 in one reasonably fast instruction. */
1925 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1926 move efficiently, as opposed to MOVE_MAX which is the maximum
1927 number of bytes we can move with a single instruction. */
1928 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1930 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1931 move-instruction pairs, we will do a movmem or libcall instead.
1932 Increasing the value will always make code faster, but eventually
1933 incurs high cost in increased code size.
1935 If you don't define this, a reasonable default is used. */
1937 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1939 /* If a clear memory operation would take CLEAR_RATIO or more simple
1940 move-instruction sequences, we will do a clrmem or libcall instead. */
1942 #define CLEAR_RATIO (optimize_size ? 2 \
1943 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1945 /* Define if shifts truncate the shift count
1946 which implies one can omit a sign-extension or zero-extension
1947 of a shift count. */
1948 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1950 /* #define SHIFT_COUNT_TRUNCATED */
1952 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1953 is done just by pretending it is already truncated. */
1954 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1956 /* A macro to update M and UNSIGNEDP when an object whose type is
1957 TYPE and which has the specified mode and signedness is to be
1958 stored in a register. This macro is only called when TYPE is a
1961 On i386 it is sometimes useful to promote HImode and QImode
1962 quantities to SImode. The choice depends on target type. */
1964 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1966 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1967 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1971 /* Specify the machine mode that pointers have.
1972 After generation of rtl, the compiler makes no further distinction
1973 between pointers and any other objects of this machine mode. */
1974 #define Pmode (TARGET_64BIT ? DImode : SImode)
1976 /* A function address in a call instruction
1977 is a byte address (for indexing purposes)
1978 so give the MEM rtx a byte's mode. */
1979 #define FUNCTION_MODE QImode
1981 /* A C expression for the cost of moving data from a register in class FROM to
1982 one in class TO. The classes are expressed using the enumeration values
1983 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1984 interpreted relative to that.
1986 It is not required that the cost always equal 2 when FROM is the same as TO;
1987 on some machines it is expensive to move between registers if they are not
1988 general registers. */
1990 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1991 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1993 /* A C expression for the cost of moving data of mode M between a
1994 register and memory. A value of 2 is the default; this cost is
1995 relative to those in `REGISTER_MOVE_COST'.
1997 If moving between registers and memory is more expensive than
1998 between two registers, you should define this macro to express the
2001 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2002 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2004 /* A C expression for the cost of a branch instruction. A value of 1
2005 is the default; other values are interpreted relative to that. */
2007 #define BRANCH_COST ix86_branch_cost
2009 /* Define this macro as a C expression which is nonzero if accessing
2010 less than a word of memory (i.e. a `char' or a `short') is no
2011 faster than accessing a word of memory, i.e., if such access
2012 require more than one instruction or if there is no difference in
2013 cost between byte and (aligned) word loads.
2015 When this macro is not defined, the compiler will access a field by
2016 finding the smallest containing object; when it is defined, a
2017 fullword load will be used if alignment permits. Unless bytes
2018 accesses are faster than word accesses, using word accesses is
2019 preferable since it may eliminate subsequent memory access if
2020 subsequent accesses occur to other fields in the same word of the
2021 structure, but to different bytes. */
2023 #define SLOW_BYTE_ACCESS 0
2025 /* Nonzero if access to memory by shorts is slow and undesirable. */
2026 #define SLOW_SHORT_ACCESS 0
2028 /* Define this macro to be the value 1 if unaligned accesses have a
2029 cost many times greater than aligned accesses, for example if they
2030 are emulated in a trap handler.
2032 When this macro is nonzero, the compiler will act as if
2033 `STRICT_ALIGNMENT' were nonzero when generating code for block
2034 moves. This can cause significantly more instructions to be
2035 produced. Therefore, do not set this macro nonzero if unaligned
2036 accesses only add a cycle or two to the time for a memory access.
2038 If the value of this macro is always zero, it need not be defined. */
2040 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2042 /* Define this macro if it is as good or better to call a constant
2043 function address than to call an address kept in a register.
2045 Desirable on the 386 because a CALL with a constant address is
2046 faster than one with a register address. */
2048 #define NO_FUNCTION_CSE
2050 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2051 return the mode to be used for the comparison.
2053 For floating-point equality comparisons, CCFPEQmode should be used.
2054 VOIDmode should be used in all other cases.
2056 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2057 possible, to allow for more combinations. */
2059 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2061 /* Return nonzero if MODE implies a floating point inequality can be
2064 #define REVERSIBLE_CC_MODE(MODE) 1
2066 /* A C expression whose value is reversed condition code of the CODE for
2067 comparison done in CC_MODE mode. */
2068 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2071 /* Control the assembler format that we output, to the extent
2072 this does not vary between assemblers. */
2074 /* How to refer to registers in assembler output.
2075 This sequence is indexed by compiler's hard-register-number (see above). */
2077 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2078 For non floating point regs, the following are the HImode names.
2080 For float regs, the stack top is sometimes referred to as "%st(0)"
2081 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2083 #define HI_REGISTER_NAMES \
2084 {"ax","dx","cx","bx","si","di","bp","sp", \
2085 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2086 "argp", "flags", "fpsr", "fpcr", "frame", \
2087 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2088 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2089 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2090 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2092 #define REGISTER_NAMES HI_REGISTER_NAMES
2094 /* Table of additional register names to use in user input. */
2096 #define ADDITIONAL_REGISTER_NAMES \
2097 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2098 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2099 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2100 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2101 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2102 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2104 /* Note we are omitting these since currently I don't know how
2105 to get gcc to use these, since they want the same but different
2106 number as al, and ax.
2109 #define QI_REGISTER_NAMES \
2110 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2112 /* These parallel the array above, and can be used to access bits 8:15
2113 of regs 0 through 3. */
2115 #define QI_HIGH_REGISTER_NAMES \
2116 {"ah", "dh", "ch", "bh", }
2118 /* How to renumber registers for dbx and gdb. */
2120 #define DBX_REGISTER_NUMBER(N) \
2121 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2123 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2124 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2125 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2127 /* Before the prologue, RA is at 0(%esp). */
2128 #define INCOMING_RETURN_ADDR_RTX \
2129 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2131 /* After the prologue, RA is at -4(AP) in the current frame. */
2132 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2134 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2135 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2137 /* PC is dbx register 8; let's use that column for RA. */
2138 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2140 /* Before the prologue, the top of the frame is at 4(%esp). */
2141 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2143 /* Describe how we implement __builtin_eh_return. */
2144 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2145 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2148 /* Select a format to encode pointers in exception handling data. CODE
2149 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2150 true if the symbol may be affected by dynamic relocations.
2152 ??? All x86 object file formats are capable of representing this.
2153 After all, the relocation needed is the same as for the call insn.
2154 Whether or not a particular assembler allows us to enter such, I
2155 guess we'll have to see. */
2156 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2157 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2159 /* This is how to output an insn to push a register on the stack.
2160 It need not be very fast code. */
2162 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2165 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2166 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2168 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2171 /* This is how to output an insn to pop a register from the stack.
2172 It need not be very fast code. */
2174 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2177 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2178 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2180 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2183 /* This is how to output an element of a case-vector that is absolute. */
2185 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2186 ix86_output_addr_vec_elt ((FILE), (VALUE))
2188 /* This is how to output an element of a case-vector that is relative. */
2190 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2191 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2193 /* Under some conditions we need jump tables in the text section,
2194 because the assembler cannot handle label differences between
2195 sections. This is the case for x86_64 on Mach-O for example. */
2197 #define JUMP_TABLES_IN_TEXT_SECTION \
2198 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2199 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2201 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2202 and switch back. For x86 we do this only to save a few bytes that
2203 would otherwise be unused in the text section. */
2204 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2205 asm (SECTION_OP "\n\t" \
2206 "call " USER_LABEL_PREFIX #FUNC "\n" \
2207 TEXT_SECTION_ASM_OP);
2209 /* Print operand X (an rtx) in assembler syntax to file FILE.
2210 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2211 Effect of various CODE letters is described in i386.c near
2212 print_operand function. */
2214 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2215 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2217 #define PRINT_OPERAND(FILE, X, CODE) \
2218 print_operand ((FILE), (X), (CODE))
2220 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2221 print_operand_address ((FILE), (ADDR))
2223 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2225 if (! output_addr_const_extra (FILE, (X))) \
2229 /* Which processor to schedule for. The cpu attribute defines a list that
2230 mirrors this list, so changes to i386.md must be made at the same time. */
2234 PROCESSOR_I386, /* 80386 */
2235 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2237 PROCESSOR_PENTIUMPRO,
2245 PROCESSOR_GENERIC32,
2246 PROCESSOR_GENERIC64,
2251 extern enum processor_type ix86_tune;
2252 extern enum processor_type ix86_arch;
2260 extern enum fpmath_unit ix86_fpmath;
2269 extern enum tls_dialect ix86_tls_dialect;
2272 CM_32, /* The traditional 32-bit ABI. */
2273 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2274 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2275 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2276 CM_LARGE, /* No assumptions. */
2277 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2278 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2279 CM_LARGE_PIC /* No assumptions. */
2282 extern enum cmodel ix86_cmodel;
2284 /* Size of the RED_ZONE area. */
2285 #define RED_ZONE_SIZE 128
2286 /* Reserved area of the red zone for temporaries. */
2287 #define RED_ZONE_RESERVE 8
2294 extern enum asm_dialect ix86_asm_dialect;
2295 extern unsigned int ix86_preferred_stack_boundary;
2296 extern int ix86_branch_cost, ix86_section_threshold;
2298 /* Smallest class containing REGNO. */
2299 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2301 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2302 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2303 extern rtx ix86_compare_emitted;
2305 /* To properly truncate FP values into integers, we need to set i387 control
2306 word. We can't emit proper mode switching code before reload, as spills
2307 generated by reload may truncate values incorrectly, but we still can avoid
2308 redundant computation of new control word by the mode switching pass.
2309 The fldcw instructions are still emitted redundantly, but this is probably
2310 not going to be noticeable problem, as most CPUs do have fast path for
2313 The machinery is to emit simple truncation instructions and split them
2314 before reload to instructions having USEs of two memory locations that
2315 are filled by this code to old and new control word.
2317 Post-reload pass may be later used to eliminate the redundant fildcw if
2329 enum ix86_stack_slot
2337 MAX_386_STACK_LOCALS
2340 /* Define this macro if the port needs extra instructions inserted
2341 for mode switching in an optimizing compilation. */
2343 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2344 ix86_optimize_mode_switching[(ENTITY)]
2346 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2347 initializer for an array of integers. Each initializer element N
2348 refers to an entity that needs mode switching, and specifies the
2349 number of different modes that might need to be set for this
2350 entity. The position of the initializer in the initializer -
2351 starting counting at zero - determines the integer that is used to
2352 refer to the mode-switched entity in question. */
2354 #define NUM_MODES_FOR_MODE_SWITCHING \
2355 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2357 /* ENTITY is an integer specifying a mode-switched entity. If
2358 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2359 return an integer value not larger than the corresponding element
2360 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2361 must be switched into prior to the execution of INSN. */
2363 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2365 /* This macro specifies the order in which modes for ENTITY are
2366 processed. 0 is the highest priority. */
2368 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2370 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2371 is the set of hard registers live at the point where the insn(s)
2372 are to be inserted. */
2374 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2375 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2376 ? emit_i387_cw_initialization (MODE), 0 \
2380 /* Avoid renaming of stack registers, as doing so in combination with
2381 scheduling just increases amount of live registers at time and in
2382 the turn amount of fxch instructions needed.
2384 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2386 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2387 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2390 #define FASTCALL_PREFIX '@'
2392 struct machine_function GTY(())
2394 struct stack_local_entry *stack_locals;
2395 const char *some_ld_name;
2396 rtx force_align_arg_pointer;
2397 int save_varrargs_registers;
2398 int accesses_prev_frame;
2399 int optimize_mode_switching[MAX_386_ENTITIES];
2400 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2401 determine the style used. */
2402 int use_fast_prologue_epilogue;
2403 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2405 int use_fast_prologue_epilogue_nregs;
2406 /* If true, the current function needs the default PIC register, not
2407 an alternate register (on x86) and must not use the red zone (on
2408 x86_64), even if it's a leaf function. We don't want the
2409 function to be regarded as non-leaf because TLS calls need not
2410 affect register allocation. This flag is set when a TLS call
2411 instruction is expanded within a function, and never reset, even
2412 if all such instructions are optimized away. Use the
2413 ix86_current_function_calls_tls_descriptor macro for a better
2415 int tls_descriptor_call_expanded_p;
2418 #define ix86_stack_locals (cfun->machine->stack_locals)
2419 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2420 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2421 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2422 (cfun->machine->tls_descriptor_call_expanded_p)
2423 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2424 calls are optimized away, we try to detect cases in which it was
2425 optimized away. Since such instructions (use (reg REG_SP)), we can
2426 verify whether there's any such instruction live by testing that
2428 #define ix86_current_function_calls_tls_descriptor \
2429 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2431 /* Control behavior of x86_file_start. */
2432 #define X86_FILE_START_VERSION_DIRECTIVE false
2433 #define X86_FILE_START_FLTUSED false
2435 /* Flag to mark data that is in the large address area. */
2436 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2437 #define SYMBOL_REF_FAR_ADDR_P(X) \
2438 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2440 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2441 have defined always, to avoid ifdefing. */
2442 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2443 #define SYMBOL_REF_DLLIMPORT_P(X) \
2444 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2446 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2447 #define SYMBOL_REF_DLLEXPORT_P(X) \
2448 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
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