1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 /* The purpose of this file is to define the characteristics of the i386,
24 independent of assembler syntax or operating system.
26 Three other files build on this one to describe a specific assembler syntax:
27 bsd386.h, att386.h, and sun386.h.
29 The actual tm.h file for a particular system should include
30 this file, and then the file for the appropriate assembler syntax.
32 Many macros that specify assembler syntax are omitted entirely from
33 this file because they really belong in the files for particular
34 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
35 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
36 that start with ASM_ or end in ASM_OP. */
38 #include "config/vxworks-dummy.h"
40 /* Algorithm to expand string function with. */
53 #define NAX_STRINGOP_ALGS 4
55 /* Specify what algorithm to use for stringops on known size.
56 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
57 known at compile time or estimated via feedback, the SIZE array
58 is walked in order until MAX is greater then the estimate (or -1
59 means infinity). Corresponding ALG is used then.
60 For example initializer:
61 {{256, loop}, {-1, rep_prefix_4_byte}}
62 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
66 const enum stringop_alg unknown_size;
67 const struct stringop_strategy {
69 const enum stringop_alg alg;
70 } size [NAX_STRINGOP_ALGS];
73 /* Define the specific costs for a given cpu */
75 struct processor_costs {
76 const int add; /* cost of an add instruction */
77 const int lea; /* cost of a lea instruction */
78 const int shift_var; /* variable shift costs */
79 const int shift_const; /* constant shift costs */
80 const int mult_init[5]; /* cost of starting a multiply
81 in QImode, HImode, SImode, DImode, TImode*/
82 const int mult_bit; /* cost of multiply per each bit set */
83 const int divide[5]; /* cost of a divide/mod
84 in QImode, HImode, SImode, DImode, TImode*/
85 int movsx; /* The cost of movsx operation. */
86 int movzx; /* The cost of movzx operation. */
87 const int large_insn; /* insns larger than this cost more */
88 const int move_ratio; /* The threshold of number of scalar
89 memory-to-memory move insns. */
90 const int movzbl_load; /* cost of loading using movzbl */
91 const int int_load[3]; /* cost of loading integer registers
92 in QImode, HImode and SImode relative
93 to reg-reg move (2). */
94 const int int_store[3]; /* cost of storing integer register
95 in QImode, HImode and SImode */
96 const int fp_move; /* cost of reg,reg fld/fst */
97 const int fp_load[3]; /* cost of loading FP register
98 in SFmode, DFmode and XFmode */
99 const int fp_store[3]; /* cost of storing FP register
100 in SFmode, DFmode and XFmode */
101 const int mmx_move; /* cost of moving MMX register. */
102 const int mmx_load[2]; /* cost of loading MMX register
103 in SImode and DImode */
104 const int mmx_store[2]; /* cost of storing MMX register
105 in SImode and DImode */
106 const int sse_move; /* cost of moving SSE register. */
107 const int sse_load[3]; /* cost of loading SSE register
108 in SImode, DImode and TImode*/
109 const int sse_store[3]; /* cost of storing SSE register
110 in SImode, DImode and TImode*/
111 const int mmxsse_to_integer; /* cost of moving mmxsse register to
112 integer and vice versa. */
113 const int prefetch_block; /* bytes moved to cache for prefetch. */
114 const int simultaneous_prefetches; /* number of parallel prefetch
116 const int branch_cost; /* Default value for BRANCH_COST. */
117 const int fadd; /* cost of FADD and FSUB instructions. */
118 const int fmul; /* cost of FMUL instruction. */
119 const int fdiv; /* cost of FDIV instruction. */
120 const int fabs; /* cost of FABS instruction. */
121 const int fchs; /* cost of FCHS instruction. */
122 const int fsqrt; /* cost of FSQRT instruction. */
123 /* Specify what algorithm
124 to use for stringops on unknown size. */
125 struct stringop_algs memcpy[2], memset[2];
128 extern const struct processor_costs *ix86_cost;
130 /* Macros used in the machine description to test the flags. */
132 /* configure can arrange to make this 2, to force a 486. */
134 #ifndef TARGET_CPU_DEFAULT
135 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
138 #ifndef TARGET_FPMATH_DEFAULT
139 #define TARGET_FPMATH_DEFAULT \
140 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
143 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
145 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
146 compile-time constant. */
150 #define TARGET_64BIT 1
152 #define TARGET_64BIT 0
155 #ifndef TARGET_BI_ARCH
157 #if TARGET_64BIT_DEFAULT
158 #define TARGET_64BIT 1
160 #define TARGET_64BIT 0
165 #define HAS_LONG_COND_BRANCH 1
166 #define HAS_LONG_UNCOND_BRANCH 1
168 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
169 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
170 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
171 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
172 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
173 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
174 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
175 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
176 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
177 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
178 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
179 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
180 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
181 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
182 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
183 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
185 /* Feature tests against the various tunings. */
186 enum ix86_tune_indices {
188 X86_TUNE_PUSH_MEMORY,
189 X86_TUNE_ZERO_EXTEND_WITH_AND,
190 X86_TUNE_USE_BIT_TEST,
191 X86_TUNE_UNROLL_STRLEN,
192 X86_TUNE_DEEP_BRANCH_PREDICTION,
193 X86_TUNE_BRANCH_PREDICTION_HINTS,
194 X86_TUNE_DOUBLE_WITH_ADD,
197 X86_TUNE_PARTIAL_REG_STALL,
198 X86_TUNE_PARTIAL_FLAG_REG_STALL,
199 X86_TUNE_USE_HIMODE_FIOP,
200 X86_TUNE_USE_SIMODE_FIOP,
204 X86_TUNE_SPLIT_LONG_MOVES,
205 X86_TUNE_READ_MODIFY_WRITE,
206 X86_TUNE_READ_MODIFY,
207 X86_TUNE_PROMOTE_QIMODE,
208 X86_TUNE_FAST_PREFIX,
209 X86_TUNE_SINGLE_STRINGOP,
210 X86_TUNE_QIMODE_MATH,
211 X86_TUNE_HIMODE_MATH,
212 X86_TUNE_PROMOTE_QI_REGS,
213 X86_TUNE_PROMOTE_HI_REGS,
218 X86_TUNE_INTEGER_DFMODE_MOVES,
219 X86_TUNE_PARTIAL_REG_DEPENDENCY,
220 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
221 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
222 X86_TUNE_SSE_SPLIT_REGS,
223 X86_TUNE_SSE_TYPELESS_STORES,
224 X86_TUNE_SSE_LOAD0_BY_PXOR,
225 X86_TUNE_MEMORY_MISMATCH_STALL,
226 X86_TUNE_PROLOGUE_USING_MOVE,
227 X86_TUNE_EPILOGUE_USING_MOVE,
230 X86_TUNE_INTER_UNIT_MOVES,
231 X86_TUNE_FOUR_JUMP_LIMIT,
235 X86_TUNE_PAD_RETURNS,
236 X86_TUNE_EXT_80387_CONSTANTS,
237 X86_TUNE_SHORTEN_X87_SSE,
238 X86_TUNE_AVOID_VECTOR_DECODE,
239 X86_TUNE_PROMOTE_HIMODE_IMUL,
240 X86_TUNE_SLOW_IMUL_IMM32_MEM,
241 X86_TUNE_SLOW_IMUL_IMM8,
242 X86_TUNE_MOVE_M1_VIA_OR,
243 X86_TUNE_NOT_UNPAIRABLE,
244 X86_TUNE_NOT_VECTORMODE,
249 extern unsigned int ix86_tune_features[X86_TUNE_LAST];
251 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
252 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
253 #define TARGET_ZERO_EXTEND_WITH_AND \
254 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
255 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
256 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
257 #define TARGET_DEEP_BRANCH_PREDICTION \
258 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
259 #define TARGET_BRANCH_PREDICTION_HINTS \
260 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
261 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
262 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
263 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
264 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
265 #define TARGET_PARTIAL_FLAG_REG_STALL \
266 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
267 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
268 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
269 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
270 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
271 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
272 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
273 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
274 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
275 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
276 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
277 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
278 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
279 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
280 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
281 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
282 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
283 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
284 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
285 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
286 #define TARGET_INTEGER_DFMODE_MOVES \
287 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
288 #define TARGET_PARTIAL_REG_DEPENDENCY \
289 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
290 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
291 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
292 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
293 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
294 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
295 #define TARGET_SSE_TYPELESS_STORES \
296 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
297 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
298 #define TARGET_MEMORY_MISMATCH_STALL \
299 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
300 #define TARGET_PROLOGUE_USING_MOVE \
301 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
302 #define TARGET_EPILOGUE_USING_MOVE \
303 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
304 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
305 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
306 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
307 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
308 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
309 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
310 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
311 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
312 #define TARGET_EXT_80387_CONSTANTS \
313 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
314 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
315 #define TARGET_AVOID_VECTOR_DECODE \
316 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
317 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
318 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
319 #define TARGET_SLOW_IMUL_IMM32_MEM \
320 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
321 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
322 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
323 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
324 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
326 /* Feature tests against the various architecture variations. */
327 enum ix86_arch_indices {
328 X86_ARCH_CMOVE, /* || TARGET_SSE */
337 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
339 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
340 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
341 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
342 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
343 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
345 #define TARGET_CMPXCHG16B x86_cmpxchg16b
346 #define TARGET_SAHF x86_sahf
348 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
350 extern int x86_prefetch_sse;
351 #define TARGET_PREFETCH_SSE x86_prefetch_sse
353 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
355 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
356 #define TARGET_MIX_SSE_I387 \
357 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
359 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
360 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
361 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
362 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
364 #ifndef TARGET_64BIT_DEFAULT
365 #define TARGET_64BIT_DEFAULT 0
367 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
368 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
371 /* Once GDB has been enhanced to deal with functions without frame
372 pointers, we can change this to allow for elimination of
373 the frame pointer in leaf functions. */
374 #define TARGET_DEFAULT 0
376 /* Extra bits to force on w/ 64-bit mode. */
377 #define TARGET_SUBTARGET64_DEFAULT 0
379 /* This is not really a target flag, but is done this way so that
380 it's analogous to similar code for Mach-O on PowerPC. darwin.h
381 redefines this to 1. */
382 #define TARGET_MACHO 0
384 /* Likewise, for the Windows 64-bit ABI. */
385 #define TARGET_64BIT_MS_ABI 0
387 /* Subtargets may reset this to 1 in order to enable 96-bit long double
388 with the rounding mode forced to 53 bits. */
389 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
391 /* Sometimes certain combinations of command options do not make
392 sense on a particular target machine. You can define a macro
393 `OVERRIDE_OPTIONS' to take account of this. This macro, if
394 defined, is executed once just after all the command options have
397 Don't use this macro to turn on various extra optimizations for
398 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
400 #define OVERRIDE_OPTIONS override_options ()
402 /* Define this to change the optimizations performed by default. */
403 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
404 optimization_options ((LEVEL), (SIZE))
406 /* -march=native handling only makes sense with compiler running on
407 an x86 or x86_64 chip. If changing this condition, also change
408 the condition in driver-i386.c. */
409 #if defined(__i386__) || defined(__x86_64__)
410 /* In driver-i386.c. */
411 extern const char *host_detect_local_cpu (int argc, const char **argv);
412 #define EXTRA_SPEC_FUNCTIONS \
413 { "local_cpu_detect", host_detect_local_cpu },
414 #define HAVE_LOCAL_CPU_DETECT
417 /* Support for configure-time defaults of some command line options.
418 The order here is important so that -march doesn't squash the
419 tune or cpu values. */
420 #define OPTION_DEFAULT_SPECS \
421 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
422 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
423 {"arch", "%{!march=*:-march=%(VALUE)}"}
425 /* Specs for the compiler proper */
428 #define CC1_CPU_SPEC_1 "\
430 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
432 %{mintel-syntax:-masm=intel \
433 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
434 %{mno-intel-syntax:-masm=att \
435 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
437 #ifndef HAVE_LOCAL_CPU_DETECT
438 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
440 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
441 "%{march=native:%<march=native %:local_cpu_detect(arch) \
442 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
443 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
447 /* Target CPU builtins. */
448 #define TARGET_CPU_CPP_BUILTINS() \
451 size_t arch_len = strlen (ix86_arch_string); \
452 size_t tune_len = strlen (ix86_tune_string); \
453 int last_arch_char = ix86_arch_string[arch_len - 1]; \
454 int last_tune_char = ix86_tune_string[tune_len - 1]; \
458 builtin_assert ("cpu=x86_64"); \
459 builtin_assert ("machine=x86_64"); \
460 builtin_define ("__amd64"); \
461 builtin_define ("__amd64__"); \
462 builtin_define ("__x86_64"); \
463 builtin_define ("__x86_64__"); \
467 builtin_assert ("cpu=i386"); \
468 builtin_assert ("machine=i386"); \
469 builtin_define_std ("i386"); \
472 /* Built-ins based on -mtune= (or -march= if no \
475 builtin_define ("__tune_i386__"); \
476 else if (TARGET_486) \
477 builtin_define ("__tune_i486__"); \
478 else if (TARGET_PENTIUM) \
480 builtin_define ("__tune_i586__"); \
481 builtin_define ("__tune_pentium__"); \
482 if (last_tune_char == 'x') \
483 builtin_define ("__tune_pentium_mmx__"); \
485 else if (TARGET_PENTIUMPRO) \
487 builtin_define ("__tune_i686__"); \
488 builtin_define ("__tune_pentiumpro__"); \
489 switch (last_tune_char) \
492 builtin_define ("__tune_pentium3__"); \
495 builtin_define ("__tune_pentium2__"); \
499 else if (TARGET_GEODE) \
501 builtin_define ("__tune_geode__"); \
503 else if (TARGET_K6) \
505 builtin_define ("__tune_k6__"); \
506 if (last_tune_char == '2') \
507 builtin_define ("__tune_k6_2__"); \
508 else if (last_tune_char == '3') \
509 builtin_define ("__tune_k6_3__"); \
511 else if (TARGET_ATHLON) \
513 builtin_define ("__tune_athlon__"); \
514 /* Only plain "athlon" lacks SSE. */ \
515 if (last_tune_char != 'n') \
516 builtin_define ("__tune_athlon_sse__"); \
518 else if (TARGET_K8) \
519 builtin_define ("__tune_k8__"); \
520 else if (TARGET_AMDFAM10) \
521 builtin_define ("__tune_amdfam10__"); \
522 else if (TARGET_PENTIUM4) \
523 builtin_define ("__tune_pentium4__"); \
524 else if (TARGET_NOCONA) \
525 builtin_define ("__tune_nocona__"); \
526 else if (TARGET_CORE2) \
527 builtin_define ("__tune_core2__"); \
530 builtin_define ("__MMX__"); \
532 builtin_define ("__3dNOW__"); \
533 if (TARGET_3DNOW_A) \
534 builtin_define ("__3dNOW_A__"); \
536 builtin_define ("__SSE__"); \
538 builtin_define ("__SSE2__"); \
540 builtin_define ("__SSE3__"); \
542 builtin_define ("__SSSE3__"); \
544 builtin_define ("__SSE4A__"); \
545 if (TARGET_SSE_MATH && TARGET_SSE) \
546 builtin_define ("__SSE_MATH__"); \
547 if (TARGET_SSE_MATH && TARGET_SSE2) \
548 builtin_define ("__SSE2_MATH__"); \
550 /* Built-ins based on -march=. */ \
551 if (ix86_arch == PROCESSOR_I486) \
553 builtin_define ("__i486"); \
554 builtin_define ("__i486__"); \
556 else if (ix86_arch == PROCESSOR_PENTIUM) \
558 builtin_define ("__i586"); \
559 builtin_define ("__i586__"); \
560 builtin_define ("__pentium"); \
561 builtin_define ("__pentium__"); \
562 if (last_arch_char == 'x') \
563 builtin_define ("__pentium_mmx__"); \
565 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
567 builtin_define ("__i686"); \
568 builtin_define ("__i686__"); \
569 builtin_define ("__pentiumpro"); \
570 builtin_define ("__pentiumpro__"); \
572 else if (ix86_arch == PROCESSOR_GEODE) \
574 builtin_define ("__geode"); \
575 builtin_define ("__geode__"); \
577 else if (ix86_arch == PROCESSOR_K6) \
580 builtin_define ("__k6"); \
581 builtin_define ("__k6__"); \
582 if (last_arch_char == '2') \
583 builtin_define ("__k6_2__"); \
584 else if (last_arch_char == '3') \
585 builtin_define ("__k6_3__"); \
587 else if (ix86_arch == PROCESSOR_ATHLON) \
589 builtin_define ("__athlon"); \
590 builtin_define ("__athlon__"); \
591 /* Only plain "athlon" lacks SSE. */ \
592 if (last_arch_char != 'n') \
593 builtin_define ("__athlon_sse__"); \
595 else if (ix86_arch == PROCESSOR_K8) \
597 builtin_define ("__k8"); \
598 builtin_define ("__k8__"); \
600 else if (ix86_arch == PROCESSOR_AMDFAM10) \
602 builtin_define ("__amdfam10"); \
603 builtin_define ("__amdfam10__"); \
605 else if (ix86_arch == PROCESSOR_PENTIUM4) \
607 builtin_define ("__pentium4"); \
608 builtin_define ("__pentium4__"); \
610 else if (ix86_arch == PROCESSOR_NOCONA) \
612 builtin_define ("__nocona"); \
613 builtin_define ("__nocona__"); \
615 else if (ix86_arch == PROCESSOR_CORE2) \
617 builtin_define ("__core2"); \
618 builtin_define ("__core2__"); \
623 #define TARGET_CPU_DEFAULT_i386 0
624 #define TARGET_CPU_DEFAULT_i486 1
625 #define TARGET_CPU_DEFAULT_pentium 2
626 #define TARGET_CPU_DEFAULT_pentium_mmx 3
627 #define TARGET_CPU_DEFAULT_pentiumpro 4
628 #define TARGET_CPU_DEFAULT_pentium2 5
629 #define TARGET_CPU_DEFAULT_pentium3 6
630 #define TARGET_CPU_DEFAULT_pentium4 7
631 #define TARGET_CPU_DEFAULT_geode 8
632 #define TARGET_CPU_DEFAULT_k6 9
633 #define TARGET_CPU_DEFAULT_k6_2 10
634 #define TARGET_CPU_DEFAULT_k6_3 11
635 #define TARGET_CPU_DEFAULT_athlon 12
636 #define TARGET_CPU_DEFAULT_athlon_sse 13
637 #define TARGET_CPU_DEFAULT_k8 14
638 #define TARGET_CPU_DEFAULT_pentium_m 15
639 #define TARGET_CPU_DEFAULT_prescott 16
640 #define TARGET_CPU_DEFAULT_nocona 17
641 #define TARGET_CPU_DEFAULT_core2 18
642 #define TARGET_CPU_DEFAULT_generic 19
643 #define TARGET_CPU_DEFAULT_amdfam10 20
645 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
646 "pentiumpro", "pentium2", "pentium3", \
647 "pentium4", "geode", "k6", "k6-2", "k6-3", \
648 "athlon", "athlon-4", "k8", \
649 "pentium-m", "prescott", "nocona", \
650 "core2", "generic", "amdfam10"}
653 #define CC1_SPEC "%(cc1_cpu) "
656 /* This macro defines names of additional specifications to put in the
657 specs that can be used in various specifications like CC1_SPEC. Its
658 definition is an initializer with a subgrouping for each command option.
660 Each subgrouping contains a string constant, that defines the
661 specification name, and a string constant that used by the GCC driver
664 Do not define this macro if it does not need to do anything. */
666 #ifndef SUBTARGET_EXTRA_SPECS
667 #define SUBTARGET_EXTRA_SPECS
670 #define EXTRA_SPECS \
671 { "cc1_cpu", CC1_CPU_SPEC }, \
672 SUBTARGET_EXTRA_SPECS
674 /* target machine storage layout */
676 #define LONG_DOUBLE_TYPE_SIZE 80
678 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
679 FPU, assume that the fpcw is set to extended precision; when using
680 only SSE, rounding is correct; when using both SSE and the FPU,
681 the rounding precision is indeterminate, since either may be chosen
682 apparently at random. */
683 #define TARGET_FLT_EVAL_METHOD \
684 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
686 #define SHORT_TYPE_SIZE 16
687 #define INT_TYPE_SIZE 32
688 #define FLOAT_TYPE_SIZE 32
689 #define LONG_TYPE_SIZE BITS_PER_WORD
690 #define DOUBLE_TYPE_SIZE 64
691 #define LONG_LONG_TYPE_SIZE 64
693 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
694 #define MAX_BITS_PER_WORD 64
696 #define MAX_BITS_PER_WORD 32
699 /* Define this if most significant byte of a word is the lowest numbered. */
700 /* That is true on the 80386. */
702 #define BITS_BIG_ENDIAN 0
704 /* Define this if most significant byte of a word is the lowest numbered. */
705 /* That is not true on the 80386. */
706 #define BYTES_BIG_ENDIAN 0
708 /* Define this if most significant word of a multiword number is the lowest
710 /* Not true for 80386 */
711 #define WORDS_BIG_ENDIAN 0
713 /* Width of a word, in units (bytes). */
714 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
716 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
718 #define MIN_UNITS_PER_WORD 4
721 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
722 #define PARM_BOUNDARY BITS_PER_WORD
724 /* Boundary (in *bits*) on which stack pointer should be aligned. */
725 #define STACK_BOUNDARY BITS_PER_WORD
727 /* Boundary (in *bits*) on which the stack pointer prefers to be
728 aligned; the compiler cannot rely on having this alignment. */
729 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
731 /* As of July 2001, many runtimes do not align the stack properly when
732 entering main. This causes expand_main_function to forcibly align
733 the stack, which results in aligned frames for functions called from
734 main, though it does nothing for the alignment of main itself. */
735 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
736 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
738 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
739 mandatory for the 64-bit ABI, and may or may not be true for other
740 operating systems. */
741 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
743 /* Minimum allocation boundary for the code of a function. */
744 #define FUNCTION_BOUNDARY 8
746 /* C++ stores the virtual bit in the lowest bit of function pointers. */
747 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
749 /* Alignment of field after `int : 0' in a structure. */
751 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
753 /* Minimum size in bits of the largest boundary to which any
754 and all fundamental data types supported by the hardware
755 might need to be aligned. No data type wants to be aligned
758 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
759 and Pentium Pro XFmode values at 128 bit boundaries. */
761 #define BIGGEST_ALIGNMENT 128
763 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
764 #define ALIGN_MODE_128(MODE) \
765 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
767 /* The published ABIs say that doubles should be aligned on word
768 boundaries, so lower the alignment for structure fields unless
769 -malign-double is set. */
771 /* ??? Blah -- this macro is used directly by libobjc. Since it
772 supports no vector modes, cut out the complexity and fall back
773 on BIGGEST_FIELD_ALIGNMENT. */
774 #ifdef IN_TARGET_LIBS
776 #define BIGGEST_FIELD_ALIGNMENT 128
778 #define BIGGEST_FIELD_ALIGNMENT 32
781 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
782 x86_field_alignment (FIELD, COMPUTED)
785 /* If defined, a C expression to compute the alignment given to a
786 constant that is being placed in memory. EXP is the constant
787 and ALIGN is the alignment that the object would ordinarily have.
788 The value of this macro is used instead of that alignment to align
791 If this macro is not defined, then ALIGN is used.
793 The typical use of this macro is to increase alignment for string
794 constants to be word aligned so that `strcpy' calls that copy
795 constants can be done inline. */
797 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
799 /* If defined, a C expression to compute the alignment for a static
800 variable. TYPE is the data type, and ALIGN is the alignment that
801 the object would ordinarily have. The value of this macro is used
802 instead of that alignment to align the object.
804 If this macro is not defined, then ALIGN is used.
806 One use of this macro is to increase alignment of medium-size
807 data to make it all fit in fewer cache lines. Another is to
808 cause character arrays to be word-aligned so that `strcpy' calls
809 that copy constants to character arrays can be done inline. */
811 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
813 /* If defined, a C expression to compute the alignment for a local
814 variable. TYPE is the data type, and ALIGN is the alignment that
815 the object would ordinarily have. The value of this macro is used
816 instead of that alignment to align the object.
818 If this macro is not defined, then ALIGN is used.
820 One use of this macro is to increase alignment of medium-size
821 data to make it all fit in fewer cache lines. */
823 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
825 /* If defined, a C expression that gives the alignment boundary, in
826 bits, of an argument with the specified mode and type. If it is
827 not defined, `PARM_BOUNDARY' is used for all arguments. */
829 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
830 ix86_function_arg_boundary ((MODE), (TYPE))
832 /* Set this nonzero if move instructions will actually fail to work
833 when given unaligned data. */
834 #define STRICT_ALIGNMENT 0
836 /* If bit field type is int, don't let it cross an int,
837 and give entire struct the alignment of an int. */
838 /* Required on the 386 since it doesn't have bit-field insns. */
839 #define PCC_BITFIELD_TYPE_MATTERS 1
841 /* Standard register usage. */
843 /* This processor has special stack-like registers. See reg-stack.c
847 #define IS_STACK_MODE(MODE) \
848 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
849 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
852 /* Number of actual hardware registers.
853 The hardware registers are assigned numbers for the compiler
854 from 0 to just below FIRST_PSEUDO_REGISTER.
855 All registers that the compiler knows about must be given numbers,
856 even those that are not normally considered general registers.
858 In the 80386 we give the 8 general purpose registers the numbers 0-7.
859 We number the floating point registers 8-15.
860 Note that registers 0-7 can be accessed as a short or int,
861 while only 0-3 may be used with byte `mov' instructions.
863 Reg 16 does not correspond to any hardware register, but instead
864 appears in the RTL as an argument pointer prior to reload, and is
865 eliminated during reloading in favor of either the stack or frame
868 #define FIRST_PSEUDO_REGISTER 53
870 /* Number of hardware registers that go into the DWARF-2 unwind info.
871 If not defined, equals FIRST_PSEUDO_REGISTER. */
873 #define DWARF_FRAME_REGISTERS 17
875 /* 1 for registers that have pervasive standard uses
876 and are not available for the register allocator.
877 On the 80386, the stack pointer is such, as is the arg pointer.
879 The value is zero if the register is not fixed on either 32 or
880 64 bit targets, one if the register if fixed on both 32 and 64
881 bit targets, two if it is only fixed on 32bit targets and three
882 if its only fixed on 64bit targets.
883 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
885 #define FIXED_REGISTERS \
886 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
887 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
888 /*arg,flags,fpsr,fpcr,frame*/ \
890 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
891 0, 0, 0, 0, 0, 0, 0, 0, \
892 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
893 0, 0, 0, 0, 0, 0, 0, 0, \
894 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
895 2, 2, 2, 2, 2, 2, 2, 2, \
896 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
897 2, 2, 2, 2, 2, 2, 2, 2}
900 /* 1 for registers not available across function calls.
901 These must include the FIXED_REGISTERS and also any
902 registers that can be used without being saved.
903 The latter must include the registers where values are returned
904 and the register where structure-value addresses are passed.
905 Aside from that, you can include as many other registers as you like.
907 The value is zero if the register is not call used on either 32 or
908 64 bit targets, one if the register if call used on both 32 and 64
909 bit targets, two if it is only call used on 32bit targets and three
910 if its only call used on 64bit targets.
911 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
913 #define CALL_USED_REGISTERS \
914 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
915 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
916 /*arg,flags,fpsr,fpcr,frame*/ \
918 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
919 1, 1, 1, 1, 1, 1, 1, 1, \
920 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
921 1, 1, 1, 1, 1, 1, 1, 1, \
922 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
923 1, 1, 1, 1, 2, 2, 2, 2, \
924 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
925 1, 1, 1, 1, 1, 1, 1, 1} \
927 /* Order in which to allocate registers. Each register must be
928 listed once, even those in FIXED_REGISTERS. List frame pointer
929 late and fixed registers last. Note that, in general, we prefer
930 registers listed in CALL_USED_REGISTERS, keeping the others
931 available for storage of persistent values.
933 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
934 so this is just empty initializer for array. */
936 #define REG_ALLOC_ORDER \
937 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
938 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
939 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
942 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
943 to be rearranged based on a particular function. When using sse math,
944 we want to allocate SSE before x87 registers and vice versa. */
946 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
949 /* Macro to conditionally modify fixed_regs/call_used_regs. */
950 #define CONDITIONAL_REGISTER_USAGE \
954 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
956 if (fixed_regs[i] > 1) \
957 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
958 if (call_used_regs[i] > 1) \
959 call_used_regs[i] = (call_used_regs[i] \
960 == (TARGET_64BIT ? 3 : 2)); \
962 j = PIC_OFFSET_TABLE_REGNUM; \
963 if (j != INVALID_REGNUM) \
966 call_used_regs[j] = 1; \
971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
972 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
973 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
978 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
979 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
980 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
982 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
986 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
987 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
988 if (TEST_HARD_REG_BIT (x, i)) \
989 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
991 if (! TARGET_64BIT) \
994 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
996 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
999 if (TARGET_64BIT_MS_ABI) \
1001 call_used_regs[4 /*RSI*/] = 0; \
1002 call_used_regs[5 /*RDI*/] = 0; \
1006 /* Return number of consecutive hard regs needed starting at reg REGNO
1007 to hold something of mode MODE.
1008 This is ordinarily the length in words of a value of mode MODE
1009 but can be less for certain modes in special long registers.
1011 Actually there are no two word move instructions for consecutive
1012 registers. And only registers 0-3 may have mov byte instructions
1016 #define HARD_REGNO_NREGS(REGNO, MODE) \
1017 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1018 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1019 : ((MODE) == XFmode \
1020 ? (TARGET_64BIT ? 2 : 3) \
1021 : (MODE) == XCmode \
1022 ? (TARGET_64BIT ? 4 : 6) \
1023 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1025 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1026 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1027 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1029 : ((MODE) == XFmode || (MODE) == XCmode)) \
1032 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1034 #define VALID_SSE2_REG_MODE(MODE) \
1035 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1036 || (MODE) == V2DImode || (MODE) == DFmode)
1038 #define VALID_SSE_REG_MODE(MODE) \
1039 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1040 || (MODE) == SFmode || (MODE) == TFmode)
1042 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1043 ((MODE) == V2SFmode || (MODE) == SFmode)
1045 #define VALID_MMX_REG_MODE(MODE) \
1046 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1047 || (MODE) == V2SImode || (MODE) == SImode)
1049 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1050 place emms and femms instructions. */
1051 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
1053 #define VALID_FP_MODE_P(MODE) \
1054 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1055 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1057 #define VALID_INT_MODE_P(MODE) \
1058 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1059 || (MODE) == DImode \
1060 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1061 || (MODE) == CDImode \
1062 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1063 || (MODE) == TFmode || (MODE) == TCmode)))
1065 /* Return true for modes passed in SSE registers. */
1066 #define SSE_REG_MODE_P(MODE) \
1067 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1068 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1069 || (MODE) == V4SFmode || (MODE) == V4SImode)
1071 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1073 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1074 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1076 /* Value is 1 if it is a good idea to tie two pseudo registers
1077 when one has mode MODE1 and one has mode MODE2.
1078 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1079 for any hard reg, then this must be 0 for correct output. */
1081 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1083 /* It is possible to write patterns to move flags; but until someone
1085 #define AVOID_CCMODE_COPIES
1087 /* Specify the modes required to caller save a given hard regno.
1088 We do this on i386 to prevent flags from being saved at all.
1090 Kill any attempts to combine saving of modes. */
1092 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1093 (CC_REGNO_P (REGNO) ? VOIDmode \
1094 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1095 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1096 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1097 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1099 /* Specify the registers used for certain standard purposes.
1100 The values of these macros are register numbers. */
1102 /* on the 386 the pc register is %eip, and is not usable as a general
1103 register. The ordinary mov instructions won't work */
1104 /* #define PC_REGNUM */
1106 /* Register to use for pushing function arguments. */
1107 #define STACK_POINTER_REGNUM 7
1109 /* Base register for access to local variables of the function. */
1110 #define HARD_FRAME_POINTER_REGNUM 6
1112 /* Base register for access to local variables of the function. */
1113 #define FRAME_POINTER_REGNUM 20
1115 /* First floating point reg */
1116 #define FIRST_FLOAT_REG 8
1118 /* First & last stack-like regs */
1119 #define FIRST_STACK_REG FIRST_FLOAT_REG
1120 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1122 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1123 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1125 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1126 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1128 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1129 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1131 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1132 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1134 /* Value should be nonzero if functions must have frame pointers.
1135 Zero means the frame pointer need not be set up (and parms
1136 may be accessed via the stack pointer) in functions that seem suitable.
1137 This is computed in `reload', in reload1.c. */
1138 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1140 /* Override this in other tm.h files to cope with various OS lossage
1141 requiring a frame pointer. */
1142 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1143 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1146 /* Make sure we can access arbitrary call frames. */
1147 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1149 /* Base register for access to arguments of the function. */
1150 #define ARG_POINTER_REGNUM 16
1152 /* Register in which static-chain is passed to a function.
1153 We do use ECX as static chain register for 32 bit ABI. On the
1154 64bit ABI, ECX is an argument register, so we use R10 instead. */
1155 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1157 /* Register to hold the addressing base for position independent
1158 code access to data items. We don't use PIC pointer for 64bit
1159 mode. Define the regnum to dummy value to prevent gcc from
1160 pessimizing code dealing with EBX.
1162 To avoid clobbering a call-saved register unnecessarily, we renumber
1163 the pic register when possible. The change is visible after the
1164 prologue has been emitted. */
1166 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1168 #define PIC_OFFSET_TABLE_REGNUM \
1169 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1170 || !flag_pic ? INVALID_REGNUM \
1171 : reload_completed ? REGNO (pic_offset_table_rtx) \
1172 : REAL_PIC_OFFSET_TABLE_REGNUM)
1174 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1176 /* A C expression which can inhibit the returning of certain function
1177 values in registers, based on the type of value. A nonzero value
1178 says to return the function value in memory, just as large
1179 structures are always returned. Here TYPE will be a C expression
1180 of type `tree', representing the data type of the value.
1182 Note that values of mode `BLKmode' must be explicitly handled by
1183 this macro. Also, the option `-fpcc-struct-return' takes effect
1184 regardless of this macro. On most systems, it is possible to
1185 leave the macro undefined; this causes a default definition to be
1186 used, whose value is the constant 1 for `BLKmode' values, and 0
1189 Do not use this macro to indicate that structures and unions
1190 should always be returned in memory. You should instead use
1191 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1193 #define RETURN_IN_MEMORY(TYPE) \
1194 ix86_return_in_memory (TYPE)
1196 /* This is overridden by <cygwin.h>. */
1197 #define MS_AGGREGATE_RETURN 0
1199 /* This is overridden by <netware.h>. */
1200 #define KEEP_AGGREGATE_RETURN_POINTER 0
1202 /* Define the classes of registers for register constraints in the
1203 machine description. Also define ranges of constants.
1205 One of the classes must always be named ALL_REGS and include all hard regs.
1206 If there is more than one class, another class must be named NO_REGS
1207 and contain no registers.
1209 The name GENERAL_REGS must be the name of a class (or an alias for
1210 another name such as ALL_REGS). This is the class of registers
1211 that is allowed by "g" or "r" in a register constraint.
1212 Also, registers outside this class are allocated only when
1213 instructions express preferences for them.
1215 The classes must be numbered in nondecreasing order; that is,
1216 a larger-numbered class must never be contained completely
1217 in a smaller-numbered class.
1219 For any two classes, it is very desirable that there be another
1220 class that represents their union.
1222 It might seem that class BREG is unnecessary, since no useful 386
1223 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1224 and the "b" register constraint is useful in asms for syscalls.
1226 The flags, fpsr and fpcr registers are in no class. */
1231 AREG, DREG, CREG, BREG, SIREG, DIREG,
1232 AD_REGS, /* %eax/%edx for DImode */
1233 Q_REGS, /* %eax %ebx %ecx %edx */
1234 NON_Q_REGS, /* %esi %edi %ebp %esp */
1235 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1236 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1237 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1238 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1248 ALL_REGS, LIM_REG_CLASSES
1251 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1253 #define INTEGER_CLASS_P(CLASS) \
1254 reg_class_subset_p ((CLASS), GENERAL_REGS)
1255 #define FLOAT_CLASS_P(CLASS) \
1256 reg_class_subset_p ((CLASS), FLOAT_REGS)
1257 #define SSE_CLASS_P(CLASS) \
1258 ((CLASS) == SSE_REGS)
1259 #define MMX_CLASS_P(CLASS) \
1260 ((CLASS) == MMX_REGS)
1261 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1262 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1263 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1264 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1265 #define MAYBE_SSE_CLASS_P(CLASS) \
1266 reg_classes_intersect_p (SSE_REGS, (CLASS))
1267 #define MAYBE_MMX_CLASS_P(CLASS) \
1268 reg_classes_intersect_p (MMX_REGS, (CLASS))
1270 #define Q_CLASS_P(CLASS) \
1271 reg_class_subset_p ((CLASS), Q_REGS)
1273 /* Give names of register classes as strings for dump file. */
1275 #define REG_CLASS_NAMES \
1277 "AREG", "DREG", "CREG", "BREG", \
1280 "Q_REGS", "NON_Q_REGS", \
1284 "FP_TOP_REG", "FP_SECOND_REG", \
1288 "FP_TOP_SSE_REGS", \
1289 "FP_SECOND_SSE_REGS", \
1293 "FLOAT_INT_SSE_REGS", \
1296 /* Define which registers fit in which classes.
1297 This is an initializer for a vector of HARD_REG_SET
1298 of length N_REG_CLASSES. */
1300 #define REG_CLASS_CONTENTS \
1302 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1303 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1304 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1305 { 0x03, 0x0 }, /* AD_REGS */ \
1306 { 0x0f, 0x0 }, /* Q_REGS */ \
1307 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1308 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1309 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1310 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1311 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1312 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1313 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1314 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1315 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1316 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1317 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1318 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1319 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1320 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1321 { 0xffffffff,0x1fffff } \
1324 /* The same information, inverted:
1325 Return the class number of the smallest class containing
1326 reg number REGNO. This could be a conditional expression
1327 or could index an array. */
1329 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1331 /* When defined, the compiler allows registers explicitly used in the
1332 rtl to be used as spill registers but prevents the compiler from
1333 extending the lifetime of these registers. */
1335 #define SMALL_REGISTER_CLASSES 1
1337 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1339 #define GENERAL_REGNO_P(N) \
1340 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1342 #define GENERAL_REG_P(X) \
1343 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1345 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1347 #define REX_INT_REGNO_P(N) \
1348 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1349 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1351 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1352 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1353 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1354 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1356 #define X87_FLOAT_MODE_P(MODE) \
1357 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1359 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1360 #define SSE_REGNO_P(N) \
1361 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1362 || REX_SSE_REGNO_P (N))
1364 #define REX_SSE_REGNO_P(N) \
1365 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1367 #define SSE_REGNO(N) \
1368 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1370 #define SSE_FLOAT_MODE_P(MODE) \
1371 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1373 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1374 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1376 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1377 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1379 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1381 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1382 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1384 /* The class value for index registers, and the one for base regs. */
1386 #define INDEX_REG_CLASS INDEX_REGS
1387 #define BASE_REG_CLASS GENERAL_REGS
1389 /* Place additional restrictions on the register class to use when it
1390 is necessary to be able to hold a value of mode MODE in a reload
1391 register for which class CLASS would ordinarily be used. */
1393 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1394 ((MODE) == QImode && !TARGET_64BIT \
1395 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1396 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1399 /* Given an rtx X being reloaded into a reg required to be
1400 in class CLASS, return the class of reg to actually use.
1401 In general this is just CLASS; but on some machines
1402 in some cases it is preferable to use a more restrictive class.
1403 On the 80386 series, we prevent floating constants from being
1404 reloaded into floating registers (since no move-insn can do that)
1405 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1407 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1408 QImode must go into class Q_REGS.
1409 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1410 movdf to do mem-to-mem moves through integer regs. */
1412 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1413 ix86_preferred_reload_class ((X), (CLASS))
1415 /* Discourage putting floating-point values in SSE registers unless
1416 SSE math is being used, and likewise for the 387 registers. */
1418 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1419 ix86_preferred_output_reload_class ((X), (CLASS))
1421 /* If we are copying between general and FP registers, we need a memory
1422 location. The same is true for SSE and MMX registers. */
1423 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1424 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1426 /* QImode spills from non-QI registers need a scratch. This does not
1427 happen often -- the only example so far requires an uninitialized
1430 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1431 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1432 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1435 /* Return the maximum number of consecutive registers
1436 needed to represent mode MODE in a register of class CLASS. */
1437 /* On the 80386, this is the size of MODE in words,
1438 except in the FP regs, where a single reg is always enough. */
1439 #define CLASS_MAX_NREGS(CLASS, MODE) \
1440 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1441 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1442 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1443 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1445 /* A C expression whose value is nonzero if pseudos that have been
1446 assigned to registers of class CLASS would likely be spilled
1447 because registers of CLASS are needed for spill registers.
1449 The default value of this macro returns 1 if CLASS has exactly one
1450 register and zero otherwise. On most machines, this default
1451 should be used. Only define this macro to some other expression
1452 if pseudo allocated by `local-alloc.c' end up in memory because
1453 their hard registers were needed for spill registers. If this
1454 macro returns nonzero for those classes, those pseudos will only
1455 be allocated by `global.c', which knows how to reallocate the
1456 pseudo to another register. If there would not be another
1457 register available for reallocation, you should not change the
1458 definition of this macro since the only effect of such a
1459 definition would be to slow down register allocation. */
1461 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1462 (((CLASS) == AREG) \
1463 || ((CLASS) == DREG) \
1464 || ((CLASS) == CREG) \
1465 || ((CLASS) == BREG) \
1466 || ((CLASS) == AD_REGS) \
1467 || ((CLASS) == SIREG) \
1468 || ((CLASS) == DIREG) \
1469 || ((CLASS) == FP_TOP_REG) \
1470 || ((CLASS) == FP_SECOND_REG))
1472 /* Return a class of registers that cannot change FROM mode to TO mode. */
1474 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1475 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1477 /* Stack layout; function entry, exit and calling. */
1479 /* Define this if pushing a word on the stack
1480 makes the stack pointer a smaller address. */
1481 #define STACK_GROWS_DOWNWARD
1483 /* Define this to nonzero if the nominal address of the stack frame
1484 is at the high-address end of the local variables;
1485 that is, each additional local variable allocated
1486 goes at a more negative offset in the frame. */
1487 #define FRAME_GROWS_DOWNWARD 1
1489 /* Offset within stack frame to start allocating local variables at.
1490 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1491 first local allocated. Otherwise, it is the offset to the BEGINNING
1492 of the first local allocated. */
1493 #define STARTING_FRAME_OFFSET 0
1495 /* If we generate an insn to push BYTES bytes,
1496 this says how many the stack pointer really advances by.
1497 On 386, we have pushw instruction that decrements by exactly 2 no
1498 matter what the position was, there is no pushb.
1499 But as CIE data alignment factor on this arch is -4, we need to make
1500 sure all stack pointer adjustments are in multiple of 4.
1502 For 64bit ABI we round up to 8 bytes.
1505 #define PUSH_ROUNDING(BYTES) \
1507 ? (((BYTES) + 7) & (-8)) \
1508 : (((BYTES) + 3) & (-4)))
1510 /* If defined, the maximum amount of space required for outgoing arguments will
1511 be computed and placed into the variable
1512 `current_function_outgoing_args_size'. No space will be pushed onto the
1513 stack for each call; instead, the function prologue should increase the stack
1514 frame size by this amount. */
1516 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1518 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1519 instructions to pass outgoing arguments. */
1521 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1523 /* We want the stack and args grow in opposite directions, even if
1525 #define PUSH_ARGS_REVERSED 1
1527 /* Offset of first parameter from the argument pointer register value. */
1528 #define FIRST_PARM_OFFSET(FNDECL) 0
1530 /* Define this macro if functions should assume that stack space has been
1531 allocated for arguments even when their values are passed in registers.
1533 The value of this macro is the size, in bytes, of the area reserved for
1534 arguments passed in registers for the function represented by FNDECL.
1536 This space can be allocated by the caller, or be a part of the
1537 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1539 #define REG_PARM_STACK_SPACE(FNDECL) 0
1541 /* Value is the number of bytes of arguments automatically
1542 popped when returning from a subroutine call.
1543 FUNDECL is the declaration node of the function (as a tree),
1544 FUNTYPE is the data type of the function (as a tree),
1545 or for a library call it is an identifier node for the subroutine name.
1546 SIZE is the number of bytes of arguments passed on the stack.
1548 On the 80386, the RTD insn may be used to pop them if the number
1549 of args is fixed, but if the number is variable then the caller
1550 must pop them all. RTD can't be used for library calls now
1551 because the library is compiled with the Unix compiler.
1552 Use of RTD is a selectable option, since it is incompatible with
1553 standard Unix calling sequences. If the option is not selected,
1554 the caller must always pop the args.
1556 The attribute stdcall is equivalent to RTD on a per module basis. */
1558 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1559 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1561 #define FUNCTION_VALUE_REGNO_P(N) \
1562 ix86_function_value_regno_p (N)
1564 /* Define how to find the value returned by a library function
1565 assuming the value has mode MODE. */
1567 #define LIBCALL_VALUE(MODE) \
1568 ix86_libcall_value (MODE)
1570 /* Define the size of the result block used for communication between
1571 untyped_call and untyped_return. The block contains a DImode value
1572 followed by the block used by fnsave and frstor. */
1574 #define APPLY_RESULT_SIZE (8+108)
1576 /* 1 if N is a possible register number for function argument passing. */
1577 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1579 /* Define a data type for recording info about an argument list
1580 during the scan of that argument list. This data type should
1581 hold all necessary information about the function itself
1582 and about the args processed so far, enough to enable macros
1583 such as FUNCTION_ARG to determine where the next arg should go. */
1585 typedef struct ix86_args {
1586 int words; /* # words passed so far */
1587 int nregs; /* # registers available for passing */
1588 int regno; /* next available register number */
1589 int fastcall; /* fastcall calling convention is used */
1590 int sse_words; /* # sse words passed so far */
1591 int sse_nregs; /* # sse registers available for passing */
1592 int warn_sse; /* True when we want to warn about SSE ABI. */
1593 int warn_mmx; /* True when we want to warn about MMX ABI. */
1594 int sse_regno; /* next available sse register number */
1595 int mmx_words; /* # mmx words passed so far */
1596 int mmx_nregs; /* # mmx registers available for passing */
1597 int mmx_regno; /* next available mmx register number */
1598 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1599 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1600 be passed in SSE registers. Otherwise 0. */
1603 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1604 for a call to a function whose data type is FNTYPE.
1605 For a library call, FNTYPE is 0. */
1607 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1608 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1610 /* Update the data in CUM to advance over an argument
1611 of mode MODE and data type TYPE.
1612 (TYPE is null for libcalls where that information may not be available.) */
1614 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1615 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1617 /* Define where to put the arguments to a function.
1618 Value is zero to push the argument on the stack,
1619 or a hard register in which to store the argument.
1621 MODE is the argument's machine mode.
1622 TYPE is the data type of the argument (as a tree).
1623 This is null for libcalls where that information may
1625 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1626 the preceding args and about the function being called.
1627 NAMED is nonzero if this argument is a named parameter
1628 (otherwise it is an extra parameter matching an ellipsis). */
1630 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1631 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1633 /* Implement `va_start' for varargs and stdarg. */
1634 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1635 ix86_va_start (VALIST, NEXTARG)
1637 #define TARGET_ASM_FILE_END ix86_file_end
1638 #define NEED_INDICATE_EXEC_STACK 0
1640 /* Output assembler code to FILE to increment profiler label # LABELNO
1641 for profiling a function entry. */
1643 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1645 #define MCOUNT_NAME "_mcount"
1647 #define PROFILE_COUNT_REGISTER "edx"
1649 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1650 the stack pointer does not matter. The value is tested only in
1651 functions that have frame pointers.
1652 No definition is equivalent to always zero. */
1653 /* Note on the 386 it might be more efficient not to define this since
1654 we have to restore it ourselves from the frame pointer, in order to
1657 #define EXIT_IGNORE_STACK 1
1659 /* Output assembler code for a block containing the constant parts
1660 of a trampoline, leaving space for the variable parts. */
1662 /* On the 386, the trampoline contains two instructions:
1665 The trampoline is generated entirely at runtime. The operand of JMP
1666 is the address of FUNCTION relative to the instruction following the
1667 JMP (which is 5 bytes long). */
1669 /* Length in units of the trampoline for entering a nested function. */
1671 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1673 /* Emit RTL insns to initialize the variable parts of a trampoline.
1674 FNADDR is an RTX for the address of the function's pure code.
1675 CXT is an RTX for the static chain value for the function. */
1677 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1678 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1680 /* Definitions for register eliminations.
1682 This is an array of structures. Each structure initializes one pair
1683 of eliminable registers. The "from" register number is given first,
1684 followed by "to". Eliminations of the same "from" register are listed
1685 in order of preference.
1687 There are two registers that can always be eliminated on the i386.
1688 The frame pointer and the arg pointer can be replaced by either the
1689 hard frame pointer or to the stack pointer, depending upon the
1690 circumstances. The hard frame pointer is not used before reload and
1691 so it is not eligible for elimination. */
1693 #define ELIMINABLE_REGS \
1694 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1695 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1696 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1697 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1699 /* Given FROM and TO register numbers, say whether this elimination is
1700 allowed. Frame pointer elimination is automatically handled.
1702 All other eliminations are valid. */
1704 #define CAN_ELIMINATE(FROM, TO) \
1705 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1707 /* Define the offset between two registers, one to be eliminated, and the other
1708 its replacement, at the start of a routine. */
1710 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1711 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1713 /* Addressing modes, and classification of registers for them. */
1715 /* Macros to check register numbers against specific register classes. */
1717 /* These assume that REGNO is a hard or pseudo reg number.
1718 They give nonzero only if REGNO is a hard reg of the suitable class
1719 or a pseudo reg currently allocated to a suitable hard reg.
1720 Since they use reg_renumber, they are safe only once reg_renumber
1721 has been allocated, which happens in local-alloc.c. */
1723 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1724 ((REGNO) < STACK_POINTER_REGNUM \
1725 || REX_INT_REGNO_P (REGNO) \
1726 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1727 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1729 #define REGNO_OK_FOR_BASE_P(REGNO) \
1730 (GENERAL_REGNO_P (REGNO) \
1731 || (REGNO) == ARG_POINTER_REGNUM \
1732 || (REGNO) == FRAME_POINTER_REGNUM \
1733 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1735 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1736 and check its validity for a certain class.
1737 We have two alternate definitions for each of them.
1738 The usual definition accepts all pseudo regs; the other rejects
1739 them unless they have been allocated suitable hard regs.
1740 The symbol REG_OK_STRICT causes the latter definition to be used.
1742 Most source files want to accept pseudo regs in the hope that
1743 they will get allocated to the class that the insn wants them to be in.
1744 Source files for reload pass need to be strict.
1745 After reload, it makes no difference, since pseudo regs have
1746 been eliminated by then. */
1749 /* Non strict versions, pseudos are ok. */
1750 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1751 (REGNO (X) < STACK_POINTER_REGNUM \
1752 || REX_INT_REGNO_P (REGNO (X)) \
1753 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1755 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1756 (GENERAL_REGNO_P (REGNO (X)) \
1757 || REGNO (X) == ARG_POINTER_REGNUM \
1758 || REGNO (X) == FRAME_POINTER_REGNUM \
1759 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1761 /* Strict versions, hard registers only */
1762 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1763 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1765 #ifndef REG_OK_STRICT
1766 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1767 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1770 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1771 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1774 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1775 that is a valid memory address for an instruction.
1776 The MODE argument is the machine mode for the MEM expression
1777 that wants to use this address.
1779 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1780 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1782 See legitimize_pic_address in i386.c for details as to what
1783 constitutes a legitimate address when -fpic is used. */
1785 #define MAX_REGS_PER_ADDRESS 2
1787 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1789 /* Nonzero if the constant value X is a legitimate general operand.
1790 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1792 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1794 #ifdef REG_OK_STRICT
1795 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1797 if (legitimate_address_p ((MODE), (X), 1)) \
1802 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1804 if (legitimate_address_p ((MODE), (X), 0)) \
1810 /* If defined, a C expression to determine the base term of address X.
1811 This macro is used in only one place: `find_base_term' in alias.c.
1813 It is always safe for this macro to not be defined. It exists so
1814 that alias analysis can understand machine-dependent addresses.
1816 The typical use of this macro is to handle addresses containing
1817 a label_ref or symbol_ref within an UNSPEC. */
1819 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1821 /* Try machine-dependent ways of modifying an illegitimate address
1822 to be legitimate. If we find one, return the new, valid address.
1823 This macro is used in only one place: `memory_address' in explow.c.
1825 OLDX is the address as it was before break_out_memory_refs was called.
1826 In some cases it is useful to look at this to decide what needs to be done.
1828 MODE and WIN are passed so that this macro can use
1829 GO_IF_LEGITIMATE_ADDRESS.
1831 It is always safe for this macro to do nothing. It exists to recognize
1832 opportunities to optimize the output.
1834 For the 80386, we handle X+REG by loading X into a register R and
1835 using R+REG. R will go in a general reg and indexing will be used.
1836 However, if REG is a broken-out memory address or multiplication,
1837 nothing needs to be done because REG can certainly go in a general reg.
1839 When -fpic is used, special handling is needed for symbolic references.
1840 See comments by legitimize_pic_address in i386.c for details. */
1842 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1844 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1845 if (memory_address_p ((MODE), (X))) \
1849 /* Nonzero if the constant value X is a legitimate general operand
1850 when generating PIC code. It is given that flag_pic is on and
1851 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1853 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1855 #define SYMBOLIC_CONST(X) \
1856 (GET_CODE (X) == SYMBOL_REF \
1857 || GET_CODE (X) == LABEL_REF \
1858 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1860 /* Go to LABEL if ADDR (a legitimate address expression)
1861 has an effect that depends on the machine mode it is used for.
1862 On the 80386, only postdecrement and postincrement address depend thus
1863 (the amount of decrement or increment being the length of the operand).
1864 These are now caught in recog.c. */
1865 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1867 /* Max number of args passed in registers. If this is more than 3, we will
1868 have problems with ebx (register #4), since it is a caller save register and
1869 is also used as the pic register in ELF. So for now, don't allow more than
1870 3 registers to be passed in registers. */
1872 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1874 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1876 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1879 /* Specify the machine mode that this machine uses
1880 for the index in the tablejump instruction. */
1881 #define CASE_VECTOR_MODE \
1882 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1884 /* Define this as 1 if `char' should by default be signed; else as 0. */
1885 #define DEFAULT_SIGNED_CHAR 1
1887 /* Max number of bytes we can move from memory to memory
1888 in one reasonably fast instruction. */
1891 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1892 move efficiently, as opposed to MOVE_MAX which is the maximum
1893 number of bytes we can move with a single instruction. */
1894 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1896 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1897 move-instruction pairs, we will do a movmem or libcall instead.
1898 Increasing the value will always make code faster, but eventually
1899 incurs high cost in increased code size.
1901 If you don't define this, a reasonable default is used. */
1903 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1905 /* If a clear memory operation would take CLEAR_RATIO or more simple
1906 move-instruction sequences, we will do a clrmem or libcall instead. */
1908 #define CLEAR_RATIO (optimize_size ? 2 \
1909 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1911 /* Define if shifts truncate the shift count
1912 which implies one can omit a sign-extension or zero-extension
1913 of a shift count. */
1914 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1916 /* #define SHIFT_COUNT_TRUNCATED */
1918 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1919 is done just by pretending it is already truncated. */
1920 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1922 /* A macro to update M and UNSIGNEDP when an object whose type is
1923 TYPE and which has the specified mode and signedness is to be
1924 stored in a register. This macro is only called when TYPE is a
1927 On i386 it is sometimes useful to promote HImode and QImode
1928 quantities to SImode. The choice depends on target type. */
1930 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1932 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1933 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1937 /* Specify the machine mode that pointers have.
1938 After generation of rtl, the compiler makes no further distinction
1939 between pointers and any other objects of this machine mode. */
1940 #define Pmode (TARGET_64BIT ? DImode : SImode)
1942 /* A function address in a call instruction
1943 is a byte address (for indexing purposes)
1944 so give the MEM rtx a byte's mode. */
1945 #define FUNCTION_MODE QImode
1947 /* A C expression for the cost of moving data from a register in class FROM to
1948 one in class TO. The classes are expressed using the enumeration values
1949 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1950 interpreted relative to that.
1952 It is not required that the cost always equal 2 when FROM is the same as TO;
1953 on some machines it is expensive to move between registers if they are not
1954 general registers. */
1956 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1957 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1959 /* A C expression for the cost of moving data of mode M between a
1960 register and memory. A value of 2 is the default; this cost is
1961 relative to those in `REGISTER_MOVE_COST'.
1963 If moving between registers and memory is more expensive than
1964 between two registers, you should define this macro to express the
1967 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1968 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1970 /* A C expression for the cost of a branch instruction. A value of 1
1971 is the default; other values are interpreted relative to that. */
1973 #define BRANCH_COST ix86_branch_cost
1975 /* Define this macro as a C expression which is nonzero if accessing
1976 less than a word of memory (i.e. a `char' or a `short') is no
1977 faster than accessing a word of memory, i.e., if such access
1978 require more than one instruction or if there is no difference in
1979 cost between byte and (aligned) word loads.
1981 When this macro is not defined, the compiler will access a field by
1982 finding the smallest containing object; when it is defined, a
1983 fullword load will be used if alignment permits. Unless bytes
1984 accesses are faster than word accesses, using word accesses is
1985 preferable since it may eliminate subsequent memory access if
1986 subsequent accesses occur to other fields in the same word of the
1987 structure, but to different bytes. */
1989 #define SLOW_BYTE_ACCESS 0
1991 /* Nonzero if access to memory by shorts is slow and undesirable. */
1992 #define SLOW_SHORT_ACCESS 0
1994 /* Define this macro to be the value 1 if unaligned accesses have a
1995 cost many times greater than aligned accesses, for example if they
1996 are emulated in a trap handler.
1998 When this macro is nonzero, the compiler will act as if
1999 `STRICT_ALIGNMENT' were nonzero when generating code for block
2000 moves. This can cause significantly more instructions to be
2001 produced. Therefore, do not set this macro nonzero if unaligned
2002 accesses only add a cycle or two to the time for a memory access.
2004 If the value of this macro is always zero, it need not be defined. */
2006 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2008 /* Define this macro if it is as good or better to call a constant
2009 function address than to call an address kept in a register.
2011 Desirable on the 386 because a CALL with a constant address is
2012 faster than one with a register address. */
2014 #define NO_FUNCTION_CSE
2016 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2017 return the mode to be used for the comparison.
2019 For floating-point equality comparisons, CCFPEQmode should be used.
2020 VOIDmode should be used in all other cases.
2022 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2023 possible, to allow for more combinations. */
2025 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2027 /* Return nonzero if MODE implies a floating point inequality can be
2030 #define REVERSIBLE_CC_MODE(MODE) 1
2032 /* A C expression whose value is reversed condition code of the CODE for
2033 comparison done in CC_MODE mode. */
2034 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2037 /* Control the assembler format that we output, to the extent
2038 this does not vary between assemblers. */
2040 /* How to refer to registers in assembler output.
2041 This sequence is indexed by compiler's hard-register-number (see above). */
2043 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2044 For non floating point regs, the following are the HImode names.
2046 For float regs, the stack top is sometimes referred to as "%st(0)"
2047 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2049 #define HI_REGISTER_NAMES \
2050 {"ax","dx","cx","bx","si","di","bp","sp", \
2051 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2052 "argp", "flags", "fpsr", "fpcr", "frame", \
2053 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2054 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2055 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2056 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2058 #define REGISTER_NAMES HI_REGISTER_NAMES
2060 /* Table of additional register names to use in user input. */
2062 #define ADDITIONAL_REGISTER_NAMES \
2063 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2064 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2065 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2066 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2067 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2068 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2070 /* Note we are omitting these since currently I don't know how
2071 to get gcc to use these, since they want the same but different
2072 number as al, and ax.
2075 #define QI_REGISTER_NAMES \
2076 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2078 /* These parallel the array above, and can be used to access bits 8:15
2079 of regs 0 through 3. */
2081 #define QI_HIGH_REGISTER_NAMES \
2082 {"ah", "dh", "ch", "bh", }
2084 /* How to renumber registers for dbx and gdb. */
2086 #define DBX_REGISTER_NUMBER(N) \
2087 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2089 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2090 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2091 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2093 /* Before the prologue, RA is at 0(%esp). */
2094 #define INCOMING_RETURN_ADDR_RTX \
2095 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2097 /* After the prologue, RA is at -4(AP) in the current frame. */
2098 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2100 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2101 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2103 /* PC is dbx register 8; let's use that column for RA. */
2104 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2106 /* Before the prologue, the top of the frame is at 4(%esp). */
2107 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2109 /* Describe how we implement __builtin_eh_return. */
2110 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2111 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2114 /* Select a format to encode pointers in exception handling data. CODE
2115 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2116 true if the symbol may be affected by dynamic relocations.
2118 ??? All x86 object file formats are capable of representing this.
2119 After all, the relocation needed is the same as for the call insn.
2120 Whether or not a particular assembler allows us to enter such, I
2121 guess we'll have to see. */
2122 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2123 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2125 /* This is how to output an insn to push a register on the stack.
2126 It need not be very fast code. */
2128 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2131 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2132 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2134 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2137 /* This is how to output an insn to pop a register from the stack.
2138 It need not be very fast code. */
2140 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2143 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2144 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2146 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2149 /* This is how to output an element of a case-vector that is absolute. */
2151 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2152 ix86_output_addr_vec_elt ((FILE), (VALUE))
2154 /* This is how to output an element of a case-vector that is relative. */
2156 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2157 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2159 /* Under some conditions we need jump tables in the text section,
2160 because the assembler cannot handle label differences between
2161 sections. This is the case for x86_64 on Mach-O for example. */
2163 #define JUMP_TABLES_IN_TEXT_SECTION \
2164 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2165 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2167 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2168 and switch back. For x86 we do this only to save a few bytes that
2169 would otherwise be unused in the text section. */
2170 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2171 asm (SECTION_OP "\n\t" \
2172 "call " USER_LABEL_PREFIX #FUNC "\n" \
2173 TEXT_SECTION_ASM_OP);
2175 /* Print operand X (an rtx) in assembler syntax to file FILE.
2176 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2177 Effect of various CODE letters is described in i386.c near
2178 print_operand function. */
2180 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2181 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2183 #define PRINT_OPERAND(FILE, X, CODE) \
2184 print_operand ((FILE), (X), (CODE))
2186 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2187 print_operand_address ((FILE), (ADDR))
2189 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2191 if (! output_addr_const_extra (FILE, (X))) \
2195 /* Which processor to schedule for. The cpu attribute defines a list that
2196 mirrors this list, so changes to i386.md must be made at the same time. */
2200 PROCESSOR_I386, /* 80386 */
2201 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2203 PROCESSOR_PENTIUMPRO,
2211 PROCESSOR_GENERIC32,
2212 PROCESSOR_GENERIC64,
2217 extern enum processor_type ix86_tune;
2218 extern enum processor_type ix86_arch;
2226 extern enum fpmath_unit ix86_fpmath;
2235 extern enum tls_dialect ix86_tls_dialect;
2238 CM_32, /* The traditional 32-bit ABI. */
2239 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2240 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2241 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2242 CM_LARGE, /* No assumptions. */
2243 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2244 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2245 CM_LARGE_PIC /* No assumptions. */
2248 extern enum cmodel ix86_cmodel;
2250 /* Size of the RED_ZONE area. */
2251 #define RED_ZONE_SIZE 128
2252 /* Reserved area of the red zone for temporaries. */
2253 #define RED_ZONE_RESERVE 8
2260 extern enum asm_dialect ix86_asm_dialect;
2261 extern unsigned int ix86_preferred_stack_boundary;
2262 extern int ix86_branch_cost, ix86_section_threshold;
2264 /* Smallest class containing REGNO. */
2265 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2267 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2268 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2269 extern rtx ix86_compare_emitted;
2271 /* To properly truncate FP values into integers, we need to set i387 control
2272 word. We can't emit proper mode switching code before reload, as spills
2273 generated by reload may truncate values incorrectly, but we still can avoid
2274 redundant computation of new control word by the mode switching pass.
2275 The fldcw instructions are still emitted redundantly, but this is probably
2276 not going to be noticeable problem, as most CPUs do have fast path for
2279 The machinery is to emit simple truncation instructions and split them
2280 before reload to instructions having USEs of two memory locations that
2281 are filled by this code to old and new control word.
2283 Post-reload pass may be later used to eliminate the redundant fildcw if
2295 enum ix86_stack_slot
2303 MAX_386_STACK_LOCALS
2306 /* Define this macro if the port needs extra instructions inserted
2307 for mode switching in an optimizing compilation. */
2309 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2310 ix86_optimize_mode_switching[(ENTITY)]
2312 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2313 initializer for an array of integers. Each initializer element N
2314 refers to an entity that needs mode switching, and specifies the
2315 number of different modes that might need to be set for this
2316 entity. The position of the initializer in the initializer -
2317 starting counting at zero - determines the integer that is used to
2318 refer to the mode-switched entity in question. */
2320 #define NUM_MODES_FOR_MODE_SWITCHING \
2321 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2323 /* ENTITY is an integer specifying a mode-switched entity. If
2324 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2325 return an integer value not larger than the corresponding element
2326 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2327 must be switched into prior to the execution of INSN. */
2329 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2331 /* This macro specifies the order in which modes for ENTITY are
2332 processed. 0 is the highest priority. */
2334 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2336 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2337 is the set of hard registers live at the point where the insn(s)
2338 are to be inserted. */
2340 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2341 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2342 ? emit_i387_cw_initialization (MODE), 0 \
2346 /* Avoid renaming of stack registers, as doing so in combination with
2347 scheduling just increases amount of live registers at time and in
2348 the turn amount of fxch instructions needed.
2350 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2352 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2353 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2356 #define FASTCALL_PREFIX '@'
2358 struct machine_function GTY(())
2360 struct stack_local_entry *stack_locals;
2361 const char *some_ld_name;
2362 rtx force_align_arg_pointer;
2363 int save_varrargs_registers;
2364 int accesses_prev_frame;
2365 int optimize_mode_switching[MAX_386_ENTITIES];
2366 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2367 determine the style used. */
2368 int use_fast_prologue_epilogue;
2369 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2371 int use_fast_prologue_epilogue_nregs;
2372 /* If true, the current function needs the default PIC register, not
2373 an alternate register (on x86) and must not use the red zone (on
2374 x86_64), even if it's a leaf function. We don't want the
2375 function to be regarded as non-leaf because TLS calls need not
2376 affect register allocation. This flag is set when a TLS call
2377 instruction is expanded within a function, and never reset, even
2378 if all such instructions are optimized away. Use the
2379 ix86_current_function_calls_tls_descriptor macro for a better
2381 int tls_descriptor_call_expanded_p;
2384 #define ix86_stack_locals (cfun->machine->stack_locals)
2385 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2386 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2387 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2388 (cfun->machine->tls_descriptor_call_expanded_p)
2389 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2390 calls are optimized away, we try to detect cases in which it was
2391 optimized away. Since such instructions (use (reg REG_SP)), we can
2392 verify whether there's any such instruction live by testing that
2394 #define ix86_current_function_calls_tls_descriptor \
2395 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2397 /* Control behavior of x86_file_start. */
2398 #define X86_FILE_START_VERSION_DIRECTIVE false
2399 #define X86_FILE_START_FLTUSED false
2401 /* Flag to mark data that is in the large address area. */
2402 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2403 #define SYMBOL_REF_FAR_ADDR_P(X) \
2404 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2406 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2407 have defined always, to avoid ifdefing. */
2408 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2409 #define SYMBOL_REF_DLLIMPORT_P(X) \
2410 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2412 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2413 #define SYMBOL_REF_DLLEXPORT_P(X) \
2414 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
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