1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Macros used in the machine description to test the flags. */
93 /* configure can arrange to make this 2, to force a 486. */
95 #ifndef TARGET_CPU_DEFAULT
96 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
99 #ifndef TARGET_FPMATH_DEFAULT
100 #define TARGET_FPMATH_DEFAULT \
101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
104 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
106 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
107 compile-time constant. */
111 #define TARGET_64BIT 1
113 #define TARGET_64BIT 0
116 #ifndef TARGET_BI_ARCH
118 #if TARGET_64BIT_DEFAULT
119 #define TARGET_64BIT 1
121 #define TARGET_64BIT 0
126 #define HAS_LONG_COND_BRANCH 1
127 #define HAS_LONG_UNCOND_BRANCH 1
129 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
130 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
131 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
132 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
133 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
134 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
135 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
136 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
137 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
138 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
139 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
140 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
141 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
142 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
144 #define TUNEMASK (1 << ix86_tune)
145 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
146 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
147 extern const int x86_branch_hints, x86_unroll_strlen;
148 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
149 extern const int x86_use_himode_fiop, x86_use_simode_fiop;
150 extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
151 extern const int x86_read_modify, x86_split_long_moves;
152 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
153 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
154 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
155 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
156 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
157 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
158 extern const int x86_epilogue_using_move, x86_decompose_lea;
159 extern const int x86_arch_always_fancy_math_387, x86_shift1;
160 extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
161 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
162 extern const int x86_use_ffreep;
163 extern const int x86_inter_unit_moves, x86_schedule;
164 extern const int x86_use_bt;
165 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
166 extern const int x86_use_incdec;
167 extern const int x86_pad_returns;
168 extern const int x86_bswap;
169 extern const int x86_partial_flag_reg_stall;
170 extern int x86_prefetch_sse;
172 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
173 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
174 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
175 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
176 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
177 /* For sane SSE instruction set generation we need fcomi instruction. It is
178 safe to enable all CMOVE instructions. */
179 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
180 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
181 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
182 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
183 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
184 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
185 #define TARGET_MOVX (x86_movx & TUNEMASK)
186 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
187 #define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
188 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
189 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
190 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
191 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
192 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
193 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
194 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
195 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
196 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
197 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
198 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
199 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
200 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
201 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
202 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
203 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
204 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
205 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
206 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
207 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
208 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
209 (x86_sse_partial_reg_dependency & TUNEMASK)
210 #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
211 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
212 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
213 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
214 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
215 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
216 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
217 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
218 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
219 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
220 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
221 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
222 #define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
223 #define TARGET_USE_BT (x86_use_bt & TUNEMASK)
224 #define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
225 #define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
227 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
229 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
230 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
231 && (ix86_fpmath & FPMATH_387))
233 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
234 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
235 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
236 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
238 #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
239 #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
240 #define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch))
241 #define TARGET_XADD (x86_xadd & (1 << ix86_arch))
242 #define TARGET_BSWAP (x86_bswap & (1 << ix86_arch))
244 #ifndef TARGET_64BIT_DEFAULT
245 #define TARGET_64BIT_DEFAULT 0
247 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
248 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
251 /* Once GDB has been enhanced to deal with functions without frame
252 pointers, we can change this to allow for elimination of
253 the frame pointer in leaf functions. */
254 #define TARGET_DEFAULT 0
256 /* This is not really a target flag, but is done this way so that
257 it's analogous to similar code for Mach-O on PowerPC. darwin.h
258 redefines this to 1. */
259 #define TARGET_MACHO 0
261 /* Subtargets may reset this to 1 in order to enable 96-bit long double
262 with the rounding mode forced to 53 bits. */
263 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
265 /* Sometimes certain combinations of command options do not make
266 sense on a particular target machine. You can define a macro
267 `OVERRIDE_OPTIONS' to take account of this. This macro, if
268 defined, is executed once just after all the command options have
271 Don't use this macro to turn on various extra optimizations for
272 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
274 #define OVERRIDE_OPTIONS override_options ()
276 /* Define this to change the optimizations performed by default. */
277 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
278 optimization_options ((LEVEL), (SIZE))
280 /* -march=native handling only makes sense with compiler running on
281 an x86 or x86_64 chip. If changing this condition, also change
282 the condition in driver-i386.c. */
283 #if defined(__i386__) || defined(__x86_64__)
284 /* In driver-i386.c. */
285 extern const char *host_detect_local_cpu (int argc, const char **argv);
286 #define EXTRA_SPEC_FUNCTIONS \
287 { "local_cpu_detect", host_detect_local_cpu },
288 #define HAVE_LOCAL_CPU_DETECT
291 /* Support for configure-time defaults of some command line options.
292 The order here is important so that -march doesn't squash the
293 tune or cpu values. */
294 #define OPTION_DEFAULT_SPECS \
295 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
296 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
297 {"arch", "%{!march=*:-march=%(VALUE)}"}
299 /* Specs for the compiler proper */
302 #define CC1_CPU_SPEC_1 "\
305 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
307 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
308 %{mpentium:-mtune=pentium \
309 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
310 %{mpentiumpro:-mtune=pentiumpro \
311 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
313 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
315 %{mintel-syntax:-masm=intel \
316 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
317 %{mno-intel-syntax:-masm=att \
318 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
320 #ifndef HAVE_LOCAL_CPU_DETECT
321 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
323 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
324 "%{march=native:%<march=native %:local_cpu_detect(arch)} \
325 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
329 /* Target CPU builtins. */
330 #define TARGET_CPU_CPP_BUILTINS() \
333 size_t arch_len = strlen (ix86_arch_string); \
334 size_t tune_len = strlen (ix86_tune_string); \
335 int last_arch_char = ix86_arch_string[arch_len - 1]; \
336 int last_tune_char = ix86_tune_string[tune_len - 1]; \
340 builtin_assert ("cpu=x86_64"); \
341 builtin_assert ("machine=x86_64"); \
342 builtin_define ("__amd64"); \
343 builtin_define ("__amd64__"); \
344 builtin_define ("__x86_64"); \
345 builtin_define ("__x86_64__"); \
349 builtin_assert ("cpu=i386"); \
350 builtin_assert ("machine=i386"); \
351 builtin_define_std ("i386"); \
354 /* Built-ins based on -mtune= (or -march= if no \
357 builtin_define ("__tune_i386__"); \
358 else if (TARGET_486) \
359 builtin_define ("__tune_i486__"); \
360 else if (TARGET_PENTIUM) \
362 builtin_define ("__tune_i586__"); \
363 builtin_define ("__tune_pentium__"); \
364 if (last_tune_char == 'x') \
365 builtin_define ("__tune_pentium_mmx__"); \
367 else if (TARGET_PENTIUMPRO) \
369 builtin_define ("__tune_i686__"); \
370 builtin_define ("__tune_pentiumpro__"); \
371 switch (last_tune_char) \
374 builtin_define ("__tune_pentium3__"); \
377 builtin_define ("__tune_pentium2__"); \
381 else if (TARGET_GEODE) \
383 builtin_define ("__tune_geode__"); \
385 else if (TARGET_K6) \
387 builtin_define ("__tune_k6__"); \
388 if (last_tune_char == '2') \
389 builtin_define ("__tune_k6_2__"); \
390 else if (last_tune_char == '3') \
391 builtin_define ("__tune_k6_3__"); \
393 else if (TARGET_ATHLON) \
395 builtin_define ("__tune_athlon__"); \
396 /* Only plain "athlon" lacks SSE. */ \
397 if (last_tune_char != 'n') \
398 builtin_define ("__tune_athlon_sse__"); \
400 else if (TARGET_K8) \
401 builtin_define ("__tune_k8__"); \
402 else if (TARGET_PENTIUM4) \
403 builtin_define ("__tune_pentium4__"); \
404 else if (TARGET_NOCONA) \
405 builtin_define ("__tune_nocona__"); \
408 builtin_define ("__MMX__"); \
410 builtin_define ("__3dNOW__"); \
411 if (TARGET_3DNOW_A) \
412 builtin_define ("__3dNOW_A__"); \
414 builtin_define ("__SSE__"); \
416 builtin_define ("__SSE2__"); \
418 builtin_define ("__SSE3__"); \
420 builtin_define ("__SSSE3__"); \
421 if (TARGET_SSE_MATH && TARGET_SSE) \
422 builtin_define ("__SSE_MATH__"); \
423 if (TARGET_SSE_MATH && TARGET_SSE2) \
424 builtin_define ("__SSE2_MATH__"); \
426 /* Built-ins based on -march=. */ \
427 if (ix86_arch == PROCESSOR_I486) \
429 builtin_define ("__i486"); \
430 builtin_define ("__i486__"); \
432 else if (ix86_arch == PROCESSOR_PENTIUM) \
434 builtin_define ("__i586"); \
435 builtin_define ("__i586__"); \
436 builtin_define ("__pentium"); \
437 builtin_define ("__pentium__"); \
438 if (last_arch_char == 'x') \
439 builtin_define ("__pentium_mmx__"); \
441 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
443 builtin_define ("__i686"); \
444 builtin_define ("__i686__"); \
445 builtin_define ("__pentiumpro"); \
446 builtin_define ("__pentiumpro__"); \
448 else if (ix86_arch == PROCESSOR_GEODE) \
450 builtin_define ("__geode"); \
451 builtin_define ("__geode__"); \
453 else if (ix86_arch == PROCESSOR_K6) \
456 builtin_define ("__k6"); \
457 builtin_define ("__k6__"); \
458 if (last_arch_char == '2') \
459 builtin_define ("__k6_2__"); \
460 else if (last_arch_char == '3') \
461 builtin_define ("__k6_3__"); \
463 else if (ix86_arch == PROCESSOR_ATHLON) \
465 builtin_define ("__athlon"); \
466 builtin_define ("__athlon__"); \
467 /* Only plain "athlon" lacks SSE. */ \
468 if (last_arch_char != 'n') \
469 builtin_define ("__athlon_sse__"); \
471 else if (ix86_arch == PROCESSOR_K8) \
473 builtin_define ("__k8"); \
474 builtin_define ("__k8__"); \
476 else if (ix86_arch == PROCESSOR_PENTIUM4) \
478 builtin_define ("__pentium4"); \
479 builtin_define ("__pentium4__"); \
481 else if (ix86_arch == PROCESSOR_NOCONA) \
483 builtin_define ("__nocona"); \
484 builtin_define ("__nocona__"); \
489 #define TARGET_CPU_DEFAULT_i386 0
490 #define TARGET_CPU_DEFAULT_i486 1
491 #define TARGET_CPU_DEFAULT_pentium 2
492 #define TARGET_CPU_DEFAULT_pentium_mmx 3
493 #define TARGET_CPU_DEFAULT_pentiumpro 4
494 #define TARGET_CPU_DEFAULT_pentium2 5
495 #define TARGET_CPU_DEFAULT_pentium3 6
496 #define TARGET_CPU_DEFAULT_pentium4 7
497 #define TARGET_CPU_DEFAULT_geode 8
498 #define TARGET_CPU_DEFAULT_k6 9
499 #define TARGET_CPU_DEFAULT_k6_2 10
500 #define TARGET_CPU_DEFAULT_k6_3 11
501 #define TARGET_CPU_DEFAULT_athlon 12
502 #define TARGET_CPU_DEFAULT_athlon_sse 13
503 #define TARGET_CPU_DEFAULT_k8 14
504 #define TARGET_CPU_DEFAULT_pentium_m 15
505 #define TARGET_CPU_DEFAULT_prescott 16
506 #define TARGET_CPU_DEFAULT_nocona 17
507 #define TARGET_CPU_DEFAULT_generic 18
509 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
510 "pentiumpro", "pentium2", "pentium3", \
511 "pentium4", "geode", "k6", "k6-2", "k6-3", \
512 "athlon", "athlon-4", "k8", \
513 "pentium-m", "prescott", "nocona", \
517 #define CC1_SPEC "%(cc1_cpu) "
520 /* This macro defines names of additional specifications to put in the
521 specs that can be used in various specifications like CC1_SPEC. Its
522 definition is an initializer with a subgrouping for each command option.
524 Each subgrouping contains a string constant, that defines the
525 specification name, and a string constant that used by the GCC driver
528 Do not define this macro if it does not need to do anything. */
530 #ifndef SUBTARGET_EXTRA_SPECS
531 #define SUBTARGET_EXTRA_SPECS
534 #define EXTRA_SPECS \
535 { "cc1_cpu", CC1_CPU_SPEC }, \
536 SUBTARGET_EXTRA_SPECS
538 /* target machine storage layout */
540 #define LONG_DOUBLE_TYPE_SIZE 80
542 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
543 FPU, assume that the fpcw is set to extended precision; when using
544 only SSE, rounding is correct; when using both SSE and the FPU,
545 the rounding precision is indeterminate, since either may be chosen
546 apparently at random. */
547 #define TARGET_FLT_EVAL_METHOD \
548 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
550 #define SHORT_TYPE_SIZE 16
551 #define INT_TYPE_SIZE 32
552 #define FLOAT_TYPE_SIZE 32
553 #define LONG_TYPE_SIZE BITS_PER_WORD
554 #define DOUBLE_TYPE_SIZE 64
555 #define LONG_LONG_TYPE_SIZE 64
557 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
558 #define MAX_BITS_PER_WORD 64
560 #define MAX_BITS_PER_WORD 32
563 /* Define this if most significant byte of a word is the lowest numbered. */
564 /* That is true on the 80386. */
566 #define BITS_BIG_ENDIAN 0
568 /* Define this if most significant byte of a word is the lowest numbered. */
569 /* That is not true on the 80386. */
570 #define BYTES_BIG_ENDIAN 0
572 /* Define this if most significant word of a multiword number is the lowest
574 /* Not true for 80386 */
575 #define WORDS_BIG_ENDIAN 0
577 /* Width of a word, in units (bytes). */
578 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
580 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
582 #define MIN_UNITS_PER_WORD 4
585 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
586 #define PARM_BOUNDARY BITS_PER_WORD
588 /* Boundary (in *bits*) on which stack pointer should be aligned. */
589 #define STACK_BOUNDARY BITS_PER_WORD
591 /* Boundary (in *bits*) on which the stack pointer prefers to be
592 aligned; the compiler cannot rely on having this alignment. */
593 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
595 /* As of July 2001, many runtimes do not align the stack properly when
596 entering main. This causes expand_main_function to forcibly align
597 the stack, which results in aligned frames for functions called from
598 main, though it does nothing for the alignment of main itself. */
599 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
600 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
602 /* Minimum allocation boundary for the code of a function. */
603 #define FUNCTION_BOUNDARY 8
605 /* C++ stores the virtual bit in the lowest bit of function pointers. */
606 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
608 /* Alignment of field after `int : 0' in a structure. */
610 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
612 /* Minimum size in bits of the largest boundary to which any
613 and all fundamental data types supported by the hardware
614 might need to be aligned. No data type wants to be aligned
617 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
618 and Pentium Pro XFmode values at 128 bit boundaries. */
620 #define BIGGEST_ALIGNMENT 128
622 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
623 #define ALIGN_MODE_128(MODE) \
624 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
626 /* The published ABIs say that doubles should be aligned on word
627 boundaries, so lower the alignment for structure fields unless
628 -malign-double is set. */
630 /* ??? Blah -- this macro is used directly by libobjc. Since it
631 supports no vector modes, cut out the complexity and fall back
632 on BIGGEST_FIELD_ALIGNMENT. */
633 #ifdef IN_TARGET_LIBS
635 #define BIGGEST_FIELD_ALIGNMENT 128
637 #define BIGGEST_FIELD_ALIGNMENT 32
640 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
641 x86_field_alignment (FIELD, COMPUTED)
644 /* If defined, a C expression to compute the alignment given to a
645 constant that is being placed in memory. EXP is the constant
646 and ALIGN is the alignment that the object would ordinarily have.
647 The value of this macro is used instead of that alignment to align
650 If this macro is not defined, then ALIGN is used.
652 The typical use of this macro is to increase alignment for string
653 constants to be word aligned so that `strcpy' calls that copy
654 constants can be done inline. */
656 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
658 /* If defined, a C expression to compute the alignment for a static
659 variable. TYPE is the data type, and ALIGN is the alignment that
660 the object would ordinarily have. The value of this macro is used
661 instead of that alignment to align the object.
663 If this macro is not defined, then ALIGN is used.
665 One use of this macro is to increase alignment of medium-size
666 data to make it all fit in fewer cache lines. Another is to
667 cause character arrays to be word-aligned so that `strcpy' calls
668 that copy constants to character arrays can be done inline. */
670 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
672 /* If defined, a C expression to compute the alignment for a local
673 variable. TYPE is the data type, and ALIGN is the alignment that
674 the object would ordinarily have. The value of this macro is used
675 instead of that alignment to align the object.
677 If this macro is not defined, then ALIGN is used.
679 One use of this macro is to increase alignment of medium-size
680 data to make it all fit in fewer cache lines. */
682 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
684 /* If defined, a C expression that gives the alignment boundary, in
685 bits, of an argument with the specified mode and type. If it is
686 not defined, `PARM_BOUNDARY' is used for all arguments. */
688 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
689 ix86_function_arg_boundary ((MODE), (TYPE))
691 /* Set this nonzero if move instructions will actually fail to work
692 when given unaligned data. */
693 #define STRICT_ALIGNMENT 0
695 /* If bit field type is int, don't let it cross an int,
696 and give entire struct the alignment of an int. */
697 /* Required on the 386 since it doesn't have bit-field insns. */
698 #define PCC_BITFIELD_TYPE_MATTERS 1
700 /* Standard register usage. */
702 /* This processor has special stack-like registers. See reg-stack.c
706 #define IS_STACK_MODE(MODE) \
707 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
708 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
711 /* Number of actual hardware registers.
712 The hardware registers are assigned numbers for the compiler
713 from 0 to just below FIRST_PSEUDO_REGISTER.
714 All registers that the compiler knows about must be given numbers,
715 even those that are not normally considered general registers.
717 In the 80386 we give the 8 general purpose registers the numbers 0-7.
718 We number the floating point registers 8-15.
719 Note that registers 0-7 can be accessed as a short or int,
720 while only 0-3 may be used with byte `mov' instructions.
722 Reg 16 does not correspond to any hardware register, but instead
723 appears in the RTL as an argument pointer prior to reload, and is
724 eliminated during reloading in favor of either the stack or frame
727 #define FIRST_PSEUDO_REGISTER 54
729 /* Number of hardware registers that go into the DWARF-2 unwind info.
730 If not defined, equals FIRST_PSEUDO_REGISTER. */
732 #define DWARF_FRAME_REGISTERS 17
734 /* 1 for registers that have pervasive standard uses
735 and are not available for the register allocator.
736 On the 80386, the stack pointer is such, as is the arg pointer.
738 The value is zero if the register is not fixed on either 32 or
739 64 bit targets, one if the register if fixed on both 32 and 64
740 bit targets, two if it is only fixed on 32bit targets and three
741 if its only fixed on 64bit targets.
742 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
744 #define FIXED_REGISTERS \
745 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
746 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
747 /*arg,flags,fpsr,fpcr,dir,frame*/ \
749 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
750 0, 0, 0, 0, 0, 0, 0, 0, \
751 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
752 0, 0, 0, 0, 0, 0, 0, 0, \
753 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
754 2, 2, 2, 2, 2, 2, 2, 2, \
755 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
756 2, 2, 2, 2, 2, 2, 2, 2}
759 /* 1 for registers not available across function calls.
760 These must include the FIXED_REGISTERS and also any
761 registers that can be used without being saved.
762 The latter must include the registers where values are returned
763 and the register where structure-value addresses are passed.
764 Aside from that, you can include as many other registers as you like.
766 The value is zero if the register is not call used on either 32 or
767 64 bit targets, one if the register if call used on both 32 and 64
768 bit targets, two if it is only call used on 32bit targets and three
769 if its only call used on 64bit targets.
770 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
772 #define CALL_USED_REGISTERS \
773 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
774 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
775 /*arg,flags,fpsr,fpcr,dir,frame*/ \
777 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
778 1, 1, 1, 1, 1, 1, 1, 1, \
779 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
780 1, 1, 1, 1, 1, 1, 1, 1, \
781 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
782 1, 1, 1, 1, 2, 2, 2, 2, \
783 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
784 1, 1, 1, 1, 1, 1, 1, 1} \
786 /* Order in which to allocate registers. Each register must be
787 listed once, even those in FIXED_REGISTERS. List frame pointer
788 late and fixed registers last. Note that, in general, we prefer
789 registers listed in CALL_USED_REGISTERS, keeping the others
790 available for storage of persistent values.
792 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
793 so this is just empty initializer for array. */
795 #define REG_ALLOC_ORDER \
796 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
797 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
798 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
799 48, 49, 50, 51, 52, 53 }
801 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
802 to be rearranged based on a particular function. When using sse math,
803 we want to allocate SSE before x87 registers and vice versa. */
805 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
808 /* Macro to conditionally modify fixed_regs/call_used_regs. */
809 #define CONDITIONAL_REGISTER_USAGE \
812 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
814 if (fixed_regs[i] > 1) \
815 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
816 if (call_used_regs[i] > 1) \
817 call_used_regs[i] = (call_used_regs[i] \
818 == (TARGET_64BIT ? 3 : 2)); \
820 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
822 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
823 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
828 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
829 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
830 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
835 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
836 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
837 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
839 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
843 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
844 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
845 if (TEST_HARD_REG_BIT (x, i)) \
846 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
848 if (! TARGET_64BIT) \
851 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
853 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
858 /* Return number of consecutive hard regs needed starting at reg REGNO
859 to hold something of mode MODE.
860 This is ordinarily the length in words of a value of mode MODE
861 but can be less for certain modes in special long registers.
863 Actually there are no two word move instructions for consecutive
864 registers. And only registers 0-3 may have mov byte instructions
868 #define HARD_REGNO_NREGS(REGNO, MODE) \
869 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
870 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
871 : ((MODE) == XFmode \
872 ? (TARGET_64BIT ? 2 : 3) \
874 ? (TARGET_64BIT ? 4 : 6) \
875 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
877 #define VALID_SSE2_REG_MODE(MODE) \
878 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
879 || (MODE) == V2DImode || (MODE) == DFmode)
881 #define VALID_SSE_REG_MODE(MODE) \
882 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
883 || (MODE) == SFmode || (MODE) == TFmode)
885 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
886 ((MODE) == V2SFmode || (MODE) == SFmode)
888 #define VALID_MMX_REG_MODE(MODE) \
889 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
890 || (MODE) == V2SImode || (MODE) == SImode)
892 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
893 place emms and femms instructions. */
894 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
896 #define VALID_FP_MODE_P(MODE) \
897 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
898 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
900 #define VALID_INT_MODE_P(MODE) \
901 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
902 || (MODE) == DImode \
903 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
904 || (MODE) == CDImode \
905 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
906 || (MODE) == TFmode || (MODE) == TCmode)))
908 /* Return true for modes passed in SSE registers. */
909 #define SSE_REG_MODE_P(MODE) \
910 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
911 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
912 || (MODE) == V4SFmode || (MODE) == V4SImode)
914 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
916 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
917 ix86_hard_regno_mode_ok ((REGNO), (MODE))
919 /* Value is 1 if it is a good idea to tie two pseudo registers
920 when one has mode MODE1 and one has mode MODE2.
921 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
922 for any hard reg, then this must be 0 for correct output. */
924 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
926 /* It is possible to write patterns to move flags; but until someone
928 #define AVOID_CCMODE_COPIES
930 /* Specify the modes required to caller save a given hard regno.
931 We do this on i386 to prevent flags from being saved at all.
933 Kill any attempts to combine saving of modes. */
935 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
936 (CC_REGNO_P (REGNO) ? VOIDmode \
937 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
938 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
939 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
940 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
942 /* Specify the registers used for certain standard purposes.
943 The values of these macros are register numbers. */
945 /* on the 386 the pc register is %eip, and is not usable as a general
946 register. The ordinary mov instructions won't work */
947 /* #define PC_REGNUM */
949 /* Register to use for pushing function arguments. */
950 #define STACK_POINTER_REGNUM 7
952 /* Base register for access to local variables of the function. */
953 #define HARD_FRAME_POINTER_REGNUM 6
955 /* Base register for access to local variables of the function. */
956 #define FRAME_POINTER_REGNUM 21
958 /* First floating point reg */
959 #define FIRST_FLOAT_REG 8
961 /* First & last stack-like regs */
962 #define FIRST_STACK_REG FIRST_FLOAT_REG
963 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
965 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
966 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
968 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
969 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
971 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
972 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
974 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
975 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
977 /* Value should be nonzero if functions must have frame pointers.
978 Zero means the frame pointer need not be set up (and parms
979 may be accessed via the stack pointer) in functions that seem suitable.
980 This is computed in `reload', in reload1.c. */
981 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
983 /* Override this in other tm.h files to cope with various OS lossage
984 requiring a frame pointer. */
985 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
986 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
989 /* Make sure we can access arbitrary call frames. */
990 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
992 /* Base register for access to arguments of the function. */
993 #define ARG_POINTER_REGNUM 16
995 /* Register in which static-chain is passed to a function.
996 We do use ECX as static chain register for 32 bit ABI. On the
997 64bit ABI, ECX is an argument register, so we use R10 instead. */
998 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1000 /* Register to hold the addressing base for position independent
1001 code access to data items. We don't use PIC pointer for 64bit
1002 mode. Define the regnum to dummy value to prevent gcc from
1003 pessimizing code dealing with EBX.
1005 To avoid clobbering a call-saved register unnecessarily, we renumber
1006 the pic register when possible. The change is visible after the
1007 prologue has been emitted. */
1009 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1011 #define PIC_OFFSET_TABLE_REGNUM \
1012 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1013 || !flag_pic ? INVALID_REGNUM \
1014 : reload_completed ? REGNO (pic_offset_table_rtx) \
1015 : REAL_PIC_OFFSET_TABLE_REGNUM)
1017 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1019 /* A C expression which can inhibit the returning of certain function
1020 values in registers, based on the type of value. A nonzero value
1021 says to return the function value in memory, just as large
1022 structures are always returned. Here TYPE will be a C expression
1023 of type `tree', representing the data type of the value.
1025 Note that values of mode `BLKmode' must be explicitly handled by
1026 this macro. Also, the option `-fpcc-struct-return' takes effect
1027 regardless of this macro. On most systems, it is possible to
1028 leave the macro undefined; this causes a default definition to be
1029 used, whose value is the constant 1 for `BLKmode' values, and 0
1032 Do not use this macro to indicate that structures and unions
1033 should always be returned in memory. You should instead use
1034 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1036 #define RETURN_IN_MEMORY(TYPE) \
1037 ix86_return_in_memory (TYPE)
1039 /* This is overridden by <cygwin.h>. */
1040 #define MS_AGGREGATE_RETURN 0
1042 /* This is overridden by <netware.h>. */
1043 #define KEEP_AGGREGATE_RETURN_POINTER 0
1045 /* Define the classes of registers for register constraints in the
1046 machine description. Also define ranges of constants.
1048 One of the classes must always be named ALL_REGS and include all hard regs.
1049 If there is more than one class, another class must be named NO_REGS
1050 and contain no registers.
1052 The name GENERAL_REGS must be the name of a class (or an alias for
1053 another name such as ALL_REGS). This is the class of registers
1054 that is allowed by "g" or "r" in a register constraint.
1055 Also, registers outside this class are allocated only when
1056 instructions express preferences for them.
1058 The classes must be numbered in nondecreasing order; that is,
1059 a larger-numbered class must never be contained completely
1060 in a smaller-numbered class.
1062 For any two classes, it is very desirable that there be another
1063 class that represents their union.
1065 It might seem that class BREG is unnecessary, since no useful 386
1066 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1067 and the "b" register constraint is useful in asms for syscalls.
1069 The flags, fpsr and fpcr registers are in no class. */
1074 AREG, DREG, CREG, BREG, SIREG, DIREG,
1075 AD_REGS, /* %eax/%edx for DImode */
1076 Q_REGS, /* %eax %ebx %ecx %edx */
1077 NON_Q_REGS, /* %esi %edi %ebp %esp */
1078 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1079 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1080 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1081 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1091 ALL_REGS, LIM_REG_CLASSES
1094 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1096 #define INTEGER_CLASS_P(CLASS) \
1097 reg_class_subset_p ((CLASS), GENERAL_REGS)
1098 #define FLOAT_CLASS_P(CLASS) \
1099 reg_class_subset_p ((CLASS), FLOAT_REGS)
1100 #define SSE_CLASS_P(CLASS) \
1101 ((CLASS) == SSE_REGS)
1102 #define MMX_CLASS_P(CLASS) \
1103 ((CLASS) == MMX_REGS)
1104 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1105 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1106 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1107 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1108 #define MAYBE_SSE_CLASS_P(CLASS) \
1109 reg_classes_intersect_p (SSE_REGS, (CLASS))
1110 #define MAYBE_MMX_CLASS_P(CLASS) \
1111 reg_classes_intersect_p (MMX_REGS, (CLASS))
1113 #define Q_CLASS_P(CLASS) \
1114 reg_class_subset_p ((CLASS), Q_REGS)
1116 /* Give names of register classes as strings for dump file. */
1118 #define REG_CLASS_NAMES \
1120 "AREG", "DREG", "CREG", "BREG", \
1123 "Q_REGS", "NON_Q_REGS", \
1127 "FP_TOP_REG", "FP_SECOND_REG", \
1131 "FP_TOP_SSE_REGS", \
1132 "FP_SECOND_SSE_REGS", \
1136 "FLOAT_INT_SSE_REGS", \
1139 /* Define which registers fit in which classes.
1140 This is an initializer for a vector of HARD_REG_SET
1141 of length N_REG_CLASSES. */
1143 #define REG_CLASS_CONTENTS \
1145 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1146 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1147 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1148 { 0x03, 0x0 }, /* AD_REGS */ \
1149 { 0x0f, 0x0 }, /* Q_REGS */ \
1150 { 0x2100f0, 0x3fc0 }, /* NON_Q_REGS */ \
1151 { 0x7f, 0x3fc0 }, /* INDEX_REGS */ \
1152 { 0x2100ff, 0x0 }, /* LEGACY_REGS */ \
1153 { 0x2100ff, 0x3fc0 }, /* GENERAL_REGS */ \
1154 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1155 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1156 { 0x3fc00000,0x3fc000 }, /* SSE_REGS */ \
1157 { 0xc0000000, 0x3f }, /* MMX_REGS */ \
1158 { 0x3fc00100,0x3fc000 }, /* FP_TOP_SSE_REG */ \
1159 { 0x3fc00200,0x3fc000 }, /* FP_SECOND_SSE_REG */ \
1160 { 0x3fc0ff00,0x3fc000 }, /* FLOAT_SSE_REGS */ \
1161 { 0x1ffff, 0x3fc0 }, /* FLOAT_INT_REGS */ \
1162 { 0x3fc100ff,0x3fffc0 }, /* INT_SSE_REGS */ \
1163 { 0x3fc1ffff,0x3fffc0 }, /* FLOAT_INT_SSE_REGS */ \
1164 { 0xffffffff,0x3fffff } \
1167 /* The same information, inverted:
1168 Return the class number of the smallest class containing
1169 reg number REGNO. This could be a conditional expression
1170 or could index an array. */
1172 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1174 /* When defined, the compiler allows registers explicitly used in the
1175 rtl to be used as spill registers but prevents the compiler from
1176 extending the lifetime of these registers. */
1178 #define SMALL_REGISTER_CLASSES 1
1180 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1182 #define GENERAL_REGNO_P(N) \
1183 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1185 #define GENERAL_REG_P(X) \
1186 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1188 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1190 #define NON_QI_REG_P(X) \
1191 (REG_P (X) && IN_RANGE (REGNO (X), 4, FIRST_PSEUDO_REGISTER - 1))
1193 #define REX_INT_REGNO_P(N) \
1194 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1195 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1197 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1198 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1199 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1200 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1202 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1203 #define SSE_REGNO_P(N) \
1204 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1205 || REX_SSE_REGNO_P (N))
1207 #define REX_SSE_REGNO_P(N) \
1208 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1210 #define SSE_REGNO(N) \
1211 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1213 #define SSE_FLOAT_MODE_P(MODE) \
1214 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1216 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1217 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1219 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1220 #define NON_STACK_REG_P(XOP) \
1221 (REG_P (XOP) && ! STACK_REGNO_P (REGNO (XOP)))
1222 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1224 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1226 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1227 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1229 /* The class value for index registers, and the one for base regs. */
1231 #define INDEX_REG_CLASS INDEX_REGS
1232 #define BASE_REG_CLASS GENERAL_REGS
1234 /* Place additional restrictions on the register class to use when it
1235 is necessary to be able to hold a value of mode MODE in a reload
1236 register for which class CLASS would ordinarily be used. */
1238 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1239 ((MODE) == QImode && !TARGET_64BIT \
1240 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1241 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1244 /* Given an rtx X being reloaded into a reg required to be
1245 in class CLASS, return the class of reg to actually use.
1246 In general this is just CLASS; but on some machines
1247 in some cases it is preferable to use a more restrictive class.
1248 On the 80386 series, we prevent floating constants from being
1249 reloaded into floating registers (since no move-insn can do that)
1250 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1252 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1253 QImode must go into class Q_REGS.
1254 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1255 movdf to do mem-to-mem moves through integer regs. */
1257 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1258 ix86_preferred_reload_class ((X), (CLASS))
1260 /* Discourage putting floating-point values in SSE registers unless
1261 SSE math is being used, and likewise for the 387 registers. */
1263 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1264 ix86_preferred_output_reload_class ((X), (CLASS))
1266 /* If we are copying between general and FP registers, we need a memory
1267 location. The same is true for SSE and MMX registers. */
1268 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1269 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1271 /* QImode spills from non-QI registers need a scratch. This does not
1272 happen often -- the only example so far requires an uninitialized
1275 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1276 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1277 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1280 /* Return the maximum number of consecutive registers
1281 needed to represent mode MODE in a register of class CLASS. */
1282 /* On the 80386, this is the size of MODE in words,
1283 except in the FP regs, where a single reg is always enough. */
1284 #define CLASS_MAX_NREGS(CLASS, MODE) \
1285 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1286 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1287 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1288 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1290 /* A C expression whose value is nonzero if pseudos that have been
1291 assigned to registers of class CLASS would likely be spilled
1292 because registers of CLASS are needed for spill registers.
1294 The default value of this macro returns 1 if CLASS has exactly one
1295 register and zero otherwise. On most machines, this default
1296 should be used. Only define this macro to some other expression
1297 if pseudo allocated by `local-alloc.c' end up in memory because
1298 their hard registers were needed for spill registers. If this
1299 macro returns nonzero for those classes, those pseudos will only
1300 be allocated by `global.c', which knows how to reallocate the
1301 pseudo to another register. If there would not be another
1302 register available for reallocation, you should not change the
1303 definition of this macro since the only effect of such a
1304 definition would be to slow down register allocation. */
1306 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1307 (((CLASS) == AREG) \
1308 || ((CLASS) == DREG) \
1309 || ((CLASS) == CREG) \
1310 || ((CLASS) == BREG) \
1311 || ((CLASS) == AD_REGS) \
1312 || ((CLASS) == SIREG) \
1313 || ((CLASS) == DIREG) \
1314 || ((CLASS) == FP_TOP_REG) \
1315 || ((CLASS) == FP_SECOND_REG))
1317 /* Return a class of registers that cannot change FROM mode to TO mode. */
1319 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1320 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1322 /* Stack layout; function entry, exit and calling. */
1324 /* Define this if pushing a word on the stack
1325 makes the stack pointer a smaller address. */
1326 #define STACK_GROWS_DOWNWARD
1328 /* Define this to nonzero if the nominal address of the stack frame
1329 is at the high-address end of the local variables;
1330 that is, each additional local variable allocated
1331 goes at a more negative offset in the frame. */
1332 #define FRAME_GROWS_DOWNWARD 1
1334 /* Offset within stack frame to start allocating local variables at.
1335 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1336 first local allocated. Otherwise, it is the offset to the BEGINNING
1337 of the first local allocated. */
1338 #define STARTING_FRAME_OFFSET 0
1340 /* If we generate an insn to push BYTES bytes,
1341 this says how many the stack pointer really advances by.
1342 On 386, we have pushw instruction that decrements by exactly 2 no
1343 matter what the position was, there is no pushb.
1344 But as CIE data alignment factor on this arch is -4, we need to make
1345 sure all stack pointer adjustments are in multiple of 4.
1347 For 64bit ABI we round up to 8 bytes.
1350 #define PUSH_ROUNDING(BYTES) \
1352 ? (((BYTES) + 7) & (-8)) \
1353 : (((BYTES) + 3) & (-4)))
1355 /* If defined, the maximum amount of space required for outgoing arguments will
1356 be computed and placed into the variable
1357 `current_function_outgoing_args_size'. No space will be pushed onto the
1358 stack for each call; instead, the function prologue should increase the stack
1359 frame size by this amount. */
1361 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1363 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1364 instructions to pass outgoing arguments. */
1366 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1368 /* We want the stack and args grow in opposite directions, even if
1370 #define PUSH_ARGS_REVERSED 1
1372 /* Offset of first parameter from the argument pointer register value. */
1373 #define FIRST_PARM_OFFSET(FNDECL) 0
1375 /* Define this macro if functions should assume that stack space has been
1376 allocated for arguments even when their values are passed in registers.
1378 The value of this macro is the size, in bytes, of the area reserved for
1379 arguments passed in registers for the function represented by FNDECL.
1381 This space can be allocated by the caller, or be a part of the
1382 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1384 #define REG_PARM_STACK_SPACE(FNDECL) 0
1386 /* Value is the number of bytes of arguments automatically
1387 popped when returning from a subroutine call.
1388 FUNDECL is the declaration node of the function (as a tree),
1389 FUNTYPE is the data type of the function (as a tree),
1390 or for a library call it is an identifier node for the subroutine name.
1391 SIZE is the number of bytes of arguments passed on the stack.
1393 On the 80386, the RTD insn may be used to pop them if the number
1394 of args is fixed, but if the number is variable then the caller
1395 must pop them all. RTD can't be used for library calls now
1396 because the library is compiled with the Unix compiler.
1397 Use of RTD is a selectable option, since it is incompatible with
1398 standard Unix calling sequences. If the option is not selected,
1399 the caller must always pop the args.
1401 The attribute stdcall is equivalent to RTD on a per module basis. */
1403 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1404 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1406 #define FUNCTION_VALUE_REGNO_P(N) \
1407 ix86_function_value_regno_p (N)
1409 /* Define how to find the value returned by a library function
1410 assuming the value has mode MODE. */
1412 #define LIBCALL_VALUE(MODE) \
1413 ix86_libcall_value (MODE)
1415 /* Define the size of the result block used for communication between
1416 untyped_call and untyped_return. The block contains a DImode value
1417 followed by the block used by fnsave and frstor. */
1419 #define APPLY_RESULT_SIZE (8+108)
1421 /* 1 if N is a possible register number for function argument passing. */
1422 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1424 /* Define a data type for recording info about an argument list
1425 during the scan of that argument list. This data type should
1426 hold all necessary information about the function itself
1427 and about the args processed so far, enough to enable macros
1428 such as FUNCTION_ARG to determine where the next arg should go. */
1430 typedef struct ix86_args {
1431 int words; /* # words passed so far */
1432 int nregs; /* # registers available for passing */
1433 int regno; /* next available register number */
1434 int fastcall; /* fastcall calling convention is used */
1435 int sse_words; /* # sse words passed so far */
1436 int sse_nregs; /* # sse registers available for passing */
1437 int warn_sse; /* True when we want to warn about SSE ABI. */
1438 int warn_mmx; /* True when we want to warn about MMX ABI. */
1439 int sse_regno; /* next available sse register number */
1440 int mmx_words; /* # mmx words passed so far */
1441 int mmx_nregs; /* # mmx registers available for passing */
1442 int mmx_regno; /* next available mmx register number */
1443 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1444 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1445 be passed in SSE registers. Otherwise 0. */
1448 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1449 for a call to a function whose data type is FNTYPE.
1450 For a library call, FNTYPE is 0. */
1452 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1453 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1455 /* Update the data in CUM to advance over an argument
1456 of mode MODE and data type TYPE.
1457 (TYPE is null for libcalls where that information may not be available.) */
1459 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1460 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1462 /* Define where to put the arguments to a function.
1463 Value is zero to push the argument on the stack,
1464 or a hard register in which to store the argument.
1466 MODE is the argument's machine mode.
1467 TYPE is the data type of the argument (as a tree).
1468 This is null for libcalls where that information may
1470 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1471 the preceding args and about the function being called.
1472 NAMED is nonzero if this argument is a named parameter
1473 (otherwise it is an extra parameter matching an ellipsis). */
1475 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1476 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1478 /* Implement `va_start' for varargs and stdarg. */
1479 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1480 ix86_va_start (VALIST, NEXTARG)
1482 #define TARGET_ASM_FILE_END ix86_file_end
1483 #define NEED_INDICATE_EXEC_STACK 0
1485 /* Output assembler code to FILE to increment profiler label # LABELNO
1486 for profiling a function entry. */
1488 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1490 #define MCOUNT_NAME "_mcount"
1492 #define PROFILE_COUNT_REGISTER "edx"
1494 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1495 the stack pointer does not matter. The value is tested only in
1496 functions that have frame pointers.
1497 No definition is equivalent to always zero. */
1498 /* Note on the 386 it might be more efficient not to define this since
1499 we have to restore it ourselves from the frame pointer, in order to
1502 #define EXIT_IGNORE_STACK 1
1504 /* Output assembler code for a block containing the constant parts
1505 of a trampoline, leaving space for the variable parts. */
1507 /* On the 386, the trampoline contains two instructions:
1510 The trampoline is generated entirely at runtime. The operand of JMP
1511 is the address of FUNCTION relative to the instruction following the
1512 JMP (which is 5 bytes long). */
1514 /* Length in units of the trampoline for entering a nested function. */
1516 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1518 /* Emit RTL insns to initialize the variable parts of a trampoline.
1519 FNADDR is an RTX for the address of the function's pure code.
1520 CXT is an RTX for the static chain value for the function. */
1522 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1523 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1525 /* Definitions for register eliminations.
1527 This is an array of structures. Each structure initializes one pair
1528 of eliminable registers. The "from" register number is given first,
1529 followed by "to". Eliminations of the same "from" register are listed
1530 in order of preference.
1532 There are two registers that can always be eliminated on the i386.
1533 The frame pointer and the arg pointer can be replaced by either the
1534 hard frame pointer or to the stack pointer, depending upon the
1535 circumstances. The hard frame pointer is not used before reload and
1536 so it is not eligible for elimination. */
1538 #define ELIMINABLE_REGS \
1539 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1540 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1541 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1542 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1544 /* Given FROM and TO register numbers, say whether this elimination is
1545 allowed. Frame pointer elimination is automatically handled.
1547 All other eliminations are valid. */
1549 #define CAN_ELIMINATE(FROM, TO) \
1550 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1552 /* Define the offset between two registers, one to be eliminated, and the other
1553 its replacement, at the start of a routine. */
1555 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1556 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1558 /* Addressing modes, and classification of registers for them. */
1560 /* Macros to check register numbers against specific register classes. */
1562 /* These assume that REGNO is a hard or pseudo reg number.
1563 They give nonzero only if REGNO is a hard reg of the suitable class
1564 or a pseudo reg currently allocated to a suitable hard reg.
1565 Since they use reg_renumber, they are safe only once reg_renumber
1566 has been allocated, which happens in local-alloc.c. */
1568 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1569 ((REGNO) < STACK_POINTER_REGNUM \
1570 || REX_INT_REGNO_P (REGNO) \
1571 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1572 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1574 #define REGNO_OK_FOR_BASE_P(REGNO) \
1575 (GENERAL_REGNO_P (REGNO) \
1576 || (REGNO) == ARG_POINTER_REGNUM \
1577 || (REGNO) == FRAME_POINTER_REGNUM \
1578 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1580 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1581 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1582 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1583 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1585 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1586 and check its validity for a certain class.
1587 We have two alternate definitions for each of them.
1588 The usual definition accepts all pseudo regs; the other rejects
1589 them unless they have been allocated suitable hard regs.
1590 The symbol REG_OK_STRICT causes the latter definition to be used.
1592 Most source files want to accept pseudo regs in the hope that
1593 they will get allocated to the class that the insn wants them to be in.
1594 Source files for reload pass need to be strict.
1595 After reload, it makes no difference, since pseudo regs have
1596 been eliminated by then. */
1599 /* Non strict versions, pseudos are ok. */
1600 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1601 (REGNO (X) < STACK_POINTER_REGNUM \
1602 || REX_INT_REGNO_P (REGNO (X)) \
1603 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1605 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1606 (GENERAL_REGNO_P (REGNO (X)) \
1607 || REGNO (X) == ARG_POINTER_REGNUM \
1608 || REGNO (X) == FRAME_POINTER_REGNUM \
1609 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1611 /* Strict versions, hard registers only */
1612 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1613 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1615 #ifndef REG_OK_STRICT
1616 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1617 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1620 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1621 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1624 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1625 that is a valid memory address for an instruction.
1626 The MODE argument is the machine mode for the MEM expression
1627 that wants to use this address.
1629 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1630 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1632 See legitimize_pic_address in i386.c for details as to what
1633 constitutes a legitimate address when -fpic is used. */
1635 #define MAX_REGS_PER_ADDRESS 2
1637 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1639 /* Nonzero if the constant value X is a legitimate general operand.
1640 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1642 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1644 #ifdef REG_OK_STRICT
1645 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1647 if (legitimate_address_p ((MODE), (X), 1)) \
1652 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1654 if (legitimate_address_p ((MODE), (X), 0)) \
1660 /* If defined, a C expression to determine the base term of address X.
1661 This macro is used in only one place: `find_base_term' in alias.c.
1663 It is always safe for this macro to not be defined. It exists so
1664 that alias analysis can understand machine-dependent addresses.
1666 The typical use of this macro is to handle addresses containing
1667 a label_ref or symbol_ref within an UNSPEC. */
1669 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1671 /* Try machine-dependent ways of modifying an illegitimate address
1672 to be legitimate. If we find one, return the new, valid address.
1673 This macro is used in only one place: `memory_address' in explow.c.
1675 OLDX is the address as it was before break_out_memory_refs was called.
1676 In some cases it is useful to look at this to decide what needs to be done.
1678 MODE and WIN are passed so that this macro can use
1679 GO_IF_LEGITIMATE_ADDRESS.
1681 It is always safe for this macro to do nothing. It exists to recognize
1682 opportunities to optimize the output.
1684 For the 80386, we handle X+REG by loading X into a register R and
1685 using R+REG. R will go in a general reg and indexing will be used.
1686 However, if REG is a broken-out memory address or multiplication,
1687 nothing needs to be done because REG can certainly go in a general reg.
1689 When -fpic is used, special handling is needed for symbolic references.
1690 See comments by legitimize_pic_address in i386.c for details. */
1692 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1694 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1695 if (memory_address_p ((MODE), (X))) \
1699 #define REWRITE_ADDRESS(X) rewrite_address (X)
1701 /* Nonzero if the constant value X is a legitimate general operand
1702 when generating PIC code. It is given that flag_pic is on and
1703 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1705 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1707 #define SYMBOLIC_CONST(X) \
1708 (GET_CODE (X) == SYMBOL_REF \
1709 || GET_CODE (X) == LABEL_REF \
1710 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1712 /* Go to LABEL if ADDR (a legitimate address expression)
1713 has an effect that depends on the machine mode it is used for.
1714 On the 80386, only postdecrement and postincrement address depend thus
1715 (the amount of decrement or increment being the length of the operand). */
1716 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1718 if (GET_CODE (ADDR) == POST_INC \
1719 || GET_CODE (ADDR) == POST_DEC) \
1723 /* Max number of args passed in registers. If this is more than 3, we will
1724 have problems with ebx (register #4), since it is a caller save register and
1725 is also used as the pic register in ELF. So for now, don't allow more than
1726 3 registers to be passed in registers. */
1728 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1730 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1732 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1735 /* Specify the machine mode that this machine uses
1736 for the index in the tablejump instruction. */
1737 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1739 /* Define this as 1 if `char' should by default be signed; else as 0. */
1740 #define DEFAULT_SIGNED_CHAR 1
1742 /* Number of bytes moved into a data cache for a single prefetch operation. */
1743 #define PREFETCH_BLOCK ix86_cost->prefetch_block
1745 /* Number of prefetch operations that can be done in parallel. */
1746 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1748 /* Max number of bytes we can move from memory to memory
1749 in one reasonably fast instruction. */
1752 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1753 move efficiently, as opposed to MOVE_MAX which is the maximum
1754 number of bytes we can move with a single instruction. */
1755 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1757 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1758 move-instruction pairs, we will do a movmem or libcall instead.
1759 Increasing the value will always make code faster, but eventually
1760 incurs high cost in increased code size.
1762 If you don't define this, a reasonable default is used. */
1764 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1766 /* If a clear memory operation would take CLEAR_RATIO or more simple
1767 move-instruction sequences, we will do a clrmem or libcall instead. */
1769 #define CLEAR_RATIO (optimize_size ? 2 \
1770 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1772 /* Define if shifts truncate the shift count
1773 which implies one can omit a sign-extension or zero-extension
1774 of a shift count. */
1775 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1777 /* #define SHIFT_COUNT_TRUNCATED */
1779 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1780 is done just by pretending it is already truncated. */
1781 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1783 /* A macro to update M and UNSIGNEDP when an object whose type is
1784 TYPE and which has the specified mode and signedness is to be
1785 stored in a register. This macro is only called when TYPE is a
1788 On i386 it is sometimes useful to promote HImode and QImode
1789 quantities to SImode. The choice depends on target type. */
1791 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1793 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1794 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1798 /* Specify the machine mode that pointers have.
1799 After generation of rtl, the compiler makes no further distinction
1800 between pointers and any other objects of this machine mode. */
1801 #define Pmode (TARGET_64BIT ? DImode : SImode)
1803 /* A function address in a call instruction
1804 is a byte address (for indexing purposes)
1805 so give the MEM rtx a byte's mode. */
1806 #define FUNCTION_MODE QImode
1808 /* A C expression for the cost of moving data from a register in class FROM to
1809 one in class TO. The classes are expressed using the enumeration values
1810 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1811 interpreted relative to that.
1813 It is not required that the cost always equal 2 when FROM is the same as TO;
1814 on some machines it is expensive to move between registers if they are not
1815 general registers. */
1817 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1818 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1820 /* A C expression for the cost of moving data of mode M between a
1821 register and memory. A value of 2 is the default; this cost is
1822 relative to those in `REGISTER_MOVE_COST'.
1824 If moving between registers and memory is more expensive than
1825 between two registers, you should define this macro to express the
1828 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1829 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1831 /* A C expression for the cost of a branch instruction. A value of 1
1832 is the default; other values are interpreted relative to that. */
1834 #define BRANCH_COST ix86_branch_cost
1836 /* Define this macro as a C expression which is nonzero if accessing
1837 less than a word of memory (i.e. a `char' or a `short') is no
1838 faster than accessing a word of memory, i.e., if such access
1839 require more than one instruction or if there is no difference in
1840 cost between byte and (aligned) word loads.
1842 When this macro is not defined, the compiler will access a field by
1843 finding the smallest containing object; when it is defined, a
1844 fullword load will be used if alignment permits. Unless bytes
1845 accesses are faster than word accesses, using word accesses is
1846 preferable since it may eliminate subsequent memory access if
1847 subsequent accesses occur to other fields in the same word of the
1848 structure, but to different bytes. */
1850 #define SLOW_BYTE_ACCESS 0
1852 /* Nonzero if access to memory by shorts is slow and undesirable. */
1853 #define SLOW_SHORT_ACCESS 0
1855 /* Define this macro to be the value 1 if unaligned accesses have a
1856 cost many times greater than aligned accesses, for example if they
1857 are emulated in a trap handler.
1859 When this macro is nonzero, the compiler will act as if
1860 `STRICT_ALIGNMENT' were nonzero when generating code for block
1861 moves. This can cause significantly more instructions to be
1862 produced. Therefore, do not set this macro nonzero if unaligned
1863 accesses only add a cycle or two to the time for a memory access.
1865 If the value of this macro is always zero, it need not be defined. */
1867 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1869 /* Define this macro if it is as good or better to call a constant
1870 function address than to call an address kept in a register.
1872 Desirable on the 386 because a CALL with a constant address is
1873 faster than one with a register address. */
1875 #define NO_FUNCTION_CSE
1877 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1878 return the mode to be used for the comparison.
1880 For floating-point equality comparisons, CCFPEQmode should be used.
1881 VOIDmode should be used in all other cases.
1883 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1884 possible, to allow for more combinations. */
1886 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1888 /* Return nonzero if MODE implies a floating point inequality can be
1891 #define REVERSIBLE_CC_MODE(MODE) 1
1893 /* A C expression whose value is reversed condition code of the CODE for
1894 comparison done in CC_MODE mode. */
1895 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1898 /* Control the assembler format that we output, to the extent
1899 this does not vary between assemblers. */
1901 /* How to refer to registers in assembler output.
1902 This sequence is indexed by compiler's hard-register-number (see above). */
1904 /* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1905 For non floating point regs, the following are the HImode names.
1907 For float regs, the stack top is sometimes referred to as "%st(0)"
1908 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1910 #define HI_REGISTER_NAMES \
1911 {"ax","dx","cx","bx","si","di","bp","sp", \
1912 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1913 "argp", "flags", "fpsr", "fpcr", "dirflag", "frame", \
1914 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1915 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1916 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1917 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1919 #define REGISTER_NAMES HI_REGISTER_NAMES
1921 /* Table of additional register names to use in user input. */
1923 #define ADDITIONAL_REGISTER_NAMES \
1924 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1925 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1926 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1927 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1928 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1929 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1931 /* Note we are omitting these since currently I don't know how
1932 to get gcc to use these, since they want the same but different
1933 number as al, and ax.
1936 #define QI_REGISTER_NAMES \
1937 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1939 /* These parallel the array above, and can be used to access bits 8:15
1940 of regs 0 through 3. */
1942 #define QI_HIGH_REGISTER_NAMES \
1943 {"ah", "dh", "ch", "bh", }
1945 /* How to renumber registers for dbx and gdb. */
1947 #define DBX_REGISTER_NUMBER(N) \
1948 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1950 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1951 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1952 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1954 /* Before the prologue, RA is at 0(%esp). */
1955 #define INCOMING_RETURN_ADDR_RTX \
1956 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1958 /* After the prologue, RA is at -4(AP) in the current frame. */
1959 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1961 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1962 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1964 /* PC is dbx register 8; let's use that column for RA. */
1965 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1967 /* Before the prologue, the top of the frame is at 4(%esp). */
1968 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1970 /* Describe how we implement __builtin_eh_return. */
1971 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
1972 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1975 /* Select a format to encode pointers in exception handling data. CODE
1976 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1977 true if the symbol may be affected by dynamic relocations.
1979 ??? All x86 object file formats are capable of representing this.
1980 After all, the relocation needed is the same as for the call insn.
1981 Whether or not a particular assembler allows us to enter such, I
1982 guess we'll have to see. */
1983 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1984 asm_preferred_eh_data_format ((CODE), (GLOBAL))
1986 /* This is how to output an insn to push a register on the stack.
1987 It need not be very fast code. */
1989 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1992 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
1993 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1995 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
1998 /* This is how to output an insn to pop a register from the stack.
1999 It need not be very fast code. */
2001 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2004 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2005 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2007 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2010 /* This is how to output an element of a case-vector that is absolute. */
2012 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2013 ix86_output_addr_vec_elt ((FILE), (VALUE))
2015 /* This is how to output an element of a case-vector that is relative. */
2017 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2018 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2020 /* Under some conditions we need jump tables in the text section,
2021 because the assembler cannot handle label differences between
2022 sections. This is the case for x86_64 on Mach-O for example. */
2024 #define JUMP_TABLES_IN_TEXT_SECTION \
2025 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2026 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2028 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2029 and switch back. For x86 we do this only to save a few bytes that
2030 would otherwise be unused in the text section. */
2031 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2032 asm (SECTION_OP "\n\t" \
2033 "call " USER_LABEL_PREFIX #FUNC "\n" \
2034 TEXT_SECTION_ASM_OP);
2036 /* Print operand X (an rtx) in assembler syntax to file FILE.
2037 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2038 Effect of various CODE letters is described in i386.c near
2039 print_operand function. */
2041 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2042 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2044 #define PRINT_OPERAND(FILE, X, CODE) \
2045 print_operand ((FILE), (X), (CODE))
2047 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2048 print_operand_address ((FILE), (ADDR))
2050 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2052 if (! output_addr_const_extra (FILE, (X))) \
2056 /* a letter which is not needed by the normal asm syntax, which
2057 we can use for operand syntax in the extended asm */
2059 #define ASM_OPERAND_LETTER '#'
2060 #define RET return ""
2061 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2063 /* Which processor to schedule for. The cpu attribute defines a list that
2064 mirrors this list, so changes to i386.md must be made at the same time. */
2068 PROCESSOR_I386, /* 80386 */
2069 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2071 PROCESSOR_PENTIUMPRO,
2078 PROCESSOR_GENERIC32,
2079 PROCESSOR_GENERIC64,
2083 extern enum processor_type ix86_tune;
2084 extern enum processor_type ix86_arch;
2092 extern enum fpmath_unit ix86_fpmath;
2101 extern enum tls_dialect ix86_tls_dialect;
2104 CM_32, /* The traditional 32-bit ABI. */
2105 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2106 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2107 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2108 CM_LARGE, /* No assumptions. */
2109 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2110 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2113 extern enum cmodel ix86_cmodel;
2115 /* Size of the RED_ZONE area. */
2116 #define RED_ZONE_SIZE 128
2117 /* Reserved area of the red zone for temporaries. */
2118 #define RED_ZONE_RESERVE 8
2125 extern enum asm_dialect ix86_asm_dialect;
2126 extern unsigned int ix86_preferred_stack_boundary;
2127 extern int ix86_branch_cost, ix86_section_threshold;
2129 /* Smallest class containing REGNO. */
2130 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2132 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2133 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2134 extern rtx ix86_compare_emitted;
2136 /* To properly truncate FP values into integers, we need to set i387 control
2137 word. We can't emit proper mode switching code before reload, as spills
2138 generated by reload may truncate values incorrectly, but we still can avoid
2139 redundant computation of new control word by the mode switching pass.
2140 The fldcw instructions are still emitted redundantly, but this is probably
2141 not going to be noticeable problem, as most CPUs do have fast path for
2144 The machinery is to emit simple truncation instructions and split them
2145 before reload to instructions having USEs of two memory locations that
2146 are filled by this code to old and new control word.
2148 Post-reload pass may be later used to eliminate the redundant fildcw if
2160 enum ix86_stack_slot
2168 MAX_386_STACK_LOCALS
2171 /* Define this macro if the port needs extra instructions inserted
2172 for mode switching in an optimizing compilation. */
2174 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2175 ix86_optimize_mode_switching[(ENTITY)]
2177 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2178 initializer for an array of integers. Each initializer element N
2179 refers to an entity that needs mode switching, and specifies the
2180 number of different modes that might need to be set for this
2181 entity. The position of the initializer in the initializer -
2182 starting counting at zero - determines the integer that is used to
2183 refer to the mode-switched entity in question. */
2185 #define NUM_MODES_FOR_MODE_SWITCHING \
2186 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2188 /* ENTITY is an integer specifying a mode-switched entity. If
2189 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2190 return an integer value not larger than the corresponding element
2191 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2192 must be switched into prior to the execution of INSN. */
2194 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2196 /* This macro specifies the order in which modes for ENTITY are
2197 processed. 0 is the highest priority. */
2199 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2201 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2202 is the set of hard registers live at the point where the insn(s)
2203 are to be inserted. */
2205 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2206 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2207 ? emit_i387_cw_initialization (MODE), 0 \
2211 /* Avoid renaming of stack registers, as doing so in combination with
2212 scheduling just increases amount of live registers at time and in
2213 the turn amount of fxch instructions needed.
2215 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2217 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2218 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2221 #define DLL_IMPORT_EXPORT_PREFIX '#'
2223 #define FASTCALL_PREFIX '@'
2225 struct machine_function GTY(())
2227 struct stack_local_entry *stack_locals;
2228 const char *some_ld_name;
2229 rtx force_align_arg_pointer;
2230 int save_varrargs_registers;
2231 int accesses_prev_frame;
2232 int optimize_mode_switching[MAX_386_ENTITIES];
2233 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2234 determine the style used. */
2235 int use_fast_prologue_epilogue;
2236 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2238 int use_fast_prologue_epilogue_nregs;
2239 /* If true, the current function needs the default PIC register, not
2240 an alternate register (on x86) and must not use the red zone (on
2241 x86_64), even if it's a leaf function. We don't want the
2242 function to be regarded as non-leaf because TLS calls need not
2243 affect register allocation. This flag is set when a TLS call
2244 instruction is expanded within a function, and never reset, even
2245 if all such instructions are optimized away. Use the
2246 ix86_current_function_calls_tls_descriptor macro for a better
2248 int tls_descriptor_call_expanded_p;
2251 #define ix86_stack_locals (cfun->machine->stack_locals)
2252 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2253 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2254 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2255 (cfun->machine->tls_descriptor_call_expanded_p)
2256 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2257 calls are optimized away, we try to detect cases in which it was
2258 optimized away. Since such instructions (use (reg REG_SP)), we can
2259 verify whether there's any such instruction live by testing that
2261 #define ix86_current_function_calls_tls_descriptor \
2262 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2264 /* Control behavior of x86_file_start. */
2265 #define X86_FILE_START_VERSION_DIRECTIVE false
2266 #define X86_FILE_START_FLTUSED false
2268 /* Flag to mark data that is in the large address area. */
2269 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2270 #define SYMBOL_REF_FAR_ADDR_P(X) \
2271 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
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