1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Redefines for option macros. */
39 #define TARGET_64BIT OPTION_ISA_64BIT
40 #define TARGET_MMX OPTION_ISA_MMX
41 #define TARGET_3DNOW OPTION_ISA_3DNOW
42 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
43 #define TARGET_SSE OPTION_ISA_SSE
44 #define TARGET_SSE2 OPTION_ISA_SSE2
45 #define TARGET_SSE3 OPTION_ISA_SSE3
46 #define TARGET_SSSE3 OPTION_ISA_SSSE3
47 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
48 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
49 #define TARGET_SSE4A OPTION_ISA_SSE4A
50 #define TARGET_SSE5 OPTION_ISA_SSE5
51 #define TARGET_ROUND OPTION_ISA_ROUND
52 #define TARGET_ABM OPTION_ISA_ABM
53 #define TARGET_POPCNT OPTION_ISA_POPCNT
54 #define TARGET_SAHF OPTION_ISA_SAHF
55 #define TARGET_AES OPTION_ISA_AES
56 #define TARGET_PCLMUL OPTION_ISA_PCLMUL
57 #define TARGET_CMPXCHG16B OPTION_ISA_CX16
60 /* SSE5 and SSE4.1 define the same round instructions */
61 #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5)
62 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
64 #include "config/vxworks-dummy.h"
66 /* Algorithm to expand string function with. */
79 #define NAX_STRINGOP_ALGS 4
81 /* Specify what algorithm to use for stringops on known size.
82 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
83 known at compile time or estimated via feedback, the SIZE array
84 is walked in order until MAX is greater then the estimate (or -1
85 means infinity). Corresponding ALG is used then.
86 For example initializer:
87 {{256, loop}, {-1, rep_prefix_4_byte}}
88 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
92 const enum stringop_alg unknown_size;
93 const struct stringop_strategy {
95 const enum stringop_alg alg;
96 } size [NAX_STRINGOP_ALGS];
99 /* Define the specific costs for a given cpu */
101 struct processor_costs {
102 const int add; /* cost of an add instruction */
103 const int lea; /* cost of a lea instruction */
104 const int shift_var; /* variable shift costs */
105 const int shift_const; /* constant shift costs */
106 const int mult_init[5]; /* cost of starting a multiply
107 in QImode, HImode, SImode, DImode, TImode*/
108 const int mult_bit; /* cost of multiply per each bit set */
109 const int divide[5]; /* cost of a divide/mod
110 in QImode, HImode, SImode, DImode, TImode*/
111 int movsx; /* The cost of movsx operation. */
112 int movzx; /* The cost of movzx operation. */
113 const int large_insn; /* insns larger than this cost more */
114 const int move_ratio; /* The threshold of number of scalar
115 memory-to-memory move insns. */
116 const int movzbl_load; /* cost of loading using movzbl */
117 const int int_load[3]; /* cost of loading integer registers
118 in QImode, HImode and SImode relative
119 to reg-reg move (2). */
120 const int int_store[3]; /* cost of storing integer register
121 in QImode, HImode and SImode */
122 const int fp_move; /* cost of reg,reg fld/fst */
123 const int fp_load[3]; /* cost of loading FP register
124 in SFmode, DFmode and XFmode */
125 const int fp_store[3]; /* cost of storing FP register
126 in SFmode, DFmode and XFmode */
127 const int mmx_move; /* cost of moving MMX register. */
128 const int mmx_load[2]; /* cost of loading MMX register
129 in SImode and DImode */
130 const int mmx_store[2]; /* cost of storing MMX register
131 in SImode and DImode */
132 const int sse_move; /* cost of moving SSE register. */
133 const int sse_load[3]; /* cost of loading SSE register
134 in SImode, DImode and TImode*/
135 const int sse_store[3]; /* cost of storing SSE register
136 in SImode, DImode and TImode*/
137 const int mmxsse_to_integer; /* cost of moving mmxsse register to
138 integer and vice versa. */
139 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
140 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
141 const int prefetch_block; /* bytes moved to cache for prefetch. */
142 const int simultaneous_prefetches; /* number of parallel prefetch
144 const int branch_cost; /* Default value for BRANCH_COST. */
145 const int fadd; /* cost of FADD and FSUB instructions. */
146 const int fmul; /* cost of FMUL instruction. */
147 const int fdiv; /* cost of FDIV instruction. */
148 const int fabs; /* cost of FABS instruction. */
149 const int fchs; /* cost of FCHS instruction. */
150 const int fsqrt; /* cost of FSQRT instruction. */
151 /* Specify what algorithm
152 to use for stringops on unknown size. */
153 struct stringop_algs memcpy[2], memset[2];
154 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
156 const int scalar_load_cost; /* Cost of scalar load. */
157 const int scalar_store_cost; /* Cost of scalar store. */
158 const int vec_stmt_cost; /* Cost of any vector operation, excluding
159 load, store, vector-to-scalar and
160 scalar-to-vector operation. */
161 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
162 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
163 const int vec_align_load_cost; /* Cost of aligned vector load. */
164 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
165 const int vec_store_cost; /* Cost of vector store. */
166 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
168 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
169 vectorizer cost model. */
172 extern const struct processor_costs *ix86_cost;
174 /* Macros used in the machine description to test the flags. */
176 /* configure can arrange to make this 2, to force a 486. */
178 #ifndef TARGET_CPU_DEFAULT
179 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
182 #ifndef TARGET_FPMATH_DEFAULT
183 #define TARGET_FPMATH_DEFAULT \
184 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
187 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
189 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
190 compile-time constant. */
194 #define TARGET_64BIT 1
196 #define TARGET_64BIT 0
199 #ifndef TARGET_BI_ARCH
201 #if TARGET_64BIT_DEFAULT
202 #define TARGET_64BIT 1
204 #define TARGET_64BIT 0
209 #define HAS_LONG_COND_BRANCH 1
210 #define HAS_LONG_UNCOND_BRANCH 1
212 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
213 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
214 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
215 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
216 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
217 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
218 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
219 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
220 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
221 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
222 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
223 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
224 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
225 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
226 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
227 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
229 /* Feature tests against the various tunings. */
230 enum ix86_tune_indices {
232 X86_TUNE_PUSH_MEMORY,
233 X86_TUNE_ZERO_EXTEND_WITH_AND,
234 X86_TUNE_USE_BIT_TEST,
235 X86_TUNE_UNROLL_STRLEN,
236 X86_TUNE_DEEP_BRANCH_PREDICTION,
237 X86_TUNE_BRANCH_PREDICTION_HINTS,
238 X86_TUNE_DOUBLE_WITH_ADD,
241 X86_TUNE_PARTIAL_REG_STALL,
242 X86_TUNE_PARTIAL_FLAG_REG_STALL,
243 X86_TUNE_USE_HIMODE_FIOP,
244 X86_TUNE_USE_SIMODE_FIOP,
248 X86_TUNE_SPLIT_LONG_MOVES,
249 X86_TUNE_READ_MODIFY_WRITE,
250 X86_TUNE_READ_MODIFY,
251 X86_TUNE_PROMOTE_QIMODE,
252 X86_TUNE_FAST_PREFIX,
253 X86_TUNE_SINGLE_STRINGOP,
254 X86_TUNE_QIMODE_MATH,
255 X86_TUNE_HIMODE_MATH,
256 X86_TUNE_PROMOTE_QI_REGS,
257 X86_TUNE_PROMOTE_HI_REGS,
262 X86_TUNE_INTEGER_DFMODE_MOVES,
263 X86_TUNE_PARTIAL_REG_DEPENDENCY,
264 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
265 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
266 X86_TUNE_SSE_SPLIT_REGS,
267 X86_TUNE_SSE_TYPELESS_STORES,
268 X86_TUNE_SSE_LOAD0_BY_PXOR,
269 X86_TUNE_MEMORY_MISMATCH_STALL,
270 X86_TUNE_PROLOGUE_USING_MOVE,
271 X86_TUNE_EPILOGUE_USING_MOVE,
274 X86_TUNE_INTER_UNIT_MOVES,
275 X86_TUNE_INTER_UNIT_CONVERSIONS,
276 X86_TUNE_FOUR_JUMP_LIMIT,
280 X86_TUNE_PAD_RETURNS,
281 X86_TUNE_EXT_80387_CONSTANTS,
282 X86_TUNE_SHORTEN_X87_SSE,
283 X86_TUNE_AVOID_VECTOR_DECODE,
284 X86_TUNE_PROMOTE_HIMODE_IMUL,
285 X86_TUNE_SLOW_IMUL_IMM32_MEM,
286 X86_TUNE_SLOW_IMUL_IMM8,
287 X86_TUNE_MOVE_M1_VIA_OR,
288 X86_TUNE_NOT_UNPAIRABLE,
289 X86_TUNE_NOT_VECTORMODE,
290 X86_TUNE_USE_VECTOR_CONVERTS,
291 X86_TUNE_FUSE_CMP_AND_BRANCH,
296 extern unsigned char ix86_tune_features[X86_TUNE_LAST];
298 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
299 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
300 #define TARGET_ZERO_EXTEND_WITH_AND \
301 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
302 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
303 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
304 #define TARGET_DEEP_BRANCH_PREDICTION \
305 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
306 #define TARGET_BRANCH_PREDICTION_HINTS \
307 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
308 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
309 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
310 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
311 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
312 #define TARGET_PARTIAL_FLAG_REG_STALL \
313 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
314 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
315 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
316 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
317 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
318 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
319 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
320 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
321 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
322 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
323 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
324 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
325 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
326 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
327 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
328 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
329 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
330 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
331 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
332 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
333 #define TARGET_INTEGER_DFMODE_MOVES \
334 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
335 #define TARGET_PARTIAL_REG_DEPENDENCY \
336 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
337 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
338 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
339 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
340 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
341 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
342 #define TARGET_SSE_TYPELESS_STORES \
343 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
344 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
345 #define TARGET_MEMORY_MISMATCH_STALL \
346 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
347 #define TARGET_PROLOGUE_USING_MOVE \
348 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
349 #define TARGET_EPILOGUE_USING_MOVE \
350 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
351 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
352 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
353 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
354 #define TARGET_INTER_UNIT_CONVERSIONS\
355 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
356 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
357 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
358 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
359 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
360 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
361 #define TARGET_EXT_80387_CONSTANTS \
362 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
363 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
364 #define TARGET_AVOID_VECTOR_DECODE \
365 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
366 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
367 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
368 #define TARGET_SLOW_IMUL_IMM32_MEM \
369 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
370 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
371 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
372 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
373 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
374 #define TARGET_USE_VECTOR_CONVERTS \
375 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
376 #define TARGET_FUSE_CMP_AND_BRANCH \
377 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
379 /* Feature tests against the various architecture variations. */
380 enum ix86_arch_indices {
381 X86_ARCH_CMOVE, /* || TARGET_SSE */
390 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
392 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
393 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
394 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
395 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
396 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
398 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
400 extern int x86_prefetch_sse;
402 #define TARGET_PREFETCH_SSE x86_prefetch_sse
404 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
406 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
407 #define TARGET_MIX_SSE_I387 \
408 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
410 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
411 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
412 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
413 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
415 extern int ix86_isa_flags;
417 #ifndef TARGET_64BIT_DEFAULT
418 #define TARGET_64BIT_DEFAULT 0
420 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
421 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
424 /* Fence to use after loop using storent. */
426 extern tree x86_mfence;
427 #define FENCE_FOLLOWING_MOVNT x86_mfence
429 /* Once GDB has been enhanced to deal with functions without frame
430 pointers, we can change this to allow for elimination of
431 the frame pointer in leaf functions. */
432 #define TARGET_DEFAULT 0
434 /* Extra bits to force. */
435 #define TARGET_SUBTARGET_DEFAULT 0
436 #define TARGET_SUBTARGET_ISA_DEFAULT 0
438 /* Extra bits to force on w/ 32-bit mode. */
439 #define TARGET_SUBTARGET32_DEFAULT 0
440 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
442 /* Extra bits to force on w/ 64-bit mode. */
443 #define TARGET_SUBTARGET64_DEFAULT 0
444 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
446 /* This is not really a target flag, but is done this way so that
447 it's analogous to similar code for Mach-O on PowerPC. darwin.h
448 redefines this to 1. */
449 #define TARGET_MACHO 0
451 /* Likewise, for the Windows 64-bit ABI. */
452 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
454 /* Available call abi. */
461 /* The default abi form used by target. */
462 #define DEFAULT_ABI SYSV_ABI
464 /* Subtargets may reset this to 1 in order to enable 96-bit long double
465 with the rounding mode forced to 53 bits. */
466 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
468 /* Sometimes certain combinations of command options do not make
469 sense on a particular target machine. You can define a macro
470 `OVERRIDE_OPTIONS' to take account of this. This macro, if
471 defined, is executed once just after all the command options have
474 Don't use this macro to turn on various extra optimizations for
475 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
477 #define OVERRIDE_OPTIONS override_options (true)
479 /* Define this to change the optimizations performed by default. */
480 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
481 optimization_options ((LEVEL), (SIZE))
483 /* -march=native handling only makes sense with compiler running on
484 an x86 or x86_64 chip. If changing this condition, also change
485 the condition in driver-i386.c. */
486 #if defined(__i386__) || defined(__x86_64__)
487 /* In driver-i386.c. */
488 extern const char *host_detect_local_cpu (int argc, const char **argv);
489 #define EXTRA_SPEC_FUNCTIONS \
490 { "local_cpu_detect", host_detect_local_cpu },
491 #define HAVE_LOCAL_CPU_DETECT
494 #if TARGET_64BIT_DEFAULT
495 #define OPT_ARCH64 "!m32"
496 #define OPT_ARCH32 "m32"
498 #define OPT_ARCH64 "m64"
499 #define OPT_ARCH32 "!m64"
502 /* Support for configure-time defaults of some command line options.
503 The order here is important so that -march doesn't squash the
504 tune or cpu values. */
505 #define OPTION_DEFAULT_SPECS \
506 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
507 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
508 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
509 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
510 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
511 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
512 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
513 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
514 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
516 /* Specs for the compiler proper */
519 #define CC1_CPU_SPEC_1 "\
521 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
523 %{mintel-syntax:-masm=intel \
524 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
525 %{mno-intel-syntax:-masm=att \
526 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
528 #ifndef HAVE_LOCAL_CPU_DETECT
529 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
531 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
532 "%{march=native:%<march=native %:local_cpu_detect(arch) \
533 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
534 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
538 /* Target CPU builtins. */
539 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
541 /* Target Pragmas. */
542 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
544 enum target_cpu_default
546 TARGET_CPU_DEFAULT_generic = 0,
548 TARGET_CPU_DEFAULT_i386,
549 TARGET_CPU_DEFAULT_i486,
550 TARGET_CPU_DEFAULT_pentium,
551 TARGET_CPU_DEFAULT_pentium_mmx,
552 TARGET_CPU_DEFAULT_pentiumpro,
553 TARGET_CPU_DEFAULT_pentium2,
554 TARGET_CPU_DEFAULT_pentium3,
555 TARGET_CPU_DEFAULT_pentium4,
556 TARGET_CPU_DEFAULT_pentium_m,
557 TARGET_CPU_DEFAULT_prescott,
558 TARGET_CPU_DEFAULT_nocona,
559 TARGET_CPU_DEFAULT_core2,
561 TARGET_CPU_DEFAULT_geode,
562 TARGET_CPU_DEFAULT_k6,
563 TARGET_CPU_DEFAULT_k6_2,
564 TARGET_CPU_DEFAULT_k6_3,
565 TARGET_CPU_DEFAULT_athlon,
566 TARGET_CPU_DEFAULT_athlon_sse,
567 TARGET_CPU_DEFAULT_k8,
568 TARGET_CPU_DEFAULT_amdfam10,
570 TARGET_CPU_DEFAULT_max
574 #define CC1_SPEC "%(cc1_cpu) "
577 /* This macro defines names of additional specifications to put in the
578 specs that can be used in various specifications like CC1_SPEC. Its
579 definition is an initializer with a subgrouping for each command option.
581 Each subgrouping contains a string constant, that defines the
582 specification name, and a string constant that used by the GCC driver
585 Do not define this macro if it does not need to do anything. */
587 #ifndef SUBTARGET_EXTRA_SPECS
588 #define SUBTARGET_EXTRA_SPECS
591 #define EXTRA_SPECS \
592 { "cc1_cpu", CC1_CPU_SPEC }, \
593 SUBTARGET_EXTRA_SPECS
596 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
597 FPU, assume that the fpcw is set to extended precision; when using
598 only SSE, rounding is correct; when using both SSE and the FPU,
599 the rounding precision is indeterminate, since either may be chosen
600 apparently at random. */
601 #define TARGET_FLT_EVAL_METHOD \
602 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
604 /* target machine storage layout */
606 #define SHORT_TYPE_SIZE 16
607 #define INT_TYPE_SIZE 32
608 #define FLOAT_TYPE_SIZE 32
609 #define LONG_TYPE_SIZE BITS_PER_WORD
610 #define DOUBLE_TYPE_SIZE 64
611 #define LONG_LONG_TYPE_SIZE 64
612 #define LONG_DOUBLE_TYPE_SIZE 80
614 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
616 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
617 #define MAX_BITS_PER_WORD 64
619 #define MAX_BITS_PER_WORD 32
622 /* Define this if most significant byte of a word is the lowest numbered. */
623 /* That is true on the 80386. */
625 #define BITS_BIG_ENDIAN 0
627 /* Define this if most significant byte of a word is the lowest numbered. */
628 /* That is not true on the 80386. */
629 #define BYTES_BIG_ENDIAN 0
631 /* Define this if most significant word of a multiword number is the lowest
633 /* Not true for 80386 */
634 #define WORDS_BIG_ENDIAN 0
636 /* Width of a word, in units (bytes). */
637 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
639 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
641 #define MIN_UNITS_PER_WORD 4
644 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
645 #define PARM_BOUNDARY BITS_PER_WORD
647 /* Boundary (in *bits*) on which stack pointer should be aligned. */
648 #define STACK_BOUNDARY (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 \
651 /* Stack boundary of the main function guaranteed by OS. */
652 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
654 /* Minimum stack boundary. */
655 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
657 /* Boundary (in *bits*) on which the stack pointer prefers to be
658 aligned; the compiler cannot rely on having this alignment. */
659 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
661 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
662 both 32bit and 64bit, to support codes that need 128 bit stack
663 alignment for SSE instructions, but can't realign the stack. */
664 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
666 /* 1 if -mstackrealign should be turned on by default. It will
667 generate an alternate prologue and epilogue that realigns the
668 runtime stack if nessary. This supports mixing codes that keep a
669 4-byte aligned stack, as specified by i386 psABI, with codes that
670 need a 16-byte aligned stack, as required by SSE instructions. If
671 STACK_REALIGN_DEFAULT is 1 and PREFERRED_STACK_BOUNDARY_DEFAULT is
672 128, stacks for all functions may be realigned. */
673 #define STACK_REALIGN_DEFAULT 0
675 /* Boundary (in *bits*) on which the incoming stack is aligned. */
676 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
678 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
679 mandatory for the 64-bit ABI, and may or may not be true for other
680 operating systems. */
681 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
683 /* Minimum allocation boundary for the code of a function. */
684 #define FUNCTION_BOUNDARY 8
686 /* C++ stores the virtual bit in the lowest bit of function pointers. */
687 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
689 /* Alignment of field after `int : 0' in a structure. */
691 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
693 /* Minimum size in bits of the largest boundary to which any
694 and all fundamental data types supported by the hardware
695 might need to be aligned. No data type wants to be aligned
698 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
699 and Pentium Pro XFmode values at 128 bit boundaries. */
701 #define BIGGEST_ALIGNMENT 128
703 /* Maximum stack alignment. */
704 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
706 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
707 #define ALIGN_MODE_128(MODE) \
708 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
710 /* The published ABIs say that doubles should be aligned on word
711 boundaries, so lower the alignment for structure fields unless
712 -malign-double is set. */
714 /* ??? Blah -- this macro is used directly by libobjc. Since it
715 supports no vector modes, cut out the complexity and fall back
716 on BIGGEST_FIELD_ALIGNMENT. */
717 #ifdef IN_TARGET_LIBS
719 #define BIGGEST_FIELD_ALIGNMENT 128
721 #define BIGGEST_FIELD_ALIGNMENT 32
724 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
725 x86_field_alignment (FIELD, COMPUTED)
728 /* If defined, a C expression to compute the alignment given to a
729 constant that is being placed in memory. EXP is the constant
730 and ALIGN is the alignment that the object would ordinarily have.
731 The value of this macro is used instead of that alignment to align
734 If this macro is not defined, then ALIGN is used.
736 The typical use of this macro is to increase alignment for string
737 constants to be word aligned so that `strcpy' calls that copy
738 constants can be done inline. */
740 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
742 /* If defined, a C expression to compute the alignment for a static
743 variable. TYPE is the data type, and ALIGN is the alignment that
744 the object would ordinarily have. The value of this macro is used
745 instead of that alignment to align the object.
747 If this macro is not defined, then ALIGN is used.
749 One use of this macro is to increase alignment of medium-size
750 data to make it all fit in fewer cache lines. Another is to
751 cause character arrays to be word-aligned so that `strcpy' calls
752 that copy constants to character arrays can be done inline. */
754 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
756 /* If defined, a C expression to compute the alignment for a local
757 variable. TYPE is the data type, and ALIGN is the alignment that
758 the object would ordinarily have. The value of this macro is used
759 instead of that alignment to align the object.
761 If this macro is not defined, then ALIGN is used.
763 One use of this macro is to increase alignment of medium-size
764 data to make it all fit in fewer cache lines. */
766 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
767 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
769 /* If defined, a C expression to compute the alignment for stack slot.
770 TYPE is the data type, MODE is the widest mode available, and ALIGN
771 is the alignment that the slot would ordinarily have. The value of
772 this macro is used instead of that alignment to align the slot.
774 If this macro is not defined, then ALIGN is used when TYPE is NULL,
775 Otherwise, LOCAL_ALIGNMENT will be used.
777 One use of this macro is to set alignment of stack slot to the
778 maximum alignment of all possible modes which the slot may have. */
780 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
781 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
783 /* If defined, a C expression that gives the alignment boundary, in
784 bits, of an argument with the specified mode and type. If it is
785 not defined, `PARM_BOUNDARY' is used for all arguments. */
787 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
788 ix86_function_arg_boundary ((MODE), (TYPE))
790 /* Set this nonzero if move instructions will actually fail to work
791 when given unaligned data. */
792 #define STRICT_ALIGNMENT 0
794 /* If bit field type is int, don't let it cross an int,
795 and give entire struct the alignment of an int. */
796 /* Required on the 386 since it doesn't have bit-field insns. */
797 #define PCC_BITFIELD_TYPE_MATTERS 1
799 /* Standard register usage. */
801 /* This processor has special stack-like registers. See reg-stack.c
806 #define IS_STACK_MODE(MODE) \
807 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
808 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
811 /* Number of actual hardware registers.
812 The hardware registers are assigned numbers for the compiler
813 from 0 to just below FIRST_PSEUDO_REGISTER.
814 All registers that the compiler knows about must be given numbers,
815 even those that are not normally considered general registers.
817 In the 80386 we give the 8 general purpose registers the numbers 0-7.
818 We number the floating point registers 8-15.
819 Note that registers 0-7 can be accessed as a short or int,
820 while only 0-3 may be used with byte `mov' instructions.
822 Reg 16 does not correspond to any hardware register, but instead
823 appears in the RTL as an argument pointer prior to reload, and is
824 eliminated during reloading in favor of either the stack or frame
827 #define FIRST_PSEUDO_REGISTER 53
829 /* Number of hardware registers that go into the DWARF-2 unwind info.
830 If not defined, equals FIRST_PSEUDO_REGISTER. */
832 #define DWARF_FRAME_REGISTERS 17
834 /* 1 for registers that have pervasive standard uses
835 and are not available for the register allocator.
836 On the 80386, the stack pointer is such, as is the arg pointer.
838 The value is zero if the register is not fixed on either 32 or
839 64 bit targets, one if the register if fixed on both 32 and 64
840 bit targets, two if it is only fixed on 32bit targets and three
841 if its only fixed on 64bit targets.
842 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
844 #define FIXED_REGISTERS \
845 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
846 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
847 /*arg,flags,fpsr,fpcr,frame*/ \
849 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
850 0, 0, 0, 0, 0, 0, 0, 0, \
851 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
852 0, 0, 0, 0, 0, 0, 0, 0, \
853 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
854 2, 2, 2, 2, 2, 2, 2, 2, \
855 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
856 2, 2, 2, 2, 2, 2, 2, 2 }
859 /* 1 for registers not available across function calls.
860 These must include the FIXED_REGISTERS and also any
861 registers that can be used without being saved.
862 The latter must include the registers where values are returned
863 and the register where structure-value addresses are passed.
864 Aside from that, you can include as many other registers as you like.
866 The value is zero if the register is not call used on either 32 or
867 64 bit targets, one if the register if call used on both 32 and 64
868 bit targets, two if it is only call used on 32bit targets and three
869 if its only call used on 64bit targets.
870 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
872 #define CALL_USED_REGISTERS \
873 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
874 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
875 /*arg,flags,fpsr,fpcr,frame*/ \
877 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
878 1, 1, 1, 1, 1, 1, 1, 1, \
879 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
880 1, 1, 1, 1, 1, 1, 1, 1, \
881 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
882 1, 1, 1, 1, 2, 2, 2, 2, \
883 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
884 1, 1, 1, 1, 1, 1, 1, 1 }
886 /* Order in which to allocate registers. Each register must be
887 listed once, even those in FIXED_REGISTERS. List frame pointer
888 late and fixed registers last. Note that, in general, we prefer
889 registers listed in CALL_USED_REGISTERS, keeping the others
890 available for storage of persistent values.
892 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
893 so this is just empty initializer for array. */
895 #define REG_ALLOC_ORDER \
896 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
897 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
898 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
901 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
902 to be rearranged based on a particular function. When using sse math,
903 we want to allocate SSE before x87 registers and vice versa. */
905 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
908 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
910 /* Macro to conditionally modify fixed_regs/call_used_regs. */
911 #define CONDITIONAL_REGISTER_USAGE \
915 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
917 if (fixed_regs[i] > 1) \
918 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
919 if (call_used_regs[i] > 1) \
920 call_used_regs[i] = (call_used_regs[i] \
921 == (TARGET_64BIT ? 3 : 2)); \
923 j = PIC_OFFSET_TABLE_REGNUM; \
924 if (j != INVALID_REGNUM) \
927 call_used_regs[j] = 1; \
932 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
933 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
934 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
940 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
941 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
943 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
947 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
948 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
949 if (TEST_HARD_REG_BIT (x, i)) \
950 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
952 if (! TARGET_64BIT) \
955 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
957 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
960 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) \
962 call_used_regs[4 /*RSI*/] = 0; \
963 call_used_regs[5 /*RDI*/] = 0; \
967 /* Return number of consecutive hard regs needed starting at reg REGNO
968 to hold something of mode MODE.
969 This is ordinarily the length in words of a value of mode MODE
970 but can be less for certain modes in special long registers.
972 Actually there are no two word move instructions for consecutive
973 registers. And only registers 0-3 may have mov byte instructions
977 #define HARD_REGNO_NREGS(REGNO, MODE) \
978 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
979 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
980 : ((MODE) == XFmode \
981 ? (TARGET_64BIT ? 2 : 3) \
983 ? (TARGET_64BIT ? 4 : 6) \
984 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
986 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
987 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
988 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
990 : ((MODE) == XFmode || (MODE) == XCmode)) \
993 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
995 #define VALID_SSE2_REG_MODE(MODE) \
996 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
997 || (MODE) == V2DImode || (MODE) == DFmode)
999 #define VALID_SSE_REG_MODE(MODE) \
1000 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1001 || (MODE) == SFmode || (MODE) == TFmode)
1003 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1004 ((MODE) == V2SFmode || (MODE) == SFmode)
1006 #define VALID_MMX_REG_MODE(MODE) \
1007 ((MODE == V1DImode) || (MODE) == DImode \
1008 || (MODE) == V2SImode || (MODE) == SImode \
1009 || (MODE) == V4HImode || (MODE) == V8QImode)
1011 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1012 place emms and femms instructions. */
1013 #define UNITS_PER_SIMD_WORD(MODE) (TARGET_SSE ? 16 : UNITS_PER_WORD)
1015 #define VALID_DFP_MODE_P(MODE) \
1016 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1018 #define VALID_FP_MODE_P(MODE) \
1019 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1020 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1022 #define VALID_INT_MODE_P(MODE) \
1023 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1024 || (MODE) == DImode \
1025 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1026 || (MODE) == CDImode \
1027 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1028 || (MODE) == TFmode || (MODE) == TCmode)))
1030 /* Return true for modes passed in SSE registers. */
1031 #define SSE_REG_MODE_P(MODE) \
1032 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1033 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1034 || (MODE) == V4SFmode || (MODE) == V4SImode)
1036 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1038 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1039 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1041 /* Value is 1 if it is a good idea to tie two pseudo registers
1042 when one has mode MODE1 and one has mode MODE2.
1043 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1044 for any hard reg, then this must be 0 for correct output. */
1046 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1048 /* It is possible to write patterns to move flags; but until someone
1050 #define AVOID_CCMODE_COPIES
1052 /* Specify the modes required to caller save a given hard regno.
1053 We do this on i386 to prevent flags from being saved at all.
1055 Kill any attempts to combine saving of modes. */
1057 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1058 (CC_REGNO_P (REGNO) ? VOIDmode \
1059 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1060 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1061 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1062 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1065 /* Specify the registers used for certain standard purposes.
1066 The values of these macros are register numbers. */
1068 /* on the 386 the pc register is %eip, and is not usable as a general
1069 register. The ordinary mov instructions won't work */
1070 /* #define PC_REGNUM */
1072 /* Register to use for pushing function arguments. */
1073 #define STACK_POINTER_REGNUM 7
1075 /* Base register for access to local variables of the function. */
1076 #define HARD_FRAME_POINTER_REGNUM 6
1078 /* Base register for access to local variables of the function. */
1079 #define FRAME_POINTER_REGNUM 20
1081 /* First floating point reg */
1082 #define FIRST_FLOAT_REG 8
1084 /* First & last stack-like regs */
1085 #define FIRST_STACK_REG FIRST_FLOAT_REG
1086 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1088 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1089 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1091 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1092 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1094 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1095 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1097 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1098 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1100 /* Value should be nonzero if functions must have frame pointers.
1101 Zero means the frame pointer need not be set up (and parms
1102 may be accessed via the stack pointer) in functions that seem suitable.
1103 This is computed in `reload', in reload1.c. */
1104 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1106 /* Override this in other tm.h files to cope with various OS lossage
1107 requiring a frame pointer. */
1108 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1109 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1112 /* Make sure we can access arbitrary call frames. */
1113 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1115 /* Base register for access to arguments of the function. */
1116 #define ARG_POINTER_REGNUM 16
1118 /* Register in which static-chain is passed to a function.
1119 We do use ECX as static chain register for 32 bit ABI. On the
1120 64bit ABI, ECX is an argument register, so we use R10 instead. */
1121 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG)
1123 /* Register to hold the addressing base for position independent
1124 code access to data items. We don't use PIC pointer for 64bit
1125 mode. Define the regnum to dummy value to prevent gcc from
1126 pessimizing code dealing with EBX.
1128 To avoid clobbering a call-saved register unnecessarily, we renumber
1129 the pic register when possible. The change is visible after the
1130 prologue has been emitted. */
1132 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1134 #define PIC_OFFSET_TABLE_REGNUM \
1135 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1136 || !flag_pic ? INVALID_REGNUM \
1137 : reload_completed ? REGNO (pic_offset_table_rtx) \
1138 : REAL_PIC_OFFSET_TABLE_REGNUM)
1140 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1142 /* This is overridden by <cygwin.h>. */
1143 #define MS_AGGREGATE_RETURN 0
1145 /* This is overridden by <netware.h>. */
1146 #define KEEP_AGGREGATE_RETURN_POINTER 0
1148 /* Define the classes of registers for register constraints in the
1149 machine description. Also define ranges of constants.
1151 One of the classes must always be named ALL_REGS and include all hard regs.
1152 If there is more than one class, another class must be named NO_REGS
1153 and contain no registers.
1155 The name GENERAL_REGS must be the name of a class (or an alias for
1156 another name such as ALL_REGS). This is the class of registers
1157 that is allowed by "g" or "r" in a register constraint.
1158 Also, registers outside this class are allocated only when
1159 instructions express preferences for them.
1161 The classes must be numbered in nondecreasing order; that is,
1162 a larger-numbered class must never be contained completely
1163 in a smaller-numbered class.
1165 For any two classes, it is very desirable that there be another
1166 class that represents their union.
1168 It might seem that class BREG is unnecessary, since no useful 386
1169 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1170 and the "b" register constraint is useful in asms for syscalls.
1172 The flags, fpsr and fpcr registers are in no class. */
1177 AREG, DREG, CREG, BREG, SIREG, DIREG,
1178 AD_REGS, /* %eax/%edx for DImode */
1179 Q_REGS, /* %eax %ebx %ecx %edx */
1180 NON_Q_REGS, /* %esi %edi %ebp %esp */
1181 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1182 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1183 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1184 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1195 ALL_REGS, LIM_REG_CLASSES
1198 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1200 #define INTEGER_CLASS_P(CLASS) \
1201 reg_class_subset_p ((CLASS), GENERAL_REGS)
1202 #define FLOAT_CLASS_P(CLASS) \
1203 reg_class_subset_p ((CLASS), FLOAT_REGS)
1204 #define SSE_CLASS_P(CLASS) \
1205 reg_class_subset_p ((CLASS), SSE_REGS)
1206 #define MMX_CLASS_P(CLASS) \
1207 ((CLASS) == MMX_REGS)
1208 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1209 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1210 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1211 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1212 #define MAYBE_SSE_CLASS_P(CLASS) \
1213 reg_classes_intersect_p (SSE_REGS, (CLASS))
1214 #define MAYBE_MMX_CLASS_P(CLASS) \
1215 reg_classes_intersect_p (MMX_REGS, (CLASS))
1217 #define Q_CLASS_P(CLASS) \
1218 reg_class_subset_p ((CLASS), Q_REGS)
1220 /* Give names of register classes as strings for dump file. */
1222 #define REG_CLASS_NAMES \
1224 "AREG", "DREG", "CREG", "BREG", \
1227 "Q_REGS", "NON_Q_REGS", \
1231 "FP_TOP_REG", "FP_SECOND_REG", \
1236 "FP_TOP_SSE_REGS", \
1237 "FP_SECOND_SSE_REGS", \
1241 "FLOAT_INT_SSE_REGS", \
1244 /* Define which registers fit in which classes.
1245 This is an initializer for a vector of HARD_REG_SET
1246 of length N_REG_CLASSES. */
1248 #define REG_CLASS_CONTENTS \
1250 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1251 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1252 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1253 { 0x03, 0x0 }, /* AD_REGS */ \
1254 { 0x0f, 0x0 }, /* Q_REGS */ \
1255 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1256 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1257 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1258 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1259 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1260 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1261 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1262 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1263 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1264 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1265 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1266 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1267 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1268 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1269 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1270 { 0xffffffff,0x1fffff } \
1273 /* The same information, inverted:
1274 Return the class number of the smallest class containing
1275 reg number REGNO. This could be a conditional expression
1276 or could index an array. */
1278 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1280 /* When defined, the compiler allows registers explicitly used in the
1281 rtl to be used as spill registers but prevents the compiler from
1282 extending the lifetime of these registers. */
1284 #define SMALL_REGISTER_CLASSES 1
1286 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1288 #define GENERAL_REGNO_P(N) \
1289 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1291 #define GENERAL_REG_P(X) \
1292 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1294 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1296 #define REX_INT_REGNO_P(N) \
1297 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1298 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1300 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1301 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1302 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1303 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1305 #define X87_FLOAT_MODE_P(MODE) \
1306 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1308 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1309 #define SSE_REGNO_P(N) \
1310 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1311 || REX_SSE_REGNO_P (N))
1313 #define REX_SSE_REGNO_P(N) \
1314 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1316 #define SSE_REGNO(N) \
1317 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1319 #define SSE_FLOAT_MODE_P(MODE) \
1320 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1322 #define SSE_VEC_FLOAT_MODE_P(MODE) \
1323 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
1325 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1326 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1328 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1329 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1331 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1333 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1334 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1336 /* The class value for index registers, and the one for base regs. */
1338 #define INDEX_REG_CLASS INDEX_REGS
1339 #define BASE_REG_CLASS GENERAL_REGS
1341 /* Place additional restrictions on the register class to use when it
1342 is necessary to be able to hold a value of mode MODE in a reload
1343 register for which class CLASS would ordinarily be used. */
1345 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1346 ((MODE) == QImode && !TARGET_64BIT \
1347 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1348 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1351 /* Given an rtx X being reloaded into a reg required to be
1352 in class CLASS, return the class of reg to actually use.
1353 In general this is just CLASS; but on some machines
1354 in some cases it is preferable to use a more restrictive class.
1355 On the 80386 series, we prevent floating constants from being
1356 reloaded into floating registers (since no move-insn can do that)
1357 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1359 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1360 QImode must go into class Q_REGS.
1361 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1362 movdf to do mem-to-mem moves through integer regs. */
1364 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1365 ix86_preferred_reload_class ((X), (CLASS))
1367 /* Discourage putting floating-point values in SSE registers unless
1368 SSE math is being used, and likewise for the 387 registers. */
1370 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1371 ix86_preferred_output_reload_class ((X), (CLASS))
1373 /* If we are copying between general and FP registers, we need a memory
1374 location. The same is true for SSE and MMX registers. */
1375 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1376 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1378 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1379 There is no need to emit full 64 bit move on 64 bit targets
1380 for integral modes that can be moved using 32 bit move. */
1381 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1382 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1383 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1386 /* Return the maximum number of consecutive registers
1387 needed to represent mode MODE in a register of class CLASS. */
1388 /* On the 80386, this is the size of MODE in words,
1389 except in the FP regs, where a single reg is always enough. */
1390 #define CLASS_MAX_NREGS(CLASS, MODE) \
1391 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1392 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1393 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1394 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1396 /* A C expression whose value is nonzero if pseudos that have been
1397 assigned to registers of class CLASS would likely be spilled
1398 because registers of CLASS are needed for spill registers.
1400 The default value of this macro returns 1 if CLASS has exactly one
1401 register and zero otherwise. On most machines, this default
1402 should be used. Only define this macro to some other expression
1403 if pseudo allocated by `local-alloc.c' end up in memory because
1404 their hard registers were needed for spill registers. If this
1405 macro returns nonzero for those classes, those pseudos will only
1406 be allocated by `global.c', which knows how to reallocate the
1407 pseudo to another register. If there would not be another
1408 register available for reallocation, you should not change the
1409 definition of this macro since the only effect of such a
1410 definition would be to slow down register allocation. */
1412 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1413 (((CLASS) == AREG) \
1414 || ((CLASS) == DREG) \
1415 || ((CLASS) == CREG) \
1416 || ((CLASS) == BREG) \
1417 || ((CLASS) == AD_REGS) \
1418 || ((CLASS) == SIREG) \
1419 || ((CLASS) == DIREG) \
1420 || ((CLASS) == FP_TOP_REG) \
1421 || ((CLASS) == FP_SECOND_REG))
1423 /* Return a class of registers that cannot change FROM mode to TO mode. */
1425 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1426 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1428 /* Stack layout; function entry, exit and calling. */
1430 /* Define this if pushing a word on the stack
1431 makes the stack pointer a smaller address. */
1432 #define STACK_GROWS_DOWNWARD
1434 /* Define this to nonzero if the nominal address of the stack frame
1435 is at the high-address end of the local variables;
1436 that is, each additional local variable allocated
1437 goes at a more negative offset in the frame. */
1438 #define FRAME_GROWS_DOWNWARD 1
1440 /* Offset within stack frame to start allocating local variables at.
1441 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1442 first local allocated. Otherwise, it is the offset to the BEGINNING
1443 of the first local allocated. */
1444 #define STARTING_FRAME_OFFSET 0
1446 /* If we generate an insn to push BYTES bytes,
1447 this says how many the stack pointer really advances by.
1448 On 386, we have pushw instruction that decrements by exactly 2 no
1449 matter what the position was, there is no pushb.
1450 But as CIE data alignment factor on this arch is -4, we need to make
1451 sure all stack pointer adjustments are in multiple of 4.
1453 For 64bit ABI we round up to 8 bytes.
1456 #define PUSH_ROUNDING(BYTES) \
1458 ? (((BYTES) + 7) & (-8)) \
1459 : (((BYTES) + 3) & (-4)))
1461 /* If defined, the maximum amount of space required for outgoing arguments will
1462 be computed and placed into the variable
1463 `crtl->outgoing_args_size'. No space will be pushed onto the
1464 stack for each call; instead, the function prologue should increase the stack
1465 frame size by this amount. */
1467 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1469 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1470 instructions to pass outgoing arguments. */
1472 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1474 /* We want the stack and args grow in opposite directions, even if
1476 #define PUSH_ARGS_REVERSED 1
1478 /* Offset of first parameter from the argument pointer register value. */
1479 #define FIRST_PARM_OFFSET(FNDECL) 0
1481 /* Define this macro if functions should assume that stack space has been
1482 allocated for arguments even when their values are passed in registers.
1484 The value of this macro is the size, in bytes, of the area reserved for
1485 arguments passed in registers for the function represented by FNDECL.
1487 This space can be allocated by the caller, or be a part of the
1488 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1490 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1492 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) (ix86_function_type_abi (FNTYPE) == MS_ABI ? 1 : 0)
1494 /* Value is the number of bytes of arguments automatically
1495 popped when returning from a subroutine call.
1496 FUNDECL is the declaration node of the function (as a tree),
1497 FUNTYPE is the data type of the function (as a tree),
1498 or for a library call it is an identifier node for the subroutine name.
1499 SIZE is the number of bytes of arguments passed on the stack.
1501 On the 80386, the RTD insn may be used to pop them if the number
1502 of args is fixed, but if the number is variable then the caller
1503 must pop them all. RTD can't be used for library calls now
1504 because the library is compiled with the Unix compiler.
1505 Use of RTD is a selectable option, since it is incompatible with
1506 standard Unix calling sequences. If the option is not selected,
1507 the caller must always pop the args.
1509 The attribute stdcall is equivalent to RTD on a per module basis. */
1511 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1512 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1514 #define FUNCTION_VALUE_REGNO_P(N) \
1515 ix86_function_value_regno_p (N)
1517 /* Define how to find the value returned by a library function
1518 assuming the value has mode MODE. */
1520 #define LIBCALL_VALUE(MODE) \
1521 ix86_libcall_value (MODE)
1523 /* Define the size of the result block used for communication between
1524 untyped_call and untyped_return. The block contains a DImode value
1525 followed by the block used by fnsave and frstor. */
1527 #define APPLY_RESULT_SIZE (8+108)
1529 /* 1 if N is a possible register number for function argument passing. */
1530 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1532 /* Define a data type for recording info about an argument list
1533 during the scan of that argument list. This data type should
1534 hold all necessary information about the function itself
1535 and about the args processed so far, enough to enable macros
1536 such as FUNCTION_ARG to determine where the next arg should go. */
1538 typedef struct ix86_args {
1539 int words; /* # words passed so far */
1540 int nregs; /* # registers available for passing */
1541 int regno; /* next available register number */
1542 int fastcall; /* fastcall calling convention is used */
1543 int sse_words; /* # sse words passed so far */
1544 int sse_nregs; /* # sse registers available for passing */
1545 int warn_sse; /* True when we want to warn about SSE ABI. */
1546 int warn_mmx; /* True when we want to warn about MMX ABI. */
1547 int sse_regno; /* next available sse register number */
1548 int mmx_words; /* # mmx words passed so far */
1549 int mmx_nregs; /* # mmx registers available for passing */
1550 int mmx_regno; /* next available mmx register number */
1551 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1552 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1553 be passed in SSE registers. Otherwise 0. */
1554 int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1555 MS_ABI for ms abi. */
1558 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1559 for a call to a function whose data type is FNTYPE.
1560 For a library call, FNTYPE is 0. */
1562 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1563 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1565 /* Update the data in CUM to advance over an argument
1566 of mode MODE and data type TYPE.
1567 (TYPE is null for libcalls where that information may not be available.) */
1569 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1570 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1572 /* Define where to put the arguments to a function.
1573 Value is zero to push the argument on the stack,
1574 or a hard register in which to store the argument.
1576 MODE is the argument's machine mode.
1577 TYPE is the data type of the argument (as a tree).
1578 This is null for libcalls where that information may
1580 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1581 the preceding args and about the function being called.
1582 NAMED is nonzero if this argument is a named parameter
1583 (otherwise it is an extra parameter matching an ellipsis). */
1585 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1586 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1588 #define TARGET_ASM_FILE_END ix86_file_end
1589 #define NEED_INDICATE_EXEC_STACK 0
1591 /* Output assembler code to FILE to increment profiler label # LABELNO
1592 for profiling a function entry. */
1594 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1596 #define MCOUNT_NAME "_mcount"
1598 #define PROFILE_COUNT_REGISTER "edx"
1600 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1601 the stack pointer does not matter. The value is tested only in
1602 functions that have frame pointers.
1603 No definition is equivalent to always zero. */
1604 /* Note on the 386 it might be more efficient not to define this since
1605 we have to restore it ourselves from the frame pointer, in order to
1608 #define EXIT_IGNORE_STACK 1
1610 /* Output assembler code for a block containing the constant parts
1611 of a trampoline, leaving space for the variable parts. */
1613 /* On the 386, the trampoline contains two instructions:
1616 The trampoline is generated entirely at runtime. The operand of JMP
1617 is the address of FUNCTION relative to the instruction following the
1618 JMP (which is 5 bytes long). */
1620 /* Length in units of the trampoline for entering a nested function. */
1622 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1624 /* Emit RTL insns to initialize the variable parts of a trampoline.
1625 FNADDR is an RTX for the address of the function's pure code.
1626 CXT is an RTX for the static chain value for the function. */
1628 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1629 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1631 /* Definitions for register eliminations.
1633 This is an array of structures. Each structure initializes one pair
1634 of eliminable registers. The "from" register number is given first,
1635 followed by "to". Eliminations of the same "from" register are listed
1636 in order of preference.
1638 There are two registers that can always be eliminated on the i386.
1639 The frame pointer and the arg pointer can be replaced by either the
1640 hard frame pointer or to the stack pointer, depending upon the
1641 circumstances. The hard frame pointer is not used before reload and
1642 so it is not eligible for elimination. */
1644 #define ELIMINABLE_REGS \
1645 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1646 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1647 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1648 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1650 /* Given FROM and TO register numbers, say whether this elimination is
1653 #define CAN_ELIMINATE(FROM, TO) ix86_can_eliminate ((FROM), (TO))
1655 /* Define the offset between two registers, one to be eliminated, and the other
1656 its replacement, at the start of a routine. */
1658 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1659 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1661 /* Addressing modes, and classification of registers for them. */
1663 /* Macros to check register numbers against specific register classes. */
1665 /* These assume that REGNO is a hard or pseudo reg number.
1666 They give nonzero only if REGNO is a hard reg of the suitable class
1667 or a pseudo reg currently allocated to a suitable hard reg.
1668 Since they use reg_renumber, they are safe only once reg_renumber
1669 has been allocated, which happens in local-alloc.c. */
1671 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1672 ((REGNO) < STACK_POINTER_REGNUM \
1673 || REX_INT_REGNO_P (REGNO) \
1674 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1675 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1677 #define REGNO_OK_FOR_BASE_P(REGNO) \
1678 (GENERAL_REGNO_P (REGNO) \
1679 || (REGNO) == ARG_POINTER_REGNUM \
1680 || (REGNO) == FRAME_POINTER_REGNUM \
1681 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1683 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1684 and check its validity for a certain class.
1685 We have two alternate definitions for each of them.
1686 The usual definition accepts all pseudo regs; the other rejects
1687 them unless they have been allocated suitable hard regs.
1688 The symbol REG_OK_STRICT causes the latter definition to be used.
1690 Most source files want to accept pseudo regs in the hope that
1691 they will get allocated to the class that the insn wants them to be in.
1692 Source files for reload pass need to be strict.
1693 After reload, it makes no difference, since pseudo regs have
1694 been eliminated by then. */
1697 /* Non strict versions, pseudos are ok. */
1698 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1699 (REGNO (X) < STACK_POINTER_REGNUM \
1700 || REX_INT_REGNO_P (REGNO (X)) \
1701 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1703 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1704 (GENERAL_REGNO_P (REGNO (X)) \
1705 || REGNO (X) == ARG_POINTER_REGNUM \
1706 || REGNO (X) == FRAME_POINTER_REGNUM \
1707 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1709 /* Strict versions, hard registers only */
1710 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1711 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1713 #ifndef REG_OK_STRICT
1714 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1715 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1718 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1719 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1722 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1723 that is a valid memory address for an instruction.
1724 The MODE argument is the machine mode for the MEM expression
1725 that wants to use this address.
1727 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1728 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1730 See legitimize_pic_address in i386.c for details as to what
1731 constitutes a legitimate address when -fpic is used. */
1733 #define MAX_REGS_PER_ADDRESS 2
1735 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1737 /* Nonzero if the constant value X is a legitimate general operand.
1738 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1740 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1742 #ifdef REG_OK_STRICT
1743 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1745 if (legitimate_address_p ((MODE), (X), 1)) \
1750 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1752 if (legitimate_address_p ((MODE), (X), 0)) \
1758 /* If defined, a C expression to determine the base term of address X.
1759 This macro is used in only one place: `find_base_term' in alias.c.
1761 It is always safe for this macro to not be defined. It exists so
1762 that alias analysis can understand machine-dependent addresses.
1764 The typical use of this macro is to handle addresses containing
1765 a label_ref or symbol_ref within an UNSPEC. */
1767 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1769 /* Try machine-dependent ways of modifying an illegitimate address
1770 to be legitimate. If we find one, return the new, valid address.
1771 This macro is used in only one place: `memory_address' in explow.c.
1773 OLDX is the address as it was before break_out_memory_refs was called.
1774 In some cases it is useful to look at this to decide what needs to be done.
1776 MODE and WIN are passed so that this macro can use
1777 GO_IF_LEGITIMATE_ADDRESS.
1779 It is always safe for this macro to do nothing. It exists to recognize
1780 opportunities to optimize the output.
1782 For the 80386, we handle X+REG by loading X into a register R and
1783 using R+REG. R will go in a general reg and indexing will be used.
1784 However, if REG is a broken-out memory address or multiplication,
1785 nothing needs to be done because REG can certainly go in a general reg.
1787 When -fpic is used, special handling is needed for symbolic references.
1788 See comments by legitimize_pic_address in i386.c for details. */
1790 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1792 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1793 if (memory_address_p ((MODE), (X))) \
1797 /* Nonzero if the constant value X is a legitimate general operand
1798 when generating PIC code. It is given that flag_pic is on and
1799 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1801 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1803 #define SYMBOLIC_CONST(X) \
1804 (GET_CODE (X) == SYMBOL_REF \
1805 || GET_CODE (X) == LABEL_REF \
1806 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1808 /* Go to LABEL if ADDR (a legitimate address expression)
1809 has an effect that depends on the machine mode it is used for.
1810 On the 80386, only postdecrement and postincrement address depend thus
1811 (the amount of decrement or increment being the length of the operand).
1812 These are now caught in recog.c. */
1813 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1815 /* Max number of args passed in registers. If this is more than 3, we will
1816 have problems with ebx (register #4), since it is a caller save register and
1817 is also used as the pic register in ELF. So for now, don't allow more than
1818 3 registers to be passed in registers. */
1820 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1821 #define X86_64_REGPARM_MAX 6
1822 #define X64_REGPARM_MAX 4
1823 #define X86_32_REGPARM_MAX 3
1825 #define X86_64_SSE_REGPARM_MAX 8
1826 #define X64_SSE_REGPARM_MAX 4
1827 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0)
1829 #define REGPARM_MAX (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_REGPARM_MAX \
1830 : X86_64_REGPARM_MAX) \
1831 : X86_32_REGPARM_MAX)
1833 #define SSE_REGPARM_MAX (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_SSE_REGPARM_MAX \
1834 : X86_64_SSE_REGPARM_MAX) \
1835 : X86_32_SSE_REGPARM_MAX)
1837 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1840 /* Specify the machine mode that this machine uses
1841 for the index in the tablejump instruction. */
1842 #define CASE_VECTOR_MODE \
1843 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1845 /* Define this as 1 if `char' should by default be signed; else as 0. */
1846 #define DEFAULT_SIGNED_CHAR 1
1848 /* Max number of bytes we can move from memory to memory
1849 in one reasonably fast instruction. */
1852 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1853 move efficiently, as opposed to MOVE_MAX which is the maximum
1854 number of bytes we can move with a single instruction. */
1855 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1857 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1858 move-instruction pairs, we will do a movmem or libcall instead.
1859 Increasing the value will always make code faster, but eventually
1860 incurs high cost in increased code size.
1862 If you don't define this, a reasonable default is used. */
1864 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1866 /* If a clear memory operation would take CLEAR_RATIO or more simple
1867 move-instruction sequences, we will do a clrmem or libcall instead. */
1869 #define CLEAR_RATIO (optimize_size ? 2 : MIN (6, ix86_cost->move_ratio))
1871 /* Define if shifts truncate the shift count
1872 which implies one can omit a sign-extension or zero-extension
1873 of a shift count. */
1874 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1876 /* #define SHIFT_COUNT_TRUNCATED */
1878 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1879 is done just by pretending it is already truncated. */
1880 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1882 /* A macro to update M and UNSIGNEDP when an object whose type is
1883 TYPE and which has the specified mode and signedness is to be
1884 stored in a register. This macro is only called when TYPE is a
1887 On i386 it is sometimes useful to promote HImode and QImode
1888 quantities to SImode. The choice depends on target type. */
1890 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1892 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1893 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1897 /* Specify the machine mode that pointers have.
1898 After generation of rtl, the compiler makes no further distinction
1899 between pointers and any other objects of this machine mode. */
1900 #define Pmode (TARGET_64BIT ? DImode : SImode)
1902 /* A function address in a call instruction
1903 is a byte address (for indexing purposes)
1904 so give the MEM rtx a byte's mode. */
1905 #define FUNCTION_MODE QImode
1907 /* A C expression for the cost of moving data from a register in class FROM to
1908 one in class TO. The classes are expressed using the enumeration values
1909 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1910 interpreted relative to that.
1912 It is not required that the cost always equal 2 when FROM is the same as TO;
1913 on some machines it is expensive to move between registers if they are not
1914 general registers. */
1916 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1917 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1919 /* A C expression for the cost of moving data of mode M between a
1920 register and memory. A value of 2 is the default; this cost is
1921 relative to those in `REGISTER_MOVE_COST'.
1923 If moving between registers and memory is more expensive than
1924 between two registers, you should define this macro to express the
1927 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1928 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1930 /* A C expression for the cost of a branch instruction. A value of 1
1931 is the default; other values are interpreted relative to that. */
1933 #define BRANCH_COST ix86_branch_cost
1935 /* Define this macro as a C expression which is nonzero if accessing
1936 less than a word of memory (i.e. a `char' or a `short') is no
1937 faster than accessing a word of memory, i.e., if such access
1938 require more than one instruction or if there is no difference in
1939 cost between byte and (aligned) word loads.
1941 When this macro is not defined, the compiler will access a field by
1942 finding the smallest containing object; when it is defined, a
1943 fullword load will be used if alignment permits. Unless bytes
1944 accesses are faster than word accesses, using word accesses is
1945 preferable since it may eliminate subsequent memory access if
1946 subsequent accesses occur to other fields in the same word of the
1947 structure, but to different bytes. */
1949 #define SLOW_BYTE_ACCESS 0
1951 /* Nonzero if access to memory by shorts is slow and undesirable. */
1952 #define SLOW_SHORT_ACCESS 0
1954 /* Define this macro to be the value 1 if unaligned accesses have a
1955 cost many times greater than aligned accesses, for example if they
1956 are emulated in a trap handler.
1958 When this macro is nonzero, the compiler will act as if
1959 `STRICT_ALIGNMENT' were nonzero when generating code for block
1960 moves. This can cause significantly more instructions to be
1961 produced. Therefore, do not set this macro nonzero if unaligned
1962 accesses only add a cycle or two to the time for a memory access.
1964 If the value of this macro is always zero, it need not be defined. */
1966 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1968 /* Define this macro if it is as good or better to call a constant
1969 function address than to call an address kept in a register.
1971 Desirable on the 386 because a CALL with a constant address is
1972 faster than one with a register address. */
1974 #define NO_FUNCTION_CSE
1976 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1977 return the mode to be used for the comparison.
1979 For floating-point equality comparisons, CCFPEQmode should be used.
1980 VOIDmode should be used in all other cases.
1982 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1983 possible, to allow for more combinations. */
1985 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1987 /* Return nonzero if MODE implies a floating point inequality can be
1990 #define REVERSIBLE_CC_MODE(MODE) 1
1992 /* A C expression whose value is reversed condition code of the CODE for
1993 comparison done in CC_MODE mode. */
1994 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1997 /* Control the assembler format that we output, to the extent
1998 this does not vary between assemblers. */
2000 /* How to refer to registers in assembler output.
2001 This sequence is indexed by compiler's hard-register-number (see above). */
2003 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2004 For non floating point regs, the following are the HImode names.
2006 For float regs, the stack top is sometimes referred to as "%st(0)"
2007 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2009 #define HI_REGISTER_NAMES \
2010 {"ax","dx","cx","bx","si","di","bp","sp", \
2011 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2012 "argp", "flags", "fpsr", "fpcr", "frame", \
2013 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2014 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2015 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2016 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2018 #define REGISTER_NAMES HI_REGISTER_NAMES
2020 /* Table of additional register names to use in user input. */
2022 #define ADDITIONAL_REGISTER_NAMES \
2023 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2024 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2025 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2026 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2027 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2028 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2030 /* Note we are omitting these since currently I don't know how
2031 to get gcc to use these, since they want the same but different
2032 number as al, and ax.
2035 #define QI_REGISTER_NAMES \
2036 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2038 /* These parallel the array above, and can be used to access bits 8:15
2039 of regs 0 through 3. */
2041 #define QI_HIGH_REGISTER_NAMES \
2042 {"ah", "dh", "ch", "bh", }
2044 /* How to renumber registers for dbx and gdb. */
2046 #define DBX_REGISTER_NUMBER(N) \
2047 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2049 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2050 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2051 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2053 /* Before the prologue, RA is at 0(%esp). */
2054 #define INCOMING_RETURN_ADDR_RTX \
2055 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2057 /* After the prologue, RA is at -4(AP) in the current frame. */
2058 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2060 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2061 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2063 /* PC is dbx register 8; let's use that column for RA. */
2064 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2066 /* Before the prologue, the top of the frame is at 4(%esp). */
2067 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2069 /* Describe how we implement __builtin_eh_return. */
2070 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2071 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2074 /* Select a format to encode pointers in exception handling data. CODE
2075 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2076 true if the symbol may be affected by dynamic relocations.
2078 ??? All x86 object file formats are capable of representing this.
2079 After all, the relocation needed is the same as for the call insn.
2080 Whether or not a particular assembler allows us to enter such, I
2081 guess we'll have to see. */
2082 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2083 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2085 /* This is how to output an insn to push a register on the stack.
2086 It need not be very fast code. */
2088 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2091 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2092 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2094 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2097 /* This is how to output an insn to pop a register from the stack.
2098 It need not be very fast code. */
2100 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2103 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2104 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2106 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2109 /* This is how to output an element of a case-vector that is absolute. */
2111 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2112 ix86_output_addr_vec_elt ((FILE), (VALUE))
2114 /* This is how to output an element of a case-vector that is relative. */
2116 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2117 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2119 /* Under some conditions we need jump tables in the text section,
2120 because the assembler cannot handle label differences between
2121 sections. This is the case for x86_64 on Mach-O for example. */
2123 #define JUMP_TABLES_IN_TEXT_SECTION \
2124 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2125 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2127 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2128 and switch back. For x86 we do this only to save a few bytes that
2129 would otherwise be unused in the text section. */
2130 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2131 asm (SECTION_OP "\n\t" \
2132 "call " USER_LABEL_PREFIX #FUNC "\n" \
2133 TEXT_SECTION_ASM_OP);
2135 /* Print operand X (an rtx) in assembler syntax to file FILE.
2136 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2137 Effect of various CODE letters is described in i386.c near
2138 print_operand function. */
2140 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2141 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
2143 #define PRINT_OPERAND(FILE, X, CODE) \
2144 print_operand ((FILE), (X), (CODE))
2146 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2147 print_operand_address ((FILE), (ADDR))
2149 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2151 if (! output_addr_const_extra (FILE, (X))) \
2155 /* Which processor to schedule for. The cpu attribute defines a list that
2156 mirrors this list, so changes to i386.md must be made at the same time. */
2160 PROCESSOR_I386 = 0, /* 80386 */
2161 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2163 PROCESSOR_PENTIUMPRO,
2171 PROCESSOR_GENERIC32,
2172 PROCESSOR_GENERIC64,
2177 extern enum processor_type ix86_tune;
2178 extern enum processor_type ix86_arch;
2186 extern enum fpmath_unit ix86_fpmath;
2195 extern enum tls_dialect ix86_tls_dialect;
2198 CM_32, /* The traditional 32-bit ABI. */
2199 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2200 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2201 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2202 CM_LARGE, /* No assumptions. */
2203 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2204 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2205 CM_LARGE_PIC /* No assumptions. */
2208 extern enum cmodel ix86_cmodel;
2210 /* Size of the RED_ZONE area. */
2211 #define RED_ZONE_SIZE 128
2212 /* Reserved area of the red zone for temporaries. */
2213 #define RED_ZONE_RESERVE 8
2220 extern enum asm_dialect ix86_asm_dialect;
2221 extern unsigned int ix86_preferred_stack_boundary;
2222 extern unsigned int ix86_incoming_stack_boundary;
2223 extern int ix86_branch_cost, ix86_section_threshold;
2225 /* Smallest class containing REGNO. */
2226 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2228 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2229 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2230 extern rtx ix86_compare_emitted;
2232 /* To properly truncate FP values into integers, we need to set i387 control
2233 word. We can't emit proper mode switching code before reload, as spills
2234 generated by reload may truncate values incorrectly, but we still can avoid
2235 redundant computation of new control word by the mode switching pass.
2236 The fldcw instructions are still emitted redundantly, but this is probably
2237 not going to be noticeable problem, as most CPUs do have fast path for
2240 The machinery is to emit simple truncation instructions and split them
2241 before reload to instructions having USEs of two memory locations that
2242 are filled by this code to old and new control word.
2244 Post-reload pass may be later used to eliminate the redundant fildcw if
2256 enum ix86_stack_slot
2265 MAX_386_STACK_LOCALS
2268 /* Define this macro if the port needs extra instructions inserted
2269 for mode switching in an optimizing compilation. */
2271 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2272 ix86_optimize_mode_switching[(ENTITY)]
2274 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2275 initializer for an array of integers. Each initializer element N
2276 refers to an entity that needs mode switching, and specifies the
2277 number of different modes that might need to be set for this
2278 entity. The position of the initializer in the initializer -
2279 starting counting at zero - determines the integer that is used to
2280 refer to the mode-switched entity in question. */
2282 #define NUM_MODES_FOR_MODE_SWITCHING \
2283 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2285 /* ENTITY is an integer specifying a mode-switched entity. If
2286 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2287 return an integer value not larger than the corresponding element
2288 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2289 must be switched into prior to the execution of INSN. */
2291 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2293 /* This macro specifies the order in which modes for ENTITY are
2294 processed. 0 is the highest priority. */
2296 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2298 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2299 is the set of hard registers live at the point where the insn(s)
2300 are to be inserted. */
2302 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2303 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2304 ? emit_i387_cw_initialization (MODE), 0 \
2308 /* Avoid renaming of stack registers, as doing so in combination with
2309 scheduling just increases amount of live registers at time and in
2310 the turn amount of fxch instructions needed.
2312 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2314 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2315 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2318 #define FASTCALL_PREFIX '@'
2320 struct machine_function GTY(())
2322 struct stack_local_entry *stack_locals;
2323 const char *some_ld_name;
2324 int save_varrargs_registers;
2325 int accesses_prev_frame;
2326 int optimize_mode_switching[MAX_386_ENTITIES];
2328 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2329 expander to determine the style used. */
2330 int use_fast_prologue_epilogue;
2331 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2333 int use_fast_prologue_epilogue_nregs;
2334 /* If true, the current function needs the default PIC register, not
2335 an alternate register (on x86) and must not use the red zone (on
2336 x86_64), even if it's a leaf function. We don't want the
2337 function to be regarded as non-leaf because TLS calls need not
2338 affect register allocation. This flag is set when a TLS call
2339 instruction is expanded within a function, and never reset, even
2340 if all such instructions are optimized away. Use the
2341 ix86_current_function_calls_tls_descriptor macro for a better
2343 int tls_descriptor_call_expanded_p;
2344 /* This value is used for amd64 targets and specifies the current abi
2345 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2349 #define ix86_stack_locals (cfun->machine->stack_locals)
2350 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2351 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2352 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2353 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2354 (cfun->machine->tls_descriptor_call_expanded_p)
2355 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2356 calls are optimized away, we try to detect cases in which it was
2357 optimized away. Since such instructions (use (reg REG_SP)), we can
2358 verify whether there's any such instruction live by testing that
2360 #define ix86_current_function_calls_tls_descriptor \
2361 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2363 /* Control behavior of x86_file_start. */
2364 #define X86_FILE_START_VERSION_DIRECTIVE false
2365 #define X86_FILE_START_FLTUSED false
2367 /* Flag to mark data that is in the large address area. */
2368 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2369 #define SYMBOL_REF_FAR_ADDR_P(X) \
2370 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2372 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2373 have defined always, to avoid ifdefing. */
2374 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2375 #define SYMBOL_REF_DLLIMPORT_P(X) \
2376 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2378 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2379 #define SYMBOL_REF_DLLEXPORT_P(X) \
2380 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2382 /* Model costs for vectorizer. */
2384 /* Cost of conditional branch. */
2385 #undef TARG_COND_BRANCH_COST
2386 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost
2388 /* Enum through the target specific extra va_list types. Please, do not
2389 iterate the base va_list type name. */
2390 #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \
2391 (!TARGET_64BIT ? 0 : ix86_enum_va_list (IDX, PNAME, PTYPE))
2393 /* Cost of any scalar operation, excluding load and store. */
2394 #undef TARG_SCALAR_STMT_COST
2395 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost
2397 /* Cost of scalar load. */
2398 #undef TARG_SCALAR_LOAD_COST
2399 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost
2401 /* Cost of scalar store. */
2402 #undef TARG_SCALAR_STORE_COST
2403 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost
2405 /* Cost of any vector operation, excluding load, store or vector to scalar
2407 #undef TARG_VEC_STMT_COST
2408 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost
2410 /* Cost of vector to scalar operation. */
2411 #undef TARG_VEC_TO_SCALAR_COST
2412 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost
2414 /* Cost of scalar to vector operation. */
2415 #undef TARG_SCALAR_TO_VEC_COST
2416 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost
2418 /* Cost of aligned vector load. */
2419 #undef TARG_VEC_LOAD_COST
2420 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost
2422 /* Cost of misaligned vector load. */
2423 #undef TARG_VEC_UNALIGNED_LOAD_COST
2424 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost
2426 /* Cost of vector store. */
2427 #undef TARG_VEC_STORE_COST
2428 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost
2430 /* Cost of conditional taken branch for vectorizer cost model. */
2431 #undef TARG_COND_TAKEN_BRANCH_COST
2432 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost
2434 /* Cost of conditional not taken branch for vectorizer cost model. */
2435 #undef TARG_COND_NOT_TAKEN_BRANCH_COST
2436 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost