1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs {
54 int add; /* cost of an add instruction */
55 int lea; /* cost of a lea instruction */
56 int shift_var; /* variable shift costs */
57 int shift_const; /* constant shift costs */
58 int mult_init; /* cost of starting a multiply */
59 int mult_bit; /* cost of multiply per each bit set */
60 int divide; /* cost of a divide/mod */
61 int large_insn; /* insns larger than this cost more */
62 int move_ratio; /* The threshold of number of scalar
63 memory-to-memory move insns. */
64 int movzbl_load; /* cost of loading using movzbl */
65 int int_load[3]; /* cost of loading integer registers
66 in QImode, HImode and SImode relative
67 to reg-reg move (2). */
68 int int_store[3]; /* cost of storing integer register
69 in QImode, HImode and SImode */
70 int fp_move; /* cost of reg,reg fld/fst */
71 int fp_load[3]; /* cost of loading FP register
72 in SFmode, DFmode and XFmode */
73 int fp_store[3]; /* cost of storing FP register
74 in SFmode, DFmode and XFmode */
75 int mmx_move; /* cost of moving MMX register. */
76 int mmx_load[2]; /* cost of loading MMX register
77 in SImode and DImode */
78 int mmx_store[2]; /* cost of storing MMX register
79 in SImode and DImode */
80 int sse_move; /* cost of moving SSE register. */
81 int sse_load[3]; /* cost of loading SSE register
82 in SImode, DImode and TImode*/
83 int sse_store[3]; /* cost of storing SSE register
84 in SImode, DImode and TImode*/
85 int mmxsse_to_integer; /* cost of moving mmxsse register to
86 integer and vice versa. */
89 extern struct processor_costs *ix86_cost;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #define TARGET_CPU_DEFAULT 0
103 /* Masks for the -m switches */
104 #define MASK_80387 0x00000001 /* Hardware floating point */
105 #define MASK_RTD 0x00000002 /* Use ret that pops args */
106 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
107 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
108 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
109 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
110 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
111 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
112 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
113 #define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */
114 #define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */
115 #define MASK_NO_PUSH_ARGS 0x00004000 /* Use push instructions */
116 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
117 #define MASK_MMX 0x00010000 /* Support MMX regs/builtins */
118 #define MASK_SSE 0x00020000 /* Support SSE regs/builtins */
119 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
120 #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
121 #define MASK_MIX_SSE_I387 0x00100000 /* Mix SSE and i387 instructions */
122 #define MASK_64BIT 0x00200000 /* Produce 64bit code */
124 /* Temporary codegen switches */
125 #define MASK_INTEL_SYNTAX 0x00000200
126 #define MASK_DEBUG_ARG 0x00000400 /* function_arg */
127 #define MASK_DEBUG_ADDR 0x00000800 /* GO_IF_LEGITIMATE_ADDRESS */
129 /* Use the floating point instructions */
130 #define TARGET_80387 (target_flags & MASK_80387)
132 /* Compile using ret insn that pops args.
133 This will not work unless you use prototypes at least
134 for all functions that can take varying numbers of args. */
135 #define TARGET_RTD (target_flags & MASK_RTD)
137 /* Align doubles to a two word boundary. This breaks compatibility with
138 the published ABI's for structures containing doubles, but produces
139 faster code on the pentium. */
140 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
142 /* Use push instructions to save outgoing args. */
143 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
145 /* Accumulate stack adjustments to prologue/epilogue. */
146 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
147 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
149 /* Put uninitialized locals into bss, not data.
150 Meaningful only on svr3. */
151 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
153 /* Use IEEE floating point comparisons. These handle correctly the cases
154 where the result of a comparison is unordered. Normally SIGFPE is
155 generated in such cases, in which case this isn't needed. */
156 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
158 /* Functions that return a floating point value may return that value
159 in the 387 FPU or in 386 integer registers. If set, this flag causes
160 the 387 to be used, which is compatible with most calling conventions. */
161 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
163 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
164 This mode wastes cache, but avoid missaligned data accesses and simplifies
165 address calculations. */
166 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
168 /* Disable generation of FP sin, cos and sqrt operations for 387.
169 This is because FreeBSD lacks these in the math-emulator-code */
170 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
172 /* Don't create frame pointers for leaf functions */
173 #define TARGET_OMIT_LEAF_FRAME_POINTER \
174 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
176 /* Debug GO_IF_LEGITIMATE_ADDRESS */
177 #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
179 /* Debug FUNCTION_ARG macros */
180 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
182 /* 64bit Sledgehammer mode */
183 #define TARGET_64BIT (target_flags & MASK_64BIT)
185 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
186 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
187 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
188 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
189 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
190 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
191 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
193 #define CPUMASK (1 << ix86_cpu)
194 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
195 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
196 extern const int x86_unroll_strlen;
197 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
198 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
199 extern const int x86_use_cltd, x86_read_modify_write;
200 extern const int x86_read_modify, x86_split_long_moves;
201 extern const int x86_promote_QImode, x86_single_stringop;
202 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
203 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
204 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
205 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
207 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
208 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
209 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
210 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
211 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
212 /* For sane SSE instruction set generation we need fcomi instruction. It is
213 safe to enable all CMOVE instructions. */
214 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
215 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
216 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
217 #define TARGET_USE_SAHF (x86_use_sahf & CPUMASK)
218 #define TARGET_MOVX (x86_movx & CPUMASK)
219 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
220 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
221 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
222 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
223 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
224 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
225 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
226 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
227 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
228 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
229 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
230 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
231 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
232 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
233 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
234 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
235 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
236 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
237 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
238 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
239 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
241 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
243 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
244 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
246 #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
248 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
249 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
250 #define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
251 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
253 #define TARGET_SWITCHES \
254 { { "80387", MASK_80387, N_("Use hardware fp") }, \
255 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
256 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
257 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
258 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
259 { "386", 0, N_("Same as -mcpu=i386") }, \
260 { "486", 0, N_("Same as -mcpu=i486") }, \
261 { "pentium", 0, N_("Same as -mcpu=pentium") }, \
262 { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
264 N_("Alternate calling convention") }, \
265 { "no-rtd", -MASK_RTD, \
266 N_("Use normal calling convention") }, \
267 { "align-double", MASK_ALIGN_DOUBLE, \
268 N_("Align some doubles on dword boundary") }, \
269 { "no-align-double", -MASK_ALIGN_DOUBLE, \
270 N_("Align doubles on word boundary") }, \
271 { "svr3-shlib", MASK_SVR3_SHLIB, \
272 N_("Uninitialized locals in .bss") }, \
273 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
274 N_("Uninitialized locals in .data") }, \
275 { "ieee-fp", MASK_IEEE_FP, \
276 N_("Use IEEE math for fp comparisons") }, \
277 { "no-ieee-fp", -MASK_IEEE_FP, \
278 N_("Do not use IEEE math for fp comparisons") }, \
279 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
280 N_("Return values of functions in FPU registers") }, \
281 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
282 N_("Do not return values of functions in FPU registers")}, \
283 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
284 N_("Do not generate sin, cos, sqrt for FPU") }, \
285 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
286 N_("Generate sin, cos, sqrt for FPU")}, \
287 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
288 N_("Omit the frame pointer in leaf functions") }, \
289 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
290 { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
291 { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
292 { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
293 { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
294 { "stack-arg-probe", MASK_STACK_PROBE, \
295 N_("Enable stack probing") }, \
296 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
297 { "windows", 0, 0 /* undocumented */ }, \
298 { "dll", 0, 0 /* undocumented */ }, \
299 { "intel-syntax", MASK_INTEL_SYNTAX, \
300 N_("Emit Intel syntax assembler opcodes") }, \
301 { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
302 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
303 N_("Align destination of the string operations") }, \
304 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
305 N_("Do not align destination of the string operations") }, \
306 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
307 N_("Inline all known string operations") }, \
308 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
309 N_("Do not inline all known string operations") }, \
310 { "push-args", -MASK_NO_PUSH_ARGS, \
311 N_("Use push instructions to save outgoing arguments") }, \
312 { "no-push-args", MASK_NO_PUSH_ARGS, \
313 N_("Do not use push instructions to save outgoing arguments") }, \
314 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
315 N_("Use push instructions to save outgoing arguments") }, \
316 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
317 N_("Do not use push instructions to save outgoing arguments") }, \
318 { "mmx", MASK_MMX, N_("Support MMX builtins") }, \
319 { "no-mmx", -MASK_MMX, \
320 N_("Do not support MMX builtins") }, \
322 N_("Support MMX and SSE builtins and code generation") }, \
323 { "no-sse", -MASK_SSE, \
324 N_("Do not support MMX and SSE builtins and code generation") }, \
325 { "sse2", MASK_SSE2, \
326 N_("Support MMX, SSE and SSE2 builtins and code generation") }, \
327 { "no-sse2", -MASK_SSE2, \
328 N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
329 { "mix-sse-i387", MASK_MIX_SSE_I387, \
330 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
331 { "nomix-sse-i387", -MASK_MIX_SSE_I387, \
332 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
333 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
334 N_("sizeof(long double) is 16.") }, \
335 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
336 N_("sizeof(long double) is 12.") }, \
337 { "64", MASK_64BIT, \
338 N_("Generate 64bit x86-64 code") }, \
339 { "32", -MASK_64BIT, \
340 N_("Generate 32bit i386 code") }, \
342 { "", TARGET_DEFAULT, 0 }}
344 #ifdef TARGET_64BIT_DEFAULT
345 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
347 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
350 /* Which processor to schedule for. The cpu attribute defines a list that
351 mirrors this list, so changes to i386.md must be made at the same time. */
355 PROCESSOR_I386, /* 80386 */
356 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
358 PROCESSOR_PENTIUMPRO,
365 extern enum processor_type ix86_cpu;
367 extern int ix86_arch;
369 /* This macro is similar to `TARGET_SWITCHES' but defines names of
370 command options that have values. Its definition is an
371 initializer with a subgrouping for each command option.
373 Each subgrouping contains a string constant, that defines the
374 fixed part of the option name, and the address of a variable. The
375 variable, type `char *', is set to the variable part of the given
376 option if the fixed part matches. The actual option name is made
377 by appending `-m' to the specified name. */
378 #define TARGET_OPTIONS \
379 { { "cpu=", &ix86_cpu_string, \
380 N_("Schedule code for given CPU")}, \
381 { "arch=", &ix86_arch_string, \
382 N_("Generate code for given CPU")}, \
383 { "regparm=", &ix86_regparm_string, \
384 N_("Number of registers used to pass integer arguments") }, \
385 { "align-loops=", &ix86_align_loops_string, \
386 N_("Loop code aligned to this power of 2") }, \
387 { "align-jumps=", &ix86_align_jumps_string, \
388 N_("Jump targets are aligned to this power of 2") }, \
389 { "align-functions=", &ix86_align_funcs_string, \
390 N_("Function starts are aligned to this power of 2") }, \
391 { "preferred-stack-boundary=", \
392 &ix86_preferred_stack_boundary_string, \
393 N_("Attempt to keep stack aligned to this power of 2") }, \
394 { "branch-cost=", &ix86_branch_cost_string, \
395 N_("Branches are this expensive (1-5, arbitrary units)") }, \
399 /* Sometimes certain combinations of command options do not make
400 sense on a particular target machine. You can define a macro
401 `OVERRIDE_OPTIONS' to take account of this. This macro, if
402 defined, is executed once just after all the command options have
405 Don't use this macro to turn on various extra optimizations for
406 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
408 #define OVERRIDE_OPTIONS override_options ()
410 /* These are meant to be redefined in the host dependent files */
411 #define SUBTARGET_SWITCHES
412 #define SUBTARGET_OPTIONS
414 /* Define this to change the optimizations performed by default. */
415 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
417 /* Specs for the compiler proper */
420 #define CC1_CPU_SPEC "\
423 %n`-mpentium' is deprecated. Use `-march' or `-mcpu' instead.\n} \
425 %n`-mpentium' is deprecated. Use `-march' or `-mcpu' instead.\n} \
426 %{mpentium:-mcpu=pentium \
427 %n`-mpentium' is deprecated. Use `-march' or `-mcpu' instead.\n} \
428 %{mpentiumpro:-mcpu=pentiumpro \
429 %n`-mpentiumpro' is deprecated. Use `-march' or `-mcpu' instead.\n}}"
432 #ifndef CPP_CPU_DEFAULT_SPEC
433 #if TARGET_CPU_DEFAULT == 1
434 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
436 #if TARGET_CPU_DEFAULT == 2
437 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
439 #if TARGET_CPU_DEFAULT == 3
440 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
442 #if TARGET_CPU_DEFAULT == 4
443 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
445 #if TARGET_CPU_DEFAULT == 5
446 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
448 #if TARGET_CPU_DEFAULT == 6
449 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
451 #ifndef CPP_CPU_DEFAULT_SPEC
452 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
454 #endif /* CPP_CPU_DEFAULT_SPEC */
457 #define CPP_CPU_SPEC "\
458 -Acpu=i386 -Amachine=i386 \
459 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 -D__i386__ \
460 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
461 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
462 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
463 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
464 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
465 -D__pentiumpro -D__pentiumpro__ \
466 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
467 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
468 %{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
469 %{mpentium4=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
470 %{m386|mcpu=i386:-D__tune_i386__ }\
471 %{m486|mcpu=i486:-D__tune_i486__ }\
472 %{mpentium|mcpu=pentium|mcpu=i586:-D__tune_i586__ -D__tune_pentium__ }\
473 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_i686__ -D__tune_pentiumpro__ }\
474 %{mcpu=k6:-D__tune_k6__ }\
475 %{mcpu=athlon:-D__tune_athlon__ }\
476 %{mcpu=pentium4:-D__tune_pentium4__ }\
477 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
481 #define CC1_SPEC "%(cc1_cpu) "
484 /* This macro defines names of additional specifications to put in the
485 specs that can be used in various specifications like CC1_SPEC. Its
486 definition is an initializer with a subgrouping for each command option.
488 Each subgrouping contains a string constant, that defines the
489 specification name, and a string constant that used by the GNU CC driver
492 Do not define this macro if it does not need to do anything. */
494 #ifndef SUBTARGET_EXTRA_SPECS
495 #define SUBTARGET_EXTRA_SPECS
498 #define EXTRA_SPECS \
499 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
500 { "cpp_cpu", CPP_CPU_SPEC }, \
501 { "cc1_cpu", CC1_CPU_SPEC }, \
502 SUBTARGET_EXTRA_SPECS
504 /* target machine storage layout */
506 /* Define for XFmode or TFmode extended real floating point support.
507 This will automatically cause REAL_ARITHMETIC to be defined.
509 The XFmode is specified by i386 ABI, while TFmode may be faster
510 due to alignment and simplifications in the address calculations.
512 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
513 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
515 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
517 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
519 /* Tell real.c that this is the 80-bit Intel extended float format
520 packaged in a 128-bit or 96bit entity. */
521 #define INTEL_EXTENDED_IEEE_FORMAT
524 #define SHORT_TYPE_SIZE 16
525 #define INT_TYPE_SIZE 32
526 #define FLOAT_TYPE_SIZE 32
527 #define LONG_TYPE_SIZE BITS_PER_WORD
528 #define MAX_WCHAR_TYPE_SIZE 32
529 #define MAX_LONG_TYPE_SIZE 64
530 #define DOUBLE_TYPE_SIZE 64
531 #define LONG_LONG_TYPE_SIZE 64
533 /* Define if you don't want extended real, but do want to use the
534 software floating point emulator for REAL_ARITHMETIC and
535 decimal <-> binary conversion. */
536 /* #define REAL_ARITHMETIC */
538 /* Define this if most significant byte of a word is the lowest numbered. */
539 /* That is true on the 80386. */
541 #define BITS_BIG_ENDIAN 0
543 /* Define this if most significant byte of a word is the lowest numbered. */
544 /* That is not true on the 80386. */
545 #define BYTES_BIG_ENDIAN 0
547 /* Define this if most significant word of a multiword number is the lowest
549 /* Not true for 80386 */
550 #define WORDS_BIG_ENDIAN 0
552 /* number of bits in an addressable storage unit */
553 #define BITS_PER_UNIT 8
555 /* Width in bits of a "word", which is the contents of a machine register.
556 Note that this is not necessarily the width of data type `int';
557 if using 16-bit ints on a 80386, this would still be 32.
558 But on a machine with 16-bit registers, this would be 16. */
559 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
560 #define MAX_BITS_PER_WORD 64
562 /* Width of a word, in units (bytes). */
563 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
564 #define MIN_UNITS_PER_WORD 4
566 /* Width in bits of a pointer.
567 See also the macro `Pmode' defined below. */
568 #define POINTER_SIZE BITS_PER_WORD
570 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
571 #define PARM_BOUNDARY BITS_PER_WORD
573 /* Boundary (in *bits*) on which stack pointer should be aligned. */
574 #define STACK_BOUNDARY BITS_PER_WORD
576 /* Boundary (in *bits*) on which the stack pointer preferrs to be
577 aligned; the compiler cannot rely on having this alignment. */
578 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
580 /* Allocation boundary for the code of a function. */
581 #define FUNCTION_BOUNDARY \
582 (1 << ((ix86_align_funcs >= 0 ? ix86_align_funcs : -ix86_align_funcs) + 3))
584 /* Alignment of field after `int : 0' in a structure. */
586 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
588 /* Minimum size in bits of the largest boundary to which any
589 and all fundamental data types supported by the hardware
590 might need to be aligned. No data type wants to be aligned
593 Pentium+ preferrs DFmode values to be alignmed to 64 bit boundary
594 and Pentium Pro XFmode values at 128 bit boundaries. */
596 #define BIGGEST_ALIGNMENT 128
598 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
599 #define ALIGN_MODE_128(MODE) \
600 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
601 || (MODE) == V4SFmode || (MODE) == V4SImode)
603 /* The published ABIs say that doubles should be aligned on word
604 boundaries, so lower the aligment for structure fields unless
605 -malign-double is set. */
606 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
607 constant. Use the smaller value in that context. */
608 #ifndef IN_TARGET_LIBS
609 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
611 #define BIGGEST_FIELD_ALIGNMENT 32
614 /* If defined, a C expression to compute the alignment given to a
615 constant that is being placed in memory. EXP is the constant
616 and ALIGN is the alignment that the object would ordinarily have.
617 The value of this macro is used instead of that alignment to align
620 If this macro is not defined, then ALIGN is used.
622 The typical use of this macro is to increase alignment for string
623 constants to be word aligned so that `strcpy' calls that copy
624 constants can be done inline. */
626 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
628 /* If defined, a C expression to compute the alignment for a static
629 variable. TYPE is the data type, and ALIGN is the alignment that
630 the object would ordinarily have. The value of this macro is used
631 instead of that alignment to align the object.
633 If this macro is not defined, then ALIGN is used.
635 One use of this macro is to increase alignment of medium-size
636 data to make it all fit in fewer cache lines. Another is to
637 cause character arrays to be word-aligned so that `strcpy' calls
638 that copy constants to character arrays can be done inline. */
640 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
642 /* If defined, a C expression to compute the alignment for a local
643 variable. TYPE is the data type, and ALIGN is the alignment that
644 the object would ordinarily have. The value of this macro is used
645 instead of that alignment to align the object.
647 If this macro is not defined, then ALIGN is used.
649 One use of this macro is to increase alignment of medium-size
650 data to make it all fit in fewer cache lines. */
652 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
654 /* Set this non-zero if move instructions will actually fail to work
655 when given unaligned data. */
656 #define STRICT_ALIGNMENT 0
658 /* If bit field type is int, don't let it cross an int,
659 and give entire struct the alignment of an int. */
660 /* Required on the 386 since it doesn't have bitfield insns. */
661 #define PCC_BITFIELD_TYPE_MATTERS 1
663 /* Align loop starts for optimal branching. */
664 #define LOOP_ALIGN(LABEL) \
665 (ix86_align_loops < 0 ? -ix86_align_loops : ix86_align_loops)
666 #define LOOP_ALIGN_MAX_SKIP \
667 (ix86_align_loops < -3 ? (1<<(-ix86_align_loops-1))-1 : 0)
669 /* This is how to align an instruction for optimal branching. */
670 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
671 (ix86_align_jumps < 0 ? -ix86_align_jumps : ix86_align_jumps)
672 #define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP \
673 (ix86_align_jumps < -3 ? (1<<(-ix86_align_jumps-1))-1 : 0)
675 /* Standard register usage. */
677 /* This processor has special stack-like registers. See reg-stack.c
681 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
682 || mode==XFmode || mode==TFmode)
684 /* Number of actual hardware registers.
685 The hardware registers are assigned numbers for the compiler
686 from 0 to just below FIRST_PSEUDO_REGISTER.
687 All registers that the compiler knows about must be given numbers,
688 even those that are not normally considered general registers.
690 In the 80386 we give the 8 general purpose registers the numbers 0-7.
691 We number the floating point registers 8-15.
692 Note that registers 0-7 can be accessed as a short or int,
693 while only 0-3 may be used with byte `mov' instructions.
695 Reg 16 does not correspond to any hardware register, but instead
696 appears in the RTL as an argument pointer prior to reload, and is
697 eliminated during reloading in favor of either the stack or frame
700 #define FIRST_PSEUDO_REGISTER 53
702 /* Number of hardware registers that go into the DWARF-2 unwind info.
703 If not defined, equals FIRST_PSEUDO_REGISTER. */
705 #define DWARF_FRAME_REGISTERS 17
707 /* 1 for registers that have pervasive standard uses
708 and are not available for the register allocator.
709 On the 80386, the stack pointer is such, as is the arg pointer.
711 The value is an mask - bit 1 is set for fixed registers
712 for 32bit target, while 2 is set for fixed registers for 64bit.
713 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
715 #define FIXED_REGISTERS \
716 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
717 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
718 /*arg,flags,fpsr,dir,frame*/ \
720 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
721 0, 0, 0, 0, 0, 0, 0, 0, \
722 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
723 0, 0, 0, 0, 0, 0, 0, 0, \
724 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
725 1, 1, 1, 1, 1, 1, 1, 1, \
726 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
727 1, 1, 1, 1, 1, 1, 1, 1}
730 /* 1 for registers not available across function calls.
731 These must include the FIXED_REGISTERS and also any
732 registers that can be used without being saved.
733 The latter must include the registers where values are returned
734 and the register where structure-value addresses are passed.
735 Aside from that, you can include as many other registers as you like.
737 The value is an mask - bit 1 is set for call used
738 for 32bit target, while 2 is set for call used for 64bit.
739 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
741 #define CALL_USED_REGISTERS \
742 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
743 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
744 /*arg,flags,fpsr,dir,frame*/ \
746 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
747 3, 3, 3, 3, 3, 3, 3, 3, \
748 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
749 3, 3, 3, 3, 3, 3, 3, 3, \
750 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
751 3, 3, 3, 3, 1, 1, 1, 1, \
752 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
753 3, 3, 3, 3, 3, 3, 3, 3} \
755 /* Order in which to allocate registers. Each register must be
756 listed once, even those in FIXED_REGISTERS. List frame pointer
757 late and fixed registers last. Note that, in general, we prefer
758 registers listed in CALL_USED_REGISTERS, keeping the others
759 available for storage of persistent values.
761 Three different versions of REG_ALLOC_ORDER have been tried:
763 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
764 but slower code on simple functions returning values in eax.
766 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
767 perl 4.036 due to not being able to create a DImode register (to hold a 2
770 If the order is eax, edx, ecx, ... it produces better code for simple
771 functions, and a slightly slower compiler. Users complained about the code
772 generated by allocating edx first, so restore the 'natural' order of things. */
774 #define REG_ALLOC_ORDER \
777 /* bx,si,di,bp,sp,*/ \
781 /*r12,r15,r14,r13*/ \
783 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
784 21, 22, 23, 24, 25, 26, 27, 28, \
785 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
786 45, 46, 47, 48, 49, 50, 51, 52, \
787 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
788 8, 9, 10, 11, 12, 13, 14, 15, \
789 /*,arg,cc,fpsr,dir,frame*/ \
791 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
792 29, 30, 31, 32, 33, 34, 35, 36 }
794 /* Macro to conditionally modify fixed_regs/call_used_regs. */
795 #define CONDITIONAL_REGISTER_USAGE \
798 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
800 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
801 call_used_regs[i] = (call_used_regs[i] \
802 & (TARGET_64BIT ? 2 : 1)) != 0; \
806 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
807 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
812 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
813 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
814 fixed_regs[i] = call_used_regs[i] = 1; \
819 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
820 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
821 fixed_regs[i] = call_used_regs[i] = 1; \
823 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
827 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
828 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
829 if (TEST_HARD_REG_BIT (x, i)) \
830 fixed_regs[i] = call_used_regs[i] = 1; \
834 /* Return number of consecutive hard regs needed starting at reg REGNO
835 to hold something of mode MODE.
836 This is ordinarily the length in words of a value of mode MODE
837 but can be less for certain modes in special long registers.
839 Actually there are no two word move instructions for consecutive
840 registers. And only registers 0-3 may have mov byte instructions
844 #define HARD_REGNO_NREGS(REGNO, MODE) \
845 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) ? 1 \
848 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
850 #define VALID_SSE_REG_MODE(MODE) \
851 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
852 || (MODE) == SFmode || (TARGET_SSE2 && (MODE) == DFmode))
854 #define VALID_MMX_REG_MODE(MODE) \
855 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
856 || (MODE) == V2SImode || (MODE) == SImode)
858 #define VECTOR_MODE_SUPPORTED_P(MODE) \
859 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
860 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 : 0)
862 #define VALID_FP_MODE_P(mode) \
863 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
864 || (!TARGET_64BIT && (mode) == XFmode) \
865 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
866 || (!TARGET_64BIT && (mode) == XCmode))
868 #define VALID_INT_MODE_P(mode) \
869 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
870 || (mode) == DImode \
871 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
872 || (mode) == CDImode)
874 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
876 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
877 ix86_hard_regno_mode_ok (REGNO, MODE)
879 /* Value is 1 if it is a good idea to tie two pseudo registers
880 when one has mode MODE1 and one has mode MODE2.
881 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
882 for any hard reg, then this must be 0 for correct output. */
884 #define MODES_TIEABLE_P(MODE1, MODE2) \
885 ((MODE1) == (MODE2) \
886 || (((MODE1) == HImode || (MODE1) == SImode \
887 || ((MODE1) == QImode \
888 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
889 || ((MODE1) == DImode && TARGET_64BIT)) \
890 && ((MODE2) == HImode || (MODE2) == SImode \
891 || ((MODE1) == QImode \
892 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
893 || ((MODE2) == DImode && TARGET_64BIT))))
896 /* Specify the modes required to caller save a given hard regno.
897 We do this on i386 to prevent flags from being saved at all.
899 Kill any attempts to combine saving of modes. */
901 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
902 (CC_REGNO_P (REGNO) ? VOIDmode \
903 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
904 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
905 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
906 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
908 /* Specify the registers used for certain standard purposes.
909 The values of these macros are register numbers. */
911 /* on the 386 the pc register is %eip, and is not usable as a general
912 register. The ordinary mov instructions won't work */
913 /* #define PC_REGNUM */
915 /* Register to use for pushing function arguments. */
916 #define STACK_POINTER_REGNUM 7
918 /* Base register for access to local variables of the function. */
919 #define HARD_FRAME_POINTER_REGNUM 6
921 /* Base register for access to local variables of the function. */
922 #define FRAME_POINTER_REGNUM 20
924 /* First floating point reg */
925 #define FIRST_FLOAT_REG 8
927 /* First & last stack-like regs */
928 #define FIRST_STACK_REG FIRST_FLOAT_REG
929 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
933 #define DIRFLAG_REG 19
935 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
936 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
938 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
939 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
941 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
942 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
944 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
945 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
947 /* Value should be nonzero if functions must have frame pointers.
948 Zero means the frame pointer need not be set up (and parms
949 may be accessed via the stack pointer) in functions that seem suitable.
950 This is computed in `reload', in reload1.c. */
951 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
953 /* Override this in other tm.h files to cope with various OS losage
954 requiring a frame pointer. */
955 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
956 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
959 /* Make sure we can access arbitrary call frames. */
960 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
962 /* Base register for access to arguments of the function. */
963 #define ARG_POINTER_REGNUM 16
965 /* Register in which static-chain is passed to a function.
966 We do use ECX as static chain register for 32 bit ABI. On the
967 64bit ABI, ECX is an argument register, so we use R10 instead. */
968 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
970 /* Register to hold the addressing base for position independent
971 code access to data items.
972 We don't use PIC pointer for 64bit mode. Define the regnum to
973 dummy value to prevent gcc from pesimizing code dealing with EBX.
975 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
977 /* Register in which address to store a structure value
978 arrives in the function. On the 386, the prologue
979 copies this from the stack to register %eax. */
980 #define STRUCT_VALUE_INCOMING 0
982 /* Place in which caller passes the structure value address.
983 0 means push the value on the stack like an argument. */
984 #define STRUCT_VALUE 0
986 /* A C expression which can inhibit the returning of certain function
987 values in registers, based on the type of value. A nonzero value
988 says to return the function value in memory, just as large
989 structures are always returned. Here TYPE will be a C expression
990 of type `tree', representing the data type of the value.
992 Note that values of mode `BLKmode' must be explicitly handled by
993 this macro. Also, the option `-fpcc-struct-return' takes effect
994 regardless of this macro. On most systems, it is possible to
995 leave the macro undefined; this causes a default definition to be
996 used, whose value is the constant 1 for `BLKmode' values, and 0
999 Do not use this macro to indicate that structures and unions
1000 should always be returned in memory. You should instead use
1001 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1003 #define RETURN_IN_MEMORY(TYPE) \
1004 ((TYPE_MODE (TYPE) == BLKmode) \
1005 || (VECTOR_MODE_P (TYPE_MODE (TYPE)) && int_size_in_bytes (TYPE) == 8)\
1006 || (int_size_in_bytes (TYPE) > 12 && TYPE_MODE (TYPE) != TImode \
1007 && TYPE_MODE (TYPE) != TFmode && ! VECTOR_MODE_P (TYPE_MODE (TYPE))))
1010 /* Define the classes of registers for register constraints in the
1011 machine description. Also define ranges of constants.
1013 One of the classes must always be named ALL_REGS and include all hard regs.
1014 If there is more than one class, another class must be named NO_REGS
1015 and contain no registers.
1017 The name GENERAL_REGS must be the name of a class (or an alias for
1018 another name such as ALL_REGS). This is the class of registers
1019 that is allowed by "g" or "r" in a register constraint.
1020 Also, registers outside this class are allocated only when
1021 instructions express preferences for them.
1023 The classes must be numbered in nondecreasing order; that is,
1024 a larger-numbered class must never be contained completely
1025 in a smaller-numbered class.
1027 For any two classes, it is very desirable that there be another
1028 class that represents their union.
1030 It might seem that class BREG is unnecessary, since no useful 386
1031 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1032 and the "b" register constraint is useful in asms for syscalls.
1034 The flags and fpsr registers are in no class. */
1039 AREG, DREG, CREG, BREG, SIREG, DIREG,
1040 AD_REGS, /* %eax/%edx for DImode */
1041 Q_REGS, /* %eax %ebx %ecx %edx */
1042 NON_Q_REGS, /* %esi %edi %ebp %esp */
1043 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1044 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1045 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1046 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1056 ALL_REGS, LIM_REG_CLASSES
1059 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1061 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1062 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1063 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1064 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1065 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1066 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1068 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1070 /* Give names of register classes as strings for dump file. */
1072 #define REG_CLASS_NAMES \
1074 "AREG", "DREG", "CREG", "BREG", \
1077 "Q_REGS", "NON_Q_REGS", \
1081 "FP_TOP_REG", "FP_SECOND_REG", \
1085 "FP_TOP_SSE_REGS", \
1086 "FP_SECOND_SSE_REGS", \
1090 "FLOAT_INT_SSE_REGS", \
1093 /* Define which registers fit in which classes.
1094 This is an initializer for a vector of HARD_REG_SET
1095 of length N_REG_CLASSES. */
1097 #define REG_CLASS_CONTENTS \
1099 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1100 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1101 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1102 { 0x03, 0x0 }, /* AD_REGS */ \
1103 { 0x0f, 0x0 }, /* Q_REGS */ \
1104 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1105 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1106 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1107 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1108 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1109 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1110 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1111 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1112 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1113 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1114 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1115 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1116 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1117 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1118 { 0xffffffff,0x1fffff } \
1121 /* The same information, inverted:
1122 Return the class number of the smallest class containing
1123 reg number REGNO. This could be a conditional expression
1124 or could index an array. */
1126 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1128 /* When defined, the compiler allows registers explicitly used in the
1129 rtl to be used as spill registers but prevents the compiler from
1130 extending the lifetime of these registers. */
1132 #define SMALL_REGISTER_CLASSES 1
1134 #define QI_REG_P(X) \
1135 (REG_P (X) && REGNO (X) < 4)
1137 #define GENERAL_REGNO_P(n) \
1138 ((n) < 8 || REX_INT_REGNO_P (n))
1140 #define GENERAL_REG_P(X) \
1141 (REG_P (X) && GENERAL_REGNO_P (X))
1143 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1145 #define NON_QI_REG_P(X) \
1146 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1148 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1149 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1151 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1152 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1153 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1154 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1156 #define SSE_REGNO_P(n) \
1157 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1158 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1160 #define SSE_REGNO(n) \
1161 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1162 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1164 #define SSE_FLOAT_MODE_P(m) \
1165 ((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1167 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1168 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1170 #define STACK_REG_P(xop) (REG_P (xop) && \
1171 REGNO (xop) >= FIRST_STACK_REG && \
1172 REGNO (xop) <= LAST_STACK_REG)
1174 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1176 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1178 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1179 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1181 /* Indicate whether hard register numbered REG_NO should be converted
1183 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1184 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1186 /* The class value for index registers, and the one for base regs. */
1188 #define INDEX_REG_CLASS INDEX_REGS
1189 #define BASE_REG_CLASS GENERAL_REGS
1191 /* Get reg_class from a letter such as appears in the machine description. */
1193 #define REG_CLASS_FROM_LETTER(C) \
1194 ((C) == 'r' ? GENERAL_REGS : \
1195 (C) == 'R' ? LEGACY_REGS : \
1196 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1197 (C) == 'Q' ? Q_REGS : \
1198 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1201 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1204 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1207 (C) == 'a' ? AREG : \
1208 (C) == 'b' ? BREG : \
1209 (C) == 'c' ? CREG : \
1210 (C) == 'd' ? DREG : \
1211 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1212 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1213 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1214 (C) == 'A' ? AD_REGS : \
1215 (C) == 'D' ? DIREG : \
1216 (C) == 'S' ? SIREG : NO_REGS)
1218 /* The letters I, J, K, L and M in a register constraint string
1219 can be used to stand for particular ranges of immediate operands.
1220 This macro defines what the ranges are.
1221 C is the letter, and VALUE is a constant value.
1222 Return 1 if VALUE is in the range specified by C.
1224 I is for non-DImode shifts.
1225 J is for DImode shifts.
1226 K is for signed imm8 operands.
1227 L is for andsi as zero-extending move.
1228 M is for shifts that can be executed by the "lea" opcode.
1229 N is for immedaite operands for out/in instructions (0-255)
1232 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1233 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1234 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1235 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1236 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1237 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1238 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1241 /* Similar, but for floating constants, and defining letters G and H.
1242 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1243 TARGET_387 isn't set, because the stack register converter may need to
1244 load 0.0 into the function value register. */
1246 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1247 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1248 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1250 /* Place additional restrictions on the register class to use when it
1251 is necessary to be able to hold a value of mode MODE in a reload
1252 register for which class CLASS would ordinarily be used. */
1254 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1255 ((MODE) == QImode && !TARGET_64BIT \
1256 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1259 /* Given an rtx X being reloaded into a reg required to be
1260 in class CLASS, return the class of reg to actually use.
1261 In general this is just CLASS; but on some machines
1262 in some cases it is preferable to use a more restrictive class.
1263 On the 80386 series, we prevent floating constants from being
1264 reloaded into floating registers (since no move-insn can do that)
1265 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1267 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1268 QImode must go into class Q_REGS.
1269 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1270 movdf to do mem-to-mem moves through integer regs. */
1272 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1273 ix86_preferred_reload_class (X, CLASS)
1275 /* If we are copying between general and FP registers, we need a memory
1276 location. The same is true for SSE and MMX registers. */
1277 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1278 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1280 /* QImode spills from non-QI registers need a scratch. This does not
1281 happen often -- the only example so far requires an uninitialized
1284 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1285 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1288 /* Return the maximum number of consecutive registers
1289 needed to represent mode MODE in a register of class CLASS. */
1290 /* On the 80386, this is the size of MODE in words,
1291 except in the FP regs, where a single reg is always enough. */
1292 #define CLASS_MAX_NREGS(CLASS, MODE) \
1293 (FLOAT_CLASS_P (CLASS) || SSE_CLASS_P (CLASS) || MMX_CLASS_P (CLASS) \
1295 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1297 /* A C expression whose value is nonzero if pseudos that have been
1298 assigned to registers of class CLASS would likely be spilled
1299 because registers of CLASS are needed for spill registers.
1301 The default value of this macro returns 1 if CLASS has exactly one
1302 register and zero otherwise. On most machines, this default
1303 should be used. Only define this macro to some other expression
1304 if pseudo allocated by `local-alloc.c' end up in memory because
1305 their hard registers were needed for spill registers. If this
1306 macro returns nonzero for those classes, those pseudos will only
1307 be allocated by `global.c', which knows how to reallocate the
1308 pseudo to another register. If there would not be another
1309 register available for reallocation, you should not change the
1310 definition of this macro since the only effect of such a
1311 definition would be to slow down register allocation. */
1313 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1314 (((CLASS) == AREG) \
1315 || ((CLASS) == DREG) \
1316 || ((CLASS) == CREG) \
1317 || ((CLASS) == BREG) \
1318 || ((CLASS) == AD_REGS) \
1319 || ((CLASS) == SIREG) \
1320 || ((CLASS) == DIREG))
1322 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1323 to automatically clobber for all asms.
1325 We do this in the new i386 backend to maintain source compatibility
1326 with the old cc0-based compiler. */
1328 #define MD_ASM_CLOBBERS(CLOBBERS) \
1330 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1331 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1332 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1335 /* Stack layout; function entry, exit and calling. */
1337 /* Define this if pushing a word on the stack
1338 makes the stack pointer a smaller address. */
1339 #define STACK_GROWS_DOWNWARD
1341 /* Define this if the nominal address of the stack frame
1342 is at the high-address end of the local variables;
1343 that is, each additional local variable allocated
1344 goes at a more negative offset in the frame. */
1345 #define FRAME_GROWS_DOWNWARD
1347 /* Offset within stack frame to start allocating local variables at.
1348 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1349 first local allocated. Otherwise, it is the offset to the BEGINNING
1350 of the first local allocated. */
1351 #define STARTING_FRAME_OFFSET 0
1353 /* If we generate an insn to push BYTES bytes,
1354 this says how many the stack pointer really advances by.
1355 On 386 pushw decrements by exactly 2 no matter what the position was.
1356 On the 386 there is no pushb; we use pushw instead, and this
1357 has the effect of rounding up to 2.
1359 For 64bit ABI we round up to 8 bytes.
1362 #define PUSH_ROUNDING(BYTES) \
1364 ? (((BYTES) + 7) & (-8)) \
1365 : (((BYTES) + 1) & (-2)))
1367 /* If defined, the maximum amount of space required for outgoing arguments will
1368 be computed and placed into the variable
1369 `current_function_outgoing_args_size'. No space will be pushed onto the
1370 stack for each call; instead, the function prologue should increase the stack
1371 frame size by this amount. */
1373 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1375 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1376 instructions to pass outgoing arguments. */
1378 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1380 /* Offset of first parameter from the argument pointer register value. */
1381 #define FIRST_PARM_OFFSET(FNDECL) 0
1383 /* Define this macro if functions should assume that stack space has been
1384 allocated for arguments even when their values are passed in registers.
1386 The value of this macro is the size, in bytes, of the area reserved for
1387 arguments passed in registers for the function represented by FNDECL.
1389 This space can be allocated by the caller, or be a part of the
1390 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1392 #define REG_PARM_STACK_SPACE(FNDECL) 0
1394 /* Define as a C expression that evaluates to nonzero if we do not know how
1395 to pass TYPE solely in registers. The file expr.h defines a
1396 definition that is usually appropriate, refer to expr.h for additional
1397 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1398 computed in the stack and then loaded into a register. */
1399 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1401 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1402 || TREE_ADDRESSABLE (TYPE) \
1403 || ((MODE) == TImode) \
1404 || ((MODE) == BLKmode \
1405 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1406 && 0 == (int_size_in_bytes (TYPE) \
1407 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1408 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1409 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1411 /* Value is the number of bytes of arguments automatically
1412 popped when returning from a subroutine call.
1413 FUNDECL is the declaration node of the function (as a tree),
1414 FUNTYPE is the data type of the function (as a tree),
1415 or for a library call it is an identifier node for the subroutine name.
1416 SIZE is the number of bytes of arguments passed on the stack.
1418 On the 80386, the RTD insn may be used to pop them if the number
1419 of args is fixed, but if the number is variable then the caller
1420 must pop them all. RTD can't be used for library calls now
1421 because the library is compiled with the Unix compiler.
1422 Use of RTD is a selectable option, since it is incompatible with
1423 standard Unix calling sequences. If the option is not selected,
1424 the caller must always pop the args.
1426 The attribute stdcall is equivalent to RTD on a per module basis. */
1428 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1429 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1431 /* Define how to find the value returned by a function.
1432 VALTYPE is the data type of the value (as a tree).
1433 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1434 otherwise, FUNC is 0. */
1435 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1436 gen_rtx_REG (TYPE_MODE (VALTYPE), \
1437 VALUE_REGNO (TYPE_MODE (VALTYPE)))
1439 /* Define how to find the value returned by a library function
1440 assuming the value has mode MODE. */
1442 #define LIBCALL_VALUE(MODE) \
1443 gen_rtx_REG (MODE, VALUE_REGNO (MODE))
1445 /* Define the size of the result block used for communication between
1446 untyped_call and untyped_return. The block contains a DImode value
1447 followed by the block used by fnsave and frstor. */
1449 #define APPLY_RESULT_SIZE (8+108)
1451 /* 1 if N is a possible register number for function argument passing. */
1452 #define FUNCTION_ARG_REGNO_P(N) ((N) < REGPARM_MAX)
1454 /* Define a data type for recording info about an argument list
1455 during the scan of that argument list. This data type should
1456 hold all necessary information about the function itself
1457 and about the args processed so far, enough to enable macros
1458 such as FUNCTION_ARG to determine where the next arg should go. */
1460 typedef struct ix86_args {
1461 int words; /* # words passed so far */
1462 int nregs; /* # registers available for passing */
1463 int regno; /* next available register number */
1464 int sse_words; /* # sse words passed so far */
1465 int sse_nregs; /* # sse registers available for passing */
1466 int sse_regno; /* next available sse register number */
1469 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1470 for a call to a function whose data type is FNTYPE.
1471 For a library call, FNTYPE is 0. */
1473 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1474 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1476 /* Update the data in CUM to advance over an argument
1477 of mode MODE and data type TYPE.
1478 (TYPE is null for libcalls where that information may not be available.) */
1480 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1481 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1483 /* Define where to put the arguments to a function.
1484 Value is zero to push the argument on the stack,
1485 or a hard register in which to store the argument.
1487 MODE is the argument's machine mode.
1488 TYPE is the data type of the argument (as a tree).
1489 This is null for libcalls where that information may
1491 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1492 the preceding args and about the function being called.
1493 NAMED is nonzero if this argument is a named parameter
1494 (otherwise it is an extra parameter matching an ellipsis). */
1496 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1497 (function_arg (&CUM, MODE, TYPE, NAMED))
1499 /* For an arg passed partly in registers and partly in memory,
1500 this is the number of registers used.
1501 For args passed entirely in registers or entirely in memory, zero. */
1503 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1505 /* If PIC, we cannot make sibling calls to global functions
1506 because the PLT requires %ebx live.
1507 If we are returning floats on the register stack, we cannot make
1508 sibling calls to functions that return floats. (The stack adjust
1509 instruction will wind up after the sibcall jump, and not be executed.) */
1510 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1512 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1513 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1514 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1515 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1517 /* This macro is invoked at the end of compilation. It is used here to
1518 output code for -fpic that will load the return address into %ebx. */
1521 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1523 /* Output assembler code to FILE to increment profiler label # LABELNO
1524 for profiling a function entry. */
1526 #define FUNCTION_PROFILER(FILE, LABELNO) \
1530 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1531 LPREFIX, (LABELNO)); \
1532 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1536 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1537 fprintf (FILE, "\tcall\t_mcount\n"); \
1542 /* There are three profiling modes for basic blocks available.
1543 The modes are selected at compile time by using the options
1544 -a or -ax of the gnu compiler.
1545 The variable `profile_block_flag' will be set according to the
1548 profile_block_flag == 0, no option used:
1552 profile_block_flag == 1, -a option used.
1554 Count frequency of execution of every basic block.
1556 profile_block_flag == 2, -ax option used.
1558 Generate code to allow several different profiling modes at run time.
1559 Available modes are:
1560 Produce a trace of all basic blocks.
1561 Count frequency of jump instructions executed.
1562 In every mode it is possible to start profiling upon entering
1563 certain functions and to disable profiling of some other functions.
1565 The result of basic-block profiling will be written to a file `bb.out'.
1566 If the -ax option is used parameters for the profiling will be read
1571 /* The following macro shall output assembler code to FILE
1572 to initialize basic-block profiling. */
1574 #undef FUNCTION_BLOCK_PROFILER
1575 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1576 ix86_output_function_block_profiler (FILE, BLOCK_OR_LABEL)
1578 /* The following macro shall output assembler code to FILE
1579 to increment a counter associated with basic block number BLOCKNO. */
1581 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1582 ix86_output_block_profiler (FILE, BLOCKNO)
1584 /* The following macro shall output rtl for the epilogue
1585 to indicate a return from function during basic-block profiling.
1587 If profiling_block_flag == 2:
1589 Output assembler code to call function `__bb_trace_ret'.
1591 Note that function `__bb_trace_ret' must not change the
1592 machine state, especially the flag register. To grant
1593 this, you must output code to save and restore registers
1594 either in this macro or in the macros MACHINE_STATE_SAVE
1595 and MACHINE_STATE_RESTORE. The last two macros will be
1596 used in the function `__bb_trace_ret', so you must make
1597 sure that the function prologue does not change any
1598 register prior to saving it with MACHINE_STATE_SAVE.
1600 else if profiling_block_flag != 0:
1602 The macro will not be used, so it need not distinguish
1606 #define FUNCTION_BLOCK_PROFILER_EXIT \
1607 emit_call_insn (gen_call (gen_rtx_MEM (QImode, \
1608 gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")), \
1611 /* The function `__bb_trace_func' is called in every basic block
1612 and is not allowed to change the machine state. Saving (restoring)
1613 the state can either be done in the BLOCK_PROFILER macro,
1614 before calling function (rsp. after returning from function)
1615 `__bb_trace_func', or it can be done inside the function by
1616 defining the macros:
1618 MACHINE_STATE_SAVE(ID)
1619 MACHINE_STATE_RESTORE(ID)
1621 In the latter case care must be taken, that the prologue code
1622 of function `__bb_trace_func' does not already change the
1623 state prior to saving it with MACHINE_STATE_SAVE.
1625 The parameter `ID' is a string identifying a unique macro use.
1627 On the i386 the initialization code at the begin of
1628 function `__bb_trace_func' contains a `sub' instruction
1629 therefore we handle save and restore of the flag register
1630 in the BLOCK_PROFILER macro.
1632 Note that ebx, esi, and edi are callee-save, so we don't have to
1633 preserve them explicitly. */
1635 #define MACHINE_STATE_SAVE(ID) \
1637 register int eax_ __asm__("eax"); \
1638 register int ecx_ __asm__("ecx"); \
1639 register int edx_ __asm__("edx"); \
1640 __asm__ __volatile__ ("\
1644 : : "r"(eax_), "r"(ecx_), "r"(edx_)); \
1647 #define MACHINE_STATE_RESTORE(ID) \
1649 register int eax_ __asm__("eax"); \
1650 register int ecx_ __asm__("ecx"); \
1651 register int edx_ __asm__("edx"); \
1652 __asm__ __volatile__ ("\
1656 : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \
1659 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1660 the stack pointer does not matter. The value is tested only in
1661 functions that have frame pointers.
1662 No definition is equivalent to always zero. */
1663 /* Note on the 386 it might be more efficient not to define this since
1664 we have to restore it ourselves from the frame pointer, in order to
1667 #define EXIT_IGNORE_STACK 1
1669 /* Output assembler code for a block containing the constant parts
1670 of a trampoline, leaving space for the variable parts. */
1672 /* On the 386, the trampoline contains two instructions:
1675 The trampoline is generated entirely at runtime. The operand of JMP
1676 is the address of FUNCTION relative to the instruction following the
1677 JMP (which is 5 bytes long). */
1679 /* Length in units of the trampoline for entering a nested function. */
1681 #define TRAMPOLINE_SIZE 10
1683 /* Emit RTL insns to initialize the variable parts of a trampoline.
1684 FNADDR is an RTX for the address of the function's pure code.
1685 CXT is an RTX for the static chain value for the function. */
1687 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1689 /* Compute offset from the end of the jmp to the target function. */ \
1690 rtx disp = expand_binop (SImode, sub_optab, FNADDR, \
1691 plus_constant (TRAMP, 10), \
1692 NULL_RTX, 1, OPTAB_DIRECT); \
1693 emit_move_insn (gen_rtx_MEM (QImode, TRAMP), GEN_INT (0xb9)); \
1694 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 1)), CXT); \
1695 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (TRAMP, 5)), GEN_INT (0xe9));\
1696 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 6)), disp); \
1699 /* Definitions for register eliminations.
1701 This is an array of structures. Each structure initializes one pair
1702 of eliminable registers. The "from" register number is given first,
1703 followed by "to". Eliminations of the same "from" register are listed
1704 in order of preference.
1706 There are two registers that can always be eliminated on the i386.
1707 The frame pointer and the arg pointer can be replaced by either the
1708 hard frame pointer or to the stack pointer, depending upon the
1709 circumstances. The hard frame pointer is not used before reload and
1710 so it is not eligible for elimination. */
1712 #define ELIMINABLE_REGS \
1713 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1714 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1715 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1716 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1718 /* Given FROM and TO register numbers, say whether this elimination is
1719 allowed. Frame pointer elimination is automatically handled.
1721 All other eliminations are valid. */
1723 #define CAN_ELIMINATE(FROM, TO) \
1724 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1726 /* Define the offset between two registers, one to be eliminated, and the other
1727 its replacement, at the start of a routine. */
1729 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1730 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1732 /* Addressing modes, and classification of registers for them. */
1734 /* #define HAVE_POST_INCREMENT 0 */
1735 /* #define HAVE_POST_DECREMENT 0 */
1737 /* #define HAVE_PRE_DECREMENT 0 */
1738 /* #define HAVE_PRE_INCREMENT 0 */
1740 /* Macros to check register numbers against specific register classes. */
1742 /* These assume that REGNO is a hard or pseudo reg number.
1743 They give nonzero only if REGNO is a hard reg of the suitable class
1744 or a pseudo reg currently allocated to a suitable hard reg.
1745 Since they use reg_renumber, they are safe only once reg_renumber
1746 has been allocated, which happens in local-alloc.c. */
1748 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1749 ((REGNO) < STACK_POINTER_REGNUM \
1750 || (REGNO >= FIRST_REX_INT_REG \
1751 && (REGNO) <= LAST_REX_INT_REG) \
1752 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1753 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1754 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1756 #define REGNO_OK_FOR_BASE_P(REGNO) \
1757 ((REGNO) <= STACK_POINTER_REGNUM \
1758 || (REGNO) == ARG_POINTER_REGNUM \
1759 || (REGNO) == FRAME_POINTER_REGNUM \
1760 || (REGNO >= FIRST_REX_INT_REG \
1761 && (REGNO) <= LAST_REX_INT_REG) \
1762 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1763 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1764 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1766 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1767 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1769 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1770 and check its validity for a certain class.
1771 We have two alternate definitions for each of them.
1772 The usual definition accepts all pseudo regs; the other rejects
1773 them unless they have been allocated suitable hard regs.
1774 The symbol REG_OK_STRICT causes the latter definition to be used.
1776 Most source files want to accept pseudo regs in the hope that
1777 they will get allocated to the class that the insn wants them to be in.
1778 Source files for reload pass need to be strict.
1779 After reload, it makes no difference, since pseudo regs have
1780 been eliminated by then. */
1783 /* Non strict versions, pseudos are ok */
1784 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1785 (REGNO (X) < STACK_POINTER_REGNUM \
1786 || (REGNO (X) >= FIRST_REX_INT_REG \
1787 && REGNO (X) <= LAST_REX_INT_REG) \
1788 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1790 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1791 (REGNO (X) <= STACK_POINTER_REGNUM \
1792 || REGNO (X) == ARG_POINTER_REGNUM \
1793 || REGNO (X) == FRAME_POINTER_REGNUM \
1794 || (REGNO (X) >= FIRST_REX_INT_REG \
1795 && REGNO (X) <= LAST_REX_INT_REG) \
1796 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1798 /* Strict versions, hard registers only */
1799 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1800 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1802 #ifndef REG_OK_STRICT
1803 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1804 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1807 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1808 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1811 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1812 that is a valid memory address for an instruction.
1813 The MODE argument is the machine mode for the MEM expression
1814 that wants to use this address.
1816 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1817 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1819 See legitimize_pic_address in i386.c for details as to what
1820 constitutes a legitimate address when -fpic is used. */
1822 #define MAX_REGS_PER_ADDRESS 2
1824 #define CONSTANT_ADDRESS_P(X) \
1825 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1826 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1827 || GET_CODE (X) == CONST_DOUBLE)
1829 /* Nonzero if the constant value X is a legitimate general operand.
1830 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1832 #define LEGITIMATE_CONSTANT_P(X) 1
1834 #ifdef REG_OK_STRICT
1835 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1837 if (legitimate_address_p (MODE, X, 1)) \
1842 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1844 if (legitimate_address_p (MODE, X, 0)) \
1850 /* If defined, a C expression to determine the base term of address X.
1851 This macro is used in only one place: `find_base_term' in alias.c.
1853 It is always safe for this macro to not be defined. It exists so
1854 that alias analysis can understand machine-dependent addresses.
1856 The typical use of this macro is to handle addresses containing
1857 a label_ref or symbol_ref within an UNSPEC. */
1859 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1861 /* Try machine-dependent ways of modifying an illegitimate address
1862 to be legitimate. If we find one, return the new, valid address.
1863 This macro is used in only one place: `memory_address' in explow.c.
1865 OLDX is the address as it was before break_out_memory_refs was called.
1866 In some cases it is useful to look at this to decide what needs to be done.
1868 MODE and WIN are passed so that this macro can use
1869 GO_IF_LEGITIMATE_ADDRESS.
1871 It is always safe for this macro to do nothing. It exists to recognize
1872 opportunities to optimize the output.
1874 For the 80386, we handle X+REG by loading X into a register R and
1875 using R+REG. R will go in a general reg and indexing will be used.
1876 However, if REG is a broken-out memory address or multiplication,
1877 nothing needs to be done because REG can certainly go in a general reg.
1879 When -fpic is used, special handling is needed for symbolic references.
1880 See comments by legitimize_pic_address in i386.c for details. */
1882 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1884 (X) = legitimize_address (X, OLDX, MODE); \
1885 if (memory_address_p (MODE, X)) \
1889 #define REWRITE_ADDRESS(x) rewrite_address(x)
1891 /* Nonzero if the constant value X is a legitimate general operand
1892 when generating PIC code. It is given that flag_pic is on and
1893 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1895 #define LEGITIMATE_PIC_OPERAND_P(X) \
1896 (! SYMBOLIC_CONST (X) \
1897 || legitimate_pic_address_disp_p (X))
1899 #define SYMBOLIC_CONST(X) \
1900 (GET_CODE (X) == SYMBOL_REF \
1901 || GET_CODE (X) == LABEL_REF \
1902 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1904 /* Go to LABEL if ADDR (a legitimate address expression)
1905 has an effect that depends on the machine mode it is used for.
1906 On the 80386, only postdecrement and postincrement address depend thus
1907 (the amount of decrement or increment being the length of the operand). */
1908 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1909 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
1911 /* Codes for all the SSE/MMX builtins. */
1923 IX86_BUILTIN_CMPEQPS,
1924 IX86_BUILTIN_CMPLTPS,
1925 IX86_BUILTIN_CMPLEPS,
1926 IX86_BUILTIN_CMPGTPS,
1927 IX86_BUILTIN_CMPGEPS,
1928 IX86_BUILTIN_CMPNEQPS,
1929 IX86_BUILTIN_CMPNLTPS,
1930 IX86_BUILTIN_CMPNLEPS,
1931 IX86_BUILTIN_CMPNGTPS,
1932 IX86_BUILTIN_CMPNGEPS,
1933 IX86_BUILTIN_CMPORDPS,
1934 IX86_BUILTIN_CMPUNORDPS,
1935 IX86_BUILTIN_CMPNEPS,
1936 IX86_BUILTIN_CMPEQSS,
1937 IX86_BUILTIN_CMPLTSS,
1938 IX86_BUILTIN_CMPLESS,
1939 IX86_BUILTIN_CMPGTSS,
1940 IX86_BUILTIN_CMPGESS,
1941 IX86_BUILTIN_CMPNEQSS,
1942 IX86_BUILTIN_CMPNLTSS,
1943 IX86_BUILTIN_CMPNLESS,
1944 IX86_BUILTIN_CMPNGTSS,
1945 IX86_BUILTIN_CMPNGESS,
1946 IX86_BUILTIN_CMPORDSS,
1947 IX86_BUILTIN_CMPUNORDSS,
1948 IX86_BUILTIN_CMPNESS,
1950 IX86_BUILTIN_COMIEQSS,
1951 IX86_BUILTIN_COMILTSS,
1952 IX86_BUILTIN_COMILESS,
1953 IX86_BUILTIN_COMIGTSS,
1954 IX86_BUILTIN_COMIGESS,
1955 IX86_BUILTIN_COMINEQSS,
1956 IX86_BUILTIN_UCOMIEQSS,
1957 IX86_BUILTIN_UCOMILTSS,
1958 IX86_BUILTIN_UCOMILESS,
1959 IX86_BUILTIN_UCOMIGTSS,
1960 IX86_BUILTIN_UCOMIGESS,
1961 IX86_BUILTIN_UCOMINEQSS,
1963 IX86_BUILTIN_CVTPI2PS,
1964 IX86_BUILTIN_CVTPS2PI,
1965 IX86_BUILTIN_CVTSI2SS,
1966 IX86_BUILTIN_CVTSS2SI,
1967 IX86_BUILTIN_CVTTPS2PI,
1968 IX86_BUILTIN_CVTTSS2SI,
1969 IX86_BUILTIN_M_FROM_INT,
1970 IX86_BUILTIN_M_TO_INT,
1977 IX86_BUILTIN_LOADAPS,
1978 IX86_BUILTIN_LOADUPS,
1979 IX86_BUILTIN_STOREAPS,
1980 IX86_BUILTIN_STOREUPS,
1981 IX86_BUILTIN_LOADSS,
1982 IX86_BUILTIN_STORESS,
1985 IX86_BUILTIN_MOVHLPS,
1986 IX86_BUILTIN_MOVLHPS,
1987 IX86_BUILTIN_LOADHPS,
1988 IX86_BUILTIN_LOADLPS,
1989 IX86_BUILTIN_STOREHPS,
1990 IX86_BUILTIN_STORELPS,
1992 IX86_BUILTIN_MASKMOVQ,
1993 IX86_BUILTIN_MOVMSKPS,
1994 IX86_BUILTIN_PMOVMSKB,
1996 IX86_BUILTIN_MOVNTPS,
1997 IX86_BUILTIN_MOVNTQ,
1999 IX86_BUILTIN_PACKSSWB,
2000 IX86_BUILTIN_PACKSSDW,
2001 IX86_BUILTIN_PACKUSWB,
2006 IX86_BUILTIN_PADDSB,
2007 IX86_BUILTIN_PADDSW,
2008 IX86_BUILTIN_PADDUSB,
2009 IX86_BUILTIN_PADDUSW,
2013 IX86_BUILTIN_PSUBSB,
2014 IX86_BUILTIN_PSUBSW,
2015 IX86_BUILTIN_PSUBUSB,
2016 IX86_BUILTIN_PSUBUSW,
2026 IX86_BUILTIN_PCMPEQB,
2027 IX86_BUILTIN_PCMPEQW,
2028 IX86_BUILTIN_PCMPEQD,
2029 IX86_BUILTIN_PCMPGTB,
2030 IX86_BUILTIN_PCMPGTW,
2031 IX86_BUILTIN_PCMPGTD,
2033 IX86_BUILTIN_PEXTRW,
2034 IX86_BUILTIN_PINSRW,
2036 IX86_BUILTIN_PMADDWD,
2038 IX86_BUILTIN_PMAXSW,
2039 IX86_BUILTIN_PMAXUB,
2040 IX86_BUILTIN_PMINSW,
2041 IX86_BUILTIN_PMINUB,
2043 IX86_BUILTIN_PMULHUW,
2044 IX86_BUILTIN_PMULHW,
2045 IX86_BUILTIN_PMULLW,
2047 IX86_BUILTIN_PSADBW,
2048 IX86_BUILTIN_PSHUFW,
2058 IX86_BUILTIN_PSLLWI,
2059 IX86_BUILTIN_PSLLDI,
2060 IX86_BUILTIN_PSLLQI,
2061 IX86_BUILTIN_PSRAWI,
2062 IX86_BUILTIN_PSRADI,
2063 IX86_BUILTIN_PSRLWI,
2064 IX86_BUILTIN_PSRLDI,
2065 IX86_BUILTIN_PSRLQI,
2067 IX86_BUILTIN_PUNPCKHBW,
2068 IX86_BUILTIN_PUNPCKHWD,
2069 IX86_BUILTIN_PUNPCKHDQ,
2070 IX86_BUILTIN_PUNPCKLBW,
2071 IX86_BUILTIN_PUNPCKLWD,
2072 IX86_BUILTIN_PUNPCKLDQ,
2074 IX86_BUILTIN_SHUFPS,
2078 IX86_BUILTIN_RSQRTPS,
2079 IX86_BUILTIN_RSQRTSS,
2080 IX86_BUILTIN_SQRTPS,
2081 IX86_BUILTIN_SQRTSS,
2083 IX86_BUILTIN_UNPCKHPS,
2084 IX86_BUILTIN_UNPCKLPS,
2087 IX86_BUILTIN_ANDNPS,
2092 IX86_BUILTIN_LDMXCSR,
2093 IX86_BUILTIN_STMXCSR,
2094 IX86_BUILTIN_SFENCE,
2095 IX86_BUILTIN_PREFETCH,
2097 /* Composite builtins, expand to more than one insn. */
2098 IX86_BUILTIN_SETPS1,
2101 IX86_BUILTIN_SETRPS,
2102 IX86_BUILTIN_LOADPS1,
2103 IX86_BUILTIN_LOADRPS,
2104 IX86_BUILTIN_STOREPS1,
2105 IX86_BUILTIN_STORERPS,
2107 IX86_BUILTIN_MMX_ZERO,
2112 /* Initialize the target-specific builtin functions. Only do something
2113 if TARGET_MMX is nonzero; we take care in ix86_init_builtins not to
2114 enable any SSE builtins if TARGET_SSE is zero. */
2115 #define MD_INIT_BUILTINS \
2119 ix86_init_builtins (); \
2123 /* Expand a target-specific builtin function. */
2124 #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
2125 ix86_expand_builtin (EXP, TARGET, SUBTARGET, MODE, IGNORE)
2127 /* Define this macro if references to a symbol must be treated
2128 differently depending on something about the variable or
2129 function named by the symbol (such as what section it is in).
2131 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2132 so that we may access it directly in the GOT. */
2134 #define ENCODE_SECTION_INFO(DECL) \
2139 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2140 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2142 if (GET_CODE (rtl) == MEM) \
2144 if (TARGET_DEBUG_ADDR \
2145 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2147 fprintf (stderr, "Encode %s, public = %d\n", \
2148 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2149 TREE_PUBLIC (DECL)); \
2152 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2153 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2154 || ! TREE_PUBLIC (DECL)); \
2160 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2161 codes once the function is being compiled into assembly code, but
2162 not before. (It is not done before, because in the case of
2163 compiling an inline function, it would lead to multiple PIC
2164 prologues being included in functions which used inline functions
2165 and were compiled to assembly language.) */
2167 #define FINALIZE_PIC \
2170 current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
2175 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2176 with arguments ARGS is a valid machine specific attribute for DECL.
2177 The attributes in ATTRIBUTES have previously been assigned to DECL. */
2179 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
2180 (ix86_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
2182 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2183 with arguments ARGS is a valid machine specific attribute for TYPE.
2184 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2186 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2187 (ix86_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2189 /* If defined, a C expression whose value is zero if the attributes on
2190 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2191 two if they are nearly compatible (which causes a warning to be
2194 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2195 (ix86_comp_type_attributes (TYPE1, TYPE2))
2197 /* If defined, a C statement that assigns default attributes to newly
2200 /* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */
2202 /* Max number of args passed in registers. If this is more than 3, we will
2203 have problems with ebx (register #4), since it is a caller save register and
2204 is also used as the pic register in ELF. So for now, don't allow more than
2205 3 registers to be passed in registers. */
2207 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2209 #define SSE_REGPARM_MAX (TARGET_64BIT ? 16 : 0)
2212 /* Specify the machine mode that this machine uses
2213 for the index in the tablejump instruction. */
2214 #define CASE_VECTOR_MODE Pmode
2216 /* Define as C expression which evaluates to nonzero if the tablejump
2217 instruction expects the table to contain offsets from the address of the
2219 Do not define this if the table should contain absolute addresses. */
2220 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2222 /* Specify the tree operation to be used to convert reals to integers.
2223 This should be changed to take advantage of fist --wfs ??
2225 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2227 /* This is the kind of divide that is easiest to do in the general case. */
2228 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2230 /* Define this as 1 if `char' should by default be signed; else as 0. */
2231 #define DEFAULT_SIGNED_CHAR 1
2233 /* Max number of bytes we can move from memory to memory
2234 in one reasonably fast instruction. */
2237 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2238 move efficiently, as opposed to MOVE_MAX which is the maximum
2239 number of bytes we can move with a single instruction. */
2240 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2242 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2243 move-instruction pairs, we will do a movstr or libcall instead.
2244 Increasing the value will always make code faster, but eventually
2245 incurs high cost in increased code size.
2247 If you don't define this, a reasonable default is used. */
2249 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2251 /* Define if shifts truncate the shift count
2252 which implies one can omit a sign-extension or zero-extension
2253 of a shift count. */
2254 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2256 /* #define SHIFT_COUNT_TRUNCATED */
2258 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2259 is done just by pretending it is already truncated. */
2260 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2262 /* We assume that the store-condition-codes instructions store 0 for false
2263 and some other value for true. This is the value stored for true. */
2265 #define STORE_FLAG_VALUE 1
2267 /* When a prototype says `char' or `short', really pass an `int'.
2268 (The 386 can't easily push less than an int.) */
2270 #define PROMOTE_PROTOTYPES 1
2272 /* A macro to update M and UNSIGNEDP when an object whose type is
2273 TYPE and which has the specified mode and signedness is to be
2274 stored in a register. This macro is only called when TYPE is a
2277 On i386 it is sometimes usefull to promote HImode and QImode
2278 quantities to SImode. The choice depends on target type. */
2280 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2281 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2282 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2285 /* Specify the machine mode that pointers have.
2286 After generation of rtl, the compiler makes no further distinction
2287 between pointers and any other objects of this machine mode. */
2288 #define Pmode (TARGET_64BIT ? DImode : SImode)
2290 /* A function address in a call instruction
2291 is a byte address (for indexing purposes)
2292 so give the MEM rtx a byte's mode. */
2293 #define FUNCTION_MODE QImode
2295 /* A part of a C `switch' statement that describes the relative costs
2296 of constant RTL expressions. It must contain `case' labels for
2297 expression codes `const_int', `const', `symbol_ref', `label_ref'
2298 and `const_double'. Each case must ultimately reach a `return'
2299 statement to return the relative cost of the use of that kind of
2300 constant value in an expression. The cost may depend on the
2301 precise value of the constant, which is available for examination
2302 in X, and the rtx code of the expression in which it is contained,
2303 found in OUTER_CODE.
2305 CODE is the expression code--redundant, since it can be obtained
2306 with `GET_CODE (X)'. */
2308 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2310 return (unsigned) INTVAL (RTX) < 256 ? 0 : 1; \
2314 return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 1; \
2316 case CONST_DOUBLE: \
2319 if (GET_MODE (RTX) == VOIDmode) \
2322 code = standard_80387_constant_p (RTX); \
2323 return code == 1 ? 0 : \
2328 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2329 #define TOPLEVEL_COSTS_N_INSNS(N) \
2330 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2332 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2333 This can be used, for example, to indicate how costly a multiply
2334 instruction is. In writing this macro, you can use the construct
2335 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2336 instructions. OUTER_CODE is the code of the expression in which X
2339 This macro is optional; do not define it if the default cost
2340 assumptions are adequate for the target machine. */
2342 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2344 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2345 && GET_MODE (XEXP (X, 0)) == SImode) \
2347 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2349 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2350 if (value == 2 || value == 3) \
2351 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2353 /* fall through */ \
2359 if (GET_MODE (XEXP (X, 0)) == DImode) \
2361 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2363 if (INTVAL (XEXP (X, 1)) > 32) \
2364 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2366 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2370 if (GET_CODE (XEXP (X, 1)) == AND) \
2371 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2373 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2378 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2379 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2381 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2386 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2388 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2391 while (value != 0) \
2397 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2398 + nbits * ix86_cost->mult_bit); \
2400 else /* This is arbitrary */ \
2401 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2402 + 7 * ix86_cost->mult_bit); \
2408 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2411 if (GET_CODE (XEXP (X, 0)) == PLUS \
2412 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2413 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2414 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2416 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1)); \
2417 if (val == 2 || val == 4 || val == 8) \
2419 return (COSTS_N_INSNS (ix86_cost->lea) \
2420 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2421 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2422 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2425 else if (GET_CODE (XEXP (X, 0)) == MULT \
2426 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2428 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2429 if (val == 2 || val == 4 || val == 8) \
2431 return (COSTS_N_INSNS (ix86_cost->lea) \
2432 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2433 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2436 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2438 return (COSTS_N_INSNS (ix86_cost->lea) \
2439 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2440 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2441 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2444 /* fall through */ \
2449 if (GET_MODE (X) == DImode) \
2450 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2451 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2452 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2453 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2454 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2456 /* fall through */ \
2459 if (GET_MODE (X) == DImode) \
2460 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2461 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2467 /* An expression giving the cost of an addressing mode that contains
2468 ADDRESS. If not defined, the cost is computed from the ADDRESS
2469 expression and the `CONST_COSTS' values.
2471 For most CISC machines, the default cost is a good approximation
2472 of the true cost of the addressing mode. However, on RISC
2473 machines, all instructions normally have the same length and
2474 execution time. Hence all addresses will have equal costs.
2476 In cases where more than one form of an address is known, the form
2477 with the lowest cost will be used. If multiple forms have the
2478 same, lowest, cost, the one that is the most complex will be used.
2480 For example, suppose an address that is equal to the sum of a
2481 register and a constant is used twice in the same basic block.
2482 When this macro is not defined, the address will be computed in a
2483 register and memory references will be indirect through that
2484 register. On machines where the cost of the addressing mode
2485 containing the sum is no higher than that of a simple indirect
2486 reference, this will produce an additional instruction and
2487 possibly require an additional register. Proper specification of
2488 this macro eliminates this overhead for such machines.
2490 Similar use of this macro is made in strength reduction of loops.
2492 ADDRESS need not be valid as an address. In such a case, the cost
2493 is not relevant and can be any value; invalid addresses need not be
2494 assigned a different cost.
2496 On machines where an address involving more than one register is as
2497 cheap as an address computation involving only one register,
2498 defining `ADDRESS_COST' to reflect this can cause two registers to
2499 be live over a region of code where only one would have been if
2500 `ADDRESS_COST' were not defined in that manner. This effect should
2501 be considered in the definition of this macro. Equivalent costs
2502 should probably only be given to addresses with different numbers
2503 of registers on machines with lots of registers.
2505 This macro will normally either not be defined or be defined as a
2508 For i386, it is better to use a complex address than let gcc copy
2509 the address into a reg and make a new pseudo. But not if the address
2510 requires to two regs - that would mean more pseudos with longer
2513 #define ADDRESS_COST(RTX) \
2514 ix86_address_cost (RTX)
2516 /* A C expression for the cost of moving data from a register in class FROM to
2517 one in class TO. The classes are expressed using the enumeration values
2518 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2519 interpreted relative to that.
2521 It is not required that the cost always equal 2 when FROM is the same as TO;
2522 on some machines it is expensive to move between registers if they are not
2523 general registers. */
2525 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2526 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2528 /* A C expression for the cost of moving data of mode M between a
2529 register and memory. A value of 2 is the default; this cost is
2530 relative to those in `REGISTER_MOVE_COST'.
2532 If moving between registers and memory is more expensive than
2533 between two registers, you should define this macro to express the
2536 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2537 ix86_memory_move_cost (MODE, CLASS, IN)
2539 /* A C expression for the cost of a branch instruction. A value of 1
2540 is the default; other values are interpreted relative to that. */
2542 #define BRANCH_COST ix86_branch_cost
2544 /* Define this macro as a C expression which is nonzero if accessing
2545 less than a word of memory (i.e. a `char' or a `short') is no
2546 faster than accessing a word of memory, i.e., if such access
2547 require more than one instruction or if there is no difference in
2548 cost between byte and (aligned) word loads.
2550 When this macro is not defined, the compiler will access a field by
2551 finding the smallest containing object; when it is defined, a
2552 fullword load will be used if alignment permits. Unless bytes
2553 accesses are faster than word accesses, using word accesses is
2554 preferable since it may eliminate subsequent memory access if
2555 subsequent accesses occur to other fields in the same word of the
2556 structure, but to different bytes. */
2558 #define SLOW_BYTE_ACCESS 0
2560 /* Nonzero if access to memory by shorts is slow and undesirable. */
2561 #define SLOW_SHORT_ACCESS 0
2563 /* Define this macro if zero-extension (of a `char' or `short' to an
2564 `int') can be done faster if the destination is a register that is
2567 If you define this macro, you must have instruction patterns that
2568 recognize RTL structures like this:
2570 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2572 and likewise for `HImode'. */
2574 /* #define SLOW_ZERO_EXTEND */
2576 /* Define this macro to be the value 1 if unaligned accesses have a
2577 cost many times greater than aligned accesses, for example if they
2578 are emulated in a trap handler.
2580 When this macro is non-zero, the compiler will act as if
2581 `STRICT_ALIGNMENT' were non-zero when generating code for block
2582 moves. This can cause significantly more instructions to be
2583 produced. Therefore, do not set this macro non-zero if unaligned
2584 accesses only add a cycle or two to the time for a memory access.
2586 If the value of this macro is always zero, it need not be defined. */
2588 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2590 /* Define this macro to inhibit strength reduction of memory
2591 addresses. (On some machines, such strength reduction seems to do
2592 harm rather than good.) */
2594 /* #define DONT_REDUCE_ADDR */
2596 /* Define this macro if it is as good or better to call a constant
2597 function address than to call an address kept in a register.
2599 Desirable on the 386 because a CALL with a constant address is
2600 faster than one with a register address. */
2602 #define NO_FUNCTION_CSE
2604 /* Define this macro if it is as good or better for a function to call
2605 itself with an explicit address than to call an address kept in a
2608 #define NO_RECURSIVE_FUNCTION_CSE
2610 /* A C statement (sans semicolon) to update the integer variable COST
2611 based on the relationship between INSN that is dependent on
2612 DEP_INSN through the dependence LINK. The default is to make no
2613 adjustment to COST. This can be used for example to specify to
2614 the scheduler that an output- or anti-dependence does not incur
2615 the same cost as a data-dependence. */
2617 #define ADJUST_COST(insn,link,dep_insn,cost) \
2618 (cost) = ix86_adjust_cost(insn, link, dep_insn, cost)
2620 #define ISSUE_RATE \
2623 #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE, MAX_READY) \
2624 ix86_sched_init (DUMP, SCHED_VERBOSE)
2626 #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \
2627 (CIM) = ix86_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK)
2629 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
2630 ((CAN_ISSUE_MORE) = \
2631 ix86_variable_issue (DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE))
2633 /* Add any extra modes needed to represent the condition code.
2635 For the i386, we need separate modes when floating-point
2636 equality comparisons are being done.
2638 Add CCNO to indicate comparisons against zero that requires
2639 Overflow flag to be unset. Sign bit test is used instead and
2640 thus can be used to form "a&b>0" type of tests.
2642 Add CCGC to indicate comparisons agains zero that allows
2643 unspecified garbage in the Carry flag. This mode is used
2644 by inc/dec instructions.
2646 Add CCGOC to indicate comparisons agains zero that allows
2647 unspecified garbage in the Carry and Overflow flag. This
2648 mode is used to simulate comparisons of (a-b) and (a+b)
2649 against zero using sub/cmp/add operations.
2651 Add CCZ to indicate that only the Zero flag is valid. */
2653 #define EXTRA_CC_MODES \
2654 CC(CCGCmode, "CCGC") \
2655 CC(CCGOCmode, "CCGOC") \
2656 CC(CCNOmode, "CCNO") \
2657 CC(CCZmode, "CCZ") \
2658 CC(CCFPmode, "CCFP") \
2659 CC(CCFPUmode, "CCFPU")
2661 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2662 return the mode to be used for the comparison.
2664 For floating-point equality comparisons, CCFPEQmode should be used.
2665 VOIDmode should be used in all other cases.
2667 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2668 possible, to allow for more combinations. */
2670 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2672 /* Return non-zero if MODE implies a floating point inequality can be
2675 #define REVERSIBLE_CC_MODE(MODE) 1
2677 /* A C expression whose value is reversed condition code of the CODE for
2678 comparison done in CC_MODE mode. */
2679 #define REVERSE_CONDITION(CODE, MODE) \
2680 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2681 : reverse_condition_maybe_unordered (CODE))
2684 /* Control the assembler format that we output, to the extent
2685 this does not vary between assemblers. */
2687 /* How to refer to registers in assembler output.
2688 This sequence is indexed by compiler's hard-register-number (see above). */
2690 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2691 For non floating point regs, the following are the HImode names.
2693 For float regs, the stack top is sometimes referred to as "%st(0)"
2694 instead of just "%st". PRINT_REG handles this with the "y" code. */
2696 #define HI_REGISTER_NAMES \
2697 {"ax","dx","cx","bx","si","di","bp","sp", \
2698 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2699 "flags","fpsr", "dirflag", "frame" }
2701 #undef HI_REGISTER_NAMES
2702 #define HI_REGISTER_NAMES \
2703 {"ax","dx","cx","bx","si","di","bp","sp", \
2704 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2705 "flags","fpsr", "dirflag", "frame", \
2706 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2707 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2708 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2709 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2711 #define REGISTER_NAMES HI_REGISTER_NAMES
2713 /* Table of additional register names to use in user input. */
2715 #define ADDITIONAL_REGISTER_NAMES \
2716 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2717 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2718 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2719 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2720 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2721 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2722 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2723 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2725 /* Note we are omitting these since currently I don't know how
2726 to get gcc to use these, since they want the same but different
2727 number as al, and ax.
2730 #define QI_REGISTER_NAMES \
2731 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2733 /* These parallel the array above, and can be used to access bits 8:15
2734 of regs 0 through 3. */
2736 #define QI_HIGH_REGISTER_NAMES \
2737 {"ah", "dh", "ch", "bh", }
2739 #define MMX_REGISTER_NAMES \
2740 {0,0,0,0,0,0,0,0,"mm0","mm1","mm2","mm3","mm4","mm5","mm6","mm7"}
2742 /* How to renumber registers for dbx and gdb. */
2744 #define DBX_REGISTER_NUMBER(n) \
2745 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2747 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2748 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2749 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2751 /* Before the prologue, RA is at 0(%esp). */
2752 #define INCOMING_RETURN_ADDR_RTX \
2753 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2755 /* After the prologue, RA is at -4(AP) in the current frame. */
2756 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2758 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, TARGET_64BIT ? -8 : -4))\
2759 : gen_rtx_MEM (Pmode, plus_constant (FRAME, TARGET_64BIT ? 8 : 4)))
2761 /* PC is dbx register 8; let's use that column for RA. */
2762 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2764 /* Before the prologue, the top of the frame is at 4(%esp). */
2765 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2767 /* This is how to output the definition of a user-level label named NAME,
2768 such as the label on a static function or variable NAME. */
2770 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2771 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2773 /* This is how to output an assembler line defining a `double' constant. */
2775 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2777 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2778 fprintf (FILE, "%s\t0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
2781 /* This is how to output a `long double' extended real constant. */
2783 #undef ASM_OUTPUT_LONG_DOUBLE
2784 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2786 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
2787 if (TARGET_128BIT_LONG_DOUBLE) \
2788 fprintf (FILE, "%s\t0x%lx,0x%lx,0x%lx,0x0\n", ASM_LONG, l[0], l[1], l[2]); \
2790 fprintf (FILE, "%s\t0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
2793 /* This is how to output an assembler line defining a `float' constant. */
2795 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2797 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2798 fprintf ((FILE), "%s\t0x%lx\n", ASM_LONG, l); \
2801 /* Store in OUTPUT a string (made with alloca) containing
2802 an assembler-name for a local static variable named NAME.
2803 LABELNO is an integer which is different for each call. */
2805 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2806 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2807 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2809 /* This is how to output an assembler line defining an `int' constant. */
2811 #define ASM_OUTPUT_INT(FILE,VALUE) \
2812 ( fprintf (FILE, "%s\t", ASM_LONG), \
2813 output_addr_const (FILE,(VALUE)), \
2816 /* Likewise for `char' and `short' constants. */
2817 /* is this supposed to do align too?? */
2819 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2820 ( fprintf (FILE, "%s\t", ASM_SHORT), \
2821 output_addr_const (FILE,(VALUE)), \
2824 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2825 ( fprintf (FILE, "%s", ASM_BYTE_OP), \
2826 output_addr_const (FILE, (VALUE)), \
2829 /* This is how to output an assembler line for a numeric constant byte. */
2831 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2832 asm_fprintf ((FILE), "%s0x%x\n", ASM_BYTE_OP, (VALUE))
2834 /* This is how to output an insn to push a register on the stack.
2835 It need not be very fast code. */
2837 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2838 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2840 /* This is how to output an insn to pop a register from the stack.
2841 It need not be very fast code. */
2843 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2844 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2846 /* This is how to output an element of a case-vector that is absolute.
2849 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2850 fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE)
2852 /* This is how to output an element of a case-vector that is relative.
2853 We don't use these on the 386 yet, because the ATT assembler can't do
2854 forward reference the differences.
2857 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2858 fprintf (FILE, "\t%s\t%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL)
2860 /* A C statement that outputs an address constant appropriate to
2861 for DWARF debugging. */
2863 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2864 i386_dwarf_output_addr_const((FILE),(X))
2866 /* Either simplify a location expression, or return the original. */
2868 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2869 i386_simplify_dwarf_addr(X)
2871 /* Define the parentheses used to group arithmetic operations
2872 in assembler code. */
2874 #define ASM_OPEN_PAREN ""
2875 #define ASM_CLOSE_PAREN ""
2877 /* Define results of standard character escape sequences. */
2878 #define TARGET_BELL 007
2879 #define TARGET_BS 010
2880 #define TARGET_TAB 011
2881 #define TARGET_NEWLINE 012
2882 #define TARGET_VT 013
2883 #define TARGET_FF 014
2884 #define TARGET_CR 015
2886 /* Print operand X (an rtx) in assembler syntax to file FILE.
2887 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2888 The CODE z takes the size of operand from the following digit, and
2889 outputs b,w,or l respectively.
2891 On the 80386, we use several such letters:
2892 f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
2893 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
2894 R -- print the prefix for register names.
2895 z -- print the opcode suffix for the size of the current operand.
2896 * -- print a star (in certain assembler syntax)
2897 A -- print an absolute memory reference.
2898 P -- if PIC, print an @PLT suffix.
2899 X -- don't print any sort of PIC '@' suffix for a symbol.
2900 s -- ??? something to do with double shifts. not actually used, afaik.
2901 C -- print a conditional move suffix corresponding to the op code.
2902 c -- likewise, but reverse the condition.
2903 F,f -- likewise, but for floating-point. */
2905 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2908 /* Print the name of a register based on its machine mode and number.
2909 If CODE is 'w', pretend the mode is HImode.
2910 If CODE is 'b', pretend the mode is QImode.
2911 If CODE is 'k', pretend the mode is SImode.
2912 If CODE is 'd', pretend the mode is DImode.
2913 If CODE is 'h', pretend the reg is the `high' byte register.
2914 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2916 #define PRINT_REG(X, CODE, FILE) \
2917 print_reg (X, CODE, FILE)
2919 #define PRINT_OPERAND(FILE, X, CODE) \
2920 print_operand (FILE, X, CODE)
2922 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2923 print_operand_address (FILE, ADDR)
2925 /* Print the name of a register for based on its machine mode and number.
2926 This macro is used to print debugging output.
2927 This macro is different from PRINT_REG in that it may be used in
2928 programs that are not linked with aux-output.o. */
2930 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2931 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2932 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2933 fprintf (FILE, "%d ", REGNO (X)); \
2934 if (REGNO (X) == FLAGS_REG) \
2935 { fputs ("flags", FILE); break; } \
2936 if (REGNO (X) == DIRFLAG_REG) \
2937 { fputs ("dirflag", FILE); break; } \
2938 if (REGNO (X) == FPSR_REG) \
2939 { fputs ("fpsr", FILE); break; } \
2940 if (REGNO (X) == ARG_POINTER_REGNUM) \
2941 { fputs ("argp", FILE); break; } \
2942 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2943 { fputs ("frame", FILE); break; } \
2944 if (STACK_TOP_P (X)) \
2945 { fputs ("st(0)", FILE); break; } \
2947 { fputs (hi_name[REGNO(X)], FILE); break; } \
2948 if (REX_INT_REG_P (X)) \
2950 switch (GET_MODE_SIZE (GET_MODE (X))) \
2954 fprintf (FILE, "r%i", REGNO (X) \
2955 - FIRST_REX_INT_REG + 8); \
2958 fprintf (FILE, "r%id", REGNO (X) \
2959 - FIRST_REX_INT_REG + 8); \
2962 fprintf (FILE, "r%iw", REGNO (X) \
2963 - FIRST_REX_INT_REG + 8); \
2966 fprintf (FILE, "r%ib", REGNO (X) \
2967 - FIRST_REX_INT_REG + 8); \
2972 switch (GET_MODE_SIZE (GET_MODE (X))) \
2975 fputs ("r", FILE); \
2976 fputs (hi_name[REGNO (X)], FILE); \
2979 fputs ("e", FILE); \
2981 fputs (hi_name[REGNO (X)], FILE); \
2984 fputs (qi_name[REGNO (X)], FILE); \
2989 /* Routines in libgcc that return floats must return them in an fp reg,
2990 just as other functions do which return such values.
2991 These macros make that happen. */
2993 #define FLOAT_VALUE_TYPE float
2994 #define INTIFY(FLOATVAL) FLOATVAL
2996 /* a letter which is not needed by the normal asm syntax, which
2997 we can use for operand syntax in the extended asm */
2999 #define ASM_OPERAND_LETTER '#'
3000 #define RET return ""
3001 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
3003 /* Define the codes that are matched by predicates in i386.c. */
3005 #define PREDICATE_CODES \
3006 {"const_int_1_operand", {CONST_INT}}, \
3007 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3008 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3009 LABEL_REF, SUBREG, REG, MEM}}, \
3010 {"pic_symbolic_operand", {CONST}}, \
3011 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3012 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3013 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3014 {"const1_operand", {CONST_INT}}, \
3015 {"const248_operand", {CONST_INT}}, \
3016 {"incdec_operand", {CONST_INT}}, \
3017 {"mmx_reg_operand", {REG}}, \
3018 {"reg_no_sp_operand", {SUBREG, REG}}, \
3019 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3020 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3021 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3022 {"q_regs_operand", {SUBREG, REG}}, \
3023 {"non_q_regs_operand", {SUBREG, REG}}, \
3024 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3025 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3026 GE, UNGE, LTGT, UNEQ}}, \
3027 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3028 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3030 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3031 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3032 UNGE, UNGT, LTGT, UNEQ }}, \
3033 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3034 {"ext_register_operand", {SUBREG, REG}}, \
3035 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3036 {"mult_operator", {MULT}}, \
3037 {"div_operator", {DIV}}, \
3038 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3039 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3040 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3041 LSHIFTRT, ROTATERT}}, \
3042 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3043 {"memory_displacement_operand", {MEM}}, \
3044 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3045 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3046 {"long_memory_operand", {MEM}},
3048 /* A list of predicates that do special things with modes, and so
3049 should not elicit warnings for VOIDmode match_operand. */
3051 #define SPECIAL_MODE_PREDICATES \
3052 "ext_register_operand",
3054 /* Variables in i386.c */
3055 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3056 extern const char *ix86_arch_string; /* for -march=<xxx> */
3057 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3058 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3059 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3060 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3061 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3062 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3063 extern int ix86_regparm; /* ix86_regparm_string as a number */
3064 extern int ix86_align_loops; /* power of two alignment for loops */
3065 extern int ix86_align_jumps; /* power of two alignment for non-loop jumps */
3066 extern int ix86_align_funcs; /* power of two alignment for functions */
3067 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3068 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3069 extern const char * const hi_reg_name[]; /* names for 16 bit regs */
3070 extern const char * const qi_reg_name[]; /* names for 8 bit regs (low) */
3071 extern const char * const qi_high_reg_name[]; /* names for 8 bit regs (high) */
3072 extern enum reg_class const regclass_map[]; /* smalled class containing REGNO */
3073 extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */
3074 extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */
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