1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 Under Section 7 of GPL version 3, you are granted additional
19 permissions described in the GCC Runtime Library Exception, version
20 3.1, as published by the Free Software Foundation.
22 You should have received a copy of the GNU General Public License and
23 a copy of the GCC Runtime Library Exception along with this program;
24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
25 <http://www.gnu.org/licenses/>. */
27 /* The purpose of this file is to define the characteristics of the i386,
28 independent of assembler syntax or operating system.
30 Three other files build on this one to describe a specific assembler syntax:
31 bsd386.h, att386.h, and sun386.h.
33 The actual tm.h file for a particular system should include
34 this file, and then the file for the appropriate assembler syntax.
36 Many macros that specify assembler syntax are omitted entirely from
37 this file because they really belong in the files for particular
38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
40 that start with ASM_ or end in ASM_OP. */
42 /* Redefines for option macros. */
44 #define TARGET_64BIT OPTION_ISA_64BIT
45 #define TARGET_MMX OPTION_ISA_MMX
46 #define TARGET_3DNOW OPTION_ISA_3DNOW
47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
48 #define TARGET_SSE OPTION_ISA_SSE
49 #define TARGET_SSE2 OPTION_ISA_SSE2
50 #define TARGET_SSE3 OPTION_ISA_SSE3
51 #define TARGET_SSSE3 OPTION_ISA_SSSE3
52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
54 #define TARGET_AVX OPTION_ISA_AVX
55 #define TARGET_FMA OPTION_ISA_FMA
56 #define TARGET_SSE4A OPTION_ISA_SSE4A
57 #define TARGET_FMA4 OPTION_ISA_FMA4
58 #define TARGET_XOP OPTION_ISA_XOP
59 #define TARGET_LWP OPTION_ISA_LWP
60 #define TARGET_ROUND OPTION_ISA_ROUND
61 #define TARGET_ABM OPTION_ISA_ABM
62 #define TARGET_BMI OPTION_ISA_BMI
63 #define TARGET_TBM OPTION_ISA_TBM
64 #define TARGET_POPCNT OPTION_ISA_POPCNT
65 #define TARGET_SAHF OPTION_ISA_SAHF
66 #define TARGET_MOVBE OPTION_ISA_MOVBE
67 #define TARGET_CRC32 OPTION_ISA_CRC32
68 #define TARGET_AES OPTION_ISA_AES
69 #define TARGET_PCLMUL OPTION_ISA_PCLMUL
70 #define TARGET_CMPXCHG16B OPTION_ISA_CX16
71 #define TARGET_FSGSBASE OPTION_ISA_FSGSBASE
72 #define TARGET_RDRND OPTION_ISA_RDRND
73 #define TARGET_F16C OPTION_ISA_F16C
76 /* SSE4.1 defines round instructions */
77 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
78 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
80 #include "config/vxworks-dummy.h"
82 /* Algorithm to expand string function with. */
95 #define MAX_STRINGOP_ALGS 4
97 /* Specify what algorithm to use for stringops on known size.
98 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
99 known at compile time or estimated via feedback, the SIZE array
100 is walked in order until MAX is greater then the estimate (or -1
101 means infinity). Corresponding ALG is used then.
102 For example initializer:
103 {{256, loop}, {-1, rep_prefix_4_byte}}
104 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
105 be used otherwise. */
108 const enum stringop_alg unknown_size;
109 const struct stringop_strategy {
111 const enum stringop_alg alg;
112 } size [MAX_STRINGOP_ALGS];
115 /* Define the specific costs for a given cpu */
117 struct processor_costs {
118 const int add; /* cost of an add instruction */
119 const int lea; /* cost of a lea instruction */
120 const int shift_var; /* variable shift costs */
121 const int shift_const; /* constant shift costs */
122 const int mult_init[5]; /* cost of starting a multiply
123 in QImode, HImode, SImode, DImode, TImode*/
124 const int mult_bit; /* cost of multiply per each bit set */
125 const int divide[5]; /* cost of a divide/mod
126 in QImode, HImode, SImode, DImode, TImode*/
127 int movsx; /* The cost of movsx operation. */
128 int movzx; /* The cost of movzx operation. */
129 const int large_insn; /* insns larger than this cost more */
130 const int move_ratio; /* The threshold of number of scalar
131 memory-to-memory move insns. */
132 const int movzbl_load; /* cost of loading using movzbl */
133 const int int_load[3]; /* cost of loading integer registers
134 in QImode, HImode and SImode relative
135 to reg-reg move (2). */
136 const int int_store[3]; /* cost of storing integer register
137 in QImode, HImode and SImode */
138 const int fp_move; /* cost of reg,reg fld/fst */
139 const int fp_load[3]; /* cost of loading FP register
140 in SFmode, DFmode and XFmode */
141 const int fp_store[3]; /* cost of storing FP register
142 in SFmode, DFmode and XFmode */
143 const int mmx_move; /* cost of moving MMX register. */
144 const int mmx_load[2]; /* cost of loading MMX register
145 in SImode and DImode */
146 const int mmx_store[2]; /* cost of storing MMX register
147 in SImode and DImode */
148 const int sse_move; /* cost of moving SSE register. */
149 const int sse_load[3]; /* cost of loading SSE register
150 in SImode, DImode and TImode*/
151 const int sse_store[3]; /* cost of storing SSE register
152 in SImode, DImode and TImode*/
153 const int mmxsse_to_integer; /* cost of moving mmxsse register to
154 integer and vice versa. */
155 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
156 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
157 const int prefetch_block; /* bytes moved to cache for prefetch. */
158 const int simultaneous_prefetches; /* number of parallel prefetch
160 const int branch_cost; /* Default value for BRANCH_COST. */
161 const int fadd; /* cost of FADD and FSUB instructions. */
162 const int fmul; /* cost of FMUL instruction. */
163 const int fdiv; /* cost of FDIV instruction. */
164 const int fabs; /* cost of FABS instruction. */
165 const int fchs; /* cost of FCHS instruction. */
166 const int fsqrt; /* cost of FSQRT instruction. */
167 /* Specify what algorithm
168 to use for stringops on unknown size. */
169 struct stringop_algs memcpy[2], memset[2];
170 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
172 const int scalar_load_cost; /* Cost of scalar load. */
173 const int scalar_store_cost; /* Cost of scalar store. */
174 const int vec_stmt_cost; /* Cost of any vector operation, excluding
175 load, store, vector-to-scalar and
176 scalar-to-vector operation. */
177 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
178 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
179 const int vec_align_load_cost; /* Cost of aligned vector load. */
180 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
181 const int vec_store_cost; /* Cost of vector store. */
182 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
184 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
185 vectorizer cost model. */
188 extern const struct processor_costs *ix86_cost;
189 extern const struct processor_costs ix86_size_cost;
191 #define ix86_cur_cost() \
192 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
194 /* Macros used in the machine description to test the flags. */
196 /* configure can arrange to make this 2, to force a 486. */
198 #ifndef TARGET_CPU_DEFAULT
199 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
202 #ifndef TARGET_FPMATH_DEFAULT
203 #define TARGET_FPMATH_DEFAULT \
204 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
207 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
209 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
210 compile-time constant. */
214 #define TARGET_64BIT 1
216 #define TARGET_64BIT 0
219 #ifndef TARGET_BI_ARCH
221 #if TARGET_64BIT_DEFAULT
222 #define TARGET_64BIT 1
224 #define TARGET_64BIT 0
229 #define HAS_LONG_COND_BRANCH 1
230 #define HAS_LONG_UNCOND_BRANCH 1
232 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
233 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
234 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
235 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
236 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
237 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
238 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
239 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
240 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
241 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
242 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
243 #define TARGET_CORE2_32 (ix86_tune == PROCESSOR_CORE2_32)
244 #define TARGET_CORE2_64 (ix86_tune == PROCESSOR_CORE2_64)
245 #define TARGET_CORE2 (TARGET_CORE2_32 || TARGET_CORE2_64)
246 #define TARGET_COREI7_32 (ix86_tune == PROCESSOR_COREI7_32)
247 #define TARGET_COREI7_64 (ix86_tune == PROCESSOR_COREI7_64)
248 #define TARGET_COREI7 (TARGET_COREI7_32 || TARGET_COREI7_64)
249 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
250 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
251 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
252 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
253 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
254 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
255 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
257 /* Feature tests against the various tunings. */
258 enum ix86_tune_indices {
260 X86_TUNE_PUSH_MEMORY,
261 X86_TUNE_ZERO_EXTEND_WITH_AND,
262 X86_TUNE_UNROLL_STRLEN,
263 X86_TUNE_DEEP_BRANCH_PREDICTION,
264 X86_TUNE_BRANCH_PREDICTION_HINTS,
265 X86_TUNE_DOUBLE_WITH_ADD,
268 X86_TUNE_PARTIAL_REG_STALL,
269 X86_TUNE_PARTIAL_FLAG_REG_STALL,
270 X86_TUNE_USE_HIMODE_FIOP,
271 X86_TUNE_USE_SIMODE_FIOP,
275 X86_TUNE_SPLIT_LONG_MOVES,
276 X86_TUNE_READ_MODIFY_WRITE,
277 X86_TUNE_READ_MODIFY,
278 X86_TUNE_PROMOTE_QIMODE,
279 X86_TUNE_FAST_PREFIX,
280 X86_TUNE_SINGLE_STRINGOP,
281 X86_TUNE_QIMODE_MATH,
282 X86_TUNE_HIMODE_MATH,
283 X86_TUNE_PROMOTE_QI_REGS,
284 X86_TUNE_PROMOTE_HI_REGS,
287 X86_TUNE_SINGLE_PUSH,
288 X86_TUNE_DOUBLE_PUSH,
289 X86_TUNE_INTEGER_DFMODE_MOVES,
290 X86_TUNE_PARTIAL_REG_DEPENDENCY,
291 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
292 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL,
293 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL,
294 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL,
295 X86_TUNE_SSE_SPLIT_REGS,
296 X86_TUNE_SSE_TYPELESS_STORES,
297 X86_TUNE_SSE_LOAD0_BY_PXOR,
298 X86_TUNE_MEMORY_MISMATCH_STALL,
299 X86_TUNE_PROLOGUE_USING_MOVE,
300 X86_TUNE_EPILOGUE_USING_MOVE,
303 X86_TUNE_INTER_UNIT_MOVES,
304 X86_TUNE_INTER_UNIT_CONVERSIONS,
305 X86_TUNE_FOUR_JUMP_LIMIT,
309 X86_TUNE_PAD_RETURNS,
310 X86_TUNE_PAD_SHORT_FUNCTION,
311 X86_TUNE_EXT_80387_CONSTANTS,
312 X86_TUNE_SHORTEN_X87_SSE,
313 X86_TUNE_AVOID_VECTOR_DECODE,
314 X86_TUNE_PROMOTE_HIMODE_IMUL,
315 X86_TUNE_SLOW_IMUL_IMM32_MEM,
316 X86_TUNE_SLOW_IMUL_IMM8,
317 X86_TUNE_MOVE_M1_VIA_OR,
318 X86_TUNE_NOT_UNPAIRABLE,
319 X86_TUNE_NOT_VECTORMODE,
320 X86_TUNE_USE_VECTOR_FP_CONVERTS,
321 X86_TUNE_USE_VECTOR_CONVERTS,
322 X86_TUNE_FUSE_CMP_AND_BRANCH,
324 X86_TUNE_VECTORIZE_DOUBLE,
329 extern unsigned char ix86_tune_features[X86_TUNE_LAST];
331 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
332 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
333 #define TARGET_ZERO_EXTEND_WITH_AND \
334 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
335 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
336 #define TARGET_DEEP_BRANCH_PREDICTION \
337 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
338 #define TARGET_BRANCH_PREDICTION_HINTS \
339 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
340 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
341 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
342 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
343 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
344 #define TARGET_PARTIAL_FLAG_REG_STALL \
345 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
346 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
347 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
348 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
349 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
350 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
351 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
352 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
353 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
354 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
355 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
356 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
357 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
358 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
359 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
360 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
361 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
362 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
363 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
364 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
365 #define TARGET_INTEGER_DFMODE_MOVES \
366 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
367 #define TARGET_PARTIAL_REG_DEPENDENCY \
368 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
369 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
370 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
371 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
372 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
373 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
374 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
375 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
376 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
377 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
378 #define TARGET_SSE_TYPELESS_STORES \
379 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
380 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
381 #define TARGET_MEMORY_MISMATCH_STALL \
382 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
383 #define TARGET_PROLOGUE_USING_MOVE \
384 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
385 #define TARGET_EPILOGUE_USING_MOVE \
386 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
387 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
388 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
389 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
390 #define TARGET_INTER_UNIT_CONVERSIONS\
391 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
392 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
393 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
394 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
395 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
396 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
397 #define TARGET_PAD_SHORT_FUNCTION \
398 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
399 #define TARGET_EXT_80387_CONSTANTS \
400 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
401 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
402 #define TARGET_AVOID_VECTOR_DECODE \
403 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
404 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
405 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
406 #define TARGET_SLOW_IMUL_IMM32_MEM \
407 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
408 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
409 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
410 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
411 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
412 #define TARGET_USE_VECTOR_FP_CONVERTS \
413 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
414 #define TARGET_USE_VECTOR_CONVERTS \
415 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
416 #define TARGET_FUSE_CMP_AND_BRANCH \
417 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
418 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
419 #define TARGET_VECTORIZE_DOUBLE \
420 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
422 /* Feature tests against the various architecture variations. */
423 enum ix86_arch_indices {
424 X86_ARCH_CMOVE, /* || TARGET_SSE */
433 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
435 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
436 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
437 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
438 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
439 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
441 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
443 extern int x86_prefetch_sse;
445 #define TARGET_PREFETCH_SSE x86_prefetch_sse
447 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
449 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
450 #define TARGET_MIX_SSE_I387 \
451 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
453 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
454 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
455 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
456 #define TARGET_SUN_TLS 0
458 #ifndef TARGET_64BIT_DEFAULT
459 #define TARGET_64BIT_DEFAULT 0
461 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
462 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
465 /* Fence to use after loop using storent. */
467 extern tree x86_mfence;
468 #define FENCE_FOLLOWING_MOVNT x86_mfence
470 /* Once GDB has been enhanced to deal with functions without frame
471 pointers, we can change this to allow for elimination of
472 the frame pointer in leaf functions. */
473 #define TARGET_DEFAULT 0
475 /* Extra bits to force. */
476 #define TARGET_SUBTARGET_DEFAULT 0
477 #define TARGET_SUBTARGET_ISA_DEFAULT 0
479 /* Extra bits to force on w/ 32-bit mode. */
480 #define TARGET_SUBTARGET32_DEFAULT 0
481 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
483 /* Extra bits to force on w/ 64-bit mode. */
484 #define TARGET_SUBTARGET64_DEFAULT 0
485 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
487 /* Replace MACH-O, ifdefs by in-line tests, where possible.
488 (a) Macros defined in config/i386/darwin.h */
489 #define TARGET_MACHO 0
490 #define TARGET_MACHO_BRANCH_ISLANDS 0
491 #define MACHOPIC_ATT_STUB 0
492 /* (b) Macros defined in config/darwin.h */
493 #define MACHO_DYNAMIC_NO_PIC_P 0
494 #define MACHOPIC_INDIRECT 0
495 #define MACHOPIC_PURE 0
497 /* For the Windows 64-bit ABI. */
498 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
500 /* This is re-defined by cygming.h. */
503 /* Available call abi. */
510 /* The abi used by target. */
511 extern enum calling_abi ix86_abi;
513 /* The default abi used by target. */
514 #define DEFAULT_ABI SYSV_ABI
516 /* Subtargets may reset this to 1 in order to enable 96-bit long double
517 with the rounding mode forced to 53 bits. */
518 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
520 /* -march=native handling only makes sense with compiler running on
521 an x86 or x86_64 chip. If changing this condition, also change
522 the condition in driver-i386.c. */
523 #if defined(__i386__) || defined(__x86_64__)
524 /* In driver-i386.c. */
525 extern const char *host_detect_local_cpu (int argc, const char **argv);
526 #define EXTRA_SPEC_FUNCTIONS \
527 { "local_cpu_detect", host_detect_local_cpu },
528 #define HAVE_LOCAL_CPU_DETECT
531 #if TARGET_64BIT_DEFAULT
532 #define OPT_ARCH64 "!m32"
533 #define OPT_ARCH32 "m32"
535 #define OPT_ARCH64 "m64"
536 #define OPT_ARCH32 "!m64"
539 /* Support for configure-time defaults of some command line options.
540 The order here is important so that -march doesn't squash the
541 tune or cpu values. */
542 #define OPTION_DEFAULT_SPECS \
543 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
544 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
545 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
546 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
547 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
548 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
549 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
550 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
551 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
553 /* Specs for the compiler proper */
556 #define CC1_CPU_SPEC_1 "\
558 %n'-msse5' was removed\n}"
560 #ifndef HAVE_LOCAL_CPU_DETECT
561 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
563 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
564 "%{march=native:%>march=native %:local_cpu_detect(arch) \
565 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
566 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
570 /* Target CPU builtins. */
571 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
573 /* Target Pragmas. */
574 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
576 enum target_cpu_default
578 TARGET_CPU_DEFAULT_generic = 0,
580 TARGET_CPU_DEFAULT_i386,
581 TARGET_CPU_DEFAULT_i486,
582 TARGET_CPU_DEFAULT_pentium,
583 TARGET_CPU_DEFAULT_pentium_mmx,
584 TARGET_CPU_DEFAULT_pentiumpro,
585 TARGET_CPU_DEFAULT_pentium2,
586 TARGET_CPU_DEFAULT_pentium3,
587 TARGET_CPU_DEFAULT_pentium4,
588 TARGET_CPU_DEFAULT_pentium_m,
589 TARGET_CPU_DEFAULT_prescott,
590 TARGET_CPU_DEFAULT_nocona,
591 TARGET_CPU_DEFAULT_core2,
592 TARGET_CPU_DEFAULT_corei7,
593 TARGET_CPU_DEFAULT_atom,
595 TARGET_CPU_DEFAULT_geode,
596 TARGET_CPU_DEFAULT_k6,
597 TARGET_CPU_DEFAULT_k6_2,
598 TARGET_CPU_DEFAULT_k6_3,
599 TARGET_CPU_DEFAULT_athlon,
600 TARGET_CPU_DEFAULT_athlon_sse,
601 TARGET_CPU_DEFAULT_k8,
602 TARGET_CPU_DEFAULT_amdfam10,
603 TARGET_CPU_DEFAULT_bdver1,
604 TARGET_CPU_DEFAULT_btver1,
606 TARGET_CPU_DEFAULT_max
610 #define CC1_SPEC "%(cc1_cpu) "
613 /* This macro defines names of additional specifications to put in the
614 specs that can be used in various specifications like CC1_SPEC. Its
615 definition is an initializer with a subgrouping for each command option.
617 Each subgrouping contains a string constant, that defines the
618 specification name, and a string constant that used by the GCC driver
621 Do not define this macro if it does not need to do anything. */
623 #ifndef SUBTARGET_EXTRA_SPECS
624 #define SUBTARGET_EXTRA_SPECS
627 #define EXTRA_SPECS \
628 { "cc1_cpu", CC1_CPU_SPEC }, \
629 SUBTARGET_EXTRA_SPECS
632 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
633 FPU, assume that the fpcw is set to extended precision; when using
634 only SSE, rounding is correct; when using both SSE and the FPU,
635 the rounding precision is indeterminate, since either may be chosen
636 apparently at random. */
637 #define TARGET_FLT_EVAL_METHOD \
638 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
640 /* Whether to allow x87 floating-point arithmetic on MODE (one of
641 SFmode, DFmode and XFmode) in the current excess precision
643 #define X87_ENABLE_ARITH(MODE) \
644 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
646 /* Likewise, whether to allow direct conversions from integer mode
647 IMODE (HImode, SImode or DImode) to MODE. */
648 #define X87_ENABLE_FLOAT(MODE, IMODE) \
649 (flag_excess_precision == EXCESS_PRECISION_FAST \
650 || (MODE) == XFmode \
651 || ((MODE) == DFmode && (IMODE) == SImode) \
652 || (IMODE) == HImode)
654 /* target machine storage layout */
656 #define SHORT_TYPE_SIZE 16
657 #define INT_TYPE_SIZE 32
658 #define LONG_LONG_TYPE_SIZE 64
659 #define FLOAT_TYPE_SIZE 32
660 #define DOUBLE_TYPE_SIZE 64
661 #define LONG_DOUBLE_TYPE_SIZE 80
663 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
665 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
666 #define MAX_BITS_PER_WORD 64
668 #define MAX_BITS_PER_WORD 32
671 /* Define this if most significant byte of a word is the lowest numbered. */
672 /* That is true on the 80386. */
674 #define BITS_BIG_ENDIAN 0
676 /* Define this if most significant byte of a word is the lowest numbered. */
677 /* That is not true on the 80386. */
678 #define BYTES_BIG_ENDIAN 0
680 /* Define this if most significant word of a multiword number is the lowest
682 /* Not true for 80386 */
683 #define WORDS_BIG_ENDIAN 0
685 /* Width of a word, in units (bytes). */
686 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
689 #define MIN_UNITS_PER_WORD 4
692 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
693 #define PARM_BOUNDARY BITS_PER_WORD
695 /* Boundary (in *bits*) on which stack pointer should be aligned. */
696 #define STACK_BOUNDARY \
697 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
699 /* Stack boundary of the main function guaranteed by OS. */
700 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
702 /* Minimum stack boundary. */
703 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
705 /* Boundary (in *bits*) on which the stack pointer prefers to be
706 aligned; the compiler cannot rely on having this alignment. */
707 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
709 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
710 both 32bit and 64bit, to support codes that need 128 bit stack
711 alignment for SSE instructions, but can't realign the stack. */
712 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
714 /* 1 if -mstackrealign should be turned on by default. It will
715 generate an alternate prologue and epilogue that realigns the
716 runtime stack if nessary. This supports mixing codes that keep a
717 4-byte aligned stack, as specified by i386 psABI, with codes that
718 need a 16-byte aligned stack, as required by SSE instructions. */
719 #define STACK_REALIGN_DEFAULT 0
721 /* Boundary (in *bits*) on which the incoming stack is aligned. */
722 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
724 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
725 mandatory for the 64-bit ABI, and may or may not be true for other
726 operating systems. */
727 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
729 /* Minimum allocation boundary for the code of a function. */
730 #define FUNCTION_BOUNDARY 8
732 /* C++ stores the virtual bit in the lowest bit of function pointers. */
733 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
735 /* Minimum size in bits of the largest boundary to which any
736 and all fundamental data types supported by the hardware
737 might need to be aligned. No data type wants to be aligned
740 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
741 and Pentium Pro XFmode values at 128 bit boundaries. */
743 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128)
745 /* Maximum stack alignment. */
746 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
748 /* Alignment value for attribute ((aligned)). It is a constant since
749 it is the part of the ABI. We shouldn't change it with -mavx. */
750 #define ATTRIBUTE_ALIGNED_VALUE 128
752 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
753 #define ALIGN_MODE_128(MODE) \
754 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
756 /* The published ABIs say that doubles should be aligned on word
757 boundaries, so lower the alignment for structure fields unless
758 -malign-double is set. */
760 /* ??? Blah -- this macro is used directly by libobjc. Since it
761 supports no vector modes, cut out the complexity and fall back
762 on BIGGEST_FIELD_ALIGNMENT. */
763 #ifdef IN_TARGET_LIBS
765 #define BIGGEST_FIELD_ALIGNMENT 128
767 #define BIGGEST_FIELD_ALIGNMENT 32
770 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
771 x86_field_alignment (FIELD, COMPUTED)
774 /* If defined, a C expression to compute the alignment given to a
775 constant that is being placed in memory. EXP is the constant
776 and ALIGN is the alignment that the object would ordinarily have.
777 The value of this macro is used instead of that alignment to align
780 If this macro is not defined, then ALIGN is used.
782 The typical use of this macro is to increase alignment for string
783 constants to be word aligned so that `strcpy' calls that copy
784 constants can be done inline. */
786 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
788 /* If defined, a C expression to compute the alignment for a static
789 variable. TYPE is the data type, and ALIGN is the alignment that
790 the object would ordinarily have. The value of this macro is used
791 instead of that alignment to align the object.
793 If this macro is not defined, then ALIGN is used.
795 One use of this macro is to increase alignment of medium-size
796 data to make it all fit in fewer cache lines. Another is to
797 cause character arrays to be word-aligned so that `strcpy' calls
798 that copy constants to character arrays can be done inline. */
800 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
802 /* If defined, a C expression to compute the alignment for a local
803 variable. TYPE is the data type, and ALIGN is the alignment that
804 the object would ordinarily have. The value of this macro is used
805 instead of that alignment to align the object.
807 If this macro is not defined, then ALIGN is used.
809 One use of this macro is to increase alignment of medium-size
810 data to make it all fit in fewer cache lines. */
812 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
813 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
815 /* If defined, a C expression to compute the alignment for stack slot.
816 TYPE is the data type, MODE is the widest mode available, and ALIGN
817 is the alignment that the slot would ordinarily have. The value of
818 this macro is used instead of that alignment to align the slot.
820 If this macro is not defined, then ALIGN is used when TYPE is NULL,
821 Otherwise, LOCAL_ALIGNMENT will be used.
823 One use of this macro is to set alignment of stack slot to the
824 maximum alignment of all possible modes which the slot may have. */
826 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
827 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
829 /* If defined, a C expression to compute the alignment for a local
832 If this macro is not defined, then
833 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
835 One use of this macro is to increase alignment of medium-size
836 data to make it all fit in fewer cache lines. */
838 #define LOCAL_DECL_ALIGNMENT(DECL) \
839 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
841 /* If defined, a C expression to compute the minimum required alignment
842 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
843 MODE, assuming normal alignment ALIGN.
845 If this macro is not defined, then (ALIGN) will be used. */
847 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
848 ix86_minimum_alignment (EXP, MODE, ALIGN)
851 /* Set this nonzero if move instructions will actually fail to work
852 when given unaligned data. */
853 #define STRICT_ALIGNMENT 0
855 /* If bit field type is int, don't let it cross an int,
856 and give entire struct the alignment of an int. */
857 /* Required on the 386 since it doesn't have bit-field insns. */
858 #define PCC_BITFIELD_TYPE_MATTERS 1
860 /* Standard register usage. */
862 /* This processor has special stack-like registers. See reg-stack.c
867 #define IS_STACK_MODE(MODE) \
868 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \
869 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \
872 /* Cover class containing the stack registers. */
873 #define STACK_REG_COVER_CLASS FLOAT_REGS
875 /* Number of actual hardware registers.
876 The hardware registers are assigned numbers for the compiler
877 from 0 to just below FIRST_PSEUDO_REGISTER.
878 All registers that the compiler knows about must be given numbers,
879 even those that are not normally considered general registers.
881 In the 80386 we give the 8 general purpose registers the numbers 0-7.
882 We number the floating point registers 8-15.
883 Note that registers 0-7 can be accessed as a short or int,
884 while only 0-3 may be used with byte `mov' instructions.
886 Reg 16 does not correspond to any hardware register, but instead
887 appears in the RTL as an argument pointer prior to reload, and is
888 eliminated during reloading in favor of either the stack or frame
891 #define FIRST_PSEUDO_REGISTER 53
893 /* Number of hardware registers that go into the DWARF-2 unwind info.
894 If not defined, equals FIRST_PSEUDO_REGISTER. */
896 #define DWARF_FRAME_REGISTERS 17
898 /* 1 for registers that have pervasive standard uses
899 and are not available for the register allocator.
900 On the 80386, the stack pointer is such, as is the arg pointer.
902 The value is zero if the register is not fixed on either 32 or
903 64 bit targets, one if the register if fixed on both 32 and 64
904 bit targets, two if it is only fixed on 32bit targets and three
905 if its only fixed on 64bit targets.
906 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
908 #define FIXED_REGISTERS \
909 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
910 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
911 /*arg,flags,fpsr,fpcr,frame*/ \
913 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
914 0, 0, 0, 0, 0, 0, 0, 0, \
915 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
916 0, 0, 0, 0, 0, 0, 0, 0, \
917 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
918 2, 2, 2, 2, 2, 2, 2, 2, \
919 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
920 2, 2, 2, 2, 2, 2, 2, 2 }
923 /* 1 for registers not available across function calls.
924 These must include the FIXED_REGISTERS and also any
925 registers that can be used without being saved.
926 The latter must include the registers where values are returned
927 and the register where structure-value addresses are passed.
928 Aside from that, you can include as many other registers as you like.
930 The value is zero if the register is not call used on either 32 or
931 64 bit targets, one if the register if call used on both 32 and 64
932 bit targets, two if it is only call used on 32bit targets and three
933 if its only call used on 64bit targets.
934 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
936 #define CALL_USED_REGISTERS \
937 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
938 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
939 /*arg,flags,fpsr,fpcr,frame*/ \
941 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
942 1, 1, 1, 1, 1, 1, 1, 1, \
943 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
944 1, 1, 1, 1, 1, 1, 1, 1, \
945 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
946 1, 1, 1, 1, 2, 2, 2, 2, \
947 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
948 1, 1, 1, 1, 1, 1, 1, 1 }
950 /* Order in which to allocate registers. Each register must be
951 listed once, even those in FIXED_REGISTERS. List frame pointer
952 late and fixed registers last. Note that, in general, we prefer
953 registers listed in CALL_USED_REGISTERS, keeping the others
954 available for storage of persistent values.
956 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
957 so this is just empty initializer for array. */
959 #define REG_ALLOC_ORDER \
960 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
961 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
962 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
965 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
966 to be rearranged based on a particular function. When using sse math,
967 we want to allocate SSE before x87 registers and vice versa. */
969 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
972 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
974 /* Return number of consecutive hard regs needed starting at reg REGNO
975 to hold something of mode MODE.
976 This is ordinarily the length in words of a value of mode MODE
977 but can be less for certain modes in special long registers.
979 Actually there are no two word move instructions for consecutive
980 registers. And only registers 0-3 may have mov byte instructions
983 #define HARD_REGNO_NREGS(REGNO, MODE) \
984 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
985 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
986 : ((MODE) == XFmode \
987 ? (TARGET_64BIT ? 2 : 3) \
989 ? (TARGET_64BIT ? 4 : 6) \
990 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
992 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
993 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
994 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
996 : ((MODE) == XFmode || (MODE) == XCmode)) \
999 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1001 #define VALID_AVX256_REG_MODE(MODE) \
1002 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1003 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1005 #define VALID_SSE2_REG_MODE(MODE) \
1006 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1007 || (MODE) == V2DImode || (MODE) == DFmode)
1009 #define VALID_SSE_REG_MODE(MODE) \
1010 ((MODE) == V1TImode || (MODE) == TImode \
1011 || (MODE) == V4SFmode || (MODE) == V4SImode \
1012 || (MODE) == SFmode || (MODE) == TFmode)
1014 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1015 ((MODE) == V2SFmode || (MODE) == SFmode)
1017 #define VALID_MMX_REG_MODE(MODE) \
1018 ((MODE == V1DImode) || (MODE) == DImode \
1019 || (MODE) == V2SImode || (MODE) == SImode \
1020 || (MODE) == V4HImode || (MODE) == V8QImode)
1022 #define VALID_DFP_MODE_P(MODE) \
1023 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1025 #define VALID_FP_MODE_P(MODE) \
1026 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1027 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1029 #define VALID_INT_MODE_P(MODE) \
1030 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1031 || (MODE) == DImode \
1032 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1033 || (MODE) == CDImode \
1034 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1035 || (MODE) == TFmode || (MODE) == TCmode)))
1037 /* Return true for modes passed in SSE registers. */
1038 #define SSE_REG_MODE_P(MODE) \
1039 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1040 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1041 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1042 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1043 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1045 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1047 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1048 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1050 /* Value is 1 if it is a good idea to tie two pseudo registers
1051 when one has mode MODE1 and one has mode MODE2.
1052 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1053 for any hard reg, then this must be 0 for correct output. */
1055 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1057 /* It is possible to write patterns to move flags; but until someone
1059 #define AVOID_CCMODE_COPIES
1061 /* Specify the modes required to caller save a given hard regno.
1062 We do this on i386 to prevent flags from being saved at all.
1064 Kill any attempts to combine saving of modes. */
1066 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1067 (CC_REGNO_P (REGNO) ? VOIDmode \
1068 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1069 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1070 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1071 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \
1074 /* The only ABI that saves SSE registers across calls is Win64 (thus no
1075 need to check the current ABI here), and with AVX enabled Win64 only
1076 guarantees that the low 16 bytes are saved. */
1077 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1078 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16)
1080 /* Specify the registers used for certain standard purposes.
1081 The values of these macros are register numbers. */
1083 /* on the 386 the pc register is %eip, and is not usable as a general
1084 register. The ordinary mov instructions won't work */
1085 /* #define PC_REGNUM */
1087 /* Register to use for pushing function arguments. */
1088 #define STACK_POINTER_REGNUM 7
1090 /* Base register for access to local variables of the function. */
1091 #define HARD_FRAME_POINTER_REGNUM 6
1093 /* Base register for access to local variables of the function. */
1094 #define FRAME_POINTER_REGNUM 20
1096 /* First floating point reg */
1097 #define FIRST_FLOAT_REG 8
1099 /* First & last stack-like regs */
1100 #define FIRST_STACK_REG FIRST_FLOAT_REG
1101 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1103 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1104 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1106 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1107 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1109 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1110 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1112 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1113 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1115 /* Override this in other tm.h files to cope with various OS lossage
1116 requiring a frame pointer. */
1117 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1118 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1121 /* Make sure we can access arbitrary call frames. */
1122 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1124 /* Base register for access to arguments of the function. */
1125 #define ARG_POINTER_REGNUM 16
1127 /* Register to hold the addressing base for position independent
1128 code access to data items. We don't use PIC pointer for 64bit
1129 mode. Define the regnum to dummy value to prevent gcc from
1130 pessimizing code dealing with EBX.
1132 To avoid clobbering a call-saved register unnecessarily, we renumber
1133 the pic register when possible. The change is visible after the
1134 prologue has been emitted. */
1136 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1138 #define PIC_OFFSET_TABLE_REGNUM \
1139 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1140 || !flag_pic ? INVALID_REGNUM \
1141 : reload_completed ? REGNO (pic_offset_table_rtx) \
1142 : REAL_PIC_OFFSET_TABLE_REGNUM)
1144 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1146 /* This is overridden by <cygwin.h>. */
1147 #define MS_AGGREGATE_RETURN 0
1149 /* This is overridden by <netware.h>. */
1150 #define KEEP_AGGREGATE_RETURN_POINTER 0
1152 /* Define the classes of registers for register constraints in the
1153 machine description. Also define ranges of constants.
1155 One of the classes must always be named ALL_REGS and include all hard regs.
1156 If there is more than one class, another class must be named NO_REGS
1157 and contain no registers.
1159 The name GENERAL_REGS must be the name of a class (or an alias for
1160 another name such as ALL_REGS). This is the class of registers
1161 that is allowed by "g" or "r" in a register constraint.
1162 Also, registers outside this class are allocated only when
1163 instructions express preferences for them.
1165 The classes must be numbered in nondecreasing order; that is,
1166 a larger-numbered class must never be contained completely
1167 in a smaller-numbered class.
1169 For any two classes, it is very desirable that there be another
1170 class that represents their union.
1172 It might seem that class BREG is unnecessary, since no useful 386
1173 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1174 and the "b" register constraint is useful in asms for syscalls.
1176 The flags, fpsr and fpcr registers are in no class. */
1181 AREG, DREG, CREG, BREG, SIREG, DIREG,
1182 AD_REGS, /* %eax/%edx for DImode */
1183 CLOBBERED_REGS, /* call-clobbered integers */
1184 Q_REGS, /* %eax %ebx %ecx %edx */
1185 NON_Q_REGS, /* %esi %edi %ebp %esp */
1186 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1187 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1188 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1189 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1190 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1201 ALL_REGS, LIM_REG_CLASSES
1204 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1206 #define INTEGER_CLASS_P(CLASS) \
1207 reg_class_subset_p ((CLASS), GENERAL_REGS)
1208 #define FLOAT_CLASS_P(CLASS) \
1209 reg_class_subset_p ((CLASS), FLOAT_REGS)
1210 #define SSE_CLASS_P(CLASS) \
1211 reg_class_subset_p ((CLASS), SSE_REGS)
1212 #define MMX_CLASS_P(CLASS) \
1213 ((CLASS) == MMX_REGS)
1214 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1215 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1216 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1217 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1218 #define MAYBE_SSE_CLASS_P(CLASS) \
1219 reg_classes_intersect_p (SSE_REGS, (CLASS))
1220 #define MAYBE_MMX_CLASS_P(CLASS) \
1221 reg_classes_intersect_p (MMX_REGS, (CLASS))
1223 #define Q_CLASS_P(CLASS) \
1224 reg_class_subset_p ((CLASS), Q_REGS)
1226 /* Give names of register classes as strings for dump file. */
1228 #define REG_CLASS_NAMES \
1230 "AREG", "DREG", "CREG", "BREG", \
1234 "Q_REGS", "NON_Q_REGS", \
1238 "FP_TOP_REG", "FP_SECOND_REG", \
1243 "FP_TOP_SSE_REGS", \
1244 "FP_SECOND_SSE_REGS", \
1248 "FLOAT_INT_SSE_REGS", \
1251 /* Define which registers fit in which classes. This is an initializer
1252 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1254 Note that the default setting of CLOBBERED_REGS is for 32-bit; this
1255 is adjusted by TARGET_CONDITIONAL_REGISTER_USAGE for the 64-bit ABI
1258 #define REG_CLASS_CONTENTS \
1260 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1261 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1262 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1263 { 0x03, 0x0 }, /* AD_REGS */ \
1264 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \
1265 { 0x0f, 0x0 }, /* Q_REGS */ \
1266 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1267 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1268 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1269 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1270 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1271 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1272 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1273 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1274 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1275 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1276 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1277 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1278 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1279 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1280 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1281 { 0xffffffff,0x1fffff } \
1284 /* The same information, inverted:
1285 Return the class number of the smallest class containing
1286 reg number REGNO. This could be a conditional expression
1287 or could index an array. */
1289 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1291 /* When this hook returns true for MODE, the compiler allows
1292 registers explicitly used in the rtl to be used as spill registers
1293 but prevents the compiler from extending the lifetime of these
1295 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1297 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG)
1299 #define GENERAL_REGNO_P(N) \
1300 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1302 #define GENERAL_REG_P(X) \
1303 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1305 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1307 #define REX_INT_REGNO_P(N) \
1308 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1309 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1311 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1312 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1313 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1314 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1316 #define X87_FLOAT_MODE_P(MODE) \
1317 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1319 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1320 #define SSE_REGNO_P(N) \
1321 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1322 || REX_SSE_REGNO_P (N))
1324 #define REX_SSE_REGNO_P(N) \
1325 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1327 #define SSE_REGNO(N) \
1328 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1330 #define SSE_FLOAT_MODE_P(MODE) \
1331 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1333 #define SSE_VEC_FLOAT_MODE_P(MODE) \
1334 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
1336 #define AVX_FLOAT_MODE_P(MODE) \
1337 (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode))
1339 #define AVX128_VEC_FLOAT_MODE_P(MODE) \
1340 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode))
1342 #define AVX256_VEC_FLOAT_MODE_P(MODE) \
1343 (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode))
1345 #define AVX_VEC_FLOAT_MODE_P(MODE) \
1346 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1347 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1349 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
1350 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1351 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1353 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1354 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1356 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1357 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1359 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1361 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1362 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1364 /* The class value for index registers, and the one for base regs. */
1366 #define INDEX_REG_CLASS INDEX_REGS
1367 #define BASE_REG_CLASS GENERAL_REGS
1369 /* Place additional restrictions on the register class to use when it
1370 is necessary to be able to hold a value of mode MODE in a reload
1371 register for which class CLASS would ordinarily be used. */
1373 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1374 ((MODE) == QImode && !TARGET_64BIT \
1375 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1376 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1379 /* If we are copying between general and FP registers, we need a memory
1380 location. The same is true for SSE and MMX registers. */
1381 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1382 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1384 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1385 There is no need to emit full 64 bit move on 64 bit targets
1386 for integral modes that can be moved using 32 bit move. */
1387 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1388 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1389 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1392 /* Return the maximum number of consecutive registers
1393 needed to represent mode MODE in a register of class CLASS. */
1394 /* On the 80386, this is the size of MODE in words,
1395 except in the FP regs, where a single reg is always enough. */
1396 #define CLASS_MAX_NREGS(CLASS, MODE) \
1397 (MAYBE_INTEGER_CLASS_P (CLASS) \
1398 ? ((MODE) == XFmode \
1399 ? (TARGET_64BIT ? 2 : 3) \
1400 : (MODE) == XCmode \
1401 ? (TARGET_64BIT ? 4 : 6) \
1402 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
1403 : (COMPLEX_MODE_P (MODE) ? 2 : 1))
1405 /* Return a class of registers that cannot change FROM mode to TO mode. */
1407 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1408 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1410 /* Stack layout; function entry, exit and calling. */
1412 /* Define this if pushing a word on the stack
1413 makes the stack pointer a smaller address. */
1414 #define STACK_GROWS_DOWNWARD
1416 /* Define this to nonzero if the nominal address of the stack frame
1417 is at the high-address end of the local variables;
1418 that is, each additional local variable allocated
1419 goes at a more negative offset in the frame. */
1420 #define FRAME_GROWS_DOWNWARD 1
1422 /* Offset within stack frame to start allocating local variables at.
1423 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1424 first local allocated. Otherwise, it is the offset to the BEGINNING
1425 of the first local allocated. */
1426 #define STARTING_FRAME_OFFSET 0
1428 /* If we generate an insn to push BYTES bytes, this says how many the stack
1429 pointer really advances by. On 386, we have pushw instruction that
1430 decrements by exactly 2 no matter what the position was, there is no pushb.
1432 But as CIE data alignment factor on this arch is -4 for 32bit targets
1433 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1434 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1436 #define PUSH_ROUNDING(BYTES) \
1437 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)
1439 /* If defined, the maximum amount of space required for outgoing arguments
1440 will be computed and placed into the variable `crtl->outgoing_args_size'.
1441 No space will be pushed onto the stack for each call; instead, the
1442 function prologue should increase the stack frame size by this amount.
1444 MS ABI seem to require 16 byte alignment everywhere except for function
1445 prologue and apilogue. This is not possible without
1446 ACCUMULATE_OUTGOING_ARGS. */
1448 #define ACCUMULATE_OUTGOING_ARGS \
1449 (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI)
1451 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1452 instructions to pass outgoing arguments. */
1454 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1456 /* We want the stack and args grow in opposite directions, even if
1458 #define PUSH_ARGS_REVERSED 1
1460 /* Offset of first parameter from the argument pointer register value. */
1461 #define FIRST_PARM_OFFSET(FNDECL) 0
1463 /* Define this macro if functions should assume that stack space has been
1464 allocated for arguments even when their values are passed in registers.
1466 The value of this macro is the size, in bytes, of the area reserved for
1467 arguments passed in registers for the function represented by FNDECL.
1469 This space can be allocated by the caller, or be a part of the
1470 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1472 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1474 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1475 (ix86_function_type_abi (FNTYPE) == MS_ABI)
1477 /* Define how to find the value returned by a library function
1478 assuming the value has mode MODE. */
1480 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1482 /* Define the size of the result block used for communication between
1483 untyped_call and untyped_return. The block contains a DImode value
1484 followed by the block used by fnsave and frstor. */
1486 #define APPLY_RESULT_SIZE (8+108)
1488 /* 1 if N is a possible register number for function argument passing. */
1489 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1491 /* Define a data type for recording info about an argument list
1492 during the scan of that argument list. This data type should
1493 hold all necessary information about the function itself
1494 and about the args processed so far, enough to enable macros
1495 such as FUNCTION_ARG to determine where the next arg should go. */
1497 typedef struct ix86_args {
1498 int words; /* # words passed so far */
1499 int nregs; /* # registers available for passing */
1500 int regno; /* next available register number */
1501 int fastcall; /* fastcall or thiscall calling convention
1503 int sse_words; /* # sse words passed so far */
1504 int sse_nregs; /* # sse registers available for passing */
1505 int warn_avx; /* True when we want to warn about AVX ABI. */
1506 int warn_sse; /* True when we want to warn about SSE ABI. */
1507 int warn_mmx; /* True when we want to warn about MMX ABI. */
1508 int sse_regno; /* next available sse register number */
1509 int mmx_words; /* # mmx words passed so far */
1510 int mmx_nregs; /* # mmx registers available for passing */
1511 int mmx_regno; /* next available mmx register number */
1512 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1513 int caller; /* true if it is caller. */
1514 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1515 SFmode/DFmode arguments should be passed
1516 in SSE registers. Otherwise 0. */
1517 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1518 MS_ABI for ms abi. */
1521 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1522 for a call to a function whose data type is FNTYPE.
1523 For a library call, FNTYPE is 0. */
1525 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1526 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1527 (N_NAMED_ARGS) != -1)
1529 /* Output assembler code to FILE to increment profiler label # LABELNO
1530 for profiling a function entry. */
1532 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1534 #define MCOUNT_NAME "_mcount"
1536 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1538 #define PROFILE_COUNT_REGISTER "edx"
1540 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1541 the stack pointer does not matter. The value is tested only in
1542 functions that have frame pointers.
1543 No definition is equivalent to always zero. */
1544 /* Note on the 386 it might be more efficient not to define this since
1545 we have to restore it ourselves from the frame pointer, in order to
1548 #define EXIT_IGNORE_STACK 1
1550 /* Output assembler code for a block containing the constant parts
1551 of a trampoline, leaving space for the variable parts. */
1553 /* On the 386, the trampoline contains two instructions:
1556 The trampoline is generated entirely at runtime. The operand of JMP
1557 is the address of FUNCTION relative to the instruction following the
1558 JMP (which is 5 bytes long). */
1560 /* Length in units of the trampoline for entering a nested function. */
1562 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1564 /* Definitions for register eliminations.
1566 This is an array of structures. Each structure initializes one pair
1567 of eliminable registers. The "from" register number is given first,
1568 followed by "to". Eliminations of the same "from" register are listed
1569 in order of preference.
1571 There are two registers that can always be eliminated on the i386.
1572 The frame pointer and the arg pointer can be replaced by either the
1573 hard frame pointer or to the stack pointer, depending upon the
1574 circumstances. The hard frame pointer is not used before reload and
1575 so it is not eligible for elimination. */
1577 #define ELIMINABLE_REGS \
1578 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1579 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1580 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1581 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1583 /* Define the offset between two registers, one to be eliminated, and the other
1584 its replacement, at the start of a routine. */
1586 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1587 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1589 /* Addressing modes, and classification of registers for them. */
1591 /* Macros to check register numbers against specific register classes. */
1593 /* These assume that REGNO is a hard or pseudo reg number.
1594 They give nonzero only if REGNO is a hard reg of the suitable class
1595 or a pseudo reg currently allocated to a suitable hard reg.
1596 Since they use reg_renumber, they are safe only once reg_renumber
1597 has been allocated, which happens in local-alloc.c. */
1599 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1600 ((REGNO) < STACK_POINTER_REGNUM \
1601 || REX_INT_REGNO_P (REGNO) \
1602 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1603 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1605 #define REGNO_OK_FOR_BASE_P(REGNO) \
1606 (GENERAL_REGNO_P (REGNO) \
1607 || (REGNO) == ARG_POINTER_REGNUM \
1608 || (REGNO) == FRAME_POINTER_REGNUM \
1609 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1611 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1612 and check its validity for a certain class.
1613 We have two alternate definitions for each of them.
1614 The usual definition accepts all pseudo regs; the other rejects
1615 them unless they have been allocated suitable hard regs.
1616 The symbol REG_OK_STRICT causes the latter definition to be used.
1618 Most source files want to accept pseudo regs in the hope that
1619 they will get allocated to the class that the insn wants them to be in.
1620 Source files for reload pass need to be strict.
1621 After reload, it makes no difference, since pseudo regs have
1622 been eliminated by then. */
1625 /* Non strict versions, pseudos are ok. */
1626 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1627 (REGNO (X) < STACK_POINTER_REGNUM \
1628 || REX_INT_REGNO_P (REGNO (X)) \
1629 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1631 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1632 (GENERAL_REGNO_P (REGNO (X)) \
1633 || REGNO (X) == ARG_POINTER_REGNUM \
1634 || REGNO (X) == FRAME_POINTER_REGNUM \
1635 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1637 /* Strict versions, hard registers only */
1638 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1639 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1641 #ifndef REG_OK_STRICT
1642 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1643 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1646 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1647 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1650 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1651 that is a valid memory address for an instruction.
1652 The MODE argument is the machine mode for the MEM expression
1653 that wants to use this address.
1655 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1656 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1658 See legitimize_pic_address in i386.c for details as to what
1659 constitutes a legitimate address when -fpic is used. */
1661 #define MAX_REGS_PER_ADDRESS 2
1663 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1665 /* Nonzero if the constant value X is a legitimate general operand.
1666 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1668 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1670 /* If defined, a C expression to determine the base term of address X.
1671 This macro is used in only one place: `find_base_term' in alias.c.
1673 It is always safe for this macro to not be defined. It exists so
1674 that alias analysis can understand machine-dependent addresses.
1676 The typical use of this macro is to handle addresses containing
1677 a label_ref or symbol_ref within an UNSPEC. */
1679 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1681 /* Nonzero if the constant value X is a legitimate general operand
1682 when generating PIC code. It is given that flag_pic is on and
1683 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1685 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1687 #define SYMBOLIC_CONST(X) \
1688 (GET_CODE (X) == SYMBOL_REF \
1689 || GET_CODE (X) == LABEL_REF \
1690 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1692 /* Max number of args passed in registers. If this is more than 3, we will
1693 have problems with ebx (register #4), since it is a caller save register and
1694 is also used as the pic register in ELF. So for now, don't allow more than
1695 3 registers to be passed in registers. */
1697 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1698 #define X86_64_REGPARM_MAX 6
1699 #define X86_64_MS_REGPARM_MAX 4
1701 #define X86_32_REGPARM_MAX 3
1703 #define REGPARM_MAX \
1705 ? (TARGET_64BIT_MS_ABI \
1706 ? X86_64_MS_REGPARM_MAX \
1707 : X86_64_REGPARM_MAX) \
1708 : X86_32_REGPARM_MAX)
1710 #define X86_64_SSE_REGPARM_MAX 8
1711 #define X86_64_MS_SSE_REGPARM_MAX 4
1713 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1715 #define SSE_REGPARM_MAX \
1717 ? (TARGET_64BIT_MS_ABI \
1718 ? X86_64_MS_SSE_REGPARM_MAX \
1719 : X86_64_SSE_REGPARM_MAX) \
1720 : X86_32_SSE_REGPARM_MAX)
1722 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1724 /* Specify the machine mode that this machine uses
1725 for the index in the tablejump instruction. */
1726 #define CASE_VECTOR_MODE \
1727 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1729 /* Define this as 1 if `char' should by default be signed; else as 0. */
1730 #define DEFAULT_SIGNED_CHAR 1
1732 /* Max number of bytes we can move from memory to memory
1733 in one reasonably fast instruction. */
1736 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1737 move efficiently, as opposed to MOVE_MAX which is the maximum
1738 number of bytes we can move with a single instruction. */
1739 #define MOVE_MAX_PIECES UNITS_PER_WORD
1741 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1742 move-instruction pairs, we will do a movmem or libcall instead.
1743 Increasing the value will always make code faster, but eventually
1744 incurs high cost in increased code size.
1746 If you don't define this, a reasonable default is used. */
1748 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1750 /* If a clear memory operation would take CLEAR_RATIO or more simple
1751 move-instruction sequences, we will do a clrmem or libcall instead. */
1753 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1755 /* Define if shifts truncate the shift count which implies one can
1756 omit a sign-extension or zero-extension of a shift count.
1758 On i386, shifts do truncate the count. But bit test instructions
1759 take the modulo of the bit offset operand. */
1761 /* #define SHIFT_COUNT_TRUNCATED */
1763 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1764 is done just by pretending it is already truncated. */
1765 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1767 /* A macro to update M and UNSIGNEDP when an object whose type is
1768 TYPE and which has the specified mode and signedness is to be
1769 stored in a register. This macro is only called when TYPE is a
1772 On i386 it is sometimes useful to promote HImode and QImode
1773 quantities to SImode. The choice depends on target type. */
1775 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1777 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1778 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1782 /* Specify the machine mode that pointers have.
1783 After generation of rtl, the compiler makes no further distinction
1784 between pointers and any other objects of this machine mode. */
1785 #define Pmode (TARGET_64BIT ? DImode : SImode)
1787 /* A function address in a call instruction
1788 is a byte address (for indexing purposes)
1789 so give the MEM rtx a byte's mode. */
1790 #define FUNCTION_MODE QImode
1793 /* A C expression for the cost of a branch instruction. A value of 1
1794 is the default; other values are interpreted relative to that. */
1796 #define BRANCH_COST(speed_p, predictable_p) \
1797 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1799 /* Define this macro as a C expression which is nonzero if accessing
1800 less than a word of memory (i.e. a `char' or a `short') is no
1801 faster than accessing a word of memory, i.e., if such access
1802 require more than one instruction or if there is no difference in
1803 cost between byte and (aligned) word loads.
1805 When this macro is not defined, the compiler will access a field by
1806 finding the smallest containing object; when it is defined, a
1807 fullword load will be used if alignment permits. Unless bytes
1808 accesses are faster than word accesses, using word accesses is
1809 preferable since it may eliminate subsequent memory access if
1810 subsequent accesses occur to other fields in the same word of the
1811 structure, but to different bytes. */
1813 #define SLOW_BYTE_ACCESS 0
1815 /* Nonzero if access to memory by shorts is slow and undesirable. */
1816 #define SLOW_SHORT_ACCESS 0
1818 /* Define this macro to be the value 1 if unaligned accesses have a
1819 cost many times greater than aligned accesses, for example if they
1820 are emulated in a trap handler.
1822 When this macro is nonzero, the compiler will act as if
1823 `STRICT_ALIGNMENT' were nonzero when generating code for block
1824 moves. This can cause significantly more instructions to be
1825 produced. Therefore, do not set this macro nonzero if unaligned
1826 accesses only add a cycle or two to the time for a memory access.
1828 If the value of this macro is always zero, it need not be defined. */
1830 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1832 /* Define this macro if it is as good or better to call a constant
1833 function address than to call an address kept in a register.
1835 Desirable on the 386 because a CALL with a constant address is
1836 faster than one with a register address. */
1838 #define NO_FUNCTION_CSE
1840 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1841 return the mode to be used for the comparison.
1843 For floating-point equality comparisons, CCFPEQmode should be used.
1844 VOIDmode should be used in all other cases.
1846 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1847 possible, to allow for more combinations. */
1849 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1851 /* Return nonzero if MODE implies a floating point inequality can be
1854 #define REVERSIBLE_CC_MODE(MODE) 1
1856 /* A C expression whose value is reversed condition code of the CODE for
1857 comparison done in CC_MODE mode. */
1858 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1861 /* Control the assembler format that we output, to the extent
1862 this does not vary between assemblers. */
1864 /* How to refer to registers in assembler output.
1865 This sequence is indexed by compiler's hard-register-number (see above). */
1867 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1868 For non floating point regs, the following are the HImode names.
1870 For float regs, the stack top is sometimes referred to as "%st(0)"
1871 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
1874 #define HI_REGISTER_NAMES \
1875 {"ax","dx","cx","bx","si","di","bp","sp", \
1876 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1877 "argp", "flags", "fpsr", "fpcr", "frame", \
1878 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1879 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1880 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1881 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1883 #define REGISTER_NAMES HI_REGISTER_NAMES
1885 /* Table of additional register names to use in user input. */
1887 #define ADDITIONAL_REGISTER_NAMES \
1888 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1889 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1890 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1891 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1892 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1893 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1895 /* Note we are omitting these since currently I don't know how
1896 to get gcc to use these, since they want the same but different
1897 number as al, and ax.
1900 #define QI_REGISTER_NAMES \
1901 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1903 /* These parallel the array above, and can be used to access bits 8:15
1904 of regs 0 through 3. */
1906 #define QI_HIGH_REGISTER_NAMES \
1907 {"ah", "dh", "ch", "bh", }
1909 /* How to renumber registers for dbx and gdb. */
1911 #define DBX_REGISTER_NUMBER(N) \
1912 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1914 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1915 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1916 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1918 /* Before the prologue, RA is at 0(%esp). */
1919 #define INCOMING_RETURN_ADDR_RTX \
1920 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1922 /* After the prologue, RA is at -4(AP) in the current frame. */
1923 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1925 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1926 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1928 /* PC is dbx register 8; let's use that column for RA. */
1929 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1931 /* Before the prologue, the top of the frame is at 4(%esp). */
1932 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1934 /* Describe how we implement __builtin_eh_return. */
1935 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
1936 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
1939 /* Select a format to encode pointers in exception handling data. CODE
1940 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1941 true if the symbol may be affected by dynamic relocations.
1943 ??? All x86 object file formats are capable of representing this.
1944 After all, the relocation needed is the same as for the call insn.
1945 Whether or not a particular assembler allows us to enter such, I
1946 guess we'll have to see. */
1947 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1948 asm_preferred_eh_data_format ((CODE), (GLOBAL))
1950 /* This is how to output an insn to push a register on the stack.
1951 It need not be very fast code. */
1953 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1956 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
1957 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1959 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
1962 /* This is how to output an insn to pop a register from the stack.
1963 It need not be very fast code. */
1965 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
1968 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
1969 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1971 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
1974 /* This is how to output an element of a case-vector that is absolute. */
1976 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1977 ix86_output_addr_vec_elt ((FILE), (VALUE))
1979 /* This is how to output an element of a case-vector that is relative. */
1981 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1982 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
1984 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
1986 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
1988 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
1989 (PTR) += TARGET_AVX ? 1 : 2; \
1992 /* A C statement or statements which output an assembler instruction
1993 opcode to the stdio stream STREAM. The macro-operand PTR is a
1994 variable of type `char *' which points to the opcode name in
1995 its "internal" form--the form that is written in the machine
1998 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1999 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2001 /* A C statement to output to the stdio stream FILE an assembler
2002 command to pad the location counter to a multiple of 1<<LOG
2003 bytes if it is within MAX_SKIP bytes. */
2005 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2006 #undef ASM_OUTPUT_MAX_SKIP_PAD
2007 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2010 if ((MAX_SKIP) == 0) \
2011 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2013 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2017 /* Write the extra assembler code needed to declare a function
2020 #undef ASM_OUTPUT_FUNCTION_LABEL
2021 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2022 ix86_asm_output_function_label (FILE, NAME, DECL)
2024 /* Under some conditions we need jump tables in the text section,
2025 because the assembler cannot handle label differences between
2026 sections. This is the case for x86_64 on Mach-O for example. */
2028 #define JUMP_TABLES_IN_TEXT_SECTION \
2029 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2030 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2032 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2033 and switch back. For x86 we do this only to save a few bytes that
2034 would otherwise be unused in the text section. */
2035 #define CRT_MKSTR2(VAL) #VAL
2036 #define CRT_MKSTR(x) CRT_MKSTR2(x)
2038 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2039 asm (SECTION_OP "\n\t" \
2040 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2041 TEXT_SECTION_ASM_OP);
2043 /* Which processor to tune code generation for. */
2047 PROCESSOR_I386 = 0, /* 80386 */
2048 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2050 PROCESSOR_PENTIUMPRO,
2059 PROCESSOR_COREI7_32,
2060 PROCESSOR_COREI7_64,
2061 PROCESSOR_GENERIC32,
2062 PROCESSOR_GENERIC64,
2070 extern enum processor_type ix86_tune;
2071 extern enum processor_type ix86_arch;
2079 extern enum fpmath_unit ix86_fpmath;
2088 extern enum tls_dialect ix86_tls_dialect;
2091 CM_32, /* The traditional 32-bit ABI. */
2092 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2093 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2094 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2095 CM_LARGE, /* No assumptions. */
2096 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2097 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2098 CM_LARGE_PIC /* No assumptions. */
2101 extern enum cmodel ix86_cmodel;
2103 /* Size of the RED_ZONE area. */
2104 #define RED_ZONE_SIZE 128
2105 /* Reserved area of the red zone for temporaries. */
2106 #define RED_ZONE_RESERVE 8
2113 extern enum asm_dialect ix86_asm_dialect;
2114 extern unsigned int ix86_preferred_stack_boundary;
2115 extern unsigned int ix86_incoming_stack_boundary;
2116 extern int ix86_branch_cost, ix86_section_threshold;
2118 /* Smallest class containing REGNO. */
2119 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2121 enum ix86_fpcmp_strategy {
2127 /* To properly truncate FP values into integers, we need to set i387 control
2128 word. We can't emit proper mode switching code before reload, as spills
2129 generated by reload may truncate values incorrectly, but we still can avoid
2130 redundant computation of new control word by the mode switching pass.
2131 The fldcw instructions are still emitted redundantly, but this is probably
2132 not going to be noticeable problem, as most CPUs do have fast path for
2135 The machinery is to emit simple truncation instructions and split them
2136 before reload to instructions having USEs of two memory locations that
2137 are filled by this code to old and new control word.
2139 Post-reload pass may be later used to eliminate the redundant fildcw if
2151 enum ix86_stack_slot
2160 MAX_386_STACK_LOCALS
2163 /* Define this macro if the port needs extra instructions inserted
2164 for mode switching in an optimizing compilation. */
2166 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2167 ix86_optimize_mode_switching[(ENTITY)]
2169 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2170 initializer for an array of integers. Each initializer element N
2171 refers to an entity that needs mode switching, and specifies the
2172 number of different modes that might need to be set for this
2173 entity. The position of the initializer in the initializer -
2174 starting counting at zero - determines the integer that is used to
2175 refer to the mode-switched entity in question. */
2177 #define NUM_MODES_FOR_MODE_SWITCHING \
2178 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2180 /* ENTITY is an integer specifying a mode-switched entity. If
2181 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2182 return an integer value not larger than the corresponding element
2183 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2184 must be switched into prior to the execution of INSN. */
2186 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2188 /* This macro specifies the order in which modes for ENTITY are
2189 processed. 0 is the highest priority. */
2191 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2193 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2194 is the set of hard registers live at the point where the insn(s)
2195 are to be inserted. */
2197 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2198 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2199 ? emit_i387_cw_initialization (MODE), 0 \
2203 /* Avoid renaming of stack registers, as doing so in combination with
2204 scheduling just increases amount of live registers at time and in
2205 the turn amount of fxch instructions needed.
2207 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2209 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2210 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2213 #define FASTCALL_PREFIX '@'
2215 /* Machine specific frame tracking during prologue/epilogue generation. */
2217 #ifndef USED_FOR_TARGET
2218 struct GTY(()) machine_frame_state
2220 /* This pair tracks the currently active CFA as reg+offset. When reg
2221 is drap_reg, we don't bother trying to record here the real CFA when
2222 it might really be a DW_CFA_def_cfa_expression. */
2224 HOST_WIDE_INT cfa_offset;
2226 /* The current offset (canonically from the CFA) of ESP and EBP.
2227 When stack frame re-alignment is active, these may not be relative
2228 to the CFA. However, in all cases they are relative to the offsets
2229 of the saved registers stored in ix86_frame. */
2230 HOST_WIDE_INT sp_offset;
2231 HOST_WIDE_INT fp_offset;
2233 /* The size of the red-zone that may be assumed for the purposes of
2234 eliding register restore notes in the epilogue. This may be zero
2235 if no red-zone is in effect, or may be reduced from the real
2236 red-zone value by a maximum runtime stack re-alignment value. */
2237 int red_zone_offset;
2239 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2240 value within the frame. If false then the offset above should be
2241 ignored. Note that DRAP, if valid, *always* points to the CFA and
2242 thus has an offset of zero. */
2243 BOOL_BITFIELD sp_valid : 1;
2244 BOOL_BITFIELD fp_valid : 1;
2245 BOOL_BITFIELD drap_valid : 1;
2247 /* Indicate whether the local stack frame has been re-aligned. When
2248 set, the SP/FP offsets above are relative to the aligned frame
2250 BOOL_BITFIELD realigned : 1;
2253 /* Private to winnt.c. */
2254 struct seh_frame_state;
2256 struct GTY(()) machine_function {
2257 struct stack_local_entry *stack_locals;
2258 const char *some_ld_name;
2259 int varargs_gpr_size;
2260 int varargs_fpr_size;
2261 int optimize_mode_switching[MAX_386_ENTITIES];
2263 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
2264 has been computed for. */
2265 int use_fast_prologue_epilogue_nregs;
2267 /* For -fsplit-stack support: A stack local which holds a pointer to
2268 the stack arguments for a function with a variable number of
2269 arguments. This is set at the start of the function and is used
2270 to initialize the overflow_arg_area field of the va_list
2272 rtx split_stack_varargs_pointer;
2274 /* This value is used for amd64 targets and specifies the current abi
2275 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2276 ENUM_BITFIELD(calling_abi) call_abi : 8;
2278 /* Nonzero if the function accesses a previous frame. */
2279 BOOL_BITFIELD accesses_prev_frame : 1;
2281 /* Nonzero if the function requires a CLD in the prologue. */
2282 BOOL_BITFIELD needs_cld : 1;
2284 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2285 expander to determine the style used. */
2286 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2288 /* If true, the current function needs the default PIC register, not
2289 an alternate register (on x86) and must not use the red zone (on
2290 x86_64), even if it's a leaf function. We don't want the
2291 function to be regarded as non-leaf because TLS calls need not
2292 affect register allocation. This flag is set when a TLS call
2293 instruction is expanded within a function, and never reset, even
2294 if all such instructions are optimized away. Use the
2295 ix86_current_function_calls_tls_descriptor macro for a better
2297 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2299 /* If true, the current function has a STATIC_CHAIN is placed on the
2300 stack below the return address. */
2301 BOOL_BITFIELD static_chain_on_stack : 1;
2303 /* Nonzero if caller passes 256bit AVX modes. */
2304 BOOL_BITFIELD caller_pass_avx256_p : 1;
2306 /* Nonzero if caller returns 256bit AVX modes. */
2307 BOOL_BITFIELD caller_return_avx256_p : 1;
2309 /* Nonzero if the current callee passes 256bit AVX modes. */
2310 BOOL_BITFIELD callee_pass_avx256_p : 1;
2312 /* Nonzero if the current callee returns 256bit AVX modes. */
2313 BOOL_BITFIELD callee_return_avx256_p : 1;
2315 /* Nonzero if rescan vzerouppers in the current function is needed. */
2316 BOOL_BITFIELD rescan_vzeroupper_p : 1;
2318 /* During prologue/epilogue generation, the current frame state.
2319 Otherwise, the frame state at the end of the prologue. */
2320 struct machine_frame_state fs;
2322 /* During SEH output, this is non-null. */
2323 struct seh_frame_state * GTY((skip(""))) seh;
2327 #define ix86_stack_locals (cfun->machine->stack_locals)
2328 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2329 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2330 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2331 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2332 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2333 (cfun->machine->tls_descriptor_call_expanded_p)
2334 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2335 calls are optimized away, we try to detect cases in which it was
2336 optimized away. Since such instructions (use (reg REG_SP)), we can
2337 verify whether there's any such instruction live by testing that
2339 #define ix86_current_function_calls_tls_descriptor \
2340 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2341 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2343 /* Control behavior of x86_file_start. */
2344 #define X86_FILE_START_VERSION_DIRECTIVE false
2345 #define X86_FILE_START_FLTUSED false
2347 /* Flag to mark data that is in the large address area. */
2348 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2349 #define SYMBOL_REF_FAR_ADDR_P(X) \
2350 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2352 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2353 have defined always, to avoid ifdefing. */
2354 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2355 #define SYMBOL_REF_DLLIMPORT_P(X) \
2356 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2358 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2359 #define SYMBOL_REF_DLLEXPORT_P(X) \
2360 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2362 extern void debug_ready_dispatch (void);
2363 extern void debug_dispatch_window (int);
2365 /* The value at zero is only defined for the BMI instructions
2366 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2367 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2368 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
2369 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2370 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)