1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 Under Section 7 of GPL version 3, you are granted additional
19 permissions described in the GCC Runtime Library Exception, version
20 3.1, as published by the Free Software Foundation.
22 You should have received a copy of the GNU General Public License and
23 a copy of the GCC Runtime Library Exception along with this program;
24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
25 <http://www.gnu.org/licenses/>. */
27 /* The purpose of this file is to define the characteristics of the i386,
28 independent of assembler syntax or operating system.
30 Three other files build on this one to describe a specific assembler syntax:
31 bsd386.h, att386.h, and sun386.h.
33 The actual tm.h file for a particular system should include
34 this file, and then the file for the appropriate assembler syntax.
36 Many macros that specify assembler syntax are omitted entirely from
37 this file because they really belong in the files for particular
38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
40 that start with ASM_ or end in ASM_OP. */
42 /* Redefines for option macros. */
44 #define TARGET_64BIT OPTION_ISA_64BIT
45 #define TARGET_MMX OPTION_ISA_MMX
46 #define TARGET_3DNOW OPTION_ISA_3DNOW
47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
48 #define TARGET_SSE OPTION_ISA_SSE
49 #define TARGET_SSE2 OPTION_ISA_SSE2
50 #define TARGET_SSE3 OPTION_ISA_SSE3
51 #define TARGET_SSSE3 OPTION_ISA_SSSE3
52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
54 #define TARGET_AVX OPTION_ISA_AVX
55 #define TARGET_FMA OPTION_ISA_FMA
56 #define TARGET_SSE4A OPTION_ISA_SSE4A
57 #define TARGET_FMA4 OPTION_ISA_FMA4
58 #define TARGET_XOP OPTION_ISA_XOP
59 #define TARGET_LWP OPTION_ISA_LWP
60 #define TARGET_ROUND OPTION_ISA_ROUND
61 #define TARGET_ABM OPTION_ISA_ABM
62 #define TARGET_BMI OPTION_ISA_BMI
63 #define TARGET_TBM OPTION_ISA_TBM
64 #define TARGET_POPCNT OPTION_ISA_POPCNT
65 #define TARGET_SAHF OPTION_ISA_SAHF
66 #define TARGET_MOVBE OPTION_ISA_MOVBE
67 #define TARGET_CRC32 OPTION_ISA_CRC32
68 #define TARGET_AES OPTION_ISA_AES
69 #define TARGET_PCLMUL OPTION_ISA_PCLMUL
70 #define TARGET_CMPXCHG16B OPTION_ISA_CX16
71 #define TARGET_FSGSBASE OPTION_ISA_FSGSBASE
72 #define TARGET_RDRND OPTION_ISA_RDRND
73 #define TARGET_F16C OPTION_ISA_F16C
76 /* SSE4.1 defines round instructions */
77 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
78 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
80 #include "config/vxworks-dummy.h"
82 /* Algorithm to expand string function with. */
95 #define MAX_STRINGOP_ALGS 4
97 /* Specify what algorithm to use for stringops on known size.
98 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
99 known at compile time or estimated via feedback, the SIZE array
100 is walked in order until MAX is greater then the estimate (or -1
101 means infinity). Corresponding ALG is used then.
102 For example initializer:
103 {{256, loop}, {-1, rep_prefix_4_byte}}
104 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
105 be used otherwise. */
108 const enum stringop_alg unknown_size;
109 const struct stringop_strategy {
111 const enum stringop_alg alg;
112 } size [MAX_STRINGOP_ALGS];
115 /* Define the specific costs for a given cpu */
117 struct processor_costs {
118 const int add; /* cost of an add instruction */
119 const int lea; /* cost of a lea instruction */
120 const int shift_var; /* variable shift costs */
121 const int shift_const; /* constant shift costs */
122 const int mult_init[5]; /* cost of starting a multiply
123 in QImode, HImode, SImode, DImode, TImode*/
124 const int mult_bit; /* cost of multiply per each bit set */
125 const int divide[5]; /* cost of a divide/mod
126 in QImode, HImode, SImode, DImode, TImode*/
127 int movsx; /* The cost of movsx operation. */
128 int movzx; /* The cost of movzx operation. */
129 const int large_insn; /* insns larger than this cost more */
130 const int move_ratio; /* The threshold of number of scalar
131 memory-to-memory move insns. */
132 const int movzbl_load; /* cost of loading using movzbl */
133 const int int_load[3]; /* cost of loading integer registers
134 in QImode, HImode and SImode relative
135 to reg-reg move (2). */
136 const int int_store[3]; /* cost of storing integer register
137 in QImode, HImode and SImode */
138 const int fp_move; /* cost of reg,reg fld/fst */
139 const int fp_load[3]; /* cost of loading FP register
140 in SFmode, DFmode and XFmode */
141 const int fp_store[3]; /* cost of storing FP register
142 in SFmode, DFmode and XFmode */
143 const int mmx_move; /* cost of moving MMX register. */
144 const int mmx_load[2]; /* cost of loading MMX register
145 in SImode and DImode */
146 const int mmx_store[2]; /* cost of storing MMX register
147 in SImode and DImode */
148 const int sse_move; /* cost of moving SSE register. */
149 const int sse_load[3]; /* cost of loading SSE register
150 in SImode, DImode and TImode*/
151 const int sse_store[3]; /* cost of storing SSE register
152 in SImode, DImode and TImode*/
153 const int mmxsse_to_integer; /* cost of moving mmxsse register to
154 integer and vice versa. */
155 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
156 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
157 const int prefetch_block; /* bytes moved to cache for prefetch. */
158 const int simultaneous_prefetches; /* number of parallel prefetch
160 const int branch_cost; /* Default value for BRANCH_COST. */
161 const int fadd; /* cost of FADD and FSUB instructions. */
162 const int fmul; /* cost of FMUL instruction. */
163 const int fdiv; /* cost of FDIV instruction. */
164 const int fabs; /* cost of FABS instruction. */
165 const int fchs; /* cost of FCHS instruction. */
166 const int fsqrt; /* cost of FSQRT instruction. */
167 /* Specify what algorithm
168 to use for stringops on unknown size. */
169 struct stringop_algs memcpy[2], memset[2];
170 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
172 const int scalar_load_cost; /* Cost of scalar load. */
173 const int scalar_store_cost; /* Cost of scalar store. */
174 const int vec_stmt_cost; /* Cost of any vector operation, excluding
175 load, store, vector-to-scalar and
176 scalar-to-vector operation. */
177 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
178 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
179 const int vec_align_load_cost; /* Cost of aligned vector load. */
180 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
181 const int vec_store_cost; /* Cost of vector store. */
182 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
184 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
185 vectorizer cost model. */
188 extern const struct processor_costs *ix86_cost;
189 extern const struct processor_costs ix86_size_cost;
191 #define ix86_cur_cost() \
192 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
194 /* Macros used in the machine description to test the flags. */
196 /* configure can arrange to make this 2, to force a 486. */
198 #ifndef TARGET_CPU_DEFAULT
199 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
202 #ifndef TARGET_FPMATH_DEFAULT
203 #define TARGET_FPMATH_DEFAULT \
204 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
207 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
209 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
210 compile-time constant. */
214 #define TARGET_64BIT 1
216 #define TARGET_64BIT 0
219 #ifndef TARGET_BI_ARCH
221 #if TARGET_64BIT_DEFAULT
222 #define TARGET_64BIT 1
224 #define TARGET_64BIT 0
229 #define HAS_LONG_COND_BRANCH 1
230 #define HAS_LONG_UNCOND_BRANCH 1
232 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
233 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
234 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
235 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
236 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
237 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
238 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
239 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
240 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
241 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
242 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
243 #define TARGET_CORE2_32 (ix86_tune == PROCESSOR_CORE2_32)
244 #define TARGET_CORE2_64 (ix86_tune == PROCESSOR_CORE2_64)
245 #define TARGET_CORE2 (TARGET_CORE2_32 || TARGET_CORE2_64)
246 #define TARGET_COREI7_32 (ix86_tune == PROCESSOR_COREI7_32)
247 #define TARGET_COREI7_64 (ix86_tune == PROCESSOR_COREI7_64)
248 #define TARGET_COREI7 (TARGET_COREI7_32 || TARGET_COREI7_64)
249 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
250 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
251 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
252 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
253 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
254 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
255 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
257 /* Feature tests against the various tunings. */
258 enum ix86_tune_indices {
260 X86_TUNE_PUSH_MEMORY,
261 X86_TUNE_ZERO_EXTEND_WITH_AND,
262 X86_TUNE_UNROLL_STRLEN,
263 X86_TUNE_DEEP_BRANCH_PREDICTION,
264 X86_TUNE_BRANCH_PREDICTION_HINTS,
265 X86_TUNE_DOUBLE_WITH_ADD,
268 X86_TUNE_PARTIAL_REG_STALL,
269 X86_TUNE_PARTIAL_FLAG_REG_STALL,
270 X86_TUNE_USE_HIMODE_FIOP,
271 X86_TUNE_USE_SIMODE_FIOP,
275 X86_TUNE_SPLIT_LONG_MOVES,
276 X86_TUNE_READ_MODIFY_WRITE,
277 X86_TUNE_READ_MODIFY,
278 X86_TUNE_PROMOTE_QIMODE,
279 X86_TUNE_FAST_PREFIX,
280 X86_TUNE_SINGLE_STRINGOP,
281 X86_TUNE_QIMODE_MATH,
282 X86_TUNE_HIMODE_MATH,
283 X86_TUNE_PROMOTE_QI_REGS,
284 X86_TUNE_PROMOTE_HI_REGS,
287 X86_TUNE_SINGLE_PUSH,
288 X86_TUNE_DOUBLE_PUSH,
289 X86_TUNE_INTEGER_DFMODE_MOVES,
290 X86_TUNE_PARTIAL_REG_DEPENDENCY,
291 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
292 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL,
293 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL,
294 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL,
295 X86_TUNE_SSE_SPLIT_REGS,
296 X86_TUNE_SSE_TYPELESS_STORES,
297 X86_TUNE_SSE_LOAD0_BY_PXOR,
298 X86_TUNE_MEMORY_MISMATCH_STALL,
299 X86_TUNE_PROLOGUE_USING_MOVE,
300 X86_TUNE_EPILOGUE_USING_MOVE,
303 X86_TUNE_INTER_UNIT_MOVES,
304 X86_TUNE_INTER_UNIT_CONVERSIONS,
305 X86_TUNE_FOUR_JUMP_LIMIT,
309 X86_TUNE_PAD_RETURNS,
310 X86_TUNE_PAD_SHORT_FUNCTION,
311 X86_TUNE_EXT_80387_CONSTANTS,
312 X86_TUNE_SHORTEN_X87_SSE,
313 X86_TUNE_AVOID_VECTOR_DECODE,
314 X86_TUNE_PROMOTE_HIMODE_IMUL,
315 X86_TUNE_SLOW_IMUL_IMM32_MEM,
316 X86_TUNE_SLOW_IMUL_IMM8,
317 X86_TUNE_MOVE_M1_VIA_OR,
318 X86_TUNE_NOT_UNPAIRABLE,
319 X86_TUNE_NOT_VECTORMODE,
320 X86_TUNE_USE_VECTOR_FP_CONVERTS,
321 X86_TUNE_USE_VECTOR_CONVERTS,
322 X86_TUNE_FUSE_CMP_AND_BRANCH,
324 X86_TUNE_VECTORIZE_DOUBLE,
329 extern unsigned char ix86_tune_features[X86_TUNE_LAST];
331 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
332 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
333 #define TARGET_ZERO_EXTEND_WITH_AND \
334 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
335 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
336 #define TARGET_DEEP_BRANCH_PREDICTION \
337 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
338 #define TARGET_BRANCH_PREDICTION_HINTS \
339 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
340 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
341 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
342 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
343 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
344 #define TARGET_PARTIAL_FLAG_REG_STALL \
345 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
346 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
347 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
348 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
349 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
350 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
351 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
352 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
353 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
354 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
355 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
356 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
357 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
358 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
359 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
360 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
361 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
362 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
363 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
364 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
365 #define TARGET_INTEGER_DFMODE_MOVES \
366 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
367 #define TARGET_PARTIAL_REG_DEPENDENCY \
368 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
369 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
370 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
371 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
372 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
373 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
374 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
375 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
376 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
377 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
378 #define TARGET_SSE_TYPELESS_STORES \
379 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
380 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
381 #define TARGET_MEMORY_MISMATCH_STALL \
382 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
383 #define TARGET_PROLOGUE_USING_MOVE \
384 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
385 #define TARGET_EPILOGUE_USING_MOVE \
386 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
387 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
388 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
389 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
390 #define TARGET_INTER_UNIT_CONVERSIONS\
391 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
392 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
393 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
394 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
395 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
396 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
397 #define TARGET_PAD_SHORT_FUNCTION \
398 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
399 #define TARGET_EXT_80387_CONSTANTS \
400 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
401 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
402 #define TARGET_AVOID_VECTOR_DECODE \
403 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
404 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
405 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
406 #define TARGET_SLOW_IMUL_IMM32_MEM \
407 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
408 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
409 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
410 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
411 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
412 #define TARGET_USE_VECTOR_FP_CONVERTS \
413 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
414 #define TARGET_USE_VECTOR_CONVERTS \
415 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
416 #define TARGET_FUSE_CMP_AND_BRANCH \
417 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
418 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
419 #define TARGET_VECTORIZE_DOUBLE \
420 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
422 /* Feature tests against the various architecture variations. */
423 enum ix86_arch_indices {
424 X86_ARCH_CMOVE, /* || TARGET_SSE */
433 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
435 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
436 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
437 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
438 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
439 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
441 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
443 extern int x86_prefetch_sse;
445 #define TARGET_PREFETCH_SSE x86_prefetch_sse
447 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
449 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
450 #define TARGET_MIX_SSE_I387 \
451 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
453 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
454 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
455 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
456 #define TARGET_SUN_TLS 0
458 #ifndef TARGET_64BIT_DEFAULT
459 #define TARGET_64BIT_DEFAULT 0
461 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
462 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
465 /* Fence to use after loop using storent. */
467 extern tree x86_mfence;
468 #define FENCE_FOLLOWING_MOVNT x86_mfence
470 /* Once GDB has been enhanced to deal with functions without frame
471 pointers, we can change this to allow for elimination of
472 the frame pointer in leaf functions. */
473 #define TARGET_DEFAULT 0
475 /* Extra bits to force. */
476 #define TARGET_SUBTARGET_DEFAULT 0
477 #define TARGET_SUBTARGET_ISA_DEFAULT 0
479 /* Extra bits to force on w/ 32-bit mode. */
480 #define TARGET_SUBTARGET32_DEFAULT 0
481 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
483 /* Extra bits to force on w/ 64-bit mode. */
484 #define TARGET_SUBTARGET64_DEFAULT 0
485 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
487 /* Replace MACH-O, ifdefs by in-line tests, where possible.
488 (a) Macros defined in config/i386/darwin.h */
489 #define TARGET_MACHO 0
490 #define TARGET_MACHO_BRANCH_ISLANDS 0
491 #define MACHOPIC_ATT_STUB 0
492 /* (b) Macros defined in config/darwin.h */
493 #define MACHO_DYNAMIC_NO_PIC_P 0
494 #define MACHOPIC_INDIRECT 0
495 #define MACHOPIC_PURE 0
497 /* For the Windows 64-bit ABI. */
498 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
500 /* For the Windows 32-bit ABI. */
501 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
503 /* This is re-defined by cygming.h. */
506 /* Available call abi. */
513 /* The abi used by target. */
514 extern enum calling_abi ix86_abi;
516 /* The default abi used by target. */
517 #define DEFAULT_ABI SYSV_ABI
519 /* Subtargets may reset this to 1 in order to enable 96-bit long double
520 with the rounding mode forced to 53 bits. */
521 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
523 /* -march=native handling only makes sense with compiler running on
524 an x86 or x86_64 chip. If changing this condition, also change
525 the condition in driver-i386.c. */
526 #if defined(__i386__) || defined(__x86_64__)
527 /* In driver-i386.c. */
528 extern const char *host_detect_local_cpu (int argc, const char **argv);
529 #define EXTRA_SPEC_FUNCTIONS \
530 { "local_cpu_detect", host_detect_local_cpu },
531 #define HAVE_LOCAL_CPU_DETECT
534 #if TARGET_64BIT_DEFAULT
535 #define OPT_ARCH64 "!m32"
536 #define OPT_ARCH32 "m32"
538 #define OPT_ARCH64 "m64"
539 #define OPT_ARCH32 "!m64"
542 /* Support for configure-time defaults of some command line options.
543 The order here is important so that -march doesn't squash the
544 tune or cpu values. */
545 #define OPTION_DEFAULT_SPECS \
546 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
547 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
548 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
549 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
550 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
551 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
552 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
553 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
554 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
556 /* Specs for the compiler proper */
559 #define CC1_CPU_SPEC_1 ""
561 #ifndef HAVE_LOCAL_CPU_DETECT
562 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
564 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
565 "%{march=native:%>march=native %:local_cpu_detect(arch) \
566 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
567 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
571 /* Target CPU builtins. */
572 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
574 /* Target Pragmas. */
575 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
577 enum target_cpu_default
579 TARGET_CPU_DEFAULT_generic = 0,
581 TARGET_CPU_DEFAULT_i386,
582 TARGET_CPU_DEFAULT_i486,
583 TARGET_CPU_DEFAULT_pentium,
584 TARGET_CPU_DEFAULT_pentium_mmx,
585 TARGET_CPU_DEFAULT_pentiumpro,
586 TARGET_CPU_DEFAULT_pentium2,
587 TARGET_CPU_DEFAULT_pentium3,
588 TARGET_CPU_DEFAULT_pentium4,
589 TARGET_CPU_DEFAULT_pentium_m,
590 TARGET_CPU_DEFAULT_prescott,
591 TARGET_CPU_DEFAULT_nocona,
592 TARGET_CPU_DEFAULT_core2,
593 TARGET_CPU_DEFAULT_corei7,
594 TARGET_CPU_DEFAULT_atom,
596 TARGET_CPU_DEFAULT_geode,
597 TARGET_CPU_DEFAULT_k6,
598 TARGET_CPU_DEFAULT_k6_2,
599 TARGET_CPU_DEFAULT_k6_3,
600 TARGET_CPU_DEFAULT_athlon,
601 TARGET_CPU_DEFAULT_athlon_sse,
602 TARGET_CPU_DEFAULT_k8,
603 TARGET_CPU_DEFAULT_amdfam10,
604 TARGET_CPU_DEFAULT_bdver1,
605 TARGET_CPU_DEFAULT_btver1,
607 TARGET_CPU_DEFAULT_max
611 #define CC1_SPEC "%(cc1_cpu) "
614 /* This macro defines names of additional specifications to put in the
615 specs that can be used in various specifications like CC1_SPEC. Its
616 definition is an initializer with a subgrouping for each command option.
618 Each subgrouping contains a string constant, that defines the
619 specification name, and a string constant that used by the GCC driver
622 Do not define this macro if it does not need to do anything. */
624 #ifndef SUBTARGET_EXTRA_SPECS
625 #define SUBTARGET_EXTRA_SPECS
628 #define EXTRA_SPECS \
629 { "cc1_cpu", CC1_CPU_SPEC }, \
630 SUBTARGET_EXTRA_SPECS
633 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
634 FPU, assume that the fpcw is set to extended precision; when using
635 only SSE, rounding is correct; when using both SSE and the FPU,
636 the rounding precision is indeterminate, since either may be chosen
637 apparently at random. */
638 #define TARGET_FLT_EVAL_METHOD \
639 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
641 /* Whether to allow x87 floating-point arithmetic on MODE (one of
642 SFmode, DFmode and XFmode) in the current excess precision
644 #define X87_ENABLE_ARITH(MODE) \
645 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
647 /* Likewise, whether to allow direct conversions from integer mode
648 IMODE (HImode, SImode or DImode) to MODE. */
649 #define X87_ENABLE_FLOAT(MODE, IMODE) \
650 (flag_excess_precision == EXCESS_PRECISION_FAST \
651 || (MODE) == XFmode \
652 || ((MODE) == DFmode && (IMODE) == SImode) \
653 || (IMODE) == HImode)
655 /* target machine storage layout */
657 #define SHORT_TYPE_SIZE 16
658 #define INT_TYPE_SIZE 32
659 #define LONG_LONG_TYPE_SIZE 64
660 #define FLOAT_TYPE_SIZE 32
661 #define DOUBLE_TYPE_SIZE 64
662 #define LONG_DOUBLE_TYPE_SIZE 80
664 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
666 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
667 #define MAX_BITS_PER_WORD 64
669 #define MAX_BITS_PER_WORD 32
672 /* Define this if most significant byte of a word is the lowest numbered. */
673 /* That is true on the 80386. */
675 #define BITS_BIG_ENDIAN 0
677 /* Define this if most significant byte of a word is the lowest numbered. */
678 /* That is not true on the 80386. */
679 #define BYTES_BIG_ENDIAN 0
681 /* Define this if most significant word of a multiword number is the lowest
683 /* Not true for 80386 */
684 #define WORDS_BIG_ENDIAN 0
686 /* Width of a word, in units (bytes). */
687 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
690 #define MIN_UNITS_PER_WORD 4
693 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
694 #define PARM_BOUNDARY BITS_PER_WORD
696 /* Boundary (in *bits*) on which stack pointer should be aligned. */
697 #define STACK_BOUNDARY \
698 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
700 /* Stack boundary of the main function guaranteed by OS. */
701 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
703 /* Minimum stack boundary. */
704 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
706 /* Boundary (in *bits*) on which the stack pointer prefers to be
707 aligned; the compiler cannot rely on having this alignment. */
708 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
710 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
711 both 32bit and 64bit, to support codes that need 128 bit stack
712 alignment for SSE instructions, but can't realign the stack. */
713 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
715 /* 1 if -mstackrealign should be turned on by default. It will
716 generate an alternate prologue and epilogue that realigns the
717 runtime stack if nessary. This supports mixing codes that keep a
718 4-byte aligned stack, as specified by i386 psABI, with codes that
719 need a 16-byte aligned stack, as required by SSE instructions. */
720 #define STACK_REALIGN_DEFAULT 0
722 /* Boundary (in *bits*) on which the incoming stack is aligned. */
723 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
725 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
726 mandatory for the 64-bit ABI, and may or may not be true for other
727 operating systems. */
728 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
730 /* Minimum allocation boundary for the code of a function. */
731 #define FUNCTION_BOUNDARY 8
733 /* C++ stores the virtual bit in the lowest bit of function pointers. */
734 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
736 /* Minimum size in bits of the largest boundary to which any
737 and all fundamental data types supported by the hardware
738 might need to be aligned. No data type wants to be aligned
741 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
742 and Pentium Pro XFmode values at 128 bit boundaries. */
744 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128)
746 /* Maximum stack alignment. */
747 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
749 /* Alignment value for attribute ((aligned)). It is a constant since
750 it is the part of the ABI. We shouldn't change it with -mavx. */
751 #define ATTRIBUTE_ALIGNED_VALUE 128
753 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
754 #define ALIGN_MODE_128(MODE) \
755 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
757 /* The published ABIs say that doubles should be aligned on word
758 boundaries, so lower the alignment for structure fields unless
759 -malign-double is set. */
761 /* ??? Blah -- this macro is used directly by libobjc. Since it
762 supports no vector modes, cut out the complexity and fall back
763 on BIGGEST_FIELD_ALIGNMENT. */
764 #ifdef IN_TARGET_LIBS
766 #define BIGGEST_FIELD_ALIGNMENT 128
768 #define BIGGEST_FIELD_ALIGNMENT 32
771 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
772 x86_field_alignment (FIELD, COMPUTED)
775 /* If defined, a C expression to compute the alignment given to a
776 constant that is being placed in memory. EXP is the constant
777 and ALIGN is the alignment that the object would ordinarily have.
778 The value of this macro is used instead of that alignment to align
781 If this macro is not defined, then ALIGN is used.
783 The typical use of this macro is to increase alignment for string
784 constants to be word aligned so that `strcpy' calls that copy
785 constants can be done inline. */
787 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
789 /* If defined, a C expression to compute the alignment for a static
790 variable. TYPE is the data type, and ALIGN is the alignment that
791 the object would ordinarily have. The value of this macro is used
792 instead of that alignment to align the object.
794 If this macro is not defined, then ALIGN is used.
796 One use of this macro is to increase alignment of medium-size
797 data to make it all fit in fewer cache lines. Another is to
798 cause character arrays to be word-aligned so that `strcpy' calls
799 that copy constants to character arrays can be done inline. */
801 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
803 /* If defined, a C expression to compute the alignment for a local
804 variable. TYPE is the data type, and ALIGN is the alignment that
805 the object would ordinarily have. The value of this macro is used
806 instead of that alignment to align the object.
808 If this macro is not defined, then ALIGN is used.
810 One use of this macro is to increase alignment of medium-size
811 data to make it all fit in fewer cache lines. */
813 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
814 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
816 /* If defined, a C expression to compute the alignment for stack slot.
817 TYPE is the data type, MODE is the widest mode available, and ALIGN
818 is the alignment that the slot would ordinarily have. The value of
819 this macro is used instead of that alignment to align the slot.
821 If this macro is not defined, then ALIGN is used when TYPE is NULL,
822 Otherwise, LOCAL_ALIGNMENT will be used.
824 One use of this macro is to set alignment of stack slot to the
825 maximum alignment of all possible modes which the slot may have. */
827 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
828 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
830 /* If defined, a C expression to compute the alignment for a local
833 If this macro is not defined, then
834 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
836 One use of this macro is to increase alignment of medium-size
837 data to make it all fit in fewer cache lines. */
839 #define LOCAL_DECL_ALIGNMENT(DECL) \
840 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
842 /* If defined, a C expression to compute the minimum required alignment
843 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
844 MODE, assuming normal alignment ALIGN.
846 If this macro is not defined, then (ALIGN) will be used. */
848 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
849 ix86_minimum_alignment (EXP, MODE, ALIGN)
852 /* Set this nonzero if move instructions will actually fail to work
853 when given unaligned data. */
854 #define STRICT_ALIGNMENT 0
856 /* If bit field type is int, don't let it cross an int,
857 and give entire struct the alignment of an int. */
858 /* Required on the 386 since it doesn't have bit-field insns. */
859 #define PCC_BITFIELD_TYPE_MATTERS 1
861 /* Standard register usage. */
863 /* This processor has special stack-like registers. See reg-stack.c
868 #define IS_STACK_MODE(MODE) \
869 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \
870 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \
873 /* Number of actual hardware registers.
874 The hardware registers are assigned numbers for the compiler
875 from 0 to just below FIRST_PSEUDO_REGISTER.
876 All registers that the compiler knows about must be given numbers,
877 even those that are not normally considered general registers.
879 In the 80386 we give the 8 general purpose registers the numbers 0-7.
880 We number the floating point registers 8-15.
881 Note that registers 0-7 can be accessed as a short or int,
882 while only 0-3 may be used with byte `mov' instructions.
884 Reg 16 does not correspond to any hardware register, but instead
885 appears in the RTL as an argument pointer prior to reload, and is
886 eliminated during reloading in favor of either the stack or frame
889 #define FIRST_PSEUDO_REGISTER 53
891 /* Number of hardware registers that go into the DWARF-2 unwind info.
892 If not defined, equals FIRST_PSEUDO_REGISTER. */
894 #define DWARF_FRAME_REGISTERS 17
896 /* 1 for registers that have pervasive standard uses
897 and are not available for the register allocator.
898 On the 80386, the stack pointer is such, as is the arg pointer.
900 The value is zero if the register is not fixed on either 32 or
901 64 bit targets, one if the register if fixed on both 32 and 64
902 bit targets, two if it is only fixed on 32bit targets and three
903 if its only fixed on 64bit targets.
904 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
906 #define FIXED_REGISTERS \
907 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
908 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
909 /*arg,flags,fpsr,fpcr,frame*/ \
911 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
912 0, 0, 0, 0, 0, 0, 0, 0, \
913 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
914 0, 0, 0, 0, 0, 0, 0, 0, \
915 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
916 2, 2, 2, 2, 2, 2, 2, 2, \
917 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
918 2, 2, 2, 2, 2, 2, 2, 2 }
921 /* 1 for registers not available across function calls.
922 These must include the FIXED_REGISTERS and also any
923 registers that can be used without being saved.
924 The latter must include the registers where values are returned
925 and the register where structure-value addresses are passed.
926 Aside from that, you can include as many other registers as you like.
928 The value is zero if the register is not call used on either 32 or
929 64 bit targets, one if the register if call used on both 32 and 64
930 bit targets, two if it is only call used on 32bit targets and three
931 if its only call used on 64bit targets.
932 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
934 #define CALL_USED_REGISTERS \
935 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
936 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
937 /*arg,flags,fpsr,fpcr,frame*/ \
939 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
940 1, 1, 1, 1, 1, 1, 1, 1, \
941 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
942 1, 1, 1, 1, 1, 1, 1, 1, \
943 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
944 1, 1, 1, 1, 2, 2, 2, 2, \
945 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
946 1, 1, 1, 1, 1, 1, 1, 1 }
948 /* Order in which to allocate registers. Each register must be
949 listed once, even those in FIXED_REGISTERS. List frame pointer
950 late and fixed registers last. Note that, in general, we prefer
951 registers listed in CALL_USED_REGISTERS, keeping the others
952 available for storage of persistent values.
954 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
955 so this is just empty initializer for array. */
957 #define REG_ALLOC_ORDER \
958 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
959 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
960 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
963 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
964 to be rearranged based on a particular function. When using sse math,
965 we want to allocate SSE before x87 registers and vice versa. */
967 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
970 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
972 /* Return number of consecutive hard regs needed starting at reg REGNO
973 to hold something of mode MODE.
974 This is ordinarily the length in words of a value of mode MODE
975 but can be less for certain modes in special long registers.
977 Actually there are no two word move instructions for consecutive
978 registers. And only registers 0-3 may have mov byte instructions
981 #define HARD_REGNO_NREGS(REGNO, MODE) \
982 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
983 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
984 : ((MODE) == XFmode \
985 ? (TARGET_64BIT ? 2 : 3) \
987 ? (TARGET_64BIT ? 4 : 6) \
988 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
990 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
991 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
992 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
994 : ((MODE) == XFmode || (MODE) == XCmode)) \
997 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
999 #define VALID_AVX256_REG_MODE(MODE) \
1000 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1001 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1003 #define VALID_SSE2_REG_MODE(MODE) \
1004 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1005 || (MODE) == V2DImode || (MODE) == DFmode)
1007 #define VALID_SSE_REG_MODE(MODE) \
1008 ((MODE) == V1TImode || (MODE) == TImode \
1009 || (MODE) == V4SFmode || (MODE) == V4SImode \
1010 || (MODE) == SFmode || (MODE) == TFmode)
1012 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1013 ((MODE) == V2SFmode || (MODE) == SFmode)
1015 #define VALID_MMX_REG_MODE(MODE) \
1016 ((MODE == V1DImode) || (MODE) == DImode \
1017 || (MODE) == V2SImode || (MODE) == SImode \
1018 || (MODE) == V4HImode || (MODE) == V8QImode)
1020 #define VALID_DFP_MODE_P(MODE) \
1021 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1023 #define VALID_FP_MODE_P(MODE) \
1024 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1025 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1027 #define VALID_INT_MODE_P(MODE) \
1028 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1029 || (MODE) == DImode \
1030 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1031 || (MODE) == CDImode \
1032 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1033 || (MODE) == TFmode || (MODE) == TCmode)))
1035 /* Return true for modes passed in SSE registers. */
1036 #define SSE_REG_MODE_P(MODE) \
1037 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1038 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1039 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1040 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1041 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1043 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1045 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1046 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1048 /* Value is 1 if it is a good idea to tie two pseudo registers
1049 when one has mode MODE1 and one has mode MODE2.
1050 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1051 for any hard reg, then this must be 0 for correct output. */
1053 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1055 /* It is possible to write patterns to move flags; but until someone
1057 #define AVOID_CCMODE_COPIES
1059 /* Specify the modes required to caller save a given hard regno.
1060 We do this on i386 to prevent flags from being saved at all.
1062 Kill any attempts to combine saving of modes. */
1064 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1065 (CC_REGNO_P (REGNO) ? VOIDmode \
1066 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1067 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1068 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1069 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \
1072 /* The only ABI that saves SSE registers across calls is Win64 (thus no
1073 need to check the current ABI here), and with AVX enabled Win64 only
1074 guarantees that the low 16 bytes are saved. */
1075 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1076 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16)
1078 /* Specify the registers used for certain standard purposes.
1079 The values of these macros are register numbers. */
1081 /* on the 386 the pc register is %eip, and is not usable as a general
1082 register. The ordinary mov instructions won't work */
1083 /* #define PC_REGNUM */
1085 /* Register to use for pushing function arguments. */
1086 #define STACK_POINTER_REGNUM 7
1088 /* Base register for access to local variables of the function. */
1089 #define HARD_FRAME_POINTER_REGNUM 6
1091 /* Base register for access to local variables of the function. */
1092 #define FRAME_POINTER_REGNUM 20
1094 /* First floating point reg */
1095 #define FIRST_FLOAT_REG 8
1097 /* First & last stack-like regs */
1098 #define FIRST_STACK_REG FIRST_FLOAT_REG
1099 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1101 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1102 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1104 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1105 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1107 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1108 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1110 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1111 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1113 /* Override this in other tm.h files to cope with various OS lossage
1114 requiring a frame pointer. */
1115 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1116 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1119 /* Make sure we can access arbitrary call frames. */
1120 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1122 /* Base register for access to arguments of the function. */
1123 #define ARG_POINTER_REGNUM 16
1125 /* Register to hold the addressing base for position independent
1126 code access to data items. We don't use PIC pointer for 64bit
1127 mode. Define the regnum to dummy value to prevent gcc from
1128 pessimizing code dealing with EBX.
1130 To avoid clobbering a call-saved register unnecessarily, we renumber
1131 the pic register when possible. The change is visible after the
1132 prologue has been emitted. */
1134 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1136 #define PIC_OFFSET_TABLE_REGNUM \
1137 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1138 || !flag_pic ? INVALID_REGNUM \
1139 : reload_completed ? REGNO (pic_offset_table_rtx) \
1140 : REAL_PIC_OFFSET_TABLE_REGNUM)
1142 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1144 /* This is overridden by <cygwin.h>. */
1145 #define MS_AGGREGATE_RETURN 0
1147 /* This is overridden by <netware.h>. */
1148 #define KEEP_AGGREGATE_RETURN_POINTER 0
1150 /* Define the classes of registers for register constraints in the
1151 machine description. Also define ranges of constants.
1153 One of the classes must always be named ALL_REGS and include all hard regs.
1154 If there is more than one class, another class must be named NO_REGS
1155 and contain no registers.
1157 The name GENERAL_REGS must be the name of a class (or an alias for
1158 another name such as ALL_REGS). This is the class of registers
1159 that is allowed by "g" or "r" in a register constraint.
1160 Also, registers outside this class are allocated only when
1161 instructions express preferences for them.
1163 The classes must be numbered in nondecreasing order; that is,
1164 a larger-numbered class must never be contained completely
1165 in a smaller-numbered class.
1167 For any two classes, it is very desirable that there be another
1168 class that represents their union.
1170 It might seem that class BREG is unnecessary, since no useful 386
1171 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1172 and the "b" register constraint is useful in asms for syscalls.
1174 The flags, fpsr and fpcr registers are in no class. */
1179 AREG, DREG, CREG, BREG, SIREG, DIREG,
1180 AD_REGS, /* %eax/%edx for DImode */
1181 CLOBBERED_REGS, /* call-clobbered integers */
1182 Q_REGS, /* %eax %ebx %ecx %edx */
1183 NON_Q_REGS, /* %esi %edi %ebp %esp */
1184 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1185 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1186 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1187 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1188 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1199 ALL_REGS, LIM_REG_CLASSES
1202 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1204 #define INTEGER_CLASS_P(CLASS) \
1205 reg_class_subset_p ((CLASS), GENERAL_REGS)
1206 #define FLOAT_CLASS_P(CLASS) \
1207 reg_class_subset_p ((CLASS), FLOAT_REGS)
1208 #define SSE_CLASS_P(CLASS) \
1209 reg_class_subset_p ((CLASS), SSE_REGS)
1210 #define MMX_CLASS_P(CLASS) \
1211 ((CLASS) == MMX_REGS)
1212 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1213 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1214 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1215 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1216 #define MAYBE_SSE_CLASS_P(CLASS) \
1217 reg_classes_intersect_p (SSE_REGS, (CLASS))
1218 #define MAYBE_MMX_CLASS_P(CLASS) \
1219 reg_classes_intersect_p (MMX_REGS, (CLASS))
1221 #define Q_CLASS_P(CLASS) \
1222 reg_class_subset_p ((CLASS), Q_REGS)
1224 /* Give names of register classes as strings for dump file. */
1226 #define REG_CLASS_NAMES \
1228 "AREG", "DREG", "CREG", "BREG", \
1232 "Q_REGS", "NON_Q_REGS", \
1236 "FP_TOP_REG", "FP_SECOND_REG", \
1241 "FP_TOP_SSE_REGS", \
1242 "FP_SECOND_SSE_REGS", \
1246 "FLOAT_INT_SSE_REGS", \
1249 /* Define which registers fit in which classes. This is an initializer
1250 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1252 Note that the default setting of CLOBBERED_REGS is for 32-bit; this
1253 is adjusted by TARGET_CONDITIONAL_REGISTER_USAGE for the 64-bit ABI
1256 #define REG_CLASS_CONTENTS \
1258 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1259 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1260 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1261 { 0x03, 0x0 }, /* AD_REGS */ \
1262 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \
1263 { 0x0f, 0x0 }, /* Q_REGS */ \
1264 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1265 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1266 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1267 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1268 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1269 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1270 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1271 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1272 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1273 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1274 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1275 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1276 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1277 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1278 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1279 { 0xffffffff,0x1fffff } \
1282 /* The same information, inverted:
1283 Return the class number of the smallest class containing
1284 reg number REGNO. This could be a conditional expression
1285 or could index an array. */
1287 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1289 /* When this hook returns true for MODE, the compiler allows
1290 registers explicitly used in the rtl to be used as spill registers
1291 but prevents the compiler from extending the lifetime of these
1293 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1295 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG)
1297 #define GENERAL_REGNO_P(N) \
1298 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1300 #define GENERAL_REG_P(X) \
1301 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1303 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1305 #define REX_INT_REGNO_P(N) \
1306 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1307 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1309 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1310 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1311 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1312 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1314 #define X87_FLOAT_MODE_P(MODE) \
1315 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1317 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1318 #define SSE_REGNO_P(N) \
1319 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1320 || REX_SSE_REGNO_P (N))
1322 #define REX_SSE_REGNO_P(N) \
1323 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1325 #define SSE_REGNO(N) \
1326 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1328 #define SSE_FLOAT_MODE_P(MODE) \
1329 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1331 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
1332 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1333 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1335 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1336 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1338 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1339 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1341 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1343 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1344 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1346 /* The class value for index registers, and the one for base regs. */
1348 #define INDEX_REG_CLASS INDEX_REGS
1349 #define BASE_REG_CLASS GENERAL_REGS
1351 /* Place additional restrictions on the register class to use when it
1352 is necessary to be able to hold a value of mode MODE in a reload
1353 register for which class CLASS would ordinarily be used. */
1355 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1356 ((MODE) == QImode && !TARGET_64BIT \
1357 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1358 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1361 /* If we are copying between general and FP registers, we need a memory
1362 location. The same is true for SSE and MMX registers. */
1363 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1364 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1366 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1367 There is no need to emit full 64 bit move on 64 bit targets
1368 for integral modes that can be moved using 32 bit move. */
1369 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1370 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1371 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1374 /* Return the maximum number of consecutive registers
1375 needed to represent mode MODE in a register of class CLASS. */
1376 /* On the 80386, this is the size of MODE in words,
1377 except in the FP regs, where a single reg is always enough. */
1378 #define CLASS_MAX_NREGS(CLASS, MODE) \
1379 (MAYBE_INTEGER_CLASS_P (CLASS) \
1380 ? ((MODE) == XFmode \
1381 ? (TARGET_64BIT ? 2 : 3) \
1382 : (MODE) == XCmode \
1383 ? (TARGET_64BIT ? 4 : 6) \
1384 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
1385 : (COMPLEX_MODE_P (MODE) ? 2 : 1))
1387 /* Return a class of registers that cannot change FROM mode to TO mode. */
1389 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1390 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1392 /* Stack layout; function entry, exit and calling. */
1394 /* Define this if pushing a word on the stack
1395 makes the stack pointer a smaller address. */
1396 #define STACK_GROWS_DOWNWARD
1398 /* Define this to nonzero if the nominal address of the stack frame
1399 is at the high-address end of the local variables;
1400 that is, each additional local variable allocated
1401 goes at a more negative offset in the frame. */
1402 #define FRAME_GROWS_DOWNWARD 1
1404 /* Offset within stack frame to start allocating local variables at.
1405 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1406 first local allocated. Otherwise, it is the offset to the BEGINNING
1407 of the first local allocated. */
1408 #define STARTING_FRAME_OFFSET 0
1410 /* If we generate an insn to push BYTES bytes, this says how many the stack
1411 pointer really advances by. On 386, we have pushw instruction that
1412 decrements by exactly 2 no matter what the position was, there is no pushb.
1414 But as CIE data alignment factor on this arch is -4 for 32bit targets
1415 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1416 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1418 #define PUSH_ROUNDING(BYTES) \
1419 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)
1421 /* If defined, the maximum amount of space required for outgoing arguments
1422 will be computed and placed into the variable `crtl->outgoing_args_size'.
1423 No space will be pushed onto the stack for each call; instead, the
1424 function prologue should increase the stack frame size by this amount.
1426 64-bit MS ABI seem to require 16 byte alignment everywhere except for
1427 function prologue and apilogue. This is not possible without
1428 ACCUMULATE_OUTGOING_ARGS. */
1430 #define ACCUMULATE_OUTGOING_ARGS \
1431 (TARGET_ACCUMULATE_OUTGOING_ARGS || TARGET_64BIT_MS_ABI)
1433 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1434 instructions to pass outgoing arguments. */
1436 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1438 /* We want the stack and args grow in opposite directions, even if
1440 #define PUSH_ARGS_REVERSED 1
1442 /* Offset of first parameter from the argument pointer register value. */
1443 #define FIRST_PARM_OFFSET(FNDECL) 0
1445 /* Define this macro if functions should assume that stack space has been
1446 allocated for arguments even when their values are passed in registers.
1448 The value of this macro is the size, in bytes, of the area reserved for
1449 arguments passed in registers for the function represented by FNDECL.
1451 This space can be allocated by the caller, or be a part of the
1452 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1454 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1456 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1457 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1459 /* Define how to find the value returned by a library function
1460 assuming the value has mode MODE. */
1462 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1464 /* Define the size of the result block used for communication between
1465 untyped_call and untyped_return. The block contains a DImode value
1466 followed by the block used by fnsave and frstor. */
1468 #define APPLY_RESULT_SIZE (8+108)
1470 /* 1 if N is a possible register number for function argument passing. */
1471 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1473 /* Define a data type for recording info about an argument list
1474 during the scan of that argument list. This data type should
1475 hold all necessary information about the function itself
1476 and about the args processed so far, enough to enable macros
1477 such as FUNCTION_ARG to determine where the next arg should go. */
1479 typedef struct ix86_args {
1480 int words; /* # words passed so far */
1481 int nregs; /* # registers available for passing */
1482 int regno; /* next available register number */
1483 int fastcall; /* fastcall or thiscall calling convention
1485 int sse_words; /* # sse words passed so far */
1486 int sse_nregs; /* # sse registers available for passing */
1487 int warn_avx; /* True when we want to warn about AVX ABI. */
1488 int warn_sse; /* True when we want to warn about SSE ABI. */
1489 int warn_mmx; /* True when we want to warn about MMX ABI. */
1490 int sse_regno; /* next available sse register number */
1491 int mmx_words; /* # mmx words passed so far */
1492 int mmx_nregs; /* # mmx registers available for passing */
1493 int mmx_regno; /* next available mmx register number */
1494 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1495 int caller; /* true if it is caller. */
1496 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1497 SFmode/DFmode arguments should be passed
1498 in SSE registers. Otherwise 0. */
1499 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1500 MS_ABI for ms abi. */
1503 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1504 for a call to a function whose data type is FNTYPE.
1505 For a library call, FNTYPE is 0. */
1507 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1508 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1509 (N_NAMED_ARGS) != -1)
1511 /* Output assembler code to FILE to increment profiler label # LABELNO
1512 for profiling a function entry. */
1514 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1516 #define MCOUNT_NAME "_mcount"
1518 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1520 #define PROFILE_COUNT_REGISTER "edx"
1522 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1523 the stack pointer does not matter. The value is tested only in
1524 functions that have frame pointers.
1525 No definition is equivalent to always zero. */
1526 /* Note on the 386 it might be more efficient not to define this since
1527 we have to restore it ourselves from the frame pointer, in order to
1530 #define EXIT_IGNORE_STACK 1
1532 /* Output assembler code for a block containing the constant parts
1533 of a trampoline, leaving space for the variable parts. */
1535 /* On the 386, the trampoline contains two instructions:
1538 The trampoline is generated entirely at runtime. The operand of JMP
1539 is the address of FUNCTION relative to the instruction following the
1540 JMP (which is 5 bytes long). */
1542 /* Length in units of the trampoline for entering a nested function. */
1544 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1546 /* Definitions for register eliminations.
1548 This is an array of structures. Each structure initializes one pair
1549 of eliminable registers. The "from" register number is given first,
1550 followed by "to". Eliminations of the same "from" register are listed
1551 in order of preference.
1553 There are two registers that can always be eliminated on the i386.
1554 The frame pointer and the arg pointer can be replaced by either the
1555 hard frame pointer or to the stack pointer, depending upon the
1556 circumstances. The hard frame pointer is not used before reload and
1557 so it is not eligible for elimination. */
1559 #define ELIMINABLE_REGS \
1560 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1561 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1562 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1563 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1565 /* Define the offset between two registers, one to be eliminated, and the other
1566 its replacement, at the start of a routine. */
1568 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1569 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1571 /* Addressing modes, and classification of registers for them. */
1573 /* Macros to check register numbers against specific register classes. */
1575 /* These assume that REGNO is a hard or pseudo reg number.
1576 They give nonzero only if REGNO is a hard reg of the suitable class
1577 or a pseudo reg currently allocated to a suitable hard reg.
1578 Since they use reg_renumber, they are safe only once reg_renumber
1579 has been allocated, which happens in local-alloc.c. */
1581 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1582 ((REGNO) < STACK_POINTER_REGNUM \
1583 || REX_INT_REGNO_P (REGNO) \
1584 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1585 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1587 #define REGNO_OK_FOR_BASE_P(REGNO) \
1588 (GENERAL_REGNO_P (REGNO) \
1589 || (REGNO) == ARG_POINTER_REGNUM \
1590 || (REGNO) == FRAME_POINTER_REGNUM \
1591 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1593 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1594 and check its validity for a certain class.
1595 We have two alternate definitions for each of them.
1596 The usual definition accepts all pseudo regs; the other rejects
1597 them unless they have been allocated suitable hard regs.
1598 The symbol REG_OK_STRICT causes the latter definition to be used.
1600 Most source files want to accept pseudo regs in the hope that
1601 they will get allocated to the class that the insn wants them to be in.
1602 Source files for reload pass need to be strict.
1603 After reload, it makes no difference, since pseudo regs have
1604 been eliminated by then. */
1607 /* Non strict versions, pseudos are ok. */
1608 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1609 (REGNO (X) < STACK_POINTER_REGNUM \
1610 || REX_INT_REGNO_P (REGNO (X)) \
1611 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1613 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1614 (GENERAL_REGNO_P (REGNO (X)) \
1615 || REGNO (X) == ARG_POINTER_REGNUM \
1616 || REGNO (X) == FRAME_POINTER_REGNUM \
1617 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1619 /* Strict versions, hard registers only */
1620 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1621 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1623 #ifndef REG_OK_STRICT
1624 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1625 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1628 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1629 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1632 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1633 that is a valid memory address for an instruction.
1634 The MODE argument is the machine mode for the MEM expression
1635 that wants to use this address.
1637 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1638 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1640 See legitimize_pic_address in i386.c for details as to what
1641 constitutes a legitimate address when -fpic is used. */
1643 #define MAX_REGS_PER_ADDRESS 2
1645 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1647 /* If defined, a C expression to determine the base term of address X.
1648 This macro is used in only one place: `find_base_term' in alias.c.
1650 It is always safe for this macro to not be defined. It exists so
1651 that alias analysis can understand machine-dependent addresses.
1653 The typical use of this macro is to handle addresses containing
1654 a label_ref or symbol_ref within an UNSPEC. */
1656 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1658 /* Nonzero if the constant value X is a legitimate general operand
1659 when generating PIC code. It is given that flag_pic is on and
1660 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1662 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1664 #define SYMBOLIC_CONST(X) \
1665 (GET_CODE (X) == SYMBOL_REF \
1666 || GET_CODE (X) == LABEL_REF \
1667 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1669 /* Max number of args passed in registers. If this is more than 3, we will
1670 have problems with ebx (register #4), since it is a caller save register and
1671 is also used as the pic register in ELF. So for now, don't allow more than
1672 3 registers to be passed in registers. */
1674 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1675 #define X86_64_REGPARM_MAX 6
1676 #define X86_64_MS_REGPARM_MAX 4
1678 #define X86_32_REGPARM_MAX 3
1680 #define REGPARM_MAX \
1682 ? (TARGET_64BIT_MS_ABI \
1683 ? X86_64_MS_REGPARM_MAX \
1684 : X86_64_REGPARM_MAX) \
1685 : X86_32_REGPARM_MAX)
1687 #define X86_64_SSE_REGPARM_MAX 8
1688 #define X86_64_MS_SSE_REGPARM_MAX 4
1690 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1692 #define SSE_REGPARM_MAX \
1694 ? (TARGET_64BIT_MS_ABI \
1695 ? X86_64_MS_SSE_REGPARM_MAX \
1696 : X86_64_SSE_REGPARM_MAX) \
1697 : X86_32_SSE_REGPARM_MAX)
1699 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1701 /* Specify the machine mode that this machine uses
1702 for the index in the tablejump instruction. */
1703 #define CASE_VECTOR_MODE \
1704 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1706 /* Define this as 1 if `char' should by default be signed; else as 0. */
1707 #define DEFAULT_SIGNED_CHAR 1
1709 /* Max number of bytes we can move from memory to memory
1710 in one reasonably fast instruction. */
1713 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1714 move efficiently, as opposed to MOVE_MAX which is the maximum
1715 number of bytes we can move with a single instruction. */
1716 #define MOVE_MAX_PIECES UNITS_PER_WORD
1718 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1719 move-instruction pairs, we will do a movmem or libcall instead.
1720 Increasing the value will always make code faster, but eventually
1721 incurs high cost in increased code size.
1723 If you don't define this, a reasonable default is used. */
1725 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1727 /* If a clear memory operation would take CLEAR_RATIO or more simple
1728 move-instruction sequences, we will do a clrmem or libcall instead. */
1730 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1732 /* Define if shifts truncate the shift count which implies one can
1733 omit a sign-extension or zero-extension of a shift count.
1735 On i386, shifts do truncate the count. But bit test instructions
1736 take the modulo of the bit offset operand. */
1738 /* #define SHIFT_COUNT_TRUNCATED */
1740 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1741 is done just by pretending it is already truncated. */
1742 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1744 /* A macro to update M and UNSIGNEDP when an object whose type is
1745 TYPE and which has the specified mode and signedness is to be
1746 stored in a register. This macro is only called when TYPE is a
1749 On i386 it is sometimes useful to promote HImode and QImode
1750 quantities to SImode. The choice depends on target type. */
1752 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1754 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1755 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1759 /* Specify the machine mode that pointers have.
1760 After generation of rtl, the compiler makes no further distinction
1761 between pointers and any other objects of this machine mode. */
1762 #define Pmode (TARGET_64BIT ? DImode : SImode)
1764 /* A function address in a call instruction
1765 is a byte address (for indexing purposes)
1766 so give the MEM rtx a byte's mode. */
1767 #define FUNCTION_MODE QImode
1770 /* A C expression for the cost of a branch instruction. A value of 1
1771 is the default; other values are interpreted relative to that. */
1773 #define BRANCH_COST(speed_p, predictable_p) \
1774 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1776 /* Define this macro as a C expression which is nonzero if accessing
1777 less than a word of memory (i.e. a `char' or a `short') is no
1778 faster than accessing a word of memory, i.e., if such access
1779 require more than one instruction or if there is no difference in
1780 cost between byte and (aligned) word loads.
1782 When this macro is not defined, the compiler will access a field by
1783 finding the smallest containing object; when it is defined, a
1784 fullword load will be used if alignment permits. Unless bytes
1785 accesses are faster than word accesses, using word accesses is
1786 preferable since it may eliminate subsequent memory access if
1787 subsequent accesses occur to other fields in the same word of the
1788 structure, but to different bytes. */
1790 #define SLOW_BYTE_ACCESS 0
1792 /* Nonzero if access to memory by shorts is slow and undesirable. */
1793 #define SLOW_SHORT_ACCESS 0
1795 /* Define this macro to be the value 1 if unaligned accesses have a
1796 cost many times greater than aligned accesses, for example if they
1797 are emulated in a trap handler.
1799 When this macro is nonzero, the compiler will act as if
1800 `STRICT_ALIGNMENT' were nonzero when generating code for block
1801 moves. This can cause significantly more instructions to be
1802 produced. Therefore, do not set this macro nonzero if unaligned
1803 accesses only add a cycle or two to the time for a memory access.
1805 If the value of this macro is always zero, it need not be defined. */
1807 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1809 /* Define this macro if it is as good or better to call a constant
1810 function address than to call an address kept in a register.
1812 Desirable on the 386 because a CALL with a constant address is
1813 faster than one with a register address. */
1815 #define NO_FUNCTION_CSE
1817 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1818 return the mode to be used for the comparison.
1820 For floating-point equality comparisons, CCFPEQmode should be used.
1821 VOIDmode should be used in all other cases.
1823 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1824 possible, to allow for more combinations. */
1826 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1828 /* Return nonzero if MODE implies a floating point inequality can be
1831 #define REVERSIBLE_CC_MODE(MODE) 1
1833 /* A C expression whose value is reversed condition code of the CODE for
1834 comparison done in CC_MODE mode. */
1835 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1838 /* Control the assembler format that we output, to the extent
1839 this does not vary between assemblers. */
1841 /* How to refer to registers in assembler output.
1842 This sequence is indexed by compiler's hard-register-number (see above). */
1844 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1845 For non floating point regs, the following are the HImode names.
1847 For float regs, the stack top is sometimes referred to as "%st(0)"
1848 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
1851 #define HI_REGISTER_NAMES \
1852 {"ax","dx","cx","bx","si","di","bp","sp", \
1853 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1854 "argp", "flags", "fpsr", "fpcr", "frame", \
1855 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1856 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1857 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1858 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1860 #define REGISTER_NAMES HI_REGISTER_NAMES
1862 /* Table of additional register names to use in user input. */
1864 #define ADDITIONAL_REGISTER_NAMES \
1865 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1866 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1867 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1868 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1869 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1870 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1872 /* Note we are omitting these since currently I don't know how
1873 to get gcc to use these, since they want the same but different
1874 number as al, and ax.
1877 #define QI_REGISTER_NAMES \
1878 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1880 /* These parallel the array above, and can be used to access bits 8:15
1881 of regs 0 through 3. */
1883 #define QI_HIGH_REGISTER_NAMES \
1884 {"ah", "dh", "ch", "bh", }
1886 /* How to renumber registers for dbx and gdb. */
1888 #define DBX_REGISTER_NUMBER(N) \
1889 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1891 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1892 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1893 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1895 /* Before the prologue, RA is at 0(%esp). */
1896 #define INCOMING_RETURN_ADDR_RTX \
1897 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1899 /* After the prologue, RA is at -4(AP) in the current frame. */
1900 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1902 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1903 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1905 /* PC is dbx register 8; let's use that column for RA. */
1906 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1908 /* Before the prologue, the top of the frame is at 4(%esp). */
1909 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1911 /* Describe how we implement __builtin_eh_return. */
1912 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
1913 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
1916 /* Select a format to encode pointers in exception handling data. CODE
1917 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1918 true if the symbol may be affected by dynamic relocations.
1920 ??? All x86 object file formats are capable of representing this.
1921 After all, the relocation needed is the same as for the call insn.
1922 Whether or not a particular assembler allows us to enter such, I
1923 guess we'll have to see. */
1924 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1925 asm_preferred_eh_data_format ((CODE), (GLOBAL))
1927 /* This is how to output an insn to push a register on the stack.
1928 It need not be very fast code. */
1930 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1933 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
1934 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1936 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
1939 /* This is how to output an insn to pop a register from the stack.
1940 It need not be very fast code. */
1942 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
1945 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
1946 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1948 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
1951 /* This is how to output an element of a case-vector that is absolute. */
1953 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1954 ix86_output_addr_vec_elt ((FILE), (VALUE))
1956 /* This is how to output an element of a case-vector that is relative. */
1958 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1959 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
1961 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
1963 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
1965 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
1966 (PTR) += TARGET_AVX ? 1 : 2; \
1969 /* A C statement or statements which output an assembler instruction
1970 opcode to the stdio stream STREAM. The macro-operand PTR is a
1971 variable of type `char *' which points to the opcode name in
1972 its "internal" form--the form that is written in the machine
1975 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1976 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
1978 /* A C statement to output to the stdio stream FILE an assembler
1979 command to pad the location counter to a multiple of 1<<LOG
1980 bytes if it is within MAX_SKIP bytes. */
1982 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
1983 #undef ASM_OUTPUT_MAX_SKIP_PAD
1984 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
1987 if ((MAX_SKIP) == 0) \
1988 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
1990 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
1994 /* Write the extra assembler code needed to declare a function
1997 #undef ASM_OUTPUT_FUNCTION_LABEL
1998 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
1999 ix86_asm_output_function_label (FILE, NAME, DECL)
2001 /* Under some conditions we need jump tables in the text section,
2002 because the assembler cannot handle label differences between
2003 sections. This is the case for x86_64 on Mach-O for example. */
2005 #define JUMP_TABLES_IN_TEXT_SECTION \
2006 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2007 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2009 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2010 and switch back. For x86 we do this only to save a few bytes that
2011 would otherwise be unused in the text section. */
2012 #define CRT_MKSTR2(VAL) #VAL
2013 #define CRT_MKSTR(x) CRT_MKSTR2(x)
2015 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2016 asm (SECTION_OP "\n\t" \
2017 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2018 TEXT_SECTION_ASM_OP);
2020 /* Which processor to tune code generation for. */
2024 PROCESSOR_I386 = 0, /* 80386 */
2025 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2027 PROCESSOR_PENTIUMPRO,
2036 PROCESSOR_COREI7_32,
2037 PROCESSOR_COREI7_64,
2038 PROCESSOR_GENERIC32,
2039 PROCESSOR_GENERIC64,
2047 extern enum processor_type ix86_tune;
2048 extern enum processor_type ix86_arch;
2056 extern enum fpmath_unit ix86_fpmath;
2065 extern enum tls_dialect ix86_tls_dialect;
2068 CM_32, /* The traditional 32-bit ABI. */
2069 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2070 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2071 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2072 CM_LARGE, /* No assumptions. */
2073 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2074 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2075 CM_LARGE_PIC /* No assumptions. */
2078 extern enum cmodel ix86_cmodel;
2080 /* Size of the RED_ZONE area. */
2081 #define RED_ZONE_SIZE 128
2082 /* Reserved area of the red zone for temporaries. */
2083 #define RED_ZONE_RESERVE 8
2090 extern enum asm_dialect ix86_asm_dialect;
2091 extern unsigned int ix86_preferred_stack_boundary;
2092 extern unsigned int ix86_incoming_stack_boundary;
2093 extern int ix86_branch_cost, ix86_section_threshold;
2095 /* Smallest class containing REGNO. */
2096 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2098 enum ix86_fpcmp_strategy {
2104 /* To properly truncate FP values into integers, we need to set i387 control
2105 word. We can't emit proper mode switching code before reload, as spills
2106 generated by reload may truncate values incorrectly, but we still can avoid
2107 redundant computation of new control word by the mode switching pass.
2108 The fldcw instructions are still emitted redundantly, but this is probably
2109 not going to be noticeable problem, as most CPUs do have fast path for
2112 The machinery is to emit simple truncation instructions and split them
2113 before reload to instructions having USEs of two memory locations that
2114 are filled by this code to old and new control word.
2116 Post-reload pass may be later used to eliminate the redundant fildcw if
2128 enum ix86_stack_slot
2137 MAX_386_STACK_LOCALS
2140 /* Define this macro if the port needs extra instructions inserted
2141 for mode switching in an optimizing compilation. */
2143 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2144 ix86_optimize_mode_switching[(ENTITY)]
2146 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2147 initializer for an array of integers. Each initializer element N
2148 refers to an entity that needs mode switching, and specifies the
2149 number of different modes that might need to be set for this
2150 entity. The position of the initializer in the initializer -
2151 starting counting at zero - determines the integer that is used to
2152 refer to the mode-switched entity in question. */
2154 #define NUM_MODES_FOR_MODE_SWITCHING \
2155 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2157 /* ENTITY is an integer specifying a mode-switched entity. If
2158 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2159 return an integer value not larger than the corresponding element
2160 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2161 must be switched into prior to the execution of INSN. */
2163 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2165 /* This macro specifies the order in which modes for ENTITY are
2166 processed. 0 is the highest priority. */
2168 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2170 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2171 is the set of hard registers live at the point where the insn(s)
2172 are to be inserted. */
2174 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2175 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2176 ? emit_i387_cw_initialization (MODE), 0 \
2180 /* Avoid renaming of stack registers, as doing so in combination with
2181 scheduling just increases amount of live registers at time and in
2182 the turn amount of fxch instructions needed.
2184 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2186 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2187 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2190 #define FASTCALL_PREFIX '@'
2192 /* Machine specific frame tracking during prologue/epilogue generation. */
2194 #ifndef USED_FOR_TARGET
2195 struct GTY(()) machine_frame_state
2197 /* This pair tracks the currently active CFA as reg+offset. When reg
2198 is drap_reg, we don't bother trying to record here the real CFA when
2199 it might really be a DW_CFA_def_cfa_expression. */
2201 HOST_WIDE_INT cfa_offset;
2203 /* The current offset (canonically from the CFA) of ESP and EBP.
2204 When stack frame re-alignment is active, these may not be relative
2205 to the CFA. However, in all cases they are relative to the offsets
2206 of the saved registers stored in ix86_frame. */
2207 HOST_WIDE_INT sp_offset;
2208 HOST_WIDE_INT fp_offset;
2210 /* The size of the red-zone that may be assumed for the purposes of
2211 eliding register restore notes in the epilogue. This may be zero
2212 if no red-zone is in effect, or may be reduced from the real
2213 red-zone value by a maximum runtime stack re-alignment value. */
2214 int red_zone_offset;
2216 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2217 value within the frame. If false then the offset above should be
2218 ignored. Note that DRAP, if valid, *always* points to the CFA and
2219 thus has an offset of zero. */
2220 BOOL_BITFIELD sp_valid : 1;
2221 BOOL_BITFIELD fp_valid : 1;
2222 BOOL_BITFIELD drap_valid : 1;
2224 /* Indicate whether the local stack frame has been re-aligned. When
2225 set, the SP/FP offsets above are relative to the aligned frame
2227 BOOL_BITFIELD realigned : 1;
2230 /* Private to winnt.c. */
2231 struct seh_frame_state;
2233 struct GTY(()) machine_function {
2234 struct stack_local_entry *stack_locals;
2235 const char *some_ld_name;
2236 int varargs_gpr_size;
2237 int varargs_fpr_size;
2238 int optimize_mode_switching[MAX_386_ENTITIES];
2240 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
2241 has been computed for. */
2242 int use_fast_prologue_epilogue_nregs;
2244 /* For -fsplit-stack support: A stack local which holds a pointer to
2245 the stack arguments for a function with a variable number of
2246 arguments. This is set at the start of the function and is used
2247 to initialize the overflow_arg_area field of the va_list
2249 rtx split_stack_varargs_pointer;
2251 /* This value is used for amd64 targets and specifies the current abi
2252 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2253 ENUM_BITFIELD(calling_abi) call_abi : 8;
2255 /* Nonzero if the function accesses a previous frame. */
2256 BOOL_BITFIELD accesses_prev_frame : 1;
2258 /* Nonzero if the function requires a CLD in the prologue. */
2259 BOOL_BITFIELD needs_cld : 1;
2261 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2262 expander to determine the style used. */
2263 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2265 /* If true, the current function needs the default PIC register, not
2266 an alternate register (on x86) and must not use the red zone (on
2267 x86_64), even if it's a leaf function. We don't want the
2268 function to be regarded as non-leaf because TLS calls need not
2269 affect register allocation. This flag is set when a TLS call
2270 instruction is expanded within a function, and never reset, even
2271 if all such instructions are optimized away. Use the
2272 ix86_current_function_calls_tls_descriptor macro for a better
2274 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2276 /* If true, the current function has a STATIC_CHAIN is placed on the
2277 stack below the return address. */
2278 BOOL_BITFIELD static_chain_on_stack : 1;
2280 /* Nonzero if caller passes 256bit AVX modes. */
2281 BOOL_BITFIELD caller_pass_avx256_p : 1;
2283 /* Nonzero if caller returns 256bit AVX modes. */
2284 BOOL_BITFIELD caller_return_avx256_p : 1;
2286 /* Nonzero if the current callee passes 256bit AVX modes. */
2287 BOOL_BITFIELD callee_pass_avx256_p : 1;
2289 /* Nonzero if the current callee returns 256bit AVX modes. */
2290 BOOL_BITFIELD callee_return_avx256_p : 1;
2292 /* Nonzero if rescan vzerouppers in the current function is needed. */
2293 BOOL_BITFIELD rescan_vzeroupper_p : 1;
2295 /* During prologue/epilogue generation, the current frame state.
2296 Otherwise, the frame state at the end of the prologue. */
2297 struct machine_frame_state fs;
2299 /* During SEH output, this is non-null. */
2300 struct seh_frame_state * GTY((skip(""))) seh;
2304 #define ix86_stack_locals (cfun->machine->stack_locals)
2305 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2306 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2307 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2308 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2309 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2310 (cfun->machine->tls_descriptor_call_expanded_p)
2311 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2312 calls are optimized away, we try to detect cases in which it was
2313 optimized away. Since such instructions (use (reg REG_SP)), we can
2314 verify whether there's any such instruction live by testing that
2316 #define ix86_current_function_calls_tls_descriptor \
2317 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2318 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2320 /* Control behavior of x86_file_start. */
2321 #define X86_FILE_START_VERSION_DIRECTIVE false
2322 #define X86_FILE_START_FLTUSED false
2324 /* Flag to mark data that is in the large address area. */
2325 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2326 #define SYMBOL_REF_FAR_ADDR_P(X) \
2327 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2329 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2330 have defined always, to avoid ifdefing. */
2331 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2332 #define SYMBOL_REF_DLLIMPORT_P(X) \
2333 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2335 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2336 #define SYMBOL_REF_DLLEXPORT_P(X) \
2337 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2339 extern void debug_ready_dispatch (void);
2340 extern void debug_dispatch_window (int);
2342 /* The value at zero is only defined for the BMI instructions
2343 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2344 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2345 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
2346 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2347 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
2350 /* Flags returned by ix86_get_callcvt (). */
2351 #define IX86_CALLCVT_CDECL 0x1
2352 #define IX86_CALLCVT_STDCALL 0x2
2353 #define IX86_CALLCVT_FASTCALL 0x4
2354 #define IX86_CALLCVT_THISCALL 0x8
2355 #define IX86_CALLCVT_REGPARM 0x10
2356 #define IX86_CALLCVT_SSEREGPARM 0x20
2358 #define IX86_BASE_CALLCVT(FLAGS) \
2359 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2360 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))