1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 static int const x86_64_int_parameter_registers[6] =
1538 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1539 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1542 static int const x86_64_ms_abi_int_parameter_registers[4] =
1544 2 /*RCX*/, 1 /*RDX*/,
1545 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1548 static int const x86_64_int_return_registers[4] =
1550 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1553 /* The "default" register map used in 64bit mode. */
1554 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1556 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1557 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1558 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1559 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1560 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1561 8,9,10,11,12,13,14,15, /* extended integer registers */
1562 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1565 /* Define the register numbers to be used in Dwarf debugging information.
1566 The SVR4 reference port C compiler uses the following register numbers
1567 in its Dwarf output code:
1568 0 for %eax (gcc regno = 0)
1569 1 for %ecx (gcc regno = 2)
1570 2 for %edx (gcc regno = 1)
1571 3 for %ebx (gcc regno = 3)
1572 4 for %esp (gcc regno = 7)
1573 5 for %ebp (gcc regno = 6)
1574 6 for %esi (gcc regno = 4)
1575 7 for %edi (gcc regno = 5)
1576 The following three DWARF register numbers are never generated by
1577 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1578 believes these numbers have these meanings.
1579 8 for %eip (no gcc equivalent)
1580 9 for %eflags (gcc regno = 17)
1581 10 for %trapno (no gcc equivalent)
1582 It is not at all clear how we should number the FP stack registers
1583 for the x86 architecture. If the version of SDB on x86/svr4 were
1584 a bit less brain dead with respect to floating-point then we would
1585 have a precedent to follow with respect to DWARF register numbers
1586 for x86 FP registers, but the SDB on x86/svr4 is so completely
1587 broken with respect to FP registers that it is hardly worth thinking
1588 of it as something to strive for compatibility with.
1589 The version of x86/svr4 SDB I have at the moment does (partially)
1590 seem to believe that DWARF register number 11 is associated with
1591 the x86 register %st(0), but that's about all. Higher DWARF
1592 register numbers don't seem to be associated with anything in
1593 particular, and even for DWARF regno 11, SDB only seems to under-
1594 stand that it should say that a variable lives in %st(0) (when
1595 asked via an `=' command) if we said it was in DWARF regno 11,
1596 but SDB still prints garbage when asked for the value of the
1597 variable in question (via a `/' command).
1598 (Also note that the labels SDB prints for various FP stack regs
1599 when doing an `x' command are all wrong.)
1600 Note that these problems generally don't affect the native SVR4
1601 C compiler because it doesn't allow the use of -O with -g and
1602 because when it is *not* optimizing, it allocates a memory
1603 location for each floating-point variable, and the memory
1604 location is what gets described in the DWARF AT_location
1605 attribute for the variable in question.
1606 Regardless of the severe mental illness of the x86/svr4 SDB, we
1607 do something sensible here and we use the following DWARF
1608 register numbers. Note that these are all stack-top-relative
1610 11 for %st(0) (gcc regno = 8)
1611 12 for %st(1) (gcc regno = 9)
1612 13 for %st(2) (gcc regno = 10)
1613 14 for %st(3) (gcc regno = 11)
1614 15 for %st(4) (gcc regno = 12)
1615 16 for %st(5) (gcc regno = 13)
1616 17 for %st(6) (gcc regno = 14)
1617 18 for %st(7) (gcc regno = 15)
1619 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1621 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1622 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1623 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1624 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1625 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1626 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1627 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1630 /* Test and compare insns in i386.md store the information needed to
1631 generate branch and scc insns here. */
1633 rtx ix86_compare_op0 = NULL_RTX;
1634 rtx ix86_compare_op1 = NULL_RTX;
1635 rtx ix86_compare_emitted = NULL_RTX;
1637 /* Define the structure for the machine field in struct function. */
1639 struct stack_local_entry GTY(())
1641 unsigned short mode;
1644 struct stack_local_entry *next;
1647 /* Structure describing stack frame layout.
1648 Stack grows downward:
1654 saved frame pointer if frame_pointer_needed
1655 <- HARD_FRAME_POINTER
1664 [va_arg registers] (
1665 > to_allocate <- FRAME_POINTER
1677 HOST_WIDE_INT frame;
1679 int outgoing_arguments_size;
1682 HOST_WIDE_INT to_allocate;
1683 /* The offsets relative to ARG_POINTER. */
1684 HOST_WIDE_INT frame_pointer_offset;
1685 HOST_WIDE_INT hard_frame_pointer_offset;
1686 HOST_WIDE_INT stack_pointer_offset;
1688 /* When save_regs_using_mov is set, emit prologue using
1689 move instead of push instructions. */
1690 bool save_regs_using_mov;
1693 /* Code model option. */
1694 enum cmodel ix86_cmodel;
1696 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1698 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1700 /* Which unit we are generating floating point math for. */
1701 enum fpmath_unit ix86_fpmath;
1703 /* Which cpu are we scheduling for. */
1704 enum attr_cpu ix86_schedule;
1706 /* Which cpu are we optimizing for. */
1707 enum processor_type ix86_tune;
1709 /* Which instruction set architecture to use. */
1710 enum processor_type ix86_arch;
1712 /* true if sse prefetch instruction is not NOOP. */
1713 int x86_prefetch_sse;
1715 /* ix86_regparm_string as a number */
1716 static int ix86_regparm;
1718 /* -mstackrealign option */
1719 extern int ix86_force_align_arg_pointer;
1720 static const char ix86_force_align_arg_pointer_string[]
1721 = "force_align_arg_pointer";
1723 static rtx (*ix86_gen_leave) (void);
1724 static rtx (*ix86_gen_pop1) (rtx);
1725 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1726 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1728 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1729 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1730 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1732 /* Preferred alignment for stack boundary in bits. */
1733 unsigned int ix86_preferred_stack_boundary;
1735 /* Alignment for incoming stack boundary in bits specified at
1737 static unsigned int ix86_user_incoming_stack_boundary;
1739 /* Default alignment for incoming stack boundary in bits. */
1740 static unsigned int ix86_default_incoming_stack_boundary;
1742 /* Alignment for incoming stack boundary in bits. */
1743 unsigned int ix86_incoming_stack_boundary;
1745 /* Values 1-5: see jump.c */
1746 int ix86_branch_cost;
1748 /* Calling abi specific va_list type nodes. */
1749 static GTY(()) tree sysv_va_list_type_node;
1750 static GTY(()) tree ms_va_list_type_node;
1752 /* Variables which are this size or smaller are put in the data/bss
1753 or ldata/lbss sections. */
1755 int ix86_section_threshold = 65536;
1757 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1758 char internal_label_prefix[16];
1759 int internal_label_prefix_len;
1761 /* Fence to use after loop using movnt. */
1764 /* Register class used for passing given 64bit part of the argument.
1765 These represent classes as documented by the PS ABI, with the exception
1766 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1767 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1769 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1770 whenever possible (upper half does contain padding). */
1771 enum x86_64_reg_class
1774 X86_64_INTEGER_CLASS,
1775 X86_64_INTEGERSI_CLASS,
1782 X86_64_COMPLEX_X87_CLASS,
1786 #define MAX_CLASSES 4
1788 /* Table of constants used by fldpi, fldln2, etc.... */
1789 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1790 static bool ext_80387_constants_init = 0;
1793 static struct machine_function * ix86_init_machine_status (void);
1794 static rtx ix86_function_value (const_tree, const_tree, bool);
1795 static int ix86_function_regparm (const_tree, const_tree);
1796 static void ix86_compute_frame_layout (struct ix86_frame *);
1797 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1799 static void ix86_add_new_builtins (int);
1801 enum ix86_function_specific_strings
1803 IX86_FUNCTION_SPECIFIC_ARCH,
1804 IX86_FUNCTION_SPECIFIC_TUNE,
1805 IX86_FUNCTION_SPECIFIC_FPMATH,
1806 IX86_FUNCTION_SPECIFIC_MAX
1809 static char *ix86_target_string (int, int, const char *, const char *,
1810 const char *, bool);
1811 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1812 static void ix86_function_specific_save (struct cl_target_option *);
1813 static void ix86_function_specific_restore (struct cl_target_option *);
1814 static void ix86_function_specific_print (FILE *, int,
1815 struct cl_target_option *);
1816 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1817 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1818 static bool ix86_can_inline_p (tree, tree);
1819 static void ix86_set_current_function (tree);
1822 /* The svr4 ABI for the i386 says that records and unions are returned
1824 #ifndef DEFAULT_PCC_STRUCT_RETURN
1825 #define DEFAULT_PCC_STRUCT_RETURN 1
1828 /* Whether -mtune= or -march= were specified */
1829 static int ix86_tune_defaulted;
1830 static int ix86_arch_specified;
1832 /* Bit flags that specify the ISA we are compiling for. */
1833 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1835 /* A mask of ix86_isa_flags that includes bit X if X
1836 was set or cleared on the command line. */
1837 static int ix86_isa_flags_explicit;
1839 /* Define a set of ISAs which are available when a given ISA is
1840 enabled. MMX and SSE ISAs are handled separately. */
1842 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1843 #define OPTION_MASK_ISA_3DNOW_SET \
1844 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1846 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1847 #define OPTION_MASK_ISA_SSE2_SET \
1848 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1849 #define OPTION_MASK_ISA_SSE3_SET \
1850 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1851 #define OPTION_MASK_ISA_SSSE3_SET \
1852 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1853 #define OPTION_MASK_ISA_SSE4_1_SET \
1854 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1855 #define OPTION_MASK_ISA_SSE4_2_SET \
1856 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1857 #define OPTION_MASK_ISA_AVX_SET \
1858 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1859 #define OPTION_MASK_ISA_FMA_SET \
1860 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1862 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1864 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1866 #define OPTION_MASK_ISA_SSE4A_SET \
1867 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1868 #define OPTION_MASK_ISA_SSE5_SET \
1869 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1871 /* AES and PCLMUL need SSE2 because they use xmm registers */
1872 #define OPTION_MASK_ISA_AES_SET \
1873 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1874 #define OPTION_MASK_ISA_PCLMUL_SET \
1875 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1877 #define OPTION_MASK_ISA_ABM_SET \
1878 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1879 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1880 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1881 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1883 /* Define a set of ISAs which aren't available when a given ISA is
1884 disabled. MMX and SSE ISAs are handled separately. */
1886 #define OPTION_MASK_ISA_MMX_UNSET \
1887 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1888 #define OPTION_MASK_ISA_3DNOW_UNSET \
1889 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1890 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1892 #define OPTION_MASK_ISA_SSE_UNSET \
1893 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1894 #define OPTION_MASK_ISA_SSE2_UNSET \
1895 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1896 #define OPTION_MASK_ISA_SSE3_UNSET \
1897 (OPTION_MASK_ISA_SSE3 \
1898 | OPTION_MASK_ISA_SSSE3_UNSET \
1899 | OPTION_MASK_ISA_SSE4A_UNSET )
1900 #define OPTION_MASK_ISA_SSSE3_UNSET \
1901 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1902 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1903 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1904 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1905 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1906 #define OPTION_MASK_ISA_AVX_UNSET \
1907 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1908 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1910 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1912 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1914 #define OPTION_MASK_ISA_SSE4A_UNSET \
1915 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1916 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1917 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1918 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1919 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1920 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1921 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1922 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1924 /* Vectorization library interface and handlers. */
1925 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1926 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1927 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1929 /* Processor target table, indexed by processor number */
1932 const struct processor_costs *cost; /* Processor costs */
1933 const int align_loop; /* Default alignments. */
1934 const int align_loop_max_skip;
1935 const int align_jump;
1936 const int align_jump_max_skip;
1937 const int align_func;
1940 static const struct ptt processor_target_table[PROCESSOR_max] =
1942 {&i386_cost, 4, 3, 4, 3, 4},
1943 {&i486_cost, 16, 15, 16, 15, 16},
1944 {&pentium_cost, 16, 7, 16, 7, 16},
1945 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1946 {&geode_cost, 0, 0, 0, 0, 0},
1947 {&k6_cost, 32, 7, 32, 7, 32},
1948 {&athlon_cost, 16, 7, 16, 7, 16},
1949 {&pentium4_cost, 0, 0, 0, 0, 0},
1950 {&k8_cost, 16, 7, 16, 7, 16},
1951 {&nocona_cost, 0, 0, 0, 0, 0},
1952 {&core2_cost, 16, 10, 16, 10, 16},
1953 {&generic32_cost, 16, 7, 16, 7, 16},
1954 {&generic64_cost, 16, 10, 16, 10, 16},
1955 {&amdfam10_cost, 32, 24, 32, 7, 32}
1958 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1983 /* Implement TARGET_HANDLE_OPTION. */
1986 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1993 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1994 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1998 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1999 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2006 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2007 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2011 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2012 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2022 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2023 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2027 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2028 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2035 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2036 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2040 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2041 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2048 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2049 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2053 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2054 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2061 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2062 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2066 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2067 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2074 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2075 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2079 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2080 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2087 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2088 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2092 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2093 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2100 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2101 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2105 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2106 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2113 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2114 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2118 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2119 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2124 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2125 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2129 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2130 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2136 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2141 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2149 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2154 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2162 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2167 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2175 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2180 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2188 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2193 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2201 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2206 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2207 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2214 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2219 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2220 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2227 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2228 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2232 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2233 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2242 /* Return a string the documents the current -m options. The caller is
2243 responsible for freeing the string. */
2246 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2247 const char *fpmath, bool add_nl_p)
2249 struct ix86_target_opts
2251 const char *option; /* option string */
2252 int mask; /* isa mask options */
2255 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2256 preceding options while match those first. */
2257 static struct ix86_target_opts isa_opts[] =
2259 { "-m64", OPTION_MASK_ISA_64BIT },
2260 { "-msse5", OPTION_MASK_ISA_SSE5 },
2261 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2262 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2263 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2264 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2265 { "-msse3", OPTION_MASK_ISA_SSE3 },
2266 { "-msse2", OPTION_MASK_ISA_SSE2 },
2267 { "-msse", OPTION_MASK_ISA_SSE },
2268 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2269 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2270 { "-mmmx", OPTION_MASK_ISA_MMX },
2271 { "-mabm", OPTION_MASK_ISA_ABM },
2272 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2273 { "-maes", OPTION_MASK_ISA_AES },
2274 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2278 static struct ix86_target_opts flag_opts[] =
2280 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2281 { "-m80387", MASK_80387 },
2282 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2283 { "-malign-double", MASK_ALIGN_DOUBLE },
2284 { "-mcld", MASK_CLD },
2285 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2286 { "-mieee-fp", MASK_IEEE_FP },
2287 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2288 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2289 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2290 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2291 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2292 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2293 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2294 { "-mno-red-zone", MASK_NO_RED_ZONE },
2295 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2296 { "-mrecip", MASK_RECIP },
2297 { "-mrtd", MASK_RTD },
2298 { "-msseregparm", MASK_SSEREGPARM },
2299 { "-mstack-arg-probe", MASK_STACK_PROBE },
2300 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2303 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2306 char target_other[40];
2315 memset (opts, '\0', sizeof (opts));
2317 /* Add -march= option. */
2320 opts[num][0] = "-march=";
2321 opts[num++][1] = arch;
2324 /* Add -mtune= option. */
2327 opts[num][0] = "-mtune=";
2328 opts[num++][1] = tune;
2331 /* Pick out the options in isa options. */
2332 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2334 if ((isa & isa_opts[i].mask) != 0)
2336 opts[num++][0] = isa_opts[i].option;
2337 isa &= ~ isa_opts[i].mask;
2341 if (isa && add_nl_p)
2343 opts[num++][0] = isa_other;
2344 sprintf (isa_other, "(other isa: 0x%x)", isa);
2347 /* Add flag options. */
2348 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2350 if ((flags & flag_opts[i].mask) != 0)
2352 opts[num++][0] = flag_opts[i].option;
2353 flags &= ~ flag_opts[i].mask;
2357 if (flags && add_nl_p)
2359 opts[num++][0] = target_other;
2360 sprintf (target_other, "(other flags: 0x%x)", isa);
2363 /* Add -fpmath= option. */
2366 opts[num][0] = "-mfpmath=";
2367 opts[num++][1] = fpmath;
2374 gcc_assert (num < ARRAY_SIZE (opts));
2376 /* Size the string. */
2378 sep_len = (add_nl_p) ? 3 : 1;
2379 for (i = 0; i < num; i++)
2382 for (j = 0; j < 2; j++)
2384 len += strlen (opts[i][j]);
2387 /* Build the string. */
2388 ret = ptr = (char *) xmalloc (len);
2391 for (i = 0; i < num; i++)
2395 for (j = 0; j < 2; j++)
2396 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2403 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2411 for (j = 0; j < 2; j++)
2414 memcpy (ptr, opts[i][j], len2[j]);
2416 line_len += len2[j];
2421 gcc_assert (ret + len >= ptr);
2426 /* Function that is callable from the debugger to print the current
2429 ix86_debug_options (void)
2431 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2432 ix86_arch_string, ix86_tune_string,
2433 ix86_fpmath_string, true);
2437 fprintf (stderr, "%s\n\n", opts);
2441 fprintf (stderr, "<no options>\n\n");
2446 /* Sometimes certain combinations of command options do not make
2447 sense on a particular target machine. You can define a macro
2448 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2449 defined, is executed once just after all the command options have
2452 Don't use this macro to turn on various extra optimizations for
2453 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2456 override_options (bool main_args_p)
2459 unsigned int ix86_arch_mask, ix86_tune_mask;
2464 /* Comes from final.c -- no real reason to change it. */
2465 #define MAX_CODE_ALIGN 16
2473 PTA_PREFETCH_SSE = 1 << 4,
2475 PTA_3DNOW_A = 1 << 6,
2479 PTA_POPCNT = 1 << 10,
2481 PTA_SSE4A = 1 << 12,
2482 PTA_NO_SAHF = 1 << 13,
2483 PTA_SSE4_1 = 1 << 14,
2484 PTA_SSE4_2 = 1 << 15,
2487 PTA_PCLMUL = 1 << 18,
2494 const char *const name; /* processor name or nickname. */
2495 const enum processor_type processor;
2496 const enum attr_cpu schedule;
2497 const unsigned /*enum pta_flags*/ flags;
2499 const processor_alias_table[] =
2501 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2502 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2503 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2504 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2505 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2506 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2507 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2508 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2509 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2510 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2511 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2512 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2513 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2515 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2517 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2518 PTA_MMX | PTA_SSE | PTA_SSE2},
2519 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2520 PTA_MMX |PTA_SSE | PTA_SSE2},
2521 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2522 PTA_MMX | PTA_SSE | PTA_SSE2},
2523 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2524 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2525 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2526 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2527 | PTA_CX16 | PTA_NO_SAHF},
2528 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2529 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2530 | PTA_SSSE3 | PTA_CX16},
2531 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2532 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2533 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2534 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2535 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2536 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2537 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2538 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2539 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2540 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2541 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2542 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2543 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2544 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2545 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2546 {"x86-64", PROCESSOR_K8, CPU_K8,
2547 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2548 {"k8", PROCESSOR_K8, CPU_K8,
2549 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2550 | PTA_SSE2 | PTA_NO_SAHF},
2551 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2552 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2553 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2554 {"opteron", PROCESSOR_K8, CPU_K8,
2555 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2556 | PTA_SSE2 | PTA_NO_SAHF},
2557 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2558 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2559 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2560 {"athlon64", PROCESSOR_K8, CPU_K8,
2561 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2562 | PTA_SSE2 | PTA_NO_SAHF},
2563 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2564 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2565 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2566 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2567 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2568 | PTA_SSE2 | PTA_NO_SAHF},
2569 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2570 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2571 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2572 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2573 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2574 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2575 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2576 0 /* flags are only used for -march switch. */ },
2577 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2578 PTA_64BIT /* flags are only used for -march switch. */ },
2581 int const pta_size = ARRAY_SIZE (processor_alias_table);
2583 /* Set up prefix/suffix so the error messages refer to either the command
2584 line argument, or the attribute(target). */
2593 prefix = "option(\"";
2598 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2599 SUBTARGET_OVERRIDE_OPTIONS;
2602 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2603 SUBSUBTARGET_OVERRIDE_OPTIONS;
2606 /* -fPIC is the default for x86_64. */
2607 if (TARGET_MACHO && TARGET_64BIT)
2610 /* Set the default values for switches whose default depends on TARGET_64BIT
2611 in case they weren't overwritten by command line options. */
2614 /* Mach-O doesn't support omitting the frame pointer for now. */
2615 if (flag_omit_frame_pointer == 2)
2616 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2617 if (flag_asynchronous_unwind_tables == 2)
2618 flag_asynchronous_unwind_tables = 1;
2619 if (flag_pcc_struct_return == 2)
2620 flag_pcc_struct_return = 0;
2624 if (flag_omit_frame_pointer == 2)
2625 flag_omit_frame_pointer = 0;
2626 if (flag_asynchronous_unwind_tables == 2)
2627 flag_asynchronous_unwind_tables = 0;
2628 if (flag_pcc_struct_return == 2)
2629 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2632 /* Need to check -mtune=generic first. */
2633 if (ix86_tune_string)
2635 if (!strcmp (ix86_tune_string, "generic")
2636 || !strcmp (ix86_tune_string, "i686")
2637 /* As special support for cross compilers we read -mtune=native
2638 as -mtune=generic. With native compilers we won't see the
2639 -mtune=native, as it was changed by the driver. */
2640 || !strcmp (ix86_tune_string, "native"))
2643 ix86_tune_string = "generic64";
2645 ix86_tune_string = "generic32";
2647 /* If this call is for setting the option attribute, allow the
2648 generic32/generic64 that was previously set. */
2649 else if (!main_args_p
2650 && (!strcmp (ix86_tune_string, "generic32")
2651 || !strcmp (ix86_tune_string, "generic64")))
2653 else if (!strncmp (ix86_tune_string, "generic", 7))
2654 error ("bad value (%s) for %stune=%s %s",
2655 ix86_tune_string, prefix, suffix, sw);
2659 if (ix86_arch_string)
2660 ix86_tune_string = ix86_arch_string;
2661 if (!ix86_tune_string)
2663 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2664 ix86_tune_defaulted = 1;
2667 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2668 need to use a sensible tune option. */
2669 if (!strcmp (ix86_tune_string, "generic")
2670 || !strcmp (ix86_tune_string, "x86-64")
2671 || !strcmp (ix86_tune_string, "i686"))
2674 ix86_tune_string = "generic64";
2676 ix86_tune_string = "generic32";
2679 if (ix86_stringop_string)
2681 if (!strcmp (ix86_stringop_string, "rep_byte"))
2682 stringop_alg = rep_prefix_1_byte;
2683 else if (!strcmp (ix86_stringop_string, "libcall"))
2684 stringop_alg = libcall;
2685 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2686 stringop_alg = rep_prefix_4_byte;
2687 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2689 /* rep; movq isn't available in 32-bit code. */
2690 stringop_alg = rep_prefix_8_byte;
2691 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2692 stringop_alg = loop_1_byte;
2693 else if (!strcmp (ix86_stringop_string, "loop"))
2694 stringop_alg = loop;
2695 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2696 stringop_alg = unrolled_loop;
2698 error ("bad value (%s) for %sstringop-strategy=%s %s",
2699 ix86_stringop_string, prefix, suffix, sw);
2701 if (!strcmp (ix86_tune_string, "x86-64"))
2702 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2703 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2704 prefix, suffix, prefix, suffix, prefix, suffix);
2706 if (!ix86_arch_string)
2707 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2709 ix86_arch_specified = 1;
2711 if (!strcmp (ix86_arch_string, "generic"))
2712 error ("generic CPU can be used only for %stune=%s %s",
2713 prefix, suffix, sw);
2714 if (!strncmp (ix86_arch_string, "generic", 7))
2715 error ("bad value (%s) for %sarch=%s %s",
2716 ix86_arch_string, prefix, suffix, sw);
2718 if (ix86_cmodel_string != 0)
2720 if (!strcmp (ix86_cmodel_string, "small"))
2721 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2722 else if (!strcmp (ix86_cmodel_string, "medium"))
2723 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2724 else if (!strcmp (ix86_cmodel_string, "large"))
2725 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2727 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2728 else if (!strcmp (ix86_cmodel_string, "32"))
2729 ix86_cmodel = CM_32;
2730 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2731 ix86_cmodel = CM_KERNEL;
2733 error ("bad value (%s) for %scmodel=%s %s",
2734 ix86_cmodel_string, prefix, suffix, sw);
2738 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2739 use of rip-relative addressing. This eliminates fixups that
2740 would otherwise be needed if this object is to be placed in a
2741 DLL, and is essentially just as efficient as direct addressing. */
2742 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2743 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2744 else if (TARGET_64BIT)
2745 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2747 ix86_cmodel = CM_32;
2749 if (ix86_asm_string != 0)
2752 && !strcmp (ix86_asm_string, "intel"))
2753 ix86_asm_dialect = ASM_INTEL;
2754 else if (!strcmp (ix86_asm_string, "att"))
2755 ix86_asm_dialect = ASM_ATT;
2757 error ("bad value (%s) for %sasm=%s %s",
2758 ix86_asm_string, prefix, suffix, sw);
2760 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2761 error ("code model %qs not supported in the %s bit mode",
2762 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2763 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2764 sorry ("%i-bit mode not compiled in",
2765 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2767 for (i = 0; i < pta_size; i++)
2768 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2770 ix86_schedule = processor_alias_table[i].schedule;
2771 ix86_arch = processor_alias_table[i].processor;
2772 /* Default cpu tuning to the architecture. */
2773 ix86_tune = ix86_arch;
2775 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2776 error ("CPU you selected does not support x86-64 "
2779 if (processor_alias_table[i].flags & PTA_MMX
2780 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2781 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2782 if (processor_alias_table[i].flags & PTA_3DNOW
2783 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2784 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2785 if (processor_alias_table[i].flags & PTA_3DNOW_A
2786 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2787 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2788 if (processor_alias_table[i].flags & PTA_SSE
2789 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2790 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2791 if (processor_alias_table[i].flags & PTA_SSE2
2792 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2793 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2794 if (processor_alias_table[i].flags & PTA_SSE3
2795 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2796 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2797 if (processor_alias_table[i].flags & PTA_SSSE3
2798 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2799 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2800 if (processor_alias_table[i].flags & PTA_SSE4_1
2801 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2802 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2803 if (processor_alias_table[i].flags & PTA_SSE4_2
2804 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2805 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2806 if (processor_alias_table[i].flags & PTA_AVX
2807 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2808 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2809 if (processor_alias_table[i].flags & PTA_FMA
2810 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2811 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2812 if (processor_alias_table[i].flags & PTA_SSE4A
2813 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2814 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2815 if (processor_alias_table[i].flags & PTA_SSE5
2816 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2817 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2818 if (processor_alias_table[i].flags & PTA_ABM
2819 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2820 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2821 if (processor_alias_table[i].flags & PTA_CX16
2822 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2823 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2824 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2825 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2826 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2827 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2828 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2829 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2830 if (processor_alias_table[i].flags & PTA_AES
2831 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2832 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2833 if (processor_alias_table[i].flags & PTA_PCLMUL
2834 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2835 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2836 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2837 x86_prefetch_sse = true;
2843 error ("bad value (%s) for %sarch=%s %s",
2844 ix86_arch_string, prefix, suffix, sw);
2846 ix86_arch_mask = 1u << ix86_arch;
2847 for (i = 0; i < X86_ARCH_LAST; ++i)
2848 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2850 for (i = 0; i < pta_size; i++)
2851 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2853 ix86_schedule = processor_alias_table[i].schedule;
2854 ix86_tune = processor_alias_table[i].processor;
2855 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2857 if (ix86_tune_defaulted)
2859 ix86_tune_string = "x86-64";
2860 for (i = 0; i < pta_size; i++)
2861 if (! strcmp (ix86_tune_string,
2862 processor_alias_table[i].name))
2864 ix86_schedule = processor_alias_table[i].schedule;
2865 ix86_tune = processor_alias_table[i].processor;
2868 error ("CPU you selected does not support x86-64 "
2871 /* Intel CPUs have always interpreted SSE prefetch instructions as
2872 NOPs; so, we can enable SSE prefetch instructions even when
2873 -mtune (rather than -march) points us to a processor that has them.
2874 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2875 higher processors. */
2877 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2878 x86_prefetch_sse = true;
2882 error ("bad value (%s) for %stune=%s %s",
2883 ix86_tune_string, prefix, suffix, sw);
2885 ix86_tune_mask = 1u << ix86_tune;
2886 for (i = 0; i < X86_TUNE_LAST; ++i)
2887 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2890 ix86_cost = &ix86_size_cost;
2892 ix86_cost = processor_target_table[ix86_tune].cost;
2894 /* Arrange to set up i386_stack_locals for all functions. */
2895 init_machine_status = ix86_init_machine_status;
2897 /* Validate -mregparm= value. */
2898 if (ix86_regparm_string)
2901 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2902 i = atoi (ix86_regparm_string);
2903 if (i < 0 || i > REGPARM_MAX)
2904 error ("%sregparm=%d%s is not between 0 and %d",
2905 prefix, i, suffix, REGPARM_MAX);
2910 ix86_regparm = REGPARM_MAX;
2912 /* If the user has provided any of the -malign-* options,
2913 warn and use that value only if -falign-* is not set.
2914 Remove this code in GCC 3.2 or later. */
2915 if (ix86_align_loops_string)
2917 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2918 prefix, suffix, suffix);
2919 if (align_loops == 0)
2921 i = atoi (ix86_align_loops_string);
2922 if (i < 0 || i > MAX_CODE_ALIGN)
2923 error ("%salign-loops=%d%s is not between 0 and %d",
2924 prefix, i, suffix, MAX_CODE_ALIGN);
2926 align_loops = 1 << i;
2930 if (ix86_align_jumps_string)
2932 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2933 prefix, suffix, suffix);
2934 if (align_jumps == 0)
2936 i = atoi (ix86_align_jumps_string);
2937 if (i < 0 || i > MAX_CODE_ALIGN)
2938 error ("%salign-loops=%d%s is not between 0 and %d",
2939 prefix, i, suffix, MAX_CODE_ALIGN);
2941 align_jumps = 1 << i;
2945 if (ix86_align_funcs_string)
2947 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2948 prefix, suffix, suffix);
2949 if (align_functions == 0)
2951 i = atoi (ix86_align_funcs_string);
2952 if (i < 0 || i > MAX_CODE_ALIGN)
2953 error ("%salign-loops=%d%s is not between 0 and %d",
2954 prefix, i, suffix, MAX_CODE_ALIGN);
2956 align_functions = 1 << i;
2960 /* Default align_* from the processor table. */
2961 if (align_loops == 0)
2963 align_loops = processor_target_table[ix86_tune].align_loop;
2964 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2966 if (align_jumps == 0)
2968 align_jumps = processor_target_table[ix86_tune].align_jump;
2969 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2971 if (align_functions == 0)
2973 align_functions = processor_target_table[ix86_tune].align_func;
2976 /* Validate -mbranch-cost= value, or provide default. */
2977 ix86_branch_cost = ix86_cost->branch_cost;
2978 if (ix86_branch_cost_string)
2980 i = atoi (ix86_branch_cost_string);
2982 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2984 ix86_branch_cost = i;
2986 if (ix86_section_threshold_string)
2988 i = atoi (ix86_section_threshold_string);
2990 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2992 ix86_section_threshold = i;
2995 if (ix86_tls_dialect_string)
2997 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2998 ix86_tls_dialect = TLS_DIALECT_GNU;
2999 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3000 ix86_tls_dialect = TLS_DIALECT_GNU2;
3001 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3002 ix86_tls_dialect = TLS_DIALECT_SUN;
3004 error ("bad value (%s) for %stls-dialect=%s %s",
3005 ix86_tls_dialect_string, prefix, suffix, sw);
3008 if (ix87_precision_string)
3010 i = atoi (ix87_precision_string);
3011 if (i != 32 && i != 64 && i != 80)
3012 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3017 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3019 /* Enable by default the SSE and MMX builtins. Do allow the user to
3020 explicitly disable any of these. In particular, disabling SSE and
3021 MMX for kernel code is extremely useful. */
3022 if (!ix86_arch_specified)
3024 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3025 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3028 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3032 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3034 if (!ix86_arch_specified)
3036 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3038 /* i386 ABI does not specify red zone. It still makes sense to use it
3039 when programmer takes care to stack from being destroyed. */
3040 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3041 target_flags |= MASK_NO_RED_ZONE;
3044 /* Keep nonleaf frame pointers. */
3045 if (flag_omit_frame_pointer)
3046 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3047 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3048 flag_omit_frame_pointer = 1;
3050 /* If we're doing fast math, we don't care about comparison order
3051 wrt NaNs. This lets us use a shorter comparison sequence. */
3052 if (flag_finite_math_only)
3053 target_flags &= ~MASK_IEEE_FP;
3055 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3056 since the insns won't need emulation. */
3057 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3058 target_flags &= ~MASK_NO_FANCY_MATH_387;
3060 /* Likewise, if the target doesn't have a 387, or we've specified
3061 software floating point, don't use 387 inline intrinsics. */
3063 target_flags |= MASK_NO_FANCY_MATH_387;
3065 /* Turn on MMX builtins for -msse. */
3068 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3069 x86_prefetch_sse = true;
3072 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3073 if (TARGET_SSE4_2 || TARGET_ABM)
3074 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3076 /* Validate -mpreferred-stack-boundary= value or default it to
3077 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3078 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3079 if (ix86_preferred_stack_boundary_string)
3081 i = atoi (ix86_preferred_stack_boundary_string);
3082 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3083 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3084 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3086 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3089 /* Set the default value for -mstackrealign. */
3090 if (ix86_force_align_arg_pointer == -1)
3091 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3093 /* Validate -mincoming-stack-boundary= value or default it to
3094 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3095 if (ix86_force_align_arg_pointer)
3096 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3098 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3099 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3100 if (ix86_incoming_stack_boundary_string)
3102 i = atoi (ix86_incoming_stack_boundary_string);
3103 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3104 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3105 i, TARGET_64BIT ? 4 : 2);
3108 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3109 ix86_incoming_stack_boundary
3110 = ix86_user_incoming_stack_boundary;
3114 /* Accept -msseregparm only if at least SSE support is enabled. */
3115 if (TARGET_SSEREGPARM
3117 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3119 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3120 if (ix86_fpmath_string != 0)
3122 if (! strcmp (ix86_fpmath_string, "387"))
3123 ix86_fpmath = FPMATH_387;
3124 else if (! strcmp (ix86_fpmath_string, "sse"))
3128 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3129 ix86_fpmath = FPMATH_387;
3132 ix86_fpmath = FPMATH_SSE;
3134 else if (! strcmp (ix86_fpmath_string, "387,sse")
3135 || ! strcmp (ix86_fpmath_string, "387+sse")
3136 || ! strcmp (ix86_fpmath_string, "sse,387")
3137 || ! strcmp (ix86_fpmath_string, "sse+387")
3138 || ! strcmp (ix86_fpmath_string, "both"))
3142 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3143 ix86_fpmath = FPMATH_387;
3145 else if (!TARGET_80387)
3147 warning (0, "387 instruction set disabled, using SSE arithmetics");
3148 ix86_fpmath = FPMATH_SSE;
3151 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3154 error ("bad value (%s) for %sfpmath=%s %s",
3155 ix86_fpmath_string, prefix, suffix, sw);
3158 /* If the i387 is disabled, then do not return values in it. */
3160 target_flags &= ~MASK_FLOAT_RETURNS;
3162 /* Use external vectorized library in vectorizing intrinsics. */
3163 if (ix86_veclibabi_string)
3165 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3166 ix86_veclib_handler = ix86_veclibabi_svml;
3167 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3168 ix86_veclib_handler = ix86_veclibabi_acml;
3170 error ("unknown vectorization library ABI type (%s) for "
3171 "%sveclibabi=%s %s", ix86_veclibabi_string,
3172 prefix, suffix, sw);
3175 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3176 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3178 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3180 /* ??? Unwind info is not correct around the CFG unless either a frame
3181 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3182 unwind info generation to be aware of the CFG and propagating states
3184 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3185 || flag_exceptions || flag_non_call_exceptions)
3186 && flag_omit_frame_pointer
3187 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3189 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3190 warning (0, "unwind tables currently require either a frame pointer "
3191 "or %saccumulate-outgoing-args%s for correctness",
3193 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3196 /* If stack probes are required, the space used for large function
3197 arguments on the stack must also be probed, so enable
3198 -maccumulate-outgoing-args so this happens in the prologue. */
3199 if (TARGET_STACK_PROBE
3200 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3202 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3203 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3204 "for correctness", prefix, suffix);
3205 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3208 /* For sane SSE instruction set generation we need fcomi instruction.
3209 It is safe to enable all CMOVE instructions. */
3213 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3216 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3217 p = strchr (internal_label_prefix, 'X');
3218 internal_label_prefix_len = p - internal_label_prefix;
3222 /* When scheduling description is not available, disable scheduler pass
3223 so it won't slow down the compilation and make x87 code slower. */
3224 if (!TARGET_SCHEDULE)
3225 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3227 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3228 set_param_value ("simultaneous-prefetches",
3229 ix86_cost->simultaneous_prefetches);
3230 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3231 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3232 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3233 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3234 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3235 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3237 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3238 can be optimized to ap = __builtin_next_arg (0). */
3240 targetm.expand_builtin_va_start = NULL;
3244 ix86_gen_leave = gen_leave_rex64;
3245 ix86_gen_pop1 = gen_popdi1;
3246 ix86_gen_add3 = gen_adddi3;
3247 ix86_gen_sub3 = gen_subdi3;
3248 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3249 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3250 ix86_gen_monitor = gen_sse3_monitor64;
3251 ix86_gen_andsp = gen_anddi3;
3255 ix86_gen_leave = gen_leave;
3256 ix86_gen_pop1 = gen_popsi1;
3257 ix86_gen_add3 = gen_addsi3;
3258 ix86_gen_sub3 = gen_subsi3;
3259 ix86_gen_sub3_carry = gen_subsi3_carry;
3260 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3261 ix86_gen_monitor = gen_sse3_monitor;
3262 ix86_gen_andsp = gen_andsi3;
3266 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3268 target_flags |= MASK_CLD & ~target_flags_explicit;
3271 /* Save the initial options in case the user does function specific options */
3273 target_option_default_node = target_option_current_node
3274 = build_target_option_node ();
3277 /* Save the current options */
3280 ix86_function_specific_save (struct cl_target_option *ptr)
3282 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3283 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3284 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3285 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3286 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3288 ptr->arch = ix86_arch;
3289 ptr->schedule = ix86_schedule;
3290 ptr->tune = ix86_tune;
3291 ptr->fpmath = ix86_fpmath;
3292 ptr->branch_cost = ix86_branch_cost;
3293 ptr->tune_defaulted = ix86_tune_defaulted;
3294 ptr->arch_specified = ix86_arch_specified;
3295 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3296 ptr->target_flags_explicit = target_flags_explicit;
3299 /* Restore the current options */
3302 ix86_function_specific_restore (struct cl_target_option *ptr)
3304 enum processor_type old_tune = ix86_tune;
3305 enum processor_type old_arch = ix86_arch;
3306 unsigned int ix86_arch_mask, ix86_tune_mask;
3309 ix86_arch = ptr->arch;
3310 ix86_schedule = ptr->schedule;
3311 ix86_tune = ptr->tune;
3312 ix86_fpmath = ptr->fpmath;
3313 ix86_branch_cost = ptr->branch_cost;
3314 ix86_tune_defaulted = ptr->tune_defaulted;
3315 ix86_arch_specified = ptr->arch_specified;
3316 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3317 target_flags_explicit = ptr->target_flags_explicit;
3319 /* Recreate the arch feature tests if the arch changed */
3320 if (old_arch != ix86_arch)
3322 ix86_arch_mask = 1u << ix86_arch;
3323 for (i = 0; i < X86_ARCH_LAST; ++i)
3324 ix86_arch_features[i]
3325 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3328 /* Recreate the tune optimization tests */
3329 if (old_tune != ix86_tune)
3331 ix86_tune_mask = 1u << ix86_tune;
3332 for (i = 0; i < X86_TUNE_LAST; ++i)
3333 ix86_tune_features[i]
3334 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3338 /* Print the current options */
3341 ix86_function_specific_print (FILE *file, int indent,
3342 struct cl_target_option *ptr)
3345 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3346 NULL, NULL, NULL, false);
3348 fprintf (file, "%*sarch = %d (%s)\n",
3351 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3352 ? cpu_names[ptr->arch]
3355 fprintf (file, "%*stune = %d (%s)\n",
3358 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3359 ? cpu_names[ptr->tune]
3362 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3363 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3364 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3365 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3369 fprintf (file, "%*s%s\n", indent, "", target_string);
3370 free (target_string);
3375 /* Inner function to process the attribute((target(...))), take an argument and
3376 set the current options from the argument. If we have a list, recursively go
3380 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3385 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3386 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3387 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3388 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3403 enum ix86_opt_type type;
3408 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3409 IX86_ATTR_ISA ("abm", OPT_mabm),
3410 IX86_ATTR_ISA ("aes", OPT_maes),
3411 IX86_ATTR_ISA ("avx", OPT_mavx),
3412 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3413 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3414 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3415 IX86_ATTR_ISA ("sse", OPT_msse),
3416 IX86_ATTR_ISA ("sse2", OPT_msse2),
3417 IX86_ATTR_ISA ("sse3", OPT_msse3),
3418 IX86_ATTR_ISA ("sse4", OPT_msse4),
3419 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3420 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3421 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3422 IX86_ATTR_ISA ("sse5", OPT_msse5),
3423 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3425 /* string options */
3426 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3427 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3428 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3431 IX86_ATTR_YES ("cld",
3435 IX86_ATTR_NO ("fancy-math-387",
3436 OPT_mfancy_math_387,
3437 MASK_NO_FANCY_MATH_387),
3439 IX86_ATTR_NO ("fused-madd",
3441 MASK_NO_FUSED_MADD),
3443 IX86_ATTR_YES ("ieee-fp",
3447 IX86_ATTR_YES ("inline-all-stringops",
3448 OPT_minline_all_stringops,
3449 MASK_INLINE_ALL_STRINGOPS),
3451 IX86_ATTR_YES ("inline-stringops-dynamically",
3452 OPT_minline_stringops_dynamically,
3453 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3455 IX86_ATTR_NO ("align-stringops",
3456 OPT_mno_align_stringops,
3457 MASK_NO_ALIGN_STRINGOPS),
3459 IX86_ATTR_YES ("recip",
3465 /* If this is a list, recurse to get the options. */
3466 if (TREE_CODE (args) == TREE_LIST)
3470 for (; args; args = TREE_CHAIN (args))
3471 if (TREE_VALUE (args)
3472 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3478 else if (TREE_CODE (args) != STRING_CST)
3481 /* Handle multiple arguments separated by commas. */
3482 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3484 while (next_optstr && *next_optstr != '\0')
3486 char *p = next_optstr;
3488 char *comma = strchr (next_optstr, ',');
3489 const char *opt_string;
3490 size_t len, opt_len;
3495 enum ix86_opt_type type = ix86_opt_unknown;
3501 len = comma - next_optstr;
3502 next_optstr = comma + 1;
3510 /* Recognize no-xxx. */
3511 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3520 /* Find the option. */
3523 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3525 type = attrs[i].type;
3526 opt_len = attrs[i].len;
3527 if (ch == attrs[i].string[0]
3528 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3529 && memcmp (p, attrs[i].string, opt_len) == 0)
3532 mask = attrs[i].mask;
3533 opt_string = attrs[i].string;
3538 /* Process the option. */
3541 error ("attribute(target(\"%s\")) is unknown", orig_p);
3545 else if (type == ix86_opt_isa)
3546 ix86_handle_option (opt, p, opt_set_p);
3548 else if (type == ix86_opt_yes || type == ix86_opt_no)
3550 if (type == ix86_opt_no)
3551 opt_set_p = !opt_set_p;
3554 target_flags |= mask;
3556 target_flags &= ~mask;
3559 else if (type == ix86_opt_str)
3563 error ("option(\"%s\") was already specified", opt_string);
3567 p_strings[opt] = xstrdup (p + opt_len);
3577 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3580 ix86_valid_target_attribute_tree (tree args)
3582 const char *orig_arch_string = ix86_arch_string;
3583 const char *orig_tune_string = ix86_tune_string;
3584 const char *orig_fpmath_string = ix86_fpmath_string;
3585 int orig_tune_defaulted = ix86_tune_defaulted;
3586 int orig_arch_specified = ix86_arch_specified;
3587 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3590 struct cl_target_option *def
3591 = TREE_TARGET_OPTION (target_option_default_node);
3593 /* Process each of the options on the chain. */
3594 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3597 /* If the changed options are different from the default, rerun override_options,
3598 and then save the options away. The string options are are attribute options,
3599 and will be undone when we copy the save structure. */
3600 if (ix86_isa_flags != def->ix86_isa_flags
3601 || target_flags != def->target_flags
3602 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3603 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3604 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3606 /* If we are using the default tune= or arch=, undo the string assigned,
3607 and use the default. */
3608 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3609 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3610 else if (!orig_arch_specified)
3611 ix86_arch_string = NULL;
3613 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3614 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3615 else if (orig_tune_defaulted)
3616 ix86_tune_string = NULL;
3618 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3619 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3620 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3621 else if (!TARGET_64BIT && TARGET_SSE)
3622 ix86_fpmath_string = "sse,387";
3624 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3625 override_options (false);
3627 /* Add any builtin functions with the new isa if any. */
3628 ix86_add_new_builtins (ix86_isa_flags);
3630 /* Save the current options unless we are validating options for
3632 t = build_target_option_node ();
3634 ix86_arch_string = orig_arch_string;
3635 ix86_tune_string = orig_tune_string;
3636 ix86_fpmath_string = orig_fpmath_string;
3638 /* Free up memory allocated to hold the strings */
3639 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3640 if (option_strings[i])
3641 free (option_strings[i]);
3647 /* Hook to validate attribute((target("string"))). */
3650 ix86_valid_target_attribute_p (tree fndecl,
3651 tree ARG_UNUSED (name),
3653 int ARG_UNUSED (flags))
3655 struct cl_target_option cur_target;
3657 tree old_optimize = build_optimization_node ();
3658 tree new_target, new_optimize;
3659 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3661 /* If the function changed the optimization levels as well as setting target
3662 options, start with the optimizations specified. */
3663 if (func_optimize && func_optimize != old_optimize)
3664 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3666 /* The target attributes may also change some optimization flags, so update
3667 the optimization options if necessary. */
3668 cl_target_option_save (&cur_target);
3669 new_target = ix86_valid_target_attribute_tree (args);
3670 new_optimize = build_optimization_node ();
3677 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3679 if (old_optimize != new_optimize)
3680 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3683 cl_target_option_restore (&cur_target);
3685 if (old_optimize != new_optimize)
3686 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3692 /* Hook to determine if one function can safely inline another. */
3695 ix86_can_inline_p (tree caller, tree callee)
3698 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3699 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3701 /* If callee has no option attributes, then it is ok to inline. */
3705 /* If caller has no option attributes, but callee does then it is not ok to
3707 else if (!caller_tree)
3712 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3713 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3715 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3716 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3718 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3719 != callee_opts->ix86_isa_flags)
3722 /* See if we have the same non-isa options. */
3723 else if (caller_opts->target_flags != callee_opts->target_flags)
3726 /* See if arch, tune, etc. are the same. */
3727 else if (caller_opts->arch != callee_opts->arch)
3730 else if (caller_opts->tune != callee_opts->tune)
3733 else if (caller_opts->fpmath != callee_opts->fpmath)
3736 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3747 /* Remember the last target of ix86_set_current_function. */
3748 static GTY(()) tree ix86_previous_fndecl;
3750 /* Establish appropriate back-end context for processing the function
3751 FNDECL. The argument might be NULL to indicate processing at top
3752 level, outside of any function scope. */
3754 ix86_set_current_function (tree fndecl)
3756 /* Only change the context if the function changes. This hook is called
3757 several times in the course of compiling a function, and we don't want to
3758 slow things down too much or call target_reinit when it isn't safe. */
3759 if (fndecl && fndecl != ix86_previous_fndecl)
3761 tree old_tree = (ix86_previous_fndecl
3762 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3765 tree new_tree = (fndecl
3766 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3769 ix86_previous_fndecl = fndecl;
3770 if (old_tree == new_tree)
3775 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3781 struct cl_target_option *def
3782 = TREE_TARGET_OPTION (target_option_current_node);
3784 cl_target_option_restore (def);
3791 /* Return true if this goes in large data/bss. */
3794 ix86_in_large_data_p (tree exp)
3796 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3799 /* Functions are never large data. */
3800 if (TREE_CODE (exp) == FUNCTION_DECL)
3803 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3805 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3806 if (strcmp (section, ".ldata") == 0
3807 || strcmp (section, ".lbss") == 0)
3813 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3815 /* If this is an incomplete type with size 0, then we can't put it
3816 in data because it might be too big when completed. */
3817 if (!size || size > ix86_section_threshold)
3824 /* Switch to the appropriate section for output of DECL.
3825 DECL is either a `VAR_DECL' node or a constant of some sort.
3826 RELOC indicates whether forming the initial value of DECL requires
3827 link-time relocations. */
3829 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3833 x86_64_elf_select_section (tree decl, int reloc,
3834 unsigned HOST_WIDE_INT align)
3836 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3837 && ix86_in_large_data_p (decl))
3839 const char *sname = NULL;
3840 unsigned int flags = SECTION_WRITE;
3841 switch (categorize_decl_for_section (decl, reloc))
3846 case SECCAT_DATA_REL:
3847 sname = ".ldata.rel";
3849 case SECCAT_DATA_REL_LOCAL:
3850 sname = ".ldata.rel.local";
3852 case SECCAT_DATA_REL_RO:
3853 sname = ".ldata.rel.ro";
3855 case SECCAT_DATA_REL_RO_LOCAL:
3856 sname = ".ldata.rel.ro.local";
3860 flags |= SECTION_BSS;
3863 case SECCAT_RODATA_MERGE_STR:
3864 case SECCAT_RODATA_MERGE_STR_INIT:
3865 case SECCAT_RODATA_MERGE_CONST:
3869 case SECCAT_SRODATA:
3876 /* We don't split these for medium model. Place them into
3877 default sections and hope for best. */
3879 case SECCAT_EMUTLS_VAR:
3880 case SECCAT_EMUTLS_TMPL:
3885 /* We might get called with string constants, but get_named_section
3886 doesn't like them as they are not DECLs. Also, we need to set
3887 flags in that case. */
3889 return get_section (sname, flags, NULL);
3890 return get_named_section (decl, sname, reloc);
3893 return default_elf_select_section (decl, reloc, align);
3896 /* Build up a unique section name, expressed as a
3897 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3898 RELOC indicates whether the initial value of EXP requires
3899 link-time relocations. */
3901 static void ATTRIBUTE_UNUSED
3902 x86_64_elf_unique_section (tree decl, int reloc)
3904 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3905 && ix86_in_large_data_p (decl))
3907 const char *prefix = NULL;
3908 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3909 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3911 switch (categorize_decl_for_section (decl, reloc))
3914 case SECCAT_DATA_REL:
3915 case SECCAT_DATA_REL_LOCAL:
3916 case SECCAT_DATA_REL_RO:
3917 case SECCAT_DATA_REL_RO_LOCAL:
3918 prefix = one_only ? ".ld" : ".ldata";
3921 prefix = one_only ? ".lb" : ".lbss";
3924 case SECCAT_RODATA_MERGE_STR:
3925 case SECCAT_RODATA_MERGE_STR_INIT:
3926 case SECCAT_RODATA_MERGE_CONST:
3927 prefix = one_only ? ".lr" : ".lrodata";
3929 case SECCAT_SRODATA:
3936 /* We don't split these for medium model. Place them into
3937 default sections and hope for best. */
3939 case SECCAT_EMUTLS_VAR:
3940 prefix = targetm.emutls.var_section;
3942 case SECCAT_EMUTLS_TMPL:
3943 prefix = targetm.emutls.tmpl_section;
3948 const char *name, *linkonce;
3951 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3952 name = targetm.strip_name_encoding (name);
3954 /* If we're using one_only, then there needs to be a .gnu.linkonce
3955 prefix to the section name. */
3956 linkonce = one_only ? ".gnu.linkonce" : "";
3958 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3960 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3964 default_unique_section (decl, reloc);
3967 #ifdef COMMON_ASM_OP
3968 /* This says how to output assembler code to declare an
3969 uninitialized external linkage data object.
3971 For medium model x86-64 we need to use .largecomm opcode for
3974 x86_elf_aligned_common (FILE *file,
3975 const char *name, unsigned HOST_WIDE_INT size,
3978 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3979 && size > (unsigned int)ix86_section_threshold)
3980 fprintf (file, ".largecomm\t");
3982 fprintf (file, "%s", COMMON_ASM_OP);
3983 assemble_name (file, name);
3984 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
3985 size, align / BITS_PER_UNIT);
3989 /* Utility function for targets to use in implementing
3990 ASM_OUTPUT_ALIGNED_BSS. */
3993 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
3994 const char *name, unsigned HOST_WIDE_INT size,
3997 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3998 && size > (unsigned int)ix86_section_threshold)
3999 switch_to_section (get_named_section (decl, ".lbss", 0));
4001 switch_to_section (bss_section);
4002 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4003 #ifdef ASM_DECLARE_OBJECT_NAME
4004 last_assemble_variable_decl = decl;
4005 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4007 /* Standard thing is just output label for the object. */
4008 ASM_OUTPUT_LABEL (file, name);
4009 #endif /* ASM_DECLARE_OBJECT_NAME */
4010 ASM_OUTPUT_SKIP (file, size ? size : 1);
4014 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4016 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4017 make the problem with not enough registers even worse. */
4018 #ifdef INSN_SCHEDULING
4020 flag_schedule_insns = 0;
4024 /* The Darwin libraries never set errno, so we might as well
4025 avoid calling them when that's the only reason we would. */
4026 flag_errno_math = 0;
4028 /* The default values of these switches depend on the TARGET_64BIT
4029 that is not known at this moment. Mark these values with 2 and
4030 let user the to override these. In case there is no command line option
4031 specifying them, we will set the defaults in override_options. */
4033 flag_omit_frame_pointer = 2;
4034 flag_pcc_struct_return = 2;
4035 flag_asynchronous_unwind_tables = 2;
4036 flag_vect_cost_model = 1;
4037 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4038 SUBTARGET_OPTIMIZATION_OPTIONS;
4042 /* Decide whether we can make a sibling call to a function. DECL is the
4043 declaration of the function being targeted by the call and EXP is the
4044 CALL_EXPR representing the call. */
4047 ix86_function_ok_for_sibcall (tree decl, tree exp)
4052 /* If we are generating position-independent code, we cannot sibcall
4053 optimize any indirect call, or a direct call to a global function,
4054 as the PLT requires %ebx be live. */
4055 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4062 func = TREE_TYPE (CALL_EXPR_FN (exp));
4063 if (POINTER_TYPE_P (func))
4064 func = TREE_TYPE (func);
4067 /* Check that the return value locations are the same. Like
4068 if we are returning floats on the 80387 register stack, we cannot
4069 make a sibcall from a function that doesn't return a float to a
4070 function that does or, conversely, from a function that does return
4071 a float to a function that doesn't; the necessary stack adjustment
4072 would not be executed. This is also the place we notice
4073 differences in the return value ABI. Note that it is ok for one
4074 of the functions to have void return type as long as the return
4075 value of the other is passed in a register. */
4076 a = ix86_function_value (TREE_TYPE (exp), func, false);
4077 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4079 if (STACK_REG_P (a) || STACK_REG_P (b))
4081 if (!rtx_equal_p (a, b))
4084 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4086 else if (!rtx_equal_p (a, b))
4089 /* If this call is indirect, we'll need to be able to use a call-clobbered
4090 register for the address of the target function. Make sure that all
4091 such registers are not used for passing parameters. */
4092 if (!decl && !TARGET_64BIT)
4096 /* We're looking at the CALL_EXPR, we need the type of the function. */
4097 type = CALL_EXPR_FN (exp); /* pointer expression */
4098 type = TREE_TYPE (type); /* pointer type */
4099 type = TREE_TYPE (type); /* function type */
4101 if (ix86_function_regparm (type, NULL) >= 3)
4103 /* ??? Need to count the actual number of registers to be used,
4104 not the possible number of registers. Fix later. */
4109 /* Dllimport'd functions are also called indirectly. */
4110 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4112 && decl && DECL_DLLIMPORT_P (decl)
4113 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4116 /* If we need to align the outgoing stack, then sibcalling would
4117 unalign the stack, which may break the called function. */
4118 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4121 /* Otherwise okay. That also includes certain types of indirect calls. */
4125 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4126 calling convention attributes;
4127 arguments as in struct attribute_spec.handler. */
4130 ix86_handle_cconv_attribute (tree *node, tree name,
4132 int flags ATTRIBUTE_UNUSED,
4135 if (TREE_CODE (*node) != FUNCTION_TYPE
4136 && TREE_CODE (*node) != METHOD_TYPE
4137 && TREE_CODE (*node) != FIELD_DECL
4138 && TREE_CODE (*node) != TYPE_DECL)
4140 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4141 IDENTIFIER_POINTER (name));
4142 *no_add_attrs = true;
4146 /* Can combine regparm with all attributes but fastcall. */
4147 if (is_attribute_p ("regparm", name))
4151 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4153 error ("fastcall and regparm attributes are not compatible");
4156 cst = TREE_VALUE (args);
4157 if (TREE_CODE (cst) != INTEGER_CST)
4159 warning (OPT_Wattributes,
4160 "%qs attribute requires an integer constant argument",
4161 IDENTIFIER_POINTER (name));
4162 *no_add_attrs = true;
4164 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4166 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4167 IDENTIFIER_POINTER (name), REGPARM_MAX);
4168 *no_add_attrs = true;
4176 /* Do not warn when emulating the MS ABI. */
4177 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4178 warning (OPT_Wattributes, "%qs attribute ignored",
4179 IDENTIFIER_POINTER (name));
4180 *no_add_attrs = true;
4184 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4185 if (is_attribute_p ("fastcall", name))
4187 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4189 error ("fastcall and cdecl attributes are not compatible");
4191 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4193 error ("fastcall and stdcall attributes are not compatible");
4195 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4197 error ("fastcall and regparm attributes are not compatible");
4201 /* Can combine stdcall with fastcall (redundant), regparm and
4203 else if (is_attribute_p ("stdcall", name))
4205 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4207 error ("stdcall and cdecl attributes are not compatible");
4209 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4211 error ("stdcall and fastcall attributes are not compatible");
4215 /* Can combine cdecl with regparm and sseregparm. */
4216 else if (is_attribute_p ("cdecl", name))
4218 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4220 error ("stdcall and cdecl attributes are not compatible");
4222 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4224 error ("fastcall and cdecl attributes are not compatible");
4228 /* Can combine sseregparm with all attributes. */
4233 /* Return 0 if the attributes for two types are incompatible, 1 if they
4234 are compatible, and 2 if they are nearly compatible (which causes a
4235 warning to be generated). */
4238 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4240 /* Check for mismatch of non-default calling convention. */
4241 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4243 if (TREE_CODE (type1) != FUNCTION_TYPE
4244 && TREE_CODE (type1) != METHOD_TYPE)
4247 /* Check for mismatched fastcall/regparm types. */
4248 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4249 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4250 || (ix86_function_regparm (type1, NULL)
4251 != ix86_function_regparm (type2, NULL)))
4254 /* Check for mismatched sseregparm types. */
4255 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4256 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4259 /* Check for mismatched return types (cdecl vs stdcall). */
4260 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4261 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4267 /* Return the regparm value for a function with the indicated TYPE and DECL.
4268 DECL may be NULL when calling function indirectly
4269 or considering a libcall. */
4272 ix86_function_regparm (const_tree type, const_tree decl)
4275 int regparm = ix86_regparm;
4277 static bool error_issued;
4281 if (ix86_function_type_abi (type) == DEFAULT_ABI)
4283 return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
4286 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4290 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4292 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4294 /* We can't use regparm(3) for nested functions because
4295 these pass static chain pointer in %ecx register. */
4296 if (!error_issued && regparm == 3
4297 && decl_function_context (decl)
4298 && !DECL_NO_STATIC_CHAIN (decl))
4300 error ("nested functions are limited to 2 register parameters");
4301 error_issued = true;
4309 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4312 /* Use register calling convention for local functions when possible. */
4313 if (decl && TREE_CODE (decl) == FUNCTION_DECL
4316 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4317 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4320 int local_regparm, globals = 0, regno;
4323 /* Make sure no regparm register is taken by a
4324 fixed register variable. */
4325 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4326 if (fixed_regs[local_regparm])
4329 /* We can't use regparm(3) for nested functions as these use
4330 static chain pointer in third argument. */
4331 if (local_regparm == 3
4332 && decl_function_context (decl)
4333 && !DECL_NO_STATIC_CHAIN (decl))
4336 /* If the function realigns its stackpointer, the prologue will
4337 clobber %ecx. If we've already generated code for the callee,
4338 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4339 scanning the attributes for the self-realigning property. */
4340 f = DECL_STRUCT_FUNCTION (decl);
4341 /* Since current internal arg pointer won't conflict with
4342 parameter passing regs, so no need to change stack
4343 realignment and adjust regparm number.
4345 Each fixed register usage increases register pressure,
4346 so less registers should be used for argument passing.
4347 This functionality can be overriden by an explicit
4349 for (regno = 0; regno <= DI_REG; regno++)
4350 if (fixed_regs[regno])
4354 = globals < local_regparm ? local_regparm - globals : 0;
4356 if (local_regparm > regparm)
4357 regparm = local_regparm;
4364 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4365 DFmode (2) arguments in SSE registers for a function with the
4366 indicated TYPE and DECL. DECL may be NULL when calling function
4367 indirectly or considering a libcall. Otherwise return 0. */
4370 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4372 gcc_assert (!TARGET_64BIT);
4374 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4375 by the sseregparm attribute. */
4376 if (TARGET_SSEREGPARM
4377 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4384 error ("Calling %qD with attribute sseregparm without "
4385 "SSE/SSE2 enabled", decl);
4387 error ("Calling %qT with attribute sseregparm without "
4388 "SSE/SSE2 enabled", type);
4396 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4397 (and DFmode for SSE2) arguments in SSE registers. */
4398 if (decl && TARGET_SSE_MATH && !profile_flag)
4400 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4401 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4403 return TARGET_SSE2 ? 2 : 1;
4409 /* Return true if EAX is live at the start of the function. Used by
4410 ix86_expand_prologue to determine if we need special help before
4411 calling allocate_stack_worker. */
4414 ix86_eax_live_at_start_p (void)
4416 /* Cheat. Don't bother working forward from ix86_function_regparm
4417 to the function type to whether an actual argument is located in
4418 eax. Instead just look at cfg info, which is still close enough
4419 to correct at this point. This gives false positives for broken
4420 functions that might use uninitialized data that happens to be
4421 allocated in eax, but who cares? */
4422 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4425 /* Value is the number of bytes of arguments automatically
4426 popped when returning from a subroutine call.
4427 FUNDECL is the declaration node of the function (as a tree),
4428 FUNTYPE is the data type of the function (as a tree),
4429 or for a library call it is an identifier node for the subroutine name.
4430 SIZE is the number of bytes of arguments passed on the stack.
4432 On the 80386, the RTD insn may be used to pop them if the number
4433 of args is fixed, but if the number is variable then the caller
4434 must pop them all. RTD can't be used for library calls now
4435 because the library is compiled with the Unix compiler.
4436 Use of RTD is a selectable option, since it is incompatible with
4437 standard Unix calling sequences. If the option is not selected,
4438 the caller must always pop the args.
4440 The attribute stdcall is equivalent to RTD on a per module basis. */
4443 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4447 /* None of the 64-bit ABIs pop arguments. */
4451 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4453 /* Cdecl functions override -mrtd, and never pop the stack. */
4454 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4456 /* Stdcall and fastcall functions will pop the stack if not
4458 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4459 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4462 if (rtd && ! stdarg_p (funtype))
4466 /* Lose any fake structure return argument if it is passed on the stack. */
4467 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4468 && !KEEP_AGGREGATE_RETURN_POINTER)
4470 int nregs = ix86_function_regparm (funtype, fundecl);
4472 return GET_MODE_SIZE (Pmode);
4478 /* Argument support functions. */
4480 /* Return true when register may be used to pass function parameters. */
4482 ix86_function_arg_regno_p (int regno)
4485 const int *parm_regs;
4490 return (regno < REGPARM_MAX
4491 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4493 return (regno < REGPARM_MAX
4494 || (TARGET_MMX && MMX_REGNO_P (regno)
4495 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4496 || (TARGET_SSE && SSE_REGNO_P (regno)
4497 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4502 if (SSE_REGNO_P (regno) && TARGET_SSE)
4507 if (TARGET_SSE && SSE_REGNO_P (regno)
4508 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4512 /* TODO: The function should depend on current function ABI but
4513 builtins.c would need updating then. Therefore we use the
4516 /* RAX is used as hidden argument to va_arg functions. */
4517 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4520 if (DEFAULT_ABI == MS_ABI)
4521 parm_regs = x86_64_ms_abi_int_parameter_registers;
4523 parm_regs = x86_64_int_parameter_registers;
4524 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4525 : X86_64_REGPARM_MAX); i++)
4526 if (regno == parm_regs[i])
4531 /* Return if we do not know how to pass TYPE solely in registers. */
4534 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4536 if (must_pass_in_stack_var_size_or_pad (mode, type))
4539 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4540 The layout_type routine is crafty and tries to trick us into passing
4541 currently unsupported vector types on the stack by using TImode. */
4542 return (!TARGET_64BIT && mode == TImode
4543 && type && TREE_CODE (type) != VECTOR_TYPE);
4546 /* It returns the size, in bytes, of the area reserved for arguments passed
4547 in registers for the function represented by fndecl dependent to the used
4550 ix86_reg_parm_stack_space (const_tree fndecl)
4552 int call_abi = SYSV_ABI;
4553 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4554 call_abi = ix86_function_abi (fndecl);
4556 call_abi = ix86_function_type_abi (fndecl);
4557 if (call_abi == MS_ABI)
4562 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4565 ix86_function_type_abi (const_tree fntype)
4567 if (TARGET_64BIT && fntype != NULL)
4570 if (DEFAULT_ABI == SYSV_ABI)
4571 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4573 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4581 ix86_function_abi (const_tree fndecl)
4585 return ix86_function_type_abi (TREE_TYPE (fndecl));
4588 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4591 ix86_cfun_abi (void)
4593 if (! cfun || ! TARGET_64BIT)
4595 return cfun->machine->call_abi;
4599 extern void init_regs (void);
4601 /* Implementation of call abi switching target hook. Specific to FNDECL
4602 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4603 for more details. */
4605 ix86_call_abi_override (const_tree fndecl)
4607 if (fndecl == NULL_TREE)
4608 cfun->machine->call_abi = DEFAULT_ABI;
4610 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4613 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4614 re-initialization of init_regs each time we switch function context since
4615 this is needed only during RTL expansion. */
4617 ix86_maybe_switch_abi (void)
4620 call_used_regs[4 /*RSI*/] == (cfun->machine->call_abi == MS_ABI))
4624 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4625 for a call to a function whose data type is FNTYPE.
4626 For a library call, FNTYPE is 0. */
4629 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4630 tree fntype, /* tree ptr for function decl */
4631 rtx libname, /* SYMBOL_REF of library name or 0 */
4634 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4635 memset (cum, 0, sizeof (*cum));
4638 cum->call_abi = ix86_function_abi (fndecl);
4640 cum->call_abi = ix86_function_type_abi (fntype);
4641 /* Set up the number of registers to use for passing arguments. */
4643 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4644 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4645 cum->nregs = ix86_regparm;
4648 if (cum->call_abi != DEFAULT_ABI)
4649 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4654 cum->sse_nregs = SSE_REGPARM_MAX;
4657 if (cum->call_abi != DEFAULT_ABI)
4658 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4659 : X64_SSE_REGPARM_MAX;
4663 cum->mmx_nregs = MMX_REGPARM_MAX;
4664 cum->warn_avx = true;
4665 cum->warn_sse = true;
4666 cum->warn_mmx = true;
4668 /* Because type might mismatch in between caller and callee, we need to
4669 use actual type of function for local calls.
4670 FIXME: cgraph_analyze can be told to actually record if function uses
4671 va_start so for local functions maybe_vaarg can be made aggressive
4673 FIXME: once typesytem is fixed, we won't need this code anymore. */
4675 fntype = TREE_TYPE (fndecl);
4676 cum->maybe_vaarg = (fntype
4677 ? (!prototype_p (fntype) || stdarg_p (fntype))
4682 /* If there are variable arguments, then we won't pass anything
4683 in registers in 32-bit mode. */
4684 if (stdarg_p (fntype))
4695 /* Use ecx and edx registers if function has fastcall attribute,
4696 else look for regparm information. */
4699 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4705 cum->nregs = ix86_function_regparm (fntype, fndecl);
4708 /* Set up the number of SSE registers used for passing SFmode
4709 and DFmode arguments. Warn for mismatching ABI. */
4710 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4714 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4715 But in the case of vector types, it is some vector mode.
4717 When we have only some of our vector isa extensions enabled, then there
4718 are some modes for which vector_mode_supported_p is false. For these
4719 modes, the generic vector support in gcc will choose some non-vector mode
4720 in order to implement the type. By computing the natural mode, we'll
4721 select the proper ABI location for the operand and not depend on whatever
4722 the middle-end decides to do with these vector types.
4724 The midde-end can't deal with the vector types > 16 bytes. In this
4725 case, we return the original mode and warn ABI change if CUM isn't
4728 static enum machine_mode
4729 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4731 enum machine_mode mode = TYPE_MODE (type);
4733 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4735 HOST_WIDE_INT size = int_size_in_bytes (type);
4736 if ((size == 8 || size == 16 || size == 32)
4737 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4738 && TYPE_VECTOR_SUBPARTS (type) > 1)
4740 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4742 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4743 mode = MIN_MODE_VECTOR_FLOAT;
4745 mode = MIN_MODE_VECTOR_INT;
4747 /* Get the mode which has this inner mode and number of units. */
4748 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4749 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4750 && GET_MODE_INNER (mode) == innermode)
4752 if (size == 32 && !TARGET_AVX)
4754 static bool warnedavx;
4761 warning (0, "AVX vector argument without AVX "
4762 " enabled changes the ABI");
4764 return TYPE_MODE (type);
4777 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4778 this may not agree with the mode that the type system has chosen for the
4779 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4780 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4783 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4788 if (orig_mode != BLKmode)
4789 tmp = gen_rtx_REG (orig_mode, regno);
4792 tmp = gen_rtx_REG (mode, regno);
4793 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4794 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4800 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4801 of this code is to classify each 8bytes of incoming argument by the register
4802 class and assign registers accordingly. */
4804 /* Return the union class of CLASS1 and CLASS2.
4805 See the x86-64 PS ABI for details. */
4807 static enum x86_64_reg_class
4808 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4810 /* Rule #1: If both classes are equal, this is the resulting class. */
4811 if (class1 == class2)
4814 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4816 if (class1 == X86_64_NO_CLASS)
4818 if (class2 == X86_64_NO_CLASS)
4821 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4822 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4823 return X86_64_MEMORY_CLASS;
4825 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4826 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4827 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4828 return X86_64_INTEGERSI_CLASS;
4829 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4830 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4831 return X86_64_INTEGER_CLASS;
4833 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4835 if (class1 == X86_64_X87_CLASS
4836 || class1 == X86_64_X87UP_CLASS
4837 || class1 == X86_64_COMPLEX_X87_CLASS
4838 || class2 == X86_64_X87_CLASS
4839 || class2 == X86_64_X87UP_CLASS
4840 || class2 == X86_64_COMPLEX_X87_CLASS)
4841 return X86_64_MEMORY_CLASS;
4843 /* Rule #6: Otherwise class SSE is used. */
4844 return X86_64_SSE_CLASS;
4847 /* Classify the argument of type TYPE and mode MODE.
4848 CLASSES will be filled by the register class used to pass each word
4849 of the operand. The number of words is returned. In case the parameter
4850 should be passed in memory, 0 is returned. As a special case for zero
4851 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4853 BIT_OFFSET is used internally for handling records and specifies offset
4854 of the offset in bits modulo 256 to avoid overflow cases.
4856 See the x86-64 PS ABI for details.
4860 classify_argument (enum machine_mode mode, const_tree type,
4861 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4863 HOST_WIDE_INT bytes =
4864 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4865 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4867 /* Variable sized entities are always passed/returned in memory. */
4871 if (mode != VOIDmode
4872 && targetm.calls.must_pass_in_stack (mode, type))
4875 if (type && AGGREGATE_TYPE_P (type))
4879 enum x86_64_reg_class subclasses[MAX_CLASSES];
4881 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4885 for (i = 0; i < words; i++)
4886 classes[i] = X86_64_NO_CLASS;
4888 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4889 signalize memory class, so handle it as special case. */
4892 classes[0] = X86_64_NO_CLASS;
4896 /* Classify each field of record and merge classes. */
4897 switch (TREE_CODE (type))
4900 /* And now merge the fields of structure. */
4901 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4903 if (TREE_CODE (field) == FIELD_DECL)
4907 if (TREE_TYPE (field) == error_mark_node)
4910 /* Bitfields are always classified as integer. Handle them
4911 early, since later code would consider them to be
4912 misaligned integers. */
4913 if (DECL_BIT_FIELD (field))
4915 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4916 i < ((int_bit_position (field) + (bit_offset % 64))
4917 + tree_low_cst (DECL_SIZE (field), 0)
4920 merge_classes (X86_64_INTEGER_CLASS,
4925 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4926 TREE_TYPE (field), subclasses,
4927 (int_bit_position (field)
4928 + bit_offset) % 256);
4931 for (i = 0; i < num; i++)
4934 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4936 merge_classes (subclasses[i], classes[i + pos]);
4944 /* Arrays are handled as small records. */
4947 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4948 TREE_TYPE (type), subclasses, bit_offset);
4952 /* The partial classes are now full classes. */
4953 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4954 subclasses[0] = X86_64_SSE_CLASS;
4955 if (subclasses[0] == X86_64_INTEGERSI_CLASS
4956 && !((bit_offset % 64) == 0 && bytes == 4))
4957 subclasses[0] = X86_64_INTEGER_CLASS;
4959 for (i = 0; i < words; i++)
4960 classes[i] = subclasses[i % num];
4965 case QUAL_UNION_TYPE:
4966 /* Unions are similar to RECORD_TYPE but offset is always 0.
4968 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4970 if (TREE_CODE (field) == FIELD_DECL)
4974 if (TREE_TYPE (field) == error_mark_node)
4977 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4978 TREE_TYPE (field), subclasses,
4982 for (i = 0; i < num; i++)
4983 classes[i] = merge_classes (subclasses[i], classes[i]);
4994 /* When size > 16 bytes, if the first one isn't
4995 X86_64_SSE_CLASS or any other ones aren't
4996 X86_64_SSEUP_CLASS, everything should be passed in
4998 if (classes[0] != X86_64_SSE_CLASS)
5001 for (i = 1; i < words; i++)
5002 if (classes[i] != X86_64_SSEUP_CLASS)
5006 /* Final merger cleanup. */
5007 for (i = 0; i < words; i++)
5009 /* If one class is MEMORY, everything should be passed in
5011 if (classes[i] == X86_64_MEMORY_CLASS)
5014 /* The X86_64_SSEUP_CLASS should be always preceded by
5015 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5016 if (classes[i] == X86_64_SSEUP_CLASS
5017 && classes[i - 1] != X86_64_SSE_CLASS
5018 && classes[i - 1] != X86_64_SSEUP_CLASS)
5020 /* The first one should never be X86_64_SSEUP_CLASS. */
5021 gcc_assert (i != 0);
5022 classes[i] = X86_64_SSE_CLASS;
5025 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5026 everything should be passed in memory. */
5027 if (classes[i] == X86_64_X87UP_CLASS
5028 && (classes[i - 1] != X86_64_X87_CLASS))
5032 /* The first one should never be X86_64_X87UP_CLASS. */
5033 gcc_assert (i != 0);
5034 if (!warned && warn_psabi)
5037 inform (input_location,
5038 "The ABI of passing union with long double"
5039 " has changed in GCC 4.4");
5047 /* Compute alignment needed. We align all types to natural boundaries with
5048 exception of XFmode that is aligned to 64bits. */
5049 if (mode != VOIDmode && mode != BLKmode)
5051 int mode_alignment = GET_MODE_BITSIZE (mode);
5054 mode_alignment = 128;
5055 else if (mode == XCmode)
5056 mode_alignment = 256;
5057 if (COMPLEX_MODE_P (mode))
5058 mode_alignment /= 2;
5059 /* Misaligned fields are always returned in memory. */
5060 if (bit_offset % mode_alignment)
5064 /* for V1xx modes, just use the base mode */
5065 if (VECTOR_MODE_P (mode) && mode != V1DImode
5066 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5067 mode = GET_MODE_INNER (mode);
5069 /* Classification of atomic types. */
5074 classes[0] = X86_64_SSE_CLASS;
5077 classes[0] = X86_64_SSE_CLASS;
5078 classes[1] = X86_64_SSEUP_CLASS;
5088 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5092 classes[0] = X86_64_INTEGERSI_CLASS;
5095 else if (size <= 64)
5097 classes[0] = X86_64_INTEGER_CLASS;
5100 else if (size <= 64+32)
5102 classes[0] = X86_64_INTEGER_CLASS;
5103 classes[1] = X86_64_INTEGERSI_CLASS;
5106 else if (size <= 64+64)
5108 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5116 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5123 if (!(bit_offset % 64))
5124 classes[0] = X86_64_SSESF_CLASS;
5126 classes[0] = X86_64_SSE_CLASS;
5129 classes[0] = X86_64_SSEDF_CLASS;
5132 classes[0] = X86_64_X87_CLASS;
5133 classes[1] = X86_64_X87UP_CLASS;
5136 classes[0] = X86_64_SSE_CLASS;
5137 classes[1] = X86_64_SSEUP_CLASS;
5140 classes[0] = X86_64_SSE_CLASS;
5143 classes[0] = X86_64_SSEDF_CLASS;
5144 classes[1] = X86_64_SSEDF_CLASS;
5147 classes[0] = X86_64_COMPLEX_X87_CLASS;
5150 /* This modes is larger than 16 bytes. */
5158 classes[0] = X86_64_SSE_CLASS;
5159 classes[1] = X86_64_SSEUP_CLASS;
5160 classes[2] = X86_64_SSEUP_CLASS;
5161 classes[3] = X86_64_SSEUP_CLASS;
5169 classes[0] = X86_64_SSE_CLASS;
5170 classes[1] = X86_64_SSEUP_CLASS;
5177 classes[0] = X86_64_SSE_CLASS;
5183 gcc_assert (VECTOR_MODE_P (mode));
5188 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5190 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5191 classes[0] = X86_64_INTEGERSI_CLASS;
5193 classes[0] = X86_64_INTEGER_CLASS;
5194 classes[1] = X86_64_INTEGER_CLASS;
5195 return 1 + (bytes > 8);
5199 /* Examine the argument and return set number of register required in each
5200 class. Return 0 iff parameter should be passed in memory. */
5202 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5203 int *int_nregs, int *sse_nregs)
5205 enum x86_64_reg_class regclass[MAX_CLASSES];
5206 int n = classify_argument (mode, type, regclass, 0);
5212 for (n--; n >= 0; n--)
5213 switch (regclass[n])
5215 case X86_64_INTEGER_CLASS:
5216 case X86_64_INTEGERSI_CLASS:
5219 case X86_64_SSE_CLASS:
5220 case X86_64_SSESF_CLASS:
5221 case X86_64_SSEDF_CLASS:
5224 case X86_64_NO_CLASS:
5225 case X86_64_SSEUP_CLASS:
5227 case X86_64_X87_CLASS:
5228 case X86_64_X87UP_CLASS:
5232 case X86_64_COMPLEX_X87_CLASS:
5233 return in_return ? 2 : 0;
5234 case X86_64_MEMORY_CLASS:
5240 /* Construct container for the argument used by GCC interface. See
5241 FUNCTION_ARG for the detailed description. */
5244 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5245 const_tree type, int in_return, int nintregs, int nsseregs,
5246 const int *intreg, int sse_regno)
5248 /* The following variables hold the static issued_error state. */
5249 static bool issued_sse_arg_error;
5250 static bool issued_sse_ret_error;
5251 static bool issued_x87_ret_error;
5253 enum machine_mode tmpmode;
5255 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5256 enum x86_64_reg_class regclass[MAX_CLASSES];
5260 int needed_sseregs, needed_intregs;
5261 rtx exp[MAX_CLASSES];
5264 n = classify_argument (mode, type, regclass, 0);
5267 if (!examine_argument (mode, type, in_return, &needed_intregs,
5270 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5273 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5274 some less clueful developer tries to use floating-point anyway. */
5275 if (needed_sseregs && !TARGET_SSE)
5279 if (!issued_sse_ret_error)
5281 error ("SSE register return with SSE disabled");
5282 issued_sse_ret_error = true;
5285 else if (!issued_sse_arg_error)
5287 error ("SSE register argument with SSE disabled");
5288 issued_sse_arg_error = true;
5293 /* Likewise, error if the ABI requires us to return values in the
5294 x87 registers and the user specified -mno-80387. */
5295 if (!TARGET_80387 && in_return)
5296 for (i = 0; i < n; i++)
5297 if (regclass[i] == X86_64_X87_CLASS
5298 || regclass[i] == X86_64_X87UP_CLASS
5299 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5301 if (!issued_x87_ret_error)
5303 error ("x87 register return with x87 disabled");
5304 issued_x87_ret_error = true;
5309 /* First construct simple cases. Avoid SCmode, since we want to use
5310 single register to pass this type. */
5311 if (n == 1 && mode != SCmode)
5312 switch (regclass[0])
5314 case X86_64_INTEGER_CLASS:
5315 case X86_64_INTEGERSI_CLASS:
5316 return gen_rtx_REG (mode, intreg[0]);
5317 case X86_64_SSE_CLASS:
5318 case X86_64_SSESF_CLASS:
5319 case X86_64_SSEDF_CLASS:
5320 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5321 case X86_64_X87_CLASS:
5322 case X86_64_COMPLEX_X87_CLASS:
5323 return gen_rtx_REG (mode, FIRST_STACK_REG);
5324 case X86_64_NO_CLASS:
5325 /* Zero sized array, struct or class. */
5330 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5331 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5332 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5334 && regclass[0] == X86_64_SSE_CLASS
5335 && regclass[1] == X86_64_SSEUP_CLASS
5336 && regclass[2] == X86_64_SSEUP_CLASS
5337 && regclass[3] == X86_64_SSEUP_CLASS
5339 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5342 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5343 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5344 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5345 && regclass[1] == X86_64_INTEGER_CLASS
5346 && (mode == CDImode || mode == TImode || mode == TFmode)
5347 && intreg[0] + 1 == intreg[1])
5348 return gen_rtx_REG (mode, intreg[0]);
5350 /* Otherwise figure out the entries of the PARALLEL. */
5351 for (i = 0; i < n; i++)
5355 switch (regclass[i])
5357 case X86_64_NO_CLASS:
5359 case X86_64_INTEGER_CLASS:
5360 case X86_64_INTEGERSI_CLASS:
5361 /* Merge TImodes on aligned occasions here too. */
5362 if (i * 8 + 8 > bytes)
5363 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5364 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5368 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5369 if (tmpmode == BLKmode)
5371 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5372 gen_rtx_REG (tmpmode, *intreg),
5376 case X86_64_SSESF_CLASS:
5377 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5378 gen_rtx_REG (SFmode,
5379 SSE_REGNO (sse_regno)),
5383 case X86_64_SSEDF_CLASS:
5384 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5385 gen_rtx_REG (DFmode,
5386 SSE_REGNO (sse_regno)),
5390 case X86_64_SSE_CLASS:
5398 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5408 && regclass[1] == X86_64_SSEUP_CLASS
5409 && regclass[2] == X86_64_SSEUP_CLASS
5410 && regclass[3] == X86_64_SSEUP_CLASS);
5417 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5418 gen_rtx_REG (tmpmode,
5419 SSE_REGNO (sse_regno)),
5428 /* Empty aligned struct, union or class. */
5432 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5433 for (i = 0; i < nexps; i++)
5434 XVECEXP (ret, 0, i) = exp [i];
5438 /* Update the data in CUM to advance over an argument of mode MODE
5439 and data type TYPE. (TYPE is null for libcalls where that information
5440 may not be available.) */
5443 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5444 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5460 cum->words += words;
5461 cum->nregs -= words;
5462 cum->regno += words;
5464 if (cum->nregs <= 0)
5472 if (cum->float_in_sse < 2)
5475 if (cum->float_in_sse < 1)
5493 if (!type || !AGGREGATE_TYPE_P (type))
5495 cum->sse_words += words;
5496 cum->sse_nregs -= 1;
5497 cum->sse_regno += 1;
5498 if (cum->sse_nregs <= 0)
5511 if (!type || !AGGREGATE_TYPE_P (type))
5513 cum->mmx_words += words;
5514 cum->mmx_nregs -= 1;
5515 cum->mmx_regno += 1;
5516 if (cum->mmx_nregs <= 0)
5527 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5528 tree type, HOST_WIDE_INT words, int named)
5530 int int_nregs, sse_nregs;
5532 /* Unnamed 256bit vector mode parameters are passed on stack. */
5533 if (!named && VALID_AVX256_REG_MODE (mode))
5536 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5537 cum->words += words;
5538 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5540 cum->nregs -= int_nregs;
5541 cum->sse_nregs -= sse_nregs;
5542 cum->regno += int_nregs;
5543 cum->sse_regno += sse_nregs;
5546 cum->words += words;
5550 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5551 HOST_WIDE_INT words)
5553 /* Otherwise, this should be passed indirect. */
5554 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5556 cum->words += words;
5565 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5566 tree type, int named)
5568 HOST_WIDE_INT bytes, words;
5570 if (mode == BLKmode)
5571 bytes = int_size_in_bytes (type);
5573 bytes = GET_MODE_SIZE (mode);
5574 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5577 mode = type_natural_mode (type, NULL);
5579 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5580 function_arg_advance_ms_64 (cum, bytes, words);
5581 else if (TARGET_64BIT)
5582 function_arg_advance_64 (cum, mode, type, words, named);
5584 function_arg_advance_32 (cum, mode, type, bytes, words);
5587 /* Define where to put the arguments to a function.
5588 Value is zero to push the argument on the stack,
5589 or a hard register in which to store the argument.
5591 MODE is the argument's machine mode.
5592 TYPE is the data type of the argument (as a tree).
5593 This is null for libcalls where that information may
5595 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5596 the preceding args and about the function being called.
5597 NAMED is nonzero if this argument is a named parameter
5598 (otherwise it is an extra parameter matching an ellipsis). */
5601 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5602 enum machine_mode orig_mode, tree type,
5603 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5605 static bool warnedsse, warnedmmx;
5607 /* Avoid the AL settings for the Unix64 ABI. */
5608 if (mode == VOIDmode)
5624 if (words <= cum->nregs)
5626 int regno = cum->regno;
5628 /* Fastcall allocates the first two DWORD (SImode) or
5629 smaller arguments to ECX and EDX if it isn't an
5635 || (type && AGGREGATE_TYPE_P (type)))
5638 /* ECX not EAX is the first allocated register. */
5639 if (regno == AX_REG)
5642 return gen_rtx_REG (mode, regno);
5647 if (cum->float_in_sse < 2)
5650 if (cum->float_in_sse < 1)
5654 /* In 32bit, we pass TImode in xmm registers. */
5661 if (!type || !AGGREGATE_TYPE_P (type))
5663 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5666 warning (0, "SSE vector argument without SSE enabled "
5670 return gen_reg_or_parallel (mode, orig_mode,
5671 cum->sse_regno + FIRST_SSE_REG);
5676 /* In 32bit, we pass OImode in ymm registers. */
5683 if (!type || !AGGREGATE_TYPE_P (type))
5686 return gen_reg_or_parallel (mode, orig_mode,
5687 cum->sse_regno + FIRST_SSE_REG);
5696 if (!type || !AGGREGATE_TYPE_P (type))
5698 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5701 warning (0, "MMX vector argument without MMX enabled "
5705 return gen_reg_or_parallel (mode, orig_mode,
5706 cum->mmx_regno + FIRST_MMX_REG);
5715 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5716 enum machine_mode orig_mode, tree type, int named)
5718 /* Handle a hidden AL argument containing number of registers
5719 for varargs x86-64 functions. */
5720 if (mode == VOIDmode)
5721 return GEN_INT (cum->maybe_vaarg
5722 ? (cum->sse_nregs < 0
5723 ? (cum->call_abi == DEFAULT_ABI
5725 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5726 : X64_SSE_REGPARM_MAX))
5741 /* In 64bit, we pass TImode in interger registers and OImode on
5744 /* Unnamed 256bit vector mode parameters are passed on stack. */
5750 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5752 &x86_64_int_parameter_registers [cum->regno],
5757 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5758 enum machine_mode orig_mode, int named,
5759 HOST_WIDE_INT bytes)
5763 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5764 We use value of -2 to specify that current function call is MSABI. */
5765 if (mode == VOIDmode)
5766 return GEN_INT (-2);
5768 /* If we've run out of registers, it goes on the stack. */
5769 if (cum->nregs == 0)
5772 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5774 /* Only floating point modes are passed in anything but integer regs. */
5775 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5778 regno = cum->regno + FIRST_SSE_REG;
5783 /* Unnamed floating parameters are passed in both the
5784 SSE and integer registers. */
5785 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5786 t2 = gen_rtx_REG (mode, regno);
5787 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5788 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5789 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5792 /* Handle aggregated types passed in register. */
5793 if (orig_mode == BLKmode)
5795 if (bytes > 0 && bytes <= 8)
5796 mode = (bytes > 4 ? DImode : SImode);
5797 if (mode == BLKmode)
5801 return gen_reg_or_parallel (mode, orig_mode, regno);
5805 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5806 tree type, int named)
5808 enum machine_mode mode = omode;
5809 HOST_WIDE_INT bytes, words;
5811 if (mode == BLKmode)
5812 bytes = int_size_in_bytes (type);
5814 bytes = GET_MODE_SIZE (mode);
5815 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5817 /* To simplify the code below, represent vector types with a vector mode
5818 even if MMX/SSE are not active. */
5819 if (type && TREE_CODE (type) == VECTOR_TYPE)
5820 mode = type_natural_mode (type, cum);
5822 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5823 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5824 else if (TARGET_64BIT)
5825 return function_arg_64 (cum, mode, omode, type, named);
5827 return function_arg_32 (cum, mode, omode, type, bytes, words);
5830 /* A C expression that indicates when an argument must be passed by
5831 reference. If nonzero for an argument, a copy of that argument is
5832 made in memory and a pointer to the argument is passed instead of
5833 the argument itself. The pointer is passed in whatever way is
5834 appropriate for passing a pointer to that type. */
5837 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5838 enum machine_mode mode ATTRIBUTE_UNUSED,
5839 const_tree type, bool named ATTRIBUTE_UNUSED)
5841 /* See Windows x64 Software Convention. */
5842 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5844 int msize = (int) GET_MODE_SIZE (mode);
5847 /* Arrays are passed by reference. */
5848 if (TREE_CODE (type) == ARRAY_TYPE)
5851 if (AGGREGATE_TYPE_P (type))
5853 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5854 are passed by reference. */
5855 msize = int_size_in_bytes (type);
5859 /* __m128 is passed by reference. */
5861 case 1: case 2: case 4: case 8:
5867 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5873 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5876 contains_aligned_value_p (tree type)
5878 enum machine_mode mode = TYPE_MODE (type);
5879 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5883 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5885 if (TYPE_ALIGN (type) < 128)
5888 if (AGGREGATE_TYPE_P (type))
5890 /* Walk the aggregates recursively. */
5891 switch (TREE_CODE (type))
5895 case QUAL_UNION_TYPE:
5899 /* Walk all the structure fields. */
5900 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5902 if (TREE_CODE (field) == FIELD_DECL
5903 && contains_aligned_value_p (TREE_TYPE (field)))
5910 /* Just for use if some languages passes arrays by value. */
5911 if (contains_aligned_value_p (TREE_TYPE (type)))
5922 /* Gives the alignment boundary, in bits, of an argument with the
5923 specified mode and type. */
5926 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5931 /* Since canonical type is used for call, we convert it to
5932 canonical type if needed. */
5933 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5934 type = TYPE_CANONICAL (type);
5935 align = TYPE_ALIGN (type);
5938 align = GET_MODE_ALIGNMENT (mode);
5939 if (align < PARM_BOUNDARY)
5940 align = PARM_BOUNDARY;
5941 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5942 natural boundaries. */
5943 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5945 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5946 make an exception for SSE modes since these require 128bit
5949 The handling here differs from field_alignment. ICC aligns MMX
5950 arguments to 4 byte boundaries, while structure fields are aligned
5951 to 8 byte boundaries. */
5954 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5955 align = PARM_BOUNDARY;
5959 if (!contains_aligned_value_p (type))
5960 align = PARM_BOUNDARY;
5963 if (align > BIGGEST_ALIGNMENT)
5964 align = BIGGEST_ALIGNMENT;
5968 /* Return true if N is a possible register number of function value. */
5971 ix86_function_value_regno_p (int regno)
5978 case FIRST_FLOAT_REG:
5979 /* TODO: The function should depend on current function ABI but
5980 builtins.c would need updating then. Therefore we use the
5982 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
5984 return TARGET_FLOAT_RETURNS_IN_80387;
5990 if (TARGET_MACHO || TARGET_64BIT)
5998 /* Define how to find the value returned by a function.
5999 VALTYPE is the data type of the value (as a tree).
6000 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6001 otherwise, FUNC is 0. */
6004 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6005 const_tree fntype, const_tree fn)
6009 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6010 we normally prevent this case when mmx is not available. However
6011 some ABIs may require the result to be returned like DImode. */
6012 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6013 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6015 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6016 we prevent this case when sse is not available. However some ABIs
6017 may require the result to be returned like integer TImode. */
6018 else if (mode == TImode
6019 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6020 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6022 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6023 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6024 regno = FIRST_FLOAT_REG;
6026 /* Most things go in %eax. */
6029 /* Override FP return register with %xmm0 for local functions when
6030 SSE math is enabled or for functions with sseregparm attribute. */
6031 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6033 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6034 if ((sse_level >= 1 && mode == SFmode)
6035 || (sse_level == 2 && mode == DFmode))
6036 regno = FIRST_SSE_REG;
6039 return gen_rtx_REG (orig_mode, regno);
6043 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6048 /* Handle libcalls, which don't provide a type node. */
6049 if (valtype == NULL)
6061 return gen_rtx_REG (mode, FIRST_SSE_REG);
6064 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6068 return gen_rtx_REG (mode, AX_REG);
6072 ret = construct_container (mode, orig_mode, valtype, 1,
6073 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6074 x86_64_int_return_registers, 0);
6076 /* For zero sized structures, construct_container returns NULL, but we
6077 need to keep rest of compiler happy by returning meaningful value. */
6079 ret = gen_rtx_REG (orig_mode, AX_REG);
6085 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6087 unsigned int regno = AX_REG;
6091 switch (GET_MODE_SIZE (mode))
6094 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6095 && !COMPLEX_MODE_P (mode))
6096 regno = FIRST_SSE_REG;
6100 if (mode == SFmode || mode == DFmode)
6101 regno = FIRST_SSE_REG;
6107 return gen_rtx_REG (orig_mode, regno);
6111 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6112 enum machine_mode orig_mode, enum machine_mode mode)
6114 const_tree fn, fntype;
6117 if (fntype_or_decl && DECL_P (fntype_or_decl))
6118 fn = fntype_or_decl;
6119 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6121 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6122 return function_value_ms_64 (orig_mode, mode);
6123 else if (TARGET_64BIT)
6124 return function_value_64 (orig_mode, mode, valtype);
6126 return function_value_32 (orig_mode, mode, fntype, fn);
6130 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6131 bool outgoing ATTRIBUTE_UNUSED)
6133 enum machine_mode mode, orig_mode;
6135 orig_mode = TYPE_MODE (valtype);
6136 mode = type_natural_mode (valtype, NULL);
6137 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6141 ix86_libcall_value (enum machine_mode mode)
6143 return ix86_function_value_1 (NULL, NULL, mode, mode);
6146 /* Return true iff type is returned in memory. */
6148 static int ATTRIBUTE_UNUSED
6149 return_in_memory_32 (const_tree type, enum machine_mode mode)
6153 if (mode == BLKmode)
6156 size = int_size_in_bytes (type);
6158 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6161 if (VECTOR_MODE_P (mode) || mode == TImode)
6163 /* User-created vectors small enough to fit in EAX. */
6167 /* MMX/3dNow values are returned in MM0,
6168 except when it doesn't exits. */
6170 return (TARGET_MMX ? 0 : 1);
6172 /* SSE values are returned in XMM0, except when it doesn't exist. */
6174 return (TARGET_SSE ? 0 : 1);
6185 static int ATTRIBUTE_UNUSED
6186 return_in_memory_64 (const_tree type, enum machine_mode mode)
6188 int needed_intregs, needed_sseregs;
6189 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6192 static int ATTRIBUTE_UNUSED
6193 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6195 HOST_WIDE_INT size = int_size_in_bytes (type);
6197 /* __m128 is returned in xmm0. */
6198 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6199 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6202 /* Otherwise, the size must be exactly in [1248]. */
6203 return (size != 1 && size != 2 && size != 4 && size != 8);
6207 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6209 #ifdef SUBTARGET_RETURN_IN_MEMORY
6210 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6212 const enum machine_mode mode = type_natural_mode (type, NULL);
6216 if (ix86_function_type_abi (fntype) == MS_ABI)
6217 return return_in_memory_ms_64 (type, mode);
6219 return return_in_memory_64 (type, mode);
6222 return return_in_memory_32 (type, mode);
6226 /* Return false iff TYPE is returned in memory. This version is used
6227 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6228 but differs notably in that when MMX is available, 8-byte vectors
6229 are returned in memory, rather than in MMX registers. */
6232 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6235 enum machine_mode mode = type_natural_mode (type, NULL);
6238 return return_in_memory_64 (type, mode);
6240 if (mode == BLKmode)
6243 size = int_size_in_bytes (type);
6245 if (VECTOR_MODE_P (mode))
6247 /* Return in memory only if MMX registers *are* available. This
6248 seems backwards, but it is consistent with the existing
6255 else if (mode == TImode)
6257 else if (mode == XFmode)
6263 /* When returning SSE vector types, we have a choice of either
6264 (1) being abi incompatible with a -march switch, or
6265 (2) generating an error.
6266 Given no good solution, I think the safest thing is one warning.
6267 The user won't be able to use -Werror, but....
6269 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6270 called in response to actually generating a caller or callee that
6271 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6272 via aggregate_value_p for general type probing from tree-ssa. */
6275 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6277 static bool warnedsse, warnedmmx;
6279 if (!TARGET_64BIT && type)
6281 /* Look at the return type of the function, not the function type. */
6282 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6284 if (!TARGET_SSE && !warnedsse)
6287 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6290 warning (0, "SSE vector return without SSE enabled "
6295 if (!TARGET_MMX && !warnedmmx)
6297 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6300 warning (0, "MMX vector return without MMX enabled "
6310 /* Create the va_list data type. */
6312 /* Returns the calling convention specific va_list date type.
6313 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6316 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6318 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6320 /* For i386 we use plain pointer to argument area. */
6321 if (!TARGET_64BIT || abi == MS_ABI)
6322 return build_pointer_type (char_type_node);
6324 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6325 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6327 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6328 unsigned_type_node);
6329 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6330 unsigned_type_node);
6331 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6333 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6336 va_list_gpr_counter_field = f_gpr;
6337 va_list_fpr_counter_field = f_fpr;
6339 DECL_FIELD_CONTEXT (f_gpr) = record;
6340 DECL_FIELD_CONTEXT (f_fpr) = record;
6341 DECL_FIELD_CONTEXT (f_ovf) = record;
6342 DECL_FIELD_CONTEXT (f_sav) = record;
6344 TREE_CHAIN (record) = type_decl;
6345 TYPE_NAME (record) = type_decl;
6346 TYPE_FIELDS (record) = f_gpr;
6347 TREE_CHAIN (f_gpr) = f_fpr;
6348 TREE_CHAIN (f_fpr) = f_ovf;
6349 TREE_CHAIN (f_ovf) = f_sav;
6351 layout_type (record);
6353 /* The correct type is an array type of one element. */
6354 return build_array_type (record, build_index_type (size_zero_node));
6357 /* Setup the builtin va_list data type and for 64-bit the additional
6358 calling convention specific va_list data types. */
6361 ix86_build_builtin_va_list (void)
6363 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6365 /* Initialize abi specific va_list builtin types. */
6369 if (DEFAULT_ABI == MS_ABI)
6371 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6372 if (TREE_CODE (t) != RECORD_TYPE)
6373 t = build_variant_type_copy (t);
6374 sysv_va_list_type_node = t;
6379 if (TREE_CODE (t) != RECORD_TYPE)
6380 t = build_variant_type_copy (t);
6381 sysv_va_list_type_node = t;
6383 if (DEFAULT_ABI != MS_ABI)
6385 t = ix86_build_builtin_va_list_abi (MS_ABI);
6386 if (TREE_CODE (t) != RECORD_TYPE)
6387 t = build_variant_type_copy (t);
6388 ms_va_list_type_node = t;
6393 if (TREE_CODE (t) != RECORD_TYPE)
6394 t = build_variant_type_copy (t);
6395 ms_va_list_type_node = t;
6402 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6405 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6414 int regparm = ix86_regparm;
6416 if (cum->call_abi != DEFAULT_ABI)
6417 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6419 /* GPR size of varargs save area. */
6420 if (cfun->va_list_gpr_size)
6421 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6423 ix86_varargs_gpr_size = 0;
6425 /* FPR size of varargs save area. We don't need it if we don't pass
6426 anything in SSE registers. */
6427 if (cum->sse_nregs && cfun->va_list_fpr_size)
6428 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6430 ix86_varargs_fpr_size = 0;
6432 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6435 save_area = frame_pointer_rtx;
6436 set = get_varargs_alias_set ();
6438 for (i = cum->regno;
6440 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6443 mem = gen_rtx_MEM (Pmode,
6444 plus_constant (save_area, i * UNITS_PER_WORD));
6445 MEM_NOTRAP_P (mem) = 1;
6446 set_mem_alias_set (mem, set);
6447 emit_move_insn (mem, gen_rtx_REG (Pmode,
6448 x86_64_int_parameter_registers[i]));
6451 if (ix86_varargs_fpr_size)
6453 /* Now emit code to save SSE registers. The AX parameter contains number
6454 of SSE parameter registers used to call this function. We use
6455 sse_prologue_save insn template that produces computed jump across
6456 SSE saves. We need some preparation work to get this working. */
6458 label = gen_label_rtx ();
6459 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6461 /* Compute address to jump to :
6462 label - eax*4 + nnamed_sse_arguments*4 Or
6463 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6464 tmp_reg = gen_reg_rtx (Pmode);
6465 nsse_reg = gen_reg_rtx (Pmode);
6466 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6467 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6468 gen_rtx_MULT (Pmode, nsse_reg,
6471 /* vmovaps is one byte longer than movaps. */
6473 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6474 gen_rtx_PLUS (Pmode, tmp_reg,
6480 gen_rtx_CONST (DImode,
6481 gen_rtx_PLUS (DImode,
6483 GEN_INT (cum->sse_regno
6484 * (TARGET_AVX ? 5 : 4)))));
6486 emit_move_insn (nsse_reg, label_ref);
6487 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6489 /* Compute address of memory block we save into. We always use pointer
6490 pointing 127 bytes after first byte to store - this is needed to keep
6491 instruction size limited by 4 bytes (5 bytes for AVX) with one
6492 byte displacement. */
6493 tmp_reg = gen_reg_rtx (Pmode);
6494 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6495 plus_constant (save_area,
6496 ix86_varargs_gpr_size + 127)));
6497 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6498 MEM_NOTRAP_P (mem) = 1;
6499 set_mem_alias_set (mem, set);
6500 set_mem_align (mem, BITS_PER_WORD);
6502 /* And finally do the dirty job! */
6503 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6504 GEN_INT (cum->sse_regno), label));
6509 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6511 alias_set_type set = get_varargs_alias_set ();
6514 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6518 mem = gen_rtx_MEM (Pmode,
6519 plus_constant (virtual_incoming_args_rtx,
6520 i * UNITS_PER_WORD));
6521 MEM_NOTRAP_P (mem) = 1;
6522 set_mem_alias_set (mem, set);
6524 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6525 emit_move_insn (mem, reg);
6530 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6531 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6534 CUMULATIVE_ARGS next_cum;
6537 /* This argument doesn't appear to be used anymore. Which is good,
6538 because the old code here didn't suppress rtl generation. */
6539 gcc_assert (!no_rtl);
6544 fntype = TREE_TYPE (current_function_decl);
6546 /* For varargs, we do not want to skip the dummy va_dcl argument.
6547 For stdargs, we do want to skip the last named argument. */
6549 if (stdarg_p (fntype))
6550 function_arg_advance (&next_cum, mode, type, 1);
6552 if (cum->call_abi == MS_ABI)
6553 setup_incoming_varargs_ms_64 (&next_cum);
6555 setup_incoming_varargs_64 (&next_cum);
6558 /* Checks if TYPE is of kind va_list char *. */
6561 is_va_list_char_pointer (tree type)
6565 /* For 32-bit it is always true. */
6568 canonic = ix86_canonical_va_list_type (type);
6569 return (canonic == ms_va_list_type_node
6570 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6573 /* Implement va_start. */
6576 ix86_va_start (tree valist, rtx nextarg)
6578 HOST_WIDE_INT words, n_gpr, n_fpr;
6579 tree f_gpr, f_fpr, f_ovf, f_sav;
6580 tree gpr, fpr, ovf, sav, t;
6583 /* Only 64bit target needs something special. */
6584 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6586 std_expand_builtin_va_start (valist, nextarg);
6590 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6591 f_fpr = TREE_CHAIN (f_gpr);
6592 f_ovf = TREE_CHAIN (f_fpr);
6593 f_sav = TREE_CHAIN (f_ovf);
6595 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6596 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6597 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6598 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6599 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6601 /* Count number of gp and fp argument registers used. */
6602 words = crtl->args.info.words;
6603 n_gpr = crtl->args.info.regno;
6604 n_fpr = crtl->args.info.sse_regno;
6606 if (cfun->va_list_gpr_size)
6608 type = TREE_TYPE (gpr);
6609 t = build2 (MODIFY_EXPR, type,
6610 gpr, build_int_cst (type, n_gpr * 8));
6611 TREE_SIDE_EFFECTS (t) = 1;
6612 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6615 if (TARGET_SSE && cfun->va_list_fpr_size)
6617 type = TREE_TYPE (fpr);
6618 t = build2 (MODIFY_EXPR, type, fpr,
6619 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6620 TREE_SIDE_EFFECTS (t) = 1;
6621 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6624 /* Find the overflow area. */
6625 type = TREE_TYPE (ovf);
6626 t = make_tree (type, crtl->args.internal_arg_pointer);
6628 t = build2 (POINTER_PLUS_EXPR, type, t,
6629 size_int (words * UNITS_PER_WORD));
6630 t = build2 (MODIFY_EXPR, type, ovf, t);
6631 TREE_SIDE_EFFECTS (t) = 1;
6632 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6634 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6636 /* Find the register save area.
6637 Prologue of the function save it right above stack frame. */
6638 type = TREE_TYPE (sav);
6639 t = make_tree (type, frame_pointer_rtx);
6640 if (!ix86_varargs_gpr_size)
6641 t = build2 (POINTER_PLUS_EXPR, type, t,
6642 size_int (-8 * X86_64_REGPARM_MAX));
6643 t = build2 (MODIFY_EXPR, type, sav, t);
6644 TREE_SIDE_EFFECTS (t) = 1;
6645 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6649 /* Implement va_arg. */
6652 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6655 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6656 tree f_gpr, f_fpr, f_ovf, f_sav;
6657 tree gpr, fpr, ovf, sav, t;
6659 tree lab_false, lab_over = NULL_TREE;
6664 enum machine_mode nat_mode;
6667 /* Only 64bit target needs something special. */
6668 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6669 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6671 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6672 f_fpr = TREE_CHAIN (f_gpr);
6673 f_ovf = TREE_CHAIN (f_fpr);
6674 f_sav = TREE_CHAIN (f_ovf);
6676 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6677 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6678 valist = build_va_arg_indirect_ref (valist);
6679 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6680 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6681 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6683 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6685 type = build_pointer_type (type);
6686 size = int_size_in_bytes (type);
6687 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6689 nat_mode = type_natural_mode (type, NULL);
6698 /* Unnamed 256bit vector mode parameters are passed on stack. */
6699 if (ix86_cfun_abi () == SYSV_ABI)
6706 container = construct_container (nat_mode, TYPE_MODE (type),
6707 type, 0, X86_64_REGPARM_MAX,
6708 X86_64_SSE_REGPARM_MAX, intreg,
6713 /* Pull the value out of the saved registers. */
6715 addr = create_tmp_var (ptr_type_node, "addr");
6716 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6720 int needed_intregs, needed_sseregs;
6722 tree int_addr, sse_addr;
6724 lab_false = create_artificial_label ();
6725 lab_over = create_artificial_label ();
6727 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6729 need_temp = (!REG_P (container)
6730 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6731 || TYPE_ALIGN (type) > 128));
6733 /* In case we are passing structure, verify that it is consecutive block
6734 on the register save area. If not we need to do moves. */
6735 if (!need_temp && !REG_P (container))
6737 /* Verify that all registers are strictly consecutive */
6738 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6742 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6744 rtx slot = XVECEXP (container, 0, i);
6745 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6746 || INTVAL (XEXP (slot, 1)) != i * 16)
6754 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6756 rtx slot = XVECEXP (container, 0, i);
6757 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6758 || INTVAL (XEXP (slot, 1)) != i * 8)
6770 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6771 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6772 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6773 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6776 /* First ensure that we fit completely in registers. */
6779 t = build_int_cst (TREE_TYPE (gpr),
6780 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6781 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6782 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6783 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6784 gimplify_and_add (t, pre_p);
6788 t = build_int_cst (TREE_TYPE (fpr),
6789 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6790 + X86_64_REGPARM_MAX * 8);
6791 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6792 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6793 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6794 gimplify_and_add (t, pre_p);
6797 /* Compute index to start of area used for integer regs. */
6800 /* int_addr = gpr + sav; */
6801 t = fold_convert (sizetype, gpr);
6802 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6803 gimplify_assign (int_addr, t, pre_p);
6807 /* sse_addr = fpr + sav; */
6808 t = fold_convert (sizetype, fpr);
6809 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6810 gimplify_assign (sse_addr, t, pre_p);
6815 tree temp = create_tmp_var (type, "va_arg_tmp");
6818 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6819 gimplify_assign (addr, t, pre_p);
6821 for (i = 0; i < XVECLEN (container, 0); i++)
6823 rtx slot = XVECEXP (container, 0, i);
6824 rtx reg = XEXP (slot, 0);
6825 enum machine_mode mode = GET_MODE (reg);
6826 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6827 tree addr_type = build_pointer_type (piece_type);
6828 tree daddr_type = build_pointer_type_for_mode (piece_type,
6832 tree dest_addr, dest;
6834 if (SSE_REGNO_P (REGNO (reg)))
6836 src_addr = sse_addr;
6837 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6841 src_addr = int_addr;
6842 src_offset = REGNO (reg) * 8;
6844 src_addr = fold_convert (addr_type, src_addr);
6845 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6846 size_int (src_offset));
6847 src = build_va_arg_indirect_ref (src_addr);
6849 dest_addr = fold_convert (daddr_type, addr);
6850 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6851 size_int (INTVAL (XEXP (slot, 1))));
6852 dest = build_va_arg_indirect_ref (dest_addr);
6854 gimplify_assign (dest, src, pre_p);
6860 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6861 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6862 gimplify_assign (gpr, t, pre_p);
6867 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6868 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6869 gimplify_assign (fpr, t, pre_p);
6872 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6874 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6877 /* ... otherwise out of the overflow area. */
6879 /* When we align parameter on stack for caller, if the parameter
6880 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6881 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6882 here with caller. */
6883 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6884 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6885 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6887 /* Care for on-stack alignment if needed. */
6888 if (arg_boundary <= 64
6889 || integer_zerop (TYPE_SIZE (type)))
6893 HOST_WIDE_INT align = arg_boundary / 8;
6894 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6895 size_int (align - 1));
6896 t = fold_convert (sizetype, t);
6897 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6899 t = fold_convert (TREE_TYPE (ovf), t);
6901 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6902 gimplify_assign (addr, t, pre_p);
6904 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6905 size_int (rsize * UNITS_PER_WORD));
6906 gimplify_assign (unshare_expr (ovf), t, pre_p);
6909 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6911 ptrtype = build_pointer_type (type);
6912 addr = fold_convert (ptrtype, addr);
6915 addr = build_va_arg_indirect_ref (addr);
6916 return build_va_arg_indirect_ref (addr);
6919 /* Return nonzero if OPNUM's MEM should be matched
6920 in movabs* patterns. */
6923 ix86_check_movabs (rtx insn, int opnum)
6927 set = PATTERN (insn);
6928 if (GET_CODE (set) == PARALLEL)
6929 set = XVECEXP (set, 0, 0);
6930 gcc_assert (GET_CODE (set) == SET);
6931 mem = XEXP (set, opnum);
6932 while (GET_CODE (mem) == SUBREG)
6933 mem = SUBREG_REG (mem);
6934 gcc_assert (MEM_P (mem));
6935 return (volatile_ok || !MEM_VOLATILE_P (mem));
6938 /* Initialize the table of extra 80387 mathematical constants. */
6941 init_ext_80387_constants (void)
6943 static const char * cst[5] =
6945 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6946 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6947 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6948 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6949 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6953 for (i = 0; i < 5; i++)
6955 real_from_string (&ext_80387_constants_table[i], cst[i]);
6956 /* Ensure each constant is rounded to XFmode precision. */
6957 real_convert (&ext_80387_constants_table[i],
6958 XFmode, &ext_80387_constants_table[i]);
6961 ext_80387_constants_init = 1;
6964 /* Return true if the constant is something that can be loaded with
6965 a special instruction. */
6968 standard_80387_constant_p (rtx x)
6970 enum machine_mode mode = GET_MODE (x);
6974 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
6977 if (x == CONST0_RTX (mode))
6979 if (x == CONST1_RTX (mode))
6982 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6984 /* For XFmode constants, try to find a special 80387 instruction when
6985 optimizing for size or on those CPUs that benefit from them. */
6987 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
6991 if (! ext_80387_constants_init)
6992 init_ext_80387_constants ();
6994 for (i = 0; i < 5; i++)
6995 if (real_identical (&r, &ext_80387_constants_table[i]))
6999 /* Load of the constant -0.0 or -1.0 will be split as
7000 fldz;fchs or fld1;fchs sequence. */
7001 if (real_isnegzero (&r))
7003 if (real_identical (&r, &dconstm1))
7009 /* Return the opcode of the special instruction to be used to load
7013 standard_80387_constant_opcode (rtx x)
7015 switch (standard_80387_constant_p (x))
7039 /* Return the CONST_DOUBLE representing the 80387 constant that is
7040 loaded by the specified special instruction. The argument IDX
7041 matches the return value from standard_80387_constant_p. */
7044 standard_80387_constant_rtx (int idx)
7048 if (! ext_80387_constants_init)
7049 init_ext_80387_constants ();
7065 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7069 /* Return 1 if mode is a valid mode for sse. */
7071 standard_sse_mode_p (enum machine_mode mode)
7088 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7089 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7090 modes and AVX is enabled. */
7093 standard_sse_constant_p (rtx x)
7095 enum machine_mode mode = GET_MODE (x);
7097 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7099 if (vector_all_ones_operand (x, mode))
7101 if (standard_sse_mode_p (mode))
7102 return TARGET_SSE2 ? 2 : -2;
7103 else if (VALID_AVX256_REG_MODE (mode))
7104 return TARGET_AVX ? 3 : -3;
7110 /* Return the opcode of the special instruction to be used to load
7114 standard_sse_constant_opcode (rtx insn, rtx x)
7116 switch (standard_sse_constant_p (x))
7119 switch (get_attr_mode (insn))
7122 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7124 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7126 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7128 return "vxorps\t%x0, %x0, %x0";
7130 return "vxorpd\t%x0, %x0, %x0";
7132 return "vpxor\t%x0, %x0, %x0";
7138 switch (get_attr_mode (insn))
7143 return "vpcmpeqd\t%0, %0, %0";
7149 return "pcmpeqd\t%0, %0";
7154 /* Returns 1 if OP contains a symbol reference */
7157 symbolic_reference_mentioned_p (rtx op)
7162 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7165 fmt = GET_RTX_FORMAT (GET_CODE (op));
7166 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7172 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7173 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7177 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7184 /* Return 1 if it is appropriate to emit `ret' instructions in the
7185 body of a function. Do this only if the epilogue is simple, needing a
7186 couple of insns. Prior to reloading, we can't tell how many registers
7187 must be saved, so return 0 then. Return 0 if there is no frame
7188 marker to de-allocate. */
7191 ix86_can_use_return_insn_p (void)
7193 struct ix86_frame frame;
7195 if (! reload_completed || frame_pointer_needed)
7198 /* Don't allow more than 32 pop, since that's all we can do
7199 with one instruction. */
7200 if (crtl->args.pops_args
7201 && crtl->args.size >= 32768)
7204 ix86_compute_frame_layout (&frame);
7205 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7208 /* Value should be nonzero if functions must have frame pointers.
7209 Zero means the frame pointer need not be set up (and parms may
7210 be accessed via the stack pointer) in functions that seem suitable. */
7213 ix86_frame_pointer_required (void)
7215 /* If we accessed previous frames, then the generated code expects
7216 to be able to access the saved ebp value in our frame. */
7217 if (cfun->machine->accesses_prev_frame)
7220 /* Several x86 os'es need a frame pointer for other reasons,
7221 usually pertaining to setjmp. */
7222 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7225 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7226 the frame pointer by default. Turn it back on now if we've not
7227 got a leaf function. */
7228 if (TARGET_OMIT_LEAF_FRAME_POINTER
7229 && (!current_function_is_leaf
7230 || ix86_current_function_calls_tls_descriptor))
7239 /* Record that the current function accesses previous call frames. */
7242 ix86_setup_frame_addresses (void)
7244 cfun->machine->accesses_prev_frame = 1;
7247 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7248 # define USE_HIDDEN_LINKONCE 1
7250 # define USE_HIDDEN_LINKONCE 0
7253 static int pic_labels_used;
7255 /* Fills in the label name that should be used for a pc thunk for
7256 the given register. */
7259 get_pc_thunk_name (char name[32], unsigned int regno)
7261 gcc_assert (!TARGET_64BIT);
7263 if (USE_HIDDEN_LINKONCE)
7264 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7266 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7270 /* This function generates code for -fpic that loads %ebx with
7271 the return address of the caller and then returns. */
7274 ix86_file_end (void)
7279 for (regno = 0; regno < 8; ++regno)
7283 if (! ((pic_labels_used >> regno) & 1))
7286 get_pc_thunk_name (name, regno);
7291 switch_to_section (darwin_sections[text_coal_section]);
7292 fputs ("\t.weak_definition\t", asm_out_file);
7293 assemble_name (asm_out_file, name);
7294 fputs ("\n\t.private_extern\t", asm_out_file);
7295 assemble_name (asm_out_file, name);
7296 fputs ("\n", asm_out_file);
7297 ASM_OUTPUT_LABEL (asm_out_file, name);
7301 if (USE_HIDDEN_LINKONCE)
7305 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7307 TREE_PUBLIC (decl) = 1;
7308 TREE_STATIC (decl) = 1;
7309 DECL_ONE_ONLY (decl) = 1;
7311 (*targetm.asm_out.unique_section) (decl, 0);
7312 switch_to_section (get_named_section (decl, NULL, 0));
7314 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7315 fputs ("\t.hidden\t", asm_out_file);
7316 assemble_name (asm_out_file, name);
7317 fputc ('\n', asm_out_file);
7318 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7322 switch_to_section (text_section);
7323 ASM_OUTPUT_LABEL (asm_out_file, name);
7326 xops[0] = gen_rtx_REG (Pmode, regno);
7327 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7328 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7329 output_asm_insn ("ret", xops);
7332 if (NEED_INDICATE_EXEC_STACK)
7333 file_end_indicate_exec_stack ();
7336 /* Emit code for the SET_GOT patterns. */
7339 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7345 if (TARGET_VXWORKS_RTP && flag_pic)
7347 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7348 xops[2] = gen_rtx_MEM (Pmode,
7349 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7350 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7352 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7353 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7354 an unadorned address. */
7355 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7356 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7357 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7361 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7363 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7365 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7368 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7370 output_asm_insn ("call\t%a2", xops);
7373 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7374 is what will be referenced by the Mach-O PIC subsystem. */
7376 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7379 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7380 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7383 output_asm_insn ("pop%z0\t%0", xops);
7388 get_pc_thunk_name (name, REGNO (dest));
7389 pic_labels_used |= 1 << REGNO (dest);
7391 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7392 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7393 output_asm_insn ("call\t%X2", xops);
7394 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7395 is what will be referenced by the Mach-O PIC subsystem. */
7398 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7400 targetm.asm_out.internal_label (asm_out_file, "L",
7401 CODE_LABEL_NUMBER (label));
7408 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7409 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7411 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7416 /* Generate an "push" pattern for input ARG. */
7421 return gen_rtx_SET (VOIDmode,
7423 gen_rtx_PRE_DEC (Pmode,
7424 stack_pointer_rtx)),
7428 /* Return >= 0 if there is an unused call-clobbered register available
7429 for the entire function. */
7432 ix86_select_alt_pic_regnum (void)
7434 if (current_function_is_leaf && !crtl->profile
7435 && !ix86_current_function_calls_tls_descriptor)
7438 /* Can't use the same register for both PIC and DRAP. */
7440 drap = REGNO (crtl->drap_reg);
7443 for (i = 2; i >= 0; --i)
7444 if (i != drap && !df_regs_ever_live_p (i))
7448 return INVALID_REGNUM;
7451 /* Return 1 if we need to save REGNO. */
7453 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7455 if (pic_offset_table_rtx
7456 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7457 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7459 || crtl->calls_eh_return
7460 || crtl->uses_const_pool))
7462 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7467 if (crtl->calls_eh_return && maybe_eh_return)
7472 unsigned test = EH_RETURN_DATA_REGNO (i);
7473 if (test == INVALID_REGNUM)
7481 && regno == REGNO (crtl->drap_reg))
7484 return (df_regs_ever_live_p (regno)
7485 && !call_used_regs[regno]
7486 && !fixed_regs[regno]
7487 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7490 /* Return number of saved general prupose registers. */
7493 ix86_nsaved_regs (void)
7498 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7499 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7504 /* Return number of saved SSE registrers. */
7507 ix86_nsaved_sseregs (void)
7512 if (ix86_cfun_abi () != MS_ABI)
7514 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7515 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7520 /* Given FROM and TO register numbers, say whether this elimination is
7521 allowed. If stack alignment is needed, we can only replace argument
7522 pointer with hard frame pointer, or replace frame pointer with stack
7523 pointer. Otherwise, frame pointer elimination is automatically
7524 handled and all other eliminations are valid. */
7527 ix86_can_eliminate (int from, int to)
7529 if (stack_realign_fp)
7530 return ((from == ARG_POINTER_REGNUM
7531 && to == HARD_FRAME_POINTER_REGNUM)
7532 || (from == FRAME_POINTER_REGNUM
7533 && to == STACK_POINTER_REGNUM));
7535 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7538 /* Return the offset between two registers, one to be eliminated, and the other
7539 its replacement, at the start of a routine. */
7542 ix86_initial_elimination_offset (int from, int to)
7544 struct ix86_frame frame;
7545 ix86_compute_frame_layout (&frame);
7547 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7548 return frame.hard_frame_pointer_offset;
7549 else if (from == FRAME_POINTER_REGNUM
7550 && to == HARD_FRAME_POINTER_REGNUM)
7551 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7554 gcc_assert (to == STACK_POINTER_REGNUM);
7556 if (from == ARG_POINTER_REGNUM)
7557 return frame.stack_pointer_offset;
7559 gcc_assert (from == FRAME_POINTER_REGNUM);
7560 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7564 /* In a dynamically-aligned function, we can't know the offset from
7565 stack pointer to frame pointer, so we must ensure that setjmp
7566 eliminates fp against the hard fp (%ebp) rather than trying to
7567 index from %esp up to the top of the frame across a gap that is
7568 of unknown (at compile-time) size. */
7570 ix86_builtin_setjmp_frame_value (void)
7572 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7575 /* Fill structure ix86_frame about frame of currently computed function. */
7578 ix86_compute_frame_layout (struct ix86_frame *frame)
7580 HOST_WIDE_INT total_size;
7581 unsigned int stack_alignment_needed;
7582 HOST_WIDE_INT offset;
7583 unsigned int preferred_alignment;
7584 HOST_WIDE_INT size = get_frame_size ();
7586 frame->nregs = ix86_nsaved_regs ();
7587 frame->nsseregs = ix86_nsaved_sseregs ();
7590 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7591 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7593 /* MS ABI seem to require stack alignment to be always 16 except for function
7595 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7597 preferred_alignment = 16;
7598 stack_alignment_needed = 16;
7599 crtl->preferred_stack_boundary = 128;
7600 crtl->stack_alignment_needed = 128;
7603 gcc_assert (!size || stack_alignment_needed);
7604 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7605 gcc_assert (preferred_alignment <= stack_alignment_needed);
7607 /* During reload iteration the amount of registers saved can change.
7608 Recompute the value as needed. Do not recompute when amount of registers
7609 didn't change as reload does multiple calls to the function and does not
7610 expect the decision to change within single iteration. */
7611 if (!optimize_function_for_size_p (cfun)
7612 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7614 int count = frame->nregs;
7616 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7617 /* The fast prologue uses move instead of push to save registers. This
7618 is significantly longer, but also executes faster as modern hardware
7619 can execute the moves in parallel, but can't do that for push/pop.
7621 Be careful about choosing what prologue to emit: When function takes
7622 many instructions to execute we may use slow version as well as in
7623 case function is known to be outside hot spot (this is known with
7624 feedback only). Weight the size of function by number of registers
7625 to save as it is cheap to use one or two push instructions but very
7626 slow to use many of them. */
7628 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7629 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7630 || (flag_branch_probabilities
7631 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7632 cfun->machine->use_fast_prologue_epilogue = false;
7634 cfun->machine->use_fast_prologue_epilogue
7635 = !expensive_function_p (count);
7637 if (TARGET_PROLOGUE_USING_MOVE
7638 && cfun->machine->use_fast_prologue_epilogue)
7639 frame->save_regs_using_mov = true;
7641 frame->save_regs_using_mov = false;
7644 /* Skip return address and saved base pointer. */
7645 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7647 frame->hard_frame_pointer_offset = offset;
7649 /* Set offset to aligned because the realigned frame starts from
7651 if (stack_realign_fp)
7652 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7654 /* Register save area */
7655 offset += frame->nregs * UNITS_PER_WORD;
7657 /* Align SSE reg save area. */
7658 if (frame->nsseregs)
7659 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7661 frame->padding0 = 0;
7663 /* SSE register save area. */
7664 offset += frame->padding0 + frame->nsseregs * 16;
7667 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7668 offset += frame->va_arg_size;
7670 /* Align start of frame for local function. */
7671 frame->padding1 = ((offset + stack_alignment_needed - 1)
7672 & -stack_alignment_needed) - offset;
7674 offset += frame->padding1;
7676 /* Frame pointer points here. */
7677 frame->frame_pointer_offset = offset;
7681 /* Add outgoing arguments area. Can be skipped if we eliminated
7682 all the function calls as dead code.
7683 Skipping is however impossible when function calls alloca. Alloca
7684 expander assumes that last crtl->outgoing_args_size
7685 of stack frame are unused. */
7686 if (ACCUMULATE_OUTGOING_ARGS
7687 && (!current_function_is_leaf || cfun->calls_alloca
7688 || ix86_current_function_calls_tls_descriptor))
7690 offset += crtl->outgoing_args_size;
7691 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7694 frame->outgoing_arguments_size = 0;
7696 /* Align stack boundary. Only needed if we're calling another function
7698 if (!current_function_is_leaf || cfun->calls_alloca
7699 || ix86_current_function_calls_tls_descriptor)
7700 frame->padding2 = ((offset + preferred_alignment - 1)
7701 & -preferred_alignment) - offset;
7703 frame->padding2 = 0;
7705 offset += frame->padding2;
7707 /* We've reached end of stack frame. */
7708 frame->stack_pointer_offset = offset;
7710 /* Size prologue needs to allocate. */
7711 frame->to_allocate =
7712 (size + frame->padding1 + frame->padding2
7713 + frame->outgoing_arguments_size + frame->va_arg_size);
7715 if ((!frame->to_allocate && frame->nregs <= 1)
7716 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7717 frame->save_regs_using_mov = false;
7719 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7720 && current_function_is_leaf
7721 && !ix86_current_function_calls_tls_descriptor)
7723 frame->red_zone_size = frame->to_allocate;
7724 if (frame->save_regs_using_mov)
7725 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7726 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7727 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7730 frame->red_zone_size = 0;
7731 frame->to_allocate -= frame->red_zone_size;
7732 frame->stack_pointer_offset -= frame->red_zone_size;
7734 fprintf (stderr, "\n");
7735 fprintf (stderr, "size: %ld\n", (long)size);
7736 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7737 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7738 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7739 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7740 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7741 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7742 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7743 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7744 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7745 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7746 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7747 (long)frame->hard_frame_pointer_offset);
7748 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7749 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7750 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7751 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7755 /* Emit code to save registers in the prologue. */
7758 ix86_emit_save_regs (void)
7763 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7764 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7766 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7767 RTX_FRAME_RELATED_P (insn) = 1;
7771 /* Emit code to save registers using MOV insns. First register
7772 is restored from POINTER + OFFSET. */
7774 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7779 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7780 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7782 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7784 gen_rtx_REG (Pmode, regno));
7785 RTX_FRAME_RELATED_P (insn) = 1;
7786 offset += UNITS_PER_WORD;
7790 /* Emit code to save registers using MOV insns. First register
7791 is restored from POINTER + OFFSET. */
7793 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7799 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7800 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7802 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7803 set_mem_align (mem, 128);
7804 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7805 RTX_FRAME_RELATED_P (insn) = 1;
7810 /* Expand prologue or epilogue stack adjustment.
7811 The pattern exist to put a dependency on all ebp-based memory accesses.
7812 STYLE should be negative if instructions should be marked as frame related,
7813 zero if %r11 register is live and cannot be freely used and positive
7817 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7822 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7823 else if (x86_64_immediate_operand (offset, DImode))
7824 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7828 /* r11 is used by indirect sibcall return as well, set before the
7829 epilogue and used after the epilogue. ATM indirect sibcall
7830 shouldn't be used together with huge frame sizes in one
7831 function because of the frame_size check in sibcall.c. */
7833 r11 = gen_rtx_REG (DImode, R11_REG);
7834 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7836 RTX_FRAME_RELATED_P (insn) = 1;
7837 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7841 RTX_FRAME_RELATED_P (insn) = 1;
7844 /* Find an available register to be used as dynamic realign argument
7845 pointer regsiter. Such a register will be written in prologue and
7846 used in begin of body, so it must not be
7847 1. parameter passing register.
7849 We reuse static-chain register if it is available. Otherwise, we
7850 use DI for i386 and R13 for x86-64. We chose R13 since it has
7853 Return: the regno of chosen register. */
7856 find_drap_reg (void)
7858 tree decl = cfun->decl;
7862 /* Use R13 for nested function or function need static chain.
7863 Since function with tail call may use any caller-saved
7864 registers in epilogue, DRAP must not use caller-saved
7865 register in such case. */
7866 if ((decl_function_context (decl)
7867 && !DECL_NO_STATIC_CHAIN (decl))
7868 || crtl->tail_call_emit)
7875 /* Use DI for nested function or function need static chain.
7876 Since function with tail call may use any caller-saved
7877 registers in epilogue, DRAP must not use caller-saved
7878 register in such case. */
7879 if ((decl_function_context (decl)
7880 && !DECL_NO_STATIC_CHAIN (decl))
7881 || crtl->tail_call_emit)
7884 /* Reuse static chain register if it isn't used for parameter
7886 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7887 && !lookup_attribute ("fastcall",
7888 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7895 /* Update incoming stack boundary and estimated stack alignment. */
7898 ix86_update_stack_boundary (void)
7900 /* Prefer the one specified at command line. */
7901 ix86_incoming_stack_boundary
7902 = (ix86_user_incoming_stack_boundary
7903 ? ix86_user_incoming_stack_boundary
7904 : ix86_default_incoming_stack_boundary);
7906 /* Incoming stack alignment can be changed on individual functions
7907 via force_align_arg_pointer attribute. We use the smallest
7908 incoming stack boundary. */
7909 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7910 && lookup_attribute (ix86_force_align_arg_pointer_string,
7911 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7912 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7914 /* The incoming stack frame has to be aligned at least at
7915 parm_stack_boundary. */
7916 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
7917 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
7919 /* Stack at entrance of main is aligned by runtime. We use the
7920 smallest incoming stack boundary. */
7921 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7922 && DECL_NAME (current_function_decl)
7923 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7924 && DECL_FILE_SCOPE_P (current_function_decl))
7925 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7927 /* x86_64 vararg needs 16byte stack alignment for register save
7931 && crtl->stack_alignment_estimated < 128)
7932 crtl->stack_alignment_estimated = 128;
7935 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7936 needed or an rtx for DRAP otherwise. */
7939 ix86_get_drap_rtx (void)
7941 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7942 crtl->need_drap = true;
7944 if (stack_realign_drap)
7946 /* Assign DRAP to vDRAP and returns vDRAP */
7947 unsigned int regno = find_drap_reg ();
7952 arg_ptr = gen_rtx_REG (Pmode, regno);
7953 crtl->drap_reg = arg_ptr;
7956 drap_vreg = copy_to_reg (arg_ptr);
7960 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
7961 RTX_FRAME_RELATED_P (insn) = 1;
7968 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7971 ix86_internal_arg_pointer (void)
7973 return virtual_incoming_args_rtx;
7976 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7977 This is called from dwarf2out.c to emit call frame instructions
7978 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7980 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
7982 rtx unspec = SET_SRC (pattern);
7983 gcc_assert (GET_CODE (unspec) == UNSPEC);
7987 case UNSPEC_REG_SAVE:
7988 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
7989 SET_DEST (pattern));
7991 case UNSPEC_DEF_CFA:
7992 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
7993 INTVAL (XVECEXP (unspec, 0, 0)));
8000 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8001 to be generated in correct form. */
8003 ix86_finalize_stack_realign_flags (void)
8005 /* Check if stack realign is really needed after reload, and
8006 stores result in cfun */
8007 unsigned int incoming_stack_boundary
8008 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8009 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8010 unsigned int stack_realign = (incoming_stack_boundary
8011 < (current_function_is_leaf
8012 ? crtl->max_used_stack_slot_alignment
8013 : crtl->stack_alignment_needed));
8015 if (crtl->stack_realign_finalized)
8017 /* After stack_realign_needed is finalized, we can't no longer
8019 gcc_assert (crtl->stack_realign_needed == stack_realign);
8023 crtl->stack_realign_needed = stack_realign;
8024 crtl->stack_realign_finalized = true;
8028 /* Expand the prologue into a bunch of separate insns. */
8031 ix86_expand_prologue (void)
8035 struct ix86_frame frame;
8036 HOST_WIDE_INT allocate;
8038 ix86_finalize_stack_realign_flags ();
8040 /* DRAP should not coexist with stack_realign_fp */
8041 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8043 ix86_compute_frame_layout (&frame);
8045 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8046 of DRAP is needed and stack realignment is really needed after reload */
8047 if (crtl->drap_reg && crtl->stack_realign_needed)
8050 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8051 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8052 ? 0 : UNITS_PER_WORD);
8054 gcc_assert (stack_realign_drap);
8056 /* Grab the argument pointer. */
8057 x = plus_constant (stack_pointer_rtx,
8058 (UNITS_PER_WORD + param_ptr_offset));
8061 /* Only need to push parameter pointer reg if it is caller
8063 if (!call_used_regs[REGNO (crtl->drap_reg)])
8065 /* Push arg pointer reg */
8066 insn = emit_insn (gen_push (y));
8067 RTX_FRAME_RELATED_P (insn) = 1;
8070 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8071 RTX_FRAME_RELATED_P (insn) = 1;
8073 /* Align the stack. */
8074 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8076 GEN_INT (-align_bytes)));
8077 RTX_FRAME_RELATED_P (insn) = 1;
8079 /* Replicate the return address on the stack so that return
8080 address can be reached via (argp - 1) slot. This is needed
8081 to implement macro RETURN_ADDR_RTX and intrinsic function
8082 expand_builtin_return_addr etc. */
8084 x = gen_frame_mem (Pmode,
8085 plus_constant (x, -UNITS_PER_WORD));
8086 insn = emit_insn (gen_push (x));
8087 RTX_FRAME_RELATED_P (insn) = 1;
8090 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8091 slower on all targets. Also sdb doesn't like it. */
8093 if (frame_pointer_needed)
8095 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8096 RTX_FRAME_RELATED_P (insn) = 1;
8098 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8099 RTX_FRAME_RELATED_P (insn) = 1;
8102 if (stack_realign_fp)
8104 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8105 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8107 /* Align the stack. */
8108 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8110 GEN_INT (-align_bytes)));
8111 RTX_FRAME_RELATED_P (insn) = 1;
8114 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8116 if (!frame.save_regs_using_mov)
8117 ix86_emit_save_regs ();
8119 allocate += frame.nregs * UNITS_PER_WORD;
8121 /* When using red zone we may start register saving before allocating
8122 the stack frame saving one cycle of the prologue. However I will
8123 avoid doing this if I am going to have to probe the stack since
8124 at least on x86_64 the stack probe can turn into a call that clobbers
8125 a red zone location */
8126 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8127 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8128 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8129 && !crtl->stack_realign_needed)
8130 ? hard_frame_pointer_rtx
8131 : stack_pointer_rtx,
8132 -frame.nregs * UNITS_PER_WORD);
8136 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8137 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8138 GEN_INT (-allocate), -1);
8141 /* Only valid for Win32. */
8142 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8146 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8148 if (cfun->machine->call_abi == MS_ABI)
8151 eax_live = ix86_eax_live_at_start_p ();
8155 emit_insn (gen_push (eax));
8156 allocate -= UNITS_PER_WORD;
8159 emit_move_insn (eax, GEN_INT (allocate));
8162 insn = gen_allocate_stack_worker_64 (eax, eax);
8164 insn = gen_allocate_stack_worker_32 (eax, eax);
8165 insn = emit_insn (insn);
8166 RTX_FRAME_RELATED_P (insn) = 1;
8167 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8168 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8169 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8170 t, REG_NOTES (insn));
8174 if (frame_pointer_needed)
8175 t = plus_constant (hard_frame_pointer_rtx,
8178 - frame.nregs * UNITS_PER_WORD);
8180 t = plus_constant (stack_pointer_rtx, allocate);
8181 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8185 if (frame.save_regs_using_mov
8186 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8187 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8189 if (!frame_pointer_needed
8190 || !frame.to_allocate
8191 || crtl->stack_realign_needed)
8192 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8194 + frame.nsseregs * 16 + frame.padding0);
8196 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8197 -frame.nregs * UNITS_PER_WORD);
8199 if (!frame_pointer_needed
8200 || !frame.to_allocate
8201 || crtl->stack_realign_needed)
8202 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8205 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8206 - frame.nregs * UNITS_PER_WORD
8207 - frame.nsseregs * 16
8210 pic_reg_used = false;
8211 if (pic_offset_table_rtx
8212 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8215 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8217 if (alt_pic_reg_used != INVALID_REGNUM)
8218 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8220 pic_reg_used = true;
8227 if (ix86_cmodel == CM_LARGE_PIC)
8229 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8230 rtx label = gen_label_rtx ();
8232 LABEL_PRESERVE_P (label) = 1;
8233 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8234 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8235 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8236 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8237 pic_offset_table_rtx, tmp_reg));
8240 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8243 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8246 /* In the pic_reg_used case, make sure that the got load isn't deleted
8247 when mcount needs it. Blockage to avoid call movement across mcount
8248 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8250 if (crtl->profile && pic_reg_used)
8251 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8253 if (crtl->drap_reg && !crtl->stack_realign_needed)
8255 /* vDRAP is setup but after reload it turns out stack realign
8256 isn't necessary, here we will emit prologue to setup DRAP
8257 without stack realign adjustment */
8258 int drap_bp_offset = UNITS_PER_WORD * 2;
8259 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8260 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8263 /* Prevent instructions from being scheduled into register save push
8264 sequence when access to the redzone area is done through frame pointer.
8265 The offset betweeh the frame pointer and the stack pointer is calculated
8266 relative to the value of the stack pointer at the end of the function
8267 prologue, and moving instructions that access redzone area via frame
8268 pointer inside push sequence violates this assumption. */
8269 if (frame_pointer_needed && frame.red_zone_size)
8270 emit_insn (gen_memory_blockage ());
8272 /* Emit cld instruction if stringops are used in the function. */
8273 if (TARGET_CLD && ix86_current_function_needs_cld)
8274 emit_insn (gen_cld ());
8277 /* Emit code to restore saved registers using MOV insns. First register
8278 is restored from POINTER + OFFSET. */
8280 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8281 int maybe_eh_return)
8284 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8286 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8287 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8289 /* Ensure that adjust_address won't be forced to produce pointer
8290 out of range allowed by x86-64 instruction set. */
8291 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8295 r11 = gen_rtx_REG (DImode, R11_REG);
8296 emit_move_insn (r11, GEN_INT (offset));
8297 emit_insn (gen_adddi3 (r11, r11, pointer));
8298 base_address = gen_rtx_MEM (Pmode, r11);
8301 emit_move_insn (gen_rtx_REG (Pmode, regno),
8302 adjust_address (base_address, Pmode, offset));
8303 offset += UNITS_PER_WORD;
8307 /* Emit code to restore saved registers using MOV insns. First register
8308 is restored from POINTER + OFFSET. */
8310 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8311 int maybe_eh_return)
8314 rtx base_address = gen_rtx_MEM (TImode, pointer);
8317 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8318 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8320 /* Ensure that adjust_address won't be forced to produce pointer
8321 out of range allowed by x86-64 instruction set. */
8322 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8326 r11 = gen_rtx_REG (DImode, R11_REG);
8327 emit_move_insn (r11, GEN_INT (offset));
8328 emit_insn (gen_adddi3 (r11, r11, pointer));
8329 base_address = gen_rtx_MEM (TImode, r11);
8332 mem = adjust_address (base_address, TImode, offset);
8333 set_mem_align (mem, 128);
8334 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8339 /* Restore function stack, frame, and registers. */
8342 ix86_expand_epilogue (int style)
8346 struct ix86_frame frame;
8347 HOST_WIDE_INT offset;
8349 ix86_finalize_stack_realign_flags ();
8351 /* When stack is realigned, SP must be valid. */
8352 sp_valid = (!frame_pointer_needed
8353 || current_function_sp_is_unchanging
8354 || stack_realign_fp);
8356 ix86_compute_frame_layout (&frame);
8358 /* See the comment about red zone and frame
8359 pointer usage in ix86_expand_prologue. */
8360 if (frame_pointer_needed && frame.red_zone_size)
8361 emit_insn (gen_memory_blockage ());
8363 /* Calculate start of saved registers relative to ebp. Special care
8364 must be taken for the normal return case of a function using
8365 eh_return: the eax and edx registers are marked as saved, but not
8366 restored along this path. */
8367 offset = frame.nregs;
8368 if (crtl->calls_eh_return && style != 2)
8370 offset *= -UNITS_PER_WORD;
8371 offset -= frame.nsseregs * 16 + frame.padding0;
8373 /* If we're only restoring one register and sp is not valid then
8374 using a move instruction to restore the register since it's
8375 less work than reloading sp and popping the register.
8377 The default code result in stack adjustment using add/lea instruction,
8378 while this code results in LEAVE instruction (or discrete equivalent),
8379 so it is profitable in some other cases as well. Especially when there
8380 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8381 and there is exactly one register to pop. This heuristic may need some
8382 tuning in future. */
8383 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8384 || (TARGET_EPILOGUE_USING_MOVE
8385 && cfun->machine->use_fast_prologue_epilogue
8386 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8387 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs) && frame.to_allocate)
8388 || (frame_pointer_needed && TARGET_USE_LEAVE
8389 && cfun->machine->use_fast_prologue_epilogue
8390 && (frame.nregs + frame.nsseregs) == 1)
8391 || crtl->calls_eh_return)
8393 /* Restore registers. We can use ebp or esp to address the memory
8394 locations. If both are available, default to ebp, since offsets
8395 are known to be small. Only exception is esp pointing directly
8396 to the end of block of saved registers, where we may simplify
8399 If we are realigning stack with bp and sp, regs restore can't
8400 be addressed by bp. sp must be used instead. */
8402 if (!frame_pointer_needed
8403 || (sp_valid && !frame.to_allocate)
8404 || stack_realign_fp)
8406 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8407 frame.to_allocate, style == 2);
8408 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8410 + frame.nsseregs * 16
8411 + frame.padding0, style == 2);
8415 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8416 offset, style == 2);
8417 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8419 + frame.nsseregs * 16
8420 + frame.padding0, style == 2);
8423 /* eh_return epilogues need %ecx added to the stack pointer. */
8426 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8428 /* Stack align doesn't work with eh_return. */
8429 gcc_assert (!crtl->stack_realign_needed);
8431 if (frame_pointer_needed)
8433 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8434 tmp = plus_constant (tmp, UNITS_PER_WORD);
8435 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8437 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8438 emit_move_insn (hard_frame_pointer_rtx, tmp);
8440 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8445 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8446 tmp = plus_constant (tmp, (frame.to_allocate
8447 + frame.nregs * UNITS_PER_WORD
8448 + frame.nsseregs * 16
8450 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8453 else if (!frame_pointer_needed)
8454 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8455 GEN_INT (frame.to_allocate
8456 + frame.nregs * UNITS_PER_WORD
8457 + frame.nsseregs * 16
8460 /* If not an i386, mov & pop is faster than "leave". */
8461 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8462 || !cfun->machine->use_fast_prologue_epilogue)
8463 emit_insn ((*ix86_gen_leave) ());
8466 pro_epilogue_adjust_stack (stack_pointer_rtx,
8467 hard_frame_pointer_rtx,
8470 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8475 /* First step is to deallocate the stack frame so that we can
8478 If we realign stack with frame pointer, then stack pointer
8479 won't be able to recover via lea $offset(%bp), %sp, because
8480 there is a padding area between bp and sp for realign.
8481 "add $to_allocate, %sp" must be used instead. */
8484 gcc_assert (frame_pointer_needed);
8485 gcc_assert (!stack_realign_fp);
8486 pro_epilogue_adjust_stack (stack_pointer_rtx,
8487 hard_frame_pointer_rtx,
8488 GEN_INT (offset), style);
8489 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8490 frame.to_allocate, style == 2);
8491 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8492 GEN_INT (frame.nsseregs * 16), style);
8494 else if (frame.to_allocate || frame.nsseregs)
8496 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8499 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8500 GEN_INT (frame.to_allocate
8501 + frame.nsseregs * 16
8502 + frame.padding0), style);
8505 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8506 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8507 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8508 if (frame_pointer_needed)
8510 /* Leave results in shorter dependency chains on CPUs that are
8511 able to grok it fast. */
8512 if (TARGET_USE_LEAVE)
8513 emit_insn ((*ix86_gen_leave) ());
8516 /* For stack realigned really happens, recover stack
8517 pointer to hard frame pointer is a must, if not using
8519 if (stack_realign_fp)
8520 pro_epilogue_adjust_stack (stack_pointer_rtx,
8521 hard_frame_pointer_rtx,
8523 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8528 if (crtl->drap_reg && crtl->stack_realign_needed)
8530 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8531 ? 0 : UNITS_PER_WORD);
8532 gcc_assert (stack_realign_drap);
8533 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8535 GEN_INT (-(UNITS_PER_WORD
8536 + param_ptr_offset))));
8537 if (!call_used_regs[REGNO (crtl->drap_reg)])
8538 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8542 /* Sibcall epilogues don't want a return instruction. */
8546 if (crtl->args.pops_args && crtl->args.size)
8548 rtx popc = GEN_INT (crtl->args.pops_args);
8550 /* i386 can only pop 64K bytes. If asked to pop more, pop
8551 return address, do explicit add, and jump indirectly to the
8554 if (crtl->args.pops_args >= 65536)
8556 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8558 /* There is no "pascal" calling convention in any 64bit ABI. */
8559 gcc_assert (!TARGET_64BIT);
8561 emit_insn (gen_popsi1 (ecx));
8562 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8563 emit_jump_insn (gen_return_indirect_internal (ecx));
8566 emit_jump_insn (gen_return_pop_internal (popc));
8569 emit_jump_insn (gen_return_internal ());
8572 /* Reset from the function's potential modifications. */
8575 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8576 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8578 if (pic_offset_table_rtx)
8579 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8581 /* Mach-O doesn't support labels at the end of objects, so if
8582 it looks like we might want one, insert a NOP. */
8584 rtx insn = get_last_insn ();
8587 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8588 insn = PREV_INSN (insn);
8592 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8593 fputs ("\tnop\n", file);
8599 /* Extract the parts of an RTL expression that is a valid memory address
8600 for an instruction. Return 0 if the structure of the address is
8601 grossly off. Return -1 if the address contains ASHIFT, so it is not
8602 strictly valid, but still used for computing length of lea instruction. */
8605 ix86_decompose_address (rtx addr, struct ix86_address *out)
8607 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8608 rtx base_reg, index_reg;
8609 HOST_WIDE_INT scale = 1;
8610 rtx scale_rtx = NULL_RTX;
8612 enum ix86_address_seg seg = SEG_DEFAULT;
8614 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8616 else if (GET_CODE (addr) == PLUS)
8626 addends[n++] = XEXP (op, 1);
8629 while (GET_CODE (op) == PLUS);
8634 for (i = n; i >= 0; --i)
8637 switch (GET_CODE (op))
8642 index = XEXP (op, 0);
8643 scale_rtx = XEXP (op, 1);
8647 if (XINT (op, 1) == UNSPEC_TP
8648 && TARGET_TLS_DIRECT_SEG_REFS
8649 && seg == SEG_DEFAULT)
8650 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8679 else if (GET_CODE (addr) == MULT)
8681 index = XEXP (addr, 0); /* index*scale */
8682 scale_rtx = XEXP (addr, 1);
8684 else if (GET_CODE (addr) == ASHIFT)
8688 /* We're called for lea too, which implements ashift on occasion. */
8689 index = XEXP (addr, 0);
8690 tmp = XEXP (addr, 1);
8691 if (!CONST_INT_P (tmp))
8693 scale = INTVAL (tmp);
8694 if ((unsigned HOST_WIDE_INT) scale > 3)
8700 disp = addr; /* displacement */
8702 /* Extract the integral value of scale. */
8705 if (!CONST_INT_P (scale_rtx))
8707 scale = INTVAL (scale_rtx);
8710 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8711 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8713 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8714 if (base_reg && index_reg && scale == 1
8715 && (index_reg == arg_pointer_rtx
8716 || index_reg == frame_pointer_rtx
8717 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8720 tmp = base, base = index, index = tmp;
8721 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8724 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8725 if ((base_reg == hard_frame_pointer_rtx
8726 || base_reg == frame_pointer_rtx
8727 || base_reg == arg_pointer_rtx) && !disp)
8730 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8731 Avoid this by transforming to [%esi+0].
8732 Reload calls address legitimization without cfun defined, so we need
8733 to test cfun for being non-NULL. */
8734 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8735 && base_reg && !index_reg && !disp
8737 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8740 /* Special case: encode reg+reg instead of reg*2. */
8741 if (!base && index && scale && scale == 2)
8742 base = index, base_reg = index_reg, scale = 1;
8744 /* Special case: scaling cannot be encoded without base or displacement. */
8745 if (!base && !disp && index && scale != 1)
8757 /* Return cost of the memory address x.
8758 For i386, it is better to use a complex address than let gcc copy
8759 the address into a reg and make a new pseudo. But not if the address
8760 requires to two regs - that would mean more pseudos with longer
8763 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8765 struct ix86_address parts;
8767 int ok = ix86_decompose_address (x, &parts);
8771 if (parts.base && GET_CODE (parts.base) == SUBREG)
8772 parts.base = SUBREG_REG (parts.base);
8773 if (parts.index && GET_CODE (parts.index) == SUBREG)
8774 parts.index = SUBREG_REG (parts.index);
8776 /* Attempt to minimize number of registers in the address. */
8778 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8780 && (!REG_P (parts.index)
8781 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8785 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8787 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8788 && parts.base != parts.index)
8791 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8792 since it's predecode logic can't detect the length of instructions
8793 and it degenerates to vector decoded. Increase cost of such
8794 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8795 to split such addresses or even refuse such addresses at all.
8797 Following addressing modes are affected:
8802 The first and last case may be avoidable by explicitly coding the zero in
8803 memory address, but I don't have AMD-K6 machine handy to check this
8807 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8808 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8809 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8815 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8816 this is used for to form addresses to local data when -fPIC is in
8820 darwin_local_data_pic (rtx disp)
8822 return (GET_CODE (disp) == UNSPEC
8823 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8826 /* Determine if a given RTX is a valid constant. We already know this
8827 satisfies CONSTANT_P. */
8830 legitimate_constant_p (rtx x)
8832 switch (GET_CODE (x))
8837 if (GET_CODE (x) == PLUS)
8839 if (!CONST_INT_P (XEXP (x, 1)))
8844 if (TARGET_MACHO && darwin_local_data_pic (x))
8847 /* Only some unspecs are valid as "constants". */
8848 if (GET_CODE (x) == UNSPEC)
8849 switch (XINT (x, 1))
8854 return TARGET_64BIT;
8857 x = XVECEXP (x, 0, 0);
8858 return (GET_CODE (x) == SYMBOL_REF
8859 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8861 x = XVECEXP (x, 0, 0);
8862 return (GET_CODE (x) == SYMBOL_REF
8863 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8868 /* We must have drilled down to a symbol. */
8869 if (GET_CODE (x) == LABEL_REF)
8871 if (GET_CODE (x) != SYMBOL_REF)
8876 /* TLS symbols are never valid. */
8877 if (SYMBOL_REF_TLS_MODEL (x))
8880 /* DLLIMPORT symbols are never valid. */
8881 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8882 && SYMBOL_REF_DLLIMPORT_P (x))
8887 if (GET_MODE (x) == TImode
8888 && x != CONST0_RTX (TImode)
8894 if (x == CONST0_RTX (GET_MODE (x)))
8902 /* Otherwise we handle everything else in the move patterns. */
8906 /* Determine if it's legal to put X into the constant pool. This
8907 is not possible for the address of thread-local symbols, which
8908 is checked above. */
8911 ix86_cannot_force_const_mem (rtx x)
8913 /* We can always put integral constants and vectors in memory. */
8914 switch (GET_CODE (x))
8924 return !legitimate_constant_p (x);
8927 /* Determine if a given RTX is a valid constant address. */
8930 constant_address_p (rtx x)
8932 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8935 /* Nonzero if the constant value X is a legitimate general operand
8936 when generating PIC code. It is given that flag_pic is on and
8937 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8940 legitimate_pic_operand_p (rtx x)
8944 switch (GET_CODE (x))
8947 inner = XEXP (x, 0);
8948 if (GET_CODE (inner) == PLUS
8949 && CONST_INT_P (XEXP (inner, 1)))
8950 inner = XEXP (inner, 0);
8952 /* Only some unspecs are valid as "constants". */
8953 if (GET_CODE (inner) == UNSPEC)
8954 switch (XINT (inner, 1))
8959 return TARGET_64BIT;
8961 x = XVECEXP (inner, 0, 0);
8962 return (GET_CODE (x) == SYMBOL_REF
8963 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8964 case UNSPEC_MACHOPIC_OFFSET:
8965 return legitimate_pic_address_disp_p (x);
8973 return legitimate_pic_address_disp_p (x);
8980 /* Determine if a given CONST RTX is a valid memory displacement
8984 legitimate_pic_address_disp_p (rtx disp)
8988 /* In 64bit mode we can allow direct addresses of symbols and labels
8989 when they are not dynamic symbols. */
8992 rtx op0 = disp, op1;
8994 switch (GET_CODE (disp))
9000 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9002 op0 = XEXP (XEXP (disp, 0), 0);
9003 op1 = XEXP (XEXP (disp, 0), 1);
9004 if (!CONST_INT_P (op1)
9005 || INTVAL (op1) >= 16*1024*1024
9006 || INTVAL (op1) < -16*1024*1024)
9008 if (GET_CODE (op0) == LABEL_REF)
9010 if (GET_CODE (op0) != SYMBOL_REF)
9015 /* TLS references should always be enclosed in UNSPEC. */
9016 if (SYMBOL_REF_TLS_MODEL (op0))
9018 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9019 && ix86_cmodel != CM_LARGE_PIC)
9027 if (GET_CODE (disp) != CONST)
9029 disp = XEXP (disp, 0);
9033 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9034 of GOT tables. We should not need these anyway. */
9035 if (GET_CODE (disp) != UNSPEC
9036 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9037 && XINT (disp, 1) != UNSPEC_GOTOFF
9038 && XINT (disp, 1) != UNSPEC_PLTOFF))
9041 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9042 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9048 if (GET_CODE (disp) == PLUS)
9050 if (!CONST_INT_P (XEXP (disp, 1)))
9052 disp = XEXP (disp, 0);
9056 if (TARGET_MACHO && darwin_local_data_pic (disp))
9059 if (GET_CODE (disp) != UNSPEC)
9062 switch (XINT (disp, 1))
9067 /* We need to check for both symbols and labels because VxWorks loads
9068 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9070 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9071 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9073 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9074 While ABI specify also 32bit relocation but we don't produce it in
9075 small PIC model at all. */
9076 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9077 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9079 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9081 case UNSPEC_GOTTPOFF:
9082 case UNSPEC_GOTNTPOFF:
9083 case UNSPEC_INDNTPOFF:
9086 disp = XVECEXP (disp, 0, 0);
9087 return (GET_CODE (disp) == SYMBOL_REF
9088 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9090 disp = XVECEXP (disp, 0, 0);
9091 return (GET_CODE (disp) == SYMBOL_REF
9092 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9094 disp = XVECEXP (disp, 0, 0);
9095 return (GET_CODE (disp) == SYMBOL_REF
9096 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9102 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9103 memory address for an instruction. The MODE argument is the machine mode
9104 for the MEM expression that wants to use this address.
9106 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9107 convert common non-canonical forms to canonical form so that they will
9111 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9112 rtx addr, int strict)
9114 struct ix86_address parts;
9115 rtx base, index, disp;
9116 HOST_WIDE_INT scale;
9117 const char *reason = NULL;
9118 rtx reason_rtx = NULL_RTX;
9120 if (ix86_decompose_address (addr, &parts) <= 0)
9122 reason = "decomposition failed";
9127 index = parts.index;
9129 scale = parts.scale;
9131 /* Validate base register.
9133 Don't allow SUBREG's that span more than a word here. It can lead to spill
9134 failures when the base is one word out of a two word structure, which is
9135 represented internally as a DImode int. */
9144 else if (GET_CODE (base) == SUBREG
9145 && REG_P (SUBREG_REG (base))
9146 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9148 reg = SUBREG_REG (base);
9151 reason = "base is not a register";
9155 if (GET_MODE (base) != Pmode)
9157 reason = "base is not in Pmode";
9161 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9162 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9164 reason = "base is not valid";
9169 /* Validate index register.
9171 Don't allow SUBREG's that span more than a word here -- same as above. */
9180 else if (GET_CODE (index) == SUBREG
9181 && REG_P (SUBREG_REG (index))
9182 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9184 reg = SUBREG_REG (index);
9187 reason = "index is not a register";
9191 if (GET_MODE (index) != Pmode)
9193 reason = "index is not in Pmode";
9197 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9198 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9200 reason = "index is not valid";
9205 /* Validate scale factor. */
9208 reason_rtx = GEN_INT (scale);
9211 reason = "scale without index";
9215 if (scale != 2 && scale != 4 && scale != 8)
9217 reason = "scale is not a valid multiplier";
9222 /* Validate displacement. */
9227 if (GET_CODE (disp) == CONST
9228 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9229 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9230 switch (XINT (XEXP (disp, 0), 1))
9232 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9233 used. While ABI specify also 32bit relocations, we don't produce
9234 them at all and use IP relative instead. */
9237 gcc_assert (flag_pic);
9239 goto is_legitimate_pic;
9240 reason = "64bit address unspec";
9243 case UNSPEC_GOTPCREL:
9244 gcc_assert (flag_pic);
9245 goto is_legitimate_pic;
9247 case UNSPEC_GOTTPOFF:
9248 case UNSPEC_GOTNTPOFF:
9249 case UNSPEC_INDNTPOFF:
9255 reason = "invalid address unspec";
9259 else if (SYMBOLIC_CONST (disp)
9263 && MACHOPIC_INDIRECT
9264 && !machopic_operand_p (disp)
9270 if (TARGET_64BIT && (index || base))
9272 /* foo@dtpoff(%rX) is ok. */
9273 if (GET_CODE (disp) != CONST
9274 || GET_CODE (XEXP (disp, 0)) != PLUS
9275 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9276 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9277 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9278 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9280 reason = "non-constant pic memory reference";
9284 else if (! legitimate_pic_address_disp_p (disp))
9286 reason = "displacement is an invalid pic construct";
9290 /* This code used to verify that a symbolic pic displacement
9291 includes the pic_offset_table_rtx register.
9293 While this is good idea, unfortunately these constructs may
9294 be created by "adds using lea" optimization for incorrect
9303 This code is nonsensical, but results in addressing
9304 GOT table with pic_offset_table_rtx base. We can't
9305 just refuse it easily, since it gets matched by
9306 "addsi3" pattern, that later gets split to lea in the
9307 case output register differs from input. While this
9308 can be handled by separate addsi pattern for this case
9309 that never results in lea, this seems to be easier and
9310 correct fix for crash to disable this test. */
9312 else if (GET_CODE (disp) != LABEL_REF
9313 && !CONST_INT_P (disp)
9314 && (GET_CODE (disp) != CONST
9315 || !legitimate_constant_p (disp))
9316 && (GET_CODE (disp) != SYMBOL_REF
9317 || !legitimate_constant_p (disp)))
9319 reason = "displacement is not constant";
9322 else if (TARGET_64BIT
9323 && !x86_64_immediate_operand (disp, VOIDmode))
9325 reason = "displacement is out of range";
9330 /* Everything looks valid. */
9337 /* Return a unique alias set for the GOT. */
9339 static alias_set_type
9340 ix86_GOT_alias_set (void)
9342 static alias_set_type set = -1;
9344 set = new_alias_set ();
9348 /* Return a legitimate reference for ORIG (an address) using the
9349 register REG. If REG is 0, a new pseudo is generated.
9351 There are two types of references that must be handled:
9353 1. Global data references must load the address from the GOT, via
9354 the PIC reg. An insn is emitted to do this load, and the reg is
9357 2. Static data references, constant pool addresses, and code labels
9358 compute the address as an offset from the GOT, whose base is in
9359 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9360 differentiate them from global data objects. The returned
9361 address is the PIC reg + an unspec constant.
9363 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9364 reg also appears in the address. */
9367 legitimize_pic_address (rtx orig, rtx reg)
9374 if (TARGET_MACHO && !TARGET_64BIT)
9377 reg = gen_reg_rtx (Pmode);
9378 /* Use the generic Mach-O PIC machinery. */
9379 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9383 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9385 else if (TARGET_64BIT
9386 && ix86_cmodel != CM_SMALL_PIC
9387 && gotoff_operand (addr, Pmode))
9390 /* This symbol may be referenced via a displacement from the PIC
9391 base address (@GOTOFF). */
9393 if (reload_in_progress)
9394 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9395 if (GET_CODE (addr) == CONST)
9396 addr = XEXP (addr, 0);
9397 if (GET_CODE (addr) == PLUS)
9399 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9401 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9404 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9405 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9407 tmpreg = gen_reg_rtx (Pmode);
9410 emit_move_insn (tmpreg, new_rtx);
9414 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9415 tmpreg, 1, OPTAB_DIRECT);
9418 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9420 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9422 /* This symbol may be referenced via a displacement from the PIC
9423 base address (@GOTOFF). */
9425 if (reload_in_progress)
9426 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9427 if (GET_CODE (addr) == CONST)
9428 addr = XEXP (addr, 0);
9429 if (GET_CODE (addr) == PLUS)
9431 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9433 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9436 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9437 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9438 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9442 emit_move_insn (reg, new_rtx);
9446 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9447 /* We can't use @GOTOFF for text labels on VxWorks;
9448 see gotoff_operand. */
9449 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9451 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9453 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9454 return legitimize_dllimport_symbol (addr, true);
9455 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9456 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9457 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9459 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9460 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9464 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9466 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9467 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9468 new_rtx = gen_const_mem (Pmode, new_rtx);
9469 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9472 reg = gen_reg_rtx (Pmode);
9473 /* Use directly gen_movsi, otherwise the address is loaded
9474 into register for CSE. We don't want to CSE this addresses,
9475 instead we CSE addresses from the GOT table, so skip this. */
9476 emit_insn (gen_movsi (reg, new_rtx));
9481 /* This symbol must be referenced via a load from the
9482 Global Offset Table (@GOT). */
9484 if (reload_in_progress)
9485 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9486 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9487 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9489 new_rtx = force_reg (Pmode, new_rtx);
9490 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9491 new_rtx = gen_const_mem (Pmode, new_rtx);
9492 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9495 reg = gen_reg_rtx (Pmode);
9496 emit_move_insn (reg, new_rtx);
9502 if (CONST_INT_P (addr)
9503 && !x86_64_immediate_operand (addr, VOIDmode))
9507 emit_move_insn (reg, addr);
9511 new_rtx = force_reg (Pmode, addr);
9513 else if (GET_CODE (addr) == CONST)
9515 addr = XEXP (addr, 0);
9517 /* We must match stuff we generate before. Assume the only
9518 unspecs that can get here are ours. Not that we could do
9519 anything with them anyway.... */
9520 if (GET_CODE (addr) == UNSPEC
9521 || (GET_CODE (addr) == PLUS
9522 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9524 gcc_assert (GET_CODE (addr) == PLUS);
9526 if (GET_CODE (addr) == PLUS)
9528 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9530 /* Check first to see if this is a constant offset from a @GOTOFF
9531 symbol reference. */
9532 if (gotoff_operand (op0, Pmode)
9533 && CONST_INT_P (op1))
9537 if (reload_in_progress)
9538 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9539 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9541 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9542 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9543 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9547 emit_move_insn (reg, new_rtx);
9553 if (INTVAL (op1) < -16*1024*1024
9554 || INTVAL (op1) >= 16*1024*1024)
9556 if (!x86_64_immediate_operand (op1, Pmode))
9557 op1 = force_reg (Pmode, op1);
9558 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9564 base = legitimize_pic_address (XEXP (addr, 0), reg);
9565 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9566 base == reg ? NULL_RTX : reg);
9568 if (CONST_INT_P (new_rtx))
9569 new_rtx = plus_constant (base, INTVAL (new_rtx));
9572 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9574 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9575 new_rtx = XEXP (new_rtx, 1);
9577 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9585 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9588 get_thread_pointer (int to_reg)
9592 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9596 reg = gen_reg_rtx (Pmode);
9597 insn = gen_rtx_SET (VOIDmode, reg, tp);
9598 insn = emit_insn (insn);
9603 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9604 false if we expect this to be used for a memory address and true if
9605 we expect to load the address into a register. */
9608 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9610 rtx dest, base, off, pic, tp;
9615 case TLS_MODEL_GLOBAL_DYNAMIC:
9616 dest = gen_reg_rtx (Pmode);
9617 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9619 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9621 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9624 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9625 insns = get_insns ();
9628 RTL_CONST_CALL_P (insns) = 1;
9629 emit_libcall_block (insns, dest, rax, x);
9631 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9632 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9634 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9636 if (TARGET_GNU2_TLS)
9638 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9640 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9644 case TLS_MODEL_LOCAL_DYNAMIC:
9645 base = gen_reg_rtx (Pmode);
9646 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9648 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9650 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9653 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9654 insns = get_insns ();
9657 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9658 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9659 RTL_CONST_CALL_P (insns) = 1;
9660 emit_libcall_block (insns, base, rax, note);
9662 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9663 emit_insn (gen_tls_local_dynamic_base_64 (base));
9665 emit_insn (gen_tls_local_dynamic_base_32 (base));
9667 if (TARGET_GNU2_TLS)
9669 rtx x = ix86_tls_module_base ();
9671 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9672 gen_rtx_MINUS (Pmode, x, tp));
9675 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9676 off = gen_rtx_CONST (Pmode, off);
9678 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9680 if (TARGET_GNU2_TLS)
9682 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9684 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9689 case TLS_MODEL_INITIAL_EXEC:
9693 type = UNSPEC_GOTNTPOFF;
9697 if (reload_in_progress)
9698 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9699 pic = pic_offset_table_rtx;
9700 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9702 else if (!TARGET_ANY_GNU_TLS)
9704 pic = gen_reg_rtx (Pmode);
9705 emit_insn (gen_set_got (pic));
9706 type = UNSPEC_GOTTPOFF;
9711 type = UNSPEC_INDNTPOFF;
9714 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9715 off = gen_rtx_CONST (Pmode, off);
9717 off = gen_rtx_PLUS (Pmode, pic, off);
9718 off = gen_const_mem (Pmode, off);
9719 set_mem_alias_set (off, ix86_GOT_alias_set ());
9721 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9723 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9724 off = force_reg (Pmode, off);
9725 return gen_rtx_PLUS (Pmode, base, off);
9729 base = get_thread_pointer (true);
9730 dest = gen_reg_rtx (Pmode);
9731 emit_insn (gen_subsi3 (dest, base, off));
9735 case TLS_MODEL_LOCAL_EXEC:
9736 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9737 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9738 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9739 off = gen_rtx_CONST (Pmode, off);
9741 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9743 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9744 return gen_rtx_PLUS (Pmode, base, off);
9748 base = get_thread_pointer (true);
9749 dest = gen_reg_rtx (Pmode);
9750 emit_insn (gen_subsi3 (dest, base, off));
9761 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9764 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9765 htab_t dllimport_map;
9768 get_dllimport_decl (tree decl)
9770 struct tree_map *h, in;
9774 size_t namelen, prefixlen;
9780 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9782 in.hash = htab_hash_pointer (decl);
9783 in.base.from = decl;
9784 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9785 h = (struct tree_map *) *loc;
9789 *loc = h = GGC_NEW (struct tree_map);
9791 h->base.from = decl;
9792 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9793 DECL_ARTIFICIAL (to) = 1;
9794 DECL_IGNORED_P (to) = 1;
9795 DECL_EXTERNAL (to) = 1;
9796 TREE_READONLY (to) = 1;
9798 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9799 name = targetm.strip_name_encoding (name);
9800 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9801 ? "*__imp_" : "*__imp__";
9802 namelen = strlen (name);
9803 prefixlen = strlen (prefix);
9804 imp_name = (char *) alloca (namelen + prefixlen + 1);
9805 memcpy (imp_name, prefix, prefixlen);
9806 memcpy (imp_name + prefixlen, name, namelen + 1);
9808 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9809 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9810 SET_SYMBOL_REF_DECL (rtl, to);
9811 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9813 rtl = gen_const_mem (Pmode, rtl);
9814 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9816 SET_DECL_RTL (to, rtl);
9817 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9822 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9823 true if we require the result be a register. */
9826 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9831 gcc_assert (SYMBOL_REF_DECL (symbol));
9832 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9834 x = DECL_RTL (imp_decl);
9836 x = force_reg (Pmode, x);
9840 /* Try machine-dependent ways of modifying an illegitimate address
9841 to be legitimate. If we find one, return the new, valid address.
9842 This macro is used in only one place: `memory_address' in explow.c.
9844 OLDX is the address as it was before break_out_memory_refs was called.
9845 In some cases it is useful to look at this to decide what needs to be done.
9847 MODE and WIN are passed so that this macro can use
9848 GO_IF_LEGITIMATE_ADDRESS.
9850 It is always safe for this macro to do nothing. It exists to recognize
9851 opportunities to optimize the output.
9853 For the 80386, we handle X+REG by loading X into a register R and
9854 using R+REG. R will go in a general reg and indexing will be used.
9855 However, if REG is a broken-out memory address or multiplication,
9856 nothing needs to be done because REG can certainly go in a general reg.
9858 When -fpic is used, special handling is needed for symbolic references.
9859 See comments by legitimize_pic_address in i386.c for details. */
9862 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9867 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9869 return legitimize_tls_address (x, (enum tls_model) log, false);
9870 if (GET_CODE (x) == CONST
9871 && GET_CODE (XEXP (x, 0)) == PLUS
9872 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9873 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9875 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9876 (enum tls_model) log, false);
9877 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9880 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9882 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9883 return legitimize_dllimport_symbol (x, true);
9884 if (GET_CODE (x) == CONST
9885 && GET_CODE (XEXP (x, 0)) == PLUS
9886 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9887 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9889 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9890 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9894 if (flag_pic && SYMBOLIC_CONST (x))
9895 return legitimize_pic_address (x, 0);
9897 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9898 if (GET_CODE (x) == ASHIFT
9899 && CONST_INT_P (XEXP (x, 1))
9900 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9903 log = INTVAL (XEXP (x, 1));
9904 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9905 GEN_INT (1 << log));
9908 if (GET_CODE (x) == PLUS)
9910 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9912 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9913 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9914 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9917 log = INTVAL (XEXP (XEXP (x, 0), 1));
9918 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9919 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9920 GEN_INT (1 << log));
9923 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9924 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9925 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9928 log = INTVAL (XEXP (XEXP (x, 1), 1));
9929 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9930 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9931 GEN_INT (1 << log));
9934 /* Put multiply first if it isn't already. */
9935 if (GET_CODE (XEXP (x, 1)) == MULT)
9937 rtx tmp = XEXP (x, 0);
9938 XEXP (x, 0) = XEXP (x, 1);
9943 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9944 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9945 created by virtual register instantiation, register elimination, and
9946 similar optimizations. */
9947 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9950 x = gen_rtx_PLUS (Pmode,
9951 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9952 XEXP (XEXP (x, 1), 0)),
9953 XEXP (XEXP (x, 1), 1));
9957 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9958 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9959 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9960 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
9961 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
9962 && CONSTANT_P (XEXP (x, 1)))
9965 rtx other = NULL_RTX;
9967 if (CONST_INT_P (XEXP (x, 1)))
9969 constant = XEXP (x, 1);
9970 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
9972 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
9974 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
9975 other = XEXP (x, 1);
9983 x = gen_rtx_PLUS (Pmode,
9984 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
9985 XEXP (XEXP (XEXP (x, 0), 1), 0)),
9986 plus_constant (other, INTVAL (constant)));
9990 if (changed && legitimate_address_p (mode, x, FALSE))
9993 if (GET_CODE (XEXP (x, 0)) == MULT)
9996 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
9999 if (GET_CODE (XEXP (x, 1)) == MULT)
10002 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10006 && REG_P (XEXP (x, 1))
10007 && REG_P (XEXP (x, 0)))
10010 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10013 x = legitimize_pic_address (x, 0);
10016 if (changed && legitimate_address_p (mode, x, FALSE))
10019 if (REG_P (XEXP (x, 0)))
10021 rtx temp = gen_reg_rtx (Pmode);
10022 rtx val = force_operand (XEXP (x, 1), temp);
10024 emit_move_insn (temp, val);
10026 XEXP (x, 1) = temp;
10030 else if (REG_P (XEXP (x, 1)))
10032 rtx temp = gen_reg_rtx (Pmode);
10033 rtx val = force_operand (XEXP (x, 0), temp);
10035 emit_move_insn (temp, val);
10037 XEXP (x, 0) = temp;
10045 /* Print an integer constant expression in assembler syntax. Addition
10046 and subtraction are the only arithmetic that may appear in these
10047 expressions. FILE is the stdio stream to write to, X is the rtx, and
10048 CODE is the operand print code from the output string. */
10051 output_pic_addr_const (FILE *file, rtx x, int code)
10055 switch (GET_CODE (x))
10058 gcc_assert (flag_pic);
10063 if (! TARGET_MACHO || TARGET_64BIT)
10064 output_addr_const (file, x);
10067 const char *name = XSTR (x, 0);
10069 /* Mark the decl as referenced so that cgraph will
10070 output the function. */
10071 if (SYMBOL_REF_DECL (x))
10072 mark_decl_referenced (SYMBOL_REF_DECL (x));
10075 if (MACHOPIC_INDIRECT
10076 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10077 name = machopic_indirection_name (x, /*stub_p=*/true);
10079 assemble_name (file, name);
10081 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10082 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10083 fputs ("@PLT", file);
10090 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10091 assemble_name (asm_out_file, buf);
10095 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10099 /* This used to output parentheses around the expression,
10100 but that does not work on the 386 (either ATT or BSD assembler). */
10101 output_pic_addr_const (file, XEXP (x, 0), code);
10105 if (GET_MODE (x) == VOIDmode)
10107 /* We can use %d if the number is <32 bits and positive. */
10108 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10109 fprintf (file, "0x%lx%08lx",
10110 (unsigned long) CONST_DOUBLE_HIGH (x),
10111 (unsigned long) CONST_DOUBLE_LOW (x));
10113 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10116 /* We can't handle floating point constants;
10117 PRINT_OPERAND must handle them. */
10118 output_operand_lossage ("floating constant misused");
10122 /* Some assemblers need integer constants to appear first. */
10123 if (CONST_INT_P (XEXP (x, 0)))
10125 output_pic_addr_const (file, XEXP (x, 0), code);
10127 output_pic_addr_const (file, XEXP (x, 1), code);
10131 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10132 output_pic_addr_const (file, XEXP (x, 1), code);
10134 output_pic_addr_const (file, XEXP (x, 0), code);
10140 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10141 output_pic_addr_const (file, XEXP (x, 0), code);
10143 output_pic_addr_const (file, XEXP (x, 1), code);
10145 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10149 gcc_assert (XVECLEN (x, 0) == 1);
10150 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10151 switch (XINT (x, 1))
10154 fputs ("@GOT", file);
10156 case UNSPEC_GOTOFF:
10157 fputs ("@GOTOFF", file);
10159 case UNSPEC_PLTOFF:
10160 fputs ("@PLTOFF", file);
10162 case UNSPEC_GOTPCREL:
10163 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10164 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10166 case UNSPEC_GOTTPOFF:
10167 /* FIXME: This might be @TPOFF in Sun ld too. */
10168 fputs ("@GOTTPOFF", file);
10171 fputs ("@TPOFF", file);
10173 case UNSPEC_NTPOFF:
10175 fputs ("@TPOFF", file);
10177 fputs ("@NTPOFF", file);
10179 case UNSPEC_DTPOFF:
10180 fputs ("@DTPOFF", file);
10182 case UNSPEC_GOTNTPOFF:
10184 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10185 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10187 fputs ("@GOTNTPOFF", file);
10189 case UNSPEC_INDNTPOFF:
10190 fputs ("@INDNTPOFF", file);
10193 case UNSPEC_MACHOPIC_OFFSET:
10195 machopic_output_function_base_name (file);
10199 output_operand_lossage ("invalid UNSPEC as operand");
10205 output_operand_lossage ("invalid expression as operand");
10209 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10210 We need to emit DTP-relative relocations. */
10212 static void ATTRIBUTE_UNUSED
10213 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10215 fputs (ASM_LONG, file);
10216 output_addr_const (file, x);
10217 fputs ("@DTPOFF", file);
10223 fputs (", 0", file);
10226 gcc_unreachable ();
10230 /* Return true if X is a representation of the PIC register. This copes
10231 with calls from ix86_find_base_term, where the register might have
10232 been replaced by a cselib value. */
10235 ix86_pic_register_p (rtx x)
10237 if (GET_CODE (x) == VALUE)
10238 return (pic_offset_table_rtx
10239 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10241 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10244 /* In the name of slightly smaller debug output, and to cater to
10245 general assembler lossage, recognize PIC+GOTOFF and turn it back
10246 into a direct symbol reference.
10248 On Darwin, this is necessary to avoid a crash, because Darwin
10249 has a different PIC label for each routine but the DWARF debugging
10250 information is not associated with any particular routine, so it's
10251 necessary to remove references to the PIC label from RTL stored by
10252 the DWARF output code. */
10255 ix86_delegitimize_address (rtx orig_x)
10258 /* reg_addend is NULL or a multiple of some register. */
10259 rtx reg_addend = NULL_RTX;
10260 /* const_addend is NULL or a const_int. */
10261 rtx const_addend = NULL_RTX;
10262 /* This is the result, or NULL. */
10263 rtx result = NULL_RTX;
10270 if (GET_CODE (x) != CONST
10271 || GET_CODE (XEXP (x, 0)) != UNSPEC
10272 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10273 || !MEM_P (orig_x))
10275 return XVECEXP (XEXP (x, 0), 0, 0);
10278 if (GET_CODE (x) != PLUS
10279 || GET_CODE (XEXP (x, 1)) != CONST)
10282 if (ix86_pic_register_p (XEXP (x, 0)))
10283 /* %ebx + GOT/GOTOFF */
10285 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10287 /* %ebx + %reg * scale + GOT/GOTOFF */
10288 reg_addend = XEXP (x, 0);
10289 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10290 reg_addend = XEXP (reg_addend, 1);
10291 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10292 reg_addend = XEXP (reg_addend, 0);
10295 if (!REG_P (reg_addend)
10296 && GET_CODE (reg_addend) != MULT
10297 && GET_CODE (reg_addend) != ASHIFT)
10303 x = XEXP (XEXP (x, 1), 0);
10304 if (GET_CODE (x) == PLUS
10305 && CONST_INT_P (XEXP (x, 1)))
10307 const_addend = XEXP (x, 1);
10311 if (GET_CODE (x) == UNSPEC
10312 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10313 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10314 result = XVECEXP (x, 0, 0);
10316 if (TARGET_MACHO && darwin_local_data_pic (x)
10317 && !MEM_P (orig_x))
10318 result = XVECEXP (x, 0, 0);
10324 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10326 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10330 /* If X is a machine specific address (i.e. a symbol or label being
10331 referenced as a displacement from the GOT implemented using an
10332 UNSPEC), then return the base term. Otherwise return X. */
10335 ix86_find_base_term (rtx x)
10341 if (GET_CODE (x) != CONST)
10343 term = XEXP (x, 0);
10344 if (GET_CODE (term) == PLUS
10345 && (CONST_INT_P (XEXP (term, 1))
10346 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10347 term = XEXP (term, 0);
10348 if (GET_CODE (term) != UNSPEC
10349 || XINT (term, 1) != UNSPEC_GOTPCREL)
10352 return XVECEXP (term, 0, 0);
10355 return ix86_delegitimize_address (x);
10359 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10360 int fp, FILE *file)
10362 const char *suffix;
10364 if (mode == CCFPmode || mode == CCFPUmode)
10366 enum rtx_code second_code, bypass_code;
10367 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10368 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10369 code = ix86_fp_compare_code_to_integer (code);
10373 code = reverse_condition (code);
10424 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10428 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10429 Those same assemblers have the same but opposite lossage on cmov. */
10430 if (mode == CCmode)
10431 suffix = fp ? "nbe" : "a";
10432 else if (mode == CCCmode)
10435 gcc_unreachable ();
10451 gcc_unreachable ();
10455 gcc_assert (mode == CCmode || mode == CCCmode);
10472 gcc_unreachable ();
10476 /* ??? As above. */
10477 gcc_assert (mode == CCmode || mode == CCCmode);
10478 suffix = fp ? "nb" : "ae";
10481 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10485 /* ??? As above. */
10486 if (mode == CCmode)
10488 else if (mode == CCCmode)
10489 suffix = fp ? "nb" : "ae";
10491 gcc_unreachable ();
10494 suffix = fp ? "u" : "p";
10497 suffix = fp ? "nu" : "np";
10500 gcc_unreachable ();
10502 fputs (suffix, file);
10505 /* Print the name of register X to FILE based on its machine mode and number.
10506 If CODE is 'w', pretend the mode is HImode.
10507 If CODE is 'b', pretend the mode is QImode.
10508 If CODE is 'k', pretend the mode is SImode.
10509 If CODE is 'q', pretend the mode is DImode.
10510 If CODE is 'x', pretend the mode is V4SFmode.
10511 If CODE is 't', pretend the mode is V8SFmode.
10512 If CODE is 'h', pretend the reg is the 'high' byte register.
10513 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10514 If CODE is 'd', duplicate the operand for AVX instruction.
10518 print_reg (rtx x, int code, FILE *file)
10521 bool duplicated = code == 'd' && TARGET_AVX;
10523 gcc_assert (x == pc_rtx
10524 || (REGNO (x) != ARG_POINTER_REGNUM
10525 && REGNO (x) != FRAME_POINTER_REGNUM
10526 && REGNO (x) != FLAGS_REG
10527 && REGNO (x) != FPSR_REG
10528 && REGNO (x) != FPCR_REG));
10530 if (ASSEMBLER_DIALECT == ASM_ATT)
10535 gcc_assert (TARGET_64BIT);
10536 fputs ("rip", file);
10540 if (code == 'w' || MMX_REG_P (x))
10542 else if (code == 'b')
10544 else if (code == 'k')
10546 else if (code == 'q')
10548 else if (code == 'y')
10550 else if (code == 'h')
10552 else if (code == 'x')
10554 else if (code == 't')
10557 code = GET_MODE_SIZE (GET_MODE (x));
10559 /* Irritatingly, AMD extended registers use different naming convention
10560 from the normal registers. */
10561 if (REX_INT_REG_P (x))
10563 gcc_assert (TARGET_64BIT);
10567 error ("extended registers have no high halves");
10570 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10573 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10576 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10579 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10582 error ("unsupported operand size for extended register");
10592 if (STACK_TOP_P (x))
10601 if (! ANY_FP_REG_P (x))
10602 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10607 reg = hi_reg_name[REGNO (x)];
10610 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10612 reg = qi_reg_name[REGNO (x)];
10615 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10617 reg = qi_high_reg_name[REGNO (x)];
10622 gcc_assert (!duplicated);
10624 fputs (hi_reg_name[REGNO (x)] + 1, file);
10629 gcc_unreachable ();
10635 if (ASSEMBLER_DIALECT == ASM_ATT)
10636 fprintf (file, ", %%%s", reg);
10638 fprintf (file, ", %s", reg);
10642 /* Locate some local-dynamic symbol still in use by this function
10643 so that we can print its name in some tls_local_dynamic_base
10647 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10651 if (GET_CODE (x) == SYMBOL_REF
10652 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10654 cfun->machine->some_ld_name = XSTR (x, 0);
10661 static const char *
10662 get_some_local_dynamic_name (void)
10666 if (cfun->machine->some_ld_name)
10667 return cfun->machine->some_ld_name;
10669 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10671 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10672 return cfun->machine->some_ld_name;
10674 gcc_unreachable ();
10677 /* Meaning of CODE:
10678 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10679 C -- print opcode suffix for set/cmov insn.
10680 c -- like C, but print reversed condition
10681 E,e -- likewise, but for compare-and-branch fused insn.
10682 F,f -- likewise, but for floating-point.
10683 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10685 R -- print the prefix for register names.
10686 z -- print the opcode suffix for the size of the current operand.
10687 * -- print a star (in certain assembler syntax)
10688 A -- print an absolute memory reference.
10689 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10690 s -- print a shift double count, followed by the assemblers argument
10692 b -- print the QImode name of the register for the indicated operand.
10693 %b0 would print %al if operands[0] is reg 0.
10694 w -- likewise, print the HImode name of the register.
10695 k -- likewise, print the SImode name of the register.
10696 q -- likewise, print the DImode name of the register.
10697 x -- likewise, print the V4SFmode name of the register.
10698 t -- likewise, print the V8SFmode name of the register.
10699 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10700 y -- print "st(0)" instead of "st" as a register.
10701 d -- print duplicated register operand for AVX instruction.
10702 D -- print condition for SSE cmp instruction.
10703 P -- if PIC, print an @PLT suffix.
10704 X -- don't print any sort of PIC '@' suffix for a symbol.
10705 & -- print some in-use local-dynamic symbol name.
10706 H -- print a memory address offset by 8; used for sse high-parts
10707 Y -- print condition for SSE5 com* instruction.
10708 + -- print a branch hint as 'cs' or 'ds' prefix
10709 ; -- print a semicolon (after prefixes due to bug in older gas).
10713 print_operand (FILE *file, rtx x, int code)
10720 if (ASSEMBLER_DIALECT == ASM_ATT)
10725 assemble_name (file, get_some_local_dynamic_name ());
10729 switch (ASSEMBLER_DIALECT)
10736 /* Intel syntax. For absolute addresses, registers should not
10737 be surrounded by braces. */
10741 PRINT_OPERAND (file, x, 0);
10748 gcc_unreachable ();
10751 PRINT_OPERAND (file, x, 0);
10756 if (ASSEMBLER_DIALECT == ASM_ATT)
10761 if (ASSEMBLER_DIALECT == ASM_ATT)
10766 if (ASSEMBLER_DIALECT == ASM_ATT)
10771 if (ASSEMBLER_DIALECT == ASM_ATT)
10776 if (ASSEMBLER_DIALECT == ASM_ATT)
10781 if (ASSEMBLER_DIALECT == ASM_ATT)
10786 /* 387 opcodes don't get size suffixes if the operands are
10788 if (STACK_REG_P (x))
10791 /* Likewise if using Intel opcodes. */
10792 if (ASSEMBLER_DIALECT == ASM_INTEL)
10795 /* This is the size of op from size of operand. */
10796 switch (GET_MODE_SIZE (GET_MODE (x)))
10805 #ifdef HAVE_GAS_FILDS_FISTS
10815 if (GET_MODE (x) == SFmode)
10830 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10834 #ifdef GAS_MNEMONICS
10849 gcc_unreachable ();
10866 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10868 PRINT_OPERAND (file, x, 0);
10869 fputs (", ", file);
10874 /* Little bit of braindamage here. The SSE compare instructions
10875 does use completely different names for the comparisons that the
10876 fp conditional moves. */
10879 switch (GET_CODE (x))
10882 fputs ("eq", file);
10885 fputs ("eq_us", file);
10888 fputs ("lt", file);
10891 fputs ("nge", file);
10894 fputs ("le", file);
10897 fputs ("ngt", file);
10900 fputs ("unord", file);
10903 fputs ("neq", file);
10906 fputs ("neq_oq", file);
10909 fputs ("ge", file);
10912 fputs ("nlt", file);
10915 fputs ("gt", file);
10918 fputs ("nle", file);
10921 fputs ("ord", file);
10924 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10930 switch (GET_CODE (x))
10934 fputs ("eq", file);
10938 fputs ("lt", file);
10942 fputs ("le", file);
10945 fputs ("unord", file);
10949 fputs ("neq", file);
10953 fputs ("nlt", file);
10957 fputs ("nle", file);
10960 fputs ("ord", file);
10963 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10969 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10970 if (ASSEMBLER_DIALECT == ASM_ATT)
10972 switch (GET_MODE (x))
10974 case HImode: putc ('w', file); break;
10976 case SFmode: putc ('l', file); break;
10978 case DFmode: putc ('q', file); break;
10979 default: gcc_unreachable ();
10986 if (!COMPARISON_P (x))
10988 output_operand_lossage ("operand is neither a constant nor a "
10989 "condition code, invalid operand code "
10993 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
10996 if (!COMPARISON_P (x))
10998 output_operand_lossage ("operand is neither a constant nor a "
10999 "condition code, invalid operand code "
11003 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11004 if (ASSEMBLER_DIALECT == ASM_ATT)
11007 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11010 /* Like above, but reverse condition */
11012 /* Check to see if argument to %c is really a constant
11013 and not a condition code which needs to be reversed. */
11014 if (!COMPARISON_P (x))
11016 output_operand_lossage ("operand is neither a constant nor a "
11017 "condition code, invalid operand "
11021 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11024 if (!COMPARISON_P (x))
11026 output_operand_lossage ("operand is neither a constant nor a "
11027 "condition code, invalid operand "
11031 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11032 if (ASSEMBLER_DIALECT == ASM_ATT)
11035 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11039 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11043 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11047 /* It doesn't actually matter what mode we use here, as we're
11048 only going to use this for printing. */
11049 x = adjust_address_nv (x, DImode, 8);
11057 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11060 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11063 int pred_val = INTVAL (XEXP (x, 0));
11065 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11066 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11068 int taken = pred_val > REG_BR_PROB_BASE / 2;
11069 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11071 /* Emit hints only in the case default branch prediction
11072 heuristics would fail. */
11073 if (taken != cputaken)
11075 /* We use 3e (DS) prefix for taken branches and
11076 2e (CS) prefix for not taken branches. */
11078 fputs ("ds ; ", file);
11080 fputs ("cs ; ", file);
11088 switch (GET_CODE (x))
11091 fputs ("neq", file);
11094 fputs ("eq", file);
11098 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11102 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11106 fputs ("le", file);
11110 fputs ("lt", file);
11113 fputs ("unord", file);
11116 fputs ("ord", file);
11119 fputs ("ueq", file);
11122 fputs ("nlt", file);
11125 fputs ("nle", file);
11128 fputs ("ule", file);
11131 fputs ("ult", file);
11134 fputs ("une", file);
11137 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11144 fputs (" ; ", file);
11151 output_operand_lossage ("invalid operand code '%c'", code);
11156 print_reg (x, code, file);
11158 else if (MEM_P (x))
11160 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11161 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11162 && GET_MODE (x) != BLKmode)
11165 switch (GET_MODE_SIZE (GET_MODE (x)))
11167 case 1: size = "BYTE"; break;
11168 case 2: size = "WORD"; break;
11169 case 4: size = "DWORD"; break;
11170 case 8: size = "QWORD"; break;
11171 case 12: size = "XWORD"; break;
11173 if (GET_MODE (x) == XFmode)
11179 gcc_unreachable ();
11182 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11185 else if (code == 'w')
11187 else if (code == 'k')
11190 fputs (size, file);
11191 fputs (" PTR ", file);
11195 /* Avoid (%rip) for call operands. */
11196 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11197 && !CONST_INT_P (x))
11198 output_addr_const (file, x);
11199 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11200 output_operand_lossage ("invalid constraints for operand");
11202 output_address (x);
11205 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11210 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11211 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11213 if (ASSEMBLER_DIALECT == ASM_ATT)
11215 fprintf (file, "0x%08lx", (long unsigned int) l);
11218 /* These float cases don't actually occur as immediate operands. */
11219 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11223 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11224 fprintf (file, "%s", dstr);
11227 else if (GET_CODE (x) == CONST_DOUBLE
11228 && GET_MODE (x) == XFmode)
11232 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11233 fprintf (file, "%s", dstr);
11238 /* We have patterns that allow zero sets of memory, for instance.
11239 In 64-bit mode, we should probably support all 8-byte vectors,
11240 since we can in fact encode that into an immediate. */
11241 if (GET_CODE (x) == CONST_VECTOR)
11243 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11249 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11251 if (ASSEMBLER_DIALECT == ASM_ATT)
11254 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11255 || GET_CODE (x) == LABEL_REF)
11257 if (ASSEMBLER_DIALECT == ASM_ATT)
11260 fputs ("OFFSET FLAT:", file);
11263 if (CONST_INT_P (x))
11264 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11266 output_pic_addr_const (file, x, code);
11268 output_addr_const (file, x);
11272 /* Print a memory operand whose address is ADDR. */
11275 print_operand_address (FILE *file, rtx addr)
11277 struct ix86_address parts;
11278 rtx base, index, disp;
11280 int ok = ix86_decompose_address (addr, &parts);
11285 index = parts.index;
11287 scale = parts.scale;
11295 if (ASSEMBLER_DIALECT == ASM_ATT)
11297 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11300 gcc_unreachable ();
11303 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11304 if (TARGET_64BIT && !base && !index)
11308 if (GET_CODE (disp) == CONST
11309 && GET_CODE (XEXP (disp, 0)) == PLUS
11310 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11311 symbol = XEXP (XEXP (disp, 0), 0);
11313 if (GET_CODE (symbol) == LABEL_REF
11314 || (GET_CODE (symbol) == SYMBOL_REF
11315 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11318 if (!base && !index)
11320 /* Displacement only requires special attention. */
11322 if (CONST_INT_P (disp))
11324 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11325 fputs ("ds:", file);
11326 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11329 output_pic_addr_const (file, disp, 0);
11331 output_addr_const (file, disp);
11335 if (ASSEMBLER_DIALECT == ASM_ATT)
11340 output_pic_addr_const (file, disp, 0);
11341 else if (GET_CODE (disp) == LABEL_REF)
11342 output_asm_label (disp);
11344 output_addr_const (file, disp);
11349 print_reg (base, 0, file);
11353 print_reg (index, 0, file);
11355 fprintf (file, ",%d", scale);
11361 rtx offset = NULL_RTX;
11365 /* Pull out the offset of a symbol; print any symbol itself. */
11366 if (GET_CODE (disp) == CONST
11367 && GET_CODE (XEXP (disp, 0)) == PLUS
11368 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11370 offset = XEXP (XEXP (disp, 0), 1);
11371 disp = gen_rtx_CONST (VOIDmode,
11372 XEXP (XEXP (disp, 0), 0));
11376 output_pic_addr_const (file, disp, 0);
11377 else if (GET_CODE (disp) == LABEL_REF)
11378 output_asm_label (disp);
11379 else if (CONST_INT_P (disp))
11382 output_addr_const (file, disp);
11388 print_reg (base, 0, file);
11391 if (INTVAL (offset) >= 0)
11393 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11397 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11404 print_reg (index, 0, file);
11406 fprintf (file, "*%d", scale);
11414 output_addr_const_extra (FILE *file, rtx x)
11418 if (GET_CODE (x) != UNSPEC)
11421 op = XVECEXP (x, 0, 0);
11422 switch (XINT (x, 1))
11424 case UNSPEC_GOTTPOFF:
11425 output_addr_const (file, op);
11426 /* FIXME: This might be @TPOFF in Sun ld. */
11427 fputs ("@GOTTPOFF", file);
11430 output_addr_const (file, op);
11431 fputs ("@TPOFF", file);
11433 case UNSPEC_NTPOFF:
11434 output_addr_const (file, op);
11436 fputs ("@TPOFF", file);
11438 fputs ("@NTPOFF", file);
11440 case UNSPEC_DTPOFF:
11441 output_addr_const (file, op);
11442 fputs ("@DTPOFF", file);
11444 case UNSPEC_GOTNTPOFF:
11445 output_addr_const (file, op);
11447 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11448 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11450 fputs ("@GOTNTPOFF", file);
11452 case UNSPEC_INDNTPOFF:
11453 output_addr_const (file, op);
11454 fputs ("@INDNTPOFF", file);
11457 case UNSPEC_MACHOPIC_OFFSET:
11458 output_addr_const (file, op);
11460 machopic_output_function_base_name (file);
11471 /* Split one or more DImode RTL references into pairs of SImode
11472 references. The RTL can be REG, offsettable MEM, integer constant, or
11473 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11474 split and "num" is its length. lo_half and hi_half are output arrays
11475 that parallel "operands". */
11478 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11482 rtx op = operands[num];
11484 /* simplify_subreg refuse to split volatile memory addresses,
11485 but we still have to handle it. */
11488 lo_half[num] = adjust_address (op, SImode, 0);
11489 hi_half[num] = adjust_address (op, SImode, 4);
11493 lo_half[num] = simplify_gen_subreg (SImode, op,
11494 GET_MODE (op) == VOIDmode
11495 ? DImode : GET_MODE (op), 0);
11496 hi_half[num] = simplify_gen_subreg (SImode, op,
11497 GET_MODE (op) == VOIDmode
11498 ? DImode : GET_MODE (op), 4);
11502 /* Split one or more TImode RTL references into pairs of DImode
11503 references. The RTL can be REG, offsettable MEM, integer constant, or
11504 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11505 split and "num" is its length. lo_half and hi_half are output arrays
11506 that parallel "operands". */
11509 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11513 rtx op = operands[num];
11515 /* simplify_subreg refuse to split volatile memory addresses, but we
11516 still have to handle it. */
11519 lo_half[num] = adjust_address (op, DImode, 0);
11520 hi_half[num] = adjust_address (op, DImode, 8);
11524 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11525 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11530 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11531 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11532 is the expression of the binary operation. The output may either be
11533 emitted here, or returned to the caller, like all output_* functions.
11535 There is no guarantee that the operands are the same mode, as they
11536 might be within FLOAT or FLOAT_EXTEND expressions. */
11538 #ifndef SYSV386_COMPAT
11539 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11540 wants to fix the assemblers because that causes incompatibility
11541 with gcc. No-one wants to fix gcc because that causes
11542 incompatibility with assemblers... You can use the option of
11543 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11544 #define SYSV386_COMPAT 1
11548 output_387_binary_op (rtx insn, rtx *operands)
11550 static char buf[40];
11553 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11555 #ifdef ENABLE_CHECKING
11556 /* Even if we do not want to check the inputs, this documents input
11557 constraints. Which helps in understanding the following code. */
11558 if (STACK_REG_P (operands[0])
11559 && ((REG_P (operands[1])
11560 && REGNO (operands[0]) == REGNO (operands[1])
11561 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11562 || (REG_P (operands[2])
11563 && REGNO (operands[0]) == REGNO (operands[2])
11564 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11565 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11568 gcc_assert (is_sse);
11571 switch (GET_CODE (operands[3]))
11574 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11575 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11583 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11584 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11592 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11593 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11601 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11602 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11610 gcc_unreachable ();
11617 strcpy (buf, ssep);
11618 if (GET_MODE (operands[0]) == SFmode)
11619 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11621 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11625 strcpy (buf, ssep + 1);
11626 if (GET_MODE (operands[0]) == SFmode)
11627 strcat (buf, "ss\t{%2, %0|%0, %2}");
11629 strcat (buf, "sd\t{%2, %0|%0, %2}");
11635 switch (GET_CODE (operands[3]))
11639 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11641 rtx temp = operands[2];
11642 operands[2] = operands[1];
11643 operands[1] = temp;
11646 /* know operands[0] == operands[1]. */
11648 if (MEM_P (operands[2]))
11654 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11656 if (STACK_TOP_P (operands[0]))
11657 /* How is it that we are storing to a dead operand[2]?
11658 Well, presumably operands[1] is dead too. We can't
11659 store the result to st(0) as st(0) gets popped on this
11660 instruction. Instead store to operands[2] (which I
11661 think has to be st(1)). st(1) will be popped later.
11662 gcc <= 2.8.1 didn't have this check and generated
11663 assembly code that the Unixware assembler rejected. */
11664 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11666 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11670 if (STACK_TOP_P (operands[0]))
11671 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11673 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11678 if (MEM_P (operands[1]))
11684 if (MEM_P (operands[2]))
11690 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11693 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11694 derived assemblers, confusingly reverse the direction of
11695 the operation for fsub{r} and fdiv{r} when the
11696 destination register is not st(0). The Intel assembler
11697 doesn't have this brain damage. Read !SYSV386_COMPAT to
11698 figure out what the hardware really does. */
11699 if (STACK_TOP_P (operands[0]))
11700 p = "{p\t%0, %2|rp\t%2, %0}";
11702 p = "{rp\t%2, %0|p\t%0, %2}";
11704 if (STACK_TOP_P (operands[0]))
11705 /* As above for fmul/fadd, we can't store to st(0). */
11706 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11708 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11713 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11716 if (STACK_TOP_P (operands[0]))
11717 p = "{rp\t%0, %1|p\t%1, %0}";
11719 p = "{p\t%1, %0|rp\t%0, %1}";
11721 if (STACK_TOP_P (operands[0]))
11722 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11724 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11729 if (STACK_TOP_P (operands[0]))
11731 if (STACK_TOP_P (operands[1]))
11732 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11734 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11737 else if (STACK_TOP_P (operands[1]))
11740 p = "{\t%1, %0|r\t%0, %1}";
11742 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11748 p = "{r\t%2, %0|\t%0, %2}";
11750 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11756 gcc_unreachable ();
11763 /* Return needed mode for entity in optimize_mode_switching pass. */
11766 ix86_mode_needed (int entity, rtx insn)
11768 enum attr_i387_cw mode;
11770 /* The mode UNINITIALIZED is used to store control word after a
11771 function call or ASM pattern. The mode ANY specify that function
11772 has no requirements on the control word and make no changes in the
11773 bits we are interested in. */
11776 || (NONJUMP_INSN_P (insn)
11777 && (asm_noperands (PATTERN (insn)) >= 0
11778 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11779 return I387_CW_UNINITIALIZED;
11781 if (recog_memoized (insn) < 0)
11782 return I387_CW_ANY;
11784 mode = get_attr_i387_cw (insn);
11789 if (mode == I387_CW_TRUNC)
11794 if (mode == I387_CW_FLOOR)
11799 if (mode == I387_CW_CEIL)
11804 if (mode == I387_CW_MASK_PM)
11809 gcc_unreachable ();
11812 return I387_CW_ANY;
11815 /* Output code to initialize control word copies used by trunc?f?i and
11816 rounding patterns. CURRENT_MODE is set to current control word,
11817 while NEW_MODE is set to new control word. */
11820 emit_i387_cw_initialization (int mode)
11822 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11825 enum ix86_stack_slot slot;
11827 rtx reg = gen_reg_rtx (HImode);
11829 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11830 emit_move_insn (reg, copy_rtx (stored_mode));
11832 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11833 || optimize_function_for_size_p (cfun))
11837 case I387_CW_TRUNC:
11838 /* round toward zero (truncate) */
11839 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11840 slot = SLOT_CW_TRUNC;
11843 case I387_CW_FLOOR:
11844 /* round down toward -oo */
11845 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11846 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11847 slot = SLOT_CW_FLOOR;
11851 /* round up toward +oo */
11852 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11853 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11854 slot = SLOT_CW_CEIL;
11857 case I387_CW_MASK_PM:
11858 /* mask precision exception for nearbyint() */
11859 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11860 slot = SLOT_CW_MASK_PM;
11864 gcc_unreachable ();
11871 case I387_CW_TRUNC:
11872 /* round toward zero (truncate) */
11873 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11874 slot = SLOT_CW_TRUNC;
11877 case I387_CW_FLOOR:
11878 /* round down toward -oo */
11879 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11880 slot = SLOT_CW_FLOOR;
11884 /* round up toward +oo */
11885 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11886 slot = SLOT_CW_CEIL;
11889 case I387_CW_MASK_PM:
11890 /* mask precision exception for nearbyint() */
11891 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11892 slot = SLOT_CW_MASK_PM;
11896 gcc_unreachable ();
11900 gcc_assert (slot < MAX_386_STACK_LOCALS);
11902 new_mode = assign_386_stack_local (HImode, slot);
11903 emit_move_insn (new_mode, reg);
11906 /* Output code for INSN to convert a float to a signed int. OPERANDS
11907 are the insn operands. The output may be [HSD]Imode and the input
11908 operand may be [SDX]Fmode. */
11911 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11913 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11914 int dimode_p = GET_MODE (operands[0]) == DImode;
11915 int round_mode = get_attr_i387_cw (insn);
11917 /* Jump through a hoop or two for DImode, since the hardware has no
11918 non-popping instruction. We used to do this a different way, but
11919 that was somewhat fragile and broke with post-reload splitters. */
11920 if ((dimode_p || fisttp) && !stack_top_dies)
11921 output_asm_insn ("fld\t%y1", operands);
11923 gcc_assert (STACK_TOP_P (operands[1]));
11924 gcc_assert (MEM_P (operands[0]));
11925 gcc_assert (GET_MODE (operands[1]) != TFmode);
11928 output_asm_insn ("fisttp%z0\t%0", operands);
11931 if (round_mode != I387_CW_ANY)
11932 output_asm_insn ("fldcw\t%3", operands);
11933 if (stack_top_dies || dimode_p)
11934 output_asm_insn ("fistp%z0\t%0", operands);
11936 output_asm_insn ("fist%z0\t%0", operands);
11937 if (round_mode != I387_CW_ANY)
11938 output_asm_insn ("fldcw\t%2", operands);
11944 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11945 have the values zero or one, indicates the ffreep insn's operand
11946 from the OPERANDS array. */
11948 static const char *
11949 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11951 if (TARGET_USE_FFREEP)
11952 #if HAVE_AS_IX86_FFREEP
11953 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11956 static char retval[] = ".word\t0xc_df";
11957 int regno = REGNO (operands[opno]);
11959 gcc_assert (FP_REGNO_P (regno));
11961 retval[9] = '0' + (regno - FIRST_STACK_REG);
11966 return opno ? "fstp\t%y1" : "fstp\t%y0";
11970 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11971 should be used. UNORDERED_P is true when fucom should be used. */
11974 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
11976 int stack_top_dies;
11977 rtx cmp_op0, cmp_op1;
11978 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
11982 cmp_op0 = operands[0];
11983 cmp_op1 = operands[1];
11987 cmp_op0 = operands[1];
11988 cmp_op1 = operands[2];
11993 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
11994 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
11995 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
11996 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
11998 if (GET_MODE (operands[0]) == SFmode)
12000 return &ucomiss[TARGET_AVX ? 0 : 1];
12002 return &comiss[TARGET_AVX ? 0 : 1];
12005 return &ucomisd[TARGET_AVX ? 0 : 1];
12007 return &comisd[TARGET_AVX ? 0 : 1];
12010 gcc_assert (STACK_TOP_P (cmp_op0));
12012 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12014 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12016 if (stack_top_dies)
12018 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12019 return output_387_ffreep (operands, 1);
12022 return "ftst\n\tfnstsw\t%0";
12025 if (STACK_REG_P (cmp_op1)
12027 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12028 && REGNO (cmp_op1) != FIRST_STACK_REG)
12030 /* If both the top of the 387 stack dies, and the other operand
12031 is also a stack register that dies, then this must be a
12032 `fcompp' float compare */
12036 /* There is no double popping fcomi variant. Fortunately,
12037 eflags is immune from the fstp's cc clobbering. */
12039 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12041 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12042 return output_387_ffreep (operands, 0);
12047 return "fucompp\n\tfnstsw\t%0";
12049 return "fcompp\n\tfnstsw\t%0";
12054 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12056 static const char * const alt[16] =
12058 "fcom%z2\t%y2\n\tfnstsw\t%0",
12059 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12060 "fucom%z2\t%y2\n\tfnstsw\t%0",
12061 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12063 "ficom%z2\t%y2\n\tfnstsw\t%0",
12064 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12068 "fcomi\t{%y1, %0|%0, %y1}",
12069 "fcomip\t{%y1, %0|%0, %y1}",
12070 "fucomi\t{%y1, %0|%0, %y1}",
12071 "fucomip\t{%y1, %0|%0, %y1}",
12082 mask = eflags_p << 3;
12083 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12084 mask |= unordered_p << 1;
12085 mask |= stack_top_dies;
12087 gcc_assert (mask < 16);
12096 ix86_output_addr_vec_elt (FILE *file, int value)
12098 const char *directive = ASM_LONG;
12102 directive = ASM_QUAD;
12104 gcc_assert (!TARGET_64BIT);
12107 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12111 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12113 const char *directive = ASM_LONG;
12116 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12117 directive = ASM_QUAD;
12119 gcc_assert (!TARGET_64BIT);
12121 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12122 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12123 fprintf (file, "%s%s%d-%s%d\n",
12124 directive, LPREFIX, value, LPREFIX, rel);
12125 else if (HAVE_AS_GOTOFF_IN_DATA)
12126 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12128 else if (TARGET_MACHO)
12130 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12131 machopic_output_function_base_name (file);
12132 fprintf(file, "\n");
12136 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12137 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12140 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12144 ix86_expand_clear (rtx dest)
12148 /* We play register width games, which are only valid after reload. */
12149 gcc_assert (reload_completed);
12151 /* Avoid HImode and its attendant prefix byte. */
12152 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12153 dest = gen_rtx_REG (SImode, REGNO (dest));
12154 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12156 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12157 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12159 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12160 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12166 /* X is an unchanging MEM. If it is a constant pool reference, return
12167 the constant pool rtx, else NULL. */
12170 maybe_get_pool_constant (rtx x)
12172 x = ix86_delegitimize_address (XEXP (x, 0));
12174 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12175 return get_pool_constant (x);
12181 ix86_expand_move (enum machine_mode mode, rtx operands[])
12184 enum tls_model model;
12189 if (GET_CODE (op1) == SYMBOL_REF)
12191 model = SYMBOL_REF_TLS_MODEL (op1);
12194 op1 = legitimize_tls_address (op1, model, true);
12195 op1 = force_operand (op1, op0);
12199 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12200 && SYMBOL_REF_DLLIMPORT_P (op1))
12201 op1 = legitimize_dllimport_symbol (op1, false);
12203 else if (GET_CODE (op1) == CONST
12204 && GET_CODE (XEXP (op1, 0)) == PLUS
12205 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12207 rtx addend = XEXP (XEXP (op1, 0), 1);
12208 rtx symbol = XEXP (XEXP (op1, 0), 0);
12211 model = SYMBOL_REF_TLS_MODEL (symbol);
12213 tmp = legitimize_tls_address (symbol, model, true);
12214 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12215 && SYMBOL_REF_DLLIMPORT_P (symbol))
12216 tmp = legitimize_dllimport_symbol (symbol, true);
12220 tmp = force_operand (tmp, NULL);
12221 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12222 op0, 1, OPTAB_DIRECT);
12228 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12230 if (TARGET_MACHO && !TARGET_64BIT)
12235 rtx temp = ((reload_in_progress
12236 || ((op0 && REG_P (op0))
12238 ? op0 : gen_reg_rtx (Pmode));
12239 op1 = machopic_indirect_data_reference (op1, temp);
12240 op1 = machopic_legitimize_pic_address (op1, mode,
12241 temp == op1 ? 0 : temp);
12243 else if (MACHOPIC_INDIRECT)
12244 op1 = machopic_indirect_data_reference (op1, 0);
12252 op1 = force_reg (Pmode, op1);
12253 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12255 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12256 op1 = legitimize_pic_address (op1, reg);
12265 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12266 || !push_operand (op0, mode))
12268 op1 = force_reg (mode, op1);
12270 if (push_operand (op0, mode)
12271 && ! general_no_elim_operand (op1, mode))
12272 op1 = copy_to_mode_reg (mode, op1);
12274 /* Force large constants in 64bit compilation into register
12275 to get them CSEed. */
12276 if (can_create_pseudo_p ()
12277 && (mode == DImode) && TARGET_64BIT
12278 && immediate_operand (op1, mode)
12279 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12280 && !register_operand (op0, mode)
12282 op1 = copy_to_mode_reg (mode, op1);
12284 if (can_create_pseudo_p ()
12285 && FLOAT_MODE_P (mode)
12286 && GET_CODE (op1) == CONST_DOUBLE)
12288 /* If we are loading a floating point constant to a register,
12289 force the value to memory now, since we'll get better code
12290 out the back end. */
12292 op1 = validize_mem (force_const_mem (mode, op1));
12293 if (!register_operand (op0, mode))
12295 rtx temp = gen_reg_rtx (mode);
12296 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12297 emit_move_insn (op0, temp);
12303 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12307 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12309 rtx op0 = operands[0], op1 = operands[1];
12310 unsigned int align = GET_MODE_ALIGNMENT (mode);
12312 /* Force constants other than zero into memory. We do not know how
12313 the instructions used to build constants modify the upper 64 bits
12314 of the register, once we have that information we may be able
12315 to handle some of them more efficiently. */
12316 if (can_create_pseudo_p ()
12317 && register_operand (op0, mode)
12318 && (CONSTANT_P (op1)
12319 || (GET_CODE (op1) == SUBREG
12320 && CONSTANT_P (SUBREG_REG (op1))))
12321 && standard_sse_constant_p (op1) <= 0)
12322 op1 = validize_mem (force_const_mem (mode, op1));
12324 /* We need to check memory alignment for SSE mode since attribute
12325 can make operands unaligned. */
12326 if (can_create_pseudo_p ()
12327 && SSE_REG_MODE_P (mode)
12328 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12329 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12333 /* ix86_expand_vector_move_misalign() does not like constants ... */
12334 if (CONSTANT_P (op1)
12335 || (GET_CODE (op1) == SUBREG
12336 && CONSTANT_P (SUBREG_REG (op1))))
12337 op1 = validize_mem (force_const_mem (mode, op1));
12339 /* ... nor both arguments in memory. */
12340 if (!register_operand (op0, mode)
12341 && !register_operand (op1, mode))
12342 op1 = force_reg (mode, op1);
12344 tmp[0] = op0; tmp[1] = op1;
12345 ix86_expand_vector_move_misalign (mode, tmp);
12349 /* Make operand1 a register if it isn't already. */
12350 if (can_create_pseudo_p ()
12351 && !register_operand (op0, mode)
12352 && !register_operand (op1, mode))
12354 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12358 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12361 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12362 straight to ix86_expand_vector_move. */
12363 /* Code generation for scalar reg-reg moves of single and double precision data:
12364 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12368 if (x86_sse_partial_reg_dependency == true)
12373 Code generation for scalar loads of double precision data:
12374 if (x86_sse_split_regs == true)
12375 movlpd mem, reg (gas syntax)
12379 Code generation for unaligned packed loads of single precision data
12380 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12381 if (x86_sse_unaligned_move_optimal)
12384 if (x86_sse_partial_reg_dependency == true)
12396 Code generation for unaligned packed loads of double precision data
12397 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12398 if (x86_sse_unaligned_move_optimal)
12401 if (x86_sse_split_regs == true)
12414 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12423 switch (GET_MODE_CLASS (mode))
12425 case MODE_VECTOR_INT:
12427 switch (GET_MODE_SIZE (mode))
12430 op0 = gen_lowpart (V16QImode, op0);
12431 op1 = gen_lowpart (V16QImode, op1);
12432 emit_insn (gen_avx_movdqu (op0, op1));
12435 op0 = gen_lowpart (V32QImode, op0);
12436 op1 = gen_lowpart (V32QImode, op1);
12437 emit_insn (gen_avx_movdqu256 (op0, op1));
12440 gcc_unreachable ();
12443 case MODE_VECTOR_FLOAT:
12444 op0 = gen_lowpart (mode, op0);
12445 op1 = gen_lowpart (mode, op1);
12450 emit_insn (gen_avx_movups (op0, op1));
12453 emit_insn (gen_avx_movups256 (op0, op1));
12456 emit_insn (gen_avx_movupd (op0, op1));
12459 emit_insn (gen_avx_movupd256 (op0, op1));
12462 gcc_unreachable ();
12467 gcc_unreachable ();
12475 /* If we're optimizing for size, movups is the smallest. */
12476 if (optimize_insn_for_size_p ())
12478 op0 = gen_lowpart (V4SFmode, op0);
12479 op1 = gen_lowpart (V4SFmode, op1);
12480 emit_insn (gen_sse_movups (op0, op1));
12484 /* ??? If we have typed data, then it would appear that using
12485 movdqu is the only way to get unaligned data loaded with
12487 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12489 op0 = gen_lowpart (V16QImode, op0);
12490 op1 = gen_lowpart (V16QImode, op1);
12491 emit_insn (gen_sse2_movdqu (op0, op1));
12495 if (TARGET_SSE2 && mode == V2DFmode)
12499 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12501 op0 = gen_lowpart (V2DFmode, op0);
12502 op1 = gen_lowpart (V2DFmode, op1);
12503 emit_insn (gen_sse2_movupd (op0, op1));
12507 /* When SSE registers are split into halves, we can avoid
12508 writing to the top half twice. */
12509 if (TARGET_SSE_SPLIT_REGS)
12511 emit_clobber (op0);
12516 /* ??? Not sure about the best option for the Intel chips.
12517 The following would seem to satisfy; the register is
12518 entirely cleared, breaking the dependency chain. We
12519 then store to the upper half, with a dependency depth
12520 of one. A rumor has it that Intel recommends two movsd
12521 followed by an unpacklpd, but this is unconfirmed. And
12522 given that the dependency depth of the unpacklpd would
12523 still be one, I'm not sure why this would be better. */
12524 zero = CONST0_RTX (V2DFmode);
12527 m = adjust_address (op1, DFmode, 0);
12528 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12529 m = adjust_address (op1, DFmode, 8);
12530 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12534 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12536 op0 = gen_lowpart (V4SFmode, op0);
12537 op1 = gen_lowpart (V4SFmode, op1);
12538 emit_insn (gen_sse_movups (op0, op1));
12542 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12543 emit_move_insn (op0, CONST0_RTX (mode));
12545 emit_clobber (op0);
12547 if (mode != V4SFmode)
12548 op0 = gen_lowpart (V4SFmode, op0);
12549 m = adjust_address (op1, V2SFmode, 0);
12550 emit_insn (gen_sse_loadlps (op0, op0, m));
12551 m = adjust_address (op1, V2SFmode, 8);
12552 emit_insn (gen_sse_loadhps (op0, op0, m));
12555 else if (MEM_P (op0))
12557 /* If we're optimizing for size, movups is the smallest. */
12558 if (optimize_insn_for_size_p ())
12560 op0 = gen_lowpart (V4SFmode, op0);
12561 op1 = gen_lowpart (V4SFmode, op1);
12562 emit_insn (gen_sse_movups (op0, op1));
12566 /* ??? Similar to above, only less clear because of quote
12567 typeless stores unquote. */
12568 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12569 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12571 op0 = gen_lowpart (V16QImode, op0);
12572 op1 = gen_lowpart (V16QImode, op1);
12573 emit_insn (gen_sse2_movdqu (op0, op1));
12577 if (TARGET_SSE2 && mode == V2DFmode)
12579 m = adjust_address (op0, DFmode, 0);
12580 emit_insn (gen_sse2_storelpd (m, op1));
12581 m = adjust_address (op0, DFmode, 8);
12582 emit_insn (gen_sse2_storehpd (m, op1));
12586 if (mode != V4SFmode)
12587 op1 = gen_lowpart (V4SFmode, op1);
12588 m = adjust_address (op0, V2SFmode, 0);
12589 emit_insn (gen_sse_storelps (m, op1));
12590 m = adjust_address (op0, V2SFmode, 8);
12591 emit_insn (gen_sse_storehps (m, op1));
12595 gcc_unreachable ();
12598 /* Expand a push in MODE. This is some mode for which we do not support
12599 proper push instructions, at least from the registers that we expect
12600 the value to live in. */
12603 ix86_expand_push (enum machine_mode mode, rtx x)
12607 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12608 GEN_INT (-GET_MODE_SIZE (mode)),
12609 stack_pointer_rtx, 1, OPTAB_DIRECT);
12610 if (tmp != stack_pointer_rtx)
12611 emit_move_insn (stack_pointer_rtx, tmp);
12613 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12615 /* When we push an operand onto stack, it has to be aligned at least
12616 at the function argument boundary. */
12617 set_mem_align (tmp,
12618 ix86_function_arg_boundary (mode, NULL_TREE));
12620 emit_move_insn (tmp, x);
12623 /* Helper function of ix86_fixup_binary_operands to canonicalize
12624 operand order. Returns true if the operands should be swapped. */
12627 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12630 rtx dst = operands[0];
12631 rtx src1 = operands[1];
12632 rtx src2 = operands[2];
12634 /* If the operation is not commutative, we can't do anything. */
12635 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12638 /* Highest priority is that src1 should match dst. */
12639 if (rtx_equal_p (dst, src1))
12641 if (rtx_equal_p (dst, src2))
12644 /* Next highest priority is that immediate constants come second. */
12645 if (immediate_operand (src2, mode))
12647 if (immediate_operand (src1, mode))
12650 /* Lowest priority is that memory references should come second. */
12660 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12661 destination to use for the operation. If different from the true
12662 destination in operands[0], a copy operation will be required. */
12665 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12668 rtx dst = operands[0];
12669 rtx src1 = operands[1];
12670 rtx src2 = operands[2];
12672 /* Canonicalize operand order. */
12673 if (ix86_swap_binary_operands_p (code, mode, operands))
12677 /* It is invalid to swap operands of different modes. */
12678 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12685 /* Both source operands cannot be in memory. */
12686 if (MEM_P (src1) && MEM_P (src2))
12688 /* Optimization: Only read from memory once. */
12689 if (rtx_equal_p (src1, src2))
12691 src2 = force_reg (mode, src2);
12695 src2 = force_reg (mode, src2);
12698 /* If the destination is memory, and we do not have matching source
12699 operands, do things in registers. */
12700 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12701 dst = gen_reg_rtx (mode);
12703 /* Source 1 cannot be a constant. */
12704 if (CONSTANT_P (src1))
12705 src1 = force_reg (mode, src1);
12707 /* Source 1 cannot be a non-matching memory. */
12708 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12709 src1 = force_reg (mode, src1);
12711 operands[1] = src1;
12712 operands[2] = src2;
12716 /* Similarly, but assume that the destination has already been
12717 set up properly. */
12720 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12721 enum machine_mode mode, rtx operands[])
12723 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12724 gcc_assert (dst == operands[0]);
12727 /* Attempt to expand a binary operator. Make the expansion closer to the
12728 actual machine, then just general_operand, which will allow 3 separate
12729 memory references (one output, two input) in a single insn. */
12732 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12735 rtx src1, src2, dst, op, clob;
12737 dst = ix86_fixup_binary_operands (code, mode, operands);
12738 src1 = operands[1];
12739 src2 = operands[2];
12741 /* Emit the instruction. */
12743 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12744 if (reload_in_progress)
12746 /* Reload doesn't know about the flags register, and doesn't know that
12747 it doesn't want to clobber it. We can only do this with PLUS. */
12748 gcc_assert (code == PLUS);
12753 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12754 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12757 /* Fix up the destination if needed. */
12758 if (dst != operands[0])
12759 emit_move_insn (operands[0], dst);
12762 /* Return TRUE or FALSE depending on whether the binary operator meets the
12763 appropriate constraints. */
12766 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12769 rtx dst = operands[0];
12770 rtx src1 = operands[1];
12771 rtx src2 = operands[2];
12773 /* Both source operands cannot be in memory. */
12774 if (MEM_P (src1) && MEM_P (src2))
12777 /* Canonicalize operand order for commutative operators. */
12778 if (ix86_swap_binary_operands_p (code, mode, operands))
12785 /* If the destination is memory, we must have a matching source operand. */
12786 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12789 /* Source 1 cannot be a constant. */
12790 if (CONSTANT_P (src1))
12793 /* Source 1 cannot be a non-matching memory. */
12794 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12800 /* Attempt to expand a unary operator. Make the expansion closer to the
12801 actual machine, then just general_operand, which will allow 2 separate
12802 memory references (one output, one input) in a single insn. */
12805 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12808 int matching_memory;
12809 rtx src, dst, op, clob;
12814 /* If the destination is memory, and we do not have matching source
12815 operands, do things in registers. */
12816 matching_memory = 0;
12819 if (rtx_equal_p (dst, src))
12820 matching_memory = 1;
12822 dst = gen_reg_rtx (mode);
12825 /* When source operand is memory, destination must match. */
12826 if (MEM_P (src) && !matching_memory)
12827 src = force_reg (mode, src);
12829 /* Emit the instruction. */
12831 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12832 if (reload_in_progress || code == NOT)
12834 /* Reload doesn't know about the flags register, and doesn't know that
12835 it doesn't want to clobber it. */
12836 gcc_assert (code == NOT);
12841 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12842 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12845 /* Fix up the destination if needed. */
12846 if (dst != operands[0])
12847 emit_move_insn (operands[0], dst);
12850 /* Return TRUE or FALSE depending on whether the unary operator meets the
12851 appropriate constraints. */
12854 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12855 enum machine_mode mode ATTRIBUTE_UNUSED,
12856 rtx operands[2] ATTRIBUTE_UNUSED)
12858 /* If one of operands is memory, source and destination must match. */
12859 if ((MEM_P (operands[0])
12860 || MEM_P (operands[1]))
12861 && ! rtx_equal_p (operands[0], operands[1]))
12866 /* Post-reload splitter for converting an SF or DFmode value in an
12867 SSE register into an unsigned SImode. */
12870 ix86_split_convert_uns_si_sse (rtx operands[])
12872 enum machine_mode vecmode;
12873 rtx value, large, zero_or_two31, input, two31, x;
12875 large = operands[1];
12876 zero_or_two31 = operands[2];
12877 input = operands[3];
12878 two31 = operands[4];
12879 vecmode = GET_MODE (large);
12880 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12882 /* Load up the value into the low element. We must ensure that the other
12883 elements are valid floats -- zero is the easiest such value. */
12886 if (vecmode == V4SFmode)
12887 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12889 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12893 input = gen_rtx_REG (vecmode, REGNO (input));
12894 emit_move_insn (value, CONST0_RTX (vecmode));
12895 if (vecmode == V4SFmode)
12896 emit_insn (gen_sse_movss (value, value, input));
12898 emit_insn (gen_sse2_movsd (value, value, input));
12901 emit_move_insn (large, two31);
12902 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12904 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12905 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12907 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12908 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12910 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12911 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12913 large = gen_rtx_REG (V4SImode, REGNO (large));
12914 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12916 x = gen_rtx_REG (V4SImode, REGNO (value));
12917 if (vecmode == V4SFmode)
12918 emit_insn (gen_sse2_cvttps2dq (x, value));
12920 emit_insn (gen_sse2_cvttpd2dq (x, value));
12923 emit_insn (gen_xorv4si3 (value, value, large));
12926 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12927 Expects the 64-bit DImode to be supplied in a pair of integral
12928 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12929 -mfpmath=sse, !optimize_size only. */
12932 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12934 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12935 rtx int_xmm, fp_xmm;
12936 rtx biases, exponents;
12939 int_xmm = gen_reg_rtx (V4SImode);
12940 if (TARGET_INTER_UNIT_MOVES)
12941 emit_insn (gen_movdi_to_sse (int_xmm, input));
12942 else if (TARGET_SSE_SPLIT_REGS)
12944 emit_clobber (int_xmm);
12945 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12949 x = gen_reg_rtx (V2DImode);
12950 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12951 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12954 x = gen_rtx_CONST_VECTOR (V4SImode,
12955 gen_rtvec (4, GEN_INT (0x43300000UL),
12956 GEN_INT (0x45300000UL),
12957 const0_rtx, const0_rtx));
12958 exponents = validize_mem (force_const_mem (V4SImode, x));
12960 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12961 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
12963 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12964 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12965 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12966 (0x1.0p84 + double(fp_value_hi_xmm)).
12967 Note these exponents differ by 32. */
12969 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
12971 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12972 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12973 real_ldexp (&bias_lo_rvt, &dconst1, 52);
12974 real_ldexp (&bias_hi_rvt, &dconst1, 84);
12975 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
12976 x = const_double_from_real_value (bias_hi_rvt, DFmode);
12977 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
12978 biases = validize_mem (force_const_mem (V2DFmode, biases));
12979 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
12981 /* Add the upper and lower DFmode values together. */
12983 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
12986 x = copy_to_mode_reg (V2DFmode, fp_xmm);
12987 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
12988 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
12991 ix86_expand_vector_extract (false, target, fp_xmm, 0);
12994 /* Not used, but eases macroization of patterns. */
12996 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
12997 rtx input ATTRIBUTE_UNUSED)
12999 gcc_unreachable ();
13002 /* Convert an unsigned SImode value into a DFmode. Only currently used
13003 for SSE, but applicable anywhere. */
13006 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13008 REAL_VALUE_TYPE TWO31r;
13011 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13012 NULL, 1, OPTAB_DIRECT);
13014 fp = gen_reg_rtx (DFmode);
13015 emit_insn (gen_floatsidf2 (fp, x));
13017 real_ldexp (&TWO31r, &dconst1, 31);
13018 x = const_double_from_real_value (TWO31r, DFmode);
13020 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13022 emit_move_insn (target, x);
13025 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13026 32-bit mode; otherwise we have a direct convert instruction. */
13029 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13031 REAL_VALUE_TYPE TWO32r;
13032 rtx fp_lo, fp_hi, x;
13034 fp_lo = gen_reg_rtx (DFmode);
13035 fp_hi = gen_reg_rtx (DFmode);
13037 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13039 real_ldexp (&TWO32r, &dconst1, 32);
13040 x = const_double_from_real_value (TWO32r, DFmode);
13041 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13043 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13045 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13048 emit_move_insn (target, x);
13051 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13052 For x86_32, -mfpmath=sse, !optimize_size only. */
13054 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13056 REAL_VALUE_TYPE ONE16r;
13057 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13059 real_ldexp (&ONE16r, &dconst1, 16);
13060 x = const_double_from_real_value (ONE16r, SFmode);
13061 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13062 NULL, 0, OPTAB_DIRECT);
13063 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13064 NULL, 0, OPTAB_DIRECT);
13065 fp_hi = gen_reg_rtx (SFmode);
13066 fp_lo = gen_reg_rtx (SFmode);
13067 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13068 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13069 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13071 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13073 if (!rtx_equal_p (target, fp_hi))
13074 emit_move_insn (target, fp_hi);
13077 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13078 then replicate the value for all elements of the vector
13082 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13089 v = gen_rtvec (4, value, value, value, value);
13090 return gen_rtx_CONST_VECTOR (V4SImode, v);
13094 v = gen_rtvec (2, value, value);
13095 return gen_rtx_CONST_VECTOR (V2DImode, v);
13099 v = gen_rtvec (4, value, value, value, value);
13101 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13102 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13103 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13107 v = gen_rtvec (2, value, value);
13109 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13110 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13113 gcc_unreachable ();
13117 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13118 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13119 for an SSE register. If VECT is true, then replicate the mask for
13120 all elements of the vector register. If INVERT is true, then create
13121 a mask excluding the sign bit. */
13124 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13126 enum machine_mode vec_mode, imode;
13127 HOST_WIDE_INT hi, lo;
13132 /* Find the sign bit, sign extended to 2*HWI. */
13138 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13139 lo = 0x80000000, hi = lo < 0;
13145 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13146 if (HOST_BITS_PER_WIDE_INT >= 64)
13147 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13149 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13154 vec_mode = VOIDmode;
13155 if (HOST_BITS_PER_WIDE_INT >= 64)
13158 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13165 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13169 lo = ~lo, hi = ~hi;
13175 mask = immed_double_const (lo, hi, imode);
13177 vec = gen_rtvec (2, v, mask);
13178 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13179 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13186 gcc_unreachable ();
13190 lo = ~lo, hi = ~hi;
13192 /* Force this value into the low part of a fp vector constant. */
13193 mask = immed_double_const (lo, hi, imode);
13194 mask = gen_lowpart (mode, mask);
13196 if (vec_mode == VOIDmode)
13197 return force_reg (mode, mask);
13199 v = ix86_build_const_vector (mode, vect, mask);
13200 return force_reg (vec_mode, v);
13203 /* Generate code for floating point ABS or NEG. */
13206 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13209 rtx mask, set, use, clob, dst, src;
13210 bool use_sse = false;
13211 bool vector_mode = VECTOR_MODE_P (mode);
13212 enum machine_mode elt_mode = mode;
13216 elt_mode = GET_MODE_INNER (mode);
13219 else if (mode == TFmode)
13221 else if (TARGET_SSE_MATH)
13222 use_sse = SSE_FLOAT_MODE_P (mode);
13224 /* NEG and ABS performed with SSE use bitwise mask operations.
13225 Create the appropriate mask now. */
13227 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13236 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13237 set = gen_rtx_SET (VOIDmode, dst, set);
13242 set = gen_rtx_fmt_e (code, mode, src);
13243 set = gen_rtx_SET (VOIDmode, dst, set);
13246 use = gen_rtx_USE (VOIDmode, mask);
13247 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13248 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13249 gen_rtvec (3, set, use, clob)));
13256 /* Expand a copysign operation. Special case operand 0 being a constant. */
13259 ix86_expand_copysign (rtx operands[])
13261 enum machine_mode mode;
13262 rtx dest, op0, op1, mask, nmask;
13264 dest = operands[0];
13268 mode = GET_MODE (dest);
13270 if (GET_CODE (op0) == CONST_DOUBLE)
13272 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13274 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13275 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13277 if (mode == SFmode || mode == DFmode)
13279 enum machine_mode vmode;
13281 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13283 if (op0 == CONST0_RTX (mode))
13284 op0 = CONST0_RTX (vmode);
13289 if (mode == SFmode)
13290 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13291 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13293 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13295 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13298 else if (op0 != CONST0_RTX (mode))
13299 op0 = force_reg (mode, op0);
13301 mask = ix86_build_signbit_mask (mode, 0, 0);
13303 if (mode == SFmode)
13304 copysign_insn = gen_copysignsf3_const;
13305 else if (mode == DFmode)
13306 copysign_insn = gen_copysigndf3_const;
13308 copysign_insn = gen_copysigntf3_const;
13310 emit_insn (copysign_insn (dest, op0, op1, mask));
13314 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13316 nmask = ix86_build_signbit_mask (mode, 0, 1);
13317 mask = ix86_build_signbit_mask (mode, 0, 0);
13319 if (mode == SFmode)
13320 copysign_insn = gen_copysignsf3_var;
13321 else if (mode == DFmode)
13322 copysign_insn = gen_copysigndf3_var;
13324 copysign_insn = gen_copysigntf3_var;
13326 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13330 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13331 be a constant, and so has already been expanded into a vector constant. */
13334 ix86_split_copysign_const (rtx operands[])
13336 enum machine_mode mode, vmode;
13337 rtx dest, op0, op1, mask, x;
13339 dest = operands[0];
13342 mask = operands[3];
13344 mode = GET_MODE (dest);
13345 vmode = GET_MODE (mask);
13347 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13348 x = gen_rtx_AND (vmode, dest, mask);
13349 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13351 if (op0 != CONST0_RTX (vmode))
13353 x = gen_rtx_IOR (vmode, dest, op0);
13354 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13358 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13359 so we have to do two masks. */
13362 ix86_split_copysign_var (rtx operands[])
13364 enum machine_mode mode, vmode;
13365 rtx dest, scratch, op0, op1, mask, nmask, x;
13367 dest = operands[0];
13368 scratch = operands[1];
13371 nmask = operands[4];
13372 mask = operands[5];
13374 mode = GET_MODE (dest);
13375 vmode = GET_MODE (mask);
13377 if (rtx_equal_p (op0, op1))
13379 /* Shouldn't happen often (it's useless, obviously), but when it does
13380 we'd generate incorrect code if we continue below. */
13381 emit_move_insn (dest, op0);
13385 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13387 gcc_assert (REGNO (op1) == REGNO (scratch));
13389 x = gen_rtx_AND (vmode, scratch, mask);
13390 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13393 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13394 x = gen_rtx_NOT (vmode, dest);
13395 x = gen_rtx_AND (vmode, x, op0);
13396 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13400 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13402 x = gen_rtx_AND (vmode, scratch, mask);
13404 else /* alternative 2,4 */
13406 gcc_assert (REGNO (mask) == REGNO (scratch));
13407 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13408 x = gen_rtx_AND (vmode, scratch, op1);
13410 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13412 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13414 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13415 x = gen_rtx_AND (vmode, dest, nmask);
13417 else /* alternative 3,4 */
13419 gcc_assert (REGNO (nmask) == REGNO (dest));
13421 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13422 x = gen_rtx_AND (vmode, dest, op0);
13424 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13427 x = gen_rtx_IOR (vmode, dest, scratch);
13428 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13431 /* Return TRUE or FALSE depending on whether the first SET in INSN
13432 has source and destination with matching CC modes, and that the
13433 CC mode is at least as constrained as REQ_MODE. */
13436 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13439 enum machine_mode set_mode;
13441 set = PATTERN (insn);
13442 if (GET_CODE (set) == PARALLEL)
13443 set = XVECEXP (set, 0, 0);
13444 gcc_assert (GET_CODE (set) == SET);
13445 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13447 set_mode = GET_MODE (SET_DEST (set));
13451 if (req_mode != CCNOmode
13452 && (req_mode != CCmode
13453 || XEXP (SET_SRC (set), 1) != const0_rtx))
13457 if (req_mode == CCGCmode)
13461 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13465 if (req_mode == CCZmode)
13476 gcc_unreachable ();
13479 return (GET_MODE (SET_SRC (set)) == set_mode);
13482 /* Generate insn patterns to do an integer compare of OPERANDS. */
13485 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13487 enum machine_mode cmpmode;
13490 cmpmode = SELECT_CC_MODE (code, op0, op1);
13491 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13493 /* This is very simple, but making the interface the same as in the
13494 FP case makes the rest of the code easier. */
13495 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13496 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13498 /* Return the test that should be put into the flags user, i.e.
13499 the bcc, scc, or cmov instruction. */
13500 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13503 /* Figure out whether to use ordered or unordered fp comparisons.
13504 Return the appropriate mode to use. */
13507 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13509 /* ??? In order to make all comparisons reversible, we do all comparisons
13510 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13511 all forms trapping and nontrapping comparisons, we can make inequality
13512 comparisons trapping again, since it results in better code when using
13513 FCOM based compares. */
13514 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13518 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13520 enum machine_mode mode = GET_MODE (op0);
13522 if (SCALAR_FLOAT_MODE_P (mode))
13524 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13525 return ix86_fp_compare_mode (code);
13530 /* Only zero flag is needed. */
13531 case EQ: /* ZF=0 */
13532 case NE: /* ZF!=0 */
13534 /* Codes needing carry flag. */
13535 case GEU: /* CF=0 */
13536 case LTU: /* CF=1 */
13537 /* Detect overflow checks. They need just the carry flag. */
13538 if (GET_CODE (op0) == PLUS
13539 && rtx_equal_p (op1, XEXP (op0, 0)))
13543 case GTU: /* CF=0 & ZF=0 */
13544 case LEU: /* CF=1 | ZF=1 */
13545 /* Detect overflow checks. They need just the carry flag. */
13546 if (GET_CODE (op0) == MINUS
13547 && rtx_equal_p (op1, XEXP (op0, 0)))
13551 /* Codes possibly doable only with sign flag when
13552 comparing against zero. */
13553 case GE: /* SF=OF or SF=0 */
13554 case LT: /* SF<>OF or SF=1 */
13555 if (op1 == const0_rtx)
13558 /* For other cases Carry flag is not required. */
13560 /* Codes doable only with sign flag when comparing
13561 against zero, but we miss jump instruction for it
13562 so we need to use relational tests against overflow
13563 that thus needs to be zero. */
13564 case GT: /* ZF=0 & SF=OF */
13565 case LE: /* ZF=1 | SF<>OF */
13566 if (op1 == const0_rtx)
13570 /* strcmp pattern do (use flags) and combine may ask us for proper
13575 gcc_unreachable ();
13579 /* Return the fixed registers used for condition codes. */
13582 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13589 /* If two condition code modes are compatible, return a condition code
13590 mode which is compatible with both. Otherwise, return
13593 static enum machine_mode
13594 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13599 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13602 if ((m1 == CCGCmode && m2 == CCGOCmode)
13603 || (m1 == CCGOCmode && m2 == CCGCmode))
13609 gcc_unreachable ();
13639 /* These are only compatible with themselves, which we already
13645 /* Split comparison code CODE into comparisons we can do using branch
13646 instructions. BYPASS_CODE is comparison code for branch that will
13647 branch around FIRST_CODE and SECOND_CODE. If some of branches
13648 is not required, set value to UNKNOWN.
13649 We never require more than two branches. */
13652 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13653 enum rtx_code *first_code,
13654 enum rtx_code *second_code)
13656 *first_code = code;
13657 *bypass_code = UNKNOWN;
13658 *second_code = UNKNOWN;
13660 /* The fcomi comparison sets flags as follows:
13670 case GT: /* GTU - CF=0 & ZF=0 */
13671 case GE: /* GEU - CF=0 */
13672 case ORDERED: /* PF=0 */
13673 case UNORDERED: /* PF=1 */
13674 case UNEQ: /* EQ - ZF=1 */
13675 case UNLT: /* LTU - CF=1 */
13676 case UNLE: /* LEU - CF=1 | ZF=1 */
13677 case LTGT: /* EQ - ZF=0 */
13679 case LT: /* LTU - CF=1 - fails on unordered */
13680 *first_code = UNLT;
13681 *bypass_code = UNORDERED;
13683 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13684 *first_code = UNLE;
13685 *bypass_code = UNORDERED;
13687 case EQ: /* EQ - ZF=1 - fails on unordered */
13688 *first_code = UNEQ;
13689 *bypass_code = UNORDERED;
13691 case NE: /* NE - ZF=0 - fails on unordered */
13692 *first_code = LTGT;
13693 *second_code = UNORDERED;
13695 case UNGE: /* GEU - CF=0 - fails on unordered */
13697 *second_code = UNORDERED;
13699 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13701 *second_code = UNORDERED;
13704 gcc_unreachable ();
13706 if (!TARGET_IEEE_FP)
13708 *second_code = UNKNOWN;
13709 *bypass_code = UNKNOWN;
13713 /* Return cost of comparison done fcom + arithmetics operations on AX.
13714 All following functions do use number of instructions as a cost metrics.
13715 In future this should be tweaked to compute bytes for optimize_size and
13716 take into account performance of various instructions on various CPUs. */
13718 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13720 if (!TARGET_IEEE_FP)
13722 /* The cost of code output by ix86_expand_fp_compare. */
13746 gcc_unreachable ();
13750 /* Return cost of comparison done using fcomi operation.
13751 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13753 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13755 enum rtx_code bypass_code, first_code, second_code;
13756 /* Return arbitrarily high cost when instruction is not supported - this
13757 prevents gcc from using it. */
13760 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13761 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13764 /* Return cost of comparison done using sahf operation.
13765 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13767 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13769 enum rtx_code bypass_code, first_code, second_code;
13770 /* Return arbitrarily high cost when instruction is not preferred - this
13771 avoids gcc from using it. */
13772 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13774 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13775 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13778 /* Compute cost of the comparison done using any method.
13779 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13781 ix86_fp_comparison_cost (enum rtx_code code)
13783 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13786 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13787 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13789 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13790 if (min > sahf_cost)
13792 if (min > fcomi_cost)
13797 /* Return true if we should use an FCOMI instruction for this
13801 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13803 enum rtx_code swapped_code = swap_condition (code);
13805 return ((ix86_fp_comparison_cost (code)
13806 == ix86_fp_comparison_fcomi_cost (code))
13807 || (ix86_fp_comparison_cost (swapped_code)
13808 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13811 /* Swap, force into registers, or otherwise massage the two operands
13812 to a fp comparison. The operands are updated in place; the new
13813 comparison code is returned. */
13815 static enum rtx_code
13816 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13818 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13819 rtx op0 = *pop0, op1 = *pop1;
13820 enum machine_mode op_mode = GET_MODE (op0);
13821 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13823 /* All of the unordered compare instructions only work on registers.
13824 The same is true of the fcomi compare instructions. The XFmode
13825 compare instructions require registers except when comparing
13826 against zero or when converting operand 1 from fixed point to
13830 && (fpcmp_mode == CCFPUmode
13831 || (op_mode == XFmode
13832 && ! (standard_80387_constant_p (op0) == 1
13833 || standard_80387_constant_p (op1) == 1)
13834 && GET_CODE (op1) != FLOAT)
13835 || ix86_use_fcomi_compare (code)))
13837 op0 = force_reg (op_mode, op0);
13838 op1 = force_reg (op_mode, op1);
13842 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13843 things around if they appear profitable, otherwise force op0
13844 into a register. */
13846 if (standard_80387_constant_p (op0) == 0
13848 && ! (standard_80387_constant_p (op1) == 0
13852 tmp = op0, op0 = op1, op1 = tmp;
13853 code = swap_condition (code);
13857 op0 = force_reg (op_mode, op0);
13859 if (CONSTANT_P (op1))
13861 int tmp = standard_80387_constant_p (op1);
13863 op1 = validize_mem (force_const_mem (op_mode, op1));
13867 op1 = force_reg (op_mode, op1);
13870 op1 = force_reg (op_mode, op1);
13874 /* Try to rearrange the comparison to make it cheaper. */
13875 if (ix86_fp_comparison_cost (code)
13876 > ix86_fp_comparison_cost (swap_condition (code))
13877 && (REG_P (op1) || can_create_pseudo_p ()))
13880 tmp = op0, op0 = op1, op1 = tmp;
13881 code = swap_condition (code);
13883 op0 = force_reg (op_mode, op0);
13891 /* Convert comparison codes we use to represent FP comparison to integer
13892 code that will result in proper branch. Return UNKNOWN if no such code
13896 ix86_fp_compare_code_to_integer (enum rtx_code code)
13925 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13928 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13929 rtx *second_test, rtx *bypass_test)
13931 enum machine_mode fpcmp_mode, intcmp_mode;
13933 int cost = ix86_fp_comparison_cost (code);
13934 enum rtx_code bypass_code, first_code, second_code;
13936 fpcmp_mode = ix86_fp_compare_mode (code);
13937 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13940 *second_test = NULL_RTX;
13942 *bypass_test = NULL_RTX;
13944 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13946 /* Do fcomi/sahf based test when profitable. */
13947 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13948 && (bypass_code == UNKNOWN || bypass_test)
13949 && (second_code == UNKNOWN || second_test))
13951 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13952 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13958 gcc_assert (TARGET_SAHF);
13961 scratch = gen_reg_rtx (HImode);
13962 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
13964 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
13967 /* The FP codes work out to act like unsigned. */
13968 intcmp_mode = fpcmp_mode;
13970 if (bypass_code != UNKNOWN)
13971 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
13972 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13974 if (second_code != UNKNOWN)
13975 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
13976 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13981 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13982 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13983 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
13985 scratch = gen_reg_rtx (HImode);
13986 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
13988 /* In the unordered case, we have to check C2 for NaN's, which
13989 doesn't happen to work out to anything nice combination-wise.
13990 So do some bit twiddling on the value we've got in AH to come
13991 up with an appropriate set of condition codes. */
13993 intcmp_mode = CCNOmode;
13998 if (code == GT || !TARGET_IEEE_FP)
14000 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14005 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14006 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14007 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14008 intcmp_mode = CCmode;
14014 if (code == LT && TARGET_IEEE_FP)
14016 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14017 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14018 intcmp_mode = CCmode;
14023 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14029 if (code == GE || !TARGET_IEEE_FP)
14031 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14036 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14037 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14044 if (code == LE && TARGET_IEEE_FP)
14046 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14047 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14048 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14049 intcmp_mode = CCmode;
14054 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14060 if (code == EQ && TARGET_IEEE_FP)
14062 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14063 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14064 intcmp_mode = CCmode;
14069 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14076 if (code == NE && TARGET_IEEE_FP)
14078 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14079 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14085 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14091 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14095 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14100 gcc_unreachable ();
14104 /* Return the test that should be put into the flags user, i.e.
14105 the bcc, scc, or cmov instruction. */
14106 return gen_rtx_fmt_ee (code, VOIDmode,
14107 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14112 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14115 op0 = ix86_compare_op0;
14116 op1 = ix86_compare_op1;
14119 *second_test = NULL_RTX;
14121 *bypass_test = NULL_RTX;
14123 if (ix86_compare_emitted)
14125 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14126 ix86_compare_emitted = NULL_RTX;
14128 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14130 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14131 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14132 second_test, bypass_test);
14135 ret = ix86_expand_int_compare (code, op0, op1);
14140 /* Return true if the CODE will result in nontrivial jump sequence. */
14142 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14144 enum rtx_code bypass_code, first_code, second_code;
14147 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14148 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14152 ix86_expand_branch (enum rtx_code code, rtx label)
14156 /* If we have emitted a compare insn, go straight to simple.
14157 ix86_expand_compare won't emit anything if ix86_compare_emitted
14159 if (ix86_compare_emitted)
14162 switch (GET_MODE (ix86_compare_op0))
14168 tmp = ix86_expand_compare (code, NULL, NULL);
14169 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14170 gen_rtx_LABEL_REF (VOIDmode, label),
14172 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14181 enum rtx_code bypass_code, first_code, second_code;
14183 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14184 &ix86_compare_op1);
14186 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14188 /* Check whether we will use the natural sequence with one jump. If
14189 so, we can expand jump early. Otherwise delay expansion by
14190 creating compound insn to not confuse optimizers. */
14191 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14193 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14194 gen_rtx_LABEL_REF (VOIDmode, label),
14195 pc_rtx, NULL_RTX, NULL_RTX);
14199 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14200 ix86_compare_op0, ix86_compare_op1);
14201 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14202 gen_rtx_LABEL_REF (VOIDmode, label),
14204 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14206 use_fcomi = ix86_use_fcomi_compare (code);
14207 vec = rtvec_alloc (3 + !use_fcomi);
14208 RTVEC_ELT (vec, 0) = tmp;
14210 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14212 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14215 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14217 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14226 /* Expand DImode branch into multiple compare+branch. */
14228 rtx lo[2], hi[2], label2;
14229 enum rtx_code code1, code2, code3;
14230 enum machine_mode submode;
14232 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14234 tmp = ix86_compare_op0;
14235 ix86_compare_op0 = ix86_compare_op1;
14236 ix86_compare_op1 = tmp;
14237 code = swap_condition (code);
14239 if (GET_MODE (ix86_compare_op0) == DImode)
14241 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14242 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14247 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14248 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14252 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14253 avoid two branches. This costs one extra insn, so disable when
14254 optimizing for size. */
14256 if ((code == EQ || code == NE)
14257 && (!optimize_insn_for_size_p ()
14258 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14263 if (hi[1] != const0_rtx)
14264 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14265 NULL_RTX, 0, OPTAB_WIDEN);
14268 if (lo[1] != const0_rtx)
14269 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14270 NULL_RTX, 0, OPTAB_WIDEN);
14272 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14273 NULL_RTX, 0, OPTAB_WIDEN);
14275 ix86_compare_op0 = tmp;
14276 ix86_compare_op1 = const0_rtx;
14277 ix86_expand_branch (code, label);
14281 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14282 op1 is a constant and the low word is zero, then we can just
14283 examine the high word. Similarly for low word -1 and
14284 less-or-equal-than or greater-than. */
14286 if (CONST_INT_P (hi[1]))
14289 case LT: case LTU: case GE: case GEU:
14290 if (lo[1] == const0_rtx)
14292 ix86_compare_op0 = hi[0];
14293 ix86_compare_op1 = hi[1];
14294 ix86_expand_branch (code, label);
14298 case LE: case LEU: case GT: case GTU:
14299 if (lo[1] == constm1_rtx)
14301 ix86_compare_op0 = hi[0];
14302 ix86_compare_op1 = hi[1];
14303 ix86_expand_branch (code, label);
14311 /* Otherwise, we need two or three jumps. */
14313 label2 = gen_label_rtx ();
14316 code2 = swap_condition (code);
14317 code3 = unsigned_condition (code);
14321 case LT: case GT: case LTU: case GTU:
14324 case LE: code1 = LT; code2 = GT; break;
14325 case GE: code1 = GT; code2 = LT; break;
14326 case LEU: code1 = LTU; code2 = GTU; break;
14327 case GEU: code1 = GTU; code2 = LTU; break;
14329 case EQ: code1 = UNKNOWN; code2 = NE; break;
14330 case NE: code2 = UNKNOWN; break;
14333 gcc_unreachable ();
14338 * if (hi(a) < hi(b)) goto true;
14339 * if (hi(a) > hi(b)) goto false;
14340 * if (lo(a) < lo(b)) goto true;
14344 ix86_compare_op0 = hi[0];
14345 ix86_compare_op1 = hi[1];
14347 if (code1 != UNKNOWN)
14348 ix86_expand_branch (code1, label);
14349 if (code2 != UNKNOWN)
14350 ix86_expand_branch (code2, label2);
14352 ix86_compare_op0 = lo[0];
14353 ix86_compare_op1 = lo[1];
14354 ix86_expand_branch (code3, label);
14356 if (code2 != UNKNOWN)
14357 emit_label (label2);
14362 gcc_unreachable ();
14366 /* Split branch based on floating point condition. */
14368 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14369 rtx target1, rtx target2, rtx tmp, rtx pushed)
14371 rtx second, bypass;
14372 rtx label = NULL_RTX;
14374 int bypass_probability = -1, second_probability = -1, probability = -1;
14377 if (target2 != pc_rtx)
14380 code = reverse_condition_maybe_unordered (code);
14385 condition = ix86_expand_fp_compare (code, op1, op2,
14386 tmp, &second, &bypass);
14388 /* Remove pushed operand from stack. */
14390 ix86_free_from_memory (GET_MODE (pushed));
14392 if (split_branch_probability >= 0)
14394 /* Distribute the probabilities across the jumps.
14395 Assume the BYPASS and SECOND to be always test
14397 probability = split_branch_probability;
14399 /* Value of 1 is low enough to make no need for probability
14400 to be updated. Later we may run some experiments and see
14401 if unordered values are more frequent in practice. */
14403 bypass_probability = 1;
14405 second_probability = 1;
14407 if (bypass != NULL_RTX)
14409 label = gen_label_rtx ();
14410 i = emit_jump_insn (gen_rtx_SET
14412 gen_rtx_IF_THEN_ELSE (VOIDmode,
14414 gen_rtx_LABEL_REF (VOIDmode,
14417 if (bypass_probability >= 0)
14419 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14420 GEN_INT (bypass_probability),
14423 i = emit_jump_insn (gen_rtx_SET
14425 gen_rtx_IF_THEN_ELSE (VOIDmode,
14426 condition, target1, target2)));
14427 if (probability >= 0)
14429 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14430 GEN_INT (probability),
14432 if (second != NULL_RTX)
14434 i = emit_jump_insn (gen_rtx_SET
14436 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14438 if (second_probability >= 0)
14440 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14441 GEN_INT (second_probability),
14444 if (label != NULL_RTX)
14445 emit_label (label);
14449 ix86_expand_setcc (enum rtx_code code, rtx dest)
14451 rtx ret, tmp, tmpreg, equiv;
14452 rtx second_test, bypass_test;
14454 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14455 return 0; /* FAIL */
14457 gcc_assert (GET_MODE (dest) == QImode);
14459 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14460 PUT_MODE (ret, QImode);
14465 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14466 if (bypass_test || second_test)
14468 rtx test = second_test;
14470 rtx tmp2 = gen_reg_rtx (QImode);
14473 gcc_assert (!second_test);
14474 test = bypass_test;
14476 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14478 PUT_MODE (test, QImode);
14479 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14482 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14484 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14487 /* Attach a REG_EQUAL note describing the comparison result. */
14488 if (ix86_compare_op0 && ix86_compare_op1)
14490 equiv = simplify_gen_relational (code, QImode,
14491 GET_MODE (ix86_compare_op0),
14492 ix86_compare_op0, ix86_compare_op1);
14493 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14496 return 1; /* DONE */
14499 /* Expand comparison setting or clearing carry flag. Return true when
14500 successful and set pop for the operation. */
14502 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14504 enum machine_mode mode =
14505 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14507 /* Do not handle DImode compares that go through special path. */
14508 if (mode == (TARGET_64BIT ? TImode : DImode))
14511 if (SCALAR_FLOAT_MODE_P (mode))
14513 rtx second_test = NULL, bypass_test = NULL;
14514 rtx compare_op, compare_seq;
14516 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14518 /* Shortcut: following common codes never translate
14519 into carry flag compares. */
14520 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14521 || code == ORDERED || code == UNORDERED)
14524 /* These comparisons require zero flag; swap operands so they won't. */
14525 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14526 && !TARGET_IEEE_FP)
14531 code = swap_condition (code);
14534 /* Try to expand the comparison and verify that we end up with
14535 carry flag based comparison. This fails to be true only when
14536 we decide to expand comparison using arithmetic that is not
14537 too common scenario. */
14539 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14540 &second_test, &bypass_test);
14541 compare_seq = get_insns ();
14544 if (second_test || bypass_test)
14547 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14548 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14549 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14551 code = GET_CODE (compare_op);
14553 if (code != LTU && code != GEU)
14556 emit_insn (compare_seq);
14561 if (!INTEGRAL_MODE_P (mode))
14570 /* Convert a==0 into (unsigned)a<1. */
14573 if (op1 != const0_rtx)
14576 code = (code == EQ ? LTU : GEU);
14579 /* Convert a>b into b<a or a>=b-1. */
14582 if (CONST_INT_P (op1))
14584 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14585 /* Bail out on overflow. We still can swap operands but that
14586 would force loading of the constant into register. */
14587 if (op1 == const0_rtx
14588 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14590 code = (code == GTU ? GEU : LTU);
14597 code = (code == GTU ? LTU : GEU);
14601 /* Convert a>=0 into (unsigned)a<0x80000000. */
14604 if (mode == DImode || op1 != const0_rtx)
14606 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14607 code = (code == LT ? GEU : LTU);
14611 if (mode == DImode || op1 != constm1_rtx)
14613 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14614 code = (code == LE ? GEU : LTU);
14620 /* Swapping operands may cause constant to appear as first operand. */
14621 if (!nonimmediate_operand (op0, VOIDmode))
14623 if (!can_create_pseudo_p ())
14625 op0 = force_reg (mode, op0);
14627 ix86_compare_op0 = op0;
14628 ix86_compare_op1 = op1;
14629 *pop = ix86_expand_compare (code, NULL, NULL);
14630 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14635 ix86_expand_int_movcc (rtx operands[])
14637 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14638 rtx compare_seq, compare_op;
14639 rtx second_test, bypass_test;
14640 enum machine_mode mode = GET_MODE (operands[0]);
14641 bool sign_bit_compare_p = false;;
14644 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14645 compare_seq = get_insns ();
14648 compare_code = GET_CODE (compare_op);
14650 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14651 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14652 sign_bit_compare_p = true;
14654 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14655 HImode insns, we'd be swallowed in word prefix ops. */
14657 if ((mode != HImode || TARGET_FAST_PREFIX)
14658 && (mode != (TARGET_64BIT ? TImode : DImode))
14659 && CONST_INT_P (operands[2])
14660 && CONST_INT_P (operands[3]))
14662 rtx out = operands[0];
14663 HOST_WIDE_INT ct = INTVAL (operands[2]);
14664 HOST_WIDE_INT cf = INTVAL (operands[3]);
14665 HOST_WIDE_INT diff;
14668 /* Sign bit compares are better done using shifts than we do by using
14670 if (sign_bit_compare_p
14671 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14672 ix86_compare_op1, &compare_op))
14674 /* Detect overlap between destination and compare sources. */
14677 if (!sign_bit_compare_p)
14679 bool fpcmp = false;
14681 compare_code = GET_CODE (compare_op);
14683 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14684 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14687 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14690 /* To simplify rest of code, restrict to the GEU case. */
14691 if (compare_code == LTU)
14693 HOST_WIDE_INT tmp = ct;
14696 compare_code = reverse_condition (compare_code);
14697 code = reverse_condition (code);
14702 PUT_CODE (compare_op,
14703 reverse_condition_maybe_unordered
14704 (GET_CODE (compare_op)));
14706 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14710 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14711 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14712 tmp = gen_reg_rtx (mode);
14714 if (mode == DImode)
14715 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14717 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14721 if (code == GT || code == GE)
14722 code = reverse_condition (code);
14725 HOST_WIDE_INT tmp = ct;
14730 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14731 ix86_compare_op1, VOIDmode, 0, -1);
14744 tmp = expand_simple_binop (mode, PLUS,
14746 copy_rtx (tmp), 1, OPTAB_DIRECT);
14757 tmp = expand_simple_binop (mode, IOR,
14759 copy_rtx (tmp), 1, OPTAB_DIRECT);
14761 else if (diff == -1 && ct)
14771 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14773 tmp = expand_simple_binop (mode, PLUS,
14774 copy_rtx (tmp), GEN_INT (cf),
14775 copy_rtx (tmp), 1, OPTAB_DIRECT);
14783 * andl cf - ct, dest
14793 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14796 tmp = expand_simple_binop (mode, AND,
14798 gen_int_mode (cf - ct, mode),
14799 copy_rtx (tmp), 1, OPTAB_DIRECT);
14801 tmp = expand_simple_binop (mode, PLUS,
14802 copy_rtx (tmp), GEN_INT (ct),
14803 copy_rtx (tmp), 1, OPTAB_DIRECT);
14806 if (!rtx_equal_p (tmp, out))
14807 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14809 return 1; /* DONE */
14814 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14817 tmp = ct, ct = cf, cf = tmp;
14820 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14822 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14824 /* We may be reversing unordered compare to normal compare, that
14825 is not valid in general (we may convert non-trapping condition
14826 to trapping one), however on i386 we currently emit all
14827 comparisons unordered. */
14828 compare_code = reverse_condition_maybe_unordered (compare_code);
14829 code = reverse_condition_maybe_unordered (code);
14833 compare_code = reverse_condition (compare_code);
14834 code = reverse_condition (code);
14838 compare_code = UNKNOWN;
14839 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14840 && CONST_INT_P (ix86_compare_op1))
14842 if (ix86_compare_op1 == const0_rtx
14843 && (code == LT || code == GE))
14844 compare_code = code;
14845 else if (ix86_compare_op1 == constm1_rtx)
14849 else if (code == GT)
14854 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14855 if (compare_code != UNKNOWN
14856 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14857 && (cf == -1 || ct == -1))
14859 /* If lea code below could be used, only optimize
14860 if it results in a 2 insn sequence. */
14862 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14863 || diff == 3 || diff == 5 || diff == 9)
14864 || (compare_code == LT && ct == -1)
14865 || (compare_code == GE && cf == -1))
14868 * notl op1 (if necessary)
14876 code = reverse_condition (code);
14879 out = emit_store_flag (out, code, ix86_compare_op0,
14880 ix86_compare_op1, VOIDmode, 0, -1);
14882 out = expand_simple_binop (mode, IOR,
14884 out, 1, OPTAB_DIRECT);
14885 if (out != operands[0])
14886 emit_move_insn (operands[0], out);
14888 return 1; /* DONE */
14893 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14894 || diff == 3 || diff == 5 || diff == 9)
14895 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14897 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14903 * lea cf(dest*(ct-cf)),dest
14907 * This also catches the degenerate setcc-only case.
14913 out = emit_store_flag (out, code, ix86_compare_op0,
14914 ix86_compare_op1, VOIDmode, 0, 1);
14917 /* On x86_64 the lea instruction operates on Pmode, so we need
14918 to get arithmetics done in proper mode to match. */
14920 tmp = copy_rtx (out);
14924 out1 = copy_rtx (out);
14925 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14929 tmp = gen_rtx_PLUS (mode, tmp, out1);
14935 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14938 if (!rtx_equal_p (tmp, out))
14941 out = force_operand (tmp, copy_rtx (out));
14943 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14945 if (!rtx_equal_p (out, operands[0]))
14946 emit_move_insn (operands[0], copy_rtx (out));
14948 return 1; /* DONE */
14952 * General case: Jumpful:
14953 * xorl dest,dest cmpl op1, op2
14954 * cmpl op1, op2 movl ct, dest
14955 * setcc dest jcc 1f
14956 * decl dest movl cf, dest
14957 * andl (cf-ct),dest 1:
14960 * Size 20. Size 14.
14962 * This is reasonably steep, but branch mispredict costs are
14963 * high on modern cpus, so consider failing only if optimizing
14967 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14968 && BRANCH_COST (optimize_insn_for_speed_p (),
14973 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14978 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14980 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14982 /* We may be reversing unordered compare to normal compare,
14983 that is not valid in general (we may convert non-trapping
14984 condition to trapping one), however on i386 we currently
14985 emit all comparisons unordered. */
14986 code = reverse_condition_maybe_unordered (code);
14990 code = reverse_condition (code);
14991 if (compare_code != UNKNOWN)
14992 compare_code = reverse_condition (compare_code);
14996 if (compare_code != UNKNOWN)
14998 /* notl op1 (if needed)
15003 For x < 0 (resp. x <= -1) there will be no notl,
15004 so if possible swap the constants to get rid of the
15006 True/false will be -1/0 while code below (store flag
15007 followed by decrement) is 0/-1, so the constants need
15008 to be exchanged once more. */
15010 if (compare_code == GE || !cf)
15012 code = reverse_condition (code);
15017 HOST_WIDE_INT tmp = cf;
15022 out = emit_store_flag (out, code, ix86_compare_op0,
15023 ix86_compare_op1, VOIDmode, 0, -1);
15027 out = emit_store_flag (out, code, ix86_compare_op0,
15028 ix86_compare_op1, VOIDmode, 0, 1);
15030 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15031 copy_rtx (out), 1, OPTAB_DIRECT);
15034 out = expand_simple_binop (mode, AND, copy_rtx (out),
15035 gen_int_mode (cf - ct, mode),
15036 copy_rtx (out), 1, OPTAB_DIRECT);
15038 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15039 copy_rtx (out), 1, OPTAB_DIRECT);
15040 if (!rtx_equal_p (out, operands[0]))
15041 emit_move_insn (operands[0], copy_rtx (out));
15043 return 1; /* DONE */
15047 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15049 /* Try a few things more with specific constants and a variable. */
15052 rtx var, orig_out, out, tmp;
15054 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15055 return 0; /* FAIL */
15057 /* If one of the two operands is an interesting constant, load a
15058 constant with the above and mask it in with a logical operation. */
15060 if (CONST_INT_P (operands[2]))
15063 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15064 operands[3] = constm1_rtx, op = and_optab;
15065 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15066 operands[3] = const0_rtx, op = ior_optab;
15068 return 0; /* FAIL */
15070 else if (CONST_INT_P (operands[3]))
15073 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15074 operands[2] = constm1_rtx, op = and_optab;
15075 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15076 operands[2] = const0_rtx, op = ior_optab;
15078 return 0; /* FAIL */
15081 return 0; /* FAIL */
15083 orig_out = operands[0];
15084 tmp = gen_reg_rtx (mode);
15087 /* Recurse to get the constant loaded. */
15088 if (ix86_expand_int_movcc (operands) == 0)
15089 return 0; /* FAIL */
15091 /* Mask in the interesting variable. */
15092 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15094 if (!rtx_equal_p (out, orig_out))
15095 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15097 return 1; /* DONE */
15101 * For comparison with above,
15111 if (! nonimmediate_operand (operands[2], mode))
15112 operands[2] = force_reg (mode, operands[2]);
15113 if (! nonimmediate_operand (operands[3], mode))
15114 operands[3] = force_reg (mode, operands[3]);
15116 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15118 rtx tmp = gen_reg_rtx (mode);
15119 emit_move_insn (tmp, operands[3]);
15122 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15124 rtx tmp = gen_reg_rtx (mode);
15125 emit_move_insn (tmp, operands[2]);
15129 if (! register_operand (operands[2], VOIDmode)
15131 || ! register_operand (operands[3], VOIDmode)))
15132 operands[2] = force_reg (mode, operands[2]);
15135 && ! register_operand (operands[3], VOIDmode))
15136 operands[3] = force_reg (mode, operands[3]);
15138 emit_insn (compare_seq);
15139 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15140 gen_rtx_IF_THEN_ELSE (mode,
15141 compare_op, operands[2],
15144 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15145 gen_rtx_IF_THEN_ELSE (mode,
15147 copy_rtx (operands[3]),
15148 copy_rtx (operands[0]))));
15150 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15151 gen_rtx_IF_THEN_ELSE (mode,
15153 copy_rtx (operands[2]),
15154 copy_rtx (operands[0]))));
15156 return 1; /* DONE */
15159 /* Swap, force into registers, or otherwise massage the two operands
15160 to an sse comparison with a mask result. Thus we differ a bit from
15161 ix86_prepare_fp_compare_args which expects to produce a flags result.
15163 The DEST operand exists to help determine whether to commute commutative
15164 operators. The POP0/POP1 operands are updated in place. The new
15165 comparison code is returned, or UNKNOWN if not implementable. */
15167 static enum rtx_code
15168 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15169 rtx *pop0, rtx *pop1)
15177 /* We have no LTGT as an operator. We could implement it with
15178 NE & ORDERED, but this requires an extra temporary. It's
15179 not clear that it's worth it. */
15186 /* These are supported directly. */
15193 /* For commutative operators, try to canonicalize the destination
15194 operand to be first in the comparison - this helps reload to
15195 avoid extra moves. */
15196 if (!dest || !rtx_equal_p (dest, *pop1))
15204 /* These are not supported directly. Swap the comparison operands
15205 to transform into something that is supported. */
15209 code = swap_condition (code);
15213 gcc_unreachable ();
15219 /* Detect conditional moves that exactly match min/max operational
15220 semantics. Note that this is IEEE safe, as long as we don't
15221 interchange the operands.
15223 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15224 and TRUE if the operation is successful and instructions are emitted. */
15227 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15228 rtx cmp_op1, rtx if_true, rtx if_false)
15230 enum machine_mode mode;
15236 else if (code == UNGE)
15239 if_true = if_false;
15245 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15247 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15252 mode = GET_MODE (dest);
15254 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15255 but MODE may be a vector mode and thus not appropriate. */
15256 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15258 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15261 if_true = force_reg (mode, if_true);
15262 v = gen_rtvec (2, if_true, if_false);
15263 tmp = gen_rtx_UNSPEC (mode, v, u);
15267 code = is_min ? SMIN : SMAX;
15268 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15271 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15275 /* Expand an sse vector comparison. Return the register with the result. */
15278 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15279 rtx op_true, rtx op_false)
15281 enum machine_mode mode = GET_MODE (dest);
15284 cmp_op0 = force_reg (mode, cmp_op0);
15285 if (!nonimmediate_operand (cmp_op1, mode))
15286 cmp_op1 = force_reg (mode, cmp_op1);
15289 || reg_overlap_mentioned_p (dest, op_true)
15290 || reg_overlap_mentioned_p (dest, op_false))
15291 dest = gen_reg_rtx (mode);
15293 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15294 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15299 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15300 operations. This is used for both scalar and vector conditional moves. */
15303 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15305 enum machine_mode mode = GET_MODE (dest);
15308 if (op_false == CONST0_RTX (mode))
15310 op_true = force_reg (mode, op_true);
15311 x = gen_rtx_AND (mode, cmp, op_true);
15312 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15314 else if (op_true == CONST0_RTX (mode))
15316 op_false = force_reg (mode, op_false);
15317 x = gen_rtx_NOT (mode, cmp);
15318 x = gen_rtx_AND (mode, x, op_false);
15319 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15321 else if (TARGET_SSE5)
15323 rtx pcmov = gen_rtx_SET (mode, dest,
15324 gen_rtx_IF_THEN_ELSE (mode, cmp,
15331 op_true = force_reg (mode, op_true);
15332 op_false = force_reg (mode, op_false);
15334 t2 = gen_reg_rtx (mode);
15336 t3 = gen_reg_rtx (mode);
15340 x = gen_rtx_AND (mode, op_true, cmp);
15341 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15343 x = gen_rtx_NOT (mode, cmp);
15344 x = gen_rtx_AND (mode, x, op_false);
15345 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15347 x = gen_rtx_IOR (mode, t3, t2);
15348 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15352 /* Expand a floating-point conditional move. Return true if successful. */
15355 ix86_expand_fp_movcc (rtx operands[])
15357 enum machine_mode mode = GET_MODE (operands[0]);
15358 enum rtx_code code = GET_CODE (operands[1]);
15359 rtx tmp, compare_op, second_test, bypass_test;
15361 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15363 enum machine_mode cmode;
15365 /* Since we've no cmove for sse registers, don't force bad register
15366 allocation just to gain access to it. Deny movcc when the
15367 comparison mode doesn't match the move mode. */
15368 cmode = GET_MODE (ix86_compare_op0);
15369 if (cmode == VOIDmode)
15370 cmode = GET_MODE (ix86_compare_op1);
15374 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15376 &ix86_compare_op1);
15377 if (code == UNKNOWN)
15380 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15381 ix86_compare_op1, operands[2],
15385 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15386 ix86_compare_op1, operands[2], operands[3]);
15387 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15391 /* The floating point conditional move instructions don't directly
15392 support conditions resulting from a signed integer comparison. */
15394 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15396 /* The floating point conditional move instructions don't directly
15397 support signed integer comparisons. */
15399 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15401 gcc_assert (!second_test && !bypass_test);
15402 tmp = gen_reg_rtx (QImode);
15403 ix86_expand_setcc (code, tmp);
15405 ix86_compare_op0 = tmp;
15406 ix86_compare_op1 = const0_rtx;
15407 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15409 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15411 tmp = gen_reg_rtx (mode);
15412 emit_move_insn (tmp, operands[3]);
15415 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15417 tmp = gen_reg_rtx (mode);
15418 emit_move_insn (tmp, operands[2]);
15422 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15423 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15424 operands[2], operands[3])));
15426 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15427 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15428 operands[3], operands[0])));
15430 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15431 gen_rtx_IF_THEN_ELSE (mode, second_test,
15432 operands[2], operands[0])));
15437 /* Expand a floating-point vector conditional move; a vcond operation
15438 rather than a movcc operation. */
15441 ix86_expand_fp_vcond (rtx operands[])
15443 enum rtx_code code = GET_CODE (operands[3]);
15446 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15447 &operands[4], &operands[5]);
15448 if (code == UNKNOWN)
15451 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15452 operands[5], operands[1], operands[2]))
15455 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15456 operands[1], operands[2]);
15457 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15461 /* Expand a signed/unsigned integral vector conditional move. */
15464 ix86_expand_int_vcond (rtx operands[])
15466 enum machine_mode mode = GET_MODE (operands[0]);
15467 enum rtx_code code = GET_CODE (operands[3]);
15468 bool negate = false;
15471 cop0 = operands[4];
15472 cop1 = operands[5];
15474 /* SSE5 supports all of the comparisons on all vector int types. */
15477 /* Canonicalize the comparison to EQ, GT, GTU. */
15488 code = reverse_condition (code);
15494 code = reverse_condition (code);
15500 code = swap_condition (code);
15501 x = cop0, cop0 = cop1, cop1 = x;
15505 gcc_unreachable ();
15508 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15509 if (mode == V2DImode)
15514 /* SSE4.1 supports EQ. */
15515 if (!TARGET_SSE4_1)
15521 /* SSE4.2 supports GT/GTU. */
15522 if (!TARGET_SSE4_2)
15527 gcc_unreachable ();
15531 /* Unsigned parallel compare is not supported by the hardware. Play some
15532 tricks to turn this into a signed comparison against 0. */
15535 cop0 = force_reg (mode, cop0);
15544 /* Perform a parallel modulo subtraction. */
15545 t1 = gen_reg_rtx (mode);
15546 emit_insn ((mode == V4SImode
15548 : gen_subv2di3) (t1, cop0, cop1));
15550 /* Extract the original sign bit of op0. */
15551 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15553 t2 = gen_reg_rtx (mode);
15554 emit_insn ((mode == V4SImode
15556 : gen_andv2di3) (t2, cop0, mask));
15558 /* XOR it back into the result of the subtraction. This results
15559 in the sign bit set iff we saw unsigned underflow. */
15560 x = gen_reg_rtx (mode);
15561 emit_insn ((mode == V4SImode
15563 : gen_xorv2di3) (x, t1, t2));
15571 /* Perform a parallel unsigned saturating subtraction. */
15572 x = gen_reg_rtx (mode);
15573 emit_insn (gen_rtx_SET (VOIDmode, x,
15574 gen_rtx_US_MINUS (mode, cop0, cop1)));
15581 gcc_unreachable ();
15585 cop1 = CONST0_RTX (mode);
15589 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15590 operands[1+negate], operands[2-negate]);
15592 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15593 operands[2-negate]);
15597 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15598 true if we should do zero extension, else sign extension. HIGH_P is
15599 true if we want the N/2 high elements, else the low elements. */
15602 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15604 enum machine_mode imode = GET_MODE (operands[1]);
15605 rtx (*unpack)(rtx, rtx, rtx);
15612 unpack = gen_vec_interleave_highv16qi;
15614 unpack = gen_vec_interleave_lowv16qi;
15618 unpack = gen_vec_interleave_highv8hi;
15620 unpack = gen_vec_interleave_lowv8hi;
15624 unpack = gen_vec_interleave_highv4si;
15626 unpack = gen_vec_interleave_lowv4si;
15629 gcc_unreachable ();
15632 dest = gen_lowpart (imode, operands[0]);
15635 se = force_reg (imode, CONST0_RTX (imode));
15637 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15638 operands[1], pc_rtx, pc_rtx);
15640 emit_insn (unpack (dest, operands[1], se));
15643 /* This function performs the same task as ix86_expand_sse_unpack,
15644 but with SSE4.1 instructions. */
15647 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15649 enum machine_mode imode = GET_MODE (operands[1]);
15650 rtx (*unpack)(rtx, rtx);
15657 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15659 unpack = gen_sse4_1_extendv8qiv8hi2;
15663 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15665 unpack = gen_sse4_1_extendv4hiv4si2;
15669 unpack = gen_sse4_1_zero_extendv2siv2di2;
15671 unpack = gen_sse4_1_extendv2siv2di2;
15674 gcc_unreachable ();
15677 dest = operands[0];
15680 /* Shift higher 8 bytes to lower 8 bytes. */
15681 src = gen_reg_rtx (imode);
15682 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15683 gen_lowpart (TImode, operands[1]),
15689 emit_insn (unpack (dest, src));
15692 /* This function performs the same task as ix86_expand_sse_unpack,
15693 but with sse5 instructions. */
15696 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15698 enum machine_mode imode = GET_MODE (operands[1]);
15699 int pperm_bytes[16];
15701 int h = (high_p) ? 8 : 0;
15704 rtvec v = rtvec_alloc (16);
15707 rtx op0 = operands[0], op1 = operands[1];
15712 vs = rtvec_alloc (8);
15713 h2 = (high_p) ? 8 : 0;
15714 for (i = 0; i < 8; i++)
15716 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15717 pperm_bytes[2*i+1] = ((unsigned_p)
15719 : PPERM_SIGN | PPERM_SRC2 | i | h);
15722 for (i = 0; i < 16; i++)
15723 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15725 for (i = 0; i < 8; i++)
15726 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15728 p = gen_rtx_PARALLEL (VOIDmode, vs);
15729 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15731 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15733 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15737 vs = rtvec_alloc (4);
15738 h2 = (high_p) ? 4 : 0;
15739 for (i = 0; i < 4; i++)
15741 sign_extend = ((unsigned_p)
15743 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15744 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15745 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15746 pperm_bytes[4*i+2] = sign_extend;
15747 pperm_bytes[4*i+3] = sign_extend;
15750 for (i = 0; i < 16; i++)
15751 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15753 for (i = 0; i < 4; i++)
15754 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15756 p = gen_rtx_PARALLEL (VOIDmode, vs);
15757 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15759 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15761 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15765 vs = rtvec_alloc (2);
15766 h2 = (high_p) ? 2 : 0;
15767 for (i = 0; i < 2; i++)
15769 sign_extend = ((unsigned_p)
15771 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15772 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15773 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15774 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15775 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15776 pperm_bytes[8*i+4] = sign_extend;
15777 pperm_bytes[8*i+5] = sign_extend;
15778 pperm_bytes[8*i+6] = sign_extend;
15779 pperm_bytes[8*i+7] = sign_extend;
15782 for (i = 0; i < 16; i++)
15783 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15785 for (i = 0; i < 2; i++)
15786 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15788 p = gen_rtx_PARALLEL (VOIDmode, vs);
15789 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15791 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15793 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15797 gcc_unreachable ();
15803 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15804 next narrower integer vector type */
15806 ix86_expand_sse5_pack (rtx operands[3])
15808 enum machine_mode imode = GET_MODE (operands[0]);
15809 int pperm_bytes[16];
15811 rtvec v = rtvec_alloc (16);
15813 rtx op0 = operands[0];
15814 rtx op1 = operands[1];
15815 rtx op2 = operands[2];
15820 for (i = 0; i < 8; i++)
15822 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15823 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15826 for (i = 0; i < 16; i++)
15827 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15829 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15830 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15834 for (i = 0; i < 4; i++)
15836 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15837 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15838 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15839 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15842 for (i = 0; i < 16; i++)
15843 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15845 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15846 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15850 for (i = 0; i < 2; i++)
15852 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15853 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15854 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15855 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15856 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15857 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15858 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15859 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15862 for (i = 0; i < 16; i++)
15863 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15865 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15866 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15870 gcc_unreachable ();
15876 /* Expand conditional increment or decrement using adb/sbb instructions.
15877 The default case using setcc followed by the conditional move can be
15878 done by generic code. */
15880 ix86_expand_int_addcc (rtx operands[])
15882 enum rtx_code code = GET_CODE (operands[1]);
15884 rtx val = const0_rtx;
15885 bool fpcmp = false;
15886 enum machine_mode mode = GET_MODE (operands[0]);
15888 if (operands[3] != const1_rtx
15889 && operands[3] != constm1_rtx)
15891 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15892 ix86_compare_op1, &compare_op))
15894 code = GET_CODE (compare_op);
15896 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15897 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15900 code = ix86_fp_compare_code_to_integer (code);
15907 PUT_CODE (compare_op,
15908 reverse_condition_maybe_unordered
15909 (GET_CODE (compare_op)));
15911 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15913 PUT_MODE (compare_op, mode);
15915 /* Construct either adc or sbb insn. */
15916 if ((code == LTU) == (operands[3] == constm1_rtx))
15918 switch (GET_MODE (operands[0]))
15921 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15924 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15927 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15930 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15933 gcc_unreachable ();
15938 switch (GET_MODE (operands[0]))
15941 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15944 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15947 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15950 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15953 gcc_unreachable ();
15956 return 1; /* DONE */
15960 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15961 works for floating pointer parameters and nonoffsetable memories.
15962 For pushes, it returns just stack offsets; the values will be saved
15963 in the right order. Maximally three parts are generated. */
15966 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
15971 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
15973 size = (GET_MODE_SIZE (mode) + 4) / 8;
15975 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
15976 gcc_assert (size >= 2 && size <= 4);
15978 /* Optimize constant pool reference to immediates. This is used by fp
15979 moves, that force all constants to memory to allow combining. */
15980 if (MEM_P (operand) && MEM_READONLY_P (operand))
15982 rtx tmp = maybe_get_pool_constant (operand);
15987 if (MEM_P (operand) && !offsettable_memref_p (operand))
15989 /* The only non-offsetable memories we handle are pushes. */
15990 int ok = push_operand (operand, VOIDmode);
15994 operand = copy_rtx (operand);
15995 PUT_MODE (operand, Pmode);
15996 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16000 if (GET_CODE (operand) == CONST_VECTOR)
16002 enum machine_mode imode = int_mode_for_mode (mode);
16003 /* Caution: if we looked through a constant pool memory above,
16004 the operand may actually have a different mode now. That's
16005 ok, since we want to pun this all the way back to an integer. */
16006 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16007 gcc_assert (operand != NULL);
16013 if (mode == DImode)
16014 split_di (&operand, 1, &parts[0], &parts[1]);
16019 if (REG_P (operand))
16021 gcc_assert (reload_completed);
16022 for (i = 0; i < size; i++)
16023 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16025 else if (offsettable_memref_p (operand))
16027 operand = adjust_address (operand, SImode, 0);
16028 parts[0] = operand;
16029 for (i = 1; i < size; i++)
16030 parts[i] = adjust_address (operand, SImode, 4 * i);
16032 else if (GET_CODE (operand) == CONST_DOUBLE)
16037 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16041 real_to_target (l, &r, mode);
16042 parts[3] = gen_int_mode (l[3], SImode);
16043 parts[2] = gen_int_mode (l[2], SImode);
16046 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16047 parts[2] = gen_int_mode (l[2], SImode);
16050 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16053 gcc_unreachable ();
16055 parts[1] = gen_int_mode (l[1], SImode);
16056 parts[0] = gen_int_mode (l[0], SImode);
16059 gcc_unreachable ();
16064 if (mode == TImode)
16065 split_ti (&operand, 1, &parts[0], &parts[1]);
16066 if (mode == XFmode || mode == TFmode)
16068 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16069 if (REG_P (operand))
16071 gcc_assert (reload_completed);
16072 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16073 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16075 else if (offsettable_memref_p (operand))
16077 operand = adjust_address (operand, DImode, 0);
16078 parts[0] = operand;
16079 parts[1] = adjust_address (operand, upper_mode, 8);
16081 else if (GET_CODE (operand) == CONST_DOUBLE)
16086 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16087 real_to_target (l, &r, mode);
16089 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16090 if (HOST_BITS_PER_WIDE_INT >= 64)
16093 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16094 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16097 parts[0] = immed_double_const (l[0], l[1], DImode);
16099 if (upper_mode == SImode)
16100 parts[1] = gen_int_mode (l[2], SImode);
16101 else if (HOST_BITS_PER_WIDE_INT >= 64)
16104 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16105 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16108 parts[1] = immed_double_const (l[2], l[3], DImode);
16111 gcc_unreachable ();
16118 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16119 Return false when normal moves are needed; true when all required
16120 insns have been emitted. Operands 2-4 contain the input values
16121 int the correct order; operands 5-7 contain the output values. */
16124 ix86_split_long_move (rtx operands[])
16129 int collisions = 0;
16130 enum machine_mode mode = GET_MODE (operands[0]);
16131 bool collisionparts[4];
16133 /* The DFmode expanders may ask us to move double.
16134 For 64bit target this is single move. By hiding the fact
16135 here we simplify i386.md splitters. */
16136 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16138 /* Optimize constant pool reference to immediates. This is used by
16139 fp moves, that force all constants to memory to allow combining. */
16141 if (MEM_P (operands[1])
16142 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16143 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16144 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16145 if (push_operand (operands[0], VOIDmode))
16147 operands[0] = copy_rtx (operands[0]);
16148 PUT_MODE (operands[0], Pmode);
16151 operands[0] = gen_lowpart (DImode, operands[0]);
16152 operands[1] = gen_lowpart (DImode, operands[1]);
16153 emit_move_insn (operands[0], operands[1]);
16157 /* The only non-offsettable memory we handle is push. */
16158 if (push_operand (operands[0], VOIDmode))
16161 gcc_assert (!MEM_P (operands[0])
16162 || offsettable_memref_p (operands[0]));
16164 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16165 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16167 /* When emitting push, take care for source operands on the stack. */
16168 if (push && MEM_P (operands[1])
16169 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16170 for (i = 0; i < nparts - 1; i++)
16171 part[1][i] = change_address (part[1][i],
16172 GET_MODE (part[1][i]),
16173 XEXP (part[1][i + 1], 0));
16175 /* We need to do copy in the right order in case an address register
16176 of the source overlaps the destination. */
16177 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16181 for (i = 0; i < nparts; i++)
16184 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16185 if (collisionparts[i])
16189 /* Collision in the middle part can be handled by reordering. */
16190 if (collisions == 1 && nparts == 3 && collisionparts [1])
16192 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16193 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16195 else if (collisions == 1
16197 && (collisionparts [1] || collisionparts [2]))
16199 if (collisionparts [1])
16201 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16202 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16206 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16207 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16211 /* If there are more collisions, we can't handle it by reordering.
16212 Do an lea to the last part and use only one colliding move. */
16213 else if (collisions > 1)
16219 base = part[0][nparts - 1];
16221 /* Handle the case when the last part isn't valid for lea.
16222 Happens in 64-bit mode storing the 12-byte XFmode. */
16223 if (GET_MODE (base) != Pmode)
16224 base = gen_rtx_REG (Pmode, REGNO (base));
16226 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16227 part[1][0] = replace_equiv_address (part[1][0], base);
16228 for (i = 1; i < nparts; i++)
16230 tmp = plus_constant (base, UNITS_PER_WORD * i);
16231 part[1][i] = replace_equiv_address (part[1][i], tmp);
16242 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16243 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
16244 emit_move_insn (part[0][2], part[1][2]);
16246 else if (nparts == 4)
16248 emit_move_insn (part[0][3], part[1][3]);
16249 emit_move_insn (part[0][2], part[1][2]);
16254 /* In 64bit mode we don't have 32bit push available. In case this is
16255 register, it is OK - we will just use larger counterpart. We also
16256 retype memory - these comes from attempt to avoid REX prefix on
16257 moving of second half of TFmode value. */
16258 if (GET_MODE (part[1][1]) == SImode)
16260 switch (GET_CODE (part[1][1]))
16263 part[1][1] = adjust_address (part[1][1], DImode, 0);
16267 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16271 gcc_unreachable ();
16274 if (GET_MODE (part[1][0]) == SImode)
16275 part[1][0] = part[1][1];
16278 emit_move_insn (part[0][1], part[1][1]);
16279 emit_move_insn (part[0][0], part[1][0]);
16283 /* Choose correct order to not overwrite the source before it is copied. */
16284 if ((REG_P (part[0][0])
16285 && REG_P (part[1][1])
16286 && (REGNO (part[0][0]) == REGNO (part[1][1])
16288 && REGNO (part[0][0]) == REGNO (part[1][2]))
16290 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16292 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16294 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16296 operands[2 + i] = part[0][j];
16297 operands[6 + i] = part[1][j];
16302 for (i = 0; i < nparts; i++)
16304 operands[2 + i] = part[0][i];
16305 operands[6 + i] = part[1][i];
16309 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16310 if (optimize_insn_for_size_p ())
16312 for (j = 0; j < nparts - 1; j++)
16313 if (CONST_INT_P (operands[6 + j])
16314 && operands[6 + j] != const0_rtx
16315 && REG_P (operands[2 + j]))
16316 for (i = j; i < nparts - 1; i++)
16317 if (CONST_INT_P (operands[7 + i])
16318 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16319 operands[7 + i] = operands[2 + j];
16322 for (i = 0; i < nparts; i++)
16323 emit_move_insn (operands[2 + i], operands[6 + i]);
16328 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16329 left shift by a constant, either using a single shift or
16330 a sequence of add instructions. */
16333 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16337 emit_insn ((mode == DImode
16339 : gen_adddi3) (operand, operand, operand));
16341 else if (!optimize_insn_for_size_p ()
16342 && count * ix86_cost->add <= ix86_cost->shift_const)
16345 for (i=0; i<count; i++)
16347 emit_insn ((mode == DImode
16349 : gen_adddi3) (operand, operand, operand));
16353 emit_insn ((mode == DImode
16355 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16359 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16361 rtx low[2], high[2];
16363 const int single_width = mode == DImode ? 32 : 64;
16365 if (CONST_INT_P (operands[2]))
16367 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16368 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16370 if (count >= single_width)
16372 emit_move_insn (high[0], low[1]);
16373 emit_move_insn (low[0], const0_rtx);
16375 if (count > single_width)
16376 ix86_expand_ashl_const (high[0], count - single_width, mode);
16380 if (!rtx_equal_p (operands[0], operands[1]))
16381 emit_move_insn (operands[0], operands[1]);
16382 emit_insn ((mode == DImode
16384 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16385 ix86_expand_ashl_const (low[0], count, mode);
16390 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16392 if (operands[1] == const1_rtx)
16394 /* Assuming we've chosen a QImode capable registers, then 1 << N
16395 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16396 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16398 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16400 ix86_expand_clear (low[0]);
16401 ix86_expand_clear (high[0]);
16402 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16404 d = gen_lowpart (QImode, low[0]);
16405 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16406 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16407 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16409 d = gen_lowpart (QImode, high[0]);
16410 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16411 s = gen_rtx_NE (QImode, flags, const0_rtx);
16412 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16415 /* Otherwise, we can get the same results by manually performing
16416 a bit extract operation on bit 5/6, and then performing the two
16417 shifts. The two methods of getting 0/1 into low/high are exactly
16418 the same size. Avoiding the shift in the bit extract case helps
16419 pentium4 a bit; no one else seems to care much either way. */
16424 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16425 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16427 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16428 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16430 emit_insn ((mode == DImode
16432 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16433 emit_insn ((mode == DImode
16435 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16436 emit_move_insn (low[0], high[0]);
16437 emit_insn ((mode == DImode
16439 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16442 emit_insn ((mode == DImode
16444 : gen_ashldi3) (low[0], low[0], operands[2]));
16445 emit_insn ((mode == DImode
16447 : gen_ashldi3) (high[0], high[0], operands[2]));
16451 if (operands[1] == constm1_rtx)
16453 /* For -1 << N, we can avoid the shld instruction, because we
16454 know that we're shifting 0...31/63 ones into a -1. */
16455 emit_move_insn (low[0], constm1_rtx);
16456 if (optimize_insn_for_size_p ())
16457 emit_move_insn (high[0], low[0]);
16459 emit_move_insn (high[0], constm1_rtx);
16463 if (!rtx_equal_p (operands[0], operands[1]))
16464 emit_move_insn (operands[0], operands[1]);
16466 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16467 emit_insn ((mode == DImode
16469 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16472 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16474 if (TARGET_CMOVE && scratch)
16476 ix86_expand_clear (scratch);
16477 emit_insn ((mode == DImode
16478 ? gen_x86_shift_adj_1
16479 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16483 emit_insn ((mode == DImode
16484 ? gen_x86_shift_adj_2
16485 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16489 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16491 rtx low[2], high[2];
16493 const int single_width = mode == DImode ? 32 : 64;
16495 if (CONST_INT_P (operands[2]))
16497 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16498 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16500 if (count == single_width * 2 - 1)
16502 emit_move_insn (high[0], high[1]);
16503 emit_insn ((mode == DImode
16505 : gen_ashrdi3) (high[0], high[0],
16506 GEN_INT (single_width - 1)));
16507 emit_move_insn (low[0], high[0]);
16510 else if (count >= single_width)
16512 emit_move_insn (low[0], high[1]);
16513 emit_move_insn (high[0], low[0]);
16514 emit_insn ((mode == DImode
16516 : gen_ashrdi3) (high[0], high[0],
16517 GEN_INT (single_width - 1)));
16518 if (count > single_width)
16519 emit_insn ((mode == DImode
16521 : gen_ashrdi3) (low[0], low[0],
16522 GEN_INT (count - single_width)));
16526 if (!rtx_equal_p (operands[0], operands[1]))
16527 emit_move_insn (operands[0], operands[1]);
16528 emit_insn ((mode == DImode
16530 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16531 emit_insn ((mode == DImode
16533 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16538 if (!rtx_equal_p (operands[0], operands[1]))
16539 emit_move_insn (operands[0], operands[1]);
16541 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16543 emit_insn ((mode == DImode
16545 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16546 emit_insn ((mode == DImode
16548 : gen_ashrdi3) (high[0], high[0], operands[2]));
16550 if (TARGET_CMOVE && scratch)
16552 emit_move_insn (scratch, high[0]);
16553 emit_insn ((mode == DImode
16555 : gen_ashrdi3) (scratch, scratch,
16556 GEN_INT (single_width - 1)));
16557 emit_insn ((mode == DImode
16558 ? gen_x86_shift_adj_1
16559 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16563 emit_insn ((mode == DImode
16564 ? gen_x86_shift_adj_3
16565 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16570 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16572 rtx low[2], high[2];
16574 const int single_width = mode == DImode ? 32 : 64;
16576 if (CONST_INT_P (operands[2]))
16578 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16579 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16581 if (count >= single_width)
16583 emit_move_insn (low[0], high[1]);
16584 ix86_expand_clear (high[0]);
16586 if (count > single_width)
16587 emit_insn ((mode == DImode
16589 : gen_lshrdi3) (low[0], low[0],
16590 GEN_INT (count - single_width)));
16594 if (!rtx_equal_p (operands[0], operands[1]))
16595 emit_move_insn (operands[0], operands[1]);
16596 emit_insn ((mode == DImode
16598 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16599 emit_insn ((mode == DImode
16601 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16606 if (!rtx_equal_p (operands[0], operands[1]))
16607 emit_move_insn (operands[0], operands[1]);
16609 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16611 emit_insn ((mode == DImode
16613 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16614 emit_insn ((mode == DImode
16616 : gen_lshrdi3) (high[0], high[0], operands[2]));
16618 /* Heh. By reversing the arguments, we can reuse this pattern. */
16619 if (TARGET_CMOVE && scratch)
16621 ix86_expand_clear (scratch);
16622 emit_insn ((mode == DImode
16623 ? gen_x86_shift_adj_1
16624 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16628 emit_insn ((mode == DImode
16629 ? gen_x86_shift_adj_2
16630 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16634 /* Predict just emitted jump instruction to be taken with probability PROB. */
16636 predict_jump (int prob)
16638 rtx insn = get_last_insn ();
16639 gcc_assert (JUMP_P (insn));
16641 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16646 /* Helper function for the string operations below. Dest VARIABLE whether
16647 it is aligned to VALUE bytes. If true, jump to the label. */
16649 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16651 rtx label = gen_label_rtx ();
16652 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16653 if (GET_MODE (variable) == DImode)
16654 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16656 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16657 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16660 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16662 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16666 /* Adjust COUNTER by the VALUE. */
16668 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16670 if (GET_MODE (countreg) == DImode)
16671 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16673 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16676 /* Zero extend possibly SImode EXP to Pmode register. */
16678 ix86_zero_extend_to_Pmode (rtx exp)
16681 if (GET_MODE (exp) == VOIDmode)
16682 return force_reg (Pmode, exp);
16683 if (GET_MODE (exp) == Pmode)
16684 return copy_to_mode_reg (Pmode, exp);
16685 r = gen_reg_rtx (Pmode);
16686 emit_insn (gen_zero_extendsidi2 (r, exp));
16690 /* Divide COUNTREG by SCALE. */
16692 scale_counter (rtx countreg, int scale)
16695 rtx piece_size_mask;
16699 if (CONST_INT_P (countreg))
16700 return GEN_INT (INTVAL (countreg) / scale);
16701 gcc_assert (REG_P (countreg));
16703 piece_size_mask = GEN_INT (scale - 1);
16704 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16705 GEN_INT (exact_log2 (scale)),
16706 NULL, 1, OPTAB_DIRECT);
16710 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16711 DImode for constant loop counts. */
16713 static enum machine_mode
16714 counter_mode (rtx count_exp)
16716 if (GET_MODE (count_exp) != VOIDmode)
16717 return GET_MODE (count_exp);
16718 if (GET_CODE (count_exp) != CONST_INT)
16720 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16725 /* When SRCPTR is non-NULL, output simple loop to move memory
16726 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16727 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16728 equivalent loop to set memory by VALUE (supposed to be in MODE).
16730 The size is rounded down to whole number of chunk size moved at once.
16731 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16735 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16736 rtx destptr, rtx srcptr, rtx value,
16737 rtx count, enum machine_mode mode, int unroll,
16740 rtx out_label, top_label, iter, tmp;
16741 enum machine_mode iter_mode = counter_mode (count);
16742 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16743 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16749 top_label = gen_label_rtx ();
16750 out_label = gen_label_rtx ();
16751 iter = gen_reg_rtx (iter_mode);
16753 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16754 NULL, 1, OPTAB_DIRECT);
16755 /* Those two should combine. */
16756 if (piece_size == const1_rtx)
16758 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16760 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16762 emit_move_insn (iter, const0_rtx);
16764 emit_label (top_label);
16766 tmp = convert_modes (Pmode, iter_mode, iter, true);
16767 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16768 destmem = change_address (destmem, mode, x_addr);
16772 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16773 srcmem = change_address (srcmem, mode, y_addr);
16775 /* When unrolling for chips that reorder memory reads and writes,
16776 we can save registers by using single temporary.
16777 Also using 4 temporaries is overkill in 32bit mode. */
16778 if (!TARGET_64BIT && 0)
16780 for (i = 0; i < unroll; i++)
16785 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16787 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16789 emit_move_insn (destmem, srcmem);
16795 gcc_assert (unroll <= 4);
16796 for (i = 0; i < unroll; i++)
16798 tmpreg[i] = gen_reg_rtx (mode);
16802 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16804 emit_move_insn (tmpreg[i], srcmem);
16806 for (i = 0; i < unroll; i++)
16811 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16813 emit_move_insn (destmem, tmpreg[i]);
16818 for (i = 0; i < unroll; i++)
16822 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16823 emit_move_insn (destmem, value);
16826 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16827 true, OPTAB_LIB_WIDEN);
16829 emit_move_insn (iter, tmp);
16831 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16833 if (expected_size != -1)
16835 expected_size /= GET_MODE_SIZE (mode) * unroll;
16836 if (expected_size == 0)
16838 else if (expected_size > REG_BR_PROB_BASE)
16839 predict_jump (REG_BR_PROB_BASE - 1);
16841 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16844 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16845 iter = ix86_zero_extend_to_Pmode (iter);
16846 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16847 true, OPTAB_LIB_WIDEN);
16848 if (tmp != destptr)
16849 emit_move_insn (destptr, tmp);
16852 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16853 true, OPTAB_LIB_WIDEN);
16855 emit_move_insn (srcptr, tmp);
16857 emit_label (out_label);
16860 /* Output "rep; mov" instruction.
16861 Arguments have same meaning as for previous function */
16863 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16864 rtx destptr, rtx srcptr,
16866 enum machine_mode mode)
16872 /* If the size is known, it is shorter to use rep movs. */
16873 if (mode == QImode && CONST_INT_P (count)
16874 && !(INTVAL (count) & 3))
16877 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16878 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16879 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16880 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16881 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16882 if (mode != QImode)
16884 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16885 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16886 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16887 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16888 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16889 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16893 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16894 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16896 if (CONST_INT_P (count))
16898 count = GEN_INT (INTVAL (count)
16899 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16900 destmem = shallow_copy_rtx (destmem);
16901 srcmem = shallow_copy_rtx (srcmem);
16902 set_mem_size (destmem, count);
16903 set_mem_size (srcmem, count);
16907 if (MEM_SIZE (destmem))
16908 set_mem_size (destmem, NULL_RTX);
16909 if (MEM_SIZE (srcmem))
16910 set_mem_size (srcmem, NULL_RTX);
16912 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16916 /* Output "rep; stos" instruction.
16917 Arguments have same meaning as for previous function */
16919 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16920 rtx count, enum machine_mode mode,
16926 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16927 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16928 value = force_reg (mode, gen_lowpart (mode, value));
16929 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16930 if (mode != QImode)
16932 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16933 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16934 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16937 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16938 if (orig_value == const0_rtx && CONST_INT_P (count))
16940 count = GEN_INT (INTVAL (count)
16941 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16942 destmem = shallow_copy_rtx (destmem);
16943 set_mem_size (destmem, count);
16945 else if (MEM_SIZE (destmem))
16946 set_mem_size (destmem, NULL_RTX);
16947 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16951 emit_strmov (rtx destmem, rtx srcmem,
16952 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16954 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16955 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16956 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16959 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16961 expand_movmem_epilogue (rtx destmem, rtx srcmem,
16962 rtx destptr, rtx srcptr, rtx count, int max_size)
16965 if (CONST_INT_P (count))
16967 HOST_WIDE_INT countval = INTVAL (count);
16970 if ((countval & 0x10) && max_size > 16)
16974 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16975 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
16978 gcc_unreachable ();
16981 if ((countval & 0x08) && max_size > 8)
16984 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16987 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16988 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
16992 if ((countval & 0x04) && max_size > 4)
16994 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16997 if ((countval & 0x02) && max_size > 2)
16999 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17002 if ((countval & 0x01) && max_size > 1)
17004 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17011 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17012 count, 1, OPTAB_DIRECT);
17013 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17014 count, QImode, 1, 4);
17018 /* When there are stringops, we can cheaply increase dest and src pointers.
17019 Otherwise we save code size by maintaining offset (zero is readily
17020 available from preceding rep operation) and using x86 addressing modes.
17022 if (TARGET_SINGLE_STRINGOP)
17026 rtx label = ix86_expand_aligntest (count, 4, true);
17027 src = change_address (srcmem, SImode, srcptr);
17028 dest = change_address (destmem, SImode, destptr);
17029 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17030 emit_label (label);
17031 LABEL_NUSES (label) = 1;
17035 rtx label = ix86_expand_aligntest (count, 2, true);
17036 src = change_address (srcmem, HImode, srcptr);
17037 dest = change_address (destmem, HImode, destptr);
17038 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17039 emit_label (label);
17040 LABEL_NUSES (label) = 1;
17044 rtx label = ix86_expand_aligntest (count, 1, true);
17045 src = change_address (srcmem, QImode, srcptr);
17046 dest = change_address (destmem, QImode, destptr);
17047 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17048 emit_label (label);
17049 LABEL_NUSES (label) = 1;
17054 rtx offset = force_reg (Pmode, const0_rtx);
17059 rtx label = ix86_expand_aligntest (count, 4, true);
17060 src = change_address (srcmem, SImode, srcptr);
17061 dest = change_address (destmem, SImode, destptr);
17062 emit_move_insn (dest, src);
17063 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17064 true, OPTAB_LIB_WIDEN);
17066 emit_move_insn (offset, tmp);
17067 emit_label (label);
17068 LABEL_NUSES (label) = 1;
17072 rtx label = ix86_expand_aligntest (count, 2, true);
17073 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17074 src = change_address (srcmem, HImode, tmp);
17075 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17076 dest = change_address (destmem, HImode, tmp);
17077 emit_move_insn (dest, src);
17078 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17079 true, OPTAB_LIB_WIDEN);
17081 emit_move_insn (offset, tmp);
17082 emit_label (label);
17083 LABEL_NUSES (label) = 1;
17087 rtx label = ix86_expand_aligntest (count, 1, true);
17088 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17089 src = change_address (srcmem, QImode, tmp);
17090 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17091 dest = change_address (destmem, QImode, tmp);
17092 emit_move_insn (dest, src);
17093 emit_label (label);
17094 LABEL_NUSES (label) = 1;
17099 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17101 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17102 rtx count, int max_size)
17105 expand_simple_binop (counter_mode (count), AND, count,
17106 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17107 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17108 gen_lowpart (QImode, value), count, QImode,
17112 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17114 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17118 if (CONST_INT_P (count))
17120 HOST_WIDE_INT countval = INTVAL (count);
17123 if ((countval & 0x10) && max_size > 16)
17127 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17128 emit_insn (gen_strset (destptr, dest, value));
17129 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17130 emit_insn (gen_strset (destptr, dest, value));
17133 gcc_unreachable ();
17136 if ((countval & 0x08) && max_size > 8)
17140 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17141 emit_insn (gen_strset (destptr, dest, value));
17145 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17146 emit_insn (gen_strset (destptr, dest, value));
17147 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17148 emit_insn (gen_strset (destptr, dest, value));
17152 if ((countval & 0x04) && max_size > 4)
17154 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17155 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17158 if ((countval & 0x02) && max_size > 2)
17160 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17161 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17164 if ((countval & 0x01) && max_size > 1)
17166 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17167 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17174 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17179 rtx label = ix86_expand_aligntest (count, 16, true);
17182 dest = change_address (destmem, DImode, destptr);
17183 emit_insn (gen_strset (destptr, dest, value));
17184 emit_insn (gen_strset (destptr, dest, value));
17188 dest = change_address (destmem, SImode, destptr);
17189 emit_insn (gen_strset (destptr, dest, value));
17190 emit_insn (gen_strset (destptr, dest, value));
17191 emit_insn (gen_strset (destptr, dest, value));
17192 emit_insn (gen_strset (destptr, dest, value));
17194 emit_label (label);
17195 LABEL_NUSES (label) = 1;
17199 rtx label = ix86_expand_aligntest (count, 8, true);
17202 dest = change_address (destmem, DImode, destptr);
17203 emit_insn (gen_strset (destptr, dest, value));
17207 dest = change_address (destmem, SImode, destptr);
17208 emit_insn (gen_strset (destptr, dest, value));
17209 emit_insn (gen_strset (destptr, dest, value));
17211 emit_label (label);
17212 LABEL_NUSES (label) = 1;
17216 rtx label = ix86_expand_aligntest (count, 4, true);
17217 dest = change_address (destmem, SImode, destptr);
17218 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17219 emit_label (label);
17220 LABEL_NUSES (label) = 1;
17224 rtx label = ix86_expand_aligntest (count, 2, true);
17225 dest = change_address (destmem, HImode, destptr);
17226 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17227 emit_label (label);
17228 LABEL_NUSES (label) = 1;
17232 rtx label = ix86_expand_aligntest (count, 1, true);
17233 dest = change_address (destmem, QImode, destptr);
17234 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17235 emit_label (label);
17236 LABEL_NUSES (label) = 1;
17240 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17241 DESIRED_ALIGNMENT. */
17243 expand_movmem_prologue (rtx destmem, rtx srcmem,
17244 rtx destptr, rtx srcptr, rtx count,
17245 int align, int desired_alignment)
17247 if (align <= 1 && desired_alignment > 1)
17249 rtx label = ix86_expand_aligntest (destptr, 1, false);
17250 srcmem = change_address (srcmem, QImode, srcptr);
17251 destmem = change_address (destmem, QImode, destptr);
17252 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17253 ix86_adjust_counter (count, 1);
17254 emit_label (label);
17255 LABEL_NUSES (label) = 1;
17257 if (align <= 2 && desired_alignment > 2)
17259 rtx label = ix86_expand_aligntest (destptr, 2, false);
17260 srcmem = change_address (srcmem, HImode, srcptr);
17261 destmem = change_address (destmem, HImode, destptr);
17262 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17263 ix86_adjust_counter (count, 2);
17264 emit_label (label);
17265 LABEL_NUSES (label) = 1;
17267 if (align <= 4 && desired_alignment > 4)
17269 rtx label = ix86_expand_aligntest (destptr, 4, false);
17270 srcmem = change_address (srcmem, SImode, srcptr);
17271 destmem = change_address (destmem, SImode, destptr);
17272 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17273 ix86_adjust_counter (count, 4);
17274 emit_label (label);
17275 LABEL_NUSES (label) = 1;
17277 gcc_assert (desired_alignment <= 8);
17280 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17281 ALIGN_BYTES is how many bytes need to be copied. */
17283 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17284 int desired_align, int align_bytes)
17287 rtx src_size, dst_size;
17289 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17290 if (src_align_bytes >= 0)
17291 src_align_bytes = desired_align - src_align_bytes;
17292 src_size = MEM_SIZE (src);
17293 dst_size = MEM_SIZE (dst);
17294 if (align_bytes & 1)
17296 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17297 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17299 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17301 if (align_bytes & 2)
17303 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17304 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17305 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17306 set_mem_align (dst, 2 * BITS_PER_UNIT);
17307 if (src_align_bytes >= 0
17308 && (src_align_bytes & 1) == (align_bytes & 1)
17309 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17310 set_mem_align (src, 2 * BITS_PER_UNIT);
17312 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17314 if (align_bytes & 4)
17316 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17317 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17318 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17319 set_mem_align (dst, 4 * BITS_PER_UNIT);
17320 if (src_align_bytes >= 0)
17322 unsigned int src_align = 0;
17323 if ((src_align_bytes & 3) == (align_bytes & 3))
17325 else if ((src_align_bytes & 1) == (align_bytes & 1))
17327 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17328 set_mem_align (src, src_align * BITS_PER_UNIT);
17331 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17333 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17334 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17335 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17336 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17337 if (src_align_bytes >= 0)
17339 unsigned int src_align = 0;
17340 if ((src_align_bytes & 7) == (align_bytes & 7))
17342 else if ((src_align_bytes & 3) == (align_bytes & 3))
17344 else if ((src_align_bytes & 1) == (align_bytes & 1))
17346 if (src_align > (unsigned int) desired_align)
17347 src_align = desired_align;
17348 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17349 set_mem_align (src, src_align * BITS_PER_UNIT);
17352 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17354 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17359 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17360 DESIRED_ALIGNMENT. */
17362 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17363 int align, int desired_alignment)
17365 if (align <= 1 && desired_alignment > 1)
17367 rtx label = ix86_expand_aligntest (destptr, 1, false);
17368 destmem = change_address (destmem, QImode, destptr);
17369 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17370 ix86_adjust_counter (count, 1);
17371 emit_label (label);
17372 LABEL_NUSES (label) = 1;
17374 if (align <= 2 && desired_alignment > 2)
17376 rtx label = ix86_expand_aligntest (destptr, 2, false);
17377 destmem = change_address (destmem, HImode, destptr);
17378 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17379 ix86_adjust_counter (count, 2);
17380 emit_label (label);
17381 LABEL_NUSES (label) = 1;
17383 if (align <= 4 && desired_alignment > 4)
17385 rtx label = ix86_expand_aligntest (destptr, 4, false);
17386 destmem = change_address (destmem, SImode, destptr);
17387 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17388 ix86_adjust_counter (count, 4);
17389 emit_label (label);
17390 LABEL_NUSES (label) = 1;
17392 gcc_assert (desired_alignment <= 8);
17395 /* Set enough from DST to align DST known to by aligned by ALIGN to
17396 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17398 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17399 int desired_align, int align_bytes)
17402 rtx dst_size = MEM_SIZE (dst);
17403 if (align_bytes & 1)
17405 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17407 emit_insn (gen_strset (destreg, dst,
17408 gen_lowpart (QImode, value)));
17410 if (align_bytes & 2)
17412 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17413 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17414 set_mem_align (dst, 2 * BITS_PER_UNIT);
17416 emit_insn (gen_strset (destreg, dst,
17417 gen_lowpart (HImode, value)));
17419 if (align_bytes & 4)
17421 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17422 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17423 set_mem_align (dst, 4 * BITS_PER_UNIT);
17425 emit_insn (gen_strset (destreg, dst,
17426 gen_lowpart (SImode, value)));
17428 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17429 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17430 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17432 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17436 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17437 static enum stringop_alg
17438 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17439 int *dynamic_check)
17441 const struct stringop_algs * algs;
17442 bool optimize_for_speed;
17443 /* Algorithms using the rep prefix want at least edi and ecx;
17444 additionally, memset wants eax and memcpy wants esi. Don't
17445 consider such algorithms if the user has appropriated those
17446 registers for their own purposes. */
17447 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17449 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17451 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17452 || (alg != rep_prefix_1_byte \
17453 && alg != rep_prefix_4_byte \
17454 && alg != rep_prefix_8_byte))
17455 const struct processor_costs *cost;
17457 /* Even if the string operation call is cold, we still might spend a lot
17458 of time processing large blocks. */
17459 if (optimize_function_for_size_p (cfun)
17460 || (optimize_insn_for_size_p ()
17461 && expected_size != -1 && expected_size < 256))
17462 optimize_for_speed = false;
17464 optimize_for_speed = true;
17466 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17468 *dynamic_check = -1;
17470 algs = &cost->memset[TARGET_64BIT != 0];
17472 algs = &cost->memcpy[TARGET_64BIT != 0];
17473 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17474 return stringop_alg;
17475 /* rep; movq or rep; movl is the smallest variant. */
17476 else if (!optimize_for_speed)
17478 if (!count || (count & 3))
17479 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17481 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17483 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17485 else if (expected_size != -1 && expected_size < 4)
17486 return loop_1_byte;
17487 else if (expected_size != -1)
17490 enum stringop_alg alg = libcall;
17491 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17493 /* We get here if the algorithms that were not libcall-based
17494 were rep-prefix based and we are unable to use rep prefixes
17495 based on global register usage. Break out of the loop and
17496 use the heuristic below. */
17497 if (algs->size[i].max == 0)
17499 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17501 enum stringop_alg candidate = algs->size[i].alg;
17503 if (candidate != libcall && ALG_USABLE_P (candidate))
17505 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17506 last non-libcall inline algorithm. */
17507 if (TARGET_INLINE_ALL_STRINGOPS)
17509 /* When the current size is best to be copied by a libcall,
17510 but we are still forced to inline, run the heuristic below
17511 that will pick code for medium sized blocks. */
17512 if (alg != libcall)
17516 else if (ALG_USABLE_P (candidate))
17520 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17522 /* When asked to inline the call anyway, try to pick meaningful choice.
17523 We look for maximal size of block that is faster to copy by hand and
17524 take blocks of at most of that size guessing that average size will
17525 be roughly half of the block.
17527 If this turns out to be bad, we might simply specify the preferred
17528 choice in ix86_costs. */
17529 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17530 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17533 enum stringop_alg alg;
17535 bool any_alg_usable_p = true;
17537 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17539 enum stringop_alg candidate = algs->size[i].alg;
17540 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17542 if (candidate != libcall && candidate
17543 && ALG_USABLE_P (candidate))
17544 max = algs->size[i].max;
17546 /* If there aren't any usable algorithms, then recursing on
17547 smaller sizes isn't going to find anything. Just return the
17548 simple byte-at-a-time copy loop. */
17549 if (!any_alg_usable_p)
17551 /* Pick something reasonable. */
17552 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17553 *dynamic_check = 128;
17554 return loop_1_byte;
17558 alg = decide_alg (count, max / 2, memset, dynamic_check);
17559 gcc_assert (*dynamic_check == -1);
17560 gcc_assert (alg != libcall);
17561 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17562 *dynamic_check = max;
17565 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17566 #undef ALG_USABLE_P
17569 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17570 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17572 decide_alignment (int align,
17573 enum stringop_alg alg,
17576 int desired_align = 0;
17580 gcc_unreachable ();
17582 case unrolled_loop:
17583 desired_align = GET_MODE_SIZE (Pmode);
17585 case rep_prefix_8_byte:
17588 case rep_prefix_4_byte:
17589 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17590 copying whole cacheline at once. */
17591 if (TARGET_PENTIUMPRO)
17596 case rep_prefix_1_byte:
17597 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17598 copying whole cacheline at once. */
17599 if (TARGET_PENTIUMPRO)
17613 if (desired_align < align)
17614 desired_align = align;
17615 if (expected_size != -1 && expected_size < 4)
17616 desired_align = align;
17617 return desired_align;
17620 /* Return the smallest power of 2 greater than VAL. */
17622 smallest_pow2_greater_than (int val)
17630 /* Expand string move (memcpy) operation. Use i386 string operations when
17631 profitable. expand_setmem contains similar code. The code depends upon
17632 architecture, block size and alignment, but always has the same
17635 1) Prologue guard: Conditional that jumps up to epilogues for small
17636 blocks that can be handled by epilogue alone. This is faster but
17637 also needed for correctness, since prologue assume the block is larger
17638 than the desired alignment.
17640 Optional dynamic check for size and libcall for large
17641 blocks is emitted here too, with -minline-stringops-dynamically.
17643 2) Prologue: copy first few bytes in order to get destination aligned
17644 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17645 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17646 We emit either a jump tree on power of two sized blocks, or a byte loop.
17648 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17649 with specified algorithm.
17651 4) Epilogue: code copying tail of the block that is too small to be
17652 handled by main body (or up to size guarded by prologue guard). */
17655 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17656 rtx expected_align_exp, rtx expected_size_exp)
17662 rtx jump_around_label = NULL;
17663 HOST_WIDE_INT align = 1;
17664 unsigned HOST_WIDE_INT count = 0;
17665 HOST_WIDE_INT expected_size = -1;
17666 int size_needed = 0, epilogue_size_needed;
17667 int desired_align = 0, align_bytes = 0;
17668 enum stringop_alg alg;
17670 bool need_zero_guard = false;
17672 if (CONST_INT_P (align_exp))
17673 align = INTVAL (align_exp);
17674 /* i386 can do misaligned access on reasonably increased cost. */
17675 if (CONST_INT_P (expected_align_exp)
17676 && INTVAL (expected_align_exp) > align)
17677 align = INTVAL (expected_align_exp);
17678 /* ALIGN is the minimum of destination and source alignment, but we care here
17679 just about destination alignment. */
17680 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17681 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17683 if (CONST_INT_P (count_exp))
17684 count = expected_size = INTVAL (count_exp);
17685 if (CONST_INT_P (expected_size_exp) && count == 0)
17686 expected_size = INTVAL (expected_size_exp);
17688 /* Make sure we don't need to care about overflow later on. */
17689 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17692 /* Step 0: Decide on preferred algorithm, desired alignment and
17693 size of chunks to be copied by main loop. */
17695 alg = decide_alg (count, expected_size, false, &dynamic_check);
17696 desired_align = decide_alignment (align, alg, expected_size);
17698 if (!TARGET_ALIGN_STRINGOPS)
17699 align = desired_align;
17701 if (alg == libcall)
17703 gcc_assert (alg != no_stringop);
17705 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17706 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17707 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17712 gcc_unreachable ();
17714 need_zero_guard = true;
17715 size_needed = GET_MODE_SIZE (Pmode);
17717 case unrolled_loop:
17718 need_zero_guard = true;
17719 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17721 case rep_prefix_8_byte:
17724 case rep_prefix_4_byte:
17727 case rep_prefix_1_byte:
17731 need_zero_guard = true;
17736 epilogue_size_needed = size_needed;
17738 /* Step 1: Prologue guard. */
17740 /* Alignment code needs count to be in register. */
17741 if (CONST_INT_P (count_exp) && desired_align > align)
17743 if (INTVAL (count_exp) > desired_align
17744 && INTVAL (count_exp) > size_needed)
17747 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17748 if (align_bytes <= 0)
17751 align_bytes = desired_align - align_bytes;
17753 if (align_bytes == 0)
17754 count_exp = force_reg (counter_mode (count_exp), count_exp);
17756 gcc_assert (desired_align >= 1 && align >= 1);
17758 /* Ensure that alignment prologue won't copy past end of block. */
17759 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17761 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17762 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17763 Make sure it is power of 2. */
17764 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17768 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17770 /* If main algorithm works on QImode, no epilogue is needed.
17771 For small sizes just don't align anything. */
17772 if (size_needed == 1)
17773 desired_align = align;
17780 label = gen_label_rtx ();
17781 emit_cmp_and_jump_insns (count_exp,
17782 GEN_INT (epilogue_size_needed),
17783 LTU, 0, counter_mode (count_exp), 1, label);
17784 if (expected_size == -1 || expected_size < epilogue_size_needed)
17785 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17787 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17791 /* Emit code to decide on runtime whether library call or inline should be
17793 if (dynamic_check != -1)
17795 if (CONST_INT_P (count_exp))
17797 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17799 emit_block_move_via_libcall (dst, src, count_exp, false);
17800 count_exp = const0_rtx;
17806 rtx hot_label = gen_label_rtx ();
17807 jump_around_label = gen_label_rtx ();
17808 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17809 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17810 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17811 emit_block_move_via_libcall (dst, src, count_exp, false);
17812 emit_jump (jump_around_label);
17813 emit_label (hot_label);
17817 /* Step 2: Alignment prologue. */
17819 if (desired_align > align)
17821 if (align_bytes == 0)
17823 /* Except for the first move in epilogue, we no longer know
17824 constant offset in aliasing info. It don't seems to worth
17825 the pain to maintain it for the first move, so throw away
17827 src = change_address (src, BLKmode, srcreg);
17828 dst = change_address (dst, BLKmode, destreg);
17829 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17834 /* If we know how many bytes need to be stored before dst is
17835 sufficiently aligned, maintain aliasing info accurately. */
17836 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17837 desired_align, align_bytes);
17838 count_exp = plus_constant (count_exp, -align_bytes);
17839 count -= align_bytes;
17841 if (need_zero_guard
17842 && (count < (unsigned HOST_WIDE_INT) size_needed
17843 || (align_bytes == 0
17844 && count < ((unsigned HOST_WIDE_INT) size_needed
17845 + desired_align - align))))
17847 /* It is possible that we copied enough so the main loop will not
17849 gcc_assert (size_needed > 1);
17850 if (label == NULL_RTX)
17851 label = gen_label_rtx ();
17852 emit_cmp_and_jump_insns (count_exp,
17853 GEN_INT (size_needed),
17854 LTU, 0, counter_mode (count_exp), 1, label);
17855 if (expected_size == -1
17856 || expected_size < (desired_align - align) / 2 + size_needed)
17857 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17859 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17862 if (label && size_needed == 1)
17864 emit_label (label);
17865 LABEL_NUSES (label) = 1;
17867 epilogue_size_needed = 1;
17869 else if (label == NULL_RTX)
17870 epilogue_size_needed = size_needed;
17872 /* Step 3: Main loop. */
17878 gcc_unreachable ();
17880 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17881 count_exp, QImode, 1, expected_size);
17884 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17885 count_exp, Pmode, 1, expected_size);
17887 case unrolled_loop:
17888 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17889 registers for 4 temporaries anyway. */
17890 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17891 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
17894 case rep_prefix_8_byte:
17895 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17898 case rep_prefix_4_byte:
17899 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17902 case rep_prefix_1_byte:
17903 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17907 /* Adjust properly the offset of src and dest memory for aliasing. */
17908 if (CONST_INT_P (count_exp))
17910 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17911 (count / size_needed) * size_needed);
17912 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17913 (count / size_needed) * size_needed);
17917 src = change_address (src, BLKmode, srcreg);
17918 dst = change_address (dst, BLKmode, destreg);
17921 /* Step 4: Epilogue to copy the remaining bytes. */
17925 /* When the main loop is done, COUNT_EXP might hold original count,
17926 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17927 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17928 bytes. Compensate if needed. */
17930 if (size_needed < epilogue_size_needed)
17933 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17934 GEN_INT (size_needed - 1), count_exp, 1,
17936 if (tmp != count_exp)
17937 emit_move_insn (count_exp, tmp);
17939 emit_label (label);
17940 LABEL_NUSES (label) = 1;
17943 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17944 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17945 epilogue_size_needed);
17946 if (jump_around_label)
17947 emit_label (jump_around_label);
17951 /* Helper function for memcpy. For QImode value 0xXY produce
17952 0xXYXYXYXY of wide specified by MODE. This is essentially
17953 a * 0x10101010, but we can do slightly better than
17954 synth_mult by unwinding the sequence by hand on CPUs with
17957 promote_duplicated_reg (enum machine_mode mode, rtx val)
17959 enum machine_mode valmode = GET_MODE (val);
17961 int nops = mode == DImode ? 3 : 2;
17963 gcc_assert (mode == SImode || mode == DImode);
17964 if (val == const0_rtx)
17965 return copy_to_mode_reg (mode, const0_rtx);
17966 if (CONST_INT_P (val))
17968 HOST_WIDE_INT v = INTVAL (val) & 255;
17972 if (mode == DImode)
17973 v |= (v << 16) << 16;
17974 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
17977 if (valmode == VOIDmode)
17979 if (valmode != QImode)
17980 val = gen_lowpart (QImode, val);
17981 if (mode == QImode)
17983 if (!TARGET_PARTIAL_REG_STALL)
17985 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
17986 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
17987 <= (ix86_cost->shift_const + ix86_cost->add) * nops
17988 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
17990 rtx reg = convert_modes (mode, QImode, val, true);
17991 tmp = promote_duplicated_reg (mode, const1_rtx);
17992 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
17997 rtx reg = convert_modes (mode, QImode, val, true);
17999 if (!TARGET_PARTIAL_REG_STALL)
18000 if (mode == SImode)
18001 emit_insn (gen_movsi_insv_1 (reg, reg));
18003 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18006 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18007 NULL, 1, OPTAB_DIRECT);
18009 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18011 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18012 NULL, 1, OPTAB_DIRECT);
18013 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18014 if (mode == SImode)
18016 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18017 NULL, 1, OPTAB_DIRECT);
18018 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18023 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18024 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18025 alignment from ALIGN to DESIRED_ALIGN. */
18027 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18032 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18033 promoted_val = promote_duplicated_reg (DImode, val);
18034 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18035 promoted_val = promote_duplicated_reg (SImode, val);
18036 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18037 promoted_val = promote_duplicated_reg (HImode, val);
18039 promoted_val = val;
18041 return promoted_val;
18044 /* Expand string clear operation (bzero). Use i386 string operations when
18045 profitable. See expand_movmem comment for explanation of individual
18046 steps performed. */
18048 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18049 rtx expected_align_exp, rtx expected_size_exp)
18054 rtx jump_around_label = NULL;
18055 HOST_WIDE_INT align = 1;
18056 unsigned HOST_WIDE_INT count = 0;
18057 HOST_WIDE_INT expected_size = -1;
18058 int size_needed = 0, epilogue_size_needed;
18059 int desired_align = 0, align_bytes = 0;
18060 enum stringop_alg alg;
18061 rtx promoted_val = NULL;
18062 bool force_loopy_epilogue = false;
18064 bool need_zero_guard = false;
18066 if (CONST_INT_P (align_exp))
18067 align = INTVAL (align_exp);
18068 /* i386 can do misaligned access on reasonably increased cost. */
18069 if (CONST_INT_P (expected_align_exp)
18070 && INTVAL (expected_align_exp) > align)
18071 align = INTVAL (expected_align_exp);
18072 if (CONST_INT_P (count_exp))
18073 count = expected_size = INTVAL (count_exp);
18074 if (CONST_INT_P (expected_size_exp) && count == 0)
18075 expected_size = INTVAL (expected_size_exp);
18077 /* Make sure we don't need to care about overflow later on. */
18078 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18081 /* Step 0: Decide on preferred algorithm, desired alignment and
18082 size of chunks to be copied by main loop. */
18084 alg = decide_alg (count, expected_size, true, &dynamic_check);
18085 desired_align = decide_alignment (align, alg, expected_size);
18087 if (!TARGET_ALIGN_STRINGOPS)
18088 align = desired_align;
18090 if (alg == libcall)
18092 gcc_assert (alg != no_stringop);
18094 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18095 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18100 gcc_unreachable ();
18102 need_zero_guard = true;
18103 size_needed = GET_MODE_SIZE (Pmode);
18105 case unrolled_loop:
18106 need_zero_guard = true;
18107 size_needed = GET_MODE_SIZE (Pmode) * 4;
18109 case rep_prefix_8_byte:
18112 case rep_prefix_4_byte:
18115 case rep_prefix_1_byte:
18119 need_zero_guard = true;
18123 epilogue_size_needed = size_needed;
18125 /* Step 1: Prologue guard. */
18127 /* Alignment code needs count to be in register. */
18128 if (CONST_INT_P (count_exp) && desired_align > align)
18130 if (INTVAL (count_exp) > desired_align
18131 && INTVAL (count_exp) > size_needed)
18134 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18135 if (align_bytes <= 0)
18138 align_bytes = desired_align - align_bytes;
18140 if (align_bytes == 0)
18142 enum machine_mode mode = SImode;
18143 if (TARGET_64BIT && (count & ~0xffffffff))
18145 count_exp = force_reg (mode, count_exp);
18148 /* Do the cheap promotion to allow better CSE across the
18149 main loop and epilogue (ie one load of the big constant in the
18150 front of all code. */
18151 if (CONST_INT_P (val_exp))
18152 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18153 desired_align, align);
18154 /* Ensure that alignment prologue won't copy past end of block. */
18155 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18157 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18158 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18159 Make sure it is power of 2. */
18160 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18162 /* To improve performance of small blocks, we jump around the VAL
18163 promoting mode. This mean that if the promoted VAL is not constant,
18164 we might not use it in the epilogue and have to use byte
18166 if (epilogue_size_needed > 2 && !promoted_val)
18167 force_loopy_epilogue = true;
18170 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18172 /* If main algorithm works on QImode, no epilogue is needed.
18173 For small sizes just don't align anything. */
18174 if (size_needed == 1)
18175 desired_align = align;
18182 label = gen_label_rtx ();
18183 emit_cmp_and_jump_insns (count_exp,
18184 GEN_INT (epilogue_size_needed),
18185 LTU, 0, counter_mode (count_exp), 1, label);
18186 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18187 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18189 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18192 if (dynamic_check != -1)
18194 rtx hot_label = gen_label_rtx ();
18195 jump_around_label = gen_label_rtx ();
18196 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18197 LEU, 0, counter_mode (count_exp), 1, hot_label);
18198 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18199 set_storage_via_libcall (dst, count_exp, val_exp, false);
18200 emit_jump (jump_around_label);
18201 emit_label (hot_label);
18204 /* Step 2: Alignment prologue. */
18206 /* Do the expensive promotion once we branched off the small blocks. */
18208 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18209 desired_align, align);
18210 gcc_assert (desired_align >= 1 && align >= 1);
18212 if (desired_align > align)
18214 if (align_bytes == 0)
18216 /* Except for the first move in epilogue, we no longer know
18217 constant offset in aliasing info. It don't seems to worth
18218 the pain to maintain it for the first move, so throw away
18220 dst = change_address (dst, BLKmode, destreg);
18221 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18226 /* If we know how many bytes need to be stored before dst is
18227 sufficiently aligned, maintain aliasing info accurately. */
18228 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18229 desired_align, align_bytes);
18230 count_exp = plus_constant (count_exp, -align_bytes);
18231 count -= align_bytes;
18233 if (need_zero_guard
18234 && (count < (unsigned HOST_WIDE_INT) size_needed
18235 || (align_bytes == 0
18236 && count < ((unsigned HOST_WIDE_INT) size_needed
18237 + desired_align - align))))
18239 /* It is possible that we copied enough so the main loop will not
18241 gcc_assert (size_needed > 1);
18242 if (label == NULL_RTX)
18243 label = gen_label_rtx ();
18244 emit_cmp_and_jump_insns (count_exp,
18245 GEN_INT (size_needed),
18246 LTU, 0, counter_mode (count_exp), 1, label);
18247 if (expected_size == -1
18248 || expected_size < (desired_align - align) / 2 + size_needed)
18249 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18251 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18254 if (label && size_needed == 1)
18256 emit_label (label);
18257 LABEL_NUSES (label) = 1;
18259 promoted_val = val_exp;
18260 epilogue_size_needed = 1;
18262 else if (label == NULL_RTX)
18263 epilogue_size_needed = size_needed;
18265 /* Step 3: Main loop. */
18271 gcc_unreachable ();
18273 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18274 count_exp, QImode, 1, expected_size);
18277 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18278 count_exp, Pmode, 1, expected_size);
18280 case unrolled_loop:
18281 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18282 count_exp, Pmode, 4, expected_size);
18284 case rep_prefix_8_byte:
18285 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18288 case rep_prefix_4_byte:
18289 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18292 case rep_prefix_1_byte:
18293 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18297 /* Adjust properly the offset of src and dest memory for aliasing. */
18298 if (CONST_INT_P (count_exp))
18299 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18300 (count / size_needed) * size_needed);
18302 dst = change_address (dst, BLKmode, destreg);
18304 /* Step 4: Epilogue to copy the remaining bytes. */
18308 /* When the main loop is done, COUNT_EXP might hold original count,
18309 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18310 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18311 bytes. Compensate if needed. */
18313 if (size_needed < epilogue_size_needed)
18316 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18317 GEN_INT (size_needed - 1), count_exp, 1,
18319 if (tmp != count_exp)
18320 emit_move_insn (count_exp, tmp);
18322 emit_label (label);
18323 LABEL_NUSES (label) = 1;
18326 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18328 if (force_loopy_epilogue)
18329 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18330 epilogue_size_needed);
18332 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18333 epilogue_size_needed);
18335 if (jump_around_label)
18336 emit_label (jump_around_label);
18340 /* Expand the appropriate insns for doing strlen if not just doing
18343 out = result, initialized with the start address
18344 align_rtx = alignment of the address.
18345 scratch = scratch register, initialized with the startaddress when
18346 not aligned, otherwise undefined
18348 This is just the body. It needs the initializations mentioned above and
18349 some address computing at the end. These things are done in i386.md. */
18352 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18356 rtx align_2_label = NULL_RTX;
18357 rtx align_3_label = NULL_RTX;
18358 rtx align_4_label = gen_label_rtx ();
18359 rtx end_0_label = gen_label_rtx ();
18361 rtx tmpreg = gen_reg_rtx (SImode);
18362 rtx scratch = gen_reg_rtx (SImode);
18366 if (CONST_INT_P (align_rtx))
18367 align = INTVAL (align_rtx);
18369 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18371 /* Is there a known alignment and is it less than 4? */
18374 rtx scratch1 = gen_reg_rtx (Pmode);
18375 emit_move_insn (scratch1, out);
18376 /* Is there a known alignment and is it not 2? */
18379 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18380 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18382 /* Leave just the 3 lower bits. */
18383 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18384 NULL_RTX, 0, OPTAB_WIDEN);
18386 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18387 Pmode, 1, align_4_label);
18388 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18389 Pmode, 1, align_2_label);
18390 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18391 Pmode, 1, align_3_label);
18395 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18396 check if is aligned to 4 - byte. */
18398 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18399 NULL_RTX, 0, OPTAB_WIDEN);
18401 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18402 Pmode, 1, align_4_label);
18405 mem = change_address (src, QImode, out);
18407 /* Now compare the bytes. */
18409 /* Compare the first n unaligned byte on a byte per byte basis. */
18410 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18411 QImode, 1, end_0_label);
18413 /* Increment the address. */
18414 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18416 /* Not needed with an alignment of 2 */
18419 emit_label (align_2_label);
18421 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18424 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18426 emit_label (align_3_label);
18429 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18432 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18435 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18436 align this loop. It gives only huge programs, but does not help to
18438 emit_label (align_4_label);
18440 mem = change_address (src, SImode, out);
18441 emit_move_insn (scratch, mem);
18442 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18444 /* This formula yields a nonzero result iff one of the bytes is zero.
18445 This saves three branches inside loop and many cycles. */
18447 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18448 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18449 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18450 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18451 gen_int_mode (0x80808080, SImode)));
18452 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18457 rtx reg = gen_reg_rtx (SImode);
18458 rtx reg2 = gen_reg_rtx (Pmode);
18459 emit_move_insn (reg, tmpreg);
18460 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18462 /* If zero is not in the first two bytes, move two bytes forward. */
18463 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18464 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18465 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18466 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18467 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18470 /* Emit lea manually to avoid clobbering of flags. */
18471 emit_insn (gen_rtx_SET (SImode, reg2,
18472 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18474 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18475 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18476 emit_insn (gen_rtx_SET (VOIDmode, out,
18477 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18484 rtx end_2_label = gen_label_rtx ();
18485 /* Is zero in the first two bytes? */
18487 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18488 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18489 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18490 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18491 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18493 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18494 JUMP_LABEL (tmp) = end_2_label;
18496 /* Not in the first two. Move two bytes forward. */
18497 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18498 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18500 emit_label (end_2_label);
18504 /* Avoid branch in fixing the byte. */
18505 tmpreg = gen_lowpart (QImode, tmpreg);
18506 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18507 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18508 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18510 emit_label (end_0_label);
18513 /* Expand strlen. */
18516 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18518 rtx addr, scratch1, scratch2, scratch3, scratch4;
18520 /* The generic case of strlen expander is long. Avoid it's
18521 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18523 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18524 && !TARGET_INLINE_ALL_STRINGOPS
18525 && !optimize_insn_for_size_p ()
18526 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18529 addr = force_reg (Pmode, XEXP (src, 0));
18530 scratch1 = gen_reg_rtx (Pmode);
18532 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18533 && !optimize_insn_for_size_p ())
18535 /* Well it seems that some optimizer does not combine a call like
18536 foo(strlen(bar), strlen(bar));
18537 when the move and the subtraction is done here. It does calculate
18538 the length just once when these instructions are done inside of
18539 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18540 often used and I use one fewer register for the lifetime of
18541 output_strlen_unroll() this is better. */
18543 emit_move_insn (out, addr);
18545 ix86_expand_strlensi_unroll_1 (out, src, align);
18547 /* strlensi_unroll_1 returns the address of the zero at the end of
18548 the string, like memchr(), so compute the length by subtracting
18549 the start address. */
18550 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18556 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18557 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18560 scratch2 = gen_reg_rtx (Pmode);
18561 scratch3 = gen_reg_rtx (Pmode);
18562 scratch4 = force_reg (Pmode, constm1_rtx);
18564 emit_move_insn (scratch3, addr);
18565 eoschar = force_reg (QImode, eoschar);
18567 src = replace_equiv_address_nv (src, scratch3);
18569 /* If .md starts supporting :P, this can be done in .md. */
18570 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18571 scratch4), UNSPEC_SCAS);
18572 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18573 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18574 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18579 /* For given symbol (function) construct code to compute address of it's PLT
18580 entry in large x86-64 PIC model. */
18582 construct_plt_address (rtx symbol)
18584 rtx tmp = gen_reg_rtx (Pmode);
18585 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18587 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18588 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18590 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18591 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18596 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18598 rtx pop, int sibcall)
18600 rtx use = NULL, call;
18601 enum calling_abi function_call_abi;
18603 if (callarg2 && INTVAL (callarg2) == -2)
18604 function_call_abi = MS_ABI;
18606 function_call_abi = SYSV_ABI;
18607 if (pop == const0_rtx)
18609 gcc_assert (!TARGET_64BIT || !pop);
18611 if (TARGET_MACHO && !TARGET_64BIT)
18614 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18615 fnaddr = machopic_indirect_call_target (fnaddr);
18620 /* Static functions and indirect calls don't need the pic register. */
18621 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18622 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18623 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18624 use_reg (&use, pic_offset_table_rtx);
18627 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18629 rtx al = gen_rtx_REG (QImode, AX_REG);
18630 emit_move_insn (al, callarg2);
18631 use_reg (&use, al);
18634 if (ix86_cmodel == CM_LARGE_PIC
18635 && GET_CODE (fnaddr) == MEM
18636 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18637 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18638 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18639 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
18641 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18642 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18644 if (sibcall && TARGET_64BIT
18645 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
18648 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18649 fnaddr = gen_rtx_REG (Pmode, R11_REG);
18650 emit_move_insn (fnaddr, addr);
18651 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18654 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18656 call = gen_rtx_SET (VOIDmode, retval, call);
18659 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18660 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18661 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18662 gcc_assert (ix86_cfun_abi () != MS_ABI || function_call_abi != SYSV_ABI);
18664 /* We need to represent that SI and DI registers are clobbered
18666 if (ix86_cfun_abi () == MS_ABI && function_call_abi == SYSV_ABI)
18668 static int clobbered_registers[] = {27, 28, 45, 46, 47, 48, 49, 50, 51,
18669 52, SI_REG, DI_REG};
18671 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18672 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18673 UNSPEC_MS_TO_SYSV_CALL);
18677 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18678 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18681 (SSE_REGNO_P (clobbered_registers[i])
18683 clobbered_registers[i]));
18685 call = gen_rtx_PARALLEL (VOIDmode,
18686 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18690 call = emit_call_insn (call);
18692 CALL_INSN_FUNCTION_USAGE (call) = use;
18696 /* Clear stack slot assignments remembered from previous functions.
18697 This is called from INIT_EXPANDERS once before RTL is emitted for each
18700 static struct machine_function *
18701 ix86_init_machine_status (void)
18703 struct machine_function *f;
18705 f = GGC_CNEW (struct machine_function);
18706 f->use_fast_prologue_epilogue_nregs = -1;
18707 f->tls_descriptor_call_expanded_p = 0;
18708 f->call_abi = DEFAULT_ABI;
18713 /* Return a MEM corresponding to a stack slot with mode MODE.
18714 Allocate a new slot if necessary.
18716 The RTL for a function can have several slots available: N is
18717 which slot to use. */
18720 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18722 struct stack_local_entry *s;
18724 gcc_assert (n < MAX_386_STACK_LOCALS);
18726 /* Virtual slot is valid only before vregs are instantiated. */
18727 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18729 for (s = ix86_stack_locals; s; s = s->next)
18730 if (s->mode == mode && s->n == n)
18731 return copy_rtx (s->rtl);
18733 s = (struct stack_local_entry *)
18734 ggc_alloc (sizeof (struct stack_local_entry));
18737 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18739 s->next = ix86_stack_locals;
18740 ix86_stack_locals = s;
18744 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18746 static GTY(()) rtx ix86_tls_symbol;
18748 ix86_tls_get_addr (void)
18751 if (!ix86_tls_symbol)
18753 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18754 (TARGET_ANY_GNU_TLS
18756 ? "___tls_get_addr"
18757 : "__tls_get_addr");
18760 return ix86_tls_symbol;
18763 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18765 static GTY(()) rtx ix86_tls_module_base_symbol;
18767 ix86_tls_module_base (void)
18770 if (!ix86_tls_module_base_symbol)
18772 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18773 "_TLS_MODULE_BASE_");
18774 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18775 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18778 return ix86_tls_module_base_symbol;
18781 /* Calculate the length of the memory address in the instruction
18782 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18785 memory_address_length (rtx addr)
18787 struct ix86_address parts;
18788 rtx base, index, disp;
18792 if (GET_CODE (addr) == PRE_DEC
18793 || GET_CODE (addr) == POST_INC
18794 || GET_CODE (addr) == PRE_MODIFY
18795 || GET_CODE (addr) == POST_MODIFY)
18798 ok = ix86_decompose_address (addr, &parts);
18801 if (parts.base && GET_CODE (parts.base) == SUBREG)
18802 parts.base = SUBREG_REG (parts.base);
18803 if (parts.index && GET_CODE (parts.index) == SUBREG)
18804 parts.index = SUBREG_REG (parts.index);
18807 index = parts.index;
18812 - esp as the base always wants an index,
18813 - ebp as the base always wants a displacement. */
18815 /* Register Indirect. */
18816 if (base && !index && !disp)
18818 /* esp (for its index) and ebp (for its displacement) need
18819 the two-byte modrm form. */
18820 if (addr == stack_pointer_rtx
18821 || addr == arg_pointer_rtx
18822 || addr == frame_pointer_rtx
18823 || addr == hard_frame_pointer_rtx)
18827 /* Direct Addressing. */
18828 else if (disp && !base && !index)
18833 /* Find the length of the displacement constant. */
18836 if (base && satisfies_constraint_K (disp))
18841 /* ebp always wants a displacement. */
18842 else if (base == hard_frame_pointer_rtx)
18845 /* An index requires the two-byte modrm form.... */
18847 /* ...like esp, which always wants an index. */
18848 || base == stack_pointer_rtx
18849 || base == arg_pointer_rtx
18850 || base == frame_pointer_rtx)
18857 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18858 is set, expect that insn have 8bit immediate alternative. */
18860 ix86_attr_length_immediate_default (rtx insn, int shortform)
18864 extract_insn_cached (insn);
18865 for (i = recog_data.n_operands - 1; i >= 0; --i)
18866 if (CONSTANT_P (recog_data.operand[i]))
18869 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
18873 switch (get_attr_mode (insn))
18884 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18889 fatal_insn ("unknown insn mode", insn);
18895 /* Compute default value for "length_address" attribute. */
18897 ix86_attr_length_address_default (rtx insn)
18901 if (get_attr_type (insn) == TYPE_LEA)
18903 rtx set = PATTERN (insn);
18905 if (GET_CODE (set) == PARALLEL)
18906 set = XVECEXP (set, 0, 0);
18908 gcc_assert (GET_CODE (set) == SET);
18910 return memory_address_length (SET_SRC (set));
18913 extract_insn_cached (insn);
18914 for (i = recog_data.n_operands - 1; i >= 0; --i)
18915 if (MEM_P (recog_data.operand[i]))
18917 return memory_address_length (XEXP (recog_data.operand[i], 0));
18923 /* Compute default value for "length_vex" attribute. It includes
18924 2 or 3 byte VEX prefix and 1 opcode byte. */
18927 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
18932 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18933 byte VEX prefix. */
18934 if (!has_0f_opcode || has_vex_w)
18937 /* We can always use 2 byte VEX prefix in 32bit. */
18941 extract_insn_cached (insn);
18943 for (i = recog_data.n_operands - 1; i >= 0; --i)
18944 if (REG_P (recog_data.operand[i]))
18946 /* REX.W bit uses 3 byte VEX prefix. */
18947 if (GET_MODE (recog_data.operand[i]) == DImode)
18952 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18953 if (MEM_P (recog_data.operand[i])
18954 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
18961 /* Return the maximum number of instructions a cpu can issue. */
18964 ix86_issue_rate (void)
18968 case PROCESSOR_PENTIUM:
18972 case PROCESSOR_PENTIUMPRO:
18973 case PROCESSOR_PENTIUM4:
18974 case PROCESSOR_ATHLON:
18976 case PROCESSOR_AMDFAM10:
18977 case PROCESSOR_NOCONA:
18978 case PROCESSOR_GENERIC32:
18979 case PROCESSOR_GENERIC64:
18982 case PROCESSOR_CORE2:
18990 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
18991 by DEP_INSN and nothing set by DEP_INSN. */
18994 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
18998 /* Simplify the test for uninteresting insns. */
18999 if (insn_type != TYPE_SETCC
19000 && insn_type != TYPE_ICMOV
19001 && insn_type != TYPE_FCMOV
19002 && insn_type != TYPE_IBR)
19005 if ((set = single_set (dep_insn)) != 0)
19007 set = SET_DEST (set);
19010 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19011 && XVECLEN (PATTERN (dep_insn), 0) == 2
19012 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19013 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19015 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19016 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19021 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19024 /* This test is true if the dependent insn reads the flags but
19025 not any other potentially set register. */
19026 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19029 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19035 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19036 address with operands set by DEP_INSN. */
19039 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19043 if (insn_type == TYPE_LEA
19046 addr = PATTERN (insn);
19048 if (GET_CODE (addr) == PARALLEL)
19049 addr = XVECEXP (addr, 0, 0);
19051 gcc_assert (GET_CODE (addr) == SET);
19053 addr = SET_SRC (addr);
19058 extract_insn_cached (insn);
19059 for (i = recog_data.n_operands - 1; i >= 0; --i)
19060 if (MEM_P (recog_data.operand[i]))
19062 addr = XEXP (recog_data.operand[i], 0);
19069 return modified_in_p (addr, dep_insn);
19073 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19075 enum attr_type insn_type, dep_insn_type;
19076 enum attr_memory memory;
19078 int dep_insn_code_number;
19080 /* Anti and output dependencies have zero cost on all CPUs. */
19081 if (REG_NOTE_KIND (link) != 0)
19084 dep_insn_code_number = recog_memoized (dep_insn);
19086 /* If we can't recognize the insns, we can't really do anything. */
19087 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19090 insn_type = get_attr_type (insn);
19091 dep_insn_type = get_attr_type (dep_insn);
19095 case PROCESSOR_PENTIUM:
19096 /* Address Generation Interlock adds a cycle of latency. */
19097 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19100 /* ??? Compares pair with jump/setcc. */
19101 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19104 /* Floating point stores require value to be ready one cycle earlier. */
19105 if (insn_type == TYPE_FMOV
19106 && get_attr_memory (insn) == MEMORY_STORE
19107 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19111 case PROCESSOR_PENTIUMPRO:
19112 memory = get_attr_memory (insn);
19114 /* INT->FP conversion is expensive. */
19115 if (get_attr_fp_int_src (dep_insn))
19118 /* There is one cycle extra latency between an FP op and a store. */
19119 if (insn_type == TYPE_FMOV
19120 && (set = single_set (dep_insn)) != NULL_RTX
19121 && (set2 = single_set (insn)) != NULL_RTX
19122 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19123 && MEM_P (SET_DEST (set2)))
19126 /* Show ability of reorder buffer to hide latency of load by executing
19127 in parallel with previous instruction in case
19128 previous instruction is not needed to compute the address. */
19129 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19130 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19132 /* Claim moves to take one cycle, as core can issue one load
19133 at time and the next load can start cycle later. */
19134 if (dep_insn_type == TYPE_IMOV
19135 || dep_insn_type == TYPE_FMOV)
19143 memory = get_attr_memory (insn);
19145 /* The esp dependency is resolved before the instruction is really
19147 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19148 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19151 /* INT->FP conversion is expensive. */
19152 if (get_attr_fp_int_src (dep_insn))
19155 /* Show ability of reorder buffer to hide latency of load by executing
19156 in parallel with previous instruction in case
19157 previous instruction is not needed to compute the address. */
19158 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19159 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19161 /* Claim moves to take one cycle, as core can issue one load
19162 at time and the next load can start cycle later. */
19163 if (dep_insn_type == TYPE_IMOV
19164 || dep_insn_type == TYPE_FMOV)
19173 case PROCESSOR_ATHLON:
19175 case PROCESSOR_AMDFAM10:
19176 case PROCESSOR_GENERIC32:
19177 case PROCESSOR_GENERIC64:
19178 memory = get_attr_memory (insn);
19180 /* Show ability of reorder buffer to hide latency of load by executing
19181 in parallel with previous instruction in case
19182 previous instruction is not needed to compute the address. */
19183 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19184 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19186 enum attr_unit unit = get_attr_unit (insn);
19189 /* Because of the difference between the length of integer and
19190 floating unit pipeline preparation stages, the memory operands
19191 for floating point are cheaper.
19193 ??? For Athlon it the difference is most probably 2. */
19194 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19197 loadcost = TARGET_ATHLON ? 2 : 0;
19199 if (cost >= loadcost)
19212 /* How many alternative schedules to try. This should be as wide as the
19213 scheduling freedom in the DFA, but no wider. Making this value too
19214 large results extra work for the scheduler. */
19217 ia32_multipass_dfa_lookahead (void)
19221 case PROCESSOR_PENTIUM:
19224 case PROCESSOR_PENTIUMPRO:
19234 /* Compute the alignment given to a constant that is being placed in memory.
19235 EXP is the constant and ALIGN is the alignment that the object would
19237 The value of this function is used instead of that alignment to align
19241 ix86_constant_alignment (tree exp, int align)
19243 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19244 || TREE_CODE (exp) == INTEGER_CST)
19246 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19248 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19251 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19252 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19253 return BITS_PER_WORD;
19258 /* Compute the alignment for a static variable.
19259 TYPE is the data type, and ALIGN is the alignment that
19260 the object would ordinarily have. The value of this function is used
19261 instead of that alignment to align the object. */
19264 ix86_data_alignment (tree type, int align)
19266 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19268 if (AGGREGATE_TYPE_P (type)
19269 && TYPE_SIZE (type)
19270 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19271 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19272 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19273 && align < max_align)
19276 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19277 to 16byte boundary. */
19280 if (AGGREGATE_TYPE_P (type)
19281 && TYPE_SIZE (type)
19282 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19283 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19284 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19288 if (TREE_CODE (type) == ARRAY_TYPE)
19290 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19292 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19295 else if (TREE_CODE (type) == COMPLEX_TYPE)
19298 if (TYPE_MODE (type) == DCmode && align < 64)
19300 if ((TYPE_MODE (type) == XCmode
19301 || TYPE_MODE (type) == TCmode) && align < 128)
19304 else if ((TREE_CODE (type) == RECORD_TYPE
19305 || TREE_CODE (type) == UNION_TYPE
19306 || TREE_CODE (type) == QUAL_UNION_TYPE)
19307 && TYPE_FIELDS (type))
19309 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19311 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19314 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19315 || TREE_CODE (type) == INTEGER_TYPE)
19317 if (TYPE_MODE (type) == DFmode && align < 64)
19319 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19326 /* Compute the alignment for a local variable or a stack slot. TYPE is
19327 the data type, MODE is the widest mode available and ALIGN is the
19328 alignment that the object would ordinarily have. The value of this
19329 macro is used instead of that alignment to align the object. */
19332 ix86_local_alignment (tree type, enum machine_mode mode,
19333 unsigned int align)
19335 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19336 register in MODE. We will return the largest alignment of XF
19340 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19341 align = GET_MODE_ALIGNMENT (DFmode);
19345 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19346 to 16byte boundary. */
19349 if (AGGREGATE_TYPE_P (type)
19350 && TYPE_SIZE (type)
19351 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19352 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19353 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19356 if (TREE_CODE (type) == ARRAY_TYPE)
19358 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19360 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19363 else if (TREE_CODE (type) == COMPLEX_TYPE)
19365 if (TYPE_MODE (type) == DCmode && align < 64)
19367 if ((TYPE_MODE (type) == XCmode
19368 || TYPE_MODE (type) == TCmode) && align < 128)
19371 else if ((TREE_CODE (type) == RECORD_TYPE
19372 || TREE_CODE (type) == UNION_TYPE
19373 || TREE_CODE (type) == QUAL_UNION_TYPE)
19374 && TYPE_FIELDS (type))
19376 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19378 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19381 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19382 || TREE_CODE (type) == INTEGER_TYPE)
19385 if (TYPE_MODE (type) == DFmode && align < 64)
19387 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19393 /* Emit RTL insns to initialize the variable parts of a trampoline.
19394 FNADDR is an RTX for the address of the function's pure code.
19395 CXT is an RTX for the static chain value for the function. */
19397 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19401 /* Compute offset from the end of the jmp to the target function. */
19402 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19403 plus_constant (tramp, 10),
19404 NULL_RTX, 1, OPTAB_DIRECT);
19405 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19406 gen_int_mode (0xb9, QImode));
19407 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19408 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19409 gen_int_mode (0xe9, QImode));
19410 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19415 /* Try to load address using shorter movl instead of movabs.
19416 We may want to support movq for kernel mode, but kernel does not use
19417 trampolines at the moment. */
19418 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19420 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19421 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19422 gen_int_mode (0xbb41, HImode));
19423 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19424 gen_lowpart (SImode, fnaddr));
19429 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19430 gen_int_mode (0xbb49, HImode));
19431 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19435 /* Load static chain using movabs to r10. */
19436 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19437 gen_int_mode (0xba49, HImode));
19438 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19441 /* Jump to the r11 */
19442 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19443 gen_int_mode (0xff49, HImode));
19444 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19445 gen_int_mode (0xe3, QImode));
19447 gcc_assert (offset <= TRAMPOLINE_SIZE);
19450 #ifdef ENABLE_EXECUTE_STACK
19451 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19452 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19456 /* Codes for all the SSE/MMX builtins. */
19459 IX86_BUILTIN_ADDPS,
19460 IX86_BUILTIN_ADDSS,
19461 IX86_BUILTIN_DIVPS,
19462 IX86_BUILTIN_DIVSS,
19463 IX86_BUILTIN_MULPS,
19464 IX86_BUILTIN_MULSS,
19465 IX86_BUILTIN_SUBPS,
19466 IX86_BUILTIN_SUBSS,
19468 IX86_BUILTIN_CMPEQPS,
19469 IX86_BUILTIN_CMPLTPS,
19470 IX86_BUILTIN_CMPLEPS,
19471 IX86_BUILTIN_CMPGTPS,
19472 IX86_BUILTIN_CMPGEPS,
19473 IX86_BUILTIN_CMPNEQPS,
19474 IX86_BUILTIN_CMPNLTPS,
19475 IX86_BUILTIN_CMPNLEPS,
19476 IX86_BUILTIN_CMPNGTPS,
19477 IX86_BUILTIN_CMPNGEPS,
19478 IX86_BUILTIN_CMPORDPS,
19479 IX86_BUILTIN_CMPUNORDPS,
19480 IX86_BUILTIN_CMPEQSS,
19481 IX86_BUILTIN_CMPLTSS,
19482 IX86_BUILTIN_CMPLESS,
19483 IX86_BUILTIN_CMPNEQSS,
19484 IX86_BUILTIN_CMPNLTSS,
19485 IX86_BUILTIN_CMPNLESS,
19486 IX86_BUILTIN_CMPNGTSS,
19487 IX86_BUILTIN_CMPNGESS,
19488 IX86_BUILTIN_CMPORDSS,
19489 IX86_BUILTIN_CMPUNORDSS,
19491 IX86_BUILTIN_COMIEQSS,
19492 IX86_BUILTIN_COMILTSS,
19493 IX86_BUILTIN_COMILESS,
19494 IX86_BUILTIN_COMIGTSS,
19495 IX86_BUILTIN_COMIGESS,
19496 IX86_BUILTIN_COMINEQSS,
19497 IX86_BUILTIN_UCOMIEQSS,
19498 IX86_BUILTIN_UCOMILTSS,
19499 IX86_BUILTIN_UCOMILESS,
19500 IX86_BUILTIN_UCOMIGTSS,
19501 IX86_BUILTIN_UCOMIGESS,
19502 IX86_BUILTIN_UCOMINEQSS,
19504 IX86_BUILTIN_CVTPI2PS,
19505 IX86_BUILTIN_CVTPS2PI,
19506 IX86_BUILTIN_CVTSI2SS,
19507 IX86_BUILTIN_CVTSI642SS,
19508 IX86_BUILTIN_CVTSS2SI,
19509 IX86_BUILTIN_CVTSS2SI64,
19510 IX86_BUILTIN_CVTTPS2PI,
19511 IX86_BUILTIN_CVTTSS2SI,
19512 IX86_BUILTIN_CVTTSS2SI64,
19514 IX86_BUILTIN_MAXPS,
19515 IX86_BUILTIN_MAXSS,
19516 IX86_BUILTIN_MINPS,
19517 IX86_BUILTIN_MINSS,
19519 IX86_BUILTIN_LOADUPS,
19520 IX86_BUILTIN_STOREUPS,
19521 IX86_BUILTIN_MOVSS,
19523 IX86_BUILTIN_MOVHLPS,
19524 IX86_BUILTIN_MOVLHPS,
19525 IX86_BUILTIN_LOADHPS,
19526 IX86_BUILTIN_LOADLPS,
19527 IX86_BUILTIN_STOREHPS,
19528 IX86_BUILTIN_STORELPS,
19530 IX86_BUILTIN_MASKMOVQ,
19531 IX86_BUILTIN_MOVMSKPS,
19532 IX86_BUILTIN_PMOVMSKB,
19534 IX86_BUILTIN_MOVNTPS,
19535 IX86_BUILTIN_MOVNTQ,
19537 IX86_BUILTIN_LOADDQU,
19538 IX86_BUILTIN_STOREDQU,
19540 IX86_BUILTIN_PACKSSWB,
19541 IX86_BUILTIN_PACKSSDW,
19542 IX86_BUILTIN_PACKUSWB,
19544 IX86_BUILTIN_PADDB,
19545 IX86_BUILTIN_PADDW,
19546 IX86_BUILTIN_PADDD,
19547 IX86_BUILTIN_PADDQ,
19548 IX86_BUILTIN_PADDSB,
19549 IX86_BUILTIN_PADDSW,
19550 IX86_BUILTIN_PADDUSB,
19551 IX86_BUILTIN_PADDUSW,
19552 IX86_BUILTIN_PSUBB,
19553 IX86_BUILTIN_PSUBW,
19554 IX86_BUILTIN_PSUBD,
19555 IX86_BUILTIN_PSUBQ,
19556 IX86_BUILTIN_PSUBSB,
19557 IX86_BUILTIN_PSUBSW,
19558 IX86_BUILTIN_PSUBUSB,
19559 IX86_BUILTIN_PSUBUSW,
19562 IX86_BUILTIN_PANDN,
19566 IX86_BUILTIN_PAVGB,
19567 IX86_BUILTIN_PAVGW,
19569 IX86_BUILTIN_PCMPEQB,
19570 IX86_BUILTIN_PCMPEQW,
19571 IX86_BUILTIN_PCMPEQD,
19572 IX86_BUILTIN_PCMPGTB,
19573 IX86_BUILTIN_PCMPGTW,
19574 IX86_BUILTIN_PCMPGTD,
19576 IX86_BUILTIN_PMADDWD,
19578 IX86_BUILTIN_PMAXSW,
19579 IX86_BUILTIN_PMAXUB,
19580 IX86_BUILTIN_PMINSW,
19581 IX86_BUILTIN_PMINUB,
19583 IX86_BUILTIN_PMULHUW,
19584 IX86_BUILTIN_PMULHW,
19585 IX86_BUILTIN_PMULLW,
19587 IX86_BUILTIN_PSADBW,
19588 IX86_BUILTIN_PSHUFW,
19590 IX86_BUILTIN_PSLLW,
19591 IX86_BUILTIN_PSLLD,
19592 IX86_BUILTIN_PSLLQ,
19593 IX86_BUILTIN_PSRAW,
19594 IX86_BUILTIN_PSRAD,
19595 IX86_BUILTIN_PSRLW,
19596 IX86_BUILTIN_PSRLD,
19597 IX86_BUILTIN_PSRLQ,
19598 IX86_BUILTIN_PSLLWI,
19599 IX86_BUILTIN_PSLLDI,
19600 IX86_BUILTIN_PSLLQI,
19601 IX86_BUILTIN_PSRAWI,
19602 IX86_BUILTIN_PSRADI,
19603 IX86_BUILTIN_PSRLWI,
19604 IX86_BUILTIN_PSRLDI,
19605 IX86_BUILTIN_PSRLQI,
19607 IX86_BUILTIN_PUNPCKHBW,
19608 IX86_BUILTIN_PUNPCKHWD,
19609 IX86_BUILTIN_PUNPCKHDQ,
19610 IX86_BUILTIN_PUNPCKLBW,
19611 IX86_BUILTIN_PUNPCKLWD,
19612 IX86_BUILTIN_PUNPCKLDQ,
19614 IX86_BUILTIN_SHUFPS,
19616 IX86_BUILTIN_RCPPS,
19617 IX86_BUILTIN_RCPSS,
19618 IX86_BUILTIN_RSQRTPS,
19619 IX86_BUILTIN_RSQRTPS_NR,
19620 IX86_BUILTIN_RSQRTSS,
19621 IX86_BUILTIN_RSQRTF,
19622 IX86_BUILTIN_SQRTPS,
19623 IX86_BUILTIN_SQRTPS_NR,
19624 IX86_BUILTIN_SQRTSS,
19626 IX86_BUILTIN_UNPCKHPS,
19627 IX86_BUILTIN_UNPCKLPS,
19629 IX86_BUILTIN_ANDPS,
19630 IX86_BUILTIN_ANDNPS,
19632 IX86_BUILTIN_XORPS,
19635 IX86_BUILTIN_LDMXCSR,
19636 IX86_BUILTIN_STMXCSR,
19637 IX86_BUILTIN_SFENCE,
19639 /* 3DNow! Original */
19640 IX86_BUILTIN_FEMMS,
19641 IX86_BUILTIN_PAVGUSB,
19642 IX86_BUILTIN_PF2ID,
19643 IX86_BUILTIN_PFACC,
19644 IX86_BUILTIN_PFADD,
19645 IX86_BUILTIN_PFCMPEQ,
19646 IX86_BUILTIN_PFCMPGE,
19647 IX86_BUILTIN_PFCMPGT,
19648 IX86_BUILTIN_PFMAX,
19649 IX86_BUILTIN_PFMIN,
19650 IX86_BUILTIN_PFMUL,
19651 IX86_BUILTIN_PFRCP,
19652 IX86_BUILTIN_PFRCPIT1,
19653 IX86_BUILTIN_PFRCPIT2,
19654 IX86_BUILTIN_PFRSQIT1,
19655 IX86_BUILTIN_PFRSQRT,
19656 IX86_BUILTIN_PFSUB,
19657 IX86_BUILTIN_PFSUBR,
19658 IX86_BUILTIN_PI2FD,
19659 IX86_BUILTIN_PMULHRW,
19661 /* 3DNow! Athlon Extensions */
19662 IX86_BUILTIN_PF2IW,
19663 IX86_BUILTIN_PFNACC,
19664 IX86_BUILTIN_PFPNACC,
19665 IX86_BUILTIN_PI2FW,
19666 IX86_BUILTIN_PSWAPDSI,
19667 IX86_BUILTIN_PSWAPDSF,
19670 IX86_BUILTIN_ADDPD,
19671 IX86_BUILTIN_ADDSD,
19672 IX86_BUILTIN_DIVPD,
19673 IX86_BUILTIN_DIVSD,
19674 IX86_BUILTIN_MULPD,
19675 IX86_BUILTIN_MULSD,
19676 IX86_BUILTIN_SUBPD,
19677 IX86_BUILTIN_SUBSD,
19679 IX86_BUILTIN_CMPEQPD,
19680 IX86_BUILTIN_CMPLTPD,
19681 IX86_BUILTIN_CMPLEPD,
19682 IX86_BUILTIN_CMPGTPD,
19683 IX86_BUILTIN_CMPGEPD,
19684 IX86_BUILTIN_CMPNEQPD,
19685 IX86_BUILTIN_CMPNLTPD,
19686 IX86_BUILTIN_CMPNLEPD,
19687 IX86_BUILTIN_CMPNGTPD,
19688 IX86_BUILTIN_CMPNGEPD,
19689 IX86_BUILTIN_CMPORDPD,
19690 IX86_BUILTIN_CMPUNORDPD,
19691 IX86_BUILTIN_CMPEQSD,
19692 IX86_BUILTIN_CMPLTSD,
19693 IX86_BUILTIN_CMPLESD,
19694 IX86_BUILTIN_CMPNEQSD,
19695 IX86_BUILTIN_CMPNLTSD,
19696 IX86_BUILTIN_CMPNLESD,
19697 IX86_BUILTIN_CMPORDSD,
19698 IX86_BUILTIN_CMPUNORDSD,
19700 IX86_BUILTIN_COMIEQSD,
19701 IX86_BUILTIN_COMILTSD,
19702 IX86_BUILTIN_COMILESD,
19703 IX86_BUILTIN_COMIGTSD,
19704 IX86_BUILTIN_COMIGESD,
19705 IX86_BUILTIN_COMINEQSD,
19706 IX86_BUILTIN_UCOMIEQSD,
19707 IX86_BUILTIN_UCOMILTSD,
19708 IX86_BUILTIN_UCOMILESD,
19709 IX86_BUILTIN_UCOMIGTSD,
19710 IX86_BUILTIN_UCOMIGESD,
19711 IX86_BUILTIN_UCOMINEQSD,
19713 IX86_BUILTIN_MAXPD,
19714 IX86_BUILTIN_MAXSD,
19715 IX86_BUILTIN_MINPD,
19716 IX86_BUILTIN_MINSD,
19718 IX86_BUILTIN_ANDPD,
19719 IX86_BUILTIN_ANDNPD,
19721 IX86_BUILTIN_XORPD,
19723 IX86_BUILTIN_SQRTPD,
19724 IX86_BUILTIN_SQRTSD,
19726 IX86_BUILTIN_UNPCKHPD,
19727 IX86_BUILTIN_UNPCKLPD,
19729 IX86_BUILTIN_SHUFPD,
19731 IX86_BUILTIN_LOADUPD,
19732 IX86_BUILTIN_STOREUPD,
19733 IX86_BUILTIN_MOVSD,
19735 IX86_BUILTIN_LOADHPD,
19736 IX86_BUILTIN_LOADLPD,
19738 IX86_BUILTIN_CVTDQ2PD,
19739 IX86_BUILTIN_CVTDQ2PS,
19741 IX86_BUILTIN_CVTPD2DQ,
19742 IX86_BUILTIN_CVTPD2PI,
19743 IX86_BUILTIN_CVTPD2PS,
19744 IX86_BUILTIN_CVTTPD2DQ,
19745 IX86_BUILTIN_CVTTPD2PI,
19747 IX86_BUILTIN_CVTPI2PD,
19748 IX86_BUILTIN_CVTSI2SD,
19749 IX86_BUILTIN_CVTSI642SD,
19751 IX86_BUILTIN_CVTSD2SI,
19752 IX86_BUILTIN_CVTSD2SI64,
19753 IX86_BUILTIN_CVTSD2SS,
19754 IX86_BUILTIN_CVTSS2SD,
19755 IX86_BUILTIN_CVTTSD2SI,
19756 IX86_BUILTIN_CVTTSD2SI64,
19758 IX86_BUILTIN_CVTPS2DQ,
19759 IX86_BUILTIN_CVTPS2PD,
19760 IX86_BUILTIN_CVTTPS2DQ,
19762 IX86_BUILTIN_MOVNTI,
19763 IX86_BUILTIN_MOVNTPD,
19764 IX86_BUILTIN_MOVNTDQ,
19766 IX86_BUILTIN_MOVQ128,
19769 IX86_BUILTIN_MASKMOVDQU,
19770 IX86_BUILTIN_MOVMSKPD,
19771 IX86_BUILTIN_PMOVMSKB128,
19773 IX86_BUILTIN_PACKSSWB128,
19774 IX86_BUILTIN_PACKSSDW128,
19775 IX86_BUILTIN_PACKUSWB128,
19777 IX86_BUILTIN_PADDB128,
19778 IX86_BUILTIN_PADDW128,
19779 IX86_BUILTIN_PADDD128,
19780 IX86_BUILTIN_PADDQ128,
19781 IX86_BUILTIN_PADDSB128,
19782 IX86_BUILTIN_PADDSW128,
19783 IX86_BUILTIN_PADDUSB128,
19784 IX86_BUILTIN_PADDUSW128,
19785 IX86_BUILTIN_PSUBB128,
19786 IX86_BUILTIN_PSUBW128,
19787 IX86_BUILTIN_PSUBD128,
19788 IX86_BUILTIN_PSUBQ128,
19789 IX86_BUILTIN_PSUBSB128,
19790 IX86_BUILTIN_PSUBSW128,
19791 IX86_BUILTIN_PSUBUSB128,
19792 IX86_BUILTIN_PSUBUSW128,
19794 IX86_BUILTIN_PAND128,
19795 IX86_BUILTIN_PANDN128,
19796 IX86_BUILTIN_POR128,
19797 IX86_BUILTIN_PXOR128,
19799 IX86_BUILTIN_PAVGB128,
19800 IX86_BUILTIN_PAVGW128,
19802 IX86_BUILTIN_PCMPEQB128,
19803 IX86_BUILTIN_PCMPEQW128,
19804 IX86_BUILTIN_PCMPEQD128,
19805 IX86_BUILTIN_PCMPGTB128,
19806 IX86_BUILTIN_PCMPGTW128,
19807 IX86_BUILTIN_PCMPGTD128,
19809 IX86_BUILTIN_PMADDWD128,
19811 IX86_BUILTIN_PMAXSW128,
19812 IX86_BUILTIN_PMAXUB128,
19813 IX86_BUILTIN_PMINSW128,
19814 IX86_BUILTIN_PMINUB128,
19816 IX86_BUILTIN_PMULUDQ,
19817 IX86_BUILTIN_PMULUDQ128,
19818 IX86_BUILTIN_PMULHUW128,
19819 IX86_BUILTIN_PMULHW128,
19820 IX86_BUILTIN_PMULLW128,
19822 IX86_BUILTIN_PSADBW128,
19823 IX86_BUILTIN_PSHUFHW,
19824 IX86_BUILTIN_PSHUFLW,
19825 IX86_BUILTIN_PSHUFD,
19827 IX86_BUILTIN_PSLLDQI128,
19828 IX86_BUILTIN_PSLLWI128,
19829 IX86_BUILTIN_PSLLDI128,
19830 IX86_BUILTIN_PSLLQI128,
19831 IX86_BUILTIN_PSRAWI128,
19832 IX86_BUILTIN_PSRADI128,
19833 IX86_BUILTIN_PSRLDQI128,
19834 IX86_BUILTIN_PSRLWI128,
19835 IX86_BUILTIN_PSRLDI128,
19836 IX86_BUILTIN_PSRLQI128,
19838 IX86_BUILTIN_PSLLDQ128,
19839 IX86_BUILTIN_PSLLW128,
19840 IX86_BUILTIN_PSLLD128,
19841 IX86_BUILTIN_PSLLQ128,
19842 IX86_BUILTIN_PSRAW128,
19843 IX86_BUILTIN_PSRAD128,
19844 IX86_BUILTIN_PSRLW128,
19845 IX86_BUILTIN_PSRLD128,
19846 IX86_BUILTIN_PSRLQ128,
19848 IX86_BUILTIN_PUNPCKHBW128,
19849 IX86_BUILTIN_PUNPCKHWD128,
19850 IX86_BUILTIN_PUNPCKHDQ128,
19851 IX86_BUILTIN_PUNPCKHQDQ128,
19852 IX86_BUILTIN_PUNPCKLBW128,
19853 IX86_BUILTIN_PUNPCKLWD128,
19854 IX86_BUILTIN_PUNPCKLDQ128,
19855 IX86_BUILTIN_PUNPCKLQDQ128,
19857 IX86_BUILTIN_CLFLUSH,
19858 IX86_BUILTIN_MFENCE,
19859 IX86_BUILTIN_LFENCE,
19862 IX86_BUILTIN_ADDSUBPS,
19863 IX86_BUILTIN_HADDPS,
19864 IX86_BUILTIN_HSUBPS,
19865 IX86_BUILTIN_MOVSHDUP,
19866 IX86_BUILTIN_MOVSLDUP,
19867 IX86_BUILTIN_ADDSUBPD,
19868 IX86_BUILTIN_HADDPD,
19869 IX86_BUILTIN_HSUBPD,
19870 IX86_BUILTIN_LDDQU,
19872 IX86_BUILTIN_MONITOR,
19873 IX86_BUILTIN_MWAIT,
19876 IX86_BUILTIN_PHADDW,
19877 IX86_BUILTIN_PHADDD,
19878 IX86_BUILTIN_PHADDSW,
19879 IX86_BUILTIN_PHSUBW,
19880 IX86_BUILTIN_PHSUBD,
19881 IX86_BUILTIN_PHSUBSW,
19882 IX86_BUILTIN_PMADDUBSW,
19883 IX86_BUILTIN_PMULHRSW,
19884 IX86_BUILTIN_PSHUFB,
19885 IX86_BUILTIN_PSIGNB,
19886 IX86_BUILTIN_PSIGNW,
19887 IX86_BUILTIN_PSIGND,
19888 IX86_BUILTIN_PALIGNR,
19889 IX86_BUILTIN_PABSB,
19890 IX86_BUILTIN_PABSW,
19891 IX86_BUILTIN_PABSD,
19893 IX86_BUILTIN_PHADDW128,
19894 IX86_BUILTIN_PHADDD128,
19895 IX86_BUILTIN_PHADDSW128,
19896 IX86_BUILTIN_PHSUBW128,
19897 IX86_BUILTIN_PHSUBD128,
19898 IX86_BUILTIN_PHSUBSW128,
19899 IX86_BUILTIN_PMADDUBSW128,
19900 IX86_BUILTIN_PMULHRSW128,
19901 IX86_BUILTIN_PSHUFB128,
19902 IX86_BUILTIN_PSIGNB128,
19903 IX86_BUILTIN_PSIGNW128,
19904 IX86_BUILTIN_PSIGND128,
19905 IX86_BUILTIN_PALIGNR128,
19906 IX86_BUILTIN_PABSB128,
19907 IX86_BUILTIN_PABSW128,
19908 IX86_BUILTIN_PABSD128,
19910 /* AMDFAM10 - SSE4A New Instructions. */
19911 IX86_BUILTIN_MOVNTSD,
19912 IX86_BUILTIN_MOVNTSS,
19913 IX86_BUILTIN_EXTRQI,
19914 IX86_BUILTIN_EXTRQ,
19915 IX86_BUILTIN_INSERTQI,
19916 IX86_BUILTIN_INSERTQ,
19919 IX86_BUILTIN_BLENDPD,
19920 IX86_BUILTIN_BLENDPS,
19921 IX86_BUILTIN_BLENDVPD,
19922 IX86_BUILTIN_BLENDVPS,
19923 IX86_BUILTIN_PBLENDVB128,
19924 IX86_BUILTIN_PBLENDW128,
19929 IX86_BUILTIN_INSERTPS128,
19931 IX86_BUILTIN_MOVNTDQA,
19932 IX86_BUILTIN_MPSADBW128,
19933 IX86_BUILTIN_PACKUSDW128,
19934 IX86_BUILTIN_PCMPEQQ,
19935 IX86_BUILTIN_PHMINPOSUW128,
19937 IX86_BUILTIN_PMAXSB128,
19938 IX86_BUILTIN_PMAXSD128,
19939 IX86_BUILTIN_PMAXUD128,
19940 IX86_BUILTIN_PMAXUW128,
19942 IX86_BUILTIN_PMINSB128,
19943 IX86_BUILTIN_PMINSD128,
19944 IX86_BUILTIN_PMINUD128,
19945 IX86_BUILTIN_PMINUW128,
19947 IX86_BUILTIN_PMOVSXBW128,
19948 IX86_BUILTIN_PMOVSXBD128,
19949 IX86_BUILTIN_PMOVSXBQ128,
19950 IX86_BUILTIN_PMOVSXWD128,
19951 IX86_BUILTIN_PMOVSXWQ128,
19952 IX86_BUILTIN_PMOVSXDQ128,
19954 IX86_BUILTIN_PMOVZXBW128,
19955 IX86_BUILTIN_PMOVZXBD128,
19956 IX86_BUILTIN_PMOVZXBQ128,
19957 IX86_BUILTIN_PMOVZXWD128,
19958 IX86_BUILTIN_PMOVZXWQ128,
19959 IX86_BUILTIN_PMOVZXDQ128,
19961 IX86_BUILTIN_PMULDQ128,
19962 IX86_BUILTIN_PMULLD128,
19964 IX86_BUILTIN_ROUNDPD,
19965 IX86_BUILTIN_ROUNDPS,
19966 IX86_BUILTIN_ROUNDSD,
19967 IX86_BUILTIN_ROUNDSS,
19969 IX86_BUILTIN_PTESTZ,
19970 IX86_BUILTIN_PTESTC,
19971 IX86_BUILTIN_PTESTNZC,
19973 IX86_BUILTIN_VEC_INIT_V2SI,
19974 IX86_BUILTIN_VEC_INIT_V4HI,
19975 IX86_BUILTIN_VEC_INIT_V8QI,
19976 IX86_BUILTIN_VEC_EXT_V2DF,
19977 IX86_BUILTIN_VEC_EXT_V2DI,
19978 IX86_BUILTIN_VEC_EXT_V4SF,
19979 IX86_BUILTIN_VEC_EXT_V4SI,
19980 IX86_BUILTIN_VEC_EXT_V8HI,
19981 IX86_BUILTIN_VEC_EXT_V2SI,
19982 IX86_BUILTIN_VEC_EXT_V4HI,
19983 IX86_BUILTIN_VEC_EXT_V16QI,
19984 IX86_BUILTIN_VEC_SET_V2DI,
19985 IX86_BUILTIN_VEC_SET_V4SF,
19986 IX86_BUILTIN_VEC_SET_V4SI,
19987 IX86_BUILTIN_VEC_SET_V8HI,
19988 IX86_BUILTIN_VEC_SET_V4HI,
19989 IX86_BUILTIN_VEC_SET_V16QI,
19991 IX86_BUILTIN_VEC_PACK_SFIX,
19994 IX86_BUILTIN_CRC32QI,
19995 IX86_BUILTIN_CRC32HI,
19996 IX86_BUILTIN_CRC32SI,
19997 IX86_BUILTIN_CRC32DI,
19999 IX86_BUILTIN_PCMPESTRI128,
20000 IX86_BUILTIN_PCMPESTRM128,
20001 IX86_BUILTIN_PCMPESTRA128,
20002 IX86_BUILTIN_PCMPESTRC128,
20003 IX86_BUILTIN_PCMPESTRO128,
20004 IX86_BUILTIN_PCMPESTRS128,
20005 IX86_BUILTIN_PCMPESTRZ128,
20006 IX86_BUILTIN_PCMPISTRI128,
20007 IX86_BUILTIN_PCMPISTRM128,
20008 IX86_BUILTIN_PCMPISTRA128,
20009 IX86_BUILTIN_PCMPISTRC128,
20010 IX86_BUILTIN_PCMPISTRO128,
20011 IX86_BUILTIN_PCMPISTRS128,
20012 IX86_BUILTIN_PCMPISTRZ128,
20014 IX86_BUILTIN_PCMPGTQ,
20016 /* AES instructions */
20017 IX86_BUILTIN_AESENC128,
20018 IX86_BUILTIN_AESENCLAST128,
20019 IX86_BUILTIN_AESDEC128,
20020 IX86_BUILTIN_AESDECLAST128,
20021 IX86_BUILTIN_AESIMC128,
20022 IX86_BUILTIN_AESKEYGENASSIST128,
20024 /* PCLMUL instruction */
20025 IX86_BUILTIN_PCLMULQDQ128,
20028 IX86_BUILTIN_ADDPD256,
20029 IX86_BUILTIN_ADDPS256,
20030 IX86_BUILTIN_ADDSUBPD256,
20031 IX86_BUILTIN_ADDSUBPS256,
20032 IX86_BUILTIN_ANDPD256,
20033 IX86_BUILTIN_ANDPS256,
20034 IX86_BUILTIN_ANDNPD256,
20035 IX86_BUILTIN_ANDNPS256,
20036 IX86_BUILTIN_BLENDPD256,
20037 IX86_BUILTIN_BLENDPS256,
20038 IX86_BUILTIN_BLENDVPD256,
20039 IX86_BUILTIN_BLENDVPS256,
20040 IX86_BUILTIN_DIVPD256,
20041 IX86_BUILTIN_DIVPS256,
20042 IX86_BUILTIN_DPPS256,
20043 IX86_BUILTIN_HADDPD256,
20044 IX86_BUILTIN_HADDPS256,
20045 IX86_BUILTIN_HSUBPD256,
20046 IX86_BUILTIN_HSUBPS256,
20047 IX86_BUILTIN_MAXPD256,
20048 IX86_BUILTIN_MAXPS256,
20049 IX86_BUILTIN_MINPD256,
20050 IX86_BUILTIN_MINPS256,
20051 IX86_BUILTIN_MULPD256,
20052 IX86_BUILTIN_MULPS256,
20053 IX86_BUILTIN_ORPD256,
20054 IX86_BUILTIN_ORPS256,
20055 IX86_BUILTIN_SHUFPD256,
20056 IX86_BUILTIN_SHUFPS256,
20057 IX86_BUILTIN_SUBPD256,
20058 IX86_BUILTIN_SUBPS256,
20059 IX86_BUILTIN_XORPD256,
20060 IX86_BUILTIN_XORPS256,
20061 IX86_BUILTIN_CMPSD,
20062 IX86_BUILTIN_CMPSS,
20063 IX86_BUILTIN_CMPPD,
20064 IX86_BUILTIN_CMPPS,
20065 IX86_BUILTIN_CMPPD256,
20066 IX86_BUILTIN_CMPPS256,
20067 IX86_BUILTIN_CVTDQ2PD256,
20068 IX86_BUILTIN_CVTDQ2PS256,
20069 IX86_BUILTIN_CVTPD2PS256,
20070 IX86_BUILTIN_CVTPS2DQ256,
20071 IX86_BUILTIN_CVTPS2PD256,
20072 IX86_BUILTIN_CVTTPD2DQ256,
20073 IX86_BUILTIN_CVTPD2DQ256,
20074 IX86_BUILTIN_CVTTPS2DQ256,
20075 IX86_BUILTIN_EXTRACTF128PD256,
20076 IX86_BUILTIN_EXTRACTF128PS256,
20077 IX86_BUILTIN_EXTRACTF128SI256,
20078 IX86_BUILTIN_VZEROALL,
20079 IX86_BUILTIN_VZEROUPPER,
20080 IX86_BUILTIN_VZEROUPPER_REX64,
20081 IX86_BUILTIN_VPERMILVARPD,
20082 IX86_BUILTIN_VPERMILVARPS,
20083 IX86_BUILTIN_VPERMILVARPD256,
20084 IX86_BUILTIN_VPERMILVARPS256,
20085 IX86_BUILTIN_VPERMILPD,
20086 IX86_BUILTIN_VPERMILPS,
20087 IX86_BUILTIN_VPERMILPD256,
20088 IX86_BUILTIN_VPERMILPS256,
20089 IX86_BUILTIN_VPERM2F128PD256,
20090 IX86_BUILTIN_VPERM2F128PS256,
20091 IX86_BUILTIN_VPERM2F128SI256,
20092 IX86_BUILTIN_VBROADCASTSS,
20093 IX86_BUILTIN_VBROADCASTSD256,
20094 IX86_BUILTIN_VBROADCASTSS256,
20095 IX86_BUILTIN_VBROADCASTPD256,
20096 IX86_BUILTIN_VBROADCASTPS256,
20097 IX86_BUILTIN_VINSERTF128PD256,
20098 IX86_BUILTIN_VINSERTF128PS256,
20099 IX86_BUILTIN_VINSERTF128SI256,
20100 IX86_BUILTIN_LOADUPD256,
20101 IX86_BUILTIN_LOADUPS256,
20102 IX86_BUILTIN_STOREUPD256,
20103 IX86_BUILTIN_STOREUPS256,
20104 IX86_BUILTIN_LDDQU256,
20105 IX86_BUILTIN_MOVNTDQ256,
20106 IX86_BUILTIN_MOVNTPD256,
20107 IX86_BUILTIN_MOVNTPS256,
20108 IX86_BUILTIN_LOADDQU256,
20109 IX86_BUILTIN_STOREDQU256,
20110 IX86_BUILTIN_MASKLOADPD,
20111 IX86_BUILTIN_MASKLOADPS,
20112 IX86_BUILTIN_MASKSTOREPD,
20113 IX86_BUILTIN_MASKSTOREPS,
20114 IX86_BUILTIN_MASKLOADPD256,
20115 IX86_BUILTIN_MASKLOADPS256,
20116 IX86_BUILTIN_MASKSTOREPD256,
20117 IX86_BUILTIN_MASKSTOREPS256,
20118 IX86_BUILTIN_MOVSHDUP256,
20119 IX86_BUILTIN_MOVSLDUP256,
20120 IX86_BUILTIN_MOVDDUP256,
20122 IX86_BUILTIN_SQRTPD256,
20123 IX86_BUILTIN_SQRTPS256,
20124 IX86_BUILTIN_SQRTPS_NR256,
20125 IX86_BUILTIN_RSQRTPS256,
20126 IX86_BUILTIN_RSQRTPS_NR256,
20128 IX86_BUILTIN_RCPPS256,
20130 IX86_BUILTIN_ROUNDPD256,
20131 IX86_BUILTIN_ROUNDPS256,
20133 IX86_BUILTIN_UNPCKHPD256,
20134 IX86_BUILTIN_UNPCKLPD256,
20135 IX86_BUILTIN_UNPCKHPS256,
20136 IX86_BUILTIN_UNPCKLPS256,
20138 IX86_BUILTIN_SI256_SI,
20139 IX86_BUILTIN_PS256_PS,
20140 IX86_BUILTIN_PD256_PD,
20141 IX86_BUILTIN_SI_SI256,
20142 IX86_BUILTIN_PS_PS256,
20143 IX86_BUILTIN_PD_PD256,
20145 IX86_BUILTIN_VTESTZPD,
20146 IX86_BUILTIN_VTESTCPD,
20147 IX86_BUILTIN_VTESTNZCPD,
20148 IX86_BUILTIN_VTESTZPS,
20149 IX86_BUILTIN_VTESTCPS,
20150 IX86_BUILTIN_VTESTNZCPS,
20151 IX86_BUILTIN_VTESTZPD256,
20152 IX86_BUILTIN_VTESTCPD256,
20153 IX86_BUILTIN_VTESTNZCPD256,
20154 IX86_BUILTIN_VTESTZPS256,
20155 IX86_BUILTIN_VTESTCPS256,
20156 IX86_BUILTIN_VTESTNZCPS256,
20157 IX86_BUILTIN_PTESTZ256,
20158 IX86_BUILTIN_PTESTC256,
20159 IX86_BUILTIN_PTESTNZC256,
20161 IX86_BUILTIN_MOVMSKPD256,
20162 IX86_BUILTIN_MOVMSKPS256,
20164 /* TFmode support builtins. */
20166 IX86_BUILTIN_FABSQ,
20167 IX86_BUILTIN_COPYSIGNQ,
20169 /* SSE5 instructions */
20170 IX86_BUILTIN_FMADDSS,
20171 IX86_BUILTIN_FMADDSD,
20172 IX86_BUILTIN_FMADDPS,
20173 IX86_BUILTIN_FMADDPD,
20174 IX86_BUILTIN_FMSUBSS,
20175 IX86_BUILTIN_FMSUBSD,
20176 IX86_BUILTIN_FMSUBPS,
20177 IX86_BUILTIN_FMSUBPD,
20178 IX86_BUILTIN_FNMADDSS,
20179 IX86_BUILTIN_FNMADDSD,
20180 IX86_BUILTIN_FNMADDPS,
20181 IX86_BUILTIN_FNMADDPD,
20182 IX86_BUILTIN_FNMSUBSS,
20183 IX86_BUILTIN_FNMSUBSD,
20184 IX86_BUILTIN_FNMSUBPS,
20185 IX86_BUILTIN_FNMSUBPD,
20186 IX86_BUILTIN_PCMOV,
20187 IX86_BUILTIN_PCMOV_V2DI,
20188 IX86_BUILTIN_PCMOV_V4SI,
20189 IX86_BUILTIN_PCMOV_V8HI,
20190 IX86_BUILTIN_PCMOV_V16QI,
20191 IX86_BUILTIN_PCMOV_V4SF,
20192 IX86_BUILTIN_PCMOV_V2DF,
20193 IX86_BUILTIN_PPERM,
20194 IX86_BUILTIN_PERMPS,
20195 IX86_BUILTIN_PERMPD,
20196 IX86_BUILTIN_PMACSSWW,
20197 IX86_BUILTIN_PMACSWW,
20198 IX86_BUILTIN_PMACSSWD,
20199 IX86_BUILTIN_PMACSWD,
20200 IX86_BUILTIN_PMACSSDD,
20201 IX86_BUILTIN_PMACSDD,
20202 IX86_BUILTIN_PMACSSDQL,
20203 IX86_BUILTIN_PMACSSDQH,
20204 IX86_BUILTIN_PMACSDQL,
20205 IX86_BUILTIN_PMACSDQH,
20206 IX86_BUILTIN_PMADCSSWD,
20207 IX86_BUILTIN_PMADCSWD,
20208 IX86_BUILTIN_PHADDBW,
20209 IX86_BUILTIN_PHADDBD,
20210 IX86_BUILTIN_PHADDBQ,
20211 IX86_BUILTIN_PHADDWD,
20212 IX86_BUILTIN_PHADDWQ,
20213 IX86_BUILTIN_PHADDDQ,
20214 IX86_BUILTIN_PHADDUBW,
20215 IX86_BUILTIN_PHADDUBD,
20216 IX86_BUILTIN_PHADDUBQ,
20217 IX86_BUILTIN_PHADDUWD,
20218 IX86_BUILTIN_PHADDUWQ,
20219 IX86_BUILTIN_PHADDUDQ,
20220 IX86_BUILTIN_PHSUBBW,
20221 IX86_BUILTIN_PHSUBWD,
20222 IX86_BUILTIN_PHSUBDQ,
20223 IX86_BUILTIN_PROTB,
20224 IX86_BUILTIN_PROTW,
20225 IX86_BUILTIN_PROTD,
20226 IX86_BUILTIN_PROTQ,
20227 IX86_BUILTIN_PROTB_IMM,
20228 IX86_BUILTIN_PROTW_IMM,
20229 IX86_BUILTIN_PROTD_IMM,
20230 IX86_BUILTIN_PROTQ_IMM,
20231 IX86_BUILTIN_PSHLB,
20232 IX86_BUILTIN_PSHLW,
20233 IX86_BUILTIN_PSHLD,
20234 IX86_BUILTIN_PSHLQ,
20235 IX86_BUILTIN_PSHAB,
20236 IX86_BUILTIN_PSHAW,
20237 IX86_BUILTIN_PSHAD,
20238 IX86_BUILTIN_PSHAQ,
20239 IX86_BUILTIN_FRCZSS,
20240 IX86_BUILTIN_FRCZSD,
20241 IX86_BUILTIN_FRCZPS,
20242 IX86_BUILTIN_FRCZPD,
20243 IX86_BUILTIN_CVTPH2PS,
20244 IX86_BUILTIN_CVTPS2PH,
20246 IX86_BUILTIN_COMEQSS,
20247 IX86_BUILTIN_COMNESS,
20248 IX86_BUILTIN_COMLTSS,
20249 IX86_BUILTIN_COMLESS,
20250 IX86_BUILTIN_COMGTSS,
20251 IX86_BUILTIN_COMGESS,
20252 IX86_BUILTIN_COMUEQSS,
20253 IX86_BUILTIN_COMUNESS,
20254 IX86_BUILTIN_COMULTSS,
20255 IX86_BUILTIN_COMULESS,
20256 IX86_BUILTIN_COMUGTSS,
20257 IX86_BUILTIN_COMUGESS,
20258 IX86_BUILTIN_COMORDSS,
20259 IX86_BUILTIN_COMUNORDSS,
20260 IX86_BUILTIN_COMFALSESS,
20261 IX86_BUILTIN_COMTRUESS,
20263 IX86_BUILTIN_COMEQSD,
20264 IX86_BUILTIN_COMNESD,
20265 IX86_BUILTIN_COMLTSD,
20266 IX86_BUILTIN_COMLESD,
20267 IX86_BUILTIN_COMGTSD,
20268 IX86_BUILTIN_COMGESD,
20269 IX86_BUILTIN_COMUEQSD,
20270 IX86_BUILTIN_COMUNESD,
20271 IX86_BUILTIN_COMULTSD,
20272 IX86_BUILTIN_COMULESD,
20273 IX86_BUILTIN_COMUGTSD,
20274 IX86_BUILTIN_COMUGESD,
20275 IX86_BUILTIN_COMORDSD,
20276 IX86_BUILTIN_COMUNORDSD,
20277 IX86_BUILTIN_COMFALSESD,
20278 IX86_BUILTIN_COMTRUESD,
20280 IX86_BUILTIN_COMEQPS,
20281 IX86_BUILTIN_COMNEPS,
20282 IX86_BUILTIN_COMLTPS,
20283 IX86_BUILTIN_COMLEPS,
20284 IX86_BUILTIN_COMGTPS,
20285 IX86_BUILTIN_COMGEPS,
20286 IX86_BUILTIN_COMUEQPS,
20287 IX86_BUILTIN_COMUNEPS,
20288 IX86_BUILTIN_COMULTPS,
20289 IX86_BUILTIN_COMULEPS,
20290 IX86_BUILTIN_COMUGTPS,
20291 IX86_BUILTIN_COMUGEPS,
20292 IX86_BUILTIN_COMORDPS,
20293 IX86_BUILTIN_COMUNORDPS,
20294 IX86_BUILTIN_COMFALSEPS,
20295 IX86_BUILTIN_COMTRUEPS,
20297 IX86_BUILTIN_COMEQPD,
20298 IX86_BUILTIN_COMNEPD,
20299 IX86_BUILTIN_COMLTPD,
20300 IX86_BUILTIN_COMLEPD,
20301 IX86_BUILTIN_COMGTPD,
20302 IX86_BUILTIN_COMGEPD,
20303 IX86_BUILTIN_COMUEQPD,
20304 IX86_BUILTIN_COMUNEPD,
20305 IX86_BUILTIN_COMULTPD,
20306 IX86_BUILTIN_COMULEPD,
20307 IX86_BUILTIN_COMUGTPD,
20308 IX86_BUILTIN_COMUGEPD,
20309 IX86_BUILTIN_COMORDPD,
20310 IX86_BUILTIN_COMUNORDPD,
20311 IX86_BUILTIN_COMFALSEPD,
20312 IX86_BUILTIN_COMTRUEPD,
20314 IX86_BUILTIN_PCOMEQUB,
20315 IX86_BUILTIN_PCOMNEUB,
20316 IX86_BUILTIN_PCOMLTUB,
20317 IX86_BUILTIN_PCOMLEUB,
20318 IX86_BUILTIN_PCOMGTUB,
20319 IX86_BUILTIN_PCOMGEUB,
20320 IX86_BUILTIN_PCOMFALSEUB,
20321 IX86_BUILTIN_PCOMTRUEUB,
20322 IX86_BUILTIN_PCOMEQUW,
20323 IX86_BUILTIN_PCOMNEUW,
20324 IX86_BUILTIN_PCOMLTUW,
20325 IX86_BUILTIN_PCOMLEUW,
20326 IX86_BUILTIN_PCOMGTUW,
20327 IX86_BUILTIN_PCOMGEUW,
20328 IX86_BUILTIN_PCOMFALSEUW,
20329 IX86_BUILTIN_PCOMTRUEUW,
20330 IX86_BUILTIN_PCOMEQUD,
20331 IX86_BUILTIN_PCOMNEUD,
20332 IX86_BUILTIN_PCOMLTUD,
20333 IX86_BUILTIN_PCOMLEUD,
20334 IX86_BUILTIN_PCOMGTUD,
20335 IX86_BUILTIN_PCOMGEUD,
20336 IX86_BUILTIN_PCOMFALSEUD,
20337 IX86_BUILTIN_PCOMTRUEUD,
20338 IX86_BUILTIN_PCOMEQUQ,
20339 IX86_BUILTIN_PCOMNEUQ,
20340 IX86_BUILTIN_PCOMLTUQ,
20341 IX86_BUILTIN_PCOMLEUQ,
20342 IX86_BUILTIN_PCOMGTUQ,
20343 IX86_BUILTIN_PCOMGEUQ,
20344 IX86_BUILTIN_PCOMFALSEUQ,
20345 IX86_BUILTIN_PCOMTRUEUQ,
20347 IX86_BUILTIN_PCOMEQB,
20348 IX86_BUILTIN_PCOMNEB,
20349 IX86_BUILTIN_PCOMLTB,
20350 IX86_BUILTIN_PCOMLEB,
20351 IX86_BUILTIN_PCOMGTB,
20352 IX86_BUILTIN_PCOMGEB,
20353 IX86_BUILTIN_PCOMFALSEB,
20354 IX86_BUILTIN_PCOMTRUEB,
20355 IX86_BUILTIN_PCOMEQW,
20356 IX86_BUILTIN_PCOMNEW,
20357 IX86_BUILTIN_PCOMLTW,
20358 IX86_BUILTIN_PCOMLEW,
20359 IX86_BUILTIN_PCOMGTW,
20360 IX86_BUILTIN_PCOMGEW,
20361 IX86_BUILTIN_PCOMFALSEW,
20362 IX86_BUILTIN_PCOMTRUEW,
20363 IX86_BUILTIN_PCOMEQD,
20364 IX86_BUILTIN_PCOMNED,
20365 IX86_BUILTIN_PCOMLTD,
20366 IX86_BUILTIN_PCOMLED,
20367 IX86_BUILTIN_PCOMGTD,
20368 IX86_BUILTIN_PCOMGED,
20369 IX86_BUILTIN_PCOMFALSED,
20370 IX86_BUILTIN_PCOMTRUED,
20371 IX86_BUILTIN_PCOMEQQ,
20372 IX86_BUILTIN_PCOMNEQ,
20373 IX86_BUILTIN_PCOMLTQ,
20374 IX86_BUILTIN_PCOMLEQ,
20375 IX86_BUILTIN_PCOMGTQ,
20376 IX86_BUILTIN_PCOMGEQ,
20377 IX86_BUILTIN_PCOMFALSEQ,
20378 IX86_BUILTIN_PCOMTRUEQ,
20383 /* Table for the ix86 builtin decls. */
20384 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20386 /* Table of all of the builtin functions that are possible with different ISA's
20387 but are waiting to be built until a function is declared to use that
20389 struct builtin_isa GTY(())
20391 tree type; /* builtin type to use in the declaration */
20392 const char *name; /* function name */
20393 int isa; /* isa_flags this builtin is defined for */
20394 bool const_p; /* true if the declaration is constant */
20397 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20400 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20401 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20402 * function decl in the ix86_builtins array. Returns the function decl or
20403 * NULL_TREE, if the builtin was not added.
20405 * If the front end has a special hook for builtin functions, delay adding
20406 * builtin functions that aren't in the current ISA until the ISA is changed
20407 * with function specific optimization. Doing so, can save about 300K for the
20408 * default compiler. When the builtin is expanded, check at that time whether
20411 * If the front end doesn't have a special hook, record all builtins, even if
20412 * it isn't an instruction set in the current ISA in case the user uses
20413 * function specific options for a different ISA, so that we don't get scope
20414 * errors if a builtin is added in the middle of a function scope. */
20417 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20419 tree decl = NULL_TREE;
20421 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20423 ix86_builtins_isa[(int) code].isa = mask;
20425 if ((mask & ix86_isa_flags) != 0
20426 || (lang_hooks.builtin_function
20427 == lang_hooks.builtin_function_ext_scope))
20430 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20432 ix86_builtins[(int) code] = decl;
20433 ix86_builtins_isa[(int) code].type = NULL_TREE;
20437 ix86_builtins[(int) code] = NULL_TREE;
20438 ix86_builtins_isa[(int) code].const_p = false;
20439 ix86_builtins_isa[(int) code].type = type;
20440 ix86_builtins_isa[(int) code].name = name;
20447 /* Like def_builtin, but also marks the function decl "const". */
20450 def_builtin_const (int mask, const char *name, tree type,
20451 enum ix86_builtins code)
20453 tree decl = def_builtin (mask, name, type, code);
20455 TREE_READONLY (decl) = 1;
20457 ix86_builtins_isa[(int) code].const_p = true;
20462 /* Add any new builtin functions for a given ISA that may not have been
20463 declared. This saves a bit of space compared to adding all of the
20464 declarations to the tree, even if we didn't use them. */
20467 ix86_add_new_builtins (int isa)
20472 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20474 if ((ix86_builtins_isa[i].isa & isa) != 0
20475 && ix86_builtins_isa[i].type != NULL_TREE)
20477 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20478 ix86_builtins_isa[i].type,
20479 i, BUILT_IN_MD, NULL,
20482 ix86_builtins[i] = decl;
20483 ix86_builtins_isa[i].type = NULL_TREE;
20484 if (ix86_builtins_isa[i].const_p)
20485 TREE_READONLY (decl) = 1;
20490 /* Bits for builtin_description.flag. */
20492 /* Set when we don't support the comparison natively, and should
20493 swap_comparison in order to support it. */
20494 #define BUILTIN_DESC_SWAP_OPERANDS 1
20496 struct builtin_description
20498 const unsigned int mask;
20499 const enum insn_code icode;
20500 const char *const name;
20501 const enum ix86_builtins code;
20502 const enum rtx_code comparison;
20506 static const struct builtin_description bdesc_comi[] =
20508 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20509 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20510 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20511 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20512 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20513 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20514 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20515 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20516 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20517 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20518 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20519 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20525 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20526 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20534 static const struct builtin_description bdesc_pcmpestr[] =
20537 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20538 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20539 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20540 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20541 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20542 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20543 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20546 static const struct builtin_description bdesc_pcmpistr[] =
20549 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20550 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20551 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20552 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20553 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20554 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20555 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20558 /* Special builtin types */
20559 enum ix86_special_builtin_type
20561 SPECIAL_FTYPE_UNKNOWN,
20563 V32QI_FTYPE_PCCHAR,
20564 V16QI_FTYPE_PCCHAR,
20566 V8SF_FTYPE_PCFLOAT,
20568 V4DF_FTYPE_PCDOUBLE,
20569 V4SF_FTYPE_PCFLOAT,
20570 V2DF_FTYPE_PCDOUBLE,
20571 V8SF_FTYPE_PCV8SF_V8SF,
20572 V4DF_FTYPE_PCV4DF_V4DF,
20573 V4SF_FTYPE_V4SF_PCV2SF,
20574 V4SF_FTYPE_PCV4SF_V4SF,
20575 V2DF_FTYPE_V2DF_PCDOUBLE,
20576 V2DF_FTYPE_PCV2DF_V2DF,
20578 VOID_FTYPE_PV2SF_V4SF,
20579 VOID_FTYPE_PV4DI_V4DI,
20580 VOID_FTYPE_PV2DI_V2DI,
20581 VOID_FTYPE_PCHAR_V32QI,
20582 VOID_FTYPE_PCHAR_V16QI,
20583 VOID_FTYPE_PFLOAT_V8SF,
20584 VOID_FTYPE_PFLOAT_V4SF,
20585 VOID_FTYPE_PDOUBLE_V4DF,
20586 VOID_FTYPE_PDOUBLE_V2DF,
20588 VOID_FTYPE_PINT_INT,
20589 VOID_FTYPE_PV8SF_V8SF_V8SF,
20590 VOID_FTYPE_PV4DF_V4DF_V4DF,
20591 VOID_FTYPE_PV4SF_V4SF_V4SF,
20592 VOID_FTYPE_PV2DF_V2DF_V2DF
20595 /* Builtin types */
20596 enum ix86_builtin_type
20599 FLOAT128_FTYPE_FLOAT128,
20601 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20602 INT_FTYPE_V8SF_V8SF_PTEST,
20603 INT_FTYPE_V4DI_V4DI_PTEST,
20604 INT_FTYPE_V4DF_V4DF_PTEST,
20605 INT_FTYPE_V4SF_V4SF_PTEST,
20606 INT_FTYPE_V2DI_V2DI_PTEST,
20607 INT_FTYPE_V2DF_V2DF_PTEST,
20639 V4SF_FTYPE_V4SF_VEC_MERGE,
20648 V2DF_FTYPE_V2DF_VEC_MERGE,
20659 V16QI_FTYPE_V16QI_V16QI,
20660 V16QI_FTYPE_V8HI_V8HI,
20661 V8QI_FTYPE_V8QI_V8QI,
20662 V8QI_FTYPE_V4HI_V4HI,
20663 V8HI_FTYPE_V8HI_V8HI,
20664 V8HI_FTYPE_V8HI_V8HI_COUNT,
20665 V8HI_FTYPE_V16QI_V16QI,
20666 V8HI_FTYPE_V4SI_V4SI,
20667 V8HI_FTYPE_V8HI_SI_COUNT,
20668 V8SF_FTYPE_V8SF_V8SF,
20669 V8SF_FTYPE_V8SF_V8SI,
20670 V4SI_FTYPE_V4SI_V4SI,
20671 V4SI_FTYPE_V4SI_V4SI_COUNT,
20672 V4SI_FTYPE_V8HI_V8HI,
20673 V4SI_FTYPE_V4SF_V4SF,
20674 V4SI_FTYPE_V2DF_V2DF,
20675 V4SI_FTYPE_V4SI_SI_COUNT,
20676 V4HI_FTYPE_V4HI_V4HI,
20677 V4HI_FTYPE_V4HI_V4HI_COUNT,
20678 V4HI_FTYPE_V8QI_V8QI,
20679 V4HI_FTYPE_V2SI_V2SI,
20680 V4HI_FTYPE_V4HI_SI_COUNT,
20681 V4DF_FTYPE_V4DF_V4DF,
20682 V4DF_FTYPE_V4DF_V4DI,
20683 V4SF_FTYPE_V4SF_V4SF,
20684 V4SF_FTYPE_V4SF_V4SF_SWAP,
20685 V4SF_FTYPE_V4SF_V4SI,
20686 V4SF_FTYPE_V4SF_V2SI,
20687 V4SF_FTYPE_V4SF_V2DF,
20688 V4SF_FTYPE_V4SF_DI,
20689 V4SF_FTYPE_V4SF_SI,
20690 V2DI_FTYPE_V2DI_V2DI,
20691 V2DI_FTYPE_V2DI_V2DI_COUNT,
20692 V2DI_FTYPE_V16QI_V16QI,
20693 V2DI_FTYPE_V4SI_V4SI,
20694 V2DI_FTYPE_V2DI_V16QI,
20695 V2DI_FTYPE_V2DF_V2DF,
20696 V2DI_FTYPE_V2DI_SI_COUNT,
20697 V2SI_FTYPE_V2SI_V2SI,
20698 V2SI_FTYPE_V2SI_V2SI_COUNT,
20699 V2SI_FTYPE_V4HI_V4HI,
20700 V2SI_FTYPE_V2SF_V2SF,
20701 V2SI_FTYPE_V2SI_SI_COUNT,
20702 V2DF_FTYPE_V2DF_V2DF,
20703 V2DF_FTYPE_V2DF_V2DF_SWAP,
20704 V2DF_FTYPE_V2DF_V4SF,
20705 V2DF_FTYPE_V2DF_V2DI,
20706 V2DF_FTYPE_V2DF_DI,
20707 V2DF_FTYPE_V2DF_SI,
20708 V2SF_FTYPE_V2SF_V2SF,
20709 V1DI_FTYPE_V1DI_V1DI,
20710 V1DI_FTYPE_V1DI_V1DI_COUNT,
20711 V1DI_FTYPE_V8QI_V8QI,
20712 V1DI_FTYPE_V2SI_V2SI,
20713 V1DI_FTYPE_V1DI_SI_COUNT,
20714 UINT64_FTYPE_UINT64_UINT64,
20715 UINT_FTYPE_UINT_UINT,
20716 UINT_FTYPE_UINT_USHORT,
20717 UINT_FTYPE_UINT_UCHAR,
20718 V8HI_FTYPE_V8HI_INT,
20719 V4SI_FTYPE_V4SI_INT,
20720 V4HI_FTYPE_V4HI_INT,
20721 V8SF_FTYPE_V8SF_INT,
20722 V4SI_FTYPE_V8SI_INT,
20723 V4SF_FTYPE_V8SF_INT,
20724 V2DF_FTYPE_V4DF_INT,
20725 V4DF_FTYPE_V4DF_INT,
20726 V4SF_FTYPE_V4SF_INT,
20727 V2DI_FTYPE_V2DI_INT,
20728 V2DI2TI_FTYPE_V2DI_INT,
20729 V2DF_FTYPE_V2DF_INT,
20730 V16QI_FTYPE_V16QI_V16QI_V16QI,
20731 V8SF_FTYPE_V8SF_V8SF_V8SF,
20732 V4DF_FTYPE_V4DF_V4DF_V4DF,
20733 V4SF_FTYPE_V4SF_V4SF_V4SF,
20734 V2DF_FTYPE_V2DF_V2DF_V2DF,
20735 V16QI_FTYPE_V16QI_V16QI_INT,
20736 V8SI_FTYPE_V8SI_V8SI_INT,
20737 V8SI_FTYPE_V8SI_V4SI_INT,
20738 V8HI_FTYPE_V8HI_V8HI_INT,
20739 V8SF_FTYPE_V8SF_V8SF_INT,
20740 V8SF_FTYPE_V8SF_V4SF_INT,
20741 V4SI_FTYPE_V4SI_V4SI_INT,
20742 V4DF_FTYPE_V4DF_V4DF_INT,
20743 V4DF_FTYPE_V4DF_V2DF_INT,
20744 V4SF_FTYPE_V4SF_V4SF_INT,
20745 V2DI_FTYPE_V2DI_V2DI_INT,
20746 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20747 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20748 V2DF_FTYPE_V2DF_V2DF_INT,
20749 V2DI_FTYPE_V2DI_UINT_UINT,
20750 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20753 /* Special builtins with variable number of arguments. */
20754 static const struct builtin_description bdesc_special_args[] =
20757 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20760 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20772 /* SSE or 3DNow!A */
20773 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20774 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20777 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20781 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20782 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20783 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20787 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20788 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20791 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20794 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20797 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20798 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20803 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
20820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20833 /* Builtins with variable number of arguments. */
20834 static const struct builtin_description bdesc_args[] =
20837 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20838 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20839 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20840 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20841 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20842 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20844 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20845 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20846 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20847 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20848 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20849 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20850 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20851 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20853 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20854 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20856 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20857 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20858 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20859 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20861 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20862 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20863 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20864 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20865 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20866 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20868 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20869 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20870 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20871 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20872 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20873 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20875 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20876 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20877 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20879 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20881 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20882 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20883 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20884 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20885 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20886 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20888 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20889 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20890 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20891 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20892 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20893 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20895 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20896 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20897 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20898 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20901 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20902 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20903 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20904 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20906 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20907 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20908 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20909 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20910 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20911 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20912 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20913 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20914 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20915 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20916 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20917 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20918 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20919 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20920 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20923 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20924 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20925 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20926 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20927 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20928 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20933 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20935 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20939 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20941 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20942 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20944 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20946 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20947 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20948 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20949 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20950 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20955 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20957 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20958 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20959 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20961 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20962 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20963 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20964 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20965 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
20966 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20967 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20968 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20969 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20970 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20971 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20972 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20973 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20974 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20975 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20976 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20978 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20979 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20980 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20983 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20984 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20985 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20986 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20988 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20989 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20990 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20992 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20994 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
20995 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
20996 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
20998 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21004 /* SSE MMX or 3Dnow!A */
21005 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21006 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21007 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21009 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21010 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21011 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21012 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21014 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21015 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21017 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21020 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21022 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21023 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21024 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21025 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21028 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21029 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21032 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21038 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21039 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21043 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21045 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21046 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21047 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21048 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21050 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21051 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21052 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21055 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21056 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21057 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21058 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21059 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21060 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21062 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21067 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21068 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21070 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21072 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21076 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21080 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21082 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21083 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21089 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21091 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21092 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21093 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21094 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21095 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21096 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21097 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21098 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21109 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21110 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21112 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21113 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21114 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21115 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21127 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21128 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21129 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21133 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21136 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21139 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21145 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21154 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21159 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21160 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21161 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21162 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21163 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21164 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21167 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21168 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21169 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21170 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21171 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21172 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21174 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21175 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21176 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21177 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21185 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21186 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21188 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21191 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21192 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21195 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21196 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21198 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21199 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21200 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21201 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21202 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21203 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21206 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21207 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21208 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21209 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21210 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21211 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21213 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21214 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21215 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21216 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21217 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21218 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21219 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21220 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21221 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21222 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21223 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21224 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21225 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21226 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21227 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21228 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21229 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21230 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21231 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21232 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21233 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21234 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21235 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21236 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21239 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21240 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21243 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21244 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21245 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21246 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21247 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21248 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21249 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21250 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21251 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21252 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21254 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21255 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21256 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21257 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21258 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21259 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21260 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21261 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21262 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21263 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21264 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21265 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21266 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21268 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21269 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21270 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21271 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21272 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21273 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21274 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21275 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21276 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21277 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21278 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21279 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21281 /* SSE4.1 and SSE5 */
21282 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21283 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21284 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21285 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21287 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21288 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21289 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21292 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21293 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21294 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21295 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21296 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21299 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21300 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21301 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21302 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21305 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21306 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21308 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21309 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21310 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21311 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21314 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21317 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21318 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21319 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21320 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21321 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21322 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21323 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21324 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21325 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21326 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21327 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21328 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21329 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21330 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21331 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21332 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21333 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21334 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21335 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21336 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21337 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21338 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21339 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21340 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21341 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21342 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21344 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21345 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21346 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21347 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21349 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21350 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21351 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21352 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21353 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21354 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21355 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21356 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21357 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21358 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21359 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21360 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21361 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21362 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21363 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21364 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21365 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21368 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21369 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21372 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21373 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21374 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21375 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21376 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21377 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21378 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21379 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21380 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21381 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21382 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21384 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21385 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21386 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21388 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21389 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21390 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21392 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21397 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21399 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21400 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21401 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21404 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21405 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21406 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21407 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21409 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21411 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21412 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21413 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21432 enum multi_arg_type {
21442 MULTI_ARG_3_PERMPS,
21443 MULTI_ARG_3_PERMPD,
21450 MULTI_ARG_2_DI_IMM,
21451 MULTI_ARG_2_SI_IMM,
21452 MULTI_ARG_2_HI_IMM,
21453 MULTI_ARG_2_QI_IMM,
21454 MULTI_ARG_2_SF_CMP,
21455 MULTI_ARG_2_DF_CMP,
21456 MULTI_ARG_2_DI_CMP,
21457 MULTI_ARG_2_SI_CMP,
21458 MULTI_ARG_2_HI_CMP,
21459 MULTI_ARG_2_QI_CMP,
21482 static const struct builtin_description bdesc_multi_arg[] =
21484 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21485 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21486 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21487 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21488 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21489 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21490 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21491 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21492 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21493 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21494 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21495 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21496 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21497 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21498 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21499 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21500 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21501 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21502 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21503 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21504 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21505 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21506 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21507 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21508 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21512 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21515 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21516 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21517 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21520 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21523 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21524 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21563 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21564 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21565 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21566 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21567 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21568 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21569 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21570 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21571 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21572 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21573 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21574 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21575 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21577 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21578 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21579 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21580 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21581 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21582 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21583 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21584 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21585 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21586 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21587 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21588 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21589 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21590 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21591 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21592 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21594 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21595 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21596 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21597 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21598 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21599 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21600 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21601 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21602 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21603 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21604 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21605 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21606 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21607 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21608 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21609 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21611 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21612 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21613 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21614 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21615 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21616 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21617 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21618 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21619 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21620 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21621 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21622 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21623 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21624 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21625 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21626 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21628 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21629 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21630 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21631 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21632 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21633 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21634 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21636 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21637 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21638 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21639 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21640 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21641 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21642 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21644 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21645 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21646 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21647 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21648 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21649 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21650 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21652 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21653 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21654 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21655 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21656 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21657 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21658 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21660 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21661 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21662 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21663 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21664 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21665 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21666 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21668 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21669 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21670 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21671 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21672 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21673 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21674 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21676 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21677 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21678 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21679 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21680 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21681 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21682 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21684 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21685 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21686 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21687 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21688 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21689 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21690 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21692 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21693 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21698 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21699 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21701 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21706 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21707 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21708 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21714 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21715 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21716 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21720 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21721 in the current target ISA to allow the user to compile particular modules
21722 with different target specific options that differ from the command line
21725 ix86_init_mmx_sse_builtins (void)
21727 const struct builtin_description * d;
21730 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21731 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21732 tree V1DI_type_node
21733 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21734 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21735 tree V2DI_type_node
21736 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21737 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21738 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21739 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21740 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21741 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21742 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21744 tree pchar_type_node = build_pointer_type (char_type_node);
21745 tree pcchar_type_node
21746 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21747 tree pfloat_type_node = build_pointer_type (float_type_node);
21748 tree pcfloat_type_node
21749 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21750 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21751 tree pcv2sf_type_node
21752 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21753 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21754 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21757 tree int_ftype_v4sf_v4sf
21758 = build_function_type_list (integer_type_node,
21759 V4SF_type_node, V4SF_type_node, NULL_TREE);
21760 tree v4si_ftype_v4sf_v4sf
21761 = build_function_type_list (V4SI_type_node,
21762 V4SF_type_node, V4SF_type_node, NULL_TREE);
21763 /* MMX/SSE/integer conversions. */
21764 tree int_ftype_v4sf
21765 = build_function_type_list (integer_type_node,
21766 V4SF_type_node, NULL_TREE);
21767 tree int64_ftype_v4sf
21768 = build_function_type_list (long_long_integer_type_node,
21769 V4SF_type_node, NULL_TREE);
21770 tree int_ftype_v8qi
21771 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21772 tree v4sf_ftype_v4sf_int
21773 = build_function_type_list (V4SF_type_node,
21774 V4SF_type_node, integer_type_node, NULL_TREE);
21775 tree v4sf_ftype_v4sf_int64
21776 = build_function_type_list (V4SF_type_node,
21777 V4SF_type_node, long_long_integer_type_node,
21779 tree v4sf_ftype_v4sf_v2si
21780 = build_function_type_list (V4SF_type_node,
21781 V4SF_type_node, V2SI_type_node, NULL_TREE);
21783 /* Miscellaneous. */
21784 tree v8qi_ftype_v4hi_v4hi
21785 = build_function_type_list (V8QI_type_node,
21786 V4HI_type_node, V4HI_type_node, NULL_TREE);
21787 tree v4hi_ftype_v2si_v2si
21788 = build_function_type_list (V4HI_type_node,
21789 V2SI_type_node, V2SI_type_node, NULL_TREE);
21790 tree v4sf_ftype_v4sf_v4sf_int
21791 = build_function_type_list (V4SF_type_node,
21792 V4SF_type_node, V4SF_type_node,
21793 integer_type_node, NULL_TREE);
21794 tree v2si_ftype_v4hi_v4hi
21795 = build_function_type_list (V2SI_type_node,
21796 V4HI_type_node, V4HI_type_node, NULL_TREE);
21797 tree v4hi_ftype_v4hi_int
21798 = build_function_type_list (V4HI_type_node,
21799 V4HI_type_node, integer_type_node, NULL_TREE);
21800 tree v2si_ftype_v2si_int
21801 = build_function_type_list (V2SI_type_node,
21802 V2SI_type_node, integer_type_node, NULL_TREE);
21803 tree v1di_ftype_v1di_int
21804 = build_function_type_list (V1DI_type_node,
21805 V1DI_type_node, integer_type_node, NULL_TREE);
21807 tree void_ftype_void
21808 = build_function_type (void_type_node, void_list_node);
21809 tree void_ftype_unsigned
21810 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21811 tree void_ftype_unsigned_unsigned
21812 = build_function_type_list (void_type_node, unsigned_type_node,
21813 unsigned_type_node, NULL_TREE);
21814 tree void_ftype_pcvoid_unsigned_unsigned
21815 = build_function_type_list (void_type_node, const_ptr_type_node,
21816 unsigned_type_node, unsigned_type_node,
21818 tree unsigned_ftype_void
21819 = build_function_type (unsigned_type_node, void_list_node);
21820 tree v2si_ftype_v4sf
21821 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21822 /* Loads/stores. */
21823 tree void_ftype_v8qi_v8qi_pchar
21824 = build_function_type_list (void_type_node,
21825 V8QI_type_node, V8QI_type_node,
21826 pchar_type_node, NULL_TREE);
21827 tree v4sf_ftype_pcfloat
21828 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21829 tree v4sf_ftype_v4sf_pcv2sf
21830 = build_function_type_list (V4SF_type_node,
21831 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21832 tree void_ftype_pv2sf_v4sf
21833 = build_function_type_list (void_type_node,
21834 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21835 tree void_ftype_pfloat_v4sf
21836 = build_function_type_list (void_type_node,
21837 pfloat_type_node, V4SF_type_node, NULL_TREE);
21838 tree void_ftype_pdi_di
21839 = build_function_type_list (void_type_node,
21840 pdi_type_node, long_long_unsigned_type_node,
21842 tree void_ftype_pv2di_v2di
21843 = build_function_type_list (void_type_node,
21844 pv2di_type_node, V2DI_type_node, NULL_TREE);
21845 /* Normal vector unops. */
21846 tree v4sf_ftype_v4sf
21847 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21848 tree v16qi_ftype_v16qi
21849 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21850 tree v8hi_ftype_v8hi
21851 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21852 tree v4si_ftype_v4si
21853 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21854 tree v8qi_ftype_v8qi
21855 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21856 tree v4hi_ftype_v4hi
21857 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21859 /* Normal vector binops. */
21860 tree v4sf_ftype_v4sf_v4sf
21861 = build_function_type_list (V4SF_type_node,
21862 V4SF_type_node, V4SF_type_node, NULL_TREE);
21863 tree v8qi_ftype_v8qi_v8qi
21864 = build_function_type_list (V8QI_type_node,
21865 V8QI_type_node, V8QI_type_node, NULL_TREE);
21866 tree v4hi_ftype_v4hi_v4hi
21867 = build_function_type_list (V4HI_type_node,
21868 V4HI_type_node, V4HI_type_node, NULL_TREE);
21869 tree v2si_ftype_v2si_v2si
21870 = build_function_type_list (V2SI_type_node,
21871 V2SI_type_node, V2SI_type_node, NULL_TREE);
21872 tree v1di_ftype_v1di_v1di
21873 = build_function_type_list (V1DI_type_node,
21874 V1DI_type_node, V1DI_type_node, NULL_TREE);
21875 tree v1di_ftype_v1di_v1di_int
21876 = build_function_type_list (V1DI_type_node,
21877 V1DI_type_node, V1DI_type_node,
21878 integer_type_node, NULL_TREE);
21879 tree v2si_ftype_v2sf
21880 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21881 tree v2sf_ftype_v2si
21882 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21883 tree v2si_ftype_v2si
21884 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21885 tree v2sf_ftype_v2sf
21886 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21887 tree v2sf_ftype_v2sf_v2sf
21888 = build_function_type_list (V2SF_type_node,
21889 V2SF_type_node, V2SF_type_node, NULL_TREE);
21890 tree v2si_ftype_v2sf_v2sf
21891 = build_function_type_list (V2SI_type_node,
21892 V2SF_type_node, V2SF_type_node, NULL_TREE);
21893 tree pint_type_node = build_pointer_type (integer_type_node);
21894 tree pdouble_type_node = build_pointer_type (double_type_node);
21895 tree pcdouble_type_node = build_pointer_type (
21896 build_type_variant (double_type_node, 1, 0));
21897 tree int_ftype_v2df_v2df
21898 = build_function_type_list (integer_type_node,
21899 V2DF_type_node, V2DF_type_node, NULL_TREE);
21901 tree void_ftype_pcvoid
21902 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21903 tree v4sf_ftype_v4si
21904 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21905 tree v4si_ftype_v4sf
21906 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21907 tree v2df_ftype_v4si
21908 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21909 tree v4si_ftype_v2df
21910 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21911 tree v4si_ftype_v2df_v2df
21912 = build_function_type_list (V4SI_type_node,
21913 V2DF_type_node, V2DF_type_node, NULL_TREE);
21914 tree v2si_ftype_v2df
21915 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21916 tree v4sf_ftype_v2df
21917 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21918 tree v2df_ftype_v2si
21919 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21920 tree v2df_ftype_v4sf
21921 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21922 tree int_ftype_v2df
21923 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21924 tree int64_ftype_v2df
21925 = build_function_type_list (long_long_integer_type_node,
21926 V2DF_type_node, NULL_TREE);
21927 tree v2df_ftype_v2df_int
21928 = build_function_type_list (V2DF_type_node,
21929 V2DF_type_node, integer_type_node, NULL_TREE);
21930 tree v2df_ftype_v2df_int64
21931 = build_function_type_list (V2DF_type_node,
21932 V2DF_type_node, long_long_integer_type_node,
21934 tree v4sf_ftype_v4sf_v2df
21935 = build_function_type_list (V4SF_type_node,
21936 V4SF_type_node, V2DF_type_node, NULL_TREE);
21937 tree v2df_ftype_v2df_v4sf
21938 = build_function_type_list (V2DF_type_node,
21939 V2DF_type_node, V4SF_type_node, NULL_TREE);
21940 tree v2df_ftype_v2df_v2df_int
21941 = build_function_type_list (V2DF_type_node,
21942 V2DF_type_node, V2DF_type_node,
21945 tree v2df_ftype_v2df_pcdouble
21946 = build_function_type_list (V2DF_type_node,
21947 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21948 tree void_ftype_pdouble_v2df
21949 = build_function_type_list (void_type_node,
21950 pdouble_type_node, V2DF_type_node, NULL_TREE);
21951 tree void_ftype_pint_int
21952 = build_function_type_list (void_type_node,
21953 pint_type_node, integer_type_node, NULL_TREE);
21954 tree void_ftype_v16qi_v16qi_pchar
21955 = build_function_type_list (void_type_node,
21956 V16QI_type_node, V16QI_type_node,
21957 pchar_type_node, NULL_TREE);
21958 tree v2df_ftype_pcdouble
21959 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
21960 tree v2df_ftype_v2df_v2df
21961 = build_function_type_list (V2DF_type_node,
21962 V2DF_type_node, V2DF_type_node, NULL_TREE);
21963 tree v16qi_ftype_v16qi_v16qi
21964 = build_function_type_list (V16QI_type_node,
21965 V16QI_type_node, V16QI_type_node, NULL_TREE);
21966 tree v8hi_ftype_v8hi_v8hi
21967 = build_function_type_list (V8HI_type_node,
21968 V8HI_type_node, V8HI_type_node, NULL_TREE);
21969 tree v4si_ftype_v4si_v4si
21970 = build_function_type_list (V4SI_type_node,
21971 V4SI_type_node, V4SI_type_node, NULL_TREE);
21972 tree v2di_ftype_v2di_v2di
21973 = build_function_type_list (V2DI_type_node,
21974 V2DI_type_node, V2DI_type_node, NULL_TREE);
21975 tree v2di_ftype_v2df_v2df
21976 = build_function_type_list (V2DI_type_node,
21977 V2DF_type_node, V2DF_type_node, NULL_TREE);
21978 tree v2df_ftype_v2df
21979 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
21980 tree v2di_ftype_v2di_int
21981 = build_function_type_list (V2DI_type_node,
21982 V2DI_type_node, integer_type_node, NULL_TREE);
21983 tree v2di_ftype_v2di_v2di_int
21984 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21985 V2DI_type_node, integer_type_node, NULL_TREE);
21986 tree v4si_ftype_v4si_int
21987 = build_function_type_list (V4SI_type_node,
21988 V4SI_type_node, integer_type_node, NULL_TREE);
21989 tree v8hi_ftype_v8hi_int
21990 = build_function_type_list (V8HI_type_node,
21991 V8HI_type_node, integer_type_node, NULL_TREE);
21992 tree v4si_ftype_v8hi_v8hi
21993 = build_function_type_list (V4SI_type_node,
21994 V8HI_type_node, V8HI_type_node, NULL_TREE);
21995 tree v1di_ftype_v8qi_v8qi
21996 = build_function_type_list (V1DI_type_node,
21997 V8QI_type_node, V8QI_type_node, NULL_TREE);
21998 tree v1di_ftype_v2si_v2si
21999 = build_function_type_list (V1DI_type_node,
22000 V2SI_type_node, V2SI_type_node, NULL_TREE);
22001 tree v2di_ftype_v16qi_v16qi
22002 = build_function_type_list (V2DI_type_node,
22003 V16QI_type_node, V16QI_type_node, NULL_TREE);
22004 tree v2di_ftype_v4si_v4si
22005 = build_function_type_list (V2DI_type_node,
22006 V4SI_type_node, V4SI_type_node, NULL_TREE);
22007 tree int_ftype_v16qi
22008 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22009 tree v16qi_ftype_pcchar
22010 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22011 tree void_ftype_pchar_v16qi
22012 = build_function_type_list (void_type_node,
22013 pchar_type_node, V16QI_type_node, NULL_TREE);
22015 tree v2di_ftype_v2di_unsigned_unsigned
22016 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22017 unsigned_type_node, unsigned_type_node,
22019 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22020 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22021 unsigned_type_node, unsigned_type_node,
22023 tree v2di_ftype_v2di_v16qi
22024 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22026 tree v2df_ftype_v2df_v2df_v2df
22027 = build_function_type_list (V2DF_type_node,
22028 V2DF_type_node, V2DF_type_node,
22029 V2DF_type_node, NULL_TREE);
22030 tree v4sf_ftype_v4sf_v4sf_v4sf
22031 = build_function_type_list (V4SF_type_node,
22032 V4SF_type_node, V4SF_type_node,
22033 V4SF_type_node, NULL_TREE);
22034 tree v8hi_ftype_v16qi
22035 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22037 tree v4si_ftype_v16qi
22038 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22040 tree v2di_ftype_v16qi
22041 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22043 tree v4si_ftype_v8hi
22044 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22046 tree v2di_ftype_v8hi
22047 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22049 tree v2di_ftype_v4si
22050 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22052 tree v2di_ftype_pv2di
22053 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22055 tree v16qi_ftype_v16qi_v16qi_int
22056 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22057 V16QI_type_node, integer_type_node,
22059 tree v16qi_ftype_v16qi_v16qi_v16qi
22060 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22061 V16QI_type_node, V16QI_type_node,
22063 tree v8hi_ftype_v8hi_v8hi_int
22064 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22065 V8HI_type_node, integer_type_node,
22067 tree v4si_ftype_v4si_v4si_int
22068 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22069 V4SI_type_node, integer_type_node,
22071 tree int_ftype_v2di_v2di
22072 = build_function_type_list (integer_type_node,
22073 V2DI_type_node, V2DI_type_node,
22075 tree int_ftype_v16qi_int_v16qi_int_int
22076 = build_function_type_list (integer_type_node,
22083 tree v16qi_ftype_v16qi_int_v16qi_int_int
22084 = build_function_type_list (V16QI_type_node,
22091 tree int_ftype_v16qi_v16qi_int
22092 = build_function_type_list (integer_type_node,
22098 /* SSE5 instructions */
22099 tree v2di_ftype_v2di_v2di_v2di
22100 = build_function_type_list (V2DI_type_node,
22106 tree v4si_ftype_v4si_v4si_v4si
22107 = build_function_type_list (V4SI_type_node,
22113 tree v4si_ftype_v4si_v4si_v2di
22114 = build_function_type_list (V4SI_type_node,
22120 tree v8hi_ftype_v8hi_v8hi_v8hi
22121 = build_function_type_list (V8HI_type_node,
22127 tree v8hi_ftype_v8hi_v8hi_v4si
22128 = build_function_type_list (V8HI_type_node,
22134 tree v2df_ftype_v2df_v2df_v16qi
22135 = build_function_type_list (V2DF_type_node,
22141 tree v4sf_ftype_v4sf_v4sf_v16qi
22142 = build_function_type_list (V4SF_type_node,
22148 tree v2di_ftype_v2di_si
22149 = build_function_type_list (V2DI_type_node,
22154 tree v4si_ftype_v4si_si
22155 = build_function_type_list (V4SI_type_node,
22160 tree v8hi_ftype_v8hi_si
22161 = build_function_type_list (V8HI_type_node,
22166 tree v16qi_ftype_v16qi_si
22167 = build_function_type_list (V16QI_type_node,
22171 tree v4sf_ftype_v4hi
22172 = build_function_type_list (V4SF_type_node,
22176 tree v4hi_ftype_v4sf
22177 = build_function_type_list (V4HI_type_node,
22181 tree v2di_ftype_v2di
22182 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22184 tree v16qi_ftype_v8hi_v8hi
22185 = build_function_type_list (V16QI_type_node,
22186 V8HI_type_node, V8HI_type_node,
22188 tree v8hi_ftype_v4si_v4si
22189 = build_function_type_list (V8HI_type_node,
22190 V4SI_type_node, V4SI_type_node,
22192 tree v8hi_ftype_v16qi_v16qi
22193 = build_function_type_list (V8HI_type_node,
22194 V16QI_type_node, V16QI_type_node,
22196 tree v4hi_ftype_v8qi_v8qi
22197 = build_function_type_list (V4HI_type_node,
22198 V8QI_type_node, V8QI_type_node,
22200 tree unsigned_ftype_unsigned_uchar
22201 = build_function_type_list (unsigned_type_node,
22202 unsigned_type_node,
22203 unsigned_char_type_node,
22205 tree unsigned_ftype_unsigned_ushort
22206 = build_function_type_list (unsigned_type_node,
22207 unsigned_type_node,
22208 short_unsigned_type_node,
22210 tree unsigned_ftype_unsigned_unsigned
22211 = build_function_type_list (unsigned_type_node,
22212 unsigned_type_node,
22213 unsigned_type_node,
22215 tree uint64_ftype_uint64_uint64
22216 = build_function_type_list (long_long_unsigned_type_node,
22217 long_long_unsigned_type_node,
22218 long_long_unsigned_type_node,
22220 tree float_ftype_float
22221 = build_function_type_list (float_type_node,
22226 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22228 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22230 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22232 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22234 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22236 tree v8sf_ftype_v8sf
22237 = build_function_type_list (V8SF_type_node,
22240 tree v8si_ftype_v8sf
22241 = build_function_type_list (V8SI_type_node,
22244 tree v8sf_ftype_v8si
22245 = build_function_type_list (V8SF_type_node,
22248 tree v4si_ftype_v4df
22249 = build_function_type_list (V4SI_type_node,
22252 tree v4df_ftype_v4df
22253 = build_function_type_list (V4DF_type_node,
22256 tree v4df_ftype_v4si
22257 = build_function_type_list (V4DF_type_node,
22260 tree v4df_ftype_v4sf
22261 = build_function_type_list (V4DF_type_node,
22264 tree v4sf_ftype_v4df
22265 = build_function_type_list (V4SF_type_node,
22268 tree v8sf_ftype_v8sf_v8sf
22269 = build_function_type_list (V8SF_type_node,
22270 V8SF_type_node, V8SF_type_node,
22272 tree v4df_ftype_v4df_v4df
22273 = build_function_type_list (V4DF_type_node,
22274 V4DF_type_node, V4DF_type_node,
22276 tree v8sf_ftype_v8sf_int
22277 = build_function_type_list (V8SF_type_node,
22278 V8SF_type_node, integer_type_node,
22280 tree v4si_ftype_v8si_int
22281 = build_function_type_list (V4SI_type_node,
22282 V8SI_type_node, integer_type_node,
22284 tree v4df_ftype_v4df_int
22285 = build_function_type_list (V4DF_type_node,
22286 V4DF_type_node, integer_type_node,
22288 tree v4sf_ftype_v8sf_int
22289 = build_function_type_list (V4SF_type_node,
22290 V8SF_type_node, integer_type_node,
22292 tree v2df_ftype_v4df_int
22293 = build_function_type_list (V2DF_type_node,
22294 V4DF_type_node, integer_type_node,
22296 tree v8sf_ftype_v8sf_v8sf_int
22297 = build_function_type_list (V8SF_type_node,
22298 V8SF_type_node, V8SF_type_node,
22301 tree v8sf_ftype_v8sf_v8sf_v8sf
22302 = build_function_type_list (V8SF_type_node,
22303 V8SF_type_node, V8SF_type_node,
22306 tree v4df_ftype_v4df_v4df_v4df
22307 = build_function_type_list (V4DF_type_node,
22308 V4DF_type_node, V4DF_type_node,
22311 tree v8si_ftype_v8si_v8si_int
22312 = build_function_type_list (V8SI_type_node,
22313 V8SI_type_node, V8SI_type_node,
22316 tree v4df_ftype_v4df_v4df_int
22317 = build_function_type_list (V4DF_type_node,
22318 V4DF_type_node, V4DF_type_node,
22321 tree v8sf_ftype_pcfloat
22322 = build_function_type_list (V8SF_type_node,
22325 tree v4df_ftype_pcdouble
22326 = build_function_type_list (V4DF_type_node,
22327 pcdouble_type_node,
22329 tree pcv4sf_type_node
22330 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22331 tree pcv2df_type_node
22332 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22333 tree v8sf_ftype_pcv4sf
22334 = build_function_type_list (V8SF_type_node,
22337 tree v4df_ftype_pcv2df
22338 = build_function_type_list (V4DF_type_node,
22341 tree v32qi_ftype_pcchar
22342 = build_function_type_list (V32QI_type_node,
22345 tree void_ftype_pchar_v32qi
22346 = build_function_type_list (void_type_node,
22347 pchar_type_node, V32QI_type_node,
22349 tree v8si_ftype_v8si_v4si_int
22350 = build_function_type_list (V8SI_type_node,
22351 V8SI_type_node, V4SI_type_node,
22354 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22355 tree void_ftype_pv4di_v4di
22356 = build_function_type_list (void_type_node,
22357 pv4di_type_node, V4DI_type_node,
22359 tree v8sf_ftype_v8sf_v4sf_int
22360 = build_function_type_list (V8SF_type_node,
22361 V8SF_type_node, V4SF_type_node,
22364 tree v4df_ftype_v4df_v2df_int
22365 = build_function_type_list (V4DF_type_node,
22366 V4DF_type_node, V2DF_type_node,
22369 tree void_ftype_pfloat_v8sf
22370 = build_function_type_list (void_type_node,
22371 pfloat_type_node, V8SF_type_node,
22373 tree void_ftype_pdouble_v4df
22374 = build_function_type_list (void_type_node,
22375 pdouble_type_node, V4DF_type_node,
22377 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22378 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22379 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22380 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22381 tree pcv8sf_type_node
22382 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22383 tree pcv4df_type_node
22384 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22385 tree v8sf_ftype_pcv8sf_v8sf
22386 = build_function_type_list (V8SF_type_node,
22387 pcv8sf_type_node, V8SF_type_node,
22389 tree v4df_ftype_pcv4df_v4df
22390 = build_function_type_list (V4DF_type_node,
22391 pcv4df_type_node, V4DF_type_node,
22393 tree v4sf_ftype_pcv4sf_v4sf
22394 = build_function_type_list (V4SF_type_node,
22395 pcv4sf_type_node, V4SF_type_node,
22397 tree v2df_ftype_pcv2df_v2df
22398 = build_function_type_list (V2DF_type_node,
22399 pcv2df_type_node, V2DF_type_node,
22401 tree void_ftype_pv8sf_v8sf_v8sf
22402 = build_function_type_list (void_type_node,
22403 pv8sf_type_node, V8SF_type_node,
22406 tree void_ftype_pv4df_v4df_v4df
22407 = build_function_type_list (void_type_node,
22408 pv4df_type_node, V4DF_type_node,
22411 tree void_ftype_pv4sf_v4sf_v4sf
22412 = build_function_type_list (void_type_node,
22413 pv4sf_type_node, V4SF_type_node,
22416 tree void_ftype_pv2df_v2df_v2df
22417 = build_function_type_list (void_type_node,
22418 pv2df_type_node, V2DF_type_node,
22421 tree v4df_ftype_v2df
22422 = build_function_type_list (V4DF_type_node,
22425 tree v8sf_ftype_v4sf
22426 = build_function_type_list (V8SF_type_node,
22429 tree v8si_ftype_v4si
22430 = build_function_type_list (V8SI_type_node,
22433 tree v2df_ftype_v4df
22434 = build_function_type_list (V2DF_type_node,
22437 tree v4sf_ftype_v8sf
22438 = build_function_type_list (V4SF_type_node,
22441 tree v4si_ftype_v8si
22442 = build_function_type_list (V4SI_type_node,
22445 tree int_ftype_v4df
22446 = build_function_type_list (integer_type_node,
22449 tree int_ftype_v8sf
22450 = build_function_type_list (integer_type_node,
22453 tree int_ftype_v8sf_v8sf
22454 = build_function_type_list (integer_type_node,
22455 V8SF_type_node, V8SF_type_node,
22457 tree int_ftype_v4di_v4di
22458 = build_function_type_list (integer_type_node,
22459 V4DI_type_node, V4DI_type_node,
22461 tree int_ftype_v4df_v4df
22462 = build_function_type_list (integer_type_node,
22463 V4DF_type_node, V4DF_type_node,
22465 tree v8sf_ftype_v8sf_v8si
22466 = build_function_type_list (V8SF_type_node,
22467 V8SF_type_node, V8SI_type_node,
22469 tree v4df_ftype_v4df_v4di
22470 = build_function_type_list (V4DF_type_node,
22471 V4DF_type_node, V4DI_type_node,
22473 tree v4sf_ftype_v4sf_v4si
22474 = build_function_type_list (V4SF_type_node,
22475 V4SF_type_node, V4SI_type_node, NULL_TREE);
22476 tree v2df_ftype_v2df_v2di
22477 = build_function_type_list (V2DF_type_node,
22478 V2DF_type_node, V2DI_type_node, NULL_TREE);
22482 /* Add all special builtins with variable number of operands. */
22483 for (i = 0, d = bdesc_special_args;
22484 i < ARRAY_SIZE (bdesc_special_args);
22492 switch ((enum ix86_special_builtin_type) d->flag)
22494 case VOID_FTYPE_VOID:
22495 type = void_ftype_void;
22497 case V32QI_FTYPE_PCCHAR:
22498 type = v32qi_ftype_pcchar;
22500 case V16QI_FTYPE_PCCHAR:
22501 type = v16qi_ftype_pcchar;
22503 case V8SF_FTYPE_PCV4SF:
22504 type = v8sf_ftype_pcv4sf;
22506 case V8SF_FTYPE_PCFLOAT:
22507 type = v8sf_ftype_pcfloat;
22509 case V4DF_FTYPE_PCV2DF:
22510 type = v4df_ftype_pcv2df;
22512 case V4DF_FTYPE_PCDOUBLE:
22513 type = v4df_ftype_pcdouble;
22515 case V4SF_FTYPE_PCFLOAT:
22516 type = v4sf_ftype_pcfloat;
22518 case V2DI_FTYPE_PV2DI:
22519 type = v2di_ftype_pv2di;
22521 case V2DF_FTYPE_PCDOUBLE:
22522 type = v2df_ftype_pcdouble;
22524 case V8SF_FTYPE_PCV8SF_V8SF:
22525 type = v8sf_ftype_pcv8sf_v8sf;
22527 case V4DF_FTYPE_PCV4DF_V4DF:
22528 type = v4df_ftype_pcv4df_v4df;
22530 case V4SF_FTYPE_V4SF_PCV2SF:
22531 type = v4sf_ftype_v4sf_pcv2sf;
22533 case V4SF_FTYPE_PCV4SF_V4SF:
22534 type = v4sf_ftype_pcv4sf_v4sf;
22536 case V2DF_FTYPE_V2DF_PCDOUBLE:
22537 type = v2df_ftype_v2df_pcdouble;
22539 case V2DF_FTYPE_PCV2DF_V2DF:
22540 type = v2df_ftype_pcv2df_v2df;
22542 case VOID_FTYPE_PV2SF_V4SF:
22543 type = void_ftype_pv2sf_v4sf;
22545 case VOID_FTYPE_PV4DI_V4DI:
22546 type = void_ftype_pv4di_v4di;
22548 case VOID_FTYPE_PV2DI_V2DI:
22549 type = void_ftype_pv2di_v2di;
22551 case VOID_FTYPE_PCHAR_V32QI:
22552 type = void_ftype_pchar_v32qi;
22554 case VOID_FTYPE_PCHAR_V16QI:
22555 type = void_ftype_pchar_v16qi;
22557 case VOID_FTYPE_PFLOAT_V8SF:
22558 type = void_ftype_pfloat_v8sf;
22560 case VOID_FTYPE_PFLOAT_V4SF:
22561 type = void_ftype_pfloat_v4sf;
22563 case VOID_FTYPE_PDOUBLE_V4DF:
22564 type = void_ftype_pdouble_v4df;
22566 case VOID_FTYPE_PDOUBLE_V2DF:
22567 type = void_ftype_pdouble_v2df;
22569 case VOID_FTYPE_PDI_DI:
22570 type = void_ftype_pdi_di;
22572 case VOID_FTYPE_PINT_INT:
22573 type = void_ftype_pint_int;
22575 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22576 type = void_ftype_pv8sf_v8sf_v8sf;
22578 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22579 type = void_ftype_pv4df_v4df_v4df;
22581 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22582 type = void_ftype_pv4sf_v4sf_v4sf;
22584 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22585 type = void_ftype_pv2df_v2df_v2df;
22588 gcc_unreachable ();
22591 def_builtin (d->mask, d->name, type, d->code);
22594 /* Add all builtins with variable number of operands. */
22595 for (i = 0, d = bdesc_args;
22596 i < ARRAY_SIZE (bdesc_args);
22604 switch ((enum ix86_builtin_type) d->flag)
22606 case FLOAT_FTYPE_FLOAT:
22607 type = float_ftype_float;
22609 case INT_FTYPE_V8SF_V8SF_PTEST:
22610 type = int_ftype_v8sf_v8sf;
22612 case INT_FTYPE_V4DI_V4DI_PTEST:
22613 type = int_ftype_v4di_v4di;
22615 case INT_FTYPE_V4DF_V4DF_PTEST:
22616 type = int_ftype_v4df_v4df;
22618 case INT_FTYPE_V4SF_V4SF_PTEST:
22619 type = int_ftype_v4sf_v4sf;
22621 case INT_FTYPE_V2DI_V2DI_PTEST:
22622 type = int_ftype_v2di_v2di;
22624 case INT_FTYPE_V2DF_V2DF_PTEST:
22625 type = int_ftype_v2df_v2df;
22627 case INT64_FTYPE_V4SF:
22628 type = int64_ftype_v4sf;
22630 case INT64_FTYPE_V2DF:
22631 type = int64_ftype_v2df;
22633 case INT_FTYPE_V16QI:
22634 type = int_ftype_v16qi;
22636 case INT_FTYPE_V8QI:
22637 type = int_ftype_v8qi;
22639 case INT_FTYPE_V8SF:
22640 type = int_ftype_v8sf;
22642 case INT_FTYPE_V4DF:
22643 type = int_ftype_v4df;
22645 case INT_FTYPE_V4SF:
22646 type = int_ftype_v4sf;
22648 case INT_FTYPE_V2DF:
22649 type = int_ftype_v2df;
22651 case V16QI_FTYPE_V16QI:
22652 type = v16qi_ftype_v16qi;
22654 case V8SI_FTYPE_V8SF:
22655 type = v8si_ftype_v8sf;
22657 case V8SI_FTYPE_V4SI:
22658 type = v8si_ftype_v4si;
22660 case V8HI_FTYPE_V8HI:
22661 type = v8hi_ftype_v8hi;
22663 case V8HI_FTYPE_V16QI:
22664 type = v8hi_ftype_v16qi;
22666 case V8QI_FTYPE_V8QI:
22667 type = v8qi_ftype_v8qi;
22669 case V8SF_FTYPE_V8SF:
22670 type = v8sf_ftype_v8sf;
22672 case V8SF_FTYPE_V8SI:
22673 type = v8sf_ftype_v8si;
22675 case V8SF_FTYPE_V4SF:
22676 type = v8sf_ftype_v4sf;
22678 case V4SI_FTYPE_V4DF:
22679 type = v4si_ftype_v4df;
22681 case V4SI_FTYPE_V4SI:
22682 type = v4si_ftype_v4si;
22684 case V4SI_FTYPE_V16QI:
22685 type = v4si_ftype_v16qi;
22687 case V4SI_FTYPE_V8SI:
22688 type = v4si_ftype_v8si;
22690 case V4SI_FTYPE_V8HI:
22691 type = v4si_ftype_v8hi;
22693 case V4SI_FTYPE_V4SF:
22694 type = v4si_ftype_v4sf;
22696 case V4SI_FTYPE_V2DF:
22697 type = v4si_ftype_v2df;
22699 case V4HI_FTYPE_V4HI:
22700 type = v4hi_ftype_v4hi;
22702 case V4DF_FTYPE_V4DF:
22703 type = v4df_ftype_v4df;
22705 case V4DF_FTYPE_V4SI:
22706 type = v4df_ftype_v4si;
22708 case V4DF_FTYPE_V4SF:
22709 type = v4df_ftype_v4sf;
22711 case V4DF_FTYPE_V2DF:
22712 type = v4df_ftype_v2df;
22714 case V4SF_FTYPE_V4SF:
22715 case V4SF_FTYPE_V4SF_VEC_MERGE:
22716 type = v4sf_ftype_v4sf;
22718 case V4SF_FTYPE_V8SF:
22719 type = v4sf_ftype_v8sf;
22721 case V4SF_FTYPE_V4SI:
22722 type = v4sf_ftype_v4si;
22724 case V4SF_FTYPE_V4DF:
22725 type = v4sf_ftype_v4df;
22727 case V4SF_FTYPE_V2DF:
22728 type = v4sf_ftype_v2df;
22730 case V2DI_FTYPE_V2DI:
22731 type = v2di_ftype_v2di;
22733 case V2DI_FTYPE_V16QI:
22734 type = v2di_ftype_v16qi;
22736 case V2DI_FTYPE_V8HI:
22737 type = v2di_ftype_v8hi;
22739 case V2DI_FTYPE_V4SI:
22740 type = v2di_ftype_v4si;
22742 case V2SI_FTYPE_V2SI:
22743 type = v2si_ftype_v2si;
22745 case V2SI_FTYPE_V4SF:
22746 type = v2si_ftype_v4sf;
22748 case V2SI_FTYPE_V2DF:
22749 type = v2si_ftype_v2df;
22751 case V2SI_FTYPE_V2SF:
22752 type = v2si_ftype_v2sf;
22754 case V2DF_FTYPE_V4DF:
22755 type = v2df_ftype_v4df;
22757 case V2DF_FTYPE_V4SF:
22758 type = v2df_ftype_v4sf;
22760 case V2DF_FTYPE_V2DF:
22761 case V2DF_FTYPE_V2DF_VEC_MERGE:
22762 type = v2df_ftype_v2df;
22764 case V2DF_FTYPE_V2SI:
22765 type = v2df_ftype_v2si;
22767 case V2DF_FTYPE_V4SI:
22768 type = v2df_ftype_v4si;
22770 case V2SF_FTYPE_V2SF:
22771 type = v2sf_ftype_v2sf;
22773 case V2SF_FTYPE_V2SI:
22774 type = v2sf_ftype_v2si;
22776 case V16QI_FTYPE_V16QI_V16QI:
22777 type = v16qi_ftype_v16qi_v16qi;
22779 case V16QI_FTYPE_V8HI_V8HI:
22780 type = v16qi_ftype_v8hi_v8hi;
22782 case V8QI_FTYPE_V8QI_V8QI:
22783 type = v8qi_ftype_v8qi_v8qi;
22785 case V8QI_FTYPE_V4HI_V4HI:
22786 type = v8qi_ftype_v4hi_v4hi;
22788 case V8HI_FTYPE_V8HI_V8HI:
22789 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22790 type = v8hi_ftype_v8hi_v8hi;
22792 case V8HI_FTYPE_V16QI_V16QI:
22793 type = v8hi_ftype_v16qi_v16qi;
22795 case V8HI_FTYPE_V4SI_V4SI:
22796 type = v8hi_ftype_v4si_v4si;
22798 case V8HI_FTYPE_V8HI_SI_COUNT:
22799 type = v8hi_ftype_v8hi_int;
22801 case V8SF_FTYPE_V8SF_V8SF:
22802 type = v8sf_ftype_v8sf_v8sf;
22804 case V8SF_FTYPE_V8SF_V8SI:
22805 type = v8sf_ftype_v8sf_v8si;
22807 case V4SI_FTYPE_V4SI_V4SI:
22808 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22809 type = v4si_ftype_v4si_v4si;
22811 case V4SI_FTYPE_V8HI_V8HI:
22812 type = v4si_ftype_v8hi_v8hi;
22814 case V4SI_FTYPE_V4SF_V4SF:
22815 type = v4si_ftype_v4sf_v4sf;
22817 case V4SI_FTYPE_V2DF_V2DF:
22818 type = v4si_ftype_v2df_v2df;
22820 case V4SI_FTYPE_V4SI_SI_COUNT:
22821 type = v4si_ftype_v4si_int;
22823 case V4HI_FTYPE_V4HI_V4HI:
22824 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22825 type = v4hi_ftype_v4hi_v4hi;
22827 case V4HI_FTYPE_V8QI_V8QI:
22828 type = v4hi_ftype_v8qi_v8qi;
22830 case V4HI_FTYPE_V2SI_V2SI:
22831 type = v4hi_ftype_v2si_v2si;
22833 case V4HI_FTYPE_V4HI_SI_COUNT:
22834 type = v4hi_ftype_v4hi_int;
22836 case V4DF_FTYPE_V4DF_V4DF:
22837 type = v4df_ftype_v4df_v4df;
22839 case V4DF_FTYPE_V4DF_V4DI:
22840 type = v4df_ftype_v4df_v4di;
22842 case V4SF_FTYPE_V4SF_V4SF:
22843 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22844 type = v4sf_ftype_v4sf_v4sf;
22846 case V4SF_FTYPE_V4SF_V4SI:
22847 type = v4sf_ftype_v4sf_v4si;
22849 case V4SF_FTYPE_V4SF_V2SI:
22850 type = v4sf_ftype_v4sf_v2si;
22852 case V4SF_FTYPE_V4SF_V2DF:
22853 type = v4sf_ftype_v4sf_v2df;
22855 case V4SF_FTYPE_V4SF_DI:
22856 type = v4sf_ftype_v4sf_int64;
22858 case V4SF_FTYPE_V4SF_SI:
22859 type = v4sf_ftype_v4sf_int;
22861 case V2DI_FTYPE_V2DI_V2DI:
22862 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22863 type = v2di_ftype_v2di_v2di;
22865 case V2DI_FTYPE_V16QI_V16QI:
22866 type = v2di_ftype_v16qi_v16qi;
22868 case V2DI_FTYPE_V4SI_V4SI:
22869 type = v2di_ftype_v4si_v4si;
22871 case V2DI_FTYPE_V2DI_V16QI:
22872 type = v2di_ftype_v2di_v16qi;
22874 case V2DI_FTYPE_V2DF_V2DF:
22875 type = v2di_ftype_v2df_v2df;
22877 case V2DI_FTYPE_V2DI_SI_COUNT:
22878 type = v2di_ftype_v2di_int;
22880 case V2SI_FTYPE_V2SI_V2SI:
22881 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22882 type = v2si_ftype_v2si_v2si;
22884 case V2SI_FTYPE_V4HI_V4HI:
22885 type = v2si_ftype_v4hi_v4hi;
22887 case V2SI_FTYPE_V2SF_V2SF:
22888 type = v2si_ftype_v2sf_v2sf;
22890 case V2SI_FTYPE_V2SI_SI_COUNT:
22891 type = v2si_ftype_v2si_int;
22893 case V2DF_FTYPE_V2DF_V2DF:
22894 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22895 type = v2df_ftype_v2df_v2df;
22897 case V2DF_FTYPE_V2DF_V4SF:
22898 type = v2df_ftype_v2df_v4sf;
22900 case V2DF_FTYPE_V2DF_V2DI:
22901 type = v2df_ftype_v2df_v2di;
22903 case V2DF_FTYPE_V2DF_DI:
22904 type = v2df_ftype_v2df_int64;
22906 case V2DF_FTYPE_V2DF_SI:
22907 type = v2df_ftype_v2df_int;
22909 case V2SF_FTYPE_V2SF_V2SF:
22910 type = v2sf_ftype_v2sf_v2sf;
22912 case V1DI_FTYPE_V1DI_V1DI:
22913 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22914 type = v1di_ftype_v1di_v1di;
22916 case V1DI_FTYPE_V8QI_V8QI:
22917 type = v1di_ftype_v8qi_v8qi;
22919 case V1DI_FTYPE_V2SI_V2SI:
22920 type = v1di_ftype_v2si_v2si;
22922 case V1DI_FTYPE_V1DI_SI_COUNT:
22923 type = v1di_ftype_v1di_int;
22925 case UINT64_FTYPE_UINT64_UINT64:
22926 type = uint64_ftype_uint64_uint64;
22928 case UINT_FTYPE_UINT_UINT:
22929 type = unsigned_ftype_unsigned_unsigned;
22931 case UINT_FTYPE_UINT_USHORT:
22932 type = unsigned_ftype_unsigned_ushort;
22934 case UINT_FTYPE_UINT_UCHAR:
22935 type = unsigned_ftype_unsigned_uchar;
22937 case V8HI_FTYPE_V8HI_INT:
22938 type = v8hi_ftype_v8hi_int;
22940 case V8SF_FTYPE_V8SF_INT:
22941 type = v8sf_ftype_v8sf_int;
22943 case V4SI_FTYPE_V4SI_INT:
22944 type = v4si_ftype_v4si_int;
22946 case V4SI_FTYPE_V8SI_INT:
22947 type = v4si_ftype_v8si_int;
22949 case V4HI_FTYPE_V4HI_INT:
22950 type = v4hi_ftype_v4hi_int;
22952 case V4DF_FTYPE_V4DF_INT:
22953 type = v4df_ftype_v4df_int;
22955 case V4SF_FTYPE_V4SF_INT:
22956 type = v4sf_ftype_v4sf_int;
22958 case V4SF_FTYPE_V8SF_INT:
22959 type = v4sf_ftype_v8sf_int;
22961 case V2DI_FTYPE_V2DI_INT:
22962 case V2DI2TI_FTYPE_V2DI_INT:
22963 type = v2di_ftype_v2di_int;
22965 case V2DF_FTYPE_V2DF_INT:
22966 type = v2df_ftype_v2df_int;
22968 case V2DF_FTYPE_V4DF_INT:
22969 type = v2df_ftype_v4df_int;
22971 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22972 type = v16qi_ftype_v16qi_v16qi_v16qi;
22974 case V8SF_FTYPE_V8SF_V8SF_V8SF:
22975 type = v8sf_ftype_v8sf_v8sf_v8sf;
22977 case V4DF_FTYPE_V4DF_V4DF_V4DF:
22978 type = v4df_ftype_v4df_v4df_v4df;
22980 case V4SF_FTYPE_V4SF_V4SF_V4SF:
22981 type = v4sf_ftype_v4sf_v4sf_v4sf;
22983 case V2DF_FTYPE_V2DF_V2DF_V2DF:
22984 type = v2df_ftype_v2df_v2df_v2df;
22986 case V16QI_FTYPE_V16QI_V16QI_INT:
22987 type = v16qi_ftype_v16qi_v16qi_int;
22989 case V8SI_FTYPE_V8SI_V8SI_INT:
22990 type = v8si_ftype_v8si_v8si_int;
22992 case V8SI_FTYPE_V8SI_V4SI_INT:
22993 type = v8si_ftype_v8si_v4si_int;
22995 case V8HI_FTYPE_V8HI_V8HI_INT:
22996 type = v8hi_ftype_v8hi_v8hi_int;
22998 case V8SF_FTYPE_V8SF_V8SF_INT:
22999 type = v8sf_ftype_v8sf_v8sf_int;
23001 case V8SF_FTYPE_V8SF_V4SF_INT:
23002 type = v8sf_ftype_v8sf_v4sf_int;
23004 case V4SI_FTYPE_V4SI_V4SI_INT:
23005 type = v4si_ftype_v4si_v4si_int;
23007 case V4DF_FTYPE_V4DF_V4DF_INT:
23008 type = v4df_ftype_v4df_v4df_int;
23010 case V4DF_FTYPE_V4DF_V2DF_INT:
23011 type = v4df_ftype_v4df_v2df_int;
23013 case V4SF_FTYPE_V4SF_V4SF_INT:
23014 type = v4sf_ftype_v4sf_v4sf_int;
23016 case V2DI_FTYPE_V2DI_V2DI_INT:
23017 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23018 type = v2di_ftype_v2di_v2di_int;
23020 case V2DF_FTYPE_V2DF_V2DF_INT:
23021 type = v2df_ftype_v2df_v2df_int;
23023 case V2DI_FTYPE_V2DI_UINT_UINT:
23024 type = v2di_ftype_v2di_unsigned_unsigned;
23026 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23027 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23029 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23030 type = v1di_ftype_v1di_v1di_int;
23033 gcc_unreachable ();
23036 def_builtin_const (d->mask, d->name, type, d->code);
23039 /* pcmpestr[im] insns. */
23040 for (i = 0, d = bdesc_pcmpestr;
23041 i < ARRAY_SIZE (bdesc_pcmpestr);
23044 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23045 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23047 ftype = int_ftype_v16qi_int_v16qi_int_int;
23048 def_builtin_const (d->mask, d->name, ftype, d->code);
23051 /* pcmpistr[im] insns. */
23052 for (i = 0, d = bdesc_pcmpistr;
23053 i < ARRAY_SIZE (bdesc_pcmpistr);
23056 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23057 ftype = v16qi_ftype_v16qi_v16qi_int;
23059 ftype = int_ftype_v16qi_v16qi_int;
23060 def_builtin_const (d->mask, d->name, ftype, d->code);
23063 /* comi/ucomi insns. */
23064 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23065 if (d->mask == OPTION_MASK_ISA_SSE2)
23066 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23068 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23071 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23072 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23074 /* SSE or 3DNow!A */
23075 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23078 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23080 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23081 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23084 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23085 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23088 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23089 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23090 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23091 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23092 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23093 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23096 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23099 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23100 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23102 /* Access to the vec_init patterns. */
23103 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23104 integer_type_node, NULL_TREE);
23105 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23107 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23108 short_integer_type_node,
23109 short_integer_type_node,
23110 short_integer_type_node, NULL_TREE);
23111 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23113 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23114 char_type_node, char_type_node,
23115 char_type_node, char_type_node,
23116 char_type_node, char_type_node,
23117 char_type_node, NULL_TREE);
23118 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23120 /* Access to the vec_extract patterns. */
23121 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23122 integer_type_node, NULL_TREE);
23123 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23125 ftype = build_function_type_list (long_long_integer_type_node,
23126 V2DI_type_node, integer_type_node,
23128 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23130 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23131 integer_type_node, NULL_TREE);
23132 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23134 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23135 integer_type_node, NULL_TREE);
23136 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23138 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23139 integer_type_node, NULL_TREE);
23140 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23142 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23143 integer_type_node, NULL_TREE);
23144 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23146 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23147 integer_type_node, NULL_TREE);
23148 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23150 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23151 integer_type_node, NULL_TREE);
23152 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23154 /* Access to the vec_set patterns. */
23155 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23157 integer_type_node, NULL_TREE);
23158 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23160 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23162 integer_type_node, NULL_TREE);
23163 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23165 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23167 integer_type_node, NULL_TREE);
23168 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23170 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23172 integer_type_node, NULL_TREE);
23173 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23175 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23177 integer_type_node, NULL_TREE);
23178 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23180 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23182 integer_type_node, NULL_TREE);
23183 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23185 /* Add SSE5 multi-arg argument instructions */
23186 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23188 tree mtype = NULL_TREE;
23193 switch ((enum multi_arg_type)d->flag)
23195 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23196 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23197 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23198 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23199 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23200 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23201 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23202 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23203 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23204 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23205 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23206 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23207 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23208 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23209 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23210 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23211 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23212 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23213 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23214 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23215 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23216 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23217 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23218 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23219 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23220 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23221 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23222 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23223 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23224 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23225 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23226 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23227 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23228 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23229 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23230 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23231 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23232 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23233 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23234 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23235 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23236 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23237 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23238 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23239 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23240 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23241 case MULTI_ARG_UNKNOWN:
23243 gcc_unreachable ();
23247 def_builtin_const (d->mask, d->name, mtype, d->code);
23251 /* Internal method for ix86_init_builtins. */
23254 ix86_init_builtins_va_builtins_abi (void)
23256 tree ms_va_ref, sysv_va_ref;
23257 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23258 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23259 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23260 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23264 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23265 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23266 ms_va_ref = build_reference_type (ms_va_list_type_node);
23268 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23271 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23272 fnvoid_va_start_ms =
23273 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23274 fnvoid_va_end_sysv =
23275 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23276 fnvoid_va_start_sysv =
23277 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23279 fnvoid_va_copy_ms =
23280 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23282 fnvoid_va_copy_sysv =
23283 build_function_type_list (void_type_node, sysv_va_ref,
23284 sysv_va_ref, NULL_TREE);
23286 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23287 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23288 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23289 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23290 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23291 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23292 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23293 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23294 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23295 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23296 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23297 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23301 ix86_init_builtins (void)
23303 tree float128_type_node = make_node (REAL_TYPE);
23306 /* The __float80 type. */
23307 if (TYPE_MODE (long_double_type_node) == XFmode)
23308 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23312 /* The __float80 type. */
23313 tree float80_type_node = make_node (REAL_TYPE);
23315 TYPE_PRECISION (float80_type_node) = 80;
23316 layout_type (float80_type_node);
23317 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23321 /* The __float128 type. */
23322 TYPE_PRECISION (float128_type_node) = 128;
23323 layout_type (float128_type_node);
23324 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23327 /* TFmode support builtins. */
23328 ftype = build_function_type (float128_type_node, void_list_node);
23329 decl = add_builtin_function ("__builtin_infq", ftype,
23330 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23332 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23334 /* We will expand them to normal call if SSE2 isn't available since
23335 they are used by libgcc. */
23336 ftype = build_function_type_list (float128_type_node,
23337 float128_type_node,
23339 decl = add_builtin_function ("__builtin_fabsq", ftype,
23340 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23341 "__fabstf2", NULL_TREE);
23342 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23343 TREE_READONLY (decl) = 1;
23345 ftype = build_function_type_list (float128_type_node,
23346 float128_type_node,
23347 float128_type_node,
23349 decl = add_builtin_function ("__builtin_copysignq", ftype,
23350 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23351 "__copysigntf3", NULL_TREE);
23352 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23353 TREE_READONLY (decl) = 1;
23355 ix86_init_mmx_sse_builtins ();
23357 ix86_init_builtins_va_builtins_abi ();
23360 /* Errors in the source file can cause expand_expr to return const0_rtx
23361 where we expect a vector. To avoid crashing, use one of the vector
23362 clear instructions. */
23364 safe_vector_operand (rtx x, enum machine_mode mode)
23366 if (x == const0_rtx)
23367 x = CONST0_RTX (mode);
23371 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23374 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23377 tree arg0 = CALL_EXPR_ARG (exp, 0);
23378 tree arg1 = CALL_EXPR_ARG (exp, 1);
23379 rtx op0 = expand_normal (arg0);
23380 rtx op1 = expand_normal (arg1);
23381 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23382 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23383 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23385 if (VECTOR_MODE_P (mode0))
23386 op0 = safe_vector_operand (op0, mode0);
23387 if (VECTOR_MODE_P (mode1))
23388 op1 = safe_vector_operand (op1, mode1);
23390 if (optimize || !target
23391 || GET_MODE (target) != tmode
23392 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23393 target = gen_reg_rtx (tmode);
23395 if (GET_MODE (op1) == SImode && mode1 == TImode)
23397 rtx x = gen_reg_rtx (V4SImode);
23398 emit_insn (gen_sse2_loadd (x, op1));
23399 op1 = gen_lowpart (TImode, x);
23402 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23403 op0 = copy_to_mode_reg (mode0, op0);
23404 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23405 op1 = copy_to_mode_reg (mode1, op1);
23407 pat = GEN_FCN (icode) (target, op0, op1);
23416 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23419 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23420 enum multi_arg_type m_type,
23421 enum insn_code sub_code)
23426 bool comparison_p = false;
23428 bool last_arg_constant = false;
23429 int num_memory = 0;
23432 enum machine_mode mode;
23435 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23439 case MULTI_ARG_3_SF:
23440 case MULTI_ARG_3_DF:
23441 case MULTI_ARG_3_DI:
23442 case MULTI_ARG_3_SI:
23443 case MULTI_ARG_3_SI_DI:
23444 case MULTI_ARG_3_HI:
23445 case MULTI_ARG_3_HI_SI:
23446 case MULTI_ARG_3_QI:
23447 case MULTI_ARG_3_PERMPS:
23448 case MULTI_ARG_3_PERMPD:
23452 case MULTI_ARG_2_SF:
23453 case MULTI_ARG_2_DF:
23454 case MULTI_ARG_2_DI:
23455 case MULTI_ARG_2_SI:
23456 case MULTI_ARG_2_HI:
23457 case MULTI_ARG_2_QI:
23461 case MULTI_ARG_2_DI_IMM:
23462 case MULTI_ARG_2_SI_IMM:
23463 case MULTI_ARG_2_HI_IMM:
23464 case MULTI_ARG_2_QI_IMM:
23466 last_arg_constant = true;
23469 case MULTI_ARG_1_SF:
23470 case MULTI_ARG_1_DF:
23471 case MULTI_ARG_1_DI:
23472 case MULTI_ARG_1_SI:
23473 case MULTI_ARG_1_HI:
23474 case MULTI_ARG_1_QI:
23475 case MULTI_ARG_1_SI_DI:
23476 case MULTI_ARG_1_HI_DI:
23477 case MULTI_ARG_1_HI_SI:
23478 case MULTI_ARG_1_QI_DI:
23479 case MULTI_ARG_1_QI_SI:
23480 case MULTI_ARG_1_QI_HI:
23481 case MULTI_ARG_1_PH2PS:
23482 case MULTI_ARG_1_PS2PH:
23486 case MULTI_ARG_2_SF_CMP:
23487 case MULTI_ARG_2_DF_CMP:
23488 case MULTI_ARG_2_DI_CMP:
23489 case MULTI_ARG_2_SI_CMP:
23490 case MULTI_ARG_2_HI_CMP:
23491 case MULTI_ARG_2_QI_CMP:
23493 comparison_p = true;
23496 case MULTI_ARG_2_SF_TF:
23497 case MULTI_ARG_2_DF_TF:
23498 case MULTI_ARG_2_DI_TF:
23499 case MULTI_ARG_2_SI_TF:
23500 case MULTI_ARG_2_HI_TF:
23501 case MULTI_ARG_2_QI_TF:
23506 case MULTI_ARG_UNKNOWN:
23508 gcc_unreachable ();
23511 if (optimize || !target
23512 || GET_MODE (target) != tmode
23513 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23514 target = gen_reg_rtx (tmode);
23516 gcc_assert (nargs <= 4);
23518 for (i = 0; i < nargs; i++)
23520 tree arg = CALL_EXPR_ARG (exp, i);
23521 rtx op = expand_normal (arg);
23522 int adjust = (comparison_p) ? 1 : 0;
23523 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23525 if (last_arg_constant && i == nargs-1)
23527 if (GET_CODE (op) != CONST_INT)
23529 error ("last argument must be an immediate");
23530 return gen_reg_rtx (tmode);
23535 if (VECTOR_MODE_P (mode))
23536 op = safe_vector_operand (op, mode);
23538 /* If we aren't optimizing, only allow one memory operand to be
23540 if (memory_operand (op, mode))
23543 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23546 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23548 op = force_reg (mode, op);
23552 args[i].mode = mode;
23558 pat = GEN_FCN (icode) (target, args[0].op);
23563 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23564 GEN_INT ((int)sub_code));
23565 else if (! comparison_p)
23566 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23569 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23573 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23578 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23582 gcc_unreachable ();
23592 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23593 insns with vec_merge. */
23596 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23600 tree arg0 = CALL_EXPR_ARG (exp, 0);
23601 rtx op1, op0 = expand_normal (arg0);
23602 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23603 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23605 if (optimize || !target
23606 || GET_MODE (target) != tmode
23607 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23608 target = gen_reg_rtx (tmode);
23610 if (VECTOR_MODE_P (mode0))
23611 op0 = safe_vector_operand (op0, mode0);
23613 if ((optimize && !register_operand (op0, mode0))
23614 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23615 op0 = copy_to_mode_reg (mode0, op0);
23618 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23619 op1 = copy_to_mode_reg (mode0, op1);
23621 pat = GEN_FCN (icode) (target, op0, op1);
23628 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23631 ix86_expand_sse_compare (const struct builtin_description *d,
23632 tree exp, rtx target, bool swap)
23635 tree arg0 = CALL_EXPR_ARG (exp, 0);
23636 tree arg1 = CALL_EXPR_ARG (exp, 1);
23637 rtx op0 = expand_normal (arg0);
23638 rtx op1 = expand_normal (arg1);
23640 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23641 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23642 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23643 enum rtx_code comparison = d->comparison;
23645 if (VECTOR_MODE_P (mode0))
23646 op0 = safe_vector_operand (op0, mode0);
23647 if (VECTOR_MODE_P (mode1))
23648 op1 = safe_vector_operand (op1, mode1);
23650 /* Swap operands if we have a comparison that isn't available in
23654 rtx tmp = gen_reg_rtx (mode1);
23655 emit_move_insn (tmp, op1);
23660 if (optimize || !target
23661 || GET_MODE (target) != tmode
23662 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23663 target = gen_reg_rtx (tmode);
23665 if ((optimize && !register_operand (op0, mode0))
23666 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23667 op0 = copy_to_mode_reg (mode0, op0);
23668 if ((optimize && !register_operand (op1, mode1))
23669 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23670 op1 = copy_to_mode_reg (mode1, op1);
23672 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23673 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23680 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23683 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23687 tree arg0 = CALL_EXPR_ARG (exp, 0);
23688 tree arg1 = CALL_EXPR_ARG (exp, 1);
23689 rtx op0 = expand_normal (arg0);
23690 rtx op1 = expand_normal (arg1);
23691 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23692 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23693 enum rtx_code comparison = d->comparison;
23695 if (VECTOR_MODE_P (mode0))
23696 op0 = safe_vector_operand (op0, mode0);
23697 if (VECTOR_MODE_P (mode1))
23698 op1 = safe_vector_operand (op1, mode1);
23700 /* Swap operands if we have a comparison that isn't available in
23702 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23709 target = gen_reg_rtx (SImode);
23710 emit_move_insn (target, const0_rtx);
23711 target = gen_rtx_SUBREG (QImode, target, 0);
23713 if ((optimize && !register_operand (op0, mode0))
23714 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23715 op0 = copy_to_mode_reg (mode0, op0);
23716 if ((optimize && !register_operand (op1, mode1))
23717 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23718 op1 = copy_to_mode_reg (mode1, op1);
23720 pat = GEN_FCN (d->icode) (op0, op1);
23724 emit_insn (gen_rtx_SET (VOIDmode,
23725 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23726 gen_rtx_fmt_ee (comparison, QImode,
23730 return SUBREG_REG (target);
23733 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23736 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23740 tree arg0 = CALL_EXPR_ARG (exp, 0);
23741 tree arg1 = CALL_EXPR_ARG (exp, 1);
23742 rtx op0 = expand_normal (arg0);
23743 rtx op1 = expand_normal (arg1);
23744 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23745 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23746 enum rtx_code comparison = d->comparison;
23748 if (VECTOR_MODE_P (mode0))
23749 op0 = safe_vector_operand (op0, mode0);
23750 if (VECTOR_MODE_P (mode1))
23751 op1 = safe_vector_operand (op1, mode1);
23753 target = gen_reg_rtx (SImode);
23754 emit_move_insn (target, const0_rtx);
23755 target = gen_rtx_SUBREG (QImode, target, 0);
23757 if ((optimize && !register_operand (op0, mode0))
23758 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23759 op0 = copy_to_mode_reg (mode0, op0);
23760 if ((optimize && !register_operand (op1, mode1))
23761 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23762 op1 = copy_to_mode_reg (mode1, op1);
23764 pat = GEN_FCN (d->icode) (op0, op1);
23768 emit_insn (gen_rtx_SET (VOIDmode,
23769 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23770 gen_rtx_fmt_ee (comparison, QImode,
23774 return SUBREG_REG (target);
23777 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23780 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23781 tree exp, rtx target)
23784 tree arg0 = CALL_EXPR_ARG (exp, 0);
23785 tree arg1 = CALL_EXPR_ARG (exp, 1);
23786 tree arg2 = CALL_EXPR_ARG (exp, 2);
23787 tree arg3 = CALL_EXPR_ARG (exp, 3);
23788 tree arg4 = CALL_EXPR_ARG (exp, 4);
23789 rtx scratch0, scratch1;
23790 rtx op0 = expand_normal (arg0);
23791 rtx op1 = expand_normal (arg1);
23792 rtx op2 = expand_normal (arg2);
23793 rtx op3 = expand_normal (arg3);
23794 rtx op4 = expand_normal (arg4);
23795 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23797 tmode0 = insn_data[d->icode].operand[0].mode;
23798 tmode1 = insn_data[d->icode].operand[1].mode;
23799 modev2 = insn_data[d->icode].operand[2].mode;
23800 modei3 = insn_data[d->icode].operand[3].mode;
23801 modev4 = insn_data[d->icode].operand[4].mode;
23802 modei5 = insn_data[d->icode].operand[5].mode;
23803 modeimm = insn_data[d->icode].operand[6].mode;
23805 if (VECTOR_MODE_P (modev2))
23806 op0 = safe_vector_operand (op0, modev2);
23807 if (VECTOR_MODE_P (modev4))
23808 op2 = safe_vector_operand (op2, modev4);
23810 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23811 op0 = copy_to_mode_reg (modev2, op0);
23812 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23813 op1 = copy_to_mode_reg (modei3, op1);
23814 if ((optimize && !register_operand (op2, modev4))
23815 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23816 op2 = copy_to_mode_reg (modev4, op2);
23817 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23818 op3 = copy_to_mode_reg (modei5, op3);
23820 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23822 error ("the fifth argument must be a 8-bit immediate");
23826 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23828 if (optimize || !target
23829 || GET_MODE (target) != tmode0
23830 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23831 target = gen_reg_rtx (tmode0);
23833 scratch1 = gen_reg_rtx (tmode1);
23835 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23837 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23839 if (optimize || !target
23840 || GET_MODE (target) != tmode1
23841 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23842 target = gen_reg_rtx (tmode1);
23844 scratch0 = gen_reg_rtx (tmode0);
23846 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23850 gcc_assert (d->flag);
23852 scratch0 = gen_reg_rtx (tmode0);
23853 scratch1 = gen_reg_rtx (tmode1);
23855 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23865 target = gen_reg_rtx (SImode);
23866 emit_move_insn (target, const0_rtx);
23867 target = gen_rtx_SUBREG (QImode, target, 0);
23870 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23871 gen_rtx_fmt_ee (EQ, QImode,
23872 gen_rtx_REG ((enum machine_mode) d->flag,
23875 return SUBREG_REG (target);
23882 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23885 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23886 tree exp, rtx target)
23889 tree arg0 = CALL_EXPR_ARG (exp, 0);
23890 tree arg1 = CALL_EXPR_ARG (exp, 1);
23891 tree arg2 = CALL_EXPR_ARG (exp, 2);
23892 rtx scratch0, scratch1;
23893 rtx op0 = expand_normal (arg0);
23894 rtx op1 = expand_normal (arg1);
23895 rtx op2 = expand_normal (arg2);
23896 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23898 tmode0 = insn_data[d->icode].operand[0].mode;
23899 tmode1 = insn_data[d->icode].operand[1].mode;
23900 modev2 = insn_data[d->icode].operand[2].mode;
23901 modev3 = insn_data[d->icode].operand[3].mode;
23902 modeimm = insn_data[d->icode].operand[4].mode;
23904 if (VECTOR_MODE_P (modev2))
23905 op0 = safe_vector_operand (op0, modev2);
23906 if (VECTOR_MODE_P (modev3))
23907 op1 = safe_vector_operand (op1, modev3);
23909 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23910 op0 = copy_to_mode_reg (modev2, op0);
23911 if ((optimize && !register_operand (op1, modev3))
23912 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23913 op1 = copy_to_mode_reg (modev3, op1);
23915 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23917 error ("the third argument must be a 8-bit immediate");
23921 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23923 if (optimize || !target
23924 || GET_MODE (target) != tmode0
23925 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23926 target = gen_reg_rtx (tmode0);
23928 scratch1 = gen_reg_rtx (tmode1);
23930 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23932 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23934 if (optimize || !target
23935 || GET_MODE (target) != tmode1
23936 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23937 target = gen_reg_rtx (tmode1);
23939 scratch0 = gen_reg_rtx (tmode0);
23941 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23945 gcc_assert (d->flag);
23947 scratch0 = gen_reg_rtx (tmode0);
23948 scratch1 = gen_reg_rtx (tmode1);
23950 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23960 target = gen_reg_rtx (SImode);
23961 emit_move_insn (target, const0_rtx);
23962 target = gen_rtx_SUBREG (QImode, target, 0);
23965 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23966 gen_rtx_fmt_ee (EQ, QImode,
23967 gen_rtx_REG ((enum machine_mode) d->flag,
23970 return SUBREG_REG (target);
23976 /* Subroutine of ix86_expand_builtin to take care of insns with
23977 variable number of operands. */
23980 ix86_expand_args_builtin (const struct builtin_description *d,
23981 tree exp, rtx target)
23983 rtx pat, real_target;
23984 unsigned int i, nargs;
23985 unsigned int nargs_constant = 0;
23986 int num_memory = 0;
23990 enum machine_mode mode;
23992 bool last_arg_count = false;
23993 enum insn_code icode = d->icode;
23994 const struct insn_data *insn_p = &insn_data[icode];
23995 enum machine_mode tmode = insn_p->operand[0].mode;
23996 enum machine_mode rmode = VOIDmode;
23998 enum rtx_code comparison = d->comparison;
24000 switch ((enum ix86_builtin_type) d->flag)
24002 case INT_FTYPE_V8SF_V8SF_PTEST:
24003 case INT_FTYPE_V4DI_V4DI_PTEST:
24004 case INT_FTYPE_V4DF_V4DF_PTEST:
24005 case INT_FTYPE_V4SF_V4SF_PTEST:
24006 case INT_FTYPE_V2DI_V2DI_PTEST:
24007 case INT_FTYPE_V2DF_V2DF_PTEST:
24008 return ix86_expand_sse_ptest (d, exp, target);
24009 case FLOAT128_FTYPE_FLOAT128:
24010 case FLOAT_FTYPE_FLOAT:
24011 case INT64_FTYPE_V4SF:
24012 case INT64_FTYPE_V2DF:
24013 case INT_FTYPE_V16QI:
24014 case INT_FTYPE_V8QI:
24015 case INT_FTYPE_V8SF:
24016 case INT_FTYPE_V4DF:
24017 case INT_FTYPE_V4SF:
24018 case INT_FTYPE_V2DF:
24019 case V16QI_FTYPE_V16QI:
24020 case V8SI_FTYPE_V8SF:
24021 case V8SI_FTYPE_V4SI:
24022 case V8HI_FTYPE_V8HI:
24023 case V8HI_FTYPE_V16QI:
24024 case V8QI_FTYPE_V8QI:
24025 case V8SF_FTYPE_V8SF:
24026 case V8SF_FTYPE_V8SI:
24027 case V8SF_FTYPE_V4SF:
24028 case V4SI_FTYPE_V4SI:
24029 case V4SI_FTYPE_V16QI:
24030 case V4SI_FTYPE_V4SF:
24031 case V4SI_FTYPE_V8SI:
24032 case V4SI_FTYPE_V8HI:
24033 case V4SI_FTYPE_V4DF:
24034 case V4SI_FTYPE_V2DF:
24035 case V4HI_FTYPE_V4HI:
24036 case V4DF_FTYPE_V4DF:
24037 case V4DF_FTYPE_V4SI:
24038 case V4DF_FTYPE_V4SF:
24039 case V4DF_FTYPE_V2DF:
24040 case V4SF_FTYPE_V4SF:
24041 case V4SF_FTYPE_V4SI:
24042 case V4SF_FTYPE_V8SF:
24043 case V4SF_FTYPE_V4DF:
24044 case V4SF_FTYPE_V2DF:
24045 case V2DI_FTYPE_V2DI:
24046 case V2DI_FTYPE_V16QI:
24047 case V2DI_FTYPE_V8HI:
24048 case V2DI_FTYPE_V4SI:
24049 case V2DF_FTYPE_V2DF:
24050 case V2DF_FTYPE_V4SI:
24051 case V2DF_FTYPE_V4DF:
24052 case V2DF_FTYPE_V4SF:
24053 case V2DF_FTYPE_V2SI:
24054 case V2SI_FTYPE_V2SI:
24055 case V2SI_FTYPE_V4SF:
24056 case V2SI_FTYPE_V2SF:
24057 case V2SI_FTYPE_V2DF:
24058 case V2SF_FTYPE_V2SF:
24059 case V2SF_FTYPE_V2SI:
24062 case V4SF_FTYPE_V4SF_VEC_MERGE:
24063 case V2DF_FTYPE_V2DF_VEC_MERGE:
24064 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24065 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24066 case V16QI_FTYPE_V16QI_V16QI:
24067 case V16QI_FTYPE_V8HI_V8HI:
24068 case V8QI_FTYPE_V8QI_V8QI:
24069 case V8QI_FTYPE_V4HI_V4HI:
24070 case V8HI_FTYPE_V8HI_V8HI:
24071 case V8HI_FTYPE_V16QI_V16QI:
24072 case V8HI_FTYPE_V4SI_V4SI:
24073 case V8SF_FTYPE_V8SF_V8SF:
24074 case V8SF_FTYPE_V8SF_V8SI:
24075 case V4SI_FTYPE_V4SI_V4SI:
24076 case V4SI_FTYPE_V8HI_V8HI:
24077 case V4SI_FTYPE_V4SF_V4SF:
24078 case V4SI_FTYPE_V2DF_V2DF:
24079 case V4HI_FTYPE_V4HI_V4HI:
24080 case V4HI_FTYPE_V8QI_V8QI:
24081 case V4HI_FTYPE_V2SI_V2SI:
24082 case V4DF_FTYPE_V4DF_V4DF:
24083 case V4DF_FTYPE_V4DF_V4DI:
24084 case V4SF_FTYPE_V4SF_V4SF:
24085 case V4SF_FTYPE_V4SF_V4SI:
24086 case V4SF_FTYPE_V4SF_V2SI:
24087 case V4SF_FTYPE_V4SF_V2DF:
24088 case V4SF_FTYPE_V4SF_DI:
24089 case V4SF_FTYPE_V4SF_SI:
24090 case V2DI_FTYPE_V2DI_V2DI:
24091 case V2DI_FTYPE_V16QI_V16QI:
24092 case V2DI_FTYPE_V4SI_V4SI:
24093 case V2DI_FTYPE_V2DI_V16QI:
24094 case V2DI_FTYPE_V2DF_V2DF:
24095 case V2SI_FTYPE_V2SI_V2SI:
24096 case V2SI_FTYPE_V4HI_V4HI:
24097 case V2SI_FTYPE_V2SF_V2SF:
24098 case V2DF_FTYPE_V2DF_V2DF:
24099 case V2DF_FTYPE_V2DF_V4SF:
24100 case V2DF_FTYPE_V2DF_V2DI:
24101 case V2DF_FTYPE_V2DF_DI:
24102 case V2DF_FTYPE_V2DF_SI:
24103 case V2SF_FTYPE_V2SF_V2SF:
24104 case V1DI_FTYPE_V1DI_V1DI:
24105 case V1DI_FTYPE_V8QI_V8QI:
24106 case V1DI_FTYPE_V2SI_V2SI:
24107 if (comparison == UNKNOWN)
24108 return ix86_expand_binop_builtin (icode, exp, target);
24111 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24112 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24113 gcc_assert (comparison != UNKNOWN);
24117 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24118 case V8HI_FTYPE_V8HI_SI_COUNT:
24119 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24120 case V4SI_FTYPE_V4SI_SI_COUNT:
24121 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24122 case V4HI_FTYPE_V4HI_SI_COUNT:
24123 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24124 case V2DI_FTYPE_V2DI_SI_COUNT:
24125 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24126 case V2SI_FTYPE_V2SI_SI_COUNT:
24127 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24128 case V1DI_FTYPE_V1DI_SI_COUNT:
24130 last_arg_count = true;
24132 case UINT64_FTYPE_UINT64_UINT64:
24133 case UINT_FTYPE_UINT_UINT:
24134 case UINT_FTYPE_UINT_USHORT:
24135 case UINT_FTYPE_UINT_UCHAR:
24138 case V2DI2TI_FTYPE_V2DI_INT:
24141 nargs_constant = 1;
24143 case V8HI_FTYPE_V8HI_INT:
24144 case V8SF_FTYPE_V8SF_INT:
24145 case V4SI_FTYPE_V4SI_INT:
24146 case V4SI_FTYPE_V8SI_INT:
24147 case V4HI_FTYPE_V4HI_INT:
24148 case V4DF_FTYPE_V4DF_INT:
24149 case V4SF_FTYPE_V4SF_INT:
24150 case V4SF_FTYPE_V8SF_INT:
24151 case V2DI_FTYPE_V2DI_INT:
24152 case V2DF_FTYPE_V2DF_INT:
24153 case V2DF_FTYPE_V4DF_INT:
24155 nargs_constant = 1;
24157 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24158 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24159 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24160 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24161 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24164 case V16QI_FTYPE_V16QI_V16QI_INT:
24165 case V8HI_FTYPE_V8HI_V8HI_INT:
24166 case V8SI_FTYPE_V8SI_V8SI_INT:
24167 case V8SI_FTYPE_V8SI_V4SI_INT:
24168 case V8SF_FTYPE_V8SF_V8SF_INT:
24169 case V8SF_FTYPE_V8SF_V4SF_INT:
24170 case V4SI_FTYPE_V4SI_V4SI_INT:
24171 case V4DF_FTYPE_V4DF_V4DF_INT:
24172 case V4DF_FTYPE_V4DF_V2DF_INT:
24173 case V4SF_FTYPE_V4SF_V4SF_INT:
24174 case V2DI_FTYPE_V2DI_V2DI_INT:
24175 case V2DF_FTYPE_V2DF_V2DF_INT:
24177 nargs_constant = 1;
24179 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24182 nargs_constant = 1;
24184 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24187 nargs_constant = 1;
24189 case V2DI_FTYPE_V2DI_UINT_UINT:
24191 nargs_constant = 2;
24193 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24195 nargs_constant = 2;
24198 gcc_unreachable ();
24201 gcc_assert (nargs <= ARRAY_SIZE (args));
24203 if (comparison != UNKNOWN)
24205 gcc_assert (nargs == 2);
24206 return ix86_expand_sse_compare (d, exp, target, swap);
24209 if (rmode == VOIDmode || rmode == tmode)
24213 || GET_MODE (target) != tmode
24214 || ! (*insn_p->operand[0].predicate) (target, tmode))
24215 target = gen_reg_rtx (tmode);
24216 real_target = target;
24220 target = gen_reg_rtx (rmode);
24221 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24224 for (i = 0; i < nargs; i++)
24226 tree arg = CALL_EXPR_ARG (exp, i);
24227 rtx op = expand_normal (arg);
24228 enum machine_mode mode = insn_p->operand[i + 1].mode;
24229 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24231 if (last_arg_count && (i + 1) == nargs)
24233 /* SIMD shift insns take either an 8-bit immediate or
24234 register as count. But builtin functions take int as
24235 count. If count doesn't match, we put it in register. */
24238 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24239 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24240 op = copy_to_reg (op);
24243 else if ((nargs - i) <= nargs_constant)
24248 case CODE_FOR_sse4_1_roundpd:
24249 case CODE_FOR_sse4_1_roundps:
24250 case CODE_FOR_sse4_1_roundsd:
24251 case CODE_FOR_sse4_1_roundss:
24252 case CODE_FOR_sse4_1_blendps:
24253 case CODE_FOR_avx_blendpd256:
24254 case CODE_FOR_avx_vpermilv4df:
24255 case CODE_FOR_avx_roundpd256:
24256 case CODE_FOR_avx_roundps256:
24257 error ("the last argument must be a 4-bit immediate");
24260 case CODE_FOR_sse4_1_blendpd:
24261 case CODE_FOR_avx_vpermilv2df:
24262 error ("the last argument must be a 2-bit immediate");
24265 case CODE_FOR_avx_vextractf128v4df:
24266 case CODE_FOR_avx_vextractf128v8sf:
24267 case CODE_FOR_avx_vextractf128v8si:
24268 case CODE_FOR_avx_vinsertf128v4df:
24269 case CODE_FOR_avx_vinsertf128v8sf:
24270 case CODE_FOR_avx_vinsertf128v8si:
24271 error ("the last argument must be a 1-bit immediate");
24274 case CODE_FOR_avx_cmpsdv2df3:
24275 case CODE_FOR_avx_cmpssv4sf3:
24276 case CODE_FOR_avx_cmppdv2df3:
24277 case CODE_FOR_avx_cmppsv4sf3:
24278 case CODE_FOR_avx_cmppdv4df3:
24279 case CODE_FOR_avx_cmppsv8sf3:
24280 error ("the last argument must be a 5-bit immediate");
24284 switch (nargs_constant)
24287 if ((nargs - i) == nargs_constant)
24289 error ("the next to last argument must be an 8-bit immediate");
24293 error ("the last argument must be an 8-bit immediate");
24296 gcc_unreachable ();
24303 if (VECTOR_MODE_P (mode))
24304 op = safe_vector_operand (op, mode);
24306 /* If we aren't optimizing, only allow one memory operand to
24308 if (memory_operand (op, mode))
24311 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24313 if (optimize || !match || num_memory > 1)
24314 op = copy_to_mode_reg (mode, op);
24318 op = copy_to_reg (op);
24319 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24324 args[i].mode = mode;
24330 pat = GEN_FCN (icode) (real_target, args[0].op);
24333 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24336 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24340 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24341 args[2].op, args[3].op);
24344 gcc_unreachable ();
24354 /* Subroutine of ix86_expand_builtin to take care of special insns
24355 with variable number of operands. */
24358 ix86_expand_special_args_builtin (const struct builtin_description *d,
24359 tree exp, rtx target)
24363 unsigned int i, nargs, arg_adjust, memory;
24367 enum machine_mode mode;
24369 enum insn_code icode = d->icode;
24370 bool last_arg_constant = false;
24371 const struct insn_data *insn_p = &insn_data[icode];
24372 enum machine_mode tmode = insn_p->operand[0].mode;
24373 enum { load, store } klass;
24375 switch ((enum ix86_special_builtin_type) d->flag)
24377 case VOID_FTYPE_VOID:
24378 emit_insn (GEN_FCN (icode) (target));
24380 case V2DI_FTYPE_PV2DI:
24381 case V32QI_FTYPE_PCCHAR:
24382 case V16QI_FTYPE_PCCHAR:
24383 case V8SF_FTYPE_PCV4SF:
24384 case V8SF_FTYPE_PCFLOAT:
24385 case V4SF_FTYPE_PCFLOAT:
24386 case V4DF_FTYPE_PCV2DF:
24387 case V4DF_FTYPE_PCDOUBLE:
24388 case V2DF_FTYPE_PCDOUBLE:
24393 case VOID_FTYPE_PV2SF_V4SF:
24394 case VOID_FTYPE_PV4DI_V4DI:
24395 case VOID_FTYPE_PV2DI_V2DI:
24396 case VOID_FTYPE_PCHAR_V32QI:
24397 case VOID_FTYPE_PCHAR_V16QI:
24398 case VOID_FTYPE_PFLOAT_V8SF:
24399 case VOID_FTYPE_PFLOAT_V4SF:
24400 case VOID_FTYPE_PDOUBLE_V4DF:
24401 case VOID_FTYPE_PDOUBLE_V2DF:
24402 case VOID_FTYPE_PDI_DI:
24403 case VOID_FTYPE_PINT_INT:
24406 /* Reserve memory operand for target. */
24407 memory = ARRAY_SIZE (args);
24409 case V4SF_FTYPE_V4SF_PCV2SF:
24410 case V2DF_FTYPE_V2DF_PCDOUBLE:
24415 case V8SF_FTYPE_PCV8SF_V8SF:
24416 case V4DF_FTYPE_PCV4DF_V4DF:
24417 case V4SF_FTYPE_PCV4SF_V4SF:
24418 case V2DF_FTYPE_PCV2DF_V2DF:
24423 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24424 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24425 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24426 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24429 /* Reserve memory operand for target. */
24430 memory = ARRAY_SIZE (args);
24433 gcc_unreachable ();
24436 gcc_assert (nargs <= ARRAY_SIZE (args));
24438 if (klass == store)
24440 arg = CALL_EXPR_ARG (exp, 0);
24441 op = expand_normal (arg);
24442 gcc_assert (target == 0);
24443 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24451 || GET_MODE (target) != tmode
24452 || ! (*insn_p->operand[0].predicate) (target, tmode))
24453 target = gen_reg_rtx (tmode);
24456 for (i = 0; i < nargs; i++)
24458 enum machine_mode mode = insn_p->operand[i + 1].mode;
24461 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24462 op = expand_normal (arg);
24463 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24465 if (last_arg_constant && (i + 1) == nargs)
24471 error ("the last argument must be an 8-bit immediate");
24479 /* This must be the memory operand. */
24480 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24481 gcc_assert (GET_MODE (op) == mode
24482 || GET_MODE (op) == VOIDmode);
24486 /* This must be register. */
24487 if (VECTOR_MODE_P (mode))
24488 op = safe_vector_operand (op, mode);
24490 gcc_assert (GET_MODE (op) == mode
24491 || GET_MODE (op) == VOIDmode);
24492 op = copy_to_mode_reg (mode, op);
24497 args[i].mode = mode;
24503 pat = GEN_FCN (icode) (target, args[0].op);
24506 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24509 gcc_unreachable ();
24515 return klass == store ? 0 : target;
24518 /* Return the integer constant in ARG. Constrain it to be in the range
24519 of the subparts of VEC_TYPE; issue an error if not. */
24522 get_element_number (tree vec_type, tree arg)
24524 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24526 if (!host_integerp (arg, 1)
24527 || (elt = tree_low_cst (arg, 1), elt > max))
24529 error ("selector must be an integer constant in the range 0..%wi", max);
24536 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24537 ix86_expand_vector_init. We DO have language-level syntax for this, in
24538 the form of (type){ init-list }. Except that since we can't place emms
24539 instructions from inside the compiler, we can't allow the use of MMX
24540 registers unless the user explicitly asks for it. So we do *not* define
24541 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24542 we have builtins invoked by mmintrin.h that gives us license to emit
24543 these sorts of instructions. */
24546 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24548 enum machine_mode tmode = TYPE_MODE (type);
24549 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24550 int i, n_elt = GET_MODE_NUNITS (tmode);
24551 rtvec v = rtvec_alloc (n_elt);
24553 gcc_assert (VECTOR_MODE_P (tmode));
24554 gcc_assert (call_expr_nargs (exp) == n_elt);
24556 for (i = 0; i < n_elt; ++i)
24558 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24559 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24562 if (!target || !register_operand (target, tmode))
24563 target = gen_reg_rtx (tmode);
24565 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24569 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24570 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24571 had a language-level syntax for referencing vector elements. */
24574 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24576 enum machine_mode tmode, mode0;
24581 arg0 = CALL_EXPR_ARG (exp, 0);
24582 arg1 = CALL_EXPR_ARG (exp, 1);
24584 op0 = expand_normal (arg0);
24585 elt = get_element_number (TREE_TYPE (arg0), arg1);
24587 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24588 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24589 gcc_assert (VECTOR_MODE_P (mode0));
24591 op0 = force_reg (mode0, op0);
24593 if (optimize || !target || !register_operand (target, tmode))
24594 target = gen_reg_rtx (tmode);
24596 ix86_expand_vector_extract (true, target, op0, elt);
24601 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24602 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24603 a language-level syntax for referencing vector elements. */
24606 ix86_expand_vec_set_builtin (tree exp)
24608 enum machine_mode tmode, mode1;
24609 tree arg0, arg1, arg2;
24611 rtx op0, op1, target;
24613 arg0 = CALL_EXPR_ARG (exp, 0);
24614 arg1 = CALL_EXPR_ARG (exp, 1);
24615 arg2 = CALL_EXPR_ARG (exp, 2);
24617 tmode = TYPE_MODE (TREE_TYPE (arg0));
24618 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24619 gcc_assert (VECTOR_MODE_P (tmode));
24621 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24622 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24623 elt = get_element_number (TREE_TYPE (arg0), arg2);
24625 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24626 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24628 op0 = force_reg (tmode, op0);
24629 op1 = force_reg (mode1, op1);
24631 /* OP0 is the source of these builtin functions and shouldn't be
24632 modified. Create a copy, use it and return it as target. */
24633 target = gen_reg_rtx (tmode);
24634 emit_move_insn (target, op0);
24635 ix86_expand_vector_set (true, target, op1, elt);
24640 /* Expand an expression EXP that calls a built-in function,
24641 with result going to TARGET if that's convenient
24642 (and in mode MODE if that's convenient).
24643 SUBTARGET may be used as the target for computing one of EXP's operands.
24644 IGNORE is nonzero if the value is to be ignored. */
24647 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24648 enum machine_mode mode ATTRIBUTE_UNUSED,
24649 int ignore ATTRIBUTE_UNUSED)
24651 const struct builtin_description *d;
24653 enum insn_code icode;
24654 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24655 tree arg0, arg1, arg2;
24656 rtx op0, op1, op2, pat;
24657 enum machine_mode mode0, mode1, mode2;
24658 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24660 /* Determine whether the builtin function is available under the current ISA.
24661 Originally the builtin was not created if it wasn't applicable to the
24662 current ISA based on the command line switches. With function specific
24663 options, we need to check in the context of the function making the call
24664 whether it is supported. */
24665 if (ix86_builtins_isa[fcode].isa
24666 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24668 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24669 NULL, NULL, false);
24672 error ("%qE needs unknown isa option", fndecl);
24675 gcc_assert (opts != NULL);
24676 error ("%qE needs isa option %s", fndecl, opts);
24684 case IX86_BUILTIN_MASKMOVQ:
24685 case IX86_BUILTIN_MASKMOVDQU:
24686 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24687 ? CODE_FOR_mmx_maskmovq
24688 : CODE_FOR_sse2_maskmovdqu);
24689 /* Note the arg order is different from the operand order. */
24690 arg1 = CALL_EXPR_ARG (exp, 0);
24691 arg2 = CALL_EXPR_ARG (exp, 1);
24692 arg0 = CALL_EXPR_ARG (exp, 2);
24693 op0 = expand_normal (arg0);
24694 op1 = expand_normal (arg1);
24695 op2 = expand_normal (arg2);
24696 mode0 = insn_data[icode].operand[0].mode;
24697 mode1 = insn_data[icode].operand[1].mode;
24698 mode2 = insn_data[icode].operand[2].mode;
24700 op0 = force_reg (Pmode, op0);
24701 op0 = gen_rtx_MEM (mode1, op0);
24703 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24704 op0 = copy_to_mode_reg (mode0, op0);
24705 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24706 op1 = copy_to_mode_reg (mode1, op1);
24707 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24708 op2 = copy_to_mode_reg (mode2, op2);
24709 pat = GEN_FCN (icode) (op0, op1, op2);
24715 case IX86_BUILTIN_LDMXCSR:
24716 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24717 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24718 emit_move_insn (target, op0);
24719 emit_insn (gen_sse_ldmxcsr (target));
24722 case IX86_BUILTIN_STMXCSR:
24723 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24724 emit_insn (gen_sse_stmxcsr (target));
24725 return copy_to_mode_reg (SImode, target);
24727 case IX86_BUILTIN_CLFLUSH:
24728 arg0 = CALL_EXPR_ARG (exp, 0);
24729 op0 = expand_normal (arg0);
24730 icode = CODE_FOR_sse2_clflush;
24731 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24732 op0 = copy_to_mode_reg (Pmode, op0);
24734 emit_insn (gen_sse2_clflush (op0));
24737 case IX86_BUILTIN_MONITOR:
24738 arg0 = CALL_EXPR_ARG (exp, 0);
24739 arg1 = CALL_EXPR_ARG (exp, 1);
24740 arg2 = CALL_EXPR_ARG (exp, 2);
24741 op0 = expand_normal (arg0);
24742 op1 = expand_normal (arg1);
24743 op2 = expand_normal (arg2);
24745 op0 = copy_to_mode_reg (Pmode, op0);
24747 op1 = copy_to_mode_reg (SImode, op1);
24749 op2 = copy_to_mode_reg (SImode, op2);
24750 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24753 case IX86_BUILTIN_MWAIT:
24754 arg0 = CALL_EXPR_ARG (exp, 0);
24755 arg1 = CALL_EXPR_ARG (exp, 1);
24756 op0 = expand_normal (arg0);
24757 op1 = expand_normal (arg1);
24759 op0 = copy_to_mode_reg (SImode, op0);
24761 op1 = copy_to_mode_reg (SImode, op1);
24762 emit_insn (gen_sse3_mwait (op0, op1));
24765 case IX86_BUILTIN_VEC_INIT_V2SI:
24766 case IX86_BUILTIN_VEC_INIT_V4HI:
24767 case IX86_BUILTIN_VEC_INIT_V8QI:
24768 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24770 case IX86_BUILTIN_VEC_EXT_V2DF:
24771 case IX86_BUILTIN_VEC_EXT_V2DI:
24772 case IX86_BUILTIN_VEC_EXT_V4SF:
24773 case IX86_BUILTIN_VEC_EXT_V4SI:
24774 case IX86_BUILTIN_VEC_EXT_V8HI:
24775 case IX86_BUILTIN_VEC_EXT_V2SI:
24776 case IX86_BUILTIN_VEC_EXT_V4HI:
24777 case IX86_BUILTIN_VEC_EXT_V16QI:
24778 return ix86_expand_vec_ext_builtin (exp, target);
24780 case IX86_BUILTIN_VEC_SET_V2DI:
24781 case IX86_BUILTIN_VEC_SET_V4SF:
24782 case IX86_BUILTIN_VEC_SET_V4SI:
24783 case IX86_BUILTIN_VEC_SET_V8HI:
24784 case IX86_BUILTIN_VEC_SET_V4HI:
24785 case IX86_BUILTIN_VEC_SET_V16QI:
24786 return ix86_expand_vec_set_builtin (exp);
24788 case IX86_BUILTIN_INFQ:
24790 REAL_VALUE_TYPE inf;
24794 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24796 tmp = validize_mem (force_const_mem (mode, tmp));
24799 target = gen_reg_rtx (mode);
24801 emit_move_insn (target, tmp);
24809 for (i = 0, d = bdesc_special_args;
24810 i < ARRAY_SIZE (bdesc_special_args);
24812 if (d->code == fcode)
24813 return ix86_expand_special_args_builtin (d, exp, target);
24815 for (i = 0, d = bdesc_args;
24816 i < ARRAY_SIZE (bdesc_args);
24818 if (d->code == fcode)
24821 case IX86_BUILTIN_FABSQ:
24822 case IX86_BUILTIN_COPYSIGNQ:
24824 /* Emit a normal call if SSE2 isn't available. */
24825 return expand_call (exp, target, ignore);
24827 return ix86_expand_args_builtin (d, exp, target);
24830 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24831 if (d->code == fcode)
24832 return ix86_expand_sse_comi (d, exp, target);
24834 for (i = 0, d = bdesc_pcmpestr;
24835 i < ARRAY_SIZE (bdesc_pcmpestr);
24837 if (d->code == fcode)
24838 return ix86_expand_sse_pcmpestr (d, exp, target);
24840 for (i = 0, d = bdesc_pcmpistr;
24841 i < ARRAY_SIZE (bdesc_pcmpistr);
24843 if (d->code == fcode)
24844 return ix86_expand_sse_pcmpistr (d, exp, target);
24846 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24847 if (d->code == fcode)
24848 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24849 (enum multi_arg_type)d->flag,
24852 gcc_unreachable ();
24855 /* Returns a function decl for a vectorized version of the builtin function
24856 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24857 if it is not available. */
24860 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24863 enum machine_mode in_mode, out_mode;
24866 if (TREE_CODE (type_out) != VECTOR_TYPE
24867 || TREE_CODE (type_in) != VECTOR_TYPE)
24870 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24871 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24872 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24873 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24877 case BUILT_IN_SQRT:
24878 if (out_mode == DFmode && out_n == 2
24879 && in_mode == DFmode && in_n == 2)
24880 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24883 case BUILT_IN_SQRTF:
24884 if (out_mode == SFmode && out_n == 4
24885 && in_mode == SFmode && in_n == 4)
24886 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24889 case BUILT_IN_LRINT:
24890 if (out_mode == SImode && out_n == 4
24891 && in_mode == DFmode && in_n == 2)
24892 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24895 case BUILT_IN_LRINTF:
24896 if (out_mode == SImode && out_n == 4
24897 && in_mode == SFmode && in_n == 4)
24898 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24905 /* Dispatch to a handler for a vectorization library. */
24906 if (ix86_veclib_handler)
24907 return (*ix86_veclib_handler)(fn, type_out, type_in);
24912 /* Handler for an SVML-style interface to
24913 a library with vectorized intrinsics. */
24916 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24919 tree fntype, new_fndecl, args;
24922 enum machine_mode el_mode, in_mode;
24925 /* The SVML is suitable for unsafe math only. */
24926 if (!flag_unsafe_math_optimizations)
24929 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24930 n = TYPE_VECTOR_SUBPARTS (type_out);
24931 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24932 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24933 if (el_mode != in_mode
24941 case BUILT_IN_LOG10:
24943 case BUILT_IN_TANH:
24945 case BUILT_IN_ATAN:
24946 case BUILT_IN_ATAN2:
24947 case BUILT_IN_ATANH:
24948 case BUILT_IN_CBRT:
24949 case BUILT_IN_SINH:
24951 case BUILT_IN_ASINH:
24952 case BUILT_IN_ASIN:
24953 case BUILT_IN_COSH:
24955 case BUILT_IN_ACOSH:
24956 case BUILT_IN_ACOS:
24957 if (el_mode != DFmode || n != 2)
24961 case BUILT_IN_EXPF:
24962 case BUILT_IN_LOGF:
24963 case BUILT_IN_LOG10F:
24964 case BUILT_IN_POWF:
24965 case BUILT_IN_TANHF:
24966 case BUILT_IN_TANF:
24967 case BUILT_IN_ATANF:
24968 case BUILT_IN_ATAN2F:
24969 case BUILT_IN_ATANHF:
24970 case BUILT_IN_CBRTF:
24971 case BUILT_IN_SINHF:
24972 case BUILT_IN_SINF:
24973 case BUILT_IN_ASINHF:
24974 case BUILT_IN_ASINF:
24975 case BUILT_IN_COSHF:
24976 case BUILT_IN_COSF:
24977 case BUILT_IN_ACOSHF:
24978 case BUILT_IN_ACOSF:
24979 if (el_mode != SFmode || n != 4)
24987 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24989 if (fn == BUILT_IN_LOGF)
24990 strcpy (name, "vmlsLn4");
24991 else if (fn == BUILT_IN_LOG)
24992 strcpy (name, "vmldLn2");
24995 sprintf (name, "vmls%s", bname+10);
24996 name[strlen (name)-1] = '4';
24999 sprintf (name, "vmld%s2", bname+10);
25001 /* Convert to uppercase. */
25005 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25006 args = TREE_CHAIN (args))
25010 fntype = build_function_type_list (type_out, type_in, NULL);
25012 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25014 /* Build a function declaration for the vectorized function. */
25015 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25016 TREE_PUBLIC (new_fndecl) = 1;
25017 DECL_EXTERNAL (new_fndecl) = 1;
25018 DECL_IS_NOVOPS (new_fndecl) = 1;
25019 TREE_READONLY (new_fndecl) = 1;
25024 /* Handler for an ACML-style interface to
25025 a library with vectorized intrinsics. */
25028 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25030 char name[20] = "__vr.._";
25031 tree fntype, new_fndecl, args;
25034 enum machine_mode el_mode, in_mode;
25037 /* The ACML is 64bits only and suitable for unsafe math only as
25038 it does not correctly support parts of IEEE with the required
25039 precision such as denormals. */
25041 || !flag_unsafe_math_optimizations)
25044 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25045 n = TYPE_VECTOR_SUBPARTS (type_out);
25046 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25047 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25048 if (el_mode != in_mode
25058 case BUILT_IN_LOG2:
25059 case BUILT_IN_LOG10:
25062 if (el_mode != DFmode
25067 case BUILT_IN_SINF:
25068 case BUILT_IN_COSF:
25069 case BUILT_IN_EXPF:
25070 case BUILT_IN_POWF:
25071 case BUILT_IN_LOGF:
25072 case BUILT_IN_LOG2F:
25073 case BUILT_IN_LOG10F:
25076 if (el_mode != SFmode
25085 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25086 sprintf (name + 7, "%s", bname+10);
25089 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25090 args = TREE_CHAIN (args))
25094 fntype = build_function_type_list (type_out, type_in, NULL);
25096 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25098 /* Build a function declaration for the vectorized function. */
25099 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25100 TREE_PUBLIC (new_fndecl) = 1;
25101 DECL_EXTERNAL (new_fndecl) = 1;
25102 DECL_IS_NOVOPS (new_fndecl) = 1;
25103 TREE_READONLY (new_fndecl) = 1;
25109 /* Returns a decl of a function that implements conversion of an integer vector
25110 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25111 side of the conversion.
25112 Return NULL_TREE if it is not available. */
25115 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25117 if (TREE_CODE (type) != VECTOR_TYPE)
25123 switch (TYPE_MODE (type))
25126 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25131 case FIX_TRUNC_EXPR:
25132 switch (TYPE_MODE (type))
25135 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25145 /* Returns a code for a target-specific builtin that implements
25146 reciprocal of the function, or NULL_TREE if not available. */
25149 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25150 bool sqrt ATTRIBUTE_UNUSED)
25152 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25153 && flag_finite_math_only && !flag_trapping_math
25154 && flag_unsafe_math_optimizations))
25158 /* Machine dependent builtins. */
25161 /* Vectorized version of sqrt to rsqrt conversion. */
25162 case IX86_BUILTIN_SQRTPS_NR:
25163 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25169 /* Normal builtins. */
25172 /* Sqrt to rsqrt conversion. */
25173 case BUILT_IN_SQRTF:
25174 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25181 /* Store OPERAND to the memory after reload is completed. This means
25182 that we can't easily use assign_stack_local. */
25184 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25188 gcc_assert (reload_completed);
25189 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25191 result = gen_rtx_MEM (mode,
25192 gen_rtx_PLUS (Pmode,
25194 GEN_INT (-RED_ZONE_SIZE)));
25195 emit_move_insn (result, operand);
25197 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25203 operand = gen_lowpart (DImode, operand);
25207 gen_rtx_SET (VOIDmode,
25208 gen_rtx_MEM (DImode,
25209 gen_rtx_PRE_DEC (DImode,
25210 stack_pointer_rtx)),
25214 gcc_unreachable ();
25216 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25225 split_di (&operand, 1, operands, operands + 1);
25227 gen_rtx_SET (VOIDmode,
25228 gen_rtx_MEM (SImode,
25229 gen_rtx_PRE_DEC (Pmode,
25230 stack_pointer_rtx)),
25233 gen_rtx_SET (VOIDmode,
25234 gen_rtx_MEM (SImode,
25235 gen_rtx_PRE_DEC (Pmode,
25236 stack_pointer_rtx)),
25241 /* Store HImodes as SImodes. */
25242 operand = gen_lowpart (SImode, operand);
25246 gen_rtx_SET (VOIDmode,
25247 gen_rtx_MEM (GET_MODE (operand),
25248 gen_rtx_PRE_DEC (SImode,
25249 stack_pointer_rtx)),
25253 gcc_unreachable ();
25255 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25260 /* Free operand from the memory. */
25262 ix86_free_from_memory (enum machine_mode mode)
25264 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25268 if (mode == DImode || TARGET_64BIT)
25272 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25273 to pop or add instruction if registers are available. */
25274 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25275 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25280 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25281 QImode must go into class Q_REGS.
25282 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25283 movdf to do mem-to-mem moves through integer regs. */
25285 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25287 enum machine_mode mode = GET_MODE (x);
25289 /* We're only allowed to return a subclass of CLASS. Many of the
25290 following checks fail for NO_REGS, so eliminate that early. */
25291 if (regclass == NO_REGS)
25294 /* All classes can load zeros. */
25295 if (x == CONST0_RTX (mode))
25298 /* Force constants into memory if we are loading a (nonzero) constant into
25299 an MMX or SSE register. This is because there are no MMX/SSE instructions
25300 to load from a constant. */
25302 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25305 /* Prefer SSE regs only, if we can use them for math. */
25306 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25307 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25309 /* Floating-point constants need more complex checks. */
25310 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25312 /* General regs can load everything. */
25313 if (reg_class_subset_p (regclass, GENERAL_REGS))
25316 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25317 zero above. We only want to wind up preferring 80387 registers if
25318 we plan on doing computation with them. */
25320 && standard_80387_constant_p (x))
25322 /* Limit class to non-sse. */
25323 if (regclass == FLOAT_SSE_REGS)
25325 if (regclass == FP_TOP_SSE_REGS)
25327 if (regclass == FP_SECOND_SSE_REGS)
25328 return FP_SECOND_REG;
25329 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25336 /* Generally when we see PLUS here, it's the function invariant
25337 (plus soft-fp const_int). Which can only be computed into general
25339 if (GET_CODE (x) == PLUS)
25340 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25342 /* QImode constants are easy to load, but non-constant QImode data
25343 must go into Q_REGS. */
25344 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25346 if (reg_class_subset_p (regclass, Q_REGS))
25348 if (reg_class_subset_p (Q_REGS, regclass))
25356 /* Discourage putting floating-point values in SSE registers unless
25357 SSE math is being used, and likewise for the 387 registers. */
25359 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25361 enum machine_mode mode = GET_MODE (x);
25363 /* Restrict the output reload class to the register bank that we are doing
25364 math on. If we would like not to return a subset of CLASS, reject this
25365 alternative: if reload cannot do this, it will still use its choice. */
25366 mode = GET_MODE (x);
25367 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25368 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25370 if (X87_FLOAT_MODE_P (mode))
25372 if (regclass == FP_TOP_SSE_REGS)
25374 else if (regclass == FP_SECOND_SSE_REGS)
25375 return FP_SECOND_REG;
25377 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25383 static enum reg_class
25384 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25385 enum machine_mode mode,
25386 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25388 /* QImode spills from non-QI registers require
25389 intermediate register on 32bit targets. */
25390 if (!in_p && mode == QImode && !TARGET_64BIT
25391 && (rclass == GENERAL_REGS
25392 || rclass == LEGACY_REGS
25393 || rclass == INDEX_REGS))
25402 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25403 regno = true_regnum (x);
25405 /* Return Q_REGS if the operand is in memory. */
25413 /* If we are copying between general and FP registers, we need a memory
25414 location. The same is true for SSE and MMX registers.
25416 To optimize register_move_cost performance, allow inline variant.
25418 The macro can't work reliably when one of the CLASSES is class containing
25419 registers from multiple units (SSE, MMX, integer). We avoid this by never
25420 combining those units in single alternative in the machine description.
25421 Ensure that this constraint holds to avoid unexpected surprises.
25423 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25424 enforce these sanity checks. */
25427 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25428 enum machine_mode mode, int strict)
25430 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25431 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25432 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25433 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25434 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25435 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25437 gcc_assert (!strict);
25441 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25444 /* ??? This is a lie. We do have moves between mmx/general, and for
25445 mmx/sse2. But by saying we need secondary memory we discourage the
25446 register allocator from using the mmx registers unless needed. */
25447 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25450 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25452 /* SSE1 doesn't have any direct moves from other classes. */
25456 /* If the target says that inter-unit moves are more expensive
25457 than moving through memory, then don't generate them. */
25458 if (!TARGET_INTER_UNIT_MOVES)
25461 /* Between SSE and general, we have moves no larger than word size. */
25462 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25470 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25471 enum machine_mode mode, int strict)
25473 return inline_secondary_memory_needed (class1, class2, mode, strict);
25476 /* Return true if the registers in CLASS cannot represent the change from
25477 modes FROM to TO. */
25480 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25481 enum reg_class regclass)
25486 /* x87 registers can't do subreg at all, as all values are reformatted
25487 to extended precision. */
25488 if (MAYBE_FLOAT_CLASS_P (regclass))
25491 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25493 /* Vector registers do not support QI or HImode loads. If we don't
25494 disallow a change to these modes, reload will assume it's ok to
25495 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25496 the vec_dupv4hi pattern. */
25497 if (GET_MODE_SIZE (from) < 4)
25500 /* Vector registers do not support subreg with nonzero offsets, which
25501 are otherwise valid for integer registers. Since we can't see
25502 whether we have a nonzero offset from here, prohibit all
25503 nonparadoxical subregs changing size. */
25504 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25511 /* Return the cost of moving data of mode M between a
25512 register and memory. A value of 2 is the default; this cost is
25513 relative to those in `REGISTER_MOVE_COST'.
25515 This function is used extensively by register_move_cost that is used to
25516 build tables at startup. Make it inline in this case.
25517 When IN is 2, return maximum of in and out move cost.
25519 If moving between registers and memory is more expensive than
25520 between two registers, you should define this macro to express the
25523 Model also increased moving costs of QImode registers in non
25527 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25531 if (FLOAT_CLASS_P (regclass))
25549 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25550 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25552 if (SSE_CLASS_P (regclass))
25555 switch (GET_MODE_SIZE (mode))
25570 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25571 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25573 if (MMX_CLASS_P (regclass))
25576 switch (GET_MODE_SIZE (mode))
25588 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25589 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25591 switch (GET_MODE_SIZE (mode))
25594 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25597 return ix86_cost->int_store[0];
25598 if (TARGET_PARTIAL_REG_DEPENDENCY
25599 && optimize_function_for_speed_p (cfun))
25600 cost = ix86_cost->movzbl_load;
25602 cost = ix86_cost->int_load[0];
25604 return MAX (cost, ix86_cost->int_store[0]);
25610 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25612 return ix86_cost->movzbl_load;
25614 return ix86_cost->int_store[0] + 4;
25619 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25620 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25622 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25623 if (mode == TFmode)
25626 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25628 cost = ix86_cost->int_load[2];
25630 cost = ix86_cost->int_store[2];
25631 return (cost * (((int) GET_MODE_SIZE (mode)
25632 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25637 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25639 return inline_memory_move_cost (mode, regclass, in);
25643 /* Return the cost of moving data from a register in class CLASS1 to
25644 one in class CLASS2.
25646 It is not required that the cost always equal 2 when FROM is the same as TO;
25647 on some machines it is expensive to move between registers if they are not
25648 general registers. */
25651 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25652 enum reg_class class2)
25654 /* In case we require secondary memory, compute cost of the store followed
25655 by load. In order to avoid bad register allocation choices, we need
25656 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25658 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25662 cost += inline_memory_move_cost (mode, class1, 2);
25663 cost += inline_memory_move_cost (mode, class2, 2);
25665 /* In case of copying from general_purpose_register we may emit multiple
25666 stores followed by single load causing memory size mismatch stall.
25667 Count this as arbitrarily high cost of 20. */
25668 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25671 /* In the case of FP/MMX moves, the registers actually overlap, and we
25672 have to switch modes in order to treat them differently. */
25673 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25674 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25680 /* Moves between SSE/MMX and integer unit are expensive. */
25681 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25682 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25684 /* ??? By keeping returned value relatively high, we limit the number
25685 of moves between integer and MMX/SSE registers for all targets.
25686 Additionally, high value prevents problem with x86_modes_tieable_p(),
25687 where integer modes in MMX/SSE registers are not tieable
25688 because of missing QImode and HImode moves to, from or between
25689 MMX/SSE registers. */
25690 return MAX (8, ix86_cost->mmxsse_to_integer);
25692 if (MAYBE_FLOAT_CLASS_P (class1))
25693 return ix86_cost->fp_move;
25694 if (MAYBE_SSE_CLASS_P (class1))
25695 return ix86_cost->sse_move;
25696 if (MAYBE_MMX_CLASS_P (class1))
25697 return ix86_cost->mmx_move;
25701 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25704 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25706 /* Flags and only flags can only hold CCmode values. */
25707 if (CC_REGNO_P (regno))
25708 return GET_MODE_CLASS (mode) == MODE_CC;
25709 if (GET_MODE_CLASS (mode) == MODE_CC
25710 || GET_MODE_CLASS (mode) == MODE_RANDOM
25711 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25713 if (FP_REGNO_P (regno))
25714 return VALID_FP_MODE_P (mode);
25715 if (SSE_REGNO_P (regno))
25717 /* We implement the move patterns for all vector modes into and
25718 out of SSE registers, even when no operation instructions
25719 are available. OImode move is available only when AVX is
25721 return ((TARGET_AVX && mode == OImode)
25722 || VALID_AVX256_REG_MODE (mode)
25723 || VALID_SSE_REG_MODE (mode)
25724 || VALID_SSE2_REG_MODE (mode)
25725 || VALID_MMX_REG_MODE (mode)
25726 || VALID_MMX_REG_MODE_3DNOW (mode));
25728 if (MMX_REGNO_P (regno))
25730 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25731 so if the register is available at all, then we can move data of
25732 the given mode into or out of it. */
25733 return (VALID_MMX_REG_MODE (mode)
25734 || VALID_MMX_REG_MODE_3DNOW (mode));
25737 if (mode == QImode)
25739 /* Take care for QImode values - they can be in non-QI regs,
25740 but then they do cause partial register stalls. */
25741 if (regno < 4 || TARGET_64BIT)
25743 if (!TARGET_PARTIAL_REG_STALL)
25745 return reload_in_progress || reload_completed;
25747 /* We handle both integer and floats in the general purpose registers. */
25748 else if (VALID_INT_MODE_P (mode))
25750 else if (VALID_FP_MODE_P (mode))
25752 else if (VALID_DFP_MODE_P (mode))
25754 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25755 on to use that value in smaller contexts, this can easily force a
25756 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25757 supporting DImode, allow it. */
25758 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25764 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25765 tieable integer mode. */
25768 ix86_tieable_integer_mode_p (enum machine_mode mode)
25777 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25780 return TARGET_64BIT;
25787 /* Return true if MODE1 is accessible in a register that can hold MODE2
25788 without copying. That is, all register classes that can hold MODE2
25789 can also hold MODE1. */
25792 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25794 if (mode1 == mode2)
25797 if (ix86_tieable_integer_mode_p (mode1)
25798 && ix86_tieable_integer_mode_p (mode2))
25801 /* MODE2 being XFmode implies fp stack or general regs, which means we
25802 can tie any smaller floating point modes to it. Note that we do not
25803 tie this with TFmode. */
25804 if (mode2 == XFmode)
25805 return mode1 == SFmode || mode1 == DFmode;
25807 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25808 that we can tie it with SFmode. */
25809 if (mode2 == DFmode)
25810 return mode1 == SFmode;
25812 /* If MODE2 is only appropriate for an SSE register, then tie with
25813 any other mode acceptable to SSE registers. */
25814 if (GET_MODE_SIZE (mode2) == 16
25815 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25816 return (GET_MODE_SIZE (mode1) == 16
25817 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25819 /* If MODE2 is appropriate for an MMX register, then tie
25820 with any other mode acceptable to MMX registers. */
25821 if (GET_MODE_SIZE (mode2) == 8
25822 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25823 return (GET_MODE_SIZE (mode1) == 8
25824 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25829 /* Compute a (partial) cost for rtx X. Return true if the complete
25830 cost has been computed, and false if subexpressions should be
25831 scanned. In either case, *TOTAL contains the cost result. */
25834 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25836 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25837 enum machine_mode mode = GET_MODE (x);
25838 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25846 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25848 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25850 else if (flag_pic && SYMBOLIC_CONST (x)
25852 || (!GET_CODE (x) != LABEL_REF
25853 && (GET_CODE (x) != SYMBOL_REF
25854 || !SYMBOL_REF_LOCAL_P (x)))))
25861 if (mode == VOIDmode)
25864 switch (standard_80387_constant_p (x))
25869 default: /* Other constants */
25874 /* Start with (MEM (SYMBOL_REF)), since that's where
25875 it'll probably end up. Add a penalty for size. */
25876 *total = (COSTS_N_INSNS (1)
25877 + (flag_pic != 0 && !TARGET_64BIT)
25878 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25884 /* The zero extensions is often completely free on x86_64, so make
25885 it as cheap as possible. */
25886 if (TARGET_64BIT && mode == DImode
25887 && GET_MODE (XEXP (x, 0)) == SImode)
25889 else if (TARGET_ZERO_EXTEND_WITH_AND)
25890 *total = cost->add;
25892 *total = cost->movzx;
25896 *total = cost->movsx;
25900 if (CONST_INT_P (XEXP (x, 1))
25901 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25903 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25906 *total = cost->add;
25909 if ((value == 2 || value == 3)
25910 && cost->lea <= cost->shift_const)
25912 *total = cost->lea;
25922 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25924 if (CONST_INT_P (XEXP (x, 1)))
25926 if (INTVAL (XEXP (x, 1)) > 32)
25927 *total = cost->shift_const + COSTS_N_INSNS (2);
25929 *total = cost->shift_const * 2;
25933 if (GET_CODE (XEXP (x, 1)) == AND)
25934 *total = cost->shift_var * 2;
25936 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25941 if (CONST_INT_P (XEXP (x, 1)))
25942 *total = cost->shift_const;
25944 *total = cost->shift_var;
25949 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25951 /* ??? SSE scalar cost should be used here. */
25952 *total = cost->fmul;
25955 else if (X87_FLOAT_MODE_P (mode))
25957 *total = cost->fmul;
25960 else if (FLOAT_MODE_P (mode))
25962 /* ??? SSE vector cost should be used here. */
25963 *total = cost->fmul;
25968 rtx op0 = XEXP (x, 0);
25969 rtx op1 = XEXP (x, 1);
25971 if (CONST_INT_P (XEXP (x, 1)))
25973 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25974 for (nbits = 0; value != 0; value &= value - 1)
25978 /* This is arbitrary. */
25981 /* Compute costs correctly for widening multiplication. */
25982 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
25983 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
25984 == GET_MODE_SIZE (mode))
25986 int is_mulwiden = 0;
25987 enum machine_mode inner_mode = GET_MODE (op0);
25989 if (GET_CODE (op0) == GET_CODE (op1))
25990 is_mulwiden = 1, op1 = XEXP (op1, 0);
25991 else if (CONST_INT_P (op1))
25993 if (GET_CODE (op0) == SIGN_EXTEND)
25994 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
25997 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26001 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26004 *total = (cost->mult_init[MODE_INDEX (mode)]
26005 + nbits * cost->mult_bit
26006 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26015 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26016 /* ??? SSE cost should be used here. */
26017 *total = cost->fdiv;
26018 else if (X87_FLOAT_MODE_P (mode))
26019 *total = cost->fdiv;
26020 else if (FLOAT_MODE_P (mode))
26021 /* ??? SSE vector cost should be used here. */
26022 *total = cost->fdiv;
26024 *total = cost->divide[MODE_INDEX (mode)];
26028 if (GET_MODE_CLASS (mode) == MODE_INT
26029 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26031 if (GET_CODE (XEXP (x, 0)) == PLUS
26032 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26033 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26034 && CONSTANT_P (XEXP (x, 1)))
26036 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26037 if (val == 2 || val == 4 || val == 8)
26039 *total = cost->lea;
26040 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26041 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26042 outer_code, speed);
26043 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26047 else if (GET_CODE (XEXP (x, 0)) == MULT
26048 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26050 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26051 if (val == 2 || val == 4 || val == 8)
26053 *total = cost->lea;
26054 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26055 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26059 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26061 *total = cost->lea;
26062 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26063 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26064 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26071 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26073 /* ??? SSE cost should be used here. */
26074 *total = cost->fadd;
26077 else if (X87_FLOAT_MODE_P (mode))
26079 *total = cost->fadd;
26082 else if (FLOAT_MODE_P (mode))
26084 /* ??? SSE vector cost should be used here. */
26085 *total = cost->fadd;
26093 if (!TARGET_64BIT && mode == DImode)
26095 *total = (cost->add * 2
26096 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26097 << (GET_MODE (XEXP (x, 0)) != DImode))
26098 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26099 << (GET_MODE (XEXP (x, 1)) != DImode)));
26105 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26107 /* ??? SSE cost should be used here. */
26108 *total = cost->fchs;
26111 else if (X87_FLOAT_MODE_P (mode))
26113 *total = cost->fchs;
26116 else if (FLOAT_MODE_P (mode))
26118 /* ??? SSE vector cost should be used here. */
26119 *total = cost->fchs;
26125 if (!TARGET_64BIT && mode == DImode)
26126 *total = cost->add * 2;
26128 *total = cost->add;
26132 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26133 && XEXP (XEXP (x, 0), 1) == const1_rtx
26134 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26135 && XEXP (x, 1) == const0_rtx)
26137 /* This kind of construct is implemented using test[bwl].
26138 Treat it as if we had an AND. */
26139 *total = (cost->add
26140 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26141 + rtx_cost (const1_rtx, outer_code, speed));
26147 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26152 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26153 /* ??? SSE cost should be used here. */
26154 *total = cost->fabs;
26155 else if (X87_FLOAT_MODE_P (mode))
26156 *total = cost->fabs;
26157 else if (FLOAT_MODE_P (mode))
26158 /* ??? SSE vector cost should be used here. */
26159 *total = cost->fabs;
26163 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26164 /* ??? SSE cost should be used here. */
26165 *total = cost->fsqrt;
26166 else if (X87_FLOAT_MODE_P (mode))
26167 *total = cost->fsqrt;
26168 else if (FLOAT_MODE_P (mode))
26169 /* ??? SSE vector cost should be used here. */
26170 *total = cost->fsqrt;
26174 if (XINT (x, 1) == UNSPEC_TP)
26185 static int current_machopic_label_num;
26187 /* Given a symbol name and its associated stub, write out the
26188 definition of the stub. */
26191 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26193 unsigned int length;
26194 char *binder_name, *symbol_name, lazy_ptr_name[32];
26195 int label = ++current_machopic_label_num;
26197 /* For 64-bit we shouldn't get here. */
26198 gcc_assert (!TARGET_64BIT);
26200 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26201 symb = (*targetm.strip_name_encoding) (symb);
26203 length = strlen (stub);
26204 binder_name = XALLOCAVEC (char, length + 32);
26205 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26207 length = strlen (symb);
26208 symbol_name = XALLOCAVEC (char, length + 32);
26209 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26211 sprintf (lazy_ptr_name, "L%d$lz", label);
26214 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26216 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26218 fprintf (file, "%s:\n", stub);
26219 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26223 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26224 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26225 fprintf (file, "\tjmp\t*%%edx\n");
26228 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26230 fprintf (file, "%s:\n", binder_name);
26234 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26235 fprintf (file, "\tpushl\t%%eax\n");
26238 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26240 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26242 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26243 fprintf (file, "%s:\n", lazy_ptr_name);
26244 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26245 fprintf (file, "\t.long %s\n", binder_name);
26249 darwin_x86_file_end (void)
26251 darwin_file_end ();
26254 #endif /* TARGET_MACHO */
26256 /* Order the registers for register allocator. */
26259 x86_order_regs_for_local_alloc (void)
26264 /* First allocate the local general purpose registers. */
26265 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26266 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26267 reg_alloc_order [pos++] = i;
26269 /* Global general purpose registers. */
26270 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26271 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26272 reg_alloc_order [pos++] = i;
26274 /* x87 registers come first in case we are doing FP math
26276 if (!TARGET_SSE_MATH)
26277 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26278 reg_alloc_order [pos++] = i;
26280 /* SSE registers. */
26281 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26282 reg_alloc_order [pos++] = i;
26283 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26284 reg_alloc_order [pos++] = i;
26286 /* x87 registers. */
26287 if (TARGET_SSE_MATH)
26288 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26289 reg_alloc_order [pos++] = i;
26291 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26292 reg_alloc_order [pos++] = i;
26294 /* Initialize the rest of array as we do not allocate some registers
26296 while (pos < FIRST_PSEUDO_REGISTER)
26297 reg_alloc_order [pos++] = 0;
26300 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26301 struct attribute_spec.handler. */
26303 ix86_handle_abi_attribute (tree *node, tree name,
26304 tree args ATTRIBUTE_UNUSED,
26305 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26307 if (TREE_CODE (*node) != FUNCTION_TYPE
26308 && TREE_CODE (*node) != METHOD_TYPE
26309 && TREE_CODE (*node) != FIELD_DECL
26310 && TREE_CODE (*node) != TYPE_DECL)
26312 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26313 IDENTIFIER_POINTER (name));
26314 *no_add_attrs = true;
26319 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26320 IDENTIFIER_POINTER (name));
26321 *no_add_attrs = true;
26325 /* Can combine regparm with all attributes but fastcall. */
26326 if (is_attribute_p ("ms_abi", name))
26328 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26330 error ("ms_abi and sysv_abi attributes are not compatible");
26335 else if (is_attribute_p ("sysv_abi", name))
26337 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26339 error ("ms_abi and sysv_abi attributes are not compatible");
26348 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26349 struct attribute_spec.handler. */
26351 ix86_handle_struct_attribute (tree *node, tree name,
26352 tree args ATTRIBUTE_UNUSED,
26353 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26356 if (DECL_P (*node))
26358 if (TREE_CODE (*node) == TYPE_DECL)
26359 type = &TREE_TYPE (*node);
26364 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26365 || TREE_CODE (*type) == UNION_TYPE)))
26367 warning (OPT_Wattributes, "%qs attribute ignored",
26368 IDENTIFIER_POINTER (name));
26369 *no_add_attrs = true;
26372 else if ((is_attribute_p ("ms_struct", name)
26373 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26374 || ((is_attribute_p ("gcc_struct", name)
26375 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26377 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26378 IDENTIFIER_POINTER (name));
26379 *no_add_attrs = true;
26386 ix86_ms_bitfield_layout_p (const_tree record_type)
26388 return (TARGET_MS_BITFIELD_LAYOUT &&
26389 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26390 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26393 /* Returns an expression indicating where the this parameter is
26394 located on entry to the FUNCTION. */
26397 x86_this_parameter (tree function)
26399 tree type = TREE_TYPE (function);
26400 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26405 const int *parm_regs;
26407 if (ix86_function_type_abi (type) == MS_ABI)
26408 parm_regs = x86_64_ms_abi_int_parameter_registers;
26410 parm_regs = x86_64_int_parameter_registers;
26411 return gen_rtx_REG (DImode, parm_regs[aggr]);
26414 nregs = ix86_function_regparm (type, function);
26416 if (nregs > 0 && !stdarg_p (type))
26420 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26421 regno = aggr ? DX_REG : CX_REG;
26429 return gen_rtx_MEM (SImode,
26430 plus_constant (stack_pointer_rtx, 4));
26433 return gen_rtx_REG (SImode, regno);
26436 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26439 /* Determine whether x86_output_mi_thunk can succeed. */
26442 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26443 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26444 HOST_WIDE_INT vcall_offset, const_tree function)
26446 /* 64-bit can handle anything. */
26450 /* For 32-bit, everything's fine if we have one free register. */
26451 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26454 /* Need a free register for vcall_offset. */
26458 /* Need a free register for GOT references. */
26459 if (flag_pic && !(*targetm.binds_local_p) (function))
26462 /* Otherwise ok. */
26466 /* Output the assembler code for a thunk function. THUNK_DECL is the
26467 declaration for the thunk function itself, FUNCTION is the decl for
26468 the target function. DELTA is an immediate constant offset to be
26469 added to THIS. If VCALL_OFFSET is nonzero, the word at
26470 *(*this + vcall_offset) should be added to THIS. */
26473 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26474 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26475 HOST_WIDE_INT vcall_offset, tree function)
26478 rtx this_param = x86_this_parameter (function);
26481 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26482 pull it in now and let DELTA benefit. */
26483 if (REG_P (this_param))
26484 this_reg = this_param;
26485 else if (vcall_offset)
26487 /* Put the this parameter into %eax. */
26488 xops[0] = this_param;
26489 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26490 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26493 this_reg = NULL_RTX;
26495 /* Adjust the this parameter by a fixed constant. */
26498 xops[0] = GEN_INT (delta);
26499 xops[1] = this_reg ? this_reg : this_param;
26502 if (!x86_64_general_operand (xops[0], DImode))
26504 tmp = gen_rtx_REG (DImode, R10_REG);
26506 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26508 xops[1] = this_param;
26510 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26513 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26516 /* Adjust the this parameter by a value stored in the vtable. */
26520 tmp = gen_rtx_REG (DImode, R10_REG);
26523 int tmp_regno = CX_REG;
26524 if (lookup_attribute ("fastcall",
26525 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26526 tmp_regno = AX_REG;
26527 tmp = gen_rtx_REG (SImode, tmp_regno);
26530 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26532 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26534 /* Adjust the this parameter. */
26535 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26536 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26538 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26539 xops[0] = GEN_INT (vcall_offset);
26541 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26542 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26544 xops[1] = this_reg;
26545 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26548 /* If necessary, drop THIS back to its stack slot. */
26549 if (this_reg && this_reg != this_param)
26551 xops[0] = this_reg;
26552 xops[1] = this_param;
26553 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26556 xops[0] = XEXP (DECL_RTL (function), 0);
26559 if (!flag_pic || (*targetm.binds_local_p) (function))
26560 output_asm_insn ("jmp\t%P0", xops);
26561 /* All thunks should be in the same object as their target,
26562 and thus binds_local_p should be true. */
26563 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26564 gcc_unreachable ();
26567 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26568 tmp = gen_rtx_CONST (Pmode, tmp);
26569 tmp = gen_rtx_MEM (QImode, tmp);
26571 output_asm_insn ("jmp\t%A0", xops);
26576 if (!flag_pic || (*targetm.binds_local_p) (function))
26577 output_asm_insn ("jmp\t%P0", xops);
26582 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26583 tmp = (gen_rtx_SYMBOL_REF
26585 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26586 tmp = gen_rtx_MEM (QImode, tmp);
26588 output_asm_insn ("jmp\t%0", xops);
26591 #endif /* TARGET_MACHO */
26593 tmp = gen_rtx_REG (SImode, CX_REG);
26594 output_set_got (tmp, NULL_RTX);
26597 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26598 output_asm_insn ("jmp\t{*}%1", xops);
26604 x86_file_start (void)
26606 default_file_start ();
26608 darwin_file_start ();
26610 if (X86_FILE_START_VERSION_DIRECTIVE)
26611 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26612 if (X86_FILE_START_FLTUSED)
26613 fputs ("\t.global\t__fltused\n", asm_out_file);
26614 if (ix86_asm_dialect == ASM_INTEL)
26615 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26619 x86_field_alignment (tree field, int computed)
26621 enum machine_mode mode;
26622 tree type = TREE_TYPE (field);
26624 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26626 mode = TYPE_MODE (strip_array_types (type));
26627 if (mode == DFmode || mode == DCmode
26628 || GET_MODE_CLASS (mode) == MODE_INT
26629 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26630 return MIN (32, computed);
26634 /* Output assembler code to FILE to increment profiler label # LABELNO
26635 for profiling a function entry. */
26637 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26641 #ifndef NO_PROFILE_COUNTERS
26642 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26645 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26646 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26648 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26652 #ifndef NO_PROFILE_COUNTERS
26653 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26654 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26656 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26660 #ifndef NO_PROFILE_COUNTERS
26661 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26662 PROFILE_COUNT_REGISTER);
26664 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26668 /* We don't have exact information about the insn sizes, but we may assume
26669 quite safely that we are informed about all 1 byte insns and memory
26670 address sizes. This is enough to eliminate unnecessary padding in
26674 min_insn_size (rtx insn)
26678 if (!INSN_P (insn) || !active_insn_p (insn))
26681 /* Discard alignments we've emit and jump instructions. */
26682 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26683 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26686 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26687 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26690 /* Important case - calls are always 5 bytes.
26691 It is common to have many calls in the row. */
26693 && symbolic_reference_mentioned_p (PATTERN (insn))
26694 && !SIBLING_CALL_P (insn))
26696 if (get_attr_length (insn) <= 1)
26699 /* For normal instructions we may rely on the sizes of addresses
26700 and the presence of symbol to require 4 bytes of encoding.
26701 This is not the case for jumps where references are PC relative. */
26702 if (!JUMP_P (insn))
26704 l = get_attr_length_address (insn);
26705 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26714 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26718 ix86_avoid_jump_misspredicts (void)
26720 rtx insn, start = get_insns ();
26721 int nbytes = 0, njumps = 0;
26724 /* Look for all minimal intervals of instructions containing 4 jumps.
26725 The intervals are bounded by START and INSN. NBYTES is the total
26726 size of instructions in the interval including INSN and not including
26727 START. When the NBYTES is smaller than 16 bytes, it is possible
26728 that the end of START and INSN ends up in the same 16byte page.
26730 The smallest offset in the page INSN can start is the case where START
26731 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26732 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26734 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26737 nbytes += min_insn_size (insn);
26739 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26740 INSN_UID (insn), min_insn_size (insn));
26742 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26743 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26751 start = NEXT_INSN (start);
26752 if ((JUMP_P (start)
26753 && GET_CODE (PATTERN (start)) != ADDR_VEC
26754 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26756 njumps--, isjump = 1;
26759 nbytes -= min_insn_size (start);
26761 gcc_assert (njumps >= 0);
26763 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26764 INSN_UID (start), INSN_UID (insn), nbytes);
26766 if (njumps == 3 && isjump && nbytes < 16)
26768 int padsize = 15 - nbytes + min_insn_size (insn);
26771 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26772 INSN_UID (insn), padsize);
26773 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26778 /* AMD Athlon works faster
26779 when RET is not destination of conditional jump or directly preceded
26780 by other jump instruction. We avoid the penalty by inserting NOP just
26781 before the RET instructions in such cases. */
26783 ix86_pad_returns (void)
26788 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26790 basic_block bb = e->src;
26791 rtx ret = BB_END (bb);
26793 bool replace = false;
26795 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26796 || optimize_bb_for_size_p (bb))
26798 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26799 if (active_insn_p (prev) || LABEL_P (prev))
26801 if (prev && LABEL_P (prev))
26806 FOR_EACH_EDGE (e, ei, bb->preds)
26807 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26808 && !(e->flags & EDGE_FALLTHRU))
26813 prev = prev_active_insn (ret);
26815 && ((JUMP_P (prev) && any_condjump_p (prev))
26818 /* Empty functions get branch mispredict even when the jump destination
26819 is not visible to us. */
26820 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26825 emit_insn_before (gen_return_internal_long (), ret);
26831 /* Implement machine specific optimizations. We implement padding of returns
26832 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26836 if (TARGET_PAD_RETURNS && optimize
26837 && optimize_function_for_speed_p (cfun))
26838 ix86_pad_returns ();
26839 if (TARGET_FOUR_JUMP_LIMIT && optimize
26840 && optimize_function_for_speed_p (cfun))
26841 ix86_avoid_jump_misspredicts ();
26844 /* Return nonzero when QImode register that must be represented via REX prefix
26847 x86_extended_QIreg_mentioned_p (rtx insn)
26850 extract_insn_cached (insn);
26851 for (i = 0; i < recog_data.n_operands; i++)
26852 if (REG_P (recog_data.operand[i])
26853 && REGNO (recog_data.operand[i]) >= 4)
26858 /* Return nonzero when P points to register encoded via REX prefix.
26859 Called via for_each_rtx. */
26861 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26863 unsigned int regno;
26866 regno = REGNO (*p);
26867 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26870 /* Return true when INSN mentions register that must be encoded using REX
26873 x86_extended_reg_mentioned_p (rtx insn)
26875 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26876 extended_reg_mentioned_1, NULL);
26879 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26880 optabs would emit if we didn't have TFmode patterns. */
26883 x86_emit_floatuns (rtx operands[2])
26885 rtx neglab, donelab, i0, i1, f0, in, out;
26886 enum machine_mode mode, inmode;
26888 inmode = GET_MODE (operands[1]);
26889 gcc_assert (inmode == SImode || inmode == DImode);
26892 in = force_reg (inmode, operands[1]);
26893 mode = GET_MODE (out);
26894 neglab = gen_label_rtx ();
26895 donelab = gen_label_rtx ();
26896 f0 = gen_reg_rtx (mode);
26898 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26900 expand_float (out, in, 0);
26902 emit_jump_insn (gen_jump (donelab));
26905 emit_label (neglab);
26907 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26909 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26911 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26913 expand_float (f0, i0, 0);
26915 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26917 emit_label (donelab);
26920 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26921 with all elements equal to VAR. Return true if successful. */
26924 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26925 rtx target, rtx val)
26927 enum machine_mode hmode, smode, wsmode, wvmode;
26942 val = force_reg (GET_MODE_INNER (mode), val);
26943 x = gen_rtx_VEC_DUPLICATE (mode, val);
26944 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26950 if (TARGET_SSE || TARGET_3DNOW_A)
26952 val = gen_lowpart (SImode, val);
26953 x = gen_rtx_TRUNCATE (HImode, val);
26954 x = gen_rtx_VEC_DUPLICATE (mode, x);
26955 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26977 /* Extend HImode to SImode using a paradoxical SUBREG. */
26978 tmp1 = gen_reg_rtx (SImode);
26979 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26980 /* Insert the SImode value as low element of V4SImode vector. */
26981 tmp2 = gen_reg_rtx (V4SImode);
26982 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26983 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26984 CONST0_RTX (V4SImode),
26986 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26987 /* Cast the V4SImode vector back to a V8HImode vector. */
26988 tmp1 = gen_reg_rtx (V8HImode);
26989 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
26990 /* Duplicate the low short through the whole low SImode word. */
26991 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
26992 /* Cast the V8HImode vector back to a V4SImode vector. */
26993 tmp2 = gen_reg_rtx (V4SImode);
26994 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26995 /* Replicate the low element of the V4SImode vector. */
26996 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26997 /* Cast the V2SImode back to V8HImode, and store in target. */
26998 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27009 /* Extend QImode to SImode using a paradoxical SUBREG. */
27010 tmp1 = gen_reg_rtx (SImode);
27011 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27012 /* Insert the SImode value as low element of V4SImode vector. */
27013 tmp2 = gen_reg_rtx (V4SImode);
27014 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27015 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27016 CONST0_RTX (V4SImode),
27018 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27019 /* Cast the V4SImode vector back to a V16QImode vector. */
27020 tmp1 = gen_reg_rtx (V16QImode);
27021 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27022 /* Duplicate the low byte through the whole low SImode word. */
27023 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27024 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27025 /* Cast the V16QImode vector back to a V4SImode vector. */
27026 tmp2 = gen_reg_rtx (V4SImode);
27027 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27028 /* Replicate the low element of the V4SImode vector. */
27029 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27030 /* Cast the V2SImode back to V16QImode, and store in target. */
27031 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27039 /* Replicate the value once into the next wider mode and recurse. */
27040 val = convert_modes (wsmode, smode, val, true);
27041 x = expand_simple_binop (wsmode, ASHIFT, val,
27042 GEN_INT (GET_MODE_BITSIZE (smode)),
27043 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27044 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27046 x = gen_reg_rtx (wvmode);
27047 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27048 gcc_unreachable ();
27049 emit_move_insn (target, gen_lowpart (mode, x));
27072 rtx tmp = gen_reg_rtx (hmode);
27073 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27074 emit_insn (gen_rtx_SET (VOIDmode, target,
27075 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27084 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27085 whose ONE_VAR element is VAR, and other elements are zero. Return true
27089 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27090 rtx target, rtx var, int one_var)
27092 enum machine_mode vsimode;
27095 bool use_vector_set = false;
27100 /* For SSE4.1, we normally use vector set. But if the second
27101 element is zero and inter-unit moves are OK, we use movq
27103 use_vector_set = (TARGET_64BIT
27105 && !(TARGET_INTER_UNIT_MOVES
27111 use_vector_set = TARGET_SSE4_1;
27114 use_vector_set = TARGET_SSE2;
27117 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27125 use_vector_set = TARGET_AVX;
27131 if (use_vector_set)
27133 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27134 var = force_reg (GET_MODE_INNER (mode), var);
27135 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27151 var = force_reg (GET_MODE_INNER (mode), var);
27152 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27153 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27158 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27159 new_target = gen_reg_rtx (mode);
27161 new_target = target;
27162 var = force_reg (GET_MODE_INNER (mode), var);
27163 x = gen_rtx_VEC_DUPLICATE (mode, var);
27164 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27165 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27168 /* We need to shuffle the value to the correct position, so
27169 create a new pseudo to store the intermediate result. */
27171 /* With SSE2, we can use the integer shuffle insns. */
27172 if (mode != V4SFmode && TARGET_SSE2)
27174 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27176 GEN_INT (one_var == 1 ? 0 : 1),
27177 GEN_INT (one_var == 2 ? 0 : 1),
27178 GEN_INT (one_var == 3 ? 0 : 1)));
27179 if (target != new_target)
27180 emit_move_insn (target, new_target);
27184 /* Otherwise convert the intermediate result to V4SFmode and
27185 use the SSE1 shuffle instructions. */
27186 if (mode != V4SFmode)
27188 tmp = gen_reg_rtx (V4SFmode);
27189 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27194 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27196 GEN_INT (one_var == 1 ? 0 : 1),
27197 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27198 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27200 if (mode != V4SFmode)
27201 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27202 else if (tmp != target)
27203 emit_move_insn (target, tmp);
27205 else if (target != new_target)
27206 emit_move_insn (target, new_target);
27211 vsimode = V4SImode;
27217 vsimode = V2SImode;
27223 /* Zero extend the variable element to SImode and recurse. */
27224 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27226 x = gen_reg_rtx (vsimode);
27227 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27229 gcc_unreachable ();
27231 emit_move_insn (target, gen_lowpart (mode, x));
27239 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27240 consisting of the values in VALS. It is known that all elements
27241 except ONE_VAR are constants. Return true if successful. */
27244 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27245 rtx target, rtx vals, int one_var)
27247 rtx var = XVECEXP (vals, 0, one_var);
27248 enum machine_mode wmode;
27251 const_vec = copy_rtx (vals);
27252 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27253 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27261 /* For the two element vectors, it's just as easy to use
27262 the general case. */
27286 /* There's no way to set one QImode entry easily. Combine
27287 the variable value with its adjacent constant value, and
27288 promote to an HImode set. */
27289 x = XVECEXP (vals, 0, one_var ^ 1);
27292 var = convert_modes (HImode, QImode, var, true);
27293 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27294 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27295 x = GEN_INT (INTVAL (x) & 0xff);
27299 var = convert_modes (HImode, QImode, var, true);
27300 x = gen_int_mode (INTVAL (x) << 8, HImode);
27302 if (x != const0_rtx)
27303 var = expand_simple_binop (HImode, IOR, var, x, var,
27304 1, OPTAB_LIB_WIDEN);
27306 x = gen_reg_rtx (wmode);
27307 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27308 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27310 emit_move_insn (target, gen_lowpart (mode, x));
27317 emit_move_insn (target, const_vec);
27318 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27322 /* A subroutine of ix86_expand_vector_init_general. Use vector
27323 concatenate to handle the most general case: all values variable,
27324 and none identical. */
27327 ix86_expand_vector_init_concat (enum machine_mode mode,
27328 rtx target, rtx *ops, int n)
27330 enum machine_mode cmode, hmode = VOIDmode;
27331 rtx first[8], second[4];
27371 gcc_unreachable ();
27374 if (!register_operand (ops[1], cmode))
27375 ops[1] = force_reg (cmode, ops[1]);
27376 if (!register_operand (ops[0], cmode))
27377 ops[0] = force_reg (cmode, ops[0]);
27378 emit_insn (gen_rtx_SET (VOIDmode, target,
27379 gen_rtx_VEC_CONCAT (mode, ops[0],
27399 gcc_unreachable ();
27415 gcc_unreachable ();
27420 /* FIXME: We process inputs backward to help RA. PR 36222. */
27423 for (; i > 0; i -= 2, j--)
27425 first[j] = gen_reg_rtx (cmode);
27426 v = gen_rtvec (2, ops[i - 1], ops[i]);
27427 ix86_expand_vector_init (false, first[j],
27428 gen_rtx_PARALLEL (cmode, v));
27434 gcc_assert (hmode != VOIDmode);
27435 for (i = j = 0; i < n; i += 2, j++)
27437 second[j] = gen_reg_rtx (hmode);
27438 ix86_expand_vector_init_concat (hmode, second [j],
27442 ix86_expand_vector_init_concat (mode, target, second, n);
27445 ix86_expand_vector_init_concat (mode, target, first, n);
27449 gcc_unreachable ();
27453 /* A subroutine of ix86_expand_vector_init_general. Use vector
27454 interleave to handle the most general case: all values variable,
27455 and none identical. */
27458 ix86_expand_vector_init_interleave (enum machine_mode mode,
27459 rtx target, rtx *ops, int n)
27461 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27464 rtx (*gen_load_even) (rtx, rtx, rtx);
27465 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27466 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27471 gen_load_even = gen_vec_setv8hi;
27472 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27473 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27474 inner_mode = HImode;
27475 first_imode = V4SImode;
27476 second_imode = V2DImode;
27477 third_imode = VOIDmode;
27480 gen_load_even = gen_vec_setv16qi;
27481 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27482 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27483 inner_mode = QImode;
27484 first_imode = V8HImode;
27485 second_imode = V4SImode;
27486 third_imode = V2DImode;
27489 gcc_unreachable ();
27492 for (i = 0; i < n; i++)
27494 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27495 op0 = gen_reg_rtx (SImode);
27496 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27498 /* Insert the SImode value as low element of V4SImode vector. */
27499 op1 = gen_reg_rtx (V4SImode);
27500 op0 = gen_rtx_VEC_MERGE (V4SImode,
27501 gen_rtx_VEC_DUPLICATE (V4SImode,
27503 CONST0_RTX (V4SImode),
27505 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27507 /* Cast the V4SImode vector back to a vector in orignal mode. */
27508 op0 = gen_reg_rtx (mode);
27509 emit_move_insn (op0, gen_lowpart (mode, op1));
27511 /* Load even elements into the second positon. */
27512 emit_insn ((*gen_load_even) (op0,
27513 force_reg (inner_mode,
27517 /* Cast vector to FIRST_IMODE vector. */
27518 ops[i] = gen_reg_rtx (first_imode);
27519 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27522 /* Interleave low FIRST_IMODE vectors. */
27523 for (i = j = 0; i < n; i += 2, j++)
27525 op0 = gen_reg_rtx (first_imode);
27526 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27528 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27529 ops[j] = gen_reg_rtx (second_imode);
27530 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27533 /* Interleave low SECOND_IMODE vectors. */
27534 switch (second_imode)
27537 for (i = j = 0; i < n / 2; i += 2, j++)
27539 op0 = gen_reg_rtx (second_imode);
27540 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27543 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27545 ops[j] = gen_reg_rtx (third_imode);
27546 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27548 second_imode = V2DImode;
27549 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27553 op0 = gen_reg_rtx (second_imode);
27554 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27557 /* Cast the SECOND_IMODE vector back to a vector on original
27559 emit_insn (gen_rtx_SET (VOIDmode, target,
27560 gen_lowpart (mode, op0)));
27564 gcc_unreachable ();
27568 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27569 all values variable, and none identical. */
27572 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27573 rtx target, rtx vals)
27575 rtx ops[32], op0, op1;
27576 enum machine_mode half_mode = VOIDmode;
27583 if (!mmx_ok && !TARGET_SSE)
27595 n = GET_MODE_NUNITS (mode);
27596 for (i = 0; i < n; i++)
27597 ops[i] = XVECEXP (vals, 0, i);
27598 ix86_expand_vector_init_concat (mode, target, ops, n);
27602 half_mode = V16QImode;
27606 half_mode = V8HImode;
27610 n = GET_MODE_NUNITS (mode);
27611 for (i = 0; i < n; i++)
27612 ops[i] = XVECEXP (vals, 0, i);
27613 op0 = gen_reg_rtx (half_mode);
27614 op1 = gen_reg_rtx (half_mode);
27615 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27617 ix86_expand_vector_init_interleave (half_mode, op1,
27618 &ops [n >> 1], n >> 2);
27619 emit_insn (gen_rtx_SET (VOIDmode, target,
27620 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27624 if (!TARGET_SSE4_1)
27632 /* Don't use ix86_expand_vector_init_interleave if we can't
27633 move from GPR to SSE register directly. */
27634 if (!TARGET_INTER_UNIT_MOVES)
27637 n = GET_MODE_NUNITS (mode);
27638 for (i = 0; i < n; i++)
27639 ops[i] = XVECEXP (vals, 0, i);
27640 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27648 gcc_unreachable ();
27652 int i, j, n_elts, n_words, n_elt_per_word;
27653 enum machine_mode inner_mode;
27654 rtx words[4], shift;
27656 inner_mode = GET_MODE_INNER (mode);
27657 n_elts = GET_MODE_NUNITS (mode);
27658 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27659 n_elt_per_word = n_elts / n_words;
27660 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27662 for (i = 0; i < n_words; ++i)
27664 rtx word = NULL_RTX;
27666 for (j = 0; j < n_elt_per_word; ++j)
27668 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27669 elt = convert_modes (word_mode, inner_mode, elt, true);
27675 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27676 word, 1, OPTAB_LIB_WIDEN);
27677 word = expand_simple_binop (word_mode, IOR, word, elt,
27678 word, 1, OPTAB_LIB_WIDEN);
27686 emit_move_insn (target, gen_lowpart (mode, words[0]));
27687 else if (n_words == 2)
27689 rtx tmp = gen_reg_rtx (mode);
27690 emit_clobber (tmp);
27691 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27692 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27693 emit_move_insn (target, tmp);
27695 else if (n_words == 4)
27697 rtx tmp = gen_reg_rtx (V4SImode);
27698 gcc_assert (word_mode == SImode);
27699 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27700 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27701 emit_move_insn (target, gen_lowpart (mode, tmp));
27704 gcc_unreachable ();
27708 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27709 instructions unless MMX_OK is true. */
27712 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27714 enum machine_mode mode = GET_MODE (target);
27715 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27716 int n_elts = GET_MODE_NUNITS (mode);
27717 int n_var = 0, one_var = -1;
27718 bool all_same = true, all_const_zero = true;
27722 for (i = 0; i < n_elts; ++i)
27724 x = XVECEXP (vals, 0, i);
27725 if (!(CONST_INT_P (x)
27726 || GET_CODE (x) == CONST_DOUBLE
27727 || GET_CODE (x) == CONST_FIXED))
27728 n_var++, one_var = i;
27729 else if (x != CONST0_RTX (inner_mode))
27730 all_const_zero = false;
27731 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27735 /* Constants are best loaded from the constant pool. */
27738 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27742 /* If all values are identical, broadcast the value. */
27744 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27745 XVECEXP (vals, 0, 0)))
27748 /* Values where only one field is non-constant are best loaded from
27749 the pool and overwritten via move later. */
27753 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27754 XVECEXP (vals, 0, one_var),
27758 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27762 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27766 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27768 enum machine_mode mode = GET_MODE (target);
27769 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27770 enum machine_mode half_mode;
27771 bool use_vec_merge = false;
27773 static rtx (*gen_extract[6][2]) (rtx, rtx)
27775 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27776 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27777 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27778 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27779 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27780 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27782 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27784 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27785 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27786 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27787 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27788 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27789 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27799 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27800 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27802 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27804 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27805 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27811 use_vec_merge = TARGET_SSE4_1;
27819 /* For the two element vectors, we implement a VEC_CONCAT with
27820 the extraction of the other element. */
27822 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27823 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27826 op0 = val, op1 = tmp;
27828 op0 = tmp, op1 = val;
27830 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27831 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27836 use_vec_merge = TARGET_SSE4_1;
27843 use_vec_merge = true;
27847 /* tmp = target = A B C D */
27848 tmp = copy_to_reg (target);
27849 /* target = A A B B */
27850 emit_insn (gen_sse_unpcklps (target, target, target));
27851 /* target = X A B B */
27852 ix86_expand_vector_set (false, target, val, 0);
27853 /* target = A X C D */
27854 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27855 GEN_INT (1), GEN_INT (0),
27856 GEN_INT (2+4), GEN_INT (3+4)));
27860 /* tmp = target = A B C D */
27861 tmp = copy_to_reg (target);
27862 /* tmp = X B C D */
27863 ix86_expand_vector_set (false, tmp, val, 0);
27864 /* target = A B X D */
27865 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27866 GEN_INT (0), GEN_INT (1),
27867 GEN_INT (0+4), GEN_INT (3+4)));
27871 /* tmp = target = A B C D */
27872 tmp = copy_to_reg (target);
27873 /* tmp = X B C D */
27874 ix86_expand_vector_set (false, tmp, val, 0);
27875 /* target = A B X D */
27876 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27877 GEN_INT (0), GEN_INT (1),
27878 GEN_INT (2+4), GEN_INT (0+4)));
27882 gcc_unreachable ();
27887 use_vec_merge = TARGET_SSE4_1;
27891 /* Element 0 handled by vec_merge below. */
27894 use_vec_merge = true;
27900 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27901 store into element 0, then shuffle them back. */
27905 order[0] = GEN_INT (elt);
27906 order[1] = const1_rtx;
27907 order[2] = const2_rtx;
27908 order[3] = GEN_INT (3);
27909 order[elt] = const0_rtx;
27911 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27912 order[1], order[2], order[3]));
27914 ix86_expand_vector_set (false, target, val, 0);
27916 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27917 order[1], order[2], order[3]));
27921 /* For SSE1, we have to reuse the V4SF code. */
27922 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27923 gen_lowpart (SFmode, val), elt);
27928 use_vec_merge = TARGET_SSE2;
27931 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27935 use_vec_merge = TARGET_SSE4_1;
27942 half_mode = V16QImode;
27948 half_mode = V8HImode;
27954 half_mode = V4SImode;
27960 half_mode = V2DImode;
27966 half_mode = V4SFmode;
27972 half_mode = V2DFmode;
27978 /* Compute offset. */
27982 gcc_assert (i <= 1);
27984 /* Extract the half. */
27985 tmp = gen_reg_rtx (half_mode);
27986 emit_insn ((*gen_extract[j][i]) (tmp, target));
27988 /* Put val in tmp at elt. */
27989 ix86_expand_vector_set (false, tmp, val, elt);
27992 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28001 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28002 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28003 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28007 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28009 emit_move_insn (mem, target);
28011 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28012 emit_move_insn (tmp, val);
28014 emit_move_insn (target, mem);
28019 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28021 enum machine_mode mode = GET_MODE (vec);
28022 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28023 bool use_vec_extr = false;
28036 use_vec_extr = true;
28040 use_vec_extr = TARGET_SSE4_1;
28052 tmp = gen_reg_rtx (mode);
28053 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28054 GEN_INT (elt), GEN_INT (elt),
28055 GEN_INT (elt+4), GEN_INT (elt+4)));
28059 tmp = gen_reg_rtx (mode);
28060 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28064 gcc_unreachable ();
28067 use_vec_extr = true;
28072 use_vec_extr = TARGET_SSE4_1;
28086 tmp = gen_reg_rtx (mode);
28087 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28088 GEN_INT (elt), GEN_INT (elt),
28089 GEN_INT (elt), GEN_INT (elt)));
28093 tmp = gen_reg_rtx (mode);
28094 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28098 gcc_unreachable ();
28101 use_vec_extr = true;
28106 /* For SSE1, we have to reuse the V4SF code. */
28107 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28108 gen_lowpart (V4SFmode, vec), elt);
28114 use_vec_extr = TARGET_SSE2;
28117 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28121 use_vec_extr = TARGET_SSE4_1;
28125 /* ??? Could extract the appropriate HImode element and shift. */
28132 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28133 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28135 /* Let the rtl optimizers know about the zero extension performed. */
28136 if (inner_mode == QImode || inner_mode == HImode)
28138 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28139 target = gen_lowpart (SImode, target);
28142 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28146 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28148 emit_move_insn (mem, vec);
28150 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28151 emit_move_insn (target, tmp);
28155 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28156 pattern to reduce; DEST is the destination; IN is the input vector. */
28159 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28161 rtx tmp1, tmp2, tmp3;
28163 tmp1 = gen_reg_rtx (V4SFmode);
28164 tmp2 = gen_reg_rtx (V4SFmode);
28165 tmp3 = gen_reg_rtx (V4SFmode);
28167 emit_insn (gen_sse_movhlps (tmp1, in, in));
28168 emit_insn (fn (tmp2, tmp1, in));
28170 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28171 GEN_INT (1), GEN_INT (1),
28172 GEN_INT (1+4), GEN_INT (1+4)));
28173 emit_insn (fn (dest, tmp2, tmp3));
28176 /* Target hook for scalar_mode_supported_p. */
28178 ix86_scalar_mode_supported_p (enum machine_mode mode)
28180 if (DECIMAL_FLOAT_MODE_P (mode))
28182 else if (mode == TFmode)
28185 return default_scalar_mode_supported_p (mode);
28188 /* Implements target hook vector_mode_supported_p. */
28190 ix86_vector_mode_supported_p (enum machine_mode mode)
28192 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28194 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28196 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28198 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28200 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28205 /* Target hook for c_mode_for_suffix. */
28206 static enum machine_mode
28207 ix86_c_mode_for_suffix (char suffix)
28217 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28219 We do this in the new i386 backend to maintain source compatibility
28220 with the old cc0-based compiler. */
28223 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28224 tree inputs ATTRIBUTE_UNUSED,
28227 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28229 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28234 /* Implements target vector targetm.asm.encode_section_info. This
28235 is not used by netware. */
28237 static void ATTRIBUTE_UNUSED
28238 ix86_encode_section_info (tree decl, rtx rtl, int first)
28240 default_encode_section_info (decl, rtl, first);
28242 if (TREE_CODE (decl) == VAR_DECL
28243 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28244 && ix86_in_large_data_p (decl))
28245 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28248 /* Worker function for REVERSE_CONDITION. */
28251 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28253 return (mode != CCFPmode && mode != CCFPUmode
28254 ? reverse_condition (code)
28255 : reverse_condition_maybe_unordered (code));
28258 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28262 output_387_reg_move (rtx insn, rtx *operands)
28264 if (REG_P (operands[0]))
28266 if (REG_P (operands[1])
28267 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28269 if (REGNO (operands[0]) == FIRST_STACK_REG)
28270 return output_387_ffreep (operands, 0);
28271 return "fstp\t%y0";
28273 if (STACK_TOP_P (operands[0]))
28274 return "fld%z1\t%y1";
28277 else if (MEM_P (operands[0]))
28279 gcc_assert (REG_P (operands[1]));
28280 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28281 return "fstp%z0\t%y0";
28284 /* There is no non-popping store to memory for XFmode.
28285 So if we need one, follow the store with a load. */
28286 if (GET_MODE (operands[0]) == XFmode)
28287 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28289 return "fst%z0\t%y0";
28296 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28297 FP status register is set. */
28300 ix86_emit_fp_unordered_jump (rtx label)
28302 rtx reg = gen_reg_rtx (HImode);
28305 emit_insn (gen_x86_fnstsw_1 (reg));
28307 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28309 emit_insn (gen_x86_sahf_1 (reg));
28311 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28312 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28316 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28318 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28319 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28322 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28323 gen_rtx_LABEL_REF (VOIDmode, label),
28325 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28327 emit_jump_insn (temp);
28328 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28331 /* Output code to perform a log1p XFmode calculation. */
28333 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28335 rtx label1 = gen_label_rtx ();
28336 rtx label2 = gen_label_rtx ();
28338 rtx tmp = gen_reg_rtx (XFmode);
28339 rtx tmp2 = gen_reg_rtx (XFmode);
28341 emit_insn (gen_absxf2 (tmp, op1));
28342 emit_insn (gen_cmpxf (tmp,
28343 CONST_DOUBLE_FROM_REAL_VALUE (
28344 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28346 emit_jump_insn (gen_bge (label1));
28348 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28349 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28350 emit_jump (label2);
28352 emit_label (label1);
28353 emit_move_insn (tmp, CONST1_RTX (XFmode));
28354 emit_insn (gen_addxf3 (tmp, op1, tmp));
28355 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28356 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28358 emit_label (label2);
28361 /* Output code to perform a Newton-Rhapson approximation of a single precision
28362 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28364 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28366 rtx x0, x1, e0, e1, two;
28368 x0 = gen_reg_rtx (mode);
28369 e0 = gen_reg_rtx (mode);
28370 e1 = gen_reg_rtx (mode);
28371 x1 = gen_reg_rtx (mode);
28373 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28375 if (VECTOR_MODE_P (mode))
28376 two = ix86_build_const_vector (SFmode, true, two);
28378 two = force_reg (mode, two);
28380 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28382 /* x0 = rcp(b) estimate */
28383 emit_insn (gen_rtx_SET (VOIDmode, x0,
28384 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28387 emit_insn (gen_rtx_SET (VOIDmode, e0,
28388 gen_rtx_MULT (mode, x0, b)));
28390 emit_insn (gen_rtx_SET (VOIDmode, e1,
28391 gen_rtx_MINUS (mode, two, e0)));
28393 emit_insn (gen_rtx_SET (VOIDmode, x1,
28394 gen_rtx_MULT (mode, x0, e1)));
28396 emit_insn (gen_rtx_SET (VOIDmode, res,
28397 gen_rtx_MULT (mode, a, x1)));
28400 /* Output code to perform a Newton-Rhapson approximation of a
28401 single precision floating point [reciprocal] square root. */
28403 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28406 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28409 x0 = gen_reg_rtx (mode);
28410 e0 = gen_reg_rtx (mode);
28411 e1 = gen_reg_rtx (mode);
28412 e2 = gen_reg_rtx (mode);
28413 e3 = gen_reg_rtx (mode);
28415 real_from_integer (&r, VOIDmode, -3, -1, 0);
28416 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28418 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28419 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28421 if (VECTOR_MODE_P (mode))
28423 mthree = ix86_build_const_vector (SFmode, true, mthree);
28424 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28427 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28428 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28430 /* x0 = rsqrt(a) estimate */
28431 emit_insn (gen_rtx_SET (VOIDmode, x0,
28432 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28435 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28440 zero = gen_reg_rtx (mode);
28441 mask = gen_reg_rtx (mode);
28443 zero = force_reg (mode, CONST0_RTX(mode));
28444 emit_insn (gen_rtx_SET (VOIDmode, mask,
28445 gen_rtx_NE (mode, zero, a)));
28447 emit_insn (gen_rtx_SET (VOIDmode, x0,
28448 gen_rtx_AND (mode, x0, mask)));
28452 emit_insn (gen_rtx_SET (VOIDmode, e0,
28453 gen_rtx_MULT (mode, x0, a)));
28455 emit_insn (gen_rtx_SET (VOIDmode, e1,
28456 gen_rtx_MULT (mode, e0, x0)));
28459 mthree = force_reg (mode, mthree);
28460 emit_insn (gen_rtx_SET (VOIDmode, e2,
28461 gen_rtx_PLUS (mode, e1, mthree)));
28463 mhalf = force_reg (mode, mhalf);
28465 /* e3 = -.5 * x0 */
28466 emit_insn (gen_rtx_SET (VOIDmode, e3,
28467 gen_rtx_MULT (mode, x0, mhalf)));
28469 /* e3 = -.5 * e0 */
28470 emit_insn (gen_rtx_SET (VOIDmode, e3,
28471 gen_rtx_MULT (mode, e0, mhalf)));
28472 /* ret = e2 * e3 */
28473 emit_insn (gen_rtx_SET (VOIDmode, res,
28474 gen_rtx_MULT (mode, e2, e3)));
28477 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28479 static void ATTRIBUTE_UNUSED
28480 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28483 /* With Binutils 2.15, the "@unwind" marker must be specified on
28484 every occurrence of the ".eh_frame" section, not just the first
28487 && strcmp (name, ".eh_frame") == 0)
28489 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28490 flags & SECTION_WRITE ? "aw" : "a");
28493 default_elf_asm_named_section (name, flags, decl);
28496 /* Return the mangling of TYPE if it is an extended fundamental type. */
28498 static const char *
28499 ix86_mangle_type (const_tree type)
28501 type = TYPE_MAIN_VARIANT (type);
28503 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28504 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28507 switch (TYPE_MODE (type))
28510 /* __float128 is "g". */
28513 /* "long double" or __float80 is "e". */
28520 /* For 32-bit code we can save PIC register setup by using
28521 __stack_chk_fail_local hidden function instead of calling
28522 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28523 register, so it is better to call __stack_chk_fail directly. */
28526 ix86_stack_protect_fail (void)
28528 return TARGET_64BIT
28529 ? default_external_stack_protect_fail ()
28530 : default_hidden_stack_protect_fail ();
28533 /* Select a format to encode pointers in exception handling data. CODE
28534 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28535 true if the symbol may be affected by dynamic relocations.
28537 ??? All x86 object file formats are capable of representing this.
28538 After all, the relocation needed is the same as for the call insn.
28539 Whether or not a particular assembler allows us to enter such, I
28540 guess we'll have to see. */
28542 asm_preferred_eh_data_format (int code, int global)
28546 int type = DW_EH_PE_sdata8;
28548 || ix86_cmodel == CM_SMALL_PIC
28549 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28550 type = DW_EH_PE_sdata4;
28551 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28553 if (ix86_cmodel == CM_SMALL
28554 || (ix86_cmodel == CM_MEDIUM && code))
28555 return DW_EH_PE_udata4;
28556 return DW_EH_PE_absptr;
28559 /* Expand copysign from SIGN to the positive value ABS_VALUE
28560 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28563 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28565 enum machine_mode mode = GET_MODE (sign);
28566 rtx sgn = gen_reg_rtx (mode);
28567 if (mask == NULL_RTX)
28569 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28570 if (!VECTOR_MODE_P (mode))
28572 /* We need to generate a scalar mode mask in this case. */
28573 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28574 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28575 mask = gen_reg_rtx (mode);
28576 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28580 mask = gen_rtx_NOT (mode, mask);
28581 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28582 gen_rtx_AND (mode, mask, sign)));
28583 emit_insn (gen_rtx_SET (VOIDmode, result,
28584 gen_rtx_IOR (mode, abs_value, sgn)));
28587 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28588 mask for masking out the sign-bit is stored in *SMASK, if that is
28591 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28593 enum machine_mode mode = GET_MODE (op0);
28596 xa = gen_reg_rtx (mode);
28597 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28598 if (!VECTOR_MODE_P (mode))
28600 /* We need to generate a scalar mode mask in this case. */
28601 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28602 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28603 mask = gen_reg_rtx (mode);
28604 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28606 emit_insn (gen_rtx_SET (VOIDmode, xa,
28607 gen_rtx_AND (mode, op0, mask)));
28615 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28616 swapping the operands if SWAP_OPERANDS is true. The expanded
28617 code is a forward jump to a newly created label in case the
28618 comparison is true. The generated label rtx is returned. */
28620 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28621 bool swap_operands)
28632 label = gen_label_rtx ();
28633 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28634 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28635 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28636 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28637 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28638 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28639 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28640 JUMP_LABEL (tmp) = label;
28645 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28646 using comparison code CODE. Operands are swapped for the comparison if
28647 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28649 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28650 bool swap_operands)
28652 enum machine_mode mode = GET_MODE (op0);
28653 rtx mask = gen_reg_rtx (mode);
28662 if (mode == DFmode)
28663 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28664 gen_rtx_fmt_ee (code, mode, op0, op1)));
28666 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28667 gen_rtx_fmt_ee (code, mode, op0, op1)));
28672 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28673 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28675 ix86_gen_TWO52 (enum machine_mode mode)
28677 REAL_VALUE_TYPE TWO52r;
28680 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28681 TWO52 = const_double_from_real_value (TWO52r, mode);
28682 TWO52 = force_reg (mode, TWO52);
28687 /* Expand SSE sequence for computing lround from OP1 storing
28690 ix86_expand_lround (rtx op0, rtx op1)
28692 /* C code for the stuff we're doing below:
28693 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28696 enum machine_mode mode = GET_MODE (op1);
28697 const struct real_format *fmt;
28698 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28701 /* load nextafter (0.5, 0.0) */
28702 fmt = REAL_MODE_FORMAT (mode);
28703 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28704 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28706 /* adj = copysign (0.5, op1) */
28707 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28708 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28710 /* adj = op1 + adj */
28711 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28713 /* op0 = (imode)adj */
28714 expand_fix (op0, adj, 0);
28717 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28720 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28722 /* C code for the stuff we're doing below (for do_floor):
28724 xi -= (double)xi > op1 ? 1 : 0;
28727 enum machine_mode fmode = GET_MODE (op1);
28728 enum machine_mode imode = GET_MODE (op0);
28729 rtx ireg, freg, label, tmp;
28731 /* reg = (long)op1 */
28732 ireg = gen_reg_rtx (imode);
28733 expand_fix (ireg, op1, 0);
28735 /* freg = (double)reg */
28736 freg = gen_reg_rtx (fmode);
28737 expand_float (freg, ireg, 0);
28739 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28740 label = ix86_expand_sse_compare_and_jump (UNLE,
28741 freg, op1, !do_floor);
28742 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28743 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28744 emit_move_insn (ireg, tmp);
28746 emit_label (label);
28747 LABEL_NUSES (label) = 1;
28749 emit_move_insn (op0, ireg);
28752 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28753 result in OPERAND0. */
28755 ix86_expand_rint (rtx operand0, rtx operand1)
28757 /* C code for the stuff we're doing below:
28758 xa = fabs (operand1);
28759 if (!isless (xa, 2**52))
28761 xa = xa + 2**52 - 2**52;
28762 return copysign (xa, operand1);
28764 enum machine_mode mode = GET_MODE (operand0);
28765 rtx res, xa, label, TWO52, mask;
28767 res = gen_reg_rtx (mode);
28768 emit_move_insn (res, operand1);
28770 /* xa = abs (operand1) */
28771 xa = ix86_expand_sse_fabs (res, &mask);
28773 /* if (!isless (xa, TWO52)) goto label; */
28774 TWO52 = ix86_gen_TWO52 (mode);
28775 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28777 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28778 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28780 ix86_sse_copysign_to_positive (res, xa, res, mask);
28782 emit_label (label);
28783 LABEL_NUSES (label) = 1;
28785 emit_move_insn (operand0, res);
28788 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28791 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28793 /* C code for the stuff we expand below.
28794 double xa = fabs (x), x2;
28795 if (!isless (xa, TWO52))
28797 xa = xa + TWO52 - TWO52;
28798 x2 = copysign (xa, x);
28807 enum machine_mode mode = GET_MODE (operand0);
28808 rtx xa, TWO52, tmp, label, one, res, mask;
28810 TWO52 = ix86_gen_TWO52 (mode);
28812 /* Temporary for holding the result, initialized to the input
28813 operand to ease control flow. */
28814 res = gen_reg_rtx (mode);
28815 emit_move_insn (res, operand1);
28817 /* xa = abs (operand1) */
28818 xa = ix86_expand_sse_fabs (res, &mask);
28820 /* if (!isless (xa, TWO52)) goto label; */
28821 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28823 /* xa = xa + TWO52 - TWO52; */
28824 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28825 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28827 /* xa = copysign (xa, operand1) */
28828 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28830 /* generate 1.0 or -1.0 */
28831 one = force_reg (mode,
28832 const_double_from_real_value (do_floor
28833 ? dconst1 : dconstm1, mode));
28835 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28836 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28837 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28838 gen_rtx_AND (mode, one, tmp)));
28839 /* We always need to subtract here to preserve signed zero. */
28840 tmp = expand_simple_binop (mode, MINUS,
28841 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28842 emit_move_insn (res, tmp);
28844 emit_label (label);
28845 LABEL_NUSES (label) = 1;
28847 emit_move_insn (operand0, res);
28850 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28853 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28855 /* C code for the stuff we expand below.
28856 double xa = fabs (x), x2;
28857 if (!isless (xa, TWO52))
28859 x2 = (double)(long)x;
28866 if (HONOR_SIGNED_ZEROS (mode))
28867 return copysign (x2, x);
28870 enum machine_mode mode = GET_MODE (operand0);
28871 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28873 TWO52 = ix86_gen_TWO52 (mode);
28875 /* Temporary for holding the result, initialized to the input
28876 operand to ease control flow. */
28877 res = gen_reg_rtx (mode);
28878 emit_move_insn (res, operand1);
28880 /* xa = abs (operand1) */
28881 xa = ix86_expand_sse_fabs (res, &mask);
28883 /* if (!isless (xa, TWO52)) goto label; */
28884 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28886 /* xa = (double)(long)x */
28887 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28888 expand_fix (xi, res, 0);
28889 expand_float (xa, xi, 0);
28892 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28894 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28895 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28896 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28897 gen_rtx_AND (mode, one, tmp)));
28898 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28899 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28900 emit_move_insn (res, tmp);
28902 if (HONOR_SIGNED_ZEROS (mode))
28903 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28905 emit_label (label);
28906 LABEL_NUSES (label) = 1;
28908 emit_move_insn (operand0, res);
28911 /* Expand SSE sequence for computing round from OPERAND1 storing
28912 into OPERAND0. Sequence that works without relying on DImode truncation
28913 via cvttsd2siq that is only available on 64bit targets. */
28915 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28917 /* C code for the stuff we expand below.
28918 double xa = fabs (x), xa2, x2;
28919 if (!isless (xa, TWO52))
28921 Using the absolute value and copying back sign makes
28922 -0.0 -> -0.0 correct.
28923 xa2 = xa + TWO52 - TWO52;
28928 else if (dxa > 0.5)
28930 x2 = copysign (xa2, x);
28933 enum machine_mode mode = GET_MODE (operand0);
28934 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28936 TWO52 = ix86_gen_TWO52 (mode);
28938 /* Temporary for holding the result, initialized to the input
28939 operand to ease control flow. */
28940 res = gen_reg_rtx (mode);
28941 emit_move_insn (res, operand1);
28943 /* xa = abs (operand1) */
28944 xa = ix86_expand_sse_fabs (res, &mask);
28946 /* if (!isless (xa, TWO52)) goto label; */
28947 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28949 /* xa2 = xa + TWO52 - TWO52; */
28950 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28951 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
28953 /* dxa = xa2 - xa; */
28954 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
28956 /* generate 0.5, 1.0 and -0.5 */
28957 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
28958 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
28959 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
28963 tmp = gen_reg_rtx (mode);
28964 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28965 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
28966 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28967 gen_rtx_AND (mode, one, tmp)));
28968 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28969 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28970 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
28971 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28972 gen_rtx_AND (mode, one, tmp)));
28973 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28975 /* res = copysign (xa2, operand1) */
28976 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
28978 emit_label (label);
28979 LABEL_NUSES (label) = 1;
28981 emit_move_insn (operand0, res);
28984 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28987 ix86_expand_trunc (rtx operand0, rtx operand1)
28989 /* C code for SSE variant we expand below.
28990 double xa = fabs (x), x2;
28991 if (!isless (xa, TWO52))
28993 x2 = (double)(long)x;
28994 if (HONOR_SIGNED_ZEROS (mode))
28995 return copysign (x2, x);
28998 enum machine_mode mode = GET_MODE (operand0);
28999 rtx xa, xi, TWO52, label, res, mask;
29001 TWO52 = ix86_gen_TWO52 (mode);
29003 /* Temporary for holding the result, initialized to the input
29004 operand to ease control flow. */
29005 res = gen_reg_rtx (mode);
29006 emit_move_insn (res, operand1);
29008 /* xa = abs (operand1) */
29009 xa = ix86_expand_sse_fabs (res, &mask);
29011 /* if (!isless (xa, TWO52)) goto label; */
29012 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29014 /* x = (double)(long)x */
29015 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29016 expand_fix (xi, res, 0);
29017 expand_float (res, xi, 0);
29019 if (HONOR_SIGNED_ZEROS (mode))
29020 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29022 emit_label (label);
29023 LABEL_NUSES (label) = 1;
29025 emit_move_insn (operand0, res);
29028 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29031 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29033 enum machine_mode mode = GET_MODE (operand0);
29034 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29036 /* C code for SSE variant we expand below.
29037 double xa = fabs (x), x2;
29038 if (!isless (xa, TWO52))
29040 xa2 = xa + TWO52 - TWO52;
29044 x2 = copysign (xa2, x);
29048 TWO52 = ix86_gen_TWO52 (mode);
29050 /* Temporary for holding the result, initialized to the input
29051 operand to ease control flow. */
29052 res = gen_reg_rtx (mode);
29053 emit_move_insn (res, operand1);
29055 /* xa = abs (operand1) */
29056 xa = ix86_expand_sse_fabs (res, &smask);
29058 /* if (!isless (xa, TWO52)) goto label; */
29059 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29061 /* res = xa + TWO52 - TWO52; */
29062 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29063 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29064 emit_move_insn (res, tmp);
29067 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29069 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29070 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29071 emit_insn (gen_rtx_SET (VOIDmode, mask,
29072 gen_rtx_AND (mode, mask, one)));
29073 tmp = expand_simple_binop (mode, MINUS,
29074 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29075 emit_move_insn (res, tmp);
29077 /* res = copysign (res, operand1) */
29078 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29080 emit_label (label);
29081 LABEL_NUSES (label) = 1;
29083 emit_move_insn (operand0, res);
29086 /* Expand SSE sequence for computing round from OPERAND1 storing
29089 ix86_expand_round (rtx operand0, rtx operand1)
29091 /* C code for the stuff we're doing below:
29092 double xa = fabs (x);
29093 if (!isless (xa, TWO52))
29095 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29096 return copysign (xa, x);
29098 enum machine_mode mode = GET_MODE (operand0);
29099 rtx res, TWO52, xa, label, xi, half, mask;
29100 const struct real_format *fmt;
29101 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29103 /* Temporary for holding the result, initialized to the input
29104 operand to ease control flow. */
29105 res = gen_reg_rtx (mode);
29106 emit_move_insn (res, operand1);
29108 TWO52 = ix86_gen_TWO52 (mode);
29109 xa = ix86_expand_sse_fabs (res, &mask);
29110 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29112 /* load nextafter (0.5, 0.0) */
29113 fmt = REAL_MODE_FORMAT (mode);
29114 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29115 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29117 /* xa = xa + 0.5 */
29118 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29119 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29121 /* xa = (double)(int64_t)xa */
29122 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29123 expand_fix (xi, xa, 0);
29124 expand_float (xa, xi, 0);
29126 /* res = copysign (xa, operand1) */
29127 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29129 emit_label (label);
29130 LABEL_NUSES (label) = 1;
29132 emit_move_insn (operand0, res);
29136 /* Validate whether a SSE5 instruction is valid or not.
29137 OPERANDS is the array of operands.
29138 NUM is the number of operands.
29139 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29140 NUM_MEMORY is the maximum number of memory operands to accept.
29141 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29144 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29145 bool uses_oc0, int num_memory, bool commutative)
29151 /* Count the number of memory arguments */
29154 for (i = 0; i < num; i++)
29156 enum machine_mode mode = GET_MODE (operands[i]);
29157 if (register_operand (operands[i], mode))
29160 else if (memory_operand (operands[i], mode))
29162 mem_mask |= (1 << i);
29168 rtx pattern = PATTERN (insn);
29170 /* allow 0 for pcmov */
29171 if (GET_CODE (pattern) != SET
29172 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29174 || operands[i] != CONST0_RTX (mode))
29179 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29180 a memory operation. */
29181 if (num_memory < 0)
29183 num_memory = -num_memory;
29184 if ((mem_mask & (1 << (num-1))) != 0)
29186 mem_mask &= ~(1 << (num-1));
29191 /* If there were no memory operations, allow the insn */
29195 /* Do not allow the destination register to be a memory operand. */
29196 else if (mem_mask & (1 << 0))
29199 /* If there are too many memory operations, disallow the instruction. While
29200 the hardware only allows 1 memory reference, before register allocation
29201 for some insns, we allow two memory operations sometimes in order to allow
29202 code like the following to be optimized:
29204 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29206 or similar cases that are vectorized into using the fmaddss
29208 else if (mem_count > num_memory)
29211 /* Don't allow more than one memory operation if not optimizing. */
29212 else if (mem_count > 1 && !optimize)
29215 else if (num == 4 && mem_count == 1)
29217 /* formats (destination is the first argument), example fmaddss:
29218 xmm1, xmm1, xmm2, xmm3/mem
29219 xmm1, xmm1, xmm2/mem, xmm3
29220 xmm1, xmm2, xmm3/mem, xmm1
29221 xmm1, xmm2/mem, xmm3, xmm1 */
29223 return ((mem_mask == (1 << 1))
29224 || (mem_mask == (1 << 2))
29225 || (mem_mask == (1 << 3)));
29227 /* format, example pmacsdd:
29228 xmm1, xmm2, xmm3/mem, xmm1 */
29230 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29232 return (mem_mask == (1 << 2));
29235 else if (num == 4 && num_memory == 2)
29237 /* If there are two memory operations, we can load one of the memory ops
29238 into the destination register. This is for optimizing the
29239 multiply/add ops, which the combiner has optimized both the multiply
29240 and the add insns to have a memory operation. We have to be careful
29241 that the destination doesn't overlap with the inputs. */
29242 rtx op0 = operands[0];
29244 if (reg_mentioned_p (op0, operands[1])
29245 || reg_mentioned_p (op0, operands[2])
29246 || reg_mentioned_p (op0, operands[3]))
29249 /* formats (destination is the first argument), example fmaddss:
29250 xmm1, xmm1, xmm2, xmm3/mem
29251 xmm1, xmm1, xmm2/mem, xmm3
29252 xmm1, xmm2, xmm3/mem, xmm1
29253 xmm1, xmm2/mem, xmm3, xmm1
29255 For the oc0 case, we will load either operands[1] or operands[3] into
29256 operands[0], so any combination of 2 memory operands is ok. */
29260 /* format, example pmacsdd:
29261 xmm1, xmm2, xmm3/mem, xmm1
29263 For the integer multiply/add instructions be more restrictive and
29264 require operands[2] and operands[3] to be the memory operands. */
29266 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29268 return (mem_mask == ((1 << 2) | (1 << 3)));
29271 else if (num == 3 && num_memory == 1)
29273 /* formats, example protb:
29274 xmm1, xmm2, xmm3/mem
29275 xmm1, xmm2/mem, xmm3 */
29277 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29279 /* format, example comeq:
29280 xmm1, xmm2, xmm3/mem */
29282 return (mem_mask == (1 << 2));
29286 gcc_unreachable ();
29292 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29293 hardware will allow by using the destination register to load one of the
29294 memory operations. Presently this is used by the multiply/add routines to
29295 allow 2 memory references. */
29298 ix86_expand_sse5_multiple_memory (rtx operands[],
29300 enum machine_mode mode)
29302 rtx op0 = operands[0];
29304 || memory_operand (op0, mode)
29305 || reg_mentioned_p (op0, operands[1])
29306 || reg_mentioned_p (op0, operands[2])
29307 || reg_mentioned_p (op0, operands[3]))
29308 gcc_unreachable ();
29310 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29311 the destination register. */
29312 if (memory_operand (operands[1], mode))
29314 emit_move_insn (op0, operands[1]);
29317 else if (memory_operand (operands[3], mode))
29319 emit_move_insn (op0, operands[3]);
29323 gcc_unreachable ();
29329 /* Table of valid machine attributes. */
29330 static const struct attribute_spec ix86_attribute_table[] =
29332 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29333 /* Stdcall attribute says callee is responsible for popping arguments
29334 if they are not variable. */
29335 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29336 /* Fastcall attribute says callee is responsible for popping arguments
29337 if they are not variable. */
29338 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29339 /* Cdecl attribute says the callee is a normal C declaration */
29340 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29341 /* Regparm attribute specifies how many integer arguments are to be
29342 passed in registers. */
29343 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29344 /* Sseregparm attribute says we are using x86_64 calling conventions
29345 for FP arguments. */
29346 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29347 /* force_align_arg_pointer says this function realigns the stack at entry. */
29348 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29349 false, true, true, ix86_handle_cconv_attribute },
29350 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29351 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29352 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29353 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29355 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29356 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29357 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29358 SUBTARGET_ATTRIBUTE_TABLE,
29360 /* ms_abi and sysv_abi calling convention function attributes. */
29361 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29362 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29364 { NULL, 0, 0, false, false, false, NULL }
29367 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29369 x86_builtin_vectorization_cost (bool runtime_test)
29371 /* If the branch of the runtime test is taken - i.e. - the vectorized
29372 version is skipped - this incurs a misprediction cost (because the
29373 vectorized version is expected to be the fall-through). So we subtract
29374 the latency of a mispredicted branch from the costs that are incured
29375 when the vectorized version is executed.
29377 TODO: The values in individual target tables have to be tuned or new
29378 fields may be needed. For eg. on K8, the default branch path is the
29379 not-taken path. If the taken path is predicted correctly, the minimum
29380 penalty of going down the taken-path is 1 cycle. If the taken-path is
29381 not predicted correctly, then the minimum penalty is 10 cycles. */
29385 return (-(ix86_cost->cond_taken_branch_cost));
29391 /* This function returns the calling abi specific va_list type node.
29392 It returns the FNDECL specific va_list type. */
29395 ix86_fn_abi_va_list (tree fndecl)
29400 return va_list_type_node;
29401 gcc_assert (fndecl != NULL_TREE);
29402 abi = ix86_function_abi ((const_tree) fndecl);
29405 return ms_va_list_type_node;
29407 return sysv_va_list_type_node;
29410 /* Returns the canonical va_list type specified by TYPE. If there
29411 is no valid TYPE provided, it return NULL_TREE. */
29414 ix86_canonical_va_list_type (tree type)
29418 /* Resolve references and pointers to va_list type. */
29419 if (INDIRECT_REF_P (type))
29420 type = TREE_TYPE (type);
29421 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29422 type = TREE_TYPE (type);
29426 wtype = va_list_type_node;
29427 gcc_assert (wtype != NULL_TREE);
29429 if (TREE_CODE (wtype) == ARRAY_TYPE)
29431 /* If va_list is an array type, the argument may have decayed
29432 to a pointer type, e.g. by being passed to another function.
29433 In that case, unwrap both types so that we can compare the
29434 underlying records. */
29435 if (TREE_CODE (htype) == ARRAY_TYPE
29436 || POINTER_TYPE_P (htype))
29438 wtype = TREE_TYPE (wtype);
29439 htype = TREE_TYPE (htype);
29442 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29443 return va_list_type_node;
29444 wtype = sysv_va_list_type_node;
29445 gcc_assert (wtype != NULL_TREE);
29447 if (TREE_CODE (wtype) == ARRAY_TYPE)
29449 /* If va_list is an array type, the argument may have decayed
29450 to a pointer type, e.g. by being passed to another function.
29451 In that case, unwrap both types so that we can compare the
29452 underlying records. */
29453 if (TREE_CODE (htype) == ARRAY_TYPE
29454 || POINTER_TYPE_P (htype))
29456 wtype = TREE_TYPE (wtype);
29457 htype = TREE_TYPE (htype);
29460 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29461 return sysv_va_list_type_node;
29462 wtype = ms_va_list_type_node;
29463 gcc_assert (wtype != NULL_TREE);
29465 if (TREE_CODE (wtype) == ARRAY_TYPE)
29467 /* If va_list is an array type, the argument may have decayed
29468 to a pointer type, e.g. by being passed to another function.
29469 In that case, unwrap both types so that we can compare the
29470 underlying records. */
29471 if (TREE_CODE (htype) == ARRAY_TYPE
29472 || POINTER_TYPE_P (htype))
29474 wtype = TREE_TYPE (wtype);
29475 htype = TREE_TYPE (htype);
29478 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29479 return ms_va_list_type_node;
29482 return std_canonical_va_list_type (type);
29485 /* Iterate through the target-specific builtin types for va_list.
29486 IDX denotes the iterator, *PTREE is set to the result type of
29487 the va_list builtin, and *PNAME to its internal type.
29488 Returns zero if there is no element for this index, otherwise
29489 IDX should be increased upon the next call.
29490 Note, do not iterate a base builtin's name like __builtin_va_list.
29491 Used from c_common_nodes_and_builtins. */
29494 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29500 *ptree = ms_va_list_type_node;
29501 *pname = "__builtin_ms_va_list";
29504 *ptree = sysv_va_list_type_node;
29505 *pname = "__builtin_sysv_va_list";
29513 /* Initialize the GCC target structure. */
29514 #undef TARGET_RETURN_IN_MEMORY
29515 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29517 #undef TARGET_ATTRIBUTE_TABLE
29518 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29519 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29520 # undef TARGET_MERGE_DECL_ATTRIBUTES
29521 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29524 #undef TARGET_COMP_TYPE_ATTRIBUTES
29525 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29527 #undef TARGET_INIT_BUILTINS
29528 #define TARGET_INIT_BUILTINS ix86_init_builtins
29529 #undef TARGET_EXPAND_BUILTIN
29530 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29532 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29533 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29534 ix86_builtin_vectorized_function
29536 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29537 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29539 #undef TARGET_BUILTIN_RECIPROCAL
29540 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29542 #undef TARGET_ASM_FUNCTION_EPILOGUE
29543 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29545 #undef TARGET_ENCODE_SECTION_INFO
29546 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29547 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29549 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29552 #undef TARGET_ASM_OPEN_PAREN
29553 #define TARGET_ASM_OPEN_PAREN ""
29554 #undef TARGET_ASM_CLOSE_PAREN
29555 #define TARGET_ASM_CLOSE_PAREN ""
29557 #undef TARGET_ASM_ALIGNED_HI_OP
29558 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29559 #undef TARGET_ASM_ALIGNED_SI_OP
29560 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29562 #undef TARGET_ASM_ALIGNED_DI_OP
29563 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29566 #undef TARGET_ASM_UNALIGNED_HI_OP
29567 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29568 #undef TARGET_ASM_UNALIGNED_SI_OP
29569 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29570 #undef TARGET_ASM_UNALIGNED_DI_OP
29571 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29573 #undef TARGET_SCHED_ADJUST_COST
29574 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29575 #undef TARGET_SCHED_ISSUE_RATE
29576 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29577 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29578 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29579 ia32_multipass_dfa_lookahead
29581 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29582 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29585 #undef TARGET_HAVE_TLS
29586 #define TARGET_HAVE_TLS true
29588 #undef TARGET_CANNOT_FORCE_CONST_MEM
29589 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29590 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29591 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29593 #undef TARGET_DELEGITIMIZE_ADDRESS
29594 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29596 #undef TARGET_MS_BITFIELD_LAYOUT_P
29597 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29600 #undef TARGET_BINDS_LOCAL_P
29601 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29603 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29604 #undef TARGET_BINDS_LOCAL_P
29605 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29608 #undef TARGET_ASM_OUTPUT_MI_THUNK
29609 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29610 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29611 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29613 #undef TARGET_ASM_FILE_START
29614 #define TARGET_ASM_FILE_START x86_file_start
29616 #undef TARGET_DEFAULT_TARGET_FLAGS
29617 #define TARGET_DEFAULT_TARGET_FLAGS \
29619 | TARGET_SUBTARGET_DEFAULT \
29620 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29622 #undef TARGET_HANDLE_OPTION
29623 #define TARGET_HANDLE_OPTION ix86_handle_option
29625 #undef TARGET_RTX_COSTS
29626 #define TARGET_RTX_COSTS ix86_rtx_costs
29627 #undef TARGET_ADDRESS_COST
29628 #define TARGET_ADDRESS_COST ix86_address_cost
29630 #undef TARGET_FIXED_CONDITION_CODE_REGS
29631 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29632 #undef TARGET_CC_MODES_COMPATIBLE
29633 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29635 #undef TARGET_MACHINE_DEPENDENT_REORG
29636 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29638 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29639 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29641 #undef TARGET_BUILD_BUILTIN_VA_LIST
29642 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29644 #undef TARGET_FN_ABI_VA_LIST
29645 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29647 #undef TARGET_CANONICAL_VA_LIST_TYPE
29648 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29650 #undef TARGET_EXPAND_BUILTIN_VA_START
29651 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29653 #undef TARGET_MD_ASM_CLOBBERS
29654 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29656 #undef TARGET_PROMOTE_PROTOTYPES
29657 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29658 #undef TARGET_STRUCT_VALUE_RTX
29659 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29660 #undef TARGET_SETUP_INCOMING_VARARGS
29661 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29662 #undef TARGET_MUST_PASS_IN_STACK
29663 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29664 #undef TARGET_PASS_BY_REFERENCE
29665 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29666 #undef TARGET_INTERNAL_ARG_POINTER
29667 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29668 #undef TARGET_UPDATE_STACK_BOUNDARY
29669 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29670 #undef TARGET_GET_DRAP_RTX
29671 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29672 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29673 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29674 #undef TARGET_STRICT_ARGUMENT_NAMING
29675 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29677 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29678 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29680 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29681 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29683 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29684 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29686 #undef TARGET_C_MODE_FOR_SUFFIX
29687 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29690 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29691 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29694 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29695 #undef TARGET_INSERT_ATTRIBUTES
29696 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29699 #undef TARGET_MANGLE_TYPE
29700 #define TARGET_MANGLE_TYPE ix86_mangle_type
29702 #undef TARGET_STACK_PROTECT_FAIL
29703 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29705 #undef TARGET_FUNCTION_VALUE
29706 #define TARGET_FUNCTION_VALUE ix86_function_value
29708 #undef TARGET_SECONDARY_RELOAD
29709 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29711 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29712 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29714 #undef TARGET_SET_CURRENT_FUNCTION
29715 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29717 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29718 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29720 #undef TARGET_OPTION_SAVE
29721 #define TARGET_OPTION_SAVE ix86_function_specific_save
29723 #undef TARGET_OPTION_RESTORE
29724 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29726 #undef TARGET_OPTION_PRINT
29727 #define TARGET_OPTION_PRINT ix86_function_specific_print
29729 #undef TARGET_OPTION_CAN_INLINE_P
29730 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29732 #undef TARGET_EXPAND_TO_RTL_HOOK
29733 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29735 struct gcc_target targetm = TARGET_INITIALIZER;
29737 #include "gt-i386.h"
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