1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static int ix86_function_regparm (const_tree, const_tree);
1883 static void ix86_compute_frame_layout (struct ix86_frame *);
1884 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1886 static void ix86_add_new_builtins (int);
1888 enum ix86_function_specific_strings
1890 IX86_FUNCTION_SPECIFIC_ARCH,
1891 IX86_FUNCTION_SPECIFIC_TUNE,
1892 IX86_FUNCTION_SPECIFIC_FPMATH,
1893 IX86_FUNCTION_SPECIFIC_MAX
1896 static char *ix86_target_string (int, int, const char *, const char *,
1897 const char *, bool);
1898 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1899 static void ix86_function_specific_save (struct cl_target_option *);
1900 static void ix86_function_specific_restore (struct cl_target_option *);
1901 static void ix86_function_specific_print (FILE *, int,
1902 struct cl_target_option *);
1903 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1904 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1905 static bool ix86_can_inline_p (tree, tree);
1906 static void ix86_set_current_function (tree);
1908 static enum calling_abi ix86_function_abi (const_tree);
1911 /* The svr4 ABI for the i386 says that records and unions are returned
1913 #ifndef DEFAULT_PCC_STRUCT_RETURN
1914 #define DEFAULT_PCC_STRUCT_RETURN 1
1917 /* Whether -mtune= or -march= were specified */
1918 static int ix86_tune_defaulted;
1919 static int ix86_arch_specified;
1921 /* Bit flags that specify the ISA we are compiling for. */
1922 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1924 /* A mask of ix86_isa_flags that includes bit X if X
1925 was set or cleared on the command line. */
1926 static int ix86_isa_flags_explicit;
1928 /* Define a set of ISAs which are available when a given ISA is
1929 enabled. MMX and SSE ISAs are handled separately. */
1931 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1932 #define OPTION_MASK_ISA_3DNOW_SET \
1933 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1935 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1936 #define OPTION_MASK_ISA_SSE2_SET \
1937 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1938 #define OPTION_MASK_ISA_SSE3_SET \
1939 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1940 #define OPTION_MASK_ISA_SSSE3_SET \
1941 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1942 #define OPTION_MASK_ISA_SSE4_1_SET \
1943 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1944 #define OPTION_MASK_ISA_SSE4_2_SET \
1945 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1946 #define OPTION_MASK_ISA_AVX_SET \
1947 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1948 #define OPTION_MASK_ISA_FMA_SET \
1949 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1951 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1953 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1955 #define OPTION_MASK_ISA_SSE4A_SET \
1956 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1957 #define OPTION_MASK_ISA_SSE5_SET \
1958 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1960 /* AES and PCLMUL need SSE2 because they use xmm registers */
1961 #define OPTION_MASK_ISA_AES_SET \
1962 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1963 #define OPTION_MASK_ISA_PCLMUL_SET \
1964 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1966 #define OPTION_MASK_ISA_ABM_SET \
1967 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1969 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1970 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1971 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1972 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1973 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1975 /* Define a set of ISAs which aren't available when a given ISA is
1976 disabled. MMX and SSE ISAs are handled separately. */
1978 #define OPTION_MASK_ISA_MMX_UNSET \
1979 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1980 #define OPTION_MASK_ISA_3DNOW_UNSET \
1981 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1982 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1984 #define OPTION_MASK_ISA_SSE_UNSET \
1985 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1986 #define OPTION_MASK_ISA_SSE2_UNSET \
1987 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1988 #define OPTION_MASK_ISA_SSE3_UNSET \
1989 (OPTION_MASK_ISA_SSE3 \
1990 | OPTION_MASK_ISA_SSSE3_UNSET \
1991 | OPTION_MASK_ISA_SSE4A_UNSET )
1992 #define OPTION_MASK_ISA_SSSE3_UNSET \
1993 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1994 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1995 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1996 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1997 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1998 #define OPTION_MASK_ISA_AVX_UNSET \
1999 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
2000 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2002 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2004 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2006 #define OPTION_MASK_ISA_SSE4A_UNSET \
2007 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
2008 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
2009 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2010 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2011 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2012 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2013 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2014 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2015 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2016 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2018 /* Vectorization library interface and handlers. */
2019 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2020 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2021 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2023 /* Processor target table, indexed by processor number */
2026 const struct processor_costs *cost; /* Processor costs */
2027 const int align_loop; /* Default alignments. */
2028 const int align_loop_max_skip;
2029 const int align_jump;
2030 const int align_jump_max_skip;
2031 const int align_func;
2034 static const struct ptt processor_target_table[PROCESSOR_max] =
2036 {&i386_cost, 4, 3, 4, 3, 4},
2037 {&i486_cost, 16, 15, 16, 15, 16},
2038 {&pentium_cost, 16, 7, 16, 7, 16},
2039 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2040 {&geode_cost, 0, 0, 0, 0, 0},
2041 {&k6_cost, 32, 7, 32, 7, 32},
2042 {&athlon_cost, 16, 7, 16, 7, 16},
2043 {&pentium4_cost, 0, 0, 0, 0, 0},
2044 {&k8_cost, 16, 7, 16, 7, 16},
2045 {&nocona_cost, 0, 0, 0, 0, 0},
2046 {&core2_cost, 16, 10, 16, 10, 16},
2047 {&generic32_cost, 16, 7, 16, 7, 16},
2048 {&generic64_cost, 16, 10, 16, 10, 16},
2049 {&amdfam10_cost, 32, 24, 32, 7, 32},
2050 {&atom_cost, 16, 7, 16, 7, 16}
2053 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2079 /* Implement TARGET_HANDLE_OPTION. */
2082 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2089 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2090 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2094 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2095 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2102 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2103 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2107 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2108 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2118 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2119 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2123 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2124 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2131 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2132 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2136 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2144 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2145 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2149 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2157 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2158 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2162 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2170 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2171 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2175 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2183 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2184 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2188 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2196 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2197 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2201 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2209 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2210 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2214 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2220 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2225 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2226 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2232 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2233 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2237 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2238 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2245 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2246 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2250 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2251 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2258 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2259 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2263 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2264 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2271 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2272 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2276 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2277 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2284 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2285 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2289 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2290 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2297 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2298 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2302 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2303 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2310 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2311 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2315 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2316 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2323 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2324 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2328 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2329 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2336 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2337 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2341 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2342 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2349 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2350 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2354 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2355 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2364 /* Return a string the documents the current -m options. The caller is
2365 responsible for freeing the string. */
2368 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2369 const char *fpmath, bool add_nl_p)
2371 struct ix86_target_opts
2373 const char *option; /* option string */
2374 int mask; /* isa mask options */
2377 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2378 preceding options while match those first. */
2379 static struct ix86_target_opts isa_opts[] =
2381 { "-m64", OPTION_MASK_ISA_64BIT },
2382 { "-msse5", OPTION_MASK_ISA_SSE5 },
2383 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2384 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2385 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2386 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2387 { "-msse3", OPTION_MASK_ISA_SSE3 },
2388 { "-msse2", OPTION_MASK_ISA_SSE2 },
2389 { "-msse", OPTION_MASK_ISA_SSE },
2390 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2391 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2392 { "-mmmx", OPTION_MASK_ISA_MMX },
2393 { "-mabm", OPTION_MASK_ISA_ABM },
2394 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2395 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2396 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2397 { "-maes", OPTION_MASK_ISA_AES },
2398 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2402 static struct ix86_target_opts flag_opts[] =
2404 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2405 { "-m80387", MASK_80387 },
2406 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2407 { "-malign-double", MASK_ALIGN_DOUBLE },
2408 { "-mcld", MASK_CLD },
2409 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2410 { "-mieee-fp", MASK_IEEE_FP },
2411 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2412 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2413 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2414 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2415 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2416 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2417 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2418 { "-mno-red-zone", MASK_NO_RED_ZONE },
2419 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2420 { "-mrecip", MASK_RECIP },
2421 { "-mrtd", MASK_RTD },
2422 { "-msseregparm", MASK_SSEREGPARM },
2423 { "-mstack-arg-probe", MASK_STACK_PROBE },
2424 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2427 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2430 char target_other[40];
2439 memset (opts, '\0', sizeof (opts));
2441 /* Add -march= option. */
2444 opts[num][0] = "-march=";
2445 opts[num++][1] = arch;
2448 /* Add -mtune= option. */
2451 opts[num][0] = "-mtune=";
2452 opts[num++][1] = tune;
2455 /* Pick out the options in isa options. */
2456 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2458 if ((isa & isa_opts[i].mask) != 0)
2460 opts[num++][0] = isa_opts[i].option;
2461 isa &= ~ isa_opts[i].mask;
2465 if (isa && add_nl_p)
2467 opts[num++][0] = isa_other;
2468 sprintf (isa_other, "(other isa: 0x%x)", isa);
2471 /* Add flag options. */
2472 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2474 if ((flags & flag_opts[i].mask) != 0)
2476 opts[num++][0] = flag_opts[i].option;
2477 flags &= ~ flag_opts[i].mask;
2481 if (flags && add_nl_p)
2483 opts[num++][0] = target_other;
2484 sprintf (target_other, "(other flags: 0x%x)", isa);
2487 /* Add -fpmath= option. */
2490 opts[num][0] = "-mfpmath=";
2491 opts[num++][1] = fpmath;
2498 gcc_assert (num < ARRAY_SIZE (opts));
2500 /* Size the string. */
2502 sep_len = (add_nl_p) ? 3 : 1;
2503 for (i = 0; i < num; i++)
2506 for (j = 0; j < 2; j++)
2508 len += strlen (opts[i][j]);
2511 /* Build the string. */
2512 ret = ptr = (char *) xmalloc (len);
2515 for (i = 0; i < num; i++)
2519 for (j = 0; j < 2; j++)
2520 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2527 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2535 for (j = 0; j < 2; j++)
2538 memcpy (ptr, opts[i][j], len2[j]);
2540 line_len += len2[j];
2545 gcc_assert (ret + len >= ptr);
2550 /* Function that is callable from the debugger to print the current
2553 ix86_debug_options (void)
2555 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2556 ix86_arch_string, ix86_tune_string,
2557 ix86_fpmath_string, true);
2561 fprintf (stderr, "%s\n\n", opts);
2565 fprintf (stderr, "<no options>\n\n");
2570 /* Sometimes certain combinations of command options do not make
2571 sense on a particular target machine. You can define a macro
2572 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2573 defined, is executed once just after all the command options have
2576 Don't use this macro to turn on various extra optimizations for
2577 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2580 override_options (bool main_args_p)
2583 unsigned int ix86_arch_mask, ix86_tune_mask;
2588 /* Comes from final.c -- no real reason to change it. */
2589 #define MAX_CODE_ALIGN 16
2597 PTA_PREFETCH_SSE = 1 << 4,
2599 PTA_3DNOW_A = 1 << 6,
2603 PTA_POPCNT = 1 << 10,
2605 PTA_SSE4A = 1 << 12,
2606 PTA_NO_SAHF = 1 << 13,
2607 PTA_SSE4_1 = 1 << 14,
2608 PTA_SSE4_2 = 1 << 15,
2611 PTA_PCLMUL = 1 << 18,
2619 const char *const name; /* processor name or nickname. */
2620 const enum processor_type processor;
2621 const enum attr_cpu schedule;
2622 const unsigned /*enum pta_flags*/ flags;
2624 const processor_alias_table[] =
2626 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2627 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2628 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2629 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2630 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2631 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2632 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2633 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2634 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2635 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2636 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2637 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2638 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2640 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2642 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2643 PTA_MMX | PTA_SSE | PTA_SSE2},
2644 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2645 PTA_MMX |PTA_SSE | PTA_SSE2},
2646 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2647 PTA_MMX | PTA_SSE | PTA_SSE2},
2648 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2649 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2650 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2651 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2652 | PTA_CX16 | PTA_NO_SAHF},
2653 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2654 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2655 | PTA_SSSE3 | PTA_CX16},
2656 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2657 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2658 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2659 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2660 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2661 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2662 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2663 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2664 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2665 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2666 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2667 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2668 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2669 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2670 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2671 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2672 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2673 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2674 {"x86-64", PROCESSOR_K8, CPU_K8,
2675 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2676 {"k8", PROCESSOR_K8, CPU_K8,
2677 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2678 | PTA_SSE2 | PTA_NO_SAHF},
2679 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2680 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2681 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2682 {"opteron", PROCESSOR_K8, CPU_K8,
2683 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2684 | PTA_SSE2 | PTA_NO_SAHF},
2685 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2686 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2687 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2688 {"athlon64", PROCESSOR_K8, CPU_K8,
2689 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2690 | PTA_SSE2 | PTA_NO_SAHF},
2691 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2692 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2693 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2694 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2695 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2696 | PTA_SSE2 | PTA_NO_SAHF},
2697 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2698 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2699 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2700 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2701 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2702 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2703 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2704 0 /* flags are only used for -march switch. */ },
2705 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2706 PTA_64BIT /* flags are only used for -march switch. */ },
2709 int const pta_size = ARRAY_SIZE (processor_alias_table);
2711 /* Set up prefix/suffix so the error messages refer to either the command
2712 line argument, or the attribute(target). */
2721 prefix = "option(\"";
2726 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2727 SUBTARGET_OVERRIDE_OPTIONS;
2730 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2731 SUBSUBTARGET_OVERRIDE_OPTIONS;
2734 /* -fPIC is the default for x86_64. */
2735 if (TARGET_MACHO && TARGET_64BIT)
2738 /* Set the default values for switches whose default depends on TARGET_64BIT
2739 in case they weren't overwritten by command line options. */
2742 /* Mach-O doesn't support omitting the frame pointer for now. */
2743 if (flag_omit_frame_pointer == 2)
2744 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2745 if (flag_asynchronous_unwind_tables == 2)
2746 flag_asynchronous_unwind_tables = 1;
2747 if (flag_pcc_struct_return == 2)
2748 flag_pcc_struct_return = 0;
2752 if (flag_omit_frame_pointer == 2)
2753 flag_omit_frame_pointer = 0;
2754 if (flag_asynchronous_unwind_tables == 2)
2755 flag_asynchronous_unwind_tables = 0;
2756 if (flag_pcc_struct_return == 2)
2757 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2760 /* Need to check -mtune=generic first. */
2761 if (ix86_tune_string)
2763 if (!strcmp (ix86_tune_string, "generic")
2764 || !strcmp (ix86_tune_string, "i686")
2765 /* As special support for cross compilers we read -mtune=native
2766 as -mtune=generic. With native compilers we won't see the
2767 -mtune=native, as it was changed by the driver. */
2768 || !strcmp (ix86_tune_string, "native"))
2771 ix86_tune_string = "generic64";
2773 ix86_tune_string = "generic32";
2775 /* If this call is for setting the option attribute, allow the
2776 generic32/generic64 that was previously set. */
2777 else if (!main_args_p
2778 && (!strcmp (ix86_tune_string, "generic32")
2779 || !strcmp (ix86_tune_string, "generic64")))
2781 else if (!strncmp (ix86_tune_string, "generic", 7))
2782 error ("bad value (%s) for %stune=%s %s",
2783 ix86_tune_string, prefix, suffix, sw);
2787 if (ix86_arch_string)
2788 ix86_tune_string = ix86_arch_string;
2789 if (!ix86_tune_string)
2791 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2792 ix86_tune_defaulted = 1;
2795 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2796 need to use a sensible tune option. */
2797 if (!strcmp (ix86_tune_string, "generic")
2798 || !strcmp (ix86_tune_string, "x86-64")
2799 || !strcmp (ix86_tune_string, "i686"))
2802 ix86_tune_string = "generic64";
2804 ix86_tune_string = "generic32";
2807 if (ix86_stringop_string)
2809 if (!strcmp (ix86_stringop_string, "rep_byte"))
2810 stringop_alg = rep_prefix_1_byte;
2811 else if (!strcmp (ix86_stringop_string, "libcall"))
2812 stringop_alg = libcall;
2813 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2814 stringop_alg = rep_prefix_4_byte;
2815 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2817 /* rep; movq isn't available in 32-bit code. */
2818 stringop_alg = rep_prefix_8_byte;
2819 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2820 stringop_alg = loop_1_byte;
2821 else if (!strcmp (ix86_stringop_string, "loop"))
2822 stringop_alg = loop;
2823 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2824 stringop_alg = unrolled_loop;
2826 error ("bad value (%s) for %sstringop-strategy=%s %s",
2827 ix86_stringop_string, prefix, suffix, sw);
2829 if (!strcmp (ix86_tune_string, "x86-64"))
2830 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2831 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2832 prefix, suffix, prefix, suffix, prefix, suffix);
2834 if (!ix86_arch_string)
2835 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2837 ix86_arch_specified = 1;
2839 if (!strcmp (ix86_arch_string, "generic"))
2840 error ("generic CPU can be used only for %stune=%s %s",
2841 prefix, suffix, sw);
2842 if (!strncmp (ix86_arch_string, "generic", 7))
2843 error ("bad value (%s) for %sarch=%s %s",
2844 ix86_arch_string, prefix, suffix, sw);
2846 /* Validate -mabi= value. */
2847 if (ix86_abi_string)
2849 if (strcmp (ix86_abi_string, "sysv") == 0)
2850 ix86_abi = SYSV_ABI;
2851 else if (strcmp (ix86_abi_string, "ms") == 0)
2854 error ("unknown ABI (%s) for %sabi=%s %s",
2855 ix86_abi_string, prefix, suffix, sw);
2858 ix86_abi = DEFAULT_ABI;
2860 if (ix86_cmodel_string != 0)
2862 if (!strcmp (ix86_cmodel_string, "small"))
2863 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2864 else if (!strcmp (ix86_cmodel_string, "medium"))
2865 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2866 else if (!strcmp (ix86_cmodel_string, "large"))
2867 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2869 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2870 else if (!strcmp (ix86_cmodel_string, "32"))
2871 ix86_cmodel = CM_32;
2872 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2873 ix86_cmodel = CM_KERNEL;
2875 error ("bad value (%s) for %scmodel=%s %s",
2876 ix86_cmodel_string, prefix, suffix, sw);
2880 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2881 use of rip-relative addressing. This eliminates fixups that
2882 would otherwise be needed if this object is to be placed in a
2883 DLL, and is essentially just as efficient as direct addressing. */
2884 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2885 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2886 else if (TARGET_64BIT)
2887 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2889 ix86_cmodel = CM_32;
2891 if (ix86_asm_string != 0)
2894 && !strcmp (ix86_asm_string, "intel"))
2895 ix86_asm_dialect = ASM_INTEL;
2896 else if (!strcmp (ix86_asm_string, "att"))
2897 ix86_asm_dialect = ASM_ATT;
2899 error ("bad value (%s) for %sasm=%s %s",
2900 ix86_asm_string, prefix, suffix, sw);
2902 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2903 error ("code model %qs not supported in the %s bit mode",
2904 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2905 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2906 sorry ("%i-bit mode not compiled in",
2907 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2909 for (i = 0; i < pta_size; i++)
2910 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2912 ix86_schedule = processor_alias_table[i].schedule;
2913 ix86_arch = processor_alias_table[i].processor;
2914 /* Default cpu tuning to the architecture. */
2915 ix86_tune = ix86_arch;
2917 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2918 error ("CPU you selected does not support x86-64 "
2921 if (processor_alias_table[i].flags & PTA_MMX
2922 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2923 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2924 if (processor_alias_table[i].flags & PTA_3DNOW
2925 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2926 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2927 if (processor_alias_table[i].flags & PTA_3DNOW_A
2928 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2929 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2930 if (processor_alias_table[i].flags & PTA_SSE
2931 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2932 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2933 if (processor_alias_table[i].flags & PTA_SSE2
2934 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2935 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2936 if (processor_alias_table[i].flags & PTA_SSE3
2937 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2938 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2939 if (processor_alias_table[i].flags & PTA_SSSE3
2940 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2941 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2942 if (processor_alias_table[i].flags & PTA_SSE4_1
2943 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2944 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2945 if (processor_alias_table[i].flags & PTA_SSE4_2
2946 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2947 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2948 if (processor_alias_table[i].flags & PTA_AVX
2949 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2950 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2951 if (processor_alias_table[i].flags & PTA_FMA
2952 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2953 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2954 if (processor_alias_table[i].flags & PTA_SSE4A
2955 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2956 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2957 if (processor_alias_table[i].flags & PTA_SSE5
2958 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2959 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2960 if (processor_alias_table[i].flags & PTA_ABM
2961 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2962 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2963 if (processor_alias_table[i].flags & PTA_CX16
2964 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2965 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2966 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2967 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2968 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2969 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2970 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2971 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2972 if (processor_alias_table[i].flags & PTA_MOVBE
2973 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
2974 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
2975 if (processor_alias_table[i].flags & PTA_AES
2976 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2977 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2978 if (processor_alias_table[i].flags & PTA_PCLMUL
2979 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2980 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2981 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2982 x86_prefetch_sse = true;
2988 error ("bad value (%s) for %sarch=%s %s",
2989 ix86_arch_string, prefix, suffix, sw);
2991 ix86_arch_mask = 1u << ix86_arch;
2992 for (i = 0; i < X86_ARCH_LAST; ++i)
2993 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2995 for (i = 0; i < pta_size; i++)
2996 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2998 ix86_schedule = processor_alias_table[i].schedule;
2999 ix86_tune = processor_alias_table[i].processor;
3000 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
3002 if (ix86_tune_defaulted)
3004 ix86_tune_string = "x86-64";
3005 for (i = 0; i < pta_size; i++)
3006 if (! strcmp (ix86_tune_string,
3007 processor_alias_table[i].name))
3009 ix86_schedule = processor_alias_table[i].schedule;
3010 ix86_tune = processor_alias_table[i].processor;
3013 error ("CPU you selected does not support x86-64 "
3016 /* Intel CPUs have always interpreted SSE prefetch instructions as
3017 NOPs; so, we can enable SSE prefetch instructions even when
3018 -mtune (rather than -march) points us to a processor that has them.
3019 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3020 higher processors. */
3022 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3023 x86_prefetch_sse = true;
3027 error ("bad value (%s) for %stune=%s %s",
3028 ix86_tune_string, prefix, suffix, sw);
3030 ix86_tune_mask = 1u << ix86_tune;
3031 for (i = 0; i < X86_TUNE_LAST; ++i)
3032 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3035 ix86_cost = &ix86_size_cost;
3037 ix86_cost = processor_target_table[ix86_tune].cost;
3039 /* Arrange to set up i386_stack_locals for all functions. */
3040 init_machine_status = ix86_init_machine_status;
3042 /* Validate -mregparm= value. */
3043 if (ix86_regparm_string)
3046 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3047 i = atoi (ix86_regparm_string);
3048 if (i < 0 || i > REGPARM_MAX)
3049 error ("%sregparm=%d%s is not between 0 and %d",
3050 prefix, i, suffix, REGPARM_MAX);
3055 ix86_regparm = REGPARM_MAX;
3057 /* If the user has provided any of the -malign-* options,
3058 warn and use that value only if -falign-* is not set.
3059 Remove this code in GCC 3.2 or later. */
3060 if (ix86_align_loops_string)
3062 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3063 prefix, suffix, suffix);
3064 if (align_loops == 0)
3066 i = atoi (ix86_align_loops_string);
3067 if (i < 0 || i > MAX_CODE_ALIGN)
3068 error ("%salign-loops=%d%s is not between 0 and %d",
3069 prefix, i, suffix, MAX_CODE_ALIGN);
3071 align_loops = 1 << i;
3075 if (ix86_align_jumps_string)
3077 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3078 prefix, suffix, suffix);
3079 if (align_jumps == 0)
3081 i = atoi (ix86_align_jumps_string);
3082 if (i < 0 || i > MAX_CODE_ALIGN)
3083 error ("%salign-loops=%d%s is not between 0 and %d",
3084 prefix, i, suffix, MAX_CODE_ALIGN);
3086 align_jumps = 1 << i;
3090 if (ix86_align_funcs_string)
3092 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3093 prefix, suffix, suffix);
3094 if (align_functions == 0)
3096 i = atoi (ix86_align_funcs_string);
3097 if (i < 0 || i > MAX_CODE_ALIGN)
3098 error ("%salign-loops=%d%s is not between 0 and %d",
3099 prefix, i, suffix, MAX_CODE_ALIGN);
3101 align_functions = 1 << i;
3105 /* Default align_* from the processor table. */
3106 if (align_loops == 0)
3108 align_loops = processor_target_table[ix86_tune].align_loop;
3109 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3111 if (align_jumps == 0)
3113 align_jumps = processor_target_table[ix86_tune].align_jump;
3114 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3116 if (align_functions == 0)
3118 align_functions = processor_target_table[ix86_tune].align_func;
3121 /* Validate -mbranch-cost= value, or provide default. */
3122 ix86_branch_cost = ix86_cost->branch_cost;
3123 if (ix86_branch_cost_string)
3125 i = atoi (ix86_branch_cost_string);
3127 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3129 ix86_branch_cost = i;
3131 if (ix86_section_threshold_string)
3133 i = atoi (ix86_section_threshold_string);
3135 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3137 ix86_section_threshold = i;
3140 if (ix86_tls_dialect_string)
3142 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3143 ix86_tls_dialect = TLS_DIALECT_GNU;
3144 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3145 ix86_tls_dialect = TLS_DIALECT_GNU2;
3146 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3147 ix86_tls_dialect = TLS_DIALECT_SUN;
3149 error ("bad value (%s) for %stls-dialect=%s %s",
3150 ix86_tls_dialect_string, prefix, suffix, sw);
3153 if (ix87_precision_string)
3155 i = atoi (ix87_precision_string);
3156 if (i != 32 && i != 64 && i != 80)
3157 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3162 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3164 /* Enable by default the SSE and MMX builtins. Do allow the user to
3165 explicitly disable any of these. In particular, disabling SSE and
3166 MMX for kernel code is extremely useful. */
3167 if (!ix86_arch_specified)
3169 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3170 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3173 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3177 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3179 if (!ix86_arch_specified)
3181 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3183 /* i386 ABI does not specify red zone. It still makes sense to use it
3184 when programmer takes care to stack from being destroyed. */
3185 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3186 target_flags |= MASK_NO_RED_ZONE;
3189 /* Keep nonleaf frame pointers. */
3190 if (flag_omit_frame_pointer)
3191 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3192 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3193 flag_omit_frame_pointer = 1;
3195 /* If we're doing fast math, we don't care about comparison order
3196 wrt NaNs. This lets us use a shorter comparison sequence. */
3197 if (flag_finite_math_only)
3198 target_flags &= ~MASK_IEEE_FP;
3200 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3201 since the insns won't need emulation. */
3202 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3203 target_flags &= ~MASK_NO_FANCY_MATH_387;
3205 /* Likewise, if the target doesn't have a 387, or we've specified
3206 software floating point, don't use 387 inline intrinsics. */
3208 target_flags |= MASK_NO_FANCY_MATH_387;
3210 /* Turn on MMX builtins for -msse. */
3213 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3214 x86_prefetch_sse = true;
3217 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3218 if (TARGET_SSE4_2 || TARGET_ABM)
3219 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3221 /* Validate -mpreferred-stack-boundary= value or default it to
3222 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3223 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3224 if (ix86_preferred_stack_boundary_string)
3226 i = atoi (ix86_preferred_stack_boundary_string);
3227 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3228 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3229 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3231 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3234 /* Set the default value for -mstackrealign. */
3235 if (ix86_force_align_arg_pointer == -1)
3236 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3238 /* Validate -mincoming-stack-boundary= value or default it to
3239 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3240 if (ix86_force_align_arg_pointer)
3241 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3243 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3244 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3245 if (ix86_incoming_stack_boundary_string)
3247 i = atoi (ix86_incoming_stack_boundary_string);
3248 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3249 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3250 i, TARGET_64BIT ? 4 : 2);
3253 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3254 ix86_incoming_stack_boundary
3255 = ix86_user_incoming_stack_boundary;
3259 /* Accept -msseregparm only if at least SSE support is enabled. */
3260 if (TARGET_SSEREGPARM
3262 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3264 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3265 if (ix86_fpmath_string != 0)
3267 if (! strcmp (ix86_fpmath_string, "387"))
3268 ix86_fpmath = FPMATH_387;
3269 else if (! strcmp (ix86_fpmath_string, "sse"))
3273 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3274 ix86_fpmath = FPMATH_387;
3277 ix86_fpmath = FPMATH_SSE;
3279 else if (! strcmp (ix86_fpmath_string, "387,sse")
3280 || ! strcmp (ix86_fpmath_string, "387+sse")
3281 || ! strcmp (ix86_fpmath_string, "sse,387")
3282 || ! strcmp (ix86_fpmath_string, "sse+387")
3283 || ! strcmp (ix86_fpmath_string, "both"))
3287 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3288 ix86_fpmath = FPMATH_387;
3290 else if (!TARGET_80387)
3292 warning (0, "387 instruction set disabled, using SSE arithmetics");
3293 ix86_fpmath = FPMATH_SSE;
3296 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3299 error ("bad value (%s) for %sfpmath=%s %s",
3300 ix86_fpmath_string, prefix, suffix, sw);
3303 /* If the i387 is disabled, then do not return values in it. */
3305 target_flags &= ~MASK_FLOAT_RETURNS;
3307 /* Use external vectorized library in vectorizing intrinsics. */
3308 if (ix86_veclibabi_string)
3310 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3311 ix86_veclib_handler = ix86_veclibabi_svml;
3312 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3313 ix86_veclib_handler = ix86_veclibabi_acml;
3315 error ("unknown vectorization library ABI type (%s) for "
3316 "%sveclibabi=%s %s", ix86_veclibabi_string,
3317 prefix, suffix, sw);
3320 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3321 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3323 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3325 /* ??? Unwind info is not correct around the CFG unless either a frame
3326 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3327 unwind info generation to be aware of the CFG and propagating states
3329 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3330 || flag_exceptions || flag_non_call_exceptions)
3331 && flag_omit_frame_pointer
3332 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3334 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3335 warning (0, "unwind tables currently require either a frame pointer "
3336 "or %saccumulate-outgoing-args%s for correctness",
3338 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3341 /* If stack probes are required, the space used for large function
3342 arguments on the stack must also be probed, so enable
3343 -maccumulate-outgoing-args so this happens in the prologue. */
3344 if (TARGET_STACK_PROBE
3345 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3347 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3348 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3349 "for correctness", prefix, suffix);
3350 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3353 /* For sane SSE instruction set generation we need fcomi instruction.
3354 It is safe to enable all CMOVE instructions. */
3358 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3361 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3362 p = strchr (internal_label_prefix, 'X');
3363 internal_label_prefix_len = p - internal_label_prefix;
3367 /* When scheduling description is not available, disable scheduler pass
3368 so it won't slow down the compilation and make x87 code slower. */
3369 if (!TARGET_SCHEDULE)
3370 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3372 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3373 set_param_value ("simultaneous-prefetches",
3374 ix86_cost->simultaneous_prefetches);
3375 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3376 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3377 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3378 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3379 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3380 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3382 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3383 can be optimized to ap = __builtin_next_arg (0). */
3385 targetm.expand_builtin_va_start = NULL;
3389 ix86_gen_leave = gen_leave_rex64;
3390 ix86_gen_pop1 = gen_popdi1;
3391 ix86_gen_add3 = gen_adddi3;
3392 ix86_gen_sub3 = gen_subdi3;
3393 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3394 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3395 ix86_gen_monitor = gen_sse3_monitor64;
3396 ix86_gen_andsp = gen_anddi3;
3400 ix86_gen_leave = gen_leave;
3401 ix86_gen_pop1 = gen_popsi1;
3402 ix86_gen_add3 = gen_addsi3;
3403 ix86_gen_sub3 = gen_subsi3;
3404 ix86_gen_sub3_carry = gen_subsi3_carry;
3405 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3406 ix86_gen_monitor = gen_sse3_monitor;
3407 ix86_gen_andsp = gen_andsi3;
3411 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3413 target_flags |= MASK_CLD & ~target_flags_explicit;
3416 /* Save the initial options in case the user does function specific options */
3418 target_option_default_node = target_option_current_node
3419 = build_target_option_node ();
3422 /* Save the current options */
3425 ix86_function_specific_save (struct cl_target_option *ptr)
3427 ptr->arch = ix86_arch;
3428 ptr->schedule = ix86_schedule;
3429 ptr->tune = ix86_tune;
3430 ptr->fpmath = ix86_fpmath;
3431 ptr->branch_cost = ix86_branch_cost;
3432 ptr->tune_defaulted = ix86_tune_defaulted;
3433 ptr->arch_specified = ix86_arch_specified;
3434 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3435 ptr->target_flags_explicit = target_flags_explicit;
3437 /* The fields are char but the variables are not; make sure the
3438 values fit in the fields. */
3439 gcc_assert (ptr->arch == ix86_arch);
3440 gcc_assert (ptr->schedule == ix86_schedule);
3441 gcc_assert (ptr->tune == ix86_tune);
3442 gcc_assert (ptr->fpmath == ix86_fpmath);
3443 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3446 /* Restore the current options */
3449 ix86_function_specific_restore (struct cl_target_option *ptr)
3451 enum processor_type old_tune = ix86_tune;
3452 enum processor_type old_arch = ix86_arch;
3453 unsigned int ix86_arch_mask, ix86_tune_mask;
3456 ix86_arch = (enum processor_type) ptr->arch;
3457 ix86_schedule = (enum attr_cpu) ptr->schedule;
3458 ix86_tune = (enum processor_type) ptr->tune;
3459 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3460 ix86_branch_cost = ptr->branch_cost;
3461 ix86_tune_defaulted = ptr->tune_defaulted;
3462 ix86_arch_specified = ptr->arch_specified;
3463 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3464 target_flags_explicit = ptr->target_flags_explicit;
3466 /* Recreate the arch feature tests if the arch changed */
3467 if (old_arch != ix86_arch)
3469 ix86_arch_mask = 1u << ix86_arch;
3470 for (i = 0; i < X86_ARCH_LAST; ++i)
3471 ix86_arch_features[i]
3472 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3475 /* Recreate the tune optimization tests */
3476 if (old_tune != ix86_tune)
3478 ix86_tune_mask = 1u << ix86_tune;
3479 for (i = 0; i < X86_TUNE_LAST; ++i)
3480 ix86_tune_features[i]
3481 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3485 /* Print the current options */
3488 ix86_function_specific_print (FILE *file, int indent,
3489 struct cl_target_option *ptr)
3492 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3493 NULL, NULL, NULL, false);
3495 fprintf (file, "%*sarch = %d (%s)\n",
3498 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3499 ? cpu_names[ptr->arch]
3502 fprintf (file, "%*stune = %d (%s)\n",
3505 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3506 ? cpu_names[ptr->tune]
3509 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3510 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3511 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3512 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3516 fprintf (file, "%*s%s\n", indent, "", target_string);
3517 free (target_string);
3522 /* Inner function to process the attribute((target(...))), take an argument and
3523 set the current options from the argument. If we have a list, recursively go
3527 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3532 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3533 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3534 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3535 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3550 enum ix86_opt_type type;
3555 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3556 IX86_ATTR_ISA ("abm", OPT_mabm),
3557 IX86_ATTR_ISA ("aes", OPT_maes),
3558 IX86_ATTR_ISA ("avx", OPT_mavx),
3559 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3560 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3561 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3562 IX86_ATTR_ISA ("sse", OPT_msse),
3563 IX86_ATTR_ISA ("sse2", OPT_msse2),
3564 IX86_ATTR_ISA ("sse3", OPT_msse3),
3565 IX86_ATTR_ISA ("sse4", OPT_msse4),
3566 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3567 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3568 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3569 IX86_ATTR_ISA ("sse5", OPT_msse5),
3570 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3572 /* string options */
3573 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3574 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3575 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3578 IX86_ATTR_YES ("cld",
3582 IX86_ATTR_NO ("fancy-math-387",
3583 OPT_mfancy_math_387,
3584 MASK_NO_FANCY_MATH_387),
3586 IX86_ATTR_NO ("fused-madd",
3588 MASK_NO_FUSED_MADD),
3590 IX86_ATTR_YES ("ieee-fp",
3594 IX86_ATTR_YES ("inline-all-stringops",
3595 OPT_minline_all_stringops,
3596 MASK_INLINE_ALL_STRINGOPS),
3598 IX86_ATTR_YES ("inline-stringops-dynamically",
3599 OPT_minline_stringops_dynamically,
3600 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3602 IX86_ATTR_NO ("align-stringops",
3603 OPT_mno_align_stringops,
3604 MASK_NO_ALIGN_STRINGOPS),
3606 IX86_ATTR_YES ("recip",
3612 /* If this is a list, recurse to get the options. */
3613 if (TREE_CODE (args) == TREE_LIST)
3617 for (; args; args = TREE_CHAIN (args))
3618 if (TREE_VALUE (args)
3619 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3625 else if (TREE_CODE (args) != STRING_CST)
3628 /* Handle multiple arguments separated by commas. */
3629 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3631 while (next_optstr && *next_optstr != '\0')
3633 char *p = next_optstr;
3635 char *comma = strchr (next_optstr, ',');
3636 const char *opt_string;
3637 size_t len, opt_len;
3642 enum ix86_opt_type type = ix86_opt_unknown;
3648 len = comma - next_optstr;
3649 next_optstr = comma + 1;
3657 /* Recognize no-xxx. */
3658 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3667 /* Find the option. */
3670 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3672 type = attrs[i].type;
3673 opt_len = attrs[i].len;
3674 if (ch == attrs[i].string[0]
3675 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3676 && memcmp (p, attrs[i].string, opt_len) == 0)
3679 mask = attrs[i].mask;
3680 opt_string = attrs[i].string;
3685 /* Process the option. */
3688 error ("attribute(target(\"%s\")) is unknown", orig_p);
3692 else if (type == ix86_opt_isa)
3693 ix86_handle_option (opt, p, opt_set_p);
3695 else if (type == ix86_opt_yes || type == ix86_opt_no)
3697 if (type == ix86_opt_no)
3698 opt_set_p = !opt_set_p;
3701 target_flags |= mask;
3703 target_flags &= ~mask;
3706 else if (type == ix86_opt_str)
3710 error ("option(\"%s\") was already specified", opt_string);
3714 p_strings[opt] = xstrdup (p + opt_len);
3724 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3727 ix86_valid_target_attribute_tree (tree args)
3729 const char *orig_arch_string = ix86_arch_string;
3730 const char *orig_tune_string = ix86_tune_string;
3731 const char *orig_fpmath_string = ix86_fpmath_string;
3732 int orig_tune_defaulted = ix86_tune_defaulted;
3733 int orig_arch_specified = ix86_arch_specified;
3734 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3737 struct cl_target_option *def
3738 = TREE_TARGET_OPTION (target_option_default_node);
3740 /* Process each of the options on the chain. */
3741 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3744 /* If the changed options are different from the default, rerun override_options,
3745 and then save the options away. The string options are are attribute options,
3746 and will be undone when we copy the save structure. */
3747 if (ix86_isa_flags != def->ix86_isa_flags
3748 || target_flags != def->target_flags
3749 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3750 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3751 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3753 /* If we are using the default tune= or arch=, undo the string assigned,
3754 and use the default. */
3755 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3756 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3757 else if (!orig_arch_specified)
3758 ix86_arch_string = NULL;
3760 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3761 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3762 else if (orig_tune_defaulted)
3763 ix86_tune_string = NULL;
3765 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3766 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3767 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3768 else if (!TARGET_64BIT && TARGET_SSE)
3769 ix86_fpmath_string = "sse,387";
3771 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3772 override_options (false);
3774 /* Add any builtin functions with the new isa if any. */
3775 ix86_add_new_builtins (ix86_isa_flags);
3777 /* Save the current options unless we are validating options for
3779 t = build_target_option_node ();
3781 ix86_arch_string = orig_arch_string;
3782 ix86_tune_string = orig_tune_string;
3783 ix86_fpmath_string = orig_fpmath_string;
3785 /* Free up memory allocated to hold the strings */
3786 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3787 if (option_strings[i])
3788 free (option_strings[i]);
3794 /* Hook to validate attribute((target("string"))). */
3797 ix86_valid_target_attribute_p (tree fndecl,
3798 tree ARG_UNUSED (name),
3800 int ARG_UNUSED (flags))
3802 struct cl_target_option cur_target;
3804 tree old_optimize = build_optimization_node ();
3805 tree new_target, new_optimize;
3806 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3808 /* If the function changed the optimization levels as well as setting target
3809 options, start with the optimizations specified. */
3810 if (func_optimize && func_optimize != old_optimize)
3811 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3813 /* The target attributes may also change some optimization flags, so update
3814 the optimization options if necessary. */
3815 cl_target_option_save (&cur_target);
3816 new_target = ix86_valid_target_attribute_tree (args);
3817 new_optimize = build_optimization_node ();
3824 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3826 if (old_optimize != new_optimize)
3827 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3830 cl_target_option_restore (&cur_target);
3832 if (old_optimize != new_optimize)
3833 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3839 /* Hook to determine if one function can safely inline another. */
3842 ix86_can_inline_p (tree caller, tree callee)
3845 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3846 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3848 /* If callee has no option attributes, then it is ok to inline. */
3852 /* If caller has no option attributes, but callee does then it is not ok to
3854 else if (!caller_tree)
3859 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3860 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3862 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3863 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3865 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3866 != callee_opts->ix86_isa_flags)
3869 /* See if we have the same non-isa options. */
3870 else if (caller_opts->target_flags != callee_opts->target_flags)
3873 /* See if arch, tune, etc. are the same. */
3874 else if (caller_opts->arch != callee_opts->arch)
3877 else if (caller_opts->tune != callee_opts->tune)
3880 else if (caller_opts->fpmath != callee_opts->fpmath)
3883 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3894 /* Remember the last target of ix86_set_current_function. */
3895 static GTY(()) tree ix86_previous_fndecl;
3897 /* Establish appropriate back-end context for processing the function
3898 FNDECL. The argument might be NULL to indicate processing at top
3899 level, outside of any function scope. */
3901 ix86_set_current_function (tree fndecl)
3903 /* Only change the context if the function changes. This hook is called
3904 several times in the course of compiling a function, and we don't want to
3905 slow things down too much or call target_reinit when it isn't safe. */
3906 if (fndecl && fndecl != ix86_previous_fndecl)
3908 tree old_tree = (ix86_previous_fndecl
3909 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3912 tree new_tree = (fndecl
3913 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3916 ix86_previous_fndecl = fndecl;
3917 if (old_tree == new_tree)
3922 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3928 struct cl_target_option *def
3929 = TREE_TARGET_OPTION (target_option_current_node);
3931 cl_target_option_restore (def);
3938 /* Return true if this goes in large data/bss. */
3941 ix86_in_large_data_p (tree exp)
3943 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3946 /* Functions are never large data. */
3947 if (TREE_CODE (exp) == FUNCTION_DECL)
3950 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3952 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3953 if (strcmp (section, ".ldata") == 0
3954 || strcmp (section, ".lbss") == 0)
3960 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3962 /* If this is an incomplete type with size 0, then we can't put it
3963 in data because it might be too big when completed. */
3964 if (!size || size > ix86_section_threshold)
3971 /* Switch to the appropriate section for output of DECL.
3972 DECL is either a `VAR_DECL' node or a constant of some sort.
3973 RELOC indicates whether forming the initial value of DECL requires
3974 link-time relocations. */
3976 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3980 x86_64_elf_select_section (tree decl, int reloc,
3981 unsigned HOST_WIDE_INT align)
3983 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3984 && ix86_in_large_data_p (decl))
3986 const char *sname = NULL;
3987 unsigned int flags = SECTION_WRITE;
3988 switch (categorize_decl_for_section (decl, reloc))
3993 case SECCAT_DATA_REL:
3994 sname = ".ldata.rel";
3996 case SECCAT_DATA_REL_LOCAL:
3997 sname = ".ldata.rel.local";
3999 case SECCAT_DATA_REL_RO:
4000 sname = ".ldata.rel.ro";
4002 case SECCAT_DATA_REL_RO_LOCAL:
4003 sname = ".ldata.rel.ro.local";
4007 flags |= SECTION_BSS;
4010 case SECCAT_RODATA_MERGE_STR:
4011 case SECCAT_RODATA_MERGE_STR_INIT:
4012 case SECCAT_RODATA_MERGE_CONST:
4016 case SECCAT_SRODATA:
4023 /* We don't split these for medium model. Place them into
4024 default sections and hope for best. */
4026 case SECCAT_EMUTLS_VAR:
4027 case SECCAT_EMUTLS_TMPL:
4032 /* We might get called with string constants, but get_named_section
4033 doesn't like them as they are not DECLs. Also, we need to set
4034 flags in that case. */
4036 return get_section (sname, flags, NULL);
4037 return get_named_section (decl, sname, reloc);
4040 return default_elf_select_section (decl, reloc, align);
4043 /* Build up a unique section name, expressed as a
4044 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4045 RELOC indicates whether the initial value of EXP requires
4046 link-time relocations. */
4048 static void ATTRIBUTE_UNUSED
4049 x86_64_elf_unique_section (tree decl, int reloc)
4051 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4052 && ix86_in_large_data_p (decl))
4054 const char *prefix = NULL;
4055 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4056 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4058 switch (categorize_decl_for_section (decl, reloc))
4061 case SECCAT_DATA_REL:
4062 case SECCAT_DATA_REL_LOCAL:
4063 case SECCAT_DATA_REL_RO:
4064 case SECCAT_DATA_REL_RO_LOCAL:
4065 prefix = one_only ? ".ld" : ".ldata";
4068 prefix = one_only ? ".lb" : ".lbss";
4071 case SECCAT_RODATA_MERGE_STR:
4072 case SECCAT_RODATA_MERGE_STR_INIT:
4073 case SECCAT_RODATA_MERGE_CONST:
4074 prefix = one_only ? ".lr" : ".lrodata";
4076 case SECCAT_SRODATA:
4083 /* We don't split these for medium model. Place them into
4084 default sections and hope for best. */
4086 case SECCAT_EMUTLS_VAR:
4087 prefix = targetm.emutls.var_section;
4089 case SECCAT_EMUTLS_TMPL:
4090 prefix = targetm.emutls.tmpl_section;
4095 const char *name, *linkonce;
4098 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4099 name = targetm.strip_name_encoding (name);
4101 /* If we're using one_only, then there needs to be a .gnu.linkonce
4102 prefix to the section name. */
4103 linkonce = one_only ? ".gnu.linkonce" : "";
4105 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4107 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4111 default_unique_section (decl, reloc);
4114 #ifdef COMMON_ASM_OP
4115 /* This says how to output assembler code to declare an
4116 uninitialized external linkage data object.
4118 For medium model x86-64 we need to use .largecomm opcode for
4121 x86_elf_aligned_common (FILE *file,
4122 const char *name, unsigned HOST_WIDE_INT size,
4125 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4126 && size > (unsigned int)ix86_section_threshold)
4127 fprintf (file, ".largecomm\t");
4129 fprintf (file, "%s", COMMON_ASM_OP);
4130 assemble_name (file, name);
4131 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
4132 size, align / BITS_PER_UNIT);
4136 /* Utility function for targets to use in implementing
4137 ASM_OUTPUT_ALIGNED_BSS. */
4140 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4141 const char *name, unsigned HOST_WIDE_INT size,
4144 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4145 && size > (unsigned int)ix86_section_threshold)
4146 switch_to_section (get_named_section (decl, ".lbss", 0));
4148 switch_to_section (bss_section);
4149 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4150 #ifdef ASM_DECLARE_OBJECT_NAME
4151 last_assemble_variable_decl = decl;
4152 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4154 /* Standard thing is just output label for the object. */
4155 ASM_OUTPUT_LABEL (file, name);
4156 #endif /* ASM_DECLARE_OBJECT_NAME */
4157 ASM_OUTPUT_SKIP (file, size ? size : 1);
4161 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4163 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4164 make the problem with not enough registers even worse. */
4165 #ifdef INSN_SCHEDULING
4167 flag_schedule_insns = 0;
4171 /* The Darwin libraries never set errno, so we might as well
4172 avoid calling them when that's the only reason we would. */
4173 flag_errno_math = 0;
4175 /* The default values of these switches depend on the TARGET_64BIT
4176 that is not known at this moment. Mark these values with 2 and
4177 let user the to override these. In case there is no command line option
4178 specifying them, we will set the defaults in override_options. */
4180 flag_omit_frame_pointer = 2;
4181 flag_pcc_struct_return = 2;
4182 flag_asynchronous_unwind_tables = 2;
4183 flag_vect_cost_model = 1;
4184 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4185 SUBTARGET_OPTIMIZATION_OPTIONS;
4189 /* Decide whether we can make a sibling call to a function. DECL is the
4190 declaration of the function being targeted by the call and EXP is the
4191 CALL_EXPR representing the call. */
4194 ix86_function_ok_for_sibcall (tree decl, tree exp)
4199 /* If we are generating position-independent code, we cannot sibcall
4200 optimize any indirect call, or a direct call to a global function,
4201 as the PLT requires %ebx be live. */
4202 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4209 func = TREE_TYPE (CALL_EXPR_FN (exp));
4210 if (POINTER_TYPE_P (func))
4211 func = TREE_TYPE (func);
4214 /* Check that the return value locations are the same. Like
4215 if we are returning floats on the 80387 register stack, we cannot
4216 make a sibcall from a function that doesn't return a float to a
4217 function that does or, conversely, from a function that does return
4218 a float to a function that doesn't; the necessary stack adjustment
4219 would not be executed. This is also the place we notice
4220 differences in the return value ABI. Note that it is ok for one
4221 of the functions to have void return type as long as the return
4222 value of the other is passed in a register. */
4223 a = ix86_function_value (TREE_TYPE (exp), func, false);
4224 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4226 if (STACK_REG_P (a) || STACK_REG_P (b))
4228 if (!rtx_equal_p (a, b))
4231 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4233 else if (!rtx_equal_p (a, b))
4236 /* If this call is indirect, we'll need to be able to use a call-clobbered
4237 register for the address of the target function. Make sure that all
4238 such registers are not used for passing parameters. */
4239 if (!decl && !TARGET_64BIT)
4243 /* We're looking at the CALL_EXPR, we need the type of the function. */
4244 type = CALL_EXPR_FN (exp); /* pointer expression */
4245 type = TREE_TYPE (type); /* pointer type */
4246 type = TREE_TYPE (type); /* function type */
4248 if (ix86_function_regparm (type, NULL) >= 3)
4250 /* ??? Need to count the actual number of registers to be used,
4251 not the possible number of registers. Fix later. */
4256 /* Dllimport'd functions are also called indirectly. */
4257 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4259 && decl && DECL_DLLIMPORT_P (decl)
4260 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4263 /* If we need to align the outgoing stack, then sibcalling would
4264 unalign the stack, which may break the called function. */
4265 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4268 /* Otherwise okay. That also includes certain types of indirect calls. */
4272 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4273 calling convention attributes;
4274 arguments as in struct attribute_spec.handler. */
4277 ix86_handle_cconv_attribute (tree *node, tree name,
4279 int flags ATTRIBUTE_UNUSED,
4282 if (TREE_CODE (*node) != FUNCTION_TYPE
4283 && TREE_CODE (*node) != METHOD_TYPE
4284 && TREE_CODE (*node) != FIELD_DECL
4285 && TREE_CODE (*node) != TYPE_DECL)
4287 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4289 *no_add_attrs = true;
4293 /* Can combine regparm with all attributes but fastcall. */
4294 if (is_attribute_p ("regparm", name))
4298 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4300 error ("fastcall and regparm attributes are not compatible");
4303 cst = TREE_VALUE (args);
4304 if (TREE_CODE (cst) != INTEGER_CST)
4306 warning (OPT_Wattributes,
4307 "%qE attribute requires an integer constant argument",
4309 *no_add_attrs = true;
4311 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4313 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4315 *no_add_attrs = true;
4323 /* Do not warn when emulating the MS ABI. */
4324 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4325 warning (OPT_Wattributes, "%qE attribute ignored",
4327 *no_add_attrs = true;
4331 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4332 if (is_attribute_p ("fastcall", name))
4334 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4336 error ("fastcall and cdecl attributes are not compatible");
4338 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4340 error ("fastcall and stdcall attributes are not compatible");
4342 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4344 error ("fastcall and regparm attributes are not compatible");
4348 /* Can combine stdcall with fastcall (redundant), regparm and
4350 else if (is_attribute_p ("stdcall", name))
4352 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4354 error ("stdcall and cdecl attributes are not compatible");
4356 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4358 error ("stdcall and fastcall attributes are not compatible");
4362 /* Can combine cdecl with regparm and sseregparm. */
4363 else if (is_attribute_p ("cdecl", name))
4365 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4367 error ("stdcall and cdecl attributes are not compatible");
4369 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4371 error ("fastcall and cdecl attributes are not compatible");
4375 /* Can combine sseregparm with all attributes. */
4380 /* Return 0 if the attributes for two types are incompatible, 1 if they
4381 are compatible, and 2 if they are nearly compatible (which causes a
4382 warning to be generated). */
4385 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4387 /* Check for mismatch of non-default calling convention. */
4388 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4390 if (TREE_CODE (type1) != FUNCTION_TYPE
4391 && TREE_CODE (type1) != METHOD_TYPE)
4394 /* Check for mismatched fastcall/regparm types. */
4395 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4396 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4397 || (ix86_function_regparm (type1, NULL)
4398 != ix86_function_regparm (type2, NULL)))
4401 /* Check for mismatched sseregparm types. */
4402 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4403 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4406 /* Check for mismatched return types (cdecl vs stdcall). */
4407 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4408 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4414 /* Return the regparm value for a function with the indicated TYPE and DECL.
4415 DECL may be NULL when calling function indirectly
4416 or considering a libcall. */
4419 ix86_function_regparm (const_tree type, const_tree decl)
4424 static bool error_issued;
4427 return (ix86_function_type_abi (type) == SYSV_ABI
4428 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4430 regparm = ix86_regparm;
4431 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4435 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4437 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4439 /* We can't use regparm(3) for nested functions because
4440 these pass static chain pointer in %ecx register. */
4441 if (!error_issued && regparm == 3
4442 && decl_function_context (decl)
4443 && !DECL_NO_STATIC_CHAIN (decl))
4445 error ("nested functions are limited to 2 register parameters");
4446 error_issued = true;
4454 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4457 /* Use register calling convention for local functions when possible. */
4459 && TREE_CODE (decl) == FUNCTION_DECL
4463 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4464 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4467 int local_regparm, globals = 0, regno;
4470 /* Make sure no regparm register is taken by a
4471 fixed register variable. */
4472 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4473 if (fixed_regs[local_regparm])
4476 /* We can't use regparm(3) for nested functions as these use
4477 static chain pointer in third argument. */
4478 if (local_regparm == 3
4479 && decl_function_context (decl)
4480 && !DECL_NO_STATIC_CHAIN (decl))
4483 /* If the function realigns its stackpointer, the prologue will
4484 clobber %ecx. If we've already generated code for the callee,
4485 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4486 scanning the attributes for the self-realigning property. */
4487 f = DECL_STRUCT_FUNCTION (decl);
4488 /* Since current internal arg pointer won't conflict with
4489 parameter passing regs, so no need to change stack
4490 realignment and adjust regparm number.
4492 Each fixed register usage increases register pressure,
4493 so less registers should be used for argument passing.
4494 This functionality can be overriden by an explicit
4496 for (regno = 0; regno <= DI_REG; regno++)
4497 if (fixed_regs[regno])
4501 = globals < local_regparm ? local_regparm - globals : 0;
4503 if (local_regparm > regparm)
4504 regparm = local_regparm;
4511 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4512 DFmode (2) arguments in SSE registers for a function with the
4513 indicated TYPE and DECL. DECL may be NULL when calling function
4514 indirectly or considering a libcall. Otherwise return 0. */
4517 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4519 gcc_assert (!TARGET_64BIT);
4521 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4522 by the sseregparm attribute. */
4523 if (TARGET_SSEREGPARM
4524 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4531 error ("Calling %qD with attribute sseregparm without "
4532 "SSE/SSE2 enabled", decl);
4534 error ("Calling %qT with attribute sseregparm without "
4535 "SSE/SSE2 enabled", type);
4543 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4544 (and DFmode for SSE2) arguments in SSE registers. */
4545 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4547 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4548 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4550 return TARGET_SSE2 ? 2 : 1;
4556 /* Return true if EAX is live at the start of the function. Used by
4557 ix86_expand_prologue to determine if we need special help before
4558 calling allocate_stack_worker. */
4561 ix86_eax_live_at_start_p (void)
4563 /* Cheat. Don't bother working forward from ix86_function_regparm
4564 to the function type to whether an actual argument is located in
4565 eax. Instead just look at cfg info, which is still close enough
4566 to correct at this point. This gives false positives for broken
4567 functions that might use uninitialized data that happens to be
4568 allocated in eax, but who cares? */
4569 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4572 /* Value is the number of bytes of arguments automatically
4573 popped when returning from a subroutine call.
4574 FUNDECL is the declaration node of the function (as a tree),
4575 FUNTYPE is the data type of the function (as a tree),
4576 or for a library call it is an identifier node for the subroutine name.
4577 SIZE is the number of bytes of arguments passed on the stack.
4579 On the 80386, the RTD insn may be used to pop them if the number
4580 of args is fixed, but if the number is variable then the caller
4581 must pop them all. RTD can't be used for library calls now
4582 because the library is compiled with the Unix compiler.
4583 Use of RTD is a selectable option, since it is incompatible with
4584 standard Unix calling sequences. If the option is not selected,
4585 the caller must always pop the args.
4587 The attribute stdcall is equivalent to RTD on a per module basis. */
4590 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4594 /* None of the 64-bit ABIs pop arguments. */
4598 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4600 /* Cdecl functions override -mrtd, and never pop the stack. */
4601 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4603 /* Stdcall and fastcall functions will pop the stack if not
4605 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4606 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4609 if (rtd && ! stdarg_p (funtype))
4613 /* Lose any fake structure return argument if it is passed on the stack. */
4614 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4615 && !KEEP_AGGREGATE_RETURN_POINTER)
4617 int nregs = ix86_function_regparm (funtype, fundecl);
4619 return GET_MODE_SIZE (Pmode);
4625 /* Argument support functions. */
4627 /* Return true when register may be used to pass function parameters. */
4629 ix86_function_arg_regno_p (int regno)
4632 const int *parm_regs;
4637 return (regno < REGPARM_MAX
4638 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4640 return (regno < REGPARM_MAX
4641 || (TARGET_MMX && MMX_REGNO_P (regno)
4642 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4643 || (TARGET_SSE && SSE_REGNO_P (regno)
4644 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4649 if (SSE_REGNO_P (regno) && TARGET_SSE)
4654 if (TARGET_SSE && SSE_REGNO_P (regno)
4655 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4659 /* TODO: The function should depend on current function ABI but
4660 builtins.c would need updating then. Therefore we use the
4663 /* RAX is used as hidden argument to va_arg functions. */
4664 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4667 if (ix86_abi == MS_ABI)
4668 parm_regs = x86_64_ms_abi_int_parameter_registers;
4670 parm_regs = x86_64_int_parameter_registers;
4671 for (i = 0; i < (ix86_abi == MS_ABI
4672 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4673 if (regno == parm_regs[i])
4678 /* Return if we do not know how to pass TYPE solely in registers. */
4681 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4683 if (must_pass_in_stack_var_size_or_pad (mode, type))
4686 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4687 The layout_type routine is crafty and tries to trick us into passing
4688 currently unsupported vector types on the stack by using TImode. */
4689 return (!TARGET_64BIT && mode == TImode
4690 && type && TREE_CODE (type) != VECTOR_TYPE);
4693 /* It returns the size, in bytes, of the area reserved for arguments passed
4694 in registers for the function represented by fndecl dependent to the used
4697 ix86_reg_parm_stack_space (const_tree fndecl)
4699 enum calling_abi call_abi = SYSV_ABI;
4700 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4701 call_abi = ix86_function_abi (fndecl);
4703 call_abi = ix86_function_type_abi (fndecl);
4704 if (call_abi == MS_ABI)
4709 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4712 ix86_function_type_abi (const_tree fntype)
4714 if (TARGET_64BIT && fntype != NULL)
4716 enum calling_abi abi = ix86_abi;
4717 if (abi == SYSV_ABI)
4719 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4722 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4729 static enum calling_abi
4730 ix86_function_abi (const_tree fndecl)
4734 return ix86_function_type_abi (TREE_TYPE (fndecl));
4737 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4740 ix86_cfun_abi (void)
4742 if (! cfun || ! TARGET_64BIT)
4744 return cfun->machine->call_abi;
4748 extern void init_regs (void);
4750 /* Implementation of call abi switching target hook. Specific to FNDECL
4751 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4752 for more details. */
4754 ix86_call_abi_override (const_tree fndecl)
4756 if (fndecl == NULL_TREE)
4757 cfun->machine->call_abi = ix86_abi;
4759 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4762 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4763 re-initialization of init_regs each time we switch function context since
4764 this is needed only during RTL expansion. */
4766 ix86_maybe_switch_abi (void)
4769 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4773 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4774 for a call to a function whose data type is FNTYPE.
4775 For a library call, FNTYPE is 0. */
4778 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4779 tree fntype, /* tree ptr for function decl */
4780 rtx libname, /* SYMBOL_REF of library name or 0 */
4783 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4784 memset (cum, 0, sizeof (*cum));
4787 cum->call_abi = ix86_function_abi (fndecl);
4789 cum->call_abi = ix86_function_type_abi (fntype);
4790 /* Set up the number of registers to use for passing arguments. */
4792 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4793 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4794 cum->nregs = ix86_regparm;
4797 if (cum->call_abi != ix86_abi)
4798 cum->nregs = (ix86_abi != SYSV_ABI
4799 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4803 cum->sse_nregs = SSE_REGPARM_MAX;
4806 if (cum->call_abi != ix86_abi)
4807 cum->sse_nregs = (ix86_abi != SYSV_ABI
4808 ? X86_64_SSE_REGPARM_MAX
4809 : X86_64_MS_SSE_REGPARM_MAX);
4813 cum->mmx_nregs = MMX_REGPARM_MAX;
4814 cum->warn_avx = true;
4815 cum->warn_sse = true;
4816 cum->warn_mmx = true;
4818 /* Because type might mismatch in between caller and callee, we need to
4819 use actual type of function for local calls.
4820 FIXME: cgraph_analyze can be told to actually record if function uses
4821 va_start so for local functions maybe_vaarg can be made aggressive
4823 FIXME: once typesytem is fixed, we won't need this code anymore. */
4825 fntype = TREE_TYPE (fndecl);
4826 cum->maybe_vaarg = (fntype
4827 ? (!prototype_p (fntype) || stdarg_p (fntype))
4832 /* If there are variable arguments, then we won't pass anything
4833 in registers in 32-bit mode. */
4834 if (stdarg_p (fntype))
4845 /* Use ecx and edx registers if function has fastcall attribute,
4846 else look for regparm information. */
4849 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4855 cum->nregs = ix86_function_regparm (fntype, fndecl);
4858 /* Set up the number of SSE registers used for passing SFmode
4859 and DFmode arguments. Warn for mismatching ABI. */
4860 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4864 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4865 But in the case of vector types, it is some vector mode.
4867 When we have only some of our vector isa extensions enabled, then there
4868 are some modes for which vector_mode_supported_p is false. For these
4869 modes, the generic vector support in gcc will choose some non-vector mode
4870 in order to implement the type. By computing the natural mode, we'll
4871 select the proper ABI location for the operand and not depend on whatever
4872 the middle-end decides to do with these vector types.
4874 The midde-end can't deal with the vector types > 16 bytes. In this
4875 case, we return the original mode and warn ABI change if CUM isn't
4878 static enum machine_mode
4879 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4881 enum machine_mode mode = TYPE_MODE (type);
4883 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4885 HOST_WIDE_INT size = int_size_in_bytes (type);
4886 if ((size == 8 || size == 16 || size == 32)
4887 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4888 && TYPE_VECTOR_SUBPARTS (type) > 1)
4890 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4892 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4893 mode = MIN_MODE_VECTOR_FLOAT;
4895 mode = MIN_MODE_VECTOR_INT;
4897 /* Get the mode which has this inner mode and number of units. */
4898 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4899 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4900 && GET_MODE_INNER (mode) == innermode)
4902 if (size == 32 && !TARGET_AVX)
4904 static bool warnedavx;
4911 warning (0, "AVX vector argument without AVX "
4912 "enabled changes the ABI");
4914 return TYPE_MODE (type);
4927 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4928 this may not agree with the mode that the type system has chosen for the
4929 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4930 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4933 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4938 if (orig_mode != BLKmode)
4939 tmp = gen_rtx_REG (orig_mode, regno);
4942 tmp = gen_rtx_REG (mode, regno);
4943 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4944 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4950 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4951 of this code is to classify each 8bytes of incoming argument by the register
4952 class and assign registers accordingly. */
4954 /* Return the union class of CLASS1 and CLASS2.
4955 See the x86-64 PS ABI for details. */
4957 static enum x86_64_reg_class
4958 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4960 /* Rule #1: If both classes are equal, this is the resulting class. */
4961 if (class1 == class2)
4964 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4966 if (class1 == X86_64_NO_CLASS)
4968 if (class2 == X86_64_NO_CLASS)
4971 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4972 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4973 return X86_64_MEMORY_CLASS;
4975 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4976 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4977 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4978 return X86_64_INTEGERSI_CLASS;
4979 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4980 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4981 return X86_64_INTEGER_CLASS;
4983 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4985 if (class1 == X86_64_X87_CLASS
4986 || class1 == X86_64_X87UP_CLASS
4987 || class1 == X86_64_COMPLEX_X87_CLASS
4988 || class2 == X86_64_X87_CLASS
4989 || class2 == X86_64_X87UP_CLASS
4990 || class2 == X86_64_COMPLEX_X87_CLASS)
4991 return X86_64_MEMORY_CLASS;
4993 /* Rule #6: Otherwise class SSE is used. */
4994 return X86_64_SSE_CLASS;
4997 /* Classify the argument of type TYPE and mode MODE.
4998 CLASSES will be filled by the register class used to pass each word
4999 of the operand. The number of words is returned. In case the parameter
5000 should be passed in memory, 0 is returned. As a special case for zero
5001 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5003 BIT_OFFSET is used internally for handling records and specifies offset
5004 of the offset in bits modulo 256 to avoid overflow cases.
5006 See the x86-64 PS ABI for details.
5010 classify_argument (enum machine_mode mode, const_tree type,
5011 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5013 HOST_WIDE_INT bytes =
5014 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5015 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5017 /* Variable sized entities are always passed/returned in memory. */
5021 if (mode != VOIDmode
5022 && targetm.calls.must_pass_in_stack (mode, type))
5025 if (type && AGGREGATE_TYPE_P (type))
5029 enum x86_64_reg_class subclasses[MAX_CLASSES];
5031 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5035 for (i = 0; i < words; i++)
5036 classes[i] = X86_64_NO_CLASS;
5038 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5039 signalize memory class, so handle it as special case. */
5042 classes[0] = X86_64_NO_CLASS;
5046 /* Classify each field of record and merge classes. */
5047 switch (TREE_CODE (type))
5050 /* And now merge the fields of structure. */
5051 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5053 if (TREE_CODE (field) == FIELD_DECL)
5057 if (TREE_TYPE (field) == error_mark_node)
5060 /* Bitfields are always classified as integer. Handle them
5061 early, since later code would consider them to be
5062 misaligned integers. */
5063 if (DECL_BIT_FIELD (field))
5065 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5066 i < ((int_bit_position (field) + (bit_offset % 64))
5067 + tree_low_cst (DECL_SIZE (field), 0)
5070 merge_classes (X86_64_INTEGER_CLASS,
5077 type = TREE_TYPE (field);
5079 /* Flexible array member is ignored. */
5080 if (TYPE_MODE (type) == BLKmode
5081 && TREE_CODE (type) == ARRAY_TYPE
5082 && TYPE_SIZE (type) == NULL_TREE
5083 && TYPE_DOMAIN (type) != NULL_TREE
5084 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5089 if (!warned && warn_psabi)
5092 inform (input_location,
5093 "The ABI of passing struct with"
5094 " a flexible array member has"
5095 " changed in GCC 4.4");
5099 num = classify_argument (TYPE_MODE (type), type,
5101 (int_bit_position (field)
5102 + bit_offset) % 256);
5105 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5106 for (i = 0; i < num && (i + pos) < words; i++)
5108 merge_classes (subclasses[i], classes[i + pos]);
5115 /* Arrays are handled as small records. */
5118 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5119 TREE_TYPE (type), subclasses, bit_offset);
5123 /* The partial classes are now full classes. */
5124 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5125 subclasses[0] = X86_64_SSE_CLASS;
5126 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5127 && !((bit_offset % 64) == 0 && bytes == 4))
5128 subclasses[0] = X86_64_INTEGER_CLASS;
5130 for (i = 0; i < words; i++)
5131 classes[i] = subclasses[i % num];
5136 case QUAL_UNION_TYPE:
5137 /* Unions are similar to RECORD_TYPE but offset is always 0.
5139 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5141 if (TREE_CODE (field) == FIELD_DECL)
5145 if (TREE_TYPE (field) == error_mark_node)
5148 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5149 TREE_TYPE (field), subclasses,
5153 for (i = 0; i < num; i++)
5154 classes[i] = merge_classes (subclasses[i], classes[i]);
5165 /* When size > 16 bytes, if the first one isn't
5166 X86_64_SSE_CLASS or any other ones aren't
5167 X86_64_SSEUP_CLASS, everything should be passed in
5169 if (classes[0] != X86_64_SSE_CLASS)
5172 for (i = 1; i < words; i++)
5173 if (classes[i] != X86_64_SSEUP_CLASS)
5177 /* Final merger cleanup. */
5178 for (i = 0; i < words; i++)
5180 /* If one class is MEMORY, everything should be passed in
5182 if (classes[i] == X86_64_MEMORY_CLASS)
5185 /* The X86_64_SSEUP_CLASS should be always preceded by
5186 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5187 if (classes[i] == X86_64_SSEUP_CLASS
5188 && classes[i - 1] != X86_64_SSE_CLASS
5189 && classes[i - 1] != X86_64_SSEUP_CLASS)
5191 /* The first one should never be X86_64_SSEUP_CLASS. */
5192 gcc_assert (i != 0);
5193 classes[i] = X86_64_SSE_CLASS;
5196 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5197 everything should be passed in memory. */
5198 if (classes[i] == X86_64_X87UP_CLASS
5199 && (classes[i - 1] != X86_64_X87_CLASS))
5203 /* The first one should never be X86_64_X87UP_CLASS. */
5204 gcc_assert (i != 0);
5205 if (!warned && warn_psabi)
5208 inform (input_location,
5209 "The ABI of passing union with long double"
5210 " has changed in GCC 4.4");
5218 /* Compute alignment needed. We align all types to natural boundaries with
5219 exception of XFmode that is aligned to 64bits. */
5220 if (mode != VOIDmode && mode != BLKmode)
5222 int mode_alignment = GET_MODE_BITSIZE (mode);
5225 mode_alignment = 128;
5226 else if (mode == XCmode)
5227 mode_alignment = 256;
5228 if (COMPLEX_MODE_P (mode))
5229 mode_alignment /= 2;
5230 /* Misaligned fields are always returned in memory. */
5231 if (bit_offset % mode_alignment)
5235 /* for V1xx modes, just use the base mode */
5236 if (VECTOR_MODE_P (mode) && mode != V1DImode
5237 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5238 mode = GET_MODE_INNER (mode);
5240 /* Classification of atomic types. */
5245 classes[0] = X86_64_SSE_CLASS;
5248 classes[0] = X86_64_SSE_CLASS;
5249 classes[1] = X86_64_SSEUP_CLASS;
5259 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5263 classes[0] = X86_64_INTEGERSI_CLASS;
5266 else if (size <= 64)
5268 classes[0] = X86_64_INTEGER_CLASS;
5271 else if (size <= 64+32)
5273 classes[0] = X86_64_INTEGER_CLASS;
5274 classes[1] = X86_64_INTEGERSI_CLASS;
5277 else if (size <= 64+64)
5279 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5287 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5291 /* OImode shouldn't be used directly. */
5296 if (!(bit_offset % 64))
5297 classes[0] = X86_64_SSESF_CLASS;
5299 classes[0] = X86_64_SSE_CLASS;
5302 classes[0] = X86_64_SSEDF_CLASS;
5305 classes[0] = X86_64_X87_CLASS;
5306 classes[1] = X86_64_X87UP_CLASS;
5309 classes[0] = X86_64_SSE_CLASS;
5310 classes[1] = X86_64_SSEUP_CLASS;
5313 classes[0] = X86_64_SSE_CLASS;
5314 if (!(bit_offset % 64))
5320 if (!warned && warn_psabi)
5323 inform (input_location,
5324 "The ABI of passing structure with complex float"
5325 " member has changed in GCC 4.4");
5327 classes[1] = X86_64_SSESF_CLASS;
5331 classes[0] = X86_64_SSEDF_CLASS;
5332 classes[1] = X86_64_SSEDF_CLASS;
5335 classes[0] = X86_64_COMPLEX_X87_CLASS;
5338 /* This modes is larger than 16 bytes. */
5346 classes[0] = X86_64_SSE_CLASS;
5347 classes[1] = X86_64_SSEUP_CLASS;
5348 classes[2] = X86_64_SSEUP_CLASS;
5349 classes[3] = X86_64_SSEUP_CLASS;
5357 classes[0] = X86_64_SSE_CLASS;
5358 classes[1] = X86_64_SSEUP_CLASS;
5365 classes[0] = X86_64_SSE_CLASS;
5371 gcc_assert (VECTOR_MODE_P (mode));
5376 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5378 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5379 classes[0] = X86_64_INTEGERSI_CLASS;
5381 classes[0] = X86_64_INTEGER_CLASS;
5382 classes[1] = X86_64_INTEGER_CLASS;
5383 return 1 + (bytes > 8);
5387 /* Examine the argument and return set number of register required in each
5388 class. Return 0 iff parameter should be passed in memory. */
5390 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5391 int *int_nregs, int *sse_nregs)
5393 enum x86_64_reg_class regclass[MAX_CLASSES];
5394 int n = classify_argument (mode, type, regclass, 0);
5400 for (n--; n >= 0; n--)
5401 switch (regclass[n])
5403 case X86_64_INTEGER_CLASS:
5404 case X86_64_INTEGERSI_CLASS:
5407 case X86_64_SSE_CLASS:
5408 case X86_64_SSESF_CLASS:
5409 case X86_64_SSEDF_CLASS:
5412 case X86_64_NO_CLASS:
5413 case X86_64_SSEUP_CLASS:
5415 case X86_64_X87_CLASS:
5416 case X86_64_X87UP_CLASS:
5420 case X86_64_COMPLEX_X87_CLASS:
5421 return in_return ? 2 : 0;
5422 case X86_64_MEMORY_CLASS:
5428 /* Construct container for the argument used by GCC interface. See
5429 FUNCTION_ARG for the detailed description. */
5432 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5433 const_tree type, int in_return, int nintregs, int nsseregs,
5434 const int *intreg, int sse_regno)
5436 /* The following variables hold the static issued_error state. */
5437 static bool issued_sse_arg_error;
5438 static bool issued_sse_ret_error;
5439 static bool issued_x87_ret_error;
5441 enum machine_mode tmpmode;
5443 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5444 enum x86_64_reg_class regclass[MAX_CLASSES];
5448 int needed_sseregs, needed_intregs;
5449 rtx exp[MAX_CLASSES];
5452 n = classify_argument (mode, type, regclass, 0);
5455 if (!examine_argument (mode, type, in_return, &needed_intregs,
5458 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5461 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5462 some less clueful developer tries to use floating-point anyway. */
5463 if (needed_sseregs && !TARGET_SSE)
5467 if (!issued_sse_ret_error)
5469 error ("SSE register return with SSE disabled");
5470 issued_sse_ret_error = true;
5473 else if (!issued_sse_arg_error)
5475 error ("SSE register argument with SSE disabled");
5476 issued_sse_arg_error = true;
5481 /* Likewise, error if the ABI requires us to return values in the
5482 x87 registers and the user specified -mno-80387. */
5483 if (!TARGET_80387 && in_return)
5484 for (i = 0; i < n; i++)
5485 if (regclass[i] == X86_64_X87_CLASS
5486 || regclass[i] == X86_64_X87UP_CLASS
5487 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5489 if (!issued_x87_ret_error)
5491 error ("x87 register return with x87 disabled");
5492 issued_x87_ret_error = true;
5497 /* First construct simple cases. Avoid SCmode, since we want to use
5498 single register to pass this type. */
5499 if (n == 1 && mode != SCmode)
5500 switch (regclass[0])
5502 case X86_64_INTEGER_CLASS:
5503 case X86_64_INTEGERSI_CLASS:
5504 return gen_rtx_REG (mode, intreg[0]);
5505 case X86_64_SSE_CLASS:
5506 case X86_64_SSESF_CLASS:
5507 case X86_64_SSEDF_CLASS:
5508 if (mode != BLKmode)
5509 return gen_reg_or_parallel (mode, orig_mode,
5510 SSE_REGNO (sse_regno));
5512 case X86_64_X87_CLASS:
5513 case X86_64_COMPLEX_X87_CLASS:
5514 return gen_rtx_REG (mode, FIRST_STACK_REG);
5515 case X86_64_NO_CLASS:
5516 /* Zero sized array, struct or class. */
5521 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5522 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5523 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5525 && regclass[0] == X86_64_SSE_CLASS
5526 && regclass[1] == X86_64_SSEUP_CLASS
5527 && regclass[2] == X86_64_SSEUP_CLASS
5528 && regclass[3] == X86_64_SSEUP_CLASS
5530 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5533 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5534 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5535 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5536 && regclass[1] == X86_64_INTEGER_CLASS
5537 && (mode == CDImode || mode == TImode || mode == TFmode)
5538 && intreg[0] + 1 == intreg[1])
5539 return gen_rtx_REG (mode, intreg[0]);
5541 /* Otherwise figure out the entries of the PARALLEL. */
5542 for (i = 0; i < n; i++)
5546 switch (regclass[i])
5548 case X86_64_NO_CLASS:
5550 case X86_64_INTEGER_CLASS:
5551 case X86_64_INTEGERSI_CLASS:
5552 /* Merge TImodes on aligned occasions here too. */
5553 if (i * 8 + 8 > bytes)
5554 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5555 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5559 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5560 if (tmpmode == BLKmode)
5562 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5563 gen_rtx_REG (tmpmode, *intreg),
5567 case X86_64_SSESF_CLASS:
5568 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5569 gen_rtx_REG (SFmode,
5570 SSE_REGNO (sse_regno)),
5574 case X86_64_SSEDF_CLASS:
5575 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5576 gen_rtx_REG (DFmode,
5577 SSE_REGNO (sse_regno)),
5581 case X86_64_SSE_CLASS:
5589 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5599 && regclass[1] == X86_64_SSEUP_CLASS
5600 && regclass[2] == X86_64_SSEUP_CLASS
5601 && regclass[3] == X86_64_SSEUP_CLASS);
5608 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5609 gen_rtx_REG (tmpmode,
5610 SSE_REGNO (sse_regno)),
5619 /* Empty aligned struct, union or class. */
5623 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5624 for (i = 0; i < nexps; i++)
5625 XVECEXP (ret, 0, i) = exp [i];
5629 /* Update the data in CUM to advance over an argument of mode MODE
5630 and data type TYPE. (TYPE is null for libcalls where that information
5631 may not be available.) */
5634 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5635 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5651 cum->words += words;
5652 cum->nregs -= words;
5653 cum->regno += words;
5655 if (cum->nregs <= 0)
5663 /* OImode shouldn't be used directly. */
5667 if (cum->float_in_sse < 2)
5670 if (cum->float_in_sse < 1)
5687 if (!type || !AGGREGATE_TYPE_P (type))
5689 cum->sse_words += words;
5690 cum->sse_nregs -= 1;
5691 cum->sse_regno += 1;
5692 if (cum->sse_nregs <= 0)
5705 if (!type || !AGGREGATE_TYPE_P (type))
5707 cum->mmx_words += words;
5708 cum->mmx_nregs -= 1;
5709 cum->mmx_regno += 1;
5710 if (cum->mmx_nregs <= 0)
5721 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5722 tree type, HOST_WIDE_INT words, int named)
5724 int int_nregs, sse_nregs;
5726 /* Unnamed 256bit vector mode parameters are passed on stack. */
5727 if (!named && VALID_AVX256_REG_MODE (mode))
5730 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5731 cum->words += words;
5732 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5734 cum->nregs -= int_nregs;
5735 cum->sse_nregs -= sse_nregs;
5736 cum->regno += int_nregs;
5737 cum->sse_regno += sse_nregs;
5740 cum->words += words;
5744 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5745 HOST_WIDE_INT words)
5747 /* Otherwise, this should be passed indirect. */
5748 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5750 cum->words += words;
5759 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5760 tree type, int named)
5762 HOST_WIDE_INT bytes, words;
5764 if (mode == BLKmode)
5765 bytes = int_size_in_bytes (type);
5767 bytes = GET_MODE_SIZE (mode);
5768 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5771 mode = type_natural_mode (type, NULL);
5773 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5774 function_arg_advance_ms_64 (cum, bytes, words);
5775 else if (TARGET_64BIT)
5776 function_arg_advance_64 (cum, mode, type, words, named);
5778 function_arg_advance_32 (cum, mode, type, bytes, words);
5781 /* Define where to put the arguments to a function.
5782 Value is zero to push the argument on the stack,
5783 or a hard register in which to store the argument.
5785 MODE is the argument's machine mode.
5786 TYPE is the data type of the argument (as a tree).
5787 This is null for libcalls where that information may
5789 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5790 the preceding args and about the function being called.
5791 NAMED is nonzero if this argument is a named parameter
5792 (otherwise it is an extra parameter matching an ellipsis). */
5795 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5796 enum machine_mode orig_mode, tree type,
5797 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5799 static bool warnedsse, warnedmmx;
5801 /* Avoid the AL settings for the Unix64 ABI. */
5802 if (mode == VOIDmode)
5818 if (words <= cum->nregs)
5820 int regno = cum->regno;
5822 /* Fastcall allocates the first two DWORD (SImode) or
5823 smaller arguments to ECX and EDX if it isn't an
5829 || (type && AGGREGATE_TYPE_P (type)))
5832 /* ECX not EAX is the first allocated register. */
5833 if (regno == AX_REG)
5836 return gen_rtx_REG (mode, regno);
5841 if (cum->float_in_sse < 2)
5844 if (cum->float_in_sse < 1)
5848 /* In 32bit, we pass TImode in xmm registers. */
5855 if (!type || !AGGREGATE_TYPE_P (type))
5857 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5860 warning (0, "SSE vector argument without SSE enabled "
5864 return gen_reg_or_parallel (mode, orig_mode,
5865 cum->sse_regno + FIRST_SSE_REG);
5870 /* OImode shouldn't be used directly. */
5879 if (!type || !AGGREGATE_TYPE_P (type))
5882 return gen_reg_or_parallel (mode, orig_mode,
5883 cum->sse_regno + FIRST_SSE_REG);
5892 if (!type || !AGGREGATE_TYPE_P (type))
5894 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5897 warning (0, "MMX vector argument without MMX enabled "
5901 return gen_reg_or_parallel (mode, orig_mode,
5902 cum->mmx_regno + FIRST_MMX_REG);
5911 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5912 enum machine_mode orig_mode, tree type, int named)
5914 /* Handle a hidden AL argument containing number of registers
5915 for varargs x86-64 functions. */
5916 if (mode == VOIDmode)
5917 return GEN_INT (cum->maybe_vaarg
5918 ? (cum->sse_nregs < 0
5919 ? (cum->call_abi == ix86_abi
5921 : (ix86_abi != SYSV_ABI
5922 ? X86_64_SSE_REGPARM_MAX
5923 : X86_64_MS_SSE_REGPARM_MAX))
5938 /* Unnamed 256bit vector mode parameters are passed on stack. */
5944 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5946 &x86_64_int_parameter_registers [cum->regno],
5951 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5952 enum machine_mode orig_mode, int named,
5953 HOST_WIDE_INT bytes)
5957 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5958 We use value of -2 to specify that current function call is MSABI. */
5959 if (mode == VOIDmode)
5960 return GEN_INT (-2);
5962 /* If we've run out of registers, it goes on the stack. */
5963 if (cum->nregs == 0)
5966 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5968 /* Only floating point modes are passed in anything but integer regs. */
5969 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5972 regno = cum->regno + FIRST_SSE_REG;
5977 /* Unnamed floating parameters are passed in both the
5978 SSE and integer registers. */
5979 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5980 t2 = gen_rtx_REG (mode, regno);
5981 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5982 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5983 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5986 /* Handle aggregated types passed in register. */
5987 if (orig_mode == BLKmode)
5989 if (bytes > 0 && bytes <= 8)
5990 mode = (bytes > 4 ? DImode : SImode);
5991 if (mode == BLKmode)
5995 return gen_reg_or_parallel (mode, orig_mode, regno);
5999 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6000 tree type, int named)
6002 enum machine_mode mode = omode;
6003 HOST_WIDE_INT bytes, words;
6005 if (mode == BLKmode)
6006 bytes = int_size_in_bytes (type);
6008 bytes = GET_MODE_SIZE (mode);
6009 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6011 /* To simplify the code below, represent vector types with a vector mode
6012 even if MMX/SSE are not active. */
6013 if (type && TREE_CODE (type) == VECTOR_TYPE)
6014 mode = type_natural_mode (type, cum);
6016 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6017 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6018 else if (TARGET_64BIT)
6019 return function_arg_64 (cum, mode, omode, type, named);
6021 return function_arg_32 (cum, mode, omode, type, bytes, words);
6024 /* A C expression that indicates when an argument must be passed by
6025 reference. If nonzero for an argument, a copy of that argument is
6026 made in memory and a pointer to the argument is passed instead of
6027 the argument itself. The pointer is passed in whatever way is
6028 appropriate for passing a pointer to that type. */
6031 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6032 enum machine_mode mode ATTRIBUTE_UNUSED,
6033 const_tree type, bool named ATTRIBUTE_UNUSED)
6035 /* See Windows x64 Software Convention. */
6036 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6038 int msize = (int) GET_MODE_SIZE (mode);
6041 /* Arrays are passed by reference. */
6042 if (TREE_CODE (type) == ARRAY_TYPE)
6045 if (AGGREGATE_TYPE_P (type))
6047 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6048 are passed by reference. */
6049 msize = int_size_in_bytes (type);
6053 /* __m128 is passed by reference. */
6055 case 1: case 2: case 4: case 8:
6061 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6067 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6070 contains_aligned_value_p (tree type)
6072 enum machine_mode mode = TYPE_MODE (type);
6073 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6077 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6079 if (TYPE_ALIGN (type) < 128)
6082 if (AGGREGATE_TYPE_P (type))
6084 /* Walk the aggregates recursively. */
6085 switch (TREE_CODE (type))
6089 case QUAL_UNION_TYPE:
6093 /* Walk all the structure fields. */
6094 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6096 if (TREE_CODE (field) == FIELD_DECL
6097 && contains_aligned_value_p (TREE_TYPE (field)))
6104 /* Just for use if some languages passes arrays by value. */
6105 if (contains_aligned_value_p (TREE_TYPE (type)))
6116 /* Gives the alignment boundary, in bits, of an argument with the
6117 specified mode and type. */
6120 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6125 /* Since canonical type is used for call, we convert it to
6126 canonical type if needed. */
6127 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6128 type = TYPE_CANONICAL (type);
6129 align = TYPE_ALIGN (type);
6132 align = GET_MODE_ALIGNMENT (mode);
6133 if (align < PARM_BOUNDARY)
6134 align = PARM_BOUNDARY;
6135 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6136 natural boundaries. */
6137 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6139 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6140 make an exception for SSE modes since these require 128bit
6143 The handling here differs from field_alignment. ICC aligns MMX
6144 arguments to 4 byte boundaries, while structure fields are aligned
6145 to 8 byte boundaries. */
6148 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6149 align = PARM_BOUNDARY;
6153 if (!contains_aligned_value_p (type))
6154 align = PARM_BOUNDARY;
6157 if (align > BIGGEST_ALIGNMENT)
6158 align = BIGGEST_ALIGNMENT;
6162 /* Return true if N is a possible register number of function value. */
6165 ix86_function_value_regno_p (int regno)
6172 case FIRST_FLOAT_REG:
6173 /* TODO: The function should depend on current function ABI but
6174 builtins.c would need updating then. Therefore we use the
6176 if (TARGET_64BIT && ix86_abi == MS_ABI)
6178 return TARGET_FLOAT_RETURNS_IN_80387;
6184 if (TARGET_MACHO || TARGET_64BIT)
6192 /* Define how to find the value returned by a function.
6193 VALTYPE is the data type of the value (as a tree).
6194 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6195 otherwise, FUNC is 0. */
6198 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6199 const_tree fntype, const_tree fn)
6203 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6204 we normally prevent this case when mmx is not available. However
6205 some ABIs may require the result to be returned like DImode. */
6206 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6207 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6209 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6210 we prevent this case when sse is not available. However some ABIs
6211 may require the result to be returned like integer TImode. */
6212 else if (mode == TImode
6213 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6214 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6216 /* 32-byte vector modes in %ymm0. */
6217 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6218 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6220 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6221 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6222 regno = FIRST_FLOAT_REG;
6224 /* Most things go in %eax. */
6227 /* Override FP return register with %xmm0 for local functions when
6228 SSE math is enabled or for functions with sseregparm attribute. */
6229 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6231 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6232 if ((sse_level >= 1 && mode == SFmode)
6233 || (sse_level == 2 && mode == DFmode))
6234 regno = FIRST_SSE_REG;
6237 /* OImode shouldn't be used directly. */
6238 gcc_assert (mode != OImode);
6240 return gen_rtx_REG (orig_mode, regno);
6244 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6249 /* Handle libcalls, which don't provide a type node. */
6250 if (valtype == NULL)
6262 return gen_rtx_REG (mode, FIRST_SSE_REG);
6265 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6269 return gen_rtx_REG (mode, AX_REG);
6273 ret = construct_container (mode, orig_mode, valtype, 1,
6274 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6275 x86_64_int_return_registers, 0);
6277 /* For zero sized structures, construct_container returns NULL, but we
6278 need to keep rest of compiler happy by returning meaningful value. */
6280 ret = gen_rtx_REG (orig_mode, AX_REG);
6286 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6288 unsigned int regno = AX_REG;
6292 switch (GET_MODE_SIZE (mode))
6295 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6296 && !COMPLEX_MODE_P (mode))
6297 regno = FIRST_SSE_REG;
6301 if (mode == SFmode || mode == DFmode)
6302 regno = FIRST_SSE_REG;
6308 return gen_rtx_REG (orig_mode, regno);
6312 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6313 enum machine_mode orig_mode, enum machine_mode mode)
6315 const_tree fn, fntype;
6318 if (fntype_or_decl && DECL_P (fntype_or_decl))
6319 fn = fntype_or_decl;
6320 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6322 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6323 return function_value_ms_64 (orig_mode, mode);
6324 else if (TARGET_64BIT)
6325 return function_value_64 (orig_mode, mode, valtype);
6327 return function_value_32 (orig_mode, mode, fntype, fn);
6331 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6332 bool outgoing ATTRIBUTE_UNUSED)
6334 enum machine_mode mode, orig_mode;
6336 orig_mode = TYPE_MODE (valtype);
6337 mode = type_natural_mode (valtype, NULL);
6338 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6342 ix86_libcall_value (enum machine_mode mode)
6344 return ix86_function_value_1 (NULL, NULL, mode, mode);
6347 /* Return true iff type is returned in memory. */
6349 static int ATTRIBUTE_UNUSED
6350 return_in_memory_32 (const_tree type, enum machine_mode mode)
6354 if (mode == BLKmode)
6357 size = int_size_in_bytes (type);
6359 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6362 if (VECTOR_MODE_P (mode) || mode == TImode)
6364 /* User-created vectors small enough to fit in EAX. */
6368 /* MMX/3dNow values are returned in MM0,
6369 except when it doesn't exits. */
6371 return (TARGET_MMX ? 0 : 1);
6373 /* SSE values are returned in XMM0, except when it doesn't exist. */
6375 return (TARGET_SSE ? 0 : 1);
6377 /* AVX values are returned in YMM0, except when it doesn't exist. */
6379 return TARGET_AVX ? 0 : 1;
6388 /* OImode shouldn't be used directly. */
6389 gcc_assert (mode != OImode);
6394 static int ATTRIBUTE_UNUSED
6395 return_in_memory_64 (const_tree type, enum machine_mode mode)
6397 int needed_intregs, needed_sseregs;
6398 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6401 static int ATTRIBUTE_UNUSED
6402 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6404 HOST_WIDE_INT size = int_size_in_bytes (type);
6406 /* __m128 is returned in xmm0. */
6407 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6408 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6411 /* Otherwise, the size must be exactly in [1248]. */
6412 return (size != 1 && size != 2 && size != 4 && size != 8);
6416 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6418 #ifdef SUBTARGET_RETURN_IN_MEMORY
6419 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6421 const enum machine_mode mode = type_natural_mode (type, NULL);
6425 if (ix86_function_type_abi (fntype) == MS_ABI)
6426 return return_in_memory_ms_64 (type, mode);
6428 return return_in_memory_64 (type, mode);
6431 return return_in_memory_32 (type, mode);
6435 /* Return false iff TYPE is returned in memory. This version is used
6436 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6437 but differs notably in that when MMX is available, 8-byte vectors
6438 are returned in memory, rather than in MMX registers. */
6441 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6444 enum machine_mode mode = type_natural_mode (type, NULL);
6447 return return_in_memory_64 (type, mode);
6449 if (mode == BLKmode)
6452 size = int_size_in_bytes (type);
6454 if (VECTOR_MODE_P (mode))
6456 /* Return in memory only if MMX registers *are* available. This
6457 seems backwards, but it is consistent with the existing
6464 else if (mode == TImode)
6466 else if (mode == XFmode)
6472 /* When returning SSE vector types, we have a choice of either
6473 (1) being abi incompatible with a -march switch, or
6474 (2) generating an error.
6475 Given no good solution, I think the safest thing is one warning.
6476 The user won't be able to use -Werror, but....
6478 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6479 called in response to actually generating a caller or callee that
6480 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6481 via aggregate_value_p for general type probing from tree-ssa. */
6484 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6486 static bool warnedsse, warnedmmx;
6488 if (!TARGET_64BIT && type)
6490 /* Look at the return type of the function, not the function type. */
6491 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6493 if (!TARGET_SSE && !warnedsse)
6496 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6499 warning (0, "SSE vector return without SSE enabled "
6504 if (!TARGET_MMX && !warnedmmx)
6506 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6509 warning (0, "MMX vector return without MMX enabled "
6519 /* Create the va_list data type. */
6521 /* Returns the calling convention specific va_list date type.
6522 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6525 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6527 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6529 /* For i386 we use plain pointer to argument area. */
6530 if (!TARGET_64BIT || abi == MS_ABI)
6531 return build_pointer_type (char_type_node);
6533 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6534 type_decl = build_decl (BUILTINS_LOCATION,
6535 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6537 f_gpr = build_decl (BUILTINS_LOCATION,
6538 FIELD_DECL, get_identifier ("gp_offset"),
6539 unsigned_type_node);
6540 f_fpr = build_decl (BUILTINS_LOCATION,
6541 FIELD_DECL, get_identifier ("fp_offset"),
6542 unsigned_type_node);
6543 f_ovf = build_decl (BUILTINS_LOCATION,
6544 FIELD_DECL, get_identifier ("overflow_arg_area"),
6546 f_sav = build_decl (BUILTINS_LOCATION,
6547 FIELD_DECL, get_identifier ("reg_save_area"),
6550 va_list_gpr_counter_field = f_gpr;
6551 va_list_fpr_counter_field = f_fpr;
6553 DECL_FIELD_CONTEXT (f_gpr) = record;
6554 DECL_FIELD_CONTEXT (f_fpr) = record;
6555 DECL_FIELD_CONTEXT (f_ovf) = record;
6556 DECL_FIELD_CONTEXT (f_sav) = record;
6558 TREE_CHAIN (record) = type_decl;
6559 TYPE_NAME (record) = type_decl;
6560 TYPE_FIELDS (record) = f_gpr;
6561 TREE_CHAIN (f_gpr) = f_fpr;
6562 TREE_CHAIN (f_fpr) = f_ovf;
6563 TREE_CHAIN (f_ovf) = f_sav;
6565 layout_type (record);
6567 /* The correct type is an array type of one element. */
6568 return build_array_type (record, build_index_type (size_zero_node));
6571 /* Setup the builtin va_list data type and for 64-bit the additional
6572 calling convention specific va_list data types. */
6575 ix86_build_builtin_va_list (void)
6577 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6579 /* Initialize abi specific va_list builtin types. */
6583 if (ix86_abi == MS_ABI)
6585 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6586 if (TREE_CODE (t) != RECORD_TYPE)
6587 t = build_variant_type_copy (t);
6588 sysv_va_list_type_node = t;
6593 if (TREE_CODE (t) != RECORD_TYPE)
6594 t = build_variant_type_copy (t);
6595 sysv_va_list_type_node = t;
6597 if (ix86_abi != MS_ABI)
6599 t = ix86_build_builtin_va_list_abi (MS_ABI);
6600 if (TREE_CODE (t) != RECORD_TYPE)
6601 t = build_variant_type_copy (t);
6602 ms_va_list_type_node = t;
6607 if (TREE_CODE (t) != RECORD_TYPE)
6608 t = build_variant_type_copy (t);
6609 ms_va_list_type_node = t;
6616 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6619 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6628 int regparm = ix86_regparm;
6630 if (cum->call_abi != ix86_abi)
6631 regparm = (ix86_abi != SYSV_ABI
6632 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6634 /* GPR size of varargs save area. */
6635 if (cfun->va_list_gpr_size)
6636 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6638 ix86_varargs_gpr_size = 0;
6640 /* FPR size of varargs save area. We don't need it if we don't pass
6641 anything in SSE registers. */
6642 if (cum->sse_nregs && cfun->va_list_fpr_size)
6643 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6645 ix86_varargs_fpr_size = 0;
6647 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6650 save_area = frame_pointer_rtx;
6651 set = get_varargs_alias_set ();
6653 for (i = cum->regno;
6655 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6658 mem = gen_rtx_MEM (Pmode,
6659 plus_constant (save_area, i * UNITS_PER_WORD));
6660 MEM_NOTRAP_P (mem) = 1;
6661 set_mem_alias_set (mem, set);
6662 emit_move_insn (mem, gen_rtx_REG (Pmode,
6663 x86_64_int_parameter_registers[i]));
6666 if (ix86_varargs_fpr_size)
6668 /* Now emit code to save SSE registers. The AX parameter contains number
6669 of SSE parameter registers used to call this function. We use
6670 sse_prologue_save insn template that produces computed jump across
6671 SSE saves. We need some preparation work to get this working. */
6673 label = gen_label_rtx ();
6674 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6676 /* Compute address to jump to :
6677 label - eax*4 + nnamed_sse_arguments*4 Or
6678 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6679 tmp_reg = gen_reg_rtx (Pmode);
6680 nsse_reg = gen_reg_rtx (Pmode);
6681 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6682 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6683 gen_rtx_MULT (Pmode, nsse_reg,
6686 /* vmovaps is one byte longer than movaps. */
6688 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6689 gen_rtx_PLUS (Pmode, tmp_reg,
6695 gen_rtx_CONST (DImode,
6696 gen_rtx_PLUS (DImode,
6698 GEN_INT (cum->sse_regno
6699 * (TARGET_AVX ? 5 : 4)))));
6701 emit_move_insn (nsse_reg, label_ref);
6702 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6704 /* Compute address of memory block we save into. We always use pointer
6705 pointing 127 bytes after first byte to store - this is needed to keep
6706 instruction size limited by 4 bytes (5 bytes for AVX) with one
6707 byte displacement. */
6708 tmp_reg = gen_reg_rtx (Pmode);
6709 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6710 plus_constant (save_area,
6711 ix86_varargs_gpr_size + 127)));
6712 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6713 MEM_NOTRAP_P (mem) = 1;
6714 set_mem_alias_set (mem, set);
6715 set_mem_align (mem, BITS_PER_WORD);
6717 /* And finally do the dirty job! */
6718 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6719 GEN_INT (cum->sse_regno), label));
6724 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6726 alias_set_type set = get_varargs_alias_set ();
6729 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6733 mem = gen_rtx_MEM (Pmode,
6734 plus_constant (virtual_incoming_args_rtx,
6735 i * UNITS_PER_WORD));
6736 MEM_NOTRAP_P (mem) = 1;
6737 set_mem_alias_set (mem, set);
6739 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6740 emit_move_insn (mem, reg);
6745 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6746 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6749 CUMULATIVE_ARGS next_cum;
6752 /* This argument doesn't appear to be used anymore. Which is good,
6753 because the old code here didn't suppress rtl generation. */
6754 gcc_assert (!no_rtl);
6759 fntype = TREE_TYPE (current_function_decl);
6761 /* For varargs, we do not want to skip the dummy va_dcl argument.
6762 For stdargs, we do want to skip the last named argument. */
6764 if (stdarg_p (fntype))
6765 function_arg_advance (&next_cum, mode, type, 1);
6767 if (cum->call_abi == MS_ABI)
6768 setup_incoming_varargs_ms_64 (&next_cum);
6770 setup_incoming_varargs_64 (&next_cum);
6773 /* Checks if TYPE is of kind va_list char *. */
6776 is_va_list_char_pointer (tree type)
6780 /* For 32-bit it is always true. */
6783 canonic = ix86_canonical_va_list_type (type);
6784 return (canonic == ms_va_list_type_node
6785 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6788 /* Implement va_start. */
6791 ix86_va_start (tree valist, rtx nextarg)
6793 HOST_WIDE_INT words, n_gpr, n_fpr;
6794 tree f_gpr, f_fpr, f_ovf, f_sav;
6795 tree gpr, fpr, ovf, sav, t;
6798 /* Only 64bit target needs something special. */
6799 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6801 std_expand_builtin_va_start (valist, nextarg);
6805 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6806 f_fpr = TREE_CHAIN (f_gpr);
6807 f_ovf = TREE_CHAIN (f_fpr);
6808 f_sav = TREE_CHAIN (f_ovf);
6810 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6811 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6812 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6813 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6814 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6816 /* Count number of gp and fp argument registers used. */
6817 words = crtl->args.info.words;
6818 n_gpr = crtl->args.info.regno;
6819 n_fpr = crtl->args.info.sse_regno;
6821 if (cfun->va_list_gpr_size)
6823 type = TREE_TYPE (gpr);
6824 t = build2 (MODIFY_EXPR, type,
6825 gpr, build_int_cst (type, n_gpr * 8));
6826 TREE_SIDE_EFFECTS (t) = 1;
6827 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6830 if (TARGET_SSE && cfun->va_list_fpr_size)
6832 type = TREE_TYPE (fpr);
6833 t = build2 (MODIFY_EXPR, type, fpr,
6834 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6835 TREE_SIDE_EFFECTS (t) = 1;
6836 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6839 /* Find the overflow area. */
6840 type = TREE_TYPE (ovf);
6841 t = make_tree (type, crtl->args.internal_arg_pointer);
6843 t = build2 (POINTER_PLUS_EXPR, type, t,
6844 size_int (words * UNITS_PER_WORD));
6845 t = build2 (MODIFY_EXPR, type, ovf, t);
6846 TREE_SIDE_EFFECTS (t) = 1;
6847 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6849 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6851 /* Find the register save area.
6852 Prologue of the function save it right above stack frame. */
6853 type = TREE_TYPE (sav);
6854 t = make_tree (type, frame_pointer_rtx);
6855 if (!ix86_varargs_gpr_size)
6856 t = build2 (POINTER_PLUS_EXPR, type, t,
6857 size_int (-8 * X86_64_REGPARM_MAX));
6858 t = build2 (MODIFY_EXPR, type, sav, t);
6859 TREE_SIDE_EFFECTS (t) = 1;
6860 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6864 /* Implement va_arg. */
6867 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6870 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6871 tree f_gpr, f_fpr, f_ovf, f_sav;
6872 tree gpr, fpr, ovf, sav, t;
6874 tree lab_false, lab_over = NULL_TREE;
6879 enum machine_mode nat_mode;
6882 /* Only 64bit target needs something special. */
6883 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6884 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6886 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6887 f_fpr = TREE_CHAIN (f_gpr);
6888 f_ovf = TREE_CHAIN (f_fpr);
6889 f_sav = TREE_CHAIN (f_ovf);
6891 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6892 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6893 valist = build_va_arg_indirect_ref (valist);
6894 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6895 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6896 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6898 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6900 type = build_pointer_type (type);
6901 size = int_size_in_bytes (type);
6902 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6904 nat_mode = type_natural_mode (type, NULL);
6913 /* Unnamed 256bit vector mode parameters are passed on stack. */
6914 if (ix86_cfun_abi () == SYSV_ABI)
6921 container = construct_container (nat_mode, TYPE_MODE (type),
6922 type, 0, X86_64_REGPARM_MAX,
6923 X86_64_SSE_REGPARM_MAX, intreg,
6928 /* Pull the value out of the saved registers. */
6930 addr = create_tmp_var (ptr_type_node, "addr");
6931 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6935 int needed_intregs, needed_sseregs;
6937 tree int_addr, sse_addr;
6939 lab_false = create_artificial_label (UNKNOWN_LOCATION);
6940 lab_over = create_artificial_label (UNKNOWN_LOCATION);
6942 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6944 need_temp = (!REG_P (container)
6945 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6946 || TYPE_ALIGN (type) > 128));
6948 /* In case we are passing structure, verify that it is consecutive block
6949 on the register save area. If not we need to do moves. */
6950 if (!need_temp && !REG_P (container))
6952 /* Verify that all registers are strictly consecutive */
6953 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6957 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6959 rtx slot = XVECEXP (container, 0, i);
6960 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6961 || INTVAL (XEXP (slot, 1)) != i * 16)
6969 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6971 rtx slot = XVECEXP (container, 0, i);
6972 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6973 || INTVAL (XEXP (slot, 1)) != i * 8)
6985 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6986 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6987 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6988 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6991 /* First ensure that we fit completely in registers. */
6994 t = build_int_cst (TREE_TYPE (gpr),
6995 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6996 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6997 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6998 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6999 gimplify_and_add (t, pre_p);
7003 t = build_int_cst (TREE_TYPE (fpr),
7004 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7005 + X86_64_REGPARM_MAX * 8);
7006 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7007 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7008 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7009 gimplify_and_add (t, pre_p);
7012 /* Compute index to start of area used for integer regs. */
7015 /* int_addr = gpr + sav; */
7016 t = fold_convert (sizetype, gpr);
7017 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7018 gimplify_assign (int_addr, t, pre_p);
7022 /* sse_addr = fpr + sav; */
7023 t = fold_convert (sizetype, fpr);
7024 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7025 gimplify_assign (sse_addr, t, pre_p);
7030 tree temp = create_tmp_var (type, "va_arg_tmp");
7033 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7034 gimplify_assign (addr, t, pre_p);
7036 for (i = 0; i < XVECLEN (container, 0); i++)
7038 rtx slot = XVECEXP (container, 0, i);
7039 rtx reg = XEXP (slot, 0);
7040 enum machine_mode mode = GET_MODE (reg);
7041 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7042 tree addr_type = build_pointer_type (piece_type);
7043 tree daddr_type = build_pointer_type_for_mode (piece_type,
7047 tree dest_addr, dest;
7049 if (SSE_REGNO_P (REGNO (reg)))
7051 src_addr = sse_addr;
7052 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7056 src_addr = int_addr;
7057 src_offset = REGNO (reg) * 8;
7059 src_addr = fold_convert (addr_type, src_addr);
7060 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7061 size_int (src_offset));
7062 src = build_va_arg_indirect_ref (src_addr);
7064 dest_addr = fold_convert (daddr_type, addr);
7065 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7066 size_int (INTVAL (XEXP (slot, 1))));
7067 dest = build_va_arg_indirect_ref (dest_addr);
7069 gimplify_assign (dest, src, pre_p);
7075 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7076 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7077 gimplify_assign (gpr, t, pre_p);
7082 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7083 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7084 gimplify_assign (fpr, t, pre_p);
7087 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7089 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7092 /* ... otherwise out of the overflow area. */
7094 /* When we align parameter on stack for caller, if the parameter
7095 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7096 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7097 here with caller. */
7098 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7099 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7100 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7102 /* Care for on-stack alignment if needed. */
7103 if (arg_boundary <= 64
7104 || integer_zerop (TYPE_SIZE (type)))
7108 HOST_WIDE_INT align = arg_boundary / 8;
7109 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7110 size_int (align - 1));
7111 t = fold_convert (sizetype, t);
7112 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7114 t = fold_convert (TREE_TYPE (ovf), t);
7116 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7117 gimplify_assign (addr, t, pre_p);
7119 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7120 size_int (rsize * UNITS_PER_WORD));
7121 gimplify_assign (unshare_expr (ovf), t, pre_p);
7124 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7126 ptrtype = build_pointer_type (type);
7127 addr = fold_convert (ptrtype, addr);
7130 addr = build_va_arg_indirect_ref (addr);
7131 return build_va_arg_indirect_ref (addr);
7134 /* Return nonzero if OPNUM's MEM should be matched
7135 in movabs* patterns. */
7138 ix86_check_movabs (rtx insn, int opnum)
7142 set = PATTERN (insn);
7143 if (GET_CODE (set) == PARALLEL)
7144 set = XVECEXP (set, 0, 0);
7145 gcc_assert (GET_CODE (set) == SET);
7146 mem = XEXP (set, opnum);
7147 while (GET_CODE (mem) == SUBREG)
7148 mem = SUBREG_REG (mem);
7149 gcc_assert (MEM_P (mem));
7150 return (volatile_ok || !MEM_VOLATILE_P (mem));
7153 /* Initialize the table of extra 80387 mathematical constants. */
7156 init_ext_80387_constants (void)
7158 static const char * cst[5] =
7160 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7161 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7162 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7163 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7164 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7168 for (i = 0; i < 5; i++)
7170 real_from_string (&ext_80387_constants_table[i], cst[i]);
7171 /* Ensure each constant is rounded to XFmode precision. */
7172 real_convert (&ext_80387_constants_table[i],
7173 XFmode, &ext_80387_constants_table[i]);
7176 ext_80387_constants_init = 1;
7179 /* Return true if the constant is something that can be loaded with
7180 a special instruction. */
7183 standard_80387_constant_p (rtx x)
7185 enum machine_mode mode = GET_MODE (x);
7189 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7192 if (x == CONST0_RTX (mode))
7194 if (x == CONST1_RTX (mode))
7197 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7199 /* For XFmode constants, try to find a special 80387 instruction when
7200 optimizing for size or on those CPUs that benefit from them. */
7202 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7206 if (! ext_80387_constants_init)
7207 init_ext_80387_constants ();
7209 for (i = 0; i < 5; i++)
7210 if (real_identical (&r, &ext_80387_constants_table[i]))
7214 /* Load of the constant -0.0 or -1.0 will be split as
7215 fldz;fchs or fld1;fchs sequence. */
7216 if (real_isnegzero (&r))
7218 if (real_identical (&r, &dconstm1))
7224 /* Return the opcode of the special instruction to be used to load
7228 standard_80387_constant_opcode (rtx x)
7230 switch (standard_80387_constant_p (x))
7254 /* Return the CONST_DOUBLE representing the 80387 constant that is
7255 loaded by the specified special instruction. The argument IDX
7256 matches the return value from standard_80387_constant_p. */
7259 standard_80387_constant_rtx (int idx)
7263 if (! ext_80387_constants_init)
7264 init_ext_80387_constants ();
7280 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7284 /* Return 1 if mode is a valid mode for sse. */
7286 standard_sse_mode_p (enum machine_mode mode)
7303 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7304 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7305 modes and AVX is enabled. */
7308 standard_sse_constant_p (rtx x)
7310 enum machine_mode mode = GET_MODE (x);
7312 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7314 if (vector_all_ones_operand (x, mode))
7316 if (standard_sse_mode_p (mode))
7317 return TARGET_SSE2 ? 2 : -2;
7318 else if (VALID_AVX256_REG_MODE (mode))
7319 return TARGET_AVX ? 3 : -3;
7325 /* Return the opcode of the special instruction to be used to load
7329 standard_sse_constant_opcode (rtx insn, rtx x)
7331 switch (standard_sse_constant_p (x))
7334 switch (get_attr_mode (insn))
7337 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7339 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7341 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7343 return "vxorps\t%x0, %x0, %x0";
7345 return "vxorpd\t%x0, %x0, %x0";
7347 return "vpxor\t%x0, %x0, %x0";
7353 switch (get_attr_mode (insn))
7358 return "vpcmpeqd\t%0, %0, %0";
7364 return "pcmpeqd\t%0, %0";
7369 /* Returns 1 if OP contains a symbol reference */
7372 symbolic_reference_mentioned_p (rtx op)
7377 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7380 fmt = GET_RTX_FORMAT (GET_CODE (op));
7381 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7387 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7388 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7392 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7399 /* Return 1 if it is appropriate to emit `ret' instructions in the
7400 body of a function. Do this only if the epilogue is simple, needing a
7401 couple of insns. Prior to reloading, we can't tell how many registers
7402 must be saved, so return 0 then. Return 0 if there is no frame
7403 marker to de-allocate. */
7406 ix86_can_use_return_insn_p (void)
7408 struct ix86_frame frame;
7410 if (! reload_completed || frame_pointer_needed)
7413 /* Don't allow more than 32 pop, since that's all we can do
7414 with one instruction. */
7415 if (crtl->args.pops_args
7416 && crtl->args.size >= 32768)
7419 ix86_compute_frame_layout (&frame);
7420 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7423 /* Value should be nonzero if functions must have frame pointers.
7424 Zero means the frame pointer need not be set up (and parms may
7425 be accessed via the stack pointer) in functions that seem suitable. */
7428 ix86_frame_pointer_required (void)
7430 /* If we accessed previous frames, then the generated code expects
7431 to be able to access the saved ebp value in our frame. */
7432 if (cfun->machine->accesses_prev_frame)
7435 /* Several x86 os'es need a frame pointer for other reasons,
7436 usually pertaining to setjmp. */
7437 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7440 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7441 the frame pointer by default. Turn it back on now if we've not
7442 got a leaf function. */
7443 if (TARGET_OMIT_LEAF_FRAME_POINTER
7444 && (!current_function_is_leaf
7445 || ix86_current_function_calls_tls_descriptor))
7454 /* Record that the current function accesses previous call frames. */
7457 ix86_setup_frame_addresses (void)
7459 cfun->machine->accesses_prev_frame = 1;
7462 #ifndef USE_HIDDEN_LINKONCE
7463 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7464 # define USE_HIDDEN_LINKONCE 1
7466 # define USE_HIDDEN_LINKONCE 0
7470 static int pic_labels_used;
7472 /* Fills in the label name that should be used for a pc thunk for
7473 the given register. */
7476 get_pc_thunk_name (char name[32], unsigned int regno)
7478 gcc_assert (!TARGET_64BIT);
7480 if (USE_HIDDEN_LINKONCE)
7481 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7483 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7487 /* This function generates code for -fpic that loads %ebx with
7488 the return address of the caller and then returns. */
7491 ix86_file_end (void)
7496 for (regno = 0; regno < 8; ++regno)
7500 if (! ((pic_labels_used >> regno) & 1))
7503 get_pc_thunk_name (name, regno);
7508 switch_to_section (darwin_sections[text_coal_section]);
7509 fputs ("\t.weak_definition\t", asm_out_file);
7510 assemble_name (asm_out_file, name);
7511 fputs ("\n\t.private_extern\t", asm_out_file);
7512 assemble_name (asm_out_file, name);
7513 fputs ("\n", asm_out_file);
7514 ASM_OUTPUT_LABEL (asm_out_file, name);
7518 if (USE_HIDDEN_LINKONCE)
7522 decl = build_decl (BUILTINS_LOCATION,
7523 FUNCTION_DECL, get_identifier (name),
7525 TREE_PUBLIC (decl) = 1;
7526 TREE_STATIC (decl) = 1;
7527 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7529 (*targetm.asm_out.unique_section) (decl, 0);
7530 switch_to_section (get_named_section (decl, NULL, 0));
7532 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7533 fputs ("\t.hidden\t", asm_out_file);
7534 assemble_name (asm_out_file, name);
7535 fputc ('\n', asm_out_file);
7536 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7540 switch_to_section (text_section);
7541 ASM_OUTPUT_LABEL (asm_out_file, name);
7544 xops[0] = gen_rtx_REG (Pmode, regno);
7545 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7546 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7547 output_asm_insn ("ret", xops);
7550 if (NEED_INDICATE_EXEC_STACK)
7551 file_end_indicate_exec_stack ();
7554 /* Emit code for the SET_GOT patterns. */
7557 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7563 if (TARGET_VXWORKS_RTP && flag_pic)
7565 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7566 xops[2] = gen_rtx_MEM (Pmode,
7567 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7568 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7570 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7571 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7572 an unadorned address. */
7573 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7574 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7575 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7579 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7581 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7583 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7586 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7588 output_asm_insn ("call\t%a2", xops);
7591 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7592 is what will be referenced by the Mach-O PIC subsystem. */
7594 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7597 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7598 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7601 output_asm_insn ("pop%z0\t%0", xops);
7606 get_pc_thunk_name (name, REGNO (dest));
7607 pic_labels_used |= 1 << REGNO (dest);
7609 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7610 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7611 output_asm_insn ("call\t%X2", xops);
7612 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7613 is what will be referenced by the Mach-O PIC subsystem. */
7616 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7618 targetm.asm_out.internal_label (asm_out_file, "L",
7619 CODE_LABEL_NUMBER (label));
7626 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7627 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7629 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7634 /* Generate an "push" pattern for input ARG. */
7639 if (ix86_cfa_state->reg == stack_pointer_rtx)
7640 ix86_cfa_state->offset += UNITS_PER_WORD;
7642 return gen_rtx_SET (VOIDmode,
7644 gen_rtx_PRE_DEC (Pmode,
7645 stack_pointer_rtx)),
7649 /* Return >= 0 if there is an unused call-clobbered register available
7650 for the entire function. */
7653 ix86_select_alt_pic_regnum (void)
7655 if (current_function_is_leaf && !crtl->profile
7656 && !ix86_current_function_calls_tls_descriptor)
7659 /* Can't use the same register for both PIC and DRAP. */
7661 drap = REGNO (crtl->drap_reg);
7664 for (i = 2; i >= 0; --i)
7665 if (i != drap && !df_regs_ever_live_p (i))
7669 return INVALID_REGNUM;
7672 /* Return 1 if we need to save REGNO. */
7674 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7676 if (pic_offset_table_rtx
7677 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7678 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7680 || crtl->calls_eh_return
7681 || crtl->uses_const_pool))
7683 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7688 if (crtl->calls_eh_return && maybe_eh_return)
7693 unsigned test = EH_RETURN_DATA_REGNO (i);
7694 if (test == INVALID_REGNUM)
7701 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7704 return (df_regs_ever_live_p (regno)
7705 && !call_used_regs[regno]
7706 && !fixed_regs[regno]
7707 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7710 /* Return number of saved general prupose registers. */
7713 ix86_nsaved_regs (void)
7718 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7719 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7724 /* Return number of saved SSE registrers. */
7727 ix86_nsaved_sseregs (void)
7732 if (ix86_cfun_abi () != MS_ABI)
7734 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7735 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7740 /* Given FROM and TO register numbers, say whether this elimination is
7741 allowed. If stack alignment is needed, we can only replace argument
7742 pointer with hard frame pointer, or replace frame pointer with stack
7743 pointer. Otherwise, frame pointer elimination is automatically
7744 handled and all other eliminations are valid. */
7747 ix86_can_eliminate (int from, int to)
7749 if (stack_realign_fp)
7750 return ((from == ARG_POINTER_REGNUM
7751 && to == HARD_FRAME_POINTER_REGNUM)
7752 || (from == FRAME_POINTER_REGNUM
7753 && to == STACK_POINTER_REGNUM));
7755 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7758 /* Return the offset between two registers, one to be eliminated, and the other
7759 its replacement, at the start of a routine. */
7762 ix86_initial_elimination_offset (int from, int to)
7764 struct ix86_frame frame;
7765 ix86_compute_frame_layout (&frame);
7767 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7768 return frame.hard_frame_pointer_offset;
7769 else if (from == FRAME_POINTER_REGNUM
7770 && to == HARD_FRAME_POINTER_REGNUM)
7771 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7774 gcc_assert (to == STACK_POINTER_REGNUM);
7776 if (from == ARG_POINTER_REGNUM)
7777 return frame.stack_pointer_offset;
7779 gcc_assert (from == FRAME_POINTER_REGNUM);
7780 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7784 /* In a dynamically-aligned function, we can't know the offset from
7785 stack pointer to frame pointer, so we must ensure that setjmp
7786 eliminates fp against the hard fp (%ebp) rather than trying to
7787 index from %esp up to the top of the frame across a gap that is
7788 of unknown (at compile-time) size. */
7790 ix86_builtin_setjmp_frame_value (void)
7792 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7795 /* Fill structure ix86_frame about frame of currently computed function. */
7798 ix86_compute_frame_layout (struct ix86_frame *frame)
7800 HOST_WIDE_INT total_size;
7801 unsigned int stack_alignment_needed;
7802 HOST_WIDE_INT offset;
7803 unsigned int preferred_alignment;
7804 HOST_WIDE_INT size = get_frame_size ();
7806 frame->nregs = ix86_nsaved_regs ();
7807 frame->nsseregs = ix86_nsaved_sseregs ();
7810 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7811 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7813 /* MS ABI seem to require stack alignment to be always 16 except for function
7815 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7817 preferred_alignment = 16;
7818 stack_alignment_needed = 16;
7819 crtl->preferred_stack_boundary = 128;
7820 crtl->stack_alignment_needed = 128;
7823 gcc_assert (!size || stack_alignment_needed);
7824 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7825 gcc_assert (preferred_alignment <= stack_alignment_needed);
7827 /* During reload iteration the amount of registers saved can change.
7828 Recompute the value as needed. Do not recompute when amount of registers
7829 didn't change as reload does multiple calls to the function and does not
7830 expect the decision to change within single iteration. */
7831 if (!optimize_function_for_size_p (cfun)
7832 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7834 int count = frame->nregs;
7836 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7837 /* The fast prologue uses move instead of push to save registers. This
7838 is significantly longer, but also executes faster as modern hardware
7839 can execute the moves in parallel, but can't do that for push/pop.
7841 Be careful about choosing what prologue to emit: When function takes
7842 many instructions to execute we may use slow version as well as in
7843 case function is known to be outside hot spot (this is known with
7844 feedback only). Weight the size of function by number of registers
7845 to save as it is cheap to use one or two push instructions but very
7846 slow to use many of them. */
7848 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7849 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7850 || (flag_branch_probabilities
7851 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7852 cfun->machine->use_fast_prologue_epilogue = false;
7854 cfun->machine->use_fast_prologue_epilogue
7855 = !expensive_function_p (count);
7857 if (TARGET_PROLOGUE_USING_MOVE
7858 && cfun->machine->use_fast_prologue_epilogue)
7859 frame->save_regs_using_mov = true;
7861 frame->save_regs_using_mov = false;
7864 /* Skip return address and saved base pointer. */
7865 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7867 frame->hard_frame_pointer_offset = offset;
7869 /* Set offset to aligned because the realigned frame starts from
7871 if (stack_realign_fp)
7872 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7874 /* Register save area */
7875 offset += frame->nregs * UNITS_PER_WORD;
7877 /* Align SSE reg save area. */
7878 if (frame->nsseregs)
7879 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7881 frame->padding0 = 0;
7883 /* SSE register save area. */
7884 offset += frame->padding0 + frame->nsseregs * 16;
7887 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7888 offset += frame->va_arg_size;
7890 /* Align start of frame for local function. */
7891 frame->padding1 = ((offset + stack_alignment_needed - 1)
7892 & -stack_alignment_needed) - offset;
7894 offset += frame->padding1;
7896 /* Frame pointer points here. */
7897 frame->frame_pointer_offset = offset;
7901 /* Add outgoing arguments area. Can be skipped if we eliminated
7902 all the function calls as dead code.
7903 Skipping is however impossible when function calls alloca. Alloca
7904 expander assumes that last crtl->outgoing_args_size
7905 of stack frame are unused. */
7906 if (ACCUMULATE_OUTGOING_ARGS
7907 && (!current_function_is_leaf || cfun->calls_alloca
7908 || ix86_current_function_calls_tls_descriptor))
7910 offset += crtl->outgoing_args_size;
7911 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7914 frame->outgoing_arguments_size = 0;
7916 /* Align stack boundary. Only needed if we're calling another function
7918 if (!current_function_is_leaf || cfun->calls_alloca
7919 || ix86_current_function_calls_tls_descriptor)
7920 frame->padding2 = ((offset + preferred_alignment - 1)
7921 & -preferred_alignment) - offset;
7923 frame->padding2 = 0;
7925 offset += frame->padding2;
7927 /* We've reached end of stack frame. */
7928 frame->stack_pointer_offset = offset;
7930 /* Size prologue needs to allocate. */
7931 frame->to_allocate =
7932 (size + frame->padding1 + frame->padding2
7933 + frame->outgoing_arguments_size + frame->va_arg_size);
7935 if ((!frame->to_allocate && frame->nregs <= 1)
7936 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7937 frame->save_regs_using_mov = false;
7939 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7940 && current_function_is_leaf
7941 && !ix86_current_function_calls_tls_descriptor)
7943 frame->red_zone_size = frame->to_allocate;
7944 if (frame->save_regs_using_mov)
7945 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7946 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7947 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7950 frame->red_zone_size = 0;
7951 frame->to_allocate -= frame->red_zone_size;
7952 frame->stack_pointer_offset -= frame->red_zone_size;
7954 fprintf (stderr, "\n");
7955 fprintf (stderr, "size: %ld\n", (long)size);
7956 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7957 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7958 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7959 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7960 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7961 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7962 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7963 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7964 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7965 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7966 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7967 (long)frame->hard_frame_pointer_offset);
7968 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7969 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7970 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7971 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7975 /* Emit code to save registers in the prologue. */
7978 ix86_emit_save_regs (void)
7983 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7984 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7986 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7987 RTX_FRAME_RELATED_P (insn) = 1;
7991 /* Emit code to save registers using MOV insns. First register
7992 is restored from POINTER + OFFSET. */
7994 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7999 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8000 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8002 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8004 gen_rtx_REG (Pmode, regno));
8005 RTX_FRAME_RELATED_P (insn) = 1;
8006 offset += UNITS_PER_WORD;
8010 /* Emit code to save registers using MOV insns. First register
8011 is restored from POINTER + OFFSET. */
8013 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8019 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8020 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8022 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8023 set_mem_align (mem, 128);
8024 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8025 RTX_FRAME_RELATED_P (insn) = 1;
8030 static GTY(()) rtx queued_cfa_restores;
8032 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8033 manipulation insn. Don't add it if the previously
8034 saved value will be left untouched within stack red-zone till return,
8035 as unwinders can find the same value in the register and
8039 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8042 && !TARGET_64BIT_MS_ABI
8043 && red_offset + RED_ZONE_SIZE >= 0
8044 && crtl->args.pops_args < 65536)
8049 add_reg_note (insn, REG_CFA_RESTORE, reg);
8050 RTX_FRAME_RELATED_P (insn) = 1;
8054 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8057 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8060 ix86_add_queued_cfa_restore_notes (rtx insn)
8063 if (!queued_cfa_restores)
8065 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8067 XEXP (last, 1) = REG_NOTES (insn);
8068 REG_NOTES (insn) = queued_cfa_restores;
8069 queued_cfa_restores = NULL_RTX;
8070 RTX_FRAME_RELATED_P (insn) = 1;
8073 /* Expand prologue or epilogue stack adjustment.
8074 The pattern exist to put a dependency on all ebp-based memory accesses.
8075 STYLE should be negative if instructions should be marked as frame related,
8076 zero if %r11 register is live and cannot be freely used and positive
8080 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8081 int style, bool set_cfa)
8086 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8087 else if (x86_64_immediate_operand (offset, DImode))
8088 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8092 /* r11 is used by indirect sibcall return as well, set before the
8093 epilogue and used after the epilogue. ATM indirect sibcall
8094 shouldn't be used together with huge frame sizes in one
8095 function because of the frame_size check in sibcall.c. */
8097 r11 = gen_rtx_REG (DImode, R11_REG);
8098 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8100 RTX_FRAME_RELATED_P (insn) = 1;
8101 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8106 ix86_add_queued_cfa_restore_notes (insn);
8112 gcc_assert (ix86_cfa_state->reg == src);
8113 ix86_cfa_state->offset += INTVAL (offset);
8114 ix86_cfa_state->reg = dest;
8116 r = gen_rtx_PLUS (Pmode, src, offset);
8117 r = gen_rtx_SET (VOIDmode, dest, r);
8118 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8119 RTX_FRAME_RELATED_P (insn) = 1;
8122 RTX_FRAME_RELATED_P (insn) = 1;
8125 /* Find an available register to be used as dynamic realign argument
8126 pointer regsiter. Such a register will be written in prologue and
8127 used in begin of body, so it must not be
8128 1. parameter passing register.
8130 We reuse static-chain register if it is available. Otherwise, we
8131 use DI for i386 and R13 for x86-64. We chose R13 since it has
8134 Return: the regno of chosen register. */
8137 find_drap_reg (void)
8139 tree decl = cfun->decl;
8143 /* Use R13 for nested function or function need static chain.
8144 Since function with tail call may use any caller-saved
8145 registers in epilogue, DRAP must not use caller-saved
8146 register in such case. */
8147 if ((decl_function_context (decl)
8148 && !DECL_NO_STATIC_CHAIN (decl))
8149 || crtl->tail_call_emit)
8156 /* Use DI for nested function or function need static chain.
8157 Since function with tail call may use any caller-saved
8158 registers in epilogue, DRAP must not use caller-saved
8159 register in such case. */
8160 if ((decl_function_context (decl)
8161 && !DECL_NO_STATIC_CHAIN (decl))
8162 || crtl->tail_call_emit)
8165 /* Reuse static chain register if it isn't used for parameter
8167 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8168 && !lookup_attribute ("fastcall",
8169 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8176 /* Update incoming stack boundary and estimated stack alignment. */
8179 ix86_update_stack_boundary (void)
8181 /* Prefer the one specified at command line. */
8182 ix86_incoming_stack_boundary
8183 = (ix86_user_incoming_stack_boundary
8184 ? ix86_user_incoming_stack_boundary
8185 : ix86_default_incoming_stack_boundary);
8187 /* Incoming stack alignment can be changed on individual functions
8188 via force_align_arg_pointer attribute. We use the smallest
8189 incoming stack boundary. */
8190 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8191 && lookup_attribute (ix86_force_align_arg_pointer_string,
8192 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8193 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8195 /* The incoming stack frame has to be aligned at least at
8196 parm_stack_boundary. */
8197 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8198 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8200 /* Stack at entrance of main is aligned by runtime. We use the
8201 smallest incoming stack boundary. */
8202 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8203 && DECL_NAME (current_function_decl)
8204 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8205 && DECL_FILE_SCOPE_P (current_function_decl))
8206 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8208 /* x86_64 vararg needs 16byte stack alignment for register save
8212 && crtl->stack_alignment_estimated < 128)
8213 crtl->stack_alignment_estimated = 128;
8216 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8217 needed or an rtx for DRAP otherwise. */
8220 ix86_get_drap_rtx (void)
8222 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8223 crtl->need_drap = true;
8225 if (stack_realign_drap)
8227 /* Assign DRAP to vDRAP and returns vDRAP */
8228 unsigned int regno = find_drap_reg ();
8233 arg_ptr = gen_rtx_REG (Pmode, regno);
8234 crtl->drap_reg = arg_ptr;
8237 drap_vreg = copy_to_reg (arg_ptr);
8241 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8242 RTX_FRAME_RELATED_P (insn) = 1;
8249 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8252 ix86_internal_arg_pointer (void)
8254 return virtual_incoming_args_rtx;
8257 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8258 to be generated in correct form. */
8260 ix86_finalize_stack_realign_flags (void)
8262 /* Check if stack realign is really needed after reload, and
8263 stores result in cfun */
8264 unsigned int incoming_stack_boundary
8265 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8266 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8267 unsigned int stack_realign = (incoming_stack_boundary
8268 < (current_function_is_leaf
8269 ? crtl->max_used_stack_slot_alignment
8270 : crtl->stack_alignment_needed));
8272 if (crtl->stack_realign_finalized)
8274 /* After stack_realign_needed is finalized, we can't no longer
8276 gcc_assert (crtl->stack_realign_needed == stack_realign);
8280 crtl->stack_realign_needed = stack_realign;
8281 crtl->stack_realign_finalized = true;
8285 /* Expand the prologue into a bunch of separate insns. */
8288 ix86_expand_prologue (void)
8292 struct ix86_frame frame;
8293 HOST_WIDE_INT allocate;
8295 ix86_finalize_stack_realign_flags ();
8297 /* DRAP should not coexist with stack_realign_fp */
8298 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8300 /* Initialize CFA state for before the prologue. */
8301 ix86_cfa_state->reg = stack_pointer_rtx;
8302 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8304 ix86_compute_frame_layout (&frame);
8306 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8307 of DRAP is needed and stack realignment is really needed after reload */
8308 if (crtl->drap_reg && crtl->stack_realign_needed)
8311 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8312 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8313 ? 0 : UNITS_PER_WORD);
8315 gcc_assert (stack_realign_drap);
8317 /* Grab the argument pointer. */
8318 x = plus_constant (stack_pointer_rtx,
8319 (UNITS_PER_WORD + param_ptr_offset));
8322 /* Only need to push parameter pointer reg if it is caller
8324 if (!call_used_regs[REGNO (crtl->drap_reg)])
8326 /* Push arg pointer reg */
8327 insn = emit_insn (gen_push (y));
8328 RTX_FRAME_RELATED_P (insn) = 1;
8331 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8332 RTX_FRAME_RELATED_P (insn) = 1;
8333 ix86_cfa_state->reg = crtl->drap_reg;
8335 /* Align the stack. */
8336 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8338 GEN_INT (-align_bytes)));
8339 RTX_FRAME_RELATED_P (insn) = 1;
8341 /* Replicate the return address on the stack so that return
8342 address can be reached via (argp - 1) slot. This is needed
8343 to implement macro RETURN_ADDR_RTX and intrinsic function
8344 expand_builtin_return_addr etc. */
8346 x = gen_frame_mem (Pmode,
8347 plus_constant (x, -UNITS_PER_WORD));
8348 insn = emit_insn (gen_push (x));
8349 RTX_FRAME_RELATED_P (insn) = 1;
8352 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8353 slower on all targets. Also sdb doesn't like it. */
8355 if (frame_pointer_needed)
8357 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8358 RTX_FRAME_RELATED_P (insn) = 1;
8360 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8361 RTX_FRAME_RELATED_P (insn) = 1;
8363 if (ix86_cfa_state->reg == stack_pointer_rtx)
8364 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8367 if (stack_realign_fp)
8369 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8370 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8372 /* Align the stack. */
8373 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8375 GEN_INT (-align_bytes)));
8376 RTX_FRAME_RELATED_P (insn) = 1;
8379 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8381 if (!frame.save_regs_using_mov)
8382 ix86_emit_save_regs ();
8384 allocate += frame.nregs * UNITS_PER_WORD;
8386 /* When using red zone we may start register saving before allocating
8387 the stack frame saving one cycle of the prologue. However I will
8388 avoid doing this if I am going to have to probe the stack since
8389 at least on x86_64 the stack probe can turn into a call that clobbers
8390 a red zone location */
8391 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8392 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8393 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8394 && !crtl->stack_realign_needed)
8395 ? hard_frame_pointer_rtx
8396 : stack_pointer_rtx,
8397 -frame.nregs * UNITS_PER_WORD);
8401 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8402 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8403 GEN_INT (-allocate), -1,
8404 ix86_cfa_state->reg == stack_pointer_rtx);
8407 /* Only valid for Win32. */
8408 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8412 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8414 if (cfun->machine->call_abi == MS_ABI)
8417 eax_live = ix86_eax_live_at_start_p ();
8421 emit_insn (gen_push (eax));
8422 allocate -= UNITS_PER_WORD;
8425 emit_move_insn (eax, GEN_INT (allocate));
8428 insn = gen_allocate_stack_worker_64 (eax, eax);
8430 insn = gen_allocate_stack_worker_32 (eax, eax);
8431 insn = emit_insn (insn);
8433 if (ix86_cfa_state->reg == stack_pointer_rtx)
8435 ix86_cfa_state->offset += allocate;
8436 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8437 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8438 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8439 RTX_FRAME_RELATED_P (insn) = 1;
8444 if (frame_pointer_needed)
8445 t = plus_constant (hard_frame_pointer_rtx,
8448 - frame.nregs * UNITS_PER_WORD);
8450 t = plus_constant (stack_pointer_rtx, allocate);
8451 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8455 if (frame.save_regs_using_mov
8456 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8457 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8459 if (!frame_pointer_needed
8460 || !frame.to_allocate
8461 || crtl->stack_realign_needed)
8462 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8464 + frame.nsseregs * 16 + frame.padding0);
8466 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8467 -frame.nregs * UNITS_PER_WORD);
8469 if (!frame_pointer_needed
8470 || !frame.to_allocate
8471 || crtl->stack_realign_needed)
8472 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8475 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8476 - frame.nregs * UNITS_PER_WORD
8477 - frame.nsseregs * 16
8480 pic_reg_used = false;
8481 if (pic_offset_table_rtx
8482 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8485 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8487 if (alt_pic_reg_used != INVALID_REGNUM)
8488 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8490 pic_reg_used = true;
8497 if (ix86_cmodel == CM_LARGE_PIC)
8499 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8500 rtx label = gen_label_rtx ();
8502 LABEL_PRESERVE_P (label) = 1;
8503 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8504 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8505 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8506 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8507 pic_offset_table_rtx, tmp_reg));
8510 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8513 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8516 /* In the pic_reg_used case, make sure that the got load isn't deleted
8517 when mcount needs it. Blockage to avoid call movement across mcount
8518 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8520 if (crtl->profile && pic_reg_used)
8521 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8523 if (crtl->drap_reg && !crtl->stack_realign_needed)
8525 /* vDRAP is setup but after reload it turns out stack realign
8526 isn't necessary, here we will emit prologue to setup DRAP
8527 without stack realign adjustment */
8528 int drap_bp_offset = UNITS_PER_WORD * 2;
8529 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8530 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8533 /* Prevent instructions from being scheduled into register save push
8534 sequence when access to the redzone area is done through frame pointer.
8535 The offset betweeh the frame pointer and the stack pointer is calculated
8536 relative to the value of the stack pointer at the end of the function
8537 prologue, and moving instructions that access redzone area via frame
8538 pointer inside push sequence violates this assumption. */
8539 if (frame_pointer_needed && frame.red_zone_size)
8540 emit_insn (gen_memory_blockage ());
8542 /* Emit cld instruction if stringops are used in the function. */
8543 if (TARGET_CLD && ix86_current_function_needs_cld)
8544 emit_insn (gen_cld ());
8547 /* Emit code to restore REG using a POP insn. */
8550 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8552 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8554 if (ix86_cfa_state->reg == crtl->drap_reg
8555 && REGNO (reg) == REGNO (crtl->drap_reg))
8557 /* Previously we'd represented the CFA as an expression
8558 like *(%ebp - 8). We've just popped that value from
8559 the stack, which means we need to reset the CFA to
8560 the drap register. This will remain until we restore
8561 the stack pointer. */
8562 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8563 RTX_FRAME_RELATED_P (insn) = 1;
8567 if (ix86_cfa_state->reg == stack_pointer_rtx)
8569 ix86_cfa_state->offset -= UNITS_PER_WORD;
8570 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8571 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8572 RTX_FRAME_RELATED_P (insn) = 1;
8575 /* When the frame pointer is the CFA, and we pop it, we are
8576 swapping back to the stack pointer as the CFA. This happens
8577 for stack frames that don't allocate other data, so we assume
8578 the stack pointer is now pointing at the return address, i.e.
8579 the function entry state, which makes the offset be 1 word. */
8580 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8581 && reg == hard_frame_pointer_rtx)
8583 ix86_cfa_state->reg = stack_pointer_rtx;
8584 ix86_cfa_state->offset = UNITS_PER_WORD;
8586 add_reg_note (insn, REG_CFA_DEF_CFA,
8587 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8588 GEN_INT (UNITS_PER_WORD)));
8589 RTX_FRAME_RELATED_P (insn) = 1;
8592 ix86_add_cfa_restore_note (insn, reg, red_offset);
8595 /* Emit code to restore saved registers using POP insns. */
8598 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8602 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8603 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8605 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8607 red_offset += UNITS_PER_WORD;
8611 /* Emit code and notes for the LEAVE instruction. */
8614 ix86_emit_leave (HOST_WIDE_INT red_offset)
8616 rtx insn = emit_insn (ix86_gen_leave ());
8618 ix86_add_queued_cfa_restore_notes (insn);
8620 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8622 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8623 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8624 RTX_FRAME_RELATED_P (insn) = 1;
8625 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8629 /* Emit code to restore saved registers using MOV insns. First register
8630 is restored from POINTER + OFFSET. */
8632 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8633 HOST_WIDE_INT red_offset,
8634 int maybe_eh_return)
8637 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8640 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8641 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8643 rtx reg = gen_rtx_REG (Pmode, regno);
8645 /* Ensure that adjust_address won't be forced to produce pointer
8646 out of range allowed by x86-64 instruction set. */
8647 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8651 r11 = gen_rtx_REG (DImode, R11_REG);
8652 emit_move_insn (r11, GEN_INT (offset));
8653 emit_insn (gen_adddi3 (r11, r11, pointer));
8654 base_address = gen_rtx_MEM (Pmode, r11);
8657 insn = emit_move_insn (reg,
8658 adjust_address (base_address, Pmode, offset));
8659 offset += UNITS_PER_WORD;
8661 if (ix86_cfa_state->reg == crtl->drap_reg
8662 && regno == REGNO (crtl->drap_reg))
8664 /* Previously we'd represented the CFA as an expression
8665 like *(%ebp - 8). We've just popped that value from
8666 the stack, which means we need to reset the CFA to
8667 the drap register. This will remain until we restore
8668 the stack pointer. */
8669 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8670 RTX_FRAME_RELATED_P (insn) = 1;
8673 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8675 red_offset += UNITS_PER_WORD;
8679 /* Emit code to restore saved registers using MOV insns. First register
8680 is restored from POINTER + OFFSET. */
8682 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8683 HOST_WIDE_INT red_offset,
8684 int maybe_eh_return)
8687 rtx base_address = gen_rtx_MEM (TImode, pointer);
8690 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8691 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8693 rtx reg = gen_rtx_REG (TImode, regno);
8695 /* Ensure that adjust_address won't be forced to produce pointer
8696 out of range allowed by x86-64 instruction set. */
8697 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8701 r11 = gen_rtx_REG (DImode, R11_REG);
8702 emit_move_insn (r11, GEN_INT (offset));
8703 emit_insn (gen_adddi3 (r11, r11, pointer));
8704 base_address = gen_rtx_MEM (TImode, r11);
8707 mem = adjust_address (base_address, TImode, offset);
8708 set_mem_align (mem, 128);
8709 insn = emit_move_insn (reg, mem);
8712 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8718 /* Restore function stack, frame, and registers. */
8721 ix86_expand_epilogue (int style)
8724 struct ix86_frame frame;
8725 HOST_WIDE_INT offset, red_offset;
8726 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8729 ix86_finalize_stack_realign_flags ();
8731 /* When stack is realigned, SP must be valid. */
8732 sp_valid = (!frame_pointer_needed
8733 || current_function_sp_is_unchanging
8734 || stack_realign_fp);
8736 ix86_compute_frame_layout (&frame);
8738 /* See the comment about red zone and frame
8739 pointer usage in ix86_expand_prologue. */
8740 if (frame_pointer_needed && frame.red_zone_size)
8741 emit_insn (gen_memory_blockage ());
8743 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8744 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8746 /* Calculate start of saved registers relative to ebp. Special care
8747 must be taken for the normal return case of a function using
8748 eh_return: the eax and edx registers are marked as saved, but not
8749 restored along this path. */
8750 offset = frame.nregs;
8751 if (crtl->calls_eh_return && style != 2)
8753 offset *= -UNITS_PER_WORD;
8754 offset -= frame.nsseregs * 16 + frame.padding0;
8756 /* Calculate start of saved registers relative to esp on entry of the
8757 function. When realigning stack, this needs to be the most negative
8758 value possible at runtime. */
8759 red_offset = offset;
8761 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8763 else if (stack_realign_fp)
8764 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8766 if (frame_pointer_needed)
8767 red_offset -= UNITS_PER_WORD;
8769 /* If we're only restoring one register and sp is not valid then
8770 using a move instruction to restore the register since it's
8771 less work than reloading sp and popping the register.
8773 The default code result in stack adjustment using add/lea instruction,
8774 while this code results in LEAVE instruction (or discrete equivalent),
8775 so it is profitable in some other cases as well. Especially when there
8776 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8777 and there is exactly one register to pop. This heuristic may need some
8778 tuning in future. */
8779 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8780 || (TARGET_EPILOGUE_USING_MOVE
8781 && cfun->machine->use_fast_prologue_epilogue
8782 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8783 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8784 && frame.to_allocate)
8785 || (frame_pointer_needed && TARGET_USE_LEAVE
8786 && cfun->machine->use_fast_prologue_epilogue
8787 && (frame.nregs + frame.nsseregs) == 1)
8788 || crtl->calls_eh_return)
8790 /* Restore registers. We can use ebp or esp to address the memory
8791 locations. If both are available, default to ebp, since offsets
8792 are known to be small. Only exception is esp pointing directly
8793 to the end of block of saved registers, where we may simplify
8796 If we are realigning stack with bp and sp, regs restore can't
8797 be addressed by bp. sp must be used instead. */
8799 if (!frame_pointer_needed
8800 || (sp_valid && !frame.to_allocate)
8801 || stack_realign_fp)
8803 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8804 frame.to_allocate, red_offset,
8806 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8808 + frame.nsseregs * 16
8811 + frame.nsseregs * 16
8812 + frame.padding0, style == 2);
8816 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8819 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8821 + frame.nsseregs * 16
8824 + frame.nsseregs * 16
8825 + frame.padding0, style == 2);
8828 red_offset -= offset;
8830 /* eh_return epilogues need %ecx added to the stack pointer. */
8833 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8835 /* Stack align doesn't work with eh_return. */
8836 gcc_assert (!crtl->stack_realign_needed);
8838 if (frame_pointer_needed)
8840 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8841 tmp = plus_constant (tmp, UNITS_PER_WORD);
8842 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8844 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8845 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
8847 /* Note that we use SA as a temporary CFA, as the return
8848 address is at the proper place relative to it. We
8849 pretend this happens at the FP restore insn because
8850 prior to this insn the FP would be stored at the wrong
8851 offset relative to SA, and after this insn we have no
8852 other reasonable register to use for the CFA. We don't
8853 bother resetting the CFA to the SP for the duration of
8855 add_reg_note (tmp, REG_CFA_DEF_CFA,
8856 plus_constant (sa, UNITS_PER_WORD));
8857 ix86_add_queued_cfa_restore_notes (tmp);
8858 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8859 RTX_FRAME_RELATED_P (tmp) = 1;
8860 ix86_cfa_state->reg = sa;
8861 ix86_cfa_state->offset = UNITS_PER_WORD;
8863 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8864 const0_rtx, style, false);
8868 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8869 tmp = plus_constant (tmp, (frame.to_allocate
8870 + frame.nregs * UNITS_PER_WORD
8871 + frame.nsseregs * 16
8873 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8874 ix86_add_queued_cfa_restore_notes (tmp);
8876 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
8877 if (ix86_cfa_state->offset != UNITS_PER_WORD)
8879 ix86_cfa_state->offset = UNITS_PER_WORD;
8880 add_reg_note (tmp, REG_CFA_DEF_CFA,
8881 plus_constant (stack_pointer_rtx,
8883 RTX_FRAME_RELATED_P (tmp) = 1;
8887 else if (!frame_pointer_needed)
8888 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8889 GEN_INT (frame.to_allocate
8890 + frame.nregs * UNITS_PER_WORD
8891 + frame.nsseregs * 16
8893 style, !using_drap);
8894 /* If not an i386, mov & pop is faster than "leave". */
8895 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8896 || !cfun->machine->use_fast_prologue_epilogue)
8897 ix86_emit_leave (red_offset);
8900 pro_epilogue_adjust_stack (stack_pointer_rtx,
8901 hard_frame_pointer_rtx,
8902 const0_rtx, style, !using_drap);
8904 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
8909 /* First step is to deallocate the stack frame so that we can
8912 If we realign stack with frame pointer, then stack pointer
8913 won't be able to recover via lea $offset(%bp), %sp, because
8914 there is a padding area between bp and sp for realign.
8915 "add $to_allocate, %sp" must be used instead. */
8918 gcc_assert (frame_pointer_needed);
8919 gcc_assert (!stack_realign_fp);
8920 pro_epilogue_adjust_stack (stack_pointer_rtx,
8921 hard_frame_pointer_rtx,
8922 GEN_INT (offset), style, false);
8923 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8924 frame.to_allocate, red_offset,
8926 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8927 GEN_INT (frame.nsseregs * 16),
8930 else if (frame.to_allocate || frame.nsseregs)
8932 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8933 frame.to_allocate, red_offset,
8935 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8936 GEN_INT (frame.to_allocate
8937 + frame.nsseregs * 16
8938 + frame.padding0), style,
8939 !using_drap && !frame_pointer_needed);
8942 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
8944 red_offset -= offset;
8946 if (frame_pointer_needed)
8948 /* Leave results in shorter dependency chains on CPUs that are
8949 able to grok it fast. */
8950 if (TARGET_USE_LEAVE)
8951 ix86_emit_leave (red_offset);
8954 /* For stack realigned really happens, recover stack
8955 pointer to hard frame pointer is a must, if not using
8957 if (stack_realign_fp)
8958 pro_epilogue_adjust_stack (stack_pointer_rtx,
8959 hard_frame_pointer_rtx,
8960 const0_rtx, style, !using_drap);
8961 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
8969 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8970 ? 0 : UNITS_PER_WORD);
8973 gcc_assert (stack_realign_drap);
8975 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8977 GEN_INT (-(UNITS_PER_WORD
8978 + param_ptr_offset))));
8980 ix86_cfa_state->reg = stack_pointer_rtx;
8981 ix86_cfa_state->offset = UNITS_PER_WORD + param_ptr_offset;
8983 add_reg_note (insn, REG_CFA_DEF_CFA,
8984 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
8985 GEN_INT (ix86_cfa_state->offset)));
8986 RTX_FRAME_RELATED_P (insn) = 1;
8988 if (param_ptr_offset)
8989 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
8992 /* Sibcall epilogues don't want a return instruction. */
8995 *ix86_cfa_state = cfa_state_save;
8999 if (crtl->args.pops_args && crtl->args.size)
9001 rtx popc = GEN_INT (crtl->args.pops_args);
9003 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9004 address, do explicit add, and jump indirectly to the caller. */
9006 if (crtl->args.pops_args >= 65536)
9008 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9011 /* There is no "pascal" calling convention in any 64bit ABI. */
9012 gcc_assert (!TARGET_64BIT);
9014 insn = emit_insn (gen_popsi1 (ecx));
9015 ix86_cfa_state->offset -= UNITS_PER_WORD;
9017 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9018 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9019 add_reg_note (insn, REG_CFA_REGISTER,
9020 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9021 RTX_FRAME_RELATED_P (insn) = 1;
9023 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9025 emit_jump_insn (gen_return_indirect_internal (ecx));
9028 emit_jump_insn (gen_return_pop_internal (popc));
9031 emit_jump_insn (gen_return_internal ());
9033 /* Restore the state back to the state from the prologue,
9034 so that it's correct for the next epilogue. */
9035 *ix86_cfa_state = cfa_state_save;
9038 /* Reset from the function's potential modifications. */
9041 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9042 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9044 if (pic_offset_table_rtx)
9045 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9047 /* Mach-O doesn't support labels at the end of objects, so if
9048 it looks like we might want one, insert a NOP. */
9050 rtx insn = get_last_insn ();
9053 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9054 insn = PREV_INSN (insn);
9058 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9059 fputs ("\tnop\n", file);
9065 /* Extract the parts of an RTL expression that is a valid memory address
9066 for an instruction. Return 0 if the structure of the address is
9067 grossly off. Return -1 if the address contains ASHIFT, so it is not
9068 strictly valid, but still used for computing length of lea instruction. */
9071 ix86_decompose_address (rtx addr, struct ix86_address *out)
9073 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9074 rtx base_reg, index_reg;
9075 HOST_WIDE_INT scale = 1;
9076 rtx scale_rtx = NULL_RTX;
9078 enum ix86_address_seg seg = SEG_DEFAULT;
9080 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9082 else if (GET_CODE (addr) == PLUS)
9092 addends[n++] = XEXP (op, 1);
9095 while (GET_CODE (op) == PLUS);
9100 for (i = n; i >= 0; --i)
9103 switch (GET_CODE (op))
9108 index = XEXP (op, 0);
9109 scale_rtx = XEXP (op, 1);
9113 if (XINT (op, 1) == UNSPEC_TP
9114 && TARGET_TLS_DIRECT_SEG_REFS
9115 && seg == SEG_DEFAULT)
9116 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9145 else if (GET_CODE (addr) == MULT)
9147 index = XEXP (addr, 0); /* index*scale */
9148 scale_rtx = XEXP (addr, 1);
9150 else if (GET_CODE (addr) == ASHIFT)
9154 /* We're called for lea too, which implements ashift on occasion. */
9155 index = XEXP (addr, 0);
9156 tmp = XEXP (addr, 1);
9157 if (!CONST_INT_P (tmp))
9159 scale = INTVAL (tmp);
9160 if ((unsigned HOST_WIDE_INT) scale > 3)
9166 disp = addr; /* displacement */
9168 /* Extract the integral value of scale. */
9171 if (!CONST_INT_P (scale_rtx))
9173 scale = INTVAL (scale_rtx);
9176 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9177 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9179 /* Avoid useless 0 displacement. */
9180 if (disp == const0_rtx && (base || index))
9183 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9184 if (base_reg && index_reg && scale == 1
9185 && (index_reg == arg_pointer_rtx
9186 || index_reg == frame_pointer_rtx
9187 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9190 tmp = base, base = index, index = tmp;
9191 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9194 /* Special case: %ebp cannot be encoded as a base without a displacement.
9198 && (base_reg == hard_frame_pointer_rtx
9199 || base_reg == frame_pointer_rtx
9200 || base_reg == arg_pointer_rtx
9201 || (REG_P (base_reg)
9202 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9203 || REGNO (base_reg) == R13_REG))))
9206 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9207 Avoid this by transforming to [%esi+0].
9208 Reload calls address legitimization without cfun defined, so we need
9209 to test cfun for being non-NULL. */
9210 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9211 && base_reg && !index_reg && !disp
9213 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9216 /* Special case: encode reg+reg instead of reg*2. */
9217 if (!base && index && scale == 2)
9218 base = index, base_reg = index_reg, scale = 1;
9220 /* Special case: scaling cannot be encoded without base or displacement. */
9221 if (!base && !disp && index && scale != 1)
9233 /* Return cost of the memory address x.
9234 For i386, it is better to use a complex address than let gcc copy
9235 the address into a reg and make a new pseudo. But not if the address
9236 requires to two regs - that would mean more pseudos with longer
9239 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9241 struct ix86_address parts;
9243 int ok = ix86_decompose_address (x, &parts);
9247 if (parts.base && GET_CODE (parts.base) == SUBREG)
9248 parts.base = SUBREG_REG (parts.base);
9249 if (parts.index && GET_CODE (parts.index) == SUBREG)
9250 parts.index = SUBREG_REG (parts.index);
9252 /* Attempt to minimize number of registers in the address. */
9254 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9256 && (!REG_P (parts.index)
9257 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9261 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9263 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9264 && parts.base != parts.index)
9267 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9268 since it's predecode logic can't detect the length of instructions
9269 and it degenerates to vector decoded. Increase cost of such
9270 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9271 to split such addresses or even refuse such addresses at all.
9273 Following addressing modes are affected:
9278 The first and last case may be avoidable by explicitly coding the zero in
9279 memory address, but I don't have AMD-K6 machine handy to check this
9283 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9284 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9285 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9291 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9292 this is used for to form addresses to local data when -fPIC is in
9296 darwin_local_data_pic (rtx disp)
9298 return (GET_CODE (disp) == UNSPEC
9299 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9302 /* Determine if a given RTX is a valid constant. We already know this
9303 satisfies CONSTANT_P. */
9306 legitimate_constant_p (rtx x)
9308 switch (GET_CODE (x))
9313 if (GET_CODE (x) == PLUS)
9315 if (!CONST_INT_P (XEXP (x, 1)))
9320 if (TARGET_MACHO && darwin_local_data_pic (x))
9323 /* Only some unspecs are valid as "constants". */
9324 if (GET_CODE (x) == UNSPEC)
9325 switch (XINT (x, 1))
9330 return TARGET_64BIT;
9333 x = XVECEXP (x, 0, 0);
9334 return (GET_CODE (x) == SYMBOL_REF
9335 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9337 x = XVECEXP (x, 0, 0);
9338 return (GET_CODE (x) == SYMBOL_REF
9339 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9344 /* We must have drilled down to a symbol. */
9345 if (GET_CODE (x) == LABEL_REF)
9347 if (GET_CODE (x) != SYMBOL_REF)
9352 /* TLS symbols are never valid. */
9353 if (SYMBOL_REF_TLS_MODEL (x))
9356 /* DLLIMPORT symbols are never valid. */
9357 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9358 && SYMBOL_REF_DLLIMPORT_P (x))
9363 if (GET_MODE (x) == TImode
9364 && x != CONST0_RTX (TImode)
9370 if (!standard_sse_constant_p (x))
9377 /* Otherwise we handle everything else in the move patterns. */
9381 /* Determine if it's legal to put X into the constant pool. This
9382 is not possible for the address of thread-local symbols, which
9383 is checked above. */
9386 ix86_cannot_force_const_mem (rtx x)
9388 /* We can always put integral constants and vectors in memory. */
9389 switch (GET_CODE (x))
9399 return !legitimate_constant_p (x);
9403 /* Nonzero if the constant value X is a legitimate general operand
9404 when generating PIC code. It is given that flag_pic is on and
9405 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9408 legitimate_pic_operand_p (rtx x)
9412 switch (GET_CODE (x))
9415 inner = XEXP (x, 0);
9416 if (GET_CODE (inner) == PLUS
9417 && CONST_INT_P (XEXP (inner, 1)))
9418 inner = XEXP (inner, 0);
9420 /* Only some unspecs are valid as "constants". */
9421 if (GET_CODE (inner) == UNSPEC)
9422 switch (XINT (inner, 1))
9427 return TARGET_64BIT;
9429 x = XVECEXP (inner, 0, 0);
9430 return (GET_CODE (x) == SYMBOL_REF
9431 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9432 case UNSPEC_MACHOPIC_OFFSET:
9433 return legitimate_pic_address_disp_p (x);
9441 return legitimate_pic_address_disp_p (x);
9448 /* Determine if a given CONST RTX is a valid memory displacement
9452 legitimate_pic_address_disp_p (rtx disp)
9456 /* In 64bit mode we can allow direct addresses of symbols and labels
9457 when they are not dynamic symbols. */
9460 rtx op0 = disp, op1;
9462 switch (GET_CODE (disp))
9468 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9470 op0 = XEXP (XEXP (disp, 0), 0);
9471 op1 = XEXP (XEXP (disp, 0), 1);
9472 if (!CONST_INT_P (op1)
9473 || INTVAL (op1) >= 16*1024*1024
9474 || INTVAL (op1) < -16*1024*1024)
9476 if (GET_CODE (op0) == LABEL_REF)
9478 if (GET_CODE (op0) != SYMBOL_REF)
9483 /* TLS references should always be enclosed in UNSPEC. */
9484 if (SYMBOL_REF_TLS_MODEL (op0))
9486 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9487 && ix86_cmodel != CM_LARGE_PIC)
9495 if (GET_CODE (disp) != CONST)
9497 disp = XEXP (disp, 0);
9501 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9502 of GOT tables. We should not need these anyway. */
9503 if (GET_CODE (disp) != UNSPEC
9504 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9505 && XINT (disp, 1) != UNSPEC_GOTOFF
9506 && XINT (disp, 1) != UNSPEC_PLTOFF))
9509 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9510 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9516 if (GET_CODE (disp) == PLUS)
9518 if (!CONST_INT_P (XEXP (disp, 1)))
9520 disp = XEXP (disp, 0);
9524 if (TARGET_MACHO && darwin_local_data_pic (disp))
9527 if (GET_CODE (disp) != UNSPEC)
9530 switch (XINT (disp, 1))
9535 /* We need to check for both symbols and labels because VxWorks loads
9536 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9538 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9539 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9541 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9542 While ABI specify also 32bit relocation but we don't produce it in
9543 small PIC model at all. */
9544 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9545 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9547 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9549 case UNSPEC_GOTTPOFF:
9550 case UNSPEC_GOTNTPOFF:
9551 case UNSPEC_INDNTPOFF:
9554 disp = XVECEXP (disp, 0, 0);
9555 return (GET_CODE (disp) == SYMBOL_REF
9556 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9558 disp = XVECEXP (disp, 0, 0);
9559 return (GET_CODE (disp) == SYMBOL_REF
9560 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9562 disp = XVECEXP (disp, 0, 0);
9563 return (GET_CODE (disp) == SYMBOL_REF
9564 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9570 /* Recognizes RTL expressions that are valid memory addresses for an
9571 instruction. The MODE argument is the machine mode for the MEM
9572 expression that wants to use this address.
9574 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9575 convert common non-canonical forms to canonical form so that they will
9579 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9580 rtx addr, bool strict)
9582 struct ix86_address parts;
9583 rtx base, index, disp;
9584 HOST_WIDE_INT scale;
9585 const char *reason = NULL;
9586 rtx reason_rtx = NULL_RTX;
9588 if (ix86_decompose_address (addr, &parts) <= 0)
9590 reason = "decomposition failed";
9595 index = parts.index;
9597 scale = parts.scale;
9599 /* Validate base register.
9601 Don't allow SUBREG's that span more than a word here. It can lead to spill
9602 failures when the base is one word out of a two word structure, which is
9603 represented internally as a DImode int. */
9612 else if (GET_CODE (base) == SUBREG
9613 && REG_P (SUBREG_REG (base))
9614 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9616 reg = SUBREG_REG (base);
9619 reason = "base is not a register";
9623 if (GET_MODE (base) != Pmode)
9625 reason = "base is not in Pmode";
9629 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9630 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9632 reason = "base is not valid";
9637 /* Validate index register.
9639 Don't allow SUBREG's that span more than a word here -- same as above. */
9648 else if (GET_CODE (index) == SUBREG
9649 && REG_P (SUBREG_REG (index))
9650 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9652 reg = SUBREG_REG (index);
9655 reason = "index is not a register";
9659 if (GET_MODE (index) != Pmode)
9661 reason = "index is not in Pmode";
9665 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9666 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9668 reason = "index is not valid";
9673 /* Validate scale factor. */
9676 reason_rtx = GEN_INT (scale);
9679 reason = "scale without index";
9683 if (scale != 2 && scale != 4 && scale != 8)
9685 reason = "scale is not a valid multiplier";
9690 /* Validate displacement. */
9695 if (GET_CODE (disp) == CONST
9696 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9697 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9698 switch (XINT (XEXP (disp, 0), 1))
9700 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9701 used. While ABI specify also 32bit relocations, we don't produce
9702 them at all and use IP relative instead. */
9705 gcc_assert (flag_pic);
9707 goto is_legitimate_pic;
9708 reason = "64bit address unspec";
9711 case UNSPEC_GOTPCREL:
9712 gcc_assert (flag_pic);
9713 goto is_legitimate_pic;
9715 case UNSPEC_GOTTPOFF:
9716 case UNSPEC_GOTNTPOFF:
9717 case UNSPEC_INDNTPOFF:
9723 reason = "invalid address unspec";
9727 else if (SYMBOLIC_CONST (disp)
9731 && MACHOPIC_INDIRECT
9732 && !machopic_operand_p (disp)
9738 if (TARGET_64BIT && (index || base))
9740 /* foo@dtpoff(%rX) is ok. */
9741 if (GET_CODE (disp) != CONST
9742 || GET_CODE (XEXP (disp, 0)) != PLUS
9743 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9744 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9745 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9746 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9748 reason = "non-constant pic memory reference";
9752 else if (! legitimate_pic_address_disp_p (disp))
9754 reason = "displacement is an invalid pic construct";
9758 /* This code used to verify that a symbolic pic displacement
9759 includes the pic_offset_table_rtx register.
9761 While this is good idea, unfortunately these constructs may
9762 be created by "adds using lea" optimization for incorrect
9771 This code is nonsensical, but results in addressing
9772 GOT table with pic_offset_table_rtx base. We can't
9773 just refuse it easily, since it gets matched by
9774 "addsi3" pattern, that later gets split to lea in the
9775 case output register differs from input. While this
9776 can be handled by separate addsi pattern for this case
9777 that never results in lea, this seems to be easier and
9778 correct fix for crash to disable this test. */
9780 else if (GET_CODE (disp) != LABEL_REF
9781 && !CONST_INT_P (disp)
9782 && (GET_CODE (disp) != CONST
9783 || !legitimate_constant_p (disp))
9784 && (GET_CODE (disp) != SYMBOL_REF
9785 || !legitimate_constant_p (disp)))
9787 reason = "displacement is not constant";
9790 else if (TARGET_64BIT
9791 && !x86_64_immediate_operand (disp, VOIDmode))
9793 reason = "displacement is out of range";
9798 /* Everything looks valid. */
9805 /* Determine if a given RTX is a valid constant address. */
9808 constant_address_p (rtx x)
9810 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9813 /* Return a unique alias set for the GOT. */
9815 static alias_set_type
9816 ix86_GOT_alias_set (void)
9818 static alias_set_type set = -1;
9820 set = new_alias_set ();
9824 /* Return a legitimate reference for ORIG (an address) using the
9825 register REG. If REG is 0, a new pseudo is generated.
9827 There are two types of references that must be handled:
9829 1. Global data references must load the address from the GOT, via
9830 the PIC reg. An insn is emitted to do this load, and the reg is
9833 2. Static data references, constant pool addresses, and code labels
9834 compute the address as an offset from the GOT, whose base is in
9835 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9836 differentiate them from global data objects. The returned
9837 address is the PIC reg + an unspec constant.
9839 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9840 reg also appears in the address. */
9843 legitimize_pic_address (rtx orig, rtx reg)
9850 if (TARGET_MACHO && !TARGET_64BIT)
9853 reg = gen_reg_rtx (Pmode);
9854 /* Use the generic Mach-O PIC machinery. */
9855 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9859 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9861 else if (TARGET_64BIT
9862 && ix86_cmodel != CM_SMALL_PIC
9863 && gotoff_operand (addr, Pmode))
9866 /* This symbol may be referenced via a displacement from the PIC
9867 base address (@GOTOFF). */
9869 if (reload_in_progress)
9870 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9871 if (GET_CODE (addr) == CONST)
9872 addr = XEXP (addr, 0);
9873 if (GET_CODE (addr) == PLUS)
9875 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9877 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9880 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9881 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9883 tmpreg = gen_reg_rtx (Pmode);
9886 emit_move_insn (tmpreg, new_rtx);
9890 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9891 tmpreg, 1, OPTAB_DIRECT);
9894 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9896 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9898 /* This symbol may be referenced via a displacement from the PIC
9899 base address (@GOTOFF). */
9901 if (reload_in_progress)
9902 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9903 if (GET_CODE (addr) == CONST)
9904 addr = XEXP (addr, 0);
9905 if (GET_CODE (addr) == PLUS)
9907 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9909 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9912 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9913 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9914 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9918 emit_move_insn (reg, new_rtx);
9922 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9923 /* We can't use @GOTOFF for text labels on VxWorks;
9924 see gotoff_operand. */
9925 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9927 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9929 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9930 return legitimize_dllimport_symbol (addr, true);
9931 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9932 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9933 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9935 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9936 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9940 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9942 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9943 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9944 new_rtx = gen_const_mem (Pmode, new_rtx);
9945 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9948 reg = gen_reg_rtx (Pmode);
9949 /* Use directly gen_movsi, otherwise the address is loaded
9950 into register for CSE. We don't want to CSE this addresses,
9951 instead we CSE addresses from the GOT table, so skip this. */
9952 emit_insn (gen_movsi (reg, new_rtx));
9957 /* This symbol must be referenced via a load from the
9958 Global Offset Table (@GOT). */
9960 if (reload_in_progress)
9961 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9962 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9963 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9965 new_rtx = force_reg (Pmode, new_rtx);
9966 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9967 new_rtx = gen_const_mem (Pmode, new_rtx);
9968 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9971 reg = gen_reg_rtx (Pmode);
9972 emit_move_insn (reg, new_rtx);
9978 if (CONST_INT_P (addr)
9979 && !x86_64_immediate_operand (addr, VOIDmode))
9983 emit_move_insn (reg, addr);
9987 new_rtx = force_reg (Pmode, addr);
9989 else if (GET_CODE (addr) == CONST)
9991 addr = XEXP (addr, 0);
9993 /* We must match stuff we generate before. Assume the only
9994 unspecs that can get here are ours. Not that we could do
9995 anything with them anyway.... */
9996 if (GET_CODE (addr) == UNSPEC
9997 || (GET_CODE (addr) == PLUS
9998 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10000 gcc_assert (GET_CODE (addr) == PLUS);
10002 if (GET_CODE (addr) == PLUS)
10004 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10006 /* Check first to see if this is a constant offset from a @GOTOFF
10007 symbol reference. */
10008 if (gotoff_operand (op0, Pmode)
10009 && CONST_INT_P (op1))
10013 if (reload_in_progress)
10014 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10015 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10017 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10018 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10019 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10023 emit_move_insn (reg, new_rtx);
10029 if (INTVAL (op1) < -16*1024*1024
10030 || INTVAL (op1) >= 16*1024*1024)
10032 if (!x86_64_immediate_operand (op1, Pmode))
10033 op1 = force_reg (Pmode, op1);
10034 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10040 base = legitimize_pic_address (XEXP (addr, 0), reg);
10041 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10042 base == reg ? NULL_RTX : reg);
10044 if (CONST_INT_P (new_rtx))
10045 new_rtx = plus_constant (base, INTVAL (new_rtx));
10048 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10050 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10051 new_rtx = XEXP (new_rtx, 1);
10053 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10061 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10064 get_thread_pointer (int to_reg)
10068 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10072 reg = gen_reg_rtx (Pmode);
10073 insn = gen_rtx_SET (VOIDmode, reg, tp);
10074 insn = emit_insn (insn);
10079 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10080 false if we expect this to be used for a memory address and true if
10081 we expect to load the address into a register. */
10084 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10086 rtx dest, base, off, pic, tp;
10091 case TLS_MODEL_GLOBAL_DYNAMIC:
10092 dest = gen_reg_rtx (Pmode);
10093 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10095 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10097 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10100 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10101 insns = get_insns ();
10104 RTL_CONST_CALL_P (insns) = 1;
10105 emit_libcall_block (insns, dest, rax, x);
10107 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10108 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10110 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10112 if (TARGET_GNU2_TLS)
10114 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10116 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10120 case TLS_MODEL_LOCAL_DYNAMIC:
10121 base = gen_reg_rtx (Pmode);
10122 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10124 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10126 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10129 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10130 insns = get_insns ();
10133 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10134 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10135 RTL_CONST_CALL_P (insns) = 1;
10136 emit_libcall_block (insns, base, rax, note);
10138 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10139 emit_insn (gen_tls_local_dynamic_base_64 (base));
10141 emit_insn (gen_tls_local_dynamic_base_32 (base));
10143 if (TARGET_GNU2_TLS)
10145 rtx x = ix86_tls_module_base ();
10147 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10148 gen_rtx_MINUS (Pmode, x, tp));
10151 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10152 off = gen_rtx_CONST (Pmode, off);
10154 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10156 if (TARGET_GNU2_TLS)
10158 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10160 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10165 case TLS_MODEL_INITIAL_EXEC:
10169 type = UNSPEC_GOTNTPOFF;
10173 if (reload_in_progress)
10174 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10175 pic = pic_offset_table_rtx;
10176 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10178 else if (!TARGET_ANY_GNU_TLS)
10180 pic = gen_reg_rtx (Pmode);
10181 emit_insn (gen_set_got (pic));
10182 type = UNSPEC_GOTTPOFF;
10187 type = UNSPEC_INDNTPOFF;
10190 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10191 off = gen_rtx_CONST (Pmode, off);
10193 off = gen_rtx_PLUS (Pmode, pic, off);
10194 off = gen_const_mem (Pmode, off);
10195 set_mem_alias_set (off, ix86_GOT_alias_set ());
10197 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10199 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10200 off = force_reg (Pmode, off);
10201 return gen_rtx_PLUS (Pmode, base, off);
10205 base = get_thread_pointer (true);
10206 dest = gen_reg_rtx (Pmode);
10207 emit_insn (gen_subsi3 (dest, base, off));
10211 case TLS_MODEL_LOCAL_EXEC:
10212 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10213 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10214 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10215 off = gen_rtx_CONST (Pmode, off);
10217 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10219 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10220 return gen_rtx_PLUS (Pmode, base, off);
10224 base = get_thread_pointer (true);
10225 dest = gen_reg_rtx (Pmode);
10226 emit_insn (gen_subsi3 (dest, base, off));
10231 gcc_unreachable ();
10237 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10240 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10241 htab_t dllimport_map;
10244 get_dllimport_decl (tree decl)
10246 struct tree_map *h, in;
10249 const char *prefix;
10250 size_t namelen, prefixlen;
10255 if (!dllimport_map)
10256 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10258 in.hash = htab_hash_pointer (decl);
10259 in.base.from = decl;
10260 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10261 h = (struct tree_map *) *loc;
10265 *loc = h = GGC_NEW (struct tree_map);
10267 h->base.from = decl;
10268 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10269 VAR_DECL, NULL, ptr_type_node);
10270 DECL_ARTIFICIAL (to) = 1;
10271 DECL_IGNORED_P (to) = 1;
10272 DECL_EXTERNAL (to) = 1;
10273 TREE_READONLY (to) = 1;
10275 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10276 name = targetm.strip_name_encoding (name);
10277 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10278 ? "*__imp_" : "*__imp__";
10279 namelen = strlen (name);
10280 prefixlen = strlen (prefix);
10281 imp_name = (char *) alloca (namelen + prefixlen + 1);
10282 memcpy (imp_name, prefix, prefixlen);
10283 memcpy (imp_name + prefixlen, name, namelen + 1);
10285 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10286 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10287 SET_SYMBOL_REF_DECL (rtl, to);
10288 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10290 rtl = gen_const_mem (Pmode, rtl);
10291 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10293 SET_DECL_RTL (to, rtl);
10294 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10299 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10300 true if we require the result be a register. */
10303 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10308 gcc_assert (SYMBOL_REF_DECL (symbol));
10309 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10311 x = DECL_RTL (imp_decl);
10313 x = force_reg (Pmode, x);
10317 /* Try machine-dependent ways of modifying an illegitimate address
10318 to be legitimate. If we find one, return the new, valid address.
10319 This macro is used in only one place: `memory_address' in explow.c.
10321 OLDX is the address as it was before break_out_memory_refs was called.
10322 In some cases it is useful to look at this to decide what needs to be done.
10324 It is always safe for this macro to do nothing. It exists to recognize
10325 opportunities to optimize the output.
10327 For the 80386, we handle X+REG by loading X into a register R and
10328 using R+REG. R will go in a general reg and indexing will be used.
10329 However, if REG is a broken-out memory address or multiplication,
10330 nothing needs to be done because REG can certainly go in a general reg.
10332 When -fpic is used, special handling is needed for symbolic references.
10333 See comments by legitimize_pic_address in i386.c for details. */
10336 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10337 enum machine_mode mode)
10342 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10344 return legitimize_tls_address (x, (enum tls_model) log, false);
10345 if (GET_CODE (x) == CONST
10346 && GET_CODE (XEXP (x, 0)) == PLUS
10347 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10348 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10350 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10351 (enum tls_model) log, false);
10352 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10355 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10357 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10358 return legitimize_dllimport_symbol (x, true);
10359 if (GET_CODE (x) == CONST
10360 && GET_CODE (XEXP (x, 0)) == PLUS
10361 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10362 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10364 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10365 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10369 if (flag_pic && SYMBOLIC_CONST (x))
10370 return legitimize_pic_address (x, 0);
10372 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10373 if (GET_CODE (x) == ASHIFT
10374 && CONST_INT_P (XEXP (x, 1))
10375 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10378 log = INTVAL (XEXP (x, 1));
10379 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10380 GEN_INT (1 << log));
10383 if (GET_CODE (x) == PLUS)
10385 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10387 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10388 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10389 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10392 log = INTVAL (XEXP (XEXP (x, 0), 1));
10393 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10394 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10395 GEN_INT (1 << log));
10398 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10399 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10400 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10403 log = INTVAL (XEXP (XEXP (x, 1), 1));
10404 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10405 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10406 GEN_INT (1 << log));
10409 /* Put multiply first if it isn't already. */
10410 if (GET_CODE (XEXP (x, 1)) == MULT)
10412 rtx tmp = XEXP (x, 0);
10413 XEXP (x, 0) = XEXP (x, 1);
10418 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10419 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10420 created by virtual register instantiation, register elimination, and
10421 similar optimizations. */
10422 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10425 x = gen_rtx_PLUS (Pmode,
10426 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10427 XEXP (XEXP (x, 1), 0)),
10428 XEXP (XEXP (x, 1), 1));
10432 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10433 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10434 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10435 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10436 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10437 && CONSTANT_P (XEXP (x, 1)))
10440 rtx other = NULL_RTX;
10442 if (CONST_INT_P (XEXP (x, 1)))
10444 constant = XEXP (x, 1);
10445 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10447 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10449 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10450 other = XEXP (x, 1);
10458 x = gen_rtx_PLUS (Pmode,
10459 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10460 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10461 plus_constant (other, INTVAL (constant)));
10465 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10468 if (GET_CODE (XEXP (x, 0)) == MULT)
10471 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10474 if (GET_CODE (XEXP (x, 1)) == MULT)
10477 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10481 && REG_P (XEXP (x, 1))
10482 && REG_P (XEXP (x, 0)))
10485 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10488 x = legitimize_pic_address (x, 0);
10491 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10494 if (REG_P (XEXP (x, 0)))
10496 rtx temp = gen_reg_rtx (Pmode);
10497 rtx val = force_operand (XEXP (x, 1), temp);
10499 emit_move_insn (temp, val);
10501 XEXP (x, 1) = temp;
10505 else if (REG_P (XEXP (x, 1)))
10507 rtx temp = gen_reg_rtx (Pmode);
10508 rtx val = force_operand (XEXP (x, 0), temp);
10510 emit_move_insn (temp, val);
10512 XEXP (x, 0) = temp;
10520 /* Print an integer constant expression in assembler syntax. Addition
10521 and subtraction are the only arithmetic that may appear in these
10522 expressions. FILE is the stdio stream to write to, X is the rtx, and
10523 CODE is the operand print code from the output string. */
10526 output_pic_addr_const (FILE *file, rtx x, int code)
10530 switch (GET_CODE (x))
10533 gcc_assert (flag_pic);
10538 if (! TARGET_MACHO || TARGET_64BIT)
10539 output_addr_const (file, x);
10542 const char *name = XSTR (x, 0);
10544 /* Mark the decl as referenced so that cgraph will
10545 output the function. */
10546 if (SYMBOL_REF_DECL (x))
10547 mark_decl_referenced (SYMBOL_REF_DECL (x));
10550 if (MACHOPIC_INDIRECT
10551 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10552 name = machopic_indirection_name (x, /*stub_p=*/true);
10554 assemble_name (file, name);
10556 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10557 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10558 fputs ("@PLT", file);
10565 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10566 assemble_name (asm_out_file, buf);
10570 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10574 /* This used to output parentheses around the expression,
10575 but that does not work on the 386 (either ATT or BSD assembler). */
10576 output_pic_addr_const (file, XEXP (x, 0), code);
10580 if (GET_MODE (x) == VOIDmode)
10582 /* We can use %d if the number is <32 bits and positive. */
10583 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10584 fprintf (file, "0x%lx%08lx",
10585 (unsigned long) CONST_DOUBLE_HIGH (x),
10586 (unsigned long) CONST_DOUBLE_LOW (x));
10588 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10591 /* We can't handle floating point constants;
10592 PRINT_OPERAND must handle them. */
10593 output_operand_lossage ("floating constant misused");
10597 /* Some assemblers need integer constants to appear first. */
10598 if (CONST_INT_P (XEXP (x, 0)))
10600 output_pic_addr_const (file, XEXP (x, 0), code);
10602 output_pic_addr_const (file, XEXP (x, 1), code);
10606 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10607 output_pic_addr_const (file, XEXP (x, 1), code);
10609 output_pic_addr_const (file, XEXP (x, 0), code);
10615 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10616 output_pic_addr_const (file, XEXP (x, 0), code);
10618 output_pic_addr_const (file, XEXP (x, 1), code);
10620 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10624 gcc_assert (XVECLEN (x, 0) == 1);
10625 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10626 switch (XINT (x, 1))
10629 fputs ("@GOT", file);
10631 case UNSPEC_GOTOFF:
10632 fputs ("@GOTOFF", file);
10634 case UNSPEC_PLTOFF:
10635 fputs ("@PLTOFF", file);
10637 case UNSPEC_GOTPCREL:
10638 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10639 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10641 case UNSPEC_GOTTPOFF:
10642 /* FIXME: This might be @TPOFF in Sun ld too. */
10643 fputs ("@GOTTPOFF", file);
10646 fputs ("@TPOFF", file);
10648 case UNSPEC_NTPOFF:
10650 fputs ("@TPOFF", file);
10652 fputs ("@NTPOFF", file);
10654 case UNSPEC_DTPOFF:
10655 fputs ("@DTPOFF", file);
10657 case UNSPEC_GOTNTPOFF:
10659 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10660 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10662 fputs ("@GOTNTPOFF", file);
10664 case UNSPEC_INDNTPOFF:
10665 fputs ("@INDNTPOFF", file);
10668 case UNSPEC_MACHOPIC_OFFSET:
10670 machopic_output_function_base_name (file);
10674 output_operand_lossage ("invalid UNSPEC as operand");
10680 output_operand_lossage ("invalid expression as operand");
10684 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10685 We need to emit DTP-relative relocations. */
10687 static void ATTRIBUTE_UNUSED
10688 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10690 fputs (ASM_LONG, file);
10691 output_addr_const (file, x);
10692 fputs ("@DTPOFF", file);
10698 fputs (", 0", file);
10701 gcc_unreachable ();
10705 /* Return true if X is a representation of the PIC register. This copes
10706 with calls from ix86_find_base_term, where the register might have
10707 been replaced by a cselib value. */
10710 ix86_pic_register_p (rtx x)
10712 if (GET_CODE (x) == VALUE)
10713 return (pic_offset_table_rtx
10714 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10716 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10719 /* In the name of slightly smaller debug output, and to cater to
10720 general assembler lossage, recognize PIC+GOTOFF and turn it back
10721 into a direct symbol reference.
10723 On Darwin, this is necessary to avoid a crash, because Darwin
10724 has a different PIC label for each routine but the DWARF debugging
10725 information is not associated with any particular routine, so it's
10726 necessary to remove references to the PIC label from RTL stored by
10727 the DWARF output code. */
10730 ix86_delegitimize_address (rtx orig_x)
10733 /* reg_addend is NULL or a multiple of some register. */
10734 rtx reg_addend = NULL_RTX;
10735 /* const_addend is NULL or a const_int. */
10736 rtx const_addend = NULL_RTX;
10737 /* This is the result, or NULL. */
10738 rtx result = NULL_RTX;
10745 if (GET_CODE (x) != CONST
10746 || GET_CODE (XEXP (x, 0)) != UNSPEC
10747 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10748 || !MEM_P (orig_x))
10750 return XVECEXP (XEXP (x, 0), 0, 0);
10753 if (GET_CODE (x) != PLUS
10754 || GET_CODE (XEXP (x, 1)) != CONST)
10757 if (ix86_pic_register_p (XEXP (x, 0)))
10758 /* %ebx + GOT/GOTOFF */
10760 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10762 /* %ebx + %reg * scale + GOT/GOTOFF */
10763 reg_addend = XEXP (x, 0);
10764 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10765 reg_addend = XEXP (reg_addend, 1);
10766 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10767 reg_addend = XEXP (reg_addend, 0);
10770 if (!REG_P (reg_addend)
10771 && GET_CODE (reg_addend) != MULT
10772 && GET_CODE (reg_addend) != ASHIFT)
10778 x = XEXP (XEXP (x, 1), 0);
10779 if (GET_CODE (x) == PLUS
10780 && CONST_INT_P (XEXP (x, 1)))
10782 const_addend = XEXP (x, 1);
10786 if (GET_CODE (x) == UNSPEC
10787 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10788 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10789 result = XVECEXP (x, 0, 0);
10791 if (TARGET_MACHO && darwin_local_data_pic (x)
10792 && !MEM_P (orig_x))
10793 result = XVECEXP (x, 0, 0);
10799 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10801 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10805 /* If X is a machine specific address (i.e. a symbol or label being
10806 referenced as a displacement from the GOT implemented using an
10807 UNSPEC), then return the base term. Otherwise return X. */
10810 ix86_find_base_term (rtx x)
10816 if (GET_CODE (x) != CONST)
10818 term = XEXP (x, 0);
10819 if (GET_CODE (term) == PLUS
10820 && (CONST_INT_P (XEXP (term, 1))
10821 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10822 term = XEXP (term, 0);
10823 if (GET_CODE (term) != UNSPEC
10824 || XINT (term, 1) != UNSPEC_GOTPCREL)
10827 return XVECEXP (term, 0, 0);
10830 return ix86_delegitimize_address (x);
10834 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10835 int fp, FILE *file)
10837 const char *suffix;
10839 if (mode == CCFPmode || mode == CCFPUmode)
10841 enum rtx_code second_code, bypass_code;
10842 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10843 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10844 code = ix86_fp_compare_code_to_integer (code);
10848 code = reverse_condition (code);
10899 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10903 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10904 Those same assemblers have the same but opposite lossage on cmov. */
10905 if (mode == CCmode)
10906 suffix = fp ? "nbe" : "a";
10907 else if (mode == CCCmode)
10910 gcc_unreachable ();
10926 gcc_unreachable ();
10930 gcc_assert (mode == CCmode || mode == CCCmode);
10947 gcc_unreachable ();
10951 /* ??? As above. */
10952 gcc_assert (mode == CCmode || mode == CCCmode);
10953 suffix = fp ? "nb" : "ae";
10956 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10960 /* ??? As above. */
10961 if (mode == CCmode)
10963 else if (mode == CCCmode)
10964 suffix = fp ? "nb" : "ae";
10966 gcc_unreachable ();
10969 suffix = fp ? "u" : "p";
10972 suffix = fp ? "nu" : "np";
10975 gcc_unreachable ();
10977 fputs (suffix, file);
10980 /* Print the name of register X to FILE based on its machine mode and number.
10981 If CODE is 'w', pretend the mode is HImode.
10982 If CODE is 'b', pretend the mode is QImode.
10983 If CODE is 'k', pretend the mode is SImode.
10984 If CODE is 'q', pretend the mode is DImode.
10985 If CODE is 'x', pretend the mode is V4SFmode.
10986 If CODE is 't', pretend the mode is V8SFmode.
10987 If CODE is 'h', pretend the reg is the 'high' byte register.
10988 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10989 If CODE is 'd', duplicate the operand for AVX instruction.
10993 print_reg (rtx x, int code, FILE *file)
10996 bool duplicated = code == 'd' && TARGET_AVX;
10998 gcc_assert (x == pc_rtx
10999 || (REGNO (x) != ARG_POINTER_REGNUM
11000 && REGNO (x) != FRAME_POINTER_REGNUM
11001 && REGNO (x) != FLAGS_REG
11002 && REGNO (x) != FPSR_REG
11003 && REGNO (x) != FPCR_REG));
11005 if (ASSEMBLER_DIALECT == ASM_ATT)
11010 gcc_assert (TARGET_64BIT);
11011 fputs ("rip", file);
11015 if (code == 'w' || MMX_REG_P (x))
11017 else if (code == 'b')
11019 else if (code == 'k')
11021 else if (code == 'q')
11023 else if (code == 'y')
11025 else if (code == 'h')
11027 else if (code == 'x')
11029 else if (code == 't')
11032 code = GET_MODE_SIZE (GET_MODE (x));
11034 /* Irritatingly, AMD extended registers use different naming convention
11035 from the normal registers. */
11036 if (REX_INT_REG_P (x))
11038 gcc_assert (TARGET_64BIT);
11042 error ("extended registers have no high halves");
11045 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11048 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11051 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11054 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11057 error ("unsupported operand size for extended register");
11067 if (STACK_TOP_P (x))
11076 if (! ANY_FP_REG_P (x))
11077 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11082 reg = hi_reg_name[REGNO (x)];
11085 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11087 reg = qi_reg_name[REGNO (x)];
11090 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11092 reg = qi_high_reg_name[REGNO (x)];
11097 gcc_assert (!duplicated);
11099 fputs (hi_reg_name[REGNO (x)] + 1, file);
11104 gcc_unreachable ();
11110 if (ASSEMBLER_DIALECT == ASM_ATT)
11111 fprintf (file, ", %%%s", reg);
11113 fprintf (file, ", %s", reg);
11117 /* Locate some local-dynamic symbol still in use by this function
11118 so that we can print its name in some tls_local_dynamic_base
11122 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11126 if (GET_CODE (x) == SYMBOL_REF
11127 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11129 cfun->machine->some_ld_name = XSTR (x, 0);
11136 static const char *
11137 get_some_local_dynamic_name (void)
11141 if (cfun->machine->some_ld_name)
11142 return cfun->machine->some_ld_name;
11144 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11146 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11147 return cfun->machine->some_ld_name;
11149 gcc_unreachable ();
11152 /* Meaning of CODE:
11153 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11154 C -- print opcode suffix for set/cmov insn.
11155 c -- like C, but print reversed condition
11156 E,e -- likewise, but for compare-and-branch fused insn.
11157 F,f -- likewise, but for floating-point.
11158 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11160 R -- print the prefix for register names.
11161 z -- print the opcode suffix for the size of the current operand.
11162 Z -- likewise, with special suffixes for x87 instructions.
11163 * -- print a star (in certain assembler syntax)
11164 A -- print an absolute memory reference.
11165 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11166 s -- print a shift double count, followed by the assemblers argument
11168 b -- print the QImode name of the register for the indicated operand.
11169 %b0 would print %al if operands[0] is reg 0.
11170 w -- likewise, print the HImode name of the register.
11171 k -- likewise, print the SImode name of the register.
11172 q -- likewise, print the DImode name of the register.
11173 x -- likewise, print the V4SFmode name of the register.
11174 t -- likewise, print the V8SFmode name of the register.
11175 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11176 y -- print "st(0)" instead of "st" as a register.
11177 d -- print duplicated register operand for AVX instruction.
11178 D -- print condition for SSE cmp instruction.
11179 P -- if PIC, print an @PLT suffix.
11180 X -- don't print any sort of PIC '@' suffix for a symbol.
11181 & -- print some in-use local-dynamic symbol name.
11182 H -- print a memory address offset by 8; used for sse high-parts
11183 Y -- print condition for SSE5 com* instruction.
11184 + -- print a branch hint as 'cs' or 'ds' prefix
11185 ; -- print a semicolon (after prefixes due to bug in older gas).
11189 print_operand (FILE *file, rtx x, int code)
11196 if (ASSEMBLER_DIALECT == ASM_ATT)
11201 assemble_name (file, get_some_local_dynamic_name ());
11205 switch (ASSEMBLER_DIALECT)
11212 /* Intel syntax. For absolute addresses, registers should not
11213 be surrounded by braces. */
11217 PRINT_OPERAND (file, x, 0);
11224 gcc_unreachable ();
11227 PRINT_OPERAND (file, x, 0);
11232 if (ASSEMBLER_DIALECT == ASM_ATT)
11237 if (ASSEMBLER_DIALECT == ASM_ATT)
11242 if (ASSEMBLER_DIALECT == ASM_ATT)
11247 if (ASSEMBLER_DIALECT == ASM_ATT)
11252 if (ASSEMBLER_DIALECT == ASM_ATT)
11257 if (ASSEMBLER_DIALECT == ASM_ATT)
11262 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11264 /* Opcodes don't get size suffixes if using Intel opcodes. */
11265 if (ASSEMBLER_DIALECT == ASM_INTEL)
11268 switch (GET_MODE_SIZE (GET_MODE (x)))
11287 output_operand_lossage
11288 ("invalid operand size for operand code '%c'", code);
11293 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11295 (0, "non-integer operand used with operand code '%c'", code);
11299 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11300 if (ASSEMBLER_DIALECT == ASM_INTEL)
11303 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11305 switch (GET_MODE_SIZE (GET_MODE (x)))
11308 #ifdef HAVE_AS_IX86_FILDS
11318 #ifdef HAVE_AS_IX86_FILDQ
11321 fputs ("ll", file);
11329 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11331 /* 387 opcodes don't get size suffixes
11332 if the operands are registers. */
11333 if (STACK_REG_P (x))
11336 switch (GET_MODE_SIZE (GET_MODE (x)))
11357 output_operand_lossage
11358 ("invalid operand type used with operand code '%c'", code);
11362 output_operand_lossage
11363 ("invalid operand size for operand code '%c'", code);
11380 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11382 PRINT_OPERAND (file, x, 0);
11383 fputs (", ", file);
11388 /* Little bit of braindamage here. The SSE compare instructions
11389 does use completely different names for the comparisons that the
11390 fp conditional moves. */
11393 switch (GET_CODE (x))
11396 fputs ("eq", file);
11399 fputs ("eq_us", file);
11402 fputs ("lt", file);
11405 fputs ("nge", file);
11408 fputs ("le", file);
11411 fputs ("ngt", file);
11414 fputs ("unord", file);
11417 fputs ("neq", file);
11420 fputs ("neq_oq", file);
11423 fputs ("ge", file);
11426 fputs ("nlt", file);
11429 fputs ("gt", file);
11432 fputs ("nle", file);
11435 fputs ("ord", file);
11438 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11444 switch (GET_CODE (x))
11448 fputs ("eq", file);
11452 fputs ("lt", file);
11456 fputs ("le", file);
11459 fputs ("unord", file);
11463 fputs ("neq", file);
11467 fputs ("nlt", file);
11471 fputs ("nle", file);
11474 fputs ("ord", file);
11477 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11483 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11484 if (ASSEMBLER_DIALECT == ASM_ATT)
11486 switch (GET_MODE (x))
11488 case HImode: putc ('w', file); break;
11490 case SFmode: putc ('l', file); break;
11492 case DFmode: putc ('q', file); break;
11493 default: gcc_unreachable ();
11500 if (!COMPARISON_P (x))
11502 output_operand_lossage ("operand is neither a constant nor a "
11503 "condition code, invalid operand code "
11507 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11510 if (!COMPARISON_P (x))
11512 output_operand_lossage ("operand is neither a constant nor a "
11513 "condition code, invalid operand code "
11517 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11518 if (ASSEMBLER_DIALECT == ASM_ATT)
11521 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11524 /* Like above, but reverse condition */
11526 /* Check to see if argument to %c is really a constant
11527 and not a condition code which needs to be reversed. */
11528 if (!COMPARISON_P (x))
11530 output_operand_lossage ("operand is neither a constant nor a "
11531 "condition code, invalid operand "
11535 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11538 if (!COMPARISON_P (x))
11540 output_operand_lossage ("operand is neither a constant nor a "
11541 "condition code, invalid operand "
11545 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11546 if (ASSEMBLER_DIALECT == ASM_ATT)
11549 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11553 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11557 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11561 /* It doesn't actually matter what mode we use here, as we're
11562 only going to use this for printing. */
11563 x = adjust_address_nv (x, DImode, 8);
11571 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11574 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11577 int pred_val = INTVAL (XEXP (x, 0));
11579 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11580 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11582 int taken = pred_val > REG_BR_PROB_BASE / 2;
11583 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11585 /* Emit hints only in the case default branch prediction
11586 heuristics would fail. */
11587 if (taken != cputaken)
11589 /* We use 3e (DS) prefix for taken branches and
11590 2e (CS) prefix for not taken branches. */
11592 fputs ("ds ; ", file);
11594 fputs ("cs ; ", file);
11602 switch (GET_CODE (x))
11605 fputs ("neq", file);
11608 fputs ("eq", file);
11612 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11616 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11620 fputs ("le", file);
11624 fputs ("lt", file);
11627 fputs ("unord", file);
11630 fputs ("ord", file);
11633 fputs ("ueq", file);
11636 fputs ("nlt", file);
11639 fputs ("nle", file);
11642 fputs ("ule", file);
11645 fputs ("ult", file);
11648 fputs ("une", file);
11651 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11658 fputs (" ; ", file);
11665 output_operand_lossage ("invalid operand code '%c'", code);
11670 print_reg (x, code, file);
11672 else if (MEM_P (x))
11674 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11675 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11676 && GET_MODE (x) != BLKmode)
11679 switch (GET_MODE_SIZE (GET_MODE (x)))
11681 case 1: size = "BYTE"; break;
11682 case 2: size = "WORD"; break;
11683 case 4: size = "DWORD"; break;
11684 case 8: size = "QWORD"; break;
11685 case 12: size = "XWORD"; break;
11687 if (GET_MODE (x) == XFmode)
11693 gcc_unreachable ();
11696 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11699 else if (code == 'w')
11701 else if (code == 'k')
11704 fputs (size, file);
11705 fputs (" PTR ", file);
11709 /* Avoid (%rip) for call operands. */
11710 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11711 && !CONST_INT_P (x))
11712 output_addr_const (file, x);
11713 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11714 output_operand_lossage ("invalid constraints for operand");
11716 output_address (x);
11719 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11724 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11725 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11727 if (ASSEMBLER_DIALECT == ASM_ATT)
11729 fprintf (file, "0x%08lx", (long unsigned int) l);
11732 /* These float cases don't actually occur as immediate operands. */
11733 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11737 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11738 fprintf (file, "%s", dstr);
11741 else if (GET_CODE (x) == CONST_DOUBLE
11742 && GET_MODE (x) == XFmode)
11746 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11747 fprintf (file, "%s", dstr);
11752 /* We have patterns that allow zero sets of memory, for instance.
11753 In 64-bit mode, we should probably support all 8-byte vectors,
11754 since we can in fact encode that into an immediate. */
11755 if (GET_CODE (x) == CONST_VECTOR)
11757 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11763 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11765 if (ASSEMBLER_DIALECT == ASM_ATT)
11768 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11769 || GET_CODE (x) == LABEL_REF)
11771 if (ASSEMBLER_DIALECT == ASM_ATT)
11774 fputs ("OFFSET FLAT:", file);
11777 if (CONST_INT_P (x))
11778 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11780 output_pic_addr_const (file, x, code);
11782 output_addr_const (file, x);
11786 /* Print a memory operand whose address is ADDR. */
11789 print_operand_address (FILE *file, rtx addr)
11791 struct ix86_address parts;
11792 rtx base, index, disp;
11794 int ok = ix86_decompose_address (addr, &parts);
11799 index = parts.index;
11801 scale = parts.scale;
11809 if (ASSEMBLER_DIALECT == ASM_ATT)
11811 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11814 gcc_unreachable ();
11817 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11818 if (TARGET_64BIT && !base && !index)
11822 if (GET_CODE (disp) == CONST
11823 && GET_CODE (XEXP (disp, 0)) == PLUS
11824 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11825 symbol = XEXP (XEXP (disp, 0), 0);
11827 if (GET_CODE (symbol) == LABEL_REF
11828 || (GET_CODE (symbol) == SYMBOL_REF
11829 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11832 if (!base && !index)
11834 /* Displacement only requires special attention. */
11836 if (CONST_INT_P (disp))
11838 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11839 fputs ("ds:", file);
11840 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11843 output_pic_addr_const (file, disp, 0);
11845 output_addr_const (file, disp);
11849 if (ASSEMBLER_DIALECT == ASM_ATT)
11854 output_pic_addr_const (file, disp, 0);
11855 else if (GET_CODE (disp) == LABEL_REF)
11856 output_asm_label (disp);
11858 output_addr_const (file, disp);
11863 print_reg (base, 0, file);
11867 print_reg (index, 0, file);
11869 fprintf (file, ",%d", scale);
11875 rtx offset = NULL_RTX;
11879 /* Pull out the offset of a symbol; print any symbol itself. */
11880 if (GET_CODE (disp) == CONST
11881 && GET_CODE (XEXP (disp, 0)) == PLUS
11882 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11884 offset = XEXP (XEXP (disp, 0), 1);
11885 disp = gen_rtx_CONST (VOIDmode,
11886 XEXP (XEXP (disp, 0), 0));
11890 output_pic_addr_const (file, disp, 0);
11891 else if (GET_CODE (disp) == LABEL_REF)
11892 output_asm_label (disp);
11893 else if (CONST_INT_P (disp))
11896 output_addr_const (file, disp);
11902 print_reg (base, 0, file);
11905 if (INTVAL (offset) >= 0)
11907 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11911 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11918 print_reg (index, 0, file);
11920 fprintf (file, "*%d", scale);
11928 output_addr_const_extra (FILE *file, rtx x)
11932 if (GET_CODE (x) != UNSPEC)
11935 op = XVECEXP (x, 0, 0);
11936 switch (XINT (x, 1))
11938 case UNSPEC_GOTTPOFF:
11939 output_addr_const (file, op);
11940 /* FIXME: This might be @TPOFF in Sun ld. */
11941 fputs ("@GOTTPOFF", file);
11944 output_addr_const (file, op);
11945 fputs ("@TPOFF", file);
11947 case UNSPEC_NTPOFF:
11948 output_addr_const (file, op);
11950 fputs ("@TPOFF", file);
11952 fputs ("@NTPOFF", file);
11954 case UNSPEC_DTPOFF:
11955 output_addr_const (file, op);
11956 fputs ("@DTPOFF", file);
11958 case UNSPEC_GOTNTPOFF:
11959 output_addr_const (file, op);
11961 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11962 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11964 fputs ("@GOTNTPOFF", file);
11966 case UNSPEC_INDNTPOFF:
11967 output_addr_const (file, op);
11968 fputs ("@INDNTPOFF", file);
11971 case UNSPEC_MACHOPIC_OFFSET:
11972 output_addr_const (file, op);
11974 machopic_output_function_base_name (file);
11985 /* Split one or more DImode RTL references into pairs of SImode
11986 references. The RTL can be REG, offsettable MEM, integer constant, or
11987 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11988 split and "num" is its length. lo_half and hi_half are output arrays
11989 that parallel "operands". */
11992 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11996 rtx op = operands[num];
11998 /* simplify_subreg refuse to split volatile memory addresses,
11999 but we still have to handle it. */
12002 lo_half[num] = adjust_address (op, SImode, 0);
12003 hi_half[num] = adjust_address (op, SImode, 4);
12007 lo_half[num] = simplify_gen_subreg (SImode, op,
12008 GET_MODE (op) == VOIDmode
12009 ? DImode : GET_MODE (op), 0);
12010 hi_half[num] = simplify_gen_subreg (SImode, op,
12011 GET_MODE (op) == VOIDmode
12012 ? DImode : GET_MODE (op), 4);
12016 /* Split one or more TImode RTL references into pairs of DImode
12017 references. The RTL can be REG, offsettable MEM, integer constant, or
12018 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12019 split and "num" is its length. lo_half and hi_half are output arrays
12020 that parallel "operands". */
12023 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12027 rtx op = operands[num];
12029 /* simplify_subreg refuse to split volatile memory addresses, but we
12030 still have to handle it. */
12033 lo_half[num] = adjust_address (op, DImode, 0);
12034 hi_half[num] = adjust_address (op, DImode, 8);
12038 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12039 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12044 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12045 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12046 is the expression of the binary operation. The output may either be
12047 emitted here, or returned to the caller, like all output_* functions.
12049 There is no guarantee that the operands are the same mode, as they
12050 might be within FLOAT or FLOAT_EXTEND expressions. */
12052 #ifndef SYSV386_COMPAT
12053 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12054 wants to fix the assemblers because that causes incompatibility
12055 with gcc. No-one wants to fix gcc because that causes
12056 incompatibility with assemblers... You can use the option of
12057 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12058 #define SYSV386_COMPAT 1
12062 output_387_binary_op (rtx insn, rtx *operands)
12064 static char buf[40];
12067 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12069 #ifdef ENABLE_CHECKING
12070 /* Even if we do not want to check the inputs, this documents input
12071 constraints. Which helps in understanding the following code. */
12072 if (STACK_REG_P (operands[0])
12073 && ((REG_P (operands[1])
12074 && REGNO (operands[0]) == REGNO (operands[1])
12075 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12076 || (REG_P (operands[2])
12077 && REGNO (operands[0]) == REGNO (operands[2])
12078 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12079 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12082 gcc_assert (is_sse);
12085 switch (GET_CODE (operands[3]))
12088 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12089 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12097 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12098 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12106 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12107 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12115 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12116 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12124 gcc_unreachable ();
12131 strcpy (buf, ssep);
12132 if (GET_MODE (operands[0]) == SFmode)
12133 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12135 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12139 strcpy (buf, ssep + 1);
12140 if (GET_MODE (operands[0]) == SFmode)
12141 strcat (buf, "ss\t{%2, %0|%0, %2}");
12143 strcat (buf, "sd\t{%2, %0|%0, %2}");
12149 switch (GET_CODE (operands[3]))
12153 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12155 rtx temp = operands[2];
12156 operands[2] = operands[1];
12157 operands[1] = temp;
12160 /* know operands[0] == operands[1]. */
12162 if (MEM_P (operands[2]))
12168 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12170 if (STACK_TOP_P (operands[0]))
12171 /* How is it that we are storing to a dead operand[2]?
12172 Well, presumably operands[1] is dead too. We can't
12173 store the result to st(0) as st(0) gets popped on this
12174 instruction. Instead store to operands[2] (which I
12175 think has to be st(1)). st(1) will be popped later.
12176 gcc <= 2.8.1 didn't have this check and generated
12177 assembly code that the Unixware assembler rejected. */
12178 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12180 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12184 if (STACK_TOP_P (operands[0]))
12185 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12187 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12192 if (MEM_P (operands[1]))
12198 if (MEM_P (operands[2]))
12204 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12207 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12208 derived assemblers, confusingly reverse the direction of
12209 the operation for fsub{r} and fdiv{r} when the
12210 destination register is not st(0). The Intel assembler
12211 doesn't have this brain damage. Read !SYSV386_COMPAT to
12212 figure out what the hardware really does. */
12213 if (STACK_TOP_P (operands[0]))
12214 p = "{p\t%0, %2|rp\t%2, %0}";
12216 p = "{rp\t%2, %0|p\t%0, %2}";
12218 if (STACK_TOP_P (operands[0]))
12219 /* As above for fmul/fadd, we can't store to st(0). */
12220 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12222 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12227 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12230 if (STACK_TOP_P (operands[0]))
12231 p = "{rp\t%0, %1|p\t%1, %0}";
12233 p = "{p\t%1, %0|rp\t%0, %1}";
12235 if (STACK_TOP_P (operands[0]))
12236 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12238 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12243 if (STACK_TOP_P (operands[0]))
12245 if (STACK_TOP_P (operands[1]))
12246 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12248 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12251 else if (STACK_TOP_P (operands[1]))
12254 p = "{\t%1, %0|r\t%0, %1}";
12256 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12262 p = "{r\t%2, %0|\t%0, %2}";
12264 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12270 gcc_unreachable ();
12277 /* Return needed mode for entity in optimize_mode_switching pass. */
12280 ix86_mode_needed (int entity, rtx insn)
12282 enum attr_i387_cw mode;
12284 /* The mode UNINITIALIZED is used to store control word after a
12285 function call or ASM pattern. The mode ANY specify that function
12286 has no requirements on the control word and make no changes in the
12287 bits we are interested in. */
12290 || (NONJUMP_INSN_P (insn)
12291 && (asm_noperands (PATTERN (insn)) >= 0
12292 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12293 return I387_CW_UNINITIALIZED;
12295 if (recog_memoized (insn) < 0)
12296 return I387_CW_ANY;
12298 mode = get_attr_i387_cw (insn);
12303 if (mode == I387_CW_TRUNC)
12308 if (mode == I387_CW_FLOOR)
12313 if (mode == I387_CW_CEIL)
12318 if (mode == I387_CW_MASK_PM)
12323 gcc_unreachable ();
12326 return I387_CW_ANY;
12329 /* Output code to initialize control word copies used by trunc?f?i and
12330 rounding patterns. CURRENT_MODE is set to current control word,
12331 while NEW_MODE is set to new control word. */
12334 emit_i387_cw_initialization (int mode)
12336 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12339 enum ix86_stack_slot slot;
12341 rtx reg = gen_reg_rtx (HImode);
12343 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12344 emit_move_insn (reg, copy_rtx (stored_mode));
12346 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12347 || optimize_function_for_size_p (cfun))
12351 case I387_CW_TRUNC:
12352 /* round toward zero (truncate) */
12353 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12354 slot = SLOT_CW_TRUNC;
12357 case I387_CW_FLOOR:
12358 /* round down toward -oo */
12359 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12360 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12361 slot = SLOT_CW_FLOOR;
12365 /* round up toward +oo */
12366 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12367 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12368 slot = SLOT_CW_CEIL;
12371 case I387_CW_MASK_PM:
12372 /* mask precision exception for nearbyint() */
12373 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12374 slot = SLOT_CW_MASK_PM;
12378 gcc_unreachable ();
12385 case I387_CW_TRUNC:
12386 /* round toward zero (truncate) */
12387 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12388 slot = SLOT_CW_TRUNC;
12391 case I387_CW_FLOOR:
12392 /* round down toward -oo */
12393 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12394 slot = SLOT_CW_FLOOR;
12398 /* round up toward +oo */
12399 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12400 slot = SLOT_CW_CEIL;
12403 case I387_CW_MASK_PM:
12404 /* mask precision exception for nearbyint() */
12405 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12406 slot = SLOT_CW_MASK_PM;
12410 gcc_unreachable ();
12414 gcc_assert (slot < MAX_386_STACK_LOCALS);
12416 new_mode = assign_386_stack_local (HImode, slot);
12417 emit_move_insn (new_mode, reg);
12420 /* Output code for INSN to convert a float to a signed int. OPERANDS
12421 are the insn operands. The output may be [HSD]Imode and the input
12422 operand may be [SDX]Fmode. */
12425 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12427 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12428 int dimode_p = GET_MODE (operands[0]) == DImode;
12429 int round_mode = get_attr_i387_cw (insn);
12431 /* Jump through a hoop or two for DImode, since the hardware has no
12432 non-popping instruction. We used to do this a different way, but
12433 that was somewhat fragile and broke with post-reload splitters. */
12434 if ((dimode_p || fisttp) && !stack_top_dies)
12435 output_asm_insn ("fld\t%y1", operands);
12437 gcc_assert (STACK_TOP_P (operands[1]));
12438 gcc_assert (MEM_P (operands[0]));
12439 gcc_assert (GET_MODE (operands[1]) != TFmode);
12442 output_asm_insn ("fisttp%Z0\t%0", operands);
12445 if (round_mode != I387_CW_ANY)
12446 output_asm_insn ("fldcw\t%3", operands);
12447 if (stack_top_dies || dimode_p)
12448 output_asm_insn ("fistp%Z0\t%0", operands);
12450 output_asm_insn ("fist%Z0\t%0", operands);
12451 if (round_mode != I387_CW_ANY)
12452 output_asm_insn ("fldcw\t%2", operands);
12458 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12459 have the values zero or one, indicates the ffreep insn's operand
12460 from the OPERANDS array. */
12462 static const char *
12463 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12465 if (TARGET_USE_FFREEP)
12466 #if HAVE_AS_IX86_FFREEP
12467 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12470 static char retval[] = ".word\t0xc_df";
12471 int regno = REGNO (operands[opno]);
12473 gcc_assert (FP_REGNO_P (regno));
12475 retval[9] = '0' + (regno - FIRST_STACK_REG);
12480 return opno ? "fstp\t%y1" : "fstp\t%y0";
12484 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12485 should be used. UNORDERED_P is true when fucom should be used. */
12488 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12490 int stack_top_dies;
12491 rtx cmp_op0, cmp_op1;
12492 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12496 cmp_op0 = operands[0];
12497 cmp_op1 = operands[1];
12501 cmp_op0 = operands[1];
12502 cmp_op1 = operands[2];
12507 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12508 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12509 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12510 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12512 if (GET_MODE (operands[0]) == SFmode)
12514 return &ucomiss[TARGET_AVX ? 0 : 1];
12516 return &comiss[TARGET_AVX ? 0 : 1];
12519 return &ucomisd[TARGET_AVX ? 0 : 1];
12521 return &comisd[TARGET_AVX ? 0 : 1];
12524 gcc_assert (STACK_TOP_P (cmp_op0));
12526 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12528 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12530 if (stack_top_dies)
12532 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12533 return output_387_ffreep (operands, 1);
12536 return "ftst\n\tfnstsw\t%0";
12539 if (STACK_REG_P (cmp_op1)
12541 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12542 && REGNO (cmp_op1) != FIRST_STACK_REG)
12544 /* If both the top of the 387 stack dies, and the other operand
12545 is also a stack register that dies, then this must be a
12546 `fcompp' float compare */
12550 /* There is no double popping fcomi variant. Fortunately,
12551 eflags is immune from the fstp's cc clobbering. */
12553 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12555 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12556 return output_387_ffreep (operands, 0);
12561 return "fucompp\n\tfnstsw\t%0";
12563 return "fcompp\n\tfnstsw\t%0";
12568 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12570 static const char * const alt[16] =
12572 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12573 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12574 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12575 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12577 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12578 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12582 "fcomi\t{%y1, %0|%0, %y1}",
12583 "fcomip\t{%y1, %0|%0, %y1}",
12584 "fucomi\t{%y1, %0|%0, %y1}",
12585 "fucomip\t{%y1, %0|%0, %y1}",
12596 mask = eflags_p << 3;
12597 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12598 mask |= unordered_p << 1;
12599 mask |= stack_top_dies;
12601 gcc_assert (mask < 16);
12610 ix86_output_addr_vec_elt (FILE *file, int value)
12612 const char *directive = ASM_LONG;
12616 directive = ASM_QUAD;
12618 gcc_assert (!TARGET_64BIT);
12621 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12625 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12627 const char *directive = ASM_LONG;
12630 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12631 directive = ASM_QUAD;
12633 gcc_assert (!TARGET_64BIT);
12635 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12636 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12637 fprintf (file, "%s%s%d-%s%d\n",
12638 directive, LPREFIX, value, LPREFIX, rel);
12639 else if (HAVE_AS_GOTOFF_IN_DATA)
12640 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12642 else if (TARGET_MACHO)
12644 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12645 machopic_output_function_base_name (file);
12646 fprintf(file, "\n");
12650 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12651 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12654 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12658 ix86_expand_clear (rtx dest)
12662 /* We play register width games, which are only valid after reload. */
12663 gcc_assert (reload_completed);
12665 /* Avoid HImode and its attendant prefix byte. */
12666 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12667 dest = gen_rtx_REG (SImode, REGNO (dest));
12668 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12670 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12671 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12673 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12674 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12680 /* X is an unchanging MEM. If it is a constant pool reference, return
12681 the constant pool rtx, else NULL. */
12684 maybe_get_pool_constant (rtx x)
12686 x = ix86_delegitimize_address (XEXP (x, 0));
12688 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12689 return get_pool_constant (x);
12695 ix86_expand_move (enum machine_mode mode, rtx operands[])
12698 enum tls_model model;
12703 if (GET_CODE (op1) == SYMBOL_REF)
12705 model = SYMBOL_REF_TLS_MODEL (op1);
12708 op1 = legitimize_tls_address (op1, model, true);
12709 op1 = force_operand (op1, op0);
12713 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12714 && SYMBOL_REF_DLLIMPORT_P (op1))
12715 op1 = legitimize_dllimport_symbol (op1, false);
12717 else if (GET_CODE (op1) == CONST
12718 && GET_CODE (XEXP (op1, 0)) == PLUS
12719 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12721 rtx addend = XEXP (XEXP (op1, 0), 1);
12722 rtx symbol = XEXP (XEXP (op1, 0), 0);
12725 model = SYMBOL_REF_TLS_MODEL (symbol);
12727 tmp = legitimize_tls_address (symbol, model, true);
12728 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12729 && SYMBOL_REF_DLLIMPORT_P (symbol))
12730 tmp = legitimize_dllimport_symbol (symbol, true);
12734 tmp = force_operand (tmp, NULL);
12735 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12736 op0, 1, OPTAB_DIRECT);
12742 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12744 if (TARGET_MACHO && !TARGET_64BIT)
12749 rtx temp = ((reload_in_progress
12750 || ((op0 && REG_P (op0))
12752 ? op0 : gen_reg_rtx (Pmode));
12753 op1 = machopic_indirect_data_reference (op1, temp);
12754 op1 = machopic_legitimize_pic_address (op1, mode,
12755 temp == op1 ? 0 : temp);
12757 else if (MACHOPIC_INDIRECT)
12758 op1 = machopic_indirect_data_reference (op1, 0);
12766 op1 = force_reg (Pmode, op1);
12767 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12769 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12770 op1 = legitimize_pic_address (op1, reg);
12779 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12780 || !push_operand (op0, mode))
12782 op1 = force_reg (mode, op1);
12784 if (push_operand (op0, mode)
12785 && ! general_no_elim_operand (op1, mode))
12786 op1 = copy_to_mode_reg (mode, op1);
12788 /* Force large constants in 64bit compilation into register
12789 to get them CSEed. */
12790 if (can_create_pseudo_p ()
12791 && (mode == DImode) && TARGET_64BIT
12792 && immediate_operand (op1, mode)
12793 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12794 && !register_operand (op0, mode)
12796 op1 = copy_to_mode_reg (mode, op1);
12798 if (can_create_pseudo_p ()
12799 && FLOAT_MODE_P (mode)
12800 && GET_CODE (op1) == CONST_DOUBLE)
12802 /* If we are loading a floating point constant to a register,
12803 force the value to memory now, since we'll get better code
12804 out the back end. */
12806 op1 = validize_mem (force_const_mem (mode, op1));
12807 if (!register_operand (op0, mode))
12809 rtx temp = gen_reg_rtx (mode);
12810 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12811 emit_move_insn (op0, temp);
12817 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12821 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12823 rtx op0 = operands[0], op1 = operands[1];
12824 unsigned int align = GET_MODE_ALIGNMENT (mode);
12826 /* Force constants other than zero into memory. We do not know how
12827 the instructions used to build constants modify the upper 64 bits
12828 of the register, once we have that information we may be able
12829 to handle some of them more efficiently. */
12830 if (can_create_pseudo_p ()
12831 && register_operand (op0, mode)
12832 && (CONSTANT_P (op1)
12833 || (GET_CODE (op1) == SUBREG
12834 && CONSTANT_P (SUBREG_REG (op1))))
12835 && standard_sse_constant_p (op1) <= 0)
12836 op1 = validize_mem (force_const_mem (mode, op1));
12838 /* We need to check memory alignment for SSE mode since attribute
12839 can make operands unaligned. */
12840 if (can_create_pseudo_p ()
12841 && SSE_REG_MODE_P (mode)
12842 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12843 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12847 /* ix86_expand_vector_move_misalign() does not like constants ... */
12848 if (CONSTANT_P (op1)
12849 || (GET_CODE (op1) == SUBREG
12850 && CONSTANT_P (SUBREG_REG (op1))))
12851 op1 = validize_mem (force_const_mem (mode, op1));
12853 /* ... nor both arguments in memory. */
12854 if (!register_operand (op0, mode)
12855 && !register_operand (op1, mode))
12856 op1 = force_reg (mode, op1);
12858 tmp[0] = op0; tmp[1] = op1;
12859 ix86_expand_vector_move_misalign (mode, tmp);
12863 /* Make operand1 a register if it isn't already. */
12864 if (can_create_pseudo_p ()
12865 && !register_operand (op0, mode)
12866 && !register_operand (op1, mode))
12868 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12872 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12875 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12876 straight to ix86_expand_vector_move. */
12877 /* Code generation for scalar reg-reg moves of single and double precision data:
12878 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12882 if (x86_sse_partial_reg_dependency == true)
12887 Code generation for scalar loads of double precision data:
12888 if (x86_sse_split_regs == true)
12889 movlpd mem, reg (gas syntax)
12893 Code generation for unaligned packed loads of single precision data
12894 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12895 if (x86_sse_unaligned_move_optimal)
12898 if (x86_sse_partial_reg_dependency == true)
12910 Code generation for unaligned packed loads of double precision data
12911 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12912 if (x86_sse_unaligned_move_optimal)
12915 if (x86_sse_split_regs == true)
12928 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12937 switch (GET_MODE_CLASS (mode))
12939 case MODE_VECTOR_INT:
12941 switch (GET_MODE_SIZE (mode))
12944 op0 = gen_lowpart (V16QImode, op0);
12945 op1 = gen_lowpart (V16QImode, op1);
12946 emit_insn (gen_avx_movdqu (op0, op1));
12949 op0 = gen_lowpart (V32QImode, op0);
12950 op1 = gen_lowpart (V32QImode, op1);
12951 emit_insn (gen_avx_movdqu256 (op0, op1));
12954 gcc_unreachable ();
12957 case MODE_VECTOR_FLOAT:
12958 op0 = gen_lowpart (mode, op0);
12959 op1 = gen_lowpart (mode, op1);
12964 emit_insn (gen_avx_movups (op0, op1));
12967 emit_insn (gen_avx_movups256 (op0, op1));
12970 emit_insn (gen_avx_movupd (op0, op1));
12973 emit_insn (gen_avx_movupd256 (op0, op1));
12976 gcc_unreachable ();
12981 gcc_unreachable ();
12989 /* If we're optimizing for size, movups is the smallest. */
12990 if (optimize_insn_for_size_p ())
12992 op0 = gen_lowpart (V4SFmode, op0);
12993 op1 = gen_lowpart (V4SFmode, op1);
12994 emit_insn (gen_sse_movups (op0, op1));
12998 /* ??? If we have typed data, then it would appear that using
12999 movdqu is the only way to get unaligned data loaded with
13001 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13003 op0 = gen_lowpart (V16QImode, op0);
13004 op1 = gen_lowpart (V16QImode, op1);
13005 emit_insn (gen_sse2_movdqu (op0, op1));
13009 if (TARGET_SSE2 && mode == V2DFmode)
13013 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13015 op0 = gen_lowpart (V2DFmode, op0);
13016 op1 = gen_lowpart (V2DFmode, op1);
13017 emit_insn (gen_sse2_movupd (op0, op1));
13021 /* When SSE registers are split into halves, we can avoid
13022 writing to the top half twice. */
13023 if (TARGET_SSE_SPLIT_REGS)
13025 emit_clobber (op0);
13030 /* ??? Not sure about the best option for the Intel chips.
13031 The following would seem to satisfy; the register is
13032 entirely cleared, breaking the dependency chain. We
13033 then store to the upper half, with a dependency depth
13034 of one. A rumor has it that Intel recommends two movsd
13035 followed by an unpacklpd, but this is unconfirmed. And
13036 given that the dependency depth of the unpacklpd would
13037 still be one, I'm not sure why this would be better. */
13038 zero = CONST0_RTX (V2DFmode);
13041 m = adjust_address (op1, DFmode, 0);
13042 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13043 m = adjust_address (op1, DFmode, 8);
13044 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13048 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13050 op0 = gen_lowpart (V4SFmode, op0);
13051 op1 = gen_lowpart (V4SFmode, op1);
13052 emit_insn (gen_sse_movups (op0, op1));
13056 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13057 emit_move_insn (op0, CONST0_RTX (mode));
13059 emit_clobber (op0);
13061 if (mode != V4SFmode)
13062 op0 = gen_lowpart (V4SFmode, op0);
13063 m = adjust_address (op1, V2SFmode, 0);
13064 emit_insn (gen_sse_loadlps (op0, op0, m));
13065 m = adjust_address (op1, V2SFmode, 8);
13066 emit_insn (gen_sse_loadhps (op0, op0, m));
13069 else if (MEM_P (op0))
13071 /* If we're optimizing for size, movups is the smallest. */
13072 if (optimize_insn_for_size_p ())
13074 op0 = gen_lowpart (V4SFmode, op0);
13075 op1 = gen_lowpart (V4SFmode, op1);
13076 emit_insn (gen_sse_movups (op0, op1));
13080 /* ??? Similar to above, only less clear because of quote
13081 typeless stores unquote. */
13082 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13083 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13085 op0 = gen_lowpart (V16QImode, op0);
13086 op1 = gen_lowpart (V16QImode, op1);
13087 emit_insn (gen_sse2_movdqu (op0, op1));
13091 if (TARGET_SSE2 && mode == V2DFmode)
13093 m = adjust_address (op0, DFmode, 0);
13094 emit_insn (gen_sse2_storelpd (m, op1));
13095 m = adjust_address (op0, DFmode, 8);
13096 emit_insn (gen_sse2_storehpd (m, op1));
13100 if (mode != V4SFmode)
13101 op1 = gen_lowpart (V4SFmode, op1);
13102 m = adjust_address (op0, V2SFmode, 0);
13103 emit_insn (gen_sse_storelps (m, op1));
13104 m = adjust_address (op0, V2SFmode, 8);
13105 emit_insn (gen_sse_storehps (m, op1));
13109 gcc_unreachable ();
13112 /* Expand a push in MODE. This is some mode for which we do not support
13113 proper push instructions, at least from the registers that we expect
13114 the value to live in. */
13117 ix86_expand_push (enum machine_mode mode, rtx x)
13121 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13122 GEN_INT (-GET_MODE_SIZE (mode)),
13123 stack_pointer_rtx, 1, OPTAB_DIRECT);
13124 if (tmp != stack_pointer_rtx)
13125 emit_move_insn (stack_pointer_rtx, tmp);
13127 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13129 /* When we push an operand onto stack, it has to be aligned at least
13130 at the function argument boundary. However since we don't have
13131 the argument type, we can't determine the actual argument
13133 emit_move_insn (tmp, x);
13136 /* Helper function of ix86_fixup_binary_operands to canonicalize
13137 operand order. Returns true if the operands should be swapped. */
13140 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13143 rtx dst = operands[0];
13144 rtx src1 = operands[1];
13145 rtx src2 = operands[2];
13147 /* If the operation is not commutative, we can't do anything. */
13148 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13151 /* Highest priority is that src1 should match dst. */
13152 if (rtx_equal_p (dst, src1))
13154 if (rtx_equal_p (dst, src2))
13157 /* Next highest priority is that immediate constants come second. */
13158 if (immediate_operand (src2, mode))
13160 if (immediate_operand (src1, mode))
13163 /* Lowest priority is that memory references should come second. */
13173 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13174 destination to use for the operation. If different from the true
13175 destination in operands[0], a copy operation will be required. */
13178 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13181 rtx dst = operands[0];
13182 rtx src1 = operands[1];
13183 rtx src2 = operands[2];
13185 /* Canonicalize operand order. */
13186 if (ix86_swap_binary_operands_p (code, mode, operands))
13190 /* It is invalid to swap operands of different modes. */
13191 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13198 /* Both source operands cannot be in memory. */
13199 if (MEM_P (src1) && MEM_P (src2))
13201 /* Optimization: Only read from memory once. */
13202 if (rtx_equal_p (src1, src2))
13204 src2 = force_reg (mode, src2);
13208 src2 = force_reg (mode, src2);
13211 /* If the destination is memory, and we do not have matching source
13212 operands, do things in registers. */
13213 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13214 dst = gen_reg_rtx (mode);
13216 /* Source 1 cannot be a constant. */
13217 if (CONSTANT_P (src1))
13218 src1 = force_reg (mode, src1);
13220 /* Source 1 cannot be a non-matching memory. */
13221 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13222 src1 = force_reg (mode, src1);
13224 operands[1] = src1;
13225 operands[2] = src2;
13229 /* Similarly, but assume that the destination has already been
13230 set up properly. */
13233 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13234 enum machine_mode mode, rtx operands[])
13236 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13237 gcc_assert (dst == operands[0]);
13240 /* Attempt to expand a binary operator. Make the expansion closer to the
13241 actual machine, then just general_operand, which will allow 3 separate
13242 memory references (one output, two input) in a single insn. */
13245 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13248 rtx src1, src2, dst, op, clob;
13250 dst = ix86_fixup_binary_operands (code, mode, operands);
13251 src1 = operands[1];
13252 src2 = operands[2];
13254 /* Emit the instruction. */
13256 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13257 if (reload_in_progress)
13259 /* Reload doesn't know about the flags register, and doesn't know that
13260 it doesn't want to clobber it. We can only do this with PLUS. */
13261 gcc_assert (code == PLUS);
13266 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13267 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13270 /* Fix up the destination if needed. */
13271 if (dst != operands[0])
13272 emit_move_insn (operands[0], dst);
13275 /* Return TRUE or FALSE depending on whether the binary operator meets the
13276 appropriate constraints. */
13279 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13282 rtx dst = operands[0];
13283 rtx src1 = operands[1];
13284 rtx src2 = operands[2];
13286 /* Both source operands cannot be in memory. */
13287 if (MEM_P (src1) && MEM_P (src2))
13290 /* Canonicalize operand order for commutative operators. */
13291 if (ix86_swap_binary_operands_p (code, mode, operands))
13298 /* If the destination is memory, we must have a matching source operand. */
13299 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13302 /* Source 1 cannot be a constant. */
13303 if (CONSTANT_P (src1))
13306 /* Source 1 cannot be a non-matching memory. */
13307 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13313 /* Attempt to expand a unary operator. Make the expansion closer to the
13314 actual machine, then just general_operand, which will allow 2 separate
13315 memory references (one output, one input) in a single insn. */
13318 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13321 int matching_memory;
13322 rtx src, dst, op, clob;
13327 /* If the destination is memory, and we do not have matching source
13328 operands, do things in registers. */
13329 matching_memory = 0;
13332 if (rtx_equal_p (dst, src))
13333 matching_memory = 1;
13335 dst = gen_reg_rtx (mode);
13338 /* When source operand is memory, destination must match. */
13339 if (MEM_P (src) && !matching_memory)
13340 src = force_reg (mode, src);
13342 /* Emit the instruction. */
13344 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13345 if (reload_in_progress || code == NOT)
13347 /* Reload doesn't know about the flags register, and doesn't know that
13348 it doesn't want to clobber it. */
13349 gcc_assert (code == NOT);
13354 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13355 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13358 /* Fix up the destination if needed. */
13359 if (dst != operands[0])
13360 emit_move_insn (operands[0], dst);
13363 #define LEA_SEARCH_THRESHOLD 12
13365 /* Search backward for non-agu definition of register number REGNO1
13366 or register number REGNO2 in INSN's basic block until
13367 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13368 2. Reach BB boundary, or
13369 3. Reach agu definition.
13370 Returns the distance between the non-agu definition point and INSN.
13371 If no definition point, returns -1. */
13374 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13377 basic_block bb = BLOCK_FOR_INSN (insn);
13380 enum attr_type insn_type;
13382 if (insn != BB_HEAD (bb))
13384 rtx prev = PREV_INSN (insn);
13385 while (prev && distance < LEA_SEARCH_THRESHOLD)
13390 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13391 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13392 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13393 && (regno1 == DF_REF_REGNO (*def_rec)
13394 || regno2 == DF_REF_REGNO (*def_rec)))
13396 insn_type = get_attr_type (prev);
13397 if (insn_type != TYPE_LEA)
13401 if (prev == BB_HEAD (bb))
13403 prev = PREV_INSN (prev);
13407 if (distance < LEA_SEARCH_THRESHOLD)
13411 bool simple_loop = false;
13413 FOR_EACH_EDGE (e, ei, bb->preds)
13416 simple_loop = true;
13422 rtx prev = BB_END (bb);
13425 && distance < LEA_SEARCH_THRESHOLD)
13430 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13431 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13432 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13433 && (regno1 == DF_REF_REGNO (*def_rec)
13434 || regno2 == DF_REF_REGNO (*def_rec)))
13436 insn_type = get_attr_type (prev);
13437 if (insn_type != TYPE_LEA)
13441 prev = PREV_INSN (prev);
13449 /* get_attr_type may modify recog data. We want to make sure
13450 that recog data is valid for instruction INSN, on which
13451 distance_non_agu_define is called. INSN is unchanged here. */
13452 extract_insn_cached (insn);
13456 /* Return the distance between INSN and the next insn that uses
13457 register number REGNO0 in memory address. Return -1 if no such
13458 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13461 distance_agu_use (unsigned int regno0, rtx insn)
13463 basic_block bb = BLOCK_FOR_INSN (insn);
13468 if (insn != BB_END (bb))
13470 rtx next = NEXT_INSN (insn);
13471 while (next && distance < LEA_SEARCH_THRESHOLD)
13477 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13478 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13479 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13480 && regno0 == DF_REF_REGNO (*use_rec))
13482 /* Return DISTANCE if OP0 is used in memory
13483 address in NEXT. */
13487 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13488 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13489 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13490 && regno0 == DF_REF_REGNO (*def_rec))
13492 /* Return -1 if OP0 is set in NEXT. */
13496 if (next == BB_END (bb))
13498 next = NEXT_INSN (next);
13502 if (distance < LEA_SEARCH_THRESHOLD)
13506 bool simple_loop = false;
13508 FOR_EACH_EDGE (e, ei, bb->succs)
13511 simple_loop = true;
13517 rtx next = BB_HEAD (bb);
13520 && distance < LEA_SEARCH_THRESHOLD)
13526 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13527 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13528 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13529 && regno0 == DF_REF_REGNO (*use_rec))
13531 /* Return DISTANCE if OP0 is used in memory
13532 address in NEXT. */
13536 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13537 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13538 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13539 && regno0 == DF_REF_REGNO (*def_rec))
13541 /* Return -1 if OP0 is set in NEXT. */
13546 next = NEXT_INSN (next);
13554 /* Define this macro to tune LEA priority vs ADD, it take effect when
13555 there is a dilemma of choicing LEA or ADD
13556 Negative value: ADD is more preferred than LEA
13558 Positive value: LEA is more preferred than ADD*/
13559 #define IX86_LEA_PRIORITY 2
13561 /* Return true if it is ok to optimize an ADD operation to LEA
13562 operation to avoid flag register consumation. For the processors
13563 like ATOM, if the destination register of LEA holds an actual
13564 address which will be used soon, LEA is better and otherwise ADD
13568 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13569 rtx insn, rtx operands[])
13571 unsigned int regno0 = true_regnum (operands[0]);
13572 unsigned int regno1 = true_regnum (operands[1]);
13573 unsigned int regno2;
13575 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13576 return regno0 != regno1;
13578 regno2 = true_regnum (operands[2]);
13580 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13581 if (regno0 != regno1 && regno0 != regno2)
13585 int dist_define, dist_use;
13586 dist_define = distance_non_agu_define (regno1, regno2, insn);
13587 if (dist_define <= 0)
13590 /* If this insn has both backward non-agu dependence and forward
13591 agu dependence, the one with short distance take effect. */
13592 dist_use = distance_agu_use (regno0, insn);
13594 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13601 /* Return true if destination reg of SET_BODY is shift count of
13605 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13611 /* Retrieve destination of SET_BODY. */
13612 switch (GET_CODE (set_body))
13615 set_dest = SET_DEST (set_body);
13616 if (!set_dest || !REG_P (set_dest))
13620 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13621 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13629 /* Retrieve shift count of USE_BODY. */
13630 switch (GET_CODE (use_body))
13633 shift_rtx = XEXP (use_body, 1);
13636 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13637 if (ix86_dep_by_shift_count_body (set_body,
13638 XVECEXP (use_body, 0, i)))
13646 && (GET_CODE (shift_rtx) == ASHIFT
13647 || GET_CODE (shift_rtx) == LSHIFTRT
13648 || GET_CODE (shift_rtx) == ASHIFTRT
13649 || GET_CODE (shift_rtx) == ROTATE
13650 || GET_CODE (shift_rtx) == ROTATERT))
13652 rtx shift_count = XEXP (shift_rtx, 1);
13654 /* Return true if shift count is dest of SET_BODY. */
13655 if (REG_P (shift_count)
13656 && true_regnum (set_dest) == true_regnum (shift_count))
13663 /* Return true if destination reg of SET_INSN is shift count of
13667 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13669 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13670 PATTERN (use_insn));
13673 /* Return TRUE or FALSE depending on whether the unary operator meets the
13674 appropriate constraints. */
13677 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13678 enum machine_mode mode ATTRIBUTE_UNUSED,
13679 rtx operands[2] ATTRIBUTE_UNUSED)
13681 /* If one of operands is memory, source and destination must match. */
13682 if ((MEM_P (operands[0])
13683 || MEM_P (operands[1]))
13684 && ! rtx_equal_p (operands[0], operands[1]))
13689 /* Post-reload splitter for converting an SF or DFmode value in an
13690 SSE register into an unsigned SImode. */
13693 ix86_split_convert_uns_si_sse (rtx operands[])
13695 enum machine_mode vecmode;
13696 rtx value, large, zero_or_two31, input, two31, x;
13698 large = operands[1];
13699 zero_or_two31 = operands[2];
13700 input = operands[3];
13701 two31 = operands[4];
13702 vecmode = GET_MODE (large);
13703 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13705 /* Load up the value into the low element. We must ensure that the other
13706 elements are valid floats -- zero is the easiest such value. */
13709 if (vecmode == V4SFmode)
13710 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13712 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13716 input = gen_rtx_REG (vecmode, REGNO (input));
13717 emit_move_insn (value, CONST0_RTX (vecmode));
13718 if (vecmode == V4SFmode)
13719 emit_insn (gen_sse_movss (value, value, input));
13721 emit_insn (gen_sse2_movsd (value, value, input));
13724 emit_move_insn (large, two31);
13725 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13727 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13728 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13730 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13731 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13733 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13734 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13736 large = gen_rtx_REG (V4SImode, REGNO (large));
13737 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13739 x = gen_rtx_REG (V4SImode, REGNO (value));
13740 if (vecmode == V4SFmode)
13741 emit_insn (gen_sse2_cvttps2dq (x, value));
13743 emit_insn (gen_sse2_cvttpd2dq (x, value));
13746 emit_insn (gen_xorv4si3 (value, value, large));
13749 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13750 Expects the 64-bit DImode to be supplied in a pair of integral
13751 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13752 -mfpmath=sse, !optimize_size only. */
13755 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13757 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13758 rtx int_xmm, fp_xmm;
13759 rtx biases, exponents;
13762 int_xmm = gen_reg_rtx (V4SImode);
13763 if (TARGET_INTER_UNIT_MOVES)
13764 emit_insn (gen_movdi_to_sse (int_xmm, input));
13765 else if (TARGET_SSE_SPLIT_REGS)
13767 emit_clobber (int_xmm);
13768 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13772 x = gen_reg_rtx (V2DImode);
13773 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13774 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13777 x = gen_rtx_CONST_VECTOR (V4SImode,
13778 gen_rtvec (4, GEN_INT (0x43300000UL),
13779 GEN_INT (0x45300000UL),
13780 const0_rtx, const0_rtx));
13781 exponents = validize_mem (force_const_mem (V4SImode, x));
13783 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13784 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13786 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13787 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13788 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13789 (0x1.0p84 + double(fp_value_hi_xmm)).
13790 Note these exponents differ by 32. */
13792 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13794 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13795 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13796 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13797 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13798 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13799 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13800 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13801 biases = validize_mem (force_const_mem (V2DFmode, biases));
13802 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13804 /* Add the upper and lower DFmode values together. */
13806 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13809 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13810 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13811 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13814 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13817 /* Not used, but eases macroization of patterns. */
13819 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13820 rtx input ATTRIBUTE_UNUSED)
13822 gcc_unreachable ();
13825 /* Convert an unsigned SImode value into a DFmode. Only currently used
13826 for SSE, but applicable anywhere. */
13829 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13831 REAL_VALUE_TYPE TWO31r;
13834 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13835 NULL, 1, OPTAB_DIRECT);
13837 fp = gen_reg_rtx (DFmode);
13838 emit_insn (gen_floatsidf2 (fp, x));
13840 real_ldexp (&TWO31r, &dconst1, 31);
13841 x = const_double_from_real_value (TWO31r, DFmode);
13843 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13845 emit_move_insn (target, x);
13848 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13849 32-bit mode; otherwise we have a direct convert instruction. */
13852 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13854 REAL_VALUE_TYPE TWO32r;
13855 rtx fp_lo, fp_hi, x;
13857 fp_lo = gen_reg_rtx (DFmode);
13858 fp_hi = gen_reg_rtx (DFmode);
13860 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13862 real_ldexp (&TWO32r, &dconst1, 32);
13863 x = const_double_from_real_value (TWO32r, DFmode);
13864 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13866 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13868 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13871 emit_move_insn (target, x);
13874 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13875 For x86_32, -mfpmath=sse, !optimize_size only. */
13877 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13879 REAL_VALUE_TYPE ONE16r;
13880 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13882 real_ldexp (&ONE16r, &dconst1, 16);
13883 x = const_double_from_real_value (ONE16r, SFmode);
13884 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13885 NULL, 0, OPTAB_DIRECT);
13886 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13887 NULL, 0, OPTAB_DIRECT);
13888 fp_hi = gen_reg_rtx (SFmode);
13889 fp_lo = gen_reg_rtx (SFmode);
13890 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13891 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13892 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13894 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13896 if (!rtx_equal_p (target, fp_hi))
13897 emit_move_insn (target, fp_hi);
13900 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
13901 then replicate the value for all elements of the vector
13905 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13912 v = gen_rtvec (4, value, value, value, value);
13913 return gen_rtx_CONST_VECTOR (V4SImode, v);
13917 v = gen_rtvec (2, value, value);
13918 return gen_rtx_CONST_VECTOR (V2DImode, v);
13922 v = gen_rtvec (4, value, value, value, value);
13924 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13925 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13926 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13930 v = gen_rtvec (2, value, value);
13932 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13933 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13936 gcc_unreachable ();
13940 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13941 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13942 for an SSE register. If VECT is true, then replicate the mask for
13943 all elements of the vector register. If INVERT is true, then create
13944 a mask excluding the sign bit. */
13947 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13949 enum machine_mode vec_mode, imode;
13950 HOST_WIDE_INT hi, lo;
13955 /* Find the sign bit, sign extended to 2*HWI. */
13961 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13962 lo = 0x80000000, hi = lo < 0;
13968 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13969 if (HOST_BITS_PER_WIDE_INT >= 64)
13970 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13972 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13977 vec_mode = VOIDmode;
13978 if (HOST_BITS_PER_WIDE_INT >= 64)
13981 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13988 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13992 lo = ~lo, hi = ~hi;
13998 mask = immed_double_const (lo, hi, imode);
14000 vec = gen_rtvec (2, v, mask);
14001 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
14002 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
14009 gcc_unreachable ();
14013 lo = ~lo, hi = ~hi;
14015 /* Force this value into the low part of a fp vector constant. */
14016 mask = immed_double_const (lo, hi, imode);
14017 mask = gen_lowpart (mode, mask);
14019 if (vec_mode == VOIDmode)
14020 return force_reg (mode, mask);
14022 v = ix86_build_const_vector (mode, vect, mask);
14023 return force_reg (vec_mode, v);
14026 /* Generate code for floating point ABS or NEG. */
14029 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14032 rtx mask, set, use, clob, dst, src;
14033 bool use_sse = false;
14034 bool vector_mode = VECTOR_MODE_P (mode);
14035 enum machine_mode elt_mode = mode;
14039 elt_mode = GET_MODE_INNER (mode);
14042 else if (mode == TFmode)
14044 else if (TARGET_SSE_MATH)
14045 use_sse = SSE_FLOAT_MODE_P (mode);
14047 /* NEG and ABS performed with SSE use bitwise mask operations.
14048 Create the appropriate mask now. */
14050 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14059 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14060 set = gen_rtx_SET (VOIDmode, dst, set);
14065 set = gen_rtx_fmt_e (code, mode, src);
14066 set = gen_rtx_SET (VOIDmode, dst, set);
14069 use = gen_rtx_USE (VOIDmode, mask);
14070 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14071 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14072 gen_rtvec (3, set, use, clob)));
14079 /* Expand a copysign operation. Special case operand 0 being a constant. */
14082 ix86_expand_copysign (rtx operands[])
14084 enum machine_mode mode;
14085 rtx dest, op0, op1, mask, nmask;
14087 dest = operands[0];
14091 mode = GET_MODE (dest);
14093 if (GET_CODE (op0) == CONST_DOUBLE)
14095 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14097 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14098 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14100 if (mode == SFmode || mode == DFmode)
14102 enum machine_mode vmode;
14104 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14106 if (op0 == CONST0_RTX (mode))
14107 op0 = CONST0_RTX (vmode);
14112 if (mode == SFmode)
14113 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
14114 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
14116 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
14118 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
14121 else if (op0 != CONST0_RTX (mode))
14122 op0 = force_reg (mode, op0);
14124 mask = ix86_build_signbit_mask (mode, 0, 0);
14126 if (mode == SFmode)
14127 copysign_insn = gen_copysignsf3_const;
14128 else if (mode == DFmode)
14129 copysign_insn = gen_copysigndf3_const;
14131 copysign_insn = gen_copysigntf3_const;
14133 emit_insn (copysign_insn (dest, op0, op1, mask));
14137 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14139 nmask = ix86_build_signbit_mask (mode, 0, 1);
14140 mask = ix86_build_signbit_mask (mode, 0, 0);
14142 if (mode == SFmode)
14143 copysign_insn = gen_copysignsf3_var;
14144 else if (mode == DFmode)
14145 copysign_insn = gen_copysigndf3_var;
14147 copysign_insn = gen_copysigntf3_var;
14149 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14153 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14154 be a constant, and so has already been expanded into a vector constant. */
14157 ix86_split_copysign_const (rtx operands[])
14159 enum machine_mode mode, vmode;
14160 rtx dest, op0, op1, mask, x;
14162 dest = operands[0];
14165 mask = operands[3];
14167 mode = GET_MODE (dest);
14168 vmode = GET_MODE (mask);
14170 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14171 x = gen_rtx_AND (vmode, dest, mask);
14172 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14174 if (op0 != CONST0_RTX (vmode))
14176 x = gen_rtx_IOR (vmode, dest, op0);
14177 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14181 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14182 so we have to do two masks. */
14185 ix86_split_copysign_var (rtx operands[])
14187 enum machine_mode mode, vmode;
14188 rtx dest, scratch, op0, op1, mask, nmask, x;
14190 dest = operands[0];
14191 scratch = operands[1];
14194 nmask = operands[4];
14195 mask = operands[5];
14197 mode = GET_MODE (dest);
14198 vmode = GET_MODE (mask);
14200 if (rtx_equal_p (op0, op1))
14202 /* Shouldn't happen often (it's useless, obviously), but when it does
14203 we'd generate incorrect code if we continue below. */
14204 emit_move_insn (dest, op0);
14208 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14210 gcc_assert (REGNO (op1) == REGNO (scratch));
14212 x = gen_rtx_AND (vmode, scratch, mask);
14213 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14216 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14217 x = gen_rtx_NOT (vmode, dest);
14218 x = gen_rtx_AND (vmode, x, op0);
14219 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14223 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14225 x = gen_rtx_AND (vmode, scratch, mask);
14227 else /* alternative 2,4 */
14229 gcc_assert (REGNO (mask) == REGNO (scratch));
14230 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14231 x = gen_rtx_AND (vmode, scratch, op1);
14233 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14235 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14237 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14238 x = gen_rtx_AND (vmode, dest, nmask);
14240 else /* alternative 3,4 */
14242 gcc_assert (REGNO (nmask) == REGNO (dest));
14244 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14245 x = gen_rtx_AND (vmode, dest, op0);
14247 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14250 x = gen_rtx_IOR (vmode, dest, scratch);
14251 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14254 /* Return TRUE or FALSE depending on whether the first SET in INSN
14255 has source and destination with matching CC modes, and that the
14256 CC mode is at least as constrained as REQ_MODE. */
14259 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14262 enum machine_mode set_mode;
14264 set = PATTERN (insn);
14265 if (GET_CODE (set) == PARALLEL)
14266 set = XVECEXP (set, 0, 0);
14267 gcc_assert (GET_CODE (set) == SET);
14268 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14270 set_mode = GET_MODE (SET_DEST (set));
14274 if (req_mode != CCNOmode
14275 && (req_mode != CCmode
14276 || XEXP (SET_SRC (set), 1) != const0_rtx))
14280 if (req_mode == CCGCmode)
14284 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14288 if (req_mode == CCZmode)
14299 gcc_unreachable ();
14302 return (GET_MODE (SET_SRC (set)) == set_mode);
14305 /* Generate insn patterns to do an integer compare of OPERANDS. */
14308 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14310 enum machine_mode cmpmode;
14313 cmpmode = SELECT_CC_MODE (code, op0, op1);
14314 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14316 /* This is very simple, but making the interface the same as in the
14317 FP case makes the rest of the code easier. */
14318 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14319 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14321 /* Return the test that should be put into the flags user, i.e.
14322 the bcc, scc, or cmov instruction. */
14323 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14326 /* Figure out whether to use ordered or unordered fp comparisons.
14327 Return the appropriate mode to use. */
14330 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14332 /* ??? In order to make all comparisons reversible, we do all comparisons
14333 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14334 all forms trapping and nontrapping comparisons, we can make inequality
14335 comparisons trapping again, since it results in better code when using
14336 FCOM based compares. */
14337 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14341 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14343 enum machine_mode mode = GET_MODE (op0);
14345 if (SCALAR_FLOAT_MODE_P (mode))
14347 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14348 return ix86_fp_compare_mode (code);
14353 /* Only zero flag is needed. */
14354 case EQ: /* ZF=0 */
14355 case NE: /* ZF!=0 */
14357 /* Codes needing carry flag. */
14358 case GEU: /* CF=0 */
14359 case LTU: /* CF=1 */
14360 /* Detect overflow checks. They need just the carry flag. */
14361 if (GET_CODE (op0) == PLUS
14362 && rtx_equal_p (op1, XEXP (op0, 0)))
14366 case GTU: /* CF=0 & ZF=0 */
14367 case LEU: /* CF=1 | ZF=1 */
14368 /* Detect overflow checks. They need just the carry flag. */
14369 if (GET_CODE (op0) == MINUS
14370 && rtx_equal_p (op1, XEXP (op0, 0)))
14374 /* Codes possibly doable only with sign flag when
14375 comparing against zero. */
14376 case GE: /* SF=OF or SF=0 */
14377 case LT: /* SF<>OF or SF=1 */
14378 if (op1 == const0_rtx)
14381 /* For other cases Carry flag is not required. */
14383 /* Codes doable only with sign flag when comparing
14384 against zero, but we miss jump instruction for it
14385 so we need to use relational tests against overflow
14386 that thus needs to be zero. */
14387 case GT: /* ZF=0 & SF=OF */
14388 case LE: /* ZF=1 | SF<>OF */
14389 if (op1 == const0_rtx)
14393 /* strcmp pattern do (use flags) and combine may ask us for proper
14398 gcc_unreachable ();
14402 /* Return the fixed registers used for condition codes. */
14405 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14412 /* If two condition code modes are compatible, return a condition code
14413 mode which is compatible with both. Otherwise, return
14416 static enum machine_mode
14417 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14422 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14425 if ((m1 == CCGCmode && m2 == CCGOCmode)
14426 || (m1 == CCGOCmode && m2 == CCGCmode))
14432 gcc_unreachable ();
14462 /* These are only compatible with themselves, which we already
14468 /* Split comparison code CODE into comparisons we can do using branch
14469 instructions. BYPASS_CODE is comparison code for branch that will
14470 branch around FIRST_CODE and SECOND_CODE. If some of branches
14471 is not required, set value to UNKNOWN.
14472 We never require more than two branches. */
14475 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
14476 enum rtx_code *first_code,
14477 enum rtx_code *second_code)
14479 *first_code = code;
14480 *bypass_code = UNKNOWN;
14481 *second_code = UNKNOWN;
14483 /* The fcomi comparison sets flags as follows:
14493 case GT: /* GTU - CF=0 & ZF=0 */
14494 case GE: /* GEU - CF=0 */
14495 case ORDERED: /* PF=0 */
14496 case UNORDERED: /* PF=1 */
14497 case UNEQ: /* EQ - ZF=1 */
14498 case UNLT: /* LTU - CF=1 */
14499 case UNLE: /* LEU - CF=1 | ZF=1 */
14500 case LTGT: /* EQ - ZF=0 */
14502 case LT: /* LTU - CF=1 - fails on unordered */
14503 *first_code = UNLT;
14504 *bypass_code = UNORDERED;
14506 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
14507 *first_code = UNLE;
14508 *bypass_code = UNORDERED;
14510 case EQ: /* EQ - ZF=1 - fails on unordered */
14511 *first_code = UNEQ;
14512 *bypass_code = UNORDERED;
14514 case NE: /* NE - ZF=0 - fails on unordered */
14515 *first_code = LTGT;
14516 *second_code = UNORDERED;
14518 case UNGE: /* GEU - CF=0 - fails on unordered */
14520 *second_code = UNORDERED;
14522 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
14524 *second_code = UNORDERED;
14527 gcc_unreachable ();
14529 if (!TARGET_IEEE_FP)
14531 *second_code = UNKNOWN;
14532 *bypass_code = UNKNOWN;
14536 /* Return cost of comparison done fcom + arithmetics operations on AX.
14537 All following functions do use number of instructions as a cost metrics.
14538 In future this should be tweaked to compute bytes for optimize_size and
14539 take into account performance of various instructions on various CPUs. */
14541 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
14543 if (!TARGET_IEEE_FP)
14545 /* The cost of code output by ix86_expand_fp_compare. */
14569 gcc_unreachable ();
14573 /* Return cost of comparison done using fcomi operation.
14574 See ix86_fp_comparison_arithmetics_cost for the metrics. */
14576 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
14578 enum rtx_code bypass_code, first_code, second_code;
14579 /* Return arbitrarily high cost when instruction is not supported - this
14580 prevents gcc from using it. */
14583 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14584 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
14587 /* Return cost of comparison done using sahf operation.
14588 See ix86_fp_comparison_arithmetics_cost for the metrics. */
14590 ix86_fp_comparison_sahf_cost (enum rtx_code code)
14592 enum rtx_code bypass_code, first_code, second_code;
14593 /* Return arbitrarily high cost when instruction is not preferred - this
14594 avoids gcc from using it. */
14595 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
14597 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14598 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
14601 /* Compute cost of the comparison done using any method.
14602 See ix86_fp_comparison_arithmetics_cost for the metrics. */
14604 ix86_fp_comparison_cost (enum rtx_code code)
14606 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
14609 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
14610 sahf_cost = ix86_fp_comparison_sahf_cost (code);
14612 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
14613 if (min > sahf_cost)
14615 if (min > fcomi_cost)
14620 /* Return true if we should use an FCOMI instruction for this
14624 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
14626 enum rtx_code swapped_code = swap_condition (code);
14628 return ((ix86_fp_comparison_cost (code)
14629 == ix86_fp_comparison_fcomi_cost (code))
14630 || (ix86_fp_comparison_cost (swapped_code)
14631 == ix86_fp_comparison_fcomi_cost (swapped_code)));
14634 /* Swap, force into registers, or otherwise massage the two operands
14635 to a fp comparison. The operands are updated in place; the new
14636 comparison code is returned. */
14638 static enum rtx_code
14639 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14641 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14642 rtx op0 = *pop0, op1 = *pop1;
14643 enum machine_mode op_mode = GET_MODE (op0);
14644 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14646 /* All of the unordered compare instructions only work on registers.
14647 The same is true of the fcomi compare instructions. The XFmode
14648 compare instructions require registers except when comparing
14649 against zero or when converting operand 1 from fixed point to
14653 && (fpcmp_mode == CCFPUmode
14654 || (op_mode == XFmode
14655 && ! (standard_80387_constant_p (op0) == 1
14656 || standard_80387_constant_p (op1) == 1)
14657 && GET_CODE (op1) != FLOAT)
14658 || ix86_use_fcomi_compare (code)))
14660 op0 = force_reg (op_mode, op0);
14661 op1 = force_reg (op_mode, op1);
14665 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14666 things around if they appear profitable, otherwise force op0
14667 into a register. */
14669 if (standard_80387_constant_p (op0) == 0
14671 && ! (standard_80387_constant_p (op1) == 0
14675 tmp = op0, op0 = op1, op1 = tmp;
14676 code = swap_condition (code);
14680 op0 = force_reg (op_mode, op0);
14682 if (CONSTANT_P (op1))
14684 int tmp = standard_80387_constant_p (op1);
14686 op1 = validize_mem (force_const_mem (op_mode, op1));
14690 op1 = force_reg (op_mode, op1);
14693 op1 = force_reg (op_mode, op1);
14697 /* Try to rearrange the comparison to make it cheaper. */
14698 if (ix86_fp_comparison_cost (code)
14699 > ix86_fp_comparison_cost (swap_condition (code))
14700 && (REG_P (op1) || can_create_pseudo_p ()))
14703 tmp = op0, op0 = op1, op1 = tmp;
14704 code = swap_condition (code);
14706 op0 = force_reg (op_mode, op0);
14714 /* Convert comparison codes we use to represent FP comparison to integer
14715 code that will result in proper branch. Return UNKNOWN if no such code
14719 ix86_fp_compare_code_to_integer (enum rtx_code code)
14748 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14751 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
14752 rtx *second_test, rtx *bypass_test)
14754 enum machine_mode fpcmp_mode, intcmp_mode;
14756 int cost = ix86_fp_comparison_cost (code);
14757 enum rtx_code bypass_code, first_code, second_code;
14759 fpcmp_mode = ix86_fp_compare_mode (code);
14760 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14763 *second_test = NULL_RTX;
14765 *bypass_test = NULL_RTX;
14767 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14769 /* Do fcomi/sahf based test when profitable. */
14770 if (ix86_fp_comparison_arithmetics_cost (code) > cost
14771 && (bypass_code == UNKNOWN || bypass_test)
14772 && (second_code == UNKNOWN || second_test))
14774 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14775 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14781 gcc_assert (TARGET_SAHF);
14784 scratch = gen_reg_rtx (HImode);
14785 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14787 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14790 /* The FP codes work out to act like unsigned. */
14791 intcmp_mode = fpcmp_mode;
14793 if (bypass_code != UNKNOWN)
14794 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
14795 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14797 if (second_code != UNKNOWN)
14798 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
14799 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14804 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14805 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14806 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14808 scratch = gen_reg_rtx (HImode);
14809 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14811 /* In the unordered case, we have to check C2 for NaN's, which
14812 doesn't happen to work out to anything nice combination-wise.
14813 So do some bit twiddling on the value we've got in AH to come
14814 up with an appropriate set of condition codes. */
14816 intcmp_mode = CCNOmode;
14821 if (code == GT || !TARGET_IEEE_FP)
14823 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14828 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14829 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14830 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14831 intcmp_mode = CCmode;
14837 if (code == LT && TARGET_IEEE_FP)
14839 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14840 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14841 intcmp_mode = CCmode;
14846 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14852 if (code == GE || !TARGET_IEEE_FP)
14854 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14859 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14860 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14867 if (code == LE && TARGET_IEEE_FP)
14869 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14870 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14871 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14872 intcmp_mode = CCmode;
14877 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14883 if (code == EQ && TARGET_IEEE_FP)
14885 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14886 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14887 intcmp_mode = CCmode;
14892 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14899 if (code == NE && TARGET_IEEE_FP)
14901 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14902 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14908 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14914 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14918 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14923 gcc_unreachable ();
14927 /* Return the test that should be put into the flags user, i.e.
14928 the bcc, scc, or cmov instruction. */
14929 return gen_rtx_fmt_ee (code, VOIDmode,
14930 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14935 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14938 op0 = ix86_compare_op0;
14939 op1 = ix86_compare_op1;
14942 *second_test = NULL_RTX;
14944 *bypass_test = NULL_RTX;
14946 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
14947 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
14949 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14951 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14952 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14953 second_test, bypass_test);
14956 ret = ix86_expand_int_compare (code, op0, op1);
14961 /* Return true if the CODE will result in nontrivial jump sequence. */
14963 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14965 enum rtx_code bypass_code, first_code, second_code;
14968 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14969 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14973 ix86_expand_branch (enum rtx_code code, rtx label)
14977 switch (GET_MODE (ix86_compare_op0))
14983 tmp = ix86_expand_compare (code, NULL, NULL);
14984 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14985 gen_rtx_LABEL_REF (VOIDmode, label),
14987 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14996 enum rtx_code bypass_code, first_code, second_code;
14998 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14999 &ix86_compare_op1);
15001 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
15003 /* Check whether we will use the natural sequence with one jump. If
15004 so, we can expand jump early. Otherwise delay expansion by
15005 creating compound insn to not confuse optimizers. */
15006 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
15008 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
15009 gen_rtx_LABEL_REF (VOIDmode, label),
15010 pc_rtx, NULL_RTX, NULL_RTX);
15014 tmp = gen_rtx_fmt_ee (code, VOIDmode,
15015 ix86_compare_op0, ix86_compare_op1);
15016 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15017 gen_rtx_LABEL_REF (VOIDmode, label),
15019 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
15021 use_fcomi = ix86_use_fcomi_compare (code);
15022 vec = rtvec_alloc (3 + !use_fcomi);
15023 RTVEC_ELT (vec, 0) = tmp;
15025 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
15027 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
15030 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
15032 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
15041 /* Expand DImode branch into multiple compare+branch. */
15043 rtx lo[2], hi[2], label2;
15044 enum rtx_code code1, code2, code3;
15045 enum machine_mode submode;
15047 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
15049 tmp = ix86_compare_op0;
15050 ix86_compare_op0 = ix86_compare_op1;
15051 ix86_compare_op1 = tmp;
15052 code = swap_condition (code);
15054 if (GET_MODE (ix86_compare_op0) == DImode)
15056 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
15057 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
15062 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
15063 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
15067 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15068 avoid two branches. This costs one extra insn, so disable when
15069 optimizing for size. */
15071 if ((code == EQ || code == NE)
15072 && (!optimize_insn_for_size_p ()
15073 || hi[1] == const0_rtx || lo[1] == const0_rtx))
15078 if (hi[1] != const0_rtx)
15079 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
15080 NULL_RTX, 0, OPTAB_WIDEN);
15083 if (lo[1] != const0_rtx)
15084 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
15085 NULL_RTX, 0, OPTAB_WIDEN);
15087 tmp = expand_binop (submode, ior_optab, xor1, xor0,
15088 NULL_RTX, 0, OPTAB_WIDEN);
15090 ix86_compare_op0 = tmp;
15091 ix86_compare_op1 = const0_rtx;
15092 ix86_expand_branch (code, label);
15096 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15097 op1 is a constant and the low word is zero, then we can just
15098 examine the high word. Similarly for low word -1 and
15099 less-or-equal-than or greater-than. */
15101 if (CONST_INT_P (hi[1]))
15104 case LT: case LTU: case GE: case GEU:
15105 if (lo[1] == const0_rtx)
15107 ix86_compare_op0 = hi[0];
15108 ix86_compare_op1 = hi[1];
15109 ix86_expand_branch (code, label);
15113 case LE: case LEU: case GT: case GTU:
15114 if (lo[1] == constm1_rtx)
15116 ix86_compare_op0 = hi[0];
15117 ix86_compare_op1 = hi[1];
15118 ix86_expand_branch (code, label);
15126 /* Otherwise, we need two or three jumps. */
15128 label2 = gen_label_rtx ();
15131 code2 = swap_condition (code);
15132 code3 = unsigned_condition (code);
15136 case LT: case GT: case LTU: case GTU:
15139 case LE: code1 = LT; code2 = GT; break;
15140 case GE: code1 = GT; code2 = LT; break;
15141 case LEU: code1 = LTU; code2 = GTU; break;
15142 case GEU: code1 = GTU; code2 = LTU; break;
15144 case EQ: code1 = UNKNOWN; code2 = NE; break;
15145 case NE: code2 = UNKNOWN; break;
15148 gcc_unreachable ();
15153 * if (hi(a) < hi(b)) goto true;
15154 * if (hi(a) > hi(b)) goto false;
15155 * if (lo(a) < lo(b)) goto true;
15159 ix86_compare_op0 = hi[0];
15160 ix86_compare_op1 = hi[1];
15162 if (code1 != UNKNOWN)
15163 ix86_expand_branch (code1, label);
15164 if (code2 != UNKNOWN)
15165 ix86_expand_branch (code2, label2);
15167 ix86_compare_op0 = lo[0];
15168 ix86_compare_op1 = lo[1];
15169 ix86_expand_branch (code3, label);
15171 if (code2 != UNKNOWN)
15172 emit_label (label2);
15177 /* If we have already emitted a compare insn, go straight to simple.
15178 ix86_expand_compare won't emit anything if ix86_compare_emitted
15180 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
15185 /* Split branch based on floating point condition. */
15187 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
15188 rtx target1, rtx target2, rtx tmp, rtx pushed)
15190 rtx second, bypass;
15191 rtx label = NULL_RTX;
15193 int bypass_probability = -1, second_probability = -1, probability = -1;
15196 if (target2 != pc_rtx)
15199 code = reverse_condition_maybe_unordered (code);
15204 condition = ix86_expand_fp_compare (code, op1, op2,
15205 tmp, &second, &bypass);
15207 /* Remove pushed operand from stack. */
15209 ix86_free_from_memory (GET_MODE (pushed));
15211 if (split_branch_probability >= 0)
15213 /* Distribute the probabilities across the jumps.
15214 Assume the BYPASS and SECOND to be always test
15216 probability = split_branch_probability;
15218 /* Value of 1 is low enough to make no need for probability
15219 to be updated. Later we may run some experiments and see
15220 if unordered values are more frequent in practice. */
15222 bypass_probability = 1;
15224 second_probability = 1;
15226 if (bypass != NULL_RTX)
15228 label = gen_label_rtx ();
15229 i = emit_jump_insn (gen_rtx_SET
15231 gen_rtx_IF_THEN_ELSE (VOIDmode,
15233 gen_rtx_LABEL_REF (VOIDmode,
15236 if (bypass_probability >= 0)
15237 add_reg_note (i, REG_BR_PROB, GEN_INT (bypass_probability));
15239 i = emit_jump_insn (gen_rtx_SET
15241 gen_rtx_IF_THEN_ELSE (VOIDmode,
15242 condition, target1, target2)));
15243 if (probability >= 0)
15244 add_reg_note (i, REG_BR_PROB, GEN_INT (probability));
15245 if (second != NULL_RTX)
15247 i = emit_jump_insn (gen_rtx_SET
15249 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
15251 if (second_probability >= 0)
15252 add_reg_note (i, REG_BR_PROB, GEN_INT (second_probability));
15254 if (label != NULL_RTX)
15255 emit_label (label);
15259 ix86_expand_setcc (enum rtx_code code, rtx dest)
15261 rtx ret, tmp, tmpreg, equiv;
15262 rtx second_test, bypass_test;
15264 gcc_assert (GET_MODE (dest) == QImode);
15266 ret = ix86_expand_compare (code, &second_test, &bypass_test);
15267 PUT_MODE (ret, QImode);
15272 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
15273 if (bypass_test || second_test)
15275 rtx test = second_test;
15277 rtx tmp2 = gen_reg_rtx (QImode);
15280 gcc_assert (!second_test);
15281 test = bypass_test;
15283 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
15285 PUT_MODE (test, QImode);
15286 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
15289 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
15291 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
15294 /* Attach a REG_EQUAL note describing the comparison result. */
15295 if (ix86_compare_op0 && ix86_compare_op1)
15297 equiv = simplify_gen_relational (code, QImode,
15298 GET_MODE (ix86_compare_op0),
15299 ix86_compare_op0, ix86_compare_op1);
15300 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
15304 /* Expand comparison setting or clearing carry flag. Return true when
15305 successful and set pop for the operation. */
15307 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15309 enum machine_mode mode =
15310 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15312 /* Do not handle DImode compares that go through special path. */
15313 if (mode == (TARGET_64BIT ? TImode : DImode))
15316 if (SCALAR_FLOAT_MODE_P (mode))
15318 rtx second_test = NULL, bypass_test = NULL;
15319 rtx compare_op, compare_seq;
15321 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15323 /* Shortcut: following common codes never translate
15324 into carry flag compares. */
15325 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15326 || code == ORDERED || code == UNORDERED)
15329 /* These comparisons require zero flag; swap operands so they won't. */
15330 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15331 && !TARGET_IEEE_FP)
15336 code = swap_condition (code);
15339 /* Try to expand the comparison and verify that we end up with
15340 carry flag based comparison. This fails to be true only when
15341 we decide to expand comparison using arithmetic that is not
15342 too common scenario. */
15344 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
15345 &second_test, &bypass_test);
15346 compare_seq = get_insns ();
15349 if (second_test || bypass_test)
15352 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15353 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15354 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15356 code = GET_CODE (compare_op);
15358 if (code != LTU && code != GEU)
15361 emit_insn (compare_seq);
15366 if (!INTEGRAL_MODE_P (mode))
15375 /* Convert a==0 into (unsigned)a<1. */
15378 if (op1 != const0_rtx)
15381 code = (code == EQ ? LTU : GEU);
15384 /* Convert a>b into b<a or a>=b-1. */
15387 if (CONST_INT_P (op1))
15389 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15390 /* Bail out on overflow. We still can swap operands but that
15391 would force loading of the constant into register. */
15392 if (op1 == const0_rtx
15393 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15395 code = (code == GTU ? GEU : LTU);
15402 code = (code == GTU ? LTU : GEU);
15406 /* Convert a>=0 into (unsigned)a<0x80000000. */
15409 if (mode == DImode || op1 != const0_rtx)
15411 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15412 code = (code == LT ? GEU : LTU);
15416 if (mode == DImode || op1 != constm1_rtx)
15418 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15419 code = (code == LE ? GEU : LTU);
15425 /* Swapping operands may cause constant to appear as first operand. */
15426 if (!nonimmediate_operand (op0, VOIDmode))
15428 if (!can_create_pseudo_p ())
15430 op0 = force_reg (mode, op0);
15432 ix86_compare_op0 = op0;
15433 ix86_compare_op1 = op1;
15434 *pop = ix86_expand_compare (code, NULL, NULL);
15435 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15440 ix86_expand_int_movcc (rtx operands[])
15442 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15443 rtx compare_seq, compare_op;
15444 rtx second_test, bypass_test;
15445 enum machine_mode mode = GET_MODE (operands[0]);
15446 bool sign_bit_compare_p = false;;
15449 ix86_compare_op0 = XEXP (operands[1], 0);
15450 ix86_compare_op1 = XEXP (operands[1], 1);
15451 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15452 compare_seq = get_insns ();
15455 compare_code = GET_CODE (compare_op);
15457 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15458 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15459 sign_bit_compare_p = true;
15461 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15462 HImode insns, we'd be swallowed in word prefix ops. */
15464 if ((mode != HImode || TARGET_FAST_PREFIX)
15465 && (mode != (TARGET_64BIT ? TImode : DImode))
15466 && CONST_INT_P (operands[2])
15467 && CONST_INT_P (operands[3]))
15469 rtx out = operands[0];
15470 HOST_WIDE_INT ct = INTVAL (operands[2]);
15471 HOST_WIDE_INT cf = INTVAL (operands[3]);
15472 HOST_WIDE_INT diff;
15475 /* Sign bit compares are better done using shifts than we do by using
15477 if (sign_bit_compare_p
15478 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15479 ix86_compare_op1, &compare_op))
15481 /* Detect overlap between destination and compare sources. */
15484 if (!sign_bit_compare_p)
15486 bool fpcmp = false;
15488 compare_code = GET_CODE (compare_op);
15490 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15491 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15494 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15497 /* To simplify rest of code, restrict to the GEU case. */
15498 if (compare_code == LTU)
15500 HOST_WIDE_INT tmp = ct;
15503 compare_code = reverse_condition (compare_code);
15504 code = reverse_condition (code);
15509 PUT_CODE (compare_op,
15510 reverse_condition_maybe_unordered
15511 (GET_CODE (compare_op)));
15513 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15517 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15518 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15519 tmp = gen_reg_rtx (mode);
15521 if (mode == DImode)
15522 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
15524 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
15528 if (code == GT || code == GE)
15529 code = reverse_condition (code);
15532 HOST_WIDE_INT tmp = ct;
15537 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15538 ix86_compare_op1, VOIDmode, 0, -1);
15551 tmp = expand_simple_binop (mode, PLUS,
15553 copy_rtx (tmp), 1, OPTAB_DIRECT);
15564 tmp = expand_simple_binop (mode, IOR,
15566 copy_rtx (tmp), 1, OPTAB_DIRECT);
15568 else if (diff == -1 && ct)
15578 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15580 tmp = expand_simple_binop (mode, PLUS,
15581 copy_rtx (tmp), GEN_INT (cf),
15582 copy_rtx (tmp), 1, OPTAB_DIRECT);
15590 * andl cf - ct, dest
15600 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15603 tmp = expand_simple_binop (mode, AND,
15605 gen_int_mode (cf - ct, mode),
15606 copy_rtx (tmp), 1, OPTAB_DIRECT);
15608 tmp = expand_simple_binop (mode, PLUS,
15609 copy_rtx (tmp), GEN_INT (ct),
15610 copy_rtx (tmp), 1, OPTAB_DIRECT);
15613 if (!rtx_equal_p (tmp, out))
15614 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15616 return 1; /* DONE */
15621 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15624 tmp = ct, ct = cf, cf = tmp;
15627 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15629 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15631 /* We may be reversing unordered compare to normal compare, that
15632 is not valid in general (we may convert non-trapping condition
15633 to trapping one), however on i386 we currently emit all
15634 comparisons unordered. */
15635 compare_code = reverse_condition_maybe_unordered (compare_code);
15636 code = reverse_condition_maybe_unordered (code);
15640 compare_code = reverse_condition (compare_code);
15641 code = reverse_condition (code);
15645 compare_code = UNKNOWN;
15646 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15647 && CONST_INT_P (ix86_compare_op1))
15649 if (ix86_compare_op1 == const0_rtx
15650 && (code == LT || code == GE))
15651 compare_code = code;
15652 else if (ix86_compare_op1 == constm1_rtx)
15656 else if (code == GT)
15661 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15662 if (compare_code != UNKNOWN
15663 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15664 && (cf == -1 || ct == -1))
15666 /* If lea code below could be used, only optimize
15667 if it results in a 2 insn sequence. */
15669 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15670 || diff == 3 || diff == 5 || diff == 9)
15671 || (compare_code == LT && ct == -1)
15672 || (compare_code == GE && cf == -1))
15675 * notl op1 (if necessary)
15683 code = reverse_condition (code);
15686 out = emit_store_flag (out, code, ix86_compare_op0,
15687 ix86_compare_op1, VOIDmode, 0, -1);
15689 out = expand_simple_binop (mode, IOR,
15691 out, 1, OPTAB_DIRECT);
15692 if (out != operands[0])
15693 emit_move_insn (operands[0], out);
15695 return 1; /* DONE */
15700 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15701 || diff == 3 || diff == 5 || diff == 9)
15702 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15704 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15710 * lea cf(dest*(ct-cf)),dest
15714 * This also catches the degenerate setcc-only case.
15720 out = emit_store_flag (out, code, ix86_compare_op0,
15721 ix86_compare_op1, VOIDmode, 0, 1);
15724 /* On x86_64 the lea instruction operates on Pmode, so we need
15725 to get arithmetics done in proper mode to match. */
15727 tmp = copy_rtx (out);
15731 out1 = copy_rtx (out);
15732 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15736 tmp = gen_rtx_PLUS (mode, tmp, out1);
15742 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15745 if (!rtx_equal_p (tmp, out))
15748 out = force_operand (tmp, copy_rtx (out));
15750 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15752 if (!rtx_equal_p (out, operands[0]))
15753 emit_move_insn (operands[0], copy_rtx (out));
15755 return 1; /* DONE */
15759 * General case: Jumpful:
15760 * xorl dest,dest cmpl op1, op2
15761 * cmpl op1, op2 movl ct, dest
15762 * setcc dest jcc 1f
15763 * decl dest movl cf, dest
15764 * andl (cf-ct),dest 1:
15767 * Size 20. Size 14.
15769 * This is reasonably steep, but branch mispredict costs are
15770 * high on modern cpus, so consider failing only if optimizing
15774 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15775 && BRANCH_COST (optimize_insn_for_speed_p (),
15780 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15785 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15787 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15789 /* We may be reversing unordered compare to normal compare,
15790 that is not valid in general (we may convert non-trapping
15791 condition to trapping one), however on i386 we currently
15792 emit all comparisons unordered. */
15793 code = reverse_condition_maybe_unordered (code);
15797 code = reverse_condition (code);
15798 if (compare_code != UNKNOWN)
15799 compare_code = reverse_condition (compare_code);
15803 if (compare_code != UNKNOWN)
15805 /* notl op1 (if needed)
15810 For x < 0 (resp. x <= -1) there will be no notl,
15811 so if possible swap the constants to get rid of the
15813 True/false will be -1/0 while code below (store flag
15814 followed by decrement) is 0/-1, so the constants need
15815 to be exchanged once more. */
15817 if (compare_code == GE || !cf)
15819 code = reverse_condition (code);
15824 HOST_WIDE_INT tmp = cf;
15829 out = emit_store_flag (out, code, ix86_compare_op0,
15830 ix86_compare_op1, VOIDmode, 0, -1);
15834 out = emit_store_flag (out, code, ix86_compare_op0,
15835 ix86_compare_op1, VOIDmode, 0, 1);
15837 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15838 copy_rtx (out), 1, OPTAB_DIRECT);
15841 out = expand_simple_binop (mode, AND, copy_rtx (out),
15842 gen_int_mode (cf - ct, mode),
15843 copy_rtx (out), 1, OPTAB_DIRECT);
15845 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15846 copy_rtx (out), 1, OPTAB_DIRECT);
15847 if (!rtx_equal_p (out, operands[0]))
15848 emit_move_insn (operands[0], copy_rtx (out));
15850 return 1; /* DONE */
15854 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15856 /* Try a few things more with specific constants and a variable. */
15859 rtx var, orig_out, out, tmp;
15861 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15862 return 0; /* FAIL */
15864 /* If one of the two operands is an interesting constant, load a
15865 constant with the above and mask it in with a logical operation. */
15867 if (CONST_INT_P (operands[2]))
15870 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15871 operands[3] = constm1_rtx, op = and_optab;
15872 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15873 operands[3] = const0_rtx, op = ior_optab;
15875 return 0; /* FAIL */
15877 else if (CONST_INT_P (operands[3]))
15880 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15881 operands[2] = constm1_rtx, op = and_optab;
15882 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15883 operands[2] = const0_rtx, op = ior_optab;
15885 return 0; /* FAIL */
15888 return 0; /* FAIL */
15890 orig_out = operands[0];
15891 tmp = gen_reg_rtx (mode);
15894 /* Recurse to get the constant loaded. */
15895 if (ix86_expand_int_movcc (operands) == 0)
15896 return 0; /* FAIL */
15898 /* Mask in the interesting variable. */
15899 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15901 if (!rtx_equal_p (out, orig_out))
15902 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15904 return 1; /* DONE */
15908 * For comparison with above,
15918 if (! nonimmediate_operand (operands[2], mode))
15919 operands[2] = force_reg (mode, operands[2]);
15920 if (! nonimmediate_operand (operands[3], mode))
15921 operands[3] = force_reg (mode, operands[3]);
15923 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15925 rtx tmp = gen_reg_rtx (mode);
15926 emit_move_insn (tmp, operands[3]);
15929 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15931 rtx tmp = gen_reg_rtx (mode);
15932 emit_move_insn (tmp, operands[2]);
15936 if (! register_operand (operands[2], VOIDmode)
15938 || ! register_operand (operands[3], VOIDmode)))
15939 operands[2] = force_reg (mode, operands[2]);
15942 && ! register_operand (operands[3], VOIDmode))
15943 operands[3] = force_reg (mode, operands[3]);
15945 emit_insn (compare_seq);
15946 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15947 gen_rtx_IF_THEN_ELSE (mode,
15948 compare_op, operands[2],
15951 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15952 gen_rtx_IF_THEN_ELSE (mode,
15954 copy_rtx (operands[3]),
15955 copy_rtx (operands[0]))));
15957 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15958 gen_rtx_IF_THEN_ELSE (mode,
15960 copy_rtx (operands[2]),
15961 copy_rtx (operands[0]))));
15963 return 1; /* DONE */
15966 /* Swap, force into registers, or otherwise massage the two operands
15967 to an sse comparison with a mask result. Thus we differ a bit from
15968 ix86_prepare_fp_compare_args which expects to produce a flags result.
15970 The DEST operand exists to help determine whether to commute commutative
15971 operators. The POP0/POP1 operands are updated in place. The new
15972 comparison code is returned, or UNKNOWN if not implementable. */
15974 static enum rtx_code
15975 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15976 rtx *pop0, rtx *pop1)
15984 /* We have no LTGT as an operator. We could implement it with
15985 NE & ORDERED, but this requires an extra temporary. It's
15986 not clear that it's worth it. */
15993 /* These are supported directly. */
16000 /* For commutative operators, try to canonicalize the destination
16001 operand to be first in the comparison - this helps reload to
16002 avoid extra moves. */
16003 if (!dest || !rtx_equal_p (dest, *pop1))
16011 /* These are not supported directly. Swap the comparison operands
16012 to transform into something that is supported. */
16016 code = swap_condition (code);
16020 gcc_unreachable ();
16026 /* Detect conditional moves that exactly match min/max operational
16027 semantics. Note that this is IEEE safe, as long as we don't
16028 interchange the operands.
16030 Returns FALSE if this conditional move doesn't match a MIN/MAX,
16031 and TRUE if the operation is successful and instructions are emitted. */
16034 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
16035 rtx cmp_op1, rtx if_true, rtx if_false)
16037 enum machine_mode mode;
16043 else if (code == UNGE)
16046 if_true = if_false;
16052 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
16054 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
16059 mode = GET_MODE (dest);
16061 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
16062 but MODE may be a vector mode and thus not appropriate. */
16063 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
16065 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
16068 if_true = force_reg (mode, if_true);
16069 v = gen_rtvec (2, if_true, if_false);
16070 tmp = gen_rtx_UNSPEC (mode, v, u);
16074 code = is_min ? SMIN : SMAX;
16075 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
16078 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
16082 /* Expand an sse vector comparison. Return the register with the result. */
16085 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
16086 rtx op_true, rtx op_false)
16088 enum machine_mode mode = GET_MODE (dest);
16091 cmp_op0 = force_reg (mode, cmp_op0);
16092 if (!nonimmediate_operand (cmp_op1, mode))
16093 cmp_op1 = force_reg (mode, cmp_op1);
16096 || reg_overlap_mentioned_p (dest, op_true)
16097 || reg_overlap_mentioned_p (dest, op_false))
16098 dest = gen_reg_rtx (mode);
16100 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
16101 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16106 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16107 operations. This is used for both scalar and vector conditional moves. */
16110 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
16112 enum machine_mode mode = GET_MODE (dest);
16115 if (op_false == CONST0_RTX (mode))
16117 op_true = force_reg (mode, op_true);
16118 x = gen_rtx_AND (mode, cmp, op_true);
16119 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16121 else if (op_true == CONST0_RTX (mode))
16123 op_false = force_reg (mode, op_false);
16124 x = gen_rtx_NOT (mode, cmp);
16125 x = gen_rtx_AND (mode, x, op_false);
16126 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16128 else if (TARGET_SSE5)
16130 rtx pcmov = gen_rtx_SET (mode, dest,
16131 gen_rtx_IF_THEN_ELSE (mode, cmp,
16138 op_true = force_reg (mode, op_true);
16139 op_false = force_reg (mode, op_false);
16141 t2 = gen_reg_rtx (mode);
16143 t3 = gen_reg_rtx (mode);
16147 x = gen_rtx_AND (mode, op_true, cmp);
16148 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
16150 x = gen_rtx_NOT (mode, cmp);
16151 x = gen_rtx_AND (mode, x, op_false);
16152 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
16154 x = gen_rtx_IOR (mode, t3, t2);
16155 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16159 /* Expand a floating-point conditional move. Return true if successful. */
16162 ix86_expand_fp_movcc (rtx operands[])
16164 enum machine_mode mode = GET_MODE (operands[0]);
16165 enum rtx_code code = GET_CODE (operands[1]);
16166 rtx tmp, compare_op, second_test, bypass_test;
16168 ix86_compare_op0 = XEXP (operands[1], 0);
16169 ix86_compare_op1 = XEXP (operands[1], 1);
16170 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
16172 enum machine_mode cmode;
16174 /* Since we've no cmove for sse registers, don't force bad register
16175 allocation just to gain access to it. Deny movcc when the
16176 comparison mode doesn't match the move mode. */
16177 cmode = GET_MODE (ix86_compare_op0);
16178 if (cmode == VOIDmode)
16179 cmode = GET_MODE (ix86_compare_op1);
16183 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16185 &ix86_compare_op1);
16186 if (code == UNKNOWN)
16189 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
16190 ix86_compare_op1, operands[2],
16194 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
16195 ix86_compare_op1, operands[2], operands[3]);
16196 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
16200 /* The floating point conditional move instructions don't directly
16201 support conditions resulting from a signed integer comparison. */
16203 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
16205 /* The floating point conditional move instructions don't directly
16206 support signed integer comparisons. */
16208 if (!fcmov_comparison_operator (compare_op, VOIDmode))
16210 gcc_assert (!second_test && !bypass_test);
16211 tmp = gen_reg_rtx (QImode);
16212 ix86_expand_setcc (code, tmp);
16214 ix86_compare_op0 = tmp;
16215 ix86_compare_op1 = const0_rtx;
16216 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
16218 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
16220 tmp = gen_reg_rtx (mode);
16221 emit_move_insn (tmp, operands[3]);
16224 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
16226 tmp = gen_reg_rtx (mode);
16227 emit_move_insn (tmp, operands[2]);
16231 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16232 gen_rtx_IF_THEN_ELSE (mode, compare_op,
16233 operands[2], operands[3])));
16235 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16236 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
16237 operands[3], operands[0])));
16239 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16240 gen_rtx_IF_THEN_ELSE (mode, second_test,
16241 operands[2], operands[0])));
16246 /* Expand a floating-point vector conditional move; a vcond operation
16247 rather than a movcc operation. */
16250 ix86_expand_fp_vcond (rtx operands[])
16252 enum rtx_code code = GET_CODE (operands[3]);
16255 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16256 &operands[4], &operands[5]);
16257 if (code == UNKNOWN)
16260 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
16261 operands[5], operands[1], operands[2]))
16264 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
16265 operands[1], operands[2]);
16266 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
16270 /* Expand a signed/unsigned integral vector conditional move. */
16273 ix86_expand_int_vcond (rtx operands[])
16275 enum machine_mode mode = GET_MODE (operands[0]);
16276 enum rtx_code code = GET_CODE (operands[3]);
16277 bool negate = false;
16280 cop0 = operands[4];
16281 cop1 = operands[5];
16283 /* SSE5 supports all of the comparisons on all vector int types. */
16286 /* Canonicalize the comparison to EQ, GT, GTU. */
16297 code = reverse_condition (code);
16303 code = reverse_condition (code);
16309 code = swap_condition (code);
16310 x = cop0, cop0 = cop1, cop1 = x;
16314 gcc_unreachable ();
16317 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16318 if (mode == V2DImode)
16323 /* SSE4.1 supports EQ. */
16324 if (!TARGET_SSE4_1)
16330 /* SSE4.2 supports GT/GTU. */
16331 if (!TARGET_SSE4_2)
16336 gcc_unreachable ();
16340 /* Unsigned parallel compare is not supported by the hardware. Play some
16341 tricks to turn this into a signed comparison against 0. */
16344 cop0 = force_reg (mode, cop0);
16353 /* Perform a parallel modulo subtraction. */
16354 t1 = gen_reg_rtx (mode);
16355 emit_insn ((mode == V4SImode
16357 : gen_subv2di3) (t1, cop0, cop1));
16359 /* Extract the original sign bit of op0. */
16360 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16362 t2 = gen_reg_rtx (mode);
16363 emit_insn ((mode == V4SImode
16365 : gen_andv2di3) (t2, cop0, mask));
16367 /* XOR it back into the result of the subtraction. This results
16368 in the sign bit set iff we saw unsigned underflow. */
16369 x = gen_reg_rtx (mode);
16370 emit_insn ((mode == V4SImode
16372 : gen_xorv2di3) (x, t1, t2));
16380 /* Perform a parallel unsigned saturating subtraction. */
16381 x = gen_reg_rtx (mode);
16382 emit_insn (gen_rtx_SET (VOIDmode, x,
16383 gen_rtx_US_MINUS (mode, cop0, cop1)));
16390 gcc_unreachable ();
16394 cop1 = CONST0_RTX (mode);
16398 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16399 operands[1+negate], operands[2-negate]);
16401 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16402 operands[2-negate]);
16406 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16407 true if we should do zero extension, else sign extension. HIGH_P is
16408 true if we want the N/2 high elements, else the low elements. */
16411 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16413 enum machine_mode imode = GET_MODE (operands[1]);
16414 rtx (*unpack)(rtx, rtx, rtx);
16421 unpack = gen_vec_interleave_highv16qi;
16423 unpack = gen_vec_interleave_lowv16qi;
16427 unpack = gen_vec_interleave_highv8hi;
16429 unpack = gen_vec_interleave_lowv8hi;
16433 unpack = gen_vec_interleave_highv4si;
16435 unpack = gen_vec_interleave_lowv4si;
16438 gcc_unreachable ();
16441 dest = gen_lowpart (imode, operands[0]);
16444 se = force_reg (imode, CONST0_RTX (imode));
16446 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16447 operands[1], pc_rtx, pc_rtx);
16449 emit_insn (unpack (dest, operands[1], se));
16452 /* This function performs the same task as ix86_expand_sse_unpack,
16453 but with SSE4.1 instructions. */
16456 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16458 enum machine_mode imode = GET_MODE (operands[1]);
16459 rtx (*unpack)(rtx, rtx);
16466 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16468 unpack = gen_sse4_1_extendv8qiv8hi2;
16472 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16474 unpack = gen_sse4_1_extendv4hiv4si2;
16478 unpack = gen_sse4_1_zero_extendv2siv2di2;
16480 unpack = gen_sse4_1_extendv2siv2di2;
16483 gcc_unreachable ();
16486 dest = operands[0];
16489 /* Shift higher 8 bytes to lower 8 bytes. */
16490 src = gen_reg_rtx (imode);
16491 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16492 gen_lowpart (TImode, operands[1]),
16498 emit_insn (unpack (dest, src));
16501 /* This function performs the same task as ix86_expand_sse_unpack,
16502 but with sse5 instructions. */
16505 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16507 enum machine_mode imode = GET_MODE (operands[1]);
16508 int pperm_bytes[16];
16510 int h = (high_p) ? 8 : 0;
16513 rtvec v = rtvec_alloc (16);
16516 rtx op0 = operands[0], op1 = operands[1];
16521 vs = rtvec_alloc (8);
16522 h2 = (high_p) ? 8 : 0;
16523 for (i = 0; i < 8; i++)
16525 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
16526 pperm_bytes[2*i+1] = ((unsigned_p)
16528 : PPERM_SIGN | PPERM_SRC2 | i | h);
16531 for (i = 0; i < 16; i++)
16532 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16534 for (i = 0; i < 8; i++)
16535 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
16537 p = gen_rtx_PARALLEL (VOIDmode, vs);
16538 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16540 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
16542 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
16546 vs = rtvec_alloc (4);
16547 h2 = (high_p) ? 4 : 0;
16548 for (i = 0; i < 4; i++)
16550 sign_extend = ((unsigned_p)
16552 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
16553 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
16554 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
16555 pperm_bytes[4*i+2] = sign_extend;
16556 pperm_bytes[4*i+3] = sign_extend;
16559 for (i = 0; i < 16; i++)
16560 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16562 for (i = 0; i < 4; i++)
16563 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
16565 p = gen_rtx_PARALLEL (VOIDmode, vs);
16566 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16568 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
16570 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
16574 vs = rtvec_alloc (2);
16575 h2 = (high_p) ? 2 : 0;
16576 for (i = 0; i < 2; i++)
16578 sign_extend = ((unsigned_p)
16580 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
16581 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
16582 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
16583 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
16584 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
16585 pperm_bytes[8*i+4] = sign_extend;
16586 pperm_bytes[8*i+5] = sign_extend;
16587 pperm_bytes[8*i+6] = sign_extend;
16588 pperm_bytes[8*i+7] = sign_extend;
16591 for (i = 0; i < 16; i++)
16592 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16594 for (i = 0; i < 2; i++)
16595 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
16597 p = gen_rtx_PARALLEL (VOIDmode, vs);
16598 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16600 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
16602 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
16606 gcc_unreachable ();
16612 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
16613 next narrower integer vector type */
16615 ix86_expand_sse5_pack (rtx operands[3])
16617 enum machine_mode imode = GET_MODE (operands[0]);
16618 int pperm_bytes[16];
16620 rtvec v = rtvec_alloc (16);
16622 rtx op0 = operands[0];
16623 rtx op1 = operands[1];
16624 rtx op2 = operands[2];
16629 for (i = 0; i < 8; i++)
16631 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
16632 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
16635 for (i = 0; i < 16; i++)
16636 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16638 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16639 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
16643 for (i = 0; i < 4; i++)
16645 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
16646 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
16647 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
16648 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
16651 for (i = 0; i < 16; i++)
16652 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16654 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16655 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
16659 for (i = 0; i < 2; i++)
16661 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
16662 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
16663 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
16664 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
16665 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
16666 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
16667 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
16668 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
16671 for (i = 0; i < 16; i++)
16672 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16674 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16675 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
16679 gcc_unreachable ();
16685 /* Expand conditional increment or decrement using adb/sbb instructions.
16686 The default case using setcc followed by the conditional move can be
16687 done by generic code. */
16689 ix86_expand_int_addcc (rtx operands[])
16691 enum rtx_code code = GET_CODE (operands[1]);
16693 rtx val = const0_rtx;
16694 bool fpcmp = false;
16695 enum machine_mode mode = GET_MODE (operands[0]);
16697 ix86_compare_op0 = XEXP (operands[1], 0);
16698 ix86_compare_op1 = XEXP (operands[1], 1);
16699 if (operands[3] != const1_rtx
16700 && operands[3] != constm1_rtx)
16702 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16703 ix86_compare_op1, &compare_op))
16705 code = GET_CODE (compare_op);
16707 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16708 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16711 code = ix86_fp_compare_code_to_integer (code);
16718 PUT_CODE (compare_op,
16719 reverse_condition_maybe_unordered
16720 (GET_CODE (compare_op)));
16722 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16724 PUT_MODE (compare_op, mode);
16726 /* Construct either adc or sbb insn. */
16727 if ((code == LTU) == (operands[3] == constm1_rtx))
16729 switch (GET_MODE (operands[0]))
16732 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16735 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16738 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16741 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16744 gcc_unreachable ();
16749 switch (GET_MODE (operands[0]))
16752 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16755 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16758 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16761 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16764 gcc_unreachable ();
16767 return 1; /* DONE */
16771 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16772 works for floating pointer parameters and nonoffsetable memories.
16773 For pushes, it returns just stack offsets; the values will be saved
16774 in the right order. Maximally three parts are generated. */
16777 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16782 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16784 size = (GET_MODE_SIZE (mode) + 4) / 8;
16786 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16787 gcc_assert (size >= 2 && size <= 4);
16789 /* Optimize constant pool reference to immediates. This is used by fp
16790 moves, that force all constants to memory to allow combining. */
16791 if (MEM_P (operand) && MEM_READONLY_P (operand))
16793 rtx tmp = maybe_get_pool_constant (operand);
16798 if (MEM_P (operand) && !offsettable_memref_p (operand))
16800 /* The only non-offsetable memories we handle are pushes. */
16801 int ok = push_operand (operand, VOIDmode);
16805 operand = copy_rtx (operand);
16806 PUT_MODE (operand, Pmode);
16807 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16811 if (GET_CODE (operand) == CONST_VECTOR)
16813 enum machine_mode imode = int_mode_for_mode (mode);
16814 /* Caution: if we looked through a constant pool memory above,
16815 the operand may actually have a different mode now. That's
16816 ok, since we want to pun this all the way back to an integer. */
16817 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16818 gcc_assert (operand != NULL);
16824 if (mode == DImode)
16825 split_di (&operand, 1, &parts[0], &parts[1]);
16830 if (REG_P (operand))
16832 gcc_assert (reload_completed);
16833 for (i = 0; i < size; i++)
16834 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16836 else if (offsettable_memref_p (operand))
16838 operand = adjust_address (operand, SImode, 0);
16839 parts[0] = operand;
16840 for (i = 1; i < size; i++)
16841 parts[i] = adjust_address (operand, SImode, 4 * i);
16843 else if (GET_CODE (operand) == CONST_DOUBLE)
16848 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16852 real_to_target (l, &r, mode);
16853 parts[3] = gen_int_mode (l[3], SImode);
16854 parts[2] = gen_int_mode (l[2], SImode);
16857 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16858 parts[2] = gen_int_mode (l[2], SImode);
16861 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16864 gcc_unreachable ();
16866 parts[1] = gen_int_mode (l[1], SImode);
16867 parts[0] = gen_int_mode (l[0], SImode);
16870 gcc_unreachable ();
16875 if (mode == TImode)
16876 split_ti (&operand, 1, &parts[0], &parts[1]);
16877 if (mode == XFmode || mode == TFmode)
16879 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16880 if (REG_P (operand))
16882 gcc_assert (reload_completed);
16883 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16884 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16886 else if (offsettable_memref_p (operand))
16888 operand = adjust_address (operand, DImode, 0);
16889 parts[0] = operand;
16890 parts[1] = adjust_address (operand, upper_mode, 8);
16892 else if (GET_CODE (operand) == CONST_DOUBLE)
16897 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16898 real_to_target (l, &r, mode);
16900 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16901 if (HOST_BITS_PER_WIDE_INT >= 64)
16904 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16905 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16908 parts[0] = immed_double_const (l[0], l[1], DImode);
16910 if (upper_mode == SImode)
16911 parts[1] = gen_int_mode (l[2], SImode);
16912 else if (HOST_BITS_PER_WIDE_INT >= 64)
16915 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16916 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16919 parts[1] = immed_double_const (l[2], l[3], DImode);
16922 gcc_unreachable ();
16929 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16930 Return false when normal moves are needed; true when all required
16931 insns have been emitted. Operands 2-4 contain the input values
16932 int the correct order; operands 5-7 contain the output values. */
16935 ix86_split_long_move (rtx operands[])
16940 int collisions = 0;
16941 enum machine_mode mode = GET_MODE (operands[0]);
16942 bool collisionparts[4];
16944 /* The DFmode expanders may ask us to move double.
16945 For 64bit target this is single move. By hiding the fact
16946 here we simplify i386.md splitters. */
16947 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16949 /* Optimize constant pool reference to immediates. This is used by
16950 fp moves, that force all constants to memory to allow combining. */
16952 if (MEM_P (operands[1])
16953 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16954 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16955 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16956 if (push_operand (operands[0], VOIDmode))
16958 operands[0] = copy_rtx (operands[0]);
16959 PUT_MODE (operands[0], Pmode);
16962 operands[0] = gen_lowpart (DImode, operands[0]);
16963 operands[1] = gen_lowpart (DImode, operands[1]);
16964 emit_move_insn (operands[0], operands[1]);
16968 /* The only non-offsettable memory we handle is push. */
16969 if (push_operand (operands[0], VOIDmode))
16972 gcc_assert (!MEM_P (operands[0])
16973 || offsettable_memref_p (operands[0]));
16975 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16976 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16978 /* When emitting push, take care for source operands on the stack. */
16979 if (push && MEM_P (operands[1])
16980 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16981 for (i = 0; i < nparts - 1; i++)
16982 part[1][i] = change_address (part[1][i],
16983 GET_MODE (part[1][i]),
16984 XEXP (part[1][i + 1], 0));
16986 /* We need to do copy in the right order in case an address register
16987 of the source overlaps the destination. */
16988 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16992 for (i = 0; i < nparts; i++)
16995 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16996 if (collisionparts[i])
17000 /* Collision in the middle part can be handled by reordering. */
17001 if (collisions == 1 && nparts == 3 && collisionparts [1])
17003 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
17004 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
17006 else if (collisions == 1
17008 && (collisionparts [1] || collisionparts [2]))
17010 if (collisionparts [1])
17012 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
17013 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
17017 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
17018 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
17022 /* If there are more collisions, we can't handle it by reordering.
17023 Do an lea to the last part and use only one colliding move. */
17024 else if (collisions > 1)
17030 base = part[0][nparts - 1];
17032 /* Handle the case when the last part isn't valid for lea.
17033 Happens in 64-bit mode storing the 12-byte XFmode. */
17034 if (GET_MODE (base) != Pmode)
17035 base = gen_rtx_REG (Pmode, REGNO (base));
17037 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
17038 part[1][0] = replace_equiv_address (part[1][0], base);
17039 for (i = 1; i < nparts; i++)
17041 tmp = plus_constant (base, UNITS_PER_WORD * i);
17042 part[1][i] = replace_equiv_address (part[1][i], tmp);
17053 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
17054 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
17055 emit_move_insn (part[0][2], part[1][2]);
17057 else if (nparts == 4)
17059 emit_move_insn (part[0][3], part[1][3]);
17060 emit_move_insn (part[0][2], part[1][2]);
17065 /* In 64bit mode we don't have 32bit push available. In case this is
17066 register, it is OK - we will just use larger counterpart. We also
17067 retype memory - these comes from attempt to avoid REX prefix on
17068 moving of second half of TFmode value. */
17069 if (GET_MODE (part[1][1]) == SImode)
17071 switch (GET_CODE (part[1][1]))
17074 part[1][1] = adjust_address (part[1][1], DImode, 0);
17078 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
17082 gcc_unreachable ();
17085 if (GET_MODE (part[1][0]) == SImode)
17086 part[1][0] = part[1][1];
17089 emit_move_insn (part[0][1], part[1][1]);
17090 emit_move_insn (part[0][0], part[1][0]);
17094 /* Choose correct order to not overwrite the source before it is copied. */
17095 if ((REG_P (part[0][0])
17096 && REG_P (part[1][1])
17097 && (REGNO (part[0][0]) == REGNO (part[1][1])
17099 && REGNO (part[0][0]) == REGNO (part[1][2]))
17101 && REGNO (part[0][0]) == REGNO (part[1][3]))))
17103 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
17105 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
17107 operands[2 + i] = part[0][j];
17108 operands[6 + i] = part[1][j];
17113 for (i = 0; i < nparts; i++)
17115 operands[2 + i] = part[0][i];
17116 operands[6 + i] = part[1][i];
17120 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
17121 if (optimize_insn_for_size_p ())
17123 for (j = 0; j < nparts - 1; j++)
17124 if (CONST_INT_P (operands[6 + j])
17125 && operands[6 + j] != const0_rtx
17126 && REG_P (operands[2 + j]))
17127 for (i = j; i < nparts - 1; i++)
17128 if (CONST_INT_P (operands[7 + i])
17129 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
17130 operands[7 + i] = operands[2 + j];
17133 for (i = 0; i < nparts; i++)
17134 emit_move_insn (operands[2 + i], operands[6 + i]);
17139 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
17140 left shift by a constant, either using a single shift or
17141 a sequence of add instructions. */
17144 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
17148 emit_insn ((mode == DImode
17150 : gen_adddi3) (operand, operand, operand));
17152 else if (!optimize_insn_for_size_p ()
17153 && count * ix86_cost->add <= ix86_cost->shift_const)
17156 for (i=0; i<count; i++)
17158 emit_insn ((mode == DImode
17160 : gen_adddi3) (operand, operand, operand));
17164 emit_insn ((mode == DImode
17166 : gen_ashldi3) (operand, operand, GEN_INT (count)));
17170 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
17172 rtx low[2], high[2];
17174 const int single_width = mode == DImode ? 32 : 64;
17176 if (CONST_INT_P (operands[2]))
17178 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17179 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17181 if (count >= single_width)
17183 emit_move_insn (high[0], low[1]);
17184 emit_move_insn (low[0], const0_rtx);
17186 if (count > single_width)
17187 ix86_expand_ashl_const (high[0], count - single_width, mode);
17191 if (!rtx_equal_p (operands[0], operands[1]))
17192 emit_move_insn (operands[0], operands[1]);
17193 emit_insn ((mode == DImode
17195 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
17196 ix86_expand_ashl_const (low[0], count, mode);
17201 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17203 if (operands[1] == const1_rtx)
17205 /* Assuming we've chosen a QImode capable registers, then 1 << N
17206 can be done with two 32/64-bit shifts, no branches, no cmoves. */
17207 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
17209 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
17211 ix86_expand_clear (low[0]);
17212 ix86_expand_clear (high[0]);
17213 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
17215 d = gen_lowpart (QImode, low[0]);
17216 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
17217 s = gen_rtx_EQ (QImode, flags, const0_rtx);
17218 emit_insn (gen_rtx_SET (VOIDmode, d, s));
17220 d = gen_lowpart (QImode, high[0]);
17221 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
17222 s = gen_rtx_NE (QImode, flags, const0_rtx);
17223 emit_insn (gen_rtx_SET (VOIDmode, d, s));
17226 /* Otherwise, we can get the same results by manually performing
17227 a bit extract operation on bit 5/6, and then performing the two
17228 shifts. The two methods of getting 0/1 into low/high are exactly
17229 the same size. Avoiding the shift in the bit extract case helps
17230 pentium4 a bit; no one else seems to care much either way. */
17235 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
17236 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
17238 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
17239 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
17241 emit_insn ((mode == DImode
17243 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
17244 emit_insn ((mode == DImode
17246 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
17247 emit_move_insn (low[0], high[0]);
17248 emit_insn ((mode == DImode
17250 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
17253 emit_insn ((mode == DImode
17255 : gen_ashldi3) (low[0], low[0], operands[2]));
17256 emit_insn ((mode == DImode
17258 : gen_ashldi3) (high[0], high[0], operands[2]));
17262 if (operands[1] == constm1_rtx)
17264 /* For -1 << N, we can avoid the shld instruction, because we
17265 know that we're shifting 0...31/63 ones into a -1. */
17266 emit_move_insn (low[0], constm1_rtx);
17267 if (optimize_insn_for_size_p ())
17268 emit_move_insn (high[0], low[0]);
17270 emit_move_insn (high[0], constm1_rtx);
17274 if (!rtx_equal_p (operands[0], operands[1]))
17275 emit_move_insn (operands[0], operands[1]);
17277 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17278 emit_insn ((mode == DImode
17280 : gen_x86_64_shld) (high[0], low[0], operands[2]));
17283 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
17285 if (TARGET_CMOVE && scratch)
17287 ix86_expand_clear (scratch);
17288 emit_insn ((mode == DImode
17289 ? gen_x86_shift_adj_1
17290 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
17294 emit_insn ((mode == DImode
17295 ? gen_x86_shift_adj_2
17296 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
17300 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
17302 rtx low[2], high[2];
17304 const int single_width = mode == DImode ? 32 : 64;
17306 if (CONST_INT_P (operands[2]))
17308 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17309 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17311 if (count == single_width * 2 - 1)
17313 emit_move_insn (high[0], high[1]);
17314 emit_insn ((mode == DImode
17316 : gen_ashrdi3) (high[0], high[0],
17317 GEN_INT (single_width - 1)));
17318 emit_move_insn (low[0], high[0]);
17321 else if (count >= single_width)
17323 emit_move_insn (low[0], high[1]);
17324 emit_move_insn (high[0], low[0]);
17325 emit_insn ((mode == DImode
17327 : gen_ashrdi3) (high[0], high[0],
17328 GEN_INT (single_width - 1)));
17329 if (count > single_width)
17330 emit_insn ((mode == DImode
17332 : gen_ashrdi3) (low[0], low[0],
17333 GEN_INT (count - single_width)));
17337 if (!rtx_equal_p (operands[0], operands[1]))
17338 emit_move_insn (operands[0], operands[1]);
17339 emit_insn ((mode == DImode
17341 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17342 emit_insn ((mode == DImode
17344 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
17349 if (!rtx_equal_p (operands[0], operands[1]))
17350 emit_move_insn (operands[0], operands[1]);
17352 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17354 emit_insn ((mode == DImode
17356 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17357 emit_insn ((mode == DImode
17359 : gen_ashrdi3) (high[0], high[0], operands[2]));
17361 if (TARGET_CMOVE && scratch)
17363 emit_move_insn (scratch, high[0]);
17364 emit_insn ((mode == DImode
17366 : gen_ashrdi3) (scratch, scratch,
17367 GEN_INT (single_width - 1)));
17368 emit_insn ((mode == DImode
17369 ? gen_x86_shift_adj_1
17370 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17374 emit_insn ((mode == DImode
17375 ? gen_x86_shift_adj_3
17376 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
17381 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
17383 rtx low[2], high[2];
17385 const int single_width = mode == DImode ? 32 : 64;
17387 if (CONST_INT_P (operands[2]))
17389 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17390 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17392 if (count >= single_width)
17394 emit_move_insn (low[0], high[1]);
17395 ix86_expand_clear (high[0]);
17397 if (count > single_width)
17398 emit_insn ((mode == DImode
17400 : gen_lshrdi3) (low[0], low[0],
17401 GEN_INT (count - single_width)));
17405 if (!rtx_equal_p (operands[0], operands[1]))
17406 emit_move_insn (operands[0], operands[1]);
17407 emit_insn ((mode == DImode
17409 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17410 emit_insn ((mode == DImode
17412 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
17417 if (!rtx_equal_p (operands[0], operands[1]))
17418 emit_move_insn (operands[0], operands[1]);
17420 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17422 emit_insn ((mode == DImode
17424 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17425 emit_insn ((mode == DImode
17427 : gen_lshrdi3) (high[0], high[0], operands[2]));
17429 /* Heh. By reversing the arguments, we can reuse this pattern. */
17430 if (TARGET_CMOVE && scratch)
17432 ix86_expand_clear (scratch);
17433 emit_insn ((mode == DImode
17434 ? gen_x86_shift_adj_1
17435 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17439 emit_insn ((mode == DImode
17440 ? gen_x86_shift_adj_2
17441 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
17445 /* Predict just emitted jump instruction to be taken with probability PROB. */
17447 predict_jump (int prob)
17449 rtx insn = get_last_insn ();
17450 gcc_assert (JUMP_P (insn));
17451 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
17454 /* Helper function for the string operations below. Dest VARIABLE whether
17455 it is aligned to VALUE bytes. If true, jump to the label. */
17457 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
17459 rtx label = gen_label_rtx ();
17460 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
17461 if (GET_MODE (variable) == DImode)
17462 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
17464 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
17465 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
17468 predict_jump (REG_BR_PROB_BASE * 50 / 100);
17470 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17474 /* Adjust COUNTER by the VALUE. */
17476 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
17478 if (GET_MODE (countreg) == DImode)
17479 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
17481 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
17484 /* Zero extend possibly SImode EXP to Pmode register. */
17486 ix86_zero_extend_to_Pmode (rtx exp)
17489 if (GET_MODE (exp) == VOIDmode)
17490 return force_reg (Pmode, exp);
17491 if (GET_MODE (exp) == Pmode)
17492 return copy_to_mode_reg (Pmode, exp);
17493 r = gen_reg_rtx (Pmode);
17494 emit_insn (gen_zero_extendsidi2 (r, exp));
17498 /* Divide COUNTREG by SCALE. */
17500 scale_counter (rtx countreg, int scale)
17503 rtx piece_size_mask;
17507 if (CONST_INT_P (countreg))
17508 return GEN_INT (INTVAL (countreg) / scale);
17509 gcc_assert (REG_P (countreg));
17511 piece_size_mask = GEN_INT (scale - 1);
17512 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17513 GEN_INT (exact_log2 (scale)),
17514 NULL, 1, OPTAB_DIRECT);
17518 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17519 DImode for constant loop counts. */
17521 static enum machine_mode
17522 counter_mode (rtx count_exp)
17524 if (GET_MODE (count_exp) != VOIDmode)
17525 return GET_MODE (count_exp);
17526 if (!CONST_INT_P (count_exp))
17528 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17533 /* When SRCPTR is non-NULL, output simple loop to move memory
17534 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17535 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17536 equivalent loop to set memory by VALUE (supposed to be in MODE).
17538 The size is rounded down to whole number of chunk size moved at once.
17539 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17543 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17544 rtx destptr, rtx srcptr, rtx value,
17545 rtx count, enum machine_mode mode, int unroll,
17548 rtx out_label, top_label, iter, tmp;
17549 enum machine_mode iter_mode = counter_mode (count);
17550 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17551 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17557 top_label = gen_label_rtx ();
17558 out_label = gen_label_rtx ();
17559 iter = gen_reg_rtx (iter_mode);
17561 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17562 NULL, 1, OPTAB_DIRECT);
17563 /* Those two should combine. */
17564 if (piece_size == const1_rtx)
17566 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17568 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17570 emit_move_insn (iter, const0_rtx);
17572 emit_label (top_label);
17574 tmp = convert_modes (Pmode, iter_mode, iter, true);
17575 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17576 destmem = change_address (destmem, mode, x_addr);
17580 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17581 srcmem = change_address (srcmem, mode, y_addr);
17583 /* When unrolling for chips that reorder memory reads and writes,
17584 we can save registers by using single temporary.
17585 Also using 4 temporaries is overkill in 32bit mode. */
17586 if (!TARGET_64BIT && 0)
17588 for (i = 0; i < unroll; i++)
17593 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17595 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17597 emit_move_insn (destmem, srcmem);
17603 gcc_assert (unroll <= 4);
17604 for (i = 0; i < unroll; i++)
17606 tmpreg[i] = gen_reg_rtx (mode);
17610 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17612 emit_move_insn (tmpreg[i], srcmem);
17614 for (i = 0; i < unroll; i++)
17619 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17621 emit_move_insn (destmem, tmpreg[i]);
17626 for (i = 0; i < unroll; i++)
17630 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17631 emit_move_insn (destmem, value);
17634 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17635 true, OPTAB_LIB_WIDEN);
17637 emit_move_insn (iter, tmp);
17639 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17641 if (expected_size != -1)
17643 expected_size /= GET_MODE_SIZE (mode) * unroll;
17644 if (expected_size == 0)
17646 else if (expected_size > REG_BR_PROB_BASE)
17647 predict_jump (REG_BR_PROB_BASE - 1);
17649 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17652 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17653 iter = ix86_zero_extend_to_Pmode (iter);
17654 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17655 true, OPTAB_LIB_WIDEN);
17656 if (tmp != destptr)
17657 emit_move_insn (destptr, tmp);
17660 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17661 true, OPTAB_LIB_WIDEN);
17663 emit_move_insn (srcptr, tmp);
17665 emit_label (out_label);
17668 /* Output "rep; mov" instruction.
17669 Arguments have same meaning as for previous function */
17671 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17672 rtx destptr, rtx srcptr,
17674 enum machine_mode mode)
17680 /* If the size is known, it is shorter to use rep movs. */
17681 if (mode == QImode && CONST_INT_P (count)
17682 && !(INTVAL (count) & 3))
17685 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17686 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17687 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17688 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17689 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17690 if (mode != QImode)
17692 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17693 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17694 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17695 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17696 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17697 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17701 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17702 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17704 if (CONST_INT_P (count))
17706 count = GEN_INT (INTVAL (count)
17707 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17708 destmem = shallow_copy_rtx (destmem);
17709 srcmem = shallow_copy_rtx (srcmem);
17710 set_mem_size (destmem, count);
17711 set_mem_size (srcmem, count);
17715 if (MEM_SIZE (destmem))
17716 set_mem_size (destmem, NULL_RTX);
17717 if (MEM_SIZE (srcmem))
17718 set_mem_size (srcmem, NULL_RTX);
17720 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17724 /* Output "rep; stos" instruction.
17725 Arguments have same meaning as for previous function */
17727 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17728 rtx count, enum machine_mode mode,
17734 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17735 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17736 value = force_reg (mode, gen_lowpart (mode, value));
17737 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17738 if (mode != QImode)
17740 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17741 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17742 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17745 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17746 if (orig_value == const0_rtx && CONST_INT_P (count))
17748 count = GEN_INT (INTVAL (count)
17749 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17750 destmem = shallow_copy_rtx (destmem);
17751 set_mem_size (destmem, count);
17753 else if (MEM_SIZE (destmem))
17754 set_mem_size (destmem, NULL_RTX);
17755 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17759 emit_strmov (rtx destmem, rtx srcmem,
17760 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17762 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17763 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17764 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17767 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17769 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17770 rtx destptr, rtx srcptr, rtx count, int max_size)
17773 if (CONST_INT_P (count))
17775 HOST_WIDE_INT countval = INTVAL (count);
17778 if ((countval & 0x10) && max_size > 16)
17782 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17783 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17786 gcc_unreachable ();
17789 if ((countval & 0x08) && max_size > 8)
17792 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17795 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17796 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17800 if ((countval & 0x04) && max_size > 4)
17802 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17805 if ((countval & 0x02) && max_size > 2)
17807 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17810 if ((countval & 0x01) && max_size > 1)
17812 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17819 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17820 count, 1, OPTAB_DIRECT);
17821 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17822 count, QImode, 1, 4);
17826 /* When there are stringops, we can cheaply increase dest and src pointers.
17827 Otherwise we save code size by maintaining offset (zero is readily
17828 available from preceding rep operation) and using x86 addressing modes.
17830 if (TARGET_SINGLE_STRINGOP)
17834 rtx label = ix86_expand_aligntest (count, 4, true);
17835 src = change_address (srcmem, SImode, srcptr);
17836 dest = change_address (destmem, SImode, destptr);
17837 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17838 emit_label (label);
17839 LABEL_NUSES (label) = 1;
17843 rtx label = ix86_expand_aligntest (count, 2, true);
17844 src = change_address (srcmem, HImode, srcptr);
17845 dest = change_address (destmem, HImode, destptr);
17846 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17847 emit_label (label);
17848 LABEL_NUSES (label) = 1;
17852 rtx label = ix86_expand_aligntest (count, 1, true);
17853 src = change_address (srcmem, QImode, srcptr);
17854 dest = change_address (destmem, QImode, destptr);
17855 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17856 emit_label (label);
17857 LABEL_NUSES (label) = 1;
17862 rtx offset = force_reg (Pmode, const0_rtx);
17867 rtx label = ix86_expand_aligntest (count, 4, true);
17868 src = change_address (srcmem, SImode, srcptr);
17869 dest = change_address (destmem, SImode, destptr);
17870 emit_move_insn (dest, src);
17871 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17872 true, OPTAB_LIB_WIDEN);
17874 emit_move_insn (offset, tmp);
17875 emit_label (label);
17876 LABEL_NUSES (label) = 1;
17880 rtx label = ix86_expand_aligntest (count, 2, true);
17881 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17882 src = change_address (srcmem, HImode, tmp);
17883 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17884 dest = change_address (destmem, HImode, tmp);
17885 emit_move_insn (dest, src);
17886 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17887 true, OPTAB_LIB_WIDEN);
17889 emit_move_insn (offset, tmp);
17890 emit_label (label);
17891 LABEL_NUSES (label) = 1;
17895 rtx label = ix86_expand_aligntest (count, 1, true);
17896 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17897 src = change_address (srcmem, QImode, tmp);
17898 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17899 dest = change_address (destmem, QImode, tmp);
17900 emit_move_insn (dest, src);
17901 emit_label (label);
17902 LABEL_NUSES (label) = 1;
17907 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17909 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17910 rtx count, int max_size)
17913 expand_simple_binop (counter_mode (count), AND, count,
17914 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17915 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17916 gen_lowpart (QImode, value), count, QImode,
17920 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17922 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17926 if (CONST_INT_P (count))
17928 HOST_WIDE_INT countval = INTVAL (count);
17931 if ((countval & 0x10) && max_size > 16)
17935 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17936 emit_insn (gen_strset (destptr, dest, value));
17937 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17938 emit_insn (gen_strset (destptr, dest, value));
17941 gcc_unreachable ();
17944 if ((countval & 0x08) && max_size > 8)
17948 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17949 emit_insn (gen_strset (destptr, dest, value));
17953 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17954 emit_insn (gen_strset (destptr, dest, value));
17955 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17956 emit_insn (gen_strset (destptr, dest, value));
17960 if ((countval & 0x04) && max_size > 4)
17962 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17963 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17966 if ((countval & 0x02) && max_size > 2)
17968 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17969 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17972 if ((countval & 0x01) && max_size > 1)
17974 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17975 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17982 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17987 rtx label = ix86_expand_aligntest (count, 16, true);
17990 dest = change_address (destmem, DImode, destptr);
17991 emit_insn (gen_strset (destptr, dest, value));
17992 emit_insn (gen_strset (destptr, dest, value));
17996 dest = change_address (destmem, SImode, destptr);
17997 emit_insn (gen_strset (destptr, dest, value));
17998 emit_insn (gen_strset (destptr, dest, value));
17999 emit_insn (gen_strset (destptr, dest, value));
18000 emit_insn (gen_strset (destptr, dest, value));
18002 emit_label (label);
18003 LABEL_NUSES (label) = 1;
18007 rtx label = ix86_expand_aligntest (count, 8, true);
18010 dest = change_address (destmem, DImode, destptr);
18011 emit_insn (gen_strset (destptr, dest, value));
18015 dest = change_address (destmem, SImode, destptr);
18016 emit_insn (gen_strset (destptr, dest, value));
18017 emit_insn (gen_strset (destptr, dest, value));
18019 emit_label (label);
18020 LABEL_NUSES (label) = 1;
18024 rtx label = ix86_expand_aligntest (count, 4, true);
18025 dest = change_address (destmem, SImode, destptr);
18026 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
18027 emit_label (label);
18028 LABEL_NUSES (label) = 1;
18032 rtx label = ix86_expand_aligntest (count, 2, true);
18033 dest = change_address (destmem, HImode, destptr);
18034 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
18035 emit_label (label);
18036 LABEL_NUSES (label) = 1;
18040 rtx label = ix86_expand_aligntest (count, 1, true);
18041 dest = change_address (destmem, QImode, destptr);
18042 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
18043 emit_label (label);
18044 LABEL_NUSES (label) = 1;
18048 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
18049 DESIRED_ALIGNMENT. */
18051 expand_movmem_prologue (rtx destmem, rtx srcmem,
18052 rtx destptr, rtx srcptr, rtx count,
18053 int align, int desired_alignment)
18055 if (align <= 1 && desired_alignment > 1)
18057 rtx label = ix86_expand_aligntest (destptr, 1, false);
18058 srcmem = change_address (srcmem, QImode, srcptr);
18059 destmem = change_address (destmem, QImode, destptr);
18060 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
18061 ix86_adjust_counter (count, 1);
18062 emit_label (label);
18063 LABEL_NUSES (label) = 1;
18065 if (align <= 2 && desired_alignment > 2)
18067 rtx label = ix86_expand_aligntest (destptr, 2, false);
18068 srcmem = change_address (srcmem, HImode, srcptr);
18069 destmem = change_address (destmem, HImode, destptr);
18070 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
18071 ix86_adjust_counter (count, 2);
18072 emit_label (label);
18073 LABEL_NUSES (label) = 1;
18075 if (align <= 4 && desired_alignment > 4)
18077 rtx label = ix86_expand_aligntest (destptr, 4, false);
18078 srcmem = change_address (srcmem, SImode, srcptr);
18079 destmem = change_address (destmem, SImode, destptr);
18080 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
18081 ix86_adjust_counter (count, 4);
18082 emit_label (label);
18083 LABEL_NUSES (label) = 1;
18085 gcc_assert (desired_alignment <= 8);
18088 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
18089 ALIGN_BYTES is how many bytes need to be copied. */
18091 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
18092 int desired_align, int align_bytes)
18095 rtx src_size, dst_size;
18097 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
18098 if (src_align_bytes >= 0)
18099 src_align_bytes = desired_align - src_align_bytes;
18100 src_size = MEM_SIZE (src);
18101 dst_size = MEM_SIZE (dst);
18102 if (align_bytes & 1)
18104 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
18105 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
18107 emit_insn (gen_strmov (destreg, dst, srcreg, src));
18109 if (align_bytes & 2)
18111 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
18112 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
18113 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
18114 set_mem_align (dst, 2 * BITS_PER_UNIT);
18115 if (src_align_bytes >= 0
18116 && (src_align_bytes & 1) == (align_bytes & 1)
18117 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
18118 set_mem_align (src, 2 * BITS_PER_UNIT);
18120 emit_insn (gen_strmov (destreg, dst, srcreg, src));
18122 if (align_bytes & 4)
18124 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
18125 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
18126 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
18127 set_mem_align (dst, 4 * BITS_PER_UNIT);
18128 if (src_align_bytes >= 0)
18130 unsigned int src_align = 0;
18131 if ((src_align_bytes & 3) == (align_bytes & 3))
18133 else if ((src_align_bytes & 1) == (align_bytes & 1))
18135 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
18136 set_mem_align (src, src_align * BITS_PER_UNIT);
18139 emit_insn (gen_strmov (destreg, dst, srcreg, src));
18141 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
18142 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
18143 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
18144 set_mem_align (dst, desired_align * BITS_PER_UNIT);
18145 if (src_align_bytes >= 0)
18147 unsigned int src_align = 0;
18148 if ((src_align_bytes & 7) == (align_bytes & 7))
18150 else if ((src_align_bytes & 3) == (align_bytes & 3))
18152 else if ((src_align_bytes & 1) == (align_bytes & 1))
18154 if (src_align > (unsigned int) desired_align)
18155 src_align = desired_align;
18156 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
18157 set_mem_align (src, src_align * BITS_PER_UNIT);
18160 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
18162 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
18167 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
18168 DESIRED_ALIGNMENT. */
18170 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
18171 int align, int desired_alignment)
18173 if (align <= 1 && desired_alignment > 1)
18175 rtx label = ix86_expand_aligntest (destptr, 1, false);
18176 destmem = change_address (destmem, QImode, destptr);
18177 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
18178 ix86_adjust_counter (count, 1);
18179 emit_label (label);
18180 LABEL_NUSES (label) = 1;
18182 if (align <= 2 && desired_alignment > 2)
18184 rtx label = ix86_expand_aligntest (destptr, 2, false);
18185 destmem = change_address (destmem, HImode, destptr);
18186 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
18187 ix86_adjust_counter (count, 2);
18188 emit_label (label);
18189 LABEL_NUSES (label) = 1;
18191 if (align <= 4 && desired_alignment > 4)
18193 rtx label = ix86_expand_aligntest (destptr, 4, false);
18194 destmem = change_address (destmem, SImode, destptr);
18195 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
18196 ix86_adjust_counter (count, 4);
18197 emit_label (label);
18198 LABEL_NUSES (label) = 1;
18200 gcc_assert (desired_alignment <= 8);
18203 /* Set enough from DST to align DST known to by aligned by ALIGN to
18204 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
18206 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
18207 int desired_align, int align_bytes)
18210 rtx dst_size = MEM_SIZE (dst);
18211 if (align_bytes & 1)
18213 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
18215 emit_insn (gen_strset (destreg, dst,
18216 gen_lowpart (QImode, value)));
18218 if (align_bytes & 2)
18220 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
18221 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
18222 set_mem_align (dst, 2 * BITS_PER_UNIT);
18224 emit_insn (gen_strset (destreg, dst,
18225 gen_lowpart (HImode, value)));
18227 if (align_bytes & 4)
18229 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
18230 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
18231 set_mem_align (dst, 4 * BITS_PER_UNIT);
18233 emit_insn (gen_strset (destreg, dst,
18234 gen_lowpart (SImode, value)));
18236 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
18237 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
18238 set_mem_align (dst, desired_align * BITS_PER_UNIT);
18240 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
18244 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
18245 static enum stringop_alg
18246 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
18247 int *dynamic_check)
18249 const struct stringop_algs * algs;
18250 bool optimize_for_speed;
18251 /* Algorithms using the rep prefix want at least edi and ecx;
18252 additionally, memset wants eax and memcpy wants esi. Don't
18253 consider such algorithms if the user has appropriated those
18254 registers for their own purposes. */
18255 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
18257 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
18259 #define ALG_USABLE_P(alg) (rep_prefix_usable \
18260 || (alg != rep_prefix_1_byte \
18261 && alg != rep_prefix_4_byte \
18262 && alg != rep_prefix_8_byte))
18263 const struct processor_costs *cost;
18265 /* Even if the string operation call is cold, we still might spend a lot
18266 of time processing large blocks. */
18267 if (optimize_function_for_size_p (cfun)
18268 || (optimize_insn_for_size_p ()
18269 && expected_size != -1 && expected_size < 256))
18270 optimize_for_speed = false;
18272 optimize_for_speed = true;
18274 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
18276 *dynamic_check = -1;
18278 algs = &cost->memset[TARGET_64BIT != 0];
18280 algs = &cost->memcpy[TARGET_64BIT != 0];
18281 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
18282 return stringop_alg;
18283 /* rep; movq or rep; movl is the smallest variant. */
18284 else if (!optimize_for_speed)
18286 if (!count || (count & 3))
18287 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
18289 return rep_prefix_usable ? rep_prefix_4_byte : loop;
18291 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
18293 else if (expected_size != -1 && expected_size < 4)
18294 return loop_1_byte;
18295 else if (expected_size != -1)
18298 enum stringop_alg alg = libcall;
18299 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18301 /* We get here if the algorithms that were not libcall-based
18302 were rep-prefix based and we are unable to use rep prefixes
18303 based on global register usage. Break out of the loop and
18304 use the heuristic below. */
18305 if (algs->size[i].max == 0)
18307 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
18309 enum stringop_alg candidate = algs->size[i].alg;
18311 if (candidate != libcall && ALG_USABLE_P (candidate))
18313 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18314 last non-libcall inline algorithm. */
18315 if (TARGET_INLINE_ALL_STRINGOPS)
18317 /* When the current size is best to be copied by a libcall,
18318 but we are still forced to inline, run the heuristic below
18319 that will pick code for medium sized blocks. */
18320 if (alg != libcall)
18324 else if (ALG_USABLE_P (candidate))
18328 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
18330 /* When asked to inline the call anyway, try to pick meaningful choice.
18331 We look for maximal size of block that is faster to copy by hand and
18332 take blocks of at most of that size guessing that average size will
18333 be roughly half of the block.
18335 If this turns out to be bad, we might simply specify the preferred
18336 choice in ix86_costs. */
18337 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18338 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
18341 enum stringop_alg alg;
18343 bool any_alg_usable_p = true;
18345 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18347 enum stringop_alg candidate = algs->size[i].alg;
18348 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
18350 if (candidate != libcall && candidate
18351 && ALG_USABLE_P (candidate))
18352 max = algs->size[i].max;
18354 /* If there aren't any usable algorithms, then recursing on
18355 smaller sizes isn't going to find anything. Just return the
18356 simple byte-at-a-time copy loop. */
18357 if (!any_alg_usable_p)
18359 /* Pick something reasonable. */
18360 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18361 *dynamic_check = 128;
18362 return loop_1_byte;
18366 alg = decide_alg (count, max / 2, memset, dynamic_check);
18367 gcc_assert (*dynamic_check == -1);
18368 gcc_assert (alg != libcall);
18369 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18370 *dynamic_check = max;
18373 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
18374 #undef ALG_USABLE_P
18377 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18378 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18380 decide_alignment (int align,
18381 enum stringop_alg alg,
18384 int desired_align = 0;
18388 gcc_unreachable ();
18390 case unrolled_loop:
18391 desired_align = GET_MODE_SIZE (Pmode);
18393 case rep_prefix_8_byte:
18396 case rep_prefix_4_byte:
18397 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18398 copying whole cacheline at once. */
18399 if (TARGET_PENTIUMPRO)
18404 case rep_prefix_1_byte:
18405 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18406 copying whole cacheline at once. */
18407 if (TARGET_PENTIUMPRO)
18421 if (desired_align < align)
18422 desired_align = align;
18423 if (expected_size != -1 && expected_size < 4)
18424 desired_align = align;
18425 return desired_align;
18428 /* Return the smallest power of 2 greater than VAL. */
18430 smallest_pow2_greater_than (int val)
18438 /* Expand string move (memcpy) operation. Use i386 string operations when
18439 profitable. expand_setmem contains similar code. The code depends upon
18440 architecture, block size and alignment, but always has the same
18443 1) Prologue guard: Conditional that jumps up to epilogues for small
18444 blocks that can be handled by epilogue alone. This is faster but
18445 also needed for correctness, since prologue assume the block is larger
18446 than the desired alignment.
18448 Optional dynamic check for size and libcall for large
18449 blocks is emitted here too, with -minline-stringops-dynamically.
18451 2) Prologue: copy first few bytes in order to get destination aligned
18452 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18453 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18454 We emit either a jump tree on power of two sized blocks, or a byte loop.
18456 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18457 with specified algorithm.
18459 4) Epilogue: code copying tail of the block that is too small to be
18460 handled by main body (or up to size guarded by prologue guard). */
18463 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
18464 rtx expected_align_exp, rtx expected_size_exp)
18470 rtx jump_around_label = NULL;
18471 HOST_WIDE_INT align = 1;
18472 unsigned HOST_WIDE_INT count = 0;
18473 HOST_WIDE_INT expected_size = -1;
18474 int size_needed = 0, epilogue_size_needed;
18475 int desired_align = 0, align_bytes = 0;
18476 enum stringop_alg alg;
18478 bool need_zero_guard = false;
18480 if (CONST_INT_P (align_exp))
18481 align = INTVAL (align_exp);
18482 /* i386 can do misaligned access on reasonably increased cost. */
18483 if (CONST_INT_P (expected_align_exp)
18484 && INTVAL (expected_align_exp) > align)
18485 align = INTVAL (expected_align_exp);
18486 /* ALIGN is the minimum of destination and source alignment, but we care here
18487 just about destination alignment. */
18488 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
18489 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
18491 if (CONST_INT_P (count_exp))
18492 count = expected_size = INTVAL (count_exp);
18493 if (CONST_INT_P (expected_size_exp) && count == 0)
18494 expected_size = INTVAL (expected_size_exp);
18496 /* Make sure we don't need to care about overflow later on. */
18497 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18500 /* Step 0: Decide on preferred algorithm, desired alignment and
18501 size of chunks to be copied by main loop. */
18503 alg = decide_alg (count, expected_size, false, &dynamic_check);
18504 desired_align = decide_alignment (align, alg, expected_size);
18506 if (!TARGET_ALIGN_STRINGOPS)
18507 align = desired_align;
18509 if (alg == libcall)
18511 gcc_assert (alg != no_stringop);
18513 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18514 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18515 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18520 gcc_unreachable ();
18522 need_zero_guard = true;
18523 size_needed = GET_MODE_SIZE (Pmode);
18525 case unrolled_loop:
18526 need_zero_guard = true;
18527 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18529 case rep_prefix_8_byte:
18532 case rep_prefix_4_byte:
18535 case rep_prefix_1_byte:
18539 need_zero_guard = true;
18544 epilogue_size_needed = size_needed;
18546 /* Step 1: Prologue guard. */
18548 /* Alignment code needs count to be in register. */
18549 if (CONST_INT_P (count_exp) && desired_align > align)
18551 if (INTVAL (count_exp) > desired_align
18552 && INTVAL (count_exp) > size_needed)
18555 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18556 if (align_bytes <= 0)
18559 align_bytes = desired_align - align_bytes;
18561 if (align_bytes == 0)
18562 count_exp = force_reg (counter_mode (count_exp), count_exp);
18564 gcc_assert (desired_align >= 1 && align >= 1);
18566 /* Ensure that alignment prologue won't copy past end of block. */
18567 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18569 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18570 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18571 Make sure it is power of 2. */
18572 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18576 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18578 /* If main algorithm works on QImode, no epilogue is needed.
18579 For small sizes just don't align anything. */
18580 if (size_needed == 1)
18581 desired_align = align;
18588 label = gen_label_rtx ();
18589 emit_cmp_and_jump_insns (count_exp,
18590 GEN_INT (epilogue_size_needed),
18591 LTU, 0, counter_mode (count_exp), 1, label);
18592 if (expected_size == -1 || expected_size < epilogue_size_needed)
18593 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18595 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18599 /* Emit code to decide on runtime whether library call or inline should be
18601 if (dynamic_check != -1)
18603 if (CONST_INT_P (count_exp))
18605 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18607 emit_block_move_via_libcall (dst, src, count_exp, false);
18608 count_exp = const0_rtx;
18614 rtx hot_label = gen_label_rtx ();
18615 jump_around_label = gen_label_rtx ();
18616 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18617 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18618 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18619 emit_block_move_via_libcall (dst, src, count_exp, false);
18620 emit_jump (jump_around_label);
18621 emit_label (hot_label);
18625 /* Step 2: Alignment prologue. */
18627 if (desired_align > align)
18629 if (align_bytes == 0)
18631 /* Except for the first move in epilogue, we no longer know
18632 constant offset in aliasing info. It don't seems to worth
18633 the pain to maintain it for the first move, so throw away
18635 src = change_address (src, BLKmode, srcreg);
18636 dst = change_address (dst, BLKmode, destreg);
18637 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18642 /* If we know how many bytes need to be stored before dst is
18643 sufficiently aligned, maintain aliasing info accurately. */
18644 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18645 desired_align, align_bytes);
18646 count_exp = plus_constant (count_exp, -align_bytes);
18647 count -= align_bytes;
18649 if (need_zero_guard
18650 && (count < (unsigned HOST_WIDE_INT) size_needed
18651 || (align_bytes == 0
18652 && count < ((unsigned HOST_WIDE_INT) size_needed
18653 + desired_align - align))))
18655 /* It is possible that we copied enough so the main loop will not
18657 gcc_assert (size_needed > 1);
18658 if (label == NULL_RTX)
18659 label = gen_label_rtx ();
18660 emit_cmp_and_jump_insns (count_exp,
18661 GEN_INT (size_needed),
18662 LTU, 0, counter_mode (count_exp), 1, label);
18663 if (expected_size == -1
18664 || expected_size < (desired_align - align) / 2 + size_needed)
18665 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18667 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18670 if (label && size_needed == 1)
18672 emit_label (label);
18673 LABEL_NUSES (label) = 1;
18675 epilogue_size_needed = 1;
18677 else if (label == NULL_RTX)
18678 epilogue_size_needed = size_needed;
18680 /* Step 3: Main loop. */
18686 gcc_unreachable ();
18688 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18689 count_exp, QImode, 1, expected_size);
18692 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18693 count_exp, Pmode, 1, expected_size);
18695 case unrolled_loop:
18696 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18697 registers for 4 temporaries anyway. */
18698 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18699 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18702 case rep_prefix_8_byte:
18703 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18706 case rep_prefix_4_byte:
18707 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18710 case rep_prefix_1_byte:
18711 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18715 /* Adjust properly the offset of src and dest memory for aliasing. */
18716 if (CONST_INT_P (count_exp))
18718 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18719 (count / size_needed) * size_needed);
18720 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18721 (count / size_needed) * size_needed);
18725 src = change_address (src, BLKmode, srcreg);
18726 dst = change_address (dst, BLKmode, destreg);
18729 /* Step 4: Epilogue to copy the remaining bytes. */
18733 /* When the main loop is done, COUNT_EXP might hold original count,
18734 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18735 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18736 bytes. Compensate if needed. */
18738 if (size_needed < epilogue_size_needed)
18741 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18742 GEN_INT (size_needed - 1), count_exp, 1,
18744 if (tmp != count_exp)
18745 emit_move_insn (count_exp, tmp);
18747 emit_label (label);
18748 LABEL_NUSES (label) = 1;
18751 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18752 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18753 epilogue_size_needed);
18754 if (jump_around_label)
18755 emit_label (jump_around_label);
18759 /* Helper function for memcpy. For QImode value 0xXY produce
18760 0xXYXYXYXY of wide specified by MODE. This is essentially
18761 a * 0x10101010, but we can do slightly better than
18762 synth_mult by unwinding the sequence by hand on CPUs with
18765 promote_duplicated_reg (enum machine_mode mode, rtx val)
18767 enum machine_mode valmode = GET_MODE (val);
18769 int nops = mode == DImode ? 3 : 2;
18771 gcc_assert (mode == SImode || mode == DImode);
18772 if (val == const0_rtx)
18773 return copy_to_mode_reg (mode, const0_rtx);
18774 if (CONST_INT_P (val))
18776 HOST_WIDE_INT v = INTVAL (val) & 255;
18780 if (mode == DImode)
18781 v |= (v << 16) << 16;
18782 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18785 if (valmode == VOIDmode)
18787 if (valmode != QImode)
18788 val = gen_lowpart (QImode, val);
18789 if (mode == QImode)
18791 if (!TARGET_PARTIAL_REG_STALL)
18793 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18794 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18795 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18796 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18798 rtx reg = convert_modes (mode, QImode, val, true);
18799 tmp = promote_duplicated_reg (mode, const1_rtx);
18800 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18805 rtx reg = convert_modes (mode, QImode, val, true);
18807 if (!TARGET_PARTIAL_REG_STALL)
18808 if (mode == SImode)
18809 emit_insn (gen_movsi_insv_1 (reg, reg));
18811 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18814 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18815 NULL, 1, OPTAB_DIRECT);
18817 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18819 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18820 NULL, 1, OPTAB_DIRECT);
18821 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18822 if (mode == SImode)
18824 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18825 NULL, 1, OPTAB_DIRECT);
18826 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18831 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18832 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18833 alignment from ALIGN to DESIRED_ALIGN. */
18835 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18840 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18841 promoted_val = promote_duplicated_reg (DImode, val);
18842 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18843 promoted_val = promote_duplicated_reg (SImode, val);
18844 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18845 promoted_val = promote_duplicated_reg (HImode, val);
18847 promoted_val = val;
18849 return promoted_val;
18852 /* Expand string clear operation (bzero). Use i386 string operations when
18853 profitable. See expand_movmem comment for explanation of individual
18854 steps performed. */
18856 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18857 rtx expected_align_exp, rtx expected_size_exp)
18862 rtx jump_around_label = NULL;
18863 HOST_WIDE_INT align = 1;
18864 unsigned HOST_WIDE_INT count = 0;
18865 HOST_WIDE_INT expected_size = -1;
18866 int size_needed = 0, epilogue_size_needed;
18867 int desired_align = 0, align_bytes = 0;
18868 enum stringop_alg alg;
18869 rtx promoted_val = NULL;
18870 bool force_loopy_epilogue = false;
18872 bool need_zero_guard = false;
18874 if (CONST_INT_P (align_exp))
18875 align = INTVAL (align_exp);
18876 /* i386 can do misaligned access on reasonably increased cost. */
18877 if (CONST_INT_P (expected_align_exp)
18878 && INTVAL (expected_align_exp) > align)
18879 align = INTVAL (expected_align_exp);
18880 if (CONST_INT_P (count_exp))
18881 count = expected_size = INTVAL (count_exp);
18882 if (CONST_INT_P (expected_size_exp) && count == 0)
18883 expected_size = INTVAL (expected_size_exp);
18885 /* Make sure we don't need to care about overflow later on. */
18886 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18889 /* Step 0: Decide on preferred algorithm, desired alignment and
18890 size of chunks to be copied by main loop. */
18892 alg = decide_alg (count, expected_size, true, &dynamic_check);
18893 desired_align = decide_alignment (align, alg, expected_size);
18895 if (!TARGET_ALIGN_STRINGOPS)
18896 align = desired_align;
18898 if (alg == libcall)
18900 gcc_assert (alg != no_stringop);
18902 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18903 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18908 gcc_unreachable ();
18910 need_zero_guard = true;
18911 size_needed = GET_MODE_SIZE (Pmode);
18913 case unrolled_loop:
18914 need_zero_guard = true;
18915 size_needed = GET_MODE_SIZE (Pmode) * 4;
18917 case rep_prefix_8_byte:
18920 case rep_prefix_4_byte:
18923 case rep_prefix_1_byte:
18927 need_zero_guard = true;
18931 epilogue_size_needed = size_needed;
18933 /* Step 1: Prologue guard. */
18935 /* Alignment code needs count to be in register. */
18936 if (CONST_INT_P (count_exp) && desired_align > align)
18938 if (INTVAL (count_exp) > desired_align
18939 && INTVAL (count_exp) > size_needed)
18942 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18943 if (align_bytes <= 0)
18946 align_bytes = desired_align - align_bytes;
18948 if (align_bytes == 0)
18950 enum machine_mode mode = SImode;
18951 if (TARGET_64BIT && (count & ~0xffffffff))
18953 count_exp = force_reg (mode, count_exp);
18956 /* Do the cheap promotion to allow better CSE across the
18957 main loop and epilogue (ie one load of the big constant in the
18958 front of all code. */
18959 if (CONST_INT_P (val_exp))
18960 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18961 desired_align, align);
18962 /* Ensure that alignment prologue won't copy past end of block. */
18963 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18965 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18966 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18967 Make sure it is power of 2. */
18968 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18970 /* To improve performance of small blocks, we jump around the VAL
18971 promoting mode. This mean that if the promoted VAL is not constant,
18972 we might not use it in the epilogue and have to use byte
18974 if (epilogue_size_needed > 2 && !promoted_val)
18975 force_loopy_epilogue = true;
18978 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18980 /* If main algorithm works on QImode, no epilogue is needed.
18981 For small sizes just don't align anything. */
18982 if (size_needed == 1)
18983 desired_align = align;
18990 label = gen_label_rtx ();
18991 emit_cmp_and_jump_insns (count_exp,
18992 GEN_INT (epilogue_size_needed),
18993 LTU, 0, counter_mode (count_exp), 1, label);
18994 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18995 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18997 predict_jump (REG_BR_PROB_BASE * 20 / 100);
19000 if (dynamic_check != -1)
19002 rtx hot_label = gen_label_rtx ();
19003 jump_around_label = gen_label_rtx ();
19004 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
19005 LEU, 0, counter_mode (count_exp), 1, hot_label);
19006 predict_jump (REG_BR_PROB_BASE * 90 / 100);
19007 set_storage_via_libcall (dst, count_exp, val_exp, false);
19008 emit_jump (jump_around_label);
19009 emit_label (hot_label);
19012 /* Step 2: Alignment prologue. */
19014 /* Do the expensive promotion once we branched off the small blocks. */
19016 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
19017 desired_align, align);
19018 gcc_assert (desired_align >= 1 && align >= 1);
19020 if (desired_align > align)
19022 if (align_bytes == 0)
19024 /* Except for the first move in epilogue, we no longer know
19025 constant offset in aliasing info. It don't seems to worth
19026 the pain to maintain it for the first move, so throw away
19028 dst = change_address (dst, BLKmode, destreg);
19029 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
19034 /* If we know how many bytes need to be stored before dst is
19035 sufficiently aligned, maintain aliasing info accurately. */
19036 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
19037 desired_align, align_bytes);
19038 count_exp = plus_constant (count_exp, -align_bytes);
19039 count -= align_bytes;
19041 if (need_zero_guard
19042 && (count < (unsigned HOST_WIDE_INT) size_needed
19043 || (align_bytes == 0
19044 && count < ((unsigned HOST_WIDE_INT) size_needed
19045 + desired_align - align))))
19047 /* It is possible that we copied enough so the main loop will not
19049 gcc_assert (size_needed > 1);
19050 if (label == NULL_RTX)
19051 label = gen_label_rtx ();
19052 emit_cmp_and_jump_insns (count_exp,
19053 GEN_INT (size_needed),
19054 LTU, 0, counter_mode (count_exp), 1, label);
19055 if (expected_size == -1
19056 || expected_size < (desired_align - align) / 2 + size_needed)
19057 predict_jump (REG_BR_PROB_BASE * 20 / 100);
19059 predict_jump (REG_BR_PROB_BASE * 60 / 100);
19062 if (label && size_needed == 1)
19064 emit_label (label);
19065 LABEL_NUSES (label) = 1;
19067 promoted_val = val_exp;
19068 epilogue_size_needed = 1;
19070 else if (label == NULL_RTX)
19071 epilogue_size_needed = size_needed;
19073 /* Step 3: Main loop. */
19079 gcc_unreachable ();
19081 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
19082 count_exp, QImode, 1, expected_size);
19085 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
19086 count_exp, Pmode, 1, expected_size);
19088 case unrolled_loop:
19089 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
19090 count_exp, Pmode, 4, expected_size);
19092 case rep_prefix_8_byte:
19093 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
19096 case rep_prefix_4_byte:
19097 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
19100 case rep_prefix_1_byte:
19101 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
19105 /* Adjust properly the offset of src and dest memory for aliasing. */
19106 if (CONST_INT_P (count_exp))
19107 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
19108 (count / size_needed) * size_needed);
19110 dst = change_address (dst, BLKmode, destreg);
19112 /* Step 4: Epilogue to copy the remaining bytes. */
19116 /* When the main loop is done, COUNT_EXP might hold original count,
19117 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
19118 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
19119 bytes. Compensate if needed. */
19121 if (size_needed < epilogue_size_needed)
19124 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
19125 GEN_INT (size_needed - 1), count_exp, 1,
19127 if (tmp != count_exp)
19128 emit_move_insn (count_exp, tmp);
19130 emit_label (label);
19131 LABEL_NUSES (label) = 1;
19134 if (count_exp != const0_rtx && epilogue_size_needed > 1)
19136 if (force_loopy_epilogue)
19137 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
19138 epilogue_size_needed);
19140 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
19141 epilogue_size_needed);
19143 if (jump_around_label)
19144 emit_label (jump_around_label);
19148 /* Expand the appropriate insns for doing strlen if not just doing
19151 out = result, initialized with the start address
19152 align_rtx = alignment of the address.
19153 scratch = scratch register, initialized with the startaddress when
19154 not aligned, otherwise undefined
19156 This is just the body. It needs the initializations mentioned above and
19157 some address computing at the end. These things are done in i386.md. */
19160 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
19164 rtx align_2_label = NULL_RTX;
19165 rtx align_3_label = NULL_RTX;
19166 rtx align_4_label = gen_label_rtx ();
19167 rtx end_0_label = gen_label_rtx ();
19169 rtx tmpreg = gen_reg_rtx (SImode);
19170 rtx scratch = gen_reg_rtx (SImode);
19174 if (CONST_INT_P (align_rtx))
19175 align = INTVAL (align_rtx);
19177 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
19179 /* Is there a known alignment and is it less than 4? */
19182 rtx scratch1 = gen_reg_rtx (Pmode);
19183 emit_move_insn (scratch1, out);
19184 /* Is there a known alignment and is it not 2? */
19187 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
19188 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
19190 /* Leave just the 3 lower bits. */
19191 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
19192 NULL_RTX, 0, OPTAB_WIDEN);
19194 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
19195 Pmode, 1, align_4_label);
19196 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
19197 Pmode, 1, align_2_label);
19198 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
19199 Pmode, 1, align_3_label);
19203 /* Since the alignment is 2, we have to check 2 or 0 bytes;
19204 check if is aligned to 4 - byte. */
19206 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
19207 NULL_RTX, 0, OPTAB_WIDEN);
19209 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
19210 Pmode, 1, align_4_label);
19213 mem = change_address (src, QImode, out);
19215 /* Now compare the bytes. */
19217 /* Compare the first n unaligned byte on a byte per byte basis. */
19218 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
19219 QImode, 1, end_0_label);
19221 /* Increment the address. */
19222 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
19224 /* Not needed with an alignment of 2 */
19227 emit_label (align_2_label);
19229 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
19232 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
19234 emit_label (align_3_label);
19237 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
19240 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
19243 /* Generate loop to check 4 bytes at a time. It is not a good idea to
19244 align this loop. It gives only huge programs, but does not help to
19246 emit_label (align_4_label);
19248 mem = change_address (src, SImode, out);
19249 emit_move_insn (scratch, mem);
19250 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
19252 /* This formula yields a nonzero result iff one of the bytes is zero.
19253 This saves three branches inside loop and many cycles. */
19255 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
19256 emit_insn (gen_one_cmplsi2 (scratch, scratch));
19257 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
19258 emit_insn (gen_andsi3 (tmpreg, tmpreg,
19259 gen_int_mode (0x80808080, SImode)));
19260 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
19265 rtx reg = gen_reg_rtx (SImode);
19266 rtx reg2 = gen_reg_rtx (Pmode);
19267 emit_move_insn (reg, tmpreg);
19268 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
19270 /* If zero is not in the first two bytes, move two bytes forward. */
19271 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
19272 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
19273 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
19274 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
19275 gen_rtx_IF_THEN_ELSE (SImode, tmp,
19278 /* Emit lea manually to avoid clobbering of flags. */
19279 emit_insn (gen_rtx_SET (SImode, reg2,
19280 gen_rtx_PLUS (Pmode, out, const2_rtx)));
19282 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
19283 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
19284 emit_insn (gen_rtx_SET (VOIDmode, out,
19285 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
19292 rtx end_2_label = gen_label_rtx ();
19293 /* Is zero in the first two bytes? */
19295 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
19296 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
19297 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
19298 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
19299 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
19301 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
19302 JUMP_LABEL (tmp) = end_2_label;
19304 /* Not in the first two. Move two bytes forward. */
19305 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
19306 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
19308 emit_label (end_2_label);
19312 /* Avoid branch in fixing the byte. */
19313 tmpreg = gen_lowpart (QImode, tmpreg);
19314 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
19315 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
19316 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
19318 emit_label (end_0_label);
19321 /* Expand strlen. */
19324 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
19326 rtx addr, scratch1, scratch2, scratch3, scratch4;
19328 /* The generic case of strlen expander is long. Avoid it's
19329 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19331 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19332 && !TARGET_INLINE_ALL_STRINGOPS
19333 && !optimize_insn_for_size_p ()
19334 && (!CONST_INT_P (align) || INTVAL (align) < 4))
19337 addr = force_reg (Pmode, XEXP (src, 0));
19338 scratch1 = gen_reg_rtx (Pmode);
19340 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19341 && !optimize_insn_for_size_p ())
19343 /* Well it seems that some optimizer does not combine a call like
19344 foo(strlen(bar), strlen(bar));
19345 when the move and the subtraction is done here. It does calculate
19346 the length just once when these instructions are done inside of
19347 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19348 often used and I use one fewer register for the lifetime of
19349 output_strlen_unroll() this is better. */
19351 emit_move_insn (out, addr);
19353 ix86_expand_strlensi_unroll_1 (out, src, align);
19355 /* strlensi_unroll_1 returns the address of the zero at the end of
19356 the string, like memchr(), so compute the length by subtracting
19357 the start address. */
19358 emit_insn ((*ix86_gen_sub3) (out, out, addr));
19364 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19365 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
19368 scratch2 = gen_reg_rtx (Pmode);
19369 scratch3 = gen_reg_rtx (Pmode);
19370 scratch4 = force_reg (Pmode, constm1_rtx);
19372 emit_move_insn (scratch3, addr);
19373 eoschar = force_reg (QImode, eoschar);
19375 src = replace_equiv_address_nv (src, scratch3);
19377 /* If .md starts supporting :P, this can be done in .md. */
19378 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
19379 scratch4), UNSPEC_SCAS);
19380 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
19381 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
19382 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
19387 /* For given symbol (function) construct code to compute address of it's PLT
19388 entry in large x86-64 PIC model. */
19390 construct_plt_address (rtx symbol)
19392 rtx tmp = gen_reg_rtx (Pmode);
19393 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
19395 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
19396 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
19398 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
19399 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
19404 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
19406 rtx pop, int sibcall)
19408 rtx use = NULL, call;
19410 if (pop == const0_rtx)
19412 gcc_assert (!TARGET_64BIT || !pop);
19414 if (TARGET_MACHO && !TARGET_64BIT)
19417 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
19418 fnaddr = machopic_indirect_call_target (fnaddr);
19423 /* Static functions and indirect calls don't need the pic register. */
19424 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
19425 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19426 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
19427 use_reg (&use, pic_offset_table_rtx);
19430 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
19432 rtx al = gen_rtx_REG (QImode, AX_REG);
19433 emit_move_insn (al, callarg2);
19434 use_reg (&use, al);
19437 if (ix86_cmodel == CM_LARGE_PIC
19439 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19440 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
19441 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
19442 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
19444 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19445 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19447 if (sibcall && TARGET_64BIT
19448 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
19451 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19452 fnaddr = gen_rtx_REG (Pmode, R11_REG);
19453 emit_move_insn (fnaddr, addr);
19454 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19457 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
19459 call = gen_rtx_SET (VOIDmode, retval, call);
19462 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
19463 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
19464 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
19467 && ix86_cfun_abi () == MS_ABI
19468 && (!callarg2 || INTVAL (callarg2) != -2))
19470 /* We need to represent that SI and DI registers are clobbered
19472 static int clobbered_registers[] = {
19473 XMM6_REG, XMM7_REG, XMM8_REG,
19474 XMM9_REG, XMM10_REG, XMM11_REG,
19475 XMM12_REG, XMM13_REG, XMM14_REG,
19476 XMM15_REG, SI_REG, DI_REG
19479 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
19480 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
19481 UNSPEC_MS_TO_SYSV_CALL);
19485 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
19486 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
19489 (SSE_REGNO_P (clobbered_registers[i])
19491 clobbered_registers[i]));
19493 call = gen_rtx_PARALLEL (VOIDmode,
19494 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
19498 call = emit_call_insn (call);
19500 CALL_INSN_FUNCTION_USAGE (call) = use;
19504 /* Clear stack slot assignments remembered from previous functions.
19505 This is called from INIT_EXPANDERS once before RTL is emitted for each
19508 static struct machine_function *
19509 ix86_init_machine_status (void)
19511 struct machine_function *f;
19513 f = GGC_CNEW (struct machine_function);
19514 f->use_fast_prologue_epilogue_nregs = -1;
19515 f->tls_descriptor_call_expanded_p = 0;
19516 f->call_abi = ix86_abi;
19521 /* Return a MEM corresponding to a stack slot with mode MODE.
19522 Allocate a new slot if necessary.
19524 The RTL for a function can have several slots available: N is
19525 which slot to use. */
19528 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19530 struct stack_local_entry *s;
19532 gcc_assert (n < MAX_386_STACK_LOCALS);
19534 /* Virtual slot is valid only before vregs are instantiated. */
19535 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19537 for (s = ix86_stack_locals; s; s = s->next)
19538 if (s->mode == mode && s->n == n)
19539 return copy_rtx (s->rtl);
19541 s = (struct stack_local_entry *)
19542 ggc_alloc (sizeof (struct stack_local_entry));
19545 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19547 s->next = ix86_stack_locals;
19548 ix86_stack_locals = s;
19552 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19554 static GTY(()) rtx ix86_tls_symbol;
19556 ix86_tls_get_addr (void)
19559 if (!ix86_tls_symbol)
19561 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19562 (TARGET_ANY_GNU_TLS
19564 ? "___tls_get_addr"
19565 : "__tls_get_addr");
19568 return ix86_tls_symbol;
19571 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19573 static GTY(()) rtx ix86_tls_module_base_symbol;
19575 ix86_tls_module_base (void)
19578 if (!ix86_tls_module_base_symbol)
19580 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19581 "_TLS_MODULE_BASE_");
19582 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19583 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19586 return ix86_tls_module_base_symbol;
19589 /* Calculate the length of the memory address in the instruction
19590 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19593 memory_address_length (rtx addr)
19595 struct ix86_address parts;
19596 rtx base, index, disp;
19600 if (GET_CODE (addr) == PRE_DEC
19601 || GET_CODE (addr) == POST_INC
19602 || GET_CODE (addr) == PRE_MODIFY
19603 || GET_CODE (addr) == POST_MODIFY)
19606 ok = ix86_decompose_address (addr, &parts);
19609 if (parts.base && GET_CODE (parts.base) == SUBREG)
19610 parts.base = SUBREG_REG (parts.base);
19611 if (parts.index && GET_CODE (parts.index) == SUBREG)
19612 parts.index = SUBREG_REG (parts.index);
19615 index = parts.index;
19620 - esp as the base always wants an index,
19621 - ebp as the base always wants a displacement,
19622 - r12 as the base always wants an index,
19623 - r13 as the base always wants a displacement. */
19625 /* Register Indirect. */
19626 if (base && !index && !disp)
19628 /* esp (for its index) and ebp (for its displacement) need
19629 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19632 && (addr == arg_pointer_rtx
19633 || addr == frame_pointer_rtx
19634 || REGNO (addr) == SP_REG
19635 || REGNO (addr) == BP_REG
19636 || REGNO (addr) == R12_REG
19637 || REGNO (addr) == R13_REG))
19641 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19642 is not disp32, but disp32(%rip), so for disp32
19643 SIB byte is needed, unless print_operand_address
19644 optimizes it into disp32(%rip) or (%rip) is implied
19646 else if (disp && !base && !index)
19653 if (GET_CODE (disp) == CONST)
19654 symbol = XEXP (disp, 0);
19655 if (GET_CODE (symbol) == PLUS
19656 && CONST_INT_P (XEXP (symbol, 1)))
19657 symbol = XEXP (symbol, 0);
19659 if (GET_CODE (symbol) != LABEL_REF
19660 && (GET_CODE (symbol) != SYMBOL_REF
19661 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19662 && (GET_CODE (symbol) != UNSPEC
19663 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19664 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19671 /* Find the length of the displacement constant. */
19674 if (base && satisfies_constraint_K (disp))
19679 /* ebp always wants a displacement. Similarly r13. */
19680 else if (REG_P (base)
19681 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19684 /* An index requires the two-byte modrm form.... */
19686 /* ...like esp (or r12), which always wants an index. */
19687 || base == arg_pointer_rtx
19688 || base == frame_pointer_rtx
19690 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19707 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19708 is set, expect that insn have 8bit immediate alternative. */
19710 ix86_attr_length_immediate_default (rtx insn, int shortform)
19714 extract_insn_cached (insn);
19715 for (i = recog_data.n_operands - 1; i >= 0; --i)
19716 if (CONSTANT_P (recog_data.operand[i]))
19718 enum attr_mode mode = get_attr_mode (insn);
19721 if (shortform && CONST_INT_P (recog_data.operand[i]))
19723 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19730 ival = trunc_int_for_mode (ival, HImode);
19733 ival = trunc_int_for_mode (ival, SImode);
19738 if (IN_RANGE (ival, -128, 127))
19755 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19760 fatal_insn ("unknown insn mode", insn);
19765 /* Compute default value for "length_address" attribute. */
19767 ix86_attr_length_address_default (rtx insn)
19771 if (get_attr_type (insn) == TYPE_LEA)
19773 rtx set = PATTERN (insn), addr;
19775 if (GET_CODE (set) == PARALLEL)
19776 set = XVECEXP (set, 0, 0);
19778 gcc_assert (GET_CODE (set) == SET);
19780 addr = SET_SRC (set);
19781 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19783 if (GET_CODE (addr) == ZERO_EXTEND)
19784 addr = XEXP (addr, 0);
19785 if (GET_CODE (addr) == SUBREG)
19786 addr = SUBREG_REG (addr);
19789 return memory_address_length (addr);
19792 extract_insn_cached (insn);
19793 for (i = recog_data.n_operands - 1; i >= 0; --i)
19794 if (MEM_P (recog_data.operand[i]))
19796 constrain_operands_cached (reload_completed);
19797 if (which_alternative != -1)
19799 const char *constraints = recog_data.constraints[i];
19800 int alt = which_alternative;
19802 while (*constraints == '=' || *constraints == '+')
19805 while (*constraints++ != ',')
19807 /* Skip ignored operands. */
19808 if (*constraints == 'X')
19811 return memory_address_length (XEXP (recog_data.operand[i], 0));
19816 /* Compute default value for "length_vex" attribute. It includes
19817 2 or 3 byte VEX prefix and 1 opcode byte. */
19820 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19825 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19826 byte VEX prefix. */
19827 if (!has_0f_opcode || has_vex_w)
19830 /* We can always use 2 byte VEX prefix in 32bit. */
19834 extract_insn_cached (insn);
19836 for (i = recog_data.n_operands - 1; i >= 0; --i)
19837 if (REG_P (recog_data.operand[i]))
19839 /* REX.W bit uses 3 byte VEX prefix. */
19840 if (GET_MODE (recog_data.operand[i]) == DImode
19841 && GENERAL_REG_P (recog_data.operand[i]))
19846 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19847 if (MEM_P (recog_data.operand[i])
19848 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19855 /* Return the maximum number of instructions a cpu can issue. */
19858 ix86_issue_rate (void)
19862 case PROCESSOR_PENTIUM:
19863 case PROCESSOR_ATOM:
19867 case PROCESSOR_PENTIUMPRO:
19868 case PROCESSOR_PENTIUM4:
19869 case PROCESSOR_ATHLON:
19871 case PROCESSOR_AMDFAM10:
19872 case PROCESSOR_NOCONA:
19873 case PROCESSOR_GENERIC32:
19874 case PROCESSOR_GENERIC64:
19877 case PROCESSOR_CORE2:
19885 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19886 by DEP_INSN and nothing set by DEP_INSN. */
19889 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19893 /* Simplify the test for uninteresting insns. */
19894 if (insn_type != TYPE_SETCC
19895 && insn_type != TYPE_ICMOV
19896 && insn_type != TYPE_FCMOV
19897 && insn_type != TYPE_IBR)
19900 if ((set = single_set (dep_insn)) != 0)
19902 set = SET_DEST (set);
19905 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19906 && XVECLEN (PATTERN (dep_insn), 0) == 2
19907 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19908 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19910 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19911 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19916 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19919 /* This test is true if the dependent insn reads the flags but
19920 not any other potentially set register. */
19921 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19924 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19930 /* Return true iff USE_INSN has a memory address with operands set by
19934 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19937 extract_insn_cached (use_insn);
19938 for (i = recog_data.n_operands - 1; i >= 0; --i)
19939 if (MEM_P (recog_data.operand[i]))
19941 rtx addr = XEXP (recog_data.operand[i], 0);
19942 return modified_in_p (addr, set_insn) != 0;
19948 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19950 enum attr_type insn_type, dep_insn_type;
19951 enum attr_memory memory;
19953 int dep_insn_code_number;
19955 /* Anti and output dependencies have zero cost on all CPUs. */
19956 if (REG_NOTE_KIND (link) != 0)
19959 dep_insn_code_number = recog_memoized (dep_insn);
19961 /* If we can't recognize the insns, we can't really do anything. */
19962 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19965 insn_type = get_attr_type (insn);
19966 dep_insn_type = get_attr_type (dep_insn);
19970 case PROCESSOR_PENTIUM:
19971 /* Address Generation Interlock adds a cycle of latency. */
19972 if (insn_type == TYPE_LEA)
19974 rtx addr = PATTERN (insn);
19976 if (GET_CODE (addr) == PARALLEL)
19977 addr = XVECEXP (addr, 0, 0);
19979 gcc_assert (GET_CODE (addr) == SET);
19981 addr = SET_SRC (addr);
19982 if (modified_in_p (addr, dep_insn))
19985 else if (ix86_agi_dependent (dep_insn, insn))
19988 /* ??? Compares pair with jump/setcc. */
19989 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19992 /* Floating point stores require value to be ready one cycle earlier. */
19993 if (insn_type == TYPE_FMOV
19994 && get_attr_memory (insn) == MEMORY_STORE
19995 && !ix86_agi_dependent (dep_insn, insn))
19999 case PROCESSOR_PENTIUMPRO:
20000 memory = get_attr_memory (insn);
20002 /* INT->FP conversion is expensive. */
20003 if (get_attr_fp_int_src (dep_insn))
20006 /* There is one cycle extra latency between an FP op and a store. */
20007 if (insn_type == TYPE_FMOV
20008 && (set = single_set (dep_insn)) != NULL_RTX
20009 && (set2 = single_set (insn)) != NULL_RTX
20010 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
20011 && MEM_P (SET_DEST (set2)))
20014 /* Show ability of reorder buffer to hide latency of load by executing
20015 in parallel with previous instruction in case
20016 previous instruction is not needed to compute the address. */
20017 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
20018 && !ix86_agi_dependent (dep_insn, insn))
20020 /* Claim moves to take one cycle, as core can issue one load
20021 at time and the next load can start cycle later. */
20022 if (dep_insn_type == TYPE_IMOV
20023 || dep_insn_type == TYPE_FMOV)
20031 memory = get_attr_memory (insn);
20033 /* The esp dependency is resolved before the instruction is really
20035 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
20036 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
20039 /* INT->FP conversion is expensive. */
20040 if (get_attr_fp_int_src (dep_insn))
20043 /* Show ability of reorder buffer to hide latency of load by executing
20044 in parallel with previous instruction in case
20045 previous instruction is not needed to compute the address. */
20046 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
20047 && !ix86_agi_dependent (dep_insn, insn))
20049 /* Claim moves to take one cycle, as core can issue one load
20050 at time and the next load can start cycle later. */
20051 if (dep_insn_type == TYPE_IMOV
20052 || dep_insn_type == TYPE_FMOV)
20061 case PROCESSOR_ATHLON:
20063 case PROCESSOR_AMDFAM10:
20064 case PROCESSOR_ATOM:
20065 case PROCESSOR_GENERIC32:
20066 case PROCESSOR_GENERIC64:
20067 memory = get_attr_memory (insn);
20069 /* Show ability of reorder buffer to hide latency of load by executing
20070 in parallel with previous instruction in case
20071 previous instruction is not needed to compute the address. */
20072 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
20073 && !ix86_agi_dependent (dep_insn, insn))
20075 enum attr_unit unit = get_attr_unit (insn);
20078 /* Because of the difference between the length of integer and
20079 floating unit pipeline preparation stages, the memory operands
20080 for floating point are cheaper.
20082 ??? For Athlon it the difference is most probably 2. */
20083 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
20086 loadcost = TARGET_ATHLON ? 2 : 0;
20088 if (cost >= loadcost)
20101 /* How many alternative schedules to try. This should be as wide as the
20102 scheduling freedom in the DFA, but no wider. Making this value too
20103 large results extra work for the scheduler. */
20106 ia32_multipass_dfa_lookahead (void)
20110 case PROCESSOR_PENTIUM:
20113 case PROCESSOR_PENTIUMPRO:
20123 /* Compute the alignment given to a constant that is being placed in memory.
20124 EXP is the constant and ALIGN is the alignment that the object would
20126 The value of this function is used instead of that alignment to align
20130 ix86_constant_alignment (tree exp, int align)
20132 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
20133 || TREE_CODE (exp) == INTEGER_CST)
20135 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
20137 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
20140 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
20141 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
20142 return BITS_PER_WORD;
20147 /* Compute the alignment for a static variable.
20148 TYPE is the data type, and ALIGN is the alignment that
20149 the object would ordinarily have. The value of this function is used
20150 instead of that alignment to align the object. */
20153 ix86_data_alignment (tree type, int align)
20155 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
20157 if (AGGREGATE_TYPE_P (type)
20158 && TYPE_SIZE (type)
20159 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
20160 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
20161 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
20162 && align < max_align)
20165 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20166 to 16byte boundary. */
20169 if (AGGREGATE_TYPE_P (type)
20170 && TYPE_SIZE (type)
20171 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
20172 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
20173 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
20177 if (TREE_CODE (type) == ARRAY_TYPE)
20179 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
20181 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
20184 else if (TREE_CODE (type) == COMPLEX_TYPE)
20187 if (TYPE_MODE (type) == DCmode && align < 64)
20189 if ((TYPE_MODE (type) == XCmode
20190 || TYPE_MODE (type) == TCmode) && align < 128)
20193 else if ((TREE_CODE (type) == RECORD_TYPE
20194 || TREE_CODE (type) == UNION_TYPE
20195 || TREE_CODE (type) == QUAL_UNION_TYPE)
20196 && TYPE_FIELDS (type))
20198 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
20200 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
20203 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
20204 || TREE_CODE (type) == INTEGER_TYPE)
20206 if (TYPE_MODE (type) == DFmode && align < 64)
20208 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
20215 /* Compute the alignment for a local variable or a stack slot. EXP is
20216 the data type or decl itself, MODE is the widest mode available and
20217 ALIGN is the alignment that the object would ordinarily have. The
20218 value of this macro is used instead of that alignment to align the
20222 ix86_local_alignment (tree exp, enum machine_mode mode,
20223 unsigned int align)
20227 if (exp && DECL_P (exp))
20229 type = TREE_TYPE (exp);
20238 /* Don't do dynamic stack realignment for long long objects with
20239 -mpreferred-stack-boundary=2. */
20242 && ix86_preferred_stack_boundary < 64
20243 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
20244 && (!type || !TYPE_USER_ALIGN (type))
20245 && (!decl || !DECL_USER_ALIGN (decl)))
20248 /* If TYPE is NULL, we are allocating a stack slot for caller-save
20249 register in MODE. We will return the largest alignment of XF
20253 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
20254 align = GET_MODE_ALIGNMENT (DFmode);
20258 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20259 to 16byte boundary. */
20262 if (AGGREGATE_TYPE_P (type)
20263 && TYPE_SIZE (type)
20264 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
20265 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
20266 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
20269 if (TREE_CODE (type) == ARRAY_TYPE)
20271 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
20273 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
20276 else if (TREE_CODE (type) == COMPLEX_TYPE)
20278 if (TYPE_MODE (type) == DCmode && align < 64)
20280 if ((TYPE_MODE (type) == XCmode
20281 || TYPE_MODE (type) == TCmode) && align < 128)
20284 else if ((TREE_CODE (type) == RECORD_TYPE
20285 || TREE_CODE (type) == UNION_TYPE
20286 || TREE_CODE (type) == QUAL_UNION_TYPE)
20287 && TYPE_FIELDS (type))
20289 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
20291 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
20294 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
20295 || TREE_CODE (type) == INTEGER_TYPE)
20298 if (TYPE_MODE (type) == DFmode && align < 64)
20300 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
20306 /* Emit RTL insns to initialize the variable parts of a trampoline.
20307 FNADDR is an RTX for the address of the function's pure code.
20308 CXT is an RTX for the static chain value for the function. */
20310 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
20314 /* Compute offset from the end of the jmp to the target function. */
20315 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
20316 plus_constant (tramp, 10),
20317 NULL_RTX, 1, OPTAB_DIRECT);
20318 emit_move_insn (gen_rtx_MEM (QImode, tramp),
20319 gen_int_mode (0xb9, QImode));
20320 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
20321 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
20322 gen_int_mode (0xe9, QImode));
20323 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
20328 /* Try to load address using shorter movl instead of movabs.
20329 We may want to support movq for kernel mode, but kernel does not use
20330 trampolines at the moment. */
20331 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
20333 fnaddr = copy_to_mode_reg (DImode, fnaddr);
20334 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
20335 gen_int_mode (0xbb41, HImode));
20336 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
20337 gen_lowpart (SImode, fnaddr));
20342 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
20343 gen_int_mode (0xbb49, HImode));
20344 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
20348 /* Load static chain using movabs to r10. */
20349 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
20350 gen_int_mode (0xba49, HImode));
20351 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
20354 /* Jump to the r11 */
20355 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
20356 gen_int_mode (0xff49, HImode));
20357 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
20358 gen_int_mode (0xe3, QImode));
20360 gcc_assert (offset <= TRAMPOLINE_SIZE);
20363 #ifdef ENABLE_EXECUTE_STACK
20364 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
20365 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
20369 /* Codes for all the SSE/MMX builtins. */
20372 IX86_BUILTIN_ADDPS,
20373 IX86_BUILTIN_ADDSS,
20374 IX86_BUILTIN_DIVPS,
20375 IX86_BUILTIN_DIVSS,
20376 IX86_BUILTIN_MULPS,
20377 IX86_BUILTIN_MULSS,
20378 IX86_BUILTIN_SUBPS,
20379 IX86_BUILTIN_SUBSS,
20381 IX86_BUILTIN_CMPEQPS,
20382 IX86_BUILTIN_CMPLTPS,
20383 IX86_BUILTIN_CMPLEPS,
20384 IX86_BUILTIN_CMPGTPS,
20385 IX86_BUILTIN_CMPGEPS,
20386 IX86_BUILTIN_CMPNEQPS,
20387 IX86_BUILTIN_CMPNLTPS,
20388 IX86_BUILTIN_CMPNLEPS,
20389 IX86_BUILTIN_CMPNGTPS,
20390 IX86_BUILTIN_CMPNGEPS,
20391 IX86_BUILTIN_CMPORDPS,
20392 IX86_BUILTIN_CMPUNORDPS,
20393 IX86_BUILTIN_CMPEQSS,
20394 IX86_BUILTIN_CMPLTSS,
20395 IX86_BUILTIN_CMPLESS,
20396 IX86_BUILTIN_CMPNEQSS,
20397 IX86_BUILTIN_CMPNLTSS,
20398 IX86_BUILTIN_CMPNLESS,
20399 IX86_BUILTIN_CMPNGTSS,
20400 IX86_BUILTIN_CMPNGESS,
20401 IX86_BUILTIN_CMPORDSS,
20402 IX86_BUILTIN_CMPUNORDSS,
20404 IX86_BUILTIN_COMIEQSS,
20405 IX86_BUILTIN_COMILTSS,
20406 IX86_BUILTIN_COMILESS,
20407 IX86_BUILTIN_COMIGTSS,
20408 IX86_BUILTIN_COMIGESS,
20409 IX86_BUILTIN_COMINEQSS,
20410 IX86_BUILTIN_UCOMIEQSS,
20411 IX86_BUILTIN_UCOMILTSS,
20412 IX86_BUILTIN_UCOMILESS,
20413 IX86_BUILTIN_UCOMIGTSS,
20414 IX86_BUILTIN_UCOMIGESS,
20415 IX86_BUILTIN_UCOMINEQSS,
20417 IX86_BUILTIN_CVTPI2PS,
20418 IX86_BUILTIN_CVTPS2PI,
20419 IX86_BUILTIN_CVTSI2SS,
20420 IX86_BUILTIN_CVTSI642SS,
20421 IX86_BUILTIN_CVTSS2SI,
20422 IX86_BUILTIN_CVTSS2SI64,
20423 IX86_BUILTIN_CVTTPS2PI,
20424 IX86_BUILTIN_CVTTSS2SI,
20425 IX86_BUILTIN_CVTTSS2SI64,
20427 IX86_BUILTIN_MAXPS,
20428 IX86_BUILTIN_MAXSS,
20429 IX86_BUILTIN_MINPS,
20430 IX86_BUILTIN_MINSS,
20432 IX86_BUILTIN_LOADUPS,
20433 IX86_BUILTIN_STOREUPS,
20434 IX86_BUILTIN_MOVSS,
20436 IX86_BUILTIN_MOVHLPS,
20437 IX86_BUILTIN_MOVLHPS,
20438 IX86_BUILTIN_LOADHPS,
20439 IX86_BUILTIN_LOADLPS,
20440 IX86_BUILTIN_STOREHPS,
20441 IX86_BUILTIN_STORELPS,
20443 IX86_BUILTIN_MASKMOVQ,
20444 IX86_BUILTIN_MOVMSKPS,
20445 IX86_BUILTIN_PMOVMSKB,
20447 IX86_BUILTIN_MOVNTPS,
20448 IX86_BUILTIN_MOVNTQ,
20450 IX86_BUILTIN_LOADDQU,
20451 IX86_BUILTIN_STOREDQU,
20453 IX86_BUILTIN_PACKSSWB,
20454 IX86_BUILTIN_PACKSSDW,
20455 IX86_BUILTIN_PACKUSWB,
20457 IX86_BUILTIN_PADDB,
20458 IX86_BUILTIN_PADDW,
20459 IX86_BUILTIN_PADDD,
20460 IX86_BUILTIN_PADDQ,
20461 IX86_BUILTIN_PADDSB,
20462 IX86_BUILTIN_PADDSW,
20463 IX86_BUILTIN_PADDUSB,
20464 IX86_BUILTIN_PADDUSW,
20465 IX86_BUILTIN_PSUBB,
20466 IX86_BUILTIN_PSUBW,
20467 IX86_BUILTIN_PSUBD,
20468 IX86_BUILTIN_PSUBQ,
20469 IX86_BUILTIN_PSUBSB,
20470 IX86_BUILTIN_PSUBSW,
20471 IX86_BUILTIN_PSUBUSB,
20472 IX86_BUILTIN_PSUBUSW,
20475 IX86_BUILTIN_PANDN,
20479 IX86_BUILTIN_PAVGB,
20480 IX86_BUILTIN_PAVGW,
20482 IX86_BUILTIN_PCMPEQB,
20483 IX86_BUILTIN_PCMPEQW,
20484 IX86_BUILTIN_PCMPEQD,
20485 IX86_BUILTIN_PCMPGTB,
20486 IX86_BUILTIN_PCMPGTW,
20487 IX86_BUILTIN_PCMPGTD,
20489 IX86_BUILTIN_PMADDWD,
20491 IX86_BUILTIN_PMAXSW,
20492 IX86_BUILTIN_PMAXUB,
20493 IX86_BUILTIN_PMINSW,
20494 IX86_BUILTIN_PMINUB,
20496 IX86_BUILTIN_PMULHUW,
20497 IX86_BUILTIN_PMULHW,
20498 IX86_BUILTIN_PMULLW,
20500 IX86_BUILTIN_PSADBW,
20501 IX86_BUILTIN_PSHUFW,
20503 IX86_BUILTIN_PSLLW,
20504 IX86_BUILTIN_PSLLD,
20505 IX86_BUILTIN_PSLLQ,
20506 IX86_BUILTIN_PSRAW,
20507 IX86_BUILTIN_PSRAD,
20508 IX86_BUILTIN_PSRLW,
20509 IX86_BUILTIN_PSRLD,
20510 IX86_BUILTIN_PSRLQ,
20511 IX86_BUILTIN_PSLLWI,
20512 IX86_BUILTIN_PSLLDI,
20513 IX86_BUILTIN_PSLLQI,
20514 IX86_BUILTIN_PSRAWI,
20515 IX86_BUILTIN_PSRADI,
20516 IX86_BUILTIN_PSRLWI,
20517 IX86_BUILTIN_PSRLDI,
20518 IX86_BUILTIN_PSRLQI,
20520 IX86_BUILTIN_PUNPCKHBW,
20521 IX86_BUILTIN_PUNPCKHWD,
20522 IX86_BUILTIN_PUNPCKHDQ,
20523 IX86_BUILTIN_PUNPCKLBW,
20524 IX86_BUILTIN_PUNPCKLWD,
20525 IX86_BUILTIN_PUNPCKLDQ,
20527 IX86_BUILTIN_SHUFPS,
20529 IX86_BUILTIN_RCPPS,
20530 IX86_BUILTIN_RCPSS,
20531 IX86_BUILTIN_RSQRTPS,
20532 IX86_BUILTIN_RSQRTPS_NR,
20533 IX86_BUILTIN_RSQRTSS,
20534 IX86_BUILTIN_RSQRTF,
20535 IX86_BUILTIN_SQRTPS,
20536 IX86_BUILTIN_SQRTPS_NR,
20537 IX86_BUILTIN_SQRTSS,
20539 IX86_BUILTIN_UNPCKHPS,
20540 IX86_BUILTIN_UNPCKLPS,
20542 IX86_BUILTIN_ANDPS,
20543 IX86_BUILTIN_ANDNPS,
20545 IX86_BUILTIN_XORPS,
20548 IX86_BUILTIN_LDMXCSR,
20549 IX86_BUILTIN_STMXCSR,
20550 IX86_BUILTIN_SFENCE,
20552 /* 3DNow! Original */
20553 IX86_BUILTIN_FEMMS,
20554 IX86_BUILTIN_PAVGUSB,
20555 IX86_BUILTIN_PF2ID,
20556 IX86_BUILTIN_PFACC,
20557 IX86_BUILTIN_PFADD,
20558 IX86_BUILTIN_PFCMPEQ,
20559 IX86_BUILTIN_PFCMPGE,
20560 IX86_BUILTIN_PFCMPGT,
20561 IX86_BUILTIN_PFMAX,
20562 IX86_BUILTIN_PFMIN,
20563 IX86_BUILTIN_PFMUL,
20564 IX86_BUILTIN_PFRCP,
20565 IX86_BUILTIN_PFRCPIT1,
20566 IX86_BUILTIN_PFRCPIT2,
20567 IX86_BUILTIN_PFRSQIT1,
20568 IX86_BUILTIN_PFRSQRT,
20569 IX86_BUILTIN_PFSUB,
20570 IX86_BUILTIN_PFSUBR,
20571 IX86_BUILTIN_PI2FD,
20572 IX86_BUILTIN_PMULHRW,
20574 /* 3DNow! Athlon Extensions */
20575 IX86_BUILTIN_PF2IW,
20576 IX86_BUILTIN_PFNACC,
20577 IX86_BUILTIN_PFPNACC,
20578 IX86_BUILTIN_PI2FW,
20579 IX86_BUILTIN_PSWAPDSI,
20580 IX86_BUILTIN_PSWAPDSF,
20583 IX86_BUILTIN_ADDPD,
20584 IX86_BUILTIN_ADDSD,
20585 IX86_BUILTIN_DIVPD,
20586 IX86_BUILTIN_DIVSD,
20587 IX86_BUILTIN_MULPD,
20588 IX86_BUILTIN_MULSD,
20589 IX86_BUILTIN_SUBPD,
20590 IX86_BUILTIN_SUBSD,
20592 IX86_BUILTIN_CMPEQPD,
20593 IX86_BUILTIN_CMPLTPD,
20594 IX86_BUILTIN_CMPLEPD,
20595 IX86_BUILTIN_CMPGTPD,
20596 IX86_BUILTIN_CMPGEPD,
20597 IX86_BUILTIN_CMPNEQPD,
20598 IX86_BUILTIN_CMPNLTPD,
20599 IX86_BUILTIN_CMPNLEPD,
20600 IX86_BUILTIN_CMPNGTPD,
20601 IX86_BUILTIN_CMPNGEPD,
20602 IX86_BUILTIN_CMPORDPD,
20603 IX86_BUILTIN_CMPUNORDPD,
20604 IX86_BUILTIN_CMPEQSD,
20605 IX86_BUILTIN_CMPLTSD,
20606 IX86_BUILTIN_CMPLESD,
20607 IX86_BUILTIN_CMPNEQSD,
20608 IX86_BUILTIN_CMPNLTSD,
20609 IX86_BUILTIN_CMPNLESD,
20610 IX86_BUILTIN_CMPORDSD,
20611 IX86_BUILTIN_CMPUNORDSD,
20613 IX86_BUILTIN_COMIEQSD,
20614 IX86_BUILTIN_COMILTSD,
20615 IX86_BUILTIN_COMILESD,
20616 IX86_BUILTIN_COMIGTSD,
20617 IX86_BUILTIN_COMIGESD,
20618 IX86_BUILTIN_COMINEQSD,
20619 IX86_BUILTIN_UCOMIEQSD,
20620 IX86_BUILTIN_UCOMILTSD,
20621 IX86_BUILTIN_UCOMILESD,
20622 IX86_BUILTIN_UCOMIGTSD,
20623 IX86_BUILTIN_UCOMIGESD,
20624 IX86_BUILTIN_UCOMINEQSD,
20626 IX86_BUILTIN_MAXPD,
20627 IX86_BUILTIN_MAXSD,
20628 IX86_BUILTIN_MINPD,
20629 IX86_BUILTIN_MINSD,
20631 IX86_BUILTIN_ANDPD,
20632 IX86_BUILTIN_ANDNPD,
20634 IX86_BUILTIN_XORPD,
20636 IX86_BUILTIN_SQRTPD,
20637 IX86_BUILTIN_SQRTSD,
20639 IX86_BUILTIN_UNPCKHPD,
20640 IX86_BUILTIN_UNPCKLPD,
20642 IX86_BUILTIN_SHUFPD,
20644 IX86_BUILTIN_LOADUPD,
20645 IX86_BUILTIN_STOREUPD,
20646 IX86_BUILTIN_MOVSD,
20648 IX86_BUILTIN_LOADHPD,
20649 IX86_BUILTIN_LOADLPD,
20651 IX86_BUILTIN_CVTDQ2PD,
20652 IX86_BUILTIN_CVTDQ2PS,
20654 IX86_BUILTIN_CVTPD2DQ,
20655 IX86_BUILTIN_CVTPD2PI,
20656 IX86_BUILTIN_CVTPD2PS,
20657 IX86_BUILTIN_CVTTPD2DQ,
20658 IX86_BUILTIN_CVTTPD2PI,
20660 IX86_BUILTIN_CVTPI2PD,
20661 IX86_BUILTIN_CVTSI2SD,
20662 IX86_BUILTIN_CVTSI642SD,
20664 IX86_BUILTIN_CVTSD2SI,
20665 IX86_BUILTIN_CVTSD2SI64,
20666 IX86_BUILTIN_CVTSD2SS,
20667 IX86_BUILTIN_CVTSS2SD,
20668 IX86_BUILTIN_CVTTSD2SI,
20669 IX86_BUILTIN_CVTTSD2SI64,
20671 IX86_BUILTIN_CVTPS2DQ,
20672 IX86_BUILTIN_CVTPS2PD,
20673 IX86_BUILTIN_CVTTPS2DQ,
20675 IX86_BUILTIN_MOVNTI,
20676 IX86_BUILTIN_MOVNTPD,
20677 IX86_BUILTIN_MOVNTDQ,
20679 IX86_BUILTIN_MOVQ128,
20682 IX86_BUILTIN_MASKMOVDQU,
20683 IX86_BUILTIN_MOVMSKPD,
20684 IX86_BUILTIN_PMOVMSKB128,
20686 IX86_BUILTIN_PACKSSWB128,
20687 IX86_BUILTIN_PACKSSDW128,
20688 IX86_BUILTIN_PACKUSWB128,
20690 IX86_BUILTIN_PADDB128,
20691 IX86_BUILTIN_PADDW128,
20692 IX86_BUILTIN_PADDD128,
20693 IX86_BUILTIN_PADDQ128,
20694 IX86_BUILTIN_PADDSB128,
20695 IX86_BUILTIN_PADDSW128,
20696 IX86_BUILTIN_PADDUSB128,
20697 IX86_BUILTIN_PADDUSW128,
20698 IX86_BUILTIN_PSUBB128,
20699 IX86_BUILTIN_PSUBW128,
20700 IX86_BUILTIN_PSUBD128,
20701 IX86_BUILTIN_PSUBQ128,
20702 IX86_BUILTIN_PSUBSB128,
20703 IX86_BUILTIN_PSUBSW128,
20704 IX86_BUILTIN_PSUBUSB128,
20705 IX86_BUILTIN_PSUBUSW128,
20707 IX86_BUILTIN_PAND128,
20708 IX86_BUILTIN_PANDN128,
20709 IX86_BUILTIN_POR128,
20710 IX86_BUILTIN_PXOR128,
20712 IX86_BUILTIN_PAVGB128,
20713 IX86_BUILTIN_PAVGW128,
20715 IX86_BUILTIN_PCMPEQB128,
20716 IX86_BUILTIN_PCMPEQW128,
20717 IX86_BUILTIN_PCMPEQD128,
20718 IX86_BUILTIN_PCMPGTB128,
20719 IX86_BUILTIN_PCMPGTW128,
20720 IX86_BUILTIN_PCMPGTD128,
20722 IX86_BUILTIN_PMADDWD128,
20724 IX86_BUILTIN_PMAXSW128,
20725 IX86_BUILTIN_PMAXUB128,
20726 IX86_BUILTIN_PMINSW128,
20727 IX86_BUILTIN_PMINUB128,
20729 IX86_BUILTIN_PMULUDQ,
20730 IX86_BUILTIN_PMULUDQ128,
20731 IX86_BUILTIN_PMULHUW128,
20732 IX86_BUILTIN_PMULHW128,
20733 IX86_BUILTIN_PMULLW128,
20735 IX86_BUILTIN_PSADBW128,
20736 IX86_BUILTIN_PSHUFHW,
20737 IX86_BUILTIN_PSHUFLW,
20738 IX86_BUILTIN_PSHUFD,
20740 IX86_BUILTIN_PSLLDQI128,
20741 IX86_BUILTIN_PSLLWI128,
20742 IX86_BUILTIN_PSLLDI128,
20743 IX86_BUILTIN_PSLLQI128,
20744 IX86_BUILTIN_PSRAWI128,
20745 IX86_BUILTIN_PSRADI128,
20746 IX86_BUILTIN_PSRLDQI128,
20747 IX86_BUILTIN_PSRLWI128,
20748 IX86_BUILTIN_PSRLDI128,
20749 IX86_BUILTIN_PSRLQI128,
20751 IX86_BUILTIN_PSLLDQ128,
20752 IX86_BUILTIN_PSLLW128,
20753 IX86_BUILTIN_PSLLD128,
20754 IX86_BUILTIN_PSLLQ128,
20755 IX86_BUILTIN_PSRAW128,
20756 IX86_BUILTIN_PSRAD128,
20757 IX86_BUILTIN_PSRLW128,
20758 IX86_BUILTIN_PSRLD128,
20759 IX86_BUILTIN_PSRLQ128,
20761 IX86_BUILTIN_PUNPCKHBW128,
20762 IX86_BUILTIN_PUNPCKHWD128,
20763 IX86_BUILTIN_PUNPCKHDQ128,
20764 IX86_BUILTIN_PUNPCKHQDQ128,
20765 IX86_BUILTIN_PUNPCKLBW128,
20766 IX86_BUILTIN_PUNPCKLWD128,
20767 IX86_BUILTIN_PUNPCKLDQ128,
20768 IX86_BUILTIN_PUNPCKLQDQ128,
20770 IX86_BUILTIN_CLFLUSH,
20771 IX86_BUILTIN_MFENCE,
20772 IX86_BUILTIN_LFENCE,
20774 IX86_BUILTIN_BSRSI,
20775 IX86_BUILTIN_BSRDI,
20776 IX86_BUILTIN_RDPMC,
20777 IX86_BUILTIN_RDTSC,
20778 IX86_BUILTIN_RDTSCP,
20779 IX86_BUILTIN_ROLQI,
20780 IX86_BUILTIN_ROLHI,
20781 IX86_BUILTIN_RORQI,
20782 IX86_BUILTIN_RORHI,
20785 IX86_BUILTIN_ADDSUBPS,
20786 IX86_BUILTIN_HADDPS,
20787 IX86_BUILTIN_HSUBPS,
20788 IX86_BUILTIN_MOVSHDUP,
20789 IX86_BUILTIN_MOVSLDUP,
20790 IX86_BUILTIN_ADDSUBPD,
20791 IX86_BUILTIN_HADDPD,
20792 IX86_BUILTIN_HSUBPD,
20793 IX86_BUILTIN_LDDQU,
20795 IX86_BUILTIN_MONITOR,
20796 IX86_BUILTIN_MWAIT,
20799 IX86_BUILTIN_PHADDW,
20800 IX86_BUILTIN_PHADDD,
20801 IX86_BUILTIN_PHADDSW,
20802 IX86_BUILTIN_PHSUBW,
20803 IX86_BUILTIN_PHSUBD,
20804 IX86_BUILTIN_PHSUBSW,
20805 IX86_BUILTIN_PMADDUBSW,
20806 IX86_BUILTIN_PMULHRSW,
20807 IX86_BUILTIN_PSHUFB,
20808 IX86_BUILTIN_PSIGNB,
20809 IX86_BUILTIN_PSIGNW,
20810 IX86_BUILTIN_PSIGND,
20811 IX86_BUILTIN_PALIGNR,
20812 IX86_BUILTIN_PABSB,
20813 IX86_BUILTIN_PABSW,
20814 IX86_BUILTIN_PABSD,
20816 IX86_BUILTIN_PHADDW128,
20817 IX86_BUILTIN_PHADDD128,
20818 IX86_BUILTIN_PHADDSW128,
20819 IX86_BUILTIN_PHSUBW128,
20820 IX86_BUILTIN_PHSUBD128,
20821 IX86_BUILTIN_PHSUBSW128,
20822 IX86_BUILTIN_PMADDUBSW128,
20823 IX86_BUILTIN_PMULHRSW128,
20824 IX86_BUILTIN_PSHUFB128,
20825 IX86_BUILTIN_PSIGNB128,
20826 IX86_BUILTIN_PSIGNW128,
20827 IX86_BUILTIN_PSIGND128,
20828 IX86_BUILTIN_PALIGNR128,
20829 IX86_BUILTIN_PABSB128,
20830 IX86_BUILTIN_PABSW128,
20831 IX86_BUILTIN_PABSD128,
20833 /* AMDFAM10 - SSE4A New Instructions. */
20834 IX86_BUILTIN_MOVNTSD,
20835 IX86_BUILTIN_MOVNTSS,
20836 IX86_BUILTIN_EXTRQI,
20837 IX86_BUILTIN_EXTRQ,
20838 IX86_BUILTIN_INSERTQI,
20839 IX86_BUILTIN_INSERTQ,
20842 IX86_BUILTIN_BLENDPD,
20843 IX86_BUILTIN_BLENDPS,
20844 IX86_BUILTIN_BLENDVPD,
20845 IX86_BUILTIN_BLENDVPS,
20846 IX86_BUILTIN_PBLENDVB128,
20847 IX86_BUILTIN_PBLENDW128,
20852 IX86_BUILTIN_INSERTPS128,
20854 IX86_BUILTIN_MOVNTDQA,
20855 IX86_BUILTIN_MPSADBW128,
20856 IX86_BUILTIN_PACKUSDW128,
20857 IX86_BUILTIN_PCMPEQQ,
20858 IX86_BUILTIN_PHMINPOSUW128,
20860 IX86_BUILTIN_PMAXSB128,
20861 IX86_BUILTIN_PMAXSD128,
20862 IX86_BUILTIN_PMAXUD128,
20863 IX86_BUILTIN_PMAXUW128,
20865 IX86_BUILTIN_PMINSB128,
20866 IX86_BUILTIN_PMINSD128,
20867 IX86_BUILTIN_PMINUD128,
20868 IX86_BUILTIN_PMINUW128,
20870 IX86_BUILTIN_PMOVSXBW128,
20871 IX86_BUILTIN_PMOVSXBD128,
20872 IX86_BUILTIN_PMOVSXBQ128,
20873 IX86_BUILTIN_PMOVSXWD128,
20874 IX86_BUILTIN_PMOVSXWQ128,
20875 IX86_BUILTIN_PMOVSXDQ128,
20877 IX86_BUILTIN_PMOVZXBW128,
20878 IX86_BUILTIN_PMOVZXBD128,
20879 IX86_BUILTIN_PMOVZXBQ128,
20880 IX86_BUILTIN_PMOVZXWD128,
20881 IX86_BUILTIN_PMOVZXWQ128,
20882 IX86_BUILTIN_PMOVZXDQ128,
20884 IX86_BUILTIN_PMULDQ128,
20885 IX86_BUILTIN_PMULLD128,
20887 IX86_BUILTIN_ROUNDPD,
20888 IX86_BUILTIN_ROUNDPS,
20889 IX86_BUILTIN_ROUNDSD,
20890 IX86_BUILTIN_ROUNDSS,
20892 IX86_BUILTIN_PTESTZ,
20893 IX86_BUILTIN_PTESTC,
20894 IX86_BUILTIN_PTESTNZC,
20896 IX86_BUILTIN_VEC_INIT_V2SI,
20897 IX86_BUILTIN_VEC_INIT_V4HI,
20898 IX86_BUILTIN_VEC_INIT_V8QI,
20899 IX86_BUILTIN_VEC_EXT_V2DF,
20900 IX86_BUILTIN_VEC_EXT_V2DI,
20901 IX86_BUILTIN_VEC_EXT_V4SF,
20902 IX86_BUILTIN_VEC_EXT_V4SI,
20903 IX86_BUILTIN_VEC_EXT_V8HI,
20904 IX86_BUILTIN_VEC_EXT_V2SI,
20905 IX86_BUILTIN_VEC_EXT_V4HI,
20906 IX86_BUILTIN_VEC_EXT_V16QI,
20907 IX86_BUILTIN_VEC_SET_V2DI,
20908 IX86_BUILTIN_VEC_SET_V4SF,
20909 IX86_BUILTIN_VEC_SET_V4SI,
20910 IX86_BUILTIN_VEC_SET_V8HI,
20911 IX86_BUILTIN_VEC_SET_V4HI,
20912 IX86_BUILTIN_VEC_SET_V16QI,
20914 IX86_BUILTIN_VEC_PACK_SFIX,
20917 IX86_BUILTIN_CRC32QI,
20918 IX86_BUILTIN_CRC32HI,
20919 IX86_BUILTIN_CRC32SI,
20920 IX86_BUILTIN_CRC32DI,
20922 IX86_BUILTIN_PCMPESTRI128,
20923 IX86_BUILTIN_PCMPESTRM128,
20924 IX86_BUILTIN_PCMPESTRA128,
20925 IX86_BUILTIN_PCMPESTRC128,
20926 IX86_BUILTIN_PCMPESTRO128,
20927 IX86_BUILTIN_PCMPESTRS128,
20928 IX86_BUILTIN_PCMPESTRZ128,
20929 IX86_BUILTIN_PCMPISTRI128,
20930 IX86_BUILTIN_PCMPISTRM128,
20931 IX86_BUILTIN_PCMPISTRA128,
20932 IX86_BUILTIN_PCMPISTRC128,
20933 IX86_BUILTIN_PCMPISTRO128,
20934 IX86_BUILTIN_PCMPISTRS128,
20935 IX86_BUILTIN_PCMPISTRZ128,
20937 IX86_BUILTIN_PCMPGTQ,
20939 /* AES instructions */
20940 IX86_BUILTIN_AESENC128,
20941 IX86_BUILTIN_AESENCLAST128,
20942 IX86_BUILTIN_AESDEC128,
20943 IX86_BUILTIN_AESDECLAST128,
20944 IX86_BUILTIN_AESIMC128,
20945 IX86_BUILTIN_AESKEYGENASSIST128,
20947 /* PCLMUL instruction */
20948 IX86_BUILTIN_PCLMULQDQ128,
20951 IX86_BUILTIN_ADDPD256,
20952 IX86_BUILTIN_ADDPS256,
20953 IX86_BUILTIN_ADDSUBPD256,
20954 IX86_BUILTIN_ADDSUBPS256,
20955 IX86_BUILTIN_ANDPD256,
20956 IX86_BUILTIN_ANDPS256,
20957 IX86_BUILTIN_ANDNPD256,
20958 IX86_BUILTIN_ANDNPS256,
20959 IX86_BUILTIN_BLENDPD256,
20960 IX86_BUILTIN_BLENDPS256,
20961 IX86_BUILTIN_BLENDVPD256,
20962 IX86_BUILTIN_BLENDVPS256,
20963 IX86_BUILTIN_DIVPD256,
20964 IX86_BUILTIN_DIVPS256,
20965 IX86_BUILTIN_DPPS256,
20966 IX86_BUILTIN_HADDPD256,
20967 IX86_BUILTIN_HADDPS256,
20968 IX86_BUILTIN_HSUBPD256,
20969 IX86_BUILTIN_HSUBPS256,
20970 IX86_BUILTIN_MAXPD256,
20971 IX86_BUILTIN_MAXPS256,
20972 IX86_BUILTIN_MINPD256,
20973 IX86_BUILTIN_MINPS256,
20974 IX86_BUILTIN_MULPD256,
20975 IX86_BUILTIN_MULPS256,
20976 IX86_BUILTIN_ORPD256,
20977 IX86_BUILTIN_ORPS256,
20978 IX86_BUILTIN_SHUFPD256,
20979 IX86_BUILTIN_SHUFPS256,
20980 IX86_BUILTIN_SUBPD256,
20981 IX86_BUILTIN_SUBPS256,
20982 IX86_BUILTIN_XORPD256,
20983 IX86_BUILTIN_XORPS256,
20984 IX86_BUILTIN_CMPSD,
20985 IX86_BUILTIN_CMPSS,
20986 IX86_BUILTIN_CMPPD,
20987 IX86_BUILTIN_CMPPS,
20988 IX86_BUILTIN_CMPPD256,
20989 IX86_BUILTIN_CMPPS256,
20990 IX86_BUILTIN_CVTDQ2PD256,
20991 IX86_BUILTIN_CVTDQ2PS256,
20992 IX86_BUILTIN_CVTPD2PS256,
20993 IX86_BUILTIN_CVTPS2DQ256,
20994 IX86_BUILTIN_CVTPS2PD256,
20995 IX86_BUILTIN_CVTTPD2DQ256,
20996 IX86_BUILTIN_CVTPD2DQ256,
20997 IX86_BUILTIN_CVTTPS2DQ256,
20998 IX86_BUILTIN_EXTRACTF128PD256,
20999 IX86_BUILTIN_EXTRACTF128PS256,
21000 IX86_BUILTIN_EXTRACTF128SI256,
21001 IX86_BUILTIN_VZEROALL,
21002 IX86_BUILTIN_VZEROUPPER,
21003 IX86_BUILTIN_VZEROUPPER_REX64,
21004 IX86_BUILTIN_VPERMILVARPD,
21005 IX86_BUILTIN_VPERMILVARPS,
21006 IX86_BUILTIN_VPERMILVARPD256,
21007 IX86_BUILTIN_VPERMILVARPS256,
21008 IX86_BUILTIN_VPERMILPD,
21009 IX86_BUILTIN_VPERMILPS,
21010 IX86_BUILTIN_VPERMILPD256,
21011 IX86_BUILTIN_VPERMILPS256,
21012 IX86_BUILTIN_VPERM2F128PD256,
21013 IX86_BUILTIN_VPERM2F128PS256,
21014 IX86_BUILTIN_VPERM2F128SI256,
21015 IX86_BUILTIN_VBROADCASTSS,
21016 IX86_BUILTIN_VBROADCASTSD256,
21017 IX86_BUILTIN_VBROADCASTSS256,
21018 IX86_BUILTIN_VBROADCASTPD256,
21019 IX86_BUILTIN_VBROADCASTPS256,
21020 IX86_BUILTIN_VINSERTF128PD256,
21021 IX86_BUILTIN_VINSERTF128PS256,
21022 IX86_BUILTIN_VINSERTF128SI256,
21023 IX86_BUILTIN_LOADUPD256,
21024 IX86_BUILTIN_LOADUPS256,
21025 IX86_BUILTIN_STOREUPD256,
21026 IX86_BUILTIN_STOREUPS256,
21027 IX86_BUILTIN_LDDQU256,
21028 IX86_BUILTIN_MOVNTDQ256,
21029 IX86_BUILTIN_MOVNTPD256,
21030 IX86_BUILTIN_MOVNTPS256,
21031 IX86_BUILTIN_LOADDQU256,
21032 IX86_BUILTIN_STOREDQU256,
21033 IX86_BUILTIN_MASKLOADPD,
21034 IX86_BUILTIN_MASKLOADPS,
21035 IX86_BUILTIN_MASKSTOREPD,
21036 IX86_BUILTIN_MASKSTOREPS,
21037 IX86_BUILTIN_MASKLOADPD256,
21038 IX86_BUILTIN_MASKLOADPS256,
21039 IX86_BUILTIN_MASKSTOREPD256,
21040 IX86_BUILTIN_MASKSTOREPS256,
21041 IX86_BUILTIN_MOVSHDUP256,
21042 IX86_BUILTIN_MOVSLDUP256,
21043 IX86_BUILTIN_MOVDDUP256,
21045 IX86_BUILTIN_SQRTPD256,
21046 IX86_BUILTIN_SQRTPS256,
21047 IX86_BUILTIN_SQRTPS_NR256,
21048 IX86_BUILTIN_RSQRTPS256,
21049 IX86_BUILTIN_RSQRTPS_NR256,
21051 IX86_BUILTIN_RCPPS256,
21053 IX86_BUILTIN_ROUNDPD256,
21054 IX86_BUILTIN_ROUNDPS256,
21056 IX86_BUILTIN_UNPCKHPD256,
21057 IX86_BUILTIN_UNPCKLPD256,
21058 IX86_BUILTIN_UNPCKHPS256,
21059 IX86_BUILTIN_UNPCKLPS256,
21061 IX86_BUILTIN_SI256_SI,
21062 IX86_BUILTIN_PS256_PS,
21063 IX86_BUILTIN_PD256_PD,
21064 IX86_BUILTIN_SI_SI256,
21065 IX86_BUILTIN_PS_PS256,
21066 IX86_BUILTIN_PD_PD256,
21068 IX86_BUILTIN_VTESTZPD,
21069 IX86_BUILTIN_VTESTCPD,
21070 IX86_BUILTIN_VTESTNZCPD,
21071 IX86_BUILTIN_VTESTZPS,
21072 IX86_BUILTIN_VTESTCPS,
21073 IX86_BUILTIN_VTESTNZCPS,
21074 IX86_BUILTIN_VTESTZPD256,
21075 IX86_BUILTIN_VTESTCPD256,
21076 IX86_BUILTIN_VTESTNZCPD256,
21077 IX86_BUILTIN_VTESTZPS256,
21078 IX86_BUILTIN_VTESTCPS256,
21079 IX86_BUILTIN_VTESTNZCPS256,
21080 IX86_BUILTIN_PTESTZ256,
21081 IX86_BUILTIN_PTESTC256,
21082 IX86_BUILTIN_PTESTNZC256,
21084 IX86_BUILTIN_MOVMSKPD256,
21085 IX86_BUILTIN_MOVMSKPS256,
21087 /* TFmode support builtins. */
21089 IX86_BUILTIN_HUGE_VALQ,
21090 IX86_BUILTIN_FABSQ,
21091 IX86_BUILTIN_COPYSIGNQ,
21093 /* SSE5 instructions */
21094 IX86_BUILTIN_FMADDSS,
21095 IX86_BUILTIN_FMADDSD,
21096 IX86_BUILTIN_FMADDPS,
21097 IX86_BUILTIN_FMADDPD,
21098 IX86_BUILTIN_FMSUBSS,
21099 IX86_BUILTIN_FMSUBSD,
21100 IX86_BUILTIN_FMSUBPS,
21101 IX86_BUILTIN_FMSUBPD,
21102 IX86_BUILTIN_FNMADDSS,
21103 IX86_BUILTIN_FNMADDSD,
21104 IX86_BUILTIN_FNMADDPS,
21105 IX86_BUILTIN_FNMADDPD,
21106 IX86_BUILTIN_FNMSUBSS,
21107 IX86_BUILTIN_FNMSUBSD,
21108 IX86_BUILTIN_FNMSUBPS,
21109 IX86_BUILTIN_FNMSUBPD,
21110 IX86_BUILTIN_PCMOV,
21111 IX86_BUILTIN_PCMOV_V2DI,
21112 IX86_BUILTIN_PCMOV_V4SI,
21113 IX86_BUILTIN_PCMOV_V8HI,
21114 IX86_BUILTIN_PCMOV_V16QI,
21115 IX86_BUILTIN_PCMOV_V4SF,
21116 IX86_BUILTIN_PCMOV_V2DF,
21117 IX86_BUILTIN_PPERM,
21118 IX86_BUILTIN_PERMPS,
21119 IX86_BUILTIN_PERMPD,
21120 IX86_BUILTIN_PMACSSWW,
21121 IX86_BUILTIN_PMACSWW,
21122 IX86_BUILTIN_PMACSSWD,
21123 IX86_BUILTIN_PMACSWD,
21124 IX86_BUILTIN_PMACSSDD,
21125 IX86_BUILTIN_PMACSDD,
21126 IX86_BUILTIN_PMACSSDQL,
21127 IX86_BUILTIN_PMACSSDQH,
21128 IX86_BUILTIN_PMACSDQL,
21129 IX86_BUILTIN_PMACSDQH,
21130 IX86_BUILTIN_PMADCSSWD,
21131 IX86_BUILTIN_PMADCSWD,
21132 IX86_BUILTIN_PHADDBW,
21133 IX86_BUILTIN_PHADDBD,
21134 IX86_BUILTIN_PHADDBQ,
21135 IX86_BUILTIN_PHADDWD,
21136 IX86_BUILTIN_PHADDWQ,
21137 IX86_BUILTIN_PHADDDQ,
21138 IX86_BUILTIN_PHADDUBW,
21139 IX86_BUILTIN_PHADDUBD,
21140 IX86_BUILTIN_PHADDUBQ,
21141 IX86_BUILTIN_PHADDUWD,
21142 IX86_BUILTIN_PHADDUWQ,
21143 IX86_BUILTIN_PHADDUDQ,
21144 IX86_BUILTIN_PHSUBBW,
21145 IX86_BUILTIN_PHSUBWD,
21146 IX86_BUILTIN_PHSUBDQ,
21147 IX86_BUILTIN_PROTB,
21148 IX86_BUILTIN_PROTW,
21149 IX86_BUILTIN_PROTD,
21150 IX86_BUILTIN_PROTQ,
21151 IX86_BUILTIN_PROTB_IMM,
21152 IX86_BUILTIN_PROTW_IMM,
21153 IX86_BUILTIN_PROTD_IMM,
21154 IX86_BUILTIN_PROTQ_IMM,
21155 IX86_BUILTIN_PSHLB,
21156 IX86_BUILTIN_PSHLW,
21157 IX86_BUILTIN_PSHLD,
21158 IX86_BUILTIN_PSHLQ,
21159 IX86_BUILTIN_PSHAB,
21160 IX86_BUILTIN_PSHAW,
21161 IX86_BUILTIN_PSHAD,
21162 IX86_BUILTIN_PSHAQ,
21163 IX86_BUILTIN_FRCZSS,
21164 IX86_BUILTIN_FRCZSD,
21165 IX86_BUILTIN_FRCZPS,
21166 IX86_BUILTIN_FRCZPD,
21167 IX86_BUILTIN_CVTPH2PS,
21168 IX86_BUILTIN_CVTPS2PH,
21170 IX86_BUILTIN_COMEQSS,
21171 IX86_BUILTIN_COMNESS,
21172 IX86_BUILTIN_COMLTSS,
21173 IX86_BUILTIN_COMLESS,
21174 IX86_BUILTIN_COMGTSS,
21175 IX86_BUILTIN_COMGESS,
21176 IX86_BUILTIN_COMUEQSS,
21177 IX86_BUILTIN_COMUNESS,
21178 IX86_BUILTIN_COMULTSS,
21179 IX86_BUILTIN_COMULESS,
21180 IX86_BUILTIN_COMUGTSS,
21181 IX86_BUILTIN_COMUGESS,
21182 IX86_BUILTIN_COMORDSS,
21183 IX86_BUILTIN_COMUNORDSS,
21184 IX86_BUILTIN_COMFALSESS,
21185 IX86_BUILTIN_COMTRUESS,
21187 IX86_BUILTIN_COMEQSD,
21188 IX86_BUILTIN_COMNESD,
21189 IX86_BUILTIN_COMLTSD,
21190 IX86_BUILTIN_COMLESD,
21191 IX86_BUILTIN_COMGTSD,
21192 IX86_BUILTIN_COMGESD,
21193 IX86_BUILTIN_COMUEQSD,
21194 IX86_BUILTIN_COMUNESD,
21195 IX86_BUILTIN_COMULTSD,
21196 IX86_BUILTIN_COMULESD,
21197 IX86_BUILTIN_COMUGTSD,
21198 IX86_BUILTIN_COMUGESD,
21199 IX86_BUILTIN_COMORDSD,
21200 IX86_BUILTIN_COMUNORDSD,
21201 IX86_BUILTIN_COMFALSESD,
21202 IX86_BUILTIN_COMTRUESD,
21204 IX86_BUILTIN_COMEQPS,
21205 IX86_BUILTIN_COMNEPS,
21206 IX86_BUILTIN_COMLTPS,
21207 IX86_BUILTIN_COMLEPS,
21208 IX86_BUILTIN_COMGTPS,
21209 IX86_BUILTIN_COMGEPS,
21210 IX86_BUILTIN_COMUEQPS,
21211 IX86_BUILTIN_COMUNEPS,
21212 IX86_BUILTIN_COMULTPS,
21213 IX86_BUILTIN_COMULEPS,
21214 IX86_BUILTIN_COMUGTPS,
21215 IX86_BUILTIN_COMUGEPS,
21216 IX86_BUILTIN_COMORDPS,
21217 IX86_BUILTIN_COMUNORDPS,
21218 IX86_BUILTIN_COMFALSEPS,
21219 IX86_BUILTIN_COMTRUEPS,
21221 IX86_BUILTIN_COMEQPD,
21222 IX86_BUILTIN_COMNEPD,
21223 IX86_BUILTIN_COMLTPD,
21224 IX86_BUILTIN_COMLEPD,
21225 IX86_BUILTIN_COMGTPD,
21226 IX86_BUILTIN_COMGEPD,
21227 IX86_BUILTIN_COMUEQPD,
21228 IX86_BUILTIN_COMUNEPD,
21229 IX86_BUILTIN_COMULTPD,
21230 IX86_BUILTIN_COMULEPD,
21231 IX86_BUILTIN_COMUGTPD,
21232 IX86_BUILTIN_COMUGEPD,
21233 IX86_BUILTIN_COMORDPD,
21234 IX86_BUILTIN_COMUNORDPD,
21235 IX86_BUILTIN_COMFALSEPD,
21236 IX86_BUILTIN_COMTRUEPD,
21238 IX86_BUILTIN_PCOMEQUB,
21239 IX86_BUILTIN_PCOMNEUB,
21240 IX86_BUILTIN_PCOMLTUB,
21241 IX86_BUILTIN_PCOMLEUB,
21242 IX86_BUILTIN_PCOMGTUB,
21243 IX86_BUILTIN_PCOMGEUB,
21244 IX86_BUILTIN_PCOMFALSEUB,
21245 IX86_BUILTIN_PCOMTRUEUB,
21246 IX86_BUILTIN_PCOMEQUW,
21247 IX86_BUILTIN_PCOMNEUW,
21248 IX86_BUILTIN_PCOMLTUW,
21249 IX86_BUILTIN_PCOMLEUW,
21250 IX86_BUILTIN_PCOMGTUW,
21251 IX86_BUILTIN_PCOMGEUW,
21252 IX86_BUILTIN_PCOMFALSEUW,
21253 IX86_BUILTIN_PCOMTRUEUW,
21254 IX86_BUILTIN_PCOMEQUD,
21255 IX86_BUILTIN_PCOMNEUD,
21256 IX86_BUILTIN_PCOMLTUD,
21257 IX86_BUILTIN_PCOMLEUD,
21258 IX86_BUILTIN_PCOMGTUD,
21259 IX86_BUILTIN_PCOMGEUD,
21260 IX86_BUILTIN_PCOMFALSEUD,
21261 IX86_BUILTIN_PCOMTRUEUD,
21262 IX86_BUILTIN_PCOMEQUQ,
21263 IX86_BUILTIN_PCOMNEUQ,
21264 IX86_BUILTIN_PCOMLTUQ,
21265 IX86_BUILTIN_PCOMLEUQ,
21266 IX86_BUILTIN_PCOMGTUQ,
21267 IX86_BUILTIN_PCOMGEUQ,
21268 IX86_BUILTIN_PCOMFALSEUQ,
21269 IX86_BUILTIN_PCOMTRUEUQ,
21271 IX86_BUILTIN_PCOMEQB,
21272 IX86_BUILTIN_PCOMNEB,
21273 IX86_BUILTIN_PCOMLTB,
21274 IX86_BUILTIN_PCOMLEB,
21275 IX86_BUILTIN_PCOMGTB,
21276 IX86_BUILTIN_PCOMGEB,
21277 IX86_BUILTIN_PCOMFALSEB,
21278 IX86_BUILTIN_PCOMTRUEB,
21279 IX86_BUILTIN_PCOMEQW,
21280 IX86_BUILTIN_PCOMNEW,
21281 IX86_BUILTIN_PCOMLTW,
21282 IX86_BUILTIN_PCOMLEW,
21283 IX86_BUILTIN_PCOMGTW,
21284 IX86_BUILTIN_PCOMGEW,
21285 IX86_BUILTIN_PCOMFALSEW,
21286 IX86_BUILTIN_PCOMTRUEW,
21287 IX86_BUILTIN_PCOMEQD,
21288 IX86_BUILTIN_PCOMNED,
21289 IX86_BUILTIN_PCOMLTD,
21290 IX86_BUILTIN_PCOMLED,
21291 IX86_BUILTIN_PCOMGTD,
21292 IX86_BUILTIN_PCOMGED,
21293 IX86_BUILTIN_PCOMFALSED,
21294 IX86_BUILTIN_PCOMTRUED,
21295 IX86_BUILTIN_PCOMEQQ,
21296 IX86_BUILTIN_PCOMNEQ,
21297 IX86_BUILTIN_PCOMLTQ,
21298 IX86_BUILTIN_PCOMLEQ,
21299 IX86_BUILTIN_PCOMGTQ,
21300 IX86_BUILTIN_PCOMGEQ,
21301 IX86_BUILTIN_PCOMFALSEQ,
21302 IX86_BUILTIN_PCOMTRUEQ,
21307 /* Table for the ix86 builtin decls. */
21308 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
21310 /* Table of all of the builtin functions that are possible with different ISA's
21311 but are waiting to be built until a function is declared to use that
21313 struct GTY(()) builtin_isa {
21314 tree type; /* builtin type to use in the declaration */
21315 const char *name; /* function name */
21316 int isa; /* isa_flags this builtin is defined for */
21317 bool const_p; /* true if the declaration is constant */
21320 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
21323 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21324 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
21325 * function decl in the ix86_builtins array. Returns the function decl or
21326 * NULL_TREE, if the builtin was not added.
21328 * If the front end has a special hook for builtin functions, delay adding
21329 * builtin functions that aren't in the current ISA until the ISA is changed
21330 * with function specific optimization. Doing so, can save about 300K for the
21331 * default compiler. When the builtin is expanded, check at that time whether
21334 * If the front end doesn't have a special hook, record all builtins, even if
21335 * it isn't an instruction set in the current ISA in case the user uses
21336 * function specific options for a different ISA, so that we don't get scope
21337 * errors if a builtin is added in the middle of a function scope. */
21340 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
21342 tree decl = NULL_TREE;
21344 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
21346 ix86_builtins_isa[(int) code].isa = mask;
21348 if ((mask & ix86_isa_flags) != 0
21349 || (lang_hooks.builtin_function
21350 == lang_hooks.builtin_function_ext_scope))
21353 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
21355 ix86_builtins[(int) code] = decl;
21356 ix86_builtins_isa[(int) code].type = NULL_TREE;
21360 ix86_builtins[(int) code] = NULL_TREE;
21361 ix86_builtins_isa[(int) code].const_p = false;
21362 ix86_builtins_isa[(int) code].type = type;
21363 ix86_builtins_isa[(int) code].name = name;
21370 /* Like def_builtin, but also marks the function decl "const". */
21373 def_builtin_const (int mask, const char *name, tree type,
21374 enum ix86_builtins code)
21376 tree decl = def_builtin (mask, name, type, code);
21378 TREE_READONLY (decl) = 1;
21380 ix86_builtins_isa[(int) code].const_p = true;
21385 /* Add any new builtin functions for a given ISA that may not have been
21386 declared. This saves a bit of space compared to adding all of the
21387 declarations to the tree, even if we didn't use them. */
21390 ix86_add_new_builtins (int isa)
21395 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
21397 if ((ix86_builtins_isa[i].isa & isa) != 0
21398 && ix86_builtins_isa[i].type != NULL_TREE)
21400 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
21401 ix86_builtins_isa[i].type,
21402 i, BUILT_IN_MD, NULL,
21405 ix86_builtins[i] = decl;
21406 ix86_builtins_isa[i].type = NULL_TREE;
21407 if (ix86_builtins_isa[i].const_p)
21408 TREE_READONLY (decl) = 1;
21413 /* Bits for builtin_description.flag. */
21415 /* Set when we don't support the comparison natively, and should
21416 swap_comparison in order to support it. */
21417 #define BUILTIN_DESC_SWAP_OPERANDS 1
21419 struct builtin_description
21421 const unsigned int mask;
21422 const enum insn_code icode;
21423 const char *const name;
21424 const enum ix86_builtins code;
21425 const enum rtx_code comparison;
21429 static const struct builtin_description bdesc_comi[] =
21431 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21432 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21433 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21435 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21436 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21439 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21440 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21441 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21442 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21457 static const struct builtin_description bdesc_pcmpestr[] =
21460 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21461 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21462 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21463 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21464 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21465 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21466 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21469 static const struct builtin_description bdesc_pcmpistr[] =
21472 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21473 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21474 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21475 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21476 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21477 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21478 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21481 /* Special builtin types */
21482 enum ix86_special_builtin_type
21484 SPECIAL_FTYPE_UNKNOWN,
21487 UINT64_FTYPE_PUNSIGNED,
21488 V32QI_FTYPE_PCCHAR,
21489 V16QI_FTYPE_PCCHAR,
21491 V8SF_FTYPE_PCFLOAT,
21493 V4DF_FTYPE_PCDOUBLE,
21494 V4SF_FTYPE_PCFLOAT,
21495 V2DF_FTYPE_PCDOUBLE,
21496 V8SF_FTYPE_PCV8SF_V8SF,
21497 V4DF_FTYPE_PCV4DF_V4DF,
21498 V4SF_FTYPE_V4SF_PCV2SF,
21499 V4SF_FTYPE_PCV4SF_V4SF,
21500 V2DF_FTYPE_V2DF_PCDOUBLE,
21501 V2DF_FTYPE_PCV2DF_V2DF,
21503 VOID_FTYPE_PV2SF_V4SF,
21504 VOID_FTYPE_PV4DI_V4DI,
21505 VOID_FTYPE_PV2DI_V2DI,
21506 VOID_FTYPE_PCHAR_V32QI,
21507 VOID_FTYPE_PCHAR_V16QI,
21508 VOID_FTYPE_PFLOAT_V8SF,
21509 VOID_FTYPE_PFLOAT_V4SF,
21510 VOID_FTYPE_PDOUBLE_V4DF,
21511 VOID_FTYPE_PDOUBLE_V2DF,
21513 VOID_FTYPE_PINT_INT,
21514 VOID_FTYPE_PV8SF_V8SF_V8SF,
21515 VOID_FTYPE_PV4DF_V4DF_V4DF,
21516 VOID_FTYPE_PV4SF_V4SF_V4SF,
21517 VOID_FTYPE_PV2DF_V2DF_V2DF
21520 /* Builtin types */
21521 enum ix86_builtin_type
21524 FLOAT128_FTYPE_FLOAT128,
21526 FLOAT128_FTYPE_FLOAT128_FLOAT128,
21527 INT_FTYPE_V8SF_V8SF_PTEST,
21528 INT_FTYPE_V4DI_V4DI_PTEST,
21529 INT_FTYPE_V4DF_V4DF_PTEST,
21530 INT_FTYPE_V4SF_V4SF_PTEST,
21531 INT_FTYPE_V2DI_V2DI_PTEST,
21532 INT_FTYPE_V2DF_V2DF_PTEST,
21567 V4SF_FTYPE_V4SF_VEC_MERGE,
21576 V2DF_FTYPE_V2DF_VEC_MERGE,
21587 V16QI_FTYPE_V16QI_V16QI,
21588 V16QI_FTYPE_V8HI_V8HI,
21589 V8QI_FTYPE_V8QI_V8QI,
21590 V8QI_FTYPE_V4HI_V4HI,
21591 V8HI_FTYPE_V8HI_V8HI,
21592 V8HI_FTYPE_V8HI_V8HI_COUNT,
21593 V8HI_FTYPE_V16QI_V16QI,
21594 V8HI_FTYPE_V4SI_V4SI,
21595 V8HI_FTYPE_V8HI_SI_COUNT,
21596 V8SF_FTYPE_V8SF_V8SF,
21597 V8SF_FTYPE_V8SF_V8SI,
21598 V4SI_FTYPE_V4SI_V4SI,
21599 V4SI_FTYPE_V4SI_V4SI_COUNT,
21600 V4SI_FTYPE_V8HI_V8HI,
21601 V4SI_FTYPE_V4SF_V4SF,
21602 V4SI_FTYPE_V2DF_V2DF,
21603 V4SI_FTYPE_V4SI_SI_COUNT,
21604 V4HI_FTYPE_V4HI_V4HI,
21605 V4HI_FTYPE_V4HI_V4HI_COUNT,
21606 V4HI_FTYPE_V8QI_V8QI,
21607 V4HI_FTYPE_V2SI_V2SI,
21608 V4HI_FTYPE_V4HI_SI_COUNT,
21609 V4DF_FTYPE_V4DF_V4DF,
21610 V4DF_FTYPE_V4DF_V4DI,
21611 V4SF_FTYPE_V4SF_V4SF,
21612 V4SF_FTYPE_V4SF_V4SF_SWAP,
21613 V4SF_FTYPE_V4SF_V4SI,
21614 V4SF_FTYPE_V4SF_V2SI,
21615 V4SF_FTYPE_V4SF_V2DF,
21616 V4SF_FTYPE_V4SF_DI,
21617 V4SF_FTYPE_V4SF_SI,
21618 V2DI_FTYPE_V2DI_V2DI,
21619 V2DI_FTYPE_V2DI_V2DI_COUNT,
21620 V2DI_FTYPE_V16QI_V16QI,
21621 V2DI_FTYPE_V4SI_V4SI,
21622 V2DI_FTYPE_V2DI_V16QI,
21623 V2DI_FTYPE_V2DF_V2DF,
21624 V2DI_FTYPE_V2DI_SI_COUNT,
21625 V2SI_FTYPE_V2SI_V2SI,
21626 V2SI_FTYPE_V2SI_V2SI_COUNT,
21627 V2SI_FTYPE_V4HI_V4HI,
21628 V2SI_FTYPE_V2SF_V2SF,
21629 V2SI_FTYPE_V2SI_SI_COUNT,
21630 V2DF_FTYPE_V2DF_V2DF,
21631 V2DF_FTYPE_V2DF_V2DF_SWAP,
21632 V2DF_FTYPE_V2DF_V4SF,
21633 V2DF_FTYPE_V2DF_V2DI,
21634 V2DF_FTYPE_V2DF_DI,
21635 V2DF_FTYPE_V2DF_SI,
21636 V2SF_FTYPE_V2SF_V2SF,
21637 V1DI_FTYPE_V1DI_V1DI,
21638 V1DI_FTYPE_V1DI_V1DI_COUNT,
21639 V1DI_FTYPE_V8QI_V8QI,
21640 V1DI_FTYPE_V2SI_V2SI,
21641 V1DI_FTYPE_V1DI_SI_COUNT,
21642 UINT64_FTYPE_UINT64_UINT64,
21643 UINT_FTYPE_UINT_UINT,
21644 UINT_FTYPE_UINT_USHORT,
21645 UINT_FTYPE_UINT_UCHAR,
21646 UINT16_FTYPE_UINT16_INT,
21647 UINT8_FTYPE_UINT8_INT,
21648 V8HI_FTYPE_V8HI_INT,
21649 V4SI_FTYPE_V4SI_INT,
21650 V4HI_FTYPE_V4HI_INT,
21651 V8SF_FTYPE_V8SF_INT,
21652 V4SI_FTYPE_V8SI_INT,
21653 V4SF_FTYPE_V8SF_INT,
21654 V2DF_FTYPE_V4DF_INT,
21655 V4DF_FTYPE_V4DF_INT,
21656 V4SF_FTYPE_V4SF_INT,
21657 V2DI_FTYPE_V2DI_INT,
21658 V2DI2TI_FTYPE_V2DI_INT,
21659 V2DF_FTYPE_V2DF_INT,
21660 V16QI_FTYPE_V16QI_V16QI_V16QI,
21661 V8SF_FTYPE_V8SF_V8SF_V8SF,
21662 V4DF_FTYPE_V4DF_V4DF_V4DF,
21663 V4SF_FTYPE_V4SF_V4SF_V4SF,
21664 V2DF_FTYPE_V2DF_V2DF_V2DF,
21665 V16QI_FTYPE_V16QI_V16QI_INT,
21666 V8SI_FTYPE_V8SI_V8SI_INT,
21667 V8SI_FTYPE_V8SI_V4SI_INT,
21668 V8HI_FTYPE_V8HI_V8HI_INT,
21669 V8SF_FTYPE_V8SF_V8SF_INT,
21670 V8SF_FTYPE_V8SF_V4SF_INT,
21671 V4SI_FTYPE_V4SI_V4SI_INT,
21672 V4DF_FTYPE_V4DF_V4DF_INT,
21673 V4DF_FTYPE_V4DF_V2DF_INT,
21674 V4SF_FTYPE_V4SF_V4SF_INT,
21675 V2DI_FTYPE_V2DI_V2DI_INT,
21676 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21677 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21678 V2DF_FTYPE_V2DF_V2DF_INT,
21679 V2DI_FTYPE_V2DI_UINT_UINT,
21680 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21683 /* Special builtins with variable number of arguments. */
21684 static const struct builtin_description bdesc_special_args[] =
21686 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21687 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21690 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21693 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21696 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21697 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21698 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21700 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21701 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21702 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21703 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21705 /* SSE or 3DNow!A */
21706 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21707 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21710 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21711 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21712 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21713 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21714 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21715 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21716 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21717 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21718 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21720 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21721 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21724 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21727 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21730 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21731 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21736 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21760 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21763 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21766 /* Builtins with variable number of arguments. */
21767 static const struct builtin_description bdesc_args[] =
21769 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21770 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21771 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21772 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21773 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21774 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21775 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21778 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21779 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21780 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21781 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21782 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21783 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21785 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21786 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21787 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21788 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21789 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21790 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21791 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21792 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21794 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21795 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21797 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21798 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21799 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21800 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21802 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21803 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21804 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21805 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21806 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21807 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21809 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21810 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21811 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21812 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21813 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21814 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21816 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21817 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21818 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21820 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21822 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21823 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21824 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21825 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21826 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21827 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21829 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21830 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21831 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21832 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21833 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21834 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21836 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21837 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21838 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21839 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21842 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21843 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21844 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21845 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21847 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21848 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21849 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21850 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21851 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21852 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21853 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21854 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21855 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21856 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21857 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21858 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21859 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21860 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21861 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21864 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21865 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21866 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21867 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21868 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21869 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21872 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21873 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21874 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21875 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21876 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21878 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21879 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21880 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21881 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21882 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21883 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21885 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21887 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21888 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21889 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21890 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21891 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21892 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21893 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21894 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21896 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21897 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21898 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21899 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21900 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21901 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21902 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21903 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21904 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21905 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21906 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21907 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21908 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21909 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21910 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21911 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21912 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21913 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21914 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21915 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21916 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21917 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21919 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21920 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21921 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21922 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21924 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21926 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21927 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21937 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21939 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21941 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21942 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21945 /* SSE MMX or 3Dnow!A */
21946 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21947 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21948 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21950 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21951 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21952 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21953 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21955 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21956 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21958 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21973 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21975 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21979 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21980 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21982 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21983 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21984 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21986 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21987 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21988 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21989 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21993 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21995 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21997 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21999 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
22000 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
22002 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
22003 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
22004 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22005 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
22006 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22007 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
22008 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
22009 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
22010 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
22012 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
22013 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
22014 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
22016 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22017 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22018 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22019 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22021 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22022 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22023 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22024 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22027 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22028 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22030 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
22032 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22033 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22034 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22035 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22036 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22037 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22038 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22039 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22043 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22048 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22050 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22051 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
22053 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22055 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22056 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22058 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22059 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22062 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22068 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22069 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22070 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22074 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22080 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22082 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
22083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
22086 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
22089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
22090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
22094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
22095 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
22096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
22097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
22099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
22100 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22101 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22102 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22103 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22104 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22105 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
22108 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22109 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22110 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22111 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22112 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22113 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22115 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22116 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22117 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22118 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
22121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
22126 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
22127 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
22129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22132 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22133 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22136 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
22137 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22139 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22140 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22141 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22142 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22143 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22144 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22147 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
22148 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
22149 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22150 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
22151 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
22152 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
22154 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22155 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22156 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22157 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22158 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22159 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22160 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22161 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22162 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22163 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22164 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22165 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22166 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
22167 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
22168 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22169 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22170 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22171 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22172 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22173 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22174 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22175 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22176 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22177 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22180 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
22181 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
22184 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22185 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22186 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
22187 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
22188 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22189 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22190 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22191 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
22192 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22193 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
22195 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22196 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22197 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22198 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22199 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22200 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22201 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22202 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22203 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22204 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22205 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22206 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22207 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22209 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22210 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22211 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22212 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22213 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22214 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22215 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22216 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22217 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22218 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22219 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22220 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22222 /* SSE4.1 and SSE5 */
22223 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22224 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22225 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22226 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22228 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22229 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22230 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22233 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22234 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22235 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22236 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22237 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22240 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22241 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22242 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22243 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22246 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22247 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22249 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22250 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22251 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22252 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22255 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22258 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22259 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22260 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22261 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22262 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22263 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22264 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22265 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22266 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22267 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22268 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22269 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22270 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22271 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22272 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22273 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22274 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22275 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22276 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22277 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22278 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22279 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22280 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22281 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22282 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22283 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22285 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22286 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22287 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22288 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22290 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22291 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22292 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22293 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22294 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22295 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22296 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22297 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22298 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22299 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22300 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22301 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22302 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22303 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22304 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22305 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22306 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22307 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22308 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22309 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22310 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22311 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22312 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22313 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22314 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22315 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22316 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22317 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22318 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22319 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22320 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22321 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22322 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22323 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22325 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22326 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22327 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22329 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22330 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22331 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22332 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22333 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22335 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22337 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22338 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22340 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22341 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22342 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22343 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22345 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22346 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22347 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22348 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22349 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22350 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22352 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22353 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22354 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22355 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22356 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22357 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22358 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22359 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22360 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22361 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22362 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22363 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22364 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22365 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22368 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22369 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22373 enum multi_arg_type {
22383 MULTI_ARG_3_PERMPS,
22384 MULTI_ARG_3_PERMPD,
22391 MULTI_ARG_2_DI_IMM,
22392 MULTI_ARG_2_SI_IMM,
22393 MULTI_ARG_2_HI_IMM,
22394 MULTI_ARG_2_QI_IMM,
22395 MULTI_ARG_2_SF_CMP,
22396 MULTI_ARG_2_DF_CMP,
22397 MULTI_ARG_2_DI_CMP,
22398 MULTI_ARG_2_SI_CMP,
22399 MULTI_ARG_2_HI_CMP,
22400 MULTI_ARG_2_QI_CMP,
22423 static const struct builtin_description bdesc_multi_arg[] =
22425 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22426 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22427 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22428 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22429 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22430 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22431 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22432 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22433 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22434 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22435 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22436 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22437 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22438 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22439 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22440 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22441 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22442 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22443 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22444 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22445 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22446 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22447 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22448 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22449 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, UNKNOWN, (int)MULTI_ARG_3_PERMPS },
22450 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, UNKNOWN, (int)MULTI_ARG_3_PERMPD },
22451 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22452 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22453 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22454 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22455 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22456 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22457 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22458 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22459 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22460 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22461 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22462 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22463 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22464 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22465 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22466 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22467 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22468 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22469 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22470 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22471 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22472 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22473 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22474 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22475 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22476 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22477 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22478 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22479 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22480 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22481 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22482 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22483 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int)MULTI_ARG_1_PH2PS },
22484 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int)MULTI_ARG_1_PS2PH },
22485 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22486 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22487 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22488 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22489 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22490 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22491 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22492 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22493 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22494 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22495 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22496 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22497 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22498 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22499 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22501 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
22502 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
22503 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
22504 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
22505 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
22506 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
22507 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
22508 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
22509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
22512 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
22513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
22514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
22515 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
22516 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
22518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
22519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
22520 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
22521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
22522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
22523 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
22524 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
22525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
22526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
22529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
22530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
22531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
22532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
22533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
22535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
22536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
22537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
22538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
22539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
22540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
22541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
22542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
22543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
22545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
22546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
22547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
22548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
22549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
22550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
22552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
22553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
22554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
22555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
22556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
22557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
22558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
22559 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
22560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
22562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
22563 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
22564 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
22565 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
22566 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
22567 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
22569 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22570 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22571 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22572 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22573 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22574 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22575 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22577 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22578 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22579 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22580 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22581 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22582 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22583 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22585 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22586 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22587 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22588 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22589 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22590 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22591 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22593 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22594 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22595 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22596 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22597 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22598 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22599 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22601 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22602 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22603 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22604 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22605 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22606 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22607 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22609 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22610 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22611 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22612 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22613 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22614 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22615 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22617 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22618 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22619 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22620 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22621 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22622 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22623 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22625 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22626 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22627 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22628 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22629 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22630 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22631 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22633 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
22634 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
22635 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
22636 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
22637 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
22638 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
22639 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
22640 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
22642 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22643 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22644 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22645 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22646 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22647 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22648 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22649 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22651 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22652 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22653 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22654 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22655 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22656 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22657 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22658 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22661 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22662 in the current target ISA to allow the user to compile particular modules
22663 with different target specific options that differ from the command line
22666 ix86_init_mmx_sse_builtins (void)
22668 const struct builtin_description * d;
22671 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
22672 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
22673 tree V1DI_type_node
22674 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
22675 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
22676 tree V2DI_type_node
22677 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
22678 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
22679 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
22680 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
22681 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
22682 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
22683 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
22685 tree pchar_type_node = build_pointer_type (char_type_node);
22686 tree pcchar_type_node
22687 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
22688 tree pfloat_type_node = build_pointer_type (float_type_node);
22689 tree pcfloat_type_node
22690 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
22691 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
22692 tree pcv2sf_type_node
22693 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
22694 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
22695 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
22698 tree int_ftype_v4sf_v4sf
22699 = build_function_type_list (integer_type_node,
22700 V4SF_type_node, V4SF_type_node, NULL_TREE);
22701 tree v4si_ftype_v4sf_v4sf
22702 = build_function_type_list (V4SI_type_node,
22703 V4SF_type_node, V4SF_type_node, NULL_TREE);
22704 /* MMX/SSE/integer conversions. */
22705 tree int_ftype_v4sf
22706 = build_function_type_list (integer_type_node,
22707 V4SF_type_node, NULL_TREE);
22708 tree int64_ftype_v4sf
22709 = build_function_type_list (long_long_integer_type_node,
22710 V4SF_type_node, NULL_TREE);
22711 tree int_ftype_v8qi
22712 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
22713 tree v4sf_ftype_v4sf_int
22714 = build_function_type_list (V4SF_type_node,
22715 V4SF_type_node, integer_type_node, NULL_TREE);
22716 tree v4sf_ftype_v4sf_int64
22717 = build_function_type_list (V4SF_type_node,
22718 V4SF_type_node, long_long_integer_type_node,
22720 tree v4sf_ftype_v4sf_v2si
22721 = build_function_type_list (V4SF_type_node,
22722 V4SF_type_node, V2SI_type_node, NULL_TREE);
22724 /* Miscellaneous. */
22725 tree v8qi_ftype_v4hi_v4hi
22726 = build_function_type_list (V8QI_type_node,
22727 V4HI_type_node, V4HI_type_node, NULL_TREE);
22728 tree v4hi_ftype_v2si_v2si
22729 = build_function_type_list (V4HI_type_node,
22730 V2SI_type_node, V2SI_type_node, NULL_TREE);
22731 tree v4sf_ftype_v4sf_v4sf_int
22732 = build_function_type_list (V4SF_type_node,
22733 V4SF_type_node, V4SF_type_node,
22734 integer_type_node, NULL_TREE);
22735 tree v2si_ftype_v4hi_v4hi
22736 = build_function_type_list (V2SI_type_node,
22737 V4HI_type_node, V4HI_type_node, NULL_TREE);
22738 tree v4hi_ftype_v4hi_int
22739 = build_function_type_list (V4HI_type_node,
22740 V4HI_type_node, integer_type_node, NULL_TREE);
22741 tree v2si_ftype_v2si_int
22742 = build_function_type_list (V2SI_type_node,
22743 V2SI_type_node, integer_type_node, NULL_TREE);
22744 tree v1di_ftype_v1di_int
22745 = build_function_type_list (V1DI_type_node,
22746 V1DI_type_node, integer_type_node, NULL_TREE);
22748 tree void_ftype_void
22749 = build_function_type (void_type_node, void_list_node);
22750 tree void_ftype_unsigned
22751 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22752 tree void_ftype_unsigned_unsigned
22753 = build_function_type_list (void_type_node, unsigned_type_node,
22754 unsigned_type_node, NULL_TREE);
22755 tree void_ftype_pcvoid_unsigned_unsigned
22756 = build_function_type_list (void_type_node, const_ptr_type_node,
22757 unsigned_type_node, unsigned_type_node,
22759 tree unsigned_ftype_void
22760 = build_function_type (unsigned_type_node, void_list_node);
22761 tree v2si_ftype_v4sf
22762 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22763 /* Loads/stores. */
22764 tree void_ftype_v8qi_v8qi_pchar
22765 = build_function_type_list (void_type_node,
22766 V8QI_type_node, V8QI_type_node,
22767 pchar_type_node, NULL_TREE);
22768 tree v4sf_ftype_pcfloat
22769 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22770 tree v4sf_ftype_v4sf_pcv2sf
22771 = build_function_type_list (V4SF_type_node,
22772 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22773 tree void_ftype_pv2sf_v4sf
22774 = build_function_type_list (void_type_node,
22775 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22776 tree void_ftype_pfloat_v4sf
22777 = build_function_type_list (void_type_node,
22778 pfloat_type_node, V4SF_type_node, NULL_TREE);
22779 tree void_ftype_pdi_di
22780 = build_function_type_list (void_type_node,
22781 pdi_type_node, long_long_unsigned_type_node,
22783 tree void_ftype_pv2di_v2di
22784 = build_function_type_list (void_type_node,
22785 pv2di_type_node, V2DI_type_node, NULL_TREE);
22786 /* Normal vector unops. */
22787 tree v4sf_ftype_v4sf
22788 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22789 tree v16qi_ftype_v16qi
22790 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22791 tree v8hi_ftype_v8hi
22792 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22793 tree v4si_ftype_v4si
22794 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22795 tree v8qi_ftype_v8qi
22796 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22797 tree v4hi_ftype_v4hi
22798 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22800 /* Normal vector binops. */
22801 tree v4sf_ftype_v4sf_v4sf
22802 = build_function_type_list (V4SF_type_node,
22803 V4SF_type_node, V4SF_type_node, NULL_TREE);
22804 tree v8qi_ftype_v8qi_v8qi
22805 = build_function_type_list (V8QI_type_node,
22806 V8QI_type_node, V8QI_type_node, NULL_TREE);
22807 tree v4hi_ftype_v4hi_v4hi
22808 = build_function_type_list (V4HI_type_node,
22809 V4HI_type_node, V4HI_type_node, NULL_TREE);
22810 tree v2si_ftype_v2si_v2si
22811 = build_function_type_list (V2SI_type_node,
22812 V2SI_type_node, V2SI_type_node, NULL_TREE);
22813 tree v1di_ftype_v1di_v1di
22814 = build_function_type_list (V1DI_type_node,
22815 V1DI_type_node, V1DI_type_node, NULL_TREE);
22816 tree v1di_ftype_v1di_v1di_int
22817 = build_function_type_list (V1DI_type_node,
22818 V1DI_type_node, V1DI_type_node,
22819 integer_type_node, NULL_TREE);
22820 tree v2si_ftype_v2sf
22821 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22822 tree v2sf_ftype_v2si
22823 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22824 tree v2si_ftype_v2si
22825 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22826 tree v2sf_ftype_v2sf
22827 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22828 tree v2sf_ftype_v2sf_v2sf
22829 = build_function_type_list (V2SF_type_node,
22830 V2SF_type_node, V2SF_type_node, NULL_TREE);
22831 tree v2si_ftype_v2sf_v2sf
22832 = build_function_type_list (V2SI_type_node,
22833 V2SF_type_node, V2SF_type_node, NULL_TREE);
22834 tree pint_type_node = build_pointer_type (integer_type_node);
22835 tree pdouble_type_node = build_pointer_type (double_type_node);
22836 tree pcdouble_type_node = build_pointer_type (
22837 build_type_variant (double_type_node, 1, 0));
22838 tree int_ftype_v2df_v2df
22839 = build_function_type_list (integer_type_node,
22840 V2DF_type_node, V2DF_type_node, NULL_TREE);
22842 tree void_ftype_pcvoid
22843 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22844 tree v4sf_ftype_v4si
22845 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22846 tree v4si_ftype_v4sf
22847 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22848 tree v2df_ftype_v4si
22849 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22850 tree v4si_ftype_v2df
22851 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22852 tree v4si_ftype_v2df_v2df
22853 = build_function_type_list (V4SI_type_node,
22854 V2DF_type_node, V2DF_type_node, NULL_TREE);
22855 tree v2si_ftype_v2df
22856 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22857 tree v4sf_ftype_v2df
22858 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22859 tree v2df_ftype_v2si
22860 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22861 tree v2df_ftype_v4sf
22862 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22863 tree int_ftype_v2df
22864 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22865 tree int64_ftype_v2df
22866 = build_function_type_list (long_long_integer_type_node,
22867 V2DF_type_node, NULL_TREE);
22868 tree v2df_ftype_v2df_int
22869 = build_function_type_list (V2DF_type_node,
22870 V2DF_type_node, integer_type_node, NULL_TREE);
22871 tree v2df_ftype_v2df_int64
22872 = build_function_type_list (V2DF_type_node,
22873 V2DF_type_node, long_long_integer_type_node,
22875 tree v4sf_ftype_v4sf_v2df
22876 = build_function_type_list (V4SF_type_node,
22877 V4SF_type_node, V2DF_type_node, NULL_TREE);
22878 tree v2df_ftype_v2df_v4sf
22879 = build_function_type_list (V2DF_type_node,
22880 V2DF_type_node, V4SF_type_node, NULL_TREE);
22881 tree v2df_ftype_v2df_v2df_int
22882 = build_function_type_list (V2DF_type_node,
22883 V2DF_type_node, V2DF_type_node,
22886 tree v2df_ftype_v2df_pcdouble
22887 = build_function_type_list (V2DF_type_node,
22888 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22889 tree void_ftype_pdouble_v2df
22890 = build_function_type_list (void_type_node,
22891 pdouble_type_node, V2DF_type_node, NULL_TREE);
22892 tree void_ftype_pint_int
22893 = build_function_type_list (void_type_node,
22894 pint_type_node, integer_type_node, NULL_TREE);
22895 tree void_ftype_v16qi_v16qi_pchar
22896 = build_function_type_list (void_type_node,
22897 V16QI_type_node, V16QI_type_node,
22898 pchar_type_node, NULL_TREE);
22899 tree v2df_ftype_pcdouble
22900 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22901 tree v2df_ftype_v2df_v2df
22902 = build_function_type_list (V2DF_type_node,
22903 V2DF_type_node, V2DF_type_node, NULL_TREE);
22904 tree v16qi_ftype_v16qi_v16qi
22905 = build_function_type_list (V16QI_type_node,
22906 V16QI_type_node, V16QI_type_node, NULL_TREE);
22907 tree v8hi_ftype_v8hi_v8hi
22908 = build_function_type_list (V8HI_type_node,
22909 V8HI_type_node, V8HI_type_node, NULL_TREE);
22910 tree v4si_ftype_v4si_v4si
22911 = build_function_type_list (V4SI_type_node,
22912 V4SI_type_node, V4SI_type_node, NULL_TREE);
22913 tree v2di_ftype_v2di_v2di
22914 = build_function_type_list (V2DI_type_node,
22915 V2DI_type_node, V2DI_type_node, NULL_TREE);
22916 tree v2di_ftype_v2df_v2df
22917 = build_function_type_list (V2DI_type_node,
22918 V2DF_type_node, V2DF_type_node, NULL_TREE);
22919 tree v2df_ftype_v2df
22920 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22921 tree v2di_ftype_v2di_int
22922 = build_function_type_list (V2DI_type_node,
22923 V2DI_type_node, integer_type_node, NULL_TREE);
22924 tree v2di_ftype_v2di_v2di_int
22925 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22926 V2DI_type_node, integer_type_node, NULL_TREE);
22927 tree v4si_ftype_v4si_int
22928 = build_function_type_list (V4SI_type_node,
22929 V4SI_type_node, integer_type_node, NULL_TREE);
22930 tree v8hi_ftype_v8hi_int
22931 = build_function_type_list (V8HI_type_node,
22932 V8HI_type_node, integer_type_node, NULL_TREE);
22933 tree v4si_ftype_v8hi_v8hi
22934 = build_function_type_list (V4SI_type_node,
22935 V8HI_type_node, V8HI_type_node, NULL_TREE);
22936 tree v1di_ftype_v8qi_v8qi
22937 = build_function_type_list (V1DI_type_node,
22938 V8QI_type_node, V8QI_type_node, NULL_TREE);
22939 tree v1di_ftype_v2si_v2si
22940 = build_function_type_list (V1DI_type_node,
22941 V2SI_type_node, V2SI_type_node, NULL_TREE);
22942 tree v2di_ftype_v16qi_v16qi
22943 = build_function_type_list (V2DI_type_node,
22944 V16QI_type_node, V16QI_type_node, NULL_TREE);
22945 tree v2di_ftype_v4si_v4si
22946 = build_function_type_list (V2DI_type_node,
22947 V4SI_type_node, V4SI_type_node, NULL_TREE);
22948 tree int_ftype_v16qi
22949 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22950 tree v16qi_ftype_pcchar
22951 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22952 tree void_ftype_pchar_v16qi
22953 = build_function_type_list (void_type_node,
22954 pchar_type_node, V16QI_type_node, NULL_TREE);
22956 tree v2di_ftype_v2di_unsigned_unsigned
22957 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22958 unsigned_type_node, unsigned_type_node,
22960 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22961 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22962 unsigned_type_node, unsigned_type_node,
22964 tree v2di_ftype_v2di_v16qi
22965 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22967 tree v2df_ftype_v2df_v2df_v2df
22968 = build_function_type_list (V2DF_type_node,
22969 V2DF_type_node, V2DF_type_node,
22970 V2DF_type_node, NULL_TREE);
22971 tree v4sf_ftype_v4sf_v4sf_v4sf
22972 = build_function_type_list (V4SF_type_node,
22973 V4SF_type_node, V4SF_type_node,
22974 V4SF_type_node, NULL_TREE);
22975 tree v8hi_ftype_v16qi
22976 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22978 tree v4si_ftype_v16qi
22979 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22981 tree v2di_ftype_v16qi
22982 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22984 tree v4si_ftype_v8hi
22985 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22987 tree v2di_ftype_v8hi
22988 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22990 tree v2di_ftype_v4si
22991 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22993 tree v2di_ftype_pv2di
22994 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22996 tree v16qi_ftype_v16qi_v16qi_int
22997 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22998 V16QI_type_node, integer_type_node,
23000 tree v16qi_ftype_v16qi_v16qi_v16qi
23001 = build_function_type_list (V16QI_type_node, V16QI_type_node,
23002 V16QI_type_node, V16QI_type_node,
23004 tree v8hi_ftype_v8hi_v8hi_int
23005 = build_function_type_list (V8HI_type_node, V8HI_type_node,
23006 V8HI_type_node, integer_type_node,
23008 tree v4si_ftype_v4si_v4si_int
23009 = build_function_type_list (V4SI_type_node, V4SI_type_node,
23010 V4SI_type_node, integer_type_node,
23012 tree int_ftype_v2di_v2di
23013 = build_function_type_list (integer_type_node,
23014 V2DI_type_node, V2DI_type_node,
23016 tree int_ftype_v16qi_int_v16qi_int_int
23017 = build_function_type_list (integer_type_node,
23024 tree v16qi_ftype_v16qi_int_v16qi_int_int
23025 = build_function_type_list (V16QI_type_node,
23032 tree int_ftype_v16qi_v16qi_int
23033 = build_function_type_list (integer_type_node,
23039 /* SSE5 instructions */
23040 tree v2di_ftype_v2di_v2di_v2di
23041 = build_function_type_list (V2DI_type_node,
23047 tree v4si_ftype_v4si_v4si_v4si
23048 = build_function_type_list (V4SI_type_node,
23054 tree v4si_ftype_v4si_v4si_v2di
23055 = build_function_type_list (V4SI_type_node,
23061 tree v8hi_ftype_v8hi_v8hi_v8hi
23062 = build_function_type_list (V8HI_type_node,
23068 tree v8hi_ftype_v8hi_v8hi_v4si
23069 = build_function_type_list (V8HI_type_node,
23075 tree v2df_ftype_v2df_v2df_v16qi
23076 = build_function_type_list (V2DF_type_node,
23082 tree v4sf_ftype_v4sf_v4sf_v16qi
23083 = build_function_type_list (V4SF_type_node,
23089 tree v2di_ftype_v2di_si
23090 = build_function_type_list (V2DI_type_node,
23095 tree v4si_ftype_v4si_si
23096 = build_function_type_list (V4SI_type_node,
23101 tree v8hi_ftype_v8hi_si
23102 = build_function_type_list (V8HI_type_node,
23107 tree v16qi_ftype_v16qi_si
23108 = build_function_type_list (V16QI_type_node,
23112 tree v4sf_ftype_v4hi
23113 = build_function_type_list (V4SF_type_node,
23117 tree v4hi_ftype_v4sf
23118 = build_function_type_list (V4HI_type_node,
23122 tree v2di_ftype_v2di
23123 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
23125 tree v16qi_ftype_v8hi_v8hi
23126 = build_function_type_list (V16QI_type_node,
23127 V8HI_type_node, V8HI_type_node,
23129 tree v8hi_ftype_v4si_v4si
23130 = build_function_type_list (V8HI_type_node,
23131 V4SI_type_node, V4SI_type_node,
23133 tree v8hi_ftype_v16qi_v16qi
23134 = build_function_type_list (V8HI_type_node,
23135 V16QI_type_node, V16QI_type_node,
23137 tree v4hi_ftype_v8qi_v8qi
23138 = build_function_type_list (V4HI_type_node,
23139 V8QI_type_node, V8QI_type_node,
23141 tree unsigned_ftype_unsigned_uchar
23142 = build_function_type_list (unsigned_type_node,
23143 unsigned_type_node,
23144 unsigned_char_type_node,
23146 tree unsigned_ftype_unsigned_ushort
23147 = build_function_type_list (unsigned_type_node,
23148 unsigned_type_node,
23149 short_unsigned_type_node,
23151 tree unsigned_ftype_unsigned_unsigned
23152 = build_function_type_list (unsigned_type_node,
23153 unsigned_type_node,
23154 unsigned_type_node,
23156 tree uint64_ftype_uint64_uint64
23157 = build_function_type_list (long_long_unsigned_type_node,
23158 long_long_unsigned_type_node,
23159 long_long_unsigned_type_node,
23161 tree float_ftype_float
23162 = build_function_type_list (float_type_node,
23167 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
23169 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
23171 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
23173 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
23175 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
23177 tree v8sf_ftype_v8sf
23178 = build_function_type_list (V8SF_type_node,
23181 tree v8si_ftype_v8sf
23182 = build_function_type_list (V8SI_type_node,
23185 tree v8sf_ftype_v8si
23186 = build_function_type_list (V8SF_type_node,
23189 tree v4si_ftype_v4df
23190 = build_function_type_list (V4SI_type_node,
23193 tree v4df_ftype_v4df
23194 = build_function_type_list (V4DF_type_node,
23197 tree v4df_ftype_v4si
23198 = build_function_type_list (V4DF_type_node,
23201 tree v4df_ftype_v4sf
23202 = build_function_type_list (V4DF_type_node,
23205 tree v4sf_ftype_v4df
23206 = build_function_type_list (V4SF_type_node,
23209 tree v8sf_ftype_v8sf_v8sf
23210 = build_function_type_list (V8SF_type_node,
23211 V8SF_type_node, V8SF_type_node,
23213 tree v4df_ftype_v4df_v4df
23214 = build_function_type_list (V4DF_type_node,
23215 V4DF_type_node, V4DF_type_node,
23217 tree v8sf_ftype_v8sf_int
23218 = build_function_type_list (V8SF_type_node,
23219 V8SF_type_node, integer_type_node,
23221 tree v4si_ftype_v8si_int
23222 = build_function_type_list (V4SI_type_node,
23223 V8SI_type_node, integer_type_node,
23225 tree v4df_ftype_v4df_int
23226 = build_function_type_list (V4DF_type_node,
23227 V4DF_type_node, integer_type_node,
23229 tree v4sf_ftype_v8sf_int
23230 = build_function_type_list (V4SF_type_node,
23231 V8SF_type_node, integer_type_node,
23233 tree v2df_ftype_v4df_int
23234 = build_function_type_list (V2DF_type_node,
23235 V4DF_type_node, integer_type_node,
23237 tree v8sf_ftype_v8sf_v8sf_int
23238 = build_function_type_list (V8SF_type_node,
23239 V8SF_type_node, V8SF_type_node,
23242 tree v8sf_ftype_v8sf_v8sf_v8sf
23243 = build_function_type_list (V8SF_type_node,
23244 V8SF_type_node, V8SF_type_node,
23247 tree v4df_ftype_v4df_v4df_v4df
23248 = build_function_type_list (V4DF_type_node,
23249 V4DF_type_node, V4DF_type_node,
23252 tree v8si_ftype_v8si_v8si_int
23253 = build_function_type_list (V8SI_type_node,
23254 V8SI_type_node, V8SI_type_node,
23257 tree v4df_ftype_v4df_v4df_int
23258 = build_function_type_list (V4DF_type_node,
23259 V4DF_type_node, V4DF_type_node,
23262 tree v8sf_ftype_pcfloat
23263 = build_function_type_list (V8SF_type_node,
23266 tree v4df_ftype_pcdouble
23267 = build_function_type_list (V4DF_type_node,
23268 pcdouble_type_node,
23270 tree pcv4sf_type_node
23271 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
23272 tree pcv2df_type_node
23273 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
23274 tree v8sf_ftype_pcv4sf
23275 = build_function_type_list (V8SF_type_node,
23278 tree v4df_ftype_pcv2df
23279 = build_function_type_list (V4DF_type_node,
23282 tree v32qi_ftype_pcchar
23283 = build_function_type_list (V32QI_type_node,
23286 tree void_ftype_pchar_v32qi
23287 = build_function_type_list (void_type_node,
23288 pchar_type_node, V32QI_type_node,
23290 tree v8si_ftype_v8si_v4si_int
23291 = build_function_type_list (V8SI_type_node,
23292 V8SI_type_node, V4SI_type_node,
23295 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
23296 tree void_ftype_pv4di_v4di
23297 = build_function_type_list (void_type_node,
23298 pv4di_type_node, V4DI_type_node,
23300 tree v8sf_ftype_v8sf_v4sf_int
23301 = build_function_type_list (V8SF_type_node,
23302 V8SF_type_node, V4SF_type_node,
23305 tree v4df_ftype_v4df_v2df_int
23306 = build_function_type_list (V4DF_type_node,
23307 V4DF_type_node, V2DF_type_node,
23310 tree void_ftype_pfloat_v8sf
23311 = build_function_type_list (void_type_node,
23312 pfloat_type_node, V8SF_type_node,
23314 tree void_ftype_pdouble_v4df
23315 = build_function_type_list (void_type_node,
23316 pdouble_type_node, V4DF_type_node,
23318 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
23319 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
23320 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
23321 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
23322 tree pcv8sf_type_node
23323 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
23324 tree pcv4df_type_node
23325 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
23326 tree v8sf_ftype_pcv8sf_v8sf
23327 = build_function_type_list (V8SF_type_node,
23328 pcv8sf_type_node, V8SF_type_node,
23330 tree v4df_ftype_pcv4df_v4df
23331 = build_function_type_list (V4DF_type_node,
23332 pcv4df_type_node, V4DF_type_node,
23334 tree v4sf_ftype_pcv4sf_v4sf
23335 = build_function_type_list (V4SF_type_node,
23336 pcv4sf_type_node, V4SF_type_node,
23338 tree v2df_ftype_pcv2df_v2df
23339 = build_function_type_list (V2DF_type_node,
23340 pcv2df_type_node, V2DF_type_node,
23342 tree void_ftype_pv8sf_v8sf_v8sf
23343 = build_function_type_list (void_type_node,
23344 pv8sf_type_node, V8SF_type_node,
23347 tree void_ftype_pv4df_v4df_v4df
23348 = build_function_type_list (void_type_node,
23349 pv4df_type_node, V4DF_type_node,
23352 tree void_ftype_pv4sf_v4sf_v4sf
23353 = build_function_type_list (void_type_node,
23354 pv4sf_type_node, V4SF_type_node,
23357 tree void_ftype_pv2df_v2df_v2df
23358 = build_function_type_list (void_type_node,
23359 pv2df_type_node, V2DF_type_node,
23362 tree v4df_ftype_v2df
23363 = build_function_type_list (V4DF_type_node,
23366 tree v8sf_ftype_v4sf
23367 = build_function_type_list (V8SF_type_node,
23370 tree v8si_ftype_v4si
23371 = build_function_type_list (V8SI_type_node,
23374 tree v2df_ftype_v4df
23375 = build_function_type_list (V2DF_type_node,
23378 tree v4sf_ftype_v8sf
23379 = build_function_type_list (V4SF_type_node,
23382 tree v4si_ftype_v8si
23383 = build_function_type_list (V4SI_type_node,
23386 tree int_ftype_v4df
23387 = build_function_type_list (integer_type_node,
23390 tree int_ftype_v8sf
23391 = build_function_type_list (integer_type_node,
23394 tree int_ftype_v8sf_v8sf
23395 = build_function_type_list (integer_type_node,
23396 V8SF_type_node, V8SF_type_node,
23398 tree int_ftype_v4di_v4di
23399 = build_function_type_list (integer_type_node,
23400 V4DI_type_node, V4DI_type_node,
23402 tree int_ftype_v4df_v4df
23403 = build_function_type_list (integer_type_node,
23404 V4DF_type_node, V4DF_type_node,
23406 tree v8sf_ftype_v8sf_v8si
23407 = build_function_type_list (V8SF_type_node,
23408 V8SF_type_node, V8SI_type_node,
23410 tree v4df_ftype_v4df_v4di
23411 = build_function_type_list (V4DF_type_node,
23412 V4DF_type_node, V4DI_type_node,
23414 tree v4sf_ftype_v4sf_v4si
23415 = build_function_type_list (V4SF_type_node,
23416 V4SF_type_node, V4SI_type_node, NULL_TREE);
23417 tree v2df_ftype_v2df_v2di
23418 = build_function_type_list (V2DF_type_node,
23419 V2DF_type_node, V2DI_type_node, NULL_TREE);
23421 /* Integer intrinsics. */
23422 tree uint64_ftype_void
23423 = build_function_type (long_long_unsigned_type_node,
23426 = build_function_type_list (integer_type_node,
23427 integer_type_node, NULL_TREE);
23428 tree int64_ftype_int64
23429 = build_function_type_list (long_long_integer_type_node,
23430 long_long_integer_type_node,
23432 tree uint64_ftype_int
23433 = build_function_type_list (long_long_unsigned_type_node,
23434 integer_type_node, NULL_TREE);
23435 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
23436 tree uint64_ftype_punsigned
23437 = build_function_type_list (long_long_unsigned_type_node,
23438 punsigned_type_node, NULL_TREE);
23439 tree ushort_ftype_ushort_int
23440 = build_function_type_list (short_unsigned_type_node,
23441 short_unsigned_type_node,
23444 tree uchar_ftype_uchar_int
23445 = build_function_type_list (unsigned_char_type_node,
23446 unsigned_char_type_node,
23452 /* Add all special builtins with variable number of operands. */
23453 for (i = 0, d = bdesc_special_args;
23454 i < ARRAY_SIZE (bdesc_special_args);
23462 switch ((enum ix86_special_builtin_type) d->flag)
23464 case VOID_FTYPE_VOID:
23465 type = void_ftype_void;
23467 case UINT64_FTYPE_VOID:
23468 type = uint64_ftype_void;
23470 case UINT64_FTYPE_PUNSIGNED:
23471 type = uint64_ftype_punsigned;
23473 case V32QI_FTYPE_PCCHAR:
23474 type = v32qi_ftype_pcchar;
23476 case V16QI_FTYPE_PCCHAR:
23477 type = v16qi_ftype_pcchar;
23479 case V8SF_FTYPE_PCV4SF:
23480 type = v8sf_ftype_pcv4sf;
23482 case V8SF_FTYPE_PCFLOAT:
23483 type = v8sf_ftype_pcfloat;
23485 case V4DF_FTYPE_PCV2DF:
23486 type = v4df_ftype_pcv2df;
23488 case V4DF_FTYPE_PCDOUBLE:
23489 type = v4df_ftype_pcdouble;
23491 case V4SF_FTYPE_PCFLOAT:
23492 type = v4sf_ftype_pcfloat;
23494 case V2DI_FTYPE_PV2DI:
23495 type = v2di_ftype_pv2di;
23497 case V2DF_FTYPE_PCDOUBLE:
23498 type = v2df_ftype_pcdouble;
23500 case V8SF_FTYPE_PCV8SF_V8SF:
23501 type = v8sf_ftype_pcv8sf_v8sf;
23503 case V4DF_FTYPE_PCV4DF_V4DF:
23504 type = v4df_ftype_pcv4df_v4df;
23506 case V4SF_FTYPE_V4SF_PCV2SF:
23507 type = v4sf_ftype_v4sf_pcv2sf;
23509 case V4SF_FTYPE_PCV4SF_V4SF:
23510 type = v4sf_ftype_pcv4sf_v4sf;
23512 case V2DF_FTYPE_V2DF_PCDOUBLE:
23513 type = v2df_ftype_v2df_pcdouble;
23515 case V2DF_FTYPE_PCV2DF_V2DF:
23516 type = v2df_ftype_pcv2df_v2df;
23518 case VOID_FTYPE_PV2SF_V4SF:
23519 type = void_ftype_pv2sf_v4sf;
23521 case VOID_FTYPE_PV4DI_V4DI:
23522 type = void_ftype_pv4di_v4di;
23524 case VOID_FTYPE_PV2DI_V2DI:
23525 type = void_ftype_pv2di_v2di;
23527 case VOID_FTYPE_PCHAR_V32QI:
23528 type = void_ftype_pchar_v32qi;
23530 case VOID_FTYPE_PCHAR_V16QI:
23531 type = void_ftype_pchar_v16qi;
23533 case VOID_FTYPE_PFLOAT_V8SF:
23534 type = void_ftype_pfloat_v8sf;
23536 case VOID_FTYPE_PFLOAT_V4SF:
23537 type = void_ftype_pfloat_v4sf;
23539 case VOID_FTYPE_PDOUBLE_V4DF:
23540 type = void_ftype_pdouble_v4df;
23542 case VOID_FTYPE_PDOUBLE_V2DF:
23543 type = void_ftype_pdouble_v2df;
23545 case VOID_FTYPE_PDI_DI:
23546 type = void_ftype_pdi_di;
23548 case VOID_FTYPE_PINT_INT:
23549 type = void_ftype_pint_int;
23551 case VOID_FTYPE_PV8SF_V8SF_V8SF:
23552 type = void_ftype_pv8sf_v8sf_v8sf;
23554 case VOID_FTYPE_PV4DF_V4DF_V4DF:
23555 type = void_ftype_pv4df_v4df_v4df;
23557 case VOID_FTYPE_PV4SF_V4SF_V4SF:
23558 type = void_ftype_pv4sf_v4sf_v4sf;
23560 case VOID_FTYPE_PV2DF_V2DF_V2DF:
23561 type = void_ftype_pv2df_v2df_v2df;
23564 gcc_unreachable ();
23567 def_builtin (d->mask, d->name, type, d->code);
23570 /* Add all builtins with variable number of operands. */
23571 for (i = 0, d = bdesc_args;
23572 i < ARRAY_SIZE (bdesc_args);
23580 switch ((enum ix86_builtin_type) d->flag)
23582 case FLOAT_FTYPE_FLOAT:
23583 type = float_ftype_float;
23585 case INT_FTYPE_V8SF_V8SF_PTEST:
23586 type = int_ftype_v8sf_v8sf;
23588 case INT_FTYPE_V4DI_V4DI_PTEST:
23589 type = int_ftype_v4di_v4di;
23591 case INT_FTYPE_V4DF_V4DF_PTEST:
23592 type = int_ftype_v4df_v4df;
23594 case INT_FTYPE_V4SF_V4SF_PTEST:
23595 type = int_ftype_v4sf_v4sf;
23597 case INT_FTYPE_V2DI_V2DI_PTEST:
23598 type = int_ftype_v2di_v2di;
23600 case INT_FTYPE_V2DF_V2DF_PTEST:
23601 type = int_ftype_v2df_v2df;
23603 case INT_FTYPE_INT:
23604 type = int_ftype_int;
23606 case UINT64_FTYPE_INT:
23607 type = uint64_ftype_int;
23609 case INT64_FTYPE_INT64:
23610 type = int64_ftype_int64;
23612 case INT64_FTYPE_V4SF:
23613 type = int64_ftype_v4sf;
23615 case INT64_FTYPE_V2DF:
23616 type = int64_ftype_v2df;
23618 case INT_FTYPE_V16QI:
23619 type = int_ftype_v16qi;
23621 case INT_FTYPE_V8QI:
23622 type = int_ftype_v8qi;
23624 case INT_FTYPE_V8SF:
23625 type = int_ftype_v8sf;
23627 case INT_FTYPE_V4DF:
23628 type = int_ftype_v4df;
23630 case INT_FTYPE_V4SF:
23631 type = int_ftype_v4sf;
23633 case INT_FTYPE_V2DF:
23634 type = int_ftype_v2df;
23636 case V16QI_FTYPE_V16QI:
23637 type = v16qi_ftype_v16qi;
23639 case V8SI_FTYPE_V8SF:
23640 type = v8si_ftype_v8sf;
23642 case V8SI_FTYPE_V4SI:
23643 type = v8si_ftype_v4si;
23645 case V8HI_FTYPE_V8HI:
23646 type = v8hi_ftype_v8hi;
23648 case V8HI_FTYPE_V16QI:
23649 type = v8hi_ftype_v16qi;
23651 case V8QI_FTYPE_V8QI:
23652 type = v8qi_ftype_v8qi;
23654 case V8SF_FTYPE_V8SF:
23655 type = v8sf_ftype_v8sf;
23657 case V8SF_FTYPE_V8SI:
23658 type = v8sf_ftype_v8si;
23660 case V8SF_FTYPE_V4SF:
23661 type = v8sf_ftype_v4sf;
23663 case V4SI_FTYPE_V4DF:
23664 type = v4si_ftype_v4df;
23666 case V4SI_FTYPE_V4SI:
23667 type = v4si_ftype_v4si;
23669 case V4SI_FTYPE_V16QI:
23670 type = v4si_ftype_v16qi;
23672 case V4SI_FTYPE_V8SI:
23673 type = v4si_ftype_v8si;
23675 case V4SI_FTYPE_V8HI:
23676 type = v4si_ftype_v8hi;
23678 case V4SI_FTYPE_V4SF:
23679 type = v4si_ftype_v4sf;
23681 case V4SI_FTYPE_V2DF:
23682 type = v4si_ftype_v2df;
23684 case V4HI_FTYPE_V4HI:
23685 type = v4hi_ftype_v4hi;
23687 case V4DF_FTYPE_V4DF:
23688 type = v4df_ftype_v4df;
23690 case V4DF_FTYPE_V4SI:
23691 type = v4df_ftype_v4si;
23693 case V4DF_FTYPE_V4SF:
23694 type = v4df_ftype_v4sf;
23696 case V4DF_FTYPE_V2DF:
23697 type = v4df_ftype_v2df;
23699 case V4SF_FTYPE_V4SF:
23700 case V4SF_FTYPE_V4SF_VEC_MERGE:
23701 type = v4sf_ftype_v4sf;
23703 case V4SF_FTYPE_V8SF:
23704 type = v4sf_ftype_v8sf;
23706 case V4SF_FTYPE_V4SI:
23707 type = v4sf_ftype_v4si;
23709 case V4SF_FTYPE_V4DF:
23710 type = v4sf_ftype_v4df;
23712 case V4SF_FTYPE_V2DF:
23713 type = v4sf_ftype_v2df;
23715 case V2DI_FTYPE_V2DI:
23716 type = v2di_ftype_v2di;
23718 case V2DI_FTYPE_V16QI:
23719 type = v2di_ftype_v16qi;
23721 case V2DI_FTYPE_V8HI:
23722 type = v2di_ftype_v8hi;
23724 case V2DI_FTYPE_V4SI:
23725 type = v2di_ftype_v4si;
23727 case V2SI_FTYPE_V2SI:
23728 type = v2si_ftype_v2si;
23730 case V2SI_FTYPE_V4SF:
23731 type = v2si_ftype_v4sf;
23733 case V2SI_FTYPE_V2DF:
23734 type = v2si_ftype_v2df;
23736 case V2SI_FTYPE_V2SF:
23737 type = v2si_ftype_v2sf;
23739 case V2DF_FTYPE_V4DF:
23740 type = v2df_ftype_v4df;
23742 case V2DF_FTYPE_V4SF:
23743 type = v2df_ftype_v4sf;
23745 case V2DF_FTYPE_V2DF:
23746 case V2DF_FTYPE_V2DF_VEC_MERGE:
23747 type = v2df_ftype_v2df;
23749 case V2DF_FTYPE_V2SI:
23750 type = v2df_ftype_v2si;
23752 case V2DF_FTYPE_V4SI:
23753 type = v2df_ftype_v4si;
23755 case V2SF_FTYPE_V2SF:
23756 type = v2sf_ftype_v2sf;
23758 case V2SF_FTYPE_V2SI:
23759 type = v2sf_ftype_v2si;
23761 case V16QI_FTYPE_V16QI_V16QI:
23762 type = v16qi_ftype_v16qi_v16qi;
23764 case V16QI_FTYPE_V8HI_V8HI:
23765 type = v16qi_ftype_v8hi_v8hi;
23767 case V8QI_FTYPE_V8QI_V8QI:
23768 type = v8qi_ftype_v8qi_v8qi;
23770 case V8QI_FTYPE_V4HI_V4HI:
23771 type = v8qi_ftype_v4hi_v4hi;
23773 case V8HI_FTYPE_V8HI_V8HI:
23774 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23775 type = v8hi_ftype_v8hi_v8hi;
23777 case V8HI_FTYPE_V16QI_V16QI:
23778 type = v8hi_ftype_v16qi_v16qi;
23780 case V8HI_FTYPE_V4SI_V4SI:
23781 type = v8hi_ftype_v4si_v4si;
23783 case V8HI_FTYPE_V8HI_SI_COUNT:
23784 type = v8hi_ftype_v8hi_int;
23786 case V8SF_FTYPE_V8SF_V8SF:
23787 type = v8sf_ftype_v8sf_v8sf;
23789 case V8SF_FTYPE_V8SF_V8SI:
23790 type = v8sf_ftype_v8sf_v8si;
23792 case V4SI_FTYPE_V4SI_V4SI:
23793 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23794 type = v4si_ftype_v4si_v4si;
23796 case V4SI_FTYPE_V8HI_V8HI:
23797 type = v4si_ftype_v8hi_v8hi;
23799 case V4SI_FTYPE_V4SF_V4SF:
23800 type = v4si_ftype_v4sf_v4sf;
23802 case V4SI_FTYPE_V2DF_V2DF:
23803 type = v4si_ftype_v2df_v2df;
23805 case V4SI_FTYPE_V4SI_SI_COUNT:
23806 type = v4si_ftype_v4si_int;
23808 case V4HI_FTYPE_V4HI_V4HI:
23809 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23810 type = v4hi_ftype_v4hi_v4hi;
23812 case V4HI_FTYPE_V8QI_V8QI:
23813 type = v4hi_ftype_v8qi_v8qi;
23815 case V4HI_FTYPE_V2SI_V2SI:
23816 type = v4hi_ftype_v2si_v2si;
23818 case V4HI_FTYPE_V4HI_SI_COUNT:
23819 type = v4hi_ftype_v4hi_int;
23821 case V4DF_FTYPE_V4DF_V4DF:
23822 type = v4df_ftype_v4df_v4df;
23824 case V4DF_FTYPE_V4DF_V4DI:
23825 type = v4df_ftype_v4df_v4di;
23827 case V4SF_FTYPE_V4SF_V4SF:
23828 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23829 type = v4sf_ftype_v4sf_v4sf;
23831 case V4SF_FTYPE_V4SF_V4SI:
23832 type = v4sf_ftype_v4sf_v4si;
23834 case V4SF_FTYPE_V4SF_V2SI:
23835 type = v4sf_ftype_v4sf_v2si;
23837 case V4SF_FTYPE_V4SF_V2DF:
23838 type = v4sf_ftype_v4sf_v2df;
23840 case V4SF_FTYPE_V4SF_DI:
23841 type = v4sf_ftype_v4sf_int64;
23843 case V4SF_FTYPE_V4SF_SI:
23844 type = v4sf_ftype_v4sf_int;
23846 case V2DI_FTYPE_V2DI_V2DI:
23847 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23848 type = v2di_ftype_v2di_v2di;
23850 case V2DI_FTYPE_V16QI_V16QI:
23851 type = v2di_ftype_v16qi_v16qi;
23853 case V2DI_FTYPE_V4SI_V4SI:
23854 type = v2di_ftype_v4si_v4si;
23856 case V2DI_FTYPE_V2DI_V16QI:
23857 type = v2di_ftype_v2di_v16qi;
23859 case V2DI_FTYPE_V2DF_V2DF:
23860 type = v2di_ftype_v2df_v2df;
23862 case V2DI_FTYPE_V2DI_SI_COUNT:
23863 type = v2di_ftype_v2di_int;
23865 case V2SI_FTYPE_V2SI_V2SI:
23866 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23867 type = v2si_ftype_v2si_v2si;
23869 case V2SI_FTYPE_V4HI_V4HI:
23870 type = v2si_ftype_v4hi_v4hi;
23872 case V2SI_FTYPE_V2SF_V2SF:
23873 type = v2si_ftype_v2sf_v2sf;
23875 case V2SI_FTYPE_V2SI_SI_COUNT:
23876 type = v2si_ftype_v2si_int;
23878 case V2DF_FTYPE_V2DF_V2DF:
23879 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23880 type = v2df_ftype_v2df_v2df;
23882 case V2DF_FTYPE_V2DF_V4SF:
23883 type = v2df_ftype_v2df_v4sf;
23885 case V2DF_FTYPE_V2DF_V2DI:
23886 type = v2df_ftype_v2df_v2di;
23888 case V2DF_FTYPE_V2DF_DI:
23889 type = v2df_ftype_v2df_int64;
23891 case V2DF_FTYPE_V2DF_SI:
23892 type = v2df_ftype_v2df_int;
23894 case V2SF_FTYPE_V2SF_V2SF:
23895 type = v2sf_ftype_v2sf_v2sf;
23897 case V1DI_FTYPE_V1DI_V1DI:
23898 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23899 type = v1di_ftype_v1di_v1di;
23901 case V1DI_FTYPE_V8QI_V8QI:
23902 type = v1di_ftype_v8qi_v8qi;
23904 case V1DI_FTYPE_V2SI_V2SI:
23905 type = v1di_ftype_v2si_v2si;
23907 case V1DI_FTYPE_V1DI_SI_COUNT:
23908 type = v1di_ftype_v1di_int;
23910 case UINT64_FTYPE_UINT64_UINT64:
23911 type = uint64_ftype_uint64_uint64;
23913 case UINT_FTYPE_UINT_UINT:
23914 type = unsigned_ftype_unsigned_unsigned;
23916 case UINT_FTYPE_UINT_USHORT:
23917 type = unsigned_ftype_unsigned_ushort;
23919 case UINT_FTYPE_UINT_UCHAR:
23920 type = unsigned_ftype_unsigned_uchar;
23922 case UINT16_FTYPE_UINT16_INT:
23923 type = ushort_ftype_ushort_int;
23925 case UINT8_FTYPE_UINT8_INT:
23926 type = uchar_ftype_uchar_int;
23928 case V8HI_FTYPE_V8HI_INT:
23929 type = v8hi_ftype_v8hi_int;
23931 case V8SF_FTYPE_V8SF_INT:
23932 type = v8sf_ftype_v8sf_int;
23934 case V4SI_FTYPE_V4SI_INT:
23935 type = v4si_ftype_v4si_int;
23937 case V4SI_FTYPE_V8SI_INT:
23938 type = v4si_ftype_v8si_int;
23940 case V4HI_FTYPE_V4HI_INT:
23941 type = v4hi_ftype_v4hi_int;
23943 case V4DF_FTYPE_V4DF_INT:
23944 type = v4df_ftype_v4df_int;
23946 case V4SF_FTYPE_V4SF_INT:
23947 type = v4sf_ftype_v4sf_int;
23949 case V4SF_FTYPE_V8SF_INT:
23950 type = v4sf_ftype_v8sf_int;
23952 case V2DI_FTYPE_V2DI_INT:
23953 case V2DI2TI_FTYPE_V2DI_INT:
23954 type = v2di_ftype_v2di_int;
23956 case V2DF_FTYPE_V2DF_INT:
23957 type = v2df_ftype_v2df_int;
23959 case V2DF_FTYPE_V4DF_INT:
23960 type = v2df_ftype_v4df_int;
23962 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23963 type = v16qi_ftype_v16qi_v16qi_v16qi;
23965 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23966 type = v8sf_ftype_v8sf_v8sf_v8sf;
23968 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23969 type = v4df_ftype_v4df_v4df_v4df;
23971 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23972 type = v4sf_ftype_v4sf_v4sf_v4sf;
23974 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23975 type = v2df_ftype_v2df_v2df_v2df;
23977 case V16QI_FTYPE_V16QI_V16QI_INT:
23978 type = v16qi_ftype_v16qi_v16qi_int;
23980 case V8SI_FTYPE_V8SI_V8SI_INT:
23981 type = v8si_ftype_v8si_v8si_int;
23983 case V8SI_FTYPE_V8SI_V4SI_INT:
23984 type = v8si_ftype_v8si_v4si_int;
23986 case V8HI_FTYPE_V8HI_V8HI_INT:
23987 type = v8hi_ftype_v8hi_v8hi_int;
23989 case V8SF_FTYPE_V8SF_V8SF_INT:
23990 type = v8sf_ftype_v8sf_v8sf_int;
23992 case V8SF_FTYPE_V8SF_V4SF_INT:
23993 type = v8sf_ftype_v8sf_v4sf_int;
23995 case V4SI_FTYPE_V4SI_V4SI_INT:
23996 type = v4si_ftype_v4si_v4si_int;
23998 case V4DF_FTYPE_V4DF_V4DF_INT:
23999 type = v4df_ftype_v4df_v4df_int;
24001 case V4DF_FTYPE_V4DF_V2DF_INT:
24002 type = v4df_ftype_v4df_v2df_int;
24004 case V4SF_FTYPE_V4SF_V4SF_INT:
24005 type = v4sf_ftype_v4sf_v4sf_int;
24007 case V2DI_FTYPE_V2DI_V2DI_INT:
24008 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24009 type = v2di_ftype_v2di_v2di_int;
24011 case V2DF_FTYPE_V2DF_V2DF_INT:
24012 type = v2df_ftype_v2df_v2df_int;
24014 case V2DI_FTYPE_V2DI_UINT_UINT:
24015 type = v2di_ftype_v2di_unsigned_unsigned;
24017 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24018 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
24020 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24021 type = v1di_ftype_v1di_v1di_int;
24024 gcc_unreachable ();
24027 def_builtin_const (d->mask, d->name, type, d->code);
24030 /* pcmpestr[im] insns. */
24031 for (i = 0, d = bdesc_pcmpestr;
24032 i < ARRAY_SIZE (bdesc_pcmpestr);
24035 if (d->code == IX86_BUILTIN_PCMPESTRM128)
24036 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
24038 ftype = int_ftype_v16qi_int_v16qi_int_int;
24039 def_builtin_const (d->mask, d->name, ftype, d->code);
24042 /* pcmpistr[im] insns. */
24043 for (i = 0, d = bdesc_pcmpistr;
24044 i < ARRAY_SIZE (bdesc_pcmpistr);
24047 if (d->code == IX86_BUILTIN_PCMPISTRM128)
24048 ftype = v16qi_ftype_v16qi_v16qi_int;
24050 ftype = int_ftype_v16qi_v16qi_int;
24051 def_builtin_const (d->mask, d->name, ftype, d->code);
24054 /* comi/ucomi insns. */
24055 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24056 if (d->mask == OPTION_MASK_ISA_SSE2)
24057 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
24059 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
24062 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
24063 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
24065 /* SSE or 3DNow!A */
24066 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
24069 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
24071 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
24072 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
24075 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
24076 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
24079 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
24080 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
24081 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
24082 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
24083 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
24084 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
24087 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
24090 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
24091 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
24093 /* Access to the vec_init patterns. */
24094 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
24095 integer_type_node, NULL_TREE);
24096 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
24098 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
24099 short_integer_type_node,
24100 short_integer_type_node,
24101 short_integer_type_node, NULL_TREE);
24102 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
24104 ftype = build_function_type_list (V8QI_type_node, char_type_node,
24105 char_type_node, char_type_node,
24106 char_type_node, char_type_node,
24107 char_type_node, char_type_node,
24108 char_type_node, NULL_TREE);
24109 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
24111 /* Access to the vec_extract patterns. */
24112 ftype = build_function_type_list (double_type_node, V2DF_type_node,
24113 integer_type_node, NULL_TREE);
24114 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
24116 ftype = build_function_type_list (long_long_integer_type_node,
24117 V2DI_type_node, integer_type_node,
24119 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
24121 ftype = build_function_type_list (float_type_node, V4SF_type_node,
24122 integer_type_node, NULL_TREE);
24123 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
24125 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
24126 integer_type_node, NULL_TREE);
24127 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
24129 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
24130 integer_type_node, NULL_TREE);
24131 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
24133 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
24134 integer_type_node, NULL_TREE);
24135 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
24137 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
24138 integer_type_node, NULL_TREE);
24139 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
24141 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
24142 integer_type_node, NULL_TREE);
24143 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
24145 /* Access to the vec_set patterns. */
24146 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
24148 integer_type_node, NULL_TREE);
24149 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
24151 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
24153 integer_type_node, NULL_TREE);
24154 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
24156 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
24158 integer_type_node, NULL_TREE);
24159 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
24161 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
24163 integer_type_node, NULL_TREE);
24164 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
24166 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
24168 integer_type_node, NULL_TREE);
24169 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
24171 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
24173 integer_type_node, NULL_TREE);
24174 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
24176 /* Add SSE5 multi-arg argument instructions */
24177 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24179 tree mtype = NULL_TREE;
24184 switch ((enum multi_arg_type)d->flag)
24186 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
24187 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
24188 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
24189 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
24190 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
24191 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
24192 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
24193 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
24194 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
24195 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
24196 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
24197 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
24198 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
24199 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
24200 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
24201 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
24202 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
24203 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
24204 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
24205 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
24206 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
24207 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
24208 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
24209 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
24210 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
24211 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
24212 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
24213 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
24214 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
24215 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
24216 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
24217 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
24218 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
24219 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
24220 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
24221 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
24222 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
24223 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
24224 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
24225 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
24226 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
24227 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
24228 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
24229 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
24230 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
24231 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
24232 case MULTI_ARG_UNKNOWN:
24234 gcc_unreachable ();
24238 def_builtin_const (d->mask, d->name, mtype, d->code);
24242 /* Internal method for ix86_init_builtins. */
24245 ix86_init_builtins_va_builtins_abi (void)
24247 tree ms_va_ref, sysv_va_ref;
24248 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
24249 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
24250 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
24251 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
24255 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
24256 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
24257 ms_va_ref = build_reference_type (ms_va_list_type_node);
24259 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
24262 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24263 fnvoid_va_start_ms =
24264 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24265 fnvoid_va_end_sysv =
24266 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
24267 fnvoid_va_start_sysv =
24268 build_varargs_function_type_list (void_type_node, sysv_va_ref,
24270 fnvoid_va_copy_ms =
24271 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
24273 fnvoid_va_copy_sysv =
24274 build_function_type_list (void_type_node, sysv_va_ref,
24275 sysv_va_ref, NULL_TREE);
24277 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
24278 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
24279 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
24280 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
24281 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
24282 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
24283 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
24284 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24285 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
24286 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24287 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
24288 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24292 ix86_init_builtins (void)
24294 tree float128_type_node = make_node (REAL_TYPE);
24297 /* The __float80 type. */
24298 if (TYPE_MODE (long_double_type_node) == XFmode)
24299 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
24303 /* The __float80 type. */
24304 tree float80_type_node = make_node (REAL_TYPE);
24306 TYPE_PRECISION (float80_type_node) = 80;
24307 layout_type (float80_type_node);
24308 (*lang_hooks.types.register_builtin_type) (float80_type_node,
24312 /* The __float128 type. */
24313 TYPE_PRECISION (float128_type_node) = 128;
24314 layout_type (float128_type_node);
24315 (*lang_hooks.types.register_builtin_type) (float128_type_node,
24318 /* TFmode support builtins. */
24319 ftype = build_function_type (float128_type_node, void_list_node);
24320 decl = add_builtin_function ("__builtin_infq", ftype,
24321 IX86_BUILTIN_INFQ, BUILT_IN_MD,
24323 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
24325 decl = add_builtin_function ("__builtin_huge_valq", ftype,
24326 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
24328 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
24330 /* We will expand them to normal call if SSE2 isn't available since
24331 they are used by libgcc. */
24332 ftype = build_function_type_list (float128_type_node,
24333 float128_type_node,
24335 decl = add_builtin_function ("__builtin_fabsq", ftype,
24336 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
24337 "__fabstf2", NULL_TREE);
24338 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
24339 TREE_READONLY (decl) = 1;
24341 ftype = build_function_type_list (float128_type_node,
24342 float128_type_node,
24343 float128_type_node,
24345 decl = add_builtin_function ("__builtin_copysignq", ftype,
24346 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
24347 "__copysigntf3", NULL_TREE);
24348 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
24349 TREE_READONLY (decl) = 1;
24351 ix86_init_mmx_sse_builtins ();
24353 ix86_init_builtins_va_builtins_abi ();
24356 /* Errors in the source file can cause expand_expr to return const0_rtx
24357 where we expect a vector. To avoid crashing, use one of the vector
24358 clear instructions. */
24360 safe_vector_operand (rtx x, enum machine_mode mode)
24362 if (x == const0_rtx)
24363 x = CONST0_RTX (mode);
24367 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
24370 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
24373 tree arg0 = CALL_EXPR_ARG (exp, 0);
24374 tree arg1 = CALL_EXPR_ARG (exp, 1);
24375 rtx op0 = expand_normal (arg0);
24376 rtx op1 = expand_normal (arg1);
24377 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24378 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24379 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
24381 if (VECTOR_MODE_P (mode0))
24382 op0 = safe_vector_operand (op0, mode0);
24383 if (VECTOR_MODE_P (mode1))
24384 op1 = safe_vector_operand (op1, mode1);
24386 if (optimize || !target
24387 || GET_MODE (target) != tmode
24388 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24389 target = gen_reg_rtx (tmode);
24391 if (GET_MODE (op1) == SImode && mode1 == TImode)
24393 rtx x = gen_reg_rtx (V4SImode);
24394 emit_insn (gen_sse2_loadd (x, op1));
24395 op1 = gen_lowpart (TImode, x);
24398 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
24399 op0 = copy_to_mode_reg (mode0, op0);
24400 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
24401 op1 = copy_to_mode_reg (mode1, op1);
24403 pat = GEN_FCN (icode) (target, op0, op1);
24412 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
24415 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
24416 enum multi_arg_type m_type,
24417 enum rtx_code sub_code)
24422 bool comparison_p = false;
24424 bool last_arg_constant = false;
24425 int num_memory = 0;
24428 enum machine_mode mode;
24431 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24435 case MULTI_ARG_3_SF:
24436 case MULTI_ARG_3_DF:
24437 case MULTI_ARG_3_DI:
24438 case MULTI_ARG_3_SI:
24439 case MULTI_ARG_3_SI_DI:
24440 case MULTI_ARG_3_HI:
24441 case MULTI_ARG_3_HI_SI:
24442 case MULTI_ARG_3_QI:
24443 case MULTI_ARG_3_PERMPS:
24444 case MULTI_ARG_3_PERMPD:
24448 case MULTI_ARG_2_SF:
24449 case MULTI_ARG_2_DF:
24450 case MULTI_ARG_2_DI:
24451 case MULTI_ARG_2_SI:
24452 case MULTI_ARG_2_HI:
24453 case MULTI_ARG_2_QI:
24457 case MULTI_ARG_2_DI_IMM:
24458 case MULTI_ARG_2_SI_IMM:
24459 case MULTI_ARG_2_HI_IMM:
24460 case MULTI_ARG_2_QI_IMM:
24462 last_arg_constant = true;
24465 case MULTI_ARG_1_SF:
24466 case MULTI_ARG_1_DF:
24467 case MULTI_ARG_1_DI:
24468 case MULTI_ARG_1_SI:
24469 case MULTI_ARG_1_HI:
24470 case MULTI_ARG_1_QI:
24471 case MULTI_ARG_1_SI_DI:
24472 case MULTI_ARG_1_HI_DI:
24473 case MULTI_ARG_1_HI_SI:
24474 case MULTI_ARG_1_QI_DI:
24475 case MULTI_ARG_1_QI_SI:
24476 case MULTI_ARG_1_QI_HI:
24477 case MULTI_ARG_1_PH2PS:
24478 case MULTI_ARG_1_PS2PH:
24482 case MULTI_ARG_2_SF_CMP:
24483 case MULTI_ARG_2_DF_CMP:
24484 case MULTI_ARG_2_DI_CMP:
24485 case MULTI_ARG_2_SI_CMP:
24486 case MULTI_ARG_2_HI_CMP:
24487 case MULTI_ARG_2_QI_CMP:
24489 comparison_p = true;
24492 case MULTI_ARG_2_SF_TF:
24493 case MULTI_ARG_2_DF_TF:
24494 case MULTI_ARG_2_DI_TF:
24495 case MULTI_ARG_2_SI_TF:
24496 case MULTI_ARG_2_HI_TF:
24497 case MULTI_ARG_2_QI_TF:
24502 case MULTI_ARG_UNKNOWN:
24504 gcc_unreachable ();
24507 if (optimize || !target
24508 || GET_MODE (target) != tmode
24509 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24510 target = gen_reg_rtx (tmode);
24512 gcc_assert (nargs <= 4);
24514 for (i = 0; i < nargs; i++)
24516 tree arg = CALL_EXPR_ARG (exp, i);
24517 rtx op = expand_normal (arg);
24518 int adjust = (comparison_p) ? 1 : 0;
24519 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
24521 if (last_arg_constant && i == nargs-1)
24523 if (!CONST_INT_P (op))
24525 error ("last argument must be an immediate");
24526 return gen_reg_rtx (tmode);
24531 if (VECTOR_MODE_P (mode))
24532 op = safe_vector_operand (op, mode);
24534 /* If we aren't optimizing, only allow one memory operand to be
24536 if (memory_operand (op, mode))
24539 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
24542 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
24544 op = force_reg (mode, op);
24548 args[i].mode = mode;
24554 pat = GEN_FCN (icode) (target, args[0].op);
24559 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
24560 GEN_INT ((int)sub_code));
24561 else if (! comparison_p)
24562 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24565 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
24569 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
24574 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
24578 gcc_unreachable ();
24588 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
24589 insns with vec_merge. */
24592 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
24596 tree arg0 = CALL_EXPR_ARG (exp, 0);
24597 rtx op1, op0 = expand_normal (arg0);
24598 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24599 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24601 if (optimize || !target
24602 || GET_MODE (target) != tmode
24603 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24604 target = gen_reg_rtx (tmode);
24606 if (VECTOR_MODE_P (mode0))
24607 op0 = safe_vector_operand (op0, mode0);
24609 if ((optimize && !register_operand (op0, mode0))
24610 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
24611 op0 = copy_to_mode_reg (mode0, op0);
24614 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
24615 op1 = copy_to_mode_reg (mode0, op1);
24617 pat = GEN_FCN (icode) (target, op0, op1);
24624 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
24627 ix86_expand_sse_compare (const struct builtin_description *d,
24628 tree exp, rtx target, bool swap)
24631 tree arg0 = CALL_EXPR_ARG (exp, 0);
24632 tree arg1 = CALL_EXPR_ARG (exp, 1);
24633 rtx op0 = expand_normal (arg0);
24634 rtx op1 = expand_normal (arg1);
24636 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
24637 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
24638 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
24639 enum rtx_code comparison = d->comparison;
24641 if (VECTOR_MODE_P (mode0))
24642 op0 = safe_vector_operand (op0, mode0);
24643 if (VECTOR_MODE_P (mode1))
24644 op1 = safe_vector_operand (op1, mode1);
24646 /* Swap operands if we have a comparison that isn't available in
24650 rtx tmp = gen_reg_rtx (mode1);
24651 emit_move_insn (tmp, op1);
24656 if (optimize || !target
24657 || GET_MODE (target) != tmode
24658 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
24659 target = gen_reg_rtx (tmode);
24661 if ((optimize && !register_operand (op0, mode0))
24662 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
24663 op0 = copy_to_mode_reg (mode0, op0);
24664 if ((optimize && !register_operand (op1, mode1))
24665 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
24666 op1 = copy_to_mode_reg (mode1, op1);
24668 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
24669 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
24676 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
24679 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
24683 tree arg0 = CALL_EXPR_ARG (exp, 0);
24684 tree arg1 = CALL_EXPR_ARG (exp, 1);
24685 rtx op0 = expand_normal (arg0);
24686 rtx op1 = expand_normal (arg1);
24687 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24688 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24689 enum rtx_code comparison = d->comparison;
24691 if (VECTOR_MODE_P (mode0))
24692 op0 = safe_vector_operand (op0, mode0);
24693 if (VECTOR_MODE_P (mode1))
24694 op1 = safe_vector_operand (op1, mode1);
24696 /* Swap operands if we have a comparison that isn't available in
24698 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
24705 target = gen_reg_rtx (SImode);
24706 emit_move_insn (target, const0_rtx);
24707 target = gen_rtx_SUBREG (QImode, target, 0);
24709 if ((optimize && !register_operand (op0, mode0))
24710 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24711 op0 = copy_to_mode_reg (mode0, op0);
24712 if ((optimize && !register_operand (op1, mode1))
24713 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24714 op1 = copy_to_mode_reg (mode1, op1);
24716 pat = GEN_FCN (d->icode) (op0, op1);
24720 emit_insn (gen_rtx_SET (VOIDmode,
24721 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24722 gen_rtx_fmt_ee (comparison, QImode,
24726 return SUBREG_REG (target);
24729 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
24732 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
24736 tree arg0 = CALL_EXPR_ARG (exp, 0);
24737 tree arg1 = CALL_EXPR_ARG (exp, 1);
24738 rtx op0 = expand_normal (arg0);
24739 rtx op1 = expand_normal (arg1);
24740 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24741 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24742 enum rtx_code comparison = d->comparison;
24744 if (VECTOR_MODE_P (mode0))
24745 op0 = safe_vector_operand (op0, mode0);
24746 if (VECTOR_MODE_P (mode1))
24747 op1 = safe_vector_operand (op1, mode1);
24749 target = gen_reg_rtx (SImode);
24750 emit_move_insn (target, const0_rtx);
24751 target = gen_rtx_SUBREG (QImode, target, 0);
24753 if ((optimize && !register_operand (op0, mode0))
24754 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24755 op0 = copy_to_mode_reg (mode0, op0);
24756 if ((optimize && !register_operand (op1, mode1))
24757 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24758 op1 = copy_to_mode_reg (mode1, op1);
24760 pat = GEN_FCN (d->icode) (op0, op1);
24764 emit_insn (gen_rtx_SET (VOIDmode,
24765 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24766 gen_rtx_fmt_ee (comparison, QImode,
24770 return SUBREG_REG (target);
24773 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
24776 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
24777 tree exp, rtx target)
24780 tree arg0 = CALL_EXPR_ARG (exp, 0);
24781 tree arg1 = CALL_EXPR_ARG (exp, 1);
24782 tree arg2 = CALL_EXPR_ARG (exp, 2);
24783 tree arg3 = CALL_EXPR_ARG (exp, 3);
24784 tree arg4 = CALL_EXPR_ARG (exp, 4);
24785 rtx scratch0, scratch1;
24786 rtx op0 = expand_normal (arg0);
24787 rtx op1 = expand_normal (arg1);
24788 rtx op2 = expand_normal (arg2);
24789 rtx op3 = expand_normal (arg3);
24790 rtx op4 = expand_normal (arg4);
24791 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
24793 tmode0 = insn_data[d->icode].operand[0].mode;
24794 tmode1 = insn_data[d->icode].operand[1].mode;
24795 modev2 = insn_data[d->icode].operand[2].mode;
24796 modei3 = insn_data[d->icode].operand[3].mode;
24797 modev4 = insn_data[d->icode].operand[4].mode;
24798 modei5 = insn_data[d->icode].operand[5].mode;
24799 modeimm = insn_data[d->icode].operand[6].mode;
24801 if (VECTOR_MODE_P (modev2))
24802 op0 = safe_vector_operand (op0, modev2);
24803 if (VECTOR_MODE_P (modev4))
24804 op2 = safe_vector_operand (op2, modev4);
24806 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24807 op0 = copy_to_mode_reg (modev2, op0);
24808 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24809 op1 = copy_to_mode_reg (modei3, op1);
24810 if ((optimize && !register_operand (op2, modev4))
24811 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24812 op2 = copy_to_mode_reg (modev4, op2);
24813 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24814 op3 = copy_to_mode_reg (modei5, op3);
24816 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24818 error ("the fifth argument must be a 8-bit immediate");
24822 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24824 if (optimize || !target
24825 || GET_MODE (target) != tmode0
24826 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24827 target = gen_reg_rtx (tmode0);
24829 scratch1 = gen_reg_rtx (tmode1);
24831 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24833 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24835 if (optimize || !target
24836 || GET_MODE (target) != tmode1
24837 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24838 target = gen_reg_rtx (tmode1);
24840 scratch0 = gen_reg_rtx (tmode0);
24842 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24846 gcc_assert (d->flag);
24848 scratch0 = gen_reg_rtx (tmode0);
24849 scratch1 = gen_reg_rtx (tmode1);
24851 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24861 target = gen_reg_rtx (SImode);
24862 emit_move_insn (target, const0_rtx);
24863 target = gen_rtx_SUBREG (QImode, target, 0);
24866 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24867 gen_rtx_fmt_ee (EQ, QImode,
24868 gen_rtx_REG ((enum machine_mode) d->flag,
24871 return SUBREG_REG (target);
24878 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24881 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24882 tree exp, rtx target)
24885 tree arg0 = CALL_EXPR_ARG (exp, 0);
24886 tree arg1 = CALL_EXPR_ARG (exp, 1);
24887 tree arg2 = CALL_EXPR_ARG (exp, 2);
24888 rtx scratch0, scratch1;
24889 rtx op0 = expand_normal (arg0);
24890 rtx op1 = expand_normal (arg1);
24891 rtx op2 = expand_normal (arg2);
24892 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24894 tmode0 = insn_data[d->icode].operand[0].mode;
24895 tmode1 = insn_data[d->icode].operand[1].mode;
24896 modev2 = insn_data[d->icode].operand[2].mode;
24897 modev3 = insn_data[d->icode].operand[3].mode;
24898 modeimm = insn_data[d->icode].operand[4].mode;
24900 if (VECTOR_MODE_P (modev2))
24901 op0 = safe_vector_operand (op0, modev2);
24902 if (VECTOR_MODE_P (modev3))
24903 op1 = safe_vector_operand (op1, modev3);
24905 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24906 op0 = copy_to_mode_reg (modev2, op0);
24907 if ((optimize && !register_operand (op1, modev3))
24908 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24909 op1 = copy_to_mode_reg (modev3, op1);
24911 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24913 error ("the third argument must be a 8-bit immediate");
24917 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24919 if (optimize || !target
24920 || GET_MODE (target) != tmode0
24921 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24922 target = gen_reg_rtx (tmode0);
24924 scratch1 = gen_reg_rtx (tmode1);
24926 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24928 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24930 if (optimize || !target
24931 || GET_MODE (target) != tmode1
24932 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24933 target = gen_reg_rtx (tmode1);
24935 scratch0 = gen_reg_rtx (tmode0);
24937 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24941 gcc_assert (d->flag);
24943 scratch0 = gen_reg_rtx (tmode0);
24944 scratch1 = gen_reg_rtx (tmode1);
24946 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24956 target = gen_reg_rtx (SImode);
24957 emit_move_insn (target, const0_rtx);
24958 target = gen_rtx_SUBREG (QImode, target, 0);
24961 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24962 gen_rtx_fmt_ee (EQ, QImode,
24963 gen_rtx_REG ((enum machine_mode) d->flag,
24966 return SUBREG_REG (target);
24972 /* Subroutine of ix86_expand_builtin to take care of insns with
24973 variable number of operands. */
24976 ix86_expand_args_builtin (const struct builtin_description *d,
24977 tree exp, rtx target)
24979 rtx pat, real_target;
24980 unsigned int i, nargs;
24981 unsigned int nargs_constant = 0;
24982 int num_memory = 0;
24986 enum machine_mode mode;
24988 bool last_arg_count = false;
24989 enum insn_code icode = d->icode;
24990 const struct insn_data *insn_p = &insn_data[icode];
24991 enum machine_mode tmode = insn_p->operand[0].mode;
24992 enum machine_mode rmode = VOIDmode;
24994 enum rtx_code comparison = d->comparison;
24996 switch ((enum ix86_builtin_type) d->flag)
24998 case INT_FTYPE_V8SF_V8SF_PTEST:
24999 case INT_FTYPE_V4DI_V4DI_PTEST:
25000 case INT_FTYPE_V4DF_V4DF_PTEST:
25001 case INT_FTYPE_V4SF_V4SF_PTEST:
25002 case INT_FTYPE_V2DI_V2DI_PTEST:
25003 case INT_FTYPE_V2DF_V2DF_PTEST:
25004 return ix86_expand_sse_ptest (d, exp, target);
25005 case FLOAT128_FTYPE_FLOAT128:
25006 case FLOAT_FTYPE_FLOAT:
25007 case INT_FTYPE_INT:
25008 case UINT64_FTYPE_INT:
25009 case INT64_FTYPE_INT64:
25010 case INT64_FTYPE_V4SF:
25011 case INT64_FTYPE_V2DF:
25012 case INT_FTYPE_V16QI:
25013 case INT_FTYPE_V8QI:
25014 case INT_FTYPE_V8SF:
25015 case INT_FTYPE_V4DF:
25016 case INT_FTYPE_V4SF:
25017 case INT_FTYPE_V2DF:
25018 case V16QI_FTYPE_V16QI:
25019 case V8SI_FTYPE_V8SF:
25020 case V8SI_FTYPE_V4SI:
25021 case V8HI_FTYPE_V8HI:
25022 case V8HI_FTYPE_V16QI:
25023 case V8QI_FTYPE_V8QI:
25024 case V8SF_FTYPE_V8SF:
25025 case V8SF_FTYPE_V8SI:
25026 case V8SF_FTYPE_V4SF:
25027 case V4SI_FTYPE_V4SI:
25028 case V4SI_FTYPE_V16QI:
25029 case V4SI_FTYPE_V4SF:
25030 case V4SI_FTYPE_V8SI:
25031 case V4SI_FTYPE_V8HI:
25032 case V4SI_FTYPE_V4DF:
25033 case V4SI_FTYPE_V2DF:
25034 case V4HI_FTYPE_V4HI:
25035 case V4DF_FTYPE_V4DF:
25036 case V4DF_FTYPE_V4SI:
25037 case V4DF_FTYPE_V4SF:
25038 case V4DF_FTYPE_V2DF:
25039 case V4SF_FTYPE_V4SF:
25040 case V4SF_FTYPE_V4SI:
25041 case V4SF_FTYPE_V8SF:
25042 case V4SF_FTYPE_V4DF:
25043 case V4SF_FTYPE_V2DF:
25044 case V2DI_FTYPE_V2DI:
25045 case V2DI_FTYPE_V16QI:
25046 case V2DI_FTYPE_V8HI:
25047 case V2DI_FTYPE_V4SI:
25048 case V2DF_FTYPE_V2DF:
25049 case V2DF_FTYPE_V4SI:
25050 case V2DF_FTYPE_V4DF:
25051 case V2DF_FTYPE_V4SF:
25052 case V2DF_FTYPE_V2SI:
25053 case V2SI_FTYPE_V2SI:
25054 case V2SI_FTYPE_V4SF:
25055 case V2SI_FTYPE_V2SF:
25056 case V2SI_FTYPE_V2DF:
25057 case V2SF_FTYPE_V2SF:
25058 case V2SF_FTYPE_V2SI:
25061 case V4SF_FTYPE_V4SF_VEC_MERGE:
25062 case V2DF_FTYPE_V2DF_VEC_MERGE:
25063 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
25064 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
25065 case V16QI_FTYPE_V16QI_V16QI:
25066 case V16QI_FTYPE_V8HI_V8HI:
25067 case V8QI_FTYPE_V8QI_V8QI:
25068 case V8QI_FTYPE_V4HI_V4HI:
25069 case V8HI_FTYPE_V8HI_V8HI:
25070 case V8HI_FTYPE_V16QI_V16QI:
25071 case V8HI_FTYPE_V4SI_V4SI:
25072 case V8SF_FTYPE_V8SF_V8SF:
25073 case V8SF_FTYPE_V8SF_V8SI:
25074 case V4SI_FTYPE_V4SI_V4SI:
25075 case V4SI_FTYPE_V8HI_V8HI:
25076 case V4SI_FTYPE_V4SF_V4SF:
25077 case V4SI_FTYPE_V2DF_V2DF:
25078 case V4HI_FTYPE_V4HI_V4HI:
25079 case V4HI_FTYPE_V8QI_V8QI:
25080 case V4HI_FTYPE_V2SI_V2SI:
25081 case V4DF_FTYPE_V4DF_V4DF:
25082 case V4DF_FTYPE_V4DF_V4DI:
25083 case V4SF_FTYPE_V4SF_V4SF:
25084 case V4SF_FTYPE_V4SF_V4SI:
25085 case V4SF_FTYPE_V4SF_V2SI:
25086 case V4SF_FTYPE_V4SF_V2DF:
25087 case V4SF_FTYPE_V4SF_DI:
25088 case V4SF_FTYPE_V4SF_SI:
25089 case V2DI_FTYPE_V2DI_V2DI:
25090 case V2DI_FTYPE_V16QI_V16QI:
25091 case V2DI_FTYPE_V4SI_V4SI:
25092 case V2DI_FTYPE_V2DI_V16QI:
25093 case V2DI_FTYPE_V2DF_V2DF:
25094 case V2SI_FTYPE_V2SI_V2SI:
25095 case V2SI_FTYPE_V4HI_V4HI:
25096 case V2SI_FTYPE_V2SF_V2SF:
25097 case V2DF_FTYPE_V2DF_V2DF:
25098 case V2DF_FTYPE_V2DF_V4SF:
25099 case V2DF_FTYPE_V2DF_V2DI:
25100 case V2DF_FTYPE_V2DF_DI:
25101 case V2DF_FTYPE_V2DF_SI:
25102 case V2SF_FTYPE_V2SF_V2SF:
25103 case V1DI_FTYPE_V1DI_V1DI:
25104 case V1DI_FTYPE_V8QI_V8QI:
25105 case V1DI_FTYPE_V2SI_V2SI:
25106 if (comparison == UNKNOWN)
25107 return ix86_expand_binop_builtin (icode, exp, target);
25110 case V4SF_FTYPE_V4SF_V4SF_SWAP:
25111 case V2DF_FTYPE_V2DF_V2DF_SWAP:
25112 gcc_assert (comparison != UNKNOWN);
25116 case V8HI_FTYPE_V8HI_V8HI_COUNT:
25117 case V8HI_FTYPE_V8HI_SI_COUNT:
25118 case V4SI_FTYPE_V4SI_V4SI_COUNT:
25119 case V4SI_FTYPE_V4SI_SI_COUNT:
25120 case V4HI_FTYPE_V4HI_V4HI_COUNT:
25121 case V4HI_FTYPE_V4HI_SI_COUNT:
25122 case V2DI_FTYPE_V2DI_V2DI_COUNT:
25123 case V2DI_FTYPE_V2DI_SI_COUNT:
25124 case V2SI_FTYPE_V2SI_V2SI_COUNT:
25125 case V2SI_FTYPE_V2SI_SI_COUNT:
25126 case V1DI_FTYPE_V1DI_V1DI_COUNT:
25127 case V1DI_FTYPE_V1DI_SI_COUNT:
25129 last_arg_count = true;
25131 case UINT64_FTYPE_UINT64_UINT64:
25132 case UINT_FTYPE_UINT_UINT:
25133 case UINT_FTYPE_UINT_USHORT:
25134 case UINT_FTYPE_UINT_UCHAR:
25135 case UINT16_FTYPE_UINT16_INT:
25136 case UINT8_FTYPE_UINT8_INT:
25139 case V2DI2TI_FTYPE_V2DI_INT:
25142 nargs_constant = 1;
25144 case V8HI_FTYPE_V8HI_INT:
25145 case V8SF_FTYPE_V8SF_INT:
25146 case V4SI_FTYPE_V4SI_INT:
25147 case V4SI_FTYPE_V8SI_INT:
25148 case V4HI_FTYPE_V4HI_INT:
25149 case V4DF_FTYPE_V4DF_INT:
25150 case V4SF_FTYPE_V4SF_INT:
25151 case V4SF_FTYPE_V8SF_INT:
25152 case V2DI_FTYPE_V2DI_INT:
25153 case V2DF_FTYPE_V2DF_INT:
25154 case V2DF_FTYPE_V4DF_INT:
25156 nargs_constant = 1;
25158 case V16QI_FTYPE_V16QI_V16QI_V16QI:
25159 case V8SF_FTYPE_V8SF_V8SF_V8SF:
25160 case V4DF_FTYPE_V4DF_V4DF_V4DF:
25161 case V4SF_FTYPE_V4SF_V4SF_V4SF:
25162 case V2DF_FTYPE_V2DF_V2DF_V2DF:
25165 case V16QI_FTYPE_V16QI_V16QI_INT:
25166 case V8HI_FTYPE_V8HI_V8HI_INT:
25167 case V8SI_FTYPE_V8SI_V8SI_INT:
25168 case V8SI_FTYPE_V8SI_V4SI_INT:
25169 case V8SF_FTYPE_V8SF_V8SF_INT:
25170 case V8SF_FTYPE_V8SF_V4SF_INT:
25171 case V4SI_FTYPE_V4SI_V4SI_INT:
25172 case V4DF_FTYPE_V4DF_V4DF_INT:
25173 case V4DF_FTYPE_V4DF_V2DF_INT:
25174 case V4SF_FTYPE_V4SF_V4SF_INT:
25175 case V2DI_FTYPE_V2DI_V2DI_INT:
25176 case V2DF_FTYPE_V2DF_V2DF_INT:
25178 nargs_constant = 1;
25180 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
25183 nargs_constant = 1;
25185 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
25188 nargs_constant = 1;
25190 case V2DI_FTYPE_V2DI_UINT_UINT:
25192 nargs_constant = 2;
25194 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
25196 nargs_constant = 2;
25199 gcc_unreachable ();
25202 gcc_assert (nargs <= ARRAY_SIZE (args));
25204 if (comparison != UNKNOWN)
25206 gcc_assert (nargs == 2);
25207 return ix86_expand_sse_compare (d, exp, target, swap);
25210 if (rmode == VOIDmode || rmode == tmode)
25214 || GET_MODE (target) != tmode
25215 || ! (*insn_p->operand[0].predicate) (target, tmode))
25216 target = gen_reg_rtx (tmode);
25217 real_target = target;
25221 target = gen_reg_rtx (rmode);
25222 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
25225 for (i = 0; i < nargs; i++)
25227 tree arg = CALL_EXPR_ARG (exp, i);
25228 rtx op = expand_normal (arg);
25229 enum machine_mode mode = insn_p->operand[i + 1].mode;
25230 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
25232 if (last_arg_count && (i + 1) == nargs)
25234 /* SIMD shift insns take either an 8-bit immediate or
25235 register as count. But builtin functions take int as
25236 count. If count doesn't match, we put it in register. */
25239 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
25240 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
25241 op = copy_to_reg (op);
25244 else if ((nargs - i) <= nargs_constant)
25249 case CODE_FOR_sse4_1_roundpd:
25250 case CODE_FOR_sse4_1_roundps:
25251 case CODE_FOR_sse4_1_roundsd:
25252 case CODE_FOR_sse4_1_roundss:
25253 case CODE_FOR_sse4_1_blendps:
25254 case CODE_FOR_avx_blendpd256:
25255 case CODE_FOR_avx_vpermilv4df:
25256 case CODE_FOR_avx_roundpd256:
25257 case CODE_FOR_avx_roundps256:
25258 error ("the last argument must be a 4-bit immediate");
25261 case CODE_FOR_sse4_1_blendpd:
25262 case CODE_FOR_avx_vpermilv2df:
25263 error ("the last argument must be a 2-bit immediate");
25266 case CODE_FOR_avx_vextractf128v4df:
25267 case CODE_FOR_avx_vextractf128v8sf:
25268 case CODE_FOR_avx_vextractf128v8si:
25269 case CODE_FOR_avx_vinsertf128v4df:
25270 case CODE_FOR_avx_vinsertf128v8sf:
25271 case CODE_FOR_avx_vinsertf128v8si:
25272 error ("the last argument must be a 1-bit immediate");
25275 case CODE_FOR_avx_cmpsdv2df3:
25276 case CODE_FOR_avx_cmpssv4sf3:
25277 case CODE_FOR_avx_cmppdv2df3:
25278 case CODE_FOR_avx_cmppsv4sf3:
25279 case CODE_FOR_avx_cmppdv4df3:
25280 case CODE_FOR_avx_cmppsv8sf3:
25281 error ("the last argument must be a 5-bit immediate");
25285 switch (nargs_constant)
25288 if ((nargs - i) == nargs_constant)
25290 error ("the next to last argument must be an 8-bit immediate");
25294 error ("the last argument must be an 8-bit immediate");
25297 gcc_unreachable ();
25304 if (VECTOR_MODE_P (mode))
25305 op = safe_vector_operand (op, mode);
25307 /* If we aren't optimizing, only allow one memory operand to
25309 if (memory_operand (op, mode))
25312 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
25314 if (optimize || !match || num_memory > 1)
25315 op = copy_to_mode_reg (mode, op);
25319 op = copy_to_reg (op);
25320 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
25325 args[i].mode = mode;
25331 pat = GEN_FCN (icode) (real_target, args[0].op);
25334 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
25337 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25341 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25342 args[2].op, args[3].op);
25345 gcc_unreachable ();
25355 /* Subroutine of ix86_expand_builtin to take care of special insns
25356 with variable number of operands. */
25359 ix86_expand_special_args_builtin (const struct builtin_description *d,
25360 tree exp, rtx target)
25364 unsigned int i, nargs, arg_adjust, memory;
25368 enum machine_mode mode;
25370 enum insn_code icode = d->icode;
25371 bool last_arg_constant = false;
25372 const struct insn_data *insn_p = &insn_data[icode];
25373 enum machine_mode tmode = insn_p->operand[0].mode;
25374 enum { load, store } klass;
25376 switch ((enum ix86_special_builtin_type) d->flag)
25378 case VOID_FTYPE_VOID:
25379 emit_insn (GEN_FCN (icode) (target));
25381 case UINT64_FTYPE_VOID:
25386 case UINT64_FTYPE_PUNSIGNED:
25387 case V2DI_FTYPE_PV2DI:
25388 case V32QI_FTYPE_PCCHAR:
25389 case V16QI_FTYPE_PCCHAR:
25390 case V8SF_FTYPE_PCV4SF:
25391 case V8SF_FTYPE_PCFLOAT:
25392 case V4SF_FTYPE_PCFLOAT:
25393 case V4DF_FTYPE_PCV2DF:
25394 case V4DF_FTYPE_PCDOUBLE:
25395 case V2DF_FTYPE_PCDOUBLE:
25400 case VOID_FTYPE_PV2SF_V4SF:
25401 case VOID_FTYPE_PV4DI_V4DI:
25402 case VOID_FTYPE_PV2DI_V2DI:
25403 case VOID_FTYPE_PCHAR_V32QI:
25404 case VOID_FTYPE_PCHAR_V16QI:
25405 case VOID_FTYPE_PFLOAT_V8SF:
25406 case VOID_FTYPE_PFLOAT_V4SF:
25407 case VOID_FTYPE_PDOUBLE_V4DF:
25408 case VOID_FTYPE_PDOUBLE_V2DF:
25409 case VOID_FTYPE_PDI_DI:
25410 case VOID_FTYPE_PINT_INT:
25413 /* Reserve memory operand for target. */
25414 memory = ARRAY_SIZE (args);
25416 case V4SF_FTYPE_V4SF_PCV2SF:
25417 case V2DF_FTYPE_V2DF_PCDOUBLE:
25422 case V8SF_FTYPE_PCV8SF_V8SF:
25423 case V4DF_FTYPE_PCV4DF_V4DF:
25424 case V4SF_FTYPE_PCV4SF_V4SF:
25425 case V2DF_FTYPE_PCV2DF_V2DF:
25430 case VOID_FTYPE_PV8SF_V8SF_V8SF:
25431 case VOID_FTYPE_PV4DF_V4DF_V4DF:
25432 case VOID_FTYPE_PV4SF_V4SF_V4SF:
25433 case VOID_FTYPE_PV2DF_V2DF_V2DF:
25436 /* Reserve memory operand for target. */
25437 memory = ARRAY_SIZE (args);
25440 gcc_unreachable ();
25443 gcc_assert (nargs <= ARRAY_SIZE (args));
25445 if (klass == store)
25447 arg = CALL_EXPR_ARG (exp, 0);
25448 op = expand_normal (arg);
25449 gcc_assert (target == 0);
25450 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
25458 || GET_MODE (target) != tmode
25459 || ! (*insn_p->operand[0].predicate) (target, tmode))
25460 target = gen_reg_rtx (tmode);
25463 for (i = 0; i < nargs; i++)
25465 enum machine_mode mode = insn_p->operand[i + 1].mode;
25468 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
25469 op = expand_normal (arg);
25470 match = (*insn_p->operand[i + 1].predicate) (op, mode);
25472 if (last_arg_constant && (i + 1) == nargs)
25478 error ("the last argument must be an 8-bit immediate");
25486 /* This must be the memory operand. */
25487 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
25488 gcc_assert (GET_MODE (op) == mode
25489 || GET_MODE (op) == VOIDmode);
25493 /* This must be register. */
25494 if (VECTOR_MODE_P (mode))
25495 op = safe_vector_operand (op, mode);
25497 gcc_assert (GET_MODE (op) == mode
25498 || GET_MODE (op) == VOIDmode);
25499 op = copy_to_mode_reg (mode, op);
25504 args[i].mode = mode;
25510 pat = GEN_FCN (icode) (target);
25513 pat = GEN_FCN (icode) (target, args[0].op);
25516 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
25519 gcc_unreachable ();
25525 return klass == store ? 0 : target;
25528 /* Return the integer constant in ARG. Constrain it to be in the range
25529 of the subparts of VEC_TYPE; issue an error if not. */
25532 get_element_number (tree vec_type, tree arg)
25534 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
25536 if (!host_integerp (arg, 1)
25537 || (elt = tree_low_cst (arg, 1), elt > max))
25539 error ("selector must be an integer constant in the range 0..%wi", max);
25546 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25547 ix86_expand_vector_init. We DO have language-level syntax for this, in
25548 the form of (type){ init-list }. Except that since we can't place emms
25549 instructions from inside the compiler, we can't allow the use of MMX
25550 registers unless the user explicitly asks for it. So we do *not* define
25551 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
25552 we have builtins invoked by mmintrin.h that gives us license to emit
25553 these sorts of instructions. */
25556 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
25558 enum machine_mode tmode = TYPE_MODE (type);
25559 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
25560 int i, n_elt = GET_MODE_NUNITS (tmode);
25561 rtvec v = rtvec_alloc (n_elt);
25563 gcc_assert (VECTOR_MODE_P (tmode));
25564 gcc_assert (call_expr_nargs (exp) == n_elt);
25566 for (i = 0; i < n_elt; ++i)
25568 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
25569 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
25572 if (!target || !register_operand (target, tmode))
25573 target = gen_reg_rtx (tmode);
25575 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
25579 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25580 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
25581 had a language-level syntax for referencing vector elements. */
25584 ix86_expand_vec_ext_builtin (tree exp, rtx target)
25586 enum machine_mode tmode, mode0;
25591 arg0 = CALL_EXPR_ARG (exp, 0);
25592 arg1 = CALL_EXPR_ARG (exp, 1);
25594 op0 = expand_normal (arg0);
25595 elt = get_element_number (TREE_TYPE (arg0), arg1);
25597 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25598 mode0 = TYPE_MODE (TREE_TYPE (arg0));
25599 gcc_assert (VECTOR_MODE_P (mode0));
25601 op0 = force_reg (mode0, op0);
25603 if (optimize || !target || !register_operand (target, tmode))
25604 target = gen_reg_rtx (tmode);
25606 ix86_expand_vector_extract (true, target, op0, elt);
25611 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25612 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
25613 a language-level syntax for referencing vector elements. */
25616 ix86_expand_vec_set_builtin (tree exp)
25618 enum machine_mode tmode, mode1;
25619 tree arg0, arg1, arg2;
25621 rtx op0, op1, target;
25623 arg0 = CALL_EXPR_ARG (exp, 0);
25624 arg1 = CALL_EXPR_ARG (exp, 1);
25625 arg2 = CALL_EXPR_ARG (exp, 2);
25627 tmode = TYPE_MODE (TREE_TYPE (arg0));
25628 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25629 gcc_assert (VECTOR_MODE_P (tmode));
25631 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
25632 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
25633 elt = get_element_number (TREE_TYPE (arg0), arg2);
25635 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
25636 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
25638 op0 = force_reg (tmode, op0);
25639 op1 = force_reg (mode1, op1);
25641 /* OP0 is the source of these builtin functions and shouldn't be
25642 modified. Create a copy, use it and return it as target. */
25643 target = gen_reg_rtx (tmode);
25644 emit_move_insn (target, op0);
25645 ix86_expand_vector_set (true, target, op1, elt);
25650 /* Expand an expression EXP that calls a built-in function,
25651 with result going to TARGET if that's convenient
25652 (and in mode MODE if that's convenient).
25653 SUBTARGET may be used as the target for computing one of EXP's operands.
25654 IGNORE is nonzero if the value is to be ignored. */
25657 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
25658 enum machine_mode mode ATTRIBUTE_UNUSED,
25659 int ignore ATTRIBUTE_UNUSED)
25661 const struct builtin_description *d;
25663 enum insn_code icode;
25664 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
25665 tree arg0, arg1, arg2;
25666 rtx op0, op1, op2, pat;
25667 enum machine_mode mode0, mode1, mode2;
25668 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
25670 /* Determine whether the builtin function is available under the current ISA.
25671 Originally the builtin was not created if it wasn't applicable to the
25672 current ISA based on the command line switches. With function specific
25673 options, we need to check in the context of the function making the call
25674 whether it is supported. */
25675 if (ix86_builtins_isa[fcode].isa
25676 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
25678 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
25679 NULL, NULL, false);
25682 error ("%qE needs unknown isa option", fndecl);
25685 gcc_assert (opts != NULL);
25686 error ("%qE needs isa option %s", fndecl, opts);
25694 case IX86_BUILTIN_MASKMOVQ:
25695 case IX86_BUILTIN_MASKMOVDQU:
25696 icode = (fcode == IX86_BUILTIN_MASKMOVQ
25697 ? CODE_FOR_mmx_maskmovq
25698 : CODE_FOR_sse2_maskmovdqu);
25699 /* Note the arg order is different from the operand order. */
25700 arg1 = CALL_EXPR_ARG (exp, 0);
25701 arg2 = CALL_EXPR_ARG (exp, 1);
25702 arg0 = CALL_EXPR_ARG (exp, 2);
25703 op0 = expand_normal (arg0);
25704 op1 = expand_normal (arg1);
25705 op2 = expand_normal (arg2);
25706 mode0 = insn_data[icode].operand[0].mode;
25707 mode1 = insn_data[icode].operand[1].mode;
25708 mode2 = insn_data[icode].operand[2].mode;
25710 op0 = force_reg (Pmode, op0);
25711 op0 = gen_rtx_MEM (mode1, op0);
25713 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
25714 op0 = copy_to_mode_reg (mode0, op0);
25715 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
25716 op1 = copy_to_mode_reg (mode1, op1);
25717 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
25718 op2 = copy_to_mode_reg (mode2, op2);
25719 pat = GEN_FCN (icode) (op0, op1, op2);
25725 case IX86_BUILTIN_LDMXCSR:
25726 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
25727 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25728 emit_move_insn (target, op0);
25729 emit_insn (gen_sse_ldmxcsr (target));
25732 case IX86_BUILTIN_STMXCSR:
25733 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25734 emit_insn (gen_sse_stmxcsr (target));
25735 return copy_to_mode_reg (SImode, target);
25737 case IX86_BUILTIN_CLFLUSH:
25738 arg0 = CALL_EXPR_ARG (exp, 0);
25739 op0 = expand_normal (arg0);
25740 icode = CODE_FOR_sse2_clflush;
25741 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
25742 op0 = copy_to_mode_reg (Pmode, op0);
25744 emit_insn (gen_sse2_clflush (op0));
25747 case IX86_BUILTIN_MONITOR:
25748 arg0 = CALL_EXPR_ARG (exp, 0);
25749 arg1 = CALL_EXPR_ARG (exp, 1);
25750 arg2 = CALL_EXPR_ARG (exp, 2);
25751 op0 = expand_normal (arg0);
25752 op1 = expand_normal (arg1);
25753 op2 = expand_normal (arg2);
25755 op0 = copy_to_mode_reg (Pmode, op0);
25757 op1 = copy_to_mode_reg (SImode, op1);
25759 op2 = copy_to_mode_reg (SImode, op2);
25760 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
25763 case IX86_BUILTIN_MWAIT:
25764 arg0 = CALL_EXPR_ARG (exp, 0);
25765 arg1 = CALL_EXPR_ARG (exp, 1);
25766 op0 = expand_normal (arg0);
25767 op1 = expand_normal (arg1);
25769 op0 = copy_to_mode_reg (SImode, op0);
25771 op1 = copy_to_mode_reg (SImode, op1);
25772 emit_insn (gen_sse3_mwait (op0, op1));
25775 case IX86_BUILTIN_VEC_INIT_V2SI:
25776 case IX86_BUILTIN_VEC_INIT_V4HI:
25777 case IX86_BUILTIN_VEC_INIT_V8QI:
25778 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
25780 case IX86_BUILTIN_VEC_EXT_V2DF:
25781 case IX86_BUILTIN_VEC_EXT_V2DI:
25782 case IX86_BUILTIN_VEC_EXT_V4SF:
25783 case IX86_BUILTIN_VEC_EXT_V4SI:
25784 case IX86_BUILTIN_VEC_EXT_V8HI:
25785 case IX86_BUILTIN_VEC_EXT_V2SI:
25786 case IX86_BUILTIN_VEC_EXT_V4HI:
25787 case IX86_BUILTIN_VEC_EXT_V16QI:
25788 return ix86_expand_vec_ext_builtin (exp, target);
25790 case IX86_BUILTIN_VEC_SET_V2DI:
25791 case IX86_BUILTIN_VEC_SET_V4SF:
25792 case IX86_BUILTIN_VEC_SET_V4SI:
25793 case IX86_BUILTIN_VEC_SET_V8HI:
25794 case IX86_BUILTIN_VEC_SET_V4HI:
25795 case IX86_BUILTIN_VEC_SET_V16QI:
25796 return ix86_expand_vec_set_builtin (exp);
25798 case IX86_BUILTIN_INFQ:
25799 case IX86_BUILTIN_HUGE_VALQ:
25801 REAL_VALUE_TYPE inf;
25805 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
25807 tmp = validize_mem (force_const_mem (mode, tmp));
25810 target = gen_reg_rtx (mode);
25812 emit_move_insn (target, tmp);
25820 for (i = 0, d = bdesc_special_args;
25821 i < ARRAY_SIZE (bdesc_special_args);
25823 if (d->code == fcode)
25824 return ix86_expand_special_args_builtin (d, exp, target);
25826 for (i = 0, d = bdesc_args;
25827 i < ARRAY_SIZE (bdesc_args);
25829 if (d->code == fcode)
25832 case IX86_BUILTIN_FABSQ:
25833 case IX86_BUILTIN_COPYSIGNQ:
25835 /* Emit a normal call if SSE2 isn't available. */
25836 return expand_call (exp, target, ignore);
25838 return ix86_expand_args_builtin (d, exp, target);
25841 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25842 if (d->code == fcode)
25843 return ix86_expand_sse_comi (d, exp, target);
25845 for (i = 0, d = bdesc_pcmpestr;
25846 i < ARRAY_SIZE (bdesc_pcmpestr);
25848 if (d->code == fcode)
25849 return ix86_expand_sse_pcmpestr (d, exp, target);
25851 for (i = 0, d = bdesc_pcmpistr;
25852 i < ARRAY_SIZE (bdesc_pcmpistr);
25854 if (d->code == fcode)
25855 return ix86_expand_sse_pcmpistr (d, exp, target);
25857 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25858 if (d->code == fcode)
25859 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25860 (enum multi_arg_type)d->flag,
25863 gcc_unreachable ();
25866 /* Returns a function decl for a vectorized version of the builtin function
25867 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25868 if it is not available. */
25871 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25874 enum machine_mode in_mode, out_mode;
25877 if (TREE_CODE (type_out) != VECTOR_TYPE
25878 || TREE_CODE (type_in) != VECTOR_TYPE)
25881 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25882 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25883 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25884 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25888 case BUILT_IN_SQRT:
25889 if (out_mode == DFmode && out_n == 2
25890 && in_mode == DFmode && in_n == 2)
25891 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25894 case BUILT_IN_SQRTF:
25895 if (out_mode == SFmode && out_n == 4
25896 && in_mode == SFmode && in_n == 4)
25897 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25900 case BUILT_IN_LRINT:
25901 if (out_mode == SImode && out_n == 4
25902 && in_mode == DFmode && in_n == 2)
25903 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25906 case BUILT_IN_LRINTF:
25907 if (out_mode == SImode && out_n == 4
25908 && in_mode == SFmode && in_n == 4)
25909 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25916 /* Dispatch to a handler for a vectorization library. */
25917 if (ix86_veclib_handler)
25918 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
25924 /* Handler for an SVML-style interface to
25925 a library with vectorized intrinsics. */
25928 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25931 tree fntype, new_fndecl, args;
25934 enum machine_mode el_mode, in_mode;
25937 /* The SVML is suitable for unsafe math only. */
25938 if (!flag_unsafe_math_optimizations)
25941 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25942 n = TYPE_VECTOR_SUBPARTS (type_out);
25943 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25944 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25945 if (el_mode != in_mode
25953 case BUILT_IN_LOG10:
25955 case BUILT_IN_TANH:
25957 case BUILT_IN_ATAN:
25958 case BUILT_IN_ATAN2:
25959 case BUILT_IN_ATANH:
25960 case BUILT_IN_CBRT:
25961 case BUILT_IN_SINH:
25963 case BUILT_IN_ASINH:
25964 case BUILT_IN_ASIN:
25965 case BUILT_IN_COSH:
25967 case BUILT_IN_ACOSH:
25968 case BUILT_IN_ACOS:
25969 if (el_mode != DFmode || n != 2)
25973 case BUILT_IN_EXPF:
25974 case BUILT_IN_LOGF:
25975 case BUILT_IN_LOG10F:
25976 case BUILT_IN_POWF:
25977 case BUILT_IN_TANHF:
25978 case BUILT_IN_TANF:
25979 case BUILT_IN_ATANF:
25980 case BUILT_IN_ATAN2F:
25981 case BUILT_IN_ATANHF:
25982 case BUILT_IN_CBRTF:
25983 case BUILT_IN_SINHF:
25984 case BUILT_IN_SINF:
25985 case BUILT_IN_ASINHF:
25986 case BUILT_IN_ASINF:
25987 case BUILT_IN_COSHF:
25988 case BUILT_IN_COSF:
25989 case BUILT_IN_ACOSHF:
25990 case BUILT_IN_ACOSF:
25991 if (el_mode != SFmode || n != 4)
25999 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
26001 if (fn == BUILT_IN_LOGF)
26002 strcpy (name, "vmlsLn4");
26003 else if (fn == BUILT_IN_LOG)
26004 strcpy (name, "vmldLn2");
26007 sprintf (name, "vmls%s", bname+10);
26008 name[strlen (name)-1] = '4';
26011 sprintf (name, "vmld%s2", bname+10);
26013 /* Convert to uppercase. */
26017 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
26018 args = TREE_CHAIN (args))
26022 fntype = build_function_type_list (type_out, type_in, NULL);
26024 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
26026 /* Build a function declaration for the vectorized function. */
26027 new_fndecl = build_decl (BUILTINS_LOCATION,
26028 FUNCTION_DECL, get_identifier (name), fntype);
26029 TREE_PUBLIC (new_fndecl) = 1;
26030 DECL_EXTERNAL (new_fndecl) = 1;
26031 DECL_IS_NOVOPS (new_fndecl) = 1;
26032 TREE_READONLY (new_fndecl) = 1;
26037 /* Handler for an ACML-style interface to
26038 a library with vectorized intrinsics. */
26041 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
26043 char name[20] = "__vr.._";
26044 tree fntype, new_fndecl, args;
26047 enum machine_mode el_mode, in_mode;
26050 /* The ACML is 64bits only and suitable for unsafe math only as
26051 it does not correctly support parts of IEEE with the required
26052 precision such as denormals. */
26054 || !flag_unsafe_math_optimizations)
26057 el_mode = TYPE_MODE (TREE_TYPE (type_out));
26058 n = TYPE_VECTOR_SUBPARTS (type_out);
26059 in_mode = TYPE_MODE (TREE_TYPE (type_in));
26060 in_n = TYPE_VECTOR_SUBPARTS (type_in);
26061 if (el_mode != in_mode
26071 case BUILT_IN_LOG2:
26072 case BUILT_IN_LOG10:
26075 if (el_mode != DFmode
26080 case BUILT_IN_SINF:
26081 case BUILT_IN_COSF:
26082 case BUILT_IN_EXPF:
26083 case BUILT_IN_POWF:
26084 case BUILT_IN_LOGF:
26085 case BUILT_IN_LOG2F:
26086 case BUILT_IN_LOG10F:
26089 if (el_mode != SFmode
26098 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
26099 sprintf (name + 7, "%s", bname+10);
26102 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
26103 args = TREE_CHAIN (args))
26107 fntype = build_function_type_list (type_out, type_in, NULL);
26109 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
26111 /* Build a function declaration for the vectorized function. */
26112 new_fndecl = build_decl (BUILTINS_LOCATION,
26113 FUNCTION_DECL, get_identifier (name), fntype);
26114 TREE_PUBLIC (new_fndecl) = 1;
26115 DECL_EXTERNAL (new_fndecl) = 1;
26116 DECL_IS_NOVOPS (new_fndecl) = 1;
26117 TREE_READONLY (new_fndecl) = 1;
26123 /* Returns a decl of a function that implements conversion of an integer vector
26124 into a floating-point vector, or vice-versa. TYPE is the type of the integer
26125 side of the conversion.
26126 Return NULL_TREE if it is not available. */
26129 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
26131 if (TREE_CODE (type) != VECTOR_TYPE
26132 /* There are only conversions from/to signed integers. */
26133 || TYPE_UNSIGNED (TREE_TYPE (type)))
26139 switch (TYPE_MODE (type))
26142 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
26147 case FIX_TRUNC_EXPR:
26148 switch (TYPE_MODE (type))
26151 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
26161 /* Returns a code for a target-specific builtin that implements
26162 reciprocal of the function, or NULL_TREE if not available. */
26165 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
26166 bool sqrt ATTRIBUTE_UNUSED)
26168 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
26169 && flag_finite_math_only && !flag_trapping_math
26170 && flag_unsafe_math_optimizations))
26174 /* Machine dependent builtins. */
26177 /* Vectorized version of sqrt to rsqrt conversion. */
26178 case IX86_BUILTIN_SQRTPS_NR:
26179 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
26185 /* Normal builtins. */
26188 /* Sqrt to rsqrt conversion. */
26189 case BUILT_IN_SQRTF:
26190 return ix86_builtins[IX86_BUILTIN_RSQRTF];
26197 /* Store OPERAND to the memory after reload is completed. This means
26198 that we can't easily use assign_stack_local. */
26200 ix86_force_to_memory (enum machine_mode mode, rtx operand)
26204 gcc_assert (reload_completed);
26205 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
26207 result = gen_rtx_MEM (mode,
26208 gen_rtx_PLUS (Pmode,
26210 GEN_INT (-RED_ZONE_SIZE)));
26211 emit_move_insn (result, operand);
26213 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
26219 operand = gen_lowpart (DImode, operand);
26223 gen_rtx_SET (VOIDmode,
26224 gen_rtx_MEM (DImode,
26225 gen_rtx_PRE_DEC (DImode,
26226 stack_pointer_rtx)),
26230 gcc_unreachable ();
26232 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26241 split_di (&operand, 1, operands, operands + 1);
26243 gen_rtx_SET (VOIDmode,
26244 gen_rtx_MEM (SImode,
26245 gen_rtx_PRE_DEC (Pmode,
26246 stack_pointer_rtx)),
26249 gen_rtx_SET (VOIDmode,
26250 gen_rtx_MEM (SImode,
26251 gen_rtx_PRE_DEC (Pmode,
26252 stack_pointer_rtx)),
26257 /* Store HImodes as SImodes. */
26258 operand = gen_lowpart (SImode, operand);
26262 gen_rtx_SET (VOIDmode,
26263 gen_rtx_MEM (GET_MODE (operand),
26264 gen_rtx_PRE_DEC (SImode,
26265 stack_pointer_rtx)),
26269 gcc_unreachable ();
26271 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26276 /* Free operand from the memory. */
26278 ix86_free_from_memory (enum machine_mode mode)
26280 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
26284 if (mode == DImode || TARGET_64BIT)
26288 /* Use LEA to deallocate stack space. In peephole2 it will be converted
26289 to pop or add instruction if registers are available. */
26290 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
26291 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
26296 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
26297 QImode must go into class Q_REGS.
26298 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
26299 movdf to do mem-to-mem moves through integer regs. */
26301 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
26303 enum machine_mode mode = GET_MODE (x);
26305 /* We're only allowed to return a subclass of CLASS. Many of the
26306 following checks fail for NO_REGS, so eliminate that early. */
26307 if (regclass == NO_REGS)
26310 /* All classes can load zeros. */
26311 if (x == CONST0_RTX (mode))
26314 /* Force constants into memory if we are loading a (nonzero) constant into
26315 an MMX or SSE register. This is because there are no MMX/SSE instructions
26316 to load from a constant. */
26318 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
26321 /* Prefer SSE regs only, if we can use them for math. */
26322 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
26323 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
26325 /* Floating-point constants need more complex checks. */
26326 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
26328 /* General regs can load everything. */
26329 if (reg_class_subset_p (regclass, GENERAL_REGS))
26332 /* Floats can load 0 and 1 plus some others. Note that we eliminated
26333 zero above. We only want to wind up preferring 80387 registers if
26334 we plan on doing computation with them. */
26336 && standard_80387_constant_p (x))
26338 /* Limit class to non-sse. */
26339 if (regclass == FLOAT_SSE_REGS)
26341 if (regclass == FP_TOP_SSE_REGS)
26343 if (regclass == FP_SECOND_SSE_REGS)
26344 return FP_SECOND_REG;
26345 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
26352 /* Generally when we see PLUS here, it's the function invariant
26353 (plus soft-fp const_int). Which can only be computed into general
26355 if (GET_CODE (x) == PLUS)
26356 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
26358 /* QImode constants are easy to load, but non-constant QImode data
26359 must go into Q_REGS. */
26360 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
26362 if (reg_class_subset_p (regclass, Q_REGS))
26364 if (reg_class_subset_p (Q_REGS, regclass))
26372 /* Discourage putting floating-point values in SSE registers unless
26373 SSE math is being used, and likewise for the 387 registers. */
26375 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
26377 enum machine_mode mode = GET_MODE (x);
26379 /* Restrict the output reload class to the register bank that we are doing
26380 math on. If we would like not to return a subset of CLASS, reject this
26381 alternative: if reload cannot do this, it will still use its choice. */
26382 mode = GET_MODE (x);
26383 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
26384 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
26386 if (X87_FLOAT_MODE_P (mode))
26388 if (regclass == FP_TOP_SSE_REGS)
26390 else if (regclass == FP_SECOND_SSE_REGS)
26391 return FP_SECOND_REG;
26393 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
26399 static enum reg_class
26400 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
26401 enum machine_mode mode,
26402 secondary_reload_info *sri ATTRIBUTE_UNUSED)
26404 /* QImode spills from non-QI registers require
26405 intermediate register on 32bit targets. */
26406 if (!in_p && mode == QImode && !TARGET_64BIT
26407 && (rclass == GENERAL_REGS
26408 || rclass == LEGACY_REGS
26409 || rclass == INDEX_REGS))
26418 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
26419 regno = true_regnum (x);
26421 /* Return Q_REGS if the operand is in memory. */
26429 /* If we are copying between general and FP registers, we need a memory
26430 location. The same is true for SSE and MMX registers.
26432 To optimize register_move_cost performance, allow inline variant.
26434 The macro can't work reliably when one of the CLASSES is class containing
26435 registers from multiple units (SSE, MMX, integer). We avoid this by never
26436 combining those units in single alternative in the machine description.
26437 Ensure that this constraint holds to avoid unexpected surprises.
26439 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
26440 enforce these sanity checks. */
26443 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26444 enum machine_mode mode, int strict)
26446 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
26447 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
26448 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
26449 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
26450 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
26451 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
26453 gcc_assert (!strict);
26457 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
26460 /* ??? This is a lie. We do have moves between mmx/general, and for
26461 mmx/sse2. But by saying we need secondary memory we discourage the
26462 register allocator from using the mmx registers unless needed. */
26463 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
26466 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26468 /* SSE1 doesn't have any direct moves from other classes. */
26472 /* If the target says that inter-unit moves are more expensive
26473 than moving through memory, then don't generate them. */
26474 if (!TARGET_INTER_UNIT_MOVES)
26477 /* Between SSE and general, we have moves no larger than word size. */
26478 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
26486 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26487 enum machine_mode mode, int strict)
26489 return inline_secondary_memory_needed (class1, class2, mode, strict);
26492 /* Return true if the registers in CLASS cannot represent the change from
26493 modes FROM to TO. */
26496 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
26497 enum reg_class regclass)
26502 /* x87 registers can't do subreg at all, as all values are reformatted
26503 to extended precision. */
26504 if (MAYBE_FLOAT_CLASS_P (regclass))
26507 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
26509 /* Vector registers do not support QI or HImode loads. If we don't
26510 disallow a change to these modes, reload will assume it's ok to
26511 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
26512 the vec_dupv4hi pattern. */
26513 if (GET_MODE_SIZE (from) < 4)
26516 /* Vector registers do not support subreg with nonzero offsets, which
26517 are otherwise valid for integer registers. Since we can't see
26518 whether we have a nonzero offset from here, prohibit all
26519 nonparadoxical subregs changing size. */
26520 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
26527 /* Return the cost of moving data of mode M between a
26528 register and memory. A value of 2 is the default; this cost is
26529 relative to those in `REGISTER_MOVE_COST'.
26531 This function is used extensively by register_move_cost that is used to
26532 build tables at startup. Make it inline in this case.
26533 When IN is 2, return maximum of in and out move cost.
26535 If moving between registers and memory is more expensive than
26536 between two registers, you should define this macro to express the
26539 Model also increased moving costs of QImode registers in non
26543 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
26547 if (FLOAT_CLASS_P (regclass))
26565 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
26566 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
26568 if (SSE_CLASS_P (regclass))
26571 switch (GET_MODE_SIZE (mode))
26586 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
26587 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
26589 if (MMX_CLASS_P (regclass))
26592 switch (GET_MODE_SIZE (mode))
26604 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
26605 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
26607 switch (GET_MODE_SIZE (mode))
26610 if (Q_CLASS_P (regclass) || TARGET_64BIT)
26613 return ix86_cost->int_store[0];
26614 if (TARGET_PARTIAL_REG_DEPENDENCY
26615 && optimize_function_for_speed_p (cfun))
26616 cost = ix86_cost->movzbl_load;
26618 cost = ix86_cost->int_load[0];
26620 return MAX (cost, ix86_cost->int_store[0]);
26626 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
26628 return ix86_cost->movzbl_load;
26630 return ix86_cost->int_store[0] + 4;
26635 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
26636 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
26638 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
26639 if (mode == TFmode)
26642 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
26644 cost = ix86_cost->int_load[2];
26646 cost = ix86_cost->int_store[2];
26647 return (cost * (((int) GET_MODE_SIZE (mode)
26648 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
26653 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
26655 return inline_memory_move_cost (mode, regclass, in);
26659 /* Return the cost of moving data from a register in class CLASS1 to
26660 one in class CLASS2.
26662 It is not required that the cost always equal 2 when FROM is the same as TO;
26663 on some machines it is expensive to move between registers if they are not
26664 general registers. */
26667 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
26668 enum reg_class class2)
26670 /* In case we require secondary memory, compute cost of the store followed
26671 by load. In order to avoid bad register allocation choices, we need
26672 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
26674 if (inline_secondary_memory_needed (class1, class2, mode, 0))
26678 cost += inline_memory_move_cost (mode, class1, 2);
26679 cost += inline_memory_move_cost (mode, class2, 2);
26681 /* In case of copying from general_purpose_register we may emit multiple
26682 stores followed by single load causing memory size mismatch stall.
26683 Count this as arbitrarily high cost of 20. */
26684 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
26687 /* In the case of FP/MMX moves, the registers actually overlap, and we
26688 have to switch modes in order to treat them differently. */
26689 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
26690 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
26696 /* Moves between SSE/MMX and integer unit are expensive. */
26697 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
26698 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26700 /* ??? By keeping returned value relatively high, we limit the number
26701 of moves between integer and MMX/SSE registers for all targets.
26702 Additionally, high value prevents problem with x86_modes_tieable_p(),
26703 where integer modes in MMX/SSE registers are not tieable
26704 because of missing QImode and HImode moves to, from or between
26705 MMX/SSE registers. */
26706 return MAX (8, ix86_cost->mmxsse_to_integer);
26708 if (MAYBE_FLOAT_CLASS_P (class1))
26709 return ix86_cost->fp_move;
26710 if (MAYBE_SSE_CLASS_P (class1))
26711 return ix86_cost->sse_move;
26712 if (MAYBE_MMX_CLASS_P (class1))
26713 return ix86_cost->mmx_move;
26717 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
26720 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
26722 /* Flags and only flags can only hold CCmode values. */
26723 if (CC_REGNO_P (regno))
26724 return GET_MODE_CLASS (mode) == MODE_CC;
26725 if (GET_MODE_CLASS (mode) == MODE_CC
26726 || GET_MODE_CLASS (mode) == MODE_RANDOM
26727 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
26729 if (FP_REGNO_P (regno))
26730 return VALID_FP_MODE_P (mode);
26731 if (SSE_REGNO_P (regno))
26733 /* We implement the move patterns for all vector modes into and
26734 out of SSE registers, even when no operation instructions
26735 are available. OImode move is available only when AVX is
26737 return ((TARGET_AVX && mode == OImode)
26738 || VALID_AVX256_REG_MODE (mode)
26739 || VALID_SSE_REG_MODE (mode)
26740 || VALID_SSE2_REG_MODE (mode)
26741 || VALID_MMX_REG_MODE (mode)
26742 || VALID_MMX_REG_MODE_3DNOW (mode));
26744 if (MMX_REGNO_P (regno))
26746 /* We implement the move patterns for 3DNOW modes even in MMX mode,
26747 so if the register is available at all, then we can move data of
26748 the given mode into or out of it. */
26749 return (VALID_MMX_REG_MODE (mode)
26750 || VALID_MMX_REG_MODE_3DNOW (mode));
26753 if (mode == QImode)
26755 /* Take care for QImode values - they can be in non-QI regs,
26756 but then they do cause partial register stalls. */
26757 if (regno <= BX_REG || TARGET_64BIT)
26759 if (!TARGET_PARTIAL_REG_STALL)
26761 return reload_in_progress || reload_completed;
26763 /* We handle both integer and floats in the general purpose registers. */
26764 else if (VALID_INT_MODE_P (mode))
26766 else if (VALID_FP_MODE_P (mode))
26768 else if (VALID_DFP_MODE_P (mode))
26770 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
26771 on to use that value in smaller contexts, this can easily force a
26772 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
26773 supporting DImode, allow it. */
26774 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
26780 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
26781 tieable integer mode. */
26784 ix86_tieable_integer_mode_p (enum machine_mode mode)
26793 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
26796 return TARGET_64BIT;
26803 /* Return true if MODE1 is accessible in a register that can hold MODE2
26804 without copying. That is, all register classes that can hold MODE2
26805 can also hold MODE1. */
26808 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
26810 if (mode1 == mode2)
26813 if (ix86_tieable_integer_mode_p (mode1)
26814 && ix86_tieable_integer_mode_p (mode2))
26817 /* MODE2 being XFmode implies fp stack or general regs, which means we
26818 can tie any smaller floating point modes to it. Note that we do not
26819 tie this with TFmode. */
26820 if (mode2 == XFmode)
26821 return mode1 == SFmode || mode1 == DFmode;
26823 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26824 that we can tie it with SFmode. */
26825 if (mode2 == DFmode)
26826 return mode1 == SFmode;
26828 /* If MODE2 is only appropriate for an SSE register, then tie with
26829 any other mode acceptable to SSE registers. */
26830 if (GET_MODE_SIZE (mode2) == 16
26831 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26832 return (GET_MODE_SIZE (mode1) == 16
26833 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26835 /* If MODE2 is appropriate for an MMX register, then tie
26836 with any other mode acceptable to MMX registers. */
26837 if (GET_MODE_SIZE (mode2) == 8
26838 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26839 return (GET_MODE_SIZE (mode1) == 8
26840 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26845 /* Compute a (partial) cost for rtx X. Return true if the complete
26846 cost has been computed, and false if subexpressions should be
26847 scanned. In either case, *TOTAL contains the cost result. */
26850 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26852 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26853 enum machine_mode mode = GET_MODE (x);
26854 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26862 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26864 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26866 else if (flag_pic && SYMBOLIC_CONST (x)
26868 || (!GET_CODE (x) != LABEL_REF
26869 && (GET_CODE (x) != SYMBOL_REF
26870 || !SYMBOL_REF_LOCAL_P (x)))))
26877 if (mode == VOIDmode)
26880 switch (standard_80387_constant_p (x))
26885 default: /* Other constants */
26890 /* Start with (MEM (SYMBOL_REF)), since that's where
26891 it'll probably end up. Add a penalty for size. */
26892 *total = (COSTS_N_INSNS (1)
26893 + (flag_pic != 0 && !TARGET_64BIT)
26894 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26900 /* The zero extensions is often completely free on x86_64, so make
26901 it as cheap as possible. */
26902 if (TARGET_64BIT && mode == DImode
26903 && GET_MODE (XEXP (x, 0)) == SImode)
26905 else if (TARGET_ZERO_EXTEND_WITH_AND)
26906 *total = cost->add;
26908 *total = cost->movzx;
26912 *total = cost->movsx;
26916 if (CONST_INT_P (XEXP (x, 1))
26917 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26919 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26922 *total = cost->add;
26925 if ((value == 2 || value == 3)
26926 && cost->lea <= cost->shift_const)
26928 *total = cost->lea;
26938 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26940 if (CONST_INT_P (XEXP (x, 1)))
26942 if (INTVAL (XEXP (x, 1)) > 32)
26943 *total = cost->shift_const + COSTS_N_INSNS (2);
26945 *total = cost->shift_const * 2;
26949 if (GET_CODE (XEXP (x, 1)) == AND)
26950 *total = cost->shift_var * 2;
26952 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26957 if (CONST_INT_P (XEXP (x, 1)))
26958 *total = cost->shift_const;
26960 *total = cost->shift_var;
26965 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26967 /* ??? SSE scalar cost should be used here. */
26968 *total = cost->fmul;
26971 else if (X87_FLOAT_MODE_P (mode))
26973 *total = cost->fmul;
26976 else if (FLOAT_MODE_P (mode))
26978 /* ??? SSE vector cost should be used here. */
26979 *total = cost->fmul;
26984 rtx op0 = XEXP (x, 0);
26985 rtx op1 = XEXP (x, 1);
26987 if (CONST_INT_P (XEXP (x, 1)))
26989 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26990 for (nbits = 0; value != 0; value &= value - 1)
26994 /* This is arbitrary. */
26997 /* Compute costs correctly for widening multiplication. */
26998 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26999 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
27000 == GET_MODE_SIZE (mode))
27002 int is_mulwiden = 0;
27003 enum machine_mode inner_mode = GET_MODE (op0);
27005 if (GET_CODE (op0) == GET_CODE (op1))
27006 is_mulwiden = 1, op1 = XEXP (op1, 0);
27007 else if (CONST_INT_P (op1))
27009 if (GET_CODE (op0) == SIGN_EXTEND)
27010 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
27013 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
27017 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
27020 *total = (cost->mult_init[MODE_INDEX (mode)]
27021 + nbits * cost->mult_bit
27022 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
27031 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27032 /* ??? SSE cost should be used here. */
27033 *total = cost->fdiv;
27034 else if (X87_FLOAT_MODE_P (mode))
27035 *total = cost->fdiv;
27036 else if (FLOAT_MODE_P (mode))
27037 /* ??? SSE vector cost should be used here. */
27038 *total = cost->fdiv;
27040 *total = cost->divide[MODE_INDEX (mode)];
27044 if (GET_MODE_CLASS (mode) == MODE_INT
27045 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
27047 if (GET_CODE (XEXP (x, 0)) == PLUS
27048 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
27049 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
27050 && CONSTANT_P (XEXP (x, 1)))
27052 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
27053 if (val == 2 || val == 4 || val == 8)
27055 *total = cost->lea;
27056 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
27057 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
27058 outer_code, speed);
27059 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27063 else if (GET_CODE (XEXP (x, 0)) == MULT
27064 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
27066 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
27067 if (val == 2 || val == 4 || val == 8)
27069 *total = cost->lea;
27070 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
27071 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27075 else if (GET_CODE (XEXP (x, 0)) == PLUS)
27077 *total = cost->lea;
27078 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
27079 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
27080 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27087 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27089 /* ??? SSE cost should be used here. */
27090 *total = cost->fadd;
27093 else if (X87_FLOAT_MODE_P (mode))
27095 *total = cost->fadd;
27098 else if (FLOAT_MODE_P (mode))
27100 /* ??? SSE vector cost should be used here. */
27101 *total = cost->fadd;
27109 if (!TARGET_64BIT && mode == DImode)
27111 *total = (cost->add * 2
27112 + (rtx_cost (XEXP (x, 0), outer_code, speed)
27113 << (GET_MODE (XEXP (x, 0)) != DImode))
27114 + (rtx_cost (XEXP (x, 1), outer_code, speed)
27115 << (GET_MODE (XEXP (x, 1)) != DImode)));
27121 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27123 /* ??? SSE cost should be used here. */
27124 *total = cost->fchs;
27127 else if (X87_FLOAT_MODE_P (mode))
27129 *total = cost->fchs;
27132 else if (FLOAT_MODE_P (mode))
27134 /* ??? SSE vector cost should be used here. */
27135 *total = cost->fchs;
27141 if (!TARGET_64BIT && mode == DImode)
27142 *total = cost->add * 2;
27144 *total = cost->add;
27148 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
27149 && XEXP (XEXP (x, 0), 1) == const1_rtx
27150 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
27151 && XEXP (x, 1) == const0_rtx)
27153 /* This kind of construct is implemented using test[bwl].
27154 Treat it as if we had an AND. */
27155 *total = (cost->add
27156 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
27157 + rtx_cost (const1_rtx, outer_code, speed));
27163 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
27168 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27169 /* ??? SSE cost should be used here. */
27170 *total = cost->fabs;
27171 else if (X87_FLOAT_MODE_P (mode))
27172 *total = cost->fabs;
27173 else if (FLOAT_MODE_P (mode))
27174 /* ??? SSE vector cost should be used here. */
27175 *total = cost->fabs;
27179 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27180 /* ??? SSE cost should be used here. */
27181 *total = cost->fsqrt;
27182 else if (X87_FLOAT_MODE_P (mode))
27183 *total = cost->fsqrt;
27184 else if (FLOAT_MODE_P (mode))
27185 /* ??? SSE vector cost should be used here. */
27186 *total = cost->fsqrt;
27190 if (XINT (x, 1) == UNSPEC_TP)
27201 static int current_machopic_label_num;
27203 /* Given a symbol name and its associated stub, write out the
27204 definition of the stub. */
27207 machopic_output_stub (FILE *file, const char *symb, const char *stub)
27209 unsigned int length;
27210 char *binder_name, *symbol_name, lazy_ptr_name[32];
27211 int label = ++current_machopic_label_num;
27213 /* For 64-bit we shouldn't get here. */
27214 gcc_assert (!TARGET_64BIT);
27216 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
27217 symb = (*targetm.strip_name_encoding) (symb);
27219 length = strlen (stub);
27220 binder_name = XALLOCAVEC (char, length + 32);
27221 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
27223 length = strlen (symb);
27224 symbol_name = XALLOCAVEC (char, length + 32);
27225 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
27227 sprintf (lazy_ptr_name, "L%d$lz", label);
27230 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
27232 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
27234 fprintf (file, "%s:\n", stub);
27235 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27239 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
27240 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
27241 fprintf (file, "\tjmp\t*%%edx\n");
27244 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
27246 fprintf (file, "%s:\n", binder_name);
27250 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
27251 fprintf (file, "\tpushl\t%%eax\n");
27254 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
27256 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
27258 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
27259 fprintf (file, "%s:\n", lazy_ptr_name);
27260 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27261 fprintf (file, "\t.long %s\n", binder_name);
27265 darwin_x86_file_end (void)
27267 darwin_file_end ();
27270 #endif /* TARGET_MACHO */
27272 /* Order the registers for register allocator. */
27275 x86_order_regs_for_local_alloc (void)
27280 /* First allocate the local general purpose registers. */
27281 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27282 if (GENERAL_REGNO_P (i) && call_used_regs[i])
27283 reg_alloc_order [pos++] = i;
27285 /* Global general purpose registers. */
27286 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27287 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
27288 reg_alloc_order [pos++] = i;
27290 /* x87 registers come first in case we are doing FP math
27292 if (!TARGET_SSE_MATH)
27293 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27294 reg_alloc_order [pos++] = i;
27296 /* SSE registers. */
27297 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
27298 reg_alloc_order [pos++] = i;
27299 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
27300 reg_alloc_order [pos++] = i;
27302 /* x87 registers. */
27303 if (TARGET_SSE_MATH)
27304 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27305 reg_alloc_order [pos++] = i;
27307 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
27308 reg_alloc_order [pos++] = i;
27310 /* Initialize the rest of array as we do not allocate some registers
27312 while (pos < FIRST_PSEUDO_REGISTER)
27313 reg_alloc_order [pos++] = 0;
27316 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
27317 struct attribute_spec.handler. */
27319 ix86_handle_abi_attribute (tree *node, tree name,
27320 tree args ATTRIBUTE_UNUSED,
27321 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27323 if (TREE_CODE (*node) != FUNCTION_TYPE
27324 && TREE_CODE (*node) != METHOD_TYPE
27325 && TREE_CODE (*node) != FIELD_DECL
27326 && TREE_CODE (*node) != TYPE_DECL)
27328 warning (OPT_Wattributes, "%qE attribute only applies to functions",
27330 *no_add_attrs = true;
27335 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
27337 *no_add_attrs = true;
27341 /* Can combine regparm with all attributes but fastcall. */
27342 if (is_attribute_p ("ms_abi", name))
27344 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
27346 error ("ms_abi and sysv_abi attributes are not compatible");
27351 else if (is_attribute_p ("sysv_abi", name))
27353 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
27355 error ("ms_abi and sysv_abi attributes are not compatible");
27364 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27365 struct attribute_spec.handler. */
27367 ix86_handle_struct_attribute (tree *node, tree name,
27368 tree args ATTRIBUTE_UNUSED,
27369 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27372 if (DECL_P (*node))
27374 if (TREE_CODE (*node) == TYPE_DECL)
27375 type = &TREE_TYPE (*node);
27380 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
27381 || TREE_CODE (*type) == UNION_TYPE)))
27383 warning (OPT_Wattributes, "%qE attribute ignored",
27385 *no_add_attrs = true;
27388 else if ((is_attribute_p ("ms_struct", name)
27389 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
27390 || ((is_attribute_p ("gcc_struct", name)
27391 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
27393 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
27395 *no_add_attrs = true;
27402 ix86_ms_bitfield_layout_p (const_tree record_type)
27404 return (TARGET_MS_BITFIELD_LAYOUT &&
27405 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
27406 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
27409 /* Returns an expression indicating where the this parameter is
27410 located on entry to the FUNCTION. */
27413 x86_this_parameter (tree function)
27415 tree type = TREE_TYPE (function);
27416 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
27421 const int *parm_regs;
27423 if (ix86_function_type_abi (type) == MS_ABI)
27424 parm_regs = x86_64_ms_abi_int_parameter_registers;
27426 parm_regs = x86_64_int_parameter_registers;
27427 return gen_rtx_REG (DImode, parm_regs[aggr]);
27430 nregs = ix86_function_regparm (type, function);
27432 if (nregs > 0 && !stdarg_p (type))
27436 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
27437 regno = aggr ? DX_REG : CX_REG;
27445 return gen_rtx_MEM (SImode,
27446 plus_constant (stack_pointer_rtx, 4));
27449 return gen_rtx_REG (SImode, regno);
27452 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
27455 /* Determine whether x86_output_mi_thunk can succeed. */
27458 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
27459 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
27460 HOST_WIDE_INT vcall_offset, const_tree function)
27462 /* 64-bit can handle anything. */
27466 /* For 32-bit, everything's fine if we have one free register. */
27467 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
27470 /* Need a free register for vcall_offset. */
27474 /* Need a free register for GOT references. */
27475 if (flag_pic && !(*targetm.binds_local_p) (function))
27478 /* Otherwise ok. */
27482 /* Output the assembler code for a thunk function. THUNK_DECL is the
27483 declaration for the thunk function itself, FUNCTION is the decl for
27484 the target function. DELTA is an immediate constant offset to be
27485 added to THIS. If VCALL_OFFSET is nonzero, the word at
27486 *(*this + vcall_offset) should be added to THIS. */
27489 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
27490 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
27491 HOST_WIDE_INT vcall_offset, tree function)
27494 rtx this_param = x86_this_parameter (function);
27497 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
27498 pull it in now and let DELTA benefit. */
27499 if (REG_P (this_param))
27500 this_reg = this_param;
27501 else if (vcall_offset)
27503 /* Put the this parameter into %eax. */
27504 xops[0] = this_param;
27505 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
27506 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27509 this_reg = NULL_RTX;
27511 /* Adjust the this parameter by a fixed constant. */
27514 xops[0] = GEN_INT (delta);
27515 xops[1] = this_reg ? this_reg : this_param;
27518 if (!x86_64_general_operand (xops[0], DImode))
27520 tmp = gen_rtx_REG (DImode, R10_REG);
27522 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
27524 xops[1] = this_param;
27526 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
27529 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
27532 /* Adjust the this parameter by a value stored in the vtable. */
27536 tmp = gen_rtx_REG (DImode, R10_REG);
27539 int tmp_regno = CX_REG;
27540 if (lookup_attribute ("fastcall",
27541 TYPE_ATTRIBUTES (TREE_TYPE (function))))
27542 tmp_regno = AX_REG;
27543 tmp = gen_rtx_REG (SImode, tmp_regno);
27546 xops[0] = gen_rtx_MEM (Pmode, this_reg);
27548 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27550 /* Adjust the this parameter. */
27551 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
27552 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
27554 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
27555 xops[0] = GEN_INT (vcall_offset);
27557 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
27558 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
27560 xops[1] = this_reg;
27561 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
27564 /* If necessary, drop THIS back to its stack slot. */
27565 if (this_reg && this_reg != this_param)
27567 xops[0] = this_reg;
27568 xops[1] = this_param;
27569 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27572 xops[0] = XEXP (DECL_RTL (function), 0);
27575 if (!flag_pic || (*targetm.binds_local_p) (function))
27576 output_asm_insn ("jmp\t%P0", xops);
27577 /* All thunks should be in the same object as their target,
27578 and thus binds_local_p should be true. */
27579 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
27580 gcc_unreachable ();
27583 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
27584 tmp = gen_rtx_CONST (Pmode, tmp);
27585 tmp = gen_rtx_MEM (QImode, tmp);
27587 output_asm_insn ("jmp\t%A0", xops);
27592 if (!flag_pic || (*targetm.binds_local_p) (function))
27593 output_asm_insn ("jmp\t%P0", xops);
27598 rtx sym_ref = XEXP (DECL_RTL (function), 0);
27599 tmp = (gen_rtx_SYMBOL_REF
27601 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
27602 tmp = gen_rtx_MEM (QImode, tmp);
27604 output_asm_insn ("jmp\t%0", xops);
27607 #endif /* TARGET_MACHO */
27609 tmp = gen_rtx_REG (SImode, CX_REG);
27610 output_set_got (tmp, NULL_RTX);
27613 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
27614 output_asm_insn ("jmp\t{*}%1", xops);
27620 x86_file_start (void)
27622 default_file_start ();
27624 darwin_file_start ();
27626 if (X86_FILE_START_VERSION_DIRECTIVE)
27627 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
27628 if (X86_FILE_START_FLTUSED)
27629 fputs ("\t.global\t__fltused\n", asm_out_file);
27630 if (ix86_asm_dialect == ASM_INTEL)
27631 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
27635 x86_field_alignment (tree field, int computed)
27637 enum machine_mode mode;
27638 tree type = TREE_TYPE (field);
27640 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
27642 mode = TYPE_MODE (strip_array_types (type));
27643 if (mode == DFmode || mode == DCmode
27644 || GET_MODE_CLASS (mode) == MODE_INT
27645 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
27646 return MIN (32, computed);
27650 /* Output assembler code to FILE to increment profiler label # LABELNO
27651 for profiling a function entry. */
27653 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
27657 #ifndef NO_PROFILE_COUNTERS
27658 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
27661 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
27662 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
27664 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
27668 #ifndef NO_PROFILE_COUNTERS
27669 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
27670 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
27672 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
27676 #ifndef NO_PROFILE_COUNTERS
27677 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
27678 PROFILE_COUNT_REGISTER);
27680 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
27684 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27685 /* We don't have exact information about the insn sizes, but we may assume
27686 quite safely that we are informed about all 1 byte insns and memory
27687 address sizes. This is enough to eliminate unnecessary padding in
27691 min_insn_size (rtx insn)
27695 if (!INSN_P (insn) || !active_insn_p (insn))
27698 /* Discard alignments we've emit and jump instructions. */
27699 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
27700 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
27702 if (JUMP_TABLE_DATA_P (insn))
27705 /* Important case - calls are always 5 bytes.
27706 It is common to have many calls in the row. */
27708 && symbolic_reference_mentioned_p (PATTERN (insn))
27709 && !SIBLING_CALL_P (insn))
27711 len = get_attr_length (insn);
27715 /* For normal instructions we rely on get_attr_length being exact,
27716 with a few exceptions. */
27717 if (!JUMP_P (insn))
27719 enum attr_type type = get_attr_type (insn);
27724 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
27725 || asm_noperands (PATTERN (insn)) >= 0)
27732 /* Otherwise trust get_attr_length. */
27736 l = get_attr_length_address (insn);
27737 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
27746 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
27750 ix86_avoid_jump_mispredicts (void)
27752 rtx insn, start = get_insns ();
27753 int nbytes = 0, njumps = 0;
27756 /* Look for all minimal intervals of instructions containing 4 jumps.
27757 The intervals are bounded by START and INSN. NBYTES is the total
27758 size of instructions in the interval including INSN and not including
27759 START. When the NBYTES is smaller than 16 bytes, it is possible
27760 that the end of START and INSN ends up in the same 16byte page.
27762 The smallest offset in the page INSN can start is the case where START
27763 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
27764 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
27766 for (insn = start; insn; insn = NEXT_INSN (insn))
27770 if (LABEL_P (insn))
27772 int align = label_to_alignment (insn);
27773 int max_skip = label_to_max_skip (insn);
27777 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
27778 already in the current 16 byte page, because otherwise
27779 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
27780 bytes to reach 16 byte boundary. */
27782 || (align <= 3 && max_skip != (1 << align) - 1))
27785 fprintf (dump_file, "Label %i with max_skip %i\n",
27786 INSN_UID (insn), max_skip);
27789 while (nbytes + max_skip >= 16)
27791 start = NEXT_INSN (start);
27792 if ((JUMP_P (start)
27793 && GET_CODE (PATTERN (start)) != ADDR_VEC
27794 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27796 njumps--, isjump = 1;
27799 nbytes -= min_insn_size (start);
27805 min_size = min_insn_size (insn);
27806 nbytes += min_size;
27808 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
27809 INSN_UID (insn), min_size);
27811 && GET_CODE (PATTERN (insn)) != ADDR_VEC
27812 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
27820 start = NEXT_INSN (start);
27821 if ((JUMP_P (start)
27822 && GET_CODE (PATTERN (start)) != ADDR_VEC
27823 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27825 njumps--, isjump = 1;
27828 nbytes -= min_insn_size (start);
27830 gcc_assert (njumps >= 0);
27832 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
27833 INSN_UID (start), INSN_UID (insn), nbytes);
27835 if (njumps == 3 && isjump && nbytes < 16)
27837 int padsize = 15 - nbytes + min_insn_size (insn);
27840 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
27841 INSN_UID (insn), padsize);
27842 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
27848 /* AMD Athlon works faster
27849 when RET is not destination of conditional jump or directly preceded
27850 by other jump instruction. We avoid the penalty by inserting NOP just
27851 before the RET instructions in such cases. */
27853 ix86_pad_returns (void)
27858 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27860 basic_block bb = e->src;
27861 rtx ret = BB_END (bb);
27863 bool replace = false;
27865 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27866 || optimize_bb_for_size_p (bb))
27868 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27869 if (active_insn_p (prev) || LABEL_P (prev))
27871 if (prev && LABEL_P (prev))
27876 FOR_EACH_EDGE (e, ei, bb->preds)
27877 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27878 && !(e->flags & EDGE_FALLTHRU))
27883 prev = prev_active_insn (ret);
27885 && ((JUMP_P (prev) && any_condjump_p (prev))
27888 /* Empty functions get branch mispredict even when the jump destination
27889 is not visible to us. */
27890 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27895 emit_jump_insn_before (gen_return_internal_long (), ret);
27901 /* Implement machine specific optimizations. We implement padding of returns
27902 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27906 if (optimize && optimize_function_for_speed_p (cfun))
27908 if (TARGET_PAD_RETURNS)
27909 ix86_pad_returns ();
27910 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27911 if (TARGET_FOUR_JUMP_LIMIT)
27912 ix86_avoid_jump_mispredicts ();
27917 /* Return nonzero when QImode register that must be represented via REX prefix
27920 x86_extended_QIreg_mentioned_p (rtx insn)
27923 extract_insn_cached (insn);
27924 for (i = 0; i < recog_data.n_operands; i++)
27925 if (REG_P (recog_data.operand[i])
27926 && REGNO (recog_data.operand[i]) > BX_REG)
27931 /* Return nonzero when P points to register encoded via REX prefix.
27932 Called via for_each_rtx. */
27934 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27936 unsigned int regno;
27939 regno = REGNO (*p);
27940 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27943 /* Return true when INSN mentions register that must be encoded using REX
27946 x86_extended_reg_mentioned_p (rtx insn)
27948 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27949 extended_reg_mentioned_1, NULL);
27952 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27953 optabs would emit if we didn't have TFmode patterns. */
27956 x86_emit_floatuns (rtx operands[2])
27958 rtx neglab, donelab, i0, i1, f0, in, out;
27959 enum machine_mode mode, inmode;
27961 inmode = GET_MODE (operands[1]);
27962 gcc_assert (inmode == SImode || inmode == DImode);
27965 in = force_reg (inmode, operands[1]);
27966 mode = GET_MODE (out);
27967 neglab = gen_label_rtx ();
27968 donelab = gen_label_rtx ();
27969 f0 = gen_reg_rtx (mode);
27971 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27973 expand_float (out, in, 0);
27975 emit_jump_insn (gen_jump (donelab));
27978 emit_label (neglab);
27980 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27982 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27984 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27986 expand_float (f0, i0, 0);
27988 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27990 emit_label (donelab);
27993 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27994 with all elements equal to VAR. Return true if successful. */
27997 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27998 rtx target, rtx val)
28000 enum machine_mode hmode, smode, wsmode, wvmode;
28015 val = force_reg (GET_MODE_INNER (mode), val);
28016 x = gen_rtx_VEC_DUPLICATE (mode, val);
28017 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28023 if (TARGET_SSE || TARGET_3DNOW_A)
28025 val = gen_lowpart (SImode, val);
28026 x = gen_rtx_TRUNCATE (HImode, val);
28027 x = gen_rtx_VEC_DUPLICATE (mode, x);
28028 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28050 /* Extend HImode to SImode using a paradoxical SUBREG. */
28051 tmp1 = gen_reg_rtx (SImode);
28052 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28053 /* Insert the SImode value as low element of V4SImode vector. */
28054 tmp2 = gen_reg_rtx (V4SImode);
28055 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28056 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28057 CONST0_RTX (V4SImode),
28059 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28060 /* Cast the V4SImode vector back to a V8HImode vector. */
28061 tmp1 = gen_reg_rtx (V8HImode);
28062 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
28063 /* Duplicate the low short through the whole low SImode word. */
28064 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
28065 /* Cast the V8HImode vector back to a V4SImode vector. */
28066 tmp2 = gen_reg_rtx (V4SImode);
28067 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28068 /* Replicate the low element of the V4SImode vector. */
28069 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28070 /* Cast the V2SImode back to V8HImode, and store in target. */
28071 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
28082 /* Extend QImode to SImode using a paradoxical SUBREG. */
28083 tmp1 = gen_reg_rtx (SImode);
28084 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28085 /* Insert the SImode value as low element of V4SImode vector. */
28086 tmp2 = gen_reg_rtx (V4SImode);
28087 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28088 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28089 CONST0_RTX (V4SImode),
28091 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28092 /* Cast the V4SImode vector back to a V16QImode vector. */
28093 tmp1 = gen_reg_rtx (V16QImode);
28094 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
28095 /* Duplicate the low byte through the whole low SImode word. */
28096 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28097 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28098 /* Cast the V16QImode vector back to a V4SImode vector. */
28099 tmp2 = gen_reg_rtx (V4SImode);
28100 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28101 /* Replicate the low element of the V4SImode vector. */
28102 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28103 /* Cast the V2SImode back to V16QImode, and store in target. */
28104 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
28112 /* Replicate the value once into the next wider mode and recurse. */
28113 val = convert_modes (wsmode, smode, val, true);
28114 x = expand_simple_binop (wsmode, ASHIFT, val,
28115 GEN_INT (GET_MODE_BITSIZE (smode)),
28116 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28117 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
28119 x = gen_reg_rtx (wvmode);
28120 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
28121 gcc_unreachable ();
28122 emit_move_insn (target, gen_lowpart (mode, x));
28145 rtx tmp = gen_reg_rtx (hmode);
28146 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
28147 emit_insn (gen_rtx_SET (VOIDmode, target,
28148 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
28157 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28158 whose ONE_VAR element is VAR, and other elements are zero. Return true
28162 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
28163 rtx target, rtx var, int one_var)
28165 enum machine_mode vsimode;
28168 bool use_vector_set = false;
28173 /* For SSE4.1, we normally use vector set. But if the second
28174 element is zero and inter-unit moves are OK, we use movq
28176 use_vector_set = (TARGET_64BIT
28178 && !(TARGET_INTER_UNIT_MOVES
28184 use_vector_set = TARGET_SSE4_1;
28187 use_vector_set = TARGET_SSE2;
28190 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
28197 use_vector_set = TARGET_AVX;
28200 /* Use ix86_expand_vector_set in 64bit mode only. */
28201 use_vector_set = TARGET_AVX && TARGET_64BIT;
28207 if (use_vector_set)
28209 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
28210 var = force_reg (GET_MODE_INNER (mode), var);
28211 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28227 var = force_reg (GET_MODE_INNER (mode), var);
28228 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
28229 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28234 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
28235 new_target = gen_reg_rtx (mode);
28237 new_target = target;
28238 var = force_reg (GET_MODE_INNER (mode), var);
28239 x = gen_rtx_VEC_DUPLICATE (mode, var);
28240 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
28241 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
28244 /* We need to shuffle the value to the correct position, so
28245 create a new pseudo to store the intermediate result. */
28247 /* With SSE2, we can use the integer shuffle insns. */
28248 if (mode != V4SFmode && TARGET_SSE2)
28250 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
28252 GEN_INT (one_var == 1 ? 0 : 1),
28253 GEN_INT (one_var == 2 ? 0 : 1),
28254 GEN_INT (one_var == 3 ? 0 : 1)));
28255 if (target != new_target)
28256 emit_move_insn (target, new_target);
28260 /* Otherwise convert the intermediate result to V4SFmode and
28261 use the SSE1 shuffle instructions. */
28262 if (mode != V4SFmode)
28264 tmp = gen_reg_rtx (V4SFmode);
28265 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
28270 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
28272 GEN_INT (one_var == 1 ? 0 : 1),
28273 GEN_INT (one_var == 2 ? 0+4 : 1+4),
28274 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
28276 if (mode != V4SFmode)
28277 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
28278 else if (tmp != target)
28279 emit_move_insn (target, tmp);
28281 else if (target != new_target)
28282 emit_move_insn (target, new_target);
28287 vsimode = V4SImode;
28293 vsimode = V2SImode;
28299 /* Zero extend the variable element to SImode and recurse. */
28300 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
28302 x = gen_reg_rtx (vsimode);
28303 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
28305 gcc_unreachable ();
28307 emit_move_insn (target, gen_lowpart (mode, x));
28315 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28316 consisting of the values in VALS. It is known that all elements
28317 except ONE_VAR are constants. Return true if successful. */
28320 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
28321 rtx target, rtx vals, int one_var)
28323 rtx var = XVECEXP (vals, 0, one_var);
28324 enum machine_mode wmode;
28327 const_vec = copy_rtx (vals);
28328 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
28329 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
28337 /* For the two element vectors, it's just as easy to use
28338 the general case. */
28342 /* Use ix86_expand_vector_set in 64bit mode only. */
28365 /* There's no way to set one QImode entry easily. Combine
28366 the variable value with its adjacent constant value, and
28367 promote to an HImode set. */
28368 x = XVECEXP (vals, 0, one_var ^ 1);
28371 var = convert_modes (HImode, QImode, var, true);
28372 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
28373 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28374 x = GEN_INT (INTVAL (x) & 0xff);
28378 var = convert_modes (HImode, QImode, var, true);
28379 x = gen_int_mode (INTVAL (x) << 8, HImode);
28381 if (x != const0_rtx)
28382 var = expand_simple_binop (HImode, IOR, var, x, var,
28383 1, OPTAB_LIB_WIDEN);
28385 x = gen_reg_rtx (wmode);
28386 emit_move_insn (x, gen_lowpart (wmode, const_vec));
28387 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
28389 emit_move_insn (target, gen_lowpart (mode, x));
28396 emit_move_insn (target, const_vec);
28397 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28401 /* A subroutine of ix86_expand_vector_init_general. Use vector
28402 concatenate to handle the most general case: all values variable,
28403 and none identical. */
28406 ix86_expand_vector_init_concat (enum machine_mode mode,
28407 rtx target, rtx *ops, int n)
28409 enum machine_mode cmode, hmode = VOIDmode;
28410 rtx first[8], second[4];
28450 gcc_unreachable ();
28453 if (!register_operand (ops[1], cmode))
28454 ops[1] = force_reg (cmode, ops[1]);
28455 if (!register_operand (ops[0], cmode))
28456 ops[0] = force_reg (cmode, ops[0]);
28457 emit_insn (gen_rtx_SET (VOIDmode, target,
28458 gen_rtx_VEC_CONCAT (mode, ops[0],
28478 gcc_unreachable ();
28494 gcc_unreachable ();
28499 /* FIXME: We process inputs backward to help RA. PR 36222. */
28502 for (; i > 0; i -= 2, j--)
28504 first[j] = gen_reg_rtx (cmode);
28505 v = gen_rtvec (2, ops[i - 1], ops[i]);
28506 ix86_expand_vector_init (false, first[j],
28507 gen_rtx_PARALLEL (cmode, v));
28513 gcc_assert (hmode != VOIDmode);
28514 for (i = j = 0; i < n; i += 2, j++)
28516 second[j] = gen_reg_rtx (hmode);
28517 ix86_expand_vector_init_concat (hmode, second [j],
28521 ix86_expand_vector_init_concat (mode, target, second, n);
28524 ix86_expand_vector_init_concat (mode, target, first, n);
28528 gcc_unreachable ();
28532 /* A subroutine of ix86_expand_vector_init_general. Use vector
28533 interleave to handle the most general case: all values variable,
28534 and none identical. */
28537 ix86_expand_vector_init_interleave (enum machine_mode mode,
28538 rtx target, rtx *ops, int n)
28540 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
28543 rtx (*gen_load_even) (rtx, rtx, rtx);
28544 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
28545 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
28550 gen_load_even = gen_vec_setv8hi;
28551 gen_interleave_first_low = gen_vec_interleave_lowv4si;
28552 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28553 inner_mode = HImode;
28554 first_imode = V4SImode;
28555 second_imode = V2DImode;
28556 third_imode = VOIDmode;
28559 gen_load_even = gen_vec_setv16qi;
28560 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
28561 gen_interleave_second_low = gen_vec_interleave_lowv4si;
28562 inner_mode = QImode;
28563 first_imode = V8HImode;
28564 second_imode = V4SImode;
28565 third_imode = V2DImode;
28568 gcc_unreachable ();
28571 for (i = 0; i < n; i++)
28573 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
28574 op0 = gen_reg_rtx (SImode);
28575 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
28577 /* Insert the SImode value as low element of V4SImode vector. */
28578 op1 = gen_reg_rtx (V4SImode);
28579 op0 = gen_rtx_VEC_MERGE (V4SImode,
28580 gen_rtx_VEC_DUPLICATE (V4SImode,
28582 CONST0_RTX (V4SImode),
28584 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
28586 /* Cast the V4SImode vector back to a vector in orignal mode. */
28587 op0 = gen_reg_rtx (mode);
28588 emit_move_insn (op0, gen_lowpart (mode, op1));
28590 /* Load even elements into the second positon. */
28591 emit_insn ((*gen_load_even) (op0,
28592 force_reg (inner_mode,
28596 /* Cast vector to FIRST_IMODE vector. */
28597 ops[i] = gen_reg_rtx (first_imode);
28598 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
28601 /* Interleave low FIRST_IMODE vectors. */
28602 for (i = j = 0; i < n; i += 2, j++)
28604 op0 = gen_reg_rtx (first_imode);
28605 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
28607 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
28608 ops[j] = gen_reg_rtx (second_imode);
28609 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
28612 /* Interleave low SECOND_IMODE vectors. */
28613 switch (second_imode)
28616 for (i = j = 0; i < n / 2; i += 2, j++)
28618 op0 = gen_reg_rtx (second_imode);
28619 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
28622 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
28624 ops[j] = gen_reg_rtx (third_imode);
28625 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
28627 second_imode = V2DImode;
28628 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28632 op0 = gen_reg_rtx (second_imode);
28633 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
28636 /* Cast the SECOND_IMODE vector back to a vector on original
28638 emit_insn (gen_rtx_SET (VOIDmode, target,
28639 gen_lowpart (mode, op0)));
28643 gcc_unreachable ();
28647 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
28648 all values variable, and none identical. */
28651 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
28652 rtx target, rtx vals)
28654 rtx ops[32], op0, op1;
28655 enum machine_mode half_mode = VOIDmode;
28662 if (!mmx_ok && !TARGET_SSE)
28674 n = GET_MODE_NUNITS (mode);
28675 for (i = 0; i < n; i++)
28676 ops[i] = XVECEXP (vals, 0, i);
28677 ix86_expand_vector_init_concat (mode, target, ops, n);
28681 half_mode = V16QImode;
28685 half_mode = V8HImode;
28689 n = GET_MODE_NUNITS (mode);
28690 for (i = 0; i < n; i++)
28691 ops[i] = XVECEXP (vals, 0, i);
28692 op0 = gen_reg_rtx (half_mode);
28693 op1 = gen_reg_rtx (half_mode);
28694 ix86_expand_vector_init_interleave (half_mode, op0, ops,
28696 ix86_expand_vector_init_interleave (half_mode, op1,
28697 &ops [n >> 1], n >> 2);
28698 emit_insn (gen_rtx_SET (VOIDmode, target,
28699 gen_rtx_VEC_CONCAT (mode, op0, op1)));
28703 if (!TARGET_SSE4_1)
28711 /* Don't use ix86_expand_vector_init_interleave if we can't
28712 move from GPR to SSE register directly. */
28713 if (!TARGET_INTER_UNIT_MOVES)
28716 n = GET_MODE_NUNITS (mode);
28717 for (i = 0; i < n; i++)
28718 ops[i] = XVECEXP (vals, 0, i);
28719 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
28727 gcc_unreachable ();
28731 int i, j, n_elts, n_words, n_elt_per_word;
28732 enum machine_mode inner_mode;
28733 rtx words[4], shift;
28735 inner_mode = GET_MODE_INNER (mode);
28736 n_elts = GET_MODE_NUNITS (mode);
28737 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
28738 n_elt_per_word = n_elts / n_words;
28739 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
28741 for (i = 0; i < n_words; ++i)
28743 rtx word = NULL_RTX;
28745 for (j = 0; j < n_elt_per_word; ++j)
28747 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
28748 elt = convert_modes (word_mode, inner_mode, elt, true);
28754 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
28755 word, 1, OPTAB_LIB_WIDEN);
28756 word = expand_simple_binop (word_mode, IOR, word, elt,
28757 word, 1, OPTAB_LIB_WIDEN);
28765 emit_move_insn (target, gen_lowpart (mode, words[0]));
28766 else if (n_words == 2)
28768 rtx tmp = gen_reg_rtx (mode);
28769 emit_clobber (tmp);
28770 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
28771 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
28772 emit_move_insn (target, tmp);
28774 else if (n_words == 4)
28776 rtx tmp = gen_reg_rtx (V4SImode);
28777 gcc_assert (word_mode == SImode);
28778 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
28779 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
28780 emit_move_insn (target, gen_lowpart (mode, tmp));
28783 gcc_unreachable ();
28787 /* Initialize vector TARGET via VALS. Suppress the use of MMX
28788 instructions unless MMX_OK is true. */
28791 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
28793 enum machine_mode mode = GET_MODE (target);
28794 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28795 int n_elts = GET_MODE_NUNITS (mode);
28796 int n_var = 0, one_var = -1;
28797 bool all_same = true, all_const_zero = true;
28801 for (i = 0; i < n_elts; ++i)
28803 x = XVECEXP (vals, 0, i);
28804 if (!(CONST_INT_P (x)
28805 || GET_CODE (x) == CONST_DOUBLE
28806 || GET_CODE (x) == CONST_FIXED))
28807 n_var++, one_var = i;
28808 else if (x != CONST0_RTX (inner_mode))
28809 all_const_zero = false;
28810 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
28814 /* Constants are best loaded from the constant pool. */
28817 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
28821 /* If all values are identical, broadcast the value. */
28823 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
28824 XVECEXP (vals, 0, 0)))
28827 /* Values where only one field is non-constant are best loaded from
28828 the pool and overwritten via move later. */
28832 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
28833 XVECEXP (vals, 0, one_var),
28837 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
28841 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
28845 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
28847 enum machine_mode mode = GET_MODE (target);
28848 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28849 enum machine_mode half_mode;
28850 bool use_vec_merge = false;
28852 static rtx (*gen_extract[6][2]) (rtx, rtx)
28854 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
28855 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
28856 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
28857 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
28858 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
28859 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
28861 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28863 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28864 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28865 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28866 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28867 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28868 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28878 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28879 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28881 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28883 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28884 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28890 use_vec_merge = TARGET_SSE4_1;
28898 /* For the two element vectors, we implement a VEC_CONCAT with
28899 the extraction of the other element. */
28901 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28902 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28905 op0 = val, op1 = tmp;
28907 op0 = tmp, op1 = val;
28909 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28910 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28915 use_vec_merge = TARGET_SSE4_1;
28922 use_vec_merge = true;
28926 /* tmp = target = A B C D */
28927 tmp = copy_to_reg (target);
28928 /* target = A A B B */
28929 emit_insn (gen_sse_unpcklps (target, target, target));
28930 /* target = X A B B */
28931 ix86_expand_vector_set (false, target, val, 0);
28932 /* target = A X C D */
28933 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28934 GEN_INT (1), GEN_INT (0),
28935 GEN_INT (2+4), GEN_INT (3+4)));
28939 /* tmp = target = A B C D */
28940 tmp = copy_to_reg (target);
28941 /* tmp = X B C D */
28942 ix86_expand_vector_set (false, tmp, val, 0);
28943 /* target = A B X D */
28944 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28945 GEN_INT (0), GEN_INT (1),
28946 GEN_INT (0+4), GEN_INT (3+4)));
28950 /* tmp = target = A B C D */
28951 tmp = copy_to_reg (target);
28952 /* tmp = X B C D */
28953 ix86_expand_vector_set (false, tmp, val, 0);
28954 /* target = A B X D */
28955 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28956 GEN_INT (0), GEN_INT (1),
28957 GEN_INT (2+4), GEN_INT (0+4)));
28961 gcc_unreachable ();
28966 use_vec_merge = TARGET_SSE4_1;
28970 /* Element 0 handled by vec_merge below. */
28973 use_vec_merge = true;
28979 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28980 store into element 0, then shuffle them back. */
28984 order[0] = GEN_INT (elt);
28985 order[1] = const1_rtx;
28986 order[2] = const2_rtx;
28987 order[3] = GEN_INT (3);
28988 order[elt] = const0_rtx;
28990 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28991 order[1], order[2], order[3]));
28993 ix86_expand_vector_set (false, target, val, 0);
28995 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28996 order[1], order[2], order[3]));
29000 /* For SSE1, we have to reuse the V4SF code. */
29001 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
29002 gen_lowpart (SFmode, val), elt);
29007 use_vec_merge = TARGET_SSE2;
29010 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
29014 use_vec_merge = TARGET_SSE4_1;
29021 half_mode = V16QImode;
29027 half_mode = V8HImode;
29033 half_mode = V4SImode;
29039 half_mode = V2DImode;
29045 half_mode = V4SFmode;
29051 half_mode = V2DFmode;
29057 /* Compute offset. */
29061 gcc_assert (i <= 1);
29063 /* Extract the half. */
29064 tmp = gen_reg_rtx (half_mode);
29065 emit_insn ((*gen_extract[j][i]) (tmp, target));
29067 /* Put val in tmp at elt. */
29068 ix86_expand_vector_set (false, tmp, val, elt);
29071 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
29080 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
29081 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
29082 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29086 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29088 emit_move_insn (mem, target);
29090 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29091 emit_move_insn (tmp, val);
29093 emit_move_insn (target, mem);
29098 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
29100 enum machine_mode mode = GET_MODE (vec);
29101 enum machine_mode inner_mode = GET_MODE_INNER (mode);
29102 bool use_vec_extr = false;
29115 use_vec_extr = true;
29119 use_vec_extr = TARGET_SSE4_1;
29131 tmp = gen_reg_rtx (mode);
29132 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
29133 GEN_INT (elt), GEN_INT (elt),
29134 GEN_INT (elt+4), GEN_INT (elt+4)));
29138 tmp = gen_reg_rtx (mode);
29139 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
29143 gcc_unreachable ();
29146 use_vec_extr = true;
29151 use_vec_extr = TARGET_SSE4_1;
29165 tmp = gen_reg_rtx (mode);
29166 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
29167 GEN_INT (elt), GEN_INT (elt),
29168 GEN_INT (elt), GEN_INT (elt)));
29172 tmp = gen_reg_rtx (mode);
29173 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
29177 gcc_unreachable ();
29180 use_vec_extr = true;
29185 /* For SSE1, we have to reuse the V4SF code. */
29186 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
29187 gen_lowpart (V4SFmode, vec), elt);
29193 use_vec_extr = TARGET_SSE2;
29196 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
29200 use_vec_extr = TARGET_SSE4_1;
29204 /* ??? Could extract the appropriate HImode element and shift. */
29211 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
29212 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
29214 /* Let the rtl optimizers know about the zero extension performed. */
29215 if (inner_mode == QImode || inner_mode == HImode)
29217 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
29218 target = gen_lowpart (SImode, target);
29221 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29225 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29227 emit_move_insn (mem, vec);
29229 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29230 emit_move_insn (target, tmp);
29234 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
29235 pattern to reduce; DEST is the destination; IN is the input vector. */
29238 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
29240 rtx tmp1, tmp2, tmp3;
29242 tmp1 = gen_reg_rtx (V4SFmode);
29243 tmp2 = gen_reg_rtx (V4SFmode);
29244 tmp3 = gen_reg_rtx (V4SFmode);
29246 emit_insn (gen_sse_movhlps (tmp1, in, in));
29247 emit_insn (fn (tmp2, tmp1, in));
29249 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
29250 GEN_INT (1), GEN_INT (1),
29251 GEN_INT (1+4), GEN_INT (1+4)));
29252 emit_insn (fn (dest, tmp2, tmp3));
29255 /* Target hook for scalar_mode_supported_p. */
29257 ix86_scalar_mode_supported_p (enum machine_mode mode)
29259 if (DECIMAL_FLOAT_MODE_P (mode))
29261 else if (mode == TFmode)
29264 return default_scalar_mode_supported_p (mode);
29267 /* Implements target hook vector_mode_supported_p. */
29269 ix86_vector_mode_supported_p (enum machine_mode mode)
29271 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
29273 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
29275 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
29277 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
29279 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
29284 /* Target hook for c_mode_for_suffix. */
29285 static enum machine_mode
29286 ix86_c_mode_for_suffix (char suffix)
29296 /* Worker function for TARGET_MD_ASM_CLOBBERS.
29298 We do this in the new i386 backend to maintain source compatibility
29299 with the old cc0-based compiler. */
29302 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
29303 tree inputs ATTRIBUTE_UNUSED,
29306 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
29308 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
29313 /* Implements target vector targetm.asm.encode_section_info. This
29314 is not used by netware. */
29316 static void ATTRIBUTE_UNUSED
29317 ix86_encode_section_info (tree decl, rtx rtl, int first)
29319 default_encode_section_info (decl, rtl, first);
29321 if (TREE_CODE (decl) == VAR_DECL
29322 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
29323 && ix86_in_large_data_p (decl))
29324 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
29327 /* Worker function for REVERSE_CONDITION. */
29330 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
29332 return (mode != CCFPmode && mode != CCFPUmode
29333 ? reverse_condition (code)
29334 : reverse_condition_maybe_unordered (code));
29337 /* Output code to perform an x87 FP register move, from OPERANDS[1]
29341 output_387_reg_move (rtx insn, rtx *operands)
29343 if (REG_P (operands[0]))
29345 if (REG_P (operands[1])
29346 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29348 if (REGNO (operands[0]) == FIRST_STACK_REG)
29349 return output_387_ffreep (operands, 0);
29350 return "fstp\t%y0";
29352 if (STACK_TOP_P (operands[0]))
29353 return "fld%Z1\t%y1";
29356 else if (MEM_P (operands[0]))
29358 gcc_assert (REG_P (operands[1]));
29359 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29360 return "fstp%Z0\t%y0";
29363 /* There is no non-popping store to memory for XFmode.
29364 So if we need one, follow the store with a load. */
29365 if (GET_MODE (operands[0]) == XFmode)
29366 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
29368 return "fst%Z0\t%y0";
29375 /* Output code to perform a conditional jump to LABEL, if C2 flag in
29376 FP status register is set. */
29379 ix86_emit_fp_unordered_jump (rtx label)
29381 rtx reg = gen_reg_rtx (HImode);
29384 emit_insn (gen_x86_fnstsw_1 (reg));
29386 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
29388 emit_insn (gen_x86_sahf_1 (reg));
29390 temp = gen_rtx_REG (CCmode, FLAGS_REG);
29391 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
29395 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
29397 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
29398 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
29401 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
29402 gen_rtx_LABEL_REF (VOIDmode, label),
29404 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
29406 emit_jump_insn (temp);
29407 predict_jump (REG_BR_PROB_BASE * 10 / 100);
29410 /* Output code to perform a log1p XFmode calculation. */
29412 void ix86_emit_i387_log1p (rtx op0, rtx op1)
29414 rtx label1 = gen_label_rtx ();
29415 rtx label2 = gen_label_rtx ();
29417 rtx tmp = gen_reg_rtx (XFmode);
29418 rtx tmp2 = gen_reg_rtx (XFmode);
29421 emit_insn (gen_absxf2 (tmp, op1));
29422 test = gen_rtx_GE (VOIDmode, tmp,
29423 CONST_DOUBLE_FROM_REAL_VALUE (
29424 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
29426 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
29428 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29429 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
29430 emit_jump (label2);
29432 emit_label (label1);
29433 emit_move_insn (tmp, CONST1_RTX (XFmode));
29434 emit_insn (gen_addxf3 (tmp, op1, tmp));
29435 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29436 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
29438 emit_label (label2);
29441 /* Output code to perform a Newton-Rhapson approximation of a single precision
29442 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
29444 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
29446 rtx x0, x1, e0, e1, two;
29448 x0 = gen_reg_rtx (mode);
29449 e0 = gen_reg_rtx (mode);
29450 e1 = gen_reg_rtx (mode);
29451 x1 = gen_reg_rtx (mode);
29453 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
29455 if (VECTOR_MODE_P (mode))
29456 two = ix86_build_const_vector (SFmode, true, two);
29458 two = force_reg (mode, two);
29460 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
29462 /* x0 = rcp(b) estimate */
29463 emit_insn (gen_rtx_SET (VOIDmode, x0,
29464 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
29467 emit_insn (gen_rtx_SET (VOIDmode, e0,
29468 gen_rtx_MULT (mode, x0, b)));
29470 emit_insn (gen_rtx_SET (VOIDmode, e1,
29471 gen_rtx_MINUS (mode, two, e0)));
29473 emit_insn (gen_rtx_SET (VOIDmode, x1,
29474 gen_rtx_MULT (mode, x0, e1)));
29476 emit_insn (gen_rtx_SET (VOIDmode, res,
29477 gen_rtx_MULT (mode, a, x1)));
29480 /* Output code to perform a Newton-Rhapson approximation of a
29481 single precision floating point [reciprocal] square root. */
29483 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
29486 rtx x0, e0, e1, e2, e3, mthree, mhalf;
29489 x0 = gen_reg_rtx (mode);
29490 e0 = gen_reg_rtx (mode);
29491 e1 = gen_reg_rtx (mode);
29492 e2 = gen_reg_rtx (mode);
29493 e3 = gen_reg_rtx (mode);
29495 real_from_integer (&r, VOIDmode, -3, -1, 0);
29496 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29498 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
29499 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29501 if (VECTOR_MODE_P (mode))
29503 mthree = ix86_build_const_vector (SFmode, true, mthree);
29504 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
29507 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
29508 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
29510 /* x0 = rsqrt(a) estimate */
29511 emit_insn (gen_rtx_SET (VOIDmode, x0,
29512 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
29515 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
29520 zero = gen_reg_rtx (mode);
29521 mask = gen_reg_rtx (mode);
29523 zero = force_reg (mode, CONST0_RTX(mode));
29524 emit_insn (gen_rtx_SET (VOIDmode, mask,
29525 gen_rtx_NE (mode, zero, a)));
29527 emit_insn (gen_rtx_SET (VOIDmode, x0,
29528 gen_rtx_AND (mode, x0, mask)));
29532 emit_insn (gen_rtx_SET (VOIDmode, e0,
29533 gen_rtx_MULT (mode, x0, a)));
29535 emit_insn (gen_rtx_SET (VOIDmode, e1,
29536 gen_rtx_MULT (mode, e0, x0)));
29539 mthree = force_reg (mode, mthree);
29540 emit_insn (gen_rtx_SET (VOIDmode, e2,
29541 gen_rtx_PLUS (mode, e1, mthree)));
29543 mhalf = force_reg (mode, mhalf);
29545 /* e3 = -.5 * x0 */
29546 emit_insn (gen_rtx_SET (VOIDmode, e3,
29547 gen_rtx_MULT (mode, x0, mhalf)));
29549 /* e3 = -.5 * e0 */
29550 emit_insn (gen_rtx_SET (VOIDmode, e3,
29551 gen_rtx_MULT (mode, e0, mhalf)));
29552 /* ret = e2 * e3 */
29553 emit_insn (gen_rtx_SET (VOIDmode, res,
29554 gen_rtx_MULT (mode, e2, e3)));
29557 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
29559 static void ATTRIBUTE_UNUSED
29560 i386_solaris_elf_named_section (const char *name, unsigned int flags,
29563 /* With Binutils 2.15, the "@unwind" marker must be specified on
29564 every occurrence of the ".eh_frame" section, not just the first
29567 && strcmp (name, ".eh_frame") == 0)
29569 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
29570 flags & SECTION_WRITE ? "aw" : "a");
29573 default_elf_asm_named_section (name, flags, decl);
29576 /* Return the mangling of TYPE if it is an extended fundamental type. */
29578 static const char *
29579 ix86_mangle_type (const_tree type)
29581 type = TYPE_MAIN_VARIANT (type);
29583 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
29584 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
29587 switch (TYPE_MODE (type))
29590 /* __float128 is "g". */
29593 /* "long double" or __float80 is "e". */
29600 /* For 32-bit code we can save PIC register setup by using
29601 __stack_chk_fail_local hidden function instead of calling
29602 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
29603 register, so it is better to call __stack_chk_fail directly. */
29606 ix86_stack_protect_fail (void)
29608 return TARGET_64BIT
29609 ? default_external_stack_protect_fail ()
29610 : default_hidden_stack_protect_fail ();
29613 /* Select a format to encode pointers in exception handling data. CODE
29614 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
29615 true if the symbol may be affected by dynamic relocations.
29617 ??? All x86 object file formats are capable of representing this.
29618 After all, the relocation needed is the same as for the call insn.
29619 Whether or not a particular assembler allows us to enter such, I
29620 guess we'll have to see. */
29622 asm_preferred_eh_data_format (int code, int global)
29626 int type = DW_EH_PE_sdata8;
29628 || ix86_cmodel == CM_SMALL_PIC
29629 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
29630 type = DW_EH_PE_sdata4;
29631 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
29633 if (ix86_cmodel == CM_SMALL
29634 || (ix86_cmodel == CM_MEDIUM && code))
29635 return DW_EH_PE_udata4;
29636 return DW_EH_PE_absptr;
29639 /* Expand copysign from SIGN to the positive value ABS_VALUE
29640 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
29643 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
29645 enum machine_mode mode = GET_MODE (sign);
29646 rtx sgn = gen_reg_rtx (mode);
29647 if (mask == NULL_RTX)
29649 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
29650 if (!VECTOR_MODE_P (mode))
29652 /* We need to generate a scalar mode mask in this case. */
29653 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29654 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29655 mask = gen_reg_rtx (mode);
29656 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29660 mask = gen_rtx_NOT (mode, mask);
29661 emit_insn (gen_rtx_SET (VOIDmode, sgn,
29662 gen_rtx_AND (mode, mask, sign)));
29663 emit_insn (gen_rtx_SET (VOIDmode, result,
29664 gen_rtx_IOR (mode, abs_value, sgn)));
29667 /* Expand fabs (OP0) and return a new rtx that holds the result. The
29668 mask for masking out the sign-bit is stored in *SMASK, if that is
29671 ix86_expand_sse_fabs (rtx op0, rtx *smask)
29673 enum machine_mode mode = GET_MODE (op0);
29676 xa = gen_reg_rtx (mode);
29677 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
29678 if (!VECTOR_MODE_P (mode))
29680 /* We need to generate a scalar mode mask in this case. */
29681 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29682 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29683 mask = gen_reg_rtx (mode);
29684 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29686 emit_insn (gen_rtx_SET (VOIDmode, xa,
29687 gen_rtx_AND (mode, op0, mask)));
29695 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
29696 swapping the operands if SWAP_OPERANDS is true. The expanded
29697 code is a forward jump to a newly created label in case the
29698 comparison is true. The generated label rtx is returned. */
29700 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
29701 bool swap_operands)
29712 label = gen_label_rtx ();
29713 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
29714 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29715 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
29716 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
29717 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
29718 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
29719 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
29720 JUMP_LABEL (tmp) = label;
29725 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
29726 using comparison code CODE. Operands are swapped for the comparison if
29727 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
29729 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
29730 bool swap_operands)
29732 enum machine_mode mode = GET_MODE (op0);
29733 rtx mask = gen_reg_rtx (mode);
29742 if (mode == DFmode)
29743 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
29744 gen_rtx_fmt_ee (code, mode, op0, op1)));
29746 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
29747 gen_rtx_fmt_ee (code, mode, op0, op1)));
29752 /* Generate and return a rtx of mode MODE for 2**n where n is the number
29753 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
29755 ix86_gen_TWO52 (enum machine_mode mode)
29757 REAL_VALUE_TYPE TWO52r;
29760 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
29761 TWO52 = const_double_from_real_value (TWO52r, mode);
29762 TWO52 = force_reg (mode, TWO52);
29767 /* Expand SSE sequence for computing lround from OP1 storing
29770 ix86_expand_lround (rtx op0, rtx op1)
29772 /* C code for the stuff we're doing below:
29773 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
29776 enum machine_mode mode = GET_MODE (op1);
29777 const struct real_format *fmt;
29778 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29781 /* load nextafter (0.5, 0.0) */
29782 fmt = REAL_MODE_FORMAT (mode);
29783 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29784 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29786 /* adj = copysign (0.5, op1) */
29787 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
29788 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
29790 /* adj = op1 + adj */
29791 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
29793 /* op0 = (imode)adj */
29794 expand_fix (op0, adj, 0);
29797 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
29800 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
29802 /* C code for the stuff we're doing below (for do_floor):
29804 xi -= (double)xi > op1 ? 1 : 0;
29807 enum machine_mode fmode = GET_MODE (op1);
29808 enum machine_mode imode = GET_MODE (op0);
29809 rtx ireg, freg, label, tmp;
29811 /* reg = (long)op1 */
29812 ireg = gen_reg_rtx (imode);
29813 expand_fix (ireg, op1, 0);
29815 /* freg = (double)reg */
29816 freg = gen_reg_rtx (fmode);
29817 expand_float (freg, ireg, 0);
29819 /* ireg = (freg > op1) ? ireg - 1 : ireg */
29820 label = ix86_expand_sse_compare_and_jump (UNLE,
29821 freg, op1, !do_floor);
29822 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
29823 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
29824 emit_move_insn (ireg, tmp);
29826 emit_label (label);
29827 LABEL_NUSES (label) = 1;
29829 emit_move_insn (op0, ireg);
29832 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
29833 result in OPERAND0. */
29835 ix86_expand_rint (rtx operand0, rtx operand1)
29837 /* C code for the stuff we're doing below:
29838 xa = fabs (operand1);
29839 if (!isless (xa, 2**52))
29841 xa = xa + 2**52 - 2**52;
29842 return copysign (xa, operand1);
29844 enum machine_mode mode = GET_MODE (operand0);
29845 rtx res, xa, label, TWO52, mask;
29847 res = gen_reg_rtx (mode);
29848 emit_move_insn (res, operand1);
29850 /* xa = abs (operand1) */
29851 xa = ix86_expand_sse_fabs (res, &mask);
29853 /* if (!isless (xa, TWO52)) goto label; */
29854 TWO52 = ix86_gen_TWO52 (mode);
29855 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29857 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29858 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29860 ix86_sse_copysign_to_positive (res, xa, res, mask);
29862 emit_label (label);
29863 LABEL_NUSES (label) = 1;
29865 emit_move_insn (operand0, res);
29868 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29871 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29873 /* C code for the stuff we expand below.
29874 double xa = fabs (x), x2;
29875 if (!isless (xa, TWO52))
29877 xa = xa + TWO52 - TWO52;
29878 x2 = copysign (xa, x);
29887 enum machine_mode mode = GET_MODE (operand0);
29888 rtx xa, TWO52, tmp, label, one, res, mask;
29890 TWO52 = ix86_gen_TWO52 (mode);
29892 /* Temporary for holding the result, initialized to the input
29893 operand to ease control flow. */
29894 res = gen_reg_rtx (mode);
29895 emit_move_insn (res, operand1);
29897 /* xa = abs (operand1) */
29898 xa = ix86_expand_sse_fabs (res, &mask);
29900 /* if (!isless (xa, TWO52)) goto label; */
29901 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29903 /* xa = xa + TWO52 - TWO52; */
29904 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29905 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29907 /* xa = copysign (xa, operand1) */
29908 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29910 /* generate 1.0 or -1.0 */
29911 one = force_reg (mode,
29912 const_double_from_real_value (do_floor
29913 ? dconst1 : dconstm1, mode));
29915 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29916 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29917 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29918 gen_rtx_AND (mode, one, tmp)));
29919 /* We always need to subtract here to preserve signed zero. */
29920 tmp = expand_simple_binop (mode, MINUS,
29921 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29922 emit_move_insn (res, tmp);
29924 emit_label (label);
29925 LABEL_NUSES (label) = 1;
29927 emit_move_insn (operand0, res);
29930 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29933 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29935 /* C code for the stuff we expand below.
29936 double xa = fabs (x), x2;
29937 if (!isless (xa, TWO52))
29939 x2 = (double)(long)x;
29946 if (HONOR_SIGNED_ZEROS (mode))
29947 return copysign (x2, x);
29950 enum machine_mode mode = GET_MODE (operand0);
29951 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29953 TWO52 = ix86_gen_TWO52 (mode);
29955 /* Temporary for holding the result, initialized to the input
29956 operand to ease control flow. */
29957 res = gen_reg_rtx (mode);
29958 emit_move_insn (res, operand1);
29960 /* xa = abs (operand1) */
29961 xa = ix86_expand_sse_fabs (res, &mask);
29963 /* if (!isless (xa, TWO52)) goto label; */
29964 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29966 /* xa = (double)(long)x */
29967 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29968 expand_fix (xi, res, 0);
29969 expand_float (xa, xi, 0);
29972 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29974 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29975 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29976 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29977 gen_rtx_AND (mode, one, tmp)));
29978 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29979 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29980 emit_move_insn (res, tmp);
29982 if (HONOR_SIGNED_ZEROS (mode))
29983 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29985 emit_label (label);
29986 LABEL_NUSES (label) = 1;
29988 emit_move_insn (operand0, res);
29991 /* Expand SSE sequence for computing round from OPERAND1 storing
29992 into OPERAND0. Sequence that works without relying on DImode truncation
29993 via cvttsd2siq that is only available on 64bit targets. */
29995 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29997 /* C code for the stuff we expand below.
29998 double xa = fabs (x), xa2, x2;
29999 if (!isless (xa, TWO52))
30001 Using the absolute value and copying back sign makes
30002 -0.0 -> -0.0 correct.
30003 xa2 = xa + TWO52 - TWO52;
30008 else if (dxa > 0.5)
30010 x2 = copysign (xa2, x);
30013 enum machine_mode mode = GET_MODE (operand0);
30014 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
30016 TWO52 = ix86_gen_TWO52 (mode);
30018 /* Temporary for holding the result, initialized to the input
30019 operand to ease control flow. */
30020 res = gen_reg_rtx (mode);
30021 emit_move_insn (res, operand1);
30023 /* xa = abs (operand1) */
30024 xa = ix86_expand_sse_fabs (res, &mask);
30026 /* if (!isless (xa, TWO52)) goto label; */
30027 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30029 /* xa2 = xa + TWO52 - TWO52; */
30030 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
30031 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
30033 /* dxa = xa2 - xa; */
30034 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
30036 /* generate 0.5, 1.0 and -0.5 */
30037 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
30038 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
30039 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
30043 tmp = gen_reg_rtx (mode);
30044 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
30045 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
30046 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30047 gen_rtx_AND (mode, one, tmp)));
30048 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30049 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
30050 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
30051 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30052 gen_rtx_AND (mode, one, tmp)));
30053 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30055 /* res = copysign (xa2, operand1) */
30056 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
30058 emit_label (label);
30059 LABEL_NUSES (label) = 1;
30061 emit_move_insn (operand0, res);
30064 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30067 ix86_expand_trunc (rtx operand0, rtx operand1)
30069 /* C code for SSE variant we expand below.
30070 double xa = fabs (x), x2;
30071 if (!isless (xa, TWO52))
30073 x2 = (double)(long)x;
30074 if (HONOR_SIGNED_ZEROS (mode))
30075 return copysign (x2, x);
30078 enum machine_mode mode = GET_MODE (operand0);
30079 rtx xa, xi, TWO52, label, res, mask;
30081 TWO52 = ix86_gen_TWO52 (mode);
30083 /* Temporary for holding the result, initialized to the input
30084 operand to ease control flow. */
30085 res = gen_reg_rtx (mode);
30086 emit_move_insn (res, operand1);
30088 /* xa = abs (operand1) */
30089 xa = ix86_expand_sse_fabs (res, &mask);
30091 /* if (!isless (xa, TWO52)) goto label; */
30092 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30094 /* x = (double)(long)x */
30095 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30096 expand_fix (xi, res, 0);
30097 expand_float (res, xi, 0);
30099 if (HONOR_SIGNED_ZEROS (mode))
30100 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
30102 emit_label (label);
30103 LABEL_NUSES (label) = 1;
30105 emit_move_insn (operand0, res);
30108 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30111 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
30113 enum machine_mode mode = GET_MODE (operand0);
30114 rtx xa, mask, TWO52, label, one, res, smask, tmp;
30116 /* C code for SSE variant we expand below.
30117 double xa = fabs (x), x2;
30118 if (!isless (xa, TWO52))
30120 xa2 = xa + TWO52 - TWO52;
30124 x2 = copysign (xa2, x);
30128 TWO52 = ix86_gen_TWO52 (mode);
30130 /* Temporary for holding the result, initialized to the input
30131 operand to ease control flow. */
30132 res = gen_reg_rtx (mode);
30133 emit_move_insn (res, operand1);
30135 /* xa = abs (operand1) */
30136 xa = ix86_expand_sse_fabs (res, &smask);
30138 /* if (!isless (xa, TWO52)) goto label; */
30139 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30141 /* res = xa + TWO52 - TWO52; */
30142 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
30143 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
30144 emit_move_insn (res, tmp);
30147 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
30149 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
30150 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
30151 emit_insn (gen_rtx_SET (VOIDmode, mask,
30152 gen_rtx_AND (mode, mask, one)));
30153 tmp = expand_simple_binop (mode, MINUS,
30154 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
30155 emit_move_insn (res, tmp);
30157 /* res = copysign (res, operand1) */
30158 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
30160 emit_label (label);
30161 LABEL_NUSES (label) = 1;
30163 emit_move_insn (operand0, res);
30166 /* Expand SSE sequence for computing round from OPERAND1 storing
30169 ix86_expand_round (rtx operand0, rtx operand1)
30171 /* C code for the stuff we're doing below:
30172 double xa = fabs (x);
30173 if (!isless (xa, TWO52))
30175 xa = (double)(long)(xa + nextafter (0.5, 0.0));
30176 return copysign (xa, x);
30178 enum machine_mode mode = GET_MODE (operand0);
30179 rtx res, TWO52, xa, label, xi, half, mask;
30180 const struct real_format *fmt;
30181 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
30183 /* Temporary for holding the result, initialized to the input
30184 operand to ease control flow. */
30185 res = gen_reg_rtx (mode);
30186 emit_move_insn (res, operand1);
30188 TWO52 = ix86_gen_TWO52 (mode);
30189 xa = ix86_expand_sse_fabs (res, &mask);
30190 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30192 /* load nextafter (0.5, 0.0) */
30193 fmt = REAL_MODE_FORMAT (mode);
30194 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
30195 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
30197 /* xa = xa + 0.5 */
30198 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
30199 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
30201 /* xa = (double)(int64_t)xa */
30202 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30203 expand_fix (xi, xa, 0);
30204 expand_float (xa, xi, 0);
30206 /* res = copysign (xa, operand1) */
30207 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
30209 emit_label (label);
30210 LABEL_NUSES (label) = 1;
30212 emit_move_insn (operand0, res);
30216 /* Validate whether a SSE5 instruction is valid or not.
30217 OPERANDS is the array of operands.
30218 NUM is the number of operands.
30219 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
30220 NUM_MEMORY is the maximum number of memory operands to accept.
30221 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
30224 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
30225 bool uses_oc0, int num_memory, bool commutative)
30231 /* Count the number of memory arguments */
30234 for (i = 0; i < num; i++)
30236 enum machine_mode mode = GET_MODE (operands[i]);
30237 if (register_operand (operands[i], mode))
30240 else if (memory_operand (operands[i], mode))
30242 mem_mask |= (1 << i);
30248 rtx pattern = PATTERN (insn);
30250 /* allow 0 for pcmov */
30251 if (GET_CODE (pattern) != SET
30252 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
30254 || operands[i] != CONST0_RTX (mode))
30259 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
30260 a memory operation. */
30261 if (num_memory < 0)
30263 num_memory = -num_memory;
30264 if ((mem_mask & (1 << (num-1))) != 0)
30266 mem_mask &= ~(1 << (num-1));
30271 /* If there were no memory operations, allow the insn */
30275 /* Do not allow the destination register to be a memory operand. */
30276 else if (mem_mask & (1 << 0))
30279 /* If there are too many memory operations, disallow the instruction. While
30280 the hardware only allows 1 memory reference, before register allocation
30281 for some insns, we allow two memory operations sometimes in order to allow
30282 code like the following to be optimized:
30284 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
30286 or similar cases that are vectorized into using the fmaddss
30288 else if (mem_count > num_memory)
30291 /* Don't allow more than one memory operation if not optimizing. */
30292 else if (mem_count > 1 && !optimize)
30295 else if (num == 4 && mem_count == 1)
30297 /* formats (destination is the first argument), example fmaddss:
30298 xmm1, xmm1, xmm2, xmm3/mem
30299 xmm1, xmm1, xmm2/mem, xmm3
30300 xmm1, xmm2, xmm3/mem, xmm1
30301 xmm1, xmm2/mem, xmm3, xmm1 */
30303 return ((mem_mask == (1 << 1))
30304 || (mem_mask == (1 << 2))
30305 || (mem_mask == (1 << 3)));
30307 /* format, example pmacsdd:
30308 xmm1, xmm2, xmm3/mem, xmm1 */
30310 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
30312 return (mem_mask == (1 << 2));
30315 else if (num == 4 && num_memory == 2)
30317 /* If there are two memory operations, we can load one of the memory ops
30318 into the destination register. This is for optimizing the
30319 multiply/add ops, which the combiner has optimized both the multiply
30320 and the add insns to have a memory operation. We have to be careful
30321 that the destination doesn't overlap with the inputs. */
30322 rtx op0 = operands[0];
30324 if (reg_mentioned_p (op0, operands[1])
30325 || reg_mentioned_p (op0, operands[2])
30326 || reg_mentioned_p (op0, operands[3]))
30329 /* formats (destination is the first argument), example fmaddss:
30330 xmm1, xmm1, xmm2, xmm3/mem
30331 xmm1, xmm1, xmm2/mem, xmm3
30332 xmm1, xmm2, xmm3/mem, xmm1
30333 xmm1, xmm2/mem, xmm3, xmm1
30335 For the oc0 case, we will load either operands[1] or operands[3] into
30336 operands[0], so any combination of 2 memory operands is ok. */
30340 /* format, example pmacsdd:
30341 xmm1, xmm2, xmm3/mem, xmm1
30343 For the integer multiply/add instructions be more restrictive and
30344 require operands[2] and operands[3] to be the memory operands. */
30346 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
30348 return (mem_mask == ((1 << 2) | (1 << 3)));
30351 else if (num == 3 && num_memory == 1)
30353 /* formats, example protb:
30354 xmm1, xmm2, xmm3/mem
30355 xmm1, xmm2/mem, xmm3 */
30357 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
30359 /* format, example comeq:
30360 xmm1, xmm2, xmm3/mem */
30362 return (mem_mask == (1 << 2));
30366 gcc_unreachable ();
30372 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
30373 hardware will allow by using the destination register to load one of the
30374 memory operations. Presently this is used by the multiply/add routines to
30375 allow 2 memory references. */
30378 ix86_expand_sse5_multiple_memory (rtx operands[],
30380 enum machine_mode mode)
30382 rtx op0 = operands[0];
30384 || memory_operand (op0, mode)
30385 || reg_mentioned_p (op0, operands[1])
30386 || reg_mentioned_p (op0, operands[2])
30387 || reg_mentioned_p (op0, operands[3]))
30388 gcc_unreachable ();
30390 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
30391 the destination register. */
30392 if (memory_operand (operands[1], mode))
30394 emit_move_insn (op0, operands[1]);
30397 else if (memory_operand (operands[3], mode))
30399 emit_move_insn (op0, operands[3]);
30403 gcc_unreachable ();
30409 /* Table of valid machine attributes. */
30410 static const struct attribute_spec ix86_attribute_table[] =
30412 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
30413 /* Stdcall attribute says callee is responsible for popping arguments
30414 if they are not variable. */
30415 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30416 /* Fastcall attribute says callee is responsible for popping arguments
30417 if they are not variable. */
30418 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30419 /* Cdecl attribute says the callee is a normal C declaration */
30420 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30421 /* Regparm attribute specifies how many integer arguments are to be
30422 passed in registers. */
30423 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
30424 /* Sseregparm attribute says we are using x86_64 calling conventions
30425 for FP arguments. */
30426 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30427 /* force_align_arg_pointer says this function realigns the stack at entry. */
30428 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
30429 false, true, true, ix86_handle_cconv_attribute },
30430 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30431 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
30432 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
30433 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
30435 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30436 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30437 #ifdef SUBTARGET_ATTRIBUTE_TABLE
30438 SUBTARGET_ATTRIBUTE_TABLE,
30440 /* ms_abi and sysv_abi calling convention function attributes. */
30441 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30442 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30444 { NULL, 0, 0, false, false, false, NULL }
30447 /* Implement targetm.vectorize.builtin_vectorization_cost. */
30449 x86_builtin_vectorization_cost (bool runtime_test)
30451 /* If the branch of the runtime test is taken - i.e. - the vectorized
30452 version is skipped - this incurs a misprediction cost (because the
30453 vectorized version is expected to be the fall-through). So we subtract
30454 the latency of a mispredicted branch from the costs that are incured
30455 when the vectorized version is executed.
30457 TODO: The values in individual target tables have to be tuned or new
30458 fields may be needed. For eg. on K8, the default branch path is the
30459 not-taken path. If the taken path is predicted correctly, the minimum
30460 penalty of going down the taken-path is 1 cycle. If the taken-path is
30461 not predicted correctly, then the minimum penalty is 10 cycles. */
30465 return (-(ix86_cost->cond_taken_branch_cost));
30471 /* This function returns the calling abi specific va_list type node.
30472 It returns the FNDECL specific va_list type. */
30475 ix86_fn_abi_va_list (tree fndecl)
30478 return va_list_type_node;
30479 gcc_assert (fndecl != NULL_TREE);
30481 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
30482 return ms_va_list_type_node;
30484 return sysv_va_list_type_node;
30487 /* Returns the canonical va_list type specified by TYPE. If there
30488 is no valid TYPE provided, it return NULL_TREE. */
30491 ix86_canonical_va_list_type (tree type)
30495 /* Resolve references and pointers to va_list type. */
30496 if (INDIRECT_REF_P (type))
30497 type = TREE_TYPE (type);
30498 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
30499 type = TREE_TYPE (type);
30503 wtype = va_list_type_node;
30504 gcc_assert (wtype != NULL_TREE);
30506 if (TREE_CODE (wtype) == ARRAY_TYPE)
30508 /* If va_list is an array type, the argument may have decayed
30509 to a pointer type, e.g. by being passed to another function.
30510 In that case, unwrap both types so that we can compare the
30511 underlying records. */
30512 if (TREE_CODE (htype) == ARRAY_TYPE
30513 || POINTER_TYPE_P (htype))
30515 wtype = TREE_TYPE (wtype);
30516 htype = TREE_TYPE (htype);
30519 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30520 return va_list_type_node;
30521 wtype = sysv_va_list_type_node;
30522 gcc_assert (wtype != NULL_TREE);
30524 if (TREE_CODE (wtype) == ARRAY_TYPE)
30526 /* If va_list is an array type, the argument may have decayed
30527 to a pointer type, e.g. by being passed to another function.
30528 In that case, unwrap both types so that we can compare the
30529 underlying records. */
30530 if (TREE_CODE (htype) == ARRAY_TYPE
30531 || POINTER_TYPE_P (htype))
30533 wtype = TREE_TYPE (wtype);
30534 htype = TREE_TYPE (htype);
30537 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30538 return sysv_va_list_type_node;
30539 wtype = ms_va_list_type_node;
30540 gcc_assert (wtype != NULL_TREE);
30542 if (TREE_CODE (wtype) == ARRAY_TYPE)
30544 /* If va_list is an array type, the argument may have decayed
30545 to a pointer type, e.g. by being passed to another function.
30546 In that case, unwrap both types so that we can compare the
30547 underlying records. */
30548 if (TREE_CODE (htype) == ARRAY_TYPE
30549 || POINTER_TYPE_P (htype))
30551 wtype = TREE_TYPE (wtype);
30552 htype = TREE_TYPE (htype);
30555 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30556 return ms_va_list_type_node;
30559 return std_canonical_va_list_type (type);
30562 /* Iterate through the target-specific builtin types for va_list.
30563 IDX denotes the iterator, *PTREE is set to the result type of
30564 the va_list builtin, and *PNAME to its internal type.
30565 Returns zero if there is no element for this index, otherwise
30566 IDX should be increased upon the next call.
30567 Note, do not iterate a base builtin's name like __builtin_va_list.
30568 Used from c_common_nodes_and_builtins. */
30571 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
30577 *ptree = ms_va_list_type_node;
30578 *pname = "__builtin_ms_va_list";
30581 *ptree = sysv_va_list_type_node;
30582 *pname = "__builtin_sysv_va_list";
30590 /* Initialize the GCC target structure. */
30591 #undef TARGET_RETURN_IN_MEMORY
30592 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30594 #undef TARGET_LEGITIMIZE_ADDRESS
30595 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30597 #undef TARGET_ATTRIBUTE_TABLE
30598 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30599 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30600 # undef TARGET_MERGE_DECL_ATTRIBUTES
30601 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30604 #undef TARGET_COMP_TYPE_ATTRIBUTES
30605 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30607 #undef TARGET_INIT_BUILTINS
30608 #define TARGET_INIT_BUILTINS ix86_init_builtins
30609 #undef TARGET_EXPAND_BUILTIN
30610 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30612 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30613 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30614 ix86_builtin_vectorized_function
30616 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30617 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30619 #undef TARGET_BUILTIN_RECIPROCAL
30620 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30622 #undef TARGET_ASM_FUNCTION_EPILOGUE
30623 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30625 #undef TARGET_ENCODE_SECTION_INFO
30626 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30627 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30629 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30632 #undef TARGET_ASM_OPEN_PAREN
30633 #define TARGET_ASM_OPEN_PAREN ""
30634 #undef TARGET_ASM_CLOSE_PAREN
30635 #define TARGET_ASM_CLOSE_PAREN ""
30637 #undef TARGET_ASM_ALIGNED_HI_OP
30638 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30639 #undef TARGET_ASM_ALIGNED_SI_OP
30640 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30642 #undef TARGET_ASM_ALIGNED_DI_OP
30643 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30646 #undef TARGET_ASM_UNALIGNED_HI_OP
30647 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30648 #undef TARGET_ASM_UNALIGNED_SI_OP
30649 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30650 #undef TARGET_ASM_UNALIGNED_DI_OP
30651 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30653 #undef TARGET_SCHED_ADJUST_COST
30654 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30655 #undef TARGET_SCHED_ISSUE_RATE
30656 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30657 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30658 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30659 ia32_multipass_dfa_lookahead
30661 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30662 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30665 #undef TARGET_HAVE_TLS
30666 #define TARGET_HAVE_TLS true
30668 #undef TARGET_CANNOT_FORCE_CONST_MEM
30669 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30670 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30671 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30673 #undef TARGET_DELEGITIMIZE_ADDRESS
30674 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30676 #undef TARGET_MS_BITFIELD_LAYOUT_P
30677 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30680 #undef TARGET_BINDS_LOCAL_P
30681 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30683 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30684 #undef TARGET_BINDS_LOCAL_P
30685 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30688 #undef TARGET_ASM_OUTPUT_MI_THUNK
30689 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30690 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30691 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30693 #undef TARGET_ASM_FILE_START
30694 #define TARGET_ASM_FILE_START x86_file_start
30696 #undef TARGET_DEFAULT_TARGET_FLAGS
30697 #define TARGET_DEFAULT_TARGET_FLAGS \
30699 | TARGET_SUBTARGET_DEFAULT \
30700 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
30702 #undef TARGET_HANDLE_OPTION
30703 #define TARGET_HANDLE_OPTION ix86_handle_option
30705 #undef TARGET_RTX_COSTS
30706 #define TARGET_RTX_COSTS ix86_rtx_costs
30707 #undef TARGET_ADDRESS_COST
30708 #define TARGET_ADDRESS_COST ix86_address_cost
30710 #undef TARGET_FIXED_CONDITION_CODE_REGS
30711 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30712 #undef TARGET_CC_MODES_COMPATIBLE
30713 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30715 #undef TARGET_MACHINE_DEPENDENT_REORG
30716 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30718 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30719 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30721 #undef TARGET_BUILD_BUILTIN_VA_LIST
30722 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30724 #undef TARGET_FN_ABI_VA_LIST
30725 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30727 #undef TARGET_CANONICAL_VA_LIST_TYPE
30728 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30730 #undef TARGET_EXPAND_BUILTIN_VA_START
30731 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30733 #undef TARGET_MD_ASM_CLOBBERS
30734 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30736 #undef TARGET_PROMOTE_PROTOTYPES
30737 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30738 #undef TARGET_STRUCT_VALUE_RTX
30739 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30740 #undef TARGET_SETUP_INCOMING_VARARGS
30741 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30742 #undef TARGET_MUST_PASS_IN_STACK
30743 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30744 #undef TARGET_PASS_BY_REFERENCE
30745 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30746 #undef TARGET_INTERNAL_ARG_POINTER
30747 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30748 #undef TARGET_UPDATE_STACK_BOUNDARY
30749 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30750 #undef TARGET_GET_DRAP_RTX
30751 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30752 #undef TARGET_STRICT_ARGUMENT_NAMING
30753 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30755 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30756 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30758 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30759 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30761 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30762 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30764 #undef TARGET_C_MODE_FOR_SUFFIX
30765 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30768 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30769 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30772 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30773 #undef TARGET_INSERT_ATTRIBUTES
30774 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30777 #undef TARGET_MANGLE_TYPE
30778 #define TARGET_MANGLE_TYPE ix86_mangle_type
30780 #undef TARGET_STACK_PROTECT_FAIL
30781 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30783 #undef TARGET_FUNCTION_VALUE
30784 #define TARGET_FUNCTION_VALUE ix86_function_value
30786 #undef TARGET_SECONDARY_RELOAD
30787 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30789 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30790 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
30792 #undef TARGET_SET_CURRENT_FUNCTION
30793 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30795 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30796 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30798 #undef TARGET_OPTION_SAVE
30799 #define TARGET_OPTION_SAVE ix86_function_specific_save
30801 #undef TARGET_OPTION_RESTORE
30802 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30804 #undef TARGET_OPTION_PRINT
30805 #define TARGET_OPTION_PRINT ix86_function_specific_print
30807 #undef TARGET_OPTION_CAN_INLINE_P
30808 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
30810 #undef TARGET_EXPAND_TO_RTL_HOOK
30811 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30813 #undef TARGET_LEGITIMATE_ADDRESS_P
30814 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30816 struct gcc_target targetm = TARGET_INITIALIZER;
30818 #include "gt-i386.h"
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