1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 92, 94-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
41 #ifdef EXTRA_CONSTRAINT
42 /* If EXTRA_CONSTRAINT is defined, then the 'S'
43 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
44 asm statements that need 'S' for class SIREG will break. */
45 error EXTRA_CONSTRAINT conflicts with S constraint letter
46 /* The previous line used to be #error, but some compilers barf
47 even if the conditional was untrue. */
50 #ifndef CHECK_STACK_LIMIT
51 #define CHECK_STACK_LIMIT -1
54 /* Type of an operand for ix86_{binary,unary}_operator_ok */
62 /* Processor costs (relative to an add) */
63 struct processor_costs i386_cost = { /* 386 specific costs */
64 1, /* cost of an add instruction */
65 1, /* cost of a lea instruction */
66 3, /* variable shift costs */
67 2, /* constant shift costs */
68 6, /* cost of starting a multiply */
69 1, /* cost of multiply per each bit set */
70 23 /* cost of a divide/mod */
73 struct processor_costs i486_cost = { /* 486 specific costs */
74 1, /* cost of an add instruction */
75 1, /* cost of a lea instruction */
76 3, /* variable shift costs */
77 2, /* constant shift costs */
78 12, /* cost of starting a multiply */
79 1, /* cost of multiply per each bit set */
80 40 /* cost of a divide/mod */
83 struct processor_costs pentium_cost = {
84 1, /* cost of an add instruction */
85 1, /* cost of a lea instruction */
86 4, /* variable shift costs */
87 1, /* constant shift costs */
88 11, /* cost of starting a multiply */
89 0, /* cost of multiply per each bit set */
90 25 /* cost of a divide/mod */
93 struct processor_costs pentiumpro_cost = {
94 1, /* cost of an add instruction */
95 1, /* cost of a lea instruction */
96 3, /* variable shift costs */
97 1, /* constant shift costs */
98 4, /* cost of starting a multiply */
99 0, /* cost of multiply per each bit set */
100 17 /* cost of a divide/mod */
103 struct processor_costs k6_cost = {
104 1, /* cost of an add instruction */
105 1, /* cost of a lea instruction */
106 1, /* variable shift costs */
107 1, /* constant shift costs */
108 2, /* cost of starting a multiply */
109 0, /* cost of multiply per each bit set */
110 18 /* cost of a divide/mod */
113 struct processor_costs *ix86_cost = &pentium_cost;
115 /* Processor feature/optimization bitmasks. */
116 #define m_386 (1<<PROCESSOR_I386)
117 #define m_486 (1<<PROCESSOR_I486)
118 #define m_PENT (1<<PROCESSOR_PENTIUM)
119 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
120 #define m_K6 (1<<PROCESSOR_K6)
122 const int x86_use_leave = m_386 | m_K6;
123 const int x86_push_memory = m_386 | m_K6;
124 const int x86_zero_extend_with_and = m_486 | m_PENT;
125 const int x86_movx = m_386 | m_PPRO | m_K6;
126 const int x86_double_with_add = ~m_386;
127 const int x86_use_bit_test = m_386;
128 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO;
129 const int x86_use_q_reg = m_PENT | m_PPRO | m_K6;
130 const int x86_use_any_reg = m_486;
131 const int x86_cmove = m_PPRO;
132 const int x86_deep_branch = m_PPRO| m_K6;
134 #define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx))
136 extern FILE *asm_out_file;
137 extern char *strcat ();
139 static void ix86_epilogue PROTO((int));
140 static void ix86_prologue PROTO((int));
142 char *singlemove_string ();
143 char *output_move_const_single ();
144 char *output_fp_cc0_set ();
146 char *hi_reg_name[] = HI_REGISTER_NAMES;
147 char *qi_reg_name[] = QI_REGISTER_NAMES;
148 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
150 /* Array of the smallest class containing reg number REGNO, indexed by
151 REGNO. Used by REGNO_REG_CLASS in i386.h. */
153 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
156 AREG, DREG, CREG, BREG,
158 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
160 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
161 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
166 /* Test and compare insns in i386.md store the information needed to
167 generate branch and scc insns here. */
169 struct rtx_def *i386_compare_op0 = NULL_RTX;
170 struct rtx_def *i386_compare_op1 = NULL_RTX;
171 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
173 /* which cpu are we scheduling for */
174 enum processor_type ix86_cpu;
176 /* which instruction set architecture to use. */
179 /* Strings to hold which cpu and instruction set architecture to use. */
180 char *ix86_cpu_string; /* for -mcpu=<xxx> */
181 char *ix86_arch_string; /* for -march=<xxx> */
183 /* Register allocation order */
184 char *i386_reg_alloc_order;
185 static char regs_allocated[FIRST_PSEUDO_REGISTER];
187 /* # of registers to use to pass arguments. */
188 char *i386_regparm_string;
190 /* i386_regparm_string as a number */
193 /* Alignment to use for loops and jumps: */
195 /* Power of two alignment for loops. */
196 char *i386_align_loops_string;
198 /* Power of two alignment for non-loop jumps. */
199 char *i386_align_jumps_string;
201 /* Values 1-5: see jump.c */
202 int i386_branch_cost;
203 char *i386_branch_cost_string;
205 /* Power of two alignment for functions. */
206 int i386_align_funcs;
207 char *i386_align_funcs_string;
209 /* Power of two alignment for loops. */
210 int i386_align_loops;
212 /* Power of two alignment for non-loop jumps. */
213 int i386_align_jumps;
215 /* Sometimes certain combinations of command options do not make
216 sense on a particular target machine. You can define a macro
217 `OVERRIDE_OPTIONS' to take account of this. This macro, if
218 defined, is executed once just after all the command options have
221 Don't use this macro to turn on various extra optimizations for
222 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
232 char *name; /* Canonical processor name. */
233 enum processor_type processor; /* Processor type enum value. */
234 struct processor_costs *cost; /* Processor costs */
235 int target_enable; /* Target flags to enable. */
236 int target_disable; /* Target flags to disable. */
237 } processor_target_table[]
238 = {{PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0},
239 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0},
240 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
241 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
242 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost,
244 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO,
245 &pentiumpro_cost, 0, 0},
246 {PROCESSOR_K6_STRING, PROCESSOR_K6, &k6_cost, 0, 0}};
248 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
250 #ifdef SUBTARGET_OVERRIDE_OPTIONS
251 SUBTARGET_OVERRIDE_OPTIONS;
254 /* Validate registers in register allocation order. */
255 if (i386_reg_alloc_order)
257 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
263 case 'a': regno = 0; break;
264 case 'd': regno = 1; break;
265 case 'c': regno = 2; break;
266 case 'b': regno = 3; break;
267 case 'S': regno = 4; break;
268 case 'D': regno = 5; break;
269 case 'B': regno = 6; break;
271 default: fatal ("Register '%c' is unknown", ch);
274 if (regs_allocated[regno])
275 fatal ("Register '%c' already specified in allocation order", ch);
277 regs_allocated[regno] = 1;
281 if (ix86_arch_string == 0)
283 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
284 if (ix86_cpu_string == 0)
285 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
288 for (i = 0; i < ptt_size; i++)
289 if (! strcmp (ix86_arch_string, processor_target_table[i].name))
291 ix86_arch = processor_target_table[i].processor;
292 if (ix86_cpu_string == 0)
293 ix86_cpu_string = processor_target_table[i].name;
299 error ("bad value (%s) for -march= switch", ix86_arch_string);
300 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
301 ix86_arch = PROCESSOR_DEFAULT;
304 if (ix86_cpu_string == 0)
305 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
307 for (j = 0; j < ptt_size; j++)
308 if (! strcmp (ix86_cpu_string, processor_target_table[j].name))
310 ix86_cpu = processor_target_table[j].processor;
311 ix86_cost = processor_target_table[j].cost;
312 if (i > j && (int) ix86_arch >= (int) PROCESSOR_K6)
313 error ("-mcpu=%s does not support -march=%s",
314 ix86_cpu_string, ix86_arch_string);
316 target_flags |= processor_target_table[j].target_enable;
317 target_flags &= ~processor_target_table[j].target_disable;
323 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
324 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
325 ix86_cpu = PROCESSOR_DEFAULT;
328 /* Validate -mregparm= value. */
329 if (i386_regparm_string)
331 i386_regparm = atoi (i386_regparm_string);
332 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
333 fatal ("-mregparm=%d is not between 0 and %d",
334 i386_regparm, REGPARM_MAX);
337 /* The 486 suffers more from non-aligned cache line fills, and the
338 larger code size results in a larger cache foot-print and more misses.
339 The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte
341 def_align = (TARGET_486) ? 4 : 2;
343 /* Validate -malign-loops= value, or provide default. */
344 if (i386_align_loops_string)
346 i386_align_loops = atoi (i386_align_loops_string);
347 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
348 fatal ("-malign-loops=%d is not between 0 and %d",
349 i386_align_loops, MAX_CODE_ALIGN);
352 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
353 i386_align_loops = 4;
355 i386_align_loops = 2;
358 /* Validate -malign-jumps= value, or provide default. */
359 if (i386_align_jumps_string)
361 i386_align_jumps = atoi (i386_align_jumps_string);
362 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
363 fatal ("-malign-jumps=%d is not between 0 and %d",
364 i386_align_jumps, MAX_CODE_ALIGN);
367 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
368 i386_align_jumps = 4;
370 i386_align_jumps = def_align;
373 /* Validate -malign-functions= value, or provide default. */
374 if (i386_align_funcs_string)
376 i386_align_funcs = atoi (i386_align_funcs_string);
377 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
378 fatal ("-malign-functions=%d is not between 0 and %d",
379 i386_align_funcs, MAX_CODE_ALIGN);
382 i386_align_funcs = def_align;
384 /* Validate -mbranch-cost= value, or provide default. */
385 if (i386_branch_cost_string)
387 i386_branch_cost = atoi (i386_branch_cost_string);
388 if (i386_branch_cost < 0 || i386_branch_cost > 5)
389 fatal ("-mbranch-cost=%d is not between 0 and 5",
393 i386_branch_cost = 1;
395 /* Keep nonleaf frame pointers. */
396 if (TARGET_OMIT_LEAF_FRAME_POINTER)
397 flag_omit_frame_pointer = 1;
400 /* A C statement (sans semicolon) to choose the order in which to
401 allocate hard registers for pseudo-registers local to a basic
404 Store the desired register order in the array `reg_alloc_order'.
405 Element 0 should be the register to allocate first; element 1, the
406 next register; and so on.
408 The macro body should not assume anything about the contents of
409 `reg_alloc_order' before execution of the macro.
411 On most machines, it is not necessary to define this macro. */
414 order_regs_for_local_alloc ()
418 /* User specified the register allocation order. */
420 if (i386_reg_alloc_order)
422 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
428 case 'a': regno = 0; break;
429 case 'd': regno = 1; break;
430 case 'c': regno = 2; break;
431 case 'b': regno = 3; break;
432 case 'S': regno = 4; break;
433 case 'D': regno = 5; break;
434 case 'B': regno = 6; break;
437 reg_alloc_order[order++] = regno;
440 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
442 if (! regs_allocated[i])
443 reg_alloc_order[order++] = i;
447 /* If user did not specify a register allocation order, use natural order. */
450 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
451 reg_alloc_order[i] = i;
456 optimization_options (level, size)
458 int size ATTRIBUTE_UNUSED;
460 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
461 make the problem with not enough registers even worse. */
462 #ifdef INSN_SCHEDULING
464 flag_schedule_insns = 0;
468 /* Sign-extend a 16-bit constant */
471 i386_sext16_if_const (op)
474 if (GET_CODE (op) == CONST_INT)
476 HOST_WIDE_INT val = INTVAL (op);
477 HOST_WIDE_INT sext_val;
479 sext_val = val | ~0xffff;
481 sext_val = val & 0xffff;
483 op = GEN_INT (sext_val);
488 /* Return nonzero if the rtx is aligned */
491 i386_aligned_reg_p (regno)
494 return (regno == STACK_POINTER_REGNUM
495 || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM));
502 /* Registers and immediate operands are always "aligned". */
503 if (GET_CODE (op) != MEM)
506 /* Don't even try to do any aligned optimizations with volatiles. */
507 if (MEM_VOLATILE_P (op))
510 /* Get address of memory operand. */
513 switch (GET_CODE (op))
520 /* Match "reg + offset" */
522 if (GET_CODE (XEXP (op, 1)) != CONST_INT)
524 if (INTVAL (XEXP (op, 1)) & 3)
528 if (GET_CODE (op) != REG)
531 /* ... fall through ... */
534 return i386_aligned_reg_p (REGNO (op));
543 /* Return nonzero if INSN looks like it won't compute useful cc bits
544 as a side effect. This information is only a hint. */
547 i386_cc_probably_useless_p (insn)
550 return ! next_cc0_user (insn);
553 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
554 attribute for DECL. The attributes in ATTRIBUTES have previously been
558 i386_valid_decl_attribute_p (decl, attributes, identifier, args)
559 tree decl ATTRIBUTE_UNUSED;
560 tree attributes ATTRIBUTE_UNUSED;
561 tree identifier ATTRIBUTE_UNUSED;
562 tree args ATTRIBUTE_UNUSED;
567 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
568 attribute for TYPE. The attributes in ATTRIBUTES have previously been
572 i386_valid_type_attribute_p (type, attributes, identifier, args)
574 tree attributes ATTRIBUTE_UNUSED;
578 if (TREE_CODE (type) != FUNCTION_TYPE
579 && TREE_CODE (type) != METHOD_TYPE
580 && TREE_CODE (type) != FIELD_DECL
581 && TREE_CODE (type) != TYPE_DECL)
584 /* Stdcall attribute says callee is responsible for popping arguments
585 if they are not variable. */
586 if (is_attribute_p ("stdcall", identifier))
587 return (args == NULL_TREE);
589 /* Cdecl attribute says the callee is a normal C declaration. */
590 if (is_attribute_p ("cdecl", identifier))
591 return (args == NULL_TREE);
593 /* Regparm attribute specifies how many integer arguments are to be
594 passed in registers. */
595 if (is_attribute_p ("regparm", identifier))
599 if (! args || TREE_CODE (args) != TREE_LIST
600 || TREE_CHAIN (args) != NULL_TREE
601 || TREE_VALUE (args) == NULL_TREE)
604 cst = TREE_VALUE (args);
605 if (TREE_CODE (cst) != INTEGER_CST)
608 if (TREE_INT_CST_HIGH (cst) != 0
609 || TREE_INT_CST_LOW (cst) < 0
610 || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
619 /* Return 0 if the attributes for two types are incompatible, 1 if they
620 are compatible, and 2 if they are nearly compatible (which causes a
621 warning to be generated). */
624 i386_comp_type_attributes (type1, type2)
628 /* Check for mismatch of non-default calling convention. */
629 char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
631 if (TREE_CODE (type1) != FUNCTION_TYPE)
634 /* Check for mismatched return types (cdecl vs stdcall). */
635 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
636 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
642 /* Value is the number of bytes of arguments automatically
643 popped when returning from a subroutine call.
644 FUNDECL is the declaration node of the function (as a tree),
645 FUNTYPE is the data type of the function (as a tree),
646 or for a library call it is an identifier node for the subroutine name.
647 SIZE is the number of bytes of arguments passed on the stack.
649 On the 80386, the RTD insn may be used to pop them if the number
650 of args is fixed, but if the number is variable then the caller
651 must pop them all. RTD can't be used for library calls now
652 because the library is compiled with the Unix compiler.
653 Use of RTD is a selectable option, since it is incompatible with
654 standard Unix calling sequences. If the option is not selected,
655 the caller must always pop the args.
657 The attribute stdcall is equivalent to RTD on a per module basis. */
660 i386_return_pops_args (fundecl, funtype, size)
665 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
667 /* Cdecl functions override -mrtd, and never pop the stack. */
668 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
670 /* Stdcall functions will pop the stack if not variable args. */
671 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
675 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
676 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
681 /* Lose any fake structure return argument. */
682 if (aggregate_value_p (TREE_TYPE (funtype)))
683 return GET_MODE_SIZE (Pmode);
689 /* Argument support functions. */
691 /* Initialize a variable CUM of type CUMULATIVE_ARGS
692 for a call to a function whose data type is FNTYPE.
693 For a library call, FNTYPE is 0. */
696 init_cumulative_args (cum, fntype, libname)
697 CUMULATIVE_ARGS *cum; /* Argument info to initialize */
698 tree fntype; /* tree ptr for function decl */
699 rtx libname; /* SYMBOL_REF of library name or 0 */
701 static CUMULATIVE_ARGS zero_cum;
702 tree param, next_param;
704 if (TARGET_DEBUG_ARG)
706 fprintf (stderr, "\ninit_cumulative_args (");
708 fprintf (stderr, "fntype code = %s, ret code = %s",
709 tree_code_name[(int) TREE_CODE (fntype)],
710 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
712 fprintf (stderr, "no fntype");
715 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
720 /* Set up the number of registers to use for passing arguments. */
721 cum->nregs = i386_regparm;
724 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
727 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
730 /* Determine if this function has variable arguments. This is
731 indicated by the last argument being 'void_type_mode' if there
732 are no variable arguments. If there are variable arguments, then
733 we won't pass anything in registers */
737 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
738 param != 0; param = next_param)
740 next_param = TREE_CHAIN (param);
741 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
746 if (TARGET_DEBUG_ARG)
747 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
752 /* Update the data in CUM to advance over an argument
753 of mode MODE and data type TYPE.
754 (TYPE is null for libcalls where that information may not be available.) */
757 function_arg_advance (cum, mode, type, named)
758 CUMULATIVE_ARGS *cum; /* current arg information */
759 enum machine_mode mode; /* current arg mode */
760 tree type; /* type of the argument or 0 if lib support */
761 int named; /* whether or not the argument was named */
764 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
765 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
767 if (TARGET_DEBUG_ARG)
769 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
770 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
785 /* Define where to put the arguments to a function.
786 Value is zero to push the argument on the stack,
787 or a hard register in which to store the argument.
789 MODE is the argument's machine mode.
790 TYPE is the data type of the argument (as a tree).
791 This is null for libcalls where that information may
793 CUM is a variable of type CUMULATIVE_ARGS which gives info about
794 the preceding args and about the function being called.
795 NAMED is nonzero if this argument is a named parameter
796 (otherwise it is an extra parameter matching an ellipsis). */
799 function_arg (cum, mode, type, named)
800 CUMULATIVE_ARGS *cum; /* current arg information */
801 enum machine_mode mode; /* current arg mode */
802 tree type; /* type of the argument or 0 if lib support */
803 int named; /* != 0 for normal args, == 0 for ... args */
807 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
808 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
812 /* For now, pass fp/complex values on the stack. */
821 if (words <= cum->nregs)
822 ret = gen_rtx_REG (mode, cum->regno);
826 if (TARGET_DEBUG_ARG)
829 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
830 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
833 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
835 fprintf (stderr, ", stack");
837 fprintf (stderr, " )\n");
843 /* For an arg passed partly in registers and partly in memory,
844 this is the number of registers used.
845 For args passed entirely in registers or entirely in memory, zero. */
848 function_arg_partial_nregs (cum, mode, type, named)
849 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; /* current arg information */
850 enum machine_mode mode ATTRIBUTE_UNUSED; /* current arg mode */
851 tree type ATTRIBUTE_UNUSED; /* type of the argument or 0 if lib support */
852 int named ATTRIBUTE_UNUSED; /* != 0 for normal args, == 0 for ... args */
857 /* Output an insn whose source is a 386 integer register. SRC is the
858 rtx for the register, and TEMPLATE is the op-code template. SRC may
859 be either SImode or DImode.
861 The template will be output with operands[0] as SRC, and operands[1]
862 as a pointer to the top of the 386 stack. So a call from floatsidf2
863 would look like this:
865 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
867 where %z0 corresponds to the caller's operands[1], and is used to
868 emit the proper size suffix.
870 ??? Extend this to handle HImode - a 387 can load and store HImode
874 output_op_from_reg (src, template)
879 int size = GET_MODE_SIZE (GET_MODE (src));
882 xops[1] = AT_SP (Pmode);
883 xops[2] = GEN_INT (size);
884 xops[3] = stack_pointer_rtx;
886 if (size > UNITS_PER_WORD)
890 if (size > 2 * UNITS_PER_WORD)
892 high = gen_rtx_REG (SImode, REGNO (src) + 2);
893 output_asm_insn (AS1 (push%L0,%0), &high);
896 high = gen_rtx_REG (SImode, REGNO (src) + 1);
897 output_asm_insn (AS1 (push%L0,%0), &high);
900 output_asm_insn (AS1 (push%L0,%0), &src);
901 output_asm_insn (template, xops);
902 output_asm_insn (AS2 (add%L3,%2,%3), xops);
905 /* Output an insn to pop an value from the 387 top-of-stack to 386
906 register DEST. The 387 register stack is popped if DIES is true. If
907 the mode of DEST is an integer mode, a `fist' integer store is done,
908 otherwise a `fst' float store is done. */
911 output_to_reg (dest, dies, scratch_mem)
917 int size = GET_MODE_SIZE (GET_MODE (dest));
920 xops[0] = AT_SP (Pmode);
922 xops[0] = scratch_mem;
924 xops[1] = stack_pointer_rtx;
925 xops[2] = GEN_INT (size);
929 output_asm_insn (AS2 (sub%L1,%2,%1), xops);
931 if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
934 output_asm_insn (AS1 (fistp%z3,%y0), xops);
935 else if (GET_MODE (xops[3]) == DImode && ! dies)
937 /* There is no DImode version of this without a stack pop, so
938 we must emulate it. It doesn't matter much what the second
939 instruction is, because the value being pushed on the FP stack
940 is not used except for the following stack popping store.
941 This case can only happen without optimization, so it doesn't
942 matter that it is inefficient. */
943 output_asm_insn (AS1 (fistp%z3,%0), xops);
944 output_asm_insn (AS1 (fild%z3,%0), xops);
947 output_asm_insn (AS1 (fist%z3,%y0), xops);
950 else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
953 output_asm_insn (AS1 (fstp%z3,%y0), xops);
956 if (GET_MODE (dest) == XFmode)
958 output_asm_insn (AS1 (fstp%z3,%y0), xops);
959 output_asm_insn (AS1 (fld%z3,%y0), xops);
962 output_asm_insn (AS1 (fst%z3,%y0), xops);
970 output_asm_insn (AS1 (pop%L0,%0), &dest);
972 output_asm_insn (AS2 (mov%L0,%0,%3), xops);
975 if (size > UNITS_PER_WORD)
977 dest = gen_rtx_REG (SImode, REGNO (dest) + 1);
979 output_asm_insn (AS1 (pop%L0,%0), &dest);
982 xops[0] = adj_offsettable_operand (xops[0], 4);
984 output_asm_insn (AS2 (mov%L0,%0,%3), xops);
987 if (size > 2 * UNITS_PER_WORD)
989 dest = gen_rtx_REG (SImode, REGNO (dest) + 1);
991 output_asm_insn (AS1 (pop%L0,%0), &dest);
994 xops[0] = adj_offsettable_operand (xops[0], 4);
995 output_asm_insn (AS2 (mov%L0,%0,%3), xops);
1002 singlemove_string (operands)
1006 if (GET_CODE (operands[0]) == MEM
1007 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
1009 if (XEXP (x, 0) != stack_pointer_rtx)
1011 return "push%L1 %1";
1013 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1014 return output_move_const_single (operands);
1015 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
1016 return AS2 (mov%L0,%1,%0);
1017 else if (CONSTANT_P (operands[1]))
1018 return AS2 (mov%L0,%1,%0);
1021 output_asm_insn ("push%L1 %1", operands);
1026 /* Return a REG that occurs in ADDR with coefficient 1.
1027 ADDR can be effectively incremented by incrementing REG. */
1030 find_addr_reg (addr)
1033 while (GET_CODE (addr) == PLUS)
1035 if (GET_CODE (XEXP (addr, 0)) == REG)
1036 addr = XEXP (addr, 0);
1037 else if (GET_CODE (XEXP (addr, 1)) == REG)
1038 addr = XEXP (addr, 1);
1039 else if (CONSTANT_P (XEXP (addr, 0)))
1040 addr = XEXP (addr, 1);
1041 else if (CONSTANT_P (XEXP (addr, 1)))
1042 addr = XEXP (addr, 0);
1047 if (GET_CODE (addr) == REG)
1052 /* Output an insn to add the constant N to the register X. */
1063 output_asm_insn (AS1 (dec%L0,%0), xops);
1065 output_asm_insn (AS1 (inc%L0,%0), xops);
1066 else if (n < 0 || n == 128)
1068 xops[1] = GEN_INT (-n);
1069 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
1073 xops[1] = GEN_INT (n);
1074 output_asm_insn (AS2 (add%L0,%1,%0), xops);
1078 /* Output assembler code to perform a doubleword move insn
1079 with operands OPERANDS. */
1082 output_move_double (operands)
1085 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
1089 rtx addreg0 = 0, addreg1 = 0;
1090 int dest_overlapped_low = 0;
1091 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
1096 /* First classify both operands. */
1098 if (REG_P (operands[0]))
1100 else if (offsettable_memref_p (operands[0]))
1102 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1104 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1106 else if (GET_CODE (operands[0]) == MEM)
1111 if (REG_P (operands[1]))
1113 else if (CONSTANT_P (operands[1]))
1115 else if (offsettable_memref_p (operands[1]))
1117 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1119 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1121 else if (GET_CODE (operands[1]) == MEM)
1126 /* Check for the cases that the operand constraints are not
1127 supposed to allow to happen. Abort if we get one,
1128 because generating code for these cases is painful. */
1130 if (optype0 == RNDOP || optype1 == RNDOP)
1133 /* If one operand is decrementing and one is incrementing
1134 decrement the former register explicitly
1135 and change that operand into ordinary indexing. */
1137 if (optype0 == PUSHOP && optype1 == POPOP)
1139 /* ??? Can this ever happen on i386? */
1140 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1141 asm_add (-size, operands[0]);
1142 if (GET_MODE (operands[1]) == XFmode)
1143 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1144 else if (GET_MODE (operands[0]) == DFmode)
1145 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1147 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1151 if (optype0 == POPOP && optype1 == PUSHOP)
1153 /* ??? Can this ever happen on i386? */
1154 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1155 asm_add (-size, operands[1]);
1156 if (GET_MODE (operands[1]) == XFmode)
1157 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1158 else if (GET_MODE (operands[1]) == DFmode)
1159 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1161 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1165 /* If an operand is an unoffsettable memory ref, find a register
1166 we can increment temporarily to make it refer to the second word. */
1168 if (optype0 == MEMOP)
1169 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1171 if (optype1 == MEMOP)
1172 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1174 /* Ok, we can do one word at a time.
1175 Normally we do the low-numbered word first,
1176 but if either operand is autodecrementing then we
1177 do the high-numbered word first.
1179 In either case, set up in LATEHALF the operands to use
1180 for the high-numbered word and in some cases alter the
1181 operands in OPERANDS to be suitable for the low-numbered word. */
1185 if (optype0 == REGOP)
1187 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1188 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1190 else if (optype0 == OFFSOP)
1192 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1193 latehalf[0] = adj_offsettable_operand (operands[0], 8);
1197 middlehalf[0] = operands[0];
1198 latehalf[0] = operands[0];
1201 if (optype1 == REGOP)
1203 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1204 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1206 else if (optype1 == OFFSOP)
1208 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1209 latehalf[1] = adj_offsettable_operand (operands[1], 8);
1211 else if (optype1 == CNSTOP)
1213 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1215 REAL_VALUE_TYPE r; long l[3];
1217 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1218 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1219 operands[1] = GEN_INT (l[0]);
1220 middlehalf[1] = GEN_INT (l[1]);
1221 latehalf[1] = GEN_INT (l[2]);
1223 else if (CONSTANT_P (operands[1]))
1224 /* No non-CONST_DOUBLE constant should ever appear here. */
1229 middlehalf[1] = operands[1];
1230 latehalf[1] = operands[1];
1236 /* Size is not 12. */
1238 if (optype0 == REGOP)
1239 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1240 else if (optype0 == OFFSOP)
1241 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1243 latehalf[0] = operands[0];
1245 if (optype1 == REGOP)
1246 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1247 else if (optype1 == OFFSOP)
1248 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1249 else if (optype1 == CNSTOP)
1250 split_double (operands[1], &operands[1], &latehalf[1]);
1252 latehalf[1] = operands[1];
1255 /* If insn is effectively movd N (sp),-(sp) then we will do the
1256 high word first. We should use the adjusted operand 1
1257 (which is N+4 (sp) or N+8 (sp))
1258 for the low word and middle word as well,
1259 to compensate for the first decrement of sp. */
1260 if (optype0 == PUSHOP
1261 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1262 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1263 middlehalf[1] = operands[1] = latehalf[1];
1265 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1266 if the upper part of reg N does not appear in the MEM, arrange to
1267 emit the move late-half first. Otherwise, compute the MEM address
1268 into the upper part of N and use that as a pointer to the memory
1270 if (optype0 == REGOP
1271 && (optype1 == OFFSOP || optype1 == MEMOP))
1273 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1274 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1276 /* If both halves of dest are used in the src memory address,
1277 compute the address into latehalf of dest. */
1279 xops[0] = latehalf[0];
1280 xops[1] = XEXP (operands[1], 0);
1281 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
1282 if (GET_MODE (operands[1]) == XFmode)
1284 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
1285 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1286 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1290 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
1291 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1296 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
1298 /* Check for two regs used by both source and dest. */
1299 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1300 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1303 /* JRV says this can't happen: */
1304 if (addreg0 || addreg1)
1307 /* Only the middle reg conflicts; simply put it last. */
1308 output_asm_insn (singlemove_string (operands), operands);
1309 output_asm_insn (singlemove_string (latehalf), latehalf);
1310 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1314 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
1315 /* If the low half of dest is mentioned in the source memory
1316 address, the arrange to emit the move late half first. */
1317 dest_overlapped_low = 1;
1320 /* If one or both operands autodecrementing,
1321 do the two words, high-numbered first. */
1323 /* Likewise, the first move would clobber the source of the second one,
1324 do them in the other order. This happens only for registers;
1325 such overlap can't happen in memory unless the user explicitly
1326 sets it up, and that is an undefined circumstance. */
1329 if (optype0 == PUSHOP || optype1 == PUSHOP
1330 || (optype0 == REGOP && optype1 == REGOP
1331 && REGNO (operands[0]) == REGNO (latehalf[1]))
1332 || dest_overlapped_low)
1335 if (optype0 == PUSHOP || optype1 == PUSHOP
1336 || (optype0 == REGOP && optype1 == REGOP
1337 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1338 || REGNO (operands[0]) == REGNO (latehalf[1])))
1339 || dest_overlapped_low)
1341 /* Make any unoffsettable addresses point at high-numbered word. */
1343 asm_add (size-4, addreg0);
1345 asm_add (size-4, addreg1);
1348 output_asm_insn (singlemove_string (latehalf), latehalf);
1350 /* Undo the adds we just did. */
1352 asm_add (-4, addreg0);
1354 asm_add (-4, addreg1);
1358 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1360 asm_add (-4, addreg0);
1362 asm_add (-4, addreg1);
1365 /* Do low-numbered word. */
1366 return singlemove_string (operands);
1369 /* Normal case: do the two words, low-numbered first. */
1371 output_asm_insn (singlemove_string (operands), operands);
1373 /* Do the middle one of the three words for long double */
1377 asm_add (4, addreg0);
1379 asm_add (4, addreg1);
1381 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1384 /* Make any unoffsettable addresses point at high-numbered word. */
1386 asm_add (4, addreg0);
1388 asm_add (4, addreg1);
1391 output_asm_insn (singlemove_string (latehalf), latehalf);
1393 /* Undo the adds we just did. */
1395 asm_add (4-size, addreg0);
1397 asm_add (4-size, addreg1);
1402 #define MAX_TMPS 2 /* max temporary registers used */
1404 /* Output the appropriate code to move push memory on the stack */
1407 output_move_pushmem (operands, insn, length, tmp_start, n_operands)
1419 } tmp_info[MAX_TMPS];
1421 rtx src = operands[1];
1424 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
1425 int stack_offset = 0;
1429 if (! offsettable_memref_p (src))
1430 fatal_insn ("Source is not offsettable", insn);
1432 if ((length & 3) != 0)
1433 fatal_insn ("Pushing non-word aligned size", insn);
1435 /* Figure out which temporary registers we have available */
1436 for (i = tmp_start; i < n_operands; i++)
1438 if (GET_CODE (operands[i]) == REG)
1440 if (reg_overlap_mentioned_p (operands[i], src))
1443 tmp_info[ max_tmps++ ].xops[1] = operands[i];
1444 if (max_tmps == MAX_TMPS)
1450 for (offset = length - 4; offset >= 0; offset -= 4)
1452 xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1453 output_asm_insn (AS1(push%L0,%0), xops);
1459 for (offset = length - 4; offset >= 0; )
1461 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
1463 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1);
1464 tmp_info[num_tmps].push = AS1(push%L0,%1);
1465 tmp_info[num_tmps].xops[0]
1466 = adj_offsettable_operand (src, offset + stack_offset);
1470 for (i = 0; i < num_tmps; i++)
1471 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1473 for (i = 0; i < num_tmps; i++)
1474 output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
1477 stack_offset += 4*num_tmps;
1483 /* Output the appropriate code to move data between two memory locations */
1486 output_move_memory (operands, insn, length, tmp_start, n_operands)
1498 } tmp_info[MAX_TMPS];
1500 rtx dest = operands[0];
1501 rtx src = operands[1];
1502 rtx qi_tmp = NULL_RTX;
1508 if (GET_CODE (dest) == MEM
1509 && GET_CODE (XEXP (dest, 0)) == PRE_INC
1510 && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)
1511 return output_move_pushmem (operands, insn, length, tmp_start, n_operands);
1513 if (! offsettable_memref_p (src))
1514 fatal_insn ("Source is not offsettable", insn);
1516 if (! offsettable_memref_p (dest))
1517 fatal_insn ("Destination is not offsettable", insn);
1519 /* Figure out which temporary registers we have available */
1520 for (i = tmp_start; i < n_operands; i++)
1522 if (GET_CODE (operands[i]) == REG)
1524 if ((length & 1) != 0 && qi_tmp == 0 && QI_REG_P (operands[i]))
1525 qi_tmp = operands[i];
1527 if (reg_overlap_mentioned_p (operands[i], dest))
1528 fatal_insn ("Temporary register overlaps the destination", insn);
1530 if (reg_overlap_mentioned_p (operands[i], src))
1531 fatal_insn ("Temporary register overlaps the source", insn);
1533 tmp_info[max_tmps++].xops[2] = operands[i];
1534 if (max_tmps == MAX_TMPS)
1540 fatal_insn ("No scratch registers were found to do memory->memory moves",
1543 if ((length & 1) != 0)
1546 fatal_insn ("No byte register found when moving odd # of bytes.",
1552 for (num_tmps = 0; num_tmps < max_tmps; num_tmps++)
1556 tmp_info[num_tmps].load = AS2(mov%L0,%1,%2);
1557 tmp_info[num_tmps].store = AS2(mov%L0,%2,%0);
1558 tmp_info[num_tmps].xops[0]
1559 = adj_offsettable_operand (dest, offset);
1560 tmp_info[num_tmps].xops[1]
1561 = adj_offsettable_operand (src, offset);
1567 else if (length >= 2)
1569 tmp_info[num_tmps].load = AS2(mov%W0,%1,%2);
1570 tmp_info[num_tmps].store = AS2(mov%W0,%2,%0);
1571 tmp_info[num_tmps].xops[0]
1572 = adj_offsettable_operand (dest, offset);
1573 tmp_info[num_tmps].xops[1]
1574 = adj_offsettable_operand (src, offset);
1583 for (i = 0; i < num_tmps; i++)
1584 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1586 for (i = 0; i < num_tmps; i++)
1587 output_asm_insn (tmp_info[i].store, tmp_info[i].xops);
1592 xops[0] = adj_offsettable_operand (dest, offset);
1593 xops[1] = adj_offsettable_operand (src, offset);
1595 output_asm_insn (AS2(mov%B0,%1,%2), xops);
1596 output_asm_insn (AS2(mov%B0,%2,%0), xops);
1603 standard_80387_constant_p (x)
1606 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1611 if (setjmp (handler))
1614 set_float_handler (handler);
1615 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1616 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d);
1617 is1 = REAL_VALUES_EQUAL (d, dconst1);
1618 set_float_handler (NULL_PTR);
1626 /* Note that on the 80387, other constants, such as pi,
1627 are much slower to load as standard constants
1628 than to load from doubles in memory! */
1629 /* ??? Not true on K6: all constants are equal cost. */
1636 output_move_const_single (operands)
1639 if (FP_REG_P (operands[0]))
1641 int conval = standard_80387_constant_p (operands[1]);
1650 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1652 REAL_VALUE_TYPE r; long l;
1654 if (GET_MODE (operands[1]) == XFmode)
1657 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1658 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1659 operands[1] = GEN_INT (l);
1662 return singlemove_string (operands);
1665 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1666 reference and a constant. */
1669 symbolic_operand (op, mode)
1671 enum machine_mode mode ATTRIBUTE_UNUSED;
1673 switch (GET_CODE (op))
1681 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1682 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1683 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1690 /* Test for a valid operand for a call instruction.
1691 Don't allow the arg pointer register or virtual regs
1692 since they may change into reg + const, which the patterns
1693 can't handle yet. */
1696 call_insn_operand (op, mode)
1698 enum machine_mode mode ATTRIBUTE_UNUSED;
1700 if (GET_CODE (op) == MEM
1701 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
1702 /* This makes a difference for PIC. */
1703 && general_operand (XEXP (op, 0), Pmode))
1704 || (GET_CODE (XEXP (op, 0)) == REG
1705 && XEXP (op, 0) != arg_pointer_rtx
1706 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1707 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1713 /* Like call_insn_operand but allow (mem (symbol_ref ...))
1717 expander_call_insn_operand (op, mode)
1719 enum machine_mode mode ATTRIBUTE_UNUSED;
1721 if (GET_CODE (op) == MEM
1722 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
1723 || (GET_CODE (XEXP (op, 0)) == REG
1724 && XEXP (op, 0) != arg_pointer_rtx
1725 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1726 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1732 /* Return 1 if OP is a comparison operator that can use the condition code
1733 generated by an arithmetic operation. */
1736 arithmetic_comparison_operator (op, mode)
1738 enum machine_mode mode;
1742 if (mode != VOIDmode && mode != GET_MODE (op))
1745 code = GET_CODE (op);
1746 if (GET_RTX_CLASS (code) != '<')
1749 return (code != GT && code != LE);
1753 ix86_logical_operator (op, mode)
1755 enum machine_mode mode ATTRIBUTE_UNUSED;
1757 return GET_CODE (op) == AND || GET_CODE (op) == IOR || GET_CODE (op) == XOR;
1761 /* Returns 1 if OP contains a symbol reference */
1764 symbolic_reference_mentioned_p (op)
1770 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1773 fmt = GET_RTX_FORMAT (GET_CODE (op));
1774 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1780 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1781 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1785 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1792 /* Attempt to expand a binary operator. Make the expansion closer to the
1793 actual machine, then just general_operand, which will allow 3 separate
1794 memory references (one output, two input) in a single insn. Return
1795 whether the insn fails, or succeeds. */
1798 ix86_expand_binary_operator (code, mode, operands)
1800 enum machine_mode mode;
1805 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
1806 if (GET_RTX_CLASS (code) == 'c'
1807 && (rtx_equal_p (operands[0], operands[2])
1808 || immediate_operand (operands[1], mode)))
1810 rtx temp = operands[1];
1811 operands[1] = operands[2];
1815 /* If optimizing, copy to regs to improve CSE */
1816 if (TARGET_PSEUDO && optimize
1817 && ((reload_in_progress | reload_completed) == 0))
1819 if (GET_CODE (operands[1]) == MEM
1820 && ! rtx_equal_p (operands[0], operands[1]))
1821 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1823 if (GET_CODE (operands[2]) == MEM)
1824 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1826 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1828 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1830 emit_move_insn (temp, operands[1]);
1836 if (!ix86_binary_operator_ok (code, mode, operands))
1838 /* If not optimizing, try to make a valid insn (optimize code
1839 previously did this above to improve chances of CSE) */
1841 if ((! TARGET_PSEUDO || !optimize)
1842 && ((reload_in_progress | reload_completed) == 0)
1843 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM))
1846 if (GET_CODE (operands[1]) == MEM
1847 && ! rtx_equal_p (operands[0], operands[1]))
1849 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1853 if (GET_CODE (operands[2]) == MEM)
1855 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1859 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1861 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1863 emit_move_insn (temp, operands[1]);
1868 if (modified && ! ix86_binary_operator_ok (code, mode, operands))
1878 /* Return TRUE or FALSE depending on whether the binary operator meets the
1879 appropriate constraints. */
1882 ix86_binary_operator_ok (code, mode, operands)
1884 enum machine_mode mode ATTRIBUTE_UNUSED;
1887 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
1888 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c');
1891 /* Attempt to expand a unary operator. Make the expansion closer to the
1892 actual machine, then just general_operand, which will allow 2 separate
1893 memory references (one output, one input) in a single insn. Return
1894 whether the insn fails, or succeeds. */
1897 ix86_expand_unary_operator (code, mode, operands)
1899 enum machine_mode mode;
1902 /* If optimizing, copy to regs to improve CSE */
1905 && ((reload_in_progress | reload_completed) == 0)
1906 && GET_CODE (operands[1]) == MEM)
1907 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1909 if (! ix86_unary_operator_ok (code, mode, operands))
1911 if ((! TARGET_PSEUDO || optimize == 0)
1912 && ((reload_in_progress | reload_completed) == 0)
1913 && GET_CODE (operands[1]) == MEM)
1915 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1916 if (! ix86_unary_operator_ok (code, mode, operands))
1926 /* Return TRUE or FALSE depending on whether the unary operator meets the
1927 appropriate constraints. */
1930 ix86_unary_operator_ok (code, mode, operands)
1931 enum rtx_code code ATTRIBUTE_UNUSED;
1932 enum machine_mode mode ATTRIBUTE_UNUSED;
1933 rtx operands[2] ATTRIBUTE_UNUSED;
1938 static rtx pic_label_rtx;
1939 static char pic_label_name [256];
1940 static int pic_label_no = 0;
1942 /* This function generates code for -fpic that loads %ebx with
1943 the return address of the caller and then returns. */
1946 asm_output_function_prefix (file, name)
1948 char *name ATTRIBUTE_UNUSED;
1951 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1952 || current_function_uses_const_pool);
1953 xops[0] = pic_offset_table_rtx;
1954 xops[1] = stack_pointer_rtx;
1956 /* Deep branch prediction favors having a return for every call. */
1957 if (pic_reg_used && TARGET_DEEP_BRANCH_PREDICTION)
1961 if (pic_label_rtx == 0)
1963 pic_label_rtx = gen_label_rtx ();
1964 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
1965 LABEL_NAME (pic_label_rtx) = pic_label_name;
1968 prologue_node = make_node (FUNCTION_DECL);
1969 DECL_RESULT (prologue_node) = 0;
1971 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
1972 internal (non-global) label that's being emitted, it didn't make
1973 sense to have .type information for local labels. This caused
1974 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
1975 me debug info for a label that you're declaring non-global?) this
1976 was changed to call ASM_OUTPUT_LABEL() instead. */
1979 ASM_OUTPUT_LABEL (file, pic_label_name);
1980 output_asm_insn ("movl (%1),%0", xops);
1981 output_asm_insn ("ret", xops);
1985 /* Generate the assembly code for function entry.
1986 FILE is an stdio stream to output the code to.
1987 SIZE is an int: how many units of temporary storage to allocate. */
1990 function_prologue (file, size)
1991 FILE *file ATTRIBUTE_UNUSED;
1992 int size ATTRIBUTE_UNUSED;
1994 if (TARGET_SCHEDULE_PROLOGUE)
2003 /* Expand the prologue into a bunch of separate insns. */
2006 ix86_expand_prologue ()
2008 if (! TARGET_SCHEDULE_PROLOGUE)
2015 load_pic_register (do_rtl)
2020 if (TARGET_DEEP_BRANCH_PREDICTION)
2022 xops[0] = pic_offset_table_rtx;
2023 if (pic_label_rtx == 0)
2025 pic_label_rtx = gen_label_rtx ();
2026 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
2027 LABEL_NAME (pic_label_rtx) = pic_label_name;
2030 xops[1] = gen_rtx_MEM (QImode,
2031 gen_rtx (SYMBOL_REF, Pmode,
2032 LABEL_NAME (pic_label_rtx)));
2036 emit_insn (gen_prologue_get_pc (xops[0], xops[1]));
2037 emit_insn (gen_prologue_set_got (xops[0],
2038 gen_rtx (SYMBOL_REF, Pmode,
2039 "$_GLOBAL_OFFSET_TABLE_"),
2044 output_asm_insn (AS1 (call,%X1), xops);
2045 output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_,%0", xops);
2052 xops[0] = pic_offset_table_rtx;
2053 xops[1] = gen_label_rtx ();
2057 /* We can't put a raw CODE_LABEL into the RTL, and we can't emit
2058 a new CODE_LABEL after reload, so we need a single pattern to
2059 emit the 3 necessary instructions. */
2060 emit_insn (gen_prologue_get_pc_and_set_got (xops[0]));
2064 output_asm_insn (AS1 (call,%P1), xops);
2065 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
2066 CODE_LABEL_NUMBER (xops[1]));
2067 output_asm_insn (AS1 (pop%L0,%0), xops);
2068 output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
2072 /* When -fpic, we must emit a scheduling barrier, so that the instruction
2073 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
2074 moved before any instruction which implicitly uses the got. */
2077 emit_insn (gen_blockage ());
2080 /* Compute the size of local storage taking into consideration the
2081 desired stack alignment which is to be maintained. Also determine
2082 the number of registers saved below the local storage. */
2085 ix86_compute_frame_size (size, nregs_on_stack)
2087 int *nregs_on_stack;
2093 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
2094 || current_function_uses_const_pool);
2095 HOST_WIDE_INT total_size;
2097 limit = frame_pointer_needed
2098 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
2102 for (regno = limit - 1; regno >= 0; regno--)
2103 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2104 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2108 total_size = size + (nregs * UNITS_PER_WORD);
2110 #ifdef PREFERRED_STACK_BOUNDARY
2113 int preferred_alignment = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT;
2116 if (frame_pointer_needed)
2117 offset += UNITS_PER_WORD;
2119 total_size += offset;
2121 padding = ((total_size + preferred_alignment - 1)
2122 & -preferred_alignment) - total_size;
2124 if (padding < (((offset + preferred_alignment - 1)
2125 & -preferred_alignment) - offset))
2126 padding += preferred_alignment;
2131 *nregs_on_stack = nregs;
2133 return size + padding;
2137 ix86_prologue (do_rtl)
2143 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
2144 || current_function_uses_const_pool);
2145 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), (int *)0);
2147 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
2149 xops[0] = stack_pointer_rtx;
2150 xops[1] = frame_pointer_rtx;
2151 xops[2] = GEN_INT (tsize);
2153 if (frame_pointer_needed)
2157 insn = emit_insn (gen_rtx (SET, VOIDmode,
2158 gen_rtx_MEM (SImode,
2159 gen_rtx (PRE_DEC, SImode,
2160 stack_pointer_rtx)),
2161 frame_pointer_rtx));
2163 RTX_FRAME_RELATED_P (insn) = 1;
2164 insn = emit_move_insn (xops[1], xops[0]);
2165 RTX_FRAME_RELATED_P (insn) = 1;
2170 output_asm_insn ("push%L1 %1", xops);
2171 #ifdef INCOMING_RETURN_ADDR_RTX
2172 if (dwarf2out_do_frame ())
2174 char *l = dwarf2out_cfi_label ();
2176 cfa_store_offset += 4;
2177 cfa_offset = cfa_store_offset;
2178 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
2179 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset);
2183 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
2184 #ifdef INCOMING_RETURN_ADDR_RTX
2185 if (dwarf2out_do_frame ())
2186 dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset);
2193 else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT)
2197 insn = emit_insn (gen_prologue_set_stack_ptr (xops[2]));
2198 RTX_FRAME_RELATED_P (insn) = 1;
2202 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
2203 #ifdef INCOMING_RETURN_ADDR_RTX
2204 if (dwarf2out_do_frame ())
2206 cfa_store_offset += tsize;
2207 if (! frame_pointer_needed)
2209 cfa_offset = cfa_store_offset;
2210 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
2218 xops[3] = gen_rtx_REG (SImode, 0);
2220 emit_move_insn (xops[3], xops[2]);
2222 output_asm_insn (AS2 (mov%L0,%2,%3), xops);
2224 xops[3] = gen_rtx_MEM (FUNCTION_MODE,
2225 gen_rtx (SYMBOL_REF, Pmode, "_alloca"));
2228 emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx));
2230 output_asm_insn (AS1 (call,%P3), xops);
2233 /* Note If use enter it is NOT reversed args.
2234 This one is not reversed from intel!!
2235 I think enter is slower. Also sdb doesn't like it.
2236 But if you want it the code is:
2238 xops[3] = const0_rtx;
2239 output_asm_insn ("enter %2,%3", xops);
2243 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2244 for (regno = limit - 1; regno >= 0; regno--)
2245 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2246 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2248 xops[0] = gen_rtx_REG (SImode, regno);
2251 insn = emit_insn (gen_rtx (SET, VOIDmode,
2252 gen_rtx_MEM (SImode,
2253 gen_rtx (PRE_DEC, SImode,
2254 stack_pointer_rtx)),
2257 RTX_FRAME_RELATED_P (insn) = 1;
2261 output_asm_insn ("push%L0 %0", xops);
2262 #ifdef INCOMING_RETURN_ADDR_RTX
2263 if (dwarf2out_do_frame ())
2265 char *l = dwarf2out_cfi_label ();
2267 cfa_store_offset += 4;
2268 if (! frame_pointer_needed)
2270 cfa_offset = cfa_store_offset;
2271 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
2274 dwarf2out_reg_save (l, regno, - cfa_store_offset);
2280 #ifdef SUBTARGET_PROLOGUE
2285 load_pic_register (do_rtl);
2287 /* If we are profiling, make sure no instructions are scheduled before
2288 the call to mcount. However, if -fpic, the above call will have
2290 if ((profile_flag || profile_block_flag)
2291 && ! pic_reg_used && do_rtl)
2292 emit_insn (gen_blockage ());
2295 /* Return 1 if it is appropriate to emit `ret' instructions in the
2296 body of a function. Do this only if the epilogue is simple, needing a
2297 couple of insns. Prior to reloading, we can't tell how many registers
2298 must be saved, so return 0 then. Return 0 if there is no frame
2299 marker to de-allocate.
2301 If NON_SAVING_SETJMP is defined and true, then it is not possible
2302 for the epilogue to be simple, so return 0. This is a special case
2303 since NON_SAVING_SETJMP will not cause regs_ever_live to change
2304 until final, but jump_optimize may need to know sooner if a
2308 ix86_can_use_return_insn_p ()
2312 int reglimit = (frame_pointer_needed
2313 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2314 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
2315 || current_function_uses_const_pool);
2317 #ifdef NON_SAVING_SETJMP
2318 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
2322 if (! reload_completed)
2325 for (regno = reglimit - 1; regno >= 0; regno--)
2326 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2327 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2330 return nregs == 0 || ! frame_pointer_needed;
2333 /* This function generates the assembly code for function exit.
2334 FILE is an stdio stream to output the code to.
2335 SIZE is an int: how many units of temporary storage to deallocate. */
2338 function_epilogue (file, size)
2339 FILE *file ATTRIBUTE_UNUSED;
2340 int size ATTRIBUTE_UNUSED;
2345 /* Restore function stack, frame, and registers. */
2348 ix86_expand_epilogue ()
2354 ix86_epilogue (do_rtl)
2361 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
2362 || current_function_uses_const_pool);
2363 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
2364 HOST_WIDE_INT offset;
2365 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), &nregs);
2367 /* sp is often unreliable so we may have to go off the frame pointer. */
2369 offset = -(tsize + nregs * UNITS_PER_WORD);
2371 xops[2] = stack_pointer_rtx;
2373 /* When -fpic, we must emit a scheduling barrier, so that the instruction
2374 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
2375 moved before any instruction which implicitly uses the got. This
2376 includes any instruction which uses a SYMBOL_REF or a LABEL_REF.
2378 Alternatively, this could be fixed by making the dependence on the
2379 PIC_OFFSET_TABLE_REGNUM explicit in the RTL. */
2381 if (flag_pic || profile_flag || profile_block_flag)
2382 emit_insn (gen_blockage ());
2384 /* If we're only restoring one register and sp is not valid then
2385 using a move instruction to restore the register since it's
2386 less work than reloading sp and popping the register. Otherwise,
2387 restore sp (if necessary) and pop the registers. */
2389 limit = frame_pointer_needed
2390 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
2392 if (nregs > 1 || sp_valid)
2396 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset);
2398 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0)));
2400 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
2403 for (regno = 0; regno < limit; regno++)
2404 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2405 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2407 xops[0] = gen_rtx_REG (SImode, regno);
2410 emit_insn (gen_pop (xops[0]));
2412 output_asm_insn ("pop%L0 %0", xops);
2417 for (regno = 0; regno < limit; regno++)
2418 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2419 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2421 xops[0] = gen_rtx_REG (SImode, regno);
2422 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
2425 emit_move_insn (xops[0], xops[1]);
2427 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
2432 if (frame_pointer_needed)
2434 /* If not an i386, mov & pop is faster than "leave". */
2436 if (TARGET_USE_LEAVE)
2439 emit_insn (gen_leave());
2441 output_asm_insn ("leave", xops);
2445 xops[0] = frame_pointer_rtx;
2446 xops[1] = stack_pointer_rtx;
2450 emit_insn (gen_epilogue_set_stack_ptr());
2451 emit_insn (gen_pop (xops[0]));
2455 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
2456 output_asm_insn ("pop%L0 %0", xops);
2463 /* Intel's docs say that for 4 or 8 bytes of stack frame one should
2464 use `pop' and not `add'. */
2465 int use_pop = tsize == 4;
2467 /* Use two pops only for the Pentium processors. */
2468 if (tsize == 8 && !TARGET_386 && !TARGET_486)
2470 rtx retval = current_function_return_rtx;
2472 xops[1] = gen_rtx_REG (SImode, 1); /* %edx */
2474 /* This case is a bit more complex. Since we cannot pop into
2475 %ecx twice we need a second register. But this is only
2476 available if the return value is not of DImode in which
2477 case the %edx register is not available. */
2478 use_pop = (retval == NULL
2479 || ! reg_overlap_mentioned_p (xops[1], retval));
2484 xops[0] = gen_rtx_REG (SImode, 2); /* %ecx */
2488 /* We have to prevent the two pops here from being scheduled.
2489 GCC otherwise would try in some situation to put other
2490 instructions in between them which has a bad effect. */
2491 emit_insn (gen_blockage ());
2492 emit_insn (gen_pop (xops[0]));
2494 emit_insn (gen_pop (xops[1]));
2498 output_asm_insn ("pop%L0 %0", xops);
2500 output_asm_insn ("pop%L1 %1", xops);
2505 /* If there is no frame pointer, we must still release the frame. */
2506 xops[0] = GEN_INT (tsize);
2509 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2510 gen_rtx (PLUS, SImode, xops[2], xops[0])));
2512 output_asm_insn (AS2 (add%L2,%0,%2), xops);
2516 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
2517 if (profile_block_flag == 2)
2519 FUNCTION_BLOCK_PROFILER_EXIT(file);
2523 if (current_function_pops_args && current_function_args_size)
2525 xops[1] = GEN_INT (current_function_pops_args);
2527 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
2528 asked to pop more, pop return address, do explicit add, and jump
2529 indirectly to the caller. */
2531 if (current_function_pops_args >= 32768)
2533 /* ??? Which register to use here? */
2534 xops[0] = gen_rtx_REG (SImode, 2);
2538 emit_insn (gen_pop (xops[0]));
2539 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2540 gen_rtx (PLUS, SImode, xops[1], xops[2])));
2541 emit_jump_insn (xops[0]);
2545 output_asm_insn ("pop%L0 %0", xops);
2546 output_asm_insn (AS2 (add%L2,%1,%2), xops);
2547 output_asm_insn ("jmp %*%0", xops);
2553 emit_jump_insn (gen_return_pop_internal (xops[1]));
2555 output_asm_insn ("ret %1", xops);
2561 emit_jump_insn (gen_return_internal ());
2563 output_asm_insn ("ret", xops);
2567 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2568 that is a valid memory address for an instruction.
2569 The MODE argument is the machine mode for the MEM expression
2570 that wants to use this address.
2572 On x86, legitimate addresses are:
2573 base movl (base),reg
2574 displacement movl disp,reg
2575 base + displacement movl disp(base),reg
2576 index + base movl (base,index),reg
2577 (index + base) + displacement movl disp(base,index),reg
2578 index*scale movl (,index,scale),reg
2579 index*scale + disp movl disp(,index,scale),reg
2580 index*scale + base movl (base,index,scale),reg
2581 (index*scale + base) + disp movl disp(base,index,scale),reg
2583 In each case, scale can be 1, 2, 4, 8. */
2585 /* This is exactly the same as print_operand_addr, except that
2586 it recognizes addresses instead of printing them.
2588 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2589 convert common non-canonical forms to canonical form so that they will
2592 #define ADDR_INVALID(msg,insn) \
2594 if (TARGET_DEBUG_ADDR) \
2596 fprintf (stderr, msg); \
2602 legitimate_pic_address_disp_p (disp)
2605 if (GET_CODE (disp) != CONST)
2607 disp = XEXP (disp, 0);
2609 if (GET_CODE (disp) == PLUS)
2611 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
2613 disp = XEXP (disp, 0);
2616 if (GET_CODE (disp) != UNSPEC
2617 || XVECLEN (disp, 0) != 1)
2620 /* Must be @GOT or @GOTOFF. */
2621 if (XINT (disp, 1) != 6
2622 && XINT (disp, 1) != 7)
2625 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2626 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
2633 legitimate_address_p (mode, addr, strict)
2634 enum machine_mode mode;
2638 rtx base = NULL_RTX;
2639 rtx indx = NULL_RTX;
2640 rtx scale = NULL_RTX;
2641 rtx disp = NULL_RTX;
2643 if (TARGET_DEBUG_ADDR)
2646 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2647 GET_MODE_NAME (mode), strict);
2652 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
2655 else if (GET_CODE (addr) == PLUS)
2657 rtx op0 = XEXP (addr, 0);
2658 rtx op1 = XEXP (addr, 1);
2659 enum rtx_code code0 = GET_CODE (op0);
2660 enum rtx_code code1 = GET_CODE (op1);
2662 if (code0 == REG || code0 == SUBREG)
2664 if (code1 == REG || code1 == SUBREG)
2666 indx = op0; /* index + base */
2672 base = op0; /* base + displacement */
2677 else if (code0 == MULT)
2679 indx = XEXP (op0, 0);
2680 scale = XEXP (op0, 1);
2682 if (code1 == REG || code1 == SUBREG)
2683 base = op1; /* index*scale + base */
2686 disp = op1; /* index*scale + disp */
2689 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
2691 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
2692 scale = XEXP (XEXP (op0, 0), 1);
2693 base = XEXP (op0, 1);
2697 else if (code0 == PLUS)
2699 indx = XEXP (op0, 0); /* index + base + disp */
2700 base = XEXP (op0, 1);
2706 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
2711 else if (GET_CODE (addr) == MULT)
2713 indx = XEXP (addr, 0); /* index*scale */
2714 scale = XEXP (addr, 1);
2718 disp = addr; /* displacement */
2720 /* Allow arg pointer and stack pointer as index if there is not scaling */
2721 if (base && indx && !scale
2722 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
2729 /* Validate base register:
2731 Don't allow SUBREG's here, it can lead to spill failures when the base
2732 is one word out of a two word structure, which is represented internally
2737 if (GET_CODE (base) != REG)
2739 ADDR_INVALID ("Base is not a register.\n", base);
2743 if (GET_MODE (base) != Pmode)
2745 ADDR_INVALID ("Base is not in Pmode.\n", base);
2749 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base))
2750 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base)))
2752 ADDR_INVALID ("Base is not valid.\n", base);
2757 /* Validate index register:
2759 Don't allow SUBREG's here, it can lead to spill failures when the index
2760 is one word out of a two word structure, which is represented internally
2764 if (GET_CODE (indx) != REG)
2766 ADDR_INVALID ("Index is not a register.\n", indx);
2770 if (GET_MODE (indx) != Pmode)
2772 ADDR_INVALID ("Index is not in Pmode.\n", indx);
2776 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx))
2777 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
2779 ADDR_INVALID ("Index is not valid.\n", indx);
2784 abort (); /* scale w/o index invalid */
2786 /* Validate scale factor: */
2789 HOST_WIDE_INT value;
2791 if (GET_CODE (scale) != CONST_INT)
2793 ADDR_INVALID ("Scale is not valid.\n", scale);
2797 value = INTVAL (scale);
2798 if (value != 1 && value != 2 && value != 4 && value != 8)
2800 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
2805 /* Validate displacement. */
2808 if (!CONSTANT_ADDRESS_P (disp))
2810 ADDR_INVALID ("Displacement is not valid.\n", disp);
2814 else if (GET_CODE (disp) == CONST_DOUBLE)
2816 ADDR_INVALID ("Displacement is a const_double.\n", disp);
2820 if (flag_pic && SYMBOLIC_CONST (disp))
2822 if (! legitimate_pic_address_disp_p (disp))
2824 ADDR_INVALID ("Displacement is an invalid PIC construct.\n",
2829 if (base != pic_offset_table_rtx
2830 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
2832 ADDR_INVALID ("PIC displacement against invalid base.\n", disp);
2837 else if (HALF_PIC_P ())
2839 if (! HALF_PIC_ADDRESS_P (disp)
2840 || (base != NULL_RTX || indx != NULL_RTX))
2842 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n",
2849 if (TARGET_DEBUG_ADDR)
2850 fprintf (stderr, "Address is valid.\n");
2852 /* Everything looks valid, return true */
2856 /* Return a legitimate reference for ORIG (an address) using the
2857 register REG. If REG is 0, a new pseudo is generated.
2859 There are two types of references that must be handled:
2861 1. Global data references must load the address from the GOT, via
2862 the PIC reg. An insn is emitted to do this load, and the reg is
2865 2. Static data references, constant pool addresses, and code labels
2866 compute the address as an offset from the GOT, whose base is in
2867 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to
2868 differentiate them from global data objects. The returned
2869 address is the PIC reg + an unspec constant.
2871 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2872 reg also appears in the address. */
2875 legitimize_pic_address (orig, reg)
2883 if (GET_CODE (addr) == LABEL_REF
2884 || (GET_CODE (addr) == SYMBOL_REF
2885 && (CONSTANT_POOL_ADDRESS_P (addr)
2886 || SYMBOL_REF_FLAG (addr))))
2888 /* This symbol may be referenced via a displacement from the PIC
2889 base address (@GOTOFF). */
2891 current_function_uses_pic_offset_table = 1;
2892 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7);
2893 new = gen_rtx_CONST (VOIDmode, new);
2894 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2898 emit_move_insn (reg, new);
2902 else if (GET_CODE (addr) == SYMBOL_REF)
2904 /* This symbol must be referenced via a load from the
2905 Global Offset Table (@GOT). */
2907 current_function_uses_pic_offset_table = 1;
2908 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6);
2909 new = gen_rtx_CONST (VOIDmode, new);
2910 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2911 new = gen_rtx_MEM (Pmode, new);
2912 RTX_UNCHANGING_P (new) = 1;
2915 reg = gen_reg_rtx (Pmode);
2916 emit_move_insn (reg, new);
2921 if (GET_CODE (addr) == CONST)
2923 addr = XEXP (addr, 0);
2924 if (GET_CODE (addr) == UNSPEC)
2926 /* Check that the unspec is one of the ones we generate? */
2928 else if (GET_CODE (addr) != PLUS)
2931 if (GET_CODE (addr) == PLUS)
2933 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2935 /* Check first to see if this is a constant offset from a @GOTOFF
2936 symbol reference. */
2937 if ((GET_CODE (op0) == LABEL_REF
2938 || (GET_CODE (op0) == SYMBOL_REF
2939 && (CONSTANT_POOL_ADDRESS_P (op0)
2940 || SYMBOL_REF_FLAG (op0))))
2941 && GET_CODE (op1) == CONST_INT)
2943 current_function_uses_pic_offset_table = 1;
2944 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7);
2945 new = gen_rtx_PLUS (VOIDmode, new, op1);
2946 new = gen_rtx_CONST (VOIDmode, new);
2947 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2951 emit_move_insn (reg, new);
2957 base = legitimize_pic_address (XEXP (addr, 0), reg);
2958 new = legitimize_pic_address (XEXP (addr, 1),
2959 base == reg ? NULL_RTX : reg);
2961 if (GET_CODE (new) == CONST_INT)
2962 new = plus_constant (base, INTVAL (new));
2965 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
2967 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
2968 new = XEXP (new, 1);
2970 new = gen_rtx_PLUS (Pmode, base, new);
2978 /* Emit insns to move operands[1] into operands[0]. */
2981 emit_pic_move (operands, mode)
2983 enum machine_mode mode ATTRIBUTE_UNUSED;
2985 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
2987 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
2988 operands[1] = force_reg (Pmode, operands[1]);
2990 operands[1] = legitimize_pic_address (operands[1], temp);
2993 /* Try machine-dependent ways of modifying an illegitimate address
2994 to be legitimate. If we find one, return the new, valid address.
2995 This macro is used in only one place: `memory_address' in explow.c.
2997 OLDX is the address as it was before break_out_memory_refs was called.
2998 In some cases it is useful to look at this to decide what needs to be done.
3000 MODE and WIN are passed so that this macro can use
3001 GO_IF_LEGITIMATE_ADDRESS.
3003 It is always safe for this macro to do nothing. It exists to recognize
3004 opportunities to optimize the output.
3006 For the 80386, we handle X+REG by loading X into a register R and
3007 using R+REG. R will go in a general reg and indexing will be used.
3008 However, if REG is a broken-out memory address or multiplication,
3009 nothing needs to be done because REG can certainly go in a general reg.
3011 When -fpic is used, special handling is needed for symbolic references.
3012 See comments by legitimize_pic_address in i386.c for details. */
3015 legitimize_address (x, oldx, mode)
3017 register rtx oldx ATTRIBUTE_UNUSED;
3018 enum machine_mode mode;
3023 if (TARGET_DEBUG_ADDR)
3025 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
3026 GET_MODE_NAME (mode));
3030 if (flag_pic && SYMBOLIC_CONST (x))
3031 return legitimize_pic_address (x, 0);
3033 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
3034 if (GET_CODE (x) == ASHIFT
3035 && GET_CODE (XEXP (x, 1)) == CONST_INT
3036 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
3039 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
3040 GEN_INT (1 << log));
3043 if (GET_CODE (x) == PLUS)
3045 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
3047 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3048 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3049 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
3052 XEXP (x, 0) = gen_rtx (MULT, Pmode,
3053 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
3054 GEN_INT (1 << log));
3057 if (GET_CODE (XEXP (x, 1)) == ASHIFT
3058 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3059 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
3062 XEXP (x, 1) = gen_rtx (MULT, Pmode,
3063 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
3064 GEN_INT (1 << log));
3067 /* Put multiply first if it isn't already. */
3068 if (GET_CODE (XEXP (x, 1)) == MULT)
3070 rtx tmp = XEXP (x, 0);
3071 XEXP (x, 0) = XEXP (x, 1);
3076 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
3077 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
3078 created by virtual register instantiation, register elimination, and
3079 similar optimizations. */
3080 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
3083 x = gen_rtx (PLUS, Pmode,
3084 gen_rtx (PLUS, Pmode, XEXP (x, 0),
3085 XEXP (XEXP (x, 1), 0)),
3086 XEXP (XEXP (x, 1), 1));
3090 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
3091 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
3092 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
3093 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3094 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
3095 && CONSTANT_P (XEXP (x, 1)))
3098 rtx other = NULL_RTX;
3100 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3102 constant = XEXP (x, 1);
3103 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
3105 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
3107 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
3108 other = XEXP (x, 1);
3116 x = gen_rtx (PLUS, Pmode,
3117 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
3118 XEXP (XEXP (XEXP (x, 0), 1), 0)),
3119 plus_constant (other, INTVAL (constant)));
3123 if (changed && legitimate_address_p (mode, x, FALSE))
3126 if (GET_CODE (XEXP (x, 0)) == MULT)
3129 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
3132 if (GET_CODE (XEXP (x, 1)) == MULT)
3135 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
3139 && GET_CODE (XEXP (x, 1)) == REG
3140 && GET_CODE (XEXP (x, 0)) == REG)
3143 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
3146 x = legitimize_pic_address (x, 0);
3149 if (changed && legitimate_address_p (mode, x, FALSE))
3152 if (GET_CODE (XEXP (x, 0)) == REG)
3154 register rtx temp = gen_reg_rtx (Pmode);
3155 register rtx val = force_operand (XEXP (x, 1), temp);
3157 emit_move_insn (temp, val);
3163 else if (GET_CODE (XEXP (x, 1)) == REG)
3165 register rtx temp = gen_reg_rtx (Pmode);
3166 register rtx val = force_operand (XEXP (x, 0), temp);
3168 emit_move_insn (temp, val);
3178 /* Print an integer constant expression in assembler syntax. Addition
3179 and subtraction are the only arithmetic that may appear in these
3180 expressions. FILE is the stdio stream to write to, X is the rtx, and
3181 CODE is the operand print code from the output string. */
3184 output_pic_addr_const (file, x, code)
3191 switch (GET_CODE (x))
3201 assemble_name (file, XSTR (x, 0));
3202 if (code == 'P' && ! SYMBOL_REF_FLAG (x))
3203 fputs ("@PLT", file);
3210 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
3211 assemble_name (asm_out_file, buf);
3215 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
3219 /* This used to output parentheses around the expression,
3220 but that does not work on the 386 (either ATT or BSD assembler). */
3221 output_pic_addr_const (file, XEXP (x, 0), code);
3225 if (GET_MODE (x) == VOIDmode)
3227 /* We can use %d if the number is <32 bits and positive. */
3228 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
3229 fprintf (file, "0x%lx%08lx",
3230 (unsigned long) CONST_DOUBLE_HIGH (x),
3231 (unsigned long) CONST_DOUBLE_LOW (x));
3233 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
3236 /* We can't handle floating point constants;
3237 PRINT_OPERAND must handle them. */
3238 output_operand_lossage ("floating constant misused");
3242 /* Some assemblers need integer constants to appear first. */
3243 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3245 output_pic_addr_const (file, XEXP (x, 0), code);
3246 fprintf (file, "+");
3247 output_pic_addr_const (file, XEXP (x, 1), code);
3249 else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3251 output_pic_addr_const (file, XEXP (x, 1), code);
3252 fprintf (file, "+");
3253 output_pic_addr_const (file, XEXP (x, 0), code);
3260 output_pic_addr_const (file, XEXP (x, 0), code);
3261 fprintf (file, "-");
3262 output_pic_addr_const (file, XEXP (x, 1), code);
3266 if (XVECLEN (x, 0) != 1)
3268 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
3269 switch (XINT (x, 1))
3272 fputs ("@GOT", file);
3275 fputs ("@GOTOFF", file);
3278 fputs ("@PLT", file);
3281 output_operand_lossage ("invalid UNSPEC as operand");
3287 output_operand_lossage ("invalid expression as operand");
3292 put_jump_code (code, reverse, file)
3297 int flags = cc_prev_status.flags;
3298 int ieee = (TARGET_IEEE_FP && (flags & CC_IN_80387));
3301 if (flags & CC_Z_IN_NOT_C)
3305 fputs (reverse ? "c" : "nc", file);
3309 fputs (reverse ? "nc" : "c", file);
3320 suffix = reverse ? "ae" : "b";
3325 suffix = reverse ? "ne" : "e";
3328 suffix = reverse ? "ne" : "e";
3331 suffix = reverse ? "e" : "ne";
3336 fputs (suffix, file);
3339 if (flags & CC_TEST_AX)
3341 if ((flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
3344 code = reverse_condition (code);
3356 suffix = flags & CC_IN_80387 ? "a" : "g";
3364 if (flags & CC_NO_OVERFLOW)
3367 suffix = flags & CC_IN_80387 ? "b" : "l";
3375 if (flags & CC_NO_OVERFLOW)
3378 suffix = flags & CC_IN_80387 ? "ae" : "ge";
3386 suffix = flags & CC_IN_80387 ? "be" : "le";
3396 fputs (suffix, file);
3399 /* Append the correct conditional move suffix which corresponds to CODE. */
3402 put_condition_code (code, reverse_cc, mode, file)
3405 enum mode_class mode;
3408 int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
3409 && ! (cc_prev_status.flags & CC_FCOMI));
3410 if (reverse_cc && ! ieee)
3411 code = reverse_condition (code);
3413 if (mode == MODE_INT)
3417 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3424 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3431 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3446 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3469 output_operand_lossage ("Invalid %%C operand");
3472 else if (mode == MODE_FLOAT)
3476 fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file);
3479 fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file);
3482 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3485 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3488 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3491 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3494 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3497 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3500 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3503 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3506 output_operand_lossage ("Invalid %%C operand");
3511 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
3512 C -- print opcode suffix for set/cmov insn.
3513 c -- like C, but print reversed condition
3514 F -- print opcode suffix for fcmov insn.
3515 f -- like F, but print reversed condition
3516 D -- print the opcode suffix for a jump
3517 d -- like D, but print reversed condition
3518 R -- print the prefix for register names.
3519 z -- print the opcode suffix for the size of the current operand.
3520 * -- print a star (in certain assembler syntax)
3521 w -- print the operand as if it's a "word" (HImode) even if it isn't.
3522 J -- print the appropriate jump operand.
3523 s -- print a shift double count, followed by the assemblers argument
3525 b -- print the QImode name of the register for the indicated operand.
3526 %b0 would print %al if operands[0] is reg 0.
3527 w -- likewise, print the HImode name of the register.
3528 k -- likewise, print the SImode name of the register.
3529 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
3530 y -- print "st(0)" instead of "st" as a register.
3531 P -- print as a PIC constant */
3534 print_operand (file, x, code)
3549 PUT_OP_SIZE (code, 'l', file);
3553 PUT_OP_SIZE (code, 'w', file);
3557 PUT_OP_SIZE (code, 'b', file);
3561 PUT_OP_SIZE (code, 'l', file);
3565 PUT_OP_SIZE (code, 's', file);
3569 PUT_OP_SIZE (code, 't', file);
3573 /* 387 opcodes don't get size suffixes if the operands are
3576 if (STACK_REG_P (x))
3579 /* this is the size of op from size of operand */
3580 switch (GET_MODE_SIZE (GET_MODE (x)))
3583 PUT_OP_SIZE ('B', 'b', file);
3587 PUT_OP_SIZE ('W', 'w', file);
3591 if (GET_MODE (x) == SFmode)
3593 PUT_OP_SIZE ('S', 's', file);
3597 PUT_OP_SIZE ('L', 'l', file);
3601 PUT_OP_SIZE ('T', 't', file);
3605 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
3607 #ifdef GAS_MNEMONICS
3608 PUT_OP_SIZE ('Q', 'q', file);
3611 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
3615 PUT_OP_SIZE ('Q', 'l', file);
3629 switch (GET_CODE (x))
3631 /* These conditions are appropriate for testing the result
3632 of an arithmetic operation, not for a compare operation.
3633 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
3634 CC_Z_IN_NOT_C false and not floating point. */
3635 case NE: fputs ("jne", file); return;
3636 case EQ: fputs ("je", file); return;
3637 case GE: fputs ("jns", file); return;
3638 case LT: fputs ("js", file); return;
3639 case GEU: fputs ("jmp", file); return;
3640 case GTU: fputs ("jne", file); return;
3641 case LEU: fputs ("je", file); return;
3642 case LTU: fputs ("#branch never", file); return;
3644 /* no matching branches for GT nor LE */
3651 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
3653 PRINT_OPERAND (file, x, 0);
3654 fputs (AS2C (,) + 1, file);
3660 put_jump_code (GET_CODE (x), 0, file);
3664 put_jump_code (GET_CODE (x), 1, file);
3667 /* This is used by the conditional move instructions. */
3669 put_condition_code (GET_CODE (x), 0, MODE_INT, file);
3672 /* Like above, but reverse condition */
3674 put_condition_code (GET_CODE (x), 1, MODE_INT, file); return;
3677 put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file);
3680 /* Like above, but reverse condition */
3682 put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file);
3689 sprintf (str, "invalid operand code `%c'", code);
3690 output_operand_lossage (str);
3695 if (GET_CODE (x) == REG)
3697 PRINT_REG (x, code, file);
3700 else if (GET_CODE (x) == MEM)
3702 PRINT_PTR (x, file);
3703 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
3706 output_pic_addr_const (file, XEXP (x, 0), code);
3708 output_addr_const (file, XEXP (x, 0));
3711 output_address (XEXP (x, 0));
3714 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
3719 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3720 REAL_VALUE_TO_TARGET_SINGLE (r, l);
3721 PRINT_IMMED_PREFIX (file);
3722 fprintf (file, "0x%lx", l);
3725 /* These float cases don't actually occur as immediate operands. */
3726 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
3731 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3732 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3733 fprintf (file, "%s", dstr);
3736 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
3741 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3742 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3743 fprintf (file, "%s", dstr);
3749 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3750 PRINT_IMMED_PREFIX (file);
3751 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
3752 || GET_CODE (x) == LABEL_REF)
3753 PRINT_OFFSET_PREFIX (file);
3756 output_pic_addr_const (file, x, code);
3758 output_addr_const (file, x);
3762 /* Print a memory operand whose address is ADDR. */
3765 print_operand_address (file, addr)
3769 register rtx reg1, reg2, breg, ireg;
3772 switch (GET_CODE (addr))
3775 /* ESI addressing makes instruction vector decoded on the K6. We can
3776 avoid this by ESI+0 addressing. */
3777 if (REGNO_REG_CLASS (REGNO (addr)) == SIREG
3778 && ix86_cpu == PROCESSOR_K6 && !optimize_size)
3779 output_addr_const (file, const0_rtx);
3781 fprintf (file, "%se", RP);
3782 fputs (hi_reg_name[REGNO (addr)], file);
3792 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
3794 offset = XEXP (addr, 0);
3795 addr = XEXP (addr, 1);
3797 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
3799 offset = XEXP (addr, 1);
3800 addr = XEXP (addr, 0);
3803 if (GET_CODE (addr) != PLUS)
3805 else if (GET_CODE (XEXP (addr, 0)) == MULT)
3806 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3807 else if (GET_CODE (XEXP (addr, 1)) == MULT)
3808 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3809 else if (GET_CODE (XEXP (addr, 0)) == REG)
3810 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3811 else if (GET_CODE (XEXP (addr, 1)) == REG)
3812 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3814 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
3831 if ((reg1 && GET_CODE (reg1) == MULT)
3832 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
3837 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3843 if (ireg != 0 || breg != 0)
3850 output_pic_addr_const (file, addr, 0);
3851 else if (GET_CODE (addr) == LABEL_REF)
3852 output_asm_label (addr);
3854 output_addr_const (file, addr);
3857 if (ireg != 0 && GET_CODE (ireg) == MULT)
3859 scale = INTVAL (XEXP (ireg, 1));
3860 ireg = XEXP (ireg, 0);
3863 /* The stack pointer can only appear as a base register,
3864 never an index register, so exchange the regs if it is wrong. */
3866 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
3875 /* output breg+ireg*scale */
3876 PRINT_B_I_S (breg, ireg, scale, file);
3884 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
3886 scale = INTVAL (XEXP (addr, 0));
3887 ireg = XEXP (addr, 1);
3891 scale = INTVAL (XEXP (addr, 1));
3892 ireg = XEXP (addr, 0);
3895 /* (reg,reg,) is shorter than (,reg,2). */
3898 PRINT_B_I_S (ireg, ireg, 1, file);
3902 output_addr_const (file, const0_rtx);
3903 PRINT_B_I_S (NULL_RTX, ireg, scale, file);
3909 if (GET_CODE (addr) == CONST_INT
3910 && INTVAL (addr) < 0x8000
3911 && INTVAL (addr) >= -0x8000)
3912 fprintf (file, "%d", (int) INTVAL (addr));
3916 output_pic_addr_const (file, addr, 0);
3918 output_addr_const (file, addr);
3923 /* Set the cc_status for the results of an insn whose pattern is EXP.
3924 On the 80386, we assume that only test and compare insns, as well
3925 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT,
3926 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
3927 Also, we assume that jumps, moves and sCOND don't affect the condition
3928 codes. All else clobbers the condition codes, by assumption.
3930 We assume that ALL integer add, minus, etc. instructions effect the
3931 condition codes. This MUST be consistent with i386.md.
3933 We don't record any float test or compare - the redundant test &
3934 compare check in final.c does not handle stack-like regs correctly. */
3937 notice_update_cc (exp)
3940 if (GET_CODE (exp) == SET)
3942 /* Jumps do not alter the cc's. */
3943 if (SET_DEST (exp) == pc_rtx)
3946 /* Moving register or memory into a register:
3947 it doesn't alter the cc's, but it might invalidate
3948 the RTX's which we remember the cc's came from.
3949 (Note that moving a constant 0 or 1 MAY set the cc's). */
3950 if (REG_P (SET_DEST (exp))
3951 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
3952 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'
3953 || GET_CODE (SET_SRC (exp)) == IF_THEN_ELSE))
3955 if (cc_status.value1
3956 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3957 cc_status.value1 = 0;
3959 if (cc_status.value2
3960 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3961 cc_status.value2 = 0;
3966 /* Moving register into memory doesn't alter the cc's.
3967 It may invalidate the RTX's which we remember the cc's came from. */
3968 if (GET_CODE (SET_DEST (exp)) == MEM
3969 && (REG_P (SET_SRC (exp))
3970 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3972 if (cc_status.value1
3973 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3974 cc_status.value1 = 0;
3975 if (cc_status.value2
3976 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3977 cc_status.value2 = 0;
3982 /* Function calls clobber the cc's. */
3983 else if (GET_CODE (SET_SRC (exp)) == CALL)
3989 /* Tests and compares set the cc's in predictable ways. */
3990 else if (SET_DEST (exp) == cc0_rtx)
3993 cc_status.value1 = SET_SRC (exp);
3997 /* Certain instructions effect the condition codes. */
3998 else if (GET_MODE (SET_SRC (exp)) == SImode
3999 || GET_MODE (SET_SRC (exp)) == HImode
4000 || GET_MODE (SET_SRC (exp)) == QImode)
4001 switch (GET_CODE (SET_SRC (exp)))
4003 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
4004 /* Shifts on the 386 don't set the condition codes if the
4005 shift count is zero. */
4006 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
4012 /* We assume that the CONST_INT is non-zero (this rtx would
4013 have been deleted if it were zero. */
4015 case PLUS: case MINUS: case NEG:
4016 case AND: case IOR: case XOR:
4017 cc_status.flags = CC_NO_OVERFLOW;
4018 cc_status.value1 = SET_SRC (exp);
4019 cc_status.value2 = SET_DEST (exp);
4022 /* This is the bsf pattern used by ffs. */
4024 if (XINT (SET_SRC (exp), 1) == 5)
4026 /* Only the Z flag is defined after bsf. */
4028 = CC_NOT_POSITIVE | CC_NOT_NEGATIVE | CC_NO_OVERFLOW;
4029 cc_status.value1 = XVECEXP (SET_SRC (exp), 0, 0);
4030 cc_status.value2 = 0;
4043 else if (GET_CODE (exp) == PARALLEL
4044 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
4046 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
4048 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
4052 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
4054 cc_status.flags |= CC_IN_80387;
4055 if (0 && TARGET_CMOVE && stack_regs_mentioned_p
4056 (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
4057 cc_status.flags |= CC_FCOMI;
4060 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
4072 /* Split one or more DImode RTL references into pairs of SImode
4073 references. The RTL can be REG, offsettable MEM, integer constant, or
4074 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
4075 split and "num" is its length. lo_half and hi_half are output arrays
4076 that parallel "operands". */
4079 split_di (operands, num, lo_half, hi_half)
4082 rtx lo_half[], hi_half[];
4086 rtx op = operands[num];
4087 if (! reload_completed)
4089 lo_half[num] = gen_lowpart (SImode, op);
4090 hi_half[num] = gen_highpart (SImode, op);
4092 else if (GET_CODE (op) == REG)
4094 lo_half[num] = gen_rtx_REG (SImode, REGNO (op));
4095 hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1);
4097 else if (CONSTANT_P (op))
4098 split_double (op, &lo_half[num], &hi_half[num]);
4099 else if (offsettable_memref_p (op))
4101 rtx lo_addr = XEXP (op, 0);
4102 rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0);
4103 lo_half[num] = change_address (op, SImode, lo_addr);
4104 hi_half[num] = change_address (op, SImode, hi_addr);
4111 /* Return 1 if this is a valid binary operation on a 387.
4112 OP is the expression matched, and MODE is its mode. */
4115 binary_387_op (op, mode)
4117 enum machine_mode mode;
4119 if (mode != VOIDmode && mode != GET_MODE (op))
4122 switch (GET_CODE (op))
4128 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
4135 /* Return 1 if this is a valid shift or rotate operation on a 386.
4136 OP is the expression matched, and MODE is its mode. */
4141 enum machine_mode mode;
4143 rtx operand = XEXP (op, 0);
4145 if (mode != VOIDmode && mode != GET_MODE (op))
4148 if (GET_MODE (operand) != GET_MODE (op)
4149 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
4152 return (GET_CODE (op) == ASHIFT
4153 || GET_CODE (op) == ASHIFTRT
4154 || GET_CODE (op) == LSHIFTRT
4155 || GET_CODE (op) == ROTATE
4156 || GET_CODE (op) == ROTATERT);
4159 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
4160 MODE is not used. */
4163 VOIDmode_compare_op (op, mode)
4165 enum machine_mode mode ATTRIBUTE_UNUSED;
4167 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
4170 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
4171 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
4172 is the expression of the binary operation. The output may either be
4173 emitted here, or returned to the caller, like all output_* functions.
4175 There is no guarantee that the operands are the same mode, as they
4176 might be within FLOAT or FLOAT_EXTEND expressions. */
4179 output_387_binary_op (insn, operands)
4185 static char buf[100];
4187 switch (GET_CODE (operands[3]))
4209 strcpy (buf, base_op);
4211 switch (GET_CODE (operands[3]))
4215 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
4218 operands[2] = operands[1];
4222 if (GET_CODE (operands[2]) == MEM)
4223 return strcat (buf, AS1 (%z2,%2));
4225 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
4228 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
4230 if (STACK_TOP_P (operands[0]))
4231 return strcat (buf, AS2 (p,%0,%2));
4233 return strcat (buf, AS2 (p,%2,%0));
4236 if (STACK_TOP_P (operands[0]))
4237 return strcat (buf, AS2C (%y2,%0));
4239 return strcat (buf, AS2C (%2,%0));
4243 if (GET_CODE (operands[1]) == MEM)
4244 return strcat (buf, AS1 (r%z1,%1));
4246 if (GET_CODE (operands[2]) == MEM)
4247 return strcat (buf, AS1 (%z2,%2));
4249 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
4252 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
4254 if (STACK_TOP_P (operands[0]))
4255 return strcat (buf, AS2 (p,%0,%2));
4257 return strcat (buf, AS2 (rp,%2,%0));
4260 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4262 if (STACK_TOP_P (operands[0]))
4263 return strcat (buf, AS2 (rp,%0,%1));
4265 return strcat (buf, AS2 (p,%1,%0));
4268 if (STACK_TOP_P (operands[0]))
4270 if (STACK_TOP_P (operands[1]))
4271 return strcat (buf, AS2C (%y2,%0));
4273 return strcat (buf, AS2 (r,%y1,%0));
4275 else if (STACK_TOP_P (operands[1]))
4276 return strcat (buf, AS2C (%1,%0));
4278 return strcat (buf, AS2 (r,%2,%0));
4285 /* Output code for INSN to convert a float to a signed int. OPERANDS
4286 are the insn operands. The output may be SFmode or DFmode and the
4287 input operand may be SImode or DImode. As a special case, make sure
4288 that the 387 stack top dies if the output mode is DImode, because the
4289 hardware requires this. */
4292 output_fix_trunc (insn, operands)
4296 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4299 if (! STACK_TOP_P (operands[1]))
4302 xops[0] = GEN_INT (12);
4303 xops[1] = operands[4];
4305 output_asm_insn (AS1 (fnstc%W2,%2), operands);
4306 output_asm_insn (AS2 (mov%L2,%2,%4), operands);
4307 output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
4308 output_asm_insn (AS2 (mov%L4,%4,%3), operands);
4309 output_asm_insn (AS1 (fldc%W3,%3), operands);
4311 if (NON_STACK_REG_P (operands[0]))
4312 output_to_reg (operands[0], stack_top_dies, operands[3]);
4314 else if (GET_CODE (operands[0]) == MEM)
4317 output_asm_insn (AS1 (fistp%z0,%0), operands);
4318 else if (GET_MODE (operands[0]) == DImode && ! stack_top_dies)
4320 /* There is no DImode version of this without a stack pop, so
4321 we must emulate it. It doesn't matter much what the second
4322 instruction is, because the value being pushed on the FP stack
4323 is not used except for the following stack popping store.
4324 This case can only happen without optimization, so it doesn't
4325 matter that it is inefficient. */
4326 output_asm_insn (AS1 (fistp%z0,%0), operands);
4327 output_asm_insn (AS1 (fild%z0,%0), operands);
4330 output_asm_insn (AS1 (fist%z0,%0), operands);
4335 return AS1 (fldc%W2,%2);
4338 /* Output code for INSN to compare OPERANDS. The two operands might
4339 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
4340 expression. If the compare is in mode CCFPEQmode, use an opcode that
4341 will not fault if a qNaN is present. */
4344 output_float_compare (insn, operands)
4349 rtx body = XVECEXP (PATTERN (insn), 0, 0);
4350 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
4353 if (0 && TARGET_CMOVE && STACK_REG_P (operands[1]))
4355 cc_status.flags |= CC_FCOMI;
4356 cc_prev_status.flags &= ~CC_TEST_AX;
4359 if (! STACK_TOP_P (operands[0]))
4362 operands[0] = operands[1];
4364 cc_status.flags |= CC_REVERSED;
4367 if (! STACK_TOP_P (operands[0]))
4370 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4372 if (STACK_REG_P (operands[1])
4374 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4375 && REGNO (operands[1]) != FIRST_STACK_REG)
4377 /* If both the top of the 387 stack dies, and the other operand
4378 is also a stack register that dies, then this must be a
4379 `fcompp' float compare */
4381 if (unordered_compare)
4383 if (cc_status.flags & CC_FCOMI)
4385 output_asm_insn (AS2 (fucomip,%y1,%0), operands);
4386 output_asm_insn (AS1 (fstp, %y0), operands);
4390 output_asm_insn ("fucompp", operands);
4394 if (cc_status.flags & CC_FCOMI)
4396 output_asm_insn (AS2 (fcomip, %y1,%0), operands);
4397 output_asm_insn (AS1 (fstp, %y0), operands);
4401 output_asm_insn ("fcompp", operands);
4406 static char buf[100];
4408 /* Decide if this is a float compare or an unordered float compare. */
4410 if (unordered_compare)
4411 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom");
4413 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom");
4415 /* Modify the opcode if the 387 stack is to be popped. */
4420 if (cc_status.flags & CC_FCOMI)
4422 output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands);
4426 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
4429 /* Now retrieve the condition code. */
4431 return output_fp_cc0_set (insn);
4434 /* Output opcodes to transfer the results of FP compare or test INSN
4435 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
4436 result of the compare or test is unordered, no comparison operator
4437 succeeds except NE. Return an output template, if any. */
4440 output_fp_cc0_set (insn)
4447 xops[0] = gen_rtx_REG (HImode, 0);
4448 output_asm_insn (AS1 (fnsts%W0,%0), xops);
4450 if (! TARGET_IEEE_FP)
4452 if (!(cc_status.flags & CC_REVERSED))
4454 next = next_cc0_user (insn);
4456 if (GET_CODE (next) == JUMP_INSN
4457 && GET_CODE (PATTERN (next)) == SET
4458 && SET_DEST (PATTERN (next)) == pc_rtx
4459 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4460 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4461 else if (GET_CODE (PATTERN (next)) == SET)
4462 code = GET_CODE (SET_SRC (PATTERN (next)));
4466 if (code == GT || code == LT || code == EQ || code == NE
4467 || code == LE || code == GE)
4469 /* We will test eax directly. */
4470 cc_status.flags |= CC_TEST_AX;
4478 next = next_cc0_user (insn);
4479 if (next == NULL_RTX)
4482 if (GET_CODE (next) == JUMP_INSN
4483 && GET_CODE (PATTERN (next)) == SET
4484 && SET_DEST (PATTERN (next)) == pc_rtx
4485 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4486 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4487 else if (GET_CODE (PATTERN (next)) == SET)
4489 if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4490 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4492 code = GET_CODE (SET_SRC (PATTERN (next)));
4495 else if (GET_CODE (PATTERN (next)) == PARALLEL
4496 && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET)
4498 if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE)
4499 code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0));
4501 code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0)));
4506 xops[0] = gen_rtx_REG (QImode, 0);
4511 xops[1] = GEN_INT (0x45);
4512 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4517 xops[1] = GEN_INT (0x45);
4518 xops[2] = GEN_INT (0x01);
4519 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4520 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4525 xops[1] = GEN_INT (0x05);
4526 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4531 xops[1] = GEN_INT (0x45);
4532 xops[2] = GEN_INT (0x40);
4533 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4534 output_asm_insn (AS1 (dec%B0,%h0), xops);
4535 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4540 xops[1] = GEN_INT (0x45);
4541 xops[2] = GEN_INT (0x40);
4542 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4543 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4548 xops[1] = GEN_INT (0x44);
4549 xops[2] = GEN_INT (0x40);
4550 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4551 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
4566 #define MAX_386_STACK_LOCALS 2
4568 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4570 /* Define the structure for the machine field in struct function. */
4571 struct machine_function
4573 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4575 char pic_label_name[256];
4578 /* Functions to save and restore i386_stack_locals.
4579 These will be called, via pointer variables,
4580 from push_function_context and pop_function_context. */
4583 save_386_machine_status (p)
4587 = (struct machine_function *) xmalloc (sizeof (struct machine_function));
4588 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
4589 sizeof i386_stack_locals);
4590 p->machine->pic_label_rtx = pic_label_rtx;
4591 bcopy (pic_label_name, p->machine->pic_label_name, 256);
4595 restore_386_machine_status (p)
4598 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
4599 sizeof i386_stack_locals);
4600 pic_label_rtx = p->machine->pic_label_rtx;
4601 bcopy (p->machine->pic_label_name, pic_label_name, 256);
4606 /* Clear stack slot assignments remembered from previous functions.
4607 This is called from INIT_EXPANDERS once before RTL is emitted for each
4611 clear_386_stack_locals ()
4613 enum machine_mode mode;
4616 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
4617 mode = (enum machine_mode) ((int) mode + 1))
4618 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
4619 i386_stack_locals[(int) mode][n] = NULL_RTX;
4621 pic_label_rtx = NULL_RTX;
4622 bzero (pic_label_name, 256);
4623 /* Arrange to save and restore i386_stack_locals around nested functions. */
4624 save_machine_status = save_386_machine_status;
4625 restore_machine_status = restore_386_machine_status;
4628 /* Return a MEM corresponding to a stack slot with mode MODE.
4629 Allocate a new slot if necessary.
4631 The RTL for a function can have several slots available: N is
4632 which slot to use. */
4635 assign_386_stack_local (mode, n)
4636 enum machine_mode mode;
4639 if (n < 0 || n >= MAX_386_STACK_LOCALS)
4642 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
4643 i386_stack_locals[(int) mode][n]
4644 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
4646 return i386_stack_locals[(int) mode][n];
4651 enum machine_mode mode ATTRIBUTE_UNUSED;
4653 return (GET_CODE (op) == MULT);
4658 enum machine_mode mode ATTRIBUTE_UNUSED;
4660 return (GET_CODE (op) == DIV);
4664 /* Create a new copy of an rtx.
4665 Recursively copies the operands of the rtx,
4666 except for those few rtx codes that are sharable.
4667 Doesn't share CONST */
4675 register RTX_CODE code;
4676 register char *format_ptr;
4678 code = GET_CODE (orig);
4691 /* SCRATCH must be shared because they represent distinct values. */
4696 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
4697 a LABEL_REF, it isn't sharable. */
4698 if (GET_CODE (XEXP (orig, 0)) == PLUS
4699 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
4700 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
4704 /* A MEM with a constant address is not sharable. The problem is that
4705 the constant address may need to be reloaded. If the mem is shared,
4706 then reloading one copy of this mem will cause all copies to appear
4707 to have been reloaded. */
4710 copy = rtx_alloc (code);
4711 PUT_MODE (copy, GET_MODE (orig));
4712 copy->in_struct = orig->in_struct;
4713 copy->volatil = orig->volatil;
4714 copy->unchanging = orig->unchanging;
4715 copy->integrated = orig->integrated;
4717 copy->is_spill_rtx = orig->is_spill_rtx;
4719 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
4721 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
4723 switch (*format_ptr++)
4726 XEXP (copy, i) = XEXP (orig, i);
4727 if (XEXP (orig, i) != NULL)
4728 XEXP (copy, i) = copy_rtx (XEXP (orig, i));
4733 XEXP (copy, i) = XEXP (orig, i);
4738 XVEC (copy, i) = XVEC (orig, i);
4739 if (XVEC (orig, i) != NULL)
4741 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
4742 for (j = 0; j < XVECLEN (copy, i); j++)
4743 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
4748 XWINT (copy, i) = XWINT (orig, i);
4752 XINT (copy, i) = XINT (orig, i);
4757 XSTR (copy, i) = XSTR (orig, i);
4768 /* Try to rewrite a memory address to make it valid */
4771 rewrite_address (mem_rtx)
4774 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
4776 int offset_adjust = 0;
4777 int was_only_offset = 0;
4778 rtx mem_addr = XEXP (mem_rtx, 0);
4779 char *storage = oballoc (0);
4781 int is_spill_rtx = 0;
4783 in_struct = MEM_IN_STRUCT_P (mem_rtx);
4784 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
4786 if (GET_CODE (mem_addr) == PLUS
4787 && GET_CODE (XEXP (mem_addr, 1)) == PLUS
4788 && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
4790 /* This part is utilized by the combiner. */
4792 = gen_rtx (PLUS, GET_MODE (mem_addr),
4793 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
4794 XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)),
4795 XEXP (XEXP (mem_addr, 1), 1));
4797 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
4799 XEXP (mem_rtx, 0) = ret_rtx;
4800 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
4807 /* This part is utilized by loop.c.
4808 If the address contains PLUS (reg,const) and this pattern is invalid
4809 in this case - try to rewrite the address to make it valid. */
4810 storage = oballoc (0);
4811 index_rtx = base_rtx = offset_rtx = NULL;
4813 /* Find the base index and offset elements of the memory address. */
4814 if (GET_CODE (mem_addr) == PLUS)
4816 if (GET_CODE (XEXP (mem_addr, 0)) == REG)
4818 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4819 base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0);
4821 base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1);
4824 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
4826 index_rtx = XEXP (mem_addr, 0);
4827 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4828 base_rtx = XEXP (mem_addr, 1);
4830 offset_rtx = XEXP (mem_addr, 1);
4833 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
4835 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS
4836 && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT
4837 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0))
4839 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1))
4841 && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1))
4843 && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG
4844 && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
4846 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
4847 offset_rtx = XEXP (mem_addr, 1);
4848 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4849 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
4853 offset_rtx = XEXP (mem_addr, 1);
4854 index_rtx = XEXP (XEXP (mem_addr, 0), 0);
4855 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4859 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
4861 was_only_offset = 1;
4864 offset_rtx = XEXP (mem_addr, 1);
4865 offset_adjust = INTVAL (XEXP (mem_addr, 0));
4866 if (offset_adjust == 0)
4868 XEXP (mem_rtx, 0) = offset_rtx;
4869 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4879 else if (GET_CODE (mem_addr) == MULT)
4880 index_rtx = mem_addr;
4887 if (index_rtx != 0 && GET_CODE (index_rtx) == MULT)
4889 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
4895 scale_rtx = XEXP (index_rtx, 1);
4896 scale = INTVAL (scale_rtx);
4897 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4900 /* Now find which of the elements are invalid and try to fix them. */
4901 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
4903 offset_adjust = INTVAL (index_rtx) * scale;
4905 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4906 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4907 else if (offset_rtx == 0)
4908 offset_rtx = const0_rtx;
4910 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4911 XEXP (mem_rtx, 0) = offset_rtx;
4915 if (base_rtx && GET_CODE (base_rtx) == PLUS
4916 && GET_CODE (XEXP (base_rtx, 0)) == REG
4917 && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
4919 offset_adjust += INTVAL (XEXP (base_rtx, 1));
4920 base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
4923 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
4925 offset_adjust += INTVAL (base_rtx);
4929 if (index_rtx && GET_CODE (index_rtx) == PLUS
4930 && GET_CODE (XEXP (index_rtx, 0)) == REG
4931 && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
4933 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
4934 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4939 if (! LEGITIMATE_INDEX_P (index_rtx)
4940 && ! (index_rtx == stack_pointer_rtx && scale == 1
4941 && base_rtx == NULL))
4950 if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
4957 if (offset_adjust != 0)
4959 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4960 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4962 offset_rtx = const0_rtx;
4970 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
4971 gen_rtx (MULT, GET_MODE (index_rtx),
4972 index_rtx, scale_rtx),
4975 if (GET_CODE (offset_rtx) != CONST_INT
4976 || INTVAL (offset_rtx) != 0)
4977 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4978 ret_rtx, offset_rtx);
4982 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4983 index_rtx, base_rtx);
4985 if (GET_CODE (offset_rtx) != CONST_INT
4986 || INTVAL (offset_rtx) != 0)
4987 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4988 ret_rtx, offset_rtx);
4995 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx),
4996 index_rtx, scale_rtx);
4998 if (GET_CODE (offset_rtx) != CONST_INT
4999 || INTVAL (offset_rtx) != 0)
5000 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
5001 ret_rtx, offset_rtx);
5005 if (GET_CODE (offset_rtx) == CONST_INT
5006 && INTVAL (offset_rtx) == 0)
5007 ret_rtx = index_rtx;
5009 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
5010 index_rtx, offset_rtx);
5018 if (GET_CODE (offset_rtx) == CONST_INT
5019 && INTVAL (offset_rtx) == 0)
5022 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx,
5025 else if (was_only_offset)
5026 ret_rtx = offset_rtx;
5034 XEXP (mem_rtx, 0) = ret_rtx;
5035 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
5046 /* Return 1 if the first insn to set cc before INSN also sets the register
5047 REG_RTX; otherwise return 0. */
5049 last_to_set_cc (reg_rtx, insn)
5052 rtx prev_insn = PREV_INSN (insn);
5056 if (GET_CODE (prev_insn) == NOTE)
5059 else if (GET_CODE (prev_insn) == INSN)
5061 if (GET_CODE (PATTERN (prev_insn)) != SET)
5064 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
5066 if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
5072 else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
5079 prev_insn = PREV_INSN (prev_insn);
5086 doesnt_set_condition_code (pat)
5089 switch (GET_CODE (pat))
5102 sets_condition_code (pat)
5105 switch (GET_CODE (pat))
5127 str_immediate_operand (op, mode)
5129 enum machine_mode mode ATTRIBUTE_UNUSED;
5131 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
5141 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5142 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5143 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5144 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode))
5150 /* Return 1 if the mode of the SET_DEST of insn is floating point
5151 and it is not an fld or a move from memory to memory.
5152 Otherwise return 0 */
5158 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5159 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5160 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5161 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5162 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
5163 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
5164 && GET_CODE (SET_SRC (PATTERN (insn))) != MEM)
5170 /* Return 1 if the mode of the SET_DEST of INSN is floating point and is
5171 memory and the source is a register. */
5177 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5178 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5179 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5180 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5181 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
5182 && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
5188 /* Return 1 if DEP_INSN sets a register which INSN uses as a base
5189 or index to reference memory.
5190 otherwise return 0 */
5193 agi_dependent (insn, dep_insn)
5196 if (GET_CODE (dep_insn) == INSN
5197 && GET_CODE (PATTERN (dep_insn)) == SET
5198 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG)
5199 return reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn);
5201 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
5202 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
5203 && push_operand (SET_DEST (PATTERN (dep_insn)),
5204 GET_MODE (SET_DEST (PATTERN (dep_insn)))))
5205 return reg_mentioned_in_mem (stack_pointer_rtx, insn);
5210 /* Return 1 if reg is used in rtl as a base or index for a memory ref
5211 otherwise return 0. */
5214 reg_mentioned_in_mem (reg, rtl)
5219 register enum rtx_code code;
5224 code = GET_CODE (rtl);
5242 if (code == MEM && reg_mentioned_p (reg, rtl))
5245 fmt = GET_RTX_FORMAT (code);
5246 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5250 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
5251 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
5255 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
5262 /* Output the appropriate insns for doing strlen if not just doing repnz; scasb
5264 operands[0] = result, initialized with the startaddress
5265 operands[1] = alignment of the address.
5266 operands[2] = scratch register, initialized with the startaddress when
5267 not aligned, otherwise undefined
5269 This is just the body. It needs the initialisations mentioned above and
5270 some address computing at the end. These things are done in i386.md. */
5273 output_strlen_unroll (operands)
5278 xops[0] = operands[0]; /* Result */
5279 /* operands[1]; * Alignment */
5280 xops[1] = operands[2]; /* Scratch */
5281 xops[2] = GEN_INT (0);
5282 xops[3] = GEN_INT (2);
5283 xops[4] = GEN_INT (3);
5284 xops[5] = GEN_INT (4);
5285 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */
5286 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */
5287 xops[8] = gen_label_rtx (); /* label of main loop */
5289 if (TARGET_USE_Q_REG && QI_REG_P (xops[1]))
5290 xops[9] = gen_label_rtx (); /* pentium optimisation */
5292 xops[10] = gen_label_rtx (); /* end label 2 */
5293 xops[11] = gen_label_rtx (); /* end label 1 */
5294 xops[12] = gen_label_rtx (); /* end label */
5295 /* xops[13] * Temporary used */
5296 xops[14] = GEN_INT (0xff);
5297 xops[15] = GEN_INT (0xff00);
5298 xops[16] = GEN_INT (0xff0000);
5299 xops[17] = GEN_INT (0xff000000);
5301 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
5303 /* Is there a known alignment and is it less than 4? */
5304 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4)
5306 /* Is there a known alignment and is it not 2? */
5307 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5309 xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */
5310 xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */
5312 /* Leave just the 3 lower bits.
5313 If this is a q-register, then the high part is used later
5314 therefore use andl rather than andb. */
5315 output_asm_insn (AS2 (and%L1,%4,%1), xops);
5317 /* Is aligned to 4-byte address when zero */
5318 output_asm_insn (AS1 (je,%l8), xops);
5320 /* Side-effect even Parity when %eax == 3 */
5321 output_asm_insn (AS1 (jp,%6), xops);
5323 /* Is it aligned to 2 bytes ? */
5324 if (QI_REG_P (xops[1]))
5325 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5327 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5329 output_asm_insn (AS1 (je,%7), xops);
5333 /* Since the alignment is 2, we have to check 2 or 0 bytes;
5334 check if is aligned to 4 - byte. */
5335 output_asm_insn (AS2 (and%L1,%3,%1), xops);
5337 /* Is aligned to 4-byte address when zero */
5338 output_asm_insn (AS1 (je,%l8), xops);
5341 xops[13] = gen_rtx_MEM (QImode, xops[0]);
5343 /* Now compare the bytes; compare with the high part of a q-reg
5344 gives shorter code. */
5345 if (QI_REG_P (xops[1]))
5347 /* Compare the first n unaligned byte on a byte per byte basis. */
5348 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5350 /* When zero we reached the end. */
5351 output_asm_insn (AS1 (je,%l12), xops);
5353 /* Increment the address. */
5354 output_asm_insn (AS1 (inc%L0,%0), xops);
5356 /* Not needed with an alignment of 2 */
5357 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5359 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5360 CODE_LABEL_NUMBER (xops[7]));
5361 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5362 output_asm_insn (AS1 (je,%l12), xops);
5363 output_asm_insn (AS1 (inc%L0,%0), xops);
5365 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5366 CODE_LABEL_NUMBER (xops[6]));
5369 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5373 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5374 output_asm_insn (AS1 (je,%l12), xops);
5375 output_asm_insn (AS1 (inc%L0,%0), xops);
5377 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5378 CODE_LABEL_NUMBER (xops[7]));
5379 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5380 output_asm_insn (AS1 (je,%l12), xops);
5381 output_asm_insn (AS1 (inc%L0,%0), xops);
5383 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5384 CODE_LABEL_NUMBER (xops[6]));
5385 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5388 output_asm_insn (AS1 (je,%l12), xops);
5389 output_asm_insn (AS1 (inc%L0,%0), xops);
5392 /* Generate loop to check 4 bytes at a time. It is not a good idea to
5393 align this loop. It gives only huge programs, but does not help to
5395 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8]));
5397 xops[13] = gen_rtx_MEM (SImode, xops[0]);
5398 output_asm_insn (AS2 (mov%L1,%13,%1), xops);
5400 if (QI_REG_P (xops[1]))
5402 /* On i586 it is faster to combine the hi- and lo- part as
5403 a kind of lookahead. If anding both yields zero, then one
5404 of both *could* be zero, otherwise none of both is zero;
5405 this saves one instruction, on i486 this is slower
5406 tested with P-90, i486DX2-66, AMD486DX2-66 */
5409 output_asm_insn (AS2 (test%B1,%h1,%b1), xops);
5410 output_asm_insn (AS1 (jne,%l9), xops);
5413 /* Check first byte. */
5414 output_asm_insn (AS2 (test%B1,%b1,%b1), xops);
5415 output_asm_insn (AS1 (je,%l12), xops);
5417 /* Check second byte. */
5418 output_asm_insn (AS2 (test%B1,%h1,%h1), xops);
5419 output_asm_insn (AS1 (je,%l11), xops);
5422 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5423 CODE_LABEL_NUMBER (xops[9]));
5428 /* Check first byte. */
5429 output_asm_insn (AS2 (test%L1,%14,%1), xops);
5430 output_asm_insn (AS1 (je,%l12), xops);
5432 /* Check second byte. */
5433 output_asm_insn (AS2 (test%L1,%15,%1), xops);
5434 output_asm_insn (AS1 (je,%l11), xops);
5437 /* Check third byte. */
5438 output_asm_insn (AS2 (test%L1,%16,%1), xops);
5439 output_asm_insn (AS1 (je,%l10), xops);
5441 /* Check fourth byte and increment address. */
5442 output_asm_insn (AS2 (add%L0,%5,%0), xops);
5443 output_asm_insn (AS2 (test%L1,%17,%1), xops);
5444 output_asm_insn (AS1 (jne,%l8), xops);
5446 /* Now generate fixups when the compare stops within a 4-byte word. */
5447 output_asm_insn (AS2 (sub%L0,%4,%0), xops);
5449 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10]));
5450 output_asm_insn (AS1 (inc%L0,%0), xops);
5452 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11]));
5453 output_asm_insn (AS1 (inc%L0,%0), xops);
5455 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12]));
5461 output_fp_conditional_move (which_alternative, operands)
5462 int which_alternative;
5465 enum rtx_code code = GET_CODE (operands[1]);
5467 /* This should never happen. */
5468 if (!(cc_prev_status.flags & CC_IN_80387)
5469 && (code == GT || code == LE || code == GE || code == LT))
5472 switch (which_alternative)
5475 /* r <- cond ? arg : r */
5476 output_asm_insn (AS2 (fcmov%F1,%2,%0), operands);
5480 /* r <- cond ? r : arg */
5481 output_asm_insn (AS2 (fcmov%f1,%3,%0), operands);
5492 output_int_conditional_move (which_alternative, operands)
5493 int which_alternative;
5496 enum rtx_code code = GET_CODE (operands[1]);
5498 /* This is very tricky. We have to do it right. For a code segement
5507 final_scan_insn () may delete the insn which sets CC. We have to
5508 tell final_scan_insn () if it should be reinserted. When CODE is
5509 GT or LE, we have to check the CC_NO_OVERFLOW bit and return
5510 NULL_PTR to tell final to reinsert the test insn because the
5511 conditional move cannot be handled properly without it. */
5512 if ((code == GT || code == LE)
5513 && (cc_prev_status.flags & CC_NO_OVERFLOW))
5516 switch (which_alternative)
5519 /* r <- cond ? arg : r */
5520 output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
5524 /* r <- cond ? r : arg */
5525 output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
5536 x86_adjust_cost (insn, link, dep_insn, cost)
5537 rtx insn, link, dep_insn;
5542 if (GET_CODE (dep_insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
5545 if (GET_CODE (dep_insn) == INSN
5546 && GET_CODE (PATTERN (dep_insn)) == SET
5547 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
5548 && GET_CODE (insn) == INSN
5549 && GET_CODE (PATTERN (insn)) == SET
5550 && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
5551 SET_SRC (PATTERN (insn))))
5557 case PROCESSOR_PENTIUM:
5558 if (cost != 0 && is_fp_insn (insn) && is_fp_insn (dep_insn)
5559 && !is_fp_dest (dep_insn))
5562 if (agi_dependent (insn, dep_insn))
5565 if (GET_CODE (insn) == INSN
5566 && GET_CODE (PATTERN (insn)) == SET
5567 && SET_DEST (PATTERN (insn)) == cc0_rtx
5568 && (next_inst = next_nonnote_insn (insn))
5569 && GET_CODE (next_inst) == JUMP_INSN)
5570 /* compare probably paired with jump */
5576 if (!is_fp_dest (dep_insn))
5578 if(!agi_dependent (insn, dep_insn))
5584 if (is_fp_store (insn) && is_fp_insn (dep_insn)
5585 && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn))
5586 && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))
5587 && (GET_CODE (NEXT_INSN (insn)) == INSN)
5588 && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN)
5589 && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE)
5590 && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))))
5591 == NOTE_INSN_LOOP_END))