1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Define parameter passing and return registers. */
1623 static int const x86_64_int_parameter_registers[6] =
1625 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1628 static int const x86_64_ms_abi_int_parameter_registers[4] =
1630 CX_REG, DX_REG, R8_REG, R9_REG
1633 static int const x86_64_int_return_registers[4] =
1635 AX_REG, DX_REG, DI_REG, SI_REG
1638 /* Define the structure for the machine field in struct function. */
1640 struct stack_local_entry GTY(())
1642 unsigned short mode;
1645 struct stack_local_entry *next;
1648 /* Structure describing stack frame layout.
1649 Stack grows downward:
1655 saved frame pointer if frame_pointer_needed
1656 <- HARD_FRAME_POINTER
1665 [va_arg registers] (
1666 > to_allocate <- FRAME_POINTER
1678 HOST_WIDE_INT frame;
1680 int outgoing_arguments_size;
1683 HOST_WIDE_INT to_allocate;
1684 /* The offsets relative to ARG_POINTER. */
1685 HOST_WIDE_INT frame_pointer_offset;
1686 HOST_WIDE_INT hard_frame_pointer_offset;
1687 HOST_WIDE_INT stack_pointer_offset;
1689 /* When save_regs_using_mov is set, emit prologue using
1690 move instead of push instructions. */
1691 bool save_regs_using_mov;
1694 /* Code model option. */
1695 enum cmodel ix86_cmodel;
1697 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1699 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1701 /* Which unit we are generating floating point math for. */
1702 enum fpmath_unit ix86_fpmath;
1704 /* Which cpu are we scheduling for. */
1705 enum attr_cpu ix86_schedule;
1707 /* Which cpu are we optimizing for. */
1708 enum processor_type ix86_tune;
1710 /* Which instruction set architecture to use. */
1711 enum processor_type ix86_arch;
1713 /* true if sse prefetch instruction is not NOOP. */
1714 int x86_prefetch_sse;
1716 /* ix86_regparm_string as a number */
1717 static int ix86_regparm;
1719 /* -mstackrealign option */
1720 extern int ix86_force_align_arg_pointer;
1721 static const char ix86_force_align_arg_pointer_string[]
1722 = "force_align_arg_pointer";
1724 static rtx (*ix86_gen_leave) (void);
1725 static rtx (*ix86_gen_pop1) (rtx);
1726 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1728 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1729 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1730 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1731 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1733 /* Preferred alignment for stack boundary in bits. */
1734 unsigned int ix86_preferred_stack_boundary;
1736 /* Alignment for incoming stack boundary in bits specified at
1738 static unsigned int ix86_user_incoming_stack_boundary;
1740 /* Default alignment for incoming stack boundary in bits. */
1741 static unsigned int ix86_default_incoming_stack_boundary;
1743 /* Alignment for incoming stack boundary in bits. */
1744 unsigned int ix86_incoming_stack_boundary;
1746 /* The abi used by target. */
1747 enum calling_abi ix86_abi = DEFAULT_ABI;
1749 /* Values 1-5: see jump.c */
1750 int ix86_branch_cost;
1752 /* Calling abi specific va_list type nodes. */
1753 static GTY(()) tree sysv_va_list_type_node;
1754 static GTY(()) tree ms_va_list_type_node;
1756 /* Variables which are this size or smaller are put in the data/bss
1757 or ldata/lbss sections. */
1759 int ix86_section_threshold = 65536;
1761 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1762 char internal_label_prefix[16];
1763 int internal_label_prefix_len;
1765 /* Fence to use after loop using movnt. */
1768 /* Register class used for passing given 64bit part of the argument.
1769 These represent classes as documented by the PS ABI, with the exception
1770 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1771 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1773 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1774 whenever possible (upper half does contain padding). */
1775 enum x86_64_reg_class
1778 X86_64_INTEGER_CLASS,
1779 X86_64_INTEGERSI_CLASS,
1786 X86_64_COMPLEX_X87_CLASS,
1790 #define MAX_CLASSES 4
1792 /* Table of constants used by fldpi, fldln2, etc.... */
1793 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1794 static bool ext_80387_constants_init = 0;
1797 static struct machine_function * ix86_init_machine_status (void);
1798 static rtx ix86_function_value (const_tree, const_tree, bool);
1799 static int ix86_function_regparm (const_tree, const_tree);
1800 static void ix86_compute_frame_layout (struct ix86_frame *);
1801 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1803 static void ix86_add_new_builtins (int);
1805 enum ix86_function_specific_strings
1807 IX86_FUNCTION_SPECIFIC_ARCH,
1808 IX86_FUNCTION_SPECIFIC_TUNE,
1809 IX86_FUNCTION_SPECIFIC_FPMATH,
1810 IX86_FUNCTION_SPECIFIC_MAX
1813 static char *ix86_target_string (int, int, const char *, const char *,
1814 const char *, bool);
1815 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1816 static void ix86_function_specific_save (struct cl_target_option *);
1817 static void ix86_function_specific_restore (struct cl_target_option *);
1818 static void ix86_function_specific_print (FILE *, int,
1819 struct cl_target_option *);
1820 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1821 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1822 static bool ix86_can_inline_p (tree, tree);
1823 static void ix86_set_current_function (tree);
1825 static enum calling_abi ix86_function_abi (const_tree);
1828 /* The svr4 ABI for the i386 says that records and unions are returned
1830 #ifndef DEFAULT_PCC_STRUCT_RETURN
1831 #define DEFAULT_PCC_STRUCT_RETURN 1
1834 /* Whether -mtune= or -march= were specified */
1835 static int ix86_tune_defaulted;
1836 static int ix86_arch_specified;
1838 /* Bit flags that specify the ISA we are compiling for. */
1839 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1841 /* A mask of ix86_isa_flags that includes bit X if X
1842 was set or cleared on the command line. */
1843 static int ix86_isa_flags_explicit;
1845 /* Define a set of ISAs which are available when a given ISA is
1846 enabled. MMX and SSE ISAs are handled separately. */
1848 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1849 #define OPTION_MASK_ISA_3DNOW_SET \
1850 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1852 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1853 #define OPTION_MASK_ISA_SSE2_SET \
1854 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1855 #define OPTION_MASK_ISA_SSE3_SET \
1856 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1857 #define OPTION_MASK_ISA_SSSE3_SET \
1858 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1859 #define OPTION_MASK_ISA_SSE4_1_SET \
1860 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1861 #define OPTION_MASK_ISA_SSE4_2_SET \
1862 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1863 #define OPTION_MASK_ISA_AVX_SET \
1864 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1865 #define OPTION_MASK_ISA_FMA_SET \
1866 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1868 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1870 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1872 #define OPTION_MASK_ISA_SSE4A_SET \
1873 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1874 #define OPTION_MASK_ISA_SSE5_SET \
1875 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1877 /* AES and PCLMUL need SSE2 because they use xmm registers */
1878 #define OPTION_MASK_ISA_AES_SET \
1879 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1880 #define OPTION_MASK_ISA_PCLMUL_SET \
1881 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1883 #define OPTION_MASK_ISA_ABM_SET \
1884 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1885 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1886 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1887 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1889 /* Define a set of ISAs which aren't available when a given ISA is
1890 disabled. MMX and SSE ISAs are handled separately. */
1892 #define OPTION_MASK_ISA_MMX_UNSET \
1893 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1894 #define OPTION_MASK_ISA_3DNOW_UNSET \
1895 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1896 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1898 #define OPTION_MASK_ISA_SSE_UNSET \
1899 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1900 #define OPTION_MASK_ISA_SSE2_UNSET \
1901 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1902 #define OPTION_MASK_ISA_SSE3_UNSET \
1903 (OPTION_MASK_ISA_SSE3 \
1904 | OPTION_MASK_ISA_SSSE3_UNSET \
1905 | OPTION_MASK_ISA_SSE4A_UNSET )
1906 #define OPTION_MASK_ISA_SSSE3_UNSET \
1907 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1908 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1909 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1910 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1911 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1912 #define OPTION_MASK_ISA_AVX_UNSET \
1913 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1914 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1916 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1918 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1920 #define OPTION_MASK_ISA_SSE4A_UNSET \
1921 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1922 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1923 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1924 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1925 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1926 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1927 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1928 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1930 /* Vectorization library interface and handlers. */
1931 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1932 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1933 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1935 /* Processor target table, indexed by processor number */
1938 const struct processor_costs *cost; /* Processor costs */
1939 const int align_loop; /* Default alignments. */
1940 const int align_loop_max_skip;
1941 const int align_jump;
1942 const int align_jump_max_skip;
1943 const int align_func;
1946 static const struct ptt processor_target_table[PROCESSOR_max] =
1948 {&i386_cost, 4, 3, 4, 3, 4},
1949 {&i486_cost, 16, 15, 16, 15, 16},
1950 {&pentium_cost, 16, 7, 16, 7, 16},
1951 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1952 {&geode_cost, 0, 0, 0, 0, 0},
1953 {&k6_cost, 32, 7, 32, 7, 32},
1954 {&athlon_cost, 16, 7, 16, 7, 16},
1955 {&pentium4_cost, 0, 0, 0, 0, 0},
1956 {&k8_cost, 16, 7, 16, 7, 16},
1957 {&nocona_cost, 0, 0, 0, 0, 0},
1958 {&core2_cost, 16, 10, 16, 10, 16},
1959 {&generic32_cost, 16, 7, 16, 7, 16},
1960 {&generic64_cost, 16, 10, 16, 10, 16},
1961 {&amdfam10_cost, 32, 24, 32, 7, 32}
1964 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1989 /* Implement TARGET_HANDLE_OPTION. */
1992 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1999 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2004 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2005 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2012 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2017 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2018 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2028 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2033 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2034 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2041 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2046 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2047 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2054 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2059 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2060 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2067 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2072 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2073 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2080 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2085 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2086 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2093 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2098 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2099 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2106 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2111 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2112 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2119 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2124 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2130 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2135 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2136 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2142 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2147 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2148 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2155 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2160 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2161 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2168 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2173 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2174 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2181 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2186 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2187 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2194 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2199 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2200 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2207 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2212 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2213 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2220 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2225 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2226 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2233 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2238 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2239 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2248 /* Return a string the documents the current -m options. The caller is
2249 responsible for freeing the string. */
2252 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2253 const char *fpmath, bool add_nl_p)
2255 struct ix86_target_opts
2257 const char *option; /* option string */
2258 int mask; /* isa mask options */
2261 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2262 preceding options while match those first. */
2263 static struct ix86_target_opts isa_opts[] =
2265 { "-m64", OPTION_MASK_ISA_64BIT },
2266 { "-msse5", OPTION_MASK_ISA_SSE5 },
2267 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2268 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2269 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2270 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2271 { "-msse3", OPTION_MASK_ISA_SSE3 },
2272 { "-msse2", OPTION_MASK_ISA_SSE2 },
2273 { "-msse", OPTION_MASK_ISA_SSE },
2274 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2275 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2276 { "-mmmx", OPTION_MASK_ISA_MMX },
2277 { "-mabm", OPTION_MASK_ISA_ABM },
2278 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2279 { "-maes", OPTION_MASK_ISA_AES },
2280 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2284 static struct ix86_target_opts flag_opts[] =
2286 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2287 { "-m80387", MASK_80387 },
2288 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2289 { "-malign-double", MASK_ALIGN_DOUBLE },
2290 { "-mcld", MASK_CLD },
2291 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2292 { "-mieee-fp", MASK_IEEE_FP },
2293 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2294 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2295 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2296 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2297 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2298 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2299 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2300 { "-mno-red-zone", MASK_NO_RED_ZONE },
2301 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2302 { "-mrecip", MASK_RECIP },
2303 { "-mrtd", MASK_RTD },
2304 { "-msseregparm", MASK_SSEREGPARM },
2305 { "-mstack-arg-probe", MASK_STACK_PROBE },
2306 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2309 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2312 char target_other[40];
2321 memset (opts, '\0', sizeof (opts));
2323 /* Add -march= option. */
2326 opts[num][0] = "-march=";
2327 opts[num++][1] = arch;
2330 /* Add -mtune= option. */
2333 opts[num][0] = "-mtune=";
2334 opts[num++][1] = tune;
2337 /* Pick out the options in isa options. */
2338 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2340 if ((isa & isa_opts[i].mask) != 0)
2342 opts[num++][0] = isa_opts[i].option;
2343 isa &= ~ isa_opts[i].mask;
2347 if (isa && add_nl_p)
2349 opts[num++][0] = isa_other;
2350 sprintf (isa_other, "(other isa: 0x%x)", isa);
2353 /* Add flag options. */
2354 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2356 if ((flags & flag_opts[i].mask) != 0)
2358 opts[num++][0] = flag_opts[i].option;
2359 flags &= ~ flag_opts[i].mask;
2363 if (flags && add_nl_p)
2365 opts[num++][0] = target_other;
2366 sprintf (target_other, "(other flags: 0x%x)", isa);
2369 /* Add -fpmath= option. */
2372 opts[num][0] = "-mfpmath=";
2373 opts[num++][1] = fpmath;
2380 gcc_assert (num < ARRAY_SIZE (opts));
2382 /* Size the string. */
2384 sep_len = (add_nl_p) ? 3 : 1;
2385 for (i = 0; i < num; i++)
2388 for (j = 0; j < 2; j++)
2390 len += strlen (opts[i][j]);
2393 /* Build the string. */
2394 ret = ptr = (char *) xmalloc (len);
2397 for (i = 0; i < num; i++)
2401 for (j = 0; j < 2; j++)
2402 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2409 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2417 for (j = 0; j < 2; j++)
2420 memcpy (ptr, opts[i][j], len2[j]);
2422 line_len += len2[j];
2427 gcc_assert (ret + len >= ptr);
2432 /* Function that is callable from the debugger to print the current
2435 ix86_debug_options (void)
2437 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2438 ix86_arch_string, ix86_tune_string,
2439 ix86_fpmath_string, true);
2443 fprintf (stderr, "%s\n\n", opts);
2447 fprintf (stderr, "<no options>\n\n");
2452 /* Sometimes certain combinations of command options do not make
2453 sense on a particular target machine. You can define a macro
2454 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2455 defined, is executed once just after all the command options have
2458 Don't use this macro to turn on various extra optimizations for
2459 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2462 override_options (bool main_args_p)
2465 unsigned int ix86_arch_mask, ix86_tune_mask;
2470 /* Comes from final.c -- no real reason to change it. */
2471 #define MAX_CODE_ALIGN 16
2479 PTA_PREFETCH_SSE = 1 << 4,
2481 PTA_3DNOW_A = 1 << 6,
2485 PTA_POPCNT = 1 << 10,
2487 PTA_SSE4A = 1 << 12,
2488 PTA_NO_SAHF = 1 << 13,
2489 PTA_SSE4_1 = 1 << 14,
2490 PTA_SSE4_2 = 1 << 15,
2493 PTA_PCLMUL = 1 << 18,
2500 const char *const name; /* processor name or nickname. */
2501 const enum processor_type processor;
2502 const enum attr_cpu schedule;
2503 const unsigned /*enum pta_flags*/ flags;
2505 const processor_alias_table[] =
2507 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2508 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2509 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2510 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2511 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2512 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2513 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2514 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2515 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2516 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2517 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2518 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2519 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2521 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2523 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2524 PTA_MMX | PTA_SSE | PTA_SSE2},
2525 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2526 PTA_MMX |PTA_SSE | PTA_SSE2},
2527 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2528 PTA_MMX | PTA_SSE | PTA_SSE2},
2529 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2530 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2531 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2532 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2533 | PTA_CX16 | PTA_NO_SAHF},
2534 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2535 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2536 | PTA_SSSE3 | PTA_CX16},
2537 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2538 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2539 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2540 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2541 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2542 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2543 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2544 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2545 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2546 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2547 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2548 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2549 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2550 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2551 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2552 {"x86-64", PROCESSOR_K8, CPU_K8,
2553 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2554 {"k8", PROCESSOR_K8, CPU_K8,
2555 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2556 | PTA_SSE2 | PTA_NO_SAHF},
2557 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2558 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2559 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2560 {"opteron", PROCESSOR_K8, CPU_K8,
2561 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2562 | PTA_SSE2 | PTA_NO_SAHF},
2563 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2564 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2565 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2566 {"athlon64", PROCESSOR_K8, CPU_K8,
2567 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2568 | PTA_SSE2 | PTA_NO_SAHF},
2569 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2570 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2571 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2572 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2573 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2574 | PTA_SSE2 | PTA_NO_SAHF},
2575 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2576 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2577 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2578 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2579 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2580 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2581 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2582 0 /* flags are only used for -march switch. */ },
2583 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2584 PTA_64BIT /* flags are only used for -march switch. */ },
2587 int const pta_size = ARRAY_SIZE (processor_alias_table);
2589 /* Set up prefix/suffix so the error messages refer to either the command
2590 line argument, or the attribute(target). */
2599 prefix = "option(\"";
2604 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2605 SUBTARGET_OVERRIDE_OPTIONS;
2608 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2609 SUBSUBTARGET_OVERRIDE_OPTIONS;
2612 /* -fPIC is the default for x86_64. */
2613 if (TARGET_MACHO && TARGET_64BIT)
2616 /* Set the default values for switches whose default depends on TARGET_64BIT
2617 in case they weren't overwritten by command line options. */
2620 /* Mach-O doesn't support omitting the frame pointer for now. */
2621 if (flag_omit_frame_pointer == 2)
2622 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2623 if (flag_asynchronous_unwind_tables == 2)
2624 flag_asynchronous_unwind_tables = 1;
2625 if (flag_pcc_struct_return == 2)
2626 flag_pcc_struct_return = 0;
2630 if (flag_omit_frame_pointer == 2)
2631 flag_omit_frame_pointer = 0;
2632 if (flag_asynchronous_unwind_tables == 2)
2633 flag_asynchronous_unwind_tables = 0;
2634 if (flag_pcc_struct_return == 2)
2635 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2638 /* Need to check -mtune=generic first. */
2639 if (ix86_tune_string)
2641 if (!strcmp (ix86_tune_string, "generic")
2642 || !strcmp (ix86_tune_string, "i686")
2643 /* As special support for cross compilers we read -mtune=native
2644 as -mtune=generic. With native compilers we won't see the
2645 -mtune=native, as it was changed by the driver. */
2646 || !strcmp (ix86_tune_string, "native"))
2649 ix86_tune_string = "generic64";
2651 ix86_tune_string = "generic32";
2653 /* If this call is for setting the option attribute, allow the
2654 generic32/generic64 that was previously set. */
2655 else if (!main_args_p
2656 && (!strcmp (ix86_tune_string, "generic32")
2657 || !strcmp (ix86_tune_string, "generic64")))
2659 else if (!strncmp (ix86_tune_string, "generic", 7))
2660 error ("bad value (%s) for %stune=%s %s",
2661 ix86_tune_string, prefix, suffix, sw);
2665 if (ix86_arch_string)
2666 ix86_tune_string = ix86_arch_string;
2667 if (!ix86_tune_string)
2669 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2670 ix86_tune_defaulted = 1;
2673 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2674 need to use a sensible tune option. */
2675 if (!strcmp (ix86_tune_string, "generic")
2676 || !strcmp (ix86_tune_string, "x86-64")
2677 || !strcmp (ix86_tune_string, "i686"))
2680 ix86_tune_string = "generic64";
2682 ix86_tune_string = "generic32";
2685 if (ix86_stringop_string)
2687 if (!strcmp (ix86_stringop_string, "rep_byte"))
2688 stringop_alg = rep_prefix_1_byte;
2689 else if (!strcmp (ix86_stringop_string, "libcall"))
2690 stringop_alg = libcall;
2691 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2692 stringop_alg = rep_prefix_4_byte;
2693 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2695 /* rep; movq isn't available in 32-bit code. */
2696 stringop_alg = rep_prefix_8_byte;
2697 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2698 stringop_alg = loop_1_byte;
2699 else if (!strcmp (ix86_stringop_string, "loop"))
2700 stringop_alg = loop;
2701 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2702 stringop_alg = unrolled_loop;
2704 error ("bad value (%s) for %sstringop-strategy=%s %s",
2705 ix86_stringop_string, prefix, suffix, sw);
2707 if (!strcmp (ix86_tune_string, "x86-64"))
2708 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2709 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2710 prefix, suffix, prefix, suffix, prefix, suffix);
2712 if (!ix86_arch_string)
2713 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2715 ix86_arch_specified = 1;
2717 if (!strcmp (ix86_arch_string, "generic"))
2718 error ("generic CPU can be used only for %stune=%s %s",
2719 prefix, suffix, sw);
2720 if (!strncmp (ix86_arch_string, "generic", 7))
2721 error ("bad value (%s) for %sarch=%s %s",
2722 ix86_arch_string, prefix, suffix, sw);
2724 /* Validate -mabi= value. */
2725 if (ix86_abi_string)
2727 if (strcmp (ix86_abi_string, "sysv") == 0)
2728 ix86_abi = SYSV_ABI;
2729 else if (strcmp (ix86_abi_string, "ms") == 0)
2732 error ("unknown ABI (%s) for %sabi=%s %s",
2733 ix86_abi_string, prefix, suffix, sw);
2736 if (ix86_cmodel_string != 0)
2738 if (!strcmp (ix86_cmodel_string, "small"))
2739 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2740 else if (!strcmp (ix86_cmodel_string, "medium"))
2741 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2742 else if (!strcmp (ix86_cmodel_string, "large"))
2743 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2745 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2746 else if (!strcmp (ix86_cmodel_string, "32"))
2747 ix86_cmodel = CM_32;
2748 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2749 ix86_cmodel = CM_KERNEL;
2751 error ("bad value (%s) for %scmodel=%s %s",
2752 ix86_cmodel_string, prefix, suffix, sw);
2756 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2757 use of rip-relative addressing. This eliminates fixups that
2758 would otherwise be needed if this object is to be placed in a
2759 DLL, and is essentially just as efficient as direct addressing. */
2760 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2761 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2762 else if (TARGET_64BIT)
2763 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2765 ix86_cmodel = CM_32;
2767 if (ix86_asm_string != 0)
2770 && !strcmp (ix86_asm_string, "intel"))
2771 ix86_asm_dialect = ASM_INTEL;
2772 else if (!strcmp (ix86_asm_string, "att"))
2773 ix86_asm_dialect = ASM_ATT;
2775 error ("bad value (%s) for %sasm=%s %s",
2776 ix86_asm_string, prefix, suffix, sw);
2778 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2779 error ("code model %qs not supported in the %s bit mode",
2780 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2781 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2782 sorry ("%i-bit mode not compiled in",
2783 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2785 for (i = 0; i < pta_size; i++)
2786 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2788 ix86_schedule = processor_alias_table[i].schedule;
2789 ix86_arch = processor_alias_table[i].processor;
2790 /* Default cpu tuning to the architecture. */
2791 ix86_tune = ix86_arch;
2793 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2794 error ("CPU you selected does not support x86-64 "
2797 if (processor_alias_table[i].flags & PTA_MMX
2798 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2799 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2800 if (processor_alias_table[i].flags & PTA_3DNOW
2801 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2802 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2803 if (processor_alias_table[i].flags & PTA_3DNOW_A
2804 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2805 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2806 if (processor_alias_table[i].flags & PTA_SSE
2807 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2808 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2809 if (processor_alias_table[i].flags & PTA_SSE2
2810 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2811 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2812 if (processor_alias_table[i].flags & PTA_SSE3
2813 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2814 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2815 if (processor_alias_table[i].flags & PTA_SSSE3
2816 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2817 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2818 if (processor_alias_table[i].flags & PTA_SSE4_1
2819 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2820 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2821 if (processor_alias_table[i].flags & PTA_SSE4_2
2822 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2823 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2824 if (processor_alias_table[i].flags & PTA_AVX
2825 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2826 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2827 if (processor_alias_table[i].flags & PTA_FMA
2828 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2829 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2830 if (processor_alias_table[i].flags & PTA_SSE4A
2831 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2832 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2833 if (processor_alias_table[i].flags & PTA_SSE5
2834 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2835 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2836 if (processor_alias_table[i].flags & PTA_ABM
2837 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2838 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2839 if (processor_alias_table[i].flags & PTA_CX16
2840 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2841 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2842 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2843 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2844 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2845 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2846 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2847 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2848 if (processor_alias_table[i].flags & PTA_AES
2849 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2850 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2851 if (processor_alias_table[i].flags & PTA_PCLMUL
2852 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2853 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2854 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2855 x86_prefetch_sse = true;
2861 error ("bad value (%s) for %sarch=%s %s",
2862 ix86_arch_string, prefix, suffix, sw);
2864 ix86_arch_mask = 1u << ix86_arch;
2865 for (i = 0; i < X86_ARCH_LAST; ++i)
2866 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2868 for (i = 0; i < pta_size; i++)
2869 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2871 ix86_schedule = processor_alias_table[i].schedule;
2872 ix86_tune = processor_alias_table[i].processor;
2873 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2875 if (ix86_tune_defaulted)
2877 ix86_tune_string = "x86-64";
2878 for (i = 0; i < pta_size; i++)
2879 if (! strcmp (ix86_tune_string,
2880 processor_alias_table[i].name))
2882 ix86_schedule = processor_alias_table[i].schedule;
2883 ix86_tune = processor_alias_table[i].processor;
2886 error ("CPU you selected does not support x86-64 "
2889 /* Intel CPUs have always interpreted SSE prefetch instructions as
2890 NOPs; so, we can enable SSE prefetch instructions even when
2891 -mtune (rather than -march) points us to a processor that has them.
2892 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2893 higher processors. */
2895 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2896 x86_prefetch_sse = true;
2900 error ("bad value (%s) for %stune=%s %s",
2901 ix86_tune_string, prefix, suffix, sw);
2903 ix86_tune_mask = 1u << ix86_tune;
2904 for (i = 0; i < X86_TUNE_LAST; ++i)
2905 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2908 ix86_cost = &ix86_size_cost;
2910 ix86_cost = processor_target_table[ix86_tune].cost;
2912 /* Arrange to set up i386_stack_locals for all functions. */
2913 init_machine_status = ix86_init_machine_status;
2915 /* Validate -mregparm= value. */
2916 if (ix86_regparm_string)
2919 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2920 i = atoi (ix86_regparm_string);
2921 if (i < 0 || i > REGPARM_MAX)
2922 error ("%sregparm=%d%s is not between 0 and %d",
2923 prefix, i, suffix, REGPARM_MAX);
2928 ix86_regparm = REGPARM_MAX;
2930 /* If the user has provided any of the -malign-* options,
2931 warn and use that value only if -falign-* is not set.
2932 Remove this code in GCC 3.2 or later. */
2933 if (ix86_align_loops_string)
2935 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2936 prefix, suffix, suffix);
2937 if (align_loops == 0)
2939 i = atoi (ix86_align_loops_string);
2940 if (i < 0 || i > MAX_CODE_ALIGN)
2941 error ("%salign-loops=%d%s is not between 0 and %d",
2942 prefix, i, suffix, MAX_CODE_ALIGN);
2944 align_loops = 1 << i;
2948 if (ix86_align_jumps_string)
2950 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2951 prefix, suffix, suffix);
2952 if (align_jumps == 0)
2954 i = atoi (ix86_align_jumps_string);
2955 if (i < 0 || i > MAX_CODE_ALIGN)
2956 error ("%salign-loops=%d%s is not between 0 and %d",
2957 prefix, i, suffix, MAX_CODE_ALIGN);
2959 align_jumps = 1 << i;
2963 if (ix86_align_funcs_string)
2965 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2966 prefix, suffix, suffix);
2967 if (align_functions == 0)
2969 i = atoi (ix86_align_funcs_string);
2970 if (i < 0 || i > MAX_CODE_ALIGN)
2971 error ("%salign-loops=%d%s is not between 0 and %d",
2972 prefix, i, suffix, MAX_CODE_ALIGN);
2974 align_functions = 1 << i;
2978 /* Default align_* from the processor table. */
2979 if (align_loops == 0)
2981 align_loops = processor_target_table[ix86_tune].align_loop;
2982 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2984 if (align_jumps == 0)
2986 align_jumps = processor_target_table[ix86_tune].align_jump;
2987 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2989 if (align_functions == 0)
2991 align_functions = processor_target_table[ix86_tune].align_func;
2994 /* Validate -mbranch-cost= value, or provide default. */
2995 ix86_branch_cost = ix86_cost->branch_cost;
2996 if (ix86_branch_cost_string)
2998 i = atoi (ix86_branch_cost_string);
3000 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3002 ix86_branch_cost = i;
3004 if (ix86_section_threshold_string)
3006 i = atoi (ix86_section_threshold_string);
3008 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3010 ix86_section_threshold = i;
3013 if (ix86_tls_dialect_string)
3015 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3016 ix86_tls_dialect = TLS_DIALECT_GNU;
3017 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3018 ix86_tls_dialect = TLS_DIALECT_GNU2;
3019 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3020 ix86_tls_dialect = TLS_DIALECT_SUN;
3022 error ("bad value (%s) for %stls-dialect=%s %s",
3023 ix86_tls_dialect_string, prefix, suffix, sw);
3026 if (ix87_precision_string)
3028 i = atoi (ix87_precision_string);
3029 if (i != 32 && i != 64 && i != 80)
3030 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3035 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3037 /* Enable by default the SSE and MMX builtins. Do allow the user to
3038 explicitly disable any of these. In particular, disabling SSE and
3039 MMX for kernel code is extremely useful. */
3040 if (!ix86_arch_specified)
3042 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3043 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3046 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3050 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3052 if (!ix86_arch_specified)
3054 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3056 /* i386 ABI does not specify red zone. It still makes sense to use it
3057 when programmer takes care to stack from being destroyed. */
3058 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3059 target_flags |= MASK_NO_RED_ZONE;
3062 /* Keep nonleaf frame pointers. */
3063 if (flag_omit_frame_pointer)
3064 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3065 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3066 flag_omit_frame_pointer = 1;
3068 /* If we're doing fast math, we don't care about comparison order
3069 wrt NaNs. This lets us use a shorter comparison sequence. */
3070 if (flag_finite_math_only)
3071 target_flags &= ~MASK_IEEE_FP;
3073 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3074 since the insns won't need emulation. */
3075 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3076 target_flags &= ~MASK_NO_FANCY_MATH_387;
3078 /* Likewise, if the target doesn't have a 387, or we've specified
3079 software floating point, don't use 387 inline intrinsics. */
3081 target_flags |= MASK_NO_FANCY_MATH_387;
3083 /* Turn on MMX builtins for -msse. */
3086 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3087 x86_prefetch_sse = true;
3090 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3091 if (TARGET_SSE4_2 || TARGET_ABM)
3092 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3094 /* Validate -mpreferred-stack-boundary= value or default it to
3095 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3096 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3097 if (ix86_preferred_stack_boundary_string)
3099 i = atoi (ix86_preferred_stack_boundary_string);
3100 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3101 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3102 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3104 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3107 /* Set the default value for -mstackrealign. */
3108 if (ix86_force_align_arg_pointer == -1)
3109 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3111 /* Validate -mincoming-stack-boundary= value or default it to
3112 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3113 if (ix86_force_align_arg_pointer)
3114 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3116 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3117 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3118 if (ix86_incoming_stack_boundary_string)
3120 i = atoi (ix86_incoming_stack_boundary_string);
3121 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3122 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3123 i, TARGET_64BIT ? 4 : 2);
3126 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3127 ix86_incoming_stack_boundary
3128 = ix86_user_incoming_stack_boundary;
3132 /* Accept -msseregparm only if at least SSE support is enabled. */
3133 if (TARGET_SSEREGPARM
3135 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3137 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3138 if (ix86_fpmath_string != 0)
3140 if (! strcmp (ix86_fpmath_string, "387"))
3141 ix86_fpmath = FPMATH_387;
3142 else if (! strcmp (ix86_fpmath_string, "sse"))
3146 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3147 ix86_fpmath = FPMATH_387;
3150 ix86_fpmath = FPMATH_SSE;
3152 else if (! strcmp (ix86_fpmath_string, "387,sse")
3153 || ! strcmp (ix86_fpmath_string, "387+sse")
3154 || ! strcmp (ix86_fpmath_string, "sse,387")
3155 || ! strcmp (ix86_fpmath_string, "sse+387")
3156 || ! strcmp (ix86_fpmath_string, "both"))
3160 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3161 ix86_fpmath = FPMATH_387;
3163 else if (!TARGET_80387)
3165 warning (0, "387 instruction set disabled, using SSE arithmetics");
3166 ix86_fpmath = FPMATH_SSE;
3169 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3172 error ("bad value (%s) for %sfpmath=%s %s",
3173 ix86_fpmath_string, prefix, suffix, sw);
3176 /* If the i387 is disabled, then do not return values in it. */
3178 target_flags &= ~MASK_FLOAT_RETURNS;
3180 /* Use external vectorized library in vectorizing intrinsics. */
3181 if (ix86_veclibabi_string)
3183 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3184 ix86_veclib_handler = ix86_veclibabi_svml;
3185 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3186 ix86_veclib_handler = ix86_veclibabi_acml;
3188 error ("unknown vectorization library ABI type (%s) for "
3189 "%sveclibabi=%s %s", ix86_veclibabi_string,
3190 prefix, suffix, sw);
3193 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3194 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3196 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3198 /* ??? Unwind info is not correct around the CFG unless either a frame
3199 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3200 unwind info generation to be aware of the CFG and propagating states
3202 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3203 || flag_exceptions || flag_non_call_exceptions)
3204 && flag_omit_frame_pointer
3205 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3207 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3208 warning (0, "unwind tables currently require either a frame pointer "
3209 "or %saccumulate-outgoing-args%s for correctness",
3211 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3214 /* If stack probes are required, the space used for large function
3215 arguments on the stack must also be probed, so enable
3216 -maccumulate-outgoing-args so this happens in the prologue. */
3217 if (TARGET_STACK_PROBE
3218 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3220 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3221 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3222 "for correctness", prefix, suffix);
3223 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3226 /* For sane SSE instruction set generation we need fcomi instruction.
3227 It is safe to enable all CMOVE instructions. */
3231 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3234 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3235 p = strchr (internal_label_prefix, 'X');
3236 internal_label_prefix_len = p - internal_label_prefix;
3240 /* When scheduling description is not available, disable scheduler pass
3241 so it won't slow down the compilation and make x87 code slower. */
3242 if (!TARGET_SCHEDULE)
3243 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3245 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3246 set_param_value ("simultaneous-prefetches",
3247 ix86_cost->simultaneous_prefetches);
3248 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3249 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3250 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3251 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3252 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3253 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3255 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3256 can be optimized to ap = __builtin_next_arg (0). */
3258 targetm.expand_builtin_va_start = NULL;
3262 ix86_gen_leave = gen_leave_rex64;
3263 ix86_gen_pop1 = gen_popdi1;
3264 ix86_gen_add3 = gen_adddi3;
3265 ix86_gen_sub3 = gen_subdi3;
3266 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3267 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3268 ix86_gen_monitor = gen_sse3_monitor64;
3269 ix86_gen_andsp = gen_anddi3;
3273 ix86_gen_leave = gen_leave;
3274 ix86_gen_pop1 = gen_popsi1;
3275 ix86_gen_add3 = gen_addsi3;
3276 ix86_gen_sub3 = gen_subsi3;
3277 ix86_gen_sub3_carry = gen_subsi3_carry;
3278 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3279 ix86_gen_monitor = gen_sse3_monitor;
3280 ix86_gen_andsp = gen_andsi3;
3284 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3286 target_flags |= MASK_CLD & ~target_flags_explicit;
3289 /* Save the initial options in case the user does function specific options */
3291 target_option_default_node = target_option_current_node
3292 = build_target_option_node ();
3295 /* Save the current options */
3298 ix86_function_specific_save (struct cl_target_option *ptr)
3300 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3301 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3302 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3303 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3304 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3306 ptr->arch = ix86_arch;
3307 ptr->schedule = ix86_schedule;
3308 ptr->tune = ix86_tune;
3309 ptr->fpmath = ix86_fpmath;
3310 ptr->branch_cost = ix86_branch_cost;
3311 ptr->tune_defaulted = ix86_tune_defaulted;
3312 ptr->arch_specified = ix86_arch_specified;
3313 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3314 ptr->target_flags_explicit = target_flags_explicit;
3317 /* Restore the current options */
3320 ix86_function_specific_restore (struct cl_target_option *ptr)
3322 enum processor_type old_tune = ix86_tune;
3323 enum processor_type old_arch = ix86_arch;
3324 unsigned int ix86_arch_mask, ix86_tune_mask;
3327 ix86_arch = ptr->arch;
3328 ix86_schedule = ptr->schedule;
3329 ix86_tune = ptr->tune;
3330 ix86_fpmath = ptr->fpmath;
3331 ix86_branch_cost = ptr->branch_cost;
3332 ix86_tune_defaulted = ptr->tune_defaulted;
3333 ix86_arch_specified = ptr->arch_specified;
3334 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3335 target_flags_explicit = ptr->target_flags_explicit;
3337 /* Recreate the arch feature tests if the arch changed */
3338 if (old_arch != ix86_arch)
3340 ix86_arch_mask = 1u << ix86_arch;
3341 for (i = 0; i < X86_ARCH_LAST; ++i)
3342 ix86_arch_features[i]
3343 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3346 /* Recreate the tune optimization tests */
3347 if (old_tune != ix86_tune)
3349 ix86_tune_mask = 1u << ix86_tune;
3350 for (i = 0; i < X86_TUNE_LAST; ++i)
3351 ix86_tune_features[i]
3352 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3356 /* Print the current options */
3359 ix86_function_specific_print (FILE *file, int indent,
3360 struct cl_target_option *ptr)
3363 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3364 NULL, NULL, NULL, false);
3366 fprintf (file, "%*sarch = %d (%s)\n",
3369 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3370 ? cpu_names[ptr->arch]
3373 fprintf (file, "%*stune = %d (%s)\n",
3376 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3377 ? cpu_names[ptr->tune]
3380 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3381 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3382 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3383 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3387 fprintf (file, "%*s%s\n", indent, "", target_string);
3388 free (target_string);
3393 /* Inner function to process the attribute((target(...))), take an argument and
3394 set the current options from the argument. If we have a list, recursively go
3398 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3403 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3404 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3405 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3406 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3421 enum ix86_opt_type type;
3426 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3427 IX86_ATTR_ISA ("abm", OPT_mabm),
3428 IX86_ATTR_ISA ("aes", OPT_maes),
3429 IX86_ATTR_ISA ("avx", OPT_mavx),
3430 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3431 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3432 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3433 IX86_ATTR_ISA ("sse", OPT_msse),
3434 IX86_ATTR_ISA ("sse2", OPT_msse2),
3435 IX86_ATTR_ISA ("sse3", OPT_msse3),
3436 IX86_ATTR_ISA ("sse4", OPT_msse4),
3437 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3438 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3439 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3440 IX86_ATTR_ISA ("sse5", OPT_msse5),
3441 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3443 /* string options */
3444 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3445 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3446 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3449 IX86_ATTR_YES ("cld",
3453 IX86_ATTR_NO ("fancy-math-387",
3454 OPT_mfancy_math_387,
3455 MASK_NO_FANCY_MATH_387),
3457 IX86_ATTR_NO ("fused-madd",
3459 MASK_NO_FUSED_MADD),
3461 IX86_ATTR_YES ("ieee-fp",
3465 IX86_ATTR_YES ("inline-all-stringops",
3466 OPT_minline_all_stringops,
3467 MASK_INLINE_ALL_STRINGOPS),
3469 IX86_ATTR_YES ("inline-stringops-dynamically",
3470 OPT_minline_stringops_dynamically,
3471 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3473 IX86_ATTR_NO ("align-stringops",
3474 OPT_mno_align_stringops,
3475 MASK_NO_ALIGN_STRINGOPS),
3477 IX86_ATTR_YES ("recip",
3483 /* If this is a list, recurse to get the options. */
3484 if (TREE_CODE (args) == TREE_LIST)
3488 for (; args; args = TREE_CHAIN (args))
3489 if (TREE_VALUE (args)
3490 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3496 else if (TREE_CODE (args) != STRING_CST)
3499 /* Handle multiple arguments separated by commas. */
3500 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3502 while (next_optstr && *next_optstr != '\0')
3504 char *p = next_optstr;
3506 char *comma = strchr (next_optstr, ',');
3507 const char *opt_string;
3508 size_t len, opt_len;
3513 enum ix86_opt_type type = ix86_opt_unknown;
3519 len = comma - next_optstr;
3520 next_optstr = comma + 1;
3528 /* Recognize no-xxx. */
3529 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3538 /* Find the option. */
3541 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3543 type = attrs[i].type;
3544 opt_len = attrs[i].len;
3545 if (ch == attrs[i].string[0]
3546 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3547 && memcmp (p, attrs[i].string, opt_len) == 0)
3550 mask = attrs[i].mask;
3551 opt_string = attrs[i].string;
3556 /* Process the option. */
3559 error ("attribute(target(\"%s\")) is unknown", orig_p);
3563 else if (type == ix86_opt_isa)
3564 ix86_handle_option (opt, p, opt_set_p);
3566 else if (type == ix86_opt_yes || type == ix86_opt_no)
3568 if (type == ix86_opt_no)
3569 opt_set_p = !opt_set_p;
3572 target_flags |= mask;
3574 target_flags &= ~mask;
3577 else if (type == ix86_opt_str)
3581 error ("option(\"%s\") was already specified", opt_string);
3585 p_strings[opt] = xstrdup (p + opt_len);
3595 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3598 ix86_valid_target_attribute_tree (tree args)
3600 const char *orig_arch_string = ix86_arch_string;
3601 const char *orig_tune_string = ix86_tune_string;
3602 const char *orig_fpmath_string = ix86_fpmath_string;
3603 int orig_tune_defaulted = ix86_tune_defaulted;
3604 int orig_arch_specified = ix86_arch_specified;
3605 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3608 struct cl_target_option *def
3609 = TREE_TARGET_OPTION (target_option_default_node);
3611 /* Process each of the options on the chain. */
3612 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3615 /* If the changed options are different from the default, rerun override_options,
3616 and then save the options away. The string options are are attribute options,
3617 and will be undone when we copy the save structure. */
3618 if (ix86_isa_flags != def->ix86_isa_flags
3619 || target_flags != def->target_flags
3620 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3621 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3622 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3624 /* If we are using the default tune= or arch=, undo the string assigned,
3625 and use the default. */
3626 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3627 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3628 else if (!orig_arch_specified)
3629 ix86_arch_string = NULL;
3631 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3632 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3633 else if (orig_tune_defaulted)
3634 ix86_tune_string = NULL;
3636 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3637 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3638 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3639 else if (!TARGET_64BIT && TARGET_SSE)
3640 ix86_fpmath_string = "sse,387";
3642 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3643 override_options (false);
3645 /* Add any builtin functions with the new isa if any. */
3646 ix86_add_new_builtins (ix86_isa_flags);
3648 /* Save the current options unless we are validating options for
3650 t = build_target_option_node ();
3652 ix86_arch_string = orig_arch_string;
3653 ix86_tune_string = orig_tune_string;
3654 ix86_fpmath_string = orig_fpmath_string;
3656 /* Free up memory allocated to hold the strings */
3657 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3658 if (option_strings[i])
3659 free (option_strings[i]);
3665 /* Hook to validate attribute((target("string"))). */
3668 ix86_valid_target_attribute_p (tree fndecl,
3669 tree ARG_UNUSED (name),
3671 int ARG_UNUSED (flags))
3673 struct cl_target_option cur_target;
3675 tree old_optimize = build_optimization_node ();
3676 tree new_target, new_optimize;
3677 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3679 /* If the function changed the optimization levels as well as setting target
3680 options, start with the optimizations specified. */
3681 if (func_optimize && func_optimize != old_optimize)
3682 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3684 /* The target attributes may also change some optimization flags, so update
3685 the optimization options if necessary. */
3686 cl_target_option_save (&cur_target);
3687 new_target = ix86_valid_target_attribute_tree (args);
3688 new_optimize = build_optimization_node ();
3695 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3697 if (old_optimize != new_optimize)
3698 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3701 cl_target_option_restore (&cur_target);
3703 if (old_optimize != new_optimize)
3704 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3710 /* Hook to determine if one function can safely inline another. */
3713 ix86_can_inline_p (tree caller, tree callee)
3716 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3717 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3719 /* If callee has no option attributes, then it is ok to inline. */
3723 /* If caller has no option attributes, but callee does then it is not ok to
3725 else if (!caller_tree)
3730 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3731 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3733 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3734 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3736 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3737 != callee_opts->ix86_isa_flags)
3740 /* See if we have the same non-isa options. */
3741 else if (caller_opts->target_flags != callee_opts->target_flags)
3744 /* See if arch, tune, etc. are the same. */
3745 else if (caller_opts->arch != callee_opts->arch)
3748 else if (caller_opts->tune != callee_opts->tune)
3751 else if (caller_opts->fpmath != callee_opts->fpmath)
3754 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3765 /* Remember the last target of ix86_set_current_function. */
3766 static GTY(()) tree ix86_previous_fndecl;
3768 /* Establish appropriate back-end context for processing the function
3769 FNDECL. The argument might be NULL to indicate processing at top
3770 level, outside of any function scope. */
3772 ix86_set_current_function (tree fndecl)
3774 /* Only change the context if the function changes. This hook is called
3775 several times in the course of compiling a function, and we don't want to
3776 slow things down too much or call target_reinit when it isn't safe. */
3777 if (fndecl && fndecl != ix86_previous_fndecl)
3779 tree old_tree = (ix86_previous_fndecl
3780 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3783 tree new_tree = (fndecl
3784 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3787 ix86_previous_fndecl = fndecl;
3788 if (old_tree == new_tree)
3793 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3799 struct cl_target_option *def
3800 = TREE_TARGET_OPTION (target_option_current_node);
3802 cl_target_option_restore (def);
3809 /* Return true if this goes in large data/bss. */
3812 ix86_in_large_data_p (tree exp)
3814 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3817 /* Functions are never large data. */
3818 if (TREE_CODE (exp) == FUNCTION_DECL)
3821 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3823 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3824 if (strcmp (section, ".ldata") == 0
3825 || strcmp (section, ".lbss") == 0)
3831 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3833 /* If this is an incomplete type with size 0, then we can't put it
3834 in data because it might be too big when completed. */
3835 if (!size || size > ix86_section_threshold)
3842 /* Switch to the appropriate section for output of DECL.
3843 DECL is either a `VAR_DECL' node or a constant of some sort.
3844 RELOC indicates whether forming the initial value of DECL requires
3845 link-time relocations. */
3847 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3851 x86_64_elf_select_section (tree decl, int reloc,
3852 unsigned HOST_WIDE_INT align)
3854 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3855 && ix86_in_large_data_p (decl))
3857 const char *sname = NULL;
3858 unsigned int flags = SECTION_WRITE;
3859 switch (categorize_decl_for_section (decl, reloc))
3864 case SECCAT_DATA_REL:
3865 sname = ".ldata.rel";
3867 case SECCAT_DATA_REL_LOCAL:
3868 sname = ".ldata.rel.local";
3870 case SECCAT_DATA_REL_RO:
3871 sname = ".ldata.rel.ro";
3873 case SECCAT_DATA_REL_RO_LOCAL:
3874 sname = ".ldata.rel.ro.local";
3878 flags |= SECTION_BSS;
3881 case SECCAT_RODATA_MERGE_STR:
3882 case SECCAT_RODATA_MERGE_STR_INIT:
3883 case SECCAT_RODATA_MERGE_CONST:
3887 case SECCAT_SRODATA:
3894 /* We don't split these for medium model. Place them into
3895 default sections and hope for best. */
3897 case SECCAT_EMUTLS_VAR:
3898 case SECCAT_EMUTLS_TMPL:
3903 /* We might get called with string constants, but get_named_section
3904 doesn't like them as they are not DECLs. Also, we need to set
3905 flags in that case. */
3907 return get_section (sname, flags, NULL);
3908 return get_named_section (decl, sname, reloc);
3911 return default_elf_select_section (decl, reloc, align);
3914 /* Build up a unique section name, expressed as a
3915 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3916 RELOC indicates whether the initial value of EXP requires
3917 link-time relocations. */
3919 static void ATTRIBUTE_UNUSED
3920 x86_64_elf_unique_section (tree decl, int reloc)
3922 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3923 && ix86_in_large_data_p (decl))
3925 const char *prefix = NULL;
3926 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3927 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3929 switch (categorize_decl_for_section (decl, reloc))
3932 case SECCAT_DATA_REL:
3933 case SECCAT_DATA_REL_LOCAL:
3934 case SECCAT_DATA_REL_RO:
3935 case SECCAT_DATA_REL_RO_LOCAL:
3936 prefix = one_only ? ".ld" : ".ldata";
3939 prefix = one_only ? ".lb" : ".lbss";
3942 case SECCAT_RODATA_MERGE_STR:
3943 case SECCAT_RODATA_MERGE_STR_INIT:
3944 case SECCAT_RODATA_MERGE_CONST:
3945 prefix = one_only ? ".lr" : ".lrodata";
3947 case SECCAT_SRODATA:
3954 /* We don't split these for medium model. Place them into
3955 default sections and hope for best. */
3957 case SECCAT_EMUTLS_VAR:
3958 prefix = targetm.emutls.var_section;
3960 case SECCAT_EMUTLS_TMPL:
3961 prefix = targetm.emutls.tmpl_section;
3966 const char *name, *linkonce;
3969 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3970 name = targetm.strip_name_encoding (name);
3972 /* If we're using one_only, then there needs to be a .gnu.linkonce
3973 prefix to the section name. */
3974 linkonce = one_only ? ".gnu.linkonce" : "";
3976 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3978 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3982 default_unique_section (decl, reloc);
3985 #ifdef COMMON_ASM_OP
3986 /* This says how to output assembler code to declare an
3987 uninitialized external linkage data object.
3989 For medium model x86-64 we need to use .largecomm opcode for
3992 x86_elf_aligned_common (FILE *file,
3993 const char *name, unsigned HOST_WIDE_INT size,
3996 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3997 && size > (unsigned int)ix86_section_threshold)
3998 fprintf (file, ".largecomm\t");
4000 fprintf (file, "%s", COMMON_ASM_OP);
4001 assemble_name (file, name);
4002 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
4003 size, align / BITS_PER_UNIT);
4007 /* Utility function for targets to use in implementing
4008 ASM_OUTPUT_ALIGNED_BSS. */
4011 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4012 const char *name, unsigned HOST_WIDE_INT size,
4015 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4016 && size > (unsigned int)ix86_section_threshold)
4017 switch_to_section (get_named_section (decl, ".lbss", 0));
4019 switch_to_section (bss_section);
4020 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4021 #ifdef ASM_DECLARE_OBJECT_NAME
4022 last_assemble_variable_decl = decl;
4023 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4025 /* Standard thing is just output label for the object. */
4026 ASM_OUTPUT_LABEL (file, name);
4027 #endif /* ASM_DECLARE_OBJECT_NAME */
4028 ASM_OUTPUT_SKIP (file, size ? size : 1);
4032 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4034 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4035 make the problem with not enough registers even worse. */
4036 #ifdef INSN_SCHEDULING
4038 flag_schedule_insns = 0;
4042 /* The Darwin libraries never set errno, so we might as well
4043 avoid calling them when that's the only reason we would. */
4044 flag_errno_math = 0;
4046 /* The default values of these switches depend on the TARGET_64BIT
4047 that is not known at this moment. Mark these values with 2 and
4048 let user the to override these. In case there is no command line option
4049 specifying them, we will set the defaults in override_options. */
4051 flag_omit_frame_pointer = 2;
4052 flag_pcc_struct_return = 2;
4053 flag_asynchronous_unwind_tables = 2;
4054 flag_vect_cost_model = 1;
4055 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4056 SUBTARGET_OPTIMIZATION_OPTIONS;
4060 /* Decide whether we can make a sibling call to a function. DECL is the
4061 declaration of the function being targeted by the call and EXP is the
4062 CALL_EXPR representing the call. */
4065 ix86_function_ok_for_sibcall (tree decl, tree exp)
4070 /* If we are generating position-independent code, we cannot sibcall
4071 optimize any indirect call, or a direct call to a global function,
4072 as the PLT requires %ebx be live. */
4073 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4080 func = TREE_TYPE (CALL_EXPR_FN (exp));
4081 if (POINTER_TYPE_P (func))
4082 func = TREE_TYPE (func);
4085 /* Check that the return value locations are the same. Like
4086 if we are returning floats on the 80387 register stack, we cannot
4087 make a sibcall from a function that doesn't return a float to a
4088 function that does or, conversely, from a function that does return
4089 a float to a function that doesn't; the necessary stack adjustment
4090 would not be executed. This is also the place we notice
4091 differences in the return value ABI. Note that it is ok for one
4092 of the functions to have void return type as long as the return
4093 value of the other is passed in a register. */
4094 a = ix86_function_value (TREE_TYPE (exp), func, false);
4095 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4097 if (STACK_REG_P (a) || STACK_REG_P (b))
4099 if (!rtx_equal_p (a, b))
4102 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4104 else if (!rtx_equal_p (a, b))
4107 /* If this call is indirect, we'll need to be able to use a call-clobbered
4108 register for the address of the target function. Make sure that all
4109 such registers are not used for passing parameters. */
4110 if (!decl && !TARGET_64BIT)
4114 /* We're looking at the CALL_EXPR, we need the type of the function. */
4115 type = CALL_EXPR_FN (exp); /* pointer expression */
4116 type = TREE_TYPE (type); /* pointer type */
4117 type = TREE_TYPE (type); /* function type */
4119 if (ix86_function_regparm (type, NULL) >= 3)
4121 /* ??? Need to count the actual number of registers to be used,
4122 not the possible number of registers. Fix later. */
4127 /* Dllimport'd functions are also called indirectly. */
4128 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4130 && decl && DECL_DLLIMPORT_P (decl)
4131 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4134 /* If we need to align the outgoing stack, then sibcalling would
4135 unalign the stack, which may break the called function. */
4136 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4139 /* Otherwise okay. That also includes certain types of indirect calls. */
4143 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4144 calling convention attributes;
4145 arguments as in struct attribute_spec.handler. */
4148 ix86_handle_cconv_attribute (tree *node, tree name,
4150 int flags ATTRIBUTE_UNUSED,
4153 if (TREE_CODE (*node) != FUNCTION_TYPE
4154 && TREE_CODE (*node) != METHOD_TYPE
4155 && TREE_CODE (*node) != FIELD_DECL
4156 && TREE_CODE (*node) != TYPE_DECL)
4158 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4159 IDENTIFIER_POINTER (name));
4160 *no_add_attrs = true;
4164 /* Can combine regparm with all attributes but fastcall. */
4165 if (is_attribute_p ("regparm", name))
4169 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4171 error ("fastcall and regparm attributes are not compatible");
4174 cst = TREE_VALUE (args);
4175 if (TREE_CODE (cst) != INTEGER_CST)
4177 warning (OPT_Wattributes,
4178 "%qs attribute requires an integer constant argument",
4179 IDENTIFIER_POINTER (name));
4180 *no_add_attrs = true;
4182 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4184 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4185 IDENTIFIER_POINTER (name), REGPARM_MAX);
4186 *no_add_attrs = true;
4194 /* Do not warn when emulating the MS ABI. */
4195 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4196 warning (OPT_Wattributes, "%qs attribute ignored",
4197 IDENTIFIER_POINTER (name));
4198 *no_add_attrs = true;
4202 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4203 if (is_attribute_p ("fastcall", name))
4205 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4207 error ("fastcall and cdecl attributes are not compatible");
4209 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4211 error ("fastcall and stdcall attributes are not compatible");
4213 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4215 error ("fastcall and regparm attributes are not compatible");
4219 /* Can combine stdcall with fastcall (redundant), regparm and
4221 else if (is_attribute_p ("stdcall", name))
4223 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4225 error ("stdcall and cdecl attributes are not compatible");
4227 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4229 error ("stdcall and fastcall attributes are not compatible");
4233 /* Can combine cdecl with regparm and sseregparm. */
4234 else if (is_attribute_p ("cdecl", name))
4236 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4238 error ("stdcall and cdecl attributes are not compatible");
4240 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4242 error ("fastcall and cdecl attributes are not compatible");
4246 /* Can combine sseregparm with all attributes. */
4251 /* Return 0 if the attributes for two types are incompatible, 1 if they
4252 are compatible, and 2 if they are nearly compatible (which causes a
4253 warning to be generated). */
4256 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4258 /* Check for mismatch of non-default calling convention. */
4259 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4261 if (TREE_CODE (type1) != FUNCTION_TYPE
4262 && TREE_CODE (type1) != METHOD_TYPE)
4265 /* Check for mismatched fastcall/regparm types. */
4266 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4267 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4268 || (ix86_function_regparm (type1, NULL)
4269 != ix86_function_regparm (type2, NULL)))
4272 /* Check for mismatched sseregparm types. */
4273 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4274 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4277 /* Check for mismatched return types (cdecl vs stdcall). */
4278 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4279 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4285 /* Return the regparm value for a function with the indicated TYPE and DECL.
4286 DECL may be NULL when calling function indirectly
4287 or considering a libcall. */
4290 ix86_function_regparm (const_tree type, const_tree decl)
4295 static bool error_issued;
4298 return (ix86_function_type_abi (type) == SYSV_ABI
4299 ? X86_64_REGPARM_MAX : X64_REGPARM_MAX);
4301 regparm = ix86_regparm;
4302 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4306 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4308 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4310 /* We can't use regparm(3) for nested functions because
4311 these pass static chain pointer in %ecx register. */
4312 if (!error_issued && regparm == 3
4313 && decl_function_context (decl)
4314 && !DECL_NO_STATIC_CHAIN (decl))
4316 error ("nested functions are limited to 2 register parameters");
4317 error_issued = true;
4325 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4328 /* Use register calling convention for local functions when possible. */
4330 && TREE_CODE (decl) == FUNCTION_DECL
4334 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4335 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4338 int local_regparm, globals = 0, regno;
4341 /* Make sure no regparm register is taken by a
4342 fixed register variable. */
4343 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4344 if (fixed_regs[local_regparm])
4347 /* We can't use regparm(3) for nested functions as these use
4348 static chain pointer in third argument. */
4349 if (local_regparm == 3
4350 && decl_function_context (decl)
4351 && !DECL_NO_STATIC_CHAIN (decl))
4354 /* If the function realigns its stackpointer, the prologue will
4355 clobber %ecx. If we've already generated code for the callee,
4356 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4357 scanning the attributes for the self-realigning property. */
4358 f = DECL_STRUCT_FUNCTION (decl);
4359 /* Since current internal arg pointer won't conflict with
4360 parameter passing regs, so no need to change stack
4361 realignment and adjust regparm number.
4363 Each fixed register usage increases register pressure,
4364 so less registers should be used for argument passing.
4365 This functionality can be overriden by an explicit
4367 for (regno = 0; regno <= DI_REG; regno++)
4368 if (fixed_regs[regno])
4372 = globals < local_regparm ? local_regparm - globals : 0;
4374 if (local_regparm > regparm)
4375 regparm = local_regparm;
4382 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4383 DFmode (2) arguments in SSE registers for a function with the
4384 indicated TYPE and DECL. DECL may be NULL when calling function
4385 indirectly or considering a libcall. Otherwise return 0. */
4388 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4390 gcc_assert (!TARGET_64BIT);
4392 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4393 by the sseregparm attribute. */
4394 if (TARGET_SSEREGPARM
4395 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4402 error ("Calling %qD with attribute sseregparm without "
4403 "SSE/SSE2 enabled", decl);
4405 error ("Calling %qT with attribute sseregparm without "
4406 "SSE/SSE2 enabled", type);
4414 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4415 (and DFmode for SSE2) arguments in SSE registers. */
4416 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4418 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4419 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4421 return TARGET_SSE2 ? 2 : 1;
4427 /* Return true if EAX is live at the start of the function. Used by
4428 ix86_expand_prologue to determine if we need special help before
4429 calling allocate_stack_worker. */
4432 ix86_eax_live_at_start_p (void)
4434 /* Cheat. Don't bother working forward from ix86_function_regparm
4435 to the function type to whether an actual argument is located in
4436 eax. Instead just look at cfg info, which is still close enough
4437 to correct at this point. This gives false positives for broken
4438 functions that might use uninitialized data that happens to be
4439 allocated in eax, but who cares? */
4440 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4443 /* Value is the number of bytes of arguments automatically
4444 popped when returning from a subroutine call.
4445 FUNDECL is the declaration node of the function (as a tree),
4446 FUNTYPE is the data type of the function (as a tree),
4447 or for a library call it is an identifier node for the subroutine name.
4448 SIZE is the number of bytes of arguments passed on the stack.
4450 On the 80386, the RTD insn may be used to pop them if the number
4451 of args is fixed, but if the number is variable then the caller
4452 must pop them all. RTD can't be used for library calls now
4453 because the library is compiled with the Unix compiler.
4454 Use of RTD is a selectable option, since it is incompatible with
4455 standard Unix calling sequences. If the option is not selected,
4456 the caller must always pop the args.
4458 The attribute stdcall is equivalent to RTD on a per module basis. */
4461 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4465 /* None of the 64-bit ABIs pop arguments. */
4469 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4471 /* Cdecl functions override -mrtd, and never pop the stack. */
4472 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4474 /* Stdcall and fastcall functions will pop the stack if not
4476 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4477 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4480 if (rtd && ! stdarg_p (funtype))
4484 /* Lose any fake structure return argument if it is passed on the stack. */
4485 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4486 && !KEEP_AGGREGATE_RETURN_POINTER)
4488 int nregs = ix86_function_regparm (funtype, fundecl);
4490 return GET_MODE_SIZE (Pmode);
4496 /* Argument support functions. */
4498 /* Return true when register may be used to pass function parameters. */
4500 ix86_function_arg_regno_p (int regno)
4503 const int *parm_regs;
4508 return (regno < REGPARM_MAX
4509 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4511 return (regno < REGPARM_MAX
4512 || (TARGET_MMX && MMX_REGNO_P (regno)
4513 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4514 || (TARGET_SSE && SSE_REGNO_P (regno)
4515 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4520 if (SSE_REGNO_P (regno) && TARGET_SSE)
4525 if (TARGET_SSE && SSE_REGNO_P (regno)
4526 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4530 /* TODO: The function should depend on current function ABI but
4531 builtins.c would need updating then. Therefore we use the
4534 /* RAX is used as hidden argument to va_arg functions. */
4535 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4538 if (ix86_abi == MS_ABI)
4539 parm_regs = x86_64_ms_abi_int_parameter_registers;
4541 parm_regs = x86_64_int_parameter_registers;
4542 for (i = 0; i < (ix86_abi == MS_ABI ? X64_REGPARM_MAX
4543 : X86_64_REGPARM_MAX); i++)
4544 if (regno == parm_regs[i])
4549 /* Return if we do not know how to pass TYPE solely in registers. */
4552 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4554 if (must_pass_in_stack_var_size_or_pad (mode, type))
4557 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4558 The layout_type routine is crafty and tries to trick us into passing
4559 currently unsupported vector types on the stack by using TImode. */
4560 return (!TARGET_64BIT && mode == TImode
4561 && type && TREE_CODE (type) != VECTOR_TYPE);
4564 /* It returns the size, in bytes, of the area reserved for arguments passed
4565 in registers for the function represented by fndecl dependent to the used
4568 ix86_reg_parm_stack_space (const_tree fndecl)
4570 enum calling_abi call_abi = SYSV_ABI;
4571 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4572 call_abi = ix86_function_abi (fndecl);
4574 call_abi = ix86_function_type_abi (fndecl);
4575 if (call_abi == MS_ABI)
4580 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4583 ix86_function_type_abi (const_tree fntype)
4585 if (TARGET_64BIT && fntype != NULL)
4587 enum calling_abi abi = ix86_abi;
4588 if (abi == SYSV_ABI)
4590 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4593 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4600 static enum calling_abi
4601 ix86_function_abi (const_tree fndecl)
4605 return ix86_function_type_abi (TREE_TYPE (fndecl));
4608 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4611 ix86_cfun_abi (void)
4613 if (! cfun || ! TARGET_64BIT)
4615 return cfun->machine->call_abi;
4619 extern void init_regs (void);
4621 /* Implementation of call abi switching target hook. Specific to FNDECL
4622 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4623 for more details. */
4625 ix86_call_abi_override (const_tree fndecl)
4627 if (fndecl == NULL_TREE)
4628 cfun->machine->call_abi = ix86_abi;
4630 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4633 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4634 re-initialization of init_regs each time we switch function context since
4635 this is needed only during RTL expansion. */
4637 ix86_maybe_switch_abi (void)
4640 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4644 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4645 for a call to a function whose data type is FNTYPE.
4646 For a library call, FNTYPE is 0. */
4649 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4650 tree fntype, /* tree ptr for function decl */
4651 rtx libname, /* SYMBOL_REF of library name or 0 */
4654 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4655 memset (cum, 0, sizeof (*cum));
4658 cum->call_abi = ix86_function_abi (fndecl);
4660 cum->call_abi = ix86_function_type_abi (fntype);
4661 /* Set up the number of registers to use for passing arguments. */
4663 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4664 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4665 cum->nregs = ix86_regparm;
4668 if (cum->call_abi != ix86_abi)
4669 cum->nregs = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX
4674 cum->sse_nregs = SSE_REGPARM_MAX;
4677 if (cum->call_abi != ix86_abi)
4678 cum->sse_nregs = ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4679 : X64_SSE_REGPARM_MAX;
4683 cum->mmx_nregs = MMX_REGPARM_MAX;
4684 cum->warn_avx = true;
4685 cum->warn_sse = true;
4686 cum->warn_mmx = true;
4688 /* Because type might mismatch in between caller and callee, we need to
4689 use actual type of function for local calls.
4690 FIXME: cgraph_analyze can be told to actually record if function uses
4691 va_start so for local functions maybe_vaarg can be made aggressive
4693 FIXME: once typesytem is fixed, we won't need this code anymore. */
4695 fntype = TREE_TYPE (fndecl);
4696 cum->maybe_vaarg = (fntype
4697 ? (!prototype_p (fntype) || stdarg_p (fntype))
4702 /* If there are variable arguments, then we won't pass anything
4703 in registers in 32-bit mode. */
4704 if (stdarg_p (fntype))
4715 /* Use ecx and edx registers if function has fastcall attribute,
4716 else look for regparm information. */
4719 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4725 cum->nregs = ix86_function_regparm (fntype, fndecl);
4728 /* Set up the number of SSE registers used for passing SFmode
4729 and DFmode arguments. Warn for mismatching ABI. */
4730 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4734 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4735 But in the case of vector types, it is some vector mode.
4737 When we have only some of our vector isa extensions enabled, then there
4738 are some modes for which vector_mode_supported_p is false. For these
4739 modes, the generic vector support in gcc will choose some non-vector mode
4740 in order to implement the type. By computing the natural mode, we'll
4741 select the proper ABI location for the operand and not depend on whatever
4742 the middle-end decides to do with these vector types.
4744 The midde-end can't deal with the vector types > 16 bytes. In this
4745 case, we return the original mode and warn ABI change if CUM isn't
4748 static enum machine_mode
4749 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4751 enum machine_mode mode = TYPE_MODE (type);
4753 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4755 HOST_WIDE_INT size = int_size_in_bytes (type);
4756 if ((size == 8 || size == 16 || size == 32)
4757 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4758 && TYPE_VECTOR_SUBPARTS (type) > 1)
4760 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4762 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4763 mode = MIN_MODE_VECTOR_FLOAT;
4765 mode = MIN_MODE_VECTOR_INT;
4767 /* Get the mode which has this inner mode and number of units. */
4768 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4769 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4770 && GET_MODE_INNER (mode) == innermode)
4772 if (size == 32 && !TARGET_AVX)
4774 static bool warnedavx;
4781 warning (0, "AVX vector argument without AVX "
4782 "enabled changes the ABI");
4784 return TYPE_MODE (type);
4797 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4798 this may not agree with the mode that the type system has chosen for the
4799 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4800 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4803 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4808 if (orig_mode != BLKmode)
4809 tmp = gen_rtx_REG (orig_mode, regno);
4812 tmp = gen_rtx_REG (mode, regno);
4813 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4814 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4820 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4821 of this code is to classify each 8bytes of incoming argument by the register
4822 class and assign registers accordingly. */
4824 /* Return the union class of CLASS1 and CLASS2.
4825 See the x86-64 PS ABI for details. */
4827 static enum x86_64_reg_class
4828 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4830 /* Rule #1: If both classes are equal, this is the resulting class. */
4831 if (class1 == class2)
4834 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4836 if (class1 == X86_64_NO_CLASS)
4838 if (class2 == X86_64_NO_CLASS)
4841 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4842 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4843 return X86_64_MEMORY_CLASS;
4845 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4846 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4847 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4848 return X86_64_INTEGERSI_CLASS;
4849 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4850 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4851 return X86_64_INTEGER_CLASS;
4853 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4855 if (class1 == X86_64_X87_CLASS
4856 || class1 == X86_64_X87UP_CLASS
4857 || class1 == X86_64_COMPLEX_X87_CLASS
4858 || class2 == X86_64_X87_CLASS
4859 || class2 == X86_64_X87UP_CLASS
4860 || class2 == X86_64_COMPLEX_X87_CLASS)
4861 return X86_64_MEMORY_CLASS;
4863 /* Rule #6: Otherwise class SSE is used. */
4864 return X86_64_SSE_CLASS;
4867 /* Classify the argument of type TYPE and mode MODE.
4868 CLASSES will be filled by the register class used to pass each word
4869 of the operand. The number of words is returned. In case the parameter
4870 should be passed in memory, 0 is returned. As a special case for zero
4871 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4873 BIT_OFFSET is used internally for handling records and specifies offset
4874 of the offset in bits modulo 256 to avoid overflow cases.
4876 See the x86-64 PS ABI for details.
4880 classify_argument (enum machine_mode mode, const_tree type,
4881 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4883 HOST_WIDE_INT bytes =
4884 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4885 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4887 /* Variable sized entities are always passed/returned in memory. */
4891 if (mode != VOIDmode
4892 && targetm.calls.must_pass_in_stack (mode, type))
4895 if (type && AGGREGATE_TYPE_P (type))
4899 enum x86_64_reg_class subclasses[MAX_CLASSES];
4901 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4905 for (i = 0; i < words; i++)
4906 classes[i] = X86_64_NO_CLASS;
4908 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4909 signalize memory class, so handle it as special case. */
4912 classes[0] = X86_64_NO_CLASS;
4916 /* Classify each field of record and merge classes. */
4917 switch (TREE_CODE (type))
4920 /* And now merge the fields of structure. */
4921 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4923 if (TREE_CODE (field) == FIELD_DECL)
4927 if (TREE_TYPE (field) == error_mark_node)
4930 /* Bitfields are always classified as integer. Handle them
4931 early, since later code would consider them to be
4932 misaligned integers. */
4933 if (DECL_BIT_FIELD (field))
4935 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4936 i < ((int_bit_position (field) + (bit_offset % 64))
4937 + tree_low_cst (DECL_SIZE (field), 0)
4940 merge_classes (X86_64_INTEGER_CLASS,
4945 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4946 TREE_TYPE (field), subclasses,
4947 (int_bit_position (field)
4948 + bit_offset) % 256);
4951 for (i = 0; i < num; i++)
4954 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4956 merge_classes (subclasses[i], classes[i + pos]);
4964 /* Arrays are handled as small records. */
4967 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4968 TREE_TYPE (type), subclasses, bit_offset);
4972 /* The partial classes are now full classes. */
4973 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4974 subclasses[0] = X86_64_SSE_CLASS;
4975 if (subclasses[0] == X86_64_INTEGERSI_CLASS
4976 && !((bit_offset % 64) == 0 && bytes == 4))
4977 subclasses[0] = X86_64_INTEGER_CLASS;
4979 for (i = 0; i < words; i++)
4980 classes[i] = subclasses[i % num];
4985 case QUAL_UNION_TYPE:
4986 /* Unions are similar to RECORD_TYPE but offset is always 0.
4988 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4990 if (TREE_CODE (field) == FIELD_DECL)
4994 if (TREE_TYPE (field) == error_mark_node)
4997 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4998 TREE_TYPE (field), subclasses,
5002 for (i = 0; i < num; i++)
5003 classes[i] = merge_classes (subclasses[i], classes[i]);
5014 /* When size > 16 bytes, if the first one isn't
5015 X86_64_SSE_CLASS or any other ones aren't
5016 X86_64_SSEUP_CLASS, everything should be passed in
5018 if (classes[0] != X86_64_SSE_CLASS)
5021 for (i = 1; i < words; i++)
5022 if (classes[i] != X86_64_SSEUP_CLASS)
5026 /* Final merger cleanup. */
5027 for (i = 0; i < words; i++)
5029 /* If one class is MEMORY, everything should be passed in
5031 if (classes[i] == X86_64_MEMORY_CLASS)
5034 /* The X86_64_SSEUP_CLASS should be always preceded by
5035 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5036 if (classes[i] == X86_64_SSEUP_CLASS
5037 && classes[i - 1] != X86_64_SSE_CLASS
5038 && classes[i - 1] != X86_64_SSEUP_CLASS)
5040 /* The first one should never be X86_64_SSEUP_CLASS. */
5041 gcc_assert (i != 0);
5042 classes[i] = X86_64_SSE_CLASS;
5045 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5046 everything should be passed in memory. */
5047 if (classes[i] == X86_64_X87UP_CLASS
5048 && (classes[i - 1] != X86_64_X87_CLASS))
5052 /* The first one should never be X86_64_X87UP_CLASS. */
5053 gcc_assert (i != 0);
5054 if (!warned && warn_psabi)
5057 inform (input_location,
5058 "The ABI of passing union with long double"
5059 " has changed in GCC 4.4");
5067 /* Compute alignment needed. We align all types to natural boundaries with
5068 exception of XFmode that is aligned to 64bits. */
5069 if (mode != VOIDmode && mode != BLKmode)
5071 int mode_alignment = GET_MODE_BITSIZE (mode);
5074 mode_alignment = 128;
5075 else if (mode == XCmode)
5076 mode_alignment = 256;
5077 if (COMPLEX_MODE_P (mode))
5078 mode_alignment /= 2;
5079 /* Misaligned fields are always returned in memory. */
5080 if (bit_offset % mode_alignment)
5084 /* for V1xx modes, just use the base mode */
5085 if (VECTOR_MODE_P (mode) && mode != V1DImode
5086 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5087 mode = GET_MODE_INNER (mode);
5089 /* Classification of atomic types. */
5094 classes[0] = X86_64_SSE_CLASS;
5097 classes[0] = X86_64_SSE_CLASS;
5098 classes[1] = X86_64_SSEUP_CLASS;
5108 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5112 classes[0] = X86_64_INTEGERSI_CLASS;
5115 else if (size <= 64)
5117 classes[0] = X86_64_INTEGER_CLASS;
5120 else if (size <= 64+32)
5122 classes[0] = X86_64_INTEGER_CLASS;
5123 classes[1] = X86_64_INTEGERSI_CLASS;
5126 else if (size <= 64+64)
5128 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5136 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5140 /* OImode shouldn't be used directly. */
5145 if (!(bit_offset % 64))
5146 classes[0] = X86_64_SSESF_CLASS;
5148 classes[0] = X86_64_SSE_CLASS;
5151 classes[0] = X86_64_SSEDF_CLASS;
5154 classes[0] = X86_64_X87_CLASS;
5155 classes[1] = X86_64_X87UP_CLASS;
5158 classes[0] = X86_64_SSE_CLASS;
5159 classes[1] = X86_64_SSEUP_CLASS;
5162 classes[0] = X86_64_SSE_CLASS;
5165 classes[0] = X86_64_SSEDF_CLASS;
5166 classes[1] = X86_64_SSEDF_CLASS;
5169 classes[0] = X86_64_COMPLEX_X87_CLASS;
5172 /* This modes is larger than 16 bytes. */
5180 classes[0] = X86_64_SSE_CLASS;
5181 classes[1] = X86_64_SSEUP_CLASS;
5182 classes[2] = X86_64_SSEUP_CLASS;
5183 classes[3] = X86_64_SSEUP_CLASS;
5191 classes[0] = X86_64_SSE_CLASS;
5192 classes[1] = X86_64_SSEUP_CLASS;
5199 classes[0] = X86_64_SSE_CLASS;
5205 gcc_assert (VECTOR_MODE_P (mode));
5210 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5212 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5213 classes[0] = X86_64_INTEGERSI_CLASS;
5215 classes[0] = X86_64_INTEGER_CLASS;
5216 classes[1] = X86_64_INTEGER_CLASS;
5217 return 1 + (bytes > 8);
5221 /* Examine the argument and return set number of register required in each
5222 class. Return 0 iff parameter should be passed in memory. */
5224 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5225 int *int_nregs, int *sse_nregs)
5227 enum x86_64_reg_class regclass[MAX_CLASSES];
5228 int n = classify_argument (mode, type, regclass, 0);
5234 for (n--; n >= 0; n--)
5235 switch (regclass[n])
5237 case X86_64_INTEGER_CLASS:
5238 case X86_64_INTEGERSI_CLASS:
5241 case X86_64_SSE_CLASS:
5242 case X86_64_SSESF_CLASS:
5243 case X86_64_SSEDF_CLASS:
5246 case X86_64_NO_CLASS:
5247 case X86_64_SSEUP_CLASS:
5249 case X86_64_X87_CLASS:
5250 case X86_64_X87UP_CLASS:
5254 case X86_64_COMPLEX_X87_CLASS:
5255 return in_return ? 2 : 0;
5256 case X86_64_MEMORY_CLASS:
5262 /* Construct container for the argument used by GCC interface. See
5263 FUNCTION_ARG for the detailed description. */
5266 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5267 const_tree type, int in_return, int nintregs, int nsseregs,
5268 const int *intreg, int sse_regno)
5270 /* The following variables hold the static issued_error state. */
5271 static bool issued_sse_arg_error;
5272 static bool issued_sse_ret_error;
5273 static bool issued_x87_ret_error;
5275 enum machine_mode tmpmode;
5277 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5278 enum x86_64_reg_class regclass[MAX_CLASSES];
5282 int needed_sseregs, needed_intregs;
5283 rtx exp[MAX_CLASSES];
5286 n = classify_argument (mode, type, regclass, 0);
5289 if (!examine_argument (mode, type, in_return, &needed_intregs,
5292 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5295 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5296 some less clueful developer tries to use floating-point anyway. */
5297 if (needed_sseregs && !TARGET_SSE)
5301 if (!issued_sse_ret_error)
5303 error ("SSE register return with SSE disabled");
5304 issued_sse_ret_error = true;
5307 else if (!issued_sse_arg_error)
5309 error ("SSE register argument with SSE disabled");
5310 issued_sse_arg_error = true;
5315 /* Likewise, error if the ABI requires us to return values in the
5316 x87 registers and the user specified -mno-80387. */
5317 if (!TARGET_80387 && in_return)
5318 for (i = 0; i < n; i++)
5319 if (regclass[i] == X86_64_X87_CLASS
5320 || regclass[i] == X86_64_X87UP_CLASS
5321 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5323 if (!issued_x87_ret_error)
5325 error ("x87 register return with x87 disabled");
5326 issued_x87_ret_error = true;
5331 /* First construct simple cases. Avoid SCmode, since we want to use
5332 single register to pass this type. */
5333 if (n == 1 && mode != SCmode)
5334 switch (regclass[0])
5336 case X86_64_INTEGER_CLASS:
5337 case X86_64_INTEGERSI_CLASS:
5338 return gen_rtx_REG (mode, intreg[0]);
5339 case X86_64_SSE_CLASS:
5340 case X86_64_SSESF_CLASS:
5341 case X86_64_SSEDF_CLASS:
5342 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5343 case X86_64_X87_CLASS:
5344 case X86_64_COMPLEX_X87_CLASS:
5345 return gen_rtx_REG (mode, FIRST_STACK_REG);
5346 case X86_64_NO_CLASS:
5347 /* Zero sized array, struct or class. */
5352 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5353 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5354 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5356 && regclass[0] == X86_64_SSE_CLASS
5357 && regclass[1] == X86_64_SSEUP_CLASS
5358 && regclass[2] == X86_64_SSEUP_CLASS
5359 && regclass[3] == X86_64_SSEUP_CLASS
5361 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5364 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5365 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5366 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5367 && regclass[1] == X86_64_INTEGER_CLASS
5368 && (mode == CDImode || mode == TImode || mode == TFmode)
5369 && intreg[0] + 1 == intreg[1])
5370 return gen_rtx_REG (mode, intreg[0]);
5372 /* Otherwise figure out the entries of the PARALLEL. */
5373 for (i = 0; i < n; i++)
5377 switch (regclass[i])
5379 case X86_64_NO_CLASS:
5381 case X86_64_INTEGER_CLASS:
5382 case X86_64_INTEGERSI_CLASS:
5383 /* Merge TImodes on aligned occasions here too. */
5384 if (i * 8 + 8 > bytes)
5385 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5386 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5390 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5391 if (tmpmode == BLKmode)
5393 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5394 gen_rtx_REG (tmpmode, *intreg),
5398 case X86_64_SSESF_CLASS:
5399 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5400 gen_rtx_REG (SFmode,
5401 SSE_REGNO (sse_regno)),
5405 case X86_64_SSEDF_CLASS:
5406 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5407 gen_rtx_REG (DFmode,
5408 SSE_REGNO (sse_regno)),
5412 case X86_64_SSE_CLASS:
5420 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5430 && regclass[1] == X86_64_SSEUP_CLASS
5431 && regclass[2] == X86_64_SSEUP_CLASS
5432 && regclass[3] == X86_64_SSEUP_CLASS);
5439 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5440 gen_rtx_REG (tmpmode,
5441 SSE_REGNO (sse_regno)),
5450 /* Empty aligned struct, union or class. */
5454 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5455 for (i = 0; i < nexps; i++)
5456 XVECEXP (ret, 0, i) = exp [i];
5460 /* Update the data in CUM to advance over an argument of mode MODE
5461 and data type TYPE. (TYPE is null for libcalls where that information
5462 may not be available.) */
5465 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5466 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5482 cum->words += words;
5483 cum->nregs -= words;
5484 cum->regno += words;
5486 if (cum->nregs <= 0)
5494 /* OImode shouldn't be used directly. */
5498 if (cum->float_in_sse < 2)
5501 if (cum->float_in_sse < 1)
5518 if (!type || !AGGREGATE_TYPE_P (type))
5520 cum->sse_words += words;
5521 cum->sse_nregs -= 1;
5522 cum->sse_regno += 1;
5523 if (cum->sse_nregs <= 0)
5536 if (!type || !AGGREGATE_TYPE_P (type))
5538 cum->mmx_words += words;
5539 cum->mmx_nregs -= 1;
5540 cum->mmx_regno += 1;
5541 if (cum->mmx_nregs <= 0)
5552 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5553 tree type, HOST_WIDE_INT words, int named)
5555 int int_nregs, sse_nregs;
5557 /* Unnamed 256bit vector mode parameters are passed on stack. */
5558 if (!named && VALID_AVX256_REG_MODE (mode))
5561 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5562 cum->words += words;
5563 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5565 cum->nregs -= int_nregs;
5566 cum->sse_nregs -= sse_nregs;
5567 cum->regno += int_nregs;
5568 cum->sse_regno += sse_nregs;
5571 cum->words += words;
5575 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5576 HOST_WIDE_INT words)
5578 /* Otherwise, this should be passed indirect. */
5579 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5581 cum->words += words;
5590 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5591 tree type, int named)
5593 HOST_WIDE_INT bytes, words;
5595 if (mode == BLKmode)
5596 bytes = int_size_in_bytes (type);
5598 bytes = GET_MODE_SIZE (mode);
5599 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5602 mode = type_natural_mode (type, NULL);
5604 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5605 function_arg_advance_ms_64 (cum, bytes, words);
5606 else if (TARGET_64BIT)
5607 function_arg_advance_64 (cum, mode, type, words, named);
5609 function_arg_advance_32 (cum, mode, type, bytes, words);
5612 /* Define where to put the arguments to a function.
5613 Value is zero to push the argument on the stack,
5614 or a hard register in which to store the argument.
5616 MODE is the argument's machine mode.
5617 TYPE is the data type of the argument (as a tree).
5618 This is null for libcalls where that information may
5620 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5621 the preceding args and about the function being called.
5622 NAMED is nonzero if this argument is a named parameter
5623 (otherwise it is an extra parameter matching an ellipsis). */
5626 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5627 enum machine_mode orig_mode, tree type,
5628 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5630 static bool warnedsse, warnedmmx;
5632 /* Avoid the AL settings for the Unix64 ABI. */
5633 if (mode == VOIDmode)
5649 if (words <= cum->nregs)
5651 int regno = cum->regno;
5653 /* Fastcall allocates the first two DWORD (SImode) or
5654 smaller arguments to ECX and EDX if it isn't an
5660 || (type && AGGREGATE_TYPE_P (type)))
5663 /* ECX not EAX is the first allocated register. */
5664 if (regno == AX_REG)
5667 return gen_rtx_REG (mode, regno);
5672 if (cum->float_in_sse < 2)
5675 if (cum->float_in_sse < 1)
5679 /* In 32bit, we pass TImode in xmm registers. */
5686 if (!type || !AGGREGATE_TYPE_P (type))
5688 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5691 warning (0, "SSE vector argument without SSE enabled "
5695 return gen_reg_or_parallel (mode, orig_mode,
5696 cum->sse_regno + FIRST_SSE_REG);
5701 /* OImode shouldn't be used directly. */
5710 if (!type || !AGGREGATE_TYPE_P (type))
5713 return gen_reg_or_parallel (mode, orig_mode,
5714 cum->sse_regno + FIRST_SSE_REG);
5723 if (!type || !AGGREGATE_TYPE_P (type))
5725 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5728 warning (0, "MMX vector argument without MMX enabled "
5732 return gen_reg_or_parallel (mode, orig_mode,
5733 cum->mmx_regno + FIRST_MMX_REG);
5742 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5743 enum machine_mode orig_mode, tree type, int named)
5745 /* Handle a hidden AL argument containing number of registers
5746 for varargs x86-64 functions. */
5747 if (mode == VOIDmode)
5748 return GEN_INT (cum->maybe_vaarg
5749 ? (cum->sse_nregs < 0
5750 ? (cum->call_abi == ix86_abi
5752 : (ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5753 : X64_SSE_REGPARM_MAX))
5768 /* Unnamed 256bit vector mode parameters are passed on stack. */
5774 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5776 &x86_64_int_parameter_registers [cum->regno],
5781 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5782 enum machine_mode orig_mode, int named,
5783 HOST_WIDE_INT bytes)
5787 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5788 We use value of -2 to specify that current function call is MSABI. */
5789 if (mode == VOIDmode)
5790 return GEN_INT (-2);
5792 /* If we've run out of registers, it goes on the stack. */
5793 if (cum->nregs == 0)
5796 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5798 /* Only floating point modes are passed in anything but integer regs. */
5799 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5802 regno = cum->regno + FIRST_SSE_REG;
5807 /* Unnamed floating parameters are passed in both the
5808 SSE and integer registers. */
5809 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5810 t2 = gen_rtx_REG (mode, regno);
5811 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5812 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5813 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5816 /* Handle aggregated types passed in register. */
5817 if (orig_mode == BLKmode)
5819 if (bytes > 0 && bytes <= 8)
5820 mode = (bytes > 4 ? DImode : SImode);
5821 if (mode == BLKmode)
5825 return gen_reg_or_parallel (mode, orig_mode, regno);
5829 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5830 tree type, int named)
5832 enum machine_mode mode = omode;
5833 HOST_WIDE_INT bytes, words;
5835 if (mode == BLKmode)
5836 bytes = int_size_in_bytes (type);
5838 bytes = GET_MODE_SIZE (mode);
5839 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5841 /* To simplify the code below, represent vector types with a vector mode
5842 even if MMX/SSE are not active. */
5843 if (type && TREE_CODE (type) == VECTOR_TYPE)
5844 mode = type_natural_mode (type, cum);
5846 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5847 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5848 else if (TARGET_64BIT)
5849 return function_arg_64 (cum, mode, omode, type, named);
5851 return function_arg_32 (cum, mode, omode, type, bytes, words);
5854 /* A C expression that indicates when an argument must be passed by
5855 reference. If nonzero for an argument, a copy of that argument is
5856 made in memory and a pointer to the argument is passed instead of
5857 the argument itself. The pointer is passed in whatever way is
5858 appropriate for passing a pointer to that type. */
5861 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5862 enum machine_mode mode ATTRIBUTE_UNUSED,
5863 const_tree type, bool named ATTRIBUTE_UNUSED)
5865 /* See Windows x64 Software Convention. */
5866 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5868 int msize = (int) GET_MODE_SIZE (mode);
5871 /* Arrays are passed by reference. */
5872 if (TREE_CODE (type) == ARRAY_TYPE)
5875 if (AGGREGATE_TYPE_P (type))
5877 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5878 are passed by reference. */
5879 msize = int_size_in_bytes (type);
5883 /* __m128 is passed by reference. */
5885 case 1: case 2: case 4: case 8:
5891 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5897 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5900 contains_aligned_value_p (tree type)
5902 enum machine_mode mode = TYPE_MODE (type);
5903 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5907 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5909 if (TYPE_ALIGN (type) < 128)
5912 if (AGGREGATE_TYPE_P (type))
5914 /* Walk the aggregates recursively. */
5915 switch (TREE_CODE (type))
5919 case QUAL_UNION_TYPE:
5923 /* Walk all the structure fields. */
5924 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5926 if (TREE_CODE (field) == FIELD_DECL
5927 && contains_aligned_value_p (TREE_TYPE (field)))
5934 /* Just for use if some languages passes arrays by value. */
5935 if (contains_aligned_value_p (TREE_TYPE (type)))
5946 /* Gives the alignment boundary, in bits, of an argument with the
5947 specified mode and type. */
5950 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5955 /* Since canonical type is used for call, we convert it to
5956 canonical type if needed. */
5957 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5958 type = TYPE_CANONICAL (type);
5959 align = TYPE_ALIGN (type);
5962 align = GET_MODE_ALIGNMENT (mode);
5963 if (align < PARM_BOUNDARY)
5964 align = PARM_BOUNDARY;
5965 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5966 natural boundaries. */
5967 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5969 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5970 make an exception for SSE modes since these require 128bit
5973 The handling here differs from field_alignment. ICC aligns MMX
5974 arguments to 4 byte boundaries, while structure fields are aligned
5975 to 8 byte boundaries. */
5978 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5979 align = PARM_BOUNDARY;
5983 if (!contains_aligned_value_p (type))
5984 align = PARM_BOUNDARY;
5987 if (align > BIGGEST_ALIGNMENT)
5988 align = BIGGEST_ALIGNMENT;
5992 /* Return true if N is a possible register number of function value. */
5995 ix86_function_value_regno_p (int regno)
6002 case FIRST_FLOAT_REG:
6003 /* TODO: The function should depend on current function ABI but
6004 builtins.c would need updating then. Therefore we use the
6006 if (TARGET_64BIT && ix86_abi == MS_ABI)
6008 return TARGET_FLOAT_RETURNS_IN_80387;
6014 if (TARGET_MACHO || TARGET_64BIT)
6022 /* Define how to find the value returned by a function.
6023 VALTYPE is the data type of the value (as a tree).
6024 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6025 otherwise, FUNC is 0. */
6028 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6029 const_tree fntype, const_tree fn)
6033 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6034 we normally prevent this case when mmx is not available. However
6035 some ABIs may require the result to be returned like DImode. */
6036 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6037 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6039 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6040 we prevent this case when sse is not available. However some ABIs
6041 may require the result to be returned like integer TImode. */
6042 else if (mode == TImode
6043 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6044 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6046 /* 32-byte vector modes in %ymm0. */
6047 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6048 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6050 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6051 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6052 regno = FIRST_FLOAT_REG;
6054 /* Most things go in %eax. */
6057 /* Override FP return register with %xmm0 for local functions when
6058 SSE math is enabled or for functions with sseregparm attribute. */
6059 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6061 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6062 if ((sse_level >= 1 && mode == SFmode)
6063 || (sse_level == 2 && mode == DFmode))
6064 regno = FIRST_SSE_REG;
6067 /* OImode shouldn't be used directly. */
6068 gcc_assert (mode != OImode);
6070 return gen_rtx_REG (orig_mode, regno);
6074 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6079 /* Handle libcalls, which don't provide a type node. */
6080 if (valtype == NULL)
6092 return gen_rtx_REG (mode, FIRST_SSE_REG);
6095 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6099 return gen_rtx_REG (mode, AX_REG);
6103 ret = construct_container (mode, orig_mode, valtype, 1,
6104 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6105 x86_64_int_return_registers, 0);
6107 /* For zero sized structures, construct_container returns NULL, but we
6108 need to keep rest of compiler happy by returning meaningful value. */
6110 ret = gen_rtx_REG (orig_mode, AX_REG);
6116 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6118 unsigned int regno = AX_REG;
6122 switch (GET_MODE_SIZE (mode))
6125 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6126 && !COMPLEX_MODE_P (mode))
6127 regno = FIRST_SSE_REG;
6131 if (mode == SFmode || mode == DFmode)
6132 regno = FIRST_SSE_REG;
6138 return gen_rtx_REG (orig_mode, regno);
6142 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6143 enum machine_mode orig_mode, enum machine_mode mode)
6145 const_tree fn, fntype;
6148 if (fntype_or_decl && DECL_P (fntype_or_decl))
6149 fn = fntype_or_decl;
6150 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6152 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6153 return function_value_ms_64 (orig_mode, mode);
6154 else if (TARGET_64BIT)
6155 return function_value_64 (orig_mode, mode, valtype);
6157 return function_value_32 (orig_mode, mode, fntype, fn);
6161 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6162 bool outgoing ATTRIBUTE_UNUSED)
6164 enum machine_mode mode, orig_mode;
6166 orig_mode = TYPE_MODE (valtype);
6167 mode = type_natural_mode (valtype, NULL);
6168 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6172 ix86_libcall_value (enum machine_mode mode)
6174 return ix86_function_value_1 (NULL, NULL, mode, mode);
6177 /* Return true iff type is returned in memory. */
6179 static int ATTRIBUTE_UNUSED
6180 return_in_memory_32 (const_tree type, enum machine_mode mode)
6184 if (mode == BLKmode)
6187 size = int_size_in_bytes (type);
6189 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6192 if (VECTOR_MODE_P (mode) || mode == TImode)
6194 /* User-created vectors small enough to fit in EAX. */
6198 /* MMX/3dNow values are returned in MM0,
6199 except when it doesn't exits. */
6201 return (TARGET_MMX ? 0 : 1);
6203 /* SSE values are returned in XMM0, except when it doesn't exist. */
6205 return (TARGET_SSE ? 0 : 1);
6207 /* AVX values are returned in YMM0, except when it doesn't exist. */
6209 return TARGET_AVX ? 0 : 1;
6218 /* OImode shouldn't be used directly. */
6219 gcc_assert (mode != OImode);
6224 static int ATTRIBUTE_UNUSED
6225 return_in_memory_64 (const_tree type, enum machine_mode mode)
6227 int needed_intregs, needed_sseregs;
6228 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6231 static int ATTRIBUTE_UNUSED
6232 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6234 HOST_WIDE_INT size = int_size_in_bytes (type);
6236 /* __m128 is returned in xmm0. */
6237 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6238 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6241 /* Otherwise, the size must be exactly in [1248]. */
6242 return (size != 1 && size != 2 && size != 4 && size != 8);
6246 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6248 #ifdef SUBTARGET_RETURN_IN_MEMORY
6249 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6251 const enum machine_mode mode = type_natural_mode (type, NULL);
6255 if (ix86_function_type_abi (fntype) == MS_ABI)
6256 return return_in_memory_ms_64 (type, mode);
6258 return return_in_memory_64 (type, mode);
6261 return return_in_memory_32 (type, mode);
6265 /* Return false iff TYPE is returned in memory. This version is used
6266 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6267 but differs notably in that when MMX is available, 8-byte vectors
6268 are returned in memory, rather than in MMX registers. */
6271 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6274 enum machine_mode mode = type_natural_mode (type, NULL);
6277 return return_in_memory_64 (type, mode);
6279 if (mode == BLKmode)
6282 size = int_size_in_bytes (type);
6284 if (VECTOR_MODE_P (mode))
6286 /* Return in memory only if MMX registers *are* available. This
6287 seems backwards, but it is consistent with the existing
6294 else if (mode == TImode)
6296 else if (mode == XFmode)
6302 /* When returning SSE vector types, we have a choice of either
6303 (1) being abi incompatible with a -march switch, or
6304 (2) generating an error.
6305 Given no good solution, I think the safest thing is one warning.
6306 The user won't be able to use -Werror, but....
6308 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6309 called in response to actually generating a caller or callee that
6310 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6311 via aggregate_value_p for general type probing from tree-ssa. */
6314 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6316 static bool warnedsse, warnedmmx;
6318 if (!TARGET_64BIT && type)
6320 /* Look at the return type of the function, not the function type. */
6321 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6323 if (!TARGET_SSE && !warnedsse)
6326 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6329 warning (0, "SSE vector return without SSE enabled "
6334 if (!TARGET_MMX && !warnedmmx)
6336 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6339 warning (0, "MMX vector return without MMX enabled "
6349 /* Create the va_list data type. */
6351 /* Returns the calling convention specific va_list date type.
6352 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6355 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6357 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6359 /* For i386 we use plain pointer to argument area. */
6360 if (!TARGET_64BIT || abi == MS_ABI)
6361 return build_pointer_type (char_type_node);
6363 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6364 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6366 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6367 unsigned_type_node);
6368 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6369 unsigned_type_node);
6370 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6372 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6375 va_list_gpr_counter_field = f_gpr;
6376 va_list_fpr_counter_field = f_fpr;
6378 DECL_FIELD_CONTEXT (f_gpr) = record;
6379 DECL_FIELD_CONTEXT (f_fpr) = record;
6380 DECL_FIELD_CONTEXT (f_ovf) = record;
6381 DECL_FIELD_CONTEXT (f_sav) = record;
6383 TREE_CHAIN (record) = type_decl;
6384 TYPE_NAME (record) = type_decl;
6385 TYPE_FIELDS (record) = f_gpr;
6386 TREE_CHAIN (f_gpr) = f_fpr;
6387 TREE_CHAIN (f_fpr) = f_ovf;
6388 TREE_CHAIN (f_ovf) = f_sav;
6390 layout_type (record);
6392 /* The correct type is an array type of one element. */
6393 return build_array_type (record, build_index_type (size_zero_node));
6396 /* Setup the builtin va_list data type and for 64-bit the additional
6397 calling convention specific va_list data types. */
6400 ix86_build_builtin_va_list (void)
6402 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6404 /* Initialize abi specific va_list builtin types. */
6408 if (ix86_abi == MS_ABI)
6410 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6411 if (TREE_CODE (t) != RECORD_TYPE)
6412 t = build_variant_type_copy (t);
6413 sysv_va_list_type_node = t;
6418 if (TREE_CODE (t) != RECORD_TYPE)
6419 t = build_variant_type_copy (t);
6420 sysv_va_list_type_node = t;
6422 if (ix86_abi != MS_ABI)
6424 t = ix86_build_builtin_va_list_abi (MS_ABI);
6425 if (TREE_CODE (t) != RECORD_TYPE)
6426 t = build_variant_type_copy (t);
6427 ms_va_list_type_node = t;
6432 if (TREE_CODE (t) != RECORD_TYPE)
6433 t = build_variant_type_copy (t);
6434 ms_va_list_type_node = t;
6441 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6444 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6453 int regparm = ix86_regparm;
6455 if (cum->call_abi != ix86_abi)
6456 regparm = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6458 /* GPR size of varargs save area. */
6459 if (cfun->va_list_gpr_size)
6460 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6462 ix86_varargs_gpr_size = 0;
6464 /* FPR size of varargs save area. We don't need it if we don't pass
6465 anything in SSE registers. */
6466 if (cum->sse_nregs && cfun->va_list_fpr_size)
6467 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6469 ix86_varargs_fpr_size = 0;
6471 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6474 save_area = frame_pointer_rtx;
6475 set = get_varargs_alias_set ();
6477 for (i = cum->regno;
6479 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6482 mem = gen_rtx_MEM (Pmode,
6483 plus_constant (save_area, i * UNITS_PER_WORD));
6484 MEM_NOTRAP_P (mem) = 1;
6485 set_mem_alias_set (mem, set);
6486 emit_move_insn (mem, gen_rtx_REG (Pmode,
6487 x86_64_int_parameter_registers[i]));
6490 if (ix86_varargs_fpr_size)
6492 /* Now emit code to save SSE registers. The AX parameter contains number
6493 of SSE parameter registers used to call this function. We use
6494 sse_prologue_save insn template that produces computed jump across
6495 SSE saves. We need some preparation work to get this working. */
6497 label = gen_label_rtx ();
6498 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6500 /* Compute address to jump to :
6501 label - eax*4 + nnamed_sse_arguments*4 Or
6502 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6503 tmp_reg = gen_reg_rtx (Pmode);
6504 nsse_reg = gen_reg_rtx (Pmode);
6505 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6506 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6507 gen_rtx_MULT (Pmode, nsse_reg,
6510 /* vmovaps is one byte longer than movaps. */
6512 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6513 gen_rtx_PLUS (Pmode, tmp_reg,
6519 gen_rtx_CONST (DImode,
6520 gen_rtx_PLUS (DImode,
6522 GEN_INT (cum->sse_regno
6523 * (TARGET_AVX ? 5 : 4)))));
6525 emit_move_insn (nsse_reg, label_ref);
6526 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6528 /* Compute address of memory block we save into. We always use pointer
6529 pointing 127 bytes after first byte to store - this is needed to keep
6530 instruction size limited by 4 bytes (5 bytes for AVX) with one
6531 byte displacement. */
6532 tmp_reg = gen_reg_rtx (Pmode);
6533 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6534 plus_constant (save_area,
6535 ix86_varargs_gpr_size + 127)));
6536 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6537 MEM_NOTRAP_P (mem) = 1;
6538 set_mem_alias_set (mem, set);
6539 set_mem_align (mem, BITS_PER_WORD);
6541 /* And finally do the dirty job! */
6542 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6543 GEN_INT (cum->sse_regno), label));
6548 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6550 alias_set_type set = get_varargs_alias_set ();
6553 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6557 mem = gen_rtx_MEM (Pmode,
6558 plus_constant (virtual_incoming_args_rtx,
6559 i * UNITS_PER_WORD));
6560 MEM_NOTRAP_P (mem) = 1;
6561 set_mem_alias_set (mem, set);
6563 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6564 emit_move_insn (mem, reg);
6569 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6570 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6573 CUMULATIVE_ARGS next_cum;
6576 /* This argument doesn't appear to be used anymore. Which is good,
6577 because the old code here didn't suppress rtl generation. */
6578 gcc_assert (!no_rtl);
6583 fntype = TREE_TYPE (current_function_decl);
6585 /* For varargs, we do not want to skip the dummy va_dcl argument.
6586 For stdargs, we do want to skip the last named argument. */
6588 if (stdarg_p (fntype))
6589 function_arg_advance (&next_cum, mode, type, 1);
6591 if (cum->call_abi == MS_ABI)
6592 setup_incoming_varargs_ms_64 (&next_cum);
6594 setup_incoming_varargs_64 (&next_cum);
6597 /* Checks if TYPE is of kind va_list char *. */
6600 is_va_list_char_pointer (tree type)
6604 /* For 32-bit it is always true. */
6607 canonic = ix86_canonical_va_list_type (type);
6608 return (canonic == ms_va_list_type_node
6609 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6612 /* Implement va_start. */
6615 ix86_va_start (tree valist, rtx nextarg)
6617 HOST_WIDE_INT words, n_gpr, n_fpr;
6618 tree f_gpr, f_fpr, f_ovf, f_sav;
6619 tree gpr, fpr, ovf, sav, t;
6622 /* Only 64bit target needs something special. */
6623 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6625 std_expand_builtin_va_start (valist, nextarg);
6629 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6630 f_fpr = TREE_CHAIN (f_gpr);
6631 f_ovf = TREE_CHAIN (f_fpr);
6632 f_sav = TREE_CHAIN (f_ovf);
6634 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6635 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6636 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6637 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6638 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6640 /* Count number of gp and fp argument registers used. */
6641 words = crtl->args.info.words;
6642 n_gpr = crtl->args.info.regno;
6643 n_fpr = crtl->args.info.sse_regno;
6645 if (cfun->va_list_gpr_size)
6647 type = TREE_TYPE (gpr);
6648 t = build2 (MODIFY_EXPR, type,
6649 gpr, build_int_cst (type, n_gpr * 8));
6650 TREE_SIDE_EFFECTS (t) = 1;
6651 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6654 if (TARGET_SSE && cfun->va_list_fpr_size)
6656 type = TREE_TYPE (fpr);
6657 t = build2 (MODIFY_EXPR, type, fpr,
6658 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6659 TREE_SIDE_EFFECTS (t) = 1;
6660 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6663 /* Find the overflow area. */
6664 type = TREE_TYPE (ovf);
6665 t = make_tree (type, crtl->args.internal_arg_pointer);
6667 t = build2 (POINTER_PLUS_EXPR, type, t,
6668 size_int (words * UNITS_PER_WORD));
6669 t = build2 (MODIFY_EXPR, type, ovf, t);
6670 TREE_SIDE_EFFECTS (t) = 1;
6671 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6673 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6675 /* Find the register save area.
6676 Prologue of the function save it right above stack frame. */
6677 type = TREE_TYPE (sav);
6678 t = make_tree (type, frame_pointer_rtx);
6679 if (!ix86_varargs_gpr_size)
6680 t = build2 (POINTER_PLUS_EXPR, type, t,
6681 size_int (-8 * X86_64_REGPARM_MAX));
6682 t = build2 (MODIFY_EXPR, type, sav, t);
6683 TREE_SIDE_EFFECTS (t) = 1;
6684 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6688 /* Implement va_arg. */
6691 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6694 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6695 tree f_gpr, f_fpr, f_ovf, f_sav;
6696 tree gpr, fpr, ovf, sav, t;
6698 tree lab_false, lab_over = NULL_TREE;
6703 enum machine_mode nat_mode;
6706 /* Only 64bit target needs something special. */
6707 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6708 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6710 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6711 f_fpr = TREE_CHAIN (f_gpr);
6712 f_ovf = TREE_CHAIN (f_fpr);
6713 f_sav = TREE_CHAIN (f_ovf);
6715 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6716 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6717 valist = build_va_arg_indirect_ref (valist);
6718 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6719 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6720 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6722 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6724 type = build_pointer_type (type);
6725 size = int_size_in_bytes (type);
6726 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6728 nat_mode = type_natural_mode (type, NULL);
6737 /* Unnamed 256bit vector mode parameters are passed on stack. */
6738 if (ix86_cfun_abi () == SYSV_ABI)
6745 container = construct_container (nat_mode, TYPE_MODE (type),
6746 type, 0, X86_64_REGPARM_MAX,
6747 X86_64_SSE_REGPARM_MAX, intreg,
6752 /* Pull the value out of the saved registers. */
6754 addr = create_tmp_var (ptr_type_node, "addr");
6755 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6759 int needed_intregs, needed_sseregs;
6761 tree int_addr, sse_addr;
6763 lab_false = create_artificial_label ();
6764 lab_over = create_artificial_label ();
6766 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6768 need_temp = (!REG_P (container)
6769 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6770 || TYPE_ALIGN (type) > 128));
6772 /* In case we are passing structure, verify that it is consecutive block
6773 on the register save area. If not we need to do moves. */
6774 if (!need_temp && !REG_P (container))
6776 /* Verify that all registers are strictly consecutive */
6777 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6781 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6783 rtx slot = XVECEXP (container, 0, i);
6784 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6785 || INTVAL (XEXP (slot, 1)) != i * 16)
6793 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6795 rtx slot = XVECEXP (container, 0, i);
6796 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6797 || INTVAL (XEXP (slot, 1)) != i * 8)
6809 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6810 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6811 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6812 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6815 /* First ensure that we fit completely in registers. */
6818 t = build_int_cst (TREE_TYPE (gpr),
6819 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6820 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6821 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6822 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6823 gimplify_and_add (t, pre_p);
6827 t = build_int_cst (TREE_TYPE (fpr),
6828 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6829 + X86_64_REGPARM_MAX * 8);
6830 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6831 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6832 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6833 gimplify_and_add (t, pre_p);
6836 /* Compute index to start of area used for integer regs. */
6839 /* int_addr = gpr + sav; */
6840 t = fold_convert (sizetype, gpr);
6841 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6842 gimplify_assign (int_addr, t, pre_p);
6846 /* sse_addr = fpr + sav; */
6847 t = fold_convert (sizetype, fpr);
6848 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6849 gimplify_assign (sse_addr, t, pre_p);
6854 tree temp = create_tmp_var (type, "va_arg_tmp");
6857 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6858 gimplify_assign (addr, t, pre_p);
6860 for (i = 0; i < XVECLEN (container, 0); i++)
6862 rtx slot = XVECEXP (container, 0, i);
6863 rtx reg = XEXP (slot, 0);
6864 enum machine_mode mode = GET_MODE (reg);
6865 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6866 tree addr_type = build_pointer_type (piece_type);
6867 tree daddr_type = build_pointer_type_for_mode (piece_type,
6871 tree dest_addr, dest;
6873 if (SSE_REGNO_P (REGNO (reg)))
6875 src_addr = sse_addr;
6876 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6880 src_addr = int_addr;
6881 src_offset = REGNO (reg) * 8;
6883 src_addr = fold_convert (addr_type, src_addr);
6884 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6885 size_int (src_offset));
6886 src = build_va_arg_indirect_ref (src_addr);
6888 dest_addr = fold_convert (daddr_type, addr);
6889 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6890 size_int (INTVAL (XEXP (slot, 1))));
6891 dest = build_va_arg_indirect_ref (dest_addr);
6893 gimplify_assign (dest, src, pre_p);
6899 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6900 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6901 gimplify_assign (gpr, t, pre_p);
6906 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6907 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6908 gimplify_assign (fpr, t, pre_p);
6911 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6913 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6916 /* ... otherwise out of the overflow area. */
6918 /* When we align parameter on stack for caller, if the parameter
6919 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6920 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6921 here with caller. */
6922 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6923 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6924 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6926 /* Care for on-stack alignment if needed. */
6927 if (arg_boundary <= 64
6928 || integer_zerop (TYPE_SIZE (type)))
6932 HOST_WIDE_INT align = arg_boundary / 8;
6933 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6934 size_int (align - 1));
6935 t = fold_convert (sizetype, t);
6936 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6938 t = fold_convert (TREE_TYPE (ovf), t);
6940 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6941 gimplify_assign (addr, t, pre_p);
6943 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6944 size_int (rsize * UNITS_PER_WORD));
6945 gimplify_assign (unshare_expr (ovf), t, pre_p);
6948 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6950 ptrtype = build_pointer_type (type);
6951 addr = fold_convert (ptrtype, addr);
6954 addr = build_va_arg_indirect_ref (addr);
6955 return build_va_arg_indirect_ref (addr);
6958 /* Return nonzero if OPNUM's MEM should be matched
6959 in movabs* patterns. */
6962 ix86_check_movabs (rtx insn, int opnum)
6966 set = PATTERN (insn);
6967 if (GET_CODE (set) == PARALLEL)
6968 set = XVECEXP (set, 0, 0);
6969 gcc_assert (GET_CODE (set) == SET);
6970 mem = XEXP (set, opnum);
6971 while (GET_CODE (mem) == SUBREG)
6972 mem = SUBREG_REG (mem);
6973 gcc_assert (MEM_P (mem));
6974 return (volatile_ok || !MEM_VOLATILE_P (mem));
6977 /* Initialize the table of extra 80387 mathematical constants. */
6980 init_ext_80387_constants (void)
6982 static const char * cst[5] =
6984 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6985 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6986 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6987 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6988 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6992 for (i = 0; i < 5; i++)
6994 real_from_string (&ext_80387_constants_table[i], cst[i]);
6995 /* Ensure each constant is rounded to XFmode precision. */
6996 real_convert (&ext_80387_constants_table[i],
6997 XFmode, &ext_80387_constants_table[i]);
7000 ext_80387_constants_init = 1;
7003 /* Return true if the constant is something that can be loaded with
7004 a special instruction. */
7007 standard_80387_constant_p (rtx x)
7009 enum machine_mode mode = GET_MODE (x);
7013 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7016 if (x == CONST0_RTX (mode))
7018 if (x == CONST1_RTX (mode))
7021 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7023 /* For XFmode constants, try to find a special 80387 instruction when
7024 optimizing for size or on those CPUs that benefit from them. */
7026 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7030 if (! ext_80387_constants_init)
7031 init_ext_80387_constants ();
7033 for (i = 0; i < 5; i++)
7034 if (real_identical (&r, &ext_80387_constants_table[i]))
7038 /* Load of the constant -0.0 or -1.0 will be split as
7039 fldz;fchs or fld1;fchs sequence. */
7040 if (real_isnegzero (&r))
7042 if (real_identical (&r, &dconstm1))
7048 /* Return the opcode of the special instruction to be used to load
7052 standard_80387_constant_opcode (rtx x)
7054 switch (standard_80387_constant_p (x))
7078 /* Return the CONST_DOUBLE representing the 80387 constant that is
7079 loaded by the specified special instruction. The argument IDX
7080 matches the return value from standard_80387_constant_p. */
7083 standard_80387_constant_rtx (int idx)
7087 if (! ext_80387_constants_init)
7088 init_ext_80387_constants ();
7104 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7108 /* Return 1 if mode is a valid mode for sse. */
7110 standard_sse_mode_p (enum machine_mode mode)
7127 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7128 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7129 modes and AVX is enabled. */
7132 standard_sse_constant_p (rtx x)
7134 enum machine_mode mode = GET_MODE (x);
7136 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7138 if (vector_all_ones_operand (x, mode))
7140 if (standard_sse_mode_p (mode))
7141 return TARGET_SSE2 ? 2 : -2;
7142 else if (VALID_AVX256_REG_MODE (mode))
7143 return TARGET_AVX ? 3 : -3;
7149 /* Return the opcode of the special instruction to be used to load
7153 standard_sse_constant_opcode (rtx insn, rtx x)
7155 switch (standard_sse_constant_p (x))
7158 switch (get_attr_mode (insn))
7161 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7163 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7165 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7167 return "vxorps\t%x0, %x0, %x0";
7169 return "vxorpd\t%x0, %x0, %x0";
7171 return "vpxor\t%x0, %x0, %x0";
7177 switch (get_attr_mode (insn))
7182 return "vpcmpeqd\t%0, %0, %0";
7188 return "pcmpeqd\t%0, %0";
7193 /* Returns 1 if OP contains a symbol reference */
7196 symbolic_reference_mentioned_p (rtx op)
7201 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7204 fmt = GET_RTX_FORMAT (GET_CODE (op));
7205 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7211 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7212 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7216 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7223 /* Return 1 if it is appropriate to emit `ret' instructions in the
7224 body of a function. Do this only if the epilogue is simple, needing a
7225 couple of insns. Prior to reloading, we can't tell how many registers
7226 must be saved, so return 0 then. Return 0 if there is no frame
7227 marker to de-allocate. */
7230 ix86_can_use_return_insn_p (void)
7232 struct ix86_frame frame;
7234 if (! reload_completed || frame_pointer_needed)
7237 /* Don't allow more than 32 pop, since that's all we can do
7238 with one instruction. */
7239 if (crtl->args.pops_args
7240 && crtl->args.size >= 32768)
7243 ix86_compute_frame_layout (&frame);
7244 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7247 /* Value should be nonzero if functions must have frame pointers.
7248 Zero means the frame pointer need not be set up (and parms may
7249 be accessed via the stack pointer) in functions that seem suitable. */
7252 ix86_frame_pointer_required (void)
7254 /* If we accessed previous frames, then the generated code expects
7255 to be able to access the saved ebp value in our frame. */
7256 if (cfun->machine->accesses_prev_frame)
7259 /* Several x86 os'es need a frame pointer for other reasons,
7260 usually pertaining to setjmp. */
7261 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7264 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7265 the frame pointer by default. Turn it back on now if we've not
7266 got a leaf function. */
7267 if (TARGET_OMIT_LEAF_FRAME_POINTER
7268 && (!current_function_is_leaf
7269 || ix86_current_function_calls_tls_descriptor))
7278 /* Record that the current function accesses previous call frames. */
7281 ix86_setup_frame_addresses (void)
7283 cfun->machine->accesses_prev_frame = 1;
7286 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7287 # define USE_HIDDEN_LINKONCE 1
7289 # define USE_HIDDEN_LINKONCE 0
7292 static int pic_labels_used;
7294 /* Fills in the label name that should be used for a pc thunk for
7295 the given register. */
7298 get_pc_thunk_name (char name[32], unsigned int regno)
7300 gcc_assert (!TARGET_64BIT);
7302 if (USE_HIDDEN_LINKONCE)
7303 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7305 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7309 /* This function generates code for -fpic that loads %ebx with
7310 the return address of the caller and then returns. */
7313 ix86_file_end (void)
7318 for (regno = 0; regno < 8; ++regno)
7322 if (! ((pic_labels_used >> regno) & 1))
7325 get_pc_thunk_name (name, regno);
7330 switch_to_section (darwin_sections[text_coal_section]);
7331 fputs ("\t.weak_definition\t", asm_out_file);
7332 assemble_name (asm_out_file, name);
7333 fputs ("\n\t.private_extern\t", asm_out_file);
7334 assemble_name (asm_out_file, name);
7335 fputs ("\n", asm_out_file);
7336 ASM_OUTPUT_LABEL (asm_out_file, name);
7340 if (USE_HIDDEN_LINKONCE)
7344 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7346 TREE_PUBLIC (decl) = 1;
7347 TREE_STATIC (decl) = 1;
7348 DECL_ONE_ONLY (decl) = 1;
7350 (*targetm.asm_out.unique_section) (decl, 0);
7351 switch_to_section (get_named_section (decl, NULL, 0));
7353 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7354 fputs ("\t.hidden\t", asm_out_file);
7355 assemble_name (asm_out_file, name);
7356 fputc ('\n', asm_out_file);
7357 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7361 switch_to_section (text_section);
7362 ASM_OUTPUT_LABEL (asm_out_file, name);
7365 xops[0] = gen_rtx_REG (Pmode, regno);
7366 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7367 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7368 output_asm_insn ("ret", xops);
7371 if (NEED_INDICATE_EXEC_STACK)
7372 file_end_indicate_exec_stack ();
7375 /* Emit code for the SET_GOT patterns. */
7378 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7384 if (TARGET_VXWORKS_RTP && flag_pic)
7386 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7387 xops[2] = gen_rtx_MEM (Pmode,
7388 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7389 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7391 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7392 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7393 an unadorned address. */
7394 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7395 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7396 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7400 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7402 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7404 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7407 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7409 output_asm_insn ("call\t%a2", xops);
7412 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7413 is what will be referenced by the Mach-O PIC subsystem. */
7415 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7418 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7419 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7422 output_asm_insn ("pop%z0\t%0", xops);
7427 get_pc_thunk_name (name, REGNO (dest));
7428 pic_labels_used |= 1 << REGNO (dest);
7430 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7431 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7432 output_asm_insn ("call\t%X2", xops);
7433 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7434 is what will be referenced by the Mach-O PIC subsystem. */
7437 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7439 targetm.asm_out.internal_label (asm_out_file, "L",
7440 CODE_LABEL_NUMBER (label));
7447 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7448 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7450 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7455 /* Generate an "push" pattern for input ARG. */
7460 return gen_rtx_SET (VOIDmode,
7462 gen_rtx_PRE_DEC (Pmode,
7463 stack_pointer_rtx)),
7467 /* Return >= 0 if there is an unused call-clobbered register available
7468 for the entire function. */
7471 ix86_select_alt_pic_regnum (void)
7473 if (current_function_is_leaf && !crtl->profile
7474 && !ix86_current_function_calls_tls_descriptor)
7477 /* Can't use the same register for both PIC and DRAP. */
7479 drap = REGNO (crtl->drap_reg);
7482 for (i = 2; i >= 0; --i)
7483 if (i != drap && !df_regs_ever_live_p (i))
7487 return INVALID_REGNUM;
7490 /* Return 1 if we need to save REGNO. */
7492 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7494 if (pic_offset_table_rtx
7495 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7496 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7498 || crtl->calls_eh_return
7499 || crtl->uses_const_pool))
7501 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7506 if (crtl->calls_eh_return && maybe_eh_return)
7511 unsigned test = EH_RETURN_DATA_REGNO (i);
7512 if (test == INVALID_REGNUM)
7520 && regno == REGNO (crtl->drap_reg))
7523 return (df_regs_ever_live_p (regno)
7524 && !call_used_regs[regno]
7525 && !fixed_regs[regno]
7526 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7529 /* Return number of saved general prupose registers. */
7532 ix86_nsaved_regs (void)
7537 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7538 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7543 /* Return number of saved SSE registrers. */
7546 ix86_nsaved_sseregs (void)
7551 if (ix86_cfun_abi () != MS_ABI)
7553 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7554 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7559 /* Given FROM and TO register numbers, say whether this elimination is
7560 allowed. If stack alignment is needed, we can only replace argument
7561 pointer with hard frame pointer, or replace frame pointer with stack
7562 pointer. Otherwise, frame pointer elimination is automatically
7563 handled and all other eliminations are valid. */
7566 ix86_can_eliminate (int from, int to)
7568 if (stack_realign_fp)
7569 return ((from == ARG_POINTER_REGNUM
7570 && to == HARD_FRAME_POINTER_REGNUM)
7571 || (from == FRAME_POINTER_REGNUM
7572 && to == STACK_POINTER_REGNUM));
7574 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7577 /* Return the offset between two registers, one to be eliminated, and the other
7578 its replacement, at the start of a routine. */
7581 ix86_initial_elimination_offset (int from, int to)
7583 struct ix86_frame frame;
7584 ix86_compute_frame_layout (&frame);
7586 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7587 return frame.hard_frame_pointer_offset;
7588 else if (from == FRAME_POINTER_REGNUM
7589 && to == HARD_FRAME_POINTER_REGNUM)
7590 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7593 gcc_assert (to == STACK_POINTER_REGNUM);
7595 if (from == ARG_POINTER_REGNUM)
7596 return frame.stack_pointer_offset;
7598 gcc_assert (from == FRAME_POINTER_REGNUM);
7599 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7603 /* In a dynamically-aligned function, we can't know the offset from
7604 stack pointer to frame pointer, so we must ensure that setjmp
7605 eliminates fp against the hard fp (%ebp) rather than trying to
7606 index from %esp up to the top of the frame across a gap that is
7607 of unknown (at compile-time) size. */
7609 ix86_builtin_setjmp_frame_value (void)
7611 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7614 /* Fill structure ix86_frame about frame of currently computed function. */
7617 ix86_compute_frame_layout (struct ix86_frame *frame)
7619 HOST_WIDE_INT total_size;
7620 unsigned int stack_alignment_needed;
7621 HOST_WIDE_INT offset;
7622 unsigned int preferred_alignment;
7623 HOST_WIDE_INT size = get_frame_size ();
7625 frame->nregs = ix86_nsaved_regs ();
7626 frame->nsseregs = ix86_nsaved_sseregs ();
7629 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7630 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7632 /* MS ABI seem to require stack alignment to be always 16 except for function
7634 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7636 preferred_alignment = 16;
7637 stack_alignment_needed = 16;
7638 crtl->preferred_stack_boundary = 128;
7639 crtl->stack_alignment_needed = 128;
7642 gcc_assert (!size || stack_alignment_needed);
7643 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7644 gcc_assert (preferred_alignment <= stack_alignment_needed);
7646 /* During reload iteration the amount of registers saved can change.
7647 Recompute the value as needed. Do not recompute when amount of registers
7648 didn't change as reload does multiple calls to the function and does not
7649 expect the decision to change within single iteration. */
7650 if (!optimize_function_for_size_p (cfun)
7651 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7653 int count = frame->nregs;
7655 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7656 /* The fast prologue uses move instead of push to save registers. This
7657 is significantly longer, but also executes faster as modern hardware
7658 can execute the moves in parallel, but can't do that for push/pop.
7660 Be careful about choosing what prologue to emit: When function takes
7661 many instructions to execute we may use slow version as well as in
7662 case function is known to be outside hot spot (this is known with
7663 feedback only). Weight the size of function by number of registers
7664 to save as it is cheap to use one or two push instructions but very
7665 slow to use many of them. */
7667 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7668 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7669 || (flag_branch_probabilities
7670 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7671 cfun->machine->use_fast_prologue_epilogue = false;
7673 cfun->machine->use_fast_prologue_epilogue
7674 = !expensive_function_p (count);
7676 if (TARGET_PROLOGUE_USING_MOVE
7677 && cfun->machine->use_fast_prologue_epilogue)
7678 frame->save_regs_using_mov = true;
7680 frame->save_regs_using_mov = false;
7683 /* Skip return address and saved base pointer. */
7684 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7686 frame->hard_frame_pointer_offset = offset;
7688 /* Set offset to aligned because the realigned frame starts from
7690 if (stack_realign_fp)
7691 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7693 /* Register save area */
7694 offset += frame->nregs * UNITS_PER_WORD;
7696 /* Align SSE reg save area. */
7697 if (frame->nsseregs)
7698 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7700 frame->padding0 = 0;
7702 /* SSE register save area. */
7703 offset += frame->padding0 + frame->nsseregs * 16;
7706 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7707 offset += frame->va_arg_size;
7709 /* Align start of frame for local function. */
7710 frame->padding1 = ((offset + stack_alignment_needed - 1)
7711 & -stack_alignment_needed) - offset;
7713 offset += frame->padding1;
7715 /* Frame pointer points here. */
7716 frame->frame_pointer_offset = offset;
7720 /* Add outgoing arguments area. Can be skipped if we eliminated
7721 all the function calls as dead code.
7722 Skipping is however impossible when function calls alloca. Alloca
7723 expander assumes that last crtl->outgoing_args_size
7724 of stack frame are unused. */
7725 if (ACCUMULATE_OUTGOING_ARGS
7726 && (!current_function_is_leaf || cfun->calls_alloca
7727 || ix86_current_function_calls_tls_descriptor))
7729 offset += crtl->outgoing_args_size;
7730 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7733 frame->outgoing_arguments_size = 0;
7735 /* Align stack boundary. Only needed if we're calling another function
7737 if (!current_function_is_leaf || cfun->calls_alloca
7738 || ix86_current_function_calls_tls_descriptor)
7739 frame->padding2 = ((offset + preferred_alignment - 1)
7740 & -preferred_alignment) - offset;
7742 frame->padding2 = 0;
7744 offset += frame->padding2;
7746 /* We've reached end of stack frame. */
7747 frame->stack_pointer_offset = offset;
7749 /* Size prologue needs to allocate. */
7750 frame->to_allocate =
7751 (size + frame->padding1 + frame->padding2
7752 + frame->outgoing_arguments_size + frame->va_arg_size);
7754 if ((!frame->to_allocate && frame->nregs <= 1)
7755 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7756 frame->save_regs_using_mov = false;
7758 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7759 && current_function_is_leaf
7760 && !ix86_current_function_calls_tls_descriptor)
7762 frame->red_zone_size = frame->to_allocate;
7763 if (frame->save_regs_using_mov)
7764 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7765 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7766 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7769 frame->red_zone_size = 0;
7770 frame->to_allocate -= frame->red_zone_size;
7771 frame->stack_pointer_offset -= frame->red_zone_size;
7773 fprintf (stderr, "\n");
7774 fprintf (stderr, "size: %ld\n", (long)size);
7775 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7776 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7777 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7778 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7779 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7780 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7781 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7782 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7783 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7784 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7785 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7786 (long)frame->hard_frame_pointer_offset);
7787 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7788 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7789 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7790 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7794 /* Emit code to save registers in the prologue. */
7797 ix86_emit_save_regs (void)
7802 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7803 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7805 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7806 RTX_FRAME_RELATED_P (insn) = 1;
7810 /* Emit code to save registers using MOV insns. First register
7811 is restored from POINTER + OFFSET. */
7813 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7818 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7819 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7821 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7823 gen_rtx_REG (Pmode, regno));
7824 RTX_FRAME_RELATED_P (insn) = 1;
7825 offset += UNITS_PER_WORD;
7829 /* Emit code to save registers using MOV insns. First register
7830 is restored from POINTER + OFFSET. */
7832 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7838 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7839 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7841 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7842 set_mem_align (mem, 128);
7843 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7844 RTX_FRAME_RELATED_P (insn) = 1;
7849 /* Expand prologue or epilogue stack adjustment.
7850 The pattern exist to put a dependency on all ebp-based memory accesses.
7851 STYLE should be negative if instructions should be marked as frame related,
7852 zero if %r11 register is live and cannot be freely used and positive
7856 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7861 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7862 else if (x86_64_immediate_operand (offset, DImode))
7863 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7867 /* r11 is used by indirect sibcall return as well, set before the
7868 epilogue and used after the epilogue. ATM indirect sibcall
7869 shouldn't be used together with huge frame sizes in one
7870 function because of the frame_size check in sibcall.c. */
7872 r11 = gen_rtx_REG (DImode, R11_REG);
7873 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7875 RTX_FRAME_RELATED_P (insn) = 1;
7876 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7880 RTX_FRAME_RELATED_P (insn) = 1;
7883 /* Find an available register to be used as dynamic realign argument
7884 pointer regsiter. Such a register will be written in prologue and
7885 used in begin of body, so it must not be
7886 1. parameter passing register.
7888 We reuse static-chain register if it is available. Otherwise, we
7889 use DI for i386 and R13 for x86-64. We chose R13 since it has
7892 Return: the regno of chosen register. */
7895 find_drap_reg (void)
7897 tree decl = cfun->decl;
7901 /* Use R13 for nested function or function need static chain.
7902 Since function with tail call may use any caller-saved
7903 registers in epilogue, DRAP must not use caller-saved
7904 register in such case. */
7905 if ((decl_function_context (decl)
7906 && !DECL_NO_STATIC_CHAIN (decl))
7907 || crtl->tail_call_emit)
7914 /* Use DI for nested function or function need static chain.
7915 Since function with tail call may use any caller-saved
7916 registers in epilogue, DRAP must not use caller-saved
7917 register in such case. */
7918 if ((decl_function_context (decl)
7919 && !DECL_NO_STATIC_CHAIN (decl))
7920 || crtl->tail_call_emit)
7923 /* Reuse static chain register if it isn't used for parameter
7925 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7926 && !lookup_attribute ("fastcall",
7927 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7934 /* Update incoming stack boundary and estimated stack alignment. */
7937 ix86_update_stack_boundary (void)
7939 /* Prefer the one specified at command line. */
7940 ix86_incoming_stack_boundary
7941 = (ix86_user_incoming_stack_boundary
7942 ? ix86_user_incoming_stack_boundary
7943 : ix86_default_incoming_stack_boundary);
7945 /* Incoming stack alignment can be changed on individual functions
7946 via force_align_arg_pointer attribute. We use the smallest
7947 incoming stack boundary. */
7948 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7949 && lookup_attribute (ix86_force_align_arg_pointer_string,
7950 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7951 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7953 /* The incoming stack frame has to be aligned at least at
7954 parm_stack_boundary. */
7955 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
7956 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
7958 /* Stack at entrance of main is aligned by runtime. We use the
7959 smallest incoming stack boundary. */
7960 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7961 && DECL_NAME (current_function_decl)
7962 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7963 && DECL_FILE_SCOPE_P (current_function_decl))
7964 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7966 /* x86_64 vararg needs 16byte stack alignment for register save
7970 && crtl->stack_alignment_estimated < 128)
7971 crtl->stack_alignment_estimated = 128;
7974 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7975 needed or an rtx for DRAP otherwise. */
7978 ix86_get_drap_rtx (void)
7980 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7981 crtl->need_drap = true;
7983 if (stack_realign_drap)
7985 /* Assign DRAP to vDRAP and returns vDRAP */
7986 unsigned int regno = find_drap_reg ();
7991 arg_ptr = gen_rtx_REG (Pmode, regno);
7992 crtl->drap_reg = arg_ptr;
7995 drap_vreg = copy_to_reg (arg_ptr);
7999 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8000 RTX_FRAME_RELATED_P (insn) = 1;
8007 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8010 ix86_internal_arg_pointer (void)
8012 return virtual_incoming_args_rtx;
8015 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8016 This is called from dwarf2out.c to emit call frame instructions
8017 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8019 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8021 rtx unspec = SET_SRC (pattern);
8022 gcc_assert (GET_CODE (unspec) == UNSPEC);
8026 case UNSPEC_REG_SAVE:
8027 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8028 SET_DEST (pattern));
8030 case UNSPEC_DEF_CFA:
8031 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8032 INTVAL (XVECEXP (unspec, 0, 0)));
8039 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8040 to be generated in correct form. */
8042 ix86_finalize_stack_realign_flags (void)
8044 /* Check if stack realign is really needed after reload, and
8045 stores result in cfun */
8046 unsigned int incoming_stack_boundary
8047 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8048 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8049 unsigned int stack_realign = (incoming_stack_boundary
8050 < (current_function_is_leaf
8051 ? crtl->max_used_stack_slot_alignment
8052 : crtl->stack_alignment_needed));
8054 if (crtl->stack_realign_finalized)
8056 /* After stack_realign_needed is finalized, we can't no longer
8058 gcc_assert (crtl->stack_realign_needed == stack_realign);
8062 crtl->stack_realign_needed = stack_realign;
8063 crtl->stack_realign_finalized = true;
8067 /* Expand the prologue into a bunch of separate insns. */
8070 ix86_expand_prologue (void)
8074 struct ix86_frame frame;
8075 HOST_WIDE_INT allocate;
8077 ix86_finalize_stack_realign_flags ();
8079 /* DRAP should not coexist with stack_realign_fp */
8080 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8082 ix86_compute_frame_layout (&frame);
8084 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8085 of DRAP is needed and stack realignment is really needed after reload */
8086 if (crtl->drap_reg && crtl->stack_realign_needed)
8089 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8090 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8091 ? 0 : UNITS_PER_WORD);
8093 gcc_assert (stack_realign_drap);
8095 /* Grab the argument pointer. */
8096 x = plus_constant (stack_pointer_rtx,
8097 (UNITS_PER_WORD + param_ptr_offset));
8100 /* Only need to push parameter pointer reg if it is caller
8102 if (!call_used_regs[REGNO (crtl->drap_reg)])
8104 /* Push arg pointer reg */
8105 insn = emit_insn (gen_push (y));
8106 RTX_FRAME_RELATED_P (insn) = 1;
8109 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8110 RTX_FRAME_RELATED_P (insn) = 1;
8112 /* Align the stack. */
8113 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8115 GEN_INT (-align_bytes)));
8116 RTX_FRAME_RELATED_P (insn) = 1;
8118 /* Replicate the return address on the stack so that return
8119 address can be reached via (argp - 1) slot. This is needed
8120 to implement macro RETURN_ADDR_RTX and intrinsic function
8121 expand_builtin_return_addr etc. */
8123 x = gen_frame_mem (Pmode,
8124 plus_constant (x, -UNITS_PER_WORD));
8125 insn = emit_insn (gen_push (x));
8126 RTX_FRAME_RELATED_P (insn) = 1;
8129 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8130 slower on all targets. Also sdb doesn't like it. */
8132 if (frame_pointer_needed)
8134 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8135 RTX_FRAME_RELATED_P (insn) = 1;
8137 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8138 RTX_FRAME_RELATED_P (insn) = 1;
8141 if (stack_realign_fp)
8143 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8144 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8146 /* Align the stack. */
8147 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8149 GEN_INT (-align_bytes)));
8150 RTX_FRAME_RELATED_P (insn) = 1;
8153 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8155 if (!frame.save_regs_using_mov)
8156 ix86_emit_save_regs ();
8158 allocate += frame.nregs * UNITS_PER_WORD;
8160 /* When using red zone we may start register saving before allocating
8161 the stack frame saving one cycle of the prologue. However I will
8162 avoid doing this if I am going to have to probe the stack since
8163 at least on x86_64 the stack probe can turn into a call that clobbers
8164 a red zone location */
8165 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8166 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8167 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8168 && !crtl->stack_realign_needed)
8169 ? hard_frame_pointer_rtx
8170 : stack_pointer_rtx,
8171 -frame.nregs * UNITS_PER_WORD);
8175 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8176 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8177 GEN_INT (-allocate), -1);
8180 /* Only valid for Win32. */
8181 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8185 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8187 if (cfun->machine->call_abi == MS_ABI)
8190 eax_live = ix86_eax_live_at_start_p ();
8194 emit_insn (gen_push (eax));
8195 allocate -= UNITS_PER_WORD;
8198 emit_move_insn (eax, GEN_INT (allocate));
8201 insn = gen_allocate_stack_worker_64 (eax, eax);
8203 insn = gen_allocate_stack_worker_32 (eax, eax);
8204 insn = emit_insn (insn);
8205 RTX_FRAME_RELATED_P (insn) = 1;
8206 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8207 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8208 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8209 t, REG_NOTES (insn));
8213 if (frame_pointer_needed)
8214 t = plus_constant (hard_frame_pointer_rtx,
8217 - frame.nregs * UNITS_PER_WORD);
8219 t = plus_constant (stack_pointer_rtx, allocate);
8220 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8224 if (frame.save_regs_using_mov
8225 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8226 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8228 if (!frame_pointer_needed
8229 || !frame.to_allocate
8230 || crtl->stack_realign_needed)
8231 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8233 + frame.nsseregs * 16 + frame.padding0);
8235 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8236 -frame.nregs * UNITS_PER_WORD);
8238 if (!frame_pointer_needed
8239 || !frame.to_allocate
8240 || crtl->stack_realign_needed)
8241 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8244 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8245 - frame.nregs * UNITS_PER_WORD
8246 - frame.nsseregs * 16
8249 pic_reg_used = false;
8250 if (pic_offset_table_rtx
8251 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8254 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8256 if (alt_pic_reg_used != INVALID_REGNUM)
8257 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8259 pic_reg_used = true;
8266 if (ix86_cmodel == CM_LARGE_PIC)
8268 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8269 rtx label = gen_label_rtx ();
8271 LABEL_PRESERVE_P (label) = 1;
8272 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8273 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8274 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8275 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8276 pic_offset_table_rtx, tmp_reg));
8279 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8282 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8285 /* In the pic_reg_used case, make sure that the got load isn't deleted
8286 when mcount needs it. Blockage to avoid call movement across mcount
8287 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8289 if (crtl->profile && pic_reg_used)
8290 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8292 if (crtl->drap_reg && !crtl->stack_realign_needed)
8294 /* vDRAP is setup but after reload it turns out stack realign
8295 isn't necessary, here we will emit prologue to setup DRAP
8296 without stack realign adjustment */
8297 int drap_bp_offset = UNITS_PER_WORD * 2;
8298 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8299 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8302 /* Prevent instructions from being scheduled into register save push
8303 sequence when access to the redzone area is done through frame pointer.
8304 The offset betweeh the frame pointer and the stack pointer is calculated
8305 relative to the value of the stack pointer at the end of the function
8306 prologue, and moving instructions that access redzone area via frame
8307 pointer inside push sequence violates this assumption. */
8308 if (frame_pointer_needed && frame.red_zone_size)
8309 emit_insn (gen_memory_blockage ());
8311 /* Emit cld instruction if stringops are used in the function. */
8312 if (TARGET_CLD && ix86_current_function_needs_cld)
8313 emit_insn (gen_cld ());
8316 /* Emit code to restore saved registers using MOV insns. First register
8317 is restored from POINTER + OFFSET. */
8319 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8320 int maybe_eh_return)
8323 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8325 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8326 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8328 /* Ensure that adjust_address won't be forced to produce pointer
8329 out of range allowed by x86-64 instruction set. */
8330 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8334 r11 = gen_rtx_REG (DImode, R11_REG);
8335 emit_move_insn (r11, GEN_INT (offset));
8336 emit_insn (gen_adddi3 (r11, r11, pointer));
8337 base_address = gen_rtx_MEM (Pmode, r11);
8340 emit_move_insn (gen_rtx_REG (Pmode, regno),
8341 adjust_address (base_address, Pmode, offset));
8342 offset += UNITS_PER_WORD;
8346 /* Emit code to restore saved registers using MOV insns. First register
8347 is restored from POINTER + OFFSET. */
8349 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8350 int maybe_eh_return)
8353 rtx base_address = gen_rtx_MEM (TImode, pointer);
8356 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8357 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8359 /* Ensure that adjust_address won't be forced to produce pointer
8360 out of range allowed by x86-64 instruction set. */
8361 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8365 r11 = gen_rtx_REG (DImode, R11_REG);
8366 emit_move_insn (r11, GEN_INT (offset));
8367 emit_insn (gen_adddi3 (r11, r11, pointer));
8368 base_address = gen_rtx_MEM (TImode, r11);
8371 mem = adjust_address (base_address, TImode, offset);
8372 set_mem_align (mem, 128);
8373 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8378 /* Restore function stack, frame, and registers. */
8381 ix86_expand_epilogue (int style)
8385 struct ix86_frame frame;
8386 HOST_WIDE_INT offset;
8388 ix86_finalize_stack_realign_flags ();
8390 /* When stack is realigned, SP must be valid. */
8391 sp_valid = (!frame_pointer_needed
8392 || current_function_sp_is_unchanging
8393 || stack_realign_fp);
8395 ix86_compute_frame_layout (&frame);
8397 /* See the comment about red zone and frame
8398 pointer usage in ix86_expand_prologue. */
8399 if (frame_pointer_needed && frame.red_zone_size)
8400 emit_insn (gen_memory_blockage ());
8402 /* Calculate start of saved registers relative to ebp. Special care
8403 must be taken for the normal return case of a function using
8404 eh_return: the eax and edx registers are marked as saved, but not
8405 restored along this path. */
8406 offset = frame.nregs;
8407 if (crtl->calls_eh_return && style != 2)
8409 offset *= -UNITS_PER_WORD;
8410 offset -= frame.nsseregs * 16 + frame.padding0;
8412 /* If we're only restoring one register and sp is not valid then
8413 using a move instruction to restore the register since it's
8414 less work than reloading sp and popping the register.
8416 The default code result in stack adjustment using add/lea instruction,
8417 while this code results in LEAVE instruction (or discrete equivalent),
8418 so it is profitable in some other cases as well. Especially when there
8419 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8420 and there is exactly one register to pop. This heuristic may need some
8421 tuning in future. */
8422 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8423 || (TARGET_EPILOGUE_USING_MOVE
8424 && cfun->machine->use_fast_prologue_epilogue
8425 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8426 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs) && frame.to_allocate)
8427 || (frame_pointer_needed && TARGET_USE_LEAVE
8428 && cfun->machine->use_fast_prologue_epilogue
8429 && (frame.nregs + frame.nsseregs) == 1)
8430 || crtl->calls_eh_return)
8432 /* Restore registers. We can use ebp or esp to address the memory
8433 locations. If both are available, default to ebp, since offsets
8434 are known to be small. Only exception is esp pointing directly
8435 to the end of block of saved registers, where we may simplify
8438 If we are realigning stack with bp and sp, regs restore can't
8439 be addressed by bp. sp must be used instead. */
8441 if (!frame_pointer_needed
8442 || (sp_valid && !frame.to_allocate)
8443 || stack_realign_fp)
8445 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8446 frame.to_allocate, style == 2);
8447 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8449 + frame.nsseregs * 16
8450 + frame.padding0, style == 2);
8454 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8455 offset, style == 2);
8456 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8458 + frame.nsseregs * 16
8459 + frame.padding0, style == 2);
8462 /* eh_return epilogues need %ecx added to the stack pointer. */
8465 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8467 /* Stack align doesn't work with eh_return. */
8468 gcc_assert (!crtl->stack_realign_needed);
8470 if (frame_pointer_needed)
8472 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8473 tmp = plus_constant (tmp, UNITS_PER_WORD);
8474 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8476 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8477 emit_move_insn (hard_frame_pointer_rtx, tmp);
8479 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8484 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8485 tmp = plus_constant (tmp, (frame.to_allocate
8486 + frame.nregs * UNITS_PER_WORD
8487 + frame.nsseregs * 16
8489 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8492 else if (!frame_pointer_needed)
8493 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8494 GEN_INT (frame.to_allocate
8495 + frame.nregs * UNITS_PER_WORD
8496 + frame.nsseregs * 16
8499 /* If not an i386, mov & pop is faster than "leave". */
8500 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8501 || !cfun->machine->use_fast_prologue_epilogue)
8502 emit_insn ((*ix86_gen_leave) ());
8505 pro_epilogue_adjust_stack (stack_pointer_rtx,
8506 hard_frame_pointer_rtx,
8509 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8514 /* First step is to deallocate the stack frame so that we can
8517 If we realign stack with frame pointer, then stack pointer
8518 won't be able to recover via lea $offset(%bp), %sp, because
8519 there is a padding area between bp and sp for realign.
8520 "add $to_allocate, %sp" must be used instead. */
8523 gcc_assert (frame_pointer_needed);
8524 gcc_assert (!stack_realign_fp);
8525 pro_epilogue_adjust_stack (stack_pointer_rtx,
8526 hard_frame_pointer_rtx,
8527 GEN_INT (offset), style);
8528 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8529 frame.to_allocate, style == 2);
8530 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8531 GEN_INT (frame.nsseregs * 16), style);
8533 else if (frame.to_allocate || frame.nsseregs)
8535 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8538 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8539 GEN_INT (frame.to_allocate
8540 + frame.nsseregs * 16
8541 + frame.padding0), style);
8544 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8545 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8546 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8547 if (frame_pointer_needed)
8549 /* Leave results in shorter dependency chains on CPUs that are
8550 able to grok it fast. */
8551 if (TARGET_USE_LEAVE)
8552 emit_insn ((*ix86_gen_leave) ());
8555 /* For stack realigned really happens, recover stack
8556 pointer to hard frame pointer is a must, if not using
8558 if (stack_realign_fp)
8559 pro_epilogue_adjust_stack (stack_pointer_rtx,
8560 hard_frame_pointer_rtx,
8562 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8567 if (crtl->drap_reg && crtl->stack_realign_needed)
8569 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8570 ? 0 : UNITS_PER_WORD);
8571 gcc_assert (stack_realign_drap);
8572 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8574 GEN_INT (-(UNITS_PER_WORD
8575 + param_ptr_offset))));
8576 if (!call_used_regs[REGNO (crtl->drap_reg)])
8577 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8581 /* Sibcall epilogues don't want a return instruction. */
8585 if (crtl->args.pops_args && crtl->args.size)
8587 rtx popc = GEN_INT (crtl->args.pops_args);
8589 /* i386 can only pop 64K bytes. If asked to pop more, pop
8590 return address, do explicit add, and jump indirectly to the
8593 if (crtl->args.pops_args >= 65536)
8595 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8597 /* There is no "pascal" calling convention in any 64bit ABI. */
8598 gcc_assert (!TARGET_64BIT);
8600 emit_insn (gen_popsi1 (ecx));
8601 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8602 emit_jump_insn (gen_return_indirect_internal (ecx));
8605 emit_jump_insn (gen_return_pop_internal (popc));
8608 emit_jump_insn (gen_return_internal ());
8611 /* Reset from the function's potential modifications. */
8614 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8615 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8617 if (pic_offset_table_rtx)
8618 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8620 /* Mach-O doesn't support labels at the end of objects, so if
8621 it looks like we might want one, insert a NOP. */
8623 rtx insn = get_last_insn ();
8626 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8627 insn = PREV_INSN (insn);
8631 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8632 fputs ("\tnop\n", file);
8638 /* Extract the parts of an RTL expression that is a valid memory address
8639 for an instruction. Return 0 if the structure of the address is
8640 grossly off. Return -1 if the address contains ASHIFT, so it is not
8641 strictly valid, but still used for computing length of lea instruction. */
8644 ix86_decompose_address (rtx addr, struct ix86_address *out)
8646 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8647 rtx base_reg, index_reg;
8648 HOST_WIDE_INT scale = 1;
8649 rtx scale_rtx = NULL_RTX;
8651 enum ix86_address_seg seg = SEG_DEFAULT;
8653 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8655 else if (GET_CODE (addr) == PLUS)
8665 addends[n++] = XEXP (op, 1);
8668 while (GET_CODE (op) == PLUS);
8673 for (i = n; i >= 0; --i)
8676 switch (GET_CODE (op))
8681 index = XEXP (op, 0);
8682 scale_rtx = XEXP (op, 1);
8686 if (XINT (op, 1) == UNSPEC_TP
8687 && TARGET_TLS_DIRECT_SEG_REFS
8688 && seg == SEG_DEFAULT)
8689 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8718 else if (GET_CODE (addr) == MULT)
8720 index = XEXP (addr, 0); /* index*scale */
8721 scale_rtx = XEXP (addr, 1);
8723 else if (GET_CODE (addr) == ASHIFT)
8727 /* We're called for lea too, which implements ashift on occasion. */
8728 index = XEXP (addr, 0);
8729 tmp = XEXP (addr, 1);
8730 if (!CONST_INT_P (tmp))
8732 scale = INTVAL (tmp);
8733 if ((unsigned HOST_WIDE_INT) scale > 3)
8739 disp = addr; /* displacement */
8741 /* Extract the integral value of scale. */
8744 if (!CONST_INT_P (scale_rtx))
8746 scale = INTVAL (scale_rtx);
8749 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8750 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8752 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8753 if (base_reg && index_reg && scale == 1
8754 && (index_reg == arg_pointer_rtx
8755 || index_reg == frame_pointer_rtx
8756 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8759 tmp = base, base = index, index = tmp;
8760 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8763 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8764 if ((base_reg == hard_frame_pointer_rtx
8765 || base_reg == frame_pointer_rtx
8766 || base_reg == arg_pointer_rtx) && !disp)
8769 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8770 Avoid this by transforming to [%esi+0].
8771 Reload calls address legitimization without cfun defined, so we need
8772 to test cfun for being non-NULL. */
8773 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8774 && base_reg && !index_reg && !disp
8776 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8779 /* Special case: encode reg+reg instead of reg*2. */
8780 if (!base && index && scale && scale == 2)
8781 base = index, base_reg = index_reg, scale = 1;
8783 /* Special case: scaling cannot be encoded without base or displacement. */
8784 if (!base && !disp && index && scale != 1)
8796 /* Return cost of the memory address x.
8797 For i386, it is better to use a complex address than let gcc copy
8798 the address into a reg and make a new pseudo. But not if the address
8799 requires to two regs - that would mean more pseudos with longer
8802 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8804 struct ix86_address parts;
8806 int ok = ix86_decompose_address (x, &parts);
8810 if (parts.base && GET_CODE (parts.base) == SUBREG)
8811 parts.base = SUBREG_REG (parts.base);
8812 if (parts.index && GET_CODE (parts.index) == SUBREG)
8813 parts.index = SUBREG_REG (parts.index);
8815 /* Attempt to minimize number of registers in the address. */
8817 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8819 && (!REG_P (parts.index)
8820 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8824 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8826 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8827 && parts.base != parts.index)
8830 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8831 since it's predecode logic can't detect the length of instructions
8832 and it degenerates to vector decoded. Increase cost of such
8833 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8834 to split such addresses or even refuse such addresses at all.
8836 Following addressing modes are affected:
8841 The first and last case may be avoidable by explicitly coding the zero in
8842 memory address, but I don't have AMD-K6 machine handy to check this
8846 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8847 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8848 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8854 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8855 this is used for to form addresses to local data when -fPIC is in
8859 darwin_local_data_pic (rtx disp)
8861 return (GET_CODE (disp) == UNSPEC
8862 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8865 /* Determine if a given RTX is a valid constant. We already know this
8866 satisfies CONSTANT_P. */
8869 legitimate_constant_p (rtx x)
8871 switch (GET_CODE (x))
8876 if (GET_CODE (x) == PLUS)
8878 if (!CONST_INT_P (XEXP (x, 1)))
8883 if (TARGET_MACHO && darwin_local_data_pic (x))
8886 /* Only some unspecs are valid as "constants". */
8887 if (GET_CODE (x) == UNSPEC)
8888 switch (XINT (x, 1))
8893 return TARGET_64BIT;
8896 x = XVECEXP (x, 0, 0);
8897 return (GET_CODE (x) == SYMBOL_REF
8898 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8900 x = XVECEXP (x, 0, 0);
8901 return (GET_CODE (x) == SYMBOL_REF
8902 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8907 /* We must have drilled down to a symbol. */
8908 if (GET_CODE (x) == LABEL_REF)
8910 if (GET_CODE (x) != SYMBOL_REF)
8915 /* TLS symbols are never valid. */
8916 if (SYMBOL_REF_TLS_MODEL (x))
8919 /* DLLIMPORT symbols are never valid. */
8920 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8921 && SYMBOL_REF_DLLIMPORT_P (x))
8926 if (GET_MODE (x) == TImode
8927 && x != CONST0_RTX (TImode)
8933 if (x == CONST0_RTX (GET_MODE (x)))
8941 /* Otherwise we handle everything else in the move patterns. */
8945 /* Determine if it's legal to put X into the constant pool. This
8946 is not possible for the address of thread-local symbols, which
8947 is checked above. */
8950 ix86_cannot_force_const_mem (rtx x)
8952 /* We can always put integral constants and vectors in memory. */
8953 switch (GET_CODE (x))
8963 return !legitimate_constant_p (x);
8966 /* Determine if a given RTX is a valid constant address. */
8969 constant_address_p (rtx x)
8971 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8974 /* Nonzero if the constant value X is a legitimate general operand
8975 when generating PIC code. It is given that flag_pic is on and
8976 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8979 legitimate_pic_operand_p (rtx x)
8983 switch (GET_CODE (x))
8986 inner = XEXP (x, 0);
8987 if (GET_CODE (inner) == PLUS
8988 && CONST_INT_P (XEXP (inner, 1)))
8989 inner = XEXP (inner, 0);
8991 /* Only some unspecs are valid as "constants". */
8992 if (GET_CODE (inner) == UNSPEC)
8993 switch (XINT (inner, 1))
8998 return TARGET_64BIT;
9000 x = XVECEXP (inner, 0, 0);
9001 return (GET_CODE (x) == SYMBOL_REF
9002 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9003 case UNSPEC_MACHOPIC_OFFSET:
9004 return legitimate_pic_address_disp_p (x);
9012 return legitimate_pic_address_disp_p (x);
9019 /* Determine if a given CONST RTX is a valid memory displacement
9023 legitimate_pic_address_disp_p (rtx disp)
9027 /* In 64bit mode we can allow direct addresses of symbols and labels
9028 when they are not dynamic symbols. */
9031 rtx op0 = disp, op1;
9033 switch (GET_CODE (disp))
9039 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9041 op0 = XEXP (XEXP (disp, 0), 0);
9042 op1 = XEXP (XEXP (disp, 0), 1);
9043 if (!CONST_INT_P (op1)
9044 || INTVAL (op1) >= 16*1024*1024
9045 || INTVAL (op1) < -16*1024*1024)
9047 if (GET_CODE (op0) == LABEL_REF)
9049 if (GET_CODE (op0) != SYMBOL_REF)
9054 /* TLS references should always be enclosed in UNSPEC. */
9055 if (SYMBOL_REF_TLS_MODEL (op0))
9057 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9058 && ix86_cmodel != CM_LARGE_PIC)
9066 if (GET_CODE (disp) != CONST)
9068 disp = XEXP (disp, 0);
9072 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9073 of GOT tables. We should not need these anyway. */
9074 if (GET_CODE (disp) != UNSPEC
9075 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9076 && XINT (disp, 1) != UNSPEC_GOTOFF
9077 && XINT (disp, 1) != UNSPEC_PLTOFF))
9080 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9081 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9087 if (GET_CODE (disp) == PLUS)
9089 if (!CONST_INT_P (XEXP (disp, 1)))
9091 disp = XEXP (disp, 0);
9095 if (TARGET_MACHO && darwin_local_data_pic (disp))
9098 if (GET_CODE (disp) != UNSPEC)
9101 switch (XINT (disp, 1))
9106 /* We need to check for both symbols and labels because VxWorks loads
9107 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9109 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9110 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9112 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9113 While ABI specify also 32bit relocation but we don't produce it in
9114 small PIC model at all. */
9115 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9116 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9118 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9120 case UNSPEC_GOTTPOFF:
9121 case UNSPEC_GOTNTPOFF:
9122 case UNSPEC_INDNTPOFF:
9125 disp = XVECEXP (disp, 0, 0);
9126 return (GET_CODE (disp) == SYMBOL_REF
9127 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9129 disp = XVECEXP (disp, 0, 0);
9130 return (GET_CODE (disp) == SYMBOL_REF
9131 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9133 disp = XVECEXP (disp, 0, 0);
9134 return (GET_CODE (disp) == SYMBOL_REF
9135 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9141 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9142 memory address for an instruction. The MODE argument is the machine mode
9143 for the MEM expression that wants to use this address.
9145 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9146 convert common non-canonical forms to canonical form so that they will
9150 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9151 rtx addr, int strict)
9153 struct ix86_address parts;
9154 rtx base, index, disp;
9155 HOST_WIDE_INT scale;
9156 const char *reason = NULL;
9157 rtx reason_rtx = NULL_RTX;
9159 if (ix86_decompose_address (addr, &parts) <= 0)
9161 reason = "decomposition failed";
9166 index = parts.index;
9168 scale = parts.scale;
9170 /* Validate base register.
9172 Don't allow SUBREG's that span more than a word here. It can lead to spill
9173 failures when the base is one word out of a two word structure, which is
9174 represented internally as a DImode int. */
9183 else if (GET_CODE (base) == SUBREG
9184 && REG_P (SUBREG_REG (base))
9185 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9187 reg = SUBREG_REG (base);
9190 reason = "base is not a register";
9194 if (GET_MODE (base) != Pmode)
9196 reason = "base is not in Pmode";
9200 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9201 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9203 reason = "base is not valid";
9208 /* Validate index register.
9210 Don't allow SUBREG's that span more than a word here -- same as above. */
9219 else if (GET_CODE (index) == SUBREG
9220 && REG_P (SUBREG_REG (index))
9221 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9223 reg = SUBREG_REG (index);
9226 reason = "index is not a register";
9230 if (GET_MODE (index) != Pmode)
9232 reason = "index is not in Pmode";
9236 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9237 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9239 reason = "index is not valid";
9244 /* Validate scale factor. */
9247 reason_rtx = GEN_INT (scale);
9250 reason = "scale without index";
9254 if (scale != 2 && scale != 4 && scale != 8)
9256 reason = "scale is not a valid multiplier";
9261 /* Validate displacement. */
9266 if (GET_CODE (disp) == CONST
9267 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9268 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9269 switch (XINT (XEXP (disp, 0), 1))
9271 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9272 used. While ABI specify also 32bit relocations, we don't produce
9273 them at all and use IP relative instead. */
9276 gcc_assert (flag_pic);
9278 goto is_legitimate_pic;
9279 reason = "64bit address unspec";
9282 case UNSPEC_GOTPCREL:
9283 gcc_assert (flag_pic);
9284 goto is_legitimate_pic;
9286 case UNSPEC_GOTTPOFF:
9287 case UNSPEC_GOTNTPOFF:
9288 case UNSPEC_INDNTPOFF:
9294 reason = "invalid address unspec";
9298 else if (SYMBOLIC_CONST (disp)
9302 && MACHOPIC_INDIRECT
9303 && !machopic_operand_p (disp)
9309 if (TARGET_64BIT && (index || base))
9311 /* foo@dtpoff(%rX) is ok. */
9312 if (GET_CODE (disp) != CONST
9313 || GET_CODE (XEXP (disp, 0)) != PLUS
9314 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9315 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9316 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9317 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9319 reason = "non-constant pic memory reference";
9323 else if (! legitimate_pic_address_disp_p (disp))
9325 reason = "displacement is an invalid pic construct";
9329 /* This code used to verify that a symbolic pic displacement
9330 includes the pic_offset_table_rtx register.
9332 While this is good idea, unfortunately these constructs may
9333 be created by "adds using lea" optimization for incorrect
9342 This code is nonsensical, but results in addressing
9343 GOT table with pic_offset_table_rtx base. We can't
9344 just refuse it easily, since it gets matched by
9345 "addsi3" pattern, that later gets split to lea in the
9346 case output register differs from input. While this
9347 can be handled by separate addsi pattern for this case
9348 that never results in lea, this seems to be easier and
9349 correct fix for crash to disable this test. */
9351 else if (GET_CODE (disp) != LABEL_REF
9352 && !CONST_INT_P (disp)
9353 && (GET_CODE (disp) != CONST
9354 || !legitimate_constant_p (disp))
9355 && (GET_CODE (disp) != SYMBOL_REF
9356 || !legitimate_constant_p (disp)))
9358 reason = "displacement is not constant";
9361 else if (TARGET_64BIT
9362 && !x86_64_immediate_operand (disp, VOIDmode))
9364 reason = "displacement is out of range";
9369 /* Everything looks valid. */
9376 /* Return a unique alias set for the GOT. */
9378 static alias_set_type
9379 ix86_GOT_alias_set (void)
9381 static alias_set_type set = -1;
9383 set = new_alias_set ();
9387 /* Return a legitimate reference for ORIG (an address) using the
9388 register REG. If REG is 0, a new pseudo is generated.
9390 There are two types of references that must be handled:
9392 1. Global data references must load the address from the GOT, via
9393 the PIC reg. An insn is emitted to do this load, and the reg is
9396 2. Static data references, constant pool addresses, and code labels
9397 compute the address as an offset from the GOT, whose base is in
9398 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9399 differentiate them from global data objects. The returned
9400 address is the PIC reg + an unspec constant.
9402 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9403 reg also appears in the address. */
9406 legitimize_pic_address (rtx orig, rtx reg)
9413 if (TARGET_MACHO && !TARGET_64BIT)
9416 reg = gen_reg_rtx (Pmode);
9417 /* Use the generic Mach-O PIC machinery. */
9418 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9422 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9424 else if (TARGET_64BIT
9425 && ix86_cmodel != CM_SMALL_PIC
9426 && gotoff_operand (addr, Pmode))
9429 /* This symbol may be referenced via a displacement from the PIC
9430 base address (@GOTOFF). */
9432 if (reload_in_progress)
9433 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9434 if (GET_CODE (addr) == CONST)
9435 addr = XEXP (addr, 0);
9436 if (GET_CODE (addr) == PLUS)
9438 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9440 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9443 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9444 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9446 tmpreg = gen_reg_rtx (Pmode);
9449 emit_move_insn (tmpreg, new_rtx);
9453 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9454 tmpreg, 1, OPTAB_DIRECT);
9457 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9459 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9461 /* This symbol may be referenced via a displacement from the PIC
9462 base address (@GOTOFF). */
9464 if (reload_in_progress)
9465 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9466 if (GET_CODE (addr) == CONST)
9467 addr = XEXP (addr, 0);
9468 if (GET_CODE (addr) == PLUS)
9470 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9472 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9475 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9476 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9477 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9481 emit_move_insn (reg, new_rtx);
9485 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9486 /* We can't use @GOTOFF for text labels on VxWorks;
9487 see gotoff_operand. */
9488 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9490 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9492 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9493 return legitimize_dllimport_symbol (addr, true);
9494 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9495 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9496 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9498 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9499 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9503 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9505 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9506 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9507 new_rtx = gen_const_mem (Pmode, new_rtx);
9508 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9511 reg = gen_reg_rtx (Pmode);
9512 /* Use directly gen_movsi, otherwise the address is loaded
9513 into register for CSE. We don't want to CSE this addresses,
9514 instead we CSE addresses from the GOT table, so skip this. */
9515 emit_insn (gen_movsi (reg, new_rtx));
9520 /* This symbol must be referenced via a load from the
9521 Global Offset Table (@GOT). */
9523 if (reload_in_progress)
9524 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9525 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9526 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9528 new_rtx = force_reg (Pmode, new_rtx);
9529 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9530 new_rtx = gen_const_mem (Pmode, new_rtx);
9531 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9534 reg = gen_reg_rtx (Pmode);
9535 emit_move_insn (reg, new_rtx);
9541 if (CONST_INT_P (addr)
9542 && !x86_64_immediate_operand (addr, VOIDmode))
9546 emit_move_insn (reg, addr);
9550 new_rtx = force_reg (Pmode, addr);
9552 else if (GET_CODE (addr) == CONST)
9554 addr = XEXP (addr, 0);
9556 /* We must match stuff we generate before. Assume the only
9557 unspecs that can get here are ours. Not that we could do
9558 anything with them anyway.... */
9559 if (GET_CODE (addr) == UNSPEC
9560 || (GET_CODE (addr) == PLUS
9561 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9563 gcc_assert (GET_CODE (addr) == PLUS);
9565 if (GET_CODE (addr) == PLUS)
9567 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9569 /* Check first to see if this is a constant offset from a @GOTOFF
9570 symbol reference. */
9571 if (gotoff_operand (op0, Pmode)
9572 && CONST_INT_P (op1))
9576 if (reload_in_progress)
9577 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9578 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9580 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9581 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9582 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9586 emit_move_insn (reg, new_rtx);
9592 if (INTVAL (op1) < -16*1024*1024
9593 || INTVAL (op1) >= 16*1024*1024)
9595 if (!x86_64_immediate_operand (op1, Pmode))
9596 op1 = force_reg (Pmode, op1);
9597 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9603 base = legitimize_pic_address (XEXP (addr, 0), reg);
9604 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9605 base == reg ? NULL_RTX : reg);
9607 if (CONST_INT_P (new_rtx))
9608 new_rtx = plus_constant (base, INTVAL (new_rtx));
9611 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9613 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9614 new_rtx = XEXP (new_rtx, 1);
9616 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9624 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9627 get_thread_pointer (int to_reg)
9631 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9635 reg = gen_reg_rtx (Pmode);
9636 insn = gen_rtx_SET (VOIDmode, reg, tp);
9637 insn = emit_insn (insn);
9642 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9643 false if we expect this to be used for a memory address and true if
9644 we expect to load the address into a register. */
9647 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9649 rtx dest, base, off, pic, tp;
9654 case TLS_MODEL_GLOBAL_DYNAMIC:
9655 dest = gen_reg_rtx (Pmode);
9656 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9658 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9660 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9663 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9664 insns = get_insns ();
9667 RTL_CONST_CALL_P (insns) = 1;
9668 emit_libcall_block (insns, dest, rax, x);
9670 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9671 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9673 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9675 if (TARGET_GNU2_TLS)
9677 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9679 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9683 case TLS_MODEL_LOCAL_DYNAMIC:
9684 base = gen_reg_rtx (Pmode);
9685 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9687 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9689 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9692 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9693 insns = get_insns ();
9696 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9697 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9698 RTL_CONST_CALL_P (insns) = 1;
9699 emit_libcall_block (insns, base, rax, note);
9701 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9702 emit_insn (gen_tls_local_dynamic_base_64 (base));
9704 emit_insn (gen_tls_local_dynamic_base_32 (base));
9706 if (TARGET_GNU2_TLS)
9708 rtx x = ix86_tls_module_base ();
9710 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9711 gen_rtx_MINUS (Pmode, x, tp));
9714 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9715 off = gen_rtx_CONST (Pmode, off);
9717 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9719 if (TARGET_GNU2_TLS)
9721 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9723 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9728 case TLS_MODEL_INITIAL_EXEC:
9732 type = UNSPEC_GOTNTPOFF;
9736 if (reload_in_progress)
9737 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9738 pic = pic_offset_table_rtx;
9739 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9741 else if (!TARGET_ANY_GNU_TLS)
9743 pic = gen_reg_rtx (Pmode);
9744 emit_insn (gen_set_got (pic));
9745 type = UNSPEC_GOTTPOFF;
9750 type = UNSPEC_INDNTPOFF;
9753 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9754 off = gen_rtx_CONST (Pmode, off);
9756 off = gen_rtx_PLUS (Pmode, pic, off);
9757 off = gen_const_mem (Pmode, off);
9758 set_mem_alias_set (off, ix86_GOT_alias_set ());
9760 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9762 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9763 off = force_reg (Pmode, off);
9764 return gen_rtx_PLUS (Pmode, base, off);
9768 base = get_thread_pointer (true);
9769 dest = gen_reg_rtx (Pmode);
9770 emit_insn (gen_subsi3 (dest, base, off));
9774 case TLS_MODEL_LOCAL_EXEC:
9775 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9776 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9777 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9778 off = gen_rtx_CONST (Pmode, off);
9780 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9782 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9783 return gen_rtx_PLUS (Pmode, base, off);
9787 base = get_thread_pointer (true);
9788 dest = gen_reg_rtx (Pmode);
9789 emit_insn (gen_subsi3 (dest, base, off));
9800 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9803 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9804 htab_t dllimport_map;
9807 get_dllimport_decl (tree decl)
9809 struct tree_map *h, in;
9813 size_t namelen, prefixlen;
9819 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9821 in.hash = htab_hash_pointer (decl);
9822 in.base.from = decl;
9823 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9824 h = (struct tree_map *) *loc;
9828 *loc = h = GGC_NEW (struct tree_map);
9830 h->base.from = decl;
9831 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9832 DECL_ARTIFICIAL (to) = 1;
9833 DECL_IGNORED_P (to) = 1;
9834 DECL_EXTERNAL (to) = 1;
9835 TREE_READONLY (to) = 1;
9837 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9838 name = targetm.strip_name_encoding (name);
9839 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9840 ? "*__imp_" : "*__imp__";
9841 namelen = strlen (name);
9842 prefixlen = strlen (prefix);
9843 imp_name = (char *) alloca (namelen + prefixlen + 1);
9844 memcpy (imp_name, prefix, prefixlen);
9845 memcpy (imp_name + prefixlen, name, namelen + 1);
9847 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9848 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9849 SET_SYMBOL_REF_DECL (rtl, to);
9850 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9852 rtl = gen_const_mem (Pmode, rtl);
9853 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9855 SET_DECL_RTL (to, rtl);
9856 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9861 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9862 true if we require the result be a register. */
9865 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9870 gcc_assert (SYMBOL_REF_DECL (symbol));
9871 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9873 x = DECL_RTL (imp_decl);
9875 x = force_reg (Pmode, x);
9879 /* Try machine-dependent ways of modifying an illegitimate address
9880 to be legitimate. If we find one, return the new, valid address.
9881 This macro is used in only one place: `memory_address' in explow.c.
9883 OLDX is the address as it was before break_out_memory_refs was called.
9884 In some cases it is useful to look at this to decide what needs to be done.
9886 MODE and WIN are passed so that this macro can use
9887 GO_IF_LEGITIMATE_ADDRESS.
9889 It is always safe for this macro to do nothing. It exists to recognize
9890 opportunities to optimize the output.
9892 For the 80386, we handle X+REG by loading X into a register R and
9893 using R+REG. R will go in a general reg and indexing will be used.
9894 However, if REG is a broken-out memory address or multiplication,
9895 nothing needs to be done because REG can certainly go in a general reg.
9897 When -fpic is used, special handling is needed for symbolic references.
9898 See comments by legitimize_pic_address in i386.c for details. */
9901 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9906 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9908 return legitimize_tls_address (x, (enum tls_model) log, false);
9909 if (GET_CODE (x) == CONST
9910 && GET_CODE (XEXP (x, 0)) == PLUS
9911 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9912 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9914 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9915 (enum tls_model) log, false);
9916 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9919 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9921 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9922 return legitimize_dllimport_symbol (x, true);
9923 if (GET_CODE (x) == CONST
9924 && GET_CODE (XEXP (x, 0)) == PLUS
9925 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9926 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9928 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9929 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9933 if (flag_pic && SYMBOLIC_CONST (x))
9934 return legitimize_pic_address (x, 0);
9936 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9937 if (GET_CODE (x) == ASHIFT
9938 && CONST_INT_P (XEXP (x, 1))
9939 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9942 log = INTVAL (XEXP (x, 1));
9943 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9944 GEN_INT (1 << log));
9947 if (GET_CODE (x) == PLUS)
9949 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9951 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9952 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9953 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9956 log = INTVAL (XEXP (XEXP (x, 0), 1));
9957 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9958 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9959 GEN_INT (1 << log));
9962 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9963 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9964 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9967 log = INTVAL (XEXP (XEXP (x, 1), 1));
9968 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9969 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9970 GEN_INT (1 << log));
9973 /* Put multiply first if it isn't already. */
9974 if (GET_CODE (XEXP (x, 1)) == MULT)
9976 rtx tmp = XEXP (x, 0);
9977 XEXP (x, 0) = XEXP (x, 1);
9982 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9983 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9984 created by virtual register instantiation, register elimination, and
9985 similar optimizations. */
9986 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9989 x = gen_rtx_PLUS (Pmode,
9990 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9991 XEXP (XEXP (x, 1), 0)),
9992 XEXP (XEXP (x, 1), 1));
9996 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9997 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9998 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9999 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10000 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10001 && CONSTANT_P (XEXP (x, 1)))
10004 rtx other = NULL_RTX;
10006 if (CONST_INT_P (XEXP (x, 1)))
10008 constant = XEXP (x, 1);
10009 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10011 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10013 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10014 other = XEXP (x, 1);
10022 x = gen_rtx_PLUS (Pmode,
10023 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10024 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10025 plus_constant (other, INTVAL (constant)));
10029 if (changed && legitimate_address_p (mode, x, FALSE))
10032 if (GET_CODE (XEXP (x, 0)) == MULT)
10035 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10038 if (GET_CODE (XEXP (x, 1)) == MULT)
10041 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10045 && REG_P (XEXP (x, 1))
10046 && REG_P (XEXP (x, 0)))
10049 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10052 x = legitimize_pic_address (x, 0);
10055 if (changed && legitimate_address_p (mode, x, FALSE))
10058 if (REG_P (XEXP (x, 0)))
10060 rtx temp = gen_reg_rtx (Pmode);
10061 rtx val = force_operand (XEXP (x, 1), temp);
10063 emit_move_insn (temp, val);
10065 XEXP (x, 1) = temp;
10069 else if (REG_P (XEXP (x, 1)))
10071 rtx temp = gen_reg_rtx (Pmode);
10072 rtx val = force_operand (XEXP (x, 0), temp);
10074 emit_move_insn (temp, val);
10076 XEXP (x, 0) = temp;
10084 /* Print an integer constant expression in assembler syntax. Addition
10085 and subtraction are the only arithmetic that may appear in these
10086 expressions. FILE is the stdio stream to write to, X is the rtx, and
10087 CODE is the operand print code from the output string. */
10090 output_pic_addr_const (FILE *file, rtx x, int code)
10094 switch (GET_CODE (x))
10097 gcc_assert (flag_pic);
10102 if (! TARGET_MACHO || TARGET_64BIT)
10103 output_addr_const (file, x);
10106 const char *name = XSTR (x, 0);
10108 /* Mark the decl as referenced so that cgraph will
10109 output the function. */
10110 if (SYMBOL_REF_DECL (x))
10111 mark_decl_referenced (SYMBOL_REF_DECL (x));
10114 if (MACHOPIC_INDIRECT
10115 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10116 name = machopic_indirection_name (x, /*stub_p=*/true);
10118 assemble_name (file, name);
10120 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10121 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10122 fputs ("@PLT", file);
10129 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10130 assemble_name (asm_out_file, buf);
10134 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10138 /* This used to output parentheses around the expression,
10139 but that does not work on the 386 (either ATT or BSD assembler). */
10140 output_pic_addr_const (file, XEXP (x, 0), code);
10144 if (GET_MODE (x) == VOIDmode)
10146 /* We can use %d if the number is <32 bits and positive. */
10147 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10148 fprintf (file, "0x%lx%08lx",
10149 (unsigned long) CONST_DOUBLE_HIGH (x),
10150 (unsigned long) CONST_DOUBLE_LOW (x));
10152 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10155 /* We can't handle floating point constants;
10156 PRINT_OPERAND must handle them. */
10157 output_operand_lossage ("floating constant misused");
10161 /* Some assemblers need integer constants to appear first. */
10162 if (CONST_INT_P (XEXP (x, 0)))
10164 output_pic_addr_const (file, XEXP (x, 0), code);
10166 output_pic_addr_const (file, XEXP (x, 1), code);
10170 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10171 output_pic_addr_const (file, XEXP (x, 1), code);
10173 output_pic_addr_const (file, XEXP (x, 0), code);
10179 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10180 output_pic_addr_const (file, XEXP (x, 0), code);
10182 output_pic_addr_const (file, XEXP (x, 1), code);
10184 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10188 gcc_assert (XVECLEN (x, 0) == 1);
10189 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10190 switch (XINT (x, 1))
10193 fputs ("@GOT", file);
10195 case UNSPEC_GOTOFF:
10196 fputs ("@GOTOFF", file);
10198 case UNSPEC_PLTOFF:
10199 fputs ("@PLTOFF", file);
10201 case UNSPEC_GOTPCREL:
10202 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10203 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10205 case UNSPEC_GOTTPOFF:
10206 /* FIXME: This might be @TPOFF in Sun ld too. */
10207 fputs ("@GOTTPOFF", file);
10210 fputs ("@TPOFF", file);
10212 case UNSPEC_NTPOFF:
10214 fputs ("@TPOFF", file);
10216 fputs ("@NTPOFF", file);
10218 case UNSPEC_DTPOFF:
10219 fputs ("@DTPOFF", file);
10221 case UNSPEC_GOTNTPOFF:
10223 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10224 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10226 fputs ("@GOTNTPOFF", file);
10228 case UNSPEC_INDNTPOFF:
10229 fputs ("@INDNTPOFF", file);
10232 case UNSPEC_MACHOPIC_OFFSET:
10234 machopic_output_function_base_name (file);
10238 output_operand_lossage ("invalid UNSPEC as operand");
10244 output_operand_lossage ("invalid expression as operand");
10248 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10249 We need to emit DTP-relative relocations. */
10251 static void ATTRIBUTE_UNUSED
10252 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10254 fputs (ASM_LONG, file);
10255 output_addr_const (file, x);
10256 fputs ("@DTPOFF", file);
10262 fputs (", 0", file);
10265 gcc_unreachable ();
10269 /* Return true if X is a representation of the PIC register. This copes
10270 with calls from ix86_find_base_term, where the register might have
10271 been replaced by a cselib value. */
10274 ix86_pic_register_p (rtx x)
10276 if (GET_CODE (x) == VALUE)
10277 return (pic_offset_table_rtx
10278 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10280 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10283 /* In the name of slightly smaller debug output, and to cater to
10284 general assembler lossage, recognize PIC+GOTOFF and turn it back
10285 into a direct symbol reference.
10287 On Darwin, this is necessary to avoid a crash, because Darwin
10288 has a different PIC label for each routine but the DWARF debugging
10289 information is not associated with any particular routine, so it's
10290 necessary to remove references to the PIC label from RTL stored by
10291 the DWARF output code. */
10294 ix86_delegitimize_address (rtx orig_x)
10297 /* reg_addend is NULL or a multiple of some register. */
10298 rtx reg_addend = NULL_RTX;
10299 /* const_addend is NULL or a const_int. */
10300 rtx const_addend = NULL_RTX;
10301 /* This is the result, or NULL. */
10302 rtx result = NULL_RTX;
10309 if (GET_CODE (x) != CONST
10310 || GET_CODE (XEXP (x, 0)) != UNSPEC
10311 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10312 || !MEM_P (orig_x))
10314 return XVECEXP (XEXP (x, 0), 0, 0);
10317 if (GET_CODE (x) != PLUS
10318 || GET_CODE (XEXP (x, 1)) != CONST)
10321 if (ix86_pic_register_p (XEXP (x, 0)))
10322 /* %ebx + GOT/GOTOFF */
10324 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10326 /* %ebx + %reg * scale + GOT/GOTOFF */
10327 reg_addend = XEXP (x, 0);
10328 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10329 reg_addend = XEXP (reg_addend, 1);
10330 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10331 reg_addend = XEXP (reg_addend, 0);
10334 if (!REG_P (reg_addend)
10335 && GET_CODE (reg_addend) != MULT
10336 && GET_CODE (reg_addend) != ASHIFT)
10342 x = XEXP (XEXP (x, 1), 0);
10343 if (GET_CODE (x) == PLUS
10344 && CONST_INT_P (XEXP (x, 1)))
10346 const_addend = XEXP (x, 1);
10350 if (GET_CODE (x) == UNSPEC
10351 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10352 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10353 result = XVECEXP (x, 0, 0);
10355 if (TARGET_MACHO && darwin_local_data_pic (x)
10356 && !MEM_P (orig_x))
10357 result = XVECEXP (x, 0, 0);
10363 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10365 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10369 /* If X is a machine specific address (i.e. a symbol or label being
10370 referenced as a displacement from the GOT implemented using an
10371 UNSPEC), then return the base term. Otherwise return X. */
10374 ix86_find_base_term (rtx x)
10380 if (GET_CODE (x) != CONST)
10382 term = XEXP (x, 0);
10383 if (GET_CODE (term) == PLUS
10384 && (CONST_INT_P (XEXP (term, 1))
10385 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10386 term = XEXP (term, 0);
10387 if (GET_CODE (term) != UNSPEC
10388 || XINT (term, 1) != UNSPEC_GOTPCREL)
10391 return XVECEXP (term, 0, 0);
10394 return ix86_delegitimize_address (x);
10398 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10399 int fp, FILE *file)
10401 const char *suffix;
10403 if (mode == CCFPmode || mode == CCFPUmode)
10405 enum rtx_code second_code, bypass_code;
10406 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10407 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10408 code = ix86_fp_compare_code_to_integer (code);
10412 code = reverse_condition (code);
10463 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10467 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10468 Those same assemblers have the same but opposite lossage on cmov. */
10469 if (mode == CCmode)
10470 suffix = fp ? "nbe" : "a";
10471 else if (mode == CCCmode)
10474 gcc_unreachable ();
10490 gcc_unreachable ();
10494 gcc_assert (mode == CCmode || mode == CCCmode);
10511 gcc_unreachable ();
10515 /* ??? As above. */
10516 gcc_assert (mode == CCmode || mode == CCCmode);
10517 suffix = fp ? "nb" : "ae";
10520 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10524 /* ??? As above. */
10525 if (mode == CCmode)
10527 else if (mode == CCCmode)
10528 suffix = fp ? "nb" : "ae";
10530 gcc_unreachable ();
10533 suffix = fp ? "u" : "p";
10536 suffix = fp ? "nu" : "np";
10539 gcc_unreachable ();
10541 fputs (suffix, file);
10544 /* Print the name of register X to FILE based on its machine mode and number.
10545 If CODE is 'w', pretend the mode is HImode.
10546 If CODE is 'b', pretend the mode is QImode.
10547 If CODE is 'k', pretend the mode is SImode.
10548 If CODE is 'q', pretend the mode is DImode.
10549 If CODE is 'x', pretend the mode is V4SFmode.
10550 If CODE is 't', pretend the mode is V8SFmode.
10551 If CODE is 'h', pretend the reg is the 'high' byte register.
10552 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10553 If CODE is 'd', duplicate the operand for AVX instruction.
10557 print_reg (rtx x, int code, FILE *file)
10560 bool duplicated = code == 'd' && TARGET_AVX;
10562 gcc_assert (x == pc_rtx
10563 || (REGNO (x) != ARG_POINTER_REGNUM
10564 && REGNO (x) != FRAME_POINTER_REGNUM
10565 && REGNO (x) != FLAGS_REG
10566 && REGNO (x) != FPSR_REG
10567 && REGNO (x) != FPCR_REG));
10569 if (ASSEMBLER_DIALECT == ASM_ATT)
10574 gcc_assert (TARGET_64BIT);
10575 fputs ("rip", file);
10579 if (code == 'w' || MMX_REG_P (x))
10581 else if (code == 'b')
10583 else if (code == 'k')
10585 else if (code == 'q')
10587 else if (code == 'y')
10589 else if (code == 'h')
10591 else if (code == 'x')
10593 else if (code == 't')
10596 code = GET_MODE_SIZE (GET_MODE (x));
10598 /* Irritatingly, AMD extended registers use different naming convention
10599 from the normal registers. */
10600 if (REX_INT_REG_P (x))
10602 gcc_assert (TARGET_64BIT);
10606 error ("extended registers have no high halves");
10609 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10612 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10615 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10618 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10621 error ("unsupported operand size for extended register");
10631 if (STACK_TOP_P (x))
10640 if (! ANY_FP_REG_P (x))
10641 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10646 reg = hi_reg_name[REGNO (x)];
10649 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10651 reg = qi_reg_name[REGNO (x)];
10654 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10656 reg = qi_high_reg_name[REGNO (x)];
10661 gcc_assert (!duplicated);
10663 fputs (hi_reg_name[REGNO (x)] + 1, file);
10668 gcc_unreachable ();
10674 if (ASSEMBLER_DIALECT == ASM_ATT)
10675 fprintf (file, ", %%%s", reg);
10677 fprintf (file, ", %s", reg);
10681 /* Locate some local-dynamic symbol still in use by this function
10682 so that we can print its name in some tls_local_dynamic_base
10686 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10690 if (GET_CODE (x) == SYMBOL_REF
10691 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10693 cfun->machine->some_ld_name = XSTR (x, 0);
10700 static const char *
10701 get_some_local_dynamic_name (void)
10705 if (cfun->machine->some_ld_name)
10706 return cfun->machine->some_ld_name;
10708 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10710 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10711 return cfun->machine->some_ld_name;
10713 gcc_unreachable ();
10716 /* Meaning of CODE:
10717 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10718 C -- print opcode suffix for set/cmov insn.
10719 c -- like C, but print reversed condition
10720 E,e -- likewise, but for compare-and-branch fused insn.
10721 F,f -- likewise, but for floating-point.
10722 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10724 R -- print the prefix for register names.
10725 z -- print the opcode suffix for the size of the current operand.
10726 * -- print a star (in certain assembler syntax)
10727 A -- print an absolute memory reference.
10728 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10729 s -- print a shift double count, followed by the assemblers argument
10731 b -- print the QImode name of the register for the indicated operand.
10732 %b0 would print %al if operands[0] is reg 0.
10733 w -- likewise, print the HImode name of the register.
10734 k -- likewise, print the SImode name of the register.
10735 q -- likewise, print the DImode name of the register.
10736 x -- likewise, print the V4SFmode name of the register.
10737 t -- likewise, print the V8SFmode name of the register.
10738 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10739 y -- print "st(0)" instead of "st" as a register.
10740 d -- print duplicated register operand for AVX instruction.
10741 D -- print condition for SSE cmp instruction.
10742 P -- if PIC, print an @PLT suffix.
10743 X -- don't print any sort of PIC '@' suffix for a symbol.
10744 & -- print some in-use local-dynamic symbol name.
10745 H -- print a memory address offset by 8; used for sse high-parts
10746 Y -- print condition for SSE5 com* instruction.
10747 + -- print a branch hint as 'cs' or 'ds' prefix
10748 ; -- print a semicolon (after prefixes due to bug in older gas).
10752 print_operand (FILE *file, rtx x, int code)
10759 if (ASSEMBLER_DIALECT == ASM_ATT)
10764 assemble_name (file, get_some_local_dynamic_name ());
10768 switch (ASSEMBLER_DIALECT)
10775 /* Intel syntax. For absolute addresses, registers should not
10776 be surrounded by braces. */
10780 PRINT_OPERAND (file, x, 0);
10787 gcc_unreachable ();
10790 PRINT_OPERAND (file, x, 0);
10795 if (ASSEMBLER_DIALECT == ASM_ATT)
10800 if (ASSEMBLER_DIALECT == ASM_ATT)
10805 if (ASSEMBLER_DIALECT == ASM_ATT)
10810 if (ASSEMBLER_DIALECT == ASM_ATT)
10815 if (ASSEMBLER_DIALECT == ASM_ATT)
10820 if (ASSEMBLER_DIALECT == ASM_ATT)
10825 /* 387 opcodes don't get size suffixes if the operands are
10827 if (STACK_REG_P (x))
10830 /* Likewise if using Intel opcodes. */
10831 if (ASSEMBLER_DIALECT == ASM_INTEL)
10834 /* This is the size of op from size of operand. */
10835 switch (GET_MODE_SIZE (GET_MODE (x)))
10844 #ifdef HAVE_GAS_FILDS_FISTS
10854 if (GET_MODE (x) == SFmode)
10869 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10873 #ifdef GAS_MNEMONICS
10888 gcc_unreachable ();
10905 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10907 PRINT_OPERAND (file, x, 0);
10908 fputs (", ", file);
10913 /* Little bit of braindamage here. The SSE compare instructions
10914 does use completely different names for the comparisons that the
10915 fp conditional moves. */
10918 switch (GET_CODE (x))
10921 fputs ("eq", file);
10924 fputs ("eq_us", file);
10927 fputs ("lt", file);
10930 fputs ("nge", file);
10933 fputs ("le", file);
10936 fputs ("ngt", file);
10939 fputs ("unord", file);
10942 fputs ("neq", file);
10945 fputs ("neq_oq", file);
10948 fputs ("ge", file);
10951 fputs ("nlt", file);
10954 fputs ("gt", file);
10957 fputs ("nle", file);
10960 fputs ("ord", file);
10963 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10969 switch (GET_CODE (x))
10973 fputs ("eq", file);
10977 fputs ("lt", file);
10981 fputs ("le", file);
10984 fputs ("unord", file);
10988 fputs ("neq", file);
10992 fputs ("nlt", file);
10996 fputs ("nle", file);
10999 fputs ("ord", file);
11002 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11008 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11009 if (ASSEMBLER_DIALECT == ASM_ATT)
11011 switch (GET_MODE (x))
11013 case HImode: putc ('w', file); break;
11015 case SFmode: putc ('l', file); break;
11017 case DFmode: putc ('q', file); break;
11018 default: gcc_unreachable ();
11025 if (!COMPARISON_P (x))
11027 output_operand_lossage ("operand is neither a constant nor a "
11028 "condition code, invalid operand code "
11032 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11035 if (!COMPARISON_P (x))
11037 output_operand_lossage ("operand is neither a constant nor a "
11038 "condition code, invalid operand code "
11042 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11043 if (ASSEMBLER_DIALECT == ASM_ATT)
11046 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11049 /* Like above, but reverse condition */
11051 /* Check to see if argument to %c is really a constant
11052 and not a condition code which needs to be reversed. */
11053 if (!COMPARISON_P (x))
11055 output_operand_lossage ("operand is neither a constant nor a "
11056 "condition code, invalid operand "
11060 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11063 if (!COMPARISON_P (x))
11065 output_operand_lossage ("operand is neither a constant nor a "
11066 "condition code, invalid operand "
11070 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11071 if (ASSEMBLER_DIALECT == ASM_ATT)
11074 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11078 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11082 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11086 /* It doesn't actually matter what mode we use here, as we're
11087 only going to use this for printing. */
11088 x = adjust_address_nv (x, DImode, 8);
11096 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11099 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11102 int pred_val = INTVAL (XEXP (x, 0));
11104 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11105 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11107 int taken = pred_val > REG_BR_PROB_BASE / 2;
11108 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11110 /* Emit hints only in the case default branch prediction
11111 heuristics would fail. */
11112 if (taken != cputaken)
11114 /* We use 3e (DS) prefix for taken branches and
11115 2e (CS) prefix for not taken branches. */
11117 fputs ("ds ; ", file);
11119 fputs ("cs ; ", file);
11127 switch (GET_CODE (x))
11130 fputs ("neq", file);
11133 fputs ("eq", file);
11137 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11141 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11145 fputs ("le", file);
11149 fputs ("lt", file);
11152 fputs ("unord", file);
11155 fputs ("ord", file);
11158 fputs ("ueq", file);
11161 fputs ("nlt", file);
11164 fputs ("nle", file);
11167 fputs ("ule", file);
11170 fputs ("ult", file);
11173 fputs ("une", file);
11176 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11183 fputs (" ; ", file);
11190 output_operand_lossage ("invalid operand code '%c'", code);
11195 print_reg (x, code, file);
11197 else if (MEM_P (x))
11199 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11200 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11201 && GET_MODE (x) != BLKmode)
11204 switch (GET_MODE_SIZE (GET_MODE (x)))
11206 case 1: size = "BYTE"; break;
11207 case 2: size = "WORD"; break;
11208 case 4: size = "DWORD"; break;
11209 case 8: size = "QWORD"; break;
11210 case 12: size = "XWORD"; break;
11212 if (GET_MODE (x) == XFmode)
11218 gcc_unreachable ();
11221 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11224 else if (code == 'w')
11226 else if (code == 'k')
11229 fputs (size, file);
11230 fputs (" PTR ", file);
11234 /* Avoid (%rip) for call operands. */
11235 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11236 && !CONST_INT_P (x))
11237 output_addr_const (file, x);
11238 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11239 output_operand_lossage ("invalid constraints for operand");
11241 output_address (x);
11244 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11249 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11250 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11252 if (ASSEMBLER_DIALECT == ASM_ATT)
11254 fprintf (file, "0x%08lx", (long unsigned int) l);
11257 /* These float cases don't actually occur as immediate operands. */
11258 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11262 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11263 fprintf (file, "%s", dstr);
11266 else if (GET_CODE (x) == CONST_DOUBLE
11267 && GET_MODE (x) == XFmode)
11271 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11272 fprintf (file, "%s", dstr);
11277 /* We have patterns that allow zero sets of memory, for instance.
11278 In 64-bit mode, we should probably support all 8-byte vectors,
11279 since we can in fact encode that into an immediate. */
11280 if (GET_CODE (x) == CONST_VECTOR)
11282 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11288 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11290 if (ASSEMBLER_DIALECT == ASM_ATT)
11293 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11294 || GET_CODE (x) == LABEL_REF)
11296 if (ASSEMBLER_DIALECT == ASM_ATT)
11299 fputs ("OFFSET FLAT:", file);
11302 if (CONST_INT_P (x))
11303 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11305 output_pic_addr_const (file, x, code);
11307 output_addr_const (file, x);
11311 /* Print a memory operand whose address is ADDR. */
11314 print_operand_address (FILE *file, rtx addr)
11316 struct ix86_address parts;
11317 rtx base, index, disp;
11319 int ok = ix86_decompose_address (addr, &parts);
11324 index = parts.index;
11326 scale = parts.scale;
11334 if (ASSEMBLER_DIALECT == ASM_ATT)
11336 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11339 gcc_unreachable ();
11342 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11343 if (TARGET_64BIT && !base && !index)
11347 if (GET_CODE (disp) == CONST
11348 && GET_CODE (XEXP (disp, 0)) == PLUS
11349 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11350 symbol = XEXP (XEXP (disp, 0), 0);
11352 if (GET_CODE (symbol) == LABEL_REF
11353 || (GET_CODE (symbol) == SYMBOL_REF
11354 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11357 if (!base && !index)
11359 /* Displacement only requires special attention. */
11361 if (CONST_INT_P (disp))
11363 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11364 fputs ("ds:", file);
11365 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11368 output_pic_addr_const (file, disp, 0);
11370 output_addr_const (file, disp);
11374 if (ASSEMBLER_DIALECT == ASM_ATT)
11379 output_pic_addr_const (file, disp, 0);
11380 else if (GET_CODE (disp) == LABEL_REF)
11381 output_asm_label (disp);
11383 output_addr_const (file, disp);
11388 print_reg (base, 0, file);
11392 print_reg (index, 0, file);
11394 fprintf (file, ",%d", scale);
11400 rtx offset = NULL_RTX;
11404 /* Pull out the offset of a symbol; print any symbol itself. */
11405 if (GET_CODE (disp) == CONST
11406 && GET_CODE (XEXP (disp, 0)) == PLUS
11407 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11409 offset = XEXP (XEXP (disp, 0), 1);
11410 disp = gen_rtx_CONST (VOIDmode,
11411 XEXP (XEXP (disp, 0), 0));
11415 output_pic_addr_const (file, disp, 0);
11416 else if (GET_CODE (disp) == LABEL_REF)
11417 output_asm_label (disp);
11418 else if (CONST_INT_P (disp))
11421 output_addr_const (file, disp);
11427 print_reg (base, 0, file);
11430 if (INTVAL (offset) >= 0)
11432 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11436 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11443 print_reg (index, 0, file);
11445 fprintf (file, "*%d", scale);
11453 output_addr_const_extra (FILE *file, rtx x)
11457 if (GET_CODE (x) != UNSPEC)
11460 op = XVECEXP (x, 0, 0);
11461 switch (XINT (x, 1))
11463 case UNSPEC_GOTTPOFF:
11464 output_addr_const (file, op);
11465 /* FIXME: This might be @TPOFF in Sun ld. */
11466 fputs ("@GOTTPOFF", file);
11469 output_addr_const (file, op);
11470 fputs ("@TPOFF", file);
11472 case UNSPEC_NTPOFF:
11473 output_addr_const (file, op);
11475 fputs ("@TPOFF", file);
11477 fputs ("@NTPOFF", file);
11479 case UNSPEC_DTPOFF:
11480 output_addr_const (file, op);
11481 fputs ("@DTPOFF", file);
11483 case UNSPEC_GOTNTPOFF:
11484 output_addr_const (file, op);
11486 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11487 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11489 fputs ("@GOTNTPOFF", file);
11491 case UNSPEC_INDNTPOFF:
11492 output_addr_const (file, op);
11493 fputs ("@INDNTPOFF", file);
11496 case UNSPEC_MACHOPIC_OFFSET:
11497 output_addr_const (file, op);
11499 machopic_output_function_base_name (file);
11510 /* Split one or more DImode RTL references into pairs of SImode
11511 references. The RTL can be REG, offsettable MEM, integer constant, or
11512 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11513 split and "num" is its length. lo_half and hi_half are output arrays
11514 that parallel "operands". */
11517 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11521 rtx op = operands[num];
11523 /* simplify_subreg refuse to split volatile memory addresses,
11524 but we still have to handle it. */
11527 lo_half[num] = adjust_address (op, SImode, 0);
11528 hi_half[num] = adjust_address (op, SImode, 4);
11532 lo_half[num] = simplify_gen_subreg (SImode, op,
11533 GET_MODE (op) == VOIDmode
11534 ? DImode : GET_MODE (op), 0);
11535 hi_half[num] = simplify_gen_subreg (SImode, op,
11536 GET_MODE (op) == VOIDmode
11537 ? DImode : GET_MODE (op), 4);
11541 /* Split one or more TImode RTL references into pairs of DImode
11542 references. The RTL can be REG, offsettable MEM, integer constant, or
11543 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11544 split and "num" is its length. lo_half and hi_half are output arrays
11545 that parallel "operands". */
11548 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11552 rtx op = operands[num];
11554 /* simplify_subreg refuse to split volatile memory addresses, but we
11555 still have to handle it. */
11558 lo_half[num] = adjust_address (op, DImode, 0);
11559 hi_half[num] = adjust_address (op, DImode, 8);
11563 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11564 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11569 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11570 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11571 is the expression of the binary operation. The output may either be
11572 emitted here, or returned to the caller, like all output_* functions.
11574 There is no guarantee that the operands are the same mode, as they
11575 might be within FLOAT or FLOAT_EXTEND expressions. */
11577 #ifndef SYSV386_COMPAT
11578 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11579 wants to fix the assemblers because that causes incompatibility
11580 with gcc. No-one wants to fix gcc because that causes
11581 incompatibility with assemblers... You can use the option of
11582 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11583 #define SYSV386_COMPAT 1
11587 output_387_binary_op (rtx insn, rtx *operands)
11589 static char buf[40];
11592 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11594 #ifdef ENABLE_CHECKING
11595 /* Even if we do not want to check the inputs, this documents input
11596 constraints. Which helps in understanding the following code. */
11597 if (STACK_REG_P (operands[0])
11598 && ((REG_P (operands[1])
11599 && REGNO (operands[0]) == REGNO (operands[1])
11600 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11601 || (REG_P (operands[2])
11602 && REGNO (operands[0]) == REGNO (operands[2])
11603 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11604 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11607 gcc_assert (is_sse);
11610 switch (GET_CODE (operands[3]))
11613 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11614 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11622 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11623 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11631 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11632 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11640 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11641 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11649 gcc_unreachable ();
11656 strcpy (buf, ssep);
11657 if (GET_MODE (operands[0]) == SFmode)
11658 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11660 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11664 strcpy (buf, ssep + 1);
11665 if (GET_MODE (operands[0]) == SFmode)
11666 strcat (buf, "ss\t{%2, %0|%0, %2}");
11668 strcat (buf, "sd\t{%2, %0|%0, %2}");
11674 switch (GET_CODE (operands[3]))
11678 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11680 rtx temp = operands[2];
11681 operands[2] = operands[1];
11682 operands[1] = temp;
11685 /* know operands[0] == operands[1]. */
11687 if (MEM_P (operands[2]))
11693 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11695 if (STACK_TOP_P (operands[0]))
11696 /* How is it that we are storing to a dead operand[2]?
11697 Well, presumably operands[1] is dead too. We can't
11698 store the result to st(0) as st(0) gets popped on this
11699 instruction. Instead store to operands[2] (which I
11700 think has to be st(1)). st(1) will be popped later.
11701 gcc <= 2.8.1 didn't have this check and generated
11702 assembly code that the Unixware assembler rejected. */
11703 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11705 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11709 if (STACK_TOP_P (operands[0]))
11710 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11712 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11717 if (MEM_P (operands[1]))
11723 if (MEM_P (operands[2]))
11729 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11732 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11733 derived assemblers, confusingly reverse the direction of
11734 the operation for fsub{r} and fdiv{r} when the
11735 destination register is not st(0). The Intel assembler
11736 doesn't have this brain damage. Read !SYSV386_COMPAT to
11737 figure out what the hardware really does. */
11738 if (STACK_TOP_P (operands[0]))
11739 p = "{p\t%0, %2|rp\t%2, %0}";
11741 p = "{rp\t%2, %0|p\t%0, %2}";
11743 if (STACK_TOP_P (operands[0]))
11744 /* As above for fmul/fadd, we can't store to st(0). */
11745 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11747 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11752 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11755 if (STACK_TOP_P (operands[0]))
11756 p = "{rp\t%0, %1|p\t%1, %0}";
11758 p = "{p\t%1, %0|rp\t%0, %1}";
11760 if (STACK_TOP_P (operands[0]))
11761 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11763 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11768 if (STACK_TOP_P (operands[0]))
11770 if (STACK_TOP_P (operands[1]))
11771 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11773 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11776 else if (STACK_TOP_P (operands[1]))
11779 p = "{\t%1, %0|r\t%0, %1}";
11781 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11787 p = "{r\t%2, %0|\t%0, %2}";
11789 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11795 gcc_unreachable ();
11802 /* Return needed mode for entity in optimize_mode_switching pass. */
11805 ix86_mode_needed (int entity, rtx insn)
11807 enum attr_i387_cw mode;
11809 /* The mode UNINITIALIZED is used to store control word after a
11810 function call or ASM pattern. The mode ANY specify that function
11811 has no requirements on the control word and make no changes in the
11812 bits we are interested in. */
11815 || (NONJUMP_INSN_P (insn)
11816 && (asm_noperands (PATTERN (insn)) >= 0
11817 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11818 return I387_CW_UNINITIALIZED;
11820 if (recog_memoized (insn) < 0)
11821 return I387_CW_ANY;
11823 mode = get_attr_i387_cw (insn);
11828 if (mode == I387_CW_TRUNC)
11833 if (mode == I387_CW_FLOOR)
11838 if (mode == I387_CW_CEIL)
11843 if (mode == I387_CW_MASK_PM)
11848 gcc_unreachable ();
11851 return I387_CW_ANY;
11854 /* Output code to initialize control word copies used by trunc?f?i and
11855 rounding patterns. CURRENT_MODE is set to current control word,
11856 while NEW_MODE is set to new control word. */
11859 emit_i387_cw_initialization (int mode)
11861 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11864 enum ix86_stack_slot slot;
11866 rtx reg = gen_reg_rtx (HImode);
11868 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11869 emit_move_insn (reg, copy_rtx (stored_mode));
11871 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11872 || optimize_function_for_size_p (cfun))
11876 case I387_CW_TRUNC:
11877 /* round toward zero (truncate) */
11878 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11879 slot = SLOT_CW_TRUNC;
11882 case I387_CW_FLOOR:
11883 /* round down toward -oo */
11884 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11885 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11886 slot = SLOT_CW_FLOOR;
11890 /* round up toward +oo */
11891 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11892 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11893 slot = SLOT_CW_CEIL;
11896 case I387_CW_MASK_PM:
11897 /* mask precision exception for nearbyint() */
11898 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11899 slot = SLOT_CW_MASK_PM;
11903 gcc_unreachable ();
11910 case I387_CW_TRUNC:
11911 /* round toward zero (truncate) */
11912 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11913 slot = SLOT_CW_TRUNC;
11916 case I387_CW_FLOOR:
11917 /* round down toward -oo */
11918 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11919 slot = SLOT_CW_FLOOR;
11923 /* round up toward +oo */
11924 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11925 slot = SLOT_CW_CEIL;
11928 case I387_CW_MASK_PM:
11929 /* mask precision exception for nearbyint() */
11930 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11931 slot = SLOT_CW_MASK_PM;
11935 gcc_unreachable ();
11939 gcc_assert (slot < MAX_386_STACK_LOCALS);
11941 new_mode = assign_386_stack_local (HImode, slot);
11942 emit_move_insn (new_mode, reg);
11945 /* Output code for INSN to convert a float to a signed int. OPERANDS
11946 are the insn operands. The output may be [HSD]Imode and the input
11947 operand may be [SDX]Fmode. */
11950 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11952 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11953 int dimode_p = GET_MODE (operands[0]) == DImode;
11954 int round_mode = get_attr_i387_cw (insn);
11956 /* Jump through a hoop or two for DImode, since the hardware has no
11957 non-popping instruction. We used to do this a different way, but
11958 that was somewhat fragile and broke with post-reload splitters. */
11959 if ((dimode_p || fisttp) && !stack_top_dies)
11960 output_asm_insn ("fld\t%y1", operands);
11962 gcc_assert (STACK_TOP_P (operands[1]));
11963 gcc_assert (MEM_P (operands[0]));
11964 gcc_assert (GET_MODE (operands[1]) != TFmode);
11967 output_asm_insn ("fisttp%z0\t%0", operands);
11970 if (round_mode != I387_CW_ANY)
11971 output_asm_insn ("fldcw\t%3", operands);
11972 if (stack_top_dies || dimode_p)
11973 output_asm_insn ("fistp%z0\t%0", operands);
11975 output_asm_insn ("fist%z0\t%0", operands);
11976 if (round_mode != I387_CW_ANY)
11977 output_asm_insn ("fldcw\t%2", operands);
11983 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11984 have the values zero or one, indicates the ffreep insn's operand
11985 from the OPERANDS array. */
11987 static const char *
11988 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11990 if (TARGET_USE_FFREEP)
11991 #if HAVE_AS_IX86_FFREEP
11992 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11995 static char retval[] = ".word\t0xc_df";
11996 int regno = REGNO (operands[opno]);
11998 gcc_assert (FP_REGNO_P (regno));
12000 retval[9] = '0' + (regno - FIRST_STACK_REG);
12005 return opno ? "fstp\t%y1" : "fstp\t%y0";
12009 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12010 should be used. UNORDERED_P is true when fucom should be used. */
12013 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12015 int stack_top_dies;
12016 rtx cmp_op0, cmp_op1;
12017 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12021 cmp_op0 = operands[0];
12022 cmp_op1 = operands[1];
12026 cmp_op0 = operands[1];
12027 cmp_op1 = operands[2];
12032 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12033 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12034 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12035 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12037 if (GET_MODE (operands[0]) == SFmode)
12039 return &ucomiss[TARGET_AVX ? 0 : 1];
12041 return &comiss[TARGET_AVX ? 0 : 1];
12044 return &ucomisd[TARGET_AVX ? 0 : 1];
12046 return &comisd[TARGET_AVX ? 0 : 1];
12049 gcc_assert (STACK_TOP_P (cmp_op0));
12051 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12053 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12055 if (stack_top_dies)
12057 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12058 return output_387_ffreep (operands, 1);
12061 return "ftst\n\tfnstsw\t%0";
12064 if (STACK_REG_P (cmp_op1)
12066 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12067 && REGNO (cmp_op1) != FIRST_STACK_REG)
12069 /* If both the top of the 387 stack dies, and the other operand
12070 is also a stack register that dies, then this must be a
12071 `fcompp' float compare */
12075 /* There is no double popping fcomi variant. Fortunately,
12076 eflags is immune from the fstp's cc clobbering. */
12078 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12080 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12081 return output_387_ffreep (operands, 0);
12086 return "fucompp\n\tfnstsw\t%0";
12088 return "fcompp\n\tfnstsw\t%0";
12093 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12095 static const char * const alt[16] =
12097 "fcom%z2\t%y2\n\tfnstsw\t%0",
12098 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12099 "fucom%z2\t%y2\n\tfnstsw\t%0",
12100 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12102 "ficom%z2\t%y2\n\tfnstsw\t%0",
12103 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12107 "fcomi\t{%y1, %0|%0, %y1}",
12108 "fcomip\t{%y1, %0|%0, %y1}",
12109 "fucomi\t{%y1, %0|%0, %y1}",
12110 "fucomip\t{%y1, %0|%0, %y1}",
12121 mask = eflags_p << 3;
12122 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12123 mask |= unordered_p << 1;
12124 mask |= stack_top_dies;
12126 gcc_assert (mask < 16);
12135 ix86_output_addr_vec_elt (FILE *file, int value)
12137 const char *directive = ASM_LONG;
12141 directive = ASM_QUAD;
12143 gcc_assert (!TARGET_64BIT);
12146 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12150 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12152 const char *directive = ASM_LONG;
12155 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12156 directive = ASM_QUAD;
12158 gcc_assert (!TARGET_64BIT);
12160 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12161 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12162 fprintf (file, "%s%s%d-%s%d\n",
12163 directive, LPREFIX, value, LPREFIX, rel);
12164 else if (HAVE_AS_GOTOFF_IN_DATA)
12165 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12167 else if (TARGET_MACHO)
12169 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12170 machopic_output_function_base_name (file);
12171 fprintf(file, "\n");
12175 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12176 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12179 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12183 ix86_expand_clear (rtx dest)
12187 /* We play register width games, which are only valid after reload. */
12188 gcc_assert (reload_completed);
12190 /* Avoid HImode and its attendant prefix byte. */
12191 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12192 dest = gen_rtx_REG (SImode, REGNO (dest));
12193 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12195 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12196 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12198 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12199 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12205 /* X is an unchanging MEM. If it is a constant pool reference, return
12206 the constant pool rtx, else NULL. */
12209 maybe_get_pool_constant (rtx x)
12211 x = ix86_delegitimize_address (XEXP (x, 0));
12213 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12214 return get_pool_constant (x);
12220 ix86_expand_move (enum machine_mode mode, rtx operands[])
12223 enum tls_model model;
12228 if (GET_CODE (op1) == SYMBOL_REF)
12230 model = SYMBOL_REF_TLS_MODEL (op1);
12233 op1 = legitimize_tls_address (op1, model, true);
12234 op1 = force_operand (op1, op0);
12238 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12239 && SYMBOL_REF_DLLIMPORT_P (op1))
12240 op1 = legitimize_dllimport_symbol (op1, false);
12242 else if (GET_CODE (op1) == CONST
12243 && GET_CODE (XEXP (op1, 0)) == PLUS
12244 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12246 rtx addend = XEXP (XEXP (op1, 0), 1);
12247 rtx symbol = XEXP (XEXP (op1, 0), 0);
12250 model = SYMBOL_REF_TLS_MODEL (symbol);
12252 tmp = legitimize_tls_address (symbol, model, true);
12253 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12254 && SYMBOL_REF_DLLIMPORT_P (symbol))
12255 tmp = legitimize_dllimport_symbol (symbol, true);
12259 tmp = force_operand (tmp, NULL);
12260 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12261 op0, 1, OPTAB_DIRECT);
12267 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12269 if (TARGET_MACHO && !TARGET_64BIT)
12274 rtx temp = ((reload_in_progress
12275 || ((op0 && REG_P (op0))
12277 ? op0 : gen_reg_rtx (Pmode));
12278 op1 = machopic_indirect_data_reference (op1, temp);
12279 op1 = machopic_legitimize_pic_address (op1, mode,
12280 temp == op1 ? 0 : temp);
12282 else if (MACHOPIC_INDIRECT)
12283 op1 = machopic_indirect_data_reference (op1, 0);
12291 op1 = force_reg (Pmode, op1);
12292 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12294 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12295 op1 = legitimize_pic_address (op1, reg);
12304 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12305 || !push_operand (op0, mode))
12307 op1 = force_reg (mode, op1);
12309 if (push_operand (op0, mode)
12310 && ! general_no_elim_operand (op1, mode))
12311 op1 = copy_to_mode_reg (mode, op1);
12313 /* Force large constants in 64bit compilation into register
12314 to get them CSEed. */
12315 if (can_create_pseudo_p ()
12316 && (mode == DImode) && TARGET_64BIT
12317 && immediate_operand (op1, mode)
12318 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12319 && !register_operand (op0, mode)
12321 op1 = copy_to_mode_reg (mode, op1);
12323 if (can_create_pseudo_p ()
12324 && FLOAT_MODE_P (mode)
12325 && GET_CODE (op1) == CONST_DOUBLE)
12327 /* If we are loading a floating point constant to a register,
12328 force the value to memory now, since we'll get better code
12329 out the back end. */
12331 op1 = validize_mem (force_const_mem (mode, op1));
12332 if (!register_operand (op0, mode))
12334 rtx temp = gen_reg_rtx (mode);
12335 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12336 emit_move_insn (op0, temp);
12342 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12346 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12348 rtx op0 = operands[0], op1 = operands[1];
12349 unsigned int align = GET_MODE_ALIGNMENT (mode);
12351 /* Force constants other than zero into memory. We do not know how
12352 the instructions used to build constants modify the upper 64 bits
12353 of the register, once we have that information we may be able
12354 to handle some of them more efficiently. */
12355 if (can_create_pseudo_p ()
12356 && register_operand (op0, mode)
12357 && (CONSTANT_P (op1)
12358 || (GET_CODE (op1) == SUBREG
12359 && CONSTANT_P (SUBREG_REG (op1))))
12360 && standard_sse_constant_p (op1) <= 0)
12361 op1 = validize_mem (force_const_mem (mode, op1));
12363 /* We need to check memory alignment for SSE mode since attribute
12364 can make operands unaligned. */
12365 if (can_create_pseudo_p ()
12366 && SSE_REG_MODE_P (mode)
12367 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12368 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12372 /* ix86_expand_vector_move_misalign() does not like constants ... */
12373 if (CONSTANT_P (op1)
12374 || (GET_CODE (op1) == SUBREG
12375 && CONSTANT_P (SUBREG_REG (op1))))
12376 op1 = validize_mem (force_const_mem (mode, op1));
12378 /* ... nor both arguments in memory. */
12379 if (!register_operand (op0, mode)
12380 && !register_operand (op1, mode))
12381 op1 = force_reg (mode, op1);
12383 tmp[0] = op0; tmp[1] = op1;
12384 ix86_expand_vector_move_misalign (mode, tmp);
12388 /* Make operand1 a register if it isn't already. */
12389 if (can_create_pseudo_p ()
12390 && !register_operand (op0, mode)
12391 && !register_operand (op1, mode))
12393 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12397 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12400 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12401 straight to ix86_expand_vector_move. */
12402 /* Code generation for scalar reg-reg moves of single and double precision data:
12403 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12407 if (x86_sse_partial_reg_dependency == true)
12412 Code generation for scalar loads of double precision data:
12413 if (x86_sse_split_regs == true)
12414 movlpd mem, reg (gas syntax)
12418 Code generation for unaligned packed loads of single precision data
12419 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12420 if (x86_sse_unaligned_move_optimal)
12423 if (x86_sse_partial_reg_dependency == true)
12435 Code generation for unaligned packed loads of double precision data
12436 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12437 if (x86_sse_unaligned_move_optimal)
12440 if (x86_sse_split_regs == true)
12453 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12462 switch (GET_MODE_CLASS (mode))
12464 case MODE_VECTOR_INT:
12466 switch (GET_MODE_SIZE (mode))
12469 op0 = gen_lowpart (V16QImode, op0);
12470 op1 = gen_lowpart (V16QImode, op1);
12471 emit_insn (gen_avx_movdqu (op0, op1));
12474 op0 = gen_lowpart (V32QImode, op0);
12475 op1 = gen_lowpart (V32QImode, op1);
12476 emit_insn (gen_avx_movdqu256 (op0, op1));
12479 gcc_unreachable ();
12482 case MODE_VECTOR_FLOAT:
12483 op0 = gen_lowpart (mode, op0);
12484 op1 = gen_lowpart (mode, op1);
12489 emit_insn (gen_avx_movups (op0, op1));
12492 emit_insn (gen_avx_movups256 (op0, op1));
12495 emit_insn (gen_avx_movupd (op0, op1));
12498 emit_insn (gen_avx_movupd256 (op0, op1));
12501 gcc_unreachable ();
12506 gcc_unreachable ();
12514 /* If we're optimizing for size, movups is the smallest. */
12515 if (optimize_insn_for_size_p ())
12517 op0 = gen_lowpart (V4SFmode, op0);
12518 op1 = gen_lowpart (V4SFmode, op1);
12519 emit_insn (gen_sse_movups (op0, op1));
12523 /* ??? If we have typed data, then it would appear that using
12524 movdqu is the only way to get unaligned data loaded with
12526 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12528 op0 = gen_lowpart (V16QImode, op0);
12529 op1 = gen_lowpart (V16QImode, op1);
12530 emit_insn (gen_sse2_movdqu (op0, op1));
12534 if (TARGET_SSE2 && mode == V2DFmode)
12538 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12540 op0 = gen_lowpart (V2DFmode, op0);
12541 op1 = gen_lowpart (V2DFmode, op1);
12542 emit_insn (gen_sse2_movupd (op0, op1));
12546 /* When SSE registers are split into halves, we can avoid
12547 writing to the top half twice. */
12548 if (TARGET_SSE_SPLIT_REGS)
12550 emit_clobber (op0);
12555 /* ??? Not sure about the best option for the Intel chips.
12556 The following would seem to satisfy; the register is
12557 entirely cleared, breaking the dependency chain. We
12558 then store to the upper half, with a dependency depth
12559 of one. A rumor has it that Intel recommends two movsd
12560 followed by an unpacklpd, but this is unconfirmed. And
12561 given that the dependency depth of the unpacklpd would
12562 still be one, I'm not sure why this would be better. */
12563 zero = CONST0_RTX (V2DFmode);
12566 m = adjust_address (op1, DFmode, 0);
12567 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12568 m = adjust_address (op1, DFmode, 8);
12569 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12573 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12575 op0 = gen_lowpart (V4SFmode, op0);
12576 op1 = gen_lowpart (V4SFmode, op1);
12577 emit_insn (gen_sse_movups (op0, op1));
12581 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12582 emit_move_insn (op0, CONST0_RTX (mode));
12584 emit_clobber (op0);
12586 if (mode != V4SFmode)
12587 op0 = gen_lowpart (V4SFmode, op0);
12588 m = adjust_address (op1, V2SFmode, 0);
12589 emit_insn (gen_sse_loadlps (op0, op0, m));
12590 m = adjust_address (op1, V2SFmode, 8);
12591 emit_insn (gen_sse_loadhps (op0, op0, m));
12594 else if (MEM_P (op0))
12596 /* If we're optimizing for size, movups is the smallest. */
12597 if (optimize_insn_for_size_p ())
12599 op0 = gen_lowpart (V4SFmode, op0);
12600 op1 = gen_lowpart (V4SFmode, op1);
12601 emit_insn (gen_sse_movups (op0, op1));
12605 /* ??? Similar to above, only less clear because of quote
12606 typeless stores unquote. */
12607 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12608 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12610 op0 = gen_lowpart (V16QImode, op0);
12611 op1 = gen_lowpart (V16QImode, op1);
12612 emit_insn (gen_sse2_movdqu (op0, op1));
12616 if (TARGET_SSE2 && mode == V2DFmode)
12618 m = adjust_address (op0, DFmode, 0);
12619 emit_insn (gen_sse2_storelpd (m, op1));
12620 m = adjust_address (op0, DFmode, 8);
12621 emit_insn (gen_sse2_storehpd (m, op1));
12625 if (mode != V4SFmode)
12626 op1 = gen_lowpart (V4SFmode, op1);
12627 m = adjust_address (op0, V2SFmode, 0);
12628 emit_insn (gen_sse_storelps (m, op1));
12629 m = adjust_address (op0, V2SFmode, 8);
12630 emit_insn (gen_sse_storehps (m, op1));
12634 gcc_unreachable ();
12637 /* Expand a push in MODE. This is some mode for which we do not support
12638 proper push instructions, at least from the registers that we expect
12639 the value to live in. */
12642 ix86_expand_push (enum machine_mode mode, rtx x)
12646 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12647 GEN_INT (-GET_MODE_SIZE (mode)),
12648 stack_pointer_rtx, 1, OPTAB_DIRECT);
12649 if (tmp != stack_pointer_rtx)
12650 emit_move_insn (stack_pointer_rtx, tmp);
12652 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12654 /* When we push an operand onto stack, it has to be aligned at least
12655 at the function argument boundary. However since we don't have
12656 the argument type, we can't determine the actual argument
12658 emit_move_insn (tmp, x);
12661 /* Helper function of ix86_fixup_binary_operands to canonicalize
12662 operand order. Returns true if the operands should be swapped. */
12665 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12668 rtx dst = operands[0];
12669 rtx src1 = operands[1];
12670 rtx src2 = operands[2];
12672 /* If the operation is not commutative, we can't do anything. */
12673 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12676 /* Highest priority is that src1 should match dst. */
12677 if (rtx_equal_p (dst, src1))
12679 if (rtx_equal_p (dst, src2))
12682 /* Next highest priority is that immediate constants come second. */
12683 if (immediate_operand (src2, mode))
12685 if (immediate_operand (src1, mode))
12688 /* Lowest priority is that memory references should come second. */
12698 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12699 destination to use for the operation. If different from the true
12700 destination in operands[0], a copy operation will be required. */
12703 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12706 rtx dst = operands[0];
12707 rtx src1 = operands[1];
12708 rtx src2 = operands[2];
12710 /* Canonicalize operand order. */
12711 if (ix86_swap_binary_operands_p (code, mode, operands))
12715 /* It is invalid to swap operands of different modes. */
12716 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12723 /* Both source operands cannot be in memory. */
12724 if (MEM_P (src1) && MEM_P (src2))
12726 /* Optimization: Only read from memory once. */
12727 if (rtx_equal_p (src1, src2))
12729 src2 = force_reg (mode, src2);
12733 src2 = force_reg (mode, src2);
12736 /* If the destination is memory, and we do not have matching source
12737 operands, do things in registers. */
12738 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12739 dst = gen_reg_rtx (mode);
12741 /* Source 1 cannot be a constant. */
12742 if (CONSTANT_P (src1))
12743 src1 = force_reg (mode, src1);
12745 /* Source 1 cannot be a non-matching memory. */
12746 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12747 src1 = force_reg (mode, src1);
12749 operands[1] = src1;
12750 operands[2] = src2;
12754 /* Similarly, but assume that the destination has already been
12755 set up properly. */
12758 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12759 enum machine_mode mode, rtx operands[])
12761 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12762 gcc_assert (dst == operands[0]);
12765 /* Attempt to expand a binary operator. Make the expansion closer to the
12766 actual machine, then just general_operand, which will allow 3 separate
12767 memory references (one output, two input) in a single insn. */
12770 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12773 rtx src1, src2, dst, op, clob;
12775 dst = ix86_fixup_binary_operands (code, mode, operands);
12776 src1 = operands[1];
12777 src2 = operands[2];
12779 /* Emit the instruction. */
12781 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12782 if (reload_in_progress)
12784 /* Reload doesn't know about the flags register, and doesn't know that
12785 it doesn't want to clobber it. We can only do this with PLUS. */
12786 gcc_assert (code == PLUS);
12791 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12792 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12795 /* Fix up the destination if needed. */
12796 if (dst != operands[0])
12797 emit_move_insn (operands[0], dst);
12800 /* Return TRUE or FALSE depending on whether the binary operator meets the
12801 appropriate constraints. */
12804 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12807 rtx dst = operands[0];
12808 rtx src1 = operands[1];
12809 rtx src2 = operands[2];
12811 /* Both source operands cannot be in memory. */
12812 if (MEM_P (src1) && MEM_P (src2))
12815 /* Canonicalize operand order for commutative operators. */
12816 if (ix86_swap_binary_operands_p (code, mode, operands))
12823 /* If the destination is memory, we must have a matching source operand. */
12824 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12827 /* Source 1 cannot be a constant. */
12828 if (CONSTANT_P (src1))
12831 /* Source 1 cannot be a non-matching memory. */
12832 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12838 /* Attempt to expand a unary operator. Make the expansion closer to the
12839 actual machine, then just general_operand, which will allow 2 separate
12840 memory references (one output, one input) in a single insn. */
12843 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12846 int matching_memory;
12847 rtx src, dst, op, clob;
12852 /* If the destination is memory, and we do not have matching source
12853 operands, do things in registers. */
12854 matching_memory = 0;
12857 if (rtx_equal_p (dst, src))
12858 matching_memory = 1;
12860 dst = gen_reg_rtx (mode);
12863 /* When source operand is memory, destination must match. */
12864 if (MEM_P (src) && !matching_memory)
12865 src = force_reg (mode, src);
12867 /* Emit the instruction. */
12869 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12870 if (reload_in_progress || code == NOT)
12872 /* Reload doesn't know about the flags register, and doesn't know that
12873 it doesn't want to clobber it. */
12874 gcc_assert (code == NOT);
12879 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12880 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12883 /* Fix up the destination if needed. */
12884 if (dst != operands[0])
12885 emit_move_insn (operands[0], dst);
12888 /* Return TRUE or FALSE depending on whether the unary operator meets the
12889 appropriate constraints. */
12892 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12893 enum machine_mode mode ATTRIBUTE_UNUSED,
12894 rtx operands[2] ATTRIBUTE_UNUSED)
12896 /* If one of operands is memory, source and destination must match. */
12897 if ((MEM_P (operands[0])
12898 || MEM_P (operands[1]))
12899 && ! rtx_equal_p (operands[0], operands[1]))
12904 /* Post-reload splitter for converting an SF or DFmode value in an
12905 SSE register into an unsigned SImode. */
12908 ix86_split_convert_uns_si_sse (rtx operands[])
12910 enum machine_mode vecmode;
12911 rtx value, large, zero_or_two31, input, two31, x;
12913 large = operands[1];
12914 zero_or_two31 = operands[2];
12915 input = operands[3];
12916 two31 = operands[4];
12917 vecmode = GET_MODE (large);
12918 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12920 /* Load up the value into the low element. We must ensure that the other
12921 elements are valid floats -- zero is the easiest such value. */
12924 if (vecmode == V4SFmode)
12925 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12927 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12931 input = gen_rtx_REG (vecmode, REGNO (input));
12932 emit_move_insn (value, CONST0_RTX (vecmode));
12933 if (vecmode == V4SFmode)
12934 emit_insn (gen_sse_movss (value, value, input));
12936 emit_insn (gen_sse2_movsd (value, value, input));
12939 emit_move_insn (large, two31);
12940 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12942 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12943 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12945 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12946 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12948 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12949 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12951 large = gen_rtx_REG (V4SImode, REGNO (large));
12952 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12954 x = gen_rtx_REG (V4SImode, REGNO (value));
12955 if (vecmode == V4SFmode)
12956 emit_insn (gen_sse2_cvttps2dq (x, value));
12958 emit_insn (gen_sse2_cvttpd2dq (x, value));
12961 emit_insn (gen_xorv4si3 (value, value, large));
12964 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12965 Expects the 64-bit DImode to be supplied in a pair of integral
12966 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12967 -mfpmath=sse, !optimize_size only. */
12970 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12972 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12973 rtx int_xmm, fp_xmm;
12974 rtx biases, exponents;
12977 int_xmm = gen_reg_rtx (V4SImode);
12978 if (TARGET_INTER_UNIT_MOVES)
12979 emit_insn (gen_movdi_to_sse (int_xmm, input));
12980 else if (TARGET_SSE_SPLIT_REGS)
12982 emit_clobber (int_xmm);
12983 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12987 x = gen_reg_rtx (V2DImode);
12988 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12989 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12992 x = gen_rtx_CONST_VECTOR (V4SImode,
12993 gen_rtvec (4, GEN_INT (0x43300000UL),
12994 GEN_INT (0x45300000UL),
12995 const0_rtx, const0_rtx));
12996 exponents = validize_mem (force_const_mem (V4SImode, x));
12998 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12999 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13001 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13002 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13003 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13004 (0x1.0p84 + double(fp_value_hi_xmm)).
13005 Note these exponents differ by 32. */
13007 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13009 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13010 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13011 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13012 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13013 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13014 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13015 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13016 biases = validize_mem (force_const_mem (V2DFmode, biases));
13017 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13019 /* Add the upper and lower DFmode values together. */
13021 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13024 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13025 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13026 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13029 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13032 /* Not used, but eases macroization of patterns. */
13034 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13035 rtx input ATTRIBUTE_UNUSED)
13037 gcc_unreachable ();
13040 /* Convert an unsigned SImode value into a DFmode. Only currently used
13041 for SSE, but applicable anywhere. */
13044 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13046 REAL_VALUE_TYPE TWO31r;
13049 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13050 NULL, 1, OPTAB_DIRECT);
13052 fp = gen_reg_rtx (DFmode);
13053 emit_insn (gen_floatsidf2 (fp, x));
13055 real_ldexp (&TWO31r, &dconst1, 31);
13056 x = const_double_from_real_value (TWO31r, DFmode);
13058 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13060 emit_move_insn (target, x);
13063 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13064 32-bit mode; otherwise we have a direct convert instruction. */
13067 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13069 REAL_VALUE_TYPE TWO32r;
13070 rtx fp_lo, fp_hi, x;
13072 fp_lo = gen_reg_rtx (DFmode);
13073 fp_hi = gen_reg_rtx (DFmode);
13075 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13077 real_ldexp (&TWO32r, &dconst1, 32);
13078 x = const_double_from_real_value (TWO32r, DFmode);
13079 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13081 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13083 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13086 emit_move_insn (target, x);
13089 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13090 For x86_32, -mfpmath=sse, !optimize_size only. */
13092 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13094 REAL_VALUE_TYPE ONE16r;
13095 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13097 real_ldexp (&ONE16r, &dconst1, 16);
13098 x = const_double_from_real_value (ONE16r, SFmode);
13099 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13100 NULL, 0, OPTAB_DIRECT);
13101 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13102 NULL, 0, OPTAB_DIRECT);
13103 fp_hi = gen_reg_rtx (SFmode);
13104 fp_lo = gen_reg_rtx (SFmode);
13105 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13106 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13107 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13109 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13111 if (!rtx_equal_p (target, fp_hi))
13112 emit_move_insn (target, fp_hi);
13115 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13116 then replicate the value for all elements of the vector
13120 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13127 v = gen_rtvec (4, value, value, value, value);
13128 return gen_rtx_CONST_VECTOR (V4SImode, v);
13132 v = gen_rtvec (2, value, value);
13133 return gen_rtx_CONST_VECTOR (V2DImode, v);
13137 v = gen_rtvec (4, value, value, value, value);
13139 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13140 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13141 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13145 v = gen_rtvec (2, value, value);
13147 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13148 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13151 gcc_unreachable ();
13155 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13156 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13157 for an SSE register. If VECT is true, then replicate the mask for
13158 all elements of the vector register. If INVERT is true, then create
13159 a mask excluding the sign bit. */
13162 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13164 enum machine_mode vec_mode, imode;
13165 HOST_WIDE_INT hi, lo;
13170 /* Find the sign bit, sign extended to 2*HWI. */
13176 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13177 lo = 0x80000000, hi = lo < 0;
13183 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13184 if (HOST_BITS_PER_WIDE_INT >= 64)
13185 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13187 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13192 vec_mode = VOIDmode;
13193 if (HOST_BITS_PER_WIDE_INT >= 64)
13196 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13203 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13207 lo = ~lo, hi = ~hi;
13213 mask = immed_double_const (lo, hi, imode);
13215 vec = gen_rtvec (2, v, mask);
13216 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13217 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13224 gcc_unreachable ();
13228 lo = ~lo, hi = ~hi;
13230 /* Force this value into the low part of a fp vector constant. */
13231 mask = immed_double_const (lo, hi, imode);
13232 mask = gen_lowpart (mode, mask);
13234 if (vec_mode == VOIDmode)
13235 return force_reg (mode, mask);
13237 v = ix86_build_const_vector (mode, vect, mask);
13238 return force_reg (vec_mode, v);
13241 /* Generate code for floating point ABS or NEG. */
13244 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13247 rtx mask, set, use, clob, dst, src;
13248 bool use_sse = false;
13249 bool vector_mode = VECTOR_MODE_P (mode);
13250 enum machine_mode elt_mode = mode;
13254 elt_mode = GET_MODE_INNER (mode);
13257 else if (mode == TFmode)
13259 else if (TARGET_SSE_MATH)
13260 use_sse = SSE_FLOAT_MODE_P (mode);
13262 /* NEG and ABS performed with SSE use bitwise mask operations.
13263 Create the appropriate mask now. */
13265 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13274 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13275 set = gen_rtx_SET (VOIDmode, dst, set);
13280 set = gen_rtx_fmt_e (code, mode, src);
13281 set = gen_rtx_SET (VOIDmode, dst, set);
13284 use = gen_rtx_USE (VOIDmode, mask);
13285 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13286 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13287 gen_rtvec (3, set, use, clob)));
13294 /* Expand a copysign operation. Special case operand 0 being a constant. */
13297 ix86_expand_copysign (rtx operands[])
13299 enum machine_mode mode;
13300 rtx dest, op0, op1, mask, nmask;
13302 dest = operands[0];
13306 mode = GET_MODE (dest);
13308 if (GET_CODE (op0) == CONST_DOUBLE)
13310 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13312 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13313 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13315 if (mode == SFmode || mode == DFmode)
13317 enum machine_mode vmode;
13319 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13321 if (op0 == CONST0_RTX (mode))
13322 op0 = CONST0_RTX (vmode);
13327 if (mode == SFmode)
13328 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13329 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13331 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13333 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13336 else if (op0 != CONST0_RTX (mode))
13337 op0 = force_reg (mode, op0);
13339 mask = ix86_build_signbit_mask (mode, 0, 0);
13341 if (mode == SFmode)
13342 copysign_insn = gen_copysignsf3_const;
13343 else if (mode == DFmode)
13344 copysign_insn = gen_copysigndf3_const;
13346 copysign_insn = gen_copysigntf3_const;
13348 emit_insn (copysign_insn (dest, op0, op1, mask));
13352 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13354 nmask = ix86_build_signbit_mask (mode, 0, 1);
13355 mask = ix86_build_signbit_mask (mode, 0, 0);
13357 if (mode == SFmode)
13358 copysign_insn = gen_copysignsf3_var;
13359 else if (mode == DFmode)
13360 copysign_insn = gen_copysigndf3_var;
13362 copysign_insn = gen_copysigntf3_var;
13364 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13368 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13369 be a constant, and so has already been expanded into a vector constant. */
13372 ix86_split_copysign_const (rtx operands[])
13374 enum machine_mode mode, vmode;
13375 rtx dest, op0, op1, mask, x;
13377 dest = operands[0];
13380 mask = operands[3];
13382 mode = GET_MODE (dest);
13383 vmode = GET_MODE (mask);
13385 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13386 x = gen_rtx_AND (vmode, dest, mask);
13387 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13389 if (op0 != CONST0_RTX (vmode))
13391 x = gen_rtx_IOR (vmode, dest, op0);
13392 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13396 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13397 so we have to do two masks. */
13400 ix86_split_copysign_var (rtx operands[])
13402 enum machine_mode mode, vmode;
13403 rtx dest, scratch, op0, op1, mask, nmask, x;
13405 dest = operands[0];
13406 scratch = operands[1];
13409 nmask = operands[4];
13410 mask = operands[5];
13412 mode = GET_MODE (dest);
13413 vmode = GET_MODE (mask);
13415 if (rtx_equal_p (op0, op1))
13417 /* Shouldn't happen often (it's useless, obviously), but when it does
13418 we'd generate incorrect code if we continue below. */
13419 emit_move_insn (dest, op0);
13423 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13425 gcc_assert (REGNO (op1) == REGNO (scratch));
13427 x = gen_rtx_AND (vmode, scratch, mask);
13428 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13431 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13432 x = gen_rtx_NOT (vmode, dest);
13433 x = gen_rtx_AND (vmode, x, op0);
13434 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13438 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13440 x = gen_rtx_AND (vmode, scratch, mask);
13442 else /* alternative 2,4 */
13444 gcc_assert (REGNO (mask) == REGNO (scratch));
13445 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13446 x = gen_rtx_AND (vmode, scratch, op1);
13448 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13450 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13452 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13453 x = gen_rtx_AND (vmode, dest, nmask);
13455 else /* alternative 3,4 */
13457 gcc_assert (REGNO (nmask) == REGNO (dest));
13459 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13460 x = gen_rtx_AND (vmode, dest, op0);
13462 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13465 x = gen_rtx_IOR (vmode, dest, scratch);
13466 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13469 /* Return TRUE or FALSE depending on whether the first SET in INSN
13470 has source and destination with matching CC modes, and that the
13471 CC mode is at least as constrained as REQ_MODE. */
13474 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13477 enum machine_mode set_mode;
13479 set = PATTERN (insn);
13480 if (GET_CODE (set) == PARALLEL)
13481 set = XVECEXP (set, 0, 0);
13482 gcc_assert (GET_CODE (set) == SET);
13483 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13485 set_mode = GET_MODE (SET_DEST (set));
13489 if (req_mode != CCNOmode
13490 && (req_mode != CCmode
13491 || XEXP (SET_SRC (set), 1) != const0_rtx))
13495 if (req_mode == CCGCmode)
13499 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13503 if (req_mode == CCZmode)
13514 gcc_unreachable ();
13517 return (GET_MODE (SET_SRC (set)) == set_mode);
13520 /* Generate insn patterns to do an integer compare of OPERANDS. */
13523 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13525 enum machine_mode cmpmode;
13528 cmpmode = SELECT_CC_MODE (code, op0, op1);
13529 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13531 /* This is very simple, but making the interface the same as in the
13532 FP case makes the rest of the code easier. */
13533 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13534 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13536 /* Return the test that should be put into the flags user, i.e.
13537 the bcc, scc, or cmov instruction. */
13538 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13541 /* Figure out whether to use ordered or unordered fp comparisons.
13542 Return the appropriate mode to use. */
13545 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13547 /* ??? In order to make all comparisons reversible, we do all comparisons
13548 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13549 all forms trapping and nontrapping comparisons, we can make inequality
13550 comparisons trapping again, since it results in better code when using
13551 FCOM based compares. */
13552 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13556 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13558 enum machine_mode mode = GET_MODE (op0);
13560 if (SCALAR_FLOAT_MODE_P (mode))
13562 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13563 return ix86_fp_compare_mode (code);
13568 /* Only zero flag is needed. */
13569 case EQ: /* ZF=0 */
13570 case NE: /* ZF!=0 */
13572 /* Codes needing carry flag. */
13573 case GEU: /* CF=0 */
13574 case LTU: /* CF=1 */
13575 /* Detect overflow checks. They need just the carry flag. */
13576 if (GET_CODE (op0) == PLUS
13577 && rtx_equal_p (op1, XEXP (op0, 0)))
13581 case GTU: /* CF=0 & ZF=0 */
13582 case LEU: /* CF=1 | ZF=1 */
13583 /* Detect overflow checks. They need just the carry flag. */
13584 if (GET_CODE (op0) == MINUS
13585 && rtx_equal_p (op1, XEXP (op0, 0)))
13589 /* Codes possibly doable only with sign flag when
13590 comparing against zero. */
13591 case GE: /* SF=OF or SF=0 */
13592 case LT: /* SF<>OF or SF=1 */
13593 if (op1 == const0_rtx)
13596 /* For other cases Carry flag is not required. */
13598 /* Codes doable only with sign flag when comparing
13599 against zero, but we miss jump instruction for it
13600 so we need to use relational tests against overflow
13601 that thus needs to be zero. */
13602 case GT: /* ZF=0 & SF=OF */
13603 case LE: /* ZF=1 | SF<>OF */
13604 if (op1 == const0_rtx)
13608 /* strcmp pattern do (use flags) and combine may ask us for proper
13613 gcc_unreachable ();
13617 /* Return the fixed registers used for condition codes. */
13620 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13627 /* If two condition code modes are compatible, return a condition code
13628 mode which is compatible with both. Otherwise, return
13631 static enum machine_mode
13632 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13637 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13640 if ((m1 == CCGCmode && m2 == CCGOCmode)
13641 || (m1 == CCGOCmode && m2 == CCGCmode))
13647 gcc_unreachable ();
13677 /* These are only compatible with themselves, which we already
13683 /* Split comparison code CODE into comparisons we can do using branch
13684 instructions. BYPASS_CODE is comparison code for branch that will
13685 branch around FIRST_CODE and SECOND_CODE. If some of branches
13686 is not required, set value to UNKNOWN.
13687 We never require more than two branches. */
13690 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13691 enum rtx_code *first_code,
13692 enum rtx_code *second_code)
13694 *first_code = code;
13695 *bypass_code = UNKNOWN;
13696 *second_code = UNKNOWN;
13698 /* The fcomi comparison sets flags as follows:
13708 case GT: /* GTU - CF=0 & ZF=0 */
13709 case GE: /* GEU - CF=0 */
13710 case ORDERED: /* PF=0 */
13711 case UNORDERED: /* PF=1 */
13712 case UNEQ: /* EQ - ZF=1 */
13713 case UNLT: /* LTU - CF=1 */
13714 case UNLE: /* LEU - CF=1 | ZF=1 */
13715 case LTGT: /* EQ - ZF=0 */
13717 case LT: /* LTU - CF=1 - fails on unordered */
13718 *first_code = UNLT;
13719 *bypass_code = UNORDERED;
13721 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13722 *first_code = UNLE;
13723 *bypass_code = UNORDERED;
13725 case EQ: /* EQ - ZF=1 - fails on unordered */
13726 *first_code = UNEQ;
13727 *bypass_code = UNORDERED;
13729 case NE: /* NE - ZF=0 - fails on unordered */
13730 *first_code = LTGT;
13731 *second_code = UNORDERED;
13733 case UNGE: /* GEU - CF=0 - fails on unordered */
13735 *second_code = UNORDERED;
13737 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13739 *second_code = UNORDERED;
13742 gcc_unreachable ();
13744 if (!TARGET_IEEE_FP)
13746 *second_code = UNKNOWN;
13747 *bypass_code = UNKNOWN;
13751 /* Return cost of comparison done fcom + arithmetics operations on AX.
13752 All following functions do use number of instructions as a cost metrics.
13753 In future this should be tweaked to compute bytes for optimize_size and
13754 take into account performance of various instructions on various CPUs. */
13756 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13758 if (!TARGET_IEEE_FP)
13760 /* The cost of code output by ix86_expand_fp_compare. */
13784 gcc_unreachable ();
13788 /* Return cost of comparison done using fcomi operation.
13789 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13791 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13793 enum rtx_code bypass_code, first_code, second_code;
13794 /* Return arbitrarily high cost when instruction is not supported - this
13795 prevents gcc from using it. */
13798 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13799 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13802 /* Return cost of comparison done using sahf operation.
13803 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13805 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13807 enum rtx_code bypass_code, first_code, second_code;
13808 /* Return arbitrarily high cost when instruction is not preferred - this
13809 avoids gcc from using it. */
13810 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13812 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13813 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13816 /* Compute cost of the comparison done using any method.
13817 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13819 ix86_fp_comparison_cost (enum rtx_code code)
13821 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13824 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13825 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13827 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13828 if (min > sahf_cost)
13830 if (min > fcomi_cost)
13835 /* Return true if we should use an FCOMI instruction for this
13839 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13841 enum rtx_code swapped_code = swap_condition (code);
13843 return ((ix86_fp_comparison_cost (code)
13844 == ix86_fp_comparison_fcomi_cost (code))
13845 || (ix86_fp_comparison_cost (swapped_code)
13846 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13849 /* Swap, force into registers, or otherwise massage the two operands
13850 to a fp comparison. The operands are updated in place; the new
13851 comparison code is returned. */
13853 static enum rtx_code
13854 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13856 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13857 rtx op0 = *pop0, op1 = *pop1;
13858 enum machine_mode op_mode = GET_MODE (op0);
13859 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13861 /* All of the unordered compare instructions only work on registers.
13862 The same is true of the fcomi compare instructions. The XFmode
13863 compare instructions require registers except when comparing
13864 against zero or when converting operand 1 from fixed point to
13868 && (fpcmp_mode == CCFPUmode
13869 || (op_mode == XFmode
13870 && ! (standard_80387_constant_p (op0) == 1
13871 || standard_80387_constant_p (op1) == 1)
13872 && GET_CODE (op1) != FLOAT)
13873 || ix86_use_fcomi_compare (code)))
13875 op0 = force_reg (op_mode, op0);
13876 op1 = force_reg (op_mode, op1);
13880 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13881 things around if they appear profitable, otherwise force op0
13882 into a register. */
13884 if (standard_80387_constant_p (op0) == 0
13886 && ! (standard_80387_constant_p (op1) == 0
13890 tmp = op0, op0 = op1, op1 = tmp;
13891 code = swap_condition (code);
13895 op0 = force_reg (op_mode, op0);
13897 if (CONSTANT_P (op1))
13899 int tmp = standard_80387_constant_p (op1);
13901 op1 = validize_mem (force_const_mem (op_mode, op1));
13905 op1 = force_reg (op_mode, op1);
13908 op1 = force_reg (op_mode, op1);
13912 /* Try to rearrange the comparison to make it cheaper. */
13913 if (ix86_fp_comparison_cost (code)
13914 > ix86_fp_comparison_cost (swap_condition (code))
13915 && (REG_P (op1) || can_create_pseudo_p ()))
13918 tmp = op0, op0 = op1, op1 = tmp;
13919 code = swap_condition (code);
13921 op0 = force_reg (op_mode, op0);
13929 /* Convert comparison codes we use to represent FP comparison to integer
13930 code that will result in proper branch. Return UNKNOWN if no such code
13934 ix86_fp_compare_code_to_integer (enum rtx_code code)
13963 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13966 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13967 rtx *second_test, rtx *bypass_test)
13969 enum machine_mode fpcmp_mode, intcmp_mode;
13971 int cost = ix86_fp_comparison_cost (code);
13972 enum rtx_code bypass_code, first_code, second_code;
13974 fpcmp_mode = ix86_fp_compare_mode (code);
13975 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13978 *second_test = NULL_RTX;
13980 *bypass_test = NULL_RTX;
13982 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13984 /* Do fcomi/sahf based test when profitable. */
13985 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13986 && (bypass_code == UNKNOWN || bypass_test)
13987 && (second_code == UNKNOWN || second_test))
13989 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13990 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13996 gcc_assert (TARGET_SAHF);
13999 scratch = gen_reg_rtx (HImode);
14000 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14002 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14005 /* The FP codes work out to act like unsigned. */
14006 intcmp_mode = fpcmp_mode;
14008 if (bypass_code != UNKNOWN)
14009 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
14010 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14012 if (second_code != UNKNOWN)
14013 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
14014 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14019 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14020 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14021 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14023 scratch = gen_reg_rtx (HImode);
14024 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14026 /* In the unordered case, we have to check C2 for NaN's, which
14027 doesn't happen to work out to anything nice combination-wise.
14028 So do some bit twiddling on the value we've got in AH to come
14029 up with an appropriate set of condition codes. */
14031 intcmp_mode = CCNOmode;
14036 if (code == GT || !TARGET_IEEE_FP)
14038 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14043 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14044 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14045 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14046 intcmp_mode = CCmode;
14052 if (code == LT && TARGET_IEEE_FP)
14054 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14055 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14056 intcmp_mode = CCmode;
14061 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14067 if (code == GE || !TARGET_IEEE_FP)
14069 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14074 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14075 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14082 if (code == LE && TARGET_IEEE_FP)
14084 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14085 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14086 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14087 intcmp_mode = CCmode;
14092 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14098 if (code == EQ && TARGET_IEEE_FP)
14100 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14101 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14102 intcmp_mode = CCmode;
14107 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14114 if (code == NE && TARGET_IEEE_FP)
14116 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14117 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14123 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14129 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14133 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14138 gcc_unreachable ();
14142 /* Return the test that should be put into the flags user, i.e.
14143 the bcc, scc, or cmov instruction. */
14144 return gen_rtx_fmt_ee (code, VOIDmode,
14145 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14150 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14153 op0 = ix86_compare_op0;
14154 op1 = ix86_compare_op1;
14157 *second_test = NULL_RTX;
14159 *bypass_test = NULL_RTX;
14161 if (ix86_compare_emitted)
14163 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14164 ix86_compare_emitted = NULL_RTX;
14166 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14168 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14169 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14170 second_test, bypass_test);
14173 ret = ix86_expand_int_compare (code, op0, op1);
14178 /* Return true if the CODE will result in nontrivial jump sequence. */
14180 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14182 enum rtx_code bypass_code, first_code, second_code;
14185 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14186 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14190 ix86_expand_branch (enum rtx_code code, rtx label)
14194 /* If we have emitted a compare insn, go straight to simple.
14195 ix86_expand_compare won't emit anything if ix86_compare_emitted
14197 if (ix86_compare_emitted)
14200 switch (GET_MODE (ix86_compare_op0))
14206 tmp = ix86_expand_compare (code, NULL, NULL);
14207 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14208 gen_rtx_LABEL_REF (VOIDmode, label),
14210 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14219 enum rtx_code bypass_code, first_code, second_code;
14221 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14222 &ix86_compare_op1);
14224 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14226 /* Check whether we will use the natural sequence with one jump. If
14227 so, we can expand jump early. Otherwise delay expansion by
14228 creating compound insn to not confuse optimizers. */
14229 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14231 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14232 gen_rtx_LABEL_REF (VOIDmode, label),
14233 pc_rtx, NULL_RTX, NULL_RTX);
14237 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14238 ix86_compare_op0, ix86_compare_op1);
14239 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14240 gen_rtx_LABEL_REF (VOIDmode, label),
14242 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14244 use_fcomi = ix86_use_fcomi_compare (code);
14245 vec = rtvec_alloc (3 + !use_fcomi);
14246 RTVEC_ELT (vec, 0) = tmp;
14248 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14250 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14253 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14255 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14264 /* Expand DImode branch into multiple compare+branch. */
14266 rtx lo[2], hi[2], label2;
14267 enum rtx_code code1, code2, code3;
14268 enum machine_mode submode;
14270 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14272 tmp = ix86_compare_op0;
14273 ix86_compare_op0 = ix86_compare_op1;
14274 ix86_compare_op1 = tmp;
14275 code = swap_condition (code);
14277 if (GET_MODE (ix86_compare_op0) == DImode)
14279 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14280 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14285 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14286 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14290 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14291 avoid two branches. This costs one extra insn, so disable when
14292 optimizing for size. */
14294 if ((code == EQ || code == NE)
14295 && (!optimize_insn_for_size_p ()
14296 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14301 if (hi[1] != const0_rtx)
14302 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14303 NULL_RTX, 0, OPTAB_WIDEN);
14306 if (lo[1] != const0_rtx)
14307 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14308 NULL_RTX, 0, OPTAB_WIDEN);
14310 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14311 NULL_RTX, 0, OPTAB_WIDEN);
14313 ix86_compare_op0 = tmp;
14314 ix86_compare_op1 = const0_rtx;
14315 ix86_expand_branch (code, label);
14319 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14320 op1 is a constant and the low word is zero, then we can just
14321 examine the high word. Similarly for low word -1 and
14322 less-or-equal-than or greater-than. */
14324 if (CONST_INT_P (hi[1]))
14327 case LT: case LTU: case GE: case GEU:
14328 if (lo[1] == const0_rtx)
14330 ix86_compare_op0 = hi[0];
14331 ix86_compare_op1 = hi[1];
14332 ix86_expand_branch (code, label);
14336 case LE: case LEU: case GT: case GTU:
14337 if (lo[1] == constm1_rtx)
14339 ix86_compare_op0 = hi[0];
14340 ix86_compare_op1 = hi[1];
14341 ix86_expand_branch (code, label);
14349 /* Otherwise, we need two or three jumps. */
14351 label2 = gen_label_rtx ();
14354 code2 = swap_condition (code);
14355 code3 = unsigned_condition (code);
14359 case LT: case GT: case LTU: case GTU:
14362 case LE: code1 = LT; code2 = GT; break;
14363 case GE: code1 = GT; code2 = LT; break;
14364 case LEU: code1 = LTU; code2 = GTU; break;
14365 case GEU: code1 = GTU; code2 = LTU; break;
14367 case EQ: code1 = UNKNOWN; code2 = NE; break;
14368 case NE: code2 = UNKNOWN; break;
14371 gcc_unreachable ();
14376 * if (hi(a) < hi(b)) goto true;
14377 * if (hi(a) > hi(b)) goto false;
14378 * if (lo(a) < lo(b)) goto true;
14382 ix86_compare_op0 = hi[0];
14383 ix86_compare_op1 = hi[1];
14385 if (code1 != UNKNOWN)
14386 ix86_expand_branch (code1, label);
14387 if (code2 != UNKNOWN)
14388 ix86_expand_branch (code2, label2);
14390 ix86_compare_op0 = lo[0];
14391 ix86_compare_op1 = lo[1];
14392 ix86_expand_branch (code3, label);
14394 if (code2 != UNKNOWN)
14395 emit_label (label2);
14400 gcc_unreachable ();
14404 /* Split branch based on floating point condition. */
14406 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14407 rtx target1, rtx target2, rtx tmp, rtx pushed)
14409 rtx second, bypass;
14410 rtx label = NULL_RTX;
14412 int bypass_probability = -1, second_probability = -1, probability = -1;
14415 if (target2 != pc_rtx)
14418 code = reverse_condition_maybe_unordered (code);
14423 condition = ix86_expand_fp_compare (code, op1, op2,
14424 tmp, &second, &bypass);
14426 /* Remove pushed operand from stack. */
14428 ix86_free_from_memory (GET_MODE (pushed));
14430 if (split_branch_probability >= 0)
14432 /* Distribute the probabilities across the jumps.
14433 Assume the BYPASS and SECOND to be always test
14435 probability = split_branch_probability;
14437 /* Value of 1 is low enough to make no need for probability
14438 to be updated. Later we may run some experiments and see
14439 if unordered values are more frequent in practice. */
14441 bypass_probability = 1;
14443 second_probability = 1;
14445 if (bypass != NULL_RTX)
14447 label = gen_label_rtx ();
14448 i = emit_jump_insn (gen_rtx_SET
14450 gen_rtx_IF_THEN_ELSE (VOIDmode,
14452 gen_rtx_LABEL_REF (VOIDmode,
14455 if (bypass_probability >= 0)
14457 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14458 GEN_INT (bypass_probability),
14461 i = emit_jump_insn (gen_rtx_SET
14463 gen_rtx_IF_THEN_ELSE (VOIDmode,
14464 condition, target1, target2)));
14465 if (probability >= 0)
14467 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14468 GEN_INT (probability),
14470 if (second != NULL_RTX)
14472 i = emit_jump_insn (gen_rtx_SET
14474 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14476 if (second_probability >= 0)
14478 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14479 GEN_INT (second_probability),
14482 if (label != NULL_RTX)
14483 emit_label (label);
14487 ix86_expand_setcc (enum rtx_code code, rtx dest)
14489 rtx ret, tmp, tmpreg, equiv;
14490 rtx second_test, bypass_test;
14492 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14493 return 0; /* FAIL */
14495 gcc_assert (GET_MODE (dest) == QImode);
14497 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14498 PUT_MODE (ret, QImode);
14503 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14504 if (bypass_test || second_test)
14506 rtx test = second_test;
14508 rtx tmp2 = gen_reg_rtx (QImode);
14511 gcc_assert (!second_test);
14512 test = bypass_test;
14514 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14516 PUT_MODE (test, QImode);
14517 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14520 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14522 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14525 /* Attach a REG_EQUAL note describing the comparison result. */
14526 if (ix86_compare_op0 && ix86_compare_op1)
14528 equiv = simplify_gen_relational (code, QImode,
14529 GET_MODE (ix86_compare_op0),
14530 ix86_compare_op0, ix86_compare_op1);
14531 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14534 return 1; /* DONE */
14537 /* Expand comparison setting or clearing carry flag. Return true when
14538 successful and set pop for the operation. */
14540 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14542 enum machine_mode mode =
14543 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14545 /* Do not handle DImode compares that go through special path. */
14546 if (mode == (TARGET_64BIT ? TImode : DImode))
14549 if (SCALAR_FLOAT_MODE_P (mode))
14551 rtx second_test = NULL, bypass_test = NULL;
14552 rtx compare_op, compare_seq;
14554 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14556 /* Shortcut: following common codes never translate
14557 into carry flag compares. */
14558 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14559 || code == ORDERED || code == UNORDERED)
14562 /* These comparisons require zero flag; swap operands so they won't. */
14563 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14564 && !TARGET_IEEE_FP)
14569 code = swap_condition (code);
14572 /* Try to expand the comparison and verify that we end up with
14573 carry flag based comparison. This fails to be true only when
14574 we decide to expand comparison using arithmetic that is not
14575 too common scenario. */
14577 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14578 &second_test, &bypass_test);
14579 compare_seq = get_insns ();
14582 if (second_test || bypass_test)
14585 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14586 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14587 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14589 code = GET_CODE (compare_op);
14591 if (code != LTU && code != GEU)
14594 emit_insn (compare_seq);
14599 if (!INTEGRAL_MODE_P (mode))
14608 /* Convert a==0 into (unsigned)a<1. */
14611 if (op1 != const0_rtx)
14614 code = (code == EQ ? LTU : GEU);
14617 /* Convert a>b into b<a or a>=b-1. */
14620 if (CONST_INT_P (op1))
14622 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14623 /* Bail out on overflow. We still can swap operands but that
14624 would force loading of the constant into register. */
14625 if (op1 == const0_rtx
14626 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14628 code = (code == GTU ? GEU : LTU);
14635 code = (code == GTU ? LTU : GEU);
14639 /* Convert a>=0 into (unsigned)a<0x80000000. */
14642 if (mode == DImode || op1 != const0_rtx)
14644 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14645 code = (code == LT ? GEU : LTU);
14649 if (mode == DImode || op1 != constm1_rtx)
14651 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14652 code = (code == LE ? GEU : LTU);
14658 /* Swapping operands may cause constant to appear as first operand. */
14659 if (!nonimmediate_operand (op0, VOIDmode))
14661 if (!can_create_pseudo_p ())
14663 op0 = force_reg (mode, op0);
14665 ix86_compare_op0 = op0;
14666 ix86_compare_op1 = op1;
14667 *pop = ix86_expand_compare (code, NULL, NULL);
14668 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14673 ix86_expand_int_movcc (rtx operands[])
14675 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14676 rtx compare_seq, compare_op;
14677 rtx second_test, bypass_test;
14678 enum machine_mode mode = GET_MODE (operands[0]);
14679 bool sign_bit_compare_p = false;;
14682 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14683 compare_seq = get_insns ();
14686 compare_code = GET_CODE (compare_op);
14688 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14689 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14690 sign_bit_compare_p = true;
14692 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14693 HImode insns, we'd be swallowed in word prefix ops. */
14695 if ((mode != HImode || TARGET_FAST_PREFIX)
14696 && (mode != (TARGET_64BIT ? TImode : DImode))
14697 && CONST_INT_P (operands[2])
14698 && CONST_INT_P (operands[3]))
14700 rtx out = operands[0];
14701 HOST_WIDE_INT ct = INTVAL (operands[2]);
14702 HOST_WIDE_INT cf = INTVAL (operands[3]);
14703 HOST_WIDE_INT diff;
14706 /* Sign bit compares are better done using shifts than we do by using
14708 if (sign_bit_compare_p
14709 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14710 ix86_compare_op1, &compare_op))
14712 /* Detect overlap between destination and compare sources. */
14715 if (!sign_bit_compare_p)
14717 bool fpcmp = false;
14719 compare_code = GET_CODE (compare_op);
14721 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14722 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14725 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14728 /* To simplify rest of code, restrict to the GEU case. */
14729 if (compare_code == LTU)
14731 HOST_WIDE_INT tmp = ct;
14734 compare_code = reverse_condition (compare_code);
14735 code = reverse_condition (code);
14740 PUT_CODE (compare_op,
14741 reverse_condition_maybe_unordered
14742 (GET_CODE (compare_op)));
14744 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14748 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14749 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14750 tmp = gen_reg_rtx (mode);
14752 if (mode == DImode)
14753 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14755 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14759 if (code == GT || code == GE)
14760 code = reverse_condition (code);
14763 HOST_WIDE_INT tmp = ct;
14768 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14769 ix86_compare_op1, VOIDmode, 0, -1);
14782 tmp = expand_simple_binop (mode, PLUS,
14784 copy_rtx (tmp), 1, OPTAB_DIRECT);
14795 tmp = expand_simple_binop (mode, IOR,
14797 copy_rtx (tmp), 1, OPTAB_DIRECT);
14799 else if (diff == -1 && ct)
14809 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14811 tmp = expand_simple_binop (mode, PLUS,
14812 copy_rtx (tmp), GEN_INT (cf),
14813 copy_rtx (tmp), 1, OPTAB_DIRECT);
14821 * andl cf - ct, dest
14831 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14834 tmp = expand_simple_binop (mode, AND,
14836 gen_int_mode (cf - ct, mode),
14837 copy_rtx (tmp), 1, OPTAB_DIRECT);
14839 tmp = expand_simple_binop (mode, PLUS,
14840 copy_rtx (tmp), GEN_INT (ct),
14841 copy_rtx (tmp), 1, OPTAB_DIRECT);
14844 if (!rtx_equal_p (tmp, out))
14845 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14847 return 1; /* DONE */
14852 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14855 tmp = ct, ct = cf, cf = tmp;
14858 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14860 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14862 /* We may be reversing unordered compare to normal compare, that
14863 is not valid in general (we may convert non-trapping condition
14864 to trapping one), however on i386 we currently emit all
14865 comparisons unordered. */
14866 compare_code = reverse_condition_maybe_unordered (compare_code);
14867 code = reverse_condition_maybe_unordered (code);
14871 compare_code = reverse_condition (compare_code);
14872 code = reverse_condition (code);
14876 compare_code = UNKNOWN;
14877 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14878 && CONST_INT_P (ix86_compare_op1))
14880 if (ix86_compare_op1 == const0_rtx
14881 && (code == LT || code == GE))
14882 compare_code = code;
14883 else if (ix86_compare_op1 == constm1_rtx)
14887 else if (code == GT)
14892 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14893 if (compare_code != UNKNOWN
14894 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14895 && (cf == -1 || ct == -1))
14897 /* If lea code below could be used, only optimize
14898 if it results in a 2 insn sequence. */
14900 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14901 || diff == 3 || diff == 5 || diff == 9)
14902 || (compare_code == LT && ct == -1)
14903 || (compare_code == GE && cf == -1))
14906 * notl op1 (if necessary)
14914 code = reverse_condition (code);
14917 out = emit_store_flag (out, code, ix86_compare_op0,
14918 ix86_compare_op1, VOIDmode, 0, -1);
14920 out = expand_simple_binop (mode, IOR,
14922 out, 1, OPTAB_DIRECT);
14923 if (out != operands[0])
14924 emit_move_insn (operands[0], out);
14926 return 1; /* DONE */
14931 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14932 || diff == 3 || diff == 5 || diff == 9)
14933 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14935 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14941 * lea cf(dest*(ct-cf)),dest
14945 * This also catches the degenerate setcc-only case.
14951 out = emit_store_flag (out, code, ix86_compare_op0,
14952 ix86_compare_op1, VOIDmode, 0, 1);
14955 /* On x86_64 the lea instruction operates on Pmode, so we need
14956 to get arithmetics done in proper mode to match. */
14958 tmp = copy_rtx (out);
14962 out1 = copy_rtx (out);
14963 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14967 tmp = gen_rtx_PLUS (mode, tmp, out1);
14973 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14976 if (!rtx_equal_p (tmp, out))
14979 out = force_operand (tmp, copy_rtx (out));
14981 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14983 if (!rtx_equal_p (out, operands[0]))
14984 emit_move_insn (operands[0], copy_rtx (out));
14986 return 1; /* DONE */
14990 * General case: Jumpful:
14991 * xorl dest,dest cmpl op1, op2
14992 * cmpl op1, op2 movl ct, dest
14993 * setcc dest jcc 1f
14994 * decl dest movl cf, dest
14995 * andl (cf-ct),dest 1:
14998 * Size 20. Size 14.
15000 * This is reasonably steep, but branch mispredict costs are
15001 * high on modern cpus, so consider failing only if optimizing
15005 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15006 && BRANCH_COST (optimize_insn_for_speed_p (),
15011 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15016 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15018 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15020 /* We may be reversing unordered compare to normal compare,
15021 that is not valid in general (we may convert non-trapping
15022 condition to trapping one), however on i386 we currently
15023 emit all comparisons unordered. */
15024 code = reverse_condition_maybe_unordered (code);
15028 code = reverse_condition (code);
15029 if (compare_code != UNKNOWN)
15030 compare_code = reverse_condition (compare_code);
15034 if (compare_code != UNKNOWN)
15036 /* notl op1 (if needed)
15041 For x < 0 (resp. x <= -1) there will be no notl,
15042 so if possible swap the constants to get rid of the
15044 True/false will be -1/0 while code below (store flag
15045 followed by decrement) is 0/-1, so the constants need
15046 to be exchanged once more. */
15048 if (compare_code == GE || !cf)
15050 code = reverse_condition (code);
15055 HOST_WIDE_INT tmp = cf;
15060 out = emit_store_flag (out, code, ix86_compare_op0,
15061 ix86_compare_op1, VOIDmode, 0, -1);
15065 out = emit_store_flag (out, code, ix86_compare_op0,
15066 ix86_compare_op1, VOIDmode, 0, 1);
15068 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15069 copy_rtx (out), 1, OPTAB_DIRECT);
15072 out = expand_simple_binop (mode, AND, copy_rtx (out),
15073 gen_int_mode (cf - ct, mode),
15074 copy_rtx (out), 1, OPTAB_DIRECT);
15076 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15077 copy_rtx (out), 1, OPTAB_DIRECT);
15078 if (!rtx_equal_p (out, operands[0]))
15079 emit_move_insn (operands[0], copy_rtx (out));
15081 return 1; /* DONE */
15085 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15087 /* Try a few things more with specific constants and a variable. */
15090 rtx var, orig_out, out, tmp;
15092 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15093 return 0; /* FAIL */
15095 /* If one of the two operands is an interesting constant, load a
15096 constant with the above and mask it in with a logical operation. */
15098 if (CONST_INT_P (operands[2]))
15101 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15102 operands[3] = constm1_rtx, op = and_optab;
15103 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15104 operands[3] = const0_rtx, op = ior_optab;
15106 return 0; /* FAIL */
15108 else if (CONST_INT_P (operands[3]))
15111 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15112 operands[2] = constm1_rtx, op = and_optab;
15113 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15114 operands[2] = const0_rtx, op = ior_optab;
15116 return 0; /* FAIL */
15119 return 0; /* FAIL */
15121 orig_out = operands[0];
15122 tmp = gen_reg_rtx (mode);
15125 /* Recurse to get the constant loaded. */
15126 if (ix86_expand_int_movcc (operands) == 0)
15127 return 0; /* FAIL */
15129 /* Mask in the interesting variable. */
15130 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15132 if (!rtx_equal_p (out, orig_out))
15133 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15135 return 1; /* DONE */
15139 * For comparison with above,
15149 if (! nonimmediate_operand (operands[2], mode))
15150 operands[2] = force_reg (mode, operands[2]);
15151 if (! nonimmediate_operand (operands[3], mode))
15152 operands[3] = force_reg (mode, operands[3]);
15154 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15156 rtx tmp = gen_reg_rtx (mode);
15157 emit_move_insn (tmp, operands[3]);
15160 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15162 rtx tmp = gen_reg_rtx (mode);
15163 emit_move_insn (tmp, operands[2]);
15167 if (! register_operand (operands[2], VOIDmode)
15169 || ! register_operand (operands[3], VOIDmode)))
15170 operands[2] = force_reg (mode, operands[2]);
15173 && ! register_operand (operands[3], VOIDmode))
15174 operands[3] = force_reg (mode, operands[3]);
15176 emit_insn (compare_seq);
15177 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15178 gen_rtx_IF_THEN_ELSE (mode,
15179 compare_op, operands[2],
15182 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15183 gen_rtx_IF_THEN_ELSE (mode,
15185 copy_rtx (operands[3]),
15186 copy_rtx (operands[0]))));
15188 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15189 gen_rtx_IF_THEN_ELSE (mode,
15191 copy_rtx (operands[2]),
15192 copy_rtx (operands[0]))));
15194 return 1; /* DONE */
15197 /* Swap, force into registers, or otherwise massage the two operands
15198 to an sse comparison with a mask result. Thus we differ a bit from
15199 ix86_prepare_fp_compare_args which expects to produce a flags result.
15201 The DEST operand exists to help determine whether to commute commutative
15202 operators. The POP0/POP1 operands are updated in place. The new
15203 comparison code is returned, or UNKNOWN if not implementable. */
15205 static enum rtx_code
15206 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15207 rtx *pop0, rtx *pop1)
15215 /* We have no LTGT as an operator. We could implement it with
15216 NE & ORDERED, but this requires an extra temporary. It's
15217 not clear that it's worth it. */
15224 /* These are supported directly. */
15231 /* For commutative operators, try to canonicalize the destination
15232 operand to be first in the comparison - this helps reload to
15233 avoid extra moves. */
15234 if (!dest || !rtx_equal_p (dest, *pop1))
15242 /* These are not supported directly. Swap the comparison operands
15243 to transform into something that is supported. */
15247 code = swap_condition (code);
15251 gcc_unreachable ();
15257 /* Detect conditional moves that exactly match min/max operational
15258 semantics. Note that this is IEEE safe, as long as we don't
15259 interchange the operands.
15261 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15262 and TRUE if the operation is successful and instructions are emitted. */
15265 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15266 rtx cmp_op1, rtx if_true, rtx if_false)
15268 enum machine_mode mode;
15274 else if (code == UNGE)
15277 if_true = if_false;
15283 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15285 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15290 mode = GET_MODE (dest);
15292 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15293 but MODE may be a vector mode and thus not appropriate. */
15294 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15296 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15299 if_true = force_reg (mode, if_true);
15300 v = gen_rtvec (2, if_true, if_false);
15301 tmp = gen_rtx_UNSPEC (mode, v, u);
15305 code = is_min ? SMIN : SMAX;
15306 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15309 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15313 /* Expand an sse vector comparison. Return the register with the result. */
15316 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15317 rtx op_true, rtx op_false)
15319 enum machine_mode mode = GET_MODE (dest);
15322 cmp_op0 = force_reg (mode, cmp_op0);
15323 if (!nonimmediate_operand (cmp_op1, mode))
15324 cmp_op1 = force_reg (mode, cmp_op1);
15327 || reg_overlap_mentioned_p (dest, op_true)
15328 || reg_overlap_mentioned_p (dest, op_false))
15329 dest = gen_reg_rtx (mode);
15331 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15332 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15337 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15338 operations. This is used for both scalar and vector conditional moves. */
15341 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15343 enum machine_mode mode = GET_MODE (dest);
15346 if (op_false == CONST0_RTX (mode))
15348 op_true = force_reg (mode, op_true);
15349 x = gen_rtx_AND (mode, cmp, op_true);
15350 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15352 else if (op_true == CONST0_RTX (mode))
15354 op_false = force_reg (mode, op_false);
15355 x = gen_rtx_NOT (mode, cmp);
15356 x = gen_rtx_AND (mode, x, op_false);
15357 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15359 else if (TARGET_SSE5)
15361 rtx pcmov = gen_rtx_SET (mode, dest,
15362 gen_rtx_IF_THEN_ELSE (mode, cmp,
15369 op_true = force_reg (mode, op_true);
15370 op_false = force_reg (mode, op_false);
15372 t2 = gen_reg_rtx (mode);
15374 t3 = gen_reg_rtx (mode);
15378 x = gen_rtx_AND (mode, op_true, cmp);
15379 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15381 x = gen_rtx_NOT (mode, cmp);
15382 x = gen_rtx_AND (mode, x, op_false);
15383 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15385 x = gen_rtx_IOR (mode, t3, t2);
15386 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15390 /* Expand a floating-point conditional move. Return true if successful. */
15393 ix86_expand_fp_movcc (rtx operands[])
15395 enum machine_mode mode = GET_MODE (operands[0]);
15396 enum rtx_code code = GET_CODE (operands[1]);
15397 rtx tmp, compare_op, second_test, bypass_test;
15399 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15401 enum machine_mode cmode;
15403 /* Since we've no cmove for sse registers, don't force bad register
15404 allocation just to gain access to it. Deny movcc when the
15405 comparison mode doesn't match the move mode. */
15406 cmode = GET_MODE (ix86_compare_op0);
15407 if (cmode == VOIDmode)
15408 cmode = GET_MODE (ix86_compare_op1);
15412 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15414 &ix86_compare_op1);
15415 if (code == UNKNOWN)
15418 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15419 ix86_compare_op1, operands[2],
15423 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15424 ix86_compare_op1, operands[2], operands[3]);
15425 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15429 /* The floating point conditional move instructions don't directly
15430 support conditions resulting from a signed integer comparison. */
15432 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15434 /* The floating point conditional move instructions don't directly
15435 support signed integer comparisons. */
15437 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15439 gcc_assert (!second_test && !bypass_test);
15440 tmp = gen_reg_rtx (QImode);
15441 ix86_expand_setcc (code, tmp);
15443 ix86_compare_op0 = tmp;
15444 ix86_compare_op1 = const0_rtx;
15445 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15447 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15449 tmp = gen_reg_rtx (mode);
15450 emit_move_insn (tmp, operands[3]);
15453 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15455 tmp = gen_reg_rtx (mode);
15456 emit_move_insn (tmp, operands[2]);
15460 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15461 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15462 operands[2], operands[3])));
15464 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15465 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15466 operands[3], operands[0])));
15468 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15469 gen_rtx_IF_THEN_ELSE (mode, second_test,
15470 operands[2], operands[0])));
15475 /* Expand a floating-point vector conditional move; a vcond operation
15476 rather than a movcc operation. */
15479 ix86_expand_fp_vcond (rtx operands[])
15481 enum rtx_code code = GET_CODE (operands[3]);
15484 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15485 &operands[4], &operands[5]);
15486 if (code == UNKNOWN)
15489 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15490 operands[5], operands[1], operands[2]))
15493 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15494 operands[1], operands[2]);
15495 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15499 /* Expand a signed/unsigned integral vector conditional move. */
15502 ix86_expand_int_vcond (rtx operands[])
15504 enum machine_mode mode = GET_MODE (operands[0]);
15505 enum rtx_code code = GET_CODE (operands[3]);
15506 bool negate = false;
15509 cop0 = operands[4];
15510 cop1 = operands[5];
15512 /* SSE5 supports all of the comparisons on all vector int types. */
15515 /* Canonicalize the comparison to EQ, GT, GTU. */
15526 code = reverse_condition (code);
15532 code = reverse_condition (code);
15538 code = swap_condition (code);
15539 x = cop0, cop0 = cop1, cop1 = x;
15543 gcc_unreachable ();
15546 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15547 if (mode == V2DImode)
15552 /* SSE4.1 supports EQ. */
15553 if (!TARGET_SSE4_1)
15559 /* SSE4.2 supports GT/GTU. */
15560 if (!TARGET_SSE4_2)
15565 gcc_unreachable ();
15569 /* Unsigned parallel compare is not supported by the hardware. Play some
15570 tricks to turn this into a signed comparison against 0. */
15573 cop0 = force_reg (mode, cop0);
15582 /* Perform a parallel modulo subtraction. */
15583 t1 = gen_reg_rtx (mode);
15584 emit_insn ((mode == V4SImode
15586 : gen_subv2di3) (t1, cop0, cop1));
15588 /* Extract the original sign bit of op0. */
15589 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15591 t2 = gen_reg_rtx (mode);
15592 emit_insn ((mode == V4SImode
15594 : gen_andv2di3) (t2, cop0, mask));
15596 /* XOR it back into the result of the subtraction. This results
15597 in the sign bit set iff we saw unsigned underflow. */
15598 x = gen_reg_rtx (mode);
15599 emit_insn ((mode == V4SImode
15601 : gen_xorv2di3) (x, t1, t2));
15609 /* Perform a parallel unsigned saturating subtraction. */
15610 x = gen_reg_rtx (mode);
15611 emit_insn (gen_rtx_SET (VOIDmode, x,
15612 gen_rtx_US_MINUS (mode, cop0, cop1)));
15619 gcc_unreachable ();
15623 cop1 = CONST0_RTX (mode);
15627 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15628 operands[1+negate], operands[2-negate]);
15630 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15631 operands[2-negate]);
15635 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15636 true if we should do zero extension, else sign extension. HIGH_P is
15637 true if we want the N/2 high elements, else the low elements. */
15640 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15642 enum machine_mode imode = GET_MODE (operands[1]);
15643 rtx (*unpack)(rtx, rtx, rtx);
15650 unpack = gen_vec_interleave_highv16qi;
15652 unpack = gen_vec_interleave_lowv16qi;
15656 unpack = gen_vec_interleave_highv8hi;
15658 unpack = gen_vec_interleave_lowv8hi;
15662 unpack = gen_vec_interleave_highv4si;
15664 unpack = gen_vec_interleave_lowv4si;
15667 gcc_unreachable ();
15670 dest = gen_lowpart (imode, operands[0]);
15673 se = force_reg (imode, CONST0_RTX (imode));
15675 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15676 operands[1], pc_rtx, pc_rtx);
15678 emit_insn (unpack (dest, operands[1], se));
15681 /* This function performs the same task as ix86_expand_sse_unpack,
15682 but with SSE4.1 instructions. */
15685 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15687 enum machine_mode imode = GET_MODE (operands[1]);
15688 rtx (*unpack)(rtx, rtx);
15695 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15697 unpack = gen_sse4_1_extendv8qiv8hi2;
15701 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15703 unpack = gen_sse4_1_extendv4hiv4si2;
15707 unpack = gen_sse4_1_zero_extendv2siv2di2;
15709 unpack = gen_sse4_1_extendv2siv2di2;
15712 gcc_unreachable ();
15715 dest = operands[0];
15718 /* Shift higher 8 bytes to lower 8 bytes. */
15719 src = gen_reg_rtx (imode);
15720 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15721 gen_lowpart (TImode, operands[1]),
15727 emit_insn (unpack (dest, src));
15730 /* This function performs the same task as ix86_expand_sse_unpack,
15731 but with sse5 instructions. */
15734 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15736 enum machine_mode imode = GET_MODE (operands[1]);
15737 int pperm_bytes[16];
15739 int h = (high_p) ? 8 : 0;
15742 rtvec v = rtvec_alloc (16);
15745 rtx op0 = operands[0], op1 = operands[1];
15750 vs = rtvec_alloc (8);
15751 h2 = (high_p) ? 8 : 0;
15752 for (i = 0; i < 8; i++)
15754 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15755 pperm_bytes[2*i+1] = ((unsigned_p)
15757 : PPERM_SIGN | PPERM_SRC2 | i | h);
15760 for (i = 0; i < 16; i++)
15761 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15763 for (i = 0; i < 8; i++)
15764 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15766 p = gen_rtx_PARALLEL (VOIDmode, vs);
15767 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15769 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15771 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15775 vs = rtvec_alloc (4);
15776 h2 = (high_p) ? 4 : 0;
15777 for (i = 0; i < 4; i++)
15779 sign_extend = ((unsigned_p)
15781 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15782 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15783 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15784 pperm_bytes[4*i+2] = sign_extend;
15785 pperm_bytes[4*i+3] = sign_extend;
15788 for (i = 0; i < 16; i++)
15789 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15791 for (i = 0; i < 4; i++)
15792 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15794 p = gen_rtx_PARALLEL (VOIDmode, vs);
15795 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15797 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15799 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15803 vs = rtvec_alloc (2);
15804 h2 = (high_p) ? 2 : 0;
15805 for (i = 0; i < 2; i++)
15807 sign_extend = ((unsigned_p)
15809 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15810 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15811 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15812 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15813 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15814 pperm_bytes[8*i+4] = sign_extend;
15815 pperm_bytes[8*i+5] = sign_extend;
15816 pperm_bytes[8*i+6] = sign_extend;
15817 pperm_bytes[8*i+7] = sign_extend;
15820 for (i = 0; i < 16; i++)
15821 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15823 for (i = 0; i < 2; i++)
15824 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15826 p = gen_rtx_PARALLEL (VOIDmode, vs);
15827 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15829 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15831 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15835 gcc_unreachable ();
15841 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15842 next narrower integer vector type */
15844 ix86_expand_sse5_pack (rtx operands[3])
15846 enum machine_mode imode = GET_MODE (operands[0]);
15847 int pperm_bytes[16];
15849 rtvec v = rtvec_alloc (16);
15851 rtx op0 = operands[0];
15852 rtx op1 = operands[1];
15853 rtx op2 = operands[2];
15858 for (i = 0; i < 8; i++)
15860 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15861 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15864 for (i = 0; i < 16; i++)
15865 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15867 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15868 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15872 for (i = 0; i < 4; i++)
15874 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15875 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15876 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15877 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15880 for (i = 0; i < 16; i++)
15881 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15883 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15884 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15888 for (i = 0; i < 2; i++)
15890 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15891 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15892 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15893 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15894 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15895 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15896 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15897 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15900 for (i = 0; i < 16; i++)
15901 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15903 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15904 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15908 gcc_unreachable ();
15914 /* Expand conditional increment or decrement using adb/sbb instructions.
15915 The default case using setcc followed by the conditional move can be
15916 done by generic code. */
15918 ix86_expand_int_addcc (rtx operands[])
15920 enum rtx_code code = GET_CODE (operands[1]);
15922 rtx val = const0_rtx;
15923 bool fpcmp = false;
15924 enum machine_mode mode = GET_MODE (operands[0]);
15926 if (operands[3] != const1_rtx
15927 && operands[3] != constm1_rtx)
15929 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15930 ix86_compare_op1, &compare_op))
15932 code = GET_CODE (compare_op);
15934 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15935 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15938 code = ix86_fp_compare_code_to_integer (code);
15945 PUT_CODE (compare_op,
15946 reverse_condition_maybe_unordered
15947 (GET_CODE (compare_op)));
15949 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15951 PUT_MODE (compare_op, mode);
15953 /* Construct either adc or sbb insn. */
15954 if ((code == LTU) == (operands[3] == constm1_rtx))
15956 switch (GET_MODE (operands[0]))
15959 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15962 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15965 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15968 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15971 gcc_unreachable ();
15976 switch (GET_MODE (operands[0]))
15979 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15982 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15985 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15988 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15991 gcc_unreachable ();
15994 return 1; /* DONE */
15998 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15999 works for floating pointer parameters and nonoffsetable memories.
16000 For pushes, it returns just stack offsets; the values will be saved
16001 in the right order. Maximally three parts are generated. */
16004 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16009 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16011 size = (GET_MODE_SIZE (mode) + 4) / 8;
16013 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16014 gcc_assert (size >= 2 && size <= 4);
16016 /* Optimize constant pool reference to immediates. This is used by fp
16017 moves, that force all constants to memory to allow combining. */
16018 if (MEM_P (operand) && MEM_READONLY_P (operand))
16020 rtx tmp = maybe_get_pool_constant (operand);
16025 if (MEM_P (operand) && !offsettable_memref_p (operand))
16027 /* The only non-offsetable memories we handle are pushes. */
16028 int ok = push_operand (operand, VOIDmode);
16032 operand = copy_rtx (operand);
16033 PUT_MODE (operand, Pmode);
16034 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16038 if (GET_CODE (operand) == CONST_VECTOR)
16040 enum machine_mode imode = int_mode_for_mode (mode);
16041 /* Caution: if we looked through a constant pool memory above,
16042 the operand may actually have a different mode now. That's
16043 ok, since we want to pun this all the way back to an integer. */
16044 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16045 gcc_assert (operand != NULL);
16051 if (mode == DImode)
16052 split_di (&operand, 1, &parts[0], &parts[1]);
16057 if (REG_P (operand))
16059 gcc_assert (reload_completed);
16060 for (i = 0; i < size; i++)
16061 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16063 else if (offsettable_memref_p (operand))
16065 operand = adjust_address (operand, SImode, 0);
16066 parts[0] = operand;
16067 for (i = 1; i < size; i++)
16068 parts[i] = adjust_address (operand, SImode, 4 * i);
16070 else if (GET_CODE (operand) == CONST_DOUBLE)
16075 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16079 real_to_target (l, &r, mode);
16080 parts[3] = gen_int_mode (l[3], SImode);
16081 parts[2] = gen_int_mode (l[2], SImode);
16084 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16085 parts[2] = gen_int_mode (l[2], SImode);
16088 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16091 gcc_unreachable ();
16093 parts[1] = gen_int_mode (l[1], SImode);
16094 parts[0] = gen_int_mode (l[0], SImode);
16097 gcc_unreachable ();
16102 if (mode == TImode)
16103 split_ti (&operand, 1, &parts[0], &parts[1]);
16104 if (mode == XFmode || mode == TFmode)
16106 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16107 if (REG_P (operand))
16109 gcc_assert (reload_completed);
16110 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16111 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16113 else if (offsettable_memref_p (operand))
16115 operand = adjust_address (operand, DImode, 0);
16116 parts[0] = operand;
16117 parts[1] = adjust_address (operand, upper_mode, 8);
16119 else if (GET_CODE (operand) == CONST_DOUBLE)
16124 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16125 real_to_target (l, &r, mode);
16127 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16128 if (HOST_BITS_PER_WIDE_INT >= 64)
16131 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16132 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16135 parts[0] = immed_double_const (l[0], l[1], DImode);
16137 if (upper_mode == SImode)
16138 parts[1] = gen_int_mode (l[2], SImode);
16139 else if (HOST_BITS_PER_WIDE_INT >= 64)
16142 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16143 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16146 parts[1] = immed_double_const (l[2], l[3], DImode);
16149 gcc_unreachable ();
16156 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16157 Return false when normal moves are needed; true when all required
16158 insns have been emitted. Operands 2-4 contain the input values
16159 int the correct order; operands 5-7 contain the output values. */
16162 ix86_split_long_move (rtx operands[])
16167 int collisions = 0;
16168 enum machine_mode mode = GET_MODE (operands[0]);
16169 bool collisionparts[4];
16171 /* The DFmode expanders may ask us to move double.
16172 For 64bit target this is single move. By hiding the fact
16173 here we simplify i386.md splitters. */
16174 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16176 /* Optimize constant pool reference to immediates. This is used by
16177 fp moves, that force all constants to memory to allow combining. */
16179 if (MEM_P (operands[1])
16180 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16181 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16182 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16183 if (push_operand (operands[0], VOIDmode))
16185 operands[0] = copy_rtx (operands[0]);
16186 PUT_MODE (operands[0], Pmode);
16189 operands[0] = gen_lowpart (DImode, operands[0]);
16190 operands[1] = gen_lowpart (DImode, operands[1]);
16191 emit_move_insn (operands[0], operands[1]);
16195 /* The only non-offsettable memory we handle is push. */
16196 if (push_operand (operands[0], VOIDmode))
16199 gcc_assert (!MEM_P (operands[0])
16200 || offsettable_memref_p (operands[0]));
16202 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16203 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16205 /* When emitting push, take care for source operands on the stack. */
16206 if (push && MEM_P (operands[1])
16207 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16208 for (i = 0; i < nparts - 1; i++)
16209 part[1][i] = change_address (part[1][i],
16210 GET_MODE (part[1][i]),
16211 XEXP (part[1][i + 1], 0));
16213 /* We need to do copy in the right order in case an address register
16214 of the source overlaps the destination. */
16215 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16219 for (i = 0; i < nparts; i++)
16222 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16223 if (collisionparts[i])
16227 /* Collision in the middle part can be handled by reordering. */
16228 if (collisions == 1 && nparts == 3 && collisionparts [1])
16230 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16231 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16233 else if (collisions == 1
16235 && (collisionparts [1] || collisionparts [2]))
16237 if (collisionparts [1])
16239 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16240 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16244 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16245 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16249 /* If there are more collisions, we can't handle it by reordering.
16250 Do an lea to the last part and use only one colliding move. */
16251 else if (collisions > 1)
16257 base = part[0][nparts - 1];
16259 /* Handle the case when the last part isn't valid for lea.
16260 Happens in 64-bit mode storing the 12-byte XFmode. */
16261 if (GET_MODE (base) != Pmode)
16262 base = gen_rtx_REG (Pmode, REGNO (base));
16264 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16265 part[1][0] = replace_equiv_address (part[1][0], base);
16266 for (i = 1; i < nparts; i++)
16268 tmp = plus_constant (base, UNITS_PER_WORD * i);
16269 part[1][i] = replace_equiv_address (part[1][i], tmp);
16280 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16281 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
16282 emit_move_insn (part[0][2], part[1][2]);
16284 else if (nparts == 4)
16286 emit_move_insn (part[0][3], part[1][3]);
16287 emit_move_insn (part[0][2], part[1][2]);
16292 /* In 64bit mode we don't have 32bit push available. In case this is
16293 register, it is OK - we will just use larger counterpart. We also
16294 retype memory - these comes from attempt to avoid REX prefix on
16295 moving of second half of TFmode value. */
16296 if (GET_MODE (part[1][1]) == SImode)
16298 switch (GET_CODE (part[1][1]))
16301 part[1][1] = adjust_address (part[1][1], DImode, 0);
16305 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16309 gcc_unreachable ();
16312 if (GET_MODE (part[1][0]) == SImode)
16313 part[1][0] = part[1][1];
16316 emit_move_insn (part[0][1], part[1][1]);
16317 emit_move_insn (part[0][0], part[1][0]);
16321 /* Choose correct order to not overwrite the source before it is copied. */
16322 if ((REG_P (part[0][0])
16323 && REG_P (part[1][1])
16324 && (REGNO (part[0][0]) == REGNO (part[1][1])
16326 && REGNO (part[0][0]) == REGNO (part[1][2]))
16328 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16330 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16332 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16334 operands[2 + i] = part[0][j];
16335 operands[6 + i] = part[1][j];
16340 for (i = 0; i < nparts; i++)
16342 operands[2 + i] = part[0][i];
16343 operands[6 + i] = part[1][i];
16347 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16348 if (optimize_insn_for_size_p ())
16350 for (j = 0; j < nparts - 1; j++)
16351 if (CONST_INT_P (operands[6 + j])
16352 && operands[6 + j] != const0_rtx
16353 && REG_P (operands[2 + j]))
16354 for (i = j; i < nparts - 1; i++)
16355 if (CONST_INT_P (operands[7 + i])
16356 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16357 operands[7 + i] = operands[2 + j];
16360 for (i = 0; i < nparts; i++)
16361 emit_move_insn (operands[2 + i], operands[6 + i]);
16366 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16367 left shift by a constant, either using a single shift or
16368 a sequence of add instructions. */
16371 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16375 emit_insn ((mode == DImode
16377 : gen_adddi3) (operand, operand, operand));
16379 else if (!optimize_insn_for_size_p ()
16380 && count * ix86_cost->add <= ix86_cost->shift_const)
16383 for (i=0; i<count; i++)
16385 emit_insn ((mode == DImode
16387 : gen_adddi3) (operand, operand, operand));
16391 emit_insn ((mode == DImode
16393 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16397 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16399 rtx low[2], high[2];
16401 const int single_width = mode == DImode ? 32 : 64;
16403 if (CONST_INT_P (operands[2]))
16405 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16406 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16408 if (count >= single_width)
16410 emit_move_insn (high[0], low[1]);
16411 emit_move_insn (low[0], const0_rtx);
16413 if (count > single_width)
16414 ix86_expand_ashl_const (high[0], count - single_width, mode);
16418 if (!rtx_equal_p (operands[0], operands[1]))
16419 emit_move_insn (operands[0], operands[1]);
16420 emit_insn ((mode == DImode
16422 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16423 ix86_expand_ashl_const (low[0], count, mode);
16428 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16430 if (operands[1] == const1_rtx)
16432 /* Assuming we've chosen a QImode capable registers, then 1 << N
16433 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16434 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16436 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16438 ix86_expand_clear (low[0]);
16439 ix86_expand_clear (high[0]);
16440 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16442 d = gen_lowpart (QImode, low[0]);
16443 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16444 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16445 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16447 d = gen_lowpart (QImode, high[0]);
16448 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16449 s = gen_rtx_NE (QImode, flags, const0_rtx);
16450 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16453 /* Otherwise, we can get the same results by manually performing
16454 a bit extract operation on bit 5/6, and then performing the two
16455 shifts. The two methods of getting 0/1 into low/high are exactly
16456 the same size. Avoiding the shift in the bit extract case helps
16457 pentium4 a bit; no one else seems to care much either way. */
16462 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16463 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16465 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16466 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16468 emit_insn ((mode == DImode
16470 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16471 emit_insn ((mode == DImode
16473 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16474 emit_move_insn (low[0], high[0]);
16475 emit_insn ((mode == DImode
16477 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16480 emit_insn ((mode == DImode
16482 : gen_ashldi3) (low[0], low[0], operands[2]));
16483 emit_insn ((mode == DImode
16485 : gen_ashldi3) (high[0], high[0], operands[2]));
16489 if (operands[1] == constm1_rtx)
16491 /* For -1 << N, we can avoid the shld instruction, because we
16492 know that we're shifting 0...31/63 ones into a -1. */
16493 emit_move_insn (low[0], constm1_rtx);
16494 if (optimize_insn_for_size_p ())
16495 emit_move_insn (high[0], low[0]);
16497 emit_move_insn (high[0], constm1_rtx);
16501 if (!rtx_equal_p (operands[0], operands[1]))
16502 emit_move_insn (operands[0], operands[1]);
16504 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16505 emit_insn ((mode == DImode
16507 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16510 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16512 if (TARGET_CMOVE && scratch)
16514 ix86_expand_clear (scratch);
16515 emit_insn ((mode == DImode
16516 ? gen_x86_shift_adj_1
16517 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16521 emit_insn ((mode == DImode
16522 ? gen_x86_shift_adj_2
16523 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16527 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16529 rtx low[2], high[2];
16531 const int single_width = mode == DImode ? 32 : 64;
16533 if (CONST_INT_P (operands[2]))
16535 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16536 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16538 if (count == single_width * 2 - 1)
16540 emit_move_insn (high[0], high[1]);
16541 emit_insn ((mode == DImode
16543 : gen_ashrdi3) (high[0], high[0],
16544 GEN_INT (single_width - 1)));
16545 emit_move_insn (low[0], high[0]);
16548 else if (count >= single_width)
16550 emit_move_insn (low[0], high[1]);
16551 emit_move_insn (high[0], low[0]);
16552 emit_insn ((mode == DImode
16554 : gen_ashrdi3) (high[0], high[0],
16555 GEN_INT (single_width - 1)));
16556 if (count > single_width)
16557 emit_insn ((mode == DImode
16559 : gen_ashrdi3) (low[0], low[0],
16560 GEN_INT (count - single_width)));
16564 if (!rtx_equal_p (operands[0], operands[1]))
16565 emit_move_insn (operands[0], operands[1]);
16566 emit_insn ((mode == DImode
16568 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16569 emit_insn ((mode == DImode
16571 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16576 if (!rtx_equal_p (operands[0], operands[1]))
16577 emit_move_insn (operands[0], operands[1]);
16579 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16581 emit_insn ((mode == DImode
16583 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16584 emit_insn ((mode == DImode
16586 : gen_ashrdi3) (high[0], high[0], operands[2]));
16588 if (TARGET_CMOVE && scratch)
16590 emit_move_insn (scratch, high[0]);
16591 emit_insn ((mode == DImode
16593 : gen_ashrdi3) (scratch, scratch,
16594 GEN_INT (single_width - 1)));
16595 emit_insn ((mode == DImode
16596 ? gen_x86_shift_adj_1
16597 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16601 emit_insn ((mode == DImode
16602 ? gen_x86_shift_adj_3
16603 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16608 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16610 rtx low[2], high[2];
16612 const int single_width = mode == DImode ? 32 : 64;
16614 if (CONST_INT_P (operands[2]))
16616 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16617 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16619 if (count >= single_width)
16621 emit_move_insn (low[0], high[1]);
16622 ix86_expand_clear (high[0]);
16624 if (count > single_width)
16625 emit_insn ((mode == DImode
16627 : gen_lshrdi3) (low[0], low[0],
16628 GEN_INT (count - single_width)));
16632 if (!rtx_equal_p (operands[0], operands[1]))
16633 emit_move_insn (operands[0], operands[1]);
16634 emit_insn ((mode == DImode
16636 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16637 emit_insn ((mode == DImode
16639 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16644 if (!rtx_equal_p (operands[0], operands[1]))
16645 emit_move_insn (operands[0], operands[1]);
16647 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16649 emit_insn ((mode == DImode
16651 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16652 emit_insn ((mode == DImode
16654 : gen_lshrdi3) (high[0], high[0], operands[2]));
16656 /* Heh. By reversing the arguments, we can reuse this pattern. */
16657 if (TARGET_CMOVE && scratch)
16659 ix86_expand_clear (scratch);
16660 emit_insn ((mode == DImode
16661 ? gen_x86_shift_adj_1
16662 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16666 emit_insn ((mode == DImode
16667 ? gen_x86_shift_adj_2
16668 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16672 /* Predict just emitted jump instruction to be taken with probability PROB. */
16674 predict_jump (int prob)
16676 rtx insn = get_last_insn ();
16677 gcc_assert (JUMP_P (insn));
16679 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16684 /* Helper function for the string operations below. Dest VARIABLE whether
16685 it is aligned to VALUE bytes. If true, jump to the label. */
16687 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16689 rtx label = gen_label_rtx ();
16690 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16691 if (GET_MODE (variable) == DImode)
16692 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16694 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16695 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16698 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16700 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16704 /* Adjust COUNTER by the VALUE. */
16706 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16708 if (GET_MODE (countreg) == DImode)
16709 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16711 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16714 /* Zero extend possibly SImode EXP to Pmode register. */
16716 ix86_zero_extend_to_Pmode (rtx exp)
16719 if (GET_MODE (exp) == VOIDmode)
16720 return force_reg (Pmode, exp);
16721 if (GET_MODE (exp) == Pmode)
16722 return copy_to_mode_reg (Pmode, exp);
16723 r = gen_reg_rtx (Pmode);
16724 emit_insn (gen_zero_extendsidi2 (r, exp));
16728 /* Divide COUNTREG by SCALE. */
16730 scale_counter (rtx countreg, int scale)
16733 rtx piece_size_mask;
16737 if (CONST_INT_P (countreg))
16738 return GEN_INT (INTVAL (countreg) / scale);
16739 gcc_assert (REG_P (countreg));
16741 piece_size_mask = GEN_INT (scale - 1);
16742 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16743 GEN_INT (exact_log2 (scale)),
16744 NULL, 1, OPTAB_DIRECT);
16748 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16749 DImode for constant loop counts. */
16751 static enum machine_mode
16752 counter_mode (rtx count_exp)
16754 if (GET_MODE (count_exp) != VOIDmode)
16755 return GET_MODE (count_exp);
16756 if (GET_CODE (count_exp) != CONST_INT)
16758 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16763 /* When SRCPTR is non-NULL, output simple loop to move memory
16764 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16765 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16766 equivalent loop to set memory by VALUE (supposed to be in MODE).
16768 The size is rounded down to whole number of chunk size moved at once.
16769 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16773 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16774 rtx destptr, rtx srcptr, rtx value,
16775 rtx count, enum machine_mode mode, int unroll,
16778 rtx out_label, top_label, iter, tmp;
16779 enum machine_mode iter_mode = counter_mode (count);
16780 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16781 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16787 top_label = gen_label_rtx ();
16788 out_label = gen_label_rtx ();
16789 iter = gen_reg_rtx (iter_mode);
16791 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16792 NULL, 1, OPTAB_DIRECT);
16793 /* Those two should combine. */
16794 if (piece_size == const1_rtx)
16796 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16798 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16800 emit_move_insn (iter, const0_rtx);
16802 emit_label (top_label);
16804 tmp = convert_modes (Pmode, iter_mode, iter, true);
16805 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16806 destmem = change_address (destmem, mode, x_addr);
16810 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16811 srcmem = change_address (srcmem, mode, y_addr);
16813 /* When unrolling for chips that reorder memory reads and writes,
16814 we can save registers by using single temporary.
16815 Also using 4 temporaries is overkill in 32bit mode. */
16816 if (!TARGET_64BIT && 0)
16818 for (i = 0; i < unroll; i++)
16823 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16825 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16827 emit_move_insn (destmem, srcmem);
16833 gcc_assert (unroll <= 4);
16834 for (i = 0; i < unroll; i++)
16836 tmpreg[i] = gen_reg_rtx (mode);
16840 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16842 emit_move_insn (tmpreg[i], srcmem);
16844 for (i = 0; i < unroll; i++)
16849 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16851 emit_move_insn (destmem, tmpreg[i]);
16856 for (i = 0; i < unroll; i++)
16860 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16861 emit_move_insn (destmem, value);
16864 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16865 true, OPTAB_LIB_WIDEN);
16867 emit_move_insn (iter, tmp);
16869 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16871 if (expected_size != -1)
16873 expected_size /= GET_MODE_SIZE (mode) * unroll;
16874 if (expected_size == 0)
16876 else if (expected_size > REG_BR_PROB_BASE)
16877 predict_jump (REG_BR_PROB_BASE - 1);
16879 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16882 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16883 iter = ix86_zero_extend_to_Pmode (iter);
16884 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16885 true, OPTAB_LIB_WIDEN);
16886 if (tmp != destptr)
16887 emit_move_insn (destptr, tmp);
16890 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16891 true, OPTAB_LIB_WIDEN);
16893 emit_move_insn (srcptr, tmp);
16895 emit_label (out_label);
16898 /* Output "rep; mov" instruction.
16899 Arguments have same meaning as for previous function */
16901 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16902 rtx destptr, rtx srcptr,
16904 enum machine_mode mode)
16910 /* If the size is known, it is shorter to use rep movs. */
16911 if (mode == QImode && CONST_INT_P (count)
16912 && !(INTVAL (count) & 3))
16915 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16916 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16917 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16918 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16919 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16920 if (mode != QImode)
16922 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16923 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16924 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16925 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16926 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16927 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16931 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16932 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16934 if (CONST_INT_P (count))
16936 count = GEN_INT (INTVAL (count)
16937 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16938 destmem = shallow_copy_rtx (destmem);
16939 srcmem = shallow_copy_rtx (srcmem);
16940 set_mem_size (destmem, count);
16941 set_mem_size (srcmem, count);
16945 if (MEM_SIZE (destmem))
16946 set_mem_size (destmem, NULL_RTX);
16947 if (MEM_SIZE (srcmem))
16948 set_mem_size (srcmem, NULL_RTX);
16950 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16954 /* Output "rep; stos" instruction.
16955 Arguments have same meaning as for previous function */
16957 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16958 rtx count, enum machine_mode mode,
16964 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16965 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16966 value = force_reg (mode, gen_lowpart (mode, value));
16967 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16968 if (mode != QImode)
16970 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16971 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16972 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16975 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16976 if (orig_value == const0_rtx && CONST_INT_P (count))
16978 count = GEN_INT (INTVAL (count)
16979 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16980 destmem = shallow_copy_rtx (destmem);
16981 set_mem_size (destmem, count);
16983 else if (MEM_SIZE (destmem))
16984 set_mem_size (destmem, NULL_RTX);
16985 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16989 emit_strmov (rtx destmem, rtx srcmem,
16990 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16992 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16993 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16994 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16997 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16999 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17000 rtx destptr, rtx srcptr, rtx count, int max_size)
17003 if (CONST_INT_P (count))
17005 HOST_WIDE_INT countval = INTVAL (count);
17008 if ((countval & 0x10) && max_size > 16)
17012 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17013 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17016 gcc_unreachable ();
17019 if ((countval & 0x08) && max_size > 8)
17022 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17025 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17026 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17030 if ((countval & 0x04) && max_size > 4)
17032 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17035 if ((countval & 0x02) && max_size > 2)
17037 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17040 if ((countval & 0x01) && max_size > 1)
17042 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17049 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17050 count, 1, OPTAB_DIRECT);
17051 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17052 count, QImode, 1, 4);
17056 /* When there are stringops, we can cheaply increase dest and src pointers.
17057 Otherwise we save code size by maintaining offset (zero is readily
17058 available from preceding rep operation) and using x86 addressing modes.
17060 if (TARGET_SINGLE_STRINGOP)
17064 rtx label = ix86_expand_aligntest (count, 4, true);
17065 src = change_address (srcmem, SImode, srcptr);
17066 dest = change_address (destmem, SImode, destptr);
17067 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17068 emit_label (label);
17069 LABEL_NUSES (label) = 1;
17073 rtx label = ix86_expand_aligntest (count, 2, true);
17074 src = change_address (srcmem, HImode, srcptr);
17075 dest = change_address (destmem, HImode, destptr);
17076 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17077 emit_label (label);
17078 LABEL_NUSES (label) = 1;
17082 rtx label = ix86_expand_aligntest (count, 1, true);
17083 src = change_address (srcmem, QImode, srcptr);
17084 dest = change_address (destmem, QImode, destptr);
17085 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17086 emit_label (label);
17087 LABEL_NUSES (label) = 1;
17092 rtx offset = force_reg (Pmode, const0_rtx);
17097 rtx label = ix86_expand_aligntest (count, 4, true);
17098 src = change_address (srcmem, SImode, srcptr);
17099 dest = change_address (destmem, SImode, destptr);
17100 emit_move_insn (dest, src);
17101 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17102 true, OPTAB_LIB_WIDEN);
17104 emit_move_insn (offset, tmp);
17105 emit_label (label);
17106 LABEL_NUSES (label) = 1;
17110 rtx label = ix86_expand_aligntest (count, 2, true);
17111 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17112 src = change_address (srcmem, HImode, tmp);
17113 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17114 dest = change_address (destmem, HImode, tmp);
17115 emit_move_insn (dest, src);
17116 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17117 true, OPTAB_LIB_WIDEN);
17119 emit_move_insn (offset, tmp);
17120 emit_label (label);
17121 LABEL_NUSES (label) = 1;
17125 rtx label = ix86_expand_aligntest (count, 1, true);
17126 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17127 src = change_address (srcmem, QImode, tmp);
17128 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17129 dest = change_address (destmem, QImode, tmp);
17130 emit_move_insn (dest, src);
17131 emit_label (label);
17132 LABEL_NUSES (label) = 1;
17137 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17139 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17140 rtx count, int max_size)
17143 expand_simple_binop (counter_mode (count), AND, count,
17144 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17145 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17146 gen_lowpart (QImode, value), count, QImode,
17150 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17152 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17156 if (CONST_INT_P (count))
17158 HOST_WIDE_INT countval = INTVAL (count);
17161 if ((countval & 0x10) && max_size > 16)
17165 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17166 emit_insn (gen_strset (destptr, dest, value));
17167 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17168 emit_insn (gen_strset (destptr, dest, value));
17171 gcc_unreachable ();
17174 if ((countval & 0x08) && max_size > 8)
17178 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17179 emit_insn (gen_strset (destptr, dest, value));
17183 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17184 emit_insn (gen_strset (destptr, dest, value));
17185 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17186 emit_insn (gen_strset (destptr, dest, value));
17190 if ((countval & 0x04) && max_size > 4)
17192 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17193 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17196 if ((countval & 0x02) && max_size > 2)
17198 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17199 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17202 if ((countval & 0x01) && max_size > 1)
17204 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17205 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17212 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17217 rtx label = ix86_expand_aligntest (count, 16, true);
17220 dest = change_address (destmem, DImode, destptr);
17221 emit_insn (gen_strset (destptr, dest, value));
17222 emit_insn (gen_strset (destptr, dest, value));
17226 dest = change_address (destmem, SImode, destptr);
17227 emit_insn (gen_strset (destptr, dest, value));
17228 emit_insn (gen_strset (destptr, dest, value));
17229 emit_insn (gen_strset (destptr, dest, value));
17230 emit_insn (gen_strset (destptr, dest, value));
17232 emit_label (label);
17233 LABEL_NUSES (label) = 1;
17237 rtx label = ix86_expand_aligntest (count, 8, true);
17240 dest = change_address (destmem, DImode, destptr);
17241 emit_insn (gen_strset (destptr, dest, value));
17245 dest = change_address (destmem, SImode, destptr);
17246 emit_insn (gen_strset (destptr, dest, value));
17247 emit_insn (gen_strset (destptr, dest, value));
17249 emit_label (label);
17250 LABEL_NUSES (label) = 1;
17254 rtx label = ix86_expand_aligntest (count, 4, true);
17255 dest = change_address (destmem, SImode, destptr);
17256 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17257 emit_label (label);
17258 LABEL_NUSES (label) = 1;
17262 rtx label = ix86_expand_aligntest (count, 2, true);
17263 dest = change_address (destmem, HImode, destptr);
17264 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17265 emit_label (label);
17266 LABEL_NUSES (label) = 1;
17270 rtx label = ix86_expand_aligntest (count, 1, true);
17271 dest = change_address (destmem, QImode, destptr);
17272 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17273 emit_label (label);
17274 LABEL_NUSES (label) = 1;
17278 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17279 DESIRED_ALIGNMENT. */
17281 expand_movmem_prologue (rtx destmem, rtx srcmem,
17282 rtx destptr, rtx srcptr, rtx count,
17283 int align, int desired_alignment)
17285 if (align <= 1 && desired_alignment > 1)
17287 rtx label = ix86_expand_aligntest (destptr, 1, false);
17288 srcmem = change_address (srcmem, QImode, srcptr);
17289 destmem = change_address (destmem, QImode, destptr);
17290 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17291 ix86_adjust_counter (count, 1);
17292 emit_label (label);
17293 LABEL_NUSES (label) = 1;
17295 if (align <= 2 && desired_alignment > 2)
17297 rtx label = ix86_expand_aligntest (destptr, 2, false);
17298 srcmem = change_address (srcmem, HImode, srcptr);
17299 destmem = change_address (destmem, HImode, destptr);
17300 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17301 ix86_adjust_counter (count, 2);
17302 emit_label (label);
17303 LABEL_NUSES (label) = 1;
17305 if (align <= 4 && desired_alignment > 4)
17307 rtx label = ix86_expand_aligntest (destptr, 4, false);
17308 srcmem = change_address (srcmem, SImode, srcptr);
17309 destmem = change_address (destmem, SImode, destptr);
17310 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17311 ix86_adjust_counter (count, 4);
17312 emit_label (label);
17313 LABEL_NUSES (label) = 1;
17315 gcc_assert (desired_alignment <= 8);
17318 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17319 ALIGN_BYTES is how many bytes need to be copied. */
17321 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17322 int desired_align, int align_bytes)
17325 rtx src_size, dst_size;
17327 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17328 if (src_align_bytes >= 0)
17329 src_align_bytes = desired_align - src_align_bytes;
17330 src_size = MEM_SIZE (src);
17331 dst_size = MEM_SIZE (dst);
17332 if (align_bytes & 1)
17334 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17335 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17337 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17339 if (align_bytes & 2)
17341 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17342 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17343 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17344 set_mem_align (dst, 2 * BITS_PER_UNIT);
17345 if (src_align_bytes >= 0
17346 && (src_align_bytes & 1) == (align_bytes & 1)
17347 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17348 set_mem_align (src, 2 * BITS_PER_UNIT);
17350 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17352 if (align_bytes & 4)
17354 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17355 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17356 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17357 set_mem_align (dst, 4 * BITS_PER_UNIT);
17358 if (src_align_bytes >= 0)
17360 unsigned int src_align = 0;
17361 if ((src_align_bytes & 3) == (align_bytes & 3))
17363 else if ((src_align_bytes & 1) == (align_bytes & 1))
17365 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17366 set_mem_align (src, src_align * BITS_PER_UNIT);
17369 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17371 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17372 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17373 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17374 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17375 if (src_align_bytes >= 0)
17377 unsigned int src_align = 0;
17378 if ((src_align_bytes & 7) == (align_bytes & 7))
17380 else if ((src_align_bytes & 3) == (align_bytes & 3))
17382 else if ((src_align_bytes & 1) == (align_bytes & 1))
17384 if (src_align > (unsigned int) desired_align)
17385 src_align = desired_align;
17386 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17387 set_mem_align (src, src_align * BITS_PER_UNIT);
17390 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17392 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17397 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17398 DESIRED_ALIGNMENT. */
17400 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17401 int align, int desired_alignment)
17403 if (align <= 1 && desired_alignment > 1)
17405 rtx label = ix86_expand_aligntest (destptr, 1, false);
17406 destmem = change_address (destmem, QImode, destptr);
17407 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17408 ix86_adjust_counter (count, 1);
17409 emit_label (label);
17410 LABEL_NUSES (label) = 1;
17412 if (align <= 2 && desired_alignment > 2)
17414 rtx label = ix86_expand_aligntest (destptr, 2, false);
17415 destmem = change_address (destmem, HImode, destptr);
17416 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17417 ix86_adjust_counter (count, 2);
17418 emit_label (label);
17419 LABEL_NUSES (label) = 1;
17421 if (align <= 4 && desired_alignment > 4)
17423 rtx label = ix86_expand_aligntest (destptr, 4, false);
17424 destmem = change_address (destmem, SImode, destptr);
17425 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17426 ix86_adjust_counter (count, 4);
17427 emit_label (label);
17428 LABEL_NUSES (label) = 1;
17430 gcc_assert (desired_alignment <= 8);
17433 /* Set enough from DST to align DST known to by aligned by ALIGN to
17434 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17436 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17437 int desired_align, int align_bytes)
17440 rtx dst_size = MEM_SIZE (dst);
17441 if (align_bytes & 1)
17443 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17445 emit_insn (gen_strset (destreg, dst,
17446 gen_lowpart (QImode, value)));
17448 if (align_bytes & 2)
17450 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17451 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17452 set_mem_align (dst, 2 * BITS_PER_UNIT);
17454 emit_insn (gen_strset (destreg, dst,
17455 gen_lowpart (HImode, value)));
17457 if (align_bytes & 4)
17459 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17460 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17461 set_mem_align (dst, 4 * BITS_PER_UNIT);
17463 emit_insn (gen_strset (destreg, dst,
17464 gen_lowpart (SImode, value)));
17466 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17467 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17468 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17470 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17474 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17475 static enum stringop_alg
17476 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17477 int *dynamic_check)
17479 const struct stringop_algs * algs;
17480 bool optimize_for_speed;
17481 /* Algorithms using the rep prefix want at least edi and ecx;
17482 additionally, memset wants eax and memcpy wants esi. Don't
17483 consider such algorithms if the user has appropriated those
17484 registers for their own purposes. */
17485 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17487 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17489 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17490 || (alg != rep_prefix_1_byte \
17491 && alg != rep_prefix_4_byte \
17492 && alg != rep_prefix_8_byte))
17493 const struct processor_costs *cost;
17495 /* Even if the string operation call is cold, we still might spend a lot
17496 of time processing large blocks. */
17497 if (optimize_function_for_size_p (cfun)
17498 || (optimize_insn_for_size_p ()
17499 && expected_size != -1 && expected_size < 256))
17500 optimize_for_speed = false;
17502 optimize_for_speed = true;
17504 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17506 *dynamic_check = -1;
17508 algs = &cost->memset[TARGET_64BIT != 0];
17510 algs = &cost->memcpy[TARGET_64BIT != 0];
17511 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17512 return stringop_alg;
17513 /* rep; movq or rep; movl is the smallest variant. */
17514 else if (!optimize_for_speed)
17516 if (!count || (count & 3))
17517 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17519 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17521 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17523 else if (expected_size != -1 && expected_size < 4)
17524 return loop_1_byte;
17525 else if (expected_size != -1)
17528 enum stringop_alg alg = libcall;
17529 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17531 /* We get here if the algorithms that were not libcall-based
17532 were rep-prefix based and we are unable to use rep prefixes
17533 based on global register usage. Break out of the loop and
17534 use the heuristic below. */
17535 if (algs->size[i].max == 0)
17537 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17539 enum stringop_alg candidate = algs->size[i].alg;
17541 if (candidate != libcall && ALG_USABLE_P (candidate))
17543 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17544 last non-libcall inline algorithm. */
17545 if (TARGET_INLINE_ALL_STRINGOPS)
17547 /* When the current size is best to be copied by a libcall,
17548 but we are still forced to inline, run the heuristic below
17549 that will pick code for medium sized blocks. */
17550 if (alg != libcall)
17554 else if (ALG_USABLE_P (candidate))
17558 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17560 /* When asked to inline the call anyway, try to pick meaningful choice.
17561 We look for maximal size of block that is faster to copy by hand and
17562 take blocks of at most of that size guessing that average size will
17563 be roughly half of the block.
17565 If this turns out to be bad, we might simply specify the preferred
17566 choice in ix86_costs. */
17567 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17568 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17571 enum stringop_alg alg;
17573 bool any_alg_usable_p = true;
17575 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17577 enum stringop_alg candidate = algs->size[i].alg;
17578 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17580 if (candidate != libcall && candidate
17581 && ALG_USABLE_P (candidate))
17582 max = algs->size[i].max;
17584 /* If there aren't any usable algorithms, then recursing on
17585 smaller sizes isn't going to find anything. Just return the
17586 simple byte-at-a-time copy loop. */
17587 if (!any_alg_usable_p)
17589 /* Pick something reasonable. */
17590 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17591 *dynamic_check = 128;
17592 return loop_1_byte;
17596 alg = decide_alg (count, max / 2, memset, dynamic_check);
17597 gcc_assert (*dynamic_check == -1);
17598 gcc_assert (alg != libcall);
17599 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17600 *dynamic_check = max;
17603 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17604 #undef ALG_USABLE_P
17607 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17608 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17610 decide_alignment (int align,
17611 enum stringop_alg alg,
17614 int desired_align = 0;
17618 gcc_unreachable ();
17620 case unrolled_loop:
17621 desired_align = GET_MODE_SIZE (Pmode);
17623 case rep_prefix_8_byte:
17626 case rep_prefix_4_byte:
17627 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17628 copying whole cacheline at once. */
17629 if (TARGET_PENTIUMPRO)
17634 case rep_prefix_1_byte:
17635 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17636 copying whole cacheline at once. */
17637 if (TARGET_PENTIUMPRO)
17651 if (desired_align < align)
17652 desired_align = align;
17653 if (expected_size != -1 && expected_size < 4)
17654 desired_align = align;
17655 return desired_align;
17658 /* Return the smallest power of 2 greater than VAL. */
17660 smallest_pow2_greater_than (int val)
17668 /* Expand string move (memcpy) operation. Use i386 string operations when
17669 profitable. expand_setmem contains similar code. The code depends upon
17670 architecture, block size and alignment, but always has the same
17673 1) Prologue guard: Conditional that jumps up to epilogues for small
17674 blocks that can be handled by epilogue alone. This is faster but
17675 also needed for correctness, since prologue assume the block is larger
17676 than the desired alignment.
17678 Optional dynamic check for size and libcall for large
17679 blocks is emitted here too, with -minline-stringops-dynamically.
17681 2) Prologue: copy first few bytes in order to get destination aligned
17682 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17683 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17684 We emit either a jump tree on power of two sized blocks, or a byte loop.
17686 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17687 with specified algorithm.
17689 4) Epilogue: code copying tail of the block that is too small to be
17690 handled by main body (or up to size guarded by prologue guard). */
17693 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17694 rtx expected_align_exp, rtx expected_size_exp)
17700 rtx jump_around_label = NULL;
17701 HOST_WIDE_INT align = 1;
17702 unsigned HOST_WIDE_INT count = 0;
17703 HOST_WIDE_INT expected_size = -1;
17704 int size_needed = 0, epilogue_size_needed;
17705 int desired_align = 0, align_bytes = 0;
17706 enum stringop_alg alg;
17708 bool need_zero_guard = false;
17710 if (CONST_INT_P (align_exp))
17711 align = INTVAL (align_exp);
17712 /* i386 can do misaligned access on reasonably increased cost. */
17713 if (CONST_INT_P (expected_align_exp)
17714 && INTVAL (expected_align_exp) > align)
17715 align = INTVAL (expected_align_exp);
17716 /* ALIGN is the minimum of destination and source alignment, but we care here
17717 just about destination alignment. */
17718 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17719 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17721 if (CONST_INT_P (count_exp))
17722 count = expected_size = INTVAL (count_exp);
17723 if (CONST_INT_P (expected_size_exp) && count == 0)
17724 expected_size = INTVAL (expected_size_exp);
17726 /* Make sure we don't need to care about overflow later on. */
17727 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17730 /* Step 0: Decide on preferred algorithm, desired alignment and
17731 size of chunks to be copied by main loop. */
17733 alg = decide_alg (count, expected_size, false, &dynamic_check);
17734 desired_align = decide_alignment (align, alg, expected_size);
17736 if (!TARGET_ALIGN_STRINGOPS)
17737 align = desired_align;
17739 if (alg == libcall)
17741 gcc_assert (alg != no_stringop);
17743 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17744 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17745 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17750 gcc_unreachable ();
17752 need_zero_guard = true;
17753 size_needed = GET_MODE_SIZE (Pmode);
17755 case unrolled_loop:
17756 need_zero_guard = true;
17757 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17759 case rep_prefix_8_byte:
17762 case rep_prefix_4_byte:
17765 case rep_prefix_1_byte:
17769 need_zero_guard = true;
17774 epilogue_size_needed = size_needed;
17776 /* Step 1: Prologue guard. */
17778 /* Alignment code needs count to be in register. */
17779 if (CONST_INT_P (count_exp) && desired_align > align)
17781 if (INTVAL (count_exp) > desired_align
17782 && INTVAL (count_exp) > size_needed)
17785 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17786 if (align_bytes <= 0)
17789 align_bytes = desired_align - align_bytes;
17791 if (align_bytes == 0)
17792 count_exp = force_reg (counter_mode (count_exp), count_exp);
17794 gcc_assert (desired_align >= 1 && align >= 1);
17796 /* Ensure that alignment prologue won't copy past end of block. */
17797 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17799 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17800 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17801 Make sure it is power of 2. */
17802 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17806 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17808 /* If main algorithm works on QImode, no epilogue is needed.
17809 For small sizes just don't align anything. */
17810 if (size_needed == 1)
17811 desired_align = align;
17818 label = gen_label_rtx ();
17819 emit_cmp_and_jump_insns (count_exp,
17820 GEN_INT (epilogue_size_needed),
17821 LTU, 0, counter_mode (count_exp), 1, label);
17822 if (expected_size == -1 || expected_size < epilogue_size_needed)
17823 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17825 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17829 /* Emit code to decide on runtime whether library call or inline should be
17831 if (dynamic_check != -1)
17833 if (CONST_INT_P (count_exp))
17835 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17837 emit_block_move_via_libcall (dst, src, count_exp, false);
17838 count_exp = const0_rtx;
17844 rtx hot_label = gen_label_rtx ();
17845 jump_around_label = gen_label_rtx ();
17846 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17847 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17848 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17849 emit_block_move_via_libcall (dst, src, count_exp, false);
17850 emit_jump (jump_around_label);
17851 emit_label (hot_label);
17855 /* Step 2: Alignment prologue. */
17857 if (desired_align > align)
17859 if (align_bytes == 0)
17861 /* Except for the first move in epilogue, we no longer know
17862 constant offset in aliasing info. It don't seems to worth
17863 the pain to maintain it for the first move, so throw away
17865 src = change_address (src, BLKmode, srcreg);
17866 dst = change_address (dst, BLKmode, destreg);
17867 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17872 /* If we know how many bytes need to be stored before dst is
17873 sufficiently aligned, maintain aliasing info accurately. */
17874 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17875 desired_align, align_bytes);
17876 count_exp = plus_constant (count_exp, -align_bytes);
17877 count -= align_bytes;
17879 if (need_zero_guard
17880 && (count < (unsigned HOST_WIDE_INT) size_needed
17881 || (align_bytes == 0
17882 && count < ((unsigned HOST_WIDE_INT) size_needed
17883 + desired_align - align))))
17885 /* It is possible that we copied enough so the main loop will not
17887 gcc_assert (size_needed > 1);
17888 if (label == NULL_RTX)
17889 label = gen_label_rtx ();
17890 emit_cmp_and_jump_insns (count_exp,
17891 GEN_INT (size_needed),
17892 LTU, 0, counter_mode (count_exp), 1, label);
17893 if (expected_size == -1
17894 || expected_size < (desired_align - align) / 2 + size_needed)
17895 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17897 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17900 if (label && size_needed == 1)
17902 emit_label (label);
17903 LABEL_NUSES (label) = 1;
17905 epilogue_size_needed = 1;
17907 else if (label == NULL_RTX)
17908 epilogue_size_needed = size_needed;
17910 /* Step 3: Main loop. */
17916 gcc_unreachable ();
17918 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17919 count_exp, QImode, 1, expected_size);
17922 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17923 count_exp, Pmode, 1, expected_size);
17925 case unrolled_loop:
17926 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17927 registers for 4 temporaries anyway. */
17928 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17929 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
17932 case rep_prefix_8_byte:
17933 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17936 case rep_prefix_4_byte:
17937 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17940 case rep_prefix_1_byte:
17941 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17945 /* Adjust properly the offset of src and dest memory for aliasing. */
17946 if (CONST_INT_P (count_exp))
17948 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17949 (count / size_needed) * size_needed);
17950 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17951 (count / size_needed) * size_needed);
17955 src = change_address (src, BLKmode, srcreg);
17956 dst = change_address (dst, BLKmode, destreg);
17959 /* Step 4: Epilogue to copy the remaining bytes. */
17963 /* When the main loop is done, COUNT_EXP might hold original count,
17964 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17965 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17966 bytes. Compensate if needed. */
17968 if (size_needed < epilogue_size_needed)
17971 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17972 GEN_INT (size_needed - 1), count_exp, 1,
17974 if (tmp != count_exp)
17975 emit_move_insn (count_exp, tmp);
17977 emit_label (label);
17978 LABEL_NUSES (label) = 1;
17981 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17982 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17983 epilogue_size_needed);
17984 if (jump_around_label)
17985 emit_label (jump_around_label);
17989 /* Helper function for memcpy. For QImode value 0xXY produce
17990 0xXYXYXYXY of wide specified by MODE. This is essentially
17991 a * 0x10101010, but we can do slightly better than
17992 synth_mult by unwinding the sequence by hand on CPUs with
17995 promote_duplicated_reg (enum machine_mode mode, rtx val)
17997 enum machine_mode valmode = GET_MODE (val);
17999 int nops = mode == DImode ? 3 : 2;
18001 gcc_assert (mode == SImode || mode == DImode);
18002 if (val == const0_rtx)
18003 return copy_to_mode_reg (mode, const0_rtx);
18004 if (CONST_INT_P (val))
18006 HOST_WIDE_INT v = INTVAL (val) & 255;
18010 if (mode == DImode)
18011 v |= (v << 16) << 16;
18012 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18015 if (valmode == VOIDmode)
18017 if (valmode != QImode)
18018 val = gen_lowpart (QImode, val);
18019 if (mode == QImode)
18021 if (!TARGET_PARTIAL_REG_STALL)
18023 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18024 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18025 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18026 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18028 rtx reg = convert_modes (mode, QImode, val, true);
18029 tmp = promote_duplicated_reg (mode, const1_rtx);
18030 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18035 rtx reg = convert_modes (mode, QImode, val, true);
18037 if (!TARGET_PARTIAL_REG_STALL)
18038 if (mode == SImode)
18039 emit_insn (gen_movsi_insv_1 (reg, reg));
18041 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18044 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18045 NULL, 1, OPTAB_DIRECT);
18047 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18049 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18050 NULL, 1, OPTAB_DIRECT);
18051 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18052 if (mode == SImode)
18054 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18055 NULL, 1, OPTAB_DIRECT);
18056 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18061 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18062 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18063 alignment from ALIGN to DESIRED_ALIGN. */
18065 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18070 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18071 promoted_val = promote_duplicated_reg (DImode, val);
18072 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18073 promoted_val = promote_duplicated_reg (SImode, val);
18074 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18075 promoted_val = promote_duplicated_reg (HImode, val);
18077 promoted_val = val;
18079 return promoted_val;
18082 /* Expand string clear operation (bzero). Use i386 string operations when
18083 profitable. See expand_movmem comment for explanation of individual
18084 steps performed. */
18086 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18087 rtx expected_align_exp, rtx expected_size_exp)
18092 rtx jump_around_label = NULL;
18093 HOST_WIDE_INT align = 1;
18094 unsigned HOST_WIDE_INT count = 0;
18095 HOST_WIDE_INT expected_size = -1;
18096 int size_needed = 0, epilogue_size_needed;
18097 int desired_align = 0, align_bytes = 0;
18098 enum stringop_alg alg;
18099 rtx promoted_val = NULL;
18100 bool force_loopy_epilogue = false;
18102 bool need_zero_guard = false;
18104 if (CONST_INT_P (align_exp))
18105 align = INTVAL (align_exp);
18106 /* i386 can do misaligned access on reasonably increased cost. */
18107 if (CONST_INT_P (expected_align_exp)
18108 && INTVAL (expected_align_exp) > align)
18109 align = INTVAL (expected_align_exp);
18110 if (CONST_INT_P (count_exp))
18111 count = expected_size = INTVAL (count_exp);
18112 if (CONST_INT_P (expected_size_exp) && count == 0)
18113 expected_size = INTVAL (expected_size_exp);
18115 /* Make sure we don't need to care about overflow later on. */
18116 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18119 /* Step 0: Decide on preferred algorithm, desired alignment and
18120 size of chunks to be copied by main loop. */
18122 alg = decide_alg (count, expected_size, true, &dynamic_check);
18123 desired_align = decide_alignment (align, alg, expected_size);
18125 if (!TARGET_ALIGN_STRINGOPS)
18126 align = desired_align;
18128 if (alg == libcall)
18130 gcc_assert (alg != no_stringop);
18132 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18133 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18138 gcc_unreachable ();
18140 need_zero_guard = true;
18141 size_needed = GET_MODE_SIZE (Pmode);
18143 case unrolled_loop:
18144 need_zero_guard = true;
18145 size_needed = GET_MODE_SIZE (Pmode) * 4;
18147 case rep_prefix_8_byte:
18150 case rep_prefix_4_byte:
18153 case rep_prefix_1_byte:
18157 need_zero_guard = true;
18161 epilogue_size_needed = size_needed;
18163 /* Step 1: Prologue guard. */
18165 /* Alignment code needs count to be in register. */
18166 if (CONST_INT_P (count_exp) && desired_align > align)
18168 if (INTVAL (count_exp) > desired_align
18169 && INTVAL (count_exp) > size_needed)
18172 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18173 if (align_bytes <= 0)
18176 align_bytes = desired_align - align_bytes;
18178 if (align_bytes == 0)
18180 enum machine_mode mode = SImode;
18181 if (TARGET_64BIT && (count & ~0xffffffff))
18183 count_exp = force_reg (mode, count_exp);
18186 /* Do the cheap promotion to allow better CSE across the
18187 main loop and epilogue (ie one load of the big constant in the
18188 front of all code. */
18189 if (CONST_INT_P (val_exp))
18190 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18191 desired_align, align);
18192 /* Ensure that alignment prologue won't copy past end of block. */
18193 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18195 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18196 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18197 Make sure it is power of 2. */
18198 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18200 /* To improve performance of small blocks, we jump around the VAL
18201 promoting mode. This mean that if the promoted VAL is not constant,
18202 we might not use it in the epilogue and have to use byte
18204 if (epilogue_size_needed > 2 && !promoted_val)
18205 force_loopy_epilogue = true;
18208 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18210 /* If main algorithm works on QImode, no epilogue is needed.
18211 For small sizes just don't align anything. */
18212 if (size_needed == 1)
18213 desired_align = align;
18220 label = gen_label_rtx ();
18221 emit_cmp_and_jump_insns (count_exp,
18222 GEN_INT (epilogue_size_needed),
18223 LTU, 0, counter_mode (count_exp), 1, label);
18224 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18225 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18227 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18230 if (dynamic_check != -1)
18232 rtx hot_label = gen_label_rtx ();
18233 jump_around_label = gen_label_rtx ();
18234 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18235 LEU, 0, counter_mode (count_exp), 1, hot_label);
18236 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18237 set_storage_via_libcall (dst, count_exp, val_exp, false);
18238 emit_jump (jump_around_label);
18239 emit_label (hot_label);
18242 /* Step 2: Alignment prologue. */
18244 /* Do the expensive promotion once we branched off the small blocks. */
18246 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18247 desired_align, align);
18248 gcc_assert (desired_align >= 1 && align >= 1);
18250 if (desired_align > align)
18252 if (align_bytes == 0)
18254 /* Except for the first move in epilogue, we no longer know
18255 constant offset in aliasing info. It don't seems to worth
18256 the pain to maintain it for the first move, so throw away
18258 dst = change_address (dst, BLKmode, destreg);
18259 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18264 /* If we know how many bytes need to be stored before dst is
18265 sufficiently aligned, maintain aliasing info accurately. */
18266 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18267 desired_align, align_bytes);
18268 count_exp = plus_constant (count_exp, -align_bytes);
18269 count -= align_bytes;
18271 if (need_zero_guard
18272 && (count < (unsigned HOST_WIDE_INT) size_needed
18273 || (align_bytes == 0
18274 && count < ((unsigned HOST_WIDE_INT) size_needed
18275 + desired_align - align))))
18277 /* It is possible that we copied enough so the main loop will not
18279 gcc_assert (size_needed > 1);
18280 if (label == NULL_RTX)
18281 label = gen_label_rtx ();
18282 emit_cmp_and_jump_insns (count_exp,
18283 GEN_INT (size_needed),
18284 LTU, 0, counter_mode (count_exp), 1, label);
18285 if (expected_size == -1
18286 || expected_size < (desired_align - align) / 2 + size_needed)
18287 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18289 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18292 if (label && size_needed == 1)
18294 emit_label (label);
18295 LABEL_NUSES (label) = 1;
18297 promoted_val = val_exp;
18298 epilogue_size_needed = 1;
18300 else if (label == NULL_RTX)
18301 epilogue_size_needed = size_needed;
18303 /* Step 3: Main loop. */
18309 gcc_unreachable ();
18311 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18312 count_exp, QImode, 1, expected_size);
18315 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18316 count_exp, Pmode, 1, expected_size);
18318 case unrolled_loop:
18319 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18320 count_exp, Pmode, 4, expected_size);
18322 case rep_prefix_8_byte:
18323 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18326 case rep_prefix_4_byte:
18327 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18330 case rep_prefix_1_byte:
18331 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18335 /* Adjust properly the offset of src and dest memory for aliasing. */
18336 if (CONST_INT_P (count_exp))
18337 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18338 (count / size_needed) * size_needed);
18340 dst = change_address (dst, BLKmode, destreg);
18342 /* Step 4: Epilogue to copy the remaining bytes. */
18346 /* When the main loop is done, COUNT_EXP might hold original count,
18347 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18348 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18349 bytes. Compensate if needed. */
18351 if (size_needed < epilogue_size_needed)
18354 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18355 GEN_INT (size_needed - 1), count_exp, 1,
18357 if (tmp != count_exp)
18358 emit_move_insn (count_exp, tmp);
18360 emit_label (label);
18361 LABEL_NUSES (label) = 1;
18364 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18366 if (force_loopy_epilogue)
18367 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18368 epilogue_size_needed);
18370 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18371 epilogue_size_needed);
18373 if (jump_around_label)
18374 emit_label (jump_around_label);
18378 /* Expand the appropriate insns for doing strlen if not just doing
18381 out = result, initialized with the start address
18382 align_rtx = alignment of the address.
18383 scratch = scratch register, initialized with the startaddress when
18384 not aligned, otherwise undefined
18386 This is just the body. It needs the initializations mentioned above and
18387 some address computing at the end. These things are done in i386.md. */
18390 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18394 rtx align_2_label = NULL_RTX;
18395 rtx align_3_label = NULL_RTX;
18396 rtx align_4_label = gen_label_rtx ();
18397 rtx end_0_label = gen_label_rtx ();
18399 rtx tmpreg = gen_reg_rtx (SImode);
18400 rtx scratch = gen_reg_rtx (SImode);
18404 if (CONST_INT_P (align_rtx))
18405 align = INTVAL (align_rtx);
18407 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18409 /* Is there a known alignment and is it less than 4? */
18412 rtx scratch1 = gen_reg_rtx (Pmode);
18413 emit_move_insn (scratch1, out);
18414 /* Is there a known alignment and is it not 2? */
18417 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18418 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18420 /* Leave just the 3 lower bits. */
18421 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18422 NULL_RTX, 0, OPTAB_WIDEN);
18424 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18425 Pmode, 1, align_4_label);
18426 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18427 Pmode, 1, align_2_label);
18428 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18429 Pmode, 1, align_3_label);
18433 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18434 check if is aligned to 4 - byte. */
18436 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18437 NULL_RTX, 0, OPTAB_WIDEN);
18439 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18440 Pmode, 1, align_4_label);
18443 mem = change_address (src, QImode, out);
18445 /* Now compare the bytes. */
18447 /* Compare the first n unaligned byte on a byte per byte basis. */
18448 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18449 QImode, 1, end_0_label);
18451 /* Increment the address. */
18452 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18454 /* Not needed with an alignment of 2 */
18457 emit_label (align_2_label);
18459 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18462 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18464 emit_label (align_3_label);
18467 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18470 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18473 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18474 align this loop. It gives only huge programs, but does not help to
18476 emit_label (align_4_label);
18478 mem = change_address (src, SImode, out);
18479 emit_move_insn (scratch, mem);
18480 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18482 /* This formula yields a nonzero result iff one of the bytes is zero.
18483 This saves three branches inside loop and many cycles. */
18485 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18486 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18487 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18488 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18489 gen_int_mode (0x80808080, SImode)));
18490 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18495 rtx reg = gen_reg_rtx (SImode);
18496 rtx reg2 = gen_reg_rtx (Pmode);
18497 emit_move_insn (reg, tmpreg);
18498 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18500 /* If zero is not in the first two bytes, move two bytes forward. */
18501 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18502 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18503 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18504 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18505 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18508 /* Emit lea manually to avoid clobbering of flags. */
18509 emit_insn (gen_rtx_SET (SImode, reg2,
18510 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18512 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18513 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18514 emit_insn (gen_rtx_SET (VOIDmode, out,
18515 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18522 rtx end_2_label = gen_label_rtx ();
18523 /* Is zero in the first two bytes? */
18525 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18526 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18527 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18528 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18529 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18531 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18532 JUMP_LABEL (tmp) = end_2_label;
18534 /* Not in the first two. Move two bytes forward. */
18535 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18536 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18538 emit_label (end_2_label);
18542 /* Avoid branch in fixing the byte. */
18543 tmpreg = gen_lowpart (QImode, tmpreg);
18544 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18545 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18546 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18548 emit_label (end_0_label);
18551 /* Expand strlen. */
18554 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18556 rtx addr, scratch1, scratch2, scratch3, scratch4;
18558 /* The generic case of strlen expander is long. Avoid it's
18559 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18561 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18562 && !TARGET_INLINE_ALL_STRINGOPS
18563 && !optimize_insn_for_size_p ()
18564 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18567 addr = force_reg (Pmode, XEXP (src, 0));
18568 scratch1 = gen_reg_rtx (Pmode);
18570 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18571 && !optimize_insn_for_size_p ())
18573 /* Well it seems that some optimizer does not combine a call like
18574 foo(strlen(bar), strlen(bar));
18575 when the move and the subtraction is done here. It does calculate
18576 the length just once when these instructions are done inside of
18577 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18578 often used and I use one fewer register for the lifetime of
18579 output_strlen_unroll() this is better. */
18581 emit_move_insn (out, addr);
18583 ix86_expand_strlensi_unroll_1 (out, src, align);
18585 /* strlensi_unroll_1 returns the address of the zero at the end of
18586 the string, like memchr(), so compute the length by subtracting
18587 the start address. */
18588 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18594 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18595 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18598 scratch2 = gen_reg_rtx (Pmode);
18599 scratch3 = gen_reg_rtx (Pmode);
18600 scratch4 = force_reg (Pmode, constm1_rtx);
18602 emit_move_insn (scratch3, addr);
18603 eoschar = force_reg (QImode, eoschar);
18605 src = replace_equiv_address_nv (src, scratch3);
18607 /* If .md starts supporting :P, this can be done in .md. */
18608 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18609 scratch4), UNSPEC_SCAS);
18610 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18611 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18612 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18617 /* For given symbol (function) construct code to compute address of it's PLT
18618 entry in large x86-64 PIC model. */
18620 construct_plt_address (rtx symbol)
18622 rtx tmp = gen_reg_rtx (Pmode);
18623 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18625 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18626 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18628 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18629 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18634 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18636 rtx pop, int sibcall)
18638 rtx use = NULL, call;
18640 if (pop == const0_rtx)
18642 gcc_assert (!TARGET_64BIT || !pop);
18644 if (TARGET_MACHO && !TARGET_64BIT)
18647 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18648 fnaddr = machopic_indirect_call_target (fnaddr);
18653 /* Static functions and indirect calls don't need the pic register. */
18654 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18655 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18656 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18657 use_reg (&use, pic_offset_table_rtx);
18660 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18662 rtx al = gen_rtx_REG (QImode, AX_REG);
18663 emit_move_insn (al, callarg2);
18664 use_reg (&use, al);
18667 if (ix86_cmodel == CM_LARGE_PIC
18668 && GET_CODE (fnaddr) == MEM
18669 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18670 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18671 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18672 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
18674 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18675 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18677 if (sibcall && TARGET_64BIT
18678 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
18681 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18682 fnaddr = gen_rtx_REG (Pmode, R11_REG);
18683 emit_move_insn (fnaddr, addr);
18684 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18687 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18689 call = gen_rtx_SET (VOIDmode, retval, call);
18692 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18693 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18694 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18697 && ix86_cfun_abi () == MS_ABI
18698 && (!callarg2 || INTVAL (callarg2) != -2))
18700 /* We need to represent that SI and DI registers are clobbered
18702 static int clobbered_registers[] = {
18703 XMM6_REG, XMM7_REG, XMM8_REG,
18704 XMM9_REG, XMM10_REG, XMM11_REG,
18705 XMM12_REG, XMM13_REG, XMM14_REG,
18706 XMM15_REG, SI_REG, DI_REG
18709 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18710 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18711 UNSPEC_MS_TO_SYSV_CALL);
18715 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18716 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18719 (SSE_REGNO_P (clobbered_registers[i])
18721 clobbered_registers[i]));
18723 call = gen_rtx_PARALLEL (VOIDmode,
18724 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18728 call = emit_call_insn (call);
18730 CALL_INSN_FUNCTION_USAGE (call) = use;
18734 /* Clear stack slot assignments remembered from previous functions.
18735 This is called from INIT_EXPANDERS once before RTL is emitted for each
18738 static struct machine_function *
18739 ix86_init_machine_status (void)
18741 struct machine_function *f;
18743 f = GGC_CNEW (struct machine_function);
18744 f->use_fast_prologue_epilogue_nregs = -1;
18745 f->tls_descriptor_call_expanded_p = 0;
18746 f->call_abi = ix86_abi;
18751 /* Return a MEM corresponding to a stack slot with mode MODE.
18752 Allocate a new slot if necessary.
18754 The RTL for a function can have several slots available: N is
18755 which slot to use. */
18758 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18760 struct stack_local_entry *s;
18762 gcc_assert (n < MAX_386_STACK_LOCALS);
18764 /* Virtual slot is valid only before vregs are instantiated. */
18765 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18767 for (s = ix86_stack_locals; s; s = s->next)
18768 if (s->mode == mode && s->n == n)
18769 return copy_rtx (s->rtl);
18771 s = (struct stack_local_entry *)
18772 ggc_alloc (sizeof (struct stack_local_entry));
18775 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18777 s->next = ix86_stack_locals;
18778 ix86_stack_locals = s;
18782 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18784 static GTY(()) rtx ix86_tls_symbol;
18786 ix86_tls_get_addr (void)
18789 if (!ix86_tls_symbol)
18791 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18792 (TARGET_ANY_GNU_TLS
18794 ? "___tls_get_addr"
18795 : "__tls_get_addr");
18798 return ix86_tls_symbol;
18801 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18803 static GTY(()) rtx ix86_tls_module_base_symbol;
18805 ix86_tls_module_base (void)
18808 if (!ix86_tls_module_base_symbol)
18810 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18811 "_TLS_MODULE_BASE_");
18812 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18813 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18816 return ix86_tls_module_base_symbol;
18819 /* Calculate the length of the memory address in the instruction
18820 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18823 memory_address_length (rtx addr)
18825 struct ix86_address parts;
18826 rtx base, index, disp;
18830 if (GET_CODE (addr) == PRE_DEC
18831 || GET_CODE (addr) == POST_INC
18832 || GET_CODE (addr) == PRE_MODIFY
18833 || GET_CODE (addr) == POST_MODIFY)
18836 ok = ix86_decompose_address (addr, &parts);
18839 if (parts.base && GET_CODE (parts.base) == SUBREG)
18840 parts.base = SUBREG_REG (parts.base);
18841 if (parts.index && GET_CODE (parts.index) == SUBREG)
18842 parts.index = SUBREG_REG (parts.index);
18845 index = parts.index;
18850 - esp as the base always wants an index,
18851 - ebp as the base always wants a displacement. */
18853 /* Register Indirect. */
18854 if (base && !index && !disp)
18856 /* esp (for its index) and ebp (for its displacement) need
18857 the two-byte modrm form. */
18858 if (addr == stack_pointer_rtx
18859 || addr == arg_pointer_rtx
18860 || addr == frame_pointer_rtx
18861 || addr == hard_frame_pointer_rtx)
18865 /* Direct Addressing. */
18866 else if (disp && !base && !index)
18871 /* Find the length of the displacement constant. */
18874 if (base && satisfies_constraint_K (disp))
18879 /* ebp always wants a displacement. */
18880 else if (base == hard_frame_pointer_rtx)
18883 /* An index requires the two-byte modrm form.... */
18885 /* ...like esp, which always wants an index. */
18886 || base == stack_pointer_rtx
18887 || base == arg_pointer_rtx
18888 || base == frame_pointer_rtx)
18895 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18896 is set, expect that insn have 8bit immediate alternative. */
18898 ix86_attr_length_immediate_default (rtx insn, int shortform)
18902 extract_insn_cached (insn);
18903 for (i = recog_data.n_operands - 1; i >= 0; --i)
18904 if (CONSTANT_P (recog_data.operand[i]))
18907 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
18911 switch (get_attr_mode (insn))
18922 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18927 fatal_insn ("unknown insn mode", insn);
18933 /* Compute default value for "length_address" attribute. */
18935 ix86_attr_length_address_default (rtx insn)
18939 if (get_attr_type (insn) == TYPE_LEA)
18941 rtx set = PATTERN (insn);
18943 if (GET_CODE (set) == PARALLEL)
18944 set = XVECEXP (set, 0, 0);
18946 gcc_assert (GET_CODE (set) == SET);
18948 return memory_address_length (SET_SRC (set));
18951 extract_insn_cached (insn);
18952 for (i = recog_data.n_operands - 1; i >= 0; --i)
18953 if (MEM_P (recog_data.operand[i]))
18955 return memory_address_length (XEXP (recog_data.operand[i], 0));
18961 /* Compute default value for "length_vex" attribute. It includes
18962 2 or 3 byte VEX prefix and 1 opcode byte. */
18965 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
18970 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18971 byte VEX prefix. */
18972 if (!has_0f_opcode || has_vex_w)
18975 /* We can always use 2 byte VEX prefix in 32bit. */
18979 extract_insn_cached (insn);
18981 for (i = recog_data.n_operands - 1; i >= 0; --i)
18982 if (REG_P (recog_data.operand[i]))
18984 /* REX.W bit uses 3 byte VEX prefix. */
18985 if (GET_MODE (recog_data.operand[i]) == DImode)
18990 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18991 if (MEM_P (recog_data.operand[i])
18992 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
18999 /* Return the maximum number of instructions a cpu can issue. */
19002 ix86_issue_rate (void)
19006 case PROCESSOR_PENTIUM:
19010 case PROCESSOR_PENTIUMPRO:
19011 case PROCESSOR_PENTIUM4:
19012 case PROCESSOR_ATHLON:
19014 case PROCESSOR_AMDFAM10:
19015 case PROCESSOR_NOCONA:
19016 case PROCESSOR_GENERIC32:
19017 case PROCESSOR_GENERIC64:
19020 case PROCESSOR_CORE2:
19028 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19029 by DEP_INSN and nothing set by DEP_INSN. */
19032 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19036 /* Simplify the test for uninteresting insns. */
19037 if (insn_type != TYPE_SETCC
19038 && insn_type != TYPE_ICMOV
19039 && insn_type != TYPE_FCMOV
19040 && insn_type != TYPE_IBR)
19043 if ((set = single_set (dep_insn)) != 0)
19045 set = SET_DEST (set);
19048 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19049 && XVECLEN (PATTERN (dep_insn), 0) == 2
19050 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19051 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19053 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19054 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19059 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19062 /* This test is true if the dependent insn reads the flags but
19063 not any other potentially set register. */
19064 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19067 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19073 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19074 address with operands set by DEP_INSN. */
19077 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19081 if (insn_type == TYPE_LEA
19084 addr = PATTERN (insn);
19086 if (GET_CODE (addr) == PARALLEL)
19087 addr = XVECEXP (addr, 0, 0);
19089 gcc_assert (GET_CODE (addr) == SET);
19091 addr = SET_SRC (addr);
19096 extract_insn_cached (insn);
19097 for (i = recog_data.n_operands - 1; i >= 0; --i)
19098 if (MEM_P (recog_data.operand[i]))
19100 addr = XEXP (recog_data.operand[i], 0);
19107 return modified_in_p (addr, dep_insn);
19111 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19113 enum attr_type insn_type, dep_insn_type;
19114 enum attr_memory memory;
19116 int dep_insn_code_number;
19118 /* Anti and output dependencies have zero cost on all CPUs. */
19119 if (REG_NOTE_KIND (link) != 0)
19122 dep_insn_code_number = recog_memoized (dep_insn);
19124 /* If we can't recognize the insns, we can't really do anything. */
19125 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19128 insn_type = get_attr_type (insn);
19129 dep_insn_type = get_attr_type (dep_insn);
19133 case PROCESSOR_PENTIUM:
19134 /* Address Generation Interlock adds a cycle of latency. */
19135 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19138 /* ??? Compares pair with jump/setcc. */
19139 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19142 /* Floating point stores require value to be ready one cycle earlier. */
19143 if (insn_type == TYPE_FMOV
19144 && get_attr_memory (insn) == MEMORY_STORE
19145 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19149 case PROCESSOR_PENTIUMPRO:
19150 memory = get_attr_memory (insn);
19152 /* INT->FP conversion is expensive. */
19153 if (get_attr_fp_int_src (dep_insn))
19156 /* There is one cycle extra latency between an FP op and a store. */
19157 if (insn_type == TYPE_FMOV
19158 && (set = single_set (dep_insn)) != NULL_RTX
19159 && (set2 = single_set (insn)) != NULL_RTX
19160 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19161 && MEM_P (SET_DEST (set2)))
19164 /* Show ability of reorder buffer to hide latency of load by executing
19165 in parallel with previous instruction in case
19166 previous instruction is not needed to compute the address. */
19167 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19168 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19170 /* Claim moves to take one cycle, as core can issue one load
19171 at time and the next load can start cycle later. */
19172 if (dep_insn_type == TYPE_IMOV
19173 || dep_insn_type == TYPE_FMOV)
19181 memory = get_attr_memory (insn);
19183 /* The esp dependency is resolved before the instruction is really
19185 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19186 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19189 /* INT->FP conversion is expensive. */
19190 if (get_attr_fp_int_src (dep_insn))
19193 /* Show ability of reorder buffer to hide latency of load by executing
19194 in parallel with previous instruction in case
19195 previous instruction is not needed to compute the address. */
19196 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19197 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19199 /* Claim moves to take one cycle, as core can issue one load
19200 at time and the next load can start cycle later. */
19201 if (dep_insn_type == TYPE_IMOV
19202 || dep_insn_type == TYPE_FMOV)
19211 case PROCESSOR_ATHLON:
19213 case PROCESSOR_AMDFAM10:
19214 case PROCESSOR_GENERIC32:
19215 case PROCESSOR_GENERIC64:
19216 memory = get_attr_memory (insn);
19218 /* Show ability of reorder buffer to hide latency of load by executing
19219 in parallel with previous instruction in case
19220 previous instruction is not needed to compute the address. */
19221 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19222 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19224 enum attr_unit unit = get_attr_unit (insn);
19227 /* Because of the difference between the length of integer and
19228 floating unit pipeline preparation stages, the memory operands
19229 for floating point are cheaper.
19231 ??? For Athlon it the difference is most probably 2. */
19232 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19235 loadcost = TARGET_ATHLON ? 2 : 0;
19237 if (cost >= loadcost)
19250 /* How many alternative schedules to try. This should be as wide as the
19251 scheduling freedom in the DFA, but no wider. Making this value too
19252 large results extra work for the scheduler. */
19255 ia32_multipass_dfa_lookahead (void)
19259 case PROCESSOR_PENTIUM:
19262 case PROCESSOR_PENTIUMPRO:
19272 /* Compute the alignment given to a constant that is being placed in memory.
19273 EXP is the constant and ALIGN is the alignment that the object would
19275 The value of this function is used instead of that alignment to align
19279 ix86_constant_alignment (tree exp, int align)
19281 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19282 || TREE_CODE (exp) == INTEGER_CST)
19284 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19286 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19289 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19290 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19291 return BITS_PER_WORD;
19296 /* Compute the alignment for a static variable.
19297 TYPE is the data type, and ALIGN is the alignment that
19298 the object would ordinarily have. The value of this function is used
19299 instead of that alignment to align the object. */
19302 ix86_data_alignment (tree type, int align)
19304 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19306 if (AGGREGATE_TYPE_P (type)
19307 && TYPE_SIZE (type)
19308 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19309 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19310 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19311 && align < max_align)
19314 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19315 to 16byte boundary. */
19318 if (AGGREGATE_TYPE_P (type)
19319 && TYPE_SIZE (type)
19320 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19321 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19322 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19326 if (TREE_CODE (type) == ARRAY_TYPE)
19328 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19330 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19333 else if (TREE_CODE (type) == COMPLEX_TYPE)
19336 if (TYPE_MODE (type) == DCmode && align < 64)
19338 if ((TYPE_MODE (type) == XCmode
19339 || TYPE_MODE (type) == TCmode) && align < 128)
19342 else if ((TREE_CODE (type) == RECORD_TYPE
19343 || TREE_CODE (type) == UNION_TYPE
19344 || TREE_CODE (type) == QUAL_UNION_TYPE)
19345 && TYPE_FIELDS (type))
19347 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19349 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19352 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19353 || TREE_CODE (type) == INTEGER_TYPE)
19355 if (TYPE_MODE (type) == DFmode && align < 64)
19357 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19364 /* Compute the alignment for a local variable or a stack slot. EXP is
19365 the data type or decl itself, MODE is the widest mode available and
19366 ALIGN is the alignment that the object would ordinarily have. The
19367 value of this macro is used instead of that alignment to align the
19371 ix86_local_alignment (tree exp, enum machine_mode mode,
19372 unsigned int align)
19376 if (exp && DECL_P (exp))
19378 type = TREE_TYPE (exp);
19387 /* Don't do dynamic stack realignment for long long objects with
19388 -mpreferred-stack-boundary=2. */
19391 && ix86_preferred_stack_boundary < 64
19392 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19393 && (!type || !TYPE_USER_ALIGN (type))
19394 && (!decl || !DECL_USER_ALIGN (decl)))
19397 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19398 register in MODE. We will return the largest alignment of XF
19402 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19403 align = GET_MODE_ALIGNMENT (DFmode);
19407 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19408 to 16byte boundary. */
19411 if (AGGREGATE_TYPE_P (type)
19412 && TYPE_SIZE (type)
19413 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19414 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19415 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19418 if (TREE_CODE (type) == ARRAY_TYPE)
19420 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19422 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19425 else if (TREE_CODE (type) == COMPLEX_TYPE)
19427 if (TYPE_MODE (type) == DCmode && align < 64)
19429 if ((TYPE_MODE (type) == XCmode
19430 || TYPE_MODE (type) == TCmode) && align < 128)
19433 else if ((TREE_CODE (type) == RECORD_TYPE
19434 || TREE_CODE (type) == UNION_TYPE
19435 || TREE_CODE (type) == QUAL_UNION_TYPE)
19436 && TYPE_FIELDS (type))
19438 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19440 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19443 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19444 || TREE_CODE (type) == INTEGER_TYPE)
19447 if (TYPE_MODE (type) == DFmode && align < 64)
19449 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19455 /* Emit RTL insns to initialize the variable parts of a trampoline.
19456 FNADDR is an RTX for the address of the function's pure code.
19457 CXT is an RTX for the static chain value for the function. */
19459 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19463 /* Compute offset from the end of the jmp to the target function. */
19464 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19465 plus_constant (tramp, 10),
19466 NULL_RTX, 1, OPTAB_DIRECT);
19467 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19468 gen_int_mode (0xb9, QImode));
19469 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19470 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19471 gen_int_mode (0xe9, QImode));
19472 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19477 /* Try to load address using shorter movl instead of movabs.
19478 We may want to support movq for kernel mode, but kernel does not use
19479 trampolines at the moment. */
19480 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19482 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19483 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19484 gen_int_mode (0xbb41, HImode));
19485 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19486 gen_lowpart (SImode, fnaddr));
19491 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19492 gen_int_mode (0xbb49, HImode));
19493 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19497 /* Load static chain using movabs to r10. */
19498 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19499 gen_int_mode (0xba49, HImode));
19500 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19503 /* Jump to the r11 */
19504 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19505 gen_int_mode (0xff49, HImode));
19506 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19507 gen_int_mode (0xe3, QImode));
19509 gcc_assert (offset <= TRAMPOLINE_SIZE);
19512 #ifdef ENABLE_EXECUTE_STACK
19513 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19514 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19518 /* Codes for all the SSE/MMX builtins. */
19521 IX86_BUILTIN_ADDPS,
19522 IX86_BUILTIN_ADDSS,
19523 IX86_BUILTIN_DIVPS,
19524 IX86_BUILTIN_DIVSS,
19525 IX86_BUILTIN_MULPS,
19526 IX86_BUILTIN_MULSS,
19527 IX86_BUILTIN_SUBPS,
19528 IX86_BUILTIN_SUBSS,
19530 IX86_BUILTIN_CMPEQPS,
19531 IX86_BUILTIN_CMPLTPS,
19532 IX86_BUILTIN_CMPLEPS,
19533 IX86_BUILTIN_CMPGTPS,
19534 IX86_BUILTIN_CMPGEPS,
19535 IX86_BUILTIN_CMPNEQPS,
19536 IX86_BUILTIN_CMPNLTPS,
19537 IX86_BUILTIN_CMPNLEPS,
19538 IX86_BUILTIN_CMPNGTPS,
19539 IX86_BUILTIN_CMPNGEPS,
19540 IX86_BUILTIN_CMPORDPS,
19541 IX86_BUILTIN_CMPUNORDPS,
19542 IX86_BUILTIN_CMPEQSS,
19543 IX86_BUILTIN_CMPLTSS,
19544 IX86_BUILTIN_CMPLESS,
19545 IX86_BUILTIN_CMPNEQSS,
19546 IX86_BUILTIN_CMPNLTSS,
19547 IX86_BUILTIN_CMPNLESS,
19548 IX86_BUILTIN_CMPNGTSS,
19549 IX86_BUILTIN_CMPNGESS,
19550 IX86_BUILTIN_CMPORDSS,
19551 IX86_BUILTIN_CMPUNORDSS,
19553 IX86_BUILTIN_COMIEQSS,
19554 IX86_BUILTIN_COMILTSS,
19555 IX86_BUILTIN_COMILESS,
19556 IX86_BUILTIN_COMIGTSS,
19557 IX86_BUILTIN_COMIGESS,
19558 IX86_BUILTIN_COMINEQSS,
19559 IX86_BUILTIN_UCOMIEQSS,
19560 IX86_BUILTIN_UCOMILTSS,
19561 IX86_BUILTIN_UCOMILESS,
19562 IX86_BUILTIN_UCOMIGTSS,
19563 IX86_BUILTIN_UCOMIGESS,
19564 IX86_BUILTIN_UCOMINEQSS,
19566 IX86_BUILTIN_CVTPI2PS,
19567 IX86_BUILTIN_CVTPS2PI,
19568 IX86_BUILTIN_CVTSI2SS,
19569 IX86_BUILTIN_CVTSI642SS,
19570 IX86_BUILTIN_CVTSS2SI,
19571 IX86_BUILTIN_CVTSS2SI64,
19572 IX86_BUILTIN_CVTTPS2PI,
19573 IX86_BUILTIN_CVTTSS2SI,
19574 IX86_BUILTIN_CVTTSS2SI64,
19576 IX86_BUILTIN_MAXPS,
19577 IX86_BUILTIN_MAXSS,
19578 IX86_BUILTIN_MINPS,
19579 IX86_BUILTIN_MINSS,
19581 IX86_BUILTIN_LOADUPS,
19582 IX86_BUILTIN_STOREUPS,
19583 IX86_BUILTIN_MOVSS,
19585 IX86_BUILTIN_MOVHLPS,
19586 IX86_BUILTIN_MOVLHPS,
19587 IX86_BUILTIN_LOADHPS,
19588 IX86_BUILTIN_LOADLPS,
19589 IX86_BUILTIN_STOREHPS,
19590 IX86_BUILTIN_STORELPS,
19592 IX86_BUILTIN_MASKMOVQ,
19593 IX86_BUILTIN_MOVMSKPS,
19594 IX86_BUILTIN_PMOVMSKB,
19596 IX86_BUILTIN_MOVNTPS,
19597 IX86_BUILTIN_MOVNTQ,
19599 IX86_BUILTIN_LOADDQU,
19600 IX86_BUILTIN_STOREDQU,
19602 IX86_BUILTIN_PACKSSWB,
19603 IX86_BUILTIN_PACKSSDW,
19604 IX86_BUILTIN_PACKUSWB,
19606 IX86_BUILTIN_PADDB,
19607 IX86_BUILTIN_PADDW,
19608 IX86_BUILTIN_PADDD,
19609 IX86_BUILTIN_PADDQ,
19610 IX86_BUILTIN_PADDSB,
19611 IX86_BUILTIN_PADDSW,
19612 IX86_BUILTIN_PADDUSB,
19613 IX86_BUILTIN_PADDUSW,
19614 IX86_BUILTIN_PSUBB,
19615 IX86_BUILTIN_PSUBW,
19616 IX86_BUILTIN_PSUBD,
19617 IX86_BUILTIN_PSUBQ,
19618 IX86_BUILTIN_PSUBSB,
19619 IX86_BUILTIN_PSUBSW,
19620 IX86_BUILTIN_PSUBUSB,
19621 IX86_BUILTIN_PSUBUSW,
19624 IX86_BUILTIN_PANDN,
19628 IX86_BUILTIN_PAVGB,
19629 IX86_BUILTIN_PAVGW,
19631 IX86_BUILTIN_PCMPEQB,
19632 IX86_BUILTIN_PCMPEQW,
19633 IX86_BUILTIN_PCMPEQD,
19634 IX86_BUILTIN_PCMPGTB,
19635 IX86_BUILTIN_PCMPGTW,
19636 IX86_BUILTIN_PCMPGTD,
19638 IX86_BUILTIN_PMADDWD,
19640 IX86_BUILTIN_PMAXSW,
19641 IX86_BUILTIN_PMAXUB,
19642 IX86_BUILTIN_PMINSW,
19643 IX86_BUILTIN_PMINUB,
19645 IX86_BUILTIN_PMULHUW,
19646 IX86_BUILTIN_PMULHW,
19647 IX86_BUILTIN_PMULLW,
19649 IX86_BUILTIN_PSADBW,
19650 IX86_BUILTIN_PSHUFW,
19652 IX86_BUILTIN_PSLLW,
19653 IX86_BUILTIN_PSLLD,
19654 IX86_BUILTIN_PSLLQ,
19655 IX86_BUILTIN_PSRAW,
19656 IX86_BUILTIN_PSRAD,
19657 IX86_BUILTIN_PSRLW,
19658 IX86_BUILTIN_PSRLD,
19659 IX86_BUILTIN_PSRLQ,
19660 IX86_BUILTIN_PSLLWI,
19661 IX86_BUILTIN_PSLLDI,
19662 IX86_BUILTIN_PSLLQI,
19663 IX86_BUILTIN_PSRAWI,
19664 IX86_BUILTIN_PSRADI,
19665 IX86_BUILTIN_PSRLWI,
19666 IX86_BUILTIN_PSRLDI,
19667 IX86_BUILTIN_PSRLQI,
19669 IX86_BUILTIN_PUNPCKHBW,
19670 IX86_BUILTIN_PUNPCKHWD,
19671 IX86_BUILTIN_PUNPCKHDQ,
19672 IX86_BUILTIN_PUNPCKLBW,
19673 IX86_BUILTIN_PUNPCKLWD,
19674 IX86_BUILTIN_PUNPCKLDQ,
19676 IX86_BUILTIN_SHUFPS,
19678 IX86_BUILTIN_RCPPS,
19679 IX86_BUILTIN_RCPSS,
19680 IX86_BUILTIN_RSQRTPS,
19681 IX86_BUILTIN_RSQRTPS_NR,
19682 IX86_BUILTIN_RSQRTSS,
19683 IX86_BUILTIN_RSQRTF,
19684 IX86_BUILTIN_SQRTPS,
19685 IX86_BUILTIN_SQRTPS_NR,
19686 IX86_BUILTIN_SQRTSS,
19688 IX86_BUILTIN_UNPCKHPS,
19689 IX86_BUILTIN_UNPCKLPS,
19691 IX86_BUILTIN_ANDPS,
19692 IX86_BUILTIN_ANDNPS,
19694 IX86_BUILTIN_XORPS,
19697 IX86_BUILTIN_LDMXCSR,
19698 IX86_BUILTIN_STMXCSR,
19699 IX86_BUILTIN_SFENCE,
19701 /* 3DNow! Original */
19702 IX86_BUILTIN_FEMMS,
19703 IX86_BUILTIN_PAVGUSB,
19704 IX86_BUILTIN_PF2ID,
19705 IX86_BUILTIN_PFACC,
19706 IX86_BUILTIN_PFADD,
19707 IX86_BUILTIN_PFCMPEQ,
19708 IX86_BUILTIN_PFCMPGE,
19709 IX86_BUILTIN_PFCMPGT,
19710 IX86_BUILTIN_PFMAX,
19711 IX86_BUILTIN_PFMIN,
19712 IX86_BUILTIN_PFMUL,
19713 IX86_BUILTIN_PFRCP,
19714 IX86_BUILTIN_PFRCPIT1,
19715 IX86_BUILTIN_PFRCPIT2,
19716 IX86_BUILTIN_PFRSQIT1,
19717 IX86_BUILTIN_PFRSQRT,
19718 IX86_BUILTIN_PFSUB,
19719 IX86_BUILTIN_PFSUBR,
19720 IX86_BUILTIN_PI2FD,
19721 IX86_BUILTIN_PMULHRW,
19723 /* 3DNow! Athlon Extensions */
19724 IX86_BUILTIN_PF2IW,
19725 IX86_BUILTIN_PFNACC,
19726 IX86_BUILTIN_PFPNACC,
19727 IX86_BUILTIN_PI2FW,
19728 IX86_BUILTIN_PSWAPDSI,
19729 IX86_BUILTIN_PSWAPDSF,
19732 IX86_BUILTIN_ADDPD,
19733 IX86_BUILTIN_ADDSD,
19734 IX86_BUILTIN_DIVPD,
19735 IX86_BUILTIN_DIVSD,
19736 IX86_BUILTIN_MULPD,
19737 IX86_BUILTIN_MULSD,
19738 IX86_BUILTIN_SUBPD,
19739 IX86_BUILTIN_SUBSD,
19741 IX86_BUILTIN_CMPEQPD,
19742 IX86_BUILTIN_CMPLTPD,
19743 IX86_BUILTIN_CMPLEPD,
19744 IX86_BUILTIN_CMPGTPD,
19745 IX86_BUILTIN_CMPGEPD,
19746 IX86_BUILTIN_CMPNEQPD,
19747 IX86_BUILTIN_CMPNLTPD,
19748 IX86_BUILTIN_CMPNLEPD,
19749 IX86_BUILTIN_CMPNGTPD,
19750 IX86_BUILTIN_CMPNGEPD,
19751 IX86_BUILTIN_CMPORDPD,
19752 IX86_BUILTIN_CMPUNORDPD,
19753 IX86_BUILTIN_CMPEQSD,
19754 IX86_BUILTIN_CMPLTSD,
19755 IX86_BUILTIN_CMPLESD,
19756 IX86_BUILTIN_CMPNEQSD,
19757 IX86_BUILTIN_CMPNLTSD,
19758 IX86_BUILTIN_CMPNLESD,
19759 IX86_BUILTIN_CMPORDSD,
19760 IX86_BUILTIN_CMPUNORDSD,
19762 IX86_BUILTIN_COMIEQSD,
19763 IX86_BUILTIN_COMILTSD,
19764 IX86_BUILTIN_COMILESD,
19765 IX86_BUILTIN_COMIGTSD,
19766 IX86_BUILTIN_COMIGESD,
19767 IX86_BUILTIN_COMINEQSD,
19768 IX86_BUILTIN_UCOMIEQSD,
19769 IX86_BUILTIN_UCOMILTSD,
19770 IX86_BUILTIN_UCOMILESD,
19771 IX86_BUILTIN_UCOMIGTSD,
19772 IX86_BUILTIN_UCOMIGESD,
19773 IX86_BUILTIN_UCOMINEQSD,
19775 IX86_BUILTIN_MAXPD,
19776 IX86_BUILTIN_MAXSD,
19777 IX86_BUILTIN_MINPD,
19778 IX86_BUILTIN_MINSD,
19780 IX86_BUILTIN_ANDPD,
19781 IX86_BUILTIN_ANDNPD,
19783 IX86_BUILTIN_XORPD,
19785 IX86_BUILTIN_SQRTPD,
19786 IX86_BUILTIN_SQRTSD,
19788 IX86_BUILTIN_UNPCKHPD,
19789 IX86_BUILTIN_UNPCKLPD,
19791 IX86_BUILTIN_SHUFPD,
19793 IX86_BUILTIN_LOADUPD,
19794 IX86_BUILTIN_STOREUPD,
19795 IX86_BUILTIN_MOVSD,
19797 IX86_BUILTIN_LOADHPD,
19798 IX86_BUILTIN_LOADLPD,
19800 IX86_BUILTIN_CVTDQ2PD,
19801 IX86_BUILTIN_CVTDQ2PS,
19803 IX86_BUILTIN_CVTPD2DQ,
19804 IX86_BUILTIN_CVTPD2PI,
19805 IX86_BUILTIN_CVTPD2PS,
19806 IX86_BUILTIN_CVTTPD2DQ,
19807 IX86_BUILTIN_CVTTPD2PI,
19809 IX86_BUILTIN_CVTPI2PD,
19810 IX86_BUILTIN_CVTSI2SD,
19811 IX86_BUILTIN_CVTSI642SD,
19813 IX86_BUILTIN_CVTSD2SI,
19814 IX86_BUILTIN_CVTSD2SI64,
19815 IX86_BUILTIN_CVTSD2SS,
19816 IX86_BUILTIN_CVTSS2SD,
19817 IX86_BUILTIN_CVTTSD2SI,
19818 IX86_BUILTIN_CVTTSD2SI64,
19820 IX86_BUILTIN_CVTPS2DQ,
19821 IX86_BUILTIN_CVTPS2PD,
19822 IX86_BUILTIN_CVTTPS2DQ,
19824 IX86_BUILTIN_MOVNTI,
19825 IX86_BUILTIN_MOVNTPD,
19826 IX86_BUILTIN_MOVNTDQ,
19828 IX86_BUILTIN_MOVQ128,
19831 IX86_BUILTIN_MASKMOVDQU,
19832 IX86_BUILTIN_MOVMSKPD,
19833 IX86_BUILTIN_PMOVMSKB128,
19835 IX86_BUILTIN_PACKSSWB128,
19836 IX86_BUILTIN_PACKSSDW128,
19837 IX86_BUILTIN_PACKUSWB128,
19839 IX86_BUILTIN_PADDB128,
19840 IX86_BUILTIN_PADDW128,
19841 IX86_BUILTIN_PADDD128,
19842 IX86_BUILTIN_PADDQ128,
19843 IX86_BUILTIN_PADDSB128,
19844 IX86_BUILTIN_PADDSW128,
19845 IX86_BUILTIN_PADDUSB128,
19846 IX86_BUILTIN_PADDUSW128,
19847 IX86_BUILTIN_PSUBB128,
19848 IX86_BUILTIN_PSUBW128,
19849 IX86_BUILTIN_PSUBD128,
19850 IX86_BUILTIN_PSUBQ128,
19851 IX86_BUILTIN_PSUBSB128,
19852 IX86_BUILTIN_PSUBSW128,
19853 IX86_BUILTIN_PSUBUSB128,
19854 IX86_BUILTIN_PSUBUSW128,
19856 IX86_BUILTIN_PAND128,
19857 IX86_BUILTIN_PANDN128,
19858 IX86_BUILTIN_POR128,
19859 IX86_BUILTIN_PXOR128,
19861 IX86_BUILTIN_PAVGB128,
19862 IX86_BUILTIN_PAVGW128,
19864 IX86_BUILTIN_PCMPEQB128,
19865 IX86_BUILTIN_PCMPEQW128,
19866 IX86_BUILTIN_PCMPEQD128,
19867 IX86_BUILTIN_PCMPGTB128,
19868 IX86_BUILTIN_PCMPGTW128,
19869 IX86_BUILTIN_PCMPGTD128,
19871 IX86_BUILTIN_PMADDWD128,
19873 IX86_BUILTIN_PMAXSW128,
19874 IX86_BUILTIN_PMAXUB128,
19875 IX86_BUILTIN_PMINSW128,
19876 IX86_BUILTIN_PMINUB128,
19878 IX86_BUILTIN_PMULUDQ,
19879 IX86_BUILTIN_PMULUDQ128,
19880 IX86_BUILTIN_PMULHUW128,
19881 IX86_BUILTIN_PMULHW128,
19882 IX86_BUILTIN_PMULLW128,
19884 IX86_BUILTIN_PSADBW128,
19885 IX86_BUILTIN_PSHUFHW,
19886 IX86_BUILTIN_PSHUFLW,
19887 IX86_BUILTIN_PSHUFD,
19889 IX86_BUILTIN_PSLLDQI128,
19890 IX86_BUILTIN_PSLLWI128,
19891 IX86_BUILTIN_PSLLDI128,
19892 IX86_BUILTIN_PSLLQI128,
19893 IX86_BUILTIN_PSRAWI128,
19894 IX86_BUILTIN_PSRADI128,
19895 IX86_BUILTIN_PSRLDQI128,
19896 IX86_BUILTIN_PSRLWI128,
19897 IX86_BUILTIN_PSRLDI128,
19898 IX86_BUILTIN_PSRLQI128,
19900 IX86_BUILTIN_PSLLDQ128,
19901 IX86_BUILTIN_PSLLW128,
19902 IX86_BUILTIN_PSLLD128,
19903 IX86_BUILTIN_PSLLQ128,
19904 IX86_BUILTIN_PSRAW128,
19905 IX86_BUILTIN_PSRAD128,
19906 IX86_BUILTIN_PSRLW128,
19907 IX86_BUILTIN_PSRLD128,
19908 IX86_BUILTIN_PSRLQ128,
19910 IX86_BUILTIN_PUNPCKHBW128,
19911 IX86_BUILTIN_PUNPCKHWD128,
19912 IX86_BUILTIN_PUNPCKHDQ128,
19913 IX86_BUILTIN_PUNPCKHQDQ128,
19914 IX86_BUILTIN_PUNPCKLBW128,
19915 IX86_BUILTIN_PUNPCKLWD128,
19916 IX86_BUILTIN_PUNPCKLDQ128,
19917 IX86_BUILTIN_PUNPCKLQDQ128,
19919 IX86_BUILTIN_CLFLUSH,
19920 IX86_BUILTIN_MFENCE,
19921 IX86_BUILTIN_LFENCE,
19924 IX86_BUILTIN_ADDSUBPS,
19925 IX86_BUILTIN_HADDPS,
19926 IX86_BUILTIN_HSUBPS,
19927 IX86_BUILTIN_MOVSHDUP,
19928 IX86_BUILTIN_MOVSLDUP,
19929 IX86_BUILTIN_ADDSUBPD,
19930 IX86_BUILTIN_HADDPD,
19931 IX86_BUILTIN_HSUBPD,
19932 IX86_BUILTIN_LDDQU,
19934 IX86_BUILTIN_MONITOR,
19935 IX86_BUILTIN_MWAIT,
19938 IX86_BUILTIN_PHADDW,
19939 IX86_BUILTIN_PHADDD,
19940 IX86_BUILTIN_PHADDSW,
19941 IX86_BUILTIN_PHSUBW,
19942 IX86_BUILTIN_PHSUBD,
19943 IX86_BUILTIN_PHSUBSW,
19944 IX86_BUILTIN_PMADDUBSW,
19945 IX86_BUILTIN_PMULHRSW,
19946 IX86_BUILTIN_PSHUFB,
19947 IX86_BUILTIN_PSIGNB,
19948 IX86_BUILTIN_PSIGNW,
19949 IX86_BUILTIN_PSIGND,
19950 IX86_BUILTIN_PALIGNR,
19951 IX86_BUILTIN_PABSB,
19952 IX86_BUILTIN_PABSW,
19953 IX86_BUILTIN_PABSD,
19955 IX86_BUILTIN_PHADDW128,
19956 IX86_BUILTIN_PHADDD128,
19957 IX86_BUILTIN_PHADDSW128,
19958 IX86_BUILTIN_PHSUBW128,
19959 IX86_BUILTIN_PHSUBD128,
19960 IX86_BUILTIN_PHSUBSW128,
19961 IX86_BUILTIN_PMADDUBSW128,
19962 IX86_BUILTIN_PMULHRSW128,
19963 IX86_BUILTIN_PSHUFB128,
19964 IX86_BUILTIN_PSIGNB128,
19965 IX86_BUILTIN_PSIGNW128,
19966 IX86_BUILTIN_PSIGND128,
19967 IX86_BUILTIN_PALIGNR128,
19968 IX86_BUILTIN_PABSB128,
19969 IX86_BUILTIN_PABSW128,
19970 IX86_BUILTIN_PABSD128,
19972 /* AMDFAM10 - SSE4A New Instructions. */
19973 IX86_BUILTIN_MOVNTSD,
19974 IX86_BUILTIN_MOVNTSS,
19975 IX86_BUILTIN_EXTRQI,
19976 IX86_BUILTIN_EXTRQ,
19977 IX86_BUILTIN_INSERTQI,
19978 IX86_BUILTIN_INSERTQ,
19981 IX86_BUILTIN_BLENDPD,
19982 IX86_BUILTIN_BLENDPS,
19983 IX86_BUILTIN_BLENDVPD,
19984 IX86_BUILTIN_BLENDVPS,
19985 IX86_BUILTIN_PBLENDVB128,
19986 IX86_BUILTIN_PBLENDW128,
19991 IX86_BUILTIN_INSERTPS128,
19993 IX86_BUILTIN_MOVNTDQA,
19994 IX86_BUILTIN_MPSADBW128,
19995 IX86_BUILTIN_PACKUSDW128,
19996 IX86_BUILTIN_PCMPEQQ,
19997 IX86_BUILTIN_PHMINPOSUW128,
19999 IX86_BUILTIN_PMAXSB128,
20000 IX86_BUILTIN_PMAXSD128,
20001 IX86_BUILTIN_PMAXUD128,
20002 IX86_BUILTIN_PMAXUW128,
20004 IX86_BUILTIN_PMINSB128,
20005 IX86_BUILTIN_PMINSD128,
20006 IX86_BUILTIN_PMINUD128,
20007 IX86_BUILTIN_PMINUW128,
20009 IX86_BUILTIN_PMOVSXBW128,
20010 IX86_BUILTIN_PMOVSXBD128,
20011 IX86_BUILTIN_PMOVSXBQ128,
20012 IX86_BUILTIN_PMOVSXWD128,
20013 IX86_BUILTIN_PMOVSXWQ128,
20014 IX86_BUILTIN_PMOVSXDQ128,
20016 IX86_BUILTIN_PMOVZXBW128,
20017 IX86_BUILTIN_PMOVZXBD128,
20018 IX86_BUILTIN_PMOVZXBQ128,
20019 IX86_BUILTIN_PMOVZXWD128,
20020 IX86_BUILTIN_PMOVZXWQ128,
20021 IX86_BUILTIN_PMOVZXDQ128,
20023 IX86_BUILTIN_PMULDQ128,
20024 IX86_BUILTIN_PMULLD128,
20026 IX86_BUILTIN_ROUNDPD,
20027 IX86_BUILTIN_ROUNDPS,
20028 IX86_BUILTIN_ROUNDSD,
20029 IX86_BUILTIN_ROUNDSS,
20031 IX86_BUILTIN_PTESTZ,
20032 IX86_BUILTIN_PTESTC,
20033 IX86_BUILTIN_PTESTNZC,
20035 IX86_BUILTIN_VEC_INIT_V2SI,
20036 IX86_BUILTIN_VEC_INIT_V4HI,
20037 IX86_BUILTIN_VEC_INIT_V8QI,
20038 IX86_BUILTIN_VEC_EXT_V2DF,
20039 IX86_BUILTIN_VEC_EXT_V2DI,
20040 IX86_BUILTIN_VEC_EXT_V4SF,
20041 IX86_BUILTIN_VEC_EXT_V4SI,
20042 IX86_BUILTIN_VEC_EXT_V8HI,
20043 IX86_BUILTIN_VEC_EXT_V2SI,
20044 IX86_BUILTIN_VEC_EXT_V4HI,
20045 IX86_BUILTIN_VEC_EXT_V16QI,
20046 IX86_BUILTIN_VEC_SET_V2DI,
20047 IX86_BUILTIN_VEC_SET_V4SF,
20048 IX86_BUILTIN_VEC_SET_V4SI,
20049 IX86_BUILTIN_VEC_SET_V8HI,
20050 IX86_BUILTIN_VEC_SET_V4HI,
20051 IX86_BUILTIN_VEC_SET_V16QI,
20053 IX86_BUILTIN_VEC_PACK_SFIX,
20056 IX86_BUILTIN_CRC32QI,
20057 IX86_BUILTIN_CRC32HI,
20058 IX86_BUILTIN_CRC32SI,
20059 IX86_BUILTIN_CRC32DI,
20061 IX86_BUILTIN_PCMPESTRI128,
20062 IX86_BUILTIN_PCMPESTRM128,
20063 IX86_BUILTIN_PCMPESTRA128,
20064 IX86_BUILTIN_PCMPESTRC128,
20065 IX86_BUILTIN_PCMPESTRO128,
20066 IX86_BUILTIN_PCMPESTRS128,
20067 IX86_BUILTIN_PCMPESTRZ128,
20068 IX86_BUILTIN_PCMPISTRI128,
20069 IX86_BUILTIN_PCMPISTRM128,
20070 IX86_BUILTIN_PCMPISTRA128,
20071 IX86_BUILTIN_PCMPISTRC128,
20072 IX86_BUILTIN_PCMPISTRO128,
20073 IX86_BUILTIN_PCMPISTRS128,
20074 IX86_BUILTIN_PCMPISTRZ128,
20076 IX86_BUILTIN_PCMPGTQ,
20078 /* AES instructions */
20079 IX86_BUILTIN_AESENC128,
20080 IX86_BUILTIN_AESENCLAST128,
20081 IX86_BUILTIN_AESDEC128,
20082 IX86_BUILTIN_AESDECLAST128,
20083 IX86_BUILTIN_AESIMC128,
20084 IX86_BUILTIN_AESKEYGENASSIST128,
20086 /* PCLMUL instruction */
20087 IX86_BUILTIN_PCLMULQDQ128,
20090 IX86_BUILTIN_ADDPD256,
20091 IX86_BUILTIN_ADDPS256,
20092 IX86_BUILTIN_ADDSUBPD256,
20093 IX86_BUILTIN_ADDSUBPS256,
20094 IX86_BUILTIN_ANDPD256,
20095 IX86_BUILTIN_ANDPS256,
20096 IX86_BUILTIN_ANDNPD256,
20097 IX86_BUILTIN_ANDNPS256,
20098 IX86_BUILTIN_BLENDPD256,
20099 IX86_BUILTIN_BLENDPS256,
20100 IX86_BUILTIN_BLENDVPD256,
20101 IX86_BUILTIN_BLENDVPS256,
20102 IX86_BUILTIN_DIVPD256,
20103 IX86_BUILTIN_DIVPS256,
20104 IX86_BUILTIN_DPPS256,
20105 IX86_BUILTIN_HADDPD256,
20106 IX86_BUILTIN_HADDPS256,
20107 IX86_BUILTIN_HSUBPD256,
20108 IX86_BUILTIN_HSUBPS256,
20109 IX86_BUILTIN_MAXPD256,
20110 IX86_BUILTIN_MAXPS256,
20111 IX86_BUILTIN_MINPD256,
20112 IX86_BUILTIN_MINPS256,
20113 IX86_BUILTIN_MULPD256,
20114 IX86_BUILTIN_MULPS256,
20115 IX86_BUILTIN_ORPD256,
20116 IX86_BUILTIN_ORPS256,
20117 IX86_BUILTIN_SHUFPD256,
20118 IX86_BUILTIN_SHUFPS256,
20119 IX86_BUILTIN_SUBPD256,
20120 IX86_BUILTIN_SUBPS256,
20121 IX86_BUILTIN_XORPD256,
20122 IX86_BUILTIN_XORPS256,
20123 IX86_BUILTIN_CMPSD,
20124 IX86_BUILTIN_CMPSS,
20125 IX86_BUILTIN_CMPPD,
20126 IX86_BUILTIN_CMPPS,
20127 IX86_BUILTIN_CMPPD256,
20128 IX86_BUILTIN_CMPPS256,
20129 IX86_BUILTIN_CVTDQ2PD256,
20130 IX86_BUILTIN_CVTDQ2PS256,
20131 IX86_BUILTIN_CVTPD2PS256,
20132 IX86_BUILTIN_CVTPS2DQ256,
20133 IX86_BUILTIN_CVTPS2PD256,
20134 IX86_BUILTIN_CVTTPD2DQ256,
20135 IX86_BUILTIN_CVTPD2DQ256,
20136 IX86_BUILTIN_CVTTPS2DQ256,
20137 IX86_BUILTIN_EXTRACTF128PD256,
20138 IX86_BUILTIN_EXTRACTF128PS256,
20139 IX86_BUILTIN_EXTRACTF128SI256,
20140 IX86_BUILTIN_VZEROALL,
20141 IX86_BUILTIN_VZEROUPPER,
20142 IX86_BUILTIN_VZEROUPPER_REX64,
20143 IX86_BUILTIN_VPERMILVARPD,
20144 IX86_BUILTIN_VPERMILVARPS,
20145 IX86_BUILTIN_VPERMILVARPD256,
20146 IX86_BUILTIN_VPERMILVARPS256,
20147 IX86_BUILTIN_VPERMILPD,
20148 IX86_BUILTIN_VPERMILPS,
20149 IX86_BUILTIN_VPERMILPD256,
20150 IX86_BUILTIN_VPERMILPS256,
20151 IX86_BUILTIN_VPERM2F128PD256,
20152 IX86_BUILTIN_VPERM2F128PS256,
20153 IX86_BUILTIN_VPERM2F128SI256,
20154 IX86_BUILTIN_VBROADCASTSS,
20155 IX86_BUILTIN_VBROADCASTSD256,
20156 IX86_BUILTIN_VBROADCASTSS256,
20157 IX86_BUILTIN_VBROADCASTPD256,
20158 IX86_BUILTIN_VBROADCASTPS256,
20159 IX86_BUILTIN_VINSERTF128PD256,
20160 IX86_BUILTIN_VINSERTF128PS256,
20161 IX86_BUILTIN_VINSERTF128SI256,
20162 IX86_BUILTIN_LOADUPD256,
20163 IX86_BUILTIN_LOADUPS256,
20164 IX86_BUILTIN_STOREUPD256,
20165 IX86_BUILTIN_STOREUPS256,
20166 IX86_BUILTIN_LDDQU256,
20167 IX86_BUILTIN_MOVNTDQ256,
20168 IX86_BUILTIN_MOVNTPD256,
20169 IX86_BUILTIN_MOVNTPS256,
20170 IX86_BUILTIN_LOADDQU256,
20171 IX86_BUILTIN_STOREDQU256,
20172 IX86_BUILTIN_MASKLOADPD,
20173 IX86_BUILTIN_MASKLOADPS,
20174 IX86_BUILTIN_MASKSTOREPD,
20175 IX86_BUILTIN_MASKSTOREPS,
20176 IX86_BUILTIN_MASKLOADPD256,
20177 IX86_BUILTIN_MASKLOADPS256,
20178 IX86_BUILTIN_MASKSTOREPD256,
20179 IX86_BUILTIN_MASKSTOREPS256,
20180 IX86_BUILTIN_MOVSHDUP256,
20181 IX86_BUILTIN_MOVSLDUP256,
20182 IX86_BUILTIN_MOVDDUP256,
20184 IX86_BUILTIN_SQRTPD256,
20185 IX86_BUILTIN_SQRTPS256,
20186 IX86_BUILTIN_SQRTPS_NR256,
20187 IX86_BUILTIN_RSQRTPS256,
20188 IX86_BUILTIN_RSQRTPS_NR256,
20190 IX86_BUILTIN_RCPPS256,
20192 IX86_BUILTIN_ROUNDPD256,
20193 IX86_BUILTIN_ROUNDPS256,
20195 IX86_BUILTIN_UNPCKHPD256,
20196 IX86_BUILTIN_UNPCKLPD256,
20197 IX86_BUILTIN_UNPCKHPS256,
20198 IX86_BUILTIN_UNPCKLPS256,
20200 IX86_BUILTIN_SI256_SI,
20201 IX86_BUILTIN_PS256_PS,
20202 IX86_BUILTIN_PD256_PD,
20203 IX86_BUILTIN_SI_SI256,
20204 IX86_BUILTIN_PS_PS256,
20205 IX86_BUILTIN_PD_PD256,
20207 IX86_BUILTIN_VTESTZPD,
20208 IX86_BUILTIN_VTESTCPD,
20209 IX86_BUILTIN_VTESTNZCPD,
20210 IX86_BUILTIN_VTESTZPS,
20211 IX86_BUILTIN_VTESTCPS,
20212 IX86_BUILTIN_VTESTNZCPS,
20213 IX86_BUILTIN_VTESTZPD256,
20214 IX86_BUILTIN_VTESTCPD256,
20215 IX86_BUILTIN_VTESTNZCPD256,
20216 IX86_BUILTIN_VTESTZPS256,
20217 IX86_BUILTIN_VTESTCPS256,
20218 IX86_BUILTIN_VTESTNZCPS256,
20219 IX86_BUILTIN_PTESTZ256,
20220 IX86_BUILTIN_PTESTC256,
20221 IX86_BUILTIN_PTESTNZC256,
20223 IX86_BUILTIN_MOVMSKPD256,
20224 IX86_BUILTIN_MOVMSKPS256,
20226 /* TFmode support builtins. */
20228 IX86_BUILTIN_HUGE_VALQ,
20229 IX86_BUILTIN_FABSQ,
20230 IX86_BUILTIN_COPYSIGNQ,
20232 /* SSE5 instructions */
20233 IX86_BUILTIN_FMADDSS,
20234 IX86_BUILTIN_FMADDSD,
20235 IX86_BUILTIN_FMADDPS,
20236 IX86_BUILTIN_FMADDPD,
20237 IX86_BUILTIN_FMSUBSS,
20238 IX86_BUILTIN_FMSUBSD,
20239 IX86_BUILTIN_FMSUBPS,
20240 IX86_BUILTIN_FMSUBPD,
20241 IX86_BUILTIN_FNMADDSS,
20242 IX86_BUILTIN_FNMADDSD,
20243 IX86_BUILTIN_FNMADDPS,
20244 IX86_BUILTIN_FNMADDPD,
20245 IX86_BUILTIN_FNMSUBSS,
20246 IX86_BUILTIN_FNMSUBSD,
20247 IX86_BUILTIN_FNMSUBPS,
20248 IX86_BUILTIN_FNMSUBPD,
20249 IX86_BUILTIN_PCMOV,
20250 IX86_BUILTIN_PCMOV_V2DI,
20251 IX86_BUILTIN_PCMOV_V4SI,
20252 IX86_BUILTIN_PCMOV_V8HI,
20253 IX86_BUILTIN_PCMOV_V16QI,
20254 IX86_BUILTIN_PCMOV_V4SF,
20255 IX86_BUILTIN_PCMOV_V2DF,
20256 IX86_BUILTIN_PPERM,
20257 IX86_BUILTIN_PERMPS,
20258 IX86_BUILTIN_PERMPD,
20259 IX86_BUILTIN_PMACSSWW,
20260 IX86_BUILTIN_PMACSWW,
20261 IX86_BUILTIN_PMACSSWD,
20262 IX86_BUILTIN_PMACSWD,
20263 IX86_BUILTIN_PMACSSDD,
20264 IX86_BUILTIN_PMACSDD,
20265 IX86_BUILTIN_PMACSSDQL,
20266 IX86_BUILTIN_PMACSSDQH,
20267 IX86_BUILTIN_PMACSDQL,
20268 IX86_BUILTIN_PMACSDQH,
20269 IX86_BUILTIN_PMADCSSWD,
20270 IX86_BUILTIN_PMADCSWD,
20271 IX86_BUILTIN_PHADDBW,
20272 IX86_BUILTIN_PHADDBD,
20273 IX86_BUILTIN_PHADDBQ,
20274 IX86_BUILTIN_PHADDWD,
20275 IX86_BUILTIN_PHADDWQ,
20276 IX86_BUILTIN_PHADDDQ,
20277 IX86_BUILTIN_PHADDUBW,
20278 IX86_BUILTIN_PHADDUBD,
20279 IX86_BUILTIN_PHADDUBQ,
20280 IX86_BUILTIN_PHADDUWD,
20281 IX86_BUILTIN_PHADDUWQ,
20282 IX86_BUILTIN_PHADDUDQ,
20283 IX86_BUILTIN_PHSUBBW,
20284 IX86_BUILTIN_PHSUBWD,
20285 IX86_BUILTIN_PHSUBDQ,
20286 IX86_BUILTIN_PROTB,
20287 IX86_BUILTIN_PROTW,
20288 IX86_BUILTIN_PROTD,
20289 IX86_BUILTIN_PROTQ,
20290 IX86_BUILTIN_PROTB_IMM,
20291 IX86_BUILTIN_PROTW_IMM,
20292 IX86_BUILTIN_PROTD_IMM,
20293 IX86_BUILTIN_PROTQ_IMM,
20294 IX86_BUILTIN_PSHLB,
20295 IX86_BUILTIN_PSHLW,
20296 IX86_BUILTIN_PSHLD,
20297 IX86_BUILTIN_PSHLQ,
20298 IX86_BUILTIN_PSHAB,
20299 IX86_BUILTIN_PSHAW,
20300 IX86_BUILTIN_PSHAD,
20301 IX86_BUILTIN_PSHAQ,
20302 IX86_BUILTIN_FRCZSS,
20303 IX86_BUILTIN_FRCZSD,
20304 IX86_BUILTIN_FRCZPS,
20305 IX86_BUILTIN_FRCZPD,
20306 IX86_BUILTIN_CVTPH2PS,
20307 IX86_BUILTIN_CVTPS2PH,
20309 IX86_BUILTIN_COMEQSS,
20310 IX86_BUILTIN_COMNESS,
20311 IX86_BUILTIN_COMLTSS,
20312 IX86_BUILTIN_COMLESS,
20313 IX86_BUILTIN_COMGTSS,
20314 IX86_BUILTIN_COMGESS,
20315 IX86_BUILTIN_COMUEQSS,
20316 IX86_BUILTIN_COMUNESS,
20317 IX86_BUILTIN_COMULTSS,
20318 IX86_BUILTIN_COMULESS,
20319 IX86_BUILTIN_COMUGTSS,
20320 IX86_BUILTIN_COMUGESS,
20321 IX86_BUILTIN_COMORDSS,
20322 IX86_BUILTIN_COMUNORDSS,
20323 IX86_BUILTIN_COMFALSESS,
20324 IX86_BUILTIN_COMTRUESS,
20326 IX86_BUILTIN_COMEQSD,
20327 IX86_BUILTIN_COMNESD,
20328 IX86_BUILTIN_COMLTSD,
20329 IX86_BUILTIN_COMLESD,
20330 IX86_BUILTIN_COMGTSD,
20331 IX86_BUILTIN_COMGESD,
20332 IX86_BUILTIN_COMUEQSD,
20333 IX86_BUILTIN_COMUNESD,
20334 IX86_BUILTIN_COMULTSD,
20335 IX86_BUILTIN_COMULESD,
20336 IX86_BUILTIN_COMUGTSD,
20337 IX86_BUILTIN_COMUGESD,
20338 IX86_BUILTIN_COMORDSD,
20339 IX86_BUILTIN_COMUNORDSD,
20340 IX86_BUILTIN_COMFALSESD,
20341 IX86_BUILTIN_COMTRUESD,
20343 IX86_BUILTIN_COMEQPS,
20344 IX86_BUILTIN_COMNEPS,
20345 IX86_BUILTIN_COMLTPS,
20346 IX86_BUILTIN_COMLEPS,
20347 IX86_BUILTIN_COMGTPS,
20348 IX86_BUILTIN_COMGEPS,
20349 IX86_BUILTIN_COMUEQPS,
20350 IX86_BUILTIN_COMUNEPS,
20351 IX86_BUILTIN_COMULTPS,
20352 IX86_BUILTIN_COMULEPS,
20353 IX86_BUILTIN_COMUGTPS,
20354 IX86_BUILTIN_COMUGEPS,
20355 IX86_BUILTIN_COMORDPS,
20356 IX86_BUILTIN_COMUNORDPS,
20357 IX86_BUILTIN_COMFALSEPS,
20358 IX86_BUILTIN_COMTRUEPS,
20360 IX86_BUILTIN_COMEQPD,
20361 IX86_BUILTIN_COMNEPD,
20362 IX86_BUILTIN_COMLTPD,
20363 IX86_BUILTIN_COMLEPD,
20364 IX86_BUILTIN_COMGTPD,
20365 IX86_BUILTIN_COMGEPD,
20366 IX86_BUILTIN_COMUEQPD,
20367 IX86_BUILTIN_COMUNEPD,
20368 IX86_BUILTIN_COMULTPD,
20369 IX86_BUILTIN_COMULEPD,
20370 IX86_BUILTIN_COMUGTPD,
20371 IX86_BUILTIN_COMUGEPD,
20372 IX86_BUILTIN_COMORDPD,
20373 IX86_BUILTIN_COMUNORDPD,
20374 IX86_BUILTIN_COMFALSEPD,
20375 IX86_BUILTIN_COMTRUEPD,
20377 IX86_BUILTIN_PCOMEQUB,
20378 IX86_BUILTIN_PCOMNEUB,
20379 IX86_BUILTIN_PCOMLTUB,
20380 IX86_BUILTIN_PCOMLEUB,
20381 IX86_BUILTIN_PCOMGTUB,
20382 IX86_BUILTIN_PCOMGEUB,
20383 IX86_BUILTIN_PCOMFALSEUB,
20384 IX86_BUILTIN_PCOMTRUEUB,
20385 IX86_BUILTIN_PCOMEQUW,
20386 IX86_BUILTIN_PCOMNEUW,
20387 IX86_BUILTIN_PCOMLTUW,
20388 IX86_BUILTIN_PCOMLEUW,
20389 IX86_BUILTIN_PCOMGTUW,
20390 IX86_BUILTIN_PCOMGEUW,
20391 IX86_BUILTIN_PCOMFALSEUW,
20392 IX86_BUILTIN_PCOMTRUEUW,
20393 IX86_BUILTIN_PCOMEQUD,
20394 IX86_BUILTIN_PCOMNEUD,
20395 IX86_BUILTIN_PCOMLTUD,
20396 IX86_BUILTIN_PCOMLEUD,
20397 IX86_BUILTIN_PCOMGTUD,
20398 IX86_BUILTIN_PCOMGEUD,
20399 IX86_BUILTIN_PCOMFALSEUD,
20400 IX86_BUILTIN_PCOMTRUEUD,
20401 IX86_BUILTIN_PCOMEQUQ,
20402 IX86_BUILTIN_PCOMNEUQ,
20403 IX86_BUILTIN_PCOMLTUQ,
20404 IX86_BUILTIN_PCOMLEUQ,
20405 IX86_BUILTIN_PCOMGTUQ,
20406 IX86_BUILTIN_PCOMGEUQ,
20407 IX86_BUILTIN_PCOMFALSEUQ,
20408 IX86_BUILTIN_PCOMTRUEUQ,
20410 IX86_BUILTIN_PCOMEQB,
20411 IX86_BUILTIN_PCOMNEB,
20412 IX86_BUILTIN_PCOMLTB,
20413 IX86_BUILTIN_PCOMLEB,
20414 IX86_BUILTIN_PCOMGTB,
20415 IX86_BUILTIN_PCOMGEB,
20416 IX86_BUILTIN_PCOMFALSEB,
20417 IX86_BUILTIN_PCOMTRUEB,
20418 IX86_BUILTIN_PCOMEQW,
20419 IX86_BUILTIN_PCOMNEW,
20420 IX86_BUILTIN_PCOMLTW,
20421 IX86_BUILTIN_PCOMLEW,
20422 IX86_BUILTIN_PCOMGTW,
20423 IX86_BUILTIN_PCOMGEW,
20424 IX86_BUILTIN_PCOMFALSEW,
20425 IX86_BUILTIN_PCOMTRUEW,
20426 IX86_BUILTIN_PCOMEQD,
20427 IX86_BUILTIN_PCOMNED,
20428 IX86_BUILTIN_PCOMLTD,
20429 IX86_BUILTIN_PCOMLED,
20430 IX86_BUILTIN_PCOMGTD,
20431 IX86_BUILTIN_PCOMGED,
20432 IX86_BUILTIN_PCOMFALSED,
20433 IX86_BUILTIN_PCOMTRUED,
20434 IX86_BUILTIN_PCOMEQQ,
20435 IX86_BUILTIN_PCOMNEQ,
20436 IX86_BUILTIN_PCOMLTQ,
20437 IX86_BUILTIN_PCOMLEQ,
20438 IX86_BUILTIN_PCOMGTQ,
20439 IX86_BUILTIN_PCOMGEQ,
20440 IX86_BUILTIN_PCOMFALSEQ,
20441 IX86_BUILTIN_PCOMTRUEQ,
20446 /* Table for the ix86 builtin decls. */
20447 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20449 /* Table of all of the builtin functions that are possible with different ISA's
20450 but are waiting to be built until a function is declared to use that
20452 struct builtin_isa GTY(())
20454 tree type; /* builtin type to use in the declaration */
20455 const char *name; /* function name */
20456 int isa; /* isa_flags this builtin is defined for */
20457 bool const_p; /* true if the declaration is constant */
20460 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20463 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20464 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20465 * function decl in the ix86_builtins array. Returns the function decl or
20466 * NULL_TREE, if the builtin was not added.
20468 * If the front end has a special hook for builtin functions, delay adding
20469 * builtin functions that aren't in the current ISA until the ISA is changed
20470 * with function specific optimization. Doing so, can save about 300K for the
20471 * default compiler. When the builtin is expanded, check at that time whether
20474 * If the front end doesn't have a special hook, record all builtins, even if
20475 * it isn't an instruction set in the current ISA in case the user uses
20476 * function specific options for a different ISA, so that we don't get scope
20477 * errors if a builtin is added in the middle of a function scope. */
20480 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20482 tree decl = NULL_TREE;
20484 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20486 ix86_builtins_isa[(int) code].isa = mask;
20488 if ((mask & ix86_isa_flags) != 0
20489 || (lang_hooks.builtin_function
20490 == lang_hooks.builtin_function_ext_scope))
20493 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20495 ix86_builtins[(int) code] = decl;
20496 ix86_builtins_isa[(int) code].type = NULL_TREE;
20500 ix86_builtins[(int) code] = NULL_TREE;
20501 ix86_builtins_isa[(int) code].const_p = false;
20502 ix86_builtins_isa[(int) code].type = type;
20503 ix86_builtins_isa[(int) code].name = name;
20510 /* Like def_builtin, but also marks the function decl "const". */
20513 def_builtin_const (int mask, const char *name, tree type,
20514 enum ix86_builtins code)
20516 tree decl = def_builtin (mask, name, type, code);
20518 TREE_READONLY (decl) = 1;
20520 ix86_builtins_isa[(int) code].const_p = true;
20525 /* Add any new builtin functions for a given ISA that may not have been
20526 declared. This saves a bit of space compared to adding all of the
20527 declarations to the tree, even if we didn't use them. */
20530 ix86_add_new_builtins (int isa)
20535 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20537 if ((ix86_builtins_isa[i].isa & isa) != 0
20538 && ix86_builtins_isa[i].type != NULL_TREE)
20540 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20541 ix86_builtins_isa[i].type,
20542 i, BUILT_IN_MD, NULL,
20545 ix86_builtins[i] = decl;
20546 ix86_builtins_isa[i].type = NULL_TREE;
20547 if (ix86_builtins_isa[i].const_p)
20548 TREE_READONLY (decl) = 1;
20553 /* Bits for builtin_description.flag. */
20555 /* Set when we don't support the comparison natively, and should
20556 swap_comparison in order to support it. */
20557 #define BUILTIN_DESC_SWAP_OPERANDS 1
20559 struct builtin_description
20561 const unsigned int mask;
20562 const enum insn_code icode;
20563 const char *const name;
20564 const enum ix86_builtins code;
20565 const enum rtx_code comparison;
20569 static const struct builtin_description bdesc_comi[] =
20571 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20572 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20573 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20574 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20575 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20576 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20577 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20578 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20579 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20580 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20581 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20582 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20586 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20587 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20588 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20589 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20590 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20591 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20593 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20594 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20597 static const struct builtin_description bdesc_pcmpestr[] =
20600 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20601 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20602 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20603 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20604 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20605 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20606 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20609 static const struct builtin_description bdesc_pcmpistr[] =
20612 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20613 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20614 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20615 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20616 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20617 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20618 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20621 /* Special builtin types */
20622 enum ix86_special_builtin_type
20624 SPECIAL_FTYPE_UNKNOWN,
20626 V32QI_FTYPE_PCCHAR,
20627 V16QI_FTYPE_PCCHAR,
20629 V8SF_FTYPE_PCFLOAT,
20631 V4DF_FTYPE_PCDOUBLE,
20632 V4SF_FTYPE_PCFLOAT,
20633 V2DF_FTYPE_PCDOUBLE,
20634 V8SF_FTYPE_PCV8SF_V8SF,
20635 V4DF_FTYPE_PCV4DF_V4DF,
20636 V4SF_FTYPE_V4SF_PCV2SF,
20637 V4SF_FTYPE_PCV4SF_V4SF,
20638 V2DF_FTYPE_V2DF_PCDOUBLE,
20639 V2DF_FTYPE_PCV2DF_V2DF,
20641 VOID_FTYPE_PV2SF_V4SF,
20642 VOID_FTYPE_PV4DI_V4DI,
20643 VOID_FTYPE_PV2DI_V2DI,
20644 VOID_FTYPE_PCHAR_V32QI,
20645 VOID_FTYPE_PCHAR_V16QI,
20646 VOID_FTYPE_PFLOAT_V8SF,
20647 VOID_FTYPE_PFLOAT_V4SF,
20648 VOID_FTYPE_PDOUBLE_V4DF,
20649 VOID_FTYPE_PDOUBLE_V2DF,
20651 VOID_FTYPE_PINT_INT,
20652 VOID_FTYPE_PV8SF_V8SF_V8SF,
20653 VOID_FTYPE_PV4DF_V4DF_V4DF,
20654 VOID_FTYPE_PV4SF_V4SF_V4SF,
20655 VOID_FTYPE_PV2DF_V2DF_V2DF
20658 /* Builtin types */
20659 enum ix86_builtin_type
20662 FLOAT128_FTYPE_FLOAT128,
20664 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20665 INT_FTYPE_V8SF_V8SF_PTEST,
20666 INT_FTYPE_V4DI_V4DI_PTEST,
20667 INT_FTYPE_V4DF_V4DF_PTEST,
20668 INT_FTYPE_V4SF_V4SF_PTEST,
20669 INT_FTYPE_V2DI_V2DI_PTEST,
20670 INT_FTYPE_V2DF_V2DF_PTEST,
20702 V4SF_FTYPE_V4SF_VEC_MERGE,
20711 V2DF_FTYPE_V2DF_VEC_MERGE,
20722 V16QI_FTYPE_V16QI_V16QI,
20723 V16QI_FTYPE_V8HI_V8HI,
20724 V8QI_FTYPE_V8QI_V8QI,
20725 V8QI_FTYPE_V4HI_V4HI,
20726 V8HI_FTYPE_V8HI_V8HI,
20727 V8HI_FTYPE_V8HI_V8HI_COUNT,
20728 V8HI_FTYPE_V16QI_V16QI,
20729 V8HI_FTYPE_V4SI_V4SI,
20730 V8HI_FTYPE_V8HI_SI_COUNT,
20731 V8SF_FTYPE_V8SF_V8SF,
20732 V8SF_FTYPE_V8SF_V8SI,
20733 V4SI_FTYPE_V4SI_V4SI,
20734 V4SI_FTYPE_V4SI_V4SI_COUNT,
20735 V4SI_FTYPE_V8HI_V8HI,
20736 V4SI_FTYPE_V4SF_V4SF,
20737 V4SI_FTYPE_V2DF_V2DF,
20738 V4SI_FTYPE_V4SI_SI_COUNT,
20739 V4HI_FTYPE_V4HI_V4HI,
20740 V4HI_FTYPE_V4HI_V4HI_COUNT,
20741 V4HI_FTYPE_V8QI_V8QI,
20742 V4HI_FTYPE_V2SI_V2SI,
20743 V4HI_FTYPE_V4HI_SI_COUNT,
20744 V4DF_FTYPE_V4DF_V4DF,
20745 V4DF_FTYPE_V4DF_V4DI,
20746 V4SF_FTYPE_V4SF_V4SF,
20747 V4SF_FTYPE_V4SF_V4SF_SWAP,
20748 V4SF_FTYPE_V4SF_V4SI,
20749 V4SF_FTYPE_V4SF_V2SI,
20750 V4SF_FTYPE_V4SF_V2DF,
20751 V4SF_FTYPE_V4SF_DI,
20752 V4SF_FTYPE_V4SF_SI,
20753 V2DI_FTYPE_V2DI_V2DI,
20754 V2DI_FTYPE_V2DI_V2DI_COUNT,
20755 V2DI_FTYPE_V16QI_V16QI,
20756 V2DI_FTYPE_V4SI_V4SI,
20757 V2DI_FTYPE_V2DI_V16QI,
20758 V2DI_FTYPE_V2DF_V2DF,
20759 V2DI_FTYPE_V2DI_SI_COUNT,
20760 V2SI_FTYPE_V2SI_V2SI,
20761 V2SI_FTYPE_V2SI_V2SI_COUNT,
20762 V2SI_FTYPE_V4HI_V4HI,
20763 V2SI_FTYPE_V2SF_V2SF,
20764 V2SI_FTYPE_V2SI_SI_COUNT,
20765 V2DF_FTYPE_V2DF_V2DF,
20766 V2DF_FTYPE_V2DF_V2DF_SWAP,
20767 V2DF_FTYPE_V2DF_V4SF,
20768 V2DF_FTYPE_V2DF_V2DI,
20769 V2DF_FTYPE_V2DF_DI,
20770 V2DF_FTYPE_V2DF_SI,
20771 V2SF_FTYPE_V2SF_V2SF,
20772 V1DI_FTYPE_V1DI_V1DI,
20773 V1DI_FTYPE_V1DI_V1DI_COUNT,
20774 V1DI_FTYPE_V8QI_V8QI,
20775 V1DI_FTYPE_V2SI_V2SI,
20776 V1DI_FTYPE_V1DI_SI_COUNT,
20777 UINT64_FTYPE_UINT64_UINT64,
20778 UINT_FTYPE_UINT_UINT,
20779 UINT_FTYPE_UINT_USHORT,
20780 UINT_FTYPE_UINT_UCHAR,
20781 V8HI_FTYPE_V8HI_INT,
20782 V4SI_FTYPE_V4SI_INT,
20783 V4HI_FTYPE_V4HI_INT,
20784 V8SF_FTYPE_V8SF_INT,
20785 V4SI_FTYPE_V8SI_INT,
20786 V4SF_FTYPE_V8SF_INT,
20787 V2DF_FTYPE_V4DF_INT,
20788 V4DF_FTYPE_V4DF_INT,
20789 V4SF_FTYPE_V4SF_INT,
20790 V2DI_FTYPE_V2DI_INT,
20791 V2DI2TI_FTYPE_V2DI_INT,
20792 V2DF_FTYPE_V2DF_INT,
20793 V16QI_FTYPE_V16QI_V16QI_V16QI,
20794 V8SF_FTYPE_V8SF_V8SF_V8SF,
20795 V4DF_FTYPE_V4DF_V4DF_V4DF,
20796 V4SF_FTYPE_V4SF_V4SF_V4SF,
20797 V2DF_FTYPE_V2DF_V2DF_V2DF,
20798 V16QI_FTYPE_V16QI_V16QI_INT,
20799 V8SI_FTYPE_V8SI_V8SI_INT,
20800 V8SI_FTYPE_V8SI_V4SI_INT,
20801 V8HI_FTYPE_V8HI_V8HI_INT,
20802 V8SF_FTYPE_V8SF_V8SF_INT,
20803 V8SF_FTYPE_V8SF_V4SF_INT,
20804 V4SI_FTYPE_V4SI_V4SI_INT,
20805 V4DF_FTYPE_V4DF_V4DF_INT,
20806 V4DF_FTYPE_V4DF_V2DF_INT,
20807 V4SF_FTYPE_V4SF_V4SF_INT,
20808 V2DI_FTYPE_V2DI_V2DI_INT,
20809 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20810 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20811 V2DF_FTYPE_V2DF_V2DF_INT,
20812 V2DI_FTYPE_V2DI_UINT_UINT,
20813 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20816 /* Special builtins with variable number of arguments. */
20817 static const struct builtin_description bdesc_special_args[] =
20820 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20823 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20826 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20827 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20828 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20830 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20831 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20832 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20833 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20835 /* SSE or 3DNow!A */
20836 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20837 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20854 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20857 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20860 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20861 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20865 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20866 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20870 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20876 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
20883 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20886 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20887 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20888 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20889 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20892 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20893 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20896 /* Builtins with variable number of arguments. */
20897 static const struct builtin_description bdesc_args[] =
20900 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20901 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20902 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20903 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20904 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20905 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20907 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20908 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20909 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20910 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20911 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20912 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20913 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20914 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20916 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20917 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20919 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20920 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20921 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20922 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20924 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20925 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20926 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20927 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20928 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20929 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20931 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20932 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20933 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20934 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20935 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20936 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20938 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20939 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20940 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20942 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20944 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20945 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20946 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20947 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20948 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20949 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20951 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20952 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20953 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20954 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20955 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20956 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20958 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20959 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20960 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20961 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20964 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20965 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20966 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20967 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20969 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20970 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20971 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20972 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20973 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20974 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20975 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20976 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20977 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20978 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20979 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20980 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20981 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20982 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20983 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20986 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20987 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20988 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20989 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20990 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20991 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20994 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20995 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20996 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20998 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20999 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21002 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21003 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21004 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21005 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21007 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21009 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21010 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21011 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21012 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21024 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21026 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21027 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21028 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21029 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21030 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21031 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21032 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21033 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21034 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21035 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21036 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21037 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21038 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21039 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21041 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21042 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21043 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21044 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21046 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21047 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21048 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21049 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21051 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21052 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21053 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21054 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21055 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21057 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21058 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21059 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21061 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21063 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21064 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21065 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21067 /* SSE MMX or 3Dnow!A */
21068 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21069 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21070 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21072 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21073 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21074 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21075 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21077 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21078 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21080 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21091 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21101 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21102 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21108 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21109 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21110 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21111 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21112 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21113 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21114 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21115 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21126 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21129 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21131 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21133 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21136 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21139 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21140 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21143 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21145 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21146 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21152 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21154 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21155 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21156 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21157 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21158 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21159 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21160 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21161 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21168 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21169 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21170 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21172 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21173 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21175 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21177 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21178 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21190 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21191 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21192 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21206 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21208 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21211 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21217 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21222 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21223 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21224 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21225 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21226 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21227 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21230 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21231 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21232 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21233 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21234 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21235 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21237 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21238 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21239 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21240 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21246 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21248 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21249 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21254 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21255 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21258 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21259 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21261 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21262 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21263 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21264 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21265 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21266 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21269 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21270 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21271 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21272 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21273 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21274 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21276 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21277 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21278 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21279 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21280 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21281 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21282 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21283 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21284 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21285 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21286 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21287 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21288 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21289 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21290 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21291 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21292 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21293 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21294 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21295 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21296 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21297 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21298 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21299 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21302 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21303 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21306 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21307 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21308 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21309 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21310 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21311 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21312 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21313 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21314 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21315 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21317 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21318 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21319 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21320 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21321 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21322 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21323 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21324 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21325 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21326 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21327 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21328 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21329 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21331 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21332 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21333 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21334 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21335 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21336 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21337 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21338 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21339 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21340 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21341 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21342 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21344 /* SSE4.1 and SSE5 */
21345 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21346 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21347 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21348 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21350 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21351 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21352 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21355 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21356 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21357 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21358 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21359 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21362 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21363 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21364 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21365 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21368 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21369 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21371 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21372 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21373 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21374 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21377 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21380 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21381 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21382 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21383 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21384 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21385 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21386 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21387 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21388 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21389 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21390 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21394 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21395 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21396 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21397 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21398 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21399 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21400 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21401 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21402 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21403 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21404 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21405 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21407 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21409 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21410 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21412 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21413 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21430 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21433 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21434 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21435 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21439 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21443 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21447 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21448 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21449 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21451 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21452 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21453 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21454 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21455 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21457 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21459 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21460 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21462 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21463 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21464 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21467 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21468 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21469 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21470 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21471 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21472 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21474 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21475 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21476 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21477 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21478 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21479 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21480 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21481 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21482 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21483 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21484 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21485 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21486 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21487 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21488 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21490 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21491 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21495 enum multi_arg_type {
21505 MULTI_ARG_3_PERMPS,
21506 MULTI_ARG_3_PERMPD,
21513 MULTI_ARG_2_DI_IMM,
21514 MULTI_ARG_2_SI_IMM,
21515 MULTI_ARG_2_HI_IMM,
21516 MULTI_ARG_2_QI_IMM,
21517 MULTI_ARG_2_SF_CMP,
21518 MULTI_ARG_2_DF_CMP,
21519 MULTI_ARG_2_DI_CMP,
21520 MULTI_ARG_2_SI_CMP,
21521 MULTI_ARG_2_HI_CMP,
21522 MULTI_ARG_2_QI_CMP,
21545 static const struct builtin_description bdesc_multi_arg[] =
21547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21559 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21563 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21564 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21565 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21566 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21567 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21568 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21569 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21570 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21571 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21572 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21573 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21574 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21575 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21576 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21577 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21578 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21579 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21580 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21581 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21582 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21583 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21584 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21585 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21586 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21587 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21588 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21589 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21590 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21591 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21592 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21593 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21594 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21595 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21596 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21597 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21598 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21599 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21600 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21601 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21602 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21603 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21604 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21605 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21606 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21607 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21608 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21609 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21610 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21611 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21612 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21613 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21614 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21615 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21616 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21617 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21618 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21619 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21620 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21621 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21623 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21624 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21625 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21626 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21627 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21628 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21629 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21630 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21631 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21632 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21633 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21634 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21635 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21636 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21637 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21638 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21640 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21641 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21642 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21643 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21644 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21645 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21646 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21647 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21648 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21649 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21650 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21651 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21652 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21653 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21654 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21655 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21657 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21658 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21659 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21660 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21661 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21662 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21663 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21664 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21665 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21666 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21667 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21668 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21669 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21670 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21671 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21672 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21674 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21675 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21676 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21677 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21678 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21679 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21680 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21681 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21682 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21683 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21684 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21685 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21686 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21687 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21688 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21689 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21691 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21692 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21693 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21699 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21700 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21701 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21707 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21708 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21709 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21715 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21716 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21718 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21719 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21720 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21721 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21724 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21727 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21732 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21733 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21736 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21737 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21739 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21740 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21741 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21742 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21743 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21744 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21745 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21747 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21748 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21749 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21750 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21751 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21752 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21753 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21755 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21756 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21757 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21758 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21759 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21760 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21761 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21762 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21764 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21765 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21766 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21767 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21768 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21769 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21770 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21771 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21773 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21774 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21775 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21776 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21777 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21778 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21779 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21780 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21783 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21784 in the current target ISA to allow the user to compile particular modules
21785 with different target specific options that differ from the command line
21788 ix86_init_mmx_sse_builtins (void)
21790 const struct builtin_description * d;
21793 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21794 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21795 tree V1DI_type_node
21796 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21797 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21798 tree V2DI_type_node
21799 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21800 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21801 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21802 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21803 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21804 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21805 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21807 tree pchar_type_node = build_pointer_type (char_type_node);
21808 tree pcchar_type_node
21809 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21810 tree pfloat_type_node = build_pointer_type (float_type_node);
21811 tree pcfloat_type_node
21812 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21813 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21814 tree pcv2sf_type_node
21815 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21816 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21817 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21820 tree int_ftype_v4sf_v4sf
21821 = build_function_type_list (integer_type_node,
21822 V4SF_type_node, V4SF_type_node, NULL_TREE);
21823 tree v4si_ftype_v4sf_v4sf
21824 = build_function_type_list (V4SI_type_node,
21825 V4SF_type_node, V4SF_type_node, NULL_TREE);
21826 /* MMX/SSE/integer conversions. */
21827 tree int_ftype_v4sf
21828 = build_function_type_list (integer_type_node,
21829 V4SF_type_node, NULL_TREE);
21830 tree int64_ftype_v4sf
21831 = build_function_type_list (long_long_integer_type_node,
21832 V4SF_type_node, NULL_TREE);
21833 tree int_ftype_v8qi
21834 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21835 tree v4sf_ftype_v4sf_int
21836 = build_function_type_list (V4SF_type_node,
21837 V4SF_type_node, integer_type_node, NULL_TREE);
21838 tree v4sf_ftype_v4sf_int64
21839 = build_function_type_list (V4SF_type_node,
21840 V4SF_type_node, long_long_integer_type_node,
21842 tree v4sf_ftype_v4sf_v2si
21843 = build_function_type_list (V4SF_type_node,
21844 V4SF_type_node, V2SI_type_node, NULL_TREE);
21846 /* Miscellaneous. */
21847 tree v8qi_ftype_v4hi_v4hi
21848 = build_function_type_list (V8QI_type_node,
21849 V4HI_type_node, V4HI_type_node, NULL_TREE);
21850 tree v4hi_ftype_v2si_v2si
21851 = build_function_type_list (V4HI_type_node,
21852 V2SI_type_node, V2SI_type_node, NULL_TREE);
21853 tree v4sf_ftype_v4sf_v4sf_int
21854 = build_function_type_list (V4SF_type_node,
21855 V4SF_type_node, V4SF_type_node,
21856 integer_type_node, NULL_TREE);
21857 tree v2si_ftype_v4hi_v4hi
21858 = build_function_type_list (V2SI_type_node,
21859 V4HI_type_node, V4HI_type_node, NULL_TREE);
21860 tree v4hi_ftype_v4hi_int
21861 = build_function_type_list (V4HI_type_node,
21862 V4HI_type_node, integer_type_node, NULL_TREE);
21863 tree v2si_ftype_v2si_int
21864 = build_function_type_list (V2SI_type_node,
21865 V2SI_type_node, integer_type_node, NULL_TREE);
21866 tree v1di_ftype_v1di_int
21867 = build_function_type_list (V1DI_type_node,
21868 V1DI_type_node, integer_type_node, NULL_TREE);
21870 tree void_ftype_void
21871 = build_function_type (void_type_node, void_list_node);
21872 tree void_ftype_unsigned
21873 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21874 tree void_ftype_unsigned_unsigned
21875 = build_function_type_list (void_type_node, unsigned_type_node,
21876 unsigned_type_node, NULL_TREE);
21877 tree void_ftype_pcvoid_unsigned_unsigned
21878 = build_function_type_list (void_type_node, const_ptr_type_node,
21879 unsigned_type_node, unsigned_type_node,
21881 tree unsigned_ftype_void
21882 = build_function_type (unsigned_type_node, void_list_node);
21883 tree v2si_ftype_v4sf
21884 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21885 /* Loads/stores. */
21886 tree void_ftype_v8qi_v8qi_pchar
21887 = build_function_type_list (void_type_node,
21888 V8QI_type_node, V8QI_type_node,
21889 pchar_type_node, NULL_TREE);
21890 tree v4sf_ftype_pcfloat
21891 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21892 tree v4sf_ftype_v4sf_pcv2sf
21893 = build_function_type_list (V4SF_type_node,
21894 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21895 tree void_ftype_pv2sf_v4sf
21896 = build_function_type_list (void_type_node,
21897 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21898 tree void_ftype_pfloat_v4sf
21899 = build_function_type_list (void_type_node,
21900 pfloat_type_node, V4SF_type_node, NULL_TREE);
21901 tree void_ftype_pdi_di
21902 = build_function_type_list (void_type_node,
21903 pdi_type_node, long_long_unsigned_type_node,
21905 tree void_ftype_pv2di_v2di
21906 = build_function_type_list (void_type_node,
21907 pv2di_type_node, V2DI_type_node, NULL_TREE);
21908 /* Normal vector unops. */
21909 tree v4sf_ftype_v4sf
21910 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21911 tree v16qi_ftype_v16qi
21912 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21913 tree v8hi_ftype_v8hi
21914 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21915 tree v4si_ftype_v4si
21916 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21917 tree v8qi_ftype_v8qi
21918 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21919 tree v4hi_ftype_v4hi
21920 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21922 /* Normal vector binops. */
21923 tree v4sf_ftype_v4sf_v4sf
21924 = build_function_type_list (V4SF_type_node,
21925 V4SF_type_node, V4SF_type_node, NULL_TREE);
21926 tree v8qi_ftype_v8qi_v8qi
21927 = build_function_type_list (V8QI_type_node,
21928 V8QI_type_node, V8QI_type_node, NULL_TREE);
21929 tree v4hi_ftype_v4hi_v4hi
21930 = build_function_type_list (V4HI_type_node,
21931 V4HI_type_node, V4HI_type_node, NULL_TREE);
21932 tree v2si_ftype_v2si_v2si
21933 = build_function_type_list (V2SI_type_node,
21934 V2SI_type_node, V2SI_type_node, NULL_TREE);
21935 tree v1di_ftype_v1di_v1di
21936 = build_function_type_list (V1DI_type_node,
21937 V1DI_type_node, V1DI_type_node, NULL_TREE);
21938 tree v1di_ftype_v1di_v1di_int
21939 = build_function_type_list (V1DI_type_node,
21940 V1DI_type_node, V1DI_type_node,
21941 integer_type_node, NULL_TREE);
21942 tree v2si_ftype_v2sf
21943 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21944 tree v2sf_ftype_v2si
21945 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21946 tree v2si_ftype_v2si
21947 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21948 tree v2sf_ftype_v2sf
21949 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21950 tree v2sf_ftype_v2sf_v2sf
21951 = build_function_type_list (V2SF_type_node,
21952 V2SF_type_node, V2SF_type_node, NULL_TREE);
21953 tree v2si_ftype_v2sf_v2sf
21954 = build_function_type_list (V2SI_type_node,
21955 V2SF_type_node, V2SF_type_node, NULL_TREE);
21956 tree pint_type_node = build_pointer_type (integer_type_node);
21957 tree pdouble_type_node = build_pointer_type (double_type_node);
21958 tree pcdouble_type_node = build_pointer_type (
21959 build_type_variant (double_type_node, 1, 0));
21960 tree int_ftype_v2df_v2df
21961 = build_function_type_list (integer_type_node,
21962 V2DF_type_node, V2DF_type_node, NULL_TREE);
21964 tree void_ftype_pcvoid
21965 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21966 tree v4sf_ftype_v4si
21967 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21968 tree v4si_ftype_v4sf
21969 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21970 tree v2df_ftype_v4si
21971 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21972 tree v4si_ftype_v2df
21973 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21974 tree v4si_ftype_v2df_v2df
21975 = build_function_type_list (V4SI_type_node,
21976 V2DF_type_node, V2DF_type_node, NULL_TREE);
21977 tree v2si_ftype_v2df
21978 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21979 tree v4sf_ftype_v2df
21980 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21981 tree v2df_ftype_v2si
21982 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21983 tree v2df_ftype_v4sf
21984 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21985 tree int_ftype_v2df
21986 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21987 tree int64_ftype_v2df
21988 = build_function_type_list (long_long_integer_type_node,
21989 V2DF_type_node, NULL_TREE);
21990 tree v2df_ftype_v2df_int
21991 = build_function_type_list (V2DF_type_node,
21992 V2DF_type_node, integer_type_node, NULL_TREE);
21993 tree v2df_ftype_v2df_int64
21994 = build_function_type_list (V2DF_type_node,
21995 V2DF_type_node, long_long_integer_type_node,
21997 tree v4sf_ftype_v4sf_v2df
21998 = build_function_type_list (V4SF_type_node,
21999 V4SF_type_node, V2DF_type_node, NULL_TREE);
22000 tree v2df_ftype_v2df_v4sf
22001 = build_function_type_list (V2DF_type_node,
22002 V2DF_type_node, V4SF_type_node, NULL_TREE);
22003 tree v2df_ftype_v2df_v2df_int
22004 = build_function_type_list (V2DF_type_node,
22005 V2DF_type_node, V2DF_type_node,
22008 tree v2df_ftype_v2df_pcdouble
22009 = build_function_type_list (V2DF_type_node,
22010 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22011 tree void_ftype_pdouble_v2df
22012 = build_function_type_list (void_type_node,
22013 pdouble_type_node, V2DF_type_node, NULL_TREE);
22014 tree void_ftype_pint_int
22015 = build_function_type_list (void_type_node,
22016 pint_type_node, integer_type_node, NULL_TREE);
22017 tree void_ftype_v16qi_v16qi_pchar
22018 = build_function_type_list (void_type_node,
22019 V16QI_type_node, V16QI_type_node,
22020 pchar_type_node, NULL_TREE);
22021 tree v2df_ftype_pcdouble
22022 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22023 tree v2df_ftype_v2df_v2df
22024 = build_function_type_list (V2DF_type_node,
22025 V2DF_type_node, V2DF_type_node, NULL_TREE);
22026 tree v16qi_ftype_v16qi_v16qi
22027 = build_function_type_list (V16QI_type_node,
22028 V16QI_type_node, V16QI_type_node, NULL_TREE);
22029 tree v8hi_ftype_v8hi_v8hi
22030 = build_function_type_list (V8HI_type_node,
22031 V8HI_type_node, V8HI_type_node, NULL_TREE);
22032 tree v4si_ftype_v4si_v4si
22033 = build_function_type_list (V4SI_type_node,
22034 V4SI_type_node, V4SI_type_node, NULL_TREE);
22035 tree v2di_ftype_v2di_v2di
22036 = build_function_type_list (V2DI_type_node,
22037 V2DI_type_node, V2DI_type_node, NULL_TREE);
22038 tree v2di_ftype_v2df_v2df
22039 = build_function_type_list (V2DI_type_node,
22040 V2DF_type_node, V2DF_type_node, NULL_TREE);
22041 tree v2df_ftype_v2df
22042 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22043 tree v2di_ftype_v2di_int
22044 = build_function_type_list (V2DI_type_node,
22045 V2DI_type_node, integer_type_node, NULL_TREE);
22046 tree v2di_ftype_v2di_v2di_int
22047 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22048 V2DI_type_node, integer_type_node, NULL_TREE);
22049 tree v4si_ftype_v4si_int
22050 = build_function_type_list (V4SI_type_node,
22051 V4SI_type_node, integer_type_node, NULL_TREE);
22052 tree v8hi_ftype_v8hi_int
22053 = build_function_type_list (V8HI_type_node,
22054 V8HI_type_node, integer_type_node, NULL_TREE);
22055 tree v4si_ftype_v8hi_v8hi
22056 = build_function_type_list (V4SI_type_node,
22057 V8HI_type_node, V8HI_type_node, NULL_TREE);
22058 tree v1di_ftype_v8qi_v8qi
22059 = build_function_type_list (V1DI_type_node,
22060 V8QI_type_node, V8QI_type_node, NULL_TREE);
22061 tree v1di_ftype_v2si_v2si
22062 = build_function_type_list (V1DI_type_node,
22063 V2SI_type_node, V2SI_type_node, NULL_TREE);
22064 tree v2di_ftype_v16qi_v16qi
22065 = build_function_type_list (V2DI_type_node,
22066 V16QI_type_node, V16QI_type_node, NULL_TREE);
22067 tree v2di_ftype_v4si_v4si
22068 = build_function_type_list (V2DI_type_node,
22069 V4SI_type_node, V4SI_type_node, NULL_TREE);
22070 tree int_ftype_v16qi
22071 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22072 tree v16qi_ftype_pcchar
22073 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22074 tree void_ftype_pchar_v16qi
22075 = build_function_type_list (void_type_node,
22076 pchar_type_node, V16QI_type_node, NULL_TREE);
22078 tree v2di_ftype_v2di_unsigned_unsigned
22079 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22080 unsigned_type_node, unsigned_type_node,
22082 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22083 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22084 unsigned_type_node, unsigned_type_node,
22086 tree v2di_ftype_v2di_v16qi
22087 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22089 tree v2df_ftype_v2df_v2df_v2df
22090 = build_function_type_list (V2DF_type_node,
22091 V2DF_type_node, V2DF_type_node,
22092 V2DF_type_node, NULL_TREE);
22093 tree v4sf_ftype_v4sf_v4sf_v4sf
22094 = build_function_type_list (V4SF_type_node,
22095 V4SF_type_node, V4SF_type_node,
22096 V4SF_type_node, NULL_TREE);
22097 tree v8hi_ftype_v16qi
22098 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22100 tree v4si_ftype_v16qi
22101 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22103 tree v2di_ftype_v16qi
22104 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22106 tree v4si_ftype_v8hi
22107 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22109 tree v2di_ftype_v8hi
22110 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22112 tree v2di_ftype_v4si
22113 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22115 tree v2di_ftype_pv2di
22116 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22118 tree v16qi_ftype_v16qi_v16qi_int
22119 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22120 V16QI_type_node, integer_type_node,
22122 tree v16qi_ftype_v16qi_v16qi_v16qi
22123 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22124 V16QI_type_node, V16QI_type_node,
22126 tree v8hi_ftype_v8hi_v8hi_int
22127 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22128 V8HI_type_node, integer_type_node,
22130 tree v4si_ftype_v4si_v4si_int
22131 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22132 V4SI_type_node, integer_type_node,
22134 tree int_ftype_v2di_v2di
22135 = build_function_type_list (integer_type_node,
22136 V2DI_type_node, V2DI_type_node,
22138 tree int_ftype_v16qi_int_v16qi_int_int
22139 = build_function_type_list (integer_type_node,
22146 tree v16qi_ftype_v16qi_int_v16qi_int_int
22147 = build_function_type_list (V16QI_type_node,
22154 tree int_ftype_v16qi_v16qi_int
22155 = build_function_type_list (integer_type_node,
22161 /* SSE5 instructions */
22162 tree v2di_ftype_v2di_v2di_v2di
22163 = build_function_type_list (V2DI_type_node,
22169 tree v4si_ftype_v4si_v4si_v4si
22170 = build_function_type_list (V4SI_type_node,
22176 tree v4si_ftype_v4si_v4si_v2di
22177 = build_function_type_list (V4SI_type_node,
22183 tree v8hi_ftype_v8hi_v8hi_v8hi
22184 = build_function_type_list (V8HI_type_node,
22190 tree v8hi_ftype_v8hi_v8hi_v4si
22191 = build_function_type_list (V8HI_type_node,
22197 tree v2df_ftype_v2df_v2df_v16qi
22198 = build_function_type_list (V2DF_type_node,
22204 tree v4sf_ftype_v4sf_v4sf_v16qi
22205 = build_function_type_list (V4SF_type_node,
22211 tree v2di_ftype_v2di_si
22212 = build_function_type_list (V2DI_type_node,
22217 tree v4si_ftype_v4si_si
22218 = build_function_type_list (V4SI_type_node,
22223 tree v8hi_ftype_v8hi_si
22224 = build_function_type_list (V8HI_type_node,
22229 tree v16qi_ftype_v16qi_si
22230 = build_function_type_list (V16QI_type_node,
22234 tree v4sf_ftype_v4hi
22235 = build_function_type_list (V4SF_type_node,
22239 tree v4hi_ftype_v4sf
22240 = build_function_type_list (V4HI_type_node,
22244 tree v2di_ftype_v2di
22245 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22247 tree v16qi_ftype_v8hi_v8hi
22248 = build_function_type_list (V16QI_type_node,
22249 V8HI_type_node, V8HI_type_node,
22251 tree v8hi_ftype_v4si_v4si
22252 = build_function_type_list (V8HI_type_node,
22253 V4SI_type_node, V4SI_type_node,
22255 tree v8hi_ftype_v16qi_v16qi
22256 = build_function_type_list (V8HI_type_node,
22257 V16QI_type_node, V16QI_type_node,
22259 tree v4hi_ftype_v8qi_v8qi
22260 = build_function_type_list (V4HI_type_node,
22261 V8QI_type_node, V8QI_type_node,
22263 tree unsigned_ftype_unsigned_uchar
22264 = build_function_type_list (unsigned_type_node,
22265 unsigned_type_node,
22266 unsigned_char_type_node,
22268 tree unsigned_ftype_unsigned_ushort
22269 = build_function_type_list (unsigned_type_node,
22270 unsigned_type_node,
22271 short_unsigned_type_node,
22273 tree unsigned_ftype_unsigned_unsigned
22274 = build_function_type_list (unsigned_type_node,
22275 unsigned_type_node,
22276 unsigned_type_node,
22278 tree uint64_ftype_uint64_uint64
22279 = build_function_type_list (long_long_unsigned_type_node,
22280 long_long_unsigned_type_node,
22281 long_long_unsigned_type_node,
22283 tree float_ftype_float
22284 = build_function_type_list (float_type_node,
22289 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22291 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22293 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22295 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22297 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22299 tree v8sf_ftype_v8sf
22300 = build_function_type_list (V8SF_type_node,
22303 tree v8si_ftype_v8sf
22304 = build_function_type_list (V8SI_type_node,
22307 tree v8sf_ftype_v8si
22308 = build_function_type_list (V8SF_type_node,
22311 tree v4si_ftype_v4df
22312 = build_function_type_list (V4SI_type_node,
22315 tree v4df_ftype_v4df
22316 = build_function_type_list (V4DF_type_node,
22319 tree v4df_ftype_v4si
22320 = build_function_type_list (V4DF_type_node,
22323 tree v4df_ftype_v4sf
22324 = build_function_type_list (V4DF_type_node,
22327 tree v4sf_ftype_v4df
22328 = build_function_type_list (V4SF_type_node,
22331 tree v8sf_ftype_v8sf_v8sf
22332 = build_function_type_list (V8SF_type_node,
22333 V8SF_type_node, V8SF_type_node,
22335 tree v4df_ftype_v4df_v4df
22336 = build_function_type_list (V4DF_type_node,
22337 V4DF_type_node, V4DF_type_node,
22339 tree v8sf_ftype_v8sf_int
22340 = build_function_type_list (V8SF_type_node,
22341 V8SF_type_node, integer_type_node,
22343 tree v4si_ftype_v8si_int
22344 = build_function_type_list (V4SI_type_node,
22345 V8SI_type_node, integer_type_node,
22347 tree v4df_ftype_v4df_int
22348 = build_function_type_list (V4DF_type_node,
22349 V4DF_type_node, integer_type_node,
22351 tree v4sf_ftype_v8sf_int
22352 = build_function_type_list (V4SF_type_node,
22353 V8SF_type_node, integer_type_node,
22355 tree v2df_ftype_v4df_int
22356 = build_function_type_list (V2DF_type_node,
22357 V4DF_type_node, integer_type_node,
22359 tree v8sf_ftype_v8sf_v8sf_int
22360 = build_function_type_list (V8SF_type_node,
22361 V8SF_type_node, V8SF_type_node,
22364 tree v8sf_ftype_v8sf_v8sf_v8sf
22365 = build_function_type_list (V8SF_type_node,
22366 V8SF_type_node, V8SF_type_node,
22369 tree v4df_ftype_v4df_v4df_v4df
22370 = build_function_type_list (V4DF_type_node,
22371 V4DF_type_node, V4DF_type_node,
22374 tree v8si_ftype_v8si_v8si_int
22375 = build_function_type_list (V8SI_type_node,
22376 V8SI_type_node, V8SI_type_node,
22379 tree v4df_ftype_v4df_v4df_int
22380 = build_function_type_list (V4DF_type_node,
22381 V4DF_type_node, V4DF_type_node,
22384 tree v8sf_ftype_pcfloat
22385 = build_function_type_list (V8SF_type_node,
22388 tree v4df_ftype_pcdouble
22389 = build_function_type_list (V4DF_type_node,
22390 pcdouble_type_node,
22392 tree pcv4sf_type_node
22393 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22394 tree pcv2df_type_node
22395 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22396 tree v8sf_ftype_pcv4sf
22397 = build_function_type_list (V8SF_type_node,
22400 tree v4df_ftype_pcv2df
22401 = build_function_type_list (V4DF_type_node,
22404 tree v32qi_ftype_pcchar
22405 = build_function_type_list (V32QI_type_node,
22408 tree void_ftype_pchar_v32qi
22409 = build_function_type_list (void_type_node,
22410 pchar_type_node, V32QI_type_node,
22412 tree v8si_ftype_v8si_v4si_int
22413 = build_function_type_list (V8SI_type_node,
22414 V8SI_type_node, V4SI_type_node,
22417 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22418 tree void_ftype_pv4di_v4di
22419 = build_function_type_list (void_type_node,
22420 pv4di_type_node, V4DI_type_node,
22422 tree v8sf_ftype_v8sf_v4sf_int
22423 = build_function_type_list (V8SF_type_node,
22424 V8SF_type_node, V4SF_type_node,
22427 tree v4df_ftype_v4df_v2df_int
22428 = build_function_type_list (V4DF_type_node,
22429 V4DF_type_node, V2DF_type_node,
22432 tree void_ftype_pfloat_v8sf
22433 = build_function_type_list (void_type_node,
22434 pfloat_type_node, V8SF_type_node,
22436 tree void_ftype_pdouble_v4df
22437 = build_function_type_list (void_type_node,
22438 pdouble_type_node, V4DF_type_node,
22440 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22441 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22442 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22443 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22444 tree pcv8sf_type_node
22445 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22446 tree pcv4df_type_node
22447 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22448 tree v8sf_ftype_pcv8sf_v8sf
22449 = build_function_type_list (V8SF_type_node,
22450 pcv8sf_type_node, V8SF_type_node,
22452 tree v4df_ftype_pcv4df_v4df
22453 = build_function_type_list (V4DF_type_node,
22454 pcv4df_type_node, V4DF_type_node,
22456 tree v4sf_ftype_pcv4sf_v4sf
22457 = build_function_type_list (V4SF_type_node,
22458 pcv4sf_type_node, V4SF_type_node,
22460 tree v2df_ftype_pcv2df_v2df
22461 = build_function_type_list (V2DF_type_node,
22462 pcv2df_type_node, V2DF_type_node,
22464 tree void_ftype_pv8sf_v8sf_v8sf
22465 = build_function_type_list (void_type_node,
22466 pv8sf_type_node, V8SF_type_node,
22469 tree void_ftype_pv4df_v4df_v4df
22470 = build_function_type_list (void_type_node,
22471 pv4df_type_node, V4DF_type_node,
22474 tree void_ftype_pv4sf_v4sf_v4sf
22475 = build_function_type_list (void_type_node,
22476 pv4sf_type_node, V4SF_type_node,
22479 tree void_ftype_pv2df_v2df_v2df
22480 = build_function_type_list (void_type_node,
22481 pv2df_type_node, V2DF_type_node,
22484 tree v4df_ftype_v2df
22485 = build_function_type_list (V4DF_type_node,
22488 tree v8sf_ftype_v4sf
22489 = build_function_type_list (V8SF_type_node,
22492 tree v8si_ftype_v4si
22493 = build_function_type_list (V8SI_type_node,
22496 tree v2df_ftype_v4df
22497 = build_function_type_list (V2DF_type_node,
22500 tree v4sf_ftype_v8sf
22501 = build_function_type_list (V4SF_type_node,
22504 tree v4si_ftype_v8si
22505 = build_function_type_list (V4SI_type_node,
22508 tree int_ftype_v4df
22509 = build_function_type_list (integer_type_node,
22512 tree int_ftype_v8sf
22513 = build_function_type_list (integer_type_node,
22516 tree int_ftype_v8sf_v8sf
22517 = build_function_type_list (integer_type_node,
22518 V8SF_type_node, V8SF_type_node,
22520 tree int_ftype_v4di_v4di
22521 = build_function_type_list (integer_type_node,
22522 V4DI_type_node, V4DI_type_node,
22524 tree int_ftype_v4df_v4df
22525 = build_function_type_list (integer_type_node,
22526 V4DF_type_node, V4DF_type_node,
22528 tree v8sf_ftype_v8sf_v8si
22529 = build_function_type_list (V8SF_type_node,
22530 V8SF_type_node, V8SI_type_node,
22532 tree v4df_ftype_v4df_v4di
22533 = build_function_type_list (V4DF_type_node,
22534 V4DF_type_node, V4DI_type_node,
22536 tree v4sf_ftype_v4sf_v4si
22537 = build_function_type_list (V4SF_type_node,
22538 V4SF_type_node, V4SI_type_node, NULL_TREE);
22539 tree v2df_ftype_v2df_v2di
22540 = build_function_type_list (V2DF_type_node,
22541 V2DF_type_node, V2DI_type_node, NULL_TREE);
22545 /* Add all special builtins with variable number of operands. */
22546 for (i = 0, d = bdesc_special_args;
22547 i < ARRAY_SIZE (bdesc_special_args);
22555 switch ((enum ix86_special_builtin_type) d->flag)
22557 case VOID_FTYPE_VOID:
22558 type = void_ftype_void;
22560 case V32QI_FTYPE_PCCHAR:
22561 type = v32qi_ftype_pcchar;
22563 case V16QI_FTYPE_PCCHAR:
22564 type = v16qi_ftype_pcchar;
22566 case V8SF_FTYPE_PCV4SF:
22567 type = v8sf_ftype_pcv4sf;
22569 case V8SF_FTYPE_PCFLOAT:
22570 type = v8sf_ftype_pcfloat;
22572 case V4DF_FTYPE_PCV2DF:
22573 type = v4df_ftype_pcv2df;
22575 case V4DF_FTYPE_PCDOUBLE:
22576 type = v4df_ftype_pcdouble;
22578 case V4SF_FTYPE_PCFLOAT:
22579 type = v4sf_ftype_pcfloat;
22581 case V2DI_FTYPE_PV2DI:
22582 type = v2di_ftype_pv2di;
22584 case V2DF_FTYPE_PCDOUBLE:
22585 type = v2df_ftype_pcdouble;
22587 case V8SF_FTYPE_PCV8SF_V8SF:
22588 type = v8sf_ftype_pcv8sf_v8sf;
22590 case V4DF_FTYPE_PCV4DF_V4DF:
22591 type = v4df_ftype_pcv4df_v4df;
22593 case V4SF_FTYPE_V4SF_PCV2SF:
22594 type = v4sf_ftype_v4sf_pcv2sf;
22596 case V4SF_FTYPE_PCV4SF_V4SF:
22597 type = v4sf_ftype_pcv4sf_v4sf;
22599 case V2DF_FTYPE_V2DF_PCDOUBLE:
22600 type = v2df_ftype_v2df_pcdouble;
22602 case V2DF_FTYPE_PCV2DF_V2DF:
22603 type = v2df_ftype_pcv2df_v2df;
22605 case VOID_FTYPE_PV2SF_V4SF:
22606 type = void_ftype_pv2sf_v4sf;
22608 case VOID_FTYPE_PV4DI_V4DI:
22609 type = void_ftype_pv4di_v4di;
22611 case VOID_FTYPE_PV2DI_V2DI:
22612 type = void_ftype_pv2di_v2di;
22614 case VOID_FTYPE_PCHAR_V32QI:
22615 type = void_ftype_pchar_v32qi;
22617 case VOID_FTYPE_PCHAR_V16QI:
22618 type = void_ftype_pchar_v16qi;
22620 case VOID_FTYPE_PFLOAT_V8SF:
22621 type = void_ftype_pfloat_v8sf;
22623 case VOID_FTYPE_PFLOAT_V4SF:
22624 type = void_ftype_pfloat_v4sf;
22626 case VOID_FTYPE_PDOUBLE_V4DF:
22627 type = void_ftype_pdouble_v4df;
22629 case VOID_FTYPE_PDOUBLE_V2DF:
22630 type = void_ftype_pdouble_v2df;
22632 case VOID_FTYPE_PDI_DI:
22633 type = void_ftype_pdi_di;
22635 case VOID_FTYPE_PINT_INT:
22636 type = void_ftype_pint_int;
22638 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22639 type = void_ftype_pv8sf_v8sf_v8sf;
22641 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22642 type = void_ftype_pv4df_v4df_v4df;
22644 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22645 type = void_ftype_pv4sf_v4sf_v4sf;
22647 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22648 type = void_ftype_pv2df_v2df_v2df;
22651 gcc_unreachable ();
22654 def_builtin (d->mask, d->name, type, d->code);
22657 /* Add all builtins with variable number of operands. */
22658 for (i = 0, d = bdesc_args;
22659 i < ARRAY_SIZE (bdesc_args);
22667 switch ((enum ix86_builtin_type) d->flag)
22669 case FLOAT_FTYPE_FLOAT:
22670 type = float_ftype_float;
22672 case INT_FTYPE_V8SF_V8SF_PTEST:
22673 type = int_ftype_v8sf_v8sf;
22675 case INT_FTYPE_V4DI_V4DI_PTEST:
22676 type = int_ftype_v4di_v4di;
22678 case INT_FTYPE_V4DF_V4DF_PTEST:
22679 type = int_ftype_v4df_v4df;
22681 case INT_FTYPE_V4SF_V4SF_PTEST:
22682 type = int_ftype_v4sf_v4sf;
22684 case INT_FTYPE_V2DI_V2DI_PTEST:
22685 type = int_ftype_v2di_v2di;
22687 case INT_FTYPE_V2DF_V2DF_PTEST:
22688 type = int_ftype_v2df_v2df;
22690 case INT64_FTYPE_V4SF:
22691 type = int64_ftype_v4sf;
22693 case INT64_FTYPE_V2DF:
22694 type = int64_ftype_v2df;
22696 case INT_FTYPE_V16QI:
22697 type = int_ftype_v16qi;
22699 case INT_FTYPE_V8QI:
22700 type = int_ftype_v8qi;
22702 case INT_FTYPE_V8SF:
22703 type = int_ftype_v8sf;
22705 case INT_FTYPE_V4DF:
22706 type = int_ftype_v4df;
22708 case INT_FTYPE_V4SF:
22709 type = int_ftype_v4sf;
22711 case INT_FTYPE_V2DF:
22712 type = int_ftype_v2df;
22714 case V16QI_FTYPE_V16QI:
22715 type = v16qi_ftype_v16qi;
22717 case V8SI_FTYPE_V8SF:
22718 type = v8si_ftype_v8sf;
22720 case V8SI_FTYPE_V4SI:
22721 type = v8si_ftype_v4si;
22723 case V8HI_FTYPE_V8HI:
22724 type = v8hi_ftype_v8hi;
22726 case V8HI_FTYPE_V16QI:
22727 type = v8hi_ftype_v16qi;
22729 case V8QI_FTYPE_V8QI:
22730 type = v8qi_ftype_v8qi;
22732 case V8SF_FTYPE_V8SF:
22733 type = v8sf_ftype_v8sf;
22735 case V8SF_FTYPE_V8SI:
22736 type = v8sf_ftype_v8si;
22738 case V8SF_FTYPE_V4SF:
22739 type = v8sf_ftype_v4sf;
22741 case V4SI_FTYPE_V4DF:
22742 type = v4si_ftype_v4df;
22744 case V4SI_FTYPE_V4SI:
22745 type = v4si_ftype_v4si;
22747 case V4SI_FTYPE_V16QI:
22748 type = v4si_ftype_v16qi;
22750 case V4SI_FTYPE_V8SI:
22751 type = v4si_ftype_v8si;
22753 case V4SI_FTYPE_V8HI:
22754 type = v4si_ftype_v8hi;
22756 case V4SI_FTYPE_V4SF:
22757 type = v4si_ftype_v4sf;
22759 case V4SI_FTYPE_V2DF:
22760 type = v4si_ftype_v2df;
22762 case V4HI_FTYPE_V4HI:
22763 type = v4hi_ftype_v4hi;
22765 case V4DF_FTYPE_V4DF:
22766 type = v4df_ftype_v4df;
22768 case V4DF_FTYPE_V4SI:
22769 type = v4df_ftype_v4si;
22771 case V4DF_FTYPE_V4SF:
22772 type = v4df_ftype_v4sf;
22774 case V4DF_FTYPE_V2DF:
22775 type = v4df_ftype_v2df;
22777 case V4SF_FTYPE_V4SF:
22778 case V4SF_FTYPE_V4SF_VEC_MERGE:
22779 type = v4sf_ftype_v4sf;
22781 case V4SF_FTYPE_V8SF:
22782 type = v4sf_ftype_v8sf;
22784 case V4SF_FTYPE_V4SI:
22785 type = v4sf_ftype_v4si;
22787 case V4SF_FTYPE_V4DF:
22788 type = v4sf_ftype_v4df;
22790 case V4SF_FTYPE_V2DF:
22791 type = v4sf_ftype_v2df;
22793 case V2DI_FTYPE_V2DI:
22794 type = v2di_ftype_v2di;
22796 case V2DI_FTYPE_V16QI:
22797 type = v2di_ftype_v16qi;
22799 case V2DI_FTYPE_V8HI:
22800 type = v2di_ftype_v8hi;
22802 case V2DI_FTYPE_V4SI:
22803 type = v2di_ftype_v4si;
22805 case V2SI_FTYPE_V2SI:
22806 type = v2si_ftype_v2si;
22808 case V2SI_FTYPE_V4SF:
22809 type = v2si_ftype_v4sf;
22811 case V2SI_FTYPE_V2DF:
22812 type = v2si_ftype_v2df;
22814 case V2SI_FTYPE_V2SF:
22815 type = v2si_ftype_v2sf;
22817 case V2DF_FTYPE_V4DF:
22818 type = v2df_ftype_v4df;
22820 case V2DF_FTYPE_V4SF:
22821 type = v2df_ftype_v4sf;
22823 case V2DF_FTYPE_V2DF:
22824 case V2DF_FTYPE_V2DF_VEC_MERGE:
22825 type = v2df_ftype_v2df;
22827 case V2DF_FTYPE_V2SI:
22828 type = v2df_ftype_v2si;
22830 case V2DF_FTYPE_V4SI:
22831 type = v2df_ftype_v4si;
22833 case V2SF_FTYPE_V2SF:
22834 type = v2sf_ftype_v2sf;
22836 case V2SF_FTYPE_V2SI:
22837 type = v2sf_ftype_v2si;
22839 case V16QI_FTYPE_V16QI_V16QI:
22840 type = v16qi_ftype_v16qi_v16qi;
22842 case V16QI_FTYPE_V8HI_V8HI:
22843 type = v16qi_ftype_v8hi_v8hi;
22845 case V8QI_FTYPE_V8QI_V8QI:
22846 type = v8qi_ftype_v8qi_v8qi;
22848 case V8QI_FTYPE_V4HI_V4HI:
22849 type = v8qi_ftype_v4hi_v4hi;
22851 case V8HI_FTYPE_V8HI_V8HI:
22852 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22853 type = v8hi_ftype_v8hi_v8hi;
22855 case V8HI_FTYPE_V16QI_V16QI:
22856 type = v8hi_ftype_v16qi_v16qi;
22858 case V8HI_FTYPE_V4SI_V4SI:
22859 type = v8hi_ftype_v4si_v4si;
22861 case V8HI_FTYPE_V8HI_SI_COUNT:
22862 type = v8hi_ftype_v8hi_int;
22864 case V8SF_FTYPE_V8SF_V8SF:
22865 type = v8sf_ftype_v8sf_v8sf;
22867 case V8SF_FTYPE_V8SF_V8SI:
22868 type = v8sf_ftype_v8sf_v8si;
22870 case V4SI_FTYPE_V4SI_V4SI:
22871 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22872 type = v4si_ftype_v4si_v4si;
22874 case V4SI_FTYPE_V8HI_V8HI:
22875 type = v4si_ftype_v8hi_v8hi;
22877 case V4SI_FTYPE_V4SF_V4SF:
22878 type = v4si_ftype_v4sf_v4sf;
22880 case V4SI_FTYPE_V2DF_V2DF:
22881 type = v4si_ftype_v2df_v2df;
22883 case V4SI_FTYPE_V4SI_SI_COUNT:
22884 type = v4si_ftype_v4si_int;
22886 case V4HI_FTYPE_V4HI_V4HI:
22887 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22888 type = v4hi_ftype_v4hi_v4hi;
22890 case V4HI_FTYPE_V8QI_V8QI:
22891 type = v4hi_ftype_v8qi_v8qi;
22893 case V4HI_FTYPE_V2SI_V2SI:
22894 type = v4hi_ftype_v2si_v2si;
22896 case V4HI_FTYPE_V4HI_SI_COUNT:
22897 type = v4hi_ftype_v4hi_int;
22899 case V4DF_FTYPE_V4DF_V4DF:
22900 type = v4df_ftype_v4df_v4df;
22902 case V4DF_FTYPE_V4DF_V4DI:
22903 type = v4df_ftype_v4df_v4di;
22905 case V4SF_FTYPE_V4SF_V4SF:
22906 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22907 type = v4sf_ftype_v4sf_v4sf;
22909 case V4SF_FTYPE_V4SF_V4SI:
22910 type = v4sf_ftype_v4sf_v4si;
22912 case V4SF_FTYPE_V4SF_V2SI:
22913 type = v4sf_ftype_v4sf_v2si;
22915 case V4SF_FTYPE_V4SF_V2DF:
22916 type = v4sf_ftype_v4sf_v2df;
22918 case V4SF_FTYPE_V4SF_DI:
22919 type = v4sf_ftype_v4sf_int64;
22921 case V4SF_FTYPE_V4SF_SI:
22922 type = v4sf_ftype_v4sf_int;
22924 case V2DI_FTYPE_V2DI_V2DI:
22925 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22926 type = v2di_ftype_v2di_v2di;
22928 case V2DI_FTYPE_V16QI_V16QI:
22929 type = v2di_ftype_v16qi_v16qi;
22931 case V2DI_FTYPE_V4SI_V4SI:
22932 type = v2di_ftype_v4si_v4si;
22934 case V2DI_FTYPE_V2DI_V16QI:
22935 type = v2di_ftype_v2di_v16qi;
22937 case V2DI_FTYPE_V2DF_V2DF:
22938 type = v2di_ftype_v2df_v2df;
22940 case V2DI_FTYPE_V2DI_SI_COUNT:
22941 type = v2di_ftype_v2di_int;
22943 case V2SI_FTYPE_V2SI_V2SI:
22944 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22945 type = v2si_ftype_v2si_v2si;
22947 case V2SI_FTYPE_V4HI_V4HI:
22948 type = v2si_ftype_v4hi_v4hi;
22950 case V2SI_FTYPE_V2SF_V2SF:
22951 type = v2si_ftype_v2sf_v2sf;
22953 case V2SI_FTYPE_V2SI_SI_COUNT:
22954 type = v2si_ftype_v2si_int;
22956 case V2DF_FTYPE_V2DF_V2DF:
22957 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22958 type = v2df_ftype_v2df_v2df;
22960 case V2DF_FTYPE_V2DF_V4SF:
22961 type = v2df_ftype_v2df_v4sf;
22963 case V2DF_FTYPE_V2DF_V2DI:
22964 type = v2df_ftype_v2df_v2di;
22966 case V2DF_FTYPE_V2DF_DI:
22967 type = v2df_ftype_v2df_int64;
22969 case V2DF_FTYPE_V2DF_SI:
22970 type = v2df_ftype_v2df_int;
22972 case V2SF_FTYPE_V2SF_V2SF:
22973 type = v2sf_ftype_v2sf_v2sf;
22975 case V1DI_FTYPE_V1DI_V1DI:
22976 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22977 type = v1di_ftype_v1di_v1di;
22979 case V1DI_FTYPE_V8QI_V8QI:
22980 type = v1di_ftype_v8qi_v8qi;
22982 case V1DI_FTYPE_V2SI_V2SI:
22983 type = v1di_ftype_v2si_v2si;
22985 case V1DI_FTYPE_V1DI_SI_COUNT:
22986 type = v1di_ftype_v1di_int;
22988 case UINT64_FTYPE_UINT64_UINT64:
22989 type = uint64_ftype_uint64_uint64;
22991 case UINT_FTYPE_UINT_UINT:
22992 type = unsigned_ftype_unsigned_unsigned;
22994 case UINT_FTYPE_UINT_USHORT:
22995 type = unsigned_ftype_unsigned_ushort;
22997 case UINT_FTYPE_UINT_UCHAR:
22998 type = unsigned_ftype_unsigned_uchar;
23000 case V8HI_FTYPE_V8HI_INT:
23001 type = v8hi_ftype_v8hi_int;
23003 case V8SF_FTYPE_V8SF_INT:
23004 type = v8sf_ftype_v8sf_int;
23006 case V4SI_FTYPE_V4SI_INT:
23007 type = v4si_ftype_v4si_int;
23009 case V4SI_FTYPE_V8SI_INT:
23010 type = v4si_ftype_v8si_int;
23012 case V4HI_FTYPE_V4HI_INT:
23013 type = v4hi_ftype_v4hi_int;
23015 case V4DF_FTYPE_V4DF_INT:
23016 type = v4df_ftype_v4df_int;
23018 case V4SF_FTYPE_V4SF_INT:
23019 type = v4sf_ftype_v4sf_int;
23021 case V4SF_FTYPE_V8SF_INT:
23022 type = v4sf_ftype_v8sf_int;
23024 case V2DI_FTYPE_V2DI_INT:
23025 case V2DI2TI_FTYPE_V2DI_INT:
23026 type = v2di_ftype_v2di_int;
23028 case V2DF_FTYPE_V2DF_INT:
23029 type = v2df_ftype_v2df_int;
23031 case V2DF_FTYPE_V4DF_INT:
23032 type = v2df_ftype_v4df_int;
23034 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23035 type = v16qi_ftype_v16qi_v16qi_v16qi;
23037 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23038 type = v8sf_ftype_v8sf_v8sf_v8sf;
23040 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23041 type = v4df_ftype_v4df_v4df_v4df;
23043 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23044 type = v4sf_ftype_v4sf_v4sf_v4sf;
23046 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23047 type = v2df_ftype_v2df_v2df_v2df;
23049 case V16QI_FTYPE_V16QI_V16QI_INT:
23050 type = v16qi_ftype_v16qi_v16qi_int;
23052 case V8SI_FTYPE_V8SI_V8SI_INT:
23053 type = v8si_ftype_v8si_v8si_int;
23055 case V8SI_FTYPE_V8SI_V4SI_INT:
23056 type = v8si_ftype_v8si_v4si_int;
23058 case V8HI_FTYPE_V8HI_V8HI_INT:
23059 type = v8hi_ftype_v8hi_v8hi_int;
23061 case V8SF_FTYPE_V8SF_V8SF_INT:
23062 type = v8sf_ftype_v8sf_v8sf_int;
23064 case V8SF_FTYPE_V8SF_V4SF_INT:
23065 type = v8sf_ftype_v8sf_v4sf_int;
23067 case V4SI_FTYPE_V4SI_V4SI_INT:
23068 type = v4si_ftype_v4si_v4si_int;
23070 case V4DF_FTYPE_V4DF_V4DF_INT:
23071 type = v4df_ftype_v4df_v4df_int;
23073 case V4DF_FTYPE_V4DF_V2DF_INT:
23074 type = v4df_ftype_v4df_v2df_int;
23076 case V4SF_FTYPE_V4SF_V4SF_INT:
23077 type = v4sf_ftype_v4sf_v4sf_int;
23079 case V2DI_FTYPE_V2DI_V2DI_INT:
23080 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23081 type = v2di_ftype_v2di_v2di_int;
23083 case V2DF_FTYPE_V2DF_V2DF_INT:
23084 type = v2df_ftype_v2df_v2df_int;
23086 case V2DI_FTYPE_V2DI_UINT_UINT:
23087 type = v2di_ftype_v2di_unsigned_unsigned;
23089 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23090 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23092 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23093 type = v1di_ftype_v1di_v1di_int;
23096 gcc_unreachable ();
23099 def_builtin_const (d->mask, d->name, type, d->code);
23102 /* pcmpestr[im] insns. */
23103 for (i = 0, d = bdesc_pcmpestr;
23104 i < ARRAY_SIZE (bdesc_pcmpestr);
23107 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23108 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23110 ftype = int_ftype_v16qi_int_v16qi_int_int;
23111 def_builtin_const (d->mask, d->name, ftype, d->code);
23114 /* pcmpistr[im] insns. */
23115 for (i = 0, d = bdesc_pcmpistr;
23116 i < ARRAY_SIZE (bdesc_pcmpistr);
23119 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23120 ftype = v16qi_ftype_v16qi_v16qi_int;
23122 ftype = int_ftype_v16qi_v16qi_int;
23123 def_builtin_const (d->mask, d->name, ftype, d->code);
23126 /* comi/ucomi insns. */
23127 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23128 if (d->mask == OPTION_MASK_ISA_SSE2)
23129 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23131 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23134 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23135 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23137 /* SSE or 3DNow!A */
23138 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23141 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23143 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23144 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23147 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23148 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23151 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23152 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23153 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23154 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23155 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23156 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23159 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23162 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23163 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23165 /* Access to the vec_init patterns. */
23166 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23167 integer_type_node, NULL_TREE);
23168 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23170 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23171 short_integer_type_node,
23172 short_integer_type_node,
23173 short_integer_type_node, NULL_TREE);
23174 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23176 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23177 char_type_node, char_type_node,
23178 char_type_node, char_type_node,
23179 char_type_node, char_type_node,
23180 char_type_node, NULL_TREE);
23181 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23183 /* Access to the vec_extract patterns. */
23184 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23185 integer_type_node, NULL_TREE);
23186 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23188 ftype = build_function_type_list (long_long_integer_type_node,
23189 V2DI_type_node, integer_type_node,
23191 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23193 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23194 integer_type_node, NULL_TREE);
23195 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23197 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23198 integer_type_node, NULL_TREE);
23199 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23201 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23202 integer_type_node, NULL_TREE);
23203 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23205 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23206 integer_type_node, NULL_TREE);
23207 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23209 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23210 integer_type_node, NULL_TREE);
23211 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23213 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23214 integer_type_node, NULL_TREE);
23215 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23217 /* Access to the vec_set patterns. */
23218 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23220 integer_type_node, NULL_TREE);
23221 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23223 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23225 integer_type_node, NULL_TREE);
23226 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23228 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23230 integer_type_node, NULL_TREE);
23231 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23233 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23235 integer_type_node, NULL_TREE);
23236 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23238 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23240 integer_type_node, NULL_TREE);
23241 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23243 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23245 integer_type_node, NULL_TREE);
23246 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23248 /* Add SSE5 multi-arg argument instructions */
23249 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23251 tree mtype = NULL_TREE;
23256 switch ((enum multi_arg_type)d->flag)
23258 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23259 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23260 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23261 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23262 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23263 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23264 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23265 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23266 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23267 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23268 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23269 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23270 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23271 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23272 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23273 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23274 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23275 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23276 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23277 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23278 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23279 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23280 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23281 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23282 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23283 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23284 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23285 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23286 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23287 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23288 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23289 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23290 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23291 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23292 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23293 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23294 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23295 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23296 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23297 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23298 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23299 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23300 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23301 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23302 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23303 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23304 case MULTI_ARG_UNKNOWN:
23306 gcc_unreachable ();
23310 def_builtin_const (d->mask, d->name, mtype, d->code);
23314 /* Internal method for ix86_init_builtins. */
23317 ix86_init_builtins_va_builtins_abi (void)
23319 tree ms_va_ref, sysv_va_ref;
23320 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23321 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23322 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23323 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23327 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23328 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23329 ms_va_ref = build_reference_type (ms_va_list_type_node);
23331 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23334 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23335 fnvoid_va_start_ms =
23336 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23337 fnvoid_va_end_sysv =
23338 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23339 fnvoid_va_start_sysv =
23340 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23342 fnvoid_va_copy_ms =
23343 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23345 fnvoid_va_copy_sysv =
23346 build_function_type_list (void_type_node, sysv_va_ref,
23347 sysv_va_ref, NULL_TREE);
23349 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23350 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23351 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23352 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23353 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23354 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23355 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23356 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23357 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23358 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23359 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23360 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23364 ix86_init_builtins (void)
23366 tree float128_type_node = make_node (REAL_TYPE);
23369 /* The __float80 type. */
23370 if (TYPE_MODE (long_double_type_node) == XFmode)
23371 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23375 /* The __float80 type. */
23376 tree float80_type_node = make_node (REAL_TYPE);
23378 TYPE_PRECISION (float80_type_node) = 80;
23379 layout_type (float80_type_node);
23380 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23384 /* The __float128 type. */
23385 TYPE_PRECISION (float128_type_node) = 128;
23386 layout_type (float128_type_node);
23387 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23390 /* TFmode support builtins. */
23391 ftype = build_function_type (float128_type_node, void_list_node);
23392 decl = add_builtin_function ("__builtin_infq", ftype,
23393 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23395 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23397 decl = add_builtin_function ("__builtin_huge_valq", ftype,
23398 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
23400 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
23402 /* We will expand them to normal call if SSE2 isn't available since
23403 they are used by libgcc. */
23404 ftype = build_function_type_list (float128_type_node,
23405 float128_type_node,
23407 decl = add_builtin_function ("__builtin_fabsq", ftype,
23408 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23409 "__fabstf2", NULL_TREE);
23410 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23411 TREE_READONLY (decl) = 1;
23413 ftype = build_function_type_list (float128_type_node,
23414 float128_type_node,
23415 float128_type_node,
23417 decl = add_builtin_function ("__builtin_copysignq", ftype,
23418 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23419 "__copysigntf3", NULL_TREE);
23420 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23421 TREE_READONLY (decl) = 1;
23423 ix86_init_mmx_sse_builtins ();
23425 ix86_init_builtins_va_builtins_abi ();
23428 /* Errors in the source file can cause expand_expr to return const0_rtx
23429 where we expect a vector. To avoid crashing, use one of the vector
23430 clear instructions. */
23432 safe_vector_operand (rtx x, enum machine_mode mode)
23434 if (x == const0_rtx)
23435 x = CONST0_RTX (mode);
23439 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23442 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23445 tree arg0 = CALL_EXPR_ARG (exp, 0);
23446 tree arg1 = CALL_EXPR_ARG (exp, 1);
23447 rtx op0 = expand_normal (arg0);
23448 rtx op1 = expand_normal (arg1);
23449 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23450 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23451 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23453 if (VECTOR_MODE_P (mode0))
23454 op0 = safe_vector_operand (op0, mode0);
23455 if (VECTOR_MODE_P (mode1))
23456 op1 = safe_vector_operand (op1, mode1);
23458 if (optimize || !target
23459 || GET_MODE (target) != tmode
23460 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23461 target = gen_reg_rtx (tmode);
23463 if (GET_MODE (op1) == SImode && mode1 == TImode)
23465 rtx x = gen_reg_rtx (V4SImode);
23466 emit_insn (gen_sse2_loadd (x, op1));
23467 op1 = gen_lowpart (TImode, x);
23470 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23471 op0 = copy_to_mode_reg (mode0, op0);
23472 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23473 op1 = copy_to_mode_reg (mode1, op1);
23475 pat = GEN_FCN (icode) (target, op0, op1);
23484 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23487 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23488 enum multi_arg_type m_type,
23489 enum insn_code sub_code)
23494 bool comparison_p = false;
23496 bool last_arg_constant = false;
23497 int num_memory = 0;
23500 enum machine_mode mode;
23503 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23507 case MULTI_ARG_3_SF:
23508 case MULTI_ARG_3_DF:
23509 case MULTI_ARG_3_DI:
23510 case MULTI_ARG_3_SI:
23511 case MULTI_ARG_3_SI_DI:
23512 case MULTI_ARG_3_HI:
23513 case MULTI_ARG_3_HI_SI:
23514 case MULTI_ARG_3_QI:
23515 case MULTI_ARG_3_PERMPS:
23516 case MULTI_ARG_3_PERMPD:
23520 case MULTI_ARG_2_SF:
23521 case MULTI_ARG_2_DF:
23522 case MULTI_ARG_2_DI:
23523 case MULTI_ARG_2_SI:
23524 case MULTI_ARG_2_HI:
23525 case MULTI_ARG_2_QI:
23529 case MULTI_ARG_2_DI_IMM:
23530 case MULTI_ARG_2_SI_IMM:
23531 case MULTI_ARG_2_HI_IMM:
23532 case MULTI_ARG_2_QI_IMM:
23534 last_arg_constant = true;
23537 case MULTI_ARG_1_SF:
23538 case MULTI_ARG_1_DF:
23539 case MULTI_ARG_1_DI:
23540 case MULTI_ARG_1_SI:
23541 case MULTI_ARG_1_HI:
23542 case MULTI_ARG_1_QI:
23543 case MULTI_ARG_1_SI_DI:
23544 case MULTI_ARG_1_HI_DI:
23545 case MULTI_ARG_1_HI_SI:
23546 case MULTI_ARG_1_QI_DI:
23547 case MULTI_ARG_1_QI_SI:
23548 case MULTI_ARG_1_QI_HI:
23549 case MULTI_ARG_1_PH2PS:
23550 case MULTI_ARG_1_PS2PH:
23554 case MULTI_ARG_2_SF_CMP:
23555 case MULTI_ARG_2_DF_CMP:
23556 case MULTI_ARG_2_DI_CMP:
23557 case MULTI_ARG_2_SI_CMP:
23558 case MULTI_ARG_2_HI_CMP:
23559 case MULTI_ARG_2_QI_CMP:
23561 comparison_p = true;
23564 case MULTI_ARG_2_SF_TF:
23565 case MULTI_ARG_2_DF_TF:
23566 case MULTI_ARG_2_DI_TF:
23567 case MULTI_ARG_2_SI_TF:
23568 case MULTI_ARG_2_HI_TF:
23569 case MULTI_ARG_2_QI_TF:
23574 case MULTI_ARG_UNKNOWN:
23576 gcc_unreachable ();
23579 if (optimize || !target
23580 || GET_MODE (target) != tmode
23581 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23582 target = gen_reg_rtx (tmode);
23584 gcc_assert (nargs <= 4);
23586 for (i = 0; i < nargs; i++)
23588 tree arg = CALL_EXPR_ARG (exp, i);
23589 rtx op = expand_normal (arg);
23590 int adjust = (comparison_p) ? 1 : 0;
23591 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23593 if (last_arg_constant && i == nargs-1)
23595 if (GET_CODE (op) != CONST_INT)
23597 error ("last argument must be an immediate");
23598 return gen_reg_rtx (tmode);
23603 if (VECTOR_MODE_P (mode))
23604 op = safe_vector_operand (op, mode);
23606 /* If we aren't optimizing, only allow one memory operand to be
23608 if (memory_operand (op, mode))
23611 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23614 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23616 op = force_reg (mode, op);
23620 args[i].mode = mode;
23626 pat = GEN_FCN (icode) (target, args[0].op);
23631 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23632 GEN_INT ((int)sub_code));
23633 else if (! comparison_p)
23634 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23637 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23641 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23646 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23650 gcc_unreachable ();
23660 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23661 insns with vec_merge. */
23664 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23668 tree arg0 = CALL_EXPR_ARG (exp, 0);
23669 rtx op1, op0 = expand_normal (arg0);
23670 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23671 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23673 if (optimize || !target
23674 || GET_MODE (target) != tmode
23675 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23676 target = gen_reg_rtx (tmode);
23678 if (VECTOR_MODE_P (mode0))
23679 op0 = safe_vector_operand (op0, mode0);
23681 if ((optimize && !register_operand (op0, mode0))
23682 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23683 op0 = copy_to_mode_reg (mode0, op0);
23686 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23687 op1 = copy_to_mode_reg (mode0, op1);
23689 pat = GEN_FCN (icode) (target, op0, op1);
23696 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23699 ix86_expand_sse_compare (const struct builtin_description *d,
23700 tree exp, rtx target, bool swap)
23703 tree arg0 = CALL_EXPR_ARG (exp, 0);
23704 tree arg1 = CALL_EXPR_ARG (exp, 1);
23705 rtx op0 = expand_normal (arg0);
23706 rtx op1 = expand_normal (arg1);
23708 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23709 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23710 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23711 enum rtx_code comparison = d->comparison;
23713 if (VECTOR_MODE_P (mode0))
23714 op0 = safe_vector_operand (op0, mode0);
23715 if (VECTOR_MODE_P (mode1))
23716 op1 = safe_vector_operand (op1, mode1);
23718 /* Swap operands if we have a comparison that isn't available in
23722 rtx tmp = gen_reg_rtx (mode1);
23723 emit_move_insn (tmp, op1);
23728 if (optimize || !target
23729 || GET_MODE (target) != tmode
23730 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23731 target = gen_reg_rtx (tmode);
23733 if ((optimize && !register_operand (op0, mode0))
23734 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23735 op0 = copy_to_mode_reg (mode0, op0);
23736 if ((optimize && !register_operand (op1, mode1))
23737 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23738 op1 = copy_to_mode_reg (mode1, op1);
23740 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23741 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23748 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23751 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23755 tree arg0 = CALL_EXPR_ARG (exp, 0);
23756 tree arg1 = CALL_EXPR_ARG (exp, 1);
23757 rtx op0 = expand_normal (arg0);
23758 rtx op1 = expand_normal (arg1);
23759 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23760 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23761 enum rtx_code comparison = d->comparison;
23763 if (VECTOR_MODE_P (mode0))
23764 op0 = safe_vector_operand (op0, mode0);
23765 if (VECTOR_MODE_P (mode1))
23766 op1 = safe_vector_operand (op1, mode1);
23768 /* Swap operands if we have a comparison that isn't available in
23770 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23777 target = gen_reg_rtx (SImode);
23778 emit_move_insn (target, const0_rtx);
23779 target = gen_rtx_SUBREG (QImode, target, 0);
23781 if ((optimize && !register_operand (op0, mode0))
23782 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23783 op0 = copy_to_mode_reg (mode0, op0);
23784 if ((optimize && !register_operand (op1, mode1))
23785 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23786 op1 = copy_to_mode_reg (mode1, op1);
23788 pat = GEN_FCN (d->icode) (op0, op1);
23792 emit_insn (gen_rtx_SET (VOIDmode,
23793 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23794 gen_rtx_fmt_ee (comparison, QImode,
23798 return SUBREG_REG (target);
23801 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23804 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23808 tree arg0 = CALL_EXPR_ARG (exp, 0);
23809 tree arg1 = CALL_EXPR_ARG (exp, 1);
23810 rtx op0 = expand_normal (arg0);
23811 rtx op1 = expand_normal (arg1);
23812 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23813 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23814 enum rtx_code comparison = d->comparison;
23816 if (VECTOR_MODE_P (mode0))
23817 op0 = safe_vector_operand (op0, mode0);
23818 if (VECTOR_MODE_P (mode1))
23819 op1 = safe_vector_operand (op1, mode1);
23821 target = gen_reg_rtx (SImode);
23822 emit_move_insn (target, const0_rtx);
23823 target = gen_rtx_SUBREG (QImode, target, 0);
23825 if ((optimize && !register_operand (op0, mode0))
23826 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23827 op0 = copy_to_mode_reg (mode0, op0);
23828 if ((optimize && !register_operand (op1, mode1))
23829 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23830 op1 = copy_to_mode_reg (mode1, op1);
23832 pat = GEN_FCN (d->icode) (op0, op1);
23836 emit_insn (gen_rtx_SET (VOIDmode,
23837 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23838 gen_rtx_fmt_ee (comparison, QImode,
23842 return SUBREG_REG (target);
23845 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23848 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23849 tree exp, rtx target)
23852 tree arg0 = CALL_EXPR_ARG (exp, 0);
23853 tree arg1 = CALL_EXPR_ARG (exp, 1);
23854 tree arg2 = CALL_EXPR_ARG (exp, 2);
23855 tree arg3 = CALL_EXPR_ARG (exp, 3);
23856 tree arg4 = CALL_EXPR_ARG (exp, 4);
23857 rtx scratch0, scratch1;
23858 rtx op0 = expand_normal (arg0);
23859 rtx op1 = expand_normal (arg1);
23860 rtx op2 = expand_normal (arg2);
23861 rtx op3 = expand_normal (arg3);
23862 rtx op4 = expand_normal (arg4);
23863 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23865 tmode0 = insn_data[d->icode].operand[0].mode;
23866 tmode1 = insn_data[d->icode].operand[1].mode;
23867 modev2 = insn_data[d->icode].operand[2].mode;
23868 modei3 = insn_data[d->icode].operand[3].mode;
23869 modev4 = insn_data[d->icode].operand[4].mode;
23870 modei5 = insn_data[d->icode].operand[5].mode;
23871 modeimm = insn_data[d->icode].operand[6].mode;
23873 if (VECTOR_MODE_P (modev2))
23874 op0 = safe_vector_operand (op0, modev2);
23875 if (VECTOR_MODE_P (modev4))
23876 op2 = safe_vector_operand (op2, modev4);
23878 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23879 op0 = copy_to_mode_reg (modev2, op0);
23880 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23881 op1 = copy_to_mode_reg (modei3, op1);
23882 if ((optimize && !register_operand (op2, modev4))
23883 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23884 op2 = copy_to_mode_reg (modev4, op2);
23885 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23886 op3 = copy_to_mode_reg (modei5, op3);
23888 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23890 error ("the fifth argument must be a 8-bit immediate");
23894 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23896 if (optimize || !target
23897 || GET_MODE (target) != tmode0
23898 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23899 target = gen_reg_rtx (tmode0);
23901 scratch1 = gen_reg_rtx (tmode1);
23903 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23905 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23907 if (optimize || !target
23908 || GET_MODE (target) != tmode1
23909 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23910 target = gen_reg_rtx (tmode1);
23912 scratch0 = gen_reg_rtx (tmode0);
23914 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23918 gcc_assert (d->flag);
23920 scratch0 = gen_reg_rtx (tmode0);
23921 scratch1 = gen_reg_rtx (tmode1);
23923 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23933 target = gen_reg_rtx (SImode);
23934 emit_move_insn (target, const0_rtx);
23935 target = gen_rtx_SUBREG (QImode, target, 0);
23938 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23939 gen_rtx_fmt_ee (EQ, QImode,
23940 gen_rtx_REG ((enum machine_mode) d->flag,
23943 return SUBREG_REG (target);
23950 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23953 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23954 tree exp, rtx target)
23957 tree arg0 = CALL_EXPR_ARG (exp, 0);
23958 tree arg1 = CALL_EXPR_ARG (exp, 1);
23959 tree arg2 = CALL_EXPR_ARG (exp, 2);
23960 rtx scratch0, scratch1;
23961 rtx op0 = expand_normal (arg0);
23962 rtx op1 = expand_normal (arg1);
23963 rtx op2 = expand_normal (arg2);
23964 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23966 tmode0 = insn_data[d->icode].operand[0].mode;
23967 tmode1 = insn_data[d->icode].operand[1].mode;
23968 modev2 = insn_data[d->icode].operand[2].mode;
23969 modev3 = insn_data[d->icode].operand[3].mode;
23970 modeimm = insn_data[d->icode].operand[4].mode;
23972 if (VECTOR_MODE_P (modev2))
23973 op0 = safe_vector_operand (op0, modev2);
23974 if (VECTOR_MODE_P (modev3))
23975 op1 = safe_vector_operand (op1, modev3);
23977 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23978 op0 = copy_to_mode_reg (modev2, op0);
23979 if ((optimize && !register_operand (op1, modev3))
23980 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23981 op1 = copy_to_mode_reg (modev3, op1);
23983 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23985 error ("the third argument must be a 8-bit immediate");
23989 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23991 if (optimize || !target
23992 || GET_MODE (target) != tmode0
23993 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23994 target = gen_reg_rtx (tmode0);
23996 scratch1 = gen_reg_rtx (tmode1);
23998 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24000 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24002 if (optimize || !target
24003 || GET_MODE (target) != tmode1
24004 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24005 target = gen_reg_rtx (tmode1);
24007 scratch0 = gen_reg_rtx (tmode0);
24009 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24013 gcc_assert (d->flag);
24015 scratch0 = gen_reg_rtx (tmode0);
24016 scratch1 = gen_reg_rtx (tmode1);
24018 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24028 target = gen_reg_rtx (SImode);
24029 emit_move_insn (target, const0_rtx);
24030 target = gen_rtx_SUBREG (QImode, target, 0);
24033 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24034 gen_rtx_fmt_ee (EQ, QImode,
24035 gen_rtx_REG ((enum machine_mode) d->flag,
24038 return SUBREG_REG (target);
24044 /* Subroutine of ix86_expand_builtin to take care of insns with
24045 variable number of operands. */
24048 ix86_expand_args_builtin (const struct builtin_description *d,
24049 tree exp, rtx target)
24051 rtx pat, real_target;
24052 unsigned int i, nargs;
24053 unsigned int nargs_constant = 0;
24054 int num_memory = 0;
24058 enum machine_mode mode;
24060 bool last_arg_count = false;
24061 enum insn_code icode = d->icode;
24062 const struct insn_data *insn_p = &insn_data[icode];
24063 enum machine_mode tmode = insn_p->operand[0].mode;
24064 enum machine_mode rmode = VOIDmode;
24066 enum rtx_code comparison = d->comparison;
24068 switch ((enum ix86_builtin_type) d->flag)
24070 case INT_FTYPE_V8SF_V8SF_PTEST:
24071 case INT_FTYPE_V4DI_V4DI_PTEST:
24072 case INT_FTYPE_V4DF_V4DF_PTEST:
24073 case INT_FTYPE_V4SF_V4SF_PTEST:
24074 case INT_FTYPE_V2DI_V2DI_PTEST:
24075 case INT_FTYPE_V2DF_V2DF_PTEST:
24076 return ix86_expand_sse_ptest (d, exp, target);
24077 case FLOAT128_FTYPE_FLOAT128:
24078 case FLOAT_FTYPE_FLOAT:
24079 case INT64_FTYPE_V4SF:
24080 case INT64_FTYPE_V2DF:
24081 case INT_FTYPE_V16QI:
24082 case INT_FTYPE_V8QI:
24083 case INT_FTYPE_V8SF:
24084 case INT_FTYPE_V4DF:
24085 case INT_FTYPE_V4SF:
24086 case INT_FTYPE_V2DF:
24087 case V16QI_FTYPE_V16QI:
24088 case V8SI_FTYPE_V8SF:
24089 case V8SI_FTYPE_V4SI:
24090 case V8HI_FTYPE_V8HI:
24091 case V8HI_FTYPE_V16QI:
24092 case V8QI_FTYPE_V8QI:
24093 case V8SF_FTYPE_V8SF:
24094 case V8SF_FTYPE_V8SI:
24095 case V8SF_FTYPE_V4SF:
24096 case V4SI_FTYPE_V4SI:
24097 case V4SI_FTYPE_V16QI:
24098 case V4SI_FTYPE_V4SF:
24099 case V4SI_FTYPE_V8SI:
24100 case V4SI_FTYPE_V8HI:
24101 case V4SI_FTYPE_V4DF:
24102 case V4SI_FTYPE_V2DF:
24103 case V4HI_FTYPE_V4HI:
24104 case V4DF_FTYPE_V4DF:
24105 case V4DF_FTYPE_V4SI:
24106 case V4DF_FTYPE_V4SF:
24107 case V4DF_FTYPE_V2DF:
24108 case V4SF_FTYPE_V4SF:
24109 case V4SF_FTYPE_V4SI:
24110 case V4SF_FTYPE_V8SF:
24111 case V4SF_FTYPE_V4DF:
24112 case V4SF_FTYPE_V2DF:
24113 case V2DI_FTYPE_V2DI:
24114 case V2DI_FTYPE_V16QI:
24115 case V2DI_FTYPE_V8HI:
24116 case V2DI_FTYPE_V4SI:
24117 case V2DF_FTYPE_V2DF:
24118 case V2DF_FTYPE_V4SI:
24119 case V2DF_FTYPE_V4DF:
24120 case V2DF_FTYPE_V4SF:
24121 case V2DF_FTYPE_V2SI:
24122 case V2SI_FTYPE_V2SI:
24123 case V2SI_FTYPE_V4SF:
24124 case V2SI_FTYPE_V2SF:
24125 case V2SI_FTYPE_V2DF:
24126 case V2SF_FTYPE_V2SF:
24127 case V2SF_FTYPE_V2SI:
24130 case V4SF_FTYPE_V4SF_VEC_MERGE:
24131 case V2DF_FTYPE_V2DF_VEC_MERGE:
24132 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24133 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24134 case V16QI_FTYPE_V16QI_V16QI:
24135 case V16QI_FTYPE_V8HI_V8HI:
24136 case V8QI_FTYPE_V8QI_V8QI:
24137 case V8QI_FTYPE_V4HI_V4HI:
24138 case V8HI_FTYPE_V8HI_V8HI:
24139 case V8HI_FTYPE_V16QI_V16QI:
24140 case V8HI_FTYPE_V4SI_V4SI:
24141 case V8SF_FTYPE_V8SF_V8SF:
24142 case V8SF_FTYPE_V8SF_V8SI:
24143 case V4SI_FTYPE_V4SI_V4SI:
24144 case V4SI_FTYPE_V8HI_V8HI:
24145 case V4SI_FTYPE_V4SF_V4SF:
24146 case V4SI_FTYPE_V2DF_V2DF:
24147 case V4HI_FTYPE_V4HI_V4HI:
24148 case V4HI_FTYPE_V8QI_V8QI:
24149 case V4HI_FTYPE_V2SI_V2SI:
24150 case V4DF_FTYPE_V4DF_V4DF:
24151 case V4DF_FTYPE_V4DF_V4DI:
24152 case V4SF_FTYPE_V4SF_V4SF:
24153 case V4SF_FTYPE_V4SF_V4SI:
24154 case V4SF_FTYPE_V4SF_V2SI:
24155 case V4SF_FTYPE_V4SF_V2DF:
24156 case V4SF_FTYPE_V4SF_DI:
24157 case V4SF_FTYPE_V4SF_SI:
24158 case V2DI_FTYPE_V2DI_V2DI:
24159 case V2DI_FTYPE_V16QI_V16QI:
24160 case V2DI_FTYPE_V4SI_V4SI:
24161 case V2DI_FTYPE_V2DI_V16QI:
24162 case V2DI_FTYPE_V2DF_V2DF:
24163 case V2SI_FTYPE_V2SI_V2SI:
24164 case V2SI_FTYPE_V4HI_V4HI:
24165 case V2SI_FTYPE_V2SF_V2SF:
24166 case V2DF_FTYPE_V2DF_V2DF:
24167 case V2DF_FTYPE_V2DF_V4SF:
24168 case V2DF_FTYPE_V2DF_V2DI:
24169 case V2DF_FTYPE_V2DF_DI:
24170 case V2DF_FTYPE_V2DF_SI:
24171 case V2SF_FTYPE_V2SF_V2SF:
24172 case V1DI_FTYPE_V1DI_V1DI:
24173 case V1DI_FTYPE_V8QI_V8QI:
24174 case V1DI_FTYPE_V2SI_V2SI:
24175 if (comparison == UNKNOWN)
24176 return ix86_expand_binop_builtin (icode, exp, target);
24179 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24180 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24181 gcc_assert (comparison != UNKNOWN);
24185 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24186 case V8HI_FTYPE_V8HI_SI_COUNT:
24187 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24188 case V4SI_FTYPE_V4SI_SI_COUNT:
24189 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24190 case V4HI_FTYPE_V4HI_SI_COUNT:
24191 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24192 case V2DI_FTYPE_V2DI_SI_COUNT:
24193 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24194 case V2SI_FTYPE_V2SI_SI_COUNT:
24195 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24196 case V1DI_FTYPE_V1DI_SI_COUNT:
24198 last_arg_count = true;
24200 case UINT64_FTYPE_UINT64_UINT64:
24201 case UINT_FTYPE_UINT_UINT:
24202 case UINT_FTYPE_UINT_USHORT:
24203 case UINT_FTYPE_UINT_UCHAR:
24206 case V2DI2TI_FTYPE_V2DI_INT:
24209 nargs_constant = 1;
24211 case V8HI_FTYPE_V8HI_INT:
24212 case V8SF_FTYPE_V8SF_INT:
24213 case V4SI_FTYPE_V4SI_INT:
24214 case V4SI_FTYPE_V8SI_INT:
24215 case V4HI_FTYPE_V4HI_INT:
24216 case V4DF_FTYPE_V4DF_INT:
24217 case V4SF_FTYPE_V4SF_INT:
24218 case V4SF_FTYPE_V8SF_INT:
24219 case V2DI_FTYPE_V2DI_INT:
24220 case V2DF_FTYPE_V2DF_INT:
24221 case V2DF_FTYPE_V4DF_INT:
24223 nargs_constant = 1;
24225 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24226 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24227 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24228 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24229 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24232 case V16QI_FTYPE_V16QI_V16QI_INT:
24233 case V8HI_FTYPE_V8HI_V8HI_INT:
24234 case V8SI_FTYPE_V8SI_V8SI_INT:
24235 case V8SI_FTYPE_V8SI_V4SI_INT:
24236 case V8SF_FTYPE_V8SF_V8SF_INT:
24237 case V8SF_FTYPE_V8SF_V4SF_INT:
24238 case V4SI_FTYPE_V4SI_V4SI_INT:
24239 case V4DF_FTYPE_V4DF_V4DF_INT:
24240 case V4DF_FTYPE_V4DF_V2DF_INT:
24241 case V4SF_FTYPE_V4SF_V4SF_INT:
24242 case V2DI_FTYPE_V2DI_V2DI_INT:
24243 case V2DF_FTYPE_V2DF_V2DF_INT:
24245 nargs_constant = 1;
24247 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24250 nargs_constant = 1;
24252 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24255 nargs_constant = 1;
24257 case V2DI_FTYPE_V2DI_UINT_UINT:
24259 nargs_constant = 2;
24261 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24263 nargs_constant = 2;
24266 gcc_unreachable ();
24269 gcc_assert (nargs <= ARRAY_SIZE (args));
24271 if (comparison != UNKNOWN)
24273 gcc_assert (nargs == 2);
24274 return ix86_expand_sse_compare (d, exp, target, swap);
24277 if (rmode == VOIDmode || rmode == tmode)
24281 || GET_MODE (target) != tmode
24282 || ! (*insn_p->operand[0].predicate) (target, tmode))
24283 target = gen_reg_rtx (tmode);
24284 real_target = target;
24288 target = gen_reg_rtx (rmode);
24289 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24292 for (i = 0; i < nargs; i++)
24294 tree arg = CALL_EXPR_ARG (exp, i);
24295 rtx op = expand_normal (arg);
24296 enum machine_mode mode = insn_p->operand[i + 1].mode;
24297 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24299 if (last_arg_count && (i + 1) == nargs)
24301 /* SIMD shift insns take either an 8-bit immediate or
24302 register as count. But builtin functions take int as
24303 count. If count doesn't match, we put it in register. */
24306 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24307 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24308 op = copy_to_reg (op);
24311 else if ((nargs - i) <= nargs_constant)
24316 case CODE_FOR_sse4_1_roundpd:
24317 case CODE_FOR_sse4_1_roundps:
24318 case CODE_FOR_sse4_1_roundsd:
24319 case CODE_FOR_sse4_1_roundss:
24320 case CODE_FOR_sse4_1_blendps:
24321 case CODE_FOR_avx_blendpd256:
24322 case CODE_FOR_avx_vpermilv4df:
24323 case CODE_FOR_avx_roundpd256:
24324 case CODE_FOR_avx_roundps256:
24325 error ("the last argument must be a 4-bit immediate");
24328 case CODE_FOR_sse4_1_blendpd:
24329 case CODE_FOR_avx_vpermilv2df:
24330 error ("the last argument must be a 2-bit immediate");
24333 case CODE_FOR_avx_vextractf128v4df:
24334 case CODE_FOR_avx_vextractf128v8sf:
24335 case CODE_FOR_avx_vextractf128v8si:
24336 case CODE_FOR_avx_vinsertf128v4df:
24337 case CODE_FOR_avx_vinsertf128v8sf:
24338 case CODE_FOR_avx_vinsertf128v8si:
24339 error ("the last argument must be a 1-bit immediate");
24342 case CODE_FOR_avx_cmpsdv2df3:
24343 case CODE_FOR_avx_cmpssv4sf3:
24344 case CODE_FOR_avx_cmppdv2df3:
24345 case CODE_FOR_avx_cmppsv4sf3:
24346 case CODE_FOR_avx_cmppdv4df3:
24347 case CODE_FOR_avx_cmppsv8sf3:
24348 error ("the last argument must be a 5-bit immediate");
24352 switch (nargs_constant)
24355 if ((nargs - i) == nargs_constant)
24357 error ("the next to last argument must be an 8-bit immediate");
24361 error ("the last argument must be an 8-bit immediate");
24364 gcc_unreachable ();
24371 if (VECTOR_MODE_P (mode))
24372 op = safe_vector_operand (op, mode);
24374 /* If we aren't optimizing, only allow one memory operand to
24376 if (memory_operand (op, mode))
24379 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24381 if (optimize || !match || num_memory > 1)
24382 op = copy_to_mode_reg (mode, op);
24386 op = copy_to_reg (op);
24387 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24392 args[i].mode = mode;
24398 pat = GEN_FCN (icode) (real_target, args[0].op);
24401 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24404 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24408 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24409 args[2].op, args[3].op);
24412 gcc_unreachable ();
24422 /* Subroutine of ix86_expand_builtin to take care of special insns
24423 with variable number of operands. */
24426 ix86_expand_special_args_builtin (const struct builtin_description *d,
24427 tree exp, rtx target)
24431 unsigned int i, nargs, arg_adjust, memory;
24435 enum machine_mode mode;
24437 enum insn_code icode = d->icode;
24438 bool last_arg_constant = false;
24439 const struct insn_data *insn_p = &insn_data[icode];
24440 enum machine_mode tmode = insn_p->operand[0].mode;
24441 enum { load, store } klass;
24443 switch ((enum ix86_special_builtin_type) d->flag)
24445 case VOID_FTYPE_VOID:
24446 emit_insn (GEN_FCN (icode) (target));
24448 case V2DI_FTYPE_PV2DI:
24449 case V32QI_FTYPE_PCCHAR:
24450 case V16QI_FTYPE_PCCHAR:
24451 case V8SF_FTYPE_PCV4SF:
24452 case V8SF_FTYPE_PCFLOAT:
24453 case V4SF_FTYPE_PCFLOAT:
24454 case V4DF_FTYPE_PCV2DF:
24455 case V4DF_FTYPE_PCDOUBLE:
24456 case V2DF_FTYPE_PCDOUBLE:
24461 case VOID_FTYPE_PV2SF_V4SF:
24462 case VOID_FTYPE_PV4DI_V4DI:
24463 case VOID_FTYPE_PV2DI_V2DI:
24464 case VOID_FTYPE_PCHAR_V32QI:
24465 case VOID_FTYPE_PCHAR_V16QI:
24466 case VOID_FTYPE_PFLOAT_V8SF:
24467 case VOID_FTYPE_PFLOAT_V4SF:
24468 case VOID_FTYPE_PDOUBLE_V4DF:
24469 case VOID_FTYPE_PDOUBLE_V2DF:
24470 case VOID_FTYPE_PDI_DI:
24471 case VOID_FTYPE_PINT_INT:
24474 /* Reserve memory operand for target. */
24475 memory = ARRAY_SIZE (args);
24477 case V4SF_FTYPE_V4SF_PCV2SF:
24478 case V2DF_FTYPE_V2DF_PCDOUBLE:
24483 case V8SF_FTYPE_PCV8SF_V8SF:
24484 case V4DF_FTYPE_PCV4DF_V4DF:
24485 case V4SF_FTYPE_PCV4SF_V4SF:
24486 case V2DF_FTYPE_PCV2DF_V2DF:
24491 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24492 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24493 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24494 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24497 /* Reserve memory operand for target. */
24498 memory = ARRAY_SIZE (args);
24501 gcc_unreachable ();
24504 gcc_assert (nargs <= ARRAY_SIZE (args));
24506 if (klass == store)
24508 arg = CALL_EXPR_ARG (exp, 0);
24509 op = expand_normal (arg);
24510 gcc_assert (target == 0);
24511 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24519 || GET_MODE (target) != tmode
24520 || ! (*insn_p->operand[0].predicate) (target, tmode))
24521 target = gen_reg_rtx (tmode);
24524 for (i = 0; i < nargs; i++)
24526 enum machine_mode mode = insn_p->operand[i + 1].mode;
24529 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24530 op = expand_normal (arg);
24531 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24533 if (last_arg_constant && (i + 1) == nargs)
24539 error ("the last argument must be an 8-bit immediate");
24547 /* This must be the memory operand. */
24548 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24549 gcc_assert (GET_MODE (op) == mode
24550 || GET_MODE (op) == VOIDmode);
24554 /* This must be register. */
24555 if (VECTOR_MODE_P (mode))
24556 op = safe_vector_operand (op, mode);
24558 gcc_assert (GET_MODE (op) == mode
24559 || GET_MODE (op) == VOIDmode);
24560 op = copy_to_mode_reg (mode, op);
24565 args[i].mode = mode;
24571 pat = GEN_FCN (icode) (target, args[0].op);
24574 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24577 gcc_unreachable ();
24583 return klass == store ? 0 : target;
24586 /* Return the integer constant in ARG. Constrain it to be in the range
24587 of the subparts of VEC_TYPE; issue an error if not. */
24590 get_element_number (tree vec_type, tree arg)
24592 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24594 if (!host_integerp (arg, 1)
24595 || (elt = tree_low_cst (arg, 1), elt > max))
24597 error ("selector must be an integer constant in the range 0..%wi", max);
24604 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24605 ix86_expand_vector_init. We DO have language-level syntax for this, in
24606 the form of (type){ init-list }. Except that since we can't place emms
24607 instructions from inside the compiler, we can't allow the use of MMX
24608 registers unless the user explicitly asks for it. So we do *not* define
24609 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24610 we have builtins invoked by mmintrin.h that gives us license to emit
24611 these sorts of instructions. */
24614 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24616 enum machine_mode tmode = TYPE_MODE (type);
24617 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24618 int i, n_elt = GET_MODE_NUNITS (tmode);
24619 rtvec v = rtvec_alloc (n_elt);
24621 gcc_assert (VECTOR_MODE_P (tmode));
24622 gcc_assert (call_expr_nargs (exp) == n_elt);
24624 for (i = 0; i < n_elt; ++i)
24626 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24627 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24630 if (!target || !register_operand (target, tmode))
24631 target = gen_reg_rtx (tmode);
24633 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24637 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24638 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24639 had a language-level syntax for referencing vector elements. */
24642 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24644 enum machine_mode tmode, mode0;
24649 arg0 = CALL_EXPR_ARG (exp, 0);
24650 arg1 = CALL_EXPR_ARG (exp, 1);
24652 op0 = expand_normal (arg0);
24653 elt = get_element_number (TREE_TYPE (arg0), arg1);
24655 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24656 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24657 gcc_assert (VECTOR_MODE_P (mode0));
24659 op0 = force_reg (mode0, op0);
24661 if (optimize || !target || !register_operand (target, tmode))
24662 target = gen_reg_rtx (tmode);
24664 ix86_expand_vector_extract (true, target, op0, elt);
24669 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24670 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24671 a language-level syntax for referencing vector elements. */
24674 ix86_expand_vec_set_builtin (tree exp)
24676 enum machine_mode tmode, mode1;
24677 tree arg0, arg1, arg2;
24679 rtx op0, op1, target;
24681 arg0 = CALL_EXPR_ARG (exp, 0);
24682 arg1 = CALL_EXPR_ARG (exp, 1);
24683 arg2 = CALL_EXPR_ARG (exp, 2);
24685 tmode = TYPE_MODE (TREE_TYPE (arg0));
24686 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24687 gcc_assert (VECTOR_MODE_P (tmode));
24689 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24690 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24691 elt = get_element_number (TREE_TYPE (arg0), arg2);
24693 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24694 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24696 op0 = force_reg (tmode, op0);
24697 op1 = force_reg (mode1, op1);
24699 /* OP0 is the source of these builtin functions and shouldn't be
24700 modified. Create a copy, use it and return it as target. */
24701 target = gen_reg_rtx (tmode);
24702 emit_move_insn (target, op0);
24703 ix86_expand_vector_set (true, target, op1, elt);
24708 /* Expand an expression EXP that calls a built-in function,
24709 with result going to TARGET if that's convenient
24710 (and in mode MODE if that's convenient).
24711 SUBTARGET may be used as the target for computing one of EXP's operands.
24712 IGNORE is nonzero if the value is to be ignored. */
24715 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24716 enum machine_mode mode ATTRIBUTE_UNUSED,
24717 int ignore ATTRIBUTE_UNUSED)
24719 const struct builtin_description *d;
24721 enum insn_code icode;
24722 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24723 tree arg0, arg1, arg2;
24724 rtx op0, op1, op2, pat;
24725 enum machine_mode mode0, mode1, mode2;
24726 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24728 /* Determine whether the builtin function is available under the current ISA.
24729 Originally the builtin was not created if it wasn't applicable to the
24730 current ISA based on the command line switches. With function specific
24731 options, we need to check in the context of the function making the call
24732 whether it is supported. */
24733 if (ix86_builtins_isa[fcode].isa
24734 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24736 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24737 NULL, NULL, false);
24740 error ("%qE needs unknown isa option", fndecl);
24743 gcc_assert (opts != NULL);
24744 error ("%qE needs isa option %s", fndecl, opts);
24752 case IX86_BUILTIN_MASKMOVQ:
24753 case IX86_BUILTIN_MASKMOVDQU:
24754 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24755 ? CODE_FOR_mmx_maskmovq
24756 : CODE_FOR_sse2_maskmovdqu);
24757 /* Note the arg order is different from the operand order. */
24758 arg1 = CALL_EXPR_ARG (exp, 0);
24759 arg2 = CALL_EXPR_ARG (exp, 1);
24760 arg0 = CALL_EXPR_ARG (exp, 2);
24761 op0 = expand_normal (arg0);
24762 op1 = expand_normal (arg1);
24763 op2 = expand_normal (arg2);
24764 mode0 = insn_data[icode].operand[0].mode;
24765 mode1 = insn_data[icode].operand[1].mode;
24766 mode2 = insn_data[icode].operand[2].mode;
24768 op0 = force_reg (Pmode, op0);
24769 op0 = gen_rtx_MEM (mode1, op0);
24771 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24772 op0 = copy_to_mode_reg (mode0, op0);
24773 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24774 op1 = copy_to_mode_reg (mode1, op1);
24775 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24776 op2 = copy_to_mode_reg (mode2, op2);
24777 pat = GEN_FCN (icode) (op0, op1, op2);
24783 case IX86_BUILTIN_LDMXCSR:
24784 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24785 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24786 emit_move_insn (target, op0);
24787 emit_insn (gen_sse_ldmxcsr (target));
24790 case IX86_BUILTIN_STMXCSR:
24791 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24792 emit_insn (gen_sse_stmxcsr (target));
24793 return copy_to_mode_reg (SImode, target);
24795 case IX86_BUILTIN_CLFLUSH:
24796 arg0 = CALL_EXPR_ARG (exp, 0);
24797 op0 = expand_normal (arg0);
24798 icode = CODE_FOR_sse2_clflush;
24799 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24800 op0 = copy_to_mode_reg (Pmode, op0);
24802 emit_insn (gen_sse2_clflush (op0));
24805 case IX86_BUILTIN_MONITOR:
24806 arg0 = CALL_EXPR_ARG (exp, 0);
24807 arg1 = CALL_EXPR_ARG (exp, 1);
24808 arg2 = CALL_EXPR_ARG (exp, 2);
24809 op0 = expand_normal (arg0);
24810 op1 = expand_normal (arg1);
24811 op2 = expand_normal (arg2);
24813 op0 = copy_to_mode_reg (Pmode, op0);
24815 op1 = copy_to_mode_reg (SImode, op1);
24817 op2 = copy_to_mode_reg (SImode, op2);
24818 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24821 case IX86_BUILTIN_MWAIT:
24822 arg0 = CALL_EXPR_ARG (exp, 0);
24823 arg1 = CALL_EXPR_ARG (exp, 1);
24824 op0 = expand_normal (arg0);
24825 op1 = expand_normal (arg1);
24827 op0 = copy_to_mode_reg (SImode, op0);
24829 op1 = copy_to_mode_reg (SImode, op1);
24830 emit_insn (gen_sse3_mwait (op0, op1));
24833 case IX86_BUILTIN_VEC_INIT_V2SI:
24834 case IX86_BUILTIN_VEC_INIT_V4HI:
24835 case IX86_BUILTIN_VEC_INIT_V8QI:
24836 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24838 case IX86_BUILTIN_VEC_EXT_V2DF:
24839 case IX86_BUILTIN_VEC_EXT_V2DI:
24840 case IX86_BUILTIN_VEC_EXT_V4SF:
24841 case IX86_BUILTIN_VEC_EXT_V4SI:
24842 case IX86_BUILTIN_VEC_EXT_V8HI:
24843 case IX86_BUILTIN_VEC_EXT_V2SI:
24844 case IX86_BUILTIN_VEC_EXT_V4HI:
24845 case IX86_BUILTIN_VEC_EXT_V16QI:
24846 return ix86_expand_vec_ext_builtin (exp, target);
24848 case IX86_BUILTIN_VEC_SET_V2DI:
24849 case IX86_BUILTIN_VEC_SET_V4SF:
24850 case IX86_BUILTIN_VEC_SET_V4SI:
24851 case IX86_BUILTIN_VEC_SET_V8HI:
24852 case IX86_BUILTIN_VEC_SET_V4HI:
24853 case IX86_BUILTIN_VEC_SET_V16QI:
24854 return ix86_expand_vec_set_builtin (exp);
24856 case IX86_BUILTIN_INFQ:
24857 case IX86_BUILTIN_HUGE_VALQ:
24859 REAL_VALUE_TYPE inf;
24863 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24865 tmp = validize_mem (force_const_mem (mode, tmp));
24868 target = gen_reg_rtx (mode);
24870 emit_move_insn (target, tmp);
24878 for (i = 0, d = bdesc_special_args;
24879 i < ARRAY_SIZE (bdesc_special_args);
24881 if (d->code == fcode)
24882 return ix86_expand_special_args_builtin (d, exp, target);
24884 for (i = 0, d = bdesc_args;
24885 i < ARRAY_SIZE (bdesc_args);
24887 if (d->code == fcode)
24890 case IX86_BUILTIN_FABSQ:
24891 case IX86_BUILTIN_COPYSIGNQ:
24893 /* Emit a normal call if SSE2 isn't available. */
24894 return expand_call (exp, target, ignore);
24896 return ix86_expand_args_builtin (d, exp, target);
24899 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24900 if (d->code == fcode)
24901 return ix86_expand_sse_comi (d, exp, target);
24903 for (i = 0, d = bdesc_pcmpestr;
24904 i < ARRAY_SIZE (bdesc_pcmpestr);
24906 if (d->code == fcode)
24907 return ix86_expand_sse_pcmpestr (d, exp, target);
24909 for (i = 0, d = bdesc_pcmpistr;
24910 i < ARRAY_SIZE (bdesc_pcmpistr);
24912 if (d->code == fcode)
24913 return ix86_expand_sse_pcmpistr (d, exp, target);
24915 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24916 if (d->code == fcode)
24917 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24918 (enum multi_arg_type)d->flag,
24921 gcc_unreachable ();
24924 /* Returns a function decl for a vectorized version of the builtin function
24925 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24926 if it is not available. */
24929 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24932 enum machine_mode in_mode, out_mode;
24935 if (TREE_CODE (type_out) != VECTOR_TYPE
24936 || TREE_CODE (type_in) != VECTOR_TYPE)
24939 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24940 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24941 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24942 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24946 case BUILT_IN_SQRT:
24947 if (out_mode == DFmode && out_n == 2
24948 && in_mode == DFmode && in_n == 2)
24949 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24952 case BUILT_IN_SQRTF:
24953 if (out_mode == SFmode && out_n == 4
24954 && in_mode == SFmode && in_n == 4)
24955 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24958 case BUILT_IN_LRINT:
24959 if (out_mode == SImode && out_n == 4
24960 && in_mode == DFmode && in_n == 2)
24961 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24964 case BUILT_IN_LRINTF:
24965 if (out_mode == SImode && out_n == 4
24966 && in_mode == SFmode && in_n == 4)
24967 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24974 /* Dispatch to a handler for a vectorization library. */
24975 if (ix86_veclib_handler)
24976 return (*ix86_veclib_handler)(fn, type_out, type_in);
24981 /* Handler for an SVML-style interface to
24982 a library with vectorized intrinsics. */
24985 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24988 tree fntype, new_fndecl, args;
24991 enum machine_mode el_mode, in_mode;
24994 /* The SVML is suitable for unsafe math only. */
24995 if (!flag_unsafe_math_optimizations)
24998 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24999 n = TYPE_VECTOR_SUBPARTS (type_out);
25000 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25001 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25002 if (el_mode != in_mode
25010 case BUILT_IN_LOG10:
25012 case BUILT_IN_TANH:
25014 case BUILT_IN_ATAN:
25015 case BUILT_IN_ATAN2:
25016 case BUILT_IN_ATANH:
25017 case BUILT_IN_CBRT:
25018 case BUILT_IN_SINH:
25020 case BUILT_IN_ASINH:
25021 case BUILT_IN_ASIN:
25022 case BUILT_IN_COSH:
25024 case BUILT_IN_ACOSH:
25025 case BUILT_IN_ACOS:
25026 if (el_mode != DFmode || n != 2)
25030 case BUILT_IN_EXPF:
25031 case BUILT_IN_LOGF:
25032 case BUILT_IN_LOG10F:
25033 case BUILT_IN_POWF:
25034 case BUILT_IN_TANHF:
25035 case BUILT_IN_TANF:
25036 case BUILT_IN_ATANF:
25037 case BUILT_IN_ATAN2F:
25038 case BUILT_IN_ATANHF:
25039 case BUILT_IN_CBRTF:
25040 case BUILT_IN_SINHF:
25041 case BUILT_IN_SINF:
25042 case BUILT_IN_ASINHF:
25043 case BUILT_IN_ASINF:
25044 case BUILT_IN_COSHF:
25045 case BUILT_IN_COSF:
25046 case BUILT_IN_ACOSHF:
25047 case BUILT_IN_ACOSF:
25048 if (el_mode != SFmode || n != 4)
25056 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25058 if (fn == BUILT_IN_LOGF)
25059 strcpy (name, "vmlsLn4");
25060 else if (fn == BUILT_IN_LOG)
25061 strcpy (name, "vmldLn2");
25064 sprintf (name, "vmls%s", bname+10);
25065 name[strlen (name)-1] = '4';
25068 sprintf (name, "vmld%s2", bname+10);
25070 /* Convert to uppercase. */
25074 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25075 args = TREE_CHAIN (args))
25079 fntype = build_function_type_list (type_out, type_in, NULL);
25081 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25083 /* Build a function declaration for the vectorized function. */
25084 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25085 TREE_PUBLIC (new_fndecl) = 1;
25086 DECL_EXTERNAL (new_fndecl) = 1;
25087 DECL_IS_NOVOPS (new_fndecl) = 1;
25088 TREE_READONLY (new_fndecl) = 1;
25093 /* Handler for an ACML-style interface to
25094 a library with vectorized intrinsics. */
25097 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25099 char name[20] = "__vr.._";
25100 tree fntype, new_fndecl, args;
25103 enum machine_mode el_mode, in_mode;
25106 /* The ACML is 64bits only and suitable for unsafe math only as
25107 it does not correctly support parts of IEEE with the required
25108 precision such as denormals. */
25110 || !flag_unsafe_math_optimizations)
25113 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25114 n = TYPE_VECTOR_SUBPARTS (type_out);
25115 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25116 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25117 if (el_mode != in_mode
25127 case BUILT_IN_LOG2:
25128 case BUILT_IN_LOG10:
25131 if (el_mode != DFmode
25136 case BUILT_IN_SINF:
25137 case BUILT_IN_COSF:
25138 case BUILT_IN_EXPF:
25139 case BUILT_IN_POWF:
25140 case BUILT_IN_LOGF:
25141 case BUILT_IN_LOG2F:
25142 case BUILT_IN_LOG10F:
25145 if (el_mode != SFmode
25154 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25155 sprintf (name + 7, "%s", bname+10);
25158 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25159 args = TREE_CHAIN (args))
25163 fntype = build_function_type_list (type_out, type_in, NULL);
25165 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25167 /* Build a function declaration for the vectorized function. */
25168 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25169 TREE_PUBLIC (new_fndecl) = 1;
25170 DECL_EXTERNAL (new_fndecl) = 1;
25171 DECL_IS_NOVOPS (new_fndecl) = 1;
25172 TREE_READONLY (new_fndecl) = 1;
25178 /* Returns a decl of a function that implements conversion of an integer vector
25179 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25180 side of the conversion.
25181 Return NULL_TREE if it is not available. */
25184 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25186 if (TREE_CODE (type) != VECTOR_TYPE)
25192 switch (TYPE_MODE (type))
25195 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25200 case FIX_TRUNC_EXPR:
25201 switch (TYPE_MODE (type))
25204 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25214 /* Returns a code for a target-specific builtin that implements
25215 reciprocal of the function, or NULL_TREE if not available. */
25218 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25219 bool sqrt ATTRIBUTE_UNUSED)
25221 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25222 && flag_finite_math_only && !flag_trapping_math
25223 && flag_unsafe_math_optimizations))
25227 /* Machine dependent builtins. */
25230 /* Vectorized version of sqrt to rsqrt conversion. */
25231 case IX86_BUILTIN_SQRTPS_NR:
25232 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25238 /* Normal builtins. */
25241 /* Sqrt to rsqrt conversion. */
25242 case BUILT_IN_SQRTF:
25243 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25250 /* Store OPERAND to the memory after reload is completed. This means
25251 that we can't easily use assign_stack_local. */
25253 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25257 gcc_assert (reload_completed);
25258 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25260 result = gen_rtx_MEM (mode,
25261 gen_rtx_PLUS (Pmode,
25263 GEN_INT (-RED_ZONE_SIZE)));
25264 emit_move_insn (result, operand);
25266 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25272 operand = gen_lowpart (DImode, operand);
25276 gen_rtx_SET (VOIDmode,
25277 gen_rtx_MEM (DImode,
25278 gen_rtx_PRE_DEC (DImode,
25279 stack_pointer_rtx)),
25283 gcc_unreachable ();
25285 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25294 split_di (&operand, 1, operands, operands + 1);
25296 gen_rtx_SET (VOIDmode,
25297 gen_rtx_MEM (SImode,
25298 gen_rtx_PRE_DEC (Pmode,
25299 stack_pointer_rtx)),
25302 gen_rtx_SET (VOIDmode,
25303 gen_rtx_MEM (SImode,
25304 gen_rtx_PRE_DEC (Pmode,
25305 stack_pointer_rtx)),
25310 /* Store HImodes as SImodes. */
25311 operand = gen_lowpart (SImode, operand);
25315 gen_rtx_SET (VOIDmode,
25316 gen_rtx_MEM (GET_MODE (operand),
25317 gen_rtx_PRE_DEC (SImode,
25318 stack_pointer_rtx)),
25322 gcc_unreachable ();
25324 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25329 /* Free operand from the memory. */
25331 ix86_free_from_memory (enum machine_mode mode)
25333 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25337 if (mode == DImode || TARGET_64BIT)
25341 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25342 to pop or add instruction if registers are available. */
25343 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25344 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25349 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25350 QImode must go into class Q_REGS.
25351 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25352 movdf to do mem-to-mem moves through integer regs. */
25354 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25356 enum machine_mode mode = GET_MODE (x);
25358 /* We're only allowed to return a subclass of CLASS. Many of the
25359 following checks fail for NO_REGS, so eliminate that early. */
25360 if (regclass == NO_REGS)
25363 /* All classes can load zeros. */
25364 if (x == CONST0_RTX (mode))
25367 /* Force constants into memory if we are loading a (nonzero) constant into
25368 an MMX or SSE register. This is because there are no MMX/SSE instructions
25369 to load from a constant. */
25371 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25374 /* Prefer SSE regs only, if we can use them for math. */
25375 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25376 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25378 /* Floating-point constants need more complex checks. */
25379 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25381 /* General regs can load everything. */
25382 if (reg_class_subset_p (regclass, GENERAL_REGS))
25385 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25386 zero above. We only want to wind up preferring 80387 registers if
25387 we plan on doing computation with them. */
25389 && standard_80387_constant_p (x))
25391 /* Limit class to non-sse. */
25392 if (regclass == FLOAT_SSE_REGS)
25394 if (regclass == FP_TOP_SSE_REGS)
25396 if (regclass == FP_SECOND_SSE_REGS)
25397 return FP_SECOND_REG;
25398 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25405 /* Generally when we see PLUS here, it's the function invariant
25406 (plus soft-fp const_int). Which can only be computed into general
25408 if (GET_CODE (x) == PLUS)
25409 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25411 /* QImode constants are easy to load, but non-constant QImode data
25412 must go into Q_REGS. */
25413 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25415 if (reg_class_subset_p (regclass, Q_REGS))
25417 if (reg_class_subset_p (Q_REGS, regclass))
25425 /* Discourage putting floating-point values in SSE registers unless
25426 SSE math is being used, and likewise for the 387 registers. */
25428 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25430 enum machine_mode mode = GET_MODE (x);
25432 /* Restrict the output reload class to the register bank that we are doing
25433 math on. If we would like not to return a subset of CLASS, reject this
25434 alternative: if reload cannot do this, it will still use its choice. */
25435 mode = GET_MODE (x);
25436 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25437 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25439 if (X87_FLOAT_MODE_P (mode))
25441 if (regclass == FP_TOP_SSE_REGS)
25443 else if (regclass == FP_SECOND_SSE_REGS)
25444 return FP_SECOND_REG;
25446 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25452 static enum reg_class
25453 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25454 enum machine_mode mode,
25455 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25457 /* QImode spills from non-QI registers require
25458 intermediate register on 32bit targets. */
25459 if (!in_p && mode == QImode && !TARGET_64BIT
25460 && (rclass == GENERAL_REGS
25461 || rclass == LEGACY_REGS
25462 || rclass == INDEX_REGS))
25471 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25472 regno = true_regnum (x);
25474 /* Return Q_REGS if the operand is in memory. */
25482 /* If we are copying between general and FP registers, we need a memory
25483 location. The same is true for SSE and MMX registers.
25485 To optimize register_move_cost performance, allow inline variant.
25487 The macro can't work reliably when one of the CLASSES is class containing
25488 registers from multiple units (SSE, MMX, integer). We avoid this by never
25489 combining those units in single alternative in the machine description.
25490 Ensure that this constraint holds to avoid unexpected surprises.
25492 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25493 enforce these sanity checks. */
25496 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25497 enum machine_mode mode, int strict)
25499 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25500 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25501 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25502 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25503 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25504 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25506 gcc_assert (!strict);
25510 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25513 /* ??? This is a lie. We do have moves between mmx/general, and for
25514 mmx/sse2. But by saying we need secondary memory we discourage the
25515 register allocator from using the mmx registers unless needed. */
25516 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25519 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25521 /* SSE1 doesn't have any direct moves from other classes. */
25525 /* If the target says that inter-unit moves are more expensive
25526 than moving through memory, then don't generate them. */
25527 if (!TARGET_INTER_UNIT_MOVES)
25530 /* Between SSE and general, we have moves no larger than word size. */
25531 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25539 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25540 enum machine_mode mode, int strict)
25542 return inline_secondary_memory_needed (class1, class2, mode, strict);
25545 /* Return true if the registers in CLASS cannot represent the change from
25546 modes FROM to TO. */
25549 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25550 enum reg_class regclass)
25555 /* x87 registers can't do subreg at all, as all values are reformatted
25556 to extended precision. */
25557 if (MAYBE_FLOAT_CLASS_P (regclass))
25560 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25562 /* Vector registers do not support QI or HImode loads. If we don't
25563 disallow a change to these modes, reload will assume it's ok to
25564 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25565 the vec_dupv4hi pattern. */
25566 if (GET_MODE_SIZE (from) < 4)
25569 /* Vector registers do not support subreg with nonzero offsets, which
25570 are otherwise valid for integer registers. Since we can't see
25571 whether we have a nonzero offset from here, prohibit all
25572 nonparadoxical subregs changing size. */
25573 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25580 /* Return the cost of moving data of mode M between a
25581 register and memory. A value of 2 is the default; this cost is
25582 relative to those in `REGISTER_MOVE_COST'.
25584 This function is used extensively by register_move_cost that is used to
25585 build tables at startup. Make it inline in this case.
25586 When IN is 2, return maximum of in and out move cost.
25588 If moving between registers and memory is more expensive than
25589 between two registers, you should define this macro to express the
25592 Model also increased moving costs of QImode registers in non
25596 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25600 if (FLOAT_CLASS_P (regclass))
25618 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25619 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25621 if (SSE_CLASS_P (regclass))
25624 switch (GET_MODE_SIZE (mode))
25639 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25640 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25642 if (MMX_CLASS_P (regclass))
25645 switch (GET_MODE_SIZE (mode))
25657 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25658 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25660 switch (GET_MODE_SIZE (mode))
25663 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25666 return ix86_cost->int_store[0];
25667 if (TARGET_PARTIAL_REG_DEPENDENCY
25668 && optimize_function_for_speed_p (cfun))
25669 cost = ix86_cost->movzbl_load;
25671 cost = ix86_cost->int_load[0];
25673 return MAX (cost, ix86_cost->int_store[0]);
25679 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25681 return ix86_cost->movzbl_load;
25683 return ix86_cost->int_store[0] + 4;
25688 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25689 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25691 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25692 if (mode == TFmode)
25695 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25697 cost = ix86_cost->int_load[2];
25699 cost = ix86_cost->int_store[2];
25700 return (cost * (((int) GET_MODE_SIZE (mode)
25701 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25706 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25708 return inline_memory_move_cost (mode, regclass, in);
25712 /* Return the cost of moving data from a register in class CLASS1 to
25713 one in class CLASS2.
25715 It is not required that the cost always equal 2 when FROM is the same as TO;
25716 on some machines it is expensive to move between registers if they are not
25717 general registers. */
25720 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25721 enum reg_class class2)
25723 /* In case we require secondary memory, compute cost of the store followed
25724 by load. In order to avoid bad register allocation choices, we need
25725 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25727 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25731 cost += inline_memory_move_cost (mode, class1, 2);
25732 cost += inline_memory_move_cost (mode, class2, 2);
25734 /* In case of copying from general_purpose_register we may emit multiple
25735 stores followed by single load causing memory size mismatch stall.
25736 Count this as arbitrarily high cost of 20. */
25737 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25740 /* In the case of FP/MMX moves, the registers actually overlap, and we
25741 have to switch modes in order to treat them differently. */
25742 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25743 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25749 /* Moves between SSE/MMX and integer unit are expensive. */
25750 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25751 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25753 /* ??? By keeping returned value relatively high, we limit the number
25754 of moves between integer and MMX/SSE registers for all targets.
25755 Additionally, high value prevents problem with x86_modes_tieable_p(),
25756 where integer modes in MMX/SSE registers are not tieable
25757 because of missing QImode and HImode moves to, from or between
25758 MMX/SSE registers. */
25759 return MAX (8, ix86_cost->mmxsse_to_integer);
25761 if (MAYBE_FLOAT_CLASS_P (class1))
25762 return ix86_cost->fp_move;
25763 if (MAYBE_SSE_CLASS_P (class1))
25764 return ix86_cost->sse_move;
25765 if (MAYBE_MMX_CLASS_P (class1))
25766 return ix86_cost->mmx_move;
25770 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25773 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25775 /* Flags and only flags can only hold CCmode values. */
25776 if (CC_REGNO_P (regno))
25777 return GET_MODE_CLASS (mode) == MODE_CC;
25778 if (GET_MODE_CLASS (mode) == MODE_CC
25779 || GET_MODE_CLASS (mode) == MODE_RANDOM
25780 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25782 if (FP_REGNO_P (regno))
25783 return VALID_FP_MODE_P (mode);
25784 if (SSE_REGNO_P (regno))
25786 /* We implement the move patterns for all vector modes into and
25787 out of SSE registers, even when no operation instructions
25788 are available. OImode move is available only when AVX is
25790 return ((TARGET_AVX && mode == OImode)
25791 || VALID_AVX256_REG_MODE (mode)
25792 || VALID_SSE_REG_MODE (mode)
25793 || VALID_SSE2_REG_MODE (mode)
25794 || VALID_MMX_REG_MODE (mode)
25795 || VALID_MMX_REG_MODE_3DNOW (mode));
25797 if (MMX_REGNO_P (regno))
25799 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25800 so if the register is available at all, then we can move data of
25801 the given mode into or out of it. */
25802 return (VALID_MMX_REG_MODE (mode)
25803 || VALID_MMX_REG_MODE_3DNOW (mode));
25806 if (mode == QImode)
25808 /* Take care for QImode values - they can be in non-QI regs,
25809 but then they do cause partial register stalls. */
25810 if (regno <= BX_REG || TARGET_64BIT)
25812 if (!TARGET_PARTIAL_REG_STALL)
25814 return reload_in_progress || reload_completed;
25816 /* We handle both integer and floats in the general purpose registers. */
25817 else if (VALID_INT_MODE_P (mode))
25819 else if (VALID_FP_MODE_P (mode))
25821 else if (VALID_DFP_MODE_P (mode))
25823 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25824 on to use that value in smaller contexts, this can easily force a
25825 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25826 supporting DImode, allow it. */
25827 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25833 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25834 tieable integer mode. */
25837 ix86_tieable_integer_mode_p (enum machine_mode mode)
25846 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25849 return TARGET_64BIT;
25856 /* Return true if MODE1 is accessible in a register that can hold MODE2
25857 without copying. That is, all register classes that can hold MODE2
25858 can also hold MODE1. */
25861 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25863 if (mode1 == mode2)
25866 if (ix86_tieable_integer_mode_p (mode1)
25867 && ix86_tieable_integer_mode_p (mode2))
25870 /* MODE2 being XFmode implies fp stack or general regs, which means we
25871 can tie any smaller floating point modes to it. Note that we do not
25872 tie this with TFmode. */
25873 if (mode2 == XFmode)
25874 return mode1 == SFmode || mode1 == DFmode;
25876 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25877 that we can tie it with SFmode. */
25878 if (mode2 == DFmode)
25879 return mode1 == SFmode;
25881 /* If MODE2 is only appropriate for an SSE register, then tie with
25882 any other mode acceptable to SSE registers. */
25883 if (GET_MODE_SIZE (mode2) == 16
25884 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25885 return (GET_MODE_SIZE (mode1) == 16
25886 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25888 /* If MODE2 is appropriate for an MMX register, then tie
25889 with any other mode acceptable to MMX registers. */
25890 if (GET_MODE_SIZE (mode2) == 8
25891 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25892 return (GET_MODE_SIZE (mode1) == 8
25893 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25898 /* Compute a (partial) cost for rtx X. Return true if the complete
25899 cost has been computed, and false if subexpressions should be
25900 scanned. In either case, *TOTAL contains the cost result. */
25903 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25905 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25906 enum machine_mode mode = GET_MODE (x);
25907 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25915 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25917 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25919 else if (flag_pic && SYMBOLIC_CONST (x)
25921 || (!GET_CODE (x) != LABEL_REF
25922 && (GET_CODE (x) != SYMBOL_REF
25923 || !SYMBOL_REF_LOCAL_P (x)))))
25930 if (mode == VOIDmode)
25933 switch (standard_80387_constant_p (x))
25938 default: /* Other constants */
25943 /* Start with (MEM (SYMBOL_REF)), since that's where
25944 it'll probably end up. Add a penalty for size. */
25945 *total = (COSTS_N_INSNS (1)
25946 + (flag_pic != 0 && !TARGET_64BIT)
25947 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25953 /* The zero extensions is often completely free on x86_64, so make
25954 it as cheap as possible. */
25955 if (TARGET_64BIT && mode == DImode
25956 && GET_MODE (XEXP (x, 0)) == SImode)
25958 else if (TARGET_ZERO_EXTEND_WITH_AND)
25959 *total = cost->add;
25961 *total = cost->movzx;
25965 *total = cost->movsx;
25969 if (CONST_INT_P (XEXP (x, 1))
25970 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25972 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25975 *total = cost->add;
25978 if ((value == 2 || value == 3)
25979 && cost->lea <= cost->shift_const)
25981 *total = cost->lea;
25991 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25993 if (CONST_INT_P (XEXP (x, 1)))
25995 if (INTVAL (XEXP (x, 1)) > 32)
25996 *total = cost->shift_const + COSTS_N_INSNS (2);
25998 *total = cost->shift_const * 2;
26002 if (GET_CODE (XEXP (x, 1)) == AND)
26003 *total = cost->shift_var * 2;
26005 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26010 if (CONST_INT_P (XEXP (x, 1)))
26011 *total = cost->shift_const;
26013 *total = cost->shift_var;
26018 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26020 /* ??? SSE scalar cost should be used here. */
26021 *total = cost->fmul;
26024 else if (X87_FLOAT_MODE_P (mode))
26026 *total = cost->fmul;
26029 else if (FLOAT_MODE_P (mode))
26031 /* ??? SSE vector cost should be used here. */
26032 *total = cost->fmul;
26037 rtx op0 = XEXP (x, 0);
26038 rtx op1 = XEXP (x, 1);
26040 if (CONST_INT_P (XEXP (x, 1)))
26042 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26043 for (nbits = 0; value != 0; value &= value - 1)
26047 /* This is arbitrary. */
26050 /* Compute costs correctly for widening multiplication. */
26051 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26052 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26053 == GET_MODE_SIZE (mode))
26055 int is_mulwiden = 0;
26056 enum machine_mode inner_mode = GET_MODE (op0);
26058 if (GET_CODE (op0) == GET_CODE (op1))
26059 is_mulwiden = 1, op1 = XEXP (op1, 0);
26060 else if (CONST_INT_P (op1))
26062 if (GET_CODE (op0) == SIGN_EXTEND)
26063 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26066 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26070 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26073 *total = (cost->mult_init[MODE_INDEX (mode)]
26074 + nbits * cost->mult_bit
26075 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26084 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26085 /* ??? SSE cost should be used here. */
26086 *total = cost->fdiv;
26087 else if (X87_FLOAT_MODE_P (mode))
26088 *total = cost->fdiv;
26089 else if (FLOAT_MODE_P (mode))
26090 /* ??? SSE vector cost should be used here. */
26091 *total = cost->fdiv;
26093 *total = cost->divide[MODE_INDEX (mode)];
26097 if (GET_MODE_CLASS (mode) == MODE_INT
26098 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26100 if (GET_CODE (XEXP (x, 0)) == PLUS
26101 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26102 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26103 && CONSTANT_P (XEXP (x, 1)))
26105 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26106 if (val == 2 || val == 4 || val == 8)
26108 *total = cost->lea;
26109 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26110 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26111 outer_code, speed);
26112 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26116 else if (GET_CODE (XEXP (x, 0)) == MULT
26117 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26119 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26120 if (val == 2 || val == 4 || val == 8)
26122 *total = cost->lea;
26123 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26124 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26128 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26130 *total = cost->lea;
26131 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26132 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26133 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26140 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26142 /* ??? SSE cost should be used here. */
26143 *total = cost->fadd;
26146 else if (X87_FLOAT_MODE_P (mode))
26148 *total = cost->fadd;
26151 else if (FLOAT_MODE_P (mode))
26153 /* ??? SSE vector cost should be used here. */
26154 *total = cost->fadd;
26162 if (!TARGET_64BIT && mode == DImode)
26164 *total = (cost->add * 2
26165 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26166 << (GET_MODE (XEXP (x, 0)) != DImode))
26167 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26168 << (GET_MODE (XEXP (x, 1)) != DImode)));
26174 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26176 /* ??? SSE cost should be used here. */
26177 *total = cost->fchs;
26180 else if (X87_FLOAT_MODE_P (mode))
26182 *total = cost->fchs;
26185 else if (FLOAT_MODE_P (mode))
26187 /* ??? SSE vector cost should be used here. */
26188 *total = cost->fchs;
26194 if (!TARGET_64BIT && mode == DImode)
26195 *total = cost->add * 2;
26197 *total = cost->add;
26201 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26202 && XEXP (XEXP (x, 0), 1) == const1_rtx
26203 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26204 && XEXP (x, 1) == const0_rtx)
26206 /* This kind of construct is implemented using test[bwl].
26207 Treat it as if we had an AND. */
26208 *total = (cost->add
26209 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26210 + rtx_cost (const1_rtx, outer_code, speed));
26216 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26221 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26222 /* ??? SSE cost should be used here. */
26223 *total = cost->fabs;
26224 else if (X87_FLOAT_MODE_P (mode))
26225 *total = cost->fabs;
26226 else if (FLOAT_MODE_P (mode))
26227 /* ??? SSE vector cost should be used here. */
26228 *total = cost->fabs;
26232 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26233 /* ??? SSE cost should be used here. */
26234 *total = cost->fsqrt;
26235 else if (X87_FLOAT_MODE_P (mode))
26236 *total = cost->fsqrt;
26237 else if (FLOAT_MODE_P (mode))
26238 /* ??? SSE vector cost should be used here. */
26239 *total = cost->fsqrt;
26243 if (XINT (x, 1) == UNSPEC_TP)
26254 static int current_machopic_label_num;
26256 /* Given a symbol name and its associated stub, write out the
26257 definition of the stub. */
26260 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26262 unsigned int length;
26263 char *binder_name, *symbol_name, lazy_ptr_name[32];
26264 int label = ++current_machopic_label_num;
26266 /* For 64-bit we shouldn't get here. */
26267 gcc_assert (!TARGET_64BIT);
26269 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26270 symb = (*targetm.strip_name_encoding) (symb);
26272 length = strlen (stub);
26273 binder_name = XALLOCAVEC (char, length + 32);
26274 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26276 length = strlen (symb);
26277 symbol_name = XALLOCAVEC (char, length + 32);
26278 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26280 sprintf (lazy_ptr_name, "L%d$lz", label);
26283 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26285 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26287 fprintf (file, "%s:\n", stub);
26288 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26292 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26293 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26294 fprintf (file, "\tjmp\t*%%edx\n");
26297 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26299 fprintf (file, "%s:\n", binder_name);
26303 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26304 fprintf (file, "\tpushl\t%%eax\n");
26307 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26309 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26311 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26312 fprintf (file, "%s:\n", lazy_ptr_name);
26313 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26314 fprintf (file, "\t.long %s\n", binder_name);
26318 darwin_x86_file_end (void)
26320 darwin_file_end ();
26323 #endif /* TARGET_MACHO */
26325 /* Order the registers for register allocator. */
26328 x86_order_regs_for_local_alloc (void)
26333 /* First allocate the local general purpose registers. */
26334 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26335 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26336 reg_alloc_order [pos++] = i;
26338 /* Global general purpose registers. */
26339 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26340 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26341 reg_alloc_order [pos++] = i;
26343 /* x87 registers come first in case we are doing FP math
26345 if (!TARGET_SSE_MATH)
26346 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26347 reg_alloc_order [pos++] = i;
26349 /* SSE registers. */
26350 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26351 reg_alloc_order [pos++] = i;
26352 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26353 reg_alloc_order [pos++] = i;
26355 /* x87 registers. */
26356 if (TARGET_SSE_MATH)
26357 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26358 reg_alloc_order [pos++] = i;
26360 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26361 reg_alloc_order [pos++] = i;
26363 /* Initialize the rest of array as we do not allocate some registers
26365 while (pos < FIRST_PSEUDO_REGISTER)
26366 reg_alloc_order [pos++] = 0;
26369 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26370 struct attribute_spec.handler. */
26372 ix86_handle_abi_attribute (tree *node, tree name,
26373 tree args ATTRIBUTE_UNUSED,
26374 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26376 if (TREE_CODE (*node) != FUNCTION_TYPE
26377 && TREE_CODE (*node) != METHOD_TYPE
26378 && TREE_CODE (*node) != FIELD_DECL
26379 && TREE_CODE (*node) != TYPE_DECL)
26381 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26382 IDENTIFIER_POINTER (name));
26383 *no_add_attrs = true;
26388 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26389 IDENTIFIER_POINTER (name));
26390 *no_add_attrs = true;
26394 /* Can combine regparm with all attributes but fastcall. */
26395 if (is_attribute_p ("ms_abi", name))
26397 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26399 error ("ms_abi and sysv_abi attributes are not compatible");
26404 else if (is_attribute_p ("sysv_abi", name))
26406 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26408 error ("ms_abi and sysv_abi attributes are not compatible");
26417 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26418 struct attribute_spec.handler. */
26420 ix86_handle_struct_attribute (tree *node, tree name,
26421 tree args ATTRIBUTE_UNUSED,
26422 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26425 if (DECL_P (*node))
26427 if (TREE_CODE (*node) == TYPE_DECL)
26428 type = &TREE_TYPE (*node);
26433 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26434 || TREE_CODE (*type) == UNION_TYPE)))
26436 warning (OPT_Wattributes, "%qs attribute ignored",
26437 IDENTIFIER_POINTER (name));
26438 *no_add_attrs = true;
26441 else if ((is_attribute_p ("ms_struct", name)
26442 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26443 || ((is_attribute_p ("gcc_struct", name)
26444 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26446 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26447 IDENTIFIER_POINTER (name));
26448 *no_add_attrs = true;
26455 ix86_ms_bitfield_layout_p (const_tree record_type)
26457 return (TARGET_MS_BITFIELD_LAYOUT &&
26458 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26459 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26462 /* Returns an expression indicating where the this parameter is
26463 located on entry to the FUNCTION. */
26466 x86_this_parameter (tree function)
26468 tree type = TREE_TYPE (function);
26469 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26474 const int *parm_regs;
26476 if (ix86_function_type_abi (type) == MS_ABI)
26477 parm_regs = x86_64_ms_abi_int_parameter_registers;
26479 parm_regs = x86_64_int_parameter_registers;
26480 return gen_rtx_REG (DImode, parm_regs[aggr]);
26483 nregs = ix86_function_regparm (type, function);
26485 if (nregs > 0 && !stdarg_p (type))
26489 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26490 regno = aggr ? DX_REG : CX_REG;
26498 return gen_rtx_MEM (SImode,
26499 plus_constant (stack_pointer_rtx, 4));
26502 return gen_rtx_REG (SImode, regno);
26505 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26508 /* Determine whether x86_output_mi_thunk can succeed. */
26511 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26512 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26513 HOST_WIDE_INT vcall_offset, const_tree function)
26515 /* 64-bit can handle anything. */
26519 /* For 32-bit, everything's fine if we have one free register. */
26520 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26523 /* Need a free register for vcall_offset. */
26527 /* Need a free register for GOT references. */
26528 if (flag_pic && !(*targetm.binds_local_p) (function))
26531 /* Otherwise ok. */
26535 /* Output the assembler code for a thunk function. THUNK_DECL is the
26536 declaration for the thunk function itself, FUNCTION is the decl for
26537 the target function. DELTA is an immediate constant offset to be
26538 added to THIS. If VCALL_OFFSET is nonzero, the word at
26539 *(*this + vcall_offset) should be added to THIS. */
26542 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26543 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26544 HOST_WIDE_INT vcall_offset, tree function)
26547 rtx this_param = x86_this_parameter (function);
26550 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26551 pull it in now and let DELTA benefit. */
26552 if (REG_P (this_param))
26553 this_reg = this_param;
26554 else if (vcall_offset)
26556 /* Put the this parameter into %eax. */
26557 xops[0] = this_param;
26558 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26559 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26562 this_reg = NULL_RTX;
26564 /* Adjust the this parameter by a fixed constant. */
26567 xops[0] = GEN_INT (delta);
26568 xops[1] = this_reg ? this_reg : this_param;
26571 if (!x86_64_general_operand (xops[0], DImode))
26573 tmp = gen_rtx_REG (DImode, R10_REG);
26575 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26577 xops[1] = this_param;
26579 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26582 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26585 /* Adjust the this parameter by a value stored in the vtable. */
26589 tmp = gen_rtx_REG (DImode, R10_REG);
26592 int tmp_regno = CX_REG;
26593 if (lookup_attribute ("fastcall",
26594 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26595 tmp_regno = AX_REG;
26596 tmp = gen_rtx_REG (SImode, tmp_regno);
26599 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26601 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26603 /* Adjust the this parameter. */
26604 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26605 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26607 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26608 xops[0] = GEN_INT (vcall_offset);
26610 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26611 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26613 xops[1] = this_reg;
26614 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26617 /* If necessary, drop THIS back to its stack slot. */
26618 if (this_reg && this_reg != this_param)
26620 xops[0] = this_reg;
26621 xops[1] = this_param;
26622 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26625 xops[0] = XEXP (DECL_RTL (function), 0);
26628 if (!flag_pic || (*targetm.binds_local_p) (function))
26629 output_asm_insn ("jmp\t%P0", xops);
26630 /* All thunks should be in the same object as their target,
26631 and thus binds_local_p should be true. */
26632 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26633 gcc_unreachable ();
26636 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26637 tmp = gen_rtx_CONST (Pmode, tmp);
26638 tmp = gen_rtx_MEM (QImode, tmp);
26640 output_asm_insn ("jmp\t%A0", xops);
26645 if (!flag_pic || (*targetm.binds_local_p) (function))
26646 output_asm_insn ("jmp\t%P0", xops);
26651 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26652 tmp = (gen_rtx_SYMBOL_REF
26654 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26655 tmp = gen_rtx_MEM (QImode, tmp);
26657 output_asm_insn ("jmp\t%0", xops);
26660 #endif /* TARGET_MACHO */
26662 tmp = gen_rtx_REG (SImode, CX_REG);
26663 output_set_got (tmp, NULL_RTX);
26666 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26667 output_asm_insn ("jmp\t{*}%1", xops);
26673 x86_file_start (void)
26675 default_file_start ();
26677 darwin_file_start ();
26679 if (X86_FILE_START_VERSION_DIRECTIVE)
26680 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26681 if (X86_FILE_START_FLTUSED)
26682 fputs ("\t.global\t__fltused\n", asm_out_file);
26683 if (ix86_asm_dialect == ASM_INTEL)
26684 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26688 x86_field_alignment (tree field, int computed)
26690 enum machine_mode mode;
26691 tree type = TREE_TYPE (field);
26693 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26695 mode = TYPE_MODE (strip_array_types (type));
26696 if (mode == DFmode || mode == DCmode
26697 || GET_MODE_CLASS (mode) == MODE_INT
26698 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26699 return MIN (32, computed);
26703 /* Output assembler code to FILE to increment profiler label # LABELNO
26704 for profiling a function entry. */
26706 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26710 #ifndef NO_PROFILE_COUNTERS
26711 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26714 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26715 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26717 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26721 #ifndef NO_PROFILE_COUNTERS
26722 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26723 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26725 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26729 #ifndef NO_PROFILE_COUNTERS
26730 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26731 PROFILE_COUNT_REGISTER);
26733 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26737 /* We don't have exact information about the insn sizes, but we may assume
26738 quite safely that we are informed about all 1 byte insns and memory
26739 address sizes. This is enough to eliminate unnecessary padding in
26743 min_insn_size (rtx insn)
26747 if (!INSN_P (insn) || !active_insn_p (insn))
26750 /* Discard alignments we've emit and jump instructions. */
26751 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26752 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26755 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26756 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26759 /* Important case - calls are always 5 bytes.
26760 It is common to have many calls in the row. */
26762 && symbolic_reference_mentioned_p (PATTERN (insn))
26763 && !SIBLING_CALL_P (insn))
26765 if (get_attr_length (insn) <= 1)
26768 /* For normal instructions we may rely on the sizes of addresses
26769 and the presence of symbol to require 4 bytes of encoding.
26770 This is not the case for jumps where references are PC relative. */
26771 if (!JUMP_P (insn))
26773 l = get_attr_length_address (insn);
26774 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26783 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26787 ix86_avoid_jump_misspredicts (void)
26789 rtx insn, start = get_insns ();
26790 int nbytes = 0, njumps = 0;
26793 /* Look for all minimal intervals of instructions containing 4 jumps.
26794 The intervals are bounded by START and INSN. NBYTES is the total
26795 size of instructions in the interval including INSN and not including
26796 START. When the NBYTES is smaller than 16 bytes, it is possible
26797 that the end of START and INSN ends up in the same 16byte page.
26799 The smallest offset in the page INSN can start is the case where START
26800 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26801 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26803 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26806 nbytes += min_insn_size (insn);
26808 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26809 INSN_UID (insn), min_insn_size (insn));
26811 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26812 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26820 start = NEXT_INSN (start);
26821 if ((JUMP_P (start)
26822 && GET_CODE (PATTERN (start)) != ADDR_VEC
26823 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26825 njumps--, isjump = 1;
26828 nbytes -= min_insn_size (start);
26830 gcc_assert (njumps >= 0);
26832 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26833 INSN_UID (start), INSN_UID (insn), nbytes);
26835 if (njumps == 3 && isjump && nbytes < 16)
26837 int padsize = 15 - nbytes + min_insn_size (insn);
26840 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26841 INSN_UID (insn), padsize);
26842 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26847 /* AMD Athlon works faster
26848 when RET is not destination of conditional jump or directly preceded
26849 by other jump instruction. We avoid the penalty by inserting NOP just
26850 before the RET instructions in such cases. */
26852 ix86_pad_returns (void)
26857 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26859 basic_block bb = e->src;
26860 rtx ret = BB_END (bb);
26862 bool replace = false;
26864 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26865 || optimize_bb_for_size_p (bb))
26867 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26868 if (active_insn_p (prev) || LABEL_P (prev))
26870 if (prev && LABEL_P (prev))
26875 FOR_EACH_EDGE (e, ei, bb->preds)
26876 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26877 && !(e->flags & EDGE_FALLTHRU))
26882 prev = prev_active_insn (ret);
26884 && ((JUMP_P (prev) && any_condjump_p (prev))
26887 /* Empty functions get branch mispredict even when the jump destination
26888 is not visible to us. */
26889 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26894 emit_insn_before (gen_return_internal_long (), ret);
26900 /* Implement machine specific optimizations. We implement padding of returns
26901 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26905 if (TARGET_PAD_RETURNS && optimize
26906 && optimize_function_for_speed_p (cfun))
26907 ix86_pad_returns ();
26908 if (TARGET_FOUR_JUMP_LIMIT && optimize
26909 && optimize_function_for_speed_p (cfun))
26910 ix86_avoid_jump_misspredicts ();
26913 /* Return nonzero when QImode register that must be represented via REX prefix
26916 x86_extended_QIreg_mentioned_p (rtx insn)
26919 extract_insn_cached (insn);
26920 for (i = 0; i < recog_data.n_operands; i++)
26921 if (REG_P (recog_data.operand[i])
26922 && REGNO (recog_data.operand[i]) > BX_REG)
26927 /* Return nonzero when P points to register encoded via REX prefix.
26928 Called via for_each_rtx. */
26930 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26932 unsigned int regno;
26935 regno = REGNO (*p);
26936 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26939 /* Return true when INSN mentions register that must be encoded using REX
26942 x86_extended_reg_mentioned_p (rtx insn)
26944 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26945 extended_reg_mentioned_1, NULL);
26948 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26949 optabs would emit if we didn't have TFmode patterns. */
26952 x86_emit_floatuns (rtx operands[2])
26954 rtx neglab, donelab, i0, i1, f0, in, out;
26955 enum machine_mode mode, inmode;
26957 inmode = GET_MODE (operands[1]);
26958 gcc_assert (inmode == SImode || inmode == DImode);
26961 in = force_reg (inmode, operands[1]);
26962 mode = GET_MODE (out);
26963 neglab = gen_label_rtx ();
26964 donelab = gen_label_rtx ();
26965 f0 = gen_reg_rtx (mode);
26967 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26969 expand_float (out, in, 0);
26971 emit_jump_insn (gen_jump (donelab));
26974 emit_label (neglab);
26976 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26978 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26980 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26982 expand_float (f0, i0, 0);
26984 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26986 emit_label (donelab);
26989 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26990 with all elements equal to VAR. Return true if successful. */
26993 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26994 rtx target, rtx val)
26996 enum machine_mode hmode, smode, wsmode, wvmode;
27011 val = force_reg (GET_MODE_INNER (mode), val);
27012 x = gen_rtx_VEC_DUPLICATE (mode, val);
27013 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27019 if (TARGET_SSE || TARGET_3DNOW_A)
27021 val = gen_lowpart (SImode, val);
27022 x = gen_rtx_TRUNCATE (HImode, val);
27023 x = gen_rtx_VEC_DUPLICATE (mode, x);
27024 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27046 /* Extend HImode to SImode using a paradoxical SUBREG. */
27047 tmp1 = gen_reg_rtx (SImode);
27048 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27049 /* Insert the SImode value as low element of V4SImode vector. */
27050 tmp2 = gen_reg_rtx (V4SImode);
27051 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27052 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27053 CONST0_RTX (V4SImode),
27055 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27056 /* Cast the V4SImode vector back to a V8HImode vector. */
27057 tmp1 = gen_reg_rtx (V8HImode);
27058 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27059 /* Duplicate the low short through the whole low SImode word. */
27060 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27061 /* Cast the V8HImode vector back to a V4SImode vector. */
27062 tmp2 = gen_reg_rtx (V4SImode);
27063 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27064 /* Replicate the low element of the V4SImode vector. */
27065 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27066 /* Cast the V2SImode back to V8HImode, and store in target. */
27067 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27078 /* Extend QImode to SImode using a paradoxical SUBREG. */
27079 tmp1 = gen_reg_rtx (SImode);
27080 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27081 /* Insert the SImode value as low element of V4SImode vector. */
27082 tmp2 = gen_reg_rtx (V4SImode);
27083 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27084 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27085 CONST0_RTX (V4SImode),
27087 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27088 /* Cast the V4SImode vector back to a V16QImode vector. */
27089 tmp1 = gen_reg_rtx (V16QImode);
27090 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27091 /* Duplicate the low byte through the whole low SImode word. */
27092 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27093 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27094 /* Cast the V16QImode vector back to a V4SImode vector. */
27095 tmp2 = gen_reg_rtx (V4SImode);
27096 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27097 /* Replicate the low element of the V4SImode vector. */
27098 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27099 /* Cast the V2SImode back to V16QImode, and store in target. */
27100 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27108 /* Replicate the value once into the next wider mode and recurse. */
27109 val = convert_modes (wsmode, smode, val, true);
27110 x = expand_simple_binop (wsmode, ASHIFT, val,
27111 GEN_INT (GET_MODE_BITSIZE (smode)),
27112 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27113 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27115 x = gen_reg_rtx (wvmode);
27116 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27117 gcc_unreachable ();
27118 emit_move_insn (target, gen_lowpart (mode, x));
27141 rtx tmp = gen_reg_rtx (hmode);
27142 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27143 emit_insn (gen_rtx_SET (VOIDmode, target,
27144 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27153 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27154 whose ONE_VAR element is VAR, and other elements are zero. Return true
27158 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27159 rtx target, rtx var, int one_var)
27161 enum machine_mode vsimode;
27164 bool use_vector_set = false;
27169 /* For SSE4.1, we normally use vector set. But if the second
27170 element is zero and inter-unit moves are OK, we use movq
27172 use_vector_set = (TARGET_64BIT
27174 && !(TARGET_INTER_UNIT_MOVES
27180 use_vector_set = TARGET_SSE4_1;
27183 use_vector_set = TARGET_SSE2;
27186 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27193 use_vector_set = TARGET_AVX;
27196 /* Use ix86_expand_vector_set in 64bit mode only. */
27197 use_vector_set = TARGET_AVX && TARGET_64BIT;
27203 if (use_vector_set)
27205 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27206 var = force_reg (GET_MODE_INNER (mode), var);
27207 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27223 var = force_reg (GET_MODE_INNER (mode), var);
27224 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27225 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27230 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27231 new_target = gen_reg_rtx (mode);
27233 new_target = target;
27234 var = force_reg (GET_MODE_INNER (mode), var);
27235 x = gen_rtx_VEC_DUPLICATE (mode, var);
27236 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27237 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27240 /* We need to shuffle the value to the correct position, so
27241 create a new pseudo to store the intermediate result. */
27243 /* With SSE2, we can use the integer shuffle insns. */
27244 if (mode != V4SFmode && TARGET_SSE2)
27246 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27248 GEN_INT (one_var == 1 ? 0 : 1),
27249 GEN_INT (one_var == 2 ? 0 : 1),
27250 GEN_INT (one_var == 3 ? 0 : 1)));
27251 if (target != new_target)
27252 emit_move_insn (target, new_target);
27256 /* Otherwise convert the intermediate result to V4SFmode and
27257 use the SSE1 shuffle instructions. */
27258 if (mode != V4SFmode)
27260 tmp = gen_reg_rtx (V4SFmode);
27261 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27266 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27268 GEN_INT (one_var == 1 ? 0 : 1),
27269 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27270 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27272 if (mode != V4SFmode)
27273 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27274 else if (tmp != target)
27275 emit_move_insn (target, tmp);
27277 else if (target != new_target)
27278 emit_move_insn (target, new_target);
27283 vsimode = V4SImode;
27289 vsimode = V2SImode;
27295 /* Zero extend the variable element to SImode and recurse. */
27296 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27298 x = gen_reg_rtx (vsimode);
27299 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27301 gcc_unreachable ();
27303 emit_move_insn (target, gen_lowpart (mode, x));
27311 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27312 consisting of the values in VALS. It is known that all elements
27313 except ONE_VAR are constants. Return true if successful. */
27316 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27317 rtx target, rtx vals, int one_var)
27319 rtx var = XVECEXP (vals, 0, one_var);
27320 enum machine_mode wmode;
27323 const_vec = copy_rtx (vals);
27324 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27325 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27333 /* For the two element vectors, it's just as easy to use
27334 the general case. */
27338 /* Use ix86_expand_vector_set in 64bit mode only. */
27361 /* There's no way to set one QImode entry easily. Combine
27362 the variable value with its adjacent constant value, and
27363 promote to an HImode set. */
27364 x = XVECEXP (vals, 0, one_var ^ 1);
27367 var = convert_modes (HImode, QImode, var, true);
27368 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27369 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27370 x = GEN_INT (INTVAL (x) & 0xff);
27374 var = convert_modes (HImode, QImode, var, true);
27375 x = gen_int_mode (INTVAL (x) << 8, HImode);
27377 if (x != const0_rtx)
27378 var = expand_simple_binop (HImode, IOR, var, x, var,
27379 1, OPTAB_LIB_WIDEN);
27381 x = gen_reg_rtx (wmode);
27382 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27383 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27385 emit_move_insn (target, gen_lowpart (mode, x));
27392 emit_move_insn (target, const_vec);
27393 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27397 /* A subroutine of ix86_expand_vector_init_general. Use vector
27398 concatenate to handle the most general case: all values variable,
27399 and none identical. */
27402 ix86_expand_vector_init_concat (enum machine_mode mode,
27403 rtx target, rtx *ops, int n)
27405 enum machine_mode cmode, hmode = VOIDmode;
27406 rtx first[8], second[4];
27446 gcc_unreachable ();
27449 if (!register_operand (ops[1], cmode))
27450 ops[1] = force_reg (cmode, ops[1]);
27451 if (!register_operand (ops[0], cmode))
27452 ops[0] = force_reg (cmode, ops[0]);
27453 emit_insn (gen_rtx_SET (VOIDmode, target,
27454 gen_rtx_VEC_CONCAT (mode, ops[0],
27474 gcc_unreachable ();
27490 gcc_unreachable ();
27495 /* FIXME: We process inputs backward to help RA. PR 36222. */
27498 for (; i > 0; i -= 2, j--)
27500 first[j] = gen_reg_rtx (cmode);
27501 v = gen_rtvec (2, ops[i - 1], ops[i]);
27502 ix86_expand_vector_init (false, first[j],
27503 gen_rtx_PARALLEL (cmode, v));
27509 gcc_assert (hmode != VOIDmode);
27510 for (i = j = 0; i < n; i += 2, j++)
27512 second[j] = gen_reg_rtx (hmode);
27513 ix86_expand_vector_init_concat (hmode, second [j],
27517 ix86_expand_vector_init_concat (mode, target, second, n);
27520 ix86_expand_vector_init_concat (mode, target, first, n);
27524 gcc_unreachable ();
27528 /* A subroutine of ix86_expand_vector_init_general. Use vector
27529 interleave to handle the most general case: all values variable,
27530 and none identical. */
27533 ix86_expand_vector_init_interleave (enum machine_mode mode,
27534 rtx target, rtx *ops, int n)
27536 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27539 rtx (*gen_load_even) (rtx, rtx, rtx);
27540 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27541 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27546 gen_load_even = gen_vec_setv8hi;
27547 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27548 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27549 inner_mode = HImode;
27550 first_imode = V4SImode;
27551 second_imode = V2DImode;
27552 third_imode = VOIDmode;
27555 gen_load_even = gen_vec_setv16qi;
27556 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27557 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27558 inner_mode = QImode;
27559 first_imode = V8HImode;
27560 second_imode = V4SImode;
27561 third_imode = V2DImode;
27564 gcc_unreachable ();
27567 for (i = 0; i < n; i++)
27569 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27570 op0 = gen_reg_rtx (SImode);
27571 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27573 /* Insert the SImode value as low element of V4SImode vector. */
27574 op1 = gen_reg_rtx (V4SImode);
27575 op0 = gen_rtx_VEC_MERGE (V4SImode,
27576 gen_rtx_VEC_DUPLICATE (V4SImode,
27578 CONST0_RTX (V4SImode),
27580 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27582 /* Cast the V4SImode vector back to a vector in orignal mode. */
27583 op0 = gen_reg_rtx (mode);
27584 emit_move_insn (op0, gen_lowpart (mode, op1));
27586 /* Load even elements into the second positon. */
27587 emit_insn ((*gen_load_even) (op0,
27588 force_reg (inner_mode,
27592 /* Cast vector to FIRST_IMODE vector. */
27593 ops[i] = gen_reg_rtx (first_imode);
27594 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27597 /* Interleave low FIRST_IMODE vectors. */
27598 for (i = j = 0; i < n; i += 2, j++)
27600 op0 = gen_reg_rtx (first_imode);
27601 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27603 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27604 ops[j] = gen_reg_rtx (second_imode);
27605 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27608 /* Interleave low SECOND_IMODE vectors. */
27609 switch (second_imode)
27612 for (i = j = 0; i < n / 2; i += 2, j++)
27614 op0 = gen_reg_rtx (second_imode);
27615 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27618 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27620 ops[j] = gen_reg_rtx (third_imode);
27621 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27623 second_imode = V2DImode;
27624 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27628 op0 = gen_reg_rtx (second_imode);
27629 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27632 /* Cast the SECOND_IMODE vector back to a vector on original
27634 emit_insn (gen_rtx_SET (VOIDmode, target,
27635 gen_lowpart (mode, op0)));
27639 gcc_unreachable ();
27643 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27644 all values variable, and none identical. */
27647 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27648 rtx target, rtx vals)
27650 rtx ops[32], op0, op1;
27651 enum machine_mode half_mode = VOIDmode;
27658 if (!mmx_ok && !TARGET_SSE)
27670 n = GET_MODE_NUNITS (mode);
27671 for (i = 0; i < n; i++)
27672 ops[i] = XVECEXP (vals, 0, i);
27673 ix86_expand_vector_init_concat (mode, target, ops, n);
27677 half_mode = V16QImode;
27681 half_mode = V8HImode;
27685 n = GET_MODE_NUNITS (mode);
27686 for (i = 0; i < n; i++)
27687 ops[i] = XVECEXP (vals, 0, i);
27688 op0 = gen_reg_rtx (half_mode);
27689 op1 = gen_reg_rtx (half_mode);
27690 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27692 ix86_expand_vector_init_interleave (half_mode, op1,
27693 &ops [n >> 1], n >> 2);
27694 emit_insn (gen_rtx_SET (VOIDmode, target,
27695 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27699 if (!TARGET_SSE4_1)
27707 /* Don't use ix86_expand_vector_init_interleave if we can't
27708 move from GPR to SSE register directly. */
27709 if (!TARGET_INTER_UNIT_MOVES)
27712 n = GET_MODE_NUNITS (mode);
27713 for (i = 0; i < n; i++)
27714 ops[i] = XVECEXP (vals, 0, i);
27715 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27723 gcc_unreachable ();
27727 int i, j, n_elts, n_words, n_elt_per_word;
27728 enum machine_mode inner_mode;
27729 rtx words[4], shift;
27731 inner_mode = GET_MODE_INNER (mode);
27732 n_elts = GET_MODE_NUNITS (mode);
27733 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27734 n_elt_per_word = n_elts / n_words;
27735 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27737 for (i = 0; i < n_words; ++i)
27739 rtx word = NULL_RTX;
27741 for (j = 0; j < n_elt_per_word; ++j)
27743 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27744 elt = convert_modes (word_mode, inner_mode, elt, true);
27750 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27751 word, 1, OPTAB_LIB_WIDEN);
27752 word = expand_simple_binop (word_mode, IOR, word, elt,
27753 word, 1, OPTAB_LIB_WIDEN);
27761 emit_move_insn (target, gen_lowpart (mode, words[0]));
27762 else if (n_words == 2)
27764 rtx tmp = gen_reg_rtx (mode);
27765 emit_clobber (tmp);
27766 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27767 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27768 emit_move_insn (target, tmp);
27770 else if (n_words == 4)
27772 rtx tmp = gen_reg_rtx (V4SImode);
27773 gcc_assert (word_mode == SImode);
27774 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27775 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27776 emit_move_insn (target, gen_lowpart (mode, tmp));
27779 gcc_unreachable ();
27783 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27784 instructions unless MMX_OK is true. */
27787 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27789 enum machine_mode mode = GET_MODE (target);
27790 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27791 int n_elts = GET_MODE_NUNITS (mode);
27792 int n_var = 0, one_var = -1;
27793 bool all_same = true, all_const_zero = true;
27797 for (i = 0; i < n_elts; ++i)
27799 x = XVECEXP (vals, 0, i);
27800 if (!(CONST_INT_P (x)
27801 || GET_CODE (x) == CONST_DOUBLE
27802 || GET_CODE (x) == CONST_FIXED))
27803 n_var++, one_var = i;
27804 else if (x != CONST0_RTX (inner_mode))
27805 all_const_zero = false;
27806 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27810 /* Constants are best loaded from the constant pool. */
27813 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27817 /* If all values are identical, broadcast the value. */
27819 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27820 XVECEXP (vals, 0, 0)))
27823 /* Values where only one field is non-constant are best loaded from
27824 the pool and overwritten via move later. */
27828 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27829 XVECEXP (vals, 0, one_var),
27833 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27837 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27841 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27843 enum machine_mode mode = GET_MODE (target);
27844 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27845 enum machine_mode half_mode;
27846 bool use_vec_merge = false;
27848 static rtx (*gen_extract[6][2]) (rtx, rtx)
27850 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27851 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27852 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27853 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27854 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27855 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27857 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27859 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27860 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27861 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27862 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27863 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27864 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27874 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27875 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27877 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27879 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27880 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27886 use_vec_merge = TARGET_SSE4_1;
27894 /* For the two element vectors, we implement a VEC_CONCAT with
27895 the extraction of the other element. */
27897 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27898 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27901 op0 = val, op1 = tmp;
27903 op0 = tmp, op1 = val;
27905 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27906 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27911 use_vec_merge = TARGET_SSE4_1;
27918 use_vec_merge = true;
27922 /* tmp = target = A B C D */
27923 tmp = copy_to_reg (target);
27924 /* target = A A B B */
27925 emit_insn (gen_sse_unpcklps (target, target, target));
27926 /* target = X A B B */
27927 ix86_expand_vector_set (false, target, val, 0);
27928 /* target = A X C D */
27929 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27930 GEN_INT (1), GEN_INT (0),
27931 GEN_INT (2+4), GEN_INT (3+4)));
27935 /* tmp = target = A B C D */
27936 tmp = copy_to_reg (target);
27937 /* tmp = X B C D */
27938 ix86_expand_vector_set (false, tmp, val, 0);
27939 /* target = A B X D */
27940 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27941 GEN_INT (0), GEN_INT (1),
27942 GEN_INT (0+4), GEN_INT (3+4)));
27946 /* tmp = target = A B C D */
27947 tmp = copy_to_reg (target);
27948 /* tmp = X B C D */
27949 ix86_expand_vector_set (false, tmp, val, 0);
27950 /* target = A B X D */
27951 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27952 GEN_INT (0), GEN_INT (1),
27953 GEN_INT (2+4), GEN_INT (0+4)));
27957 gcc_unreachable ();
27962 use_vec_merge = TARGET_SSE4_1;
27966 /* Element 0 handled by vec_merge below. */
27969 use_vec_merge = true;
27975 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27976 store into element 0, then shuffle them back. */
27980 order[0] = GEN_INT (elt);
27981 order[1] = const1_rtx;
27982 order[2] = const2_rtx;
27983 order[3] = GEN_INT (3);
27984 order[elt] = const0_rtx;
27986 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27987 order[1], order[2], order[3]));
27989 ix86_expand_vector_set (false, target, val, 0);
27991 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27992 order[1], order[2], order[3]));
27996 /* For SSE1, we have to reuse the V4SF code. */
27997 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27998 gen_lowpart (SFmode, val), elt);
28003 use_vec_merge = TARGET_SSE2;
28006 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28010 use_vec_merge = TARGET_SSE4_1;
28017 half_mode = V16QImode;
28023 half_mode = V8HImode;
28029 half_mode = V4SImode;
28035 half_mode = V2DImode;
28041 half_mode = V4SFmode;
28047 half_mode = V2DFmode;
28053 /* Compute offset. */
28057 gcc_assert (i <= 1);
28059 /* Extract the half. */
28060 tmp = gen_reg_rtx (half_mode);
28061 emit_insn ((*gen_extract[j][i]) (tmp, target));
28063 /* Put val in tmp at elt. */
28064 ix86_expand_vector_set (false, tmp, val, elt);
28067 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28076 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28077 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28078 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28082 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28084 emit_move_insn (mem, target);
28086 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28087 emit_move_insn (tmp, val);
28089 emit_move_insn (target, mem);
28094 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28096 enum machine_mode mode = GET_MODE (vec);
28097 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28098 bool use_vec_extr = false;
28111 use_vec_extr = true;
28115 use_vec_extr = TARGET_SSE4_1;
28127 tmp = gen_reg_rtx (mode);
28128 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28129 GEN_INT (elt), GEN_INT (elt),
28130 GEN_INT (elt+4), GEN_INT (elt+4)));
28134 tmp = gen_reg_rtx (mode);
28135 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28139 gcc_unreachable ();
28142 use_vec_extr = true;
28147 use_vec_extr = TARGET_SSE4_1;
28161 tmp = gen_reg_rtx (mode);
28162 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28163 GEN_INT (elt), GEN_INT (elt),
28164 GEN_INT (elt), GEN_INT (elt)));
28168 tmp = gen_reg_rtx (mode);
28169 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28173 gcc_unreachable ();
28176 use_vec_extr = true;
28181 /* For SSE1, we have to reuse the V4SF code. */
28182 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28183 gen_lowpart (V4SFmode, vec), elt);
28189 use_vec_extr = TARGET_SSE2;
28192 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28196 use_vec_extr = TARGET_SSE4_1;
28200 /* ??? Could extract the appropriate HImode element and shift. */
28207 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28208 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28210 /* Let the rtl optimizers know about the zero extension performed. */
28211 if (inner_mode == QImode || inner_mode == HImode)
28213 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28214 target = gen_lowpart (SImode, target);
28217 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28221 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28223 emit_move_insn (mem, vec);
28225 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28226 emit_move_insn (target, tmp);
28230 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28231 pattern to reduce; DEST is the destination; IN is the input vector. */
28234 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28236 rtx tmp1, tmp2, tmp3;
28238 tmp1 = gen_reg_rtx (V4SFmode);
28239 tmp2 = gen_reg_rtx (V4SFmode);
28240 tmp3 = gen_reg_rtx (V4SFmode);
28242 emit_insn (gen_sse_movhlps (tmp1, in, in));
28243 emit_insn (fn (tmp2, tmp1, in));
28245 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28246 GEN_INT (1), GEN_INT (1),
28247 GEN_INT (1+4), GEN_INT (1+4)));
28248 emit_insn (fn (dest, tmp2, tmp3));
28251 /* Target hook for scalar_mode_supported_p. */
28253 ix86_scalar_mode_supported_p (enum machine_mode mode)
28255 if (DECIMAL_FLOAT_MODE_P (mode))
28257 else if (mode == TFmode)
28260 return default_scalar_mode_supported_p (mode);
28263 /* Implements target hook vector_mode_supported_p. */
28265 ix86_vector_mode_supported_p (enum machine_mode mode)
28267 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28269 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28271 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28273 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28275 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28280 /* Target hook for c_mode_for_suffix. */
28281 static enum machine_mode
28282 ix86_c_mode_for_suffix (char suffix)
28292 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28294 We do this in the new i386 backend to maintain source compatibility
28295 with the old cc0-based compiler. */
28298 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28299 tree inputs ATTRIBUTE_UNUSED,
28302 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28304 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28309 /* Implements target vector targetm.asm.encode_section_info. This
28310 is not used by netware. */
28312 static void ATTRIBUTE_UNUSED
28313 ix86_encode_section_info (tree decl, rtx rtl, int first)
28315 default_encode_section_info (decl, rtl, first);
28317 if (TREE_CODE (decl) == VAR_DECL
28318 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28319 && ix86_in_large_data_p (decl))
28320 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28323 /* Worker function for REVERSE_CONDITION. */
28326 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28328 return (mode != CCFPmode && mode != CCFPUmode
28329 ? reverse_condition (code)
28330 : reverse_condition_maybe_unordered (code));
28333 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28337 output_387_reg_move (rtx insn, rtx *operands)
28339 if (REG_P (operands[0]))
28341 if (REG_P (operands[1])
28342 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28344 if (REGNO (operands[0]) == FIRST_STACK_REG)
28345 return output_387_ffreep (operands, 0);
28346 return "fstp\t%y0";
28348 if (STACK_TOP_P (operands[0]))
28349 return "fld%z1\t%y1";
28352 else if (MEM_P (operands[0]))
28354 gcc_assert (REG_P (operands[1]));
28355 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28356 return "fstp%z0\t%y0";
28359 /* There is no non-popping store to memory for XFmode.
28360 So if we need one, follow the store with a load. */
28361 if (GET_MODE (operands[0]) == XFmode)
28362 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28364 return "fst%z0\t%y0";
28371 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28372 FP status register is set. */
28375 ix86_emit_fp_unordered_jump (rtx label)
28377 rtx reg = gen_reg_rtx (HImode);
28380 emit_insn (gen_x86_fnstsw_1 (reg));
28382 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28384 emit_insn (gen_x86_sahf_1 (reg));
28386 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28387 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28391 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28393 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28394 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28397 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28398 gen_rtx_LABEL_REF (VOIDmode, label),
28400 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28402 emit_jump_insn (temp);
28403 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28406 /* Output code to perform a log1p XFmode calculation. */
28408 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28410 rtx label1 = gen_label_rtx ();
28411 rtx label2 = gen_label_rtx ();
28413 rtx tmp = gen_reg_rtx (XFmode);
28414 rtx tmp2 = gen_reg_rtx (XFmode);
28416 emit_insn (gen_absxf2 (tmp, op1));
28417 emit_insn (gen_cmpxf (tmp,
28418 CONST_DOUBLE_FROM_REAL_VALUE (
28419 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28421 emit_jump_insn (gen_bge (label1));
28423 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28424 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28425 emit_jump (label2);
28427 emit_label (label1);
28428 emit_move_insn (tmp, CONST1_RTX (XFmode));
28429 emit_insn (gen_addxf3 (tmp, op1, tmp));
28430 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28431 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28433 emit_label (label2);
28436 /* Output code to perform a Newton-Rhapson approximation of a single precision
28437 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28439 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28441 rtx x0, x1, e0, e1, two;
28443 x0 = gen_reg_rtx (mode);
28444 e0 = gen_reg_rtx (mode);
28445 e1 = gen_reg_rtx (mode);
28446 x1 = gen_reg_rtx (mode);
28448 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28450 if (VECTOR_MODE_P (mode))
28451 two = ix86_build_const_vector (SFmode, true, two);
28453 two = force_reg (mode, two);
28455 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28457 /* x0 = rcp(b) estimate */
28458 emit_insn (gen_rtx_SET (VOIDmode, x0,
28459 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28462 emit_insn (gen_rtx_SET (VOIDmode, e0,
28463 gen_rtx_MULT (mode, x0, b)));
28465 emit_insn (gen_rtx_SET (VOIDmode, e1,
28466 gen_rtx_MINUS (mode, two, e0)));
28468 emit_insn (gen_rtx_SET (VOIDmode, x1,
28469 gen_rtx_MULT (mode, x0, e1)));
28471 emit_insn (gen_rtx_SET (VOIDmode, res,
28472 gen_rtx_MULT (mode, a, x1)));
28475 /* Output code to perform a Newton-Rhapson approximation of a
28476 single precision floating point [reciprocal] square root. */
28478 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28481 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28484 x0 = gen_reg_rtx (mode);
28485 e0 = gen_reg_rtx (mode);
28486 e1 = gen_reg_rtx (mode);
28487 e2 = gen_reg_rtx (mode);
28488 e3 = gen_reg_rtx (mode);
28490 real_from_integer (&r, VOIDmode, -3, -1, 0);
28491 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28493 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28494 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28496 if (VECTOR_MODE_P (mode))
28498 mthree = ix86_build_const_vector (SFmode, true, mthree);
28499 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28502 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28503 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28505 /* x0 = rsqrt(a) estimate */
28506 emit_insn (gen_rtx_SET (VOIDmode, x0,
28507 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28510 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28515 zero = gen_reg_rtx (mode);
28516 mask = gen_reg_rtx (mode);
28518 zero = force_reg (mode, CONST0_RTX(mode));
28519 emit_insn (gen_rtx_SET (VOIDmode, mask,
28520 gen_rtx_NE (mode, zero, a)));
28522 emit_insn (gen_rtx_SET (VOIDmode, x0,
28523 gen_rtx_AND (mode, x0, mask)));
28527 emit_insn (gen_rtx_SET (VOIDmode, e0,
28528 gen_rtx_MULT (mode, x0, a)));
28530 emit_insn (gen_rtx_SET (VOIDmode, e1,
28531 gen_rtx_MULT (mode, e0, x0)));
28534 mthree = force_reg (mode, mthree);
28535 emit_insn (gen_rtx_SET (VOIDmode, e2,
28536 gen_rtx_PLUS (mode, e1, mthree)));
28538 mhalf = force_reg (mode, mhalf);
28540 /* e3 = -.5 * x0 */
28541 emit_insn (gen_rtx_SET (VOIDmode, e3,
28542 gen_rtx_MULT (mode, x0, mhalf)));
28544 /* e3 = -.5 * e0 */
28545 emit_insn (gen_rtx_SET (VOIDmode, e3,
28546 gen_rtx_MULT (mode, e0, mhalf)));
28547 /* ret = e2 * e3 */
28548 emit_insn (gen_rtx_SET (VOIDmode, res,
28549 gen_rtx_MULT (mode, e2, e3)));
28552 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28554 static void ATTRIBUTE_UNUSED
28555 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28558 /* With Binutils 2.15, the "@unwind" marker must be specified on
28559 every occurrence of the ".eh_frame" section, not just the first
28562 && strcmp (name, ".eh_frame") == 0)
28564 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28565 flags & SECTION_WRITE ? "aw" : "a");
28568 default_elf_asm_named_section (name, flags, decl);
28571 /* Return the mangling of TYPE if it is an extended fundamental type. */
28573 static const char *
28574 ix86_mangle_type (const_tree type)
28576 type = TYPE_MAIN_VARIANT (type);
28578 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28579 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28582 switch (TYPE_MODE (type))
28585 /* __float128 is "g". */
28588 /* "long double" or __float80 is "e". */
28595 /* For 32-bit code we can save PIC register setup by using
28596 __stack_chk_fail_local hidden function instead of calling
28597 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28598 register, so it is better to call __stack_chk_fail directly. */
28601 ix86_stack_protect_fail (void)
28603 return TARGET_64BIT
28604 ? default_external_stack_protect_fail ()
28605 : default_hidden_stack_protect_fail ();
28608 /* Select a format to encode pointers in exception handling data. CODE
28609 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28610 true if the symbol may be affected by dynamic relocations.
28612 ??? All x86 object file formats are capable of representing this.
28613 After all, the relocation needed is the same as for the call insn.
28614 Whether or not a particular assembler allows us to enter such, I
28615 guess we'll have to see. */
28617 asm_preferred_eh_data_format (int code, int global)
28621 int type = DW_EH_PE_sdata8;
28623 || ix86_cmodel == CM_SMALL_PIC
28624 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28625 type = DW_EH_PE_sdata4;
28626 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28628 if (ix86_cmodel == CM_SMALL
28629 || (ix86_cmodel == CM_MEDIUM && code))
28630 return DW_EH_PE_udata4;
28631 return DW_EH_PE_absptr;
28634 /* Expand copysign from SIGN to the positive value ABS_VALUE
28635 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28638 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28640 enum machine_mode mode = GET_MODE (sign);
28641 rtx sgn = gen_reg_rtx (mode);
28642 if (mask == NULL_RTX)
28644 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28645 if (!VECTOR_MODE_P (mode))
28647 /* We need to generate a scalar mode mask in this case. */
28648 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28649 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28650 mask = gen_reg_rtx (mode);
28651 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28655 mask = gen_rtx_NOT (mode, mask);
28656 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28657 gen_rtx_AND (mode, mask, sign)));
28658 emit_insn (gen_rtx_SET (VOIDmode, result,
28659 gen_rtx_IOR (mode, abs_value, sgn)));
28662 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28663 mask for masking out the sign-bit is stored in *SMASK, if that is
28666 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28668 enum machine_mode mode = GET_MODE (op0);
28671 xa = gen_reg_rtx (mode);
28672 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28673 if (!VECTOR_MODE_P (mode))
28675 /* We need to generate a scalar mode mask in this case. */
28676 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28677 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28678 mask = gen_reg_rtx (mode);
28679 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28681 emit_insn (gen_rtx_SET (VOIDmode, xa,
28682 gen_rtx_AND (mode, op0, mask)));
28690 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28691 swapping the operands if SWAP_OPERANDS is true. The expanded
28692 code is a forward jump to a newly created label in case the
28693 comparison is true. The generated label rtx is returned. */
28695 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28696 bool swap_operands)
28707 label = gen_label_rtx ();
28708 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28709 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28710 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28711 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28712 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28713 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28714 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28715 JUMP_LABEL (tmp) = label;
28720 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28721 using comparison code CODE. Operands are swapped for the comparison if
28722 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28724 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28725 bool swap_operands)
28727 enum machine_mode mode = GET_MODE (op0);
28728 rtx mask = gen_reg_rtx (mode);
28737 if (mode == DFmode)
28738 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28739 gen_rtx_fmt_ee (code, mode, op0, op1)));
28741 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28742 gen_rtx_fmt_ee (code, mode, op0, op1)));
28747 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28748 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28750 ix86_gen_TWO52 (enum machine_mode mode)
28752 REAL_VALUE_TYPE TWO52r;
28755 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28756 TWO52 = const_double_from_real_value (TWO52r, mode);
28757 TWO52 = force_reg (mode, TWO52);
28762 /* Expand SSE sequence for computing lround from OP1 storing
28765 ix86_expand_lround (rtx op0, rtx op1)
28767 /* C code for the stuff we're doing below:
28768 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28771 enum machine_mode mode = GET_MODE (op1);
28772 const struct real_format *fmt;
28773 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28776 /* load nextafter (0.5, 0.0) */
28777 fmt = REAL_MODE_FORMAT (mode);
28778 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28779 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28781 /* adj = copysign (0.5, op1) */
28782 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28783 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28785 /* adj = op1 + adj */
28786 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28788 /* op0 = (imode)adj */
28789 expand_fix (op0, adj, 0);
28792 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28795 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28797 /* C code for the stuff we're doing below (for do_floor):
28799 xi -= (double)xi > op1 ? 1 : 0;
28802 enum machine_mode fmode = GET_MODE (op1);
28803 enum machine_mode imode = GET_MODE (op0);
28804 rtx ireg, freg, label, tmp;
28806 /* reg = (long)op1 */
28807 ireg = gen_reg_rtx (imode);
28808 expand_fix (ireg, op1, 0);
28810 /* freg = (double)reg */
28811 freg = gen_reg_rtx (fmode);
28812 expand_float (freg, ireg, 0);
28814 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28815 label = ix86_expand_sse_compare_and_jump (UNLE,
28816 freg, op1, !do_floor);
28817 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28818 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28819 emit_move_insn (ireg, tmp);
28821 emit_label (label);
28822 LABEL_NUSES (label) = 1;
28824 emit_move_insn (op0, ireg);
28827 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28828 result in OPERAND0. */
28830 ix86_expand_rint (rtx operand0, rtx operand1)
28832 /* C code for the stuff we're doing below:
28833 xa = fabs (operand1);
28834 if (!isless (xa, 2**52))
28836 xa = xa + 2**52 - 2**52;
28837 return copysign (xa, operand1);
28839 enum machine_mode mode = GET_MODE (operand0);
28840 rtx res, xa, label, TWO52, mask;
28842 res = gen_reg_rtx (mode);
28843 emit_move_insn (res, operand1);
28845 /* xa = abs (operand1) */
28846 xa = ix86_expand_sse_fabs (res, &mask);
28848 /* if (!isless (xa, TWO52)) goto label; */
28849 TWO52 = ix86_gen_TWO52 (mode);
28850 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28852 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28853 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28855 ix86_sse_copysign_to_positive (res, xa, res, mask);
28857 emit_label (label);
28858 LABEL_NUSES (label) = 1;
28860 emit_move_insn (operand0, res);
28863 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28866 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28868 /* C code for the stuff we expand below.
28869 double xa = fabs (x), x2;
28870 if (!isless (xa, TWO52))
28872 xa = xa + TWO52 - TWO52;
28873 x2 = copysign (xa, x);
28882 enum machine_mode mode = GET_MODE (operand0);
28883 rtx xa, TWO52, tmp, label, one, res, mask;
28885 TWO52 = ix86_gen_TWO52 (mode);
28887 /* Temporary for holding the result, initialized to the input
28888 operand to ease control flow. */
28889 res = gen_reg_rtx (mode);
28890 emit_move_insn (res, operand1);
28892 /* xa = abs (operand1) */
28893 xa = ix86_expand_sse_fabs (res, &mask);
28895 /* if (!isless (xa, TWO52)) goto label; */
28896 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28898 /* xa = xa + TWO52 - TWO52; */
28899 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28900 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28902 /* xa = copysign (xa, operand1) */
28903 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28905 /* generate 1.0 or -1.0 */
28906 one = force_reg (mode,
28907 const_double_from_real_value (do_floor
28908 ? dconst1 : dconstm1, mode));
28910 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28911 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28912 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28913 gen_rtx_AND (mode, one, tmp)));
28914 /* We always need to subtract here to preserve signed zero. */
28915 tmp = expand_simple_binop (mode, MINUS,
28916 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28917 emit_move_insn (res, tmp);
28919 emit_label (label);
28920 LABEL_NUSES (label) = 1;
28922 emit_move_insn (operand0, res);
28925 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28928 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28930 /* C code for the stuff we expand below.
28931 double xa = fabs (x), x2;
28932 if (!isless (xa, TWO52))
28934 x2 = (double)(long)x;
28941 if (HONOR_SIGNED_ZEROS (mode))
28942 return copysign (x2, x);
28945 enum machine_mode mode = GET_MODE (operand0);
28946 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28948 TWO52 = ix86_gen_TWO52 (mode);
28950 /* Temporary for holding the result, initialized to the input
28951 operand to ease control flow. */
28952 res = gen_reg_rtx (mode);
28953 emit_move_insn (res, operand1);
28955 /* xa = abs (operand1) */
28956 xa = ix86_expand_sse_fabs (res, &mask);
28958 /* if (!isless (xa, TWO52)) goto label; */
28959 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28961 /* xa = (double)(long)x */
28962 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28963 expand_fix (xi, res, 0);
28964 expand_float (xa, xi, 0);
28967 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28969 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28970 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28971 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28972 gen_rtx_AND (mode, one, tmp)));
28973 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28974 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28975 emit_move_insn (res, tmp);
28977 if (HONOR_SIGNED_ZEROS (mode))
28978 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28980 emit_label (label);
28981 LABEL_NUSES (label) = 1;
28983 emit_move_insn (operand0, res);
28986 /* Expand SSE sequence for computing round from OPERAND1 storing
28987 into OPERAND0. Sequence that works without relying on DImode truncation
28988 via cvttsd2siq that is only available on 64bit targets. */
28990 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28992 /* C code for the stuff we expand below.
28993 double xa = fabs (x), xa2, x2;
28994 if (!isless (xa, TWO52))
28996 Using the absolute value and copying back sign makes
28997 -0.0 -> -0.0 correct.
28998 xa2 = xa + TWO52 - TWO52;
29003 else if (dxa > 0.5)
29005 x2 = copysign (xa2, x);
29008 enum machine_mode mode = GET_MODE (operand0);
29009 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29011 TWO52 = ix86_gen_TWO52 (mode);
29013 /* Temporary for holding the result, initialized to the input
29014 operand to ease control flow. */
29015 res = gen_reg_rtx (mode);
29016 emit_move_insn (res, operand1);
29018 /* xa = abs (operand1) */
29019 xa = ix86_expand_sse_fabs (res, &mask);
29021 /* if (!isless (xa, TWO52)) goto label; */
29022 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29024 /* xa2 = xa + TWO52 - TWO52; */
29025 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29026 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29028 /* dxa = xa2 - xa; */
29029 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29031 /* generate 0.5, 1.0 and -0.5 */
29032 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29033 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29034 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29038 tmp = gen_reg_rtx (mode);
29039 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29040 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29041 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29042 gen_rtx_AND (mode, one, tmp)));
29043 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29044 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29045 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29046 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29047 gen_rtx_AND (mode, one, tmp)));
29048 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29050 /* res = copysign (xa2, operand1) */
29051 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29053 emit_label (label);
29054 LABEL_NUSES (label) = 1;
29056 emit_move_insn (operand0, res);
29059 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29062 ix86_expand_trunc (rtx operand0, rtx operand1)
29064 /* C code for SSE variant we expand below.
29065 double xa = fabs (x), x2;
29066 if (!isless (xa, TWO52))
29068 x2 = (double)(long)x;
29069 if (HONOR_SIGNED_ZEROS (mode))
29070 return copysign (x2, x);
29073 enum machine_mode mode = GET_MODE (operand0);
29074 rtx xa, xi, TWO52, label, res, mask;
29076 TWO52 = ix86_gen_TWO52 (mode);
29078 /* Temporary for holding the result, initialized to the input
29079 operand to ease control flow. */
29080 res = gen_reg_rtx (mode);
29081 emit_move_insn (res, operand1);
29083 /* xa = abs (operand1) */
29084 xa = ix86_expand_sse_fabs (res, &mask);
29086 /* if (!isless (xa, TWO52)) goto label; */
29087 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29089 /* x = (double)(long)x */
29090 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29091 expand_fix (xi, res, 0);
29092 expand_float (res, xi, 0);
29094 if (HONOR_SIGNED_ZEROS (mode))
29095 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29097 emit_label (label);
29098 LABEL_NUSES (label) = 1;
29100 emit_move_insn (operand0, res);
29103 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29106 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29108 enum machine_mode mode = GET_MODE (operand0);
29109 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29111 /* C code for SSE variant we expand below.
29112 double xa = fabs (x), x2;
29113 if (!isless (xa, TWO52))
29115 xa2 = xa + TWO52 - TWO52;
29119 x2 = copysign (xa2, x);
29123 TWO52 = ix86_gen_TWO52 (mode);
29125 /* Temporary for holding the result, initialized to the input
29126 operand to ease control flow. */
29127 res = gen_reg_rtx (mode);
29128 emit_move_insn (res, operand1);
29130 /* xa = abs (operand1) */
29131 xa = ix86_expand_sse_fabs (res, &smask);
29133 /* if (!isless (xa, TWO52)) goto label; */
29134 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29136 /* res = xa + TWO52 - TWO52; */
29137 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29138 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29139 emit_move_insn (res, tmp);
29142 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29144 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29145 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29146 emit_insn (gen_rtx_SET (VOIDmode, mask,
29147 gen_rtx_AND (mode, mask, one)));
29148 tmp = expand_simple_binop (mode, MINUS,
29149 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29150 emit_move_insn (res, tmp);
29152 /* res = copysign (res, operand1) */
29153 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29155 emit_label (label);
29156 LABEL_NUSES (label) = 1;
29158 emit_move_insn (operand0, res);
29161 /* Expand SSE sequence for computing round from OPERAND1 storing
29164 ix86_expand_round (rtx operand0, rtx operand1)
29166 /* C code for the stuff we're doing below:
29167 double xa = fabs (x);
29168 if (!isless (xa, TWO52))
29170 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29171 return copysign (xa, x);
29173 enum machine_mode mode = GET_MODE (operand0);
29174 rtx res, TWO52, xa, label, xi, half, mask;
29175 const struct real_format *fmt;
29176 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29178 /* Temporary for holding the result, initialized to the input
29179 operand to ease control flow. */
29180 res = gen_reg_rtx (mode);
29181 emit_move_insn (res, operand1);
29183 TWO52 = ix86_gen_TWO52 (mode);
29184 xa = ix86_expand_sse_fabs (res, &mask);
29185 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29187 /* load nextafter (0.5, 0.0) */
29188 fmt = REAL_MODE_FORMAT (mode);
29189 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29190 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29192 /* xa = xa + 0.5 */
29193 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29194 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29196 /* xa = (double)(int64_t)xa */
29197 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29198 expand_fix (xi, xa, 0);
29199 expand_float (xa, xi, 0);
29201 /* res = copysign (xa, operand1) */
29202 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29204 emit_label (label);
29205 LABEL_NUSES (label) = 1;
29207 emit_move_insn (operand0, res);
29211 /* Validate whether a SSE5 instruction is valid or not.
29212 OPERANDS is the array of operands.
29213 NUM is the number of operands.
29214 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29215 NUM_MEMORY is the maximum number of memory operands to accept.
29216 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29219 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29220 bool uses_oc0, int num_memory, bool commutative)
29226 /* Count the number of memory arguments */
29229 for (i = 0; i < num; i++)
29231 enum machine_mode mode = GET_MODE (operands[i]);
29232 if (register_operand (operands[i], mode))
29235 else if (memory_operand (operands[i], mode))
29237 mem_mask |= (1 << i);
29243 rtx pattern = PATTERN (insn);
29245 /* allow 0 for pcmov */
29246 if (GET_CODE (pattern) != SET
29247 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29249 || operands[i] != CONST0_RTX (mode))
29254 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29255 a memory operation. */
29256 if (num_memory < 0)
29258 num_memory = -num_memory;
29259 if ((mem_mask & (1 << (num-1))) != 0)
29261 mem_mask &= ~(1 << (num-1));
29266 /* If there were no memory operations, allow the insn */
29270 /* Do not allow the destination register to be a memory operand. */
29271 else if (mem_mask & (1 << 0))
29274 /* If there are too many memory operations, disallow the instruction. While
29275 the hardware only allows 1 memory reference, before register allocation
29276 for some insns, we allow two memory operations sometimes in order to allow
29277 code like the following to be optimized:
29279 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29281 or similar cases that are vectorized into using the fmaddss
29283 else if (mem_count > num_memory)
29286 /* Don't allow more than one memory operation if not optimizing. */
29287 else if (mem_count > 1 && !optimize)
29290 else if (num == 4 && mem_count == 1)
29292 /* formats (destination is the first argument), example fmaddss:
29293 xmm1, xmm1, xmm2, xmm3/mem
29294 xmm1, xmm1, xmm2/mem, xmm3
29295 xmm1, xmm2, xmm3/mem, xmm1
29296 xmm1, xmm2/mem, xmm3, xmm1 */
29298 return ((mem_mask == (1 << 1))
29299 || (mem_mask == (1 << 2))
29300 || (mem_mask == (1 << 3)));
29302 /* format, example pmacsdd:
29303 xmm1, xmm2, xmm3/mem, xmm1 */
29305 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29307 return (mem_mask == (1 << 2));
29310 else if (num == 4 && num_memory == 2)
29312 /* If there are two memory operations, we can load one of the memory ops
29313 into the destination register. This is for optimizing the
29314 multiply/add ops, which the combiner has optimized both the multiply
29315 and the add insns to have a memory operation. We have to be careful
29316 that the destination doesn't overlap with the inputs. */
29317 rtx op0 = operands[0];
29319 if (reg_mentioned_p (op0, operands[1])
29320 || reg_mentioned_p (op0, operands[2])
29321 || reg_mentioned_p (op0, operands[3]))
29324 /* formats (destination is the first argument), example fmaddss:
29325 xmm1, xmm1, xmm2, xmm3/mem
29326 xmm1, xmm1, xmm2/mem, xmm3
29327 xmm1, xmm2, xmm3/mem, xmm1
29328 xmm1, xmm2/mem, xmm3, xmm1
29330 For the oc0 case, we will load either operands[1] or operands[3] into
29331 operands[0], so any combination of 2 memory operands is ok. */
29335 /* format, example pmacsdd:
29336 xmm1, xmm2, xmm3/mem, xmm1
29338 For the integer multiply/add instructions be more restrictive and
29339 require operands[2] and operands[3] to be the memory operands. */
29341 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29343 return (mem_mask == ((1 << 2) | (1 << 3)));
29346 else if (num == 3 && num_memory == 1)
29348 /* formats, example protb:
29349 xmm1, xmm2, xmm3/mem
29350 xmm1, xmm2/mem, xmm3 */
29352 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29354 /* format, example comeq:
29355 xmm1, xmm2, xmm3/mem */
29357 return (mem_mask == (1 << 2));
29361 gcc_unreachable ();
29367 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29368 hardware will allow by using the destination register to load one of the
29369 memory operations. Presently this is used by the multiply/add routines to
29370 allow 2 memory references. */
29373 ix86_expand_sse5_multiple_memory (rtx operands[],
29375 enum machine_mode mode)
29377 rtx op0 = operands[0];
29379 || memory_operand (op0, mode)
29380 || reg_mentioned_p (op0, operands[1])
29381 || reg_mentioned_p (op0, operands[2])
29382 || reg_mentioned_p (op0, operands[3]))
29383 gcc_unreachable ();
29385 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29386 the destination register. */
29387 if (memory_operand (operands[1], mode))
29389 emit_move_insn (op0, operands[1]);
29392 else if (memory_operand (operands[3], mode))
29394 emit_move_insn (op0, operands[3]);
29398 gcc_unreachable ();
29404 /* Table of valid machine attributes. */
29405 static const struct attribute_spec ix86_attribute_table[] =
29407 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29408 /* Stdcall attribute says callee is responsible for popping arguments
29409 if they are not variable. */
29410 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29411 /* Fastcall attribute says callee is responsible for popping arguments
29412 if they are not variable. */
29413 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29414 /* Cdecl attribute says the callee is a normal C declaration */
29415 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29416 /* Regparm attribute specifies how many integer arguments are to be
29417 passed in registers. */
29418 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29419 /* Sseregparm attribute says we are using x86_64 calling conventions
29420 for FP arguments. */
29421 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29422 /* force_align_arg_pointer says this function realigns the stack at entry. */
29423 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29424 false, true, true, ix86_handle_cconv_attribute },
29425 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29426 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29427 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29428 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29430 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29431 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29432 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29433 SUBTARGET_ATTRIBUTE_TABLE,
29435 /* ms_abi and sysv_abi calling convention function attributes. */
29436 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29437 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29439 { NULL, 0, 0, false, false, false, NULL }
29442 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29444 x86_builtin_vectorization_cost (bool runtime_test)
29446 /* If the branch of the runtime test is taken - i.e. - the vectorized
29447 version is skipped - this incurs a misprediction cost (because the
29448 vectorized version is expected to be the fall-through). So we subtract
29449 the latency of a mispredicted branch from the costs that are incured
29450 when the vectorized version is executed.
29452 TODO: The values in individual target tables have to be tuned or new
29453 fields may be needed. For eg. on K8, the default branch path is the
29454 not-taken path. If the taken path is predicted correctly, the minimum
29455 penalty of going down the taken-path is 1 cycle. If the taken-path is
29456 not predicted correctly, then the minimum penalty is 10 cycles. */
29460 return (-(ix86_cost->cond_taken_branch_cost));
29466 /* This function returns the calling abi specific va_list type node.
29467 It returns the FNDECL specific va_list type. */
29470 ix86_fn_abi_va_list (tree fndecl)
29473 return va_list_type_node;
29474 gcc_assert (fndecl != NULL_TREE);
29476 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
29477 return ms_va_list_type_node;
29479 return sysv_va_list_type_node;
29482 /* Returns the canonical va_list type specified by TYPE. If there
29483 is no valid TYPE provided, it return NULL_TREE. */
29486 ix86_canonical_va_list_type (tree type)
29490 /* Resolve references and pointers to va_list type. */
29491 if (INDIRECT_REF_P (type))
29492 type = TREE_TYPE (type);
29493 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29494 type = TREE_TYPE (type);
29498 wtype = va_list_type_node;
29499 gcc_assert (wtype != NULL_TREE);
29501 if (TREE_CODE (wtype) == ARRAY_TYPE)
29503 /* If va_list is an array type, the argument may have decayed
29504 to a pointer type, e.g. by being passed to another function.
29505 In that case, unwrap both types so that we can compare the
29506 underlying records. */
29507 if (TREE_CODE (htype) == ARRAY_TYPE
29508 || POINTER_TYPE_P (htype))
29510 wtype = TREE_TYPE (wtype);
29511 htype = TREE_TYPE (htype);
29514 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29515 return va_list_type_node;
29516 wtype = sysv_va_list_type_node;
29517 gcc_assert (wtype != NULL_TREE);
29519 if (TREE_CODE (wtype) == ARRAY_TYPE)
29521 /* If va_list is an array type, the argument may have decayed
29522 to a pointer type, e.g. by being passed to another function.
29523 In that case, unwrap both types so that we can compare the
29524 underlying records. */
29525 if (TREE_CODE (htype) == ARRAY_TYPE
29526 || POINTER_TYPE_P (htype))
29528 wtype = TREE_TYPE (wtype);
29529 htype = TREE_TYPE (htype);
29532 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29533 return sysv_va_list_type_node;
29534 wtype = ms_va_list_type_node;
29535 gcc_assert (wtype != NULL_TREE);
29537 if (TREE_CODE (wtype) == ARRAY_TYPE)
29539 /* If va_list is an array type, the argument may have decayed
29540 to a pointer type, e.g. by being passed to another function.
29541 In that case, unwrap both types so that we can compare the
29542 underlying records. */
29543 if (TREE_CODE (htype) == ARRAY_TYPE
29544 || POINTER_TYPE_P (htype))
29546 wtype = TREE_TYPE (wtype);
29547 htype = TREE_TYPE (htype);
29550 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29551 return ms_va_list_type_node;
29554 return std_canonical_va_list_type (type);
29557 /* Iterate through the target-specific builtin types for va_list.
29558 IDX denotes the iterator, *PTREE is set to the result type of
29559 the va_list builtin, and *PNAME to its internal type.
29560 Returns zero if there is no element for this index, otherwise
29561 IDX should be increased upon the next call.
29562 Note, do not iterate a base builtin's name like __builtin_va_list.
29563 Used from c_common_nodes_and_builtins. */
29566 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29572 *ptree = ms_va_list_type_node;
29573 *pname = "__builtin_ms_va_list";
29576 *ptree = sysv_va_list_type_node;
29577 *pname = "__builtin_sysv_va_list";
29585 /* Initialize the GCC target structure. */
29586 #undef TARGET_RETURN_IN_MEMORY
29587 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29589 #undef TARGET_ATTRIBUTE_TABLE
29590 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29591 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29592 # undef TARGET_MERGE_DECL_ATTRIBUTES
29593 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29596 #undef TARGET_COMP_TYPE_ATTRIBUTES
29597 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29599 #undef TARGET_INIT_BUILTINS
29600 #define TARGET_INIT_BUILTINS ix86_init_builtins
29601 #undef TARGET_EXPAND_BUILTIN
29602 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29604 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29605 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29606 ix86_builtin_vectorized_function
29608 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29609 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29611 #undef TARGET_BUILTIN_RECIPROCAL
29612 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29614 #undef TARGET_ASM_FUNCTION_EPILOGUE
29615 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29617 #undef TARGET_ENCODE_SECTION_INFO
29618 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29619 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29621 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29624 #undef TARGET_ASM_OPEN_PAREN
29625 #define TARGET_ASM_OPEN_PAREN ""
29626 #undef TARGET_ASM_CLOSE_PAREN
29627 #define TARGET_ASM_CLOSE_PAREN ""
29629 #undef TARGET_ASM_ALIGNED_HI_OP
29630 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29631 #undef TARGET_ASM_ALIGNED_SI_OP
29632 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29634 #undef TARGET_ASM_ALIGNED_DI_OP
29635 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29638 #undef TARGET_ASM_UNALIGNED_HI_OP
29639 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29640 #undef TARGET_ASM_UNALIGNED_SI_OP
29641 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29642 #undef TARGET_ASM_UNALIGNED_DI_OP
29643 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29645 #undef TARGET_SCHED_ADJUST_COST
29646 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29647 #undef TARGET_SCHED_ISSUE_RATE
29648 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29649 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29650 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29651 ia32_multipass_dfa_lookahead
29653 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29654 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29657 #undef TARGET_HAVE_TLS
29658 #define TARGET_HAVE_TLS true
29660 #undef TARGET_CANNOT_FORCE_CONST_MEM
29661 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29662 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29663 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29665 #undef TARGET_DELEGITIMIZE_ADDRESS
29666 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29668 #undef TARGET_MS_BITFIELD_LAYOUT_P
29669 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29672 #undef TARGET_BINDS_LOCAL_P
29673 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29675 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29676 #undef TARGET_BINDS_LOCAL_P
29677 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29680 #undef TARGET_ASM_OUTPUT_MI_THUNK
29681 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29682 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29683 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29685 #undef TARGET_ASM_FILE_START
29686 #define TARGET_ASM_FILE_START x86_file_start
29688 #undef TARGET_DEFAULT_TARGET_FLAGS
29689 #define TARGET_DEFAULT_TARGET_FLAGS \
29691 | TARGET_SUBTARGET_DEFAULT \
29692 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29694 #undef TARGET_HANDLE_OPTION
29695 #define TARGET_HANDLE_OPTION ix86_handle_option
29697 #undef TARGET_RTX_COSTS
29698 #define TARGET_RTX_COSTS ix86_rtx_costs
29699 #undef TARGET_ADDRESS_COST
29700 #define TARGET_ADDRESS_COST ix86_address_cost
29702 #undef TARGET_FIXED_CONDITION_CODE_REGS
29703 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29704 #undef TARGET_CC_MODES_COMPATIBLE
29705 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29707 #undef TARGET_MACHINE_DEPENDENT_REORG
29708 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29710 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29711 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29713 #undef TARGET_BUILD_BUILTIN_VA_LIST
29714 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29716 #undef TARGET_FN_ABI_VA_LIST
29717 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29719 #undef TARGET_CANONICAL_VA_LIST_TYPE
29720 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29722 #undef TARGET_EXPAND_BUILTIN_VA_START
29723 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29725 #undef TARGET_MD_ASM_CLOBBERS
29726 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29728 #undef TARGET_PROMOTE_PROTOTYPES
29729 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29730 #undef TARGET_STRUCT_VALUE_RTX
29731 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29732 #undef TARGET_SETUP_INCOMING_VARARGS
29733 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29734 #undef TARGET_MUST_PASS_IN_STACK
29735 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29736 #undef TARGET_PASS_BY_REFERENCE
29737 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29738 #undef TARGET_INTERNAL_ARG_POINTER
29739 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29740 #undef TARGET_UPDATE_STACK_BOUNDARY
29741 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29742 #undef TARGET_GET_DRAP_RTX
29743 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29744 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29745 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29746 #undef TARGET_STRICT_ARGUMENT_NAMING
29747 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29749 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29750 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29752 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29753 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29755 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29756 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29758 #undef TARGET_C_MODE_FOR_SUFFIX
29759 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29762 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29763 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29766 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29767 #undef TARGET_INSERT_ATTRIBUTES
29768 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29771 #undef TARGET_MANGLE_TYPE
29772 #define TARGET_MANGLE_TYPE ix86_mangle_type
29774 #undef TARGET_STACK_PROTECT_FAIL
29775 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29777 #undef TARGET_FUNCTION_VALUE
29778 #define TARGET_FUNCTION_VALUE ix86_function_value
29780 #undef TARGET_SECONDARY_RELOAD
29781 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29783 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29784 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29786 #undef TARGET_SET_CURRENT_FUNCTION
29787 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29789 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29790 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29792 #undef TARGET_OPTION_SAVE
29793 #define TARGET_OPTION_SAVE ix86_function_specific_save
29795 #undef TARGET_OPTION_RESTORE
29796 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29798 #undef TARGET_OPTION_PRINT
29799 #define TARGET_OPTION_PRINT ix86_function_specific_print
29801 #undef TARGET_OPTION_CAN_INLINE_P
29802 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29804 #undef TARGET_EXPAND_TO_RTL_HOOK
29805 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29807 struct gcc_target targetm = TARGET_INITIALIZER;
29809 #include "gt-i386.h"
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