1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #include "tm-constrs.h"
56 #ifndef CHECK_STACK_LIMIT
57 #define CHECK_STACK_LIMIT (-1)
60 /* Return index of given mode in mult and division cost tables. */
61 #define MODE_INDEX(mode) \
62 ((mode) == QImode ? 0 \
63 : (mode) == HImode ? 1 \
64 : (mode) == SImode ? 2 \
65 : (mode) == DImode ? 3 \
68 /* Processor costs (relative to an add) */
69 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
70 #define COSTS_N_BYTES(N) ((N) * 2)
72 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
75 struct processor_costs size_cost = { /* costs for tuning for size */
76 COSTS_N_BYTES (2), /* cost of an add instruction */
77 COSTS_N_BYTES (3), /* cost of a lea instruction */
78 COSTS_N_BYTES (2), /* variable shift costs */
79 COSTS_N_BYTES (3), /* constant shift costs */
80 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
81 COSTS_N_BYTES (3), /* HI */
82 COSTS_N_BYTES (3), /* SI */
83 COSTS_N_BYTES (3), /* DI */
84 COSTS_N_BYTES (5)}, /* other */
85 0, /* cost of multiply per each bit set */
86 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
87 COSTS_N_BYTES (3), /* HI */
88 COSTS_N_BYTES (3), /* SI */
89 COSTS_N_BYTES (3), /* DI */
90 COSTS_N_BYTES (5)}, /* other */
91 COSTS_N_BYTES (3), /* cost of movsx */
92 COSTS_N_BYTES (3), /* cost of movzx */
95 2, /* cost for loading QImode using movzbl */
96 {2, 2, 2}, /* cost of loading integer registers
97 in QImode, HImode and SImode.
98 Relative to reg-reg move (2). */
99 {2, 2, 2}, /* cost of storing integer registers */
100 2, /* cost of reg,reg fld/fst */
101 {2, 2, 2}, /* cost of loading fp registers
102 in SFmode, DFmode and XFmode */
103 {2, 2, 2}, /* cost of storing fp registers
104 in SFmode, DFmode and XFmode */
105 3, /* cost of moving MMX register */
106 {3, 3}, /* cost of loading MMX registers
107 in SImode and DImode */
108 {3, 3}, /* cost of storing MMX registers
109 in SImode and DImode */
110 3, /* cost of moving SSE register */
111 {3, 3, 3}, /* cost of loading SSE registers
112 in SImode, DImode and TImode */
113 {3, 3, 3}, /* cost of storing SSE registers
114 in SImode, DImode and TImode */
115 3, /* MMX or SSE register to integer */
116 0, /* size of prefetch block */
117 0, /* number of parallel prefetches */
119 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
120 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
121 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
122 COSTS_N_BYTES (2), /* cost of FABS instruction. */
123 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
124 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
125 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
126 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
127 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
128 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}}
131 /* Processor costs (relative to an add) */
133 struct processor_costs i386_cost = { /* 386 specific costs */
134 COSTS_N_INSNS (1), /* cost of an add instruction */
135 COSTS_N_INSNS (1), /* cost of a lea instruction */
136 COSTS_N_INSNS (3), /* variable shift costs */
137 COSTS_N_INSNS (2), /* constant shift costs */
138 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
139 COSTS_N_INSNS (6), /* HI */
140 COSTS_N_INSNS (6), /* SI */
141 COSTS_N_INSNS (6), /* DI */
142 COSTS_N_INSNS (6)}, /* other */
143 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
144 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
145 COSTS_N_INSNS (23), /* HI */
146 COSTS_N_INSNS (23), /* SI */
147 COSTS_N_INSNS (23), /* DI */
148 COSTS_N_INSNS (23)}, /* other */
149 COSTS_N_INSNS (3), /* cost of movsx */
150 COSTS_N_INSNS (2), /* cost of movzx */
151 15, /* "large" insn */
153 4, /* cost for loading QImode using movzbl */
154 {2, 4, 2}, /* cost of loading integer registers
155 in QImode, HImode and SImode.
156 Relative to reg-reg move (2). */
157 {2, 4, 2}, /* cost of storing integer registers */
158 2, /* cost of reg,reg fld/fst */
159 {8, 8, 8}, /* cost of loading fp registers
160 in SFmode, DFmode and XFmode */
161 {8, 8, 8}, /* cost of storing fp registers
162 in SFmode, DFmode and XFmode */
163 2, /* cost of moving MMX register */
164 {4, 8}, /* cost of loading MMX registers
165 in SImode and DImode */
166 {4, 8}, /* cost of storing MMX registers
167 in SImode and DImode */
168 2, /* cost of moving SSE register */
169 {4, 8, 16}, /* cost of loading SSE registers
170 in SImode, DImode and TImode */
171 {4, 8, 16}, /* cost of storing SSE registers
172 in SImode, DImode and TImode */
173 3, /* MMX or SSE register to integer */
174 0, /* size of prefetch block */
175 0, /* number of parallel prefetches */
177 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
178 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
179 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
180 COSTS_N_INSNS (22), /* cost of FABS instruction. */
181 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
182 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
183 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
184 DUMMY_STRINGOP_ALGS},
185 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
186 DUMMY_STRINGOP_ALGS},
190 struct processor_costs i486_cost = { /* 486 specific costs */
191 COSTS_N_INSNS (1), /* cost of an add instruction */
192 COSTS_N_INSNS (1), /* cost of a lea instruction */
193 COSTS_N_INSNS (3), /* variable shift costs */
194 COSTS_N_INSNS (2), /* constant shift costs */
195 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
196 COSTS_N_INSNS (12), /* HI */
197 COSTS_N_INSNS (12), /* SI */
198 COSTS_N_INSNS (12), /* DI */
199 COSTS_N_INSNS (12)}, /* other */
200 1, /* cost of multiply per each bit set */
201 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
202 COSTS_N_INSNS (40), /* HI */
203 COSTS_N_INSNS (40), /* SI */
204 COSTS_N_INSNS (40), /* DI */
205 COSTS_N_INSNS (40)}, /* other */
206 COSTS_N_INSNS (3), /* cost of movsx */
207 COSTS_N_INSNS (2), /* cost of movzx */
208 15, /* "large" insn */
210 4, /* cost for loading QImode using movzbl */
211 {2, 4, 2}, /* cost of loading integer registers
212 in QImode, HImode and SImode.
213 Relative to reg-reg move (2). */
214 {2, 4, 2}, /* cost of storing integer registers */
215 2, /* cost of reg,reg fld/fst */
216 {8, 8, 8}, /* cost of loading fp registers
217 in SFmode, DFmode and XFmode */
218 {8, 8, 8}, /* cost of storing fp registers
219 in SFmode, DFmode and XFmode */
220 2, /* cost of moving MMX register */
221 {4, 8}, /* cost of loading MMX registers
222 in SImode and DImode */
223 {4, 8}, /* cost of storing MMX registers
224 in SImode and DImode */
225 2, /* cost of moving SSE register */
226 {4, 8, 16}, /* cost of loading SSE registers
227 in SImode, DImode and TImode */
228 {4, 8, 16}, /* cost of storing SSE registers
229 in SImode, DImode and TImode */
230 3, /* MMX or SSE register to integer */
231 0, /* size of prefetch block */
232 0, /* number of parallel prefetches */
234 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
235 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
236 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
237 COSTS_N_INSNS (3), /* cost of FABS instruction. */
238 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
239 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
240 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
241 DUMMY_STRINGOP_ALGS},
242 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
247 struct processor_costs pentium_cost = {
248 COSTS_N_INSNS (1), /* cost of an add instruction */
249 COSTS_N_INSNS (1), /* cost of a lea instruction */
250 COSTS_N_INSNS (4), /* variable shift costs */
251 COSTS_N_INSNS (1), /* constant shift costs */
252 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
253 COSTS_N_INSNS (11), /* HI */
254 COSTS_N_INSNS (11), /* SI */
255 COSTS_N_INSNS (11), /* DI */
256 COSTS_N_INSNS (11)}, /* other */
257 0, /* cost of multiply per each bit set */
258 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
259 COSTS_N_INSNS (25), /* HI */
260 COSTS_N_INSNS (25), /* SI */
261 COSTS_N_INSNS (25), /* DI */
262 COSTS_N_INSNS (25)}, /* other */
263 COSTS_N_INSNS (3), /* cost of movsx */
264 COSTS_N_INSNS (2), /* cost of movzx */
265 8, /* "large" insn */
267 6, /* cost for loading QImode using movzbl */
268 {2, 4, 2}, /* cost of loading integer registers
269 in QImode, HImode and SImode.
270 Relative to reg-reg move (2). */
271 {2, 4, 2}, /* cost of storing integer registers */
272 2, /* cost of reg,reg fld/fst */
273 {2, 2, 6}, /* cost of loading fp registers
274 in SFmode, DFmode and XFmode */
275 {4, 4, 6}, /* cost of storing fp registers
276 in SFmode, DFmode and XFmode */
277 8, /* cost of moving MMX register */
278 {8, 8}, /* cost of loading MMX registers
279 in SImode and DImode */
280 {8, 8}, /* cost of storing MMX registers
281 in SImode and DImode */
282 2, /* cost of moving SSE register */
283 {4, 8, 16}, /* cost of loading SSE registers
284 in SImode, DImode and TImode */
285 {4, 8, 16}, /* cost of storing SSE registers
286 in SImode, DImode and TImode */
287 3, /* MMX or SSE register to integer */
288 0, /* size of prefetch block */
289 0, /* number of parallel prefetches */
291 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
292 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
293 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
294 COSTS_N_INSNS (1), /* cost of FABS instruction. */
295 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
296 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
297 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
298 DUMMY_STRINGOP_ALGS},
299 {{libcall, {{-1, rep_prefix_4_byte}}},
304 struct processor_costs pentiumpro_cost = {
305 COSTS_N_INSNS (1), /* cost of an add instruction */
306 COSTS_N_INSNS (1), /* cost of a lea instruction */
307 COSTS_N_INSNS (1), /* variable shift costs */
308 COSTS_N_INSNS (1), /* constant shift costs */
309 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
310 COSTS_N_INSNS (4), /* HI */
311 COSTS_N_INSNS (4), /* SI */
312 COSTS_N_INSNS (4), /* DI */
313 COSTS_N_INSNS (4)}, /* other */
314 0, /* cost of multiply per each bit set */
315 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
316 COSTS_N_INSNS (17), /* HI */
317 COSTS_N_INSNS (17), /* SI */
318 COSTS_N_INSNS (17), /* DI */
319 COSTS_N_INSNS (17)}, /* other */
320 COSTS_N_INSNS (1), /* cost of movsx */
321 COSTS_N_INSNS (1), /* cost of movzx */
322 8, /* "large" insn */
324 2, /* cost for loading QImode using movzbl */
325 {4, 4, 4}, /* cost of loading integer registers
326 in QImode, HImode and SImode.
327 Relative to reg-reg move (2). */
328 {2, 2, 2}, /* cost of storing integer registers */
329 2, /* cost of reg,reg fld/fst */
330 {2, 2, 6}, /* cost of loading fp registers
331 in SFmode, DFmode and XFmode */
332 {4, 4, 6}, /* cost of storing fp registers
333 in SFmode, DFmode and XFmode */
334 2, /* cost of moving MMX register */
335 {2, 2}, /* cost of loading MMX registers
336 in SImode and DImode */
337 {2, 2}, /* cost of storing MMX registers
338 in SImode and DImode */
339 2, /* cost of moving SSE register */
340 {2, 2, 8}, /* cost of loading SSE registers
341 in SImode, DImode and TImode */
342 {2, 2, 8}, /* cost of storing SSE registers
343 in SImode, DImode and TImode */
344 3, /* MMX or SSE register to integer */
345 32, /* size of prefetch block */
346 6, /* number of parallel prefetches */
348 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
349 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
350 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
351 COSTS_N_INSNS (2), /* cost of FABS instruction. */
352 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
353 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
354 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
355 the alignment). For small blocks inline loop is still a noticeable win, for bigger
356 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
357 more expensive startup time in CPU, but after 4K the difference is down in the noise.
359 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
360 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
361 DUMMY_STRINGOP_ALGS},
362 {{rep_prefix_4_byte, {{1024, unrolled_loop},
363 {8192, rep_prefix_4_byte}, {-1, libcall}}},
368 struct processor_costs geode_cost = {
369 COSTS_N_INSNS (1), /* cost of an add instruction */
370 COSTS_N_INSNS (1), /* cost of a lea instruction */
371 COSTS_N_INSNS (2), /* variable shift costs */
372 COSTS_N_INSNS (1), /* constant shift costs */
373 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
374 COSTS_N_INSNS (4), /* HI */
375 COSTS_N_INSNS (7), /* SI */
376 COSTS_N_INSNS (7), /* DI */
377 COSTS_N_INSNS (7)}, /* other */
378 0, /* cost of multiply per each bit set */
379 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
380 COSTS_N_INSNS (23), /* HI */
381 COSTS_N_INSNS (39), /* SI */
382 COSTS_N_INSNS (39), /* DI */
383 COSTS_N_INSNS (39)}, /* other */
384 COSTS_N_INSNS (1), /* cost of movsx */
385 COSTS_N_INSNS (1), /* cost of movzx */
386 8, /* "large" insn */
388 1, /* cost for loading QImode using movzbl */
389 {1, 1, 1}, /* cost of loading integer registers
390 in QImode, HImode and SImode.
391 Relative to reg-reg move (2). */
392 {1, 1, 1}, /* cost of storing integer registers */
393 1, /* cost of reg,reg fld/fst */
394 {1, 1, 1}, /* cost of loading fp registers
395 in SFmode, DFmode and XFmode */
396 {4, 6, 6}, /* cost of storing fp registers
397 in SFmode, DFmode and XFmode */
399 1, /* cost of moving MMX register */
400 {1, 1}, /* cost of loading MMX registers
401 in SImode and DImode */
402 {1, 1}, /* cost of storing MMX registers
403 in SImode and DImode */
404 1, /* cost of moving SSE register */
405 {1, 1, 1}, /* cost of loading SSE registers
406 in SImode, DImode and TImode */
407 {1, 1, 1}, /* cost of storing SSE registers
408 in SImode, DImode and TImode */
409 1, /* MMX or SSE register to integer */
410 32, /* size of prefetch block */
411 1, /* number of parallel prefetches */
413 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
414 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
415 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
416 COSTS_N_INSNS (1), /* cost of FABS instruction. */
417 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
418 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
419 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
420 DUMMY_STRINGOP_ALGS},
421 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
426 struct processor_costs k6_cost = {
427 COSTS_N_INSNS (1), /* cost of an add instruction */
428 COSTS_N_INSNS (2), /* cost of a lea instruction */
429 COSTS_N_INSNS (1), /* variable shift costs */
430 COSTS_N_INSNS (1), /* constant shift costs */
431 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
432 COSTS_N_INSNS (3), /* HI */
433 COSTS_N_INSNS (3), /* SI */
434 COSTS_N_INSNS (3), /* DI */
435 COSTS_N_INSNS (3)}, /* other */
436 0, /* cost of multiply per each bit set */
437 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
438 COSTS_N_INSNS (18), /* HI */
439 COSTS_N_INSNS (18), /* SI */
440 COSTS_N_INSNS (18), /* DI */
441 COSTS_N_INSNS (18)}, /* other */
442 COSTS_N_INSNS (2), /* cost of movsx */
443 COSTS_N_INSNS (2), /* cost of movzx */
444 8, /* "large" insn */
446 3, /* cost for loading QImode using movzbl */
447 {4, 5, 4}, /* cost of loading integer registers
448 in QImode, HImode and SImode.
449 Relative to reg-reg move (2). */
450 {2, 3, 2}, /* cost of storing integer registers */
451 4, /* cost of reg,reg fld/fst */
452 {6, 6, 6}, /* cost of loading fp registers
453 in SFmode, DFmode and XFmode */
454 {4, 4, 4}, /* cost of storing fp registers
455 in SFmode, DFmode and XFmode */
456 2, /* cost of moving MMX register */
457 {2, 2}, /* cost of loading MMX registers
458 in SImode and DImode */
459 {2, 2}, /* cost of storing MMX registers
460 in SImode and DImode */
461 2, /* cost of moving SSE register */
462 {2, 2, 8}, /* cost of loading SSE registers
463 in SImode, DImode and TImode */
464 {2, 2, 8}, /* cost of storing SSE registers
465 in SImode, DImode and TImode */
466 6, /* MMX or SSE register to integer */
467 32, /* size of prefetch block */
468 1, /* number of parallel prefetches */
470 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
471 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
472 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
473 COSTS_N_INSNS (2), /* cost of FABS instruction. */
474 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
475 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
476 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
477 DUMMY_STRINGOP_ALGS},
478 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
483 struct processor_costs athlon_cost = {
484 COSTS_N_INSNS (1), /* cost of an add instruction */
485 COSTS_N_INSNS (2), /* cost of a lea instruction */
486 COSTS_N_INSNS (1), /* variable shift costs */
487 COSTS_N_INSNS (1), /* constant shift costs */
488 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
489 COSTS_N_INSNS (5), /* HI */
490 COSTS_N_INSNS (5), /* SI */
491 COSTS_N_INSNS (5), /* DI */
492 COSTS_N_INSNS (5)}, /* other */
493 0, /* cost of multiply per each bit set */
494 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
495 COSTS_N_INSNS (26), /* HI */
496 COSTS_N_INSNS (42), /* SI */
497 COSTS_N_INSNS (74), /* DI */
498 COSTS_N_INSNS (74)}, /* other */
499 COSTS_N_INSNS (1), /* cost of movsx */
500 COSTS_N_INSNS (1), /* cost of movzx */
501 8, /* "large" insn */
503 4, /* cost for loading QImode using movzbl */
504 {3, 4, 3}, /* cost of loading integer registers
505 in QImode, HImode and SImode.
506 Relative to reg-reg move (2). */
507 {3, 4, 3}, /* cost of storing integer registers */
508 4, /* cost of reg,reg fld/fst */
509 {4, 4, 12}, /* cost of loading fp registers
510 in SFmode, DFmode and XFmode */
511 {6, 6, 8}, /* cost of storing fp registers
512 in SFmode, DFmode and XFmode */
513 2, /* cost of moving MMX register */
514 {4, 4}, /* cost of loading MMX registers
515 in SImode and DImode */
516 {4, 4}, /* cost of storing MMX registers
517 in SImode and DImode */
518 2, /* cost of moving SSE register */
519 {4, 4, 6}, /* cost of loading SSE registers
520 in SImode, DImode and TImode */
521 {4, 4, 5}, /* cost of storing SSE registers
522 in SImode, DImode and TImode */
523 5, /* MMX or SSE register to integer */
524 64, /* size of prefetch block */
525 6, /* number of parallel prefetches */
527 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
528 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
529 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
530 COSTS_N_INSNS (2), /* cost of FABS instruction. */
531 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
532 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
533 /* For some reason, Athlon deals better with REP prefix (relative to loops)
534 compared to K8. Alignment becomes important after 8 bytes for memcpy and
535 128 bytes for memset. */
536 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
537 DUMMY_STRINGOP_ALGS},
538 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
543 struct processor_costs k8_cost = {
544 COSTS_N_INSNS (1), /* cost of an add instruction */
545 COSTS_N_INSNS (2), /* cost of a lea instruction */
546 COSTS_N_INSNS (1), /* variable shift costs */
547 COSTS_N_INSNS (1), /* constant shift costs */
548 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
549 COSTS_N_INSNS (4), /* HI */
550 COSTS_N_INSNS (3), /* SI */
551 COSTS_N_INSNS (4), /* DI */
552 COSTS_N_INSNS (5)}, /* other */
553 0, /* cost of multiply per each bit set */
554 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
555 COSTS_N_INSNS (26), /* HI */
556 COSTS_N_INSNS (42), /* SI */
557 COSTS_N_INSNS (74), /* DI */
558 COSTS_N_INSNS (74)}, /* other */
559 COSTS_N_INSNS (1), /* cost of movsx */
560 COSTS_N_INSNS (1), /* cost of movzx */
561 8, /* "large" insn */
563 4, /* cost for loading QImode using movzbl */
564 {3, 4, 3}, /* cost of loading integer registers
565 in QImode, HImode and SImode.
566 Relative to reg-reg move (2). */
567 {3, 4, 3}, /* cost of storing integer registers */
568 4, /* cost of reg,reg fld/fst */
569 {4, 4, 12}, /* cost of loading fp registers
570 in SFmode, DFmode and XFmode */
571 {6, 6, 8}, /* cost of storing fp registers
572 in SFmode, DFmode and XFmode */
573 2, /* cost of moving MMX register */
574 {3, 3}, /* cost of loading MMX registers
575 in SImode and DImode */
576 {4, 4}, /* cost of storing MMX registers
577 in SImode and DImode */
578 2, /* cost of moving SSE register */
579 {4, 3, 6}, /* cost of loading SSE registers
580 in SImode, DImode and TImode */
581 {4, 4, 5}, /* cost of storing SSE registers
582 in SImode, DImode and TImode */
583 5, /* MMX or SSE register to integer */
584 64, /* size of prefetch block */
585 /* New AMD processors never drop prefetches; if they cannot be performed
586 immediately, they are queued. We set number of simultaneous prefetches
587 to a large constant to reflect this (it probably is not a good idea not
588 to limit number of prefetches at all, as their execution also takes some
590 100, /* number of parallel prefetches */
592 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
593 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
594 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
595 COSTS_N_INSNS (2), /* cost of FABS instruction. */
596 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
597 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
598 /* K8 has optimized REP instruction for medium sized blocks, but for very small
599 blocks it is better to use loop. For large blocks, libcall can do
600 nontemporary accesses and beat inline considerably. */
601 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
602 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
603 {{libcall, {{8, loop}, {24, unrolled_loop},
604 {2048, rep_prefix_4_byte}, {-1, libcall}}},
605 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
608 struct processor_costs amdfam10_cost = {
609 COSTS_N_INSNS (1), /* cost of an add instruction */
610 COSTS_N_INSNS (2), /* cost of a lea instruction */
611 COSTS_N_INSNS (1), /* variable shift costs */
612 COSTS_N_INSNS (1), /* constant shift costs */
613 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
614 COSTS_N_INSNS (4), /* HI */
615 COSTS_N_INSNS (3), /* SI */
616 COSTS_N_INSNS (4), /* DI */
617 COSTS_N_INSNS (5)}, /* other */
618 0, /* cost of multiply per each bit set */
619 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
620 COSTS_N_INSNS (35), /* HI */
621 COSTS_N_INSNS (51), /* SI */
622 COSTS_N_INSNS (83), /* DI */
623 COSTS_N_INSNS (83)}, /* other */
624 COSTS_N_INSNS (1), /* cost of movsx */
625 COSTS_N_INSNS (1), /* cost of movzx */
626 8, /* "large" insn */
628 4, /* cost for loading QImode using movzbl */
629 {3, 4, 3}, /* cost of loading integer registers
630 in QImode, HImode and SImode.
631 Relative to reg-reg move (2). */
632 {3, 4, 3}, /* cost of storing integer registers */
633 4, /* cost of reg,reg fld/fst */
634 {4, 4, 12}, /* cost of loading fp registers
635 in SFmode, DFmode and XFmode */
636 {6, 6, 8}, /* cost of storing fp registers
637 in SFmode, DFmode and XFmode */
638 2, /* cost of moving MMX register */
639 {3, 3}, /* cost of loading MMX registers
640 in SImode and DImode */
641 {4, 4}, /* cost of storing MMX registers
642 in SImode and DImode */
643 2, /* cost of moving SSE register */
644 {4, 4, 3}, /* cost of loading SSE registers
645 in SImode, DImode and TImode */
646 {4, 4, 5}, /* cost of storing SSE registers
647 in SImode, DImode and TImode */
648 3, /* MMX or SSE register to integer */
650 MOVD reg64, xmmreg Double FSTORE 4
651 MOVD reg32, xmmreg Double FSTORE 4
653 MOVD reg64, xmmreg Double FADD 3
655 MOVD reg32, xmmreg Double FADD 3
657 64, /* size of prefetch block */
658 /* New AMD processors never drop prefetches; if they cannot be performed
659 immediately, they are queued. We set number of simultaneous prefetches
660 to a large constant to reflect this (it probably is not a good idea not
661 to limit number of prefetches at all, as their execution also takes some
663 100, /* number of parallel prefetches */
665 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
666 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
667 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
668 COSTS_N_INSNS (2), /* cost of FABS instruction. */
669 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
670 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
672 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
673 very small blocks it is better to use loop. For large blocks, libcall can
674 do nontemporary accesses and beat inline considerably. */
675 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
676 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
677 {{libcall, {{8, loop}, {24, unrolled_loop},
678 {2048, rep_prefix_4_byte}, {-1, libcall}}},
679 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
683 struct processor_costs pentium4_cost = {
684 COSTS_N_INSNS (1), /* cost of an add instruction */
685 COSTS_N_INSNS (3), /* cost of a lea instruction */
686 COSTS_N_INSNS (4), /* variable shift costs */
687 COSTS_N_INSNS (4), /* constant shift costs */
688 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
689 COSTS_N_INSNS (15), /* HI */
690 COSTS_N_INSNS (15), /* SI */
691 COSTS_N_INSNS (15), /* DI */
692 COSTS_N_INSNS (15)}, /* other */
693 0, /* cost of multiply per each bit set */
694 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
695 COSTS_N_INSNS (56), /* HI */
696 COSTS_N_INSNS (56), /* SI */
697 COSTS_N_INSNS (56), /* DI */
698 COSTS_N_INSNS (56)}, /* other */
699 COSTS_N_INSNS (1), /* cost of movsx */
700 COSTS_N_INSNS (1), /* cost of movzx */
701 16, /* "large" insn */
703 2, /* cost for loading QImode using movzbl */
704 {4, 5, 4}, /* cost of loading integer registers
705 in QImode, HImode and SImode.
706 Relative to reg-reg move (2). */
707 {2, 3, 2}, /* cost of storing integer registers */
708 2, /* cost of reg,reg fld/fst */
709 {2, 2, 6}, /* cost of loading fp registers
710 in SFmode, DFmode and XFmode */
711 {4, 4, 6}, /* cost of storing fp registers
712 in SFmode, DFmode and XFmode */
713 2, /* cost of moving MMX register */
714 {2, 2}, /* cost of loading MMX registers
715 in SImode and DImode */
716 {2, 2}, /* cost of storing MMX registers
717 in SImode and DImode */
718 12, /* cost of moving SSE register */
719 {12, 12, 12}, /* cost of loading SSE registers
720 in SImode, DImode and TImode */
721 {2, 2, 8}, /* cost of storing SSE registers
722 in SImode, DImode and TImode */
723 10, /* MMX or SSE register to integer */
724 64, /* size of prefetch block */
725 6, /* number of parallel prefetches */
727 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
728 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
729 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
730 COSTS_N_INSNS (2), /* cost of FABS instruction. */
731 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
732 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
733 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
734 DUMMY_STRINGOP_ALGS},
735 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
737 DUMMY_STRINGOP_ALGS},
741 struct processor_costs nocona_cost = {
742 COSTS_N_INSNS (1), /* cost of an add instruction */
743 COSTS_N_INSNS (1), /* cost of a lea instruction */
744 COSTS_N_INSNS (1), /* variable shift costs */
745 COSTS_N_INSNS (1), /* constant shift costs */
746 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
747 COSTS_N_INSNS (10), /* HI */
748 COSTS_N_INSNS (10), /* SI */
749 COSTS_N_INSNS (10), /* DI */
750 COSTS_N_INSNS (10)}, /* other */
751 0, /* cost of multiply per each bit set */
752 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
753 COSTS_N_INSNS (66), /* HI */
754 COSTS_N_INSNS (66), /* SI */
755 COSTS_N_INSNS (66), /* DI */
756 COSTS_N_INSNS (66)}, /* other */
757 COSTS_N_INSNS (1), /* cost of movsx */
758 COSTS_N_INSNS (1), /* cost of movzx */
759 16, /* "large" insn */
761 4, /* cost for loading QImode using movzbl */
762 {4, 4, 4}, /* cost of loading integer registers
763 in QImode, HImode and SImode.
764 Relative to reg-reg move (2). */
765 {4, 4, 4}, /* cost of storing integer registers */
766 3, /* cost of reg,reg fld/fst */
767 {12, 12, 12}, /* cost of loading fp registers
768 in SFmode, DFmode and XFmode */
769 {4, 4, 4}, /* cost of storing fp registers
770 in SFmode, DFmode and XFmode */
771 6, /* cost of moving MMX register */
772 {12, 12}, /* cost of loading MMX registers
773 in SImode and DImode */
774 {12, 12}, /* cost of storing MMX registers
775 in SImode and DImode */
776 6, /* cost of moving SSE register */
777 {12, 12, 12}, /* cost of loading SSE registers
778 in SImode, DImode and TImode */
779 {12, 12, 12}, /* cost of storing SSE registers
780 in SImode, DImode and TImode */
781 8, /* MMX or SSE register to integer */
782 128, /* size of prefetch block */
783 8, /* number of parallel prefetches */
785 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
786 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
787 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
788 COSTS_N_INSNS (3), /* cost of FABS instruction. */
789 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
790 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
791 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
792 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
793 {100000, unrolled_loop}, {-1, libcall}}}},
794 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
796 {libcall, {{24, loop}, {64, unrolled_loop},
797 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
801 struct processor_costs core2_cost = {
802 COSTS_N_INSNS (1), /* cost of an add instruction */
803 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
804 COSTS_N_INSNS (1), /* variable shift costs */
805 COSTS_N_INSNS (1), /* constant shift costs */
806 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
807 COSTS_N_INSNS (3), /* HI */
808 COSTS_N_INSNS (3), /* SI */
809 COSTS_N_INSNS (3), /* DI */
810 COSTS_N_INSNS (3)}, /* other */
811 0, /* cost of multiply per each bit set */
812 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
813 COSTS_N_INSNS (22), /* HI */
814 COSTS_N_INSNS (22), /* SI */
815 COSTS_N_INSNS (22), /* DI */
816 COSTS_N_INSNS (22)}, /* other */
817 COSTS_N_INSNS (1), /* cost of movsx */
818 COSTS_N_INSNS (1), /* cost of movzx */
819 8, /* "large" insn */
821 2, /* cost for loading QImode using movzbl */
822 {6, 6, 6}, /* cost of loading integer registers
823 in QImode, HImode and SImode.
824 Relative to reg-reg move (2). */
825 {4, 4, 4}, /* cost of storing integer registers */
826 2, /* cost of reg,reg fld/fst */
827 {6, 6, 6}, /* cost of loading fp registers
828 in SFmode, DFmode and XFmode */
829 {4, 4, 4}, /* cost of loading integer registers */
830 2, /* cost of moving MMX register */
831 {6, 6}, /* cost of loading MMX registers
832 in SImode and DImode */
833 {4, 4}, /* cost of storing MMX registers
834 in SImode and DImode */
835 2, /* cost of moving SSE register */
836 {6, 6, 6}, /* cost of loading SSE registers
837 in SImode, DImode and TImode */
838 {4, 4, 4}, /* cost of storing SSE registers
839 in SImode, DImode and TImode */
840 2, /* MMX or SSE register to integer */
841 128, /* size of prefetch block */
842 8, /* number of parallel prefetches */
844 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
845 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
846 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
847 COSTS_N_INSNS (1), /* cost of FABS instruction. */
848 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
849 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
850 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
851 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
852 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
853 {{libcall, {{8, loop}, {15, unrolled_loop},
854 {2048, rep_prefix_4_byte}, {-1, libcall}}},
855 {libcall, {{24, loop}, {32, unrolled_loop},
856 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
859 /* Generic64 should produce code tuned for Nocona and K8. */
861 struct processor_costs generic64_cost = {
862 COSTS_N_INSNS (1), /* cost of an add instruction */
863 /* On all chips taken into consideration lea is 2 cycles and more. With
864 this cost however our current implementation of synth_mult results in
865 use of unnecessary temporary registers causing regression on several
866 SPECfp benchmarks. */
867 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
868 COSTS_N_INSNS (1), /* variable shift costs */
869 COSTS_N_INSNS (1), /* constant shift costs */
870 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
871 COSTS_N_INSNS (4), /* HI */
872 COSTS_N_INSNS (3), /* SI */
873 COSTS_N_INSNS (4), /* DI */
874 COSTS_N_INSNS (2)}, /* other */
875 0, /* cost of multiply per each bit set */
876 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
877 COSTS_N_INSNS (26), /* HI */
878 COSTS_N_INSNS (42), /* SI */
879 COSTS_N_INSNS (74), /* DI */
880 COSTS_N_INSNS (74)}, /* other */
881 COSTS_N_INSNS (1), /* cost of movsx */
882 COSTS_N_INSNS (1), /* cost of movzx */
883 8, /* "large" insn */
885 4, /* cost for loading QImode using movzbl */
886 {4, 4, 4}, /* cost of loading integer registers
887 in QImode, HImode and SImode.
888 Relative to reg-reg move (2). */
889 {4, 4, 4}, /* cost of storing integer registers */
890 4, /* cost of reg,reg fld/fst */
891 {12, 12, 12}, /* cost of loading fp registers
892 in SFmode, DFmode and XFmode */
893 {6, 6, 8}, /* cost of storing fp registers
894 in SFmode, DFmode and XFmode */
895 2, /* cost of moving MMX register */
896 {8, 8}, /* cost of loading MMX registers
897 in SImode and DImode */
898 {8, 8}, /* cost of storing MMX registers
899 in SImode and DImode */
900 2, /* cost of moving SSE register */
901 {8, 8, 8}, /* cost of loading SSE registers
902 in SImode, DImode and TImode */
903 {8, 8, 8}, /* cost of storing SSE registers
904 in SImode, DImode and TImode */
905 5, /* MMX or SSE register to integer */
906 64, /* size of prefetch block */
907 6, /* number of parallel prefetches */
908 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
909 is increased to perhaps more appropriate value of 5. */
911 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
912 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
913 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
914 COSTS_N_INSNS (8), /* cost of FABS instruction. */
915 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
916 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
917 {DUMMY_STRINGOP_ALGS,
918 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
919 {DUMMY_STRINGOP_ALGS,
920 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
923 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
925 struct processor_costs generic32_cost = {
926 COSTS_N_INSNS (1), /* cost of an add instruction */
927 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
928 COSTS_N_INSNS (1), /* variable shift costs */
929 COSTS_N_INSNS (1), /* constant shift costs */
930 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
931 COSTS_N_INSNS (4), /* HI */
932 COSTS_N_INSNS (3), /* SI */
933 COSTS_N_INSNS (4), /* DI */
934 COSTS_N_INSNS (2)}, /* other */
935 0, /* cost of multiply per each bit set */
936 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
937 COSTS_N_INSNS (26), /* HI */
938 COSTS_N_INSNS (42), /* SI */
939 COSTS_N_INSNS (74), /* DI */
940 COSTS_N_INSNS (74)}, /* other */
941 COSTS_N_INSNS (1), /* cost of movsx */
942 COSTS_N_INSNS (1), /* cost of movzx */
943 8, /* "large" insn */
945 4, /* cost for loading QImode using movzbl */
946 {4, 4, 4}, /* cost of loading integer registers
947 in QImode, HImode and SImode.
948 Relative to reg-reg move (2). */
949 {4, 4, 4}, /* cost of storing integer registers */
950 4, /* cost of reg,reg fld/fst */
951 {12, 12, 12}, /* cost of loading fp registers
952 in SFmode, DFmode and XFmode */
953 {6, 6, 8}, /* cost of storing fp registers
954 in SFmode, DFmode and XFmode */
955 2, /* cost of moving MMX register */
956 {8, 8}, /* cost of loading MMX registers
957 in SImode and DImode */
958 {8, 8}, /* cost of storing MMX registers
959 in SImode and DImode */
960 2, /* cost of moving SSE register */
961 {8, 8, 8}, /* cost of loading SSE registers
962 in SImode, DImode and TImode */
963 {8, 8, 8}, /* cost of storing SSE registers
964 in SImode, DImode and TImode */
965 5, /* MMX or SSE register to integer */
966 64, /* size of prefetch block */
967 6, /* number of parallel prefetches */
969 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
970 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
971 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
972 COSTS_N_INSNS (8), /* cost of FABS instruction. */
973 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
974 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
975 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
976 DUMMY_STRINGOP_ALGS},
977 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
978 DUMMY_STRINGOP_ALGS},
981 const struct processor_costs *ix86_cost = &pentium_cost;
983 /* Processor feature/optimization bitmasks. */
984 #define m_386 (1<<PROCESSOR_I386)
985 #define m_486 (1<<PROCESSOR_I486)
986 #define m_PENT (1<<PROCESSOR_PENTIUM)
987 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
988 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
989 #define m_NOCONA (1<<PROCESSOR_NOCONA)
990 #define m_CORE2 (1<<PROCESSOR_CORE2)
992 #define m_GEODE (1<<PROCESSOR_GEODE)
993 #define m_K6 (1<<PROCESSOR_K6)
994 #define m_K6_GEODE (m_K6 | m_GEODE)
995 #define m_K8 (1<<PROCESSOR_K8)
996 #define m_ATHLON (1<<PROCESSOR_ATHLON)
997 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
998 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
999 #define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
1001 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1002 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1004 /* Generic instruction choice should be common subset of supported CPUs
1005 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1006 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1008 /* Feature tests against the various tunings. */
1009 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1010 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1011 negatively, so enabling for Generic64 seems like good code size
1012 tradeoff. We can't enable it for 32bit generic because it does not
1013 work well with PPro base chips. */
1014 m_386 | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC64,
1016 /* X86_TUNE_PUSH_MEMORY */
1017 m_386 | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4
1018 | m_NOCONA | m_CORE2 | m_GENERIC,
1020 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1023 /* X86_TUNE_USE_BIT_TEST */
1026 /* X86_TUNE_UNROLL_STRLEN */
1027 m_486 | m_PENT | m_PPRO | m_ATHLON_K8_AMDFAM10 | m_K6 | m_CORE2 | m_GENERIC,
1029 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1030 m_PPRO | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_GENERIC,
1032 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1033 on simulation result. But after P4 was made, no performance benefit
1034 was observed with branch hints. It also increases the code size.
1035 As a result, icc never generates branch hints. */
1038 /* X86_TUNE_DOUBLE_WITH_ADD */
1041 /* X86_TUNE_USE_SAHF */
1042 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1043 | m_NOCONA | m_CORE2 | m_GENERIC,
1045 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1046 partial dependencies. */
1047 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_PENT4 | m_NOCONA
1048 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1050 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1051 register stalls on Generic32 compilation setting as well. However
1052 in current implementation the partial register stalls are not eliminated
1053 very well - they can be introduced via subregs synthesized by combine
1054 and can happen in caller/callee saving sequences. Because this option
1055 pays back little on PPro based chips and is in conflict with partial reg
1056 dependencies used by Athlon/P4 based chips, it is better to leave it off
1057 for generic32 for now. */
1060 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1061 m_CORE2 | m_GENERIC,
1063 /* X86_TUNE_USE_HIMODE_FIOP */
1064 m_386 | m_486 | m_K6_GEODE,
1066 /* X86_TUNE_USE_SIMODE_FIOP */
1067 ~(m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT | m_CORE2 | m_GENERIC),
1069 /* X86_TUNE_USE_MOV0 */
1072 /* X86_TUNE_USE_CLTD */
1073 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1075 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1078 /* X86_TUNE_SPLIT_LONG_MOVES */
1081 /* X86_TUNE_READ_MODIFY_WRITE */
1084 /* X86_TUNE_READ_MODIFY */
1087 /* X86_TUNE_PROMOTE_QIMODE */
1088 m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8_AMDFAM10 | m_CORE2
1089 | m_GENERIC /* | m_PENT4 ? */,
1091 /* X86_TUNE_FAST_PREFIX */
1092 ~(m_PENT | m_486 | m_386),
1094 /* X86_TUNE_SINGLE_STRINGOP */
1095 m_386 | m_PENT4 | m_NOCONA,
1097 /* X86_TUNE_QIMODE_MATH */
1100 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1101 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1102 might be considered for Generic32 if our scheme for avoiding partial
1103 stalls was more effective. */
1106 /* X86_TUNE_PROMOTE_QI_REGS */
1109 /* X86_TUNE_PROMOTE_HI_REGS */
1112 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1113 m_ATHLON_K8_AMDFAM10 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1115 /* X86_TUNE_ADD_ESP_8 */
1116 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_K6_GEODE | m_386
1117 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1119 /* X86_TUNE_SUB_ESP_4 */
1120 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1122 /* X86_TUNE_SUB_ESP_8 */
1123 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_386 | m_486
1124 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1126 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1127 for DFmode copies */
1128 ~(m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1129 | m_GENERIC | m_GEODE),
1131 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1132 m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1134 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1135 conflict here in between PPro/Pentium4 based chips that thread 128bit
1136 SSE registers as single units versus K8 based chips that divide SSE
1137 registers to two 64bit halves. This knob promotes all store destinations
1138 to be 128bit to allow register renaming on 128bit SSE units, but usually
1139 results in one extra microop on 64bit SSE units. Experimental results
1140 shows that disabling this option on P4 brings over 20% SPECfp regression,
1141 while enabling it on K8 brings roughly 2.4% regression that can be partly
1142 masked by careful scheduling of moves. */
1143 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1145 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1148 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1149 are resolved on SSE register parts instead of whole registers, so we may
1150 maintain just lower part of scalar values in proper format leaving the
1151 upper part undefined. */
1154 /* X86_TUNE_SSE_TYPELESS_STORES */
1155 m_ATHLON_K8_AMDFAM10,
1157 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1158 m_PPRO | m_PENT4 | m_NOCONA,
1160 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1161 m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1163 /* X86_TUNE_PROLOGUE_USING_MOVE */
1164 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1166 /* X86_TUNE_EPILOGUE_USING_MOVE */
1167 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1169 /* X86_TUNE_SHIFT1 */
1172 /* X86_TUNE_USE_FFREEP */
1173 m_ATHLON_K8_AMDFAM10,
1175 /* X86_TUNE_INTER_UNIT_MOVES */
1176 ~(m_ATHLON_K8_AMDFAM10 | m_GENERIC),
1178 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1179 than 4 branch instructions in the 16 byte window. */
1180 m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1182 /* X86_TUNE_SCHEDULE */
1183 m_PPRO | m_ATHLON_K8_AMDFAM10 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1185 /* X86_TUNE_USE_BT */
1186 m_ATHLON_K8_AMDFAM10,
1188 /* X86_TUNE_USE_INCDEC */
1189 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1191 /* X86_TUNE_PAD_RETURNS */
1192 m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC,
1194 /* X86_TUNE_EXT_80387_CONSTANTS */
1195 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1197 /* X86_TUNE_SHORTEN_X87_SSE */
1200 /* X86_TUNE_AVOID_VECTOR_DECODE */
1203 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1204 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1207 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1208 vector path on AMD machines. */
1209 m_K8 | m_GENERIC64 | m_AMDFAM10,
1211 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1213 m_K8 | m_GENERIC64 | m_AMDFAM10,
1215 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1219 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1220 but one byte longer. */
1223 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1224 operand that cannot be represented using a modRM byte. The XOR
1225 replacement is long decoded, so this split helps here as well. */
1229 /* Feature tests against the various architecture variations. */
1230 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1231 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1232 ~(m_386 | m_486 | m_PENT | m_K6),
1234 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1237 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1240 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1243 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1247 static const unsigned int x86_accumulate_outgoing_args
1248 = m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1250 static const unsigned int x86_arch_always_fancy_math_387
1251 = m_PENT | m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT4
1252 | m_NOCONA | m_CORE2 | m_GENERIC;
1254 static enum stringop_alg stringop_alg = no_stringop;
1256 /* In case the average insn count for single function invocation is
1257 lower than this constant, emit fast (but longer) prologue and
1259 #define FAST_PROLOGUE_INSN_COUNT 20
1261 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1262 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1263 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1264 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1266 /* Array of the smallest class containing reg number REGNO, indexed by
1267 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1269 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1271 /* ax, dx, cx, bx */
1272 AREG, DREG, CREG, BREG,
1273 /* si, di, bp, sp */
1274 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1276 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1277 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1280 /* flags, fpsr, fpcr, frame */
1281 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1283 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1286 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1289 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1290 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1291 /* SSE REX registers */
1292 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1296 /* The "default" register map used in 32bit mode. */
1298 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1300 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1301 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1302 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1303 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1304 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1305 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1306 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1309 static int const x86_64_int_parameter_registers[6] =
1311 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1312 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1315 static int const x86_64_ms_abi_int_parameter_registers[4] =
1317 2 /*RCX*/, 1 /*RDX*/,
1318 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1321 static int const x86_64_int_return_registers[4] =
1323 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1326 /* The "default" register map used in 64bit mode. */
1327 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1329 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1330 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1331 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1332 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1333 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1334 8,9,10,11,12,13,14,15, /* extended integer registers */
1335 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1338 /* Define the register numbers to be used in Dwarf debugging information.
1339 The SVR4 reference port C compiler uses the following register numbers
1340 in its Dwarf output code:
1341 0 for %eax (gcc regno = 0)
1342 1 for %ecx (gcc regno = 2)
1343 2 for %edx (gcc regno = 1)
1344 3 for %ebx (gcc regno = 3)
1345 4 for %esp (gcc regno = 7)
1346 5 for %ebp (gcc regno = 6)
1347 6 for %esi (gcc regno = 4)
1348 7 for %edi (gcc regno = 5)
1349 The following three DWARF register numbers are never generated by
1350 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1351 believes these numbers have these meanings.
1352 8 for %eip (no gcc equivalent)
1353 9 for %eflags (gcc regno = 17)
1354 10 for %trapno (no gcc equivalent)
1355 It is not at all clear how we should number the FP stack registers
1356 for the x86 architecture. If the version of SDB on x86/svr4 were
1357 a bit less brain dead with respect to floating-point then we would
1358 have a precedent to follow with respect to DWARF register numbers
1359 for x86 FP registers, but the SDB on x86/svr4 is so completely
1360 broken with respect to FP registers that it is hardly worth thinking
1361 of it as something to strive for compatibility with.
1362 The version of x86/svr4 SDB I have at the moment does (partially)
1363 seem to believe that DWARF register number 11 is associated with
1364 the x86 register %st(0), but that's about all. Higher DWARF
1365 register numbers don't seem to be associated with anything in
1366 particular, and even for DWARF regno 11, SDB only seems to under-
1367 stand that it should say that a variable lives in %st(0) (when
1368 asked via an `=' command) if we said it was in DWARF regno 11,
1369 but SDB still prints garbage when asked for the value of the
1370 variable in question (via a `/' command).
1371 (Also note that the labels SDB prints for various FP stack regs
1372 when doing an `x' command are all wrong.)
1373 Note that these problems generally don't affect the native SVR4
1374 C compiler because it doesn't allow the use of -O with -g and
1375 because when it is *not* optimizing, it allocates a memory
1376 location for each floating-point variable, and the memory
1377 location is what gets described in the DWARF AT_location
1378 attribute for the variable in question.
1379 Regardless of the severe mental illness of the x86/svr4 SDB, we
1380 do something sensible here and we use the following DWARF
1381 register numbers. Note that these are all stack-top-relative
1383 11 for %st(0) (gcc regno = 8)
1384 12 for %st(1) (gcc regno = 9)
1385 13 for %st(2) (gcc regno = 10)
1386 14 for %st(3) (gcc regno = 11)
1387 15 for %st(4) (gcc regno = 12)
1388 16 for %st(5) (gcc regno = 13)
1389 17 for %st(6) (gcc regno = 14)
1390 18 for %st(7) (gcc regno = 15)
1392 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1394 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1395 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1396 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1397 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1398 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1399 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1400 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1403 /* Test and compare insns in i386.md store the information needed to
1404 generate branch and scc insns here. */
1406 rtx ix86_compare_op0 = NULL_RTX;
1407 rtx ix86_compare_op1 = NULL_RTX;
1408 rtx ix86_compare_emitted = NULL_RTX;
1410 /* Size of the register save area. */
1411 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1413 /* Define the structure for the machine field in struct function. */
1415 struct stack_local_entry GTY(())
1417 unsigned short mode;
1420 struct stack_local_entry *next;
1423 /* Structure describing stack frame layout.
1424 Stack grows downward:
1430 saved frame pointer if frame_pointer_needed
1431 <- HARD_FRAME_POINTER
1436 [va_arg registers] (
1437 > to_allocate <- FRAME_POINTER
1447 HOST_WIDE_INT frame;
1449 int outgoing_arguments_size;
1452 HOST_WIDE_INT to_allocate;
1453 /* The offsets relative to ARG_POINTER. */
1454 HOST_WIDE_INT frame_pointer_offset;
1455 HOST_WIDE_INT hard_frame_pointer_offset;
1456 HOST_WIDE_INT stack_pointer_offset;
1458 /* When save_regs_using_mov is set, emit prologue using
1459 move instead of push instructions. */
1460 bool save_regs_using_mov;
1463 /* Code model option. */
1464 enum cmodel ix86_cmodel;
1466 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1468 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1470 /* Which unit we are generating floating point math for. */
1471 enum fpmath_unit ix86_fpmath;
1473 /* Which cpu are we scheduling for. */
1474 enum processor_type ix86_tune;
1476 /* Which instruction set architecture to use. */
1477 enum processor_type ix86_arch;
1479 /* true if sse prefetch instruction is not NOOP. */
1480 int x86_prefetch_sse;
1482 /* ix86_regparm_string as a number */
1483 static int ix86_regparm;
1485 /* -mstackrealign option */
1486 extern int ix86_force_align_arg_pointer;
1487 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1489 /* Preferred alignment for stack boundary in bits. */
1490 unsigned int ix86_preferred_stack_boundary;
1492 /* Values 1-5: see jump.c */
1493 int ix86_branch_cost;
1495 /* Variables which are this size or smaller are put in the data/bss
1496 or ldata/lbss sections. */
1498 int ix86_section_threshold = 65536;
1500 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1501 char internal_label_prefix[16];
1502 int internal_label_prefix_len;
1504 /* Fence to use after loop using movnt. */
1507 /* Register class used for passing given 64bit part of the argument.
1508 These represent classes as documented by the PS ABI, with the exception
1509 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1510 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1512 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1513 whenever possible (upper half does contain padding). */
1514 enum x86_64_reg_class
1517 X86_64_INTEGER_CLASS,
1518 X86_64_INTEGERSI_CLASS,
1525 X86_64_COMPLEX_X87_CLASS,
1528 static const char * const x86_64_reg_class_name[] =
1530 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1531 "sseup", "x87", "x87up", "cplx87", "no"
1534 #define MAX_CLASSES 4
1536 /* Table of constants used by fldpi, fldln2, etc.... */
1537 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1538 static bool ext_80387_constants_init = 0;
1541 static struct machine_function * ix86_init_machine_status (void);
1542 static rtx ix86_function_value (tree, tree, bool);
1543 static int ix86_function_regparm (tree, tree);
1544 static void ix86_compute_frame_layout (struct ix86_frame *);
1545 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1549 /* The svr4 ABI for the i386 says that records and unions are returned
1551 #ifndef DEFAULT_PCC_STRUCT_RETURN
1552 #define DEFAULT_PCC_STRUCT_RETURN 1
1555 /* Bit flags that specify the ISA we are compiling for. */
1556 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1558 /* A mask of ix86_isa_flags that includes bit X if X
1559 was set or cleared on the command line. */
1560 static int ix86_isa_flags_explicit;
1562 /* Define a set of ISAs which aren't available for a given ISA. MMX
1563 and SSE ISAs are handled separately. */
1565 #define OPTION_MASK_ISA_MMX_UNSET \
1566 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_UNSET)
1567 #define OPTION_MASK_ISA_3DNOW_UNSET OPTION_MASK_ISA_3DNOW_A
1569 #define OPTION_MASK_ISA_SSE_UNSET \
1570 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE2_UNSET)
1571 #define OPTION_MASK_ISA_SSE2_UNSET \
1572 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE3_UNSET)
1573 #define OPTION_MASK_ISA_SSE3_UNSET \
1574 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSSE3_UNSET)
1575 #define OPTION_MASK_ISA_SSSE3_UNSET \
1576 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_1_UNSET)
1577 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1578 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_2_UNSET)
1579 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4A
1581 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1582 as -msse4.1 -msse4.2. -mno-sse4 should the same as -mno-sse4.1. */
1583 #define OPTION_MASK_ISA_SSE4 \
1584 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2)
1585 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1587 #define OPTION_MASK_ISA_SSE4A_UNSET OPTION_MASK_ISA_SSE4
1589 /* Implement TARGET_HANDLE_OPTION. */
1592 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1597 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX;
1600 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1601 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1606 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW;
1609 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1610 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1618 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE;
1621 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1622 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1627 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2;
1630 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1631 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1636 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3;
1639 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1640 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1645 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3;
1648 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1649 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1654 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1;
1657 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1658 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1663 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2;
1666 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1667 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1672 ix86_isa_flags |= OPTION_MASK_ISA_SSE4;
1673 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4;
1677 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1678 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1682 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A;
1685 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1686 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1695 /* Sometimes certain combinations of command options do not make
1696 sense on a particular target machine. You can define a macro
1697 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1698 defined, is executed once just after all the command options have
1701 Don't use this macro to turn on various extra optimizations for
1702 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1705 override_options (void)
1708 int ix86_tune_defaulted = 0;
1709 int ix86_arch_specified = 0;
1710 unsigned int ix86_arch_mask, ix86_tune_mask;
1712 /* Comes from final.c -- no real reason to change it. */
1713 #define MAX_CODE_ALIGN 16
1717 const struct processor_costs *cost; /* Processor costs */
1718 const int align_loop; /* Default alignments. */
1719 const int align_loop_max_skip;
1720 const int align_jump;
1721 const int align_jump_max_skip;
1722 const int align_func;
1724 const processor_target_table[PROCESSOR_max] =
1726 {&i386_cost, 4, 3, 4, 3, 4},
1727 {&i486_cost, 16, 15, 16, 15, 16},
1728 {&pentium_cost, 16, 7, 16, 7, 16},
1729 {&pentiumpro_cost, 16, 15, 16, 7, 16},
1730 {&geode_cost, 0, 0, 0, 0, 0},
1731 {&k6_cost, 32, 7, 32, 7, 32},
1732 {&athlon_cost, 16, 7, 16, 7, 16},
1733 {&pentium4_cost, 0, 0, 0, 0, 0},
1734 {&k8_cost, 16, 7, 16, 7, 16},
1735 {&nocona_cost, 0, 0, 0, 0, 0},
1736 {&core2_cost, 16, 7, 16, 7, 16},
1737 {&generic32_cost, 16, 7, 16, 7, 16},
1738 {&generic64_cost, 16, 7, 16, 7, 16},
1739 {&amdfam10_cost, 32, 24, 32, 7, 32}
1742 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1749 PTA_PREFETCH_SSE = 1 << 4,
1751 PTA_3DNOW_A = 1 << 6,
1755 PTA_POPCNT = 1 << 10,
1757 PTA_SSE4A = 1 << 12,
1758 PTA_NO_SAHF = 1 << 13,
1759 PTA_SSE4_1 = 1 << 14,
1760 PTA_SSE4_2 = 1 << 15
1765 const char *const name; /* processor name or nickname. */
1766 const enum processor_type processor;
1767 const unsigned /*enum pta_flags*/ flags;
1769 const processor_alias_table[] =
1771 {"i386", PROCESSOR_I386, 0},
1772 {"i486", PROCESSOR_I486, 0},
1773 {"i586", PROCESSOR_PENTIUM, 0},
1774 {"pentium", PROCESSOR_PENTIUM, 0},
1775 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1776 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1777 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1778 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1779 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
1780 {"i686", PROCESSOR_PENTIUMPRO, 0},
1781 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1782 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1783 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
1784 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
1785 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
1786 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
1787 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
1788 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
1789 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
1790 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1791 | PTA_CX16 | PTA_NO_SAHF)},
1792 {"core2", PROCESSOR_CORE2, (PTA_64BIT
1793 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1796 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1797 |PTA_PREFETCH_SSE)},
1798 {"k6", PROCESSOR_K6, PTA_MMX},
1799 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1800 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1801 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1802 | PTA_PREFETCH_SSE)},
1803 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1804 | PTA_PREFETCH_SSE)},
1805 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1807 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1809 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1811 {"x86-64", PROCESSOR_K8, (PTA_64BIT
1812 | PTA_MMX | PTA_SSE | PTA_SSE2
1814 {"k8", PROCESSOR_K8, (PTA_64BIT
1815 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1816 | PTA_SSE | PTA_SSE2
1818 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
1819 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1820 | PTA_SSE | PTA_SSE2 | PTA_SSE3
1822 {"opteron", PROCESSOR_K8, (PTA_64BIT
1823 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1824 | PTA_SSE | PTA_SSE2
1826 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
1827 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1828 | PTA_SSE | PTA_SSE2 | PTA_SSE3
1830 {"athlon64", PROCESSOR_K8, (PTA_64BIT
1831 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1832 | PTA_SSE | PTA_SSE2
1834 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
1835 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1836 | PTA_SSE | PTA_SSE2 | PTA_SSE3
1838 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
1839 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1840 | PTA_SSE | PTA_SSE2
1842 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
1843 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1844 | PTA_SSE | PTA_SSE2 | PTA_SSE3
1846 | PTA_CX16 | PTA_ABM)},
1847 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
1848 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
1849 | PTA_SSE | PTA_SSE2 | PTA_SSE3
1851 | PTA_CX16 | PTA_ABM)},
1852 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1853 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1856 int const pta_size = ARRAY_SIZE (processor_alias_table);
1858 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1859 SUBTARGET_OVERRIDE_OPTIONS;
1862 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1863 SUBSUBTARGET_OVERRIDE_OPTIONS;
1866 /* -fPIC is the default for x86_64. */
1867 if (TARGET_MACHO && TARGET_64BIT)
1870 /* Set the default values for switches whose default depends on TARGET_64BIT
1871 in case they weren't overwritten by command line options. */
1874 /* Mach-O doesn't support omitting the frame pointer for now. */
1875 if (flag_omit_frame_pointer == 2)
1876 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
1877 if (flag_asynchronous_unwind_tables == 2)
1878 flag_asynchronous_unwind_tables = 1;
1879 if (flag_pcc_struct_return == 2)
1880 flag_pcc_struct_return = 0;
1884 if (flag_omit_frame_pointer == 2)
1885 flag_omit_frame_pointer = 0;
1886 if (flag_asynchronous_unwind_tables == 2)
1887 flag_asynchronous_unwind_tables = 0;
1888 if (flag_pcc_struct_return == 2)
1889 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1892 /* Need to check -mtune=generic first. */
1893 if (ix86_tune_string)
1895 if (!strcmp (ix86_tune_string, "generic")
1896 || !strcmp (ix86_tune_string, "i686")
1897 /* As special support for cross compilers we read -mtune=native
1898 as -mtune=generic. With native compilers we won't see the
1899 -mtune=native, as it was changed by the driver. */
1900 || !strcmp (ix86_tune_string, "native"))
1903 ix86_tune_string = "generic64";
1905 ix86_tune_string = "generic32";
1907 else if (!strncmp (ix86_tune_string, "generic", 7))
1908 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1912 if (ix86_arch_string)
1913 ix86_tune_string = ix86_arch_string;
1914 if (!ix86_tune_string)
1916 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1917 ix86_tune_defaulted = 1;
1920 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
1921 need to use a sensible tune option. */
1922 if (!strcmp (ix86_tune_string, "generic")
1923 || !strcmp (ix86_tune_string, "x86-64")
1924 || !strcmp (ix86_tune_string, "i686"))
1927 ix86_tune_string = "generic64";
1929 ix86_tune_string = "generic32";
1932 if (ix86_stringop_string)
1934 if (!strcmp (ix86_stringop_string, "rep_byte"))
1935 stringop_alg = rep_prefix_1_byte;
1936 else if (!strcmp (ix86_stringop_string, "libcall"))
1937 stringop_alg = libcall;
1938 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
1939 stringop_alg = rep_prefix_4_byte;
1940 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
1941 stringop_alg = rep_prefix_8_byte;
1942 else if (!strcmp (ix86_stringop_string, "byte_loop"))
1943 stringop_alg = loop_1_byte;
1944 else if (!strcmp (ix86_stringop_string, "loop"))
1945 stringop_alg = loop;
1946 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
1947 stringop_alg = unrolled_loop;
1949 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
1951 if (!strcmp (ix86_tune_string, "x86-64"))
1952 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
1953 "-mtune=generic instead as appropriate.");
1955 if (!ix86_arch_string)
1956 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1958 ix86_arch_specified = 1;
1960 if (!strcmp (ix86_arch_string, "generic"))
1961 error ("generic CPU can be used only for -mtune= switch");
1962 if (!strncmp (ix86_arch_string, "generic", 7))
1963 error ("bad value (%s) for -march= switch", ix86_arch_string);
1965 if (ix86_cmodel_string != 0)
1967 if (!strcmp (ix86_cmodel_string, "small"))
1968 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1969 else if (!strcmp (ix86_cmodel_string, "medium"))
1970 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1971 else if (!strcmp (ix86_cmodel_string, "large"))
1972 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
1974 error ("code model %s does not support PIC mode", ix86_cmodel_string);
1975 else if (!strcmp (ix86_cmodel_string, "32"))
1976 ix86_cmodel = CM_32;
1977 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1978 ix86_cmodel = CM_KERNEL;
1980 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1984 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
1985 use of rip-relative addressing. This eliminates fixups that
1986 would otherwise be needed if this object is to be placed in a
1987 DLL, and is essentially just as efficient as direct addressing. */
1988 if (TARGET_64BIT_MS_ABI)
1989 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
1990 else if (TARGET_64BIT)
1991 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1993 ix86_cmodel = CM_32;
1995 if (ix86_asm_string != 0)
1998 && !strcmp (ix86_asm_string, "intel"))
1999 ix86_asm_dialect = ASM_INTEL;
2000 else if (!strcmp (ix86_asm_string, "att"))
2001 ix86_asm_dialect = ASM_ATT;
2003 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2005 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2006 error ("code model %qs not supported in the %s bit mode",
2007 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2008 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2009 sorry ("%i-bit mode not compiled in",
2010 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2012 for (i = 0; i < pta_size; i++)
2013 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2015 ix86_arch = processor_alias_table[i].processor;
2016 /* Default cpu tuning to the architecture. */
2017 ix86_tune = ix86_arch;
2019 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2020 error ("CPU you selected does not support x86-64 "
2023 if (processor_alias_table[i].flags & PTA_MMX
2024 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2025 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2026 if (processor_alias_table[i].flags & PTA_3DNOW
2027 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2028 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2029 if (processor_alias_table[i].flags & PTA_3DNOW_A
2030 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2031 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2032 if (processor_alias_table[i].flags & PTA_SSE
2033 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2034 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2035 if (processor_alias_table[i].flags & PTA_SSE2
2036 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2037 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2038 if (processor_alias_table[i].flags & PTA_SSE3
2039 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2040 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2041 if (processor_alias_table[i].flags & PTA_SSSE3
2042 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2043 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2044 if (processor_alias_table[i].flags & PTA_SSE4_1
2045 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2046 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2047 if (processor_alias_table[i].flags & PTA_SSE4_2
2048 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2049 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2050 if (processor_alias_table[i].flags & PTA_SSE4A
2051 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2052 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2054 if (processor_alias_table[i].flags & PTA_ABM)
2056 if (processor_alias_table[i].flags & PTA_CX16)
2057 x86_cmpxchg16b = true;
2058 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2060 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2061 x86_prefetch_sse = true;
2062 if ((processor_alias_table[i].flags & PTA_NO_SAHF) && !TARGET_64BIT)
2069 error ("bad value (%s) for -march= switch", ix86_arch_string);
2071 ix86_arch_mask = 1u << ix86_arch;
2072 for (i = 0; i < X86_ARCH_LAST; ++i)
2073 ix86_arch_features[i] &= ix86_arch_mask;
2075 for (i = 0; i < pta_size; i++)
2076 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2078 ix86_tune = processor_alias_table[i].processor;
2079 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2081 if (ix86_tune_defaulted)
2083 ix86_tune_string = "x86-64";
2084 for (i = 0; i < pta_size; i++)
2085 if (! strcmp (ix86_tune_string,
2086 processor_alias_table[i].name))
2088 ix86_tune = processor_alias_table[i].processor;
2091 error ("CPU you selected does not support x86-64 "
2094 /* Intel CPUs have always interpreted SSE prefetch instructions as
2095 NOPs; so, we can enable SSE prefetch instructions even when
2096 -mtune (rather than -march) points us to a processor that has them.
2097 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2098 higher processors. */
2100 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2101 x86_prefetch_sse = true;
2105 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2107 ix86_tune_mask = 1u << ix86_tune;
2108 for (i = 0; i < X86_TUNE_LAST; ++i)
2109 ix86_tune_features[i] &= ix86_tune_mask;
2112 ix86_cost = &size_cost;
2114 ix86_cost = processor_target_table[ix86_tune].cost;
2116 /* Arrange to set up i386_stack_locals for all functions. */
2117 init_machine_status = ix86_init_machine_status;
2119 /* Validate -mregparm= value. */
2120 if (ix86_regparm_string)
2123 warning (0, "-mregparm is ignored in 64-bit mode");
2124 i = atoi (ix86_regparm_string);
2125 if (i < 0 || i > REGPARM_MAX)
2126 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2131 ix86_regparm = REGPARM_MAX;
2133 /* If the user has provided any of the -malign-* options,
2134 warn and use that value only if -falign-* is not set.
2135 Remove this code in GCC 3.2 or later. */
2136 if (ix86_align_loops_string)
2138 warning (0, "-malign-loops is obsolete, use -falign-loops");
2139 if (align_loops == 0)
2141 i = atoi (ix86_align_loops_string);
2142 if (i < 0 || i > MAX_CODE_ALIGN)
2143 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2145 align_loops = 1 << i;
2149 if (ix86_align_jumps_string)
2151 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2152 if (align_jumps == 0)
2154 i = atoi (ix86_align_jumps_string);
2155 if (i < 0 || i > MAX_CODE_ALIGN)
2156 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2158 align_jumps = 1 << i;
2162 if (ix86_align_funcs_string)
2164 warning (0, "-malign-functions is obsolete, use -falign-functions");
2165 if (align_functions == 0)
2167 i = atoi (ix86_align_funcs_string);
2168 if (i < 0 || i > MAX_CODE_ALIGN)
2169 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2171 align_functions = 1 << i;
2175 /* Default align_* from the processor table. */
2176 if (align_loops == 0)
2178 align_loops = processor_target_table[ix86_tune].align_loop;
2179 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2181 if (align_jumps == 0)
2183 align_jumps = processor_target_table[ix86_tune].align_jump;
2184 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2186 if (align_functions == 0)
2188 align_functions = processor_target_table[ix86_tune].align_func;
2191 /* Validate -mbranch-cost= value, or provide default. */
2192 ix86_branch_cost = ix86_cost->branch_cost;
2193 if (ix86_branch_cost_string)
2195 i = atoi (ix86_branch_cost_string);
2197 error ("-mbranch-cost=%d is not between 0 and 5", i);
2199 ix86_branch_cost = i;
2201 if (ix86_section_threshold_string)
2203 i = atoi (ix86_section_threshold_string);
2205 error ("-mlarge-data-threshold=%d is negative", i);
2207 ix86_section_threshold = i;
2210 if (ix86_tls_dialect_string)
2212 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2213 ix86_tls_dialect = TLS_DIALECT_GNU;
2214 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2215 ix86_tls_dialect = TLS_DIALECT_GNU2;
2216 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2217 ix86_tls_dialect = TLS_DIALECT_SUN;
2219 error ("bad value (%s) for -mtls-dialect= switch",
2220 ix86_tls_dialect_string);
2223 if (ix87_precision_string)
2225 i = atoi (ix87_precision_string);
2226 if (i != 32 && i != 64 && i != 80)
2227 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2232 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2234 /* Enable by default the SSE and MMX builtins. Do allow the user to
2235 explicitly disable any of these. In particular, disabling SSE and
2236 MMX for kernel code is extremely useful. */
2237 if (!ix86_arch_specified)
2239 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2240 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2243 warning (0, "-mrtd is ignored in 64bit mode");
2247 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2249 if (!ix86_arch_specified)
2251 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2253 /* i386 ABI does not specify red zone. It still makes sense to use it
2254 when programmer takes care to stack from being destroyed. */
2255 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2256 target_flags |= MASK_NO_RED_ZONE;
2259 /* Keep nonleaf frame pointers. */
2260 if (flag_omit_frame_pointer)
2261 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2262 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2263 flag_omit_frame_pointer = 1;
2265 /* If we're doing fast math, we don't care about comparison order
2266 wrt NaNs. This lets us use a shorter comparison sequence. */
2267 if (flag_finite_math_only)
2268 target_flags &= ~MASK_IEEE_FP;
2270 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2271 since the insns won't need emulation. */
2272 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2273 target_flags &= ~MASK_NO_FANCY_MATH_387;
2275 /* Likewise, if the target doesn't have a 387, or we've specified
2276 software floating point, don't use 387 inline intrinsics. */
2278 target_flags |= MASK_NO_FANCY_MATH_387;
2280 /* Turn on SSE4.1 builtins for -msse4.2. */
2282 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2284 /* Turn on SSSE3 builtins for -msse4.1. */
2286 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2288 /* Turn on SSE3 builtins for -mssse3. */
2290 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2292 /* Turn on SSE3 builtins for -msse4a. */
2294 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2296 /* Turn on SSE2 builtins for -msse3. */
2298 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2300 /* Turn on SSE builtins for -msse2. */
2302 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2304 /* Turn on MMX builtins for -msse. */
2307 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2308 x86_prefetch_sse = true;
2311 /* Turn on MMX builtins for 3Dnow. */
2313 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2315 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2316 if (TARGET_SSE4_2 || TARGET_ABM)
2319 /* Validate -mpreferred-stack-boundary= value, or provide default.
2320 The default of 128 bits is for Pentium III's SSE __m128. We can't
2321 change it because of optimize_size. Otherwise, we can't mix object
2322 files compiled with -Os and -On. */
2323 ix86_preferred_stack_boundary = 128;
2324 if (ix86_preferred_stack_boundary_string)
2326 i = atoi (ix86_preferred_stack_boundary_string);
2327 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2328 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2329 TARGET_64BIT ? 4 : 2);
2331 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2334 /* Accept -msseregparm only if at least SSE support is enabled. */
2335 if (TARGET_SSEREGPARM
2337 error ("-msseregparm used without SSE enabled");
2339 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2340 if (ix86_fpmath_string != 0)
2342 if (! strcmp (ix86_fpmath_string, "387"))
2343 ix86_fpmath = FPMATH_387;
2344 else if (! strcmp (ix86_fpmath_string, "sse"))
2348 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2349 ix86_fpmath = FPMATH_387;
2352 ix86_fpmath = FPMATH_SSE;
2354 else if (! strcmp (ix86_fpmath_string, "387,sse")
2355 || ! strcmp (ix86_fpmath_string, "sse,387"))
2359 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2360 ix86_fpmath = FPMATH_387;
2362 else if (!TARGET_80387)
2364 warning (0, "387 instruction set disabled, using SSE arithmetics");
2365 ix86_fpmath = FPMATH_SSE;
2368 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2371 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2374 /* If the i387 is disabled, then do not return values in it. */
2376 target_flags &= ~MASK_FLOAT_RETURNS;
2378 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2379 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2381 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2383 /* ??? Unwind info is not correct around the CFG unless either a frame
2384 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2385 unwind info generation to be aware of the CFG and propagating states
2387 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2388 || flag_exceptions || flag_non_call_exceptions)
2389 && flag_omit_frame_pointer
2390 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2392 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2393 warning (0, "unwind tables currently require either a frame pointer "
2394 "or -maccumulate-outgoing-args for correctness");
2395 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2398 /* For sane SSE instruction set generation we need fcomi instruction.
2399 It is safe to enable all CMOVE instructions. */
2403 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2406 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2407 p = strchr (internal_label_prefix, 'X');
2408 internal_label_prefix_len = p - internal_label_prefix;
2412 /* When scheduling description is not available, disable scheduler pass
2413 so it won't slow down the compilation and make x87 code slower. */
2414 if (!TARGET_SCHEDULE)
2415 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2417 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2418 set_param_value ("simultaneous-prefetches",
2419 ix86_cost->simultaneous_prefetches);
2420 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2421 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2424 /* Return true if this goes in large data/bss. */
2427 ix86_in_large_data_p (tree exp)
2429 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2432 /* Functions are never large data. */
2433 if (TREE_CODE (exp) == FUNCTION_DECL)
2436 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2438 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2439 if (strcmp (section, ".ldata") == 0
2440 || strcmp (section, ".lbss") == 0)
2446 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2448 /* If this is an incomplete type with size 0, then we can't put it
2449 in data because it might be too big when completed. */
2450 if (!size || size > ix86_section_threshold)
2457 /* Switch to the appropriate section for output of DECL.
2458 DECL is either a `VAR_DECL' node or a constant of some sort.
2459 RELOC indicates whether forming the initial value of DECL requires
2460 link-time relocations. */
2462 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2466 x86_64_elf_select_section (tree decl, int reloc,
2467 unsigned HOST_WIDE_INT align)
2469 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2470 && ix86_in_large_data_p (decl))
2472 const char *sname = NULL;
2473 unsigned int flags = SECTION_WRITE;
2474 switch (categorize_decl_for_section (decl, reloc))
2479 case SECCAT_DATA_REL:
2480 sname = ".ldata.rel";
2482 case SECCAT_DATA_REL_LOCAL:
2483 sname = ".ldata.rel.local";
2485 case SECCAT_DATA_REL_RO:
2486 sname = ".ldata.rel.ro";
2488 case SECCAT_DATA_REL_RO_LOCAL:
2489 sname = ".ldata.rel.ro.local";
2493 flags |= SECTION_BSS;
2496 case SECCAT_RODATA_MERGE_STR:
2497 case SECCAT_RODATA_MERGE_STR_INIT:
2498 case SECCAT_RODATA_MERGE_CONST:
2502 case SECCAT_SRODATA:
2509 /* We don't split these for medium model. Place them into
2510 default sections and hope for best. */
2515 /* We might get called with string constants, but get_named_section
2516 doesn't like them as they are not DECLs. Also, we need to set
2517 flags in that case. */
2519 return get_section (sname, flags, NULL);
2520 return get_named_section (decl, sname, reloc);
2523 return default_elf_select_section (decl, reloc, align);
2526 /* Build up a unique section name, expressed as a
2527 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2528 RELOC indicates whether the initial value of EXP requires
2529 link-time relocations. */
2531 static void ATTRIBUTE_UNUSED
2532 x86_64_elf_unique_section (tree decl, int reloc)
2534 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2535 && ix86_in_large_data_p (decl))
2537 const char *prefix = NULL;
2538 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2539 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2541 switch (categorize_decl_for_section (decl, reloc))
2544 case SECCAT_DATA_REL:
2545 case SECCAT_DATA_REL_LOCAL:
2546 case SECCAT_DATA_REL_RO:
2547 case SECCAT_DATA_REL_RO_LOCAL:
2548 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2551 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2554 case SECCAT_RODATA_MERGE_STR:
2555 case SECCAT_RODATA_MERGE_STR_INIT:
2556 case SECCAT_RODATA_MERGE_CONST:
2557 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2559 case SECCAT_SRODATA:
2566 /* We don't split these for medium model. Place them into
2567 default sections and hope for best. */
2575 plen = strlen (prefix);
2577 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2578 name = targetm.strip_name_encoding (name);
2579 nlen = strlen (name);
2581 string = (char *) alloca (nlen + plen + 1);
2582 memcpy (string, prefix, plen);
2583 memcpy (string + plen, name, nlen + 1);
2585 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2589 default_unique_section (decl, reloc);
2592 #ifdef COMMON_ASM_OP
2593 /* This says how to output assembler code to declare an
2594 uninitialized external linkage data object.
2596 For medium model x86-64 we need to use .largecomm opcode for
2599 x86_elf_aligned_common (FILE *file,
2600 const char *name, unsigned HOST_WIDE_INT size,
2603 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2604 && size > (unsigned int)ix86_section_threshold)
2605 fprintf (file, ".largecomm\t");
2607 fprintf (file, "%s", COMMON_ASM_OP);
2608 assemble_name (file, name);
2609 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2610 size, align / BITS_PER_UNIT);
2614 /* Utility function for targets to use in implementing
2615 ASM_OUTPUT_ALIGNED_BSS. */
2618 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2619 const char *name, unsigned HOST_WIDE_INT size,
2622 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2623 && size > (unsigned int)ix86_section_threshold)
2624 switch_to_section (get_named_section (decl, ".lbss", 0));
2626 switch_to_section (bss_section);
2627 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2628 #ifdef ASM_DECLARE_OBJECT_NAME
2629 last_assemble_variable_decl = decl;
2630 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2632 /* Standard thing is just output label for the object. */
2633 ASM_OUTPUT_LABEL (file, name);
2634 #endif /* ASM_DECLARE_OBJECT_NAME */
2635 ASM_OUTPUT_SKIP (file, size ? size : 1);
2639 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2641 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2642 make the problem with not enough registers even worse. */
2643 #ifdef INSN_SCHEDULING
2645 flag_schedule_insns = 0;
2649 /* The Darwin libraries never set errno, so we might as well
2650 avoid calling them when that's the only reason we would. */
2651 flag_errno_math = 0;
2653 /* The default values of these switches depend on the TARGET_64BIT
2654 that is not known at this moment. Mark these values with 2 and
2655 let user the to override these. In case there is no command line option
2656 specifying them, we will set the defaults in override_options. */
2658 flag_omit_frame_pointer = 2;
2659 flag_pcc_struct_return = 2;
2660 flag_asynchronous_unwind_tables = 2;
2661 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2662 SUBTARGET_OPTIMIZATION_OPTIONS;
2666 /* Decide whether we can make a sibling call to a function. DECL is the
2667 declaration of the function being targeted by the call and EXP is the
2668 CALL_EXPR representing the call. */
2671 ix86_function_ok_for_sibcall (tree decl, tree exp)
2676 /* If we are generating position-independent code, we cannot sibcall
2677 optimize any indirect call, or a direct call to a global function,
2678 as the PLT requires %ebx be live. */
2679 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
2686 func = TREE_TYPE (CALL_EXPR_FN (exp));
2687 if (POINTER_TYPE_P (func))
2688 func = TREE_TYPE (func);
2691 /* Check that the return value locations are the same. Like
2692 if we are returning floats on the 80387 register stack, we cannot
2693 make a sibcall from a function that doesn't return a float to a
2694 function that does or, conversely, from a function that does return
2695 a float to a function that doesn't; the necessary stack adjustment
2696 would not be executed. This is also the place we notice
2697 differences in the return value ABI. Note that it is ok for one
2698 of the functions to have void return type as long as the return
2699 value of the other is passed in a register. */
2700 a = ix86_function_value (TREE_TYPE (exp), func, false);
2701 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
2703 if (STACK_REG_P (a) || STACK_REG_P (b))
2705 if (!rtx_equal_p (a, b))
2708 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
2710 else if (!rtx_equal_p (a, b))
2713 /* If this call is indirect, we'll need to be able to use a call-clobbered
2714 register for the address of the target function. Make sure that all
2715 such registers are not used for passing parameters. */
2716 if (!decl && !TARGET_64BIT)
2720 /* We're looking at the CALL_EXPR, we need the type of the function. */
2721 type = CALL_EXPR_FN (exp); /* pointer expression */
2722 type = TREE_TYPE (type); /* pointer type */
2723 type = TREE_TYPE (type); /* function type */
2725 if (ix86_function_regparm (type, NULL) >= 3)
2727 /* ??? Need to count the actual number of registers to be used,
2728 not the possible number of registers. Fix later. */
2733 /* Dllimport'd functions are also called indirectly. */
2734 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
2735 && decl && DECL_DLLIMPORT_P (decl)
2736 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2739 /* If we forced aligned the stack, then sibcalling would unalign the
2740 stack, which may break the called function. */
2741 if (cfun->machine->force_align_arg_pointer)
2744 /* Otherwise okay. That also includes certain types of indirect calls. */
2748 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2749 calling convention attributes;
2750 arguments as in struct attribute_spec.handler. */
2753 ix86_handle_cconv_attribute (tree *node, tree name,
2755 int flags ATTRIBUTE_UNUSED,
2758 if (TREE_CODE (*node) != FUNCTION_TYPE
2759 && TREE_CODE (*node) != METHOD_TYPE
2760 && TREE_CODE (*node) != FIELD_DECL
2761 && TREE_CODE (*node) != TYPE_DECL)
2763 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2764 IDENTIFIER_POINTER (name));
2765 *no_add_attrs = true;
2769 /* Can combine regparm with all attributes but fastcall. */
2770 if (is_attribute_p ("regparm", name))
2774 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2776 error ("fastcall and regparm attributes are not compatible");
2779 cst = TREE_VALUE (args);
2780 if (TREE_CODE (cst) != INTEGER_CST)
2782 warning (OPT_Wattributes,
2783 "%qs attribute requires an integer constant argument",
2784 IDENTIFIER_POINTER (name));
2785 *no_add_attrs = true;
2787 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2789 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2790 IDENTIFIER_POINTER (name), REGPARM_MAX);
2791 *no_add_attrs = true;
2795 && lookup_attribute (ix86_force_align_arg_pointer_string,
2796 TYPE_ATTRIBUTES (*node))
2797 && compare_tree_int (cst, REGPARM_MAX-1))
2799 error ("%s functions limited to %d register parameters",
2800 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
2808 /* Do not warn when emulating the MS ABI. */
2809 if (!TARGET_64BIT_MS_ABI)
2810 warning (OPT_Wattributes, "%qs attribute ignored",
2811 IDENTIFIER_POINTER (name));
2812 *no_add_attrs = true;
2816 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2817 if (is_attribute_p ("fastcall", name))
2819 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2821 error ("fastcall and cdecl attributes are not compatible");
2823 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2825 error ("fastcall and stdcall attributes are not compatible");
2827 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2829 error ("fastcall and regparm attributes are not compatible");
2833 /* Can combine stdcall with fastcall (redundant), regparm and
2835 else if (is_attribute_p ("stdcall", name))
2837 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2839 error ("stdcall and cdecl attributes are not compatible");
2841 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2843 error ("stdcall and fastcall attributes are not compatible");
2847 /* Can combine cdecl with regparm and sseregparm. */
2848 else if (is_attribute_p ("cdecl", name))
2850 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2852 error ("stdcall and cdecl attributes are not compatible");
2854 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2856 error ("fastcall and cdecl attributes are not compatible");
2860 /* Can combine sseregparm with all attributes. */
2865 /* Return 0 if the attributes for two types are incompatible, 1 if they
2866 are compatible, and 2 if they are nearly compatible (which causes a
2867 warning to be generated). */
2870 ix86_comp_type_attributes (tree type1, tree type2)
2872 /* Check for mismatch of non-default calling convention. */
2873 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2875 if (TREE_CODE (type1) != FUNCTION_TYPE)
2878 /* Check for mismatched fastcall/regparm types. */
2879 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2880 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2881 || (ix86_function_regparm (type1, NULL)
2882 != ix86_function_regparm (type2, NULL)))
2885 /* Check for mismatched sseregparm types. */
2886 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2887 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2890 /* Check for mismatched return types (cdecl vs stdcall). */
2891 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2892 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2898 /* Return the regparm value for a function with the indicated TYPE and DECL.
2899 DECL may be NULL when calling function indirectly
2900 or considering a libcall. */
2903 ix86_function_regparm (tree type, tree decl)
2906 int regparm = ix86_regparm;
2911 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2913 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2915 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2918 /* Use register calling convention for local functions when possible. */
2919 if (decl && TREE_CODE (decl) == FUNCTION_DECL
2920 && flag_unit_at_a_time && !profile_flag)
2922 struct cgraph_local_info *i = cgraph_local_info (decl);
2925 int local_regparm, globals = 0, regno;
2928 /* Make sure no regparm register is taken by a
2929 global register variable. */
2930 for (local_regparm = 0; local_regparm < 3; local_regparm++)
2931 if (global_regs[local_regparm])
2934 /* We can't use regparm(3) for nested functions as these use
2935 static chain pointer in third argument. */
2936 if (local_regparm == 3
2937 && (decl_function_context (decl)
2938 || ix86_force_align_arg_pointer)
2939 && !DECL_NO_STATIC_CHAIN (decl))
2942 /* If the function realigns its stackpointer, the prologue will
2943 clobber %ecx. If we've already generated code for the callee,
2944 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
2945 scanning the attributes for the self-realigning property. */
2946 f = DECL_STRUCT_FUNCTION (decl);
2947 if (local_regparm == 3
2948 && (f ? !!f->machine->force_align_arg_pointer
2949 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
2950 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
2953 /* Each global register variable increases register preassure,
2954 so the more global reg vars there are, the smaller regparm
2955 optimization use, unless requested by the user explicitly. */
2956 for (regno = 0; regno < 6; regno++)
2957 if (global_regs[regno])
2960 = globals < local_regparm ? local_regparm - globals : 0;
2962 if (local_regparm > regparm)
2963 regparm = local_regparm;
2970 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
2971 DFmode (2) arguments in SSE registers for a function with the
2972 indicated TYPE and DECL. DECL may be NULL when calling function
2973 indirectly or considering a libcall. Otherwise return 0. */
2976 ix86_function_sseregparm (tree type, tree decl)
2978 gcc_assert (!TARGET_64BIT);
2980 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2981 by the sseregparm attribute. */
2982 if (TARGET_SSEREGPARM
2983 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2988 error ("Calling %qD with attribute sseregparm without "
2989 "SSE/SSE2 enabled", decl);
2991 error ("Calling %qT with attribute sseregparm without "
2992 "SSE/SSE2 enabled", type);
2999 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3000 (and DFmode for SSE2) arguments in SSE registers. */
3001 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3003 struct cgraph_local_info *i = cgraph_local_info (decl);
3005 return TARGET_SSE2 ? 2 : 1;
3011 /* Return true if EAX is live at the start of the function. Used by
3012 ix86_expand_prologue to determine if we need special help before
3013 calling allocate_stack_worker. */
3016 ix86_eax_live_at_start_p (void)
3018 /* Cheat. Don't bother working forward from ix86_function_regparm
3019 to the function type to whether an actual argument is located in
3020 eax. Instead just look at cfg info, which is still close enough
3021 to correct at this point. This gives false positives for broken
3022 functions that might use uninitialized data that happens to be
3023 allocated in eax, but who cares? */
3024 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3027 /* Return true if TYPE has a variable argument list. */
3030 type_has_variadic_args_p (tree type)
3032 tree n, t = TYPE_ARG_TYPES (type);
3037 while ((n = TREE_CHAIN (t)) != NULL)
3040 return TREE_VALUE (t) != void_type_node;
3043 /* Value is the number of bytes of arguments automatically
3044 popped when returning from a subroutine call.
3045 FUNDECL is the declaration node of the function (as a tree),
3046 FUNTYPE is the data type of the function (as a tree),
3047 or for a library call it is an identifier node for the subroutine name.
3048 SIZE is the number of bytes of arguments passed on the stack.
3050 On the 80386, the RTD insn may be used to pop them if the number
3051 of args is fixed, but if the number is variable then the caller
3052 must pop them all. RTD can't be used for library calls now
3053 because the library is compiled with the Unix compiler.
3054 Use of RTD is a selectable option, since it is incompatible with
3055 standard Unix calling sequences. If the option is not selected,
3056 the caller must always pop the args.
3058 The attribute stdcall is equivalent to RTD on a per module basis. */
3061 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3065 /* None of the 64-bit ABIs pop arguments. */
3069 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3071 /* Cdecl functions override -mrtd, and never pop the stack. */
3072 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3074 /* Stdcall and fastcall functions will pop the stack if not
3076 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3077 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3080 if (rtd && ! type_has_variadic_args_p (funtype))
3084 /* Lose any fake structure return argument if it is passed on the stack. */
3085 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3086 && !KEEP_AGGREGATE_RETURN_POINTER)
3088 int nregs = ix86_function_regparm (funtype, fundecl);
3090 return GET_MODE_SIZE (Pmode);
3096 /* Argument support functions. */
3098 /* Return true when register may be used to pass function parameters. */
3100 ix86_function_arg_regno_p (int regno)
3103 const int *parm_regs;
3108 return (regno < REGPARM_MAX
3109 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3111 return (regno < REGPARM_MAX
3112 || (TARGET_MMX && MMX_REGNO_P (regno)
3113 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3114 || (TARGET_SSE && SSE_REGNO_P (regno)
3115 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3120 if (SSE_REGNO_P (regno) && TARGET_SSE)
3125 if (TARGET_SSE && SSE_REGNO_P (regno)
3126 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3130 /* RAX is used as hidden argument to va_arg functions. */
3131 if (!TARGET_64BIT_MS_ABI && regno == 0)
3134 if (TARGET_64BIT_MS_ABI)
3135 parm_regs = x86_64_ms_abi_int_parameter_registers;
3137 parm_regs = x86_64_int_parameter_registers;
3138 for (i = 0; i < REGPARM_MAX; i++)
3139 if (regno == parm_regs[i])
3144 /* Return if we do not know how to pass TYPE solely in registers. */
3147 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
3149 if (must_pass_in_stack_var_size_or_pad (mode, type))
3152 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3153 The layout_type routine is crafty and tries to trick us into passing
3154 currently unsupported vector types on the stack by using TImode. */
3155 return (!TARGET_64BIT && mode == TImode
3156 && type && TREE_CODE (type) != VECTOR_TYPE);
3159 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3160 for a call to a function whose data type is FNTYPE.
3161 For a library call, FNTYPE is 0. */
3164 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3165 tree fntype, /* tree ptr for function decl */
3166 rtx libname, /* SYMBOL_REF of library name or 0 */
3169 memset (cum, 0, sizeof (*cum));
3171 /* Set up the number of registers to use for passing arguments. */
3172 cum->nregs = ix86_regparm;
3174 cum->sse_nregs = SSE_REGPARM_MAX;
3176 cum->mmx_nregs = MMX_REGPARM_MAX;
3177 cum->warn_sse = true;
3178 cum->warn_mmx = true;
3179 cum->maybe_vaarg = (fntype
3180 ? (!TYPE_ARG_TYPES (fntype)
3181 || type_has_variadic_args_p (fntype))
3186 /* If there are variable arguments, then we won't pass anything
3187 in registers in 32-bit mode. */
3188 if (cum->maybe_vaarg)
3198 /* Use ecx and edx registers if function has fastcall attribute,
3199 else look for regparm information. */
3202 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3208 cum->nregs = ix86_function_regparm (fntype, fndecl);
3211 /* Set up the number of SSE registers used for passing SFmode
3212 and DFmode arguments. Warn for mismatching ABI. */
3213 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
3217 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3218 But in the case of vector types, it is some vector mode.
3220 When we have only some of our vector isa extensions enabled, then there
3221 are some modes for which vector_mode_supported_p is false. For these
3222 modes, the generic vector support in gcc will choose some non-vector mode
3223 in order to implement the type. By computing the natural mode, we'll
3224 select the proper ABI location for the operand and not depend on whatever
3225 the middle-end decides to do with these vector types. */
3227 static enum machine_mode
3228 type_natural_mode (tree type)
3230 enum machine_mode mode = TYPE_MODE (type);
3232 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3234 HOST_WIDE_INT size = int_size_in_bytes (type);
3235 if ((size == 8 || size == 16)
3236 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3237 && TYPE_VECTOR_SUBPARTS (type) > 1)
3239 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3241 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3242 mode = MIN_MODE_VECTOR_FLOAT;
3244 mode = MIN_MODE_VECTOR_INT;
3246 /* Get the mode which has this inner mode and number of units. */
3247 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3248 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3249 && GET_MODE_INNER (mode) == innermode)
3259 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3260 this may not agree with the mode that the type system has chosen for the
3261 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3262 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3265 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3270 if (orig_mode != BLKmode)
3271 tmp = gen_rtx_REG (orig_mode, regno);
3274 tmp = gen_rtx_REG (mode, regno);
3275 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3276 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3282 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3283 of this code is to classify each 8bytes of incoming argument by the register
3284 class and assign registers accordingly. */
3286 /* Return the union class of CLASS1 and CLASS2.
3287 See the x86-64 PS ABI for details. */
3289 static enum x86_64_reg_class
3290 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3292 /* Rule #1: If both classes are equal, this is the resulting class. */
3293 if (class1 == class2)
3296 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3298 if (class1 == X86_64_NO_CLASS)
3300 if (class2 == X86_64_NO_CLASS)
3303 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3304 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3305 return X86_64_MEMORY_CLASS;
3307 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3308 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3309 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3310 return X86_64_INTEGERSI_CLASS;
3311 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3312 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3313 return X86_64_INTEGER_CLASS;
3315 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3317 if (class1 == X86_64_X87_CLASS
3318 || class1 == X86_64_X87UP_CLASS
3319 || class1 == X86_64_COMPLEX_X87_CLASS
3320 || class2 == X86_64_X87_CLASS
3321 || class2 == X86_64_X87UP_CLASS
3322 || class2 == X86_64_COMPLEX_X87_CLASS)
3323 return X86_64_MEMORY_CLASS;
3325 /* Rule #6: Otherwise class SSE is used. */
3326 return X86_64_SSE_CLASS;
3329 /* Classify the argument of type TYPE and mode MODE.
3330 CLASSES will be filled by the register class used to pass each word
3331 of the operand. The number of words is returned. In case the parameter
3332 should be passed in memory, 0 is returned. As a special case for zero
3333 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3335 BIT_OFFSET is used internally for handling records and specifies offset
3336 of the offset in bits modulo 256 to avoid overflow cases.
3338 See the x86-64 PS ABI for details.
3342 classify_argument (enum machine_mode mode, tree type,
3343 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3345 HOST_WIDE_INT bytes =
3346 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3347 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3349 /* Variable sized entities are always passed/returned in memory. */
3353 if (mode != VOIDmode
3354 && targetm.calls.must_pass_in_stack (mode, type))
3357 if (type && AGGREGATE_TYPE_P (type))
3361 enum x86_64_reg_class subclasses[MAX_CLASSES];
3363 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3367 for (i = 0; i < words; i++)
3368 classes[i] = X86_64_NO_CLASS;
3370 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3371 signalize memory class, so handle it as special case. */
3374 classes[0] = X86_64_NO_CLASS;
3378 /* Classify each field of record and merge classes. */
3379 switch (TREE_CODE (type))
3382 /* And now merge the fields of structure. */
3383 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3385 if (TREE_CODE (field) == FIELD_DECL)
3389 if (TREE_TYPE (field) == error_mark_node)
3392 /* Bitfields are always classified as integer. Handle them
3393 early, since later code would consider them to be
3394 misaligned integers. */
3395 if (DECL_BIT_FIELD (field))
3397 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3398 i < ((int_bit_position (field) + (bit_offset % 64))
3399 + tree_low_cst (DECL_SIZE (field), 0)
3402 merge_classes (X86_64_INTEGER_CLASS,
3407 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3408 TREE_TYPE (field), subclasses,
3409 (int_bit_position (field)
3410 + bit_offset) % 256);
3413 for (i = 0; i < num; i++)
3416 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3418 merge_classes (subclasses[i], classes[i + pos]);
3426 /* Arrays are handled as small records. */
3429 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3430 TREE_TYPE (type), subclasses, bit_offset);
3434 /* The partial classes are now full classes. */
3435 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3436 subclasses[0] = X86_64_SSE_CLASS;
3437 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3438 subclasses[0] = X86_64_INTEGER_CLASS;
3440 for (i = 0; i < words; i++)
3441 classes[i] = subclasses[i % num];
3446 case QUAL_UNION_TYPE:
3447 /* Unions are similar to RECORD_TYPE but offset is always 0.
3449 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3451 if (TREE_CODE (field) == FIELD_DECL)
3455 if (TREE_TYPE (field) == error_mark_node)
3458 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3459 TREE_TYPE (field), subclasses,
3463 for (i = 0; i < num; i++)
3464 classes[i] = merge_classes (subclasses[i], classes[i]);
3473 /* Final merger cleanup. */
3474 for (i = 0; i < words; i++)
3476 /* If one class is MEMORY, everything should be passed in
3478 if (classes[i] == X86_64_MEMORY_CLASS)
3481 /* The X86_64_SSEUP_CLASS should be always preceded by
3482 X86_64_SSE_CLASS. */
3483 if (classes[i] == X86_64_SSEUP_CLASS
3484 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3485 classes[i] = X86_64_SSE_CLASS;
3487 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3488 if (classes[i] == X86_64_X87UP_CLASS
3489 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3490 classes[i] = X86_64_SSE_CLASS;
3495 /* Compute alignment needed. We align all types to natural boundaries with
3496 exception of XFmode that is aligned to 64bits. */
3497 if (mode != VOIDmode && mode != BLKmode)
3499 int mode_alignment = GET_MODE_BITSIZE (mode);
3502 mode_alignment = 128;
3503 else if (mode == XCmode)
3504 mode_alignment = 256;
3505 if (COMPLEX_MODE_P (mode))
3506 mode_alignment /= 2;
3507 /* Misaligned fields are always returned in memory. */
3508 if (bit_offset % mode_alignment)
3512 /* for V1xx modes, just use the base mode */
3513 if (VECTOR_MODE_P (mode)
3514 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3515 mode = GET_MODE_INNER (mode);
3517 /* Classification of atomic types. */
3522 classes[0] = X86_64_SSE_CLASS;
3525 classes[0] = X86_64_SSE_CLASS;
3526 classes[1] = X86_64_SSEUP_CLASS;
3535 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3536 classes[0] = X86_64_INTEGERSI_CLASS;
3538 classes[0] = X86_64_INTEGER_CLASS;
3542 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3547 if (!(bit_offset % 64))
3548 classes[0] = X86_64_SSESF_CLASS;
3550 classes[0] = X86_64_SSE_CLASS;
3553 classes[0] = X86_64_SSEDF_CLASS;
3556 classes[0] = X86_64_X87_CLASS;
3557 classes[1] = X86_64_X87UP_CLASS;
3560 classes[0] = X86_64_SSE_CLASS;
3561 classes[1] = X86_64_SSEUP_CLASS;
3564 classes[0] = X86_64_SSE_CLASS;
3567 classes[0] = X86_64_SSEDF_CLASS;
3568 classes[1] = X86_64_SSEDF_CLASS;
3571 classes[0] = X86_64_COMPLEX_X87_CLASS;
3574 /* This modes is larger than 16 bytes. */
3582 classes[0] = X86_64_SSE_CLASS;
3583 classes[1] = X86_64_SSEUP_CLASS;
3589 classes[0] = X86_64_SSE_CLASS;
3595 gcc_assert (VECTOR_MODE_P (mode));
3600 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3602 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3603 classes[0] = X86_64_INTEGERSI_CLASS;
3605 classes[0] = X86_64_INTEGER_CLASS;
3606 classes[1] = X86_64_INTEGER_CLASS;
3607 return 1 + (bytes > 8);
3611 /* Examine the argument and return set number of register required in each
3612 class. Return 0 iff parameter should be passed in memory. */
3614 examine_argument (enum machine_mode mode, tree type, int in_return,
3615 int *int_nregs, int *sse_nregs)
3617 enum x86_64_reg_class regclass[MAX_CLASSES];
3618 int n = classify_argument (mode, type, regclass, 0);
3624 for (n--; n >= 0; n--)
3625 switch (regclass[n])
3627 case X86_64_INTEGER_CLASS:
3628 case X86_64_INTEGERSI_CLASS:
3631 case X86_64_SSE_CLASS:
3632 case X86_64_SSESF_CLASS:
3633 case X86_64_SSEDF_CLASS:
3636 case X86_64_NO_CLASS:
3637 case X86_64_SSEUP_CLASS:
3639 case X86_64_X87_CLASS:
3640 case X86_64_X87UP_CLASS:
3644 case X86_64_COMPLEX_X87_CLASS:
3645 return in_return ? 2 : 0;
3646 case X86_64_MEMORY_CLASS:
3652 /* Construct container for the argument used by GCC interface. See
3653 FUNCTION_ARG for the detailed description. */
3656 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3657 tree type, int in_return, int nintregs, int nsseregs,
3658 const int *intreg, int sse_regno)
3660 /* The following variables hold the static issued_error state. */
3661 static bool issued_sse_arg_error;
3662 static bool issued_sse_ret_error;
3663 static bool issued_x87_ret_error;
3665 enum machine_mode tmpmode;
3667 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3668 enum x86_64_reg_class regclass[MAX_CLASSES];
3672 int needed_sseregs, needed_intregs;
3673 rtx exp[MAX_CLASSES];
3676 n = classify_argument (mode, type, regclass, 0);
3679 if (!examine_argument (mode, type, in_return, &needed_intregs,
3682 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
3685 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3686 some less clueful developer tries to use floating-point anyway. */
3687 if (needed_sseregs && !TARGET_SSE)
3691 if (!issued_sse_ret_error)
3693 error ("SSE register return with SSE disabled");
3694 issued_sse_ret_error = true;
3697 else if (!issued_sse_arg_error)
3699 error ("SSE register argument with SSE disabled");
3700 issued_sse_arg_error = true;
3705 /* Likewise, error if the ABI requires us to return values in the
3706 x87 registers and the user specified -mno-80387. */
3707 if (!TARGET_80387 && in_return)
3708 for (i = 0; i < n; i++)
3709 if (regclass[i] == X86_64_X87_CLASS
3710 || regclass[i] == X86_64_X87UP_CLASS
3711 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
3713 if (!issued_x87_ret_error)
3715 error ("x87 register return with x87 disabled");
3716 issued_x87_ret_error = true;
3721 /* First construct simple cases. Avoid SCmode, since we want to use
3722 single register to pass this type. */
3723 if (n == 1 && mode != SCmode)
3724 switch (regclass[0])
3726 case X86_64_INTEGER_CLASS:
3727 case X86_64_INTEGERSI_CLASS:
3728 return gen_rtx_REG (mode, intreg[0]);
3729 case X86_64_SSE_CLASS:
3730 case X86_64_SSESF_CLASS:
3731 case X86_64_SSEDF_CLASS:
3732 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
3733 case X86_64_X87_CLASS:
3734 case X86_64_COMPLEX_X87_CLASS:
3735 return gen_rtx_REG (mode, FIRST_STACK_REG);
3736 case X86_64_NO_CLASS:
3737 /* Zero sized array, struct or class. */
3742 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
3743 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
3744 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
3747 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
3748 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
3749 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
3750 && regclass[1] == X86_64_INTEGER_CLASS
3751 && (mode == CDImode || mode == TImode || mode == TFmode)
3752 && intreg[0] + 1 == intreg[1])
3753 return gen_rtx_REG (mode, intreg[0]);
3755 /* Otherwise figure out the entries of the PARALLEL. */
3756 for (i = 0; i < n; i++)
3758 switch (regclass[i])
3760 case X86_64_NO_CLASS:
3762 case X86_64_INTEGER_CLASS:
3763 case X86_64_INTEGERSI_CLASS:
3764 /* Merge TImodes on aligned occasions here too. */
3765 if (i * 8 + 8 > bytes)
3766 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
3767 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
3771 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3772 if (tmpmode == BLKmode)
3774 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3775 gen_rtx_REG (tmpmode, *intreg),
3779 case X86_64_SSESF_CLASS:
3780 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3781 gen_rtx_REG (SFmode,
3782 SSE_REGNO (sse_regno)),
3786 case X86_64_SSEDF_CLASS:
3787 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3788 gen_rtx_REG (DFmode,
3789 SSE_REGNO (sse_regno)),
3793 case X86_64_SSE_CLASS:
3794 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
3798 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3799 gen_rtx_REG (tmpmode,
3800 SSE_REGNO (sse_regno)),
3802 if (tmpmode == TImode)
3811 /* Empty aligned struct, union or class. */
3815 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3816 for (i = 0; i < nexps; i++)
3817 XVECEXP (ret, 0, i) = exp [i];
3821 /* Update the data in CUM to advance over an argument of mode MODE
3822 and data type TYPE. (TYPE is null for libcalls where that information
3823 may not be available.) */
3826 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3827 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
3843 cum->words += words;
3844 cum->nregs -= words;
3845 cum->regno += words;
3847 if (cum->nregs <= 0)
3855 if (cum->float_in_sse < 2)
3858 if (cum->float_in_sse < 1)
3869 if (!type || !AGGREGATE_TYPE_P (type))
3871 cum->sse_words += words;
3872 cum->sse_nregs -= 1;
3873 cum->sse_regno += 1;
3874 if (cum->sse_nregs <= 0)
3886 if (!type || !AGGREGATE_TYPE_P (type))
3888 cum->mmx_words += words;
3889 cum->mmx_nregs -= 1;
3890 cum->mmx_regno += 1;
3891 if (cum->mmx_nregs <= 0)
3902 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3903 tree type, HOST_WIDE_INT words)
3905 int int_nregs, sse_nregs;
3907 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3908 cum->words += words;
3909 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3911 cum->nregs -= int_nregs;
3912 cum->sse_nregs -= sse_nregs;
3913 cum->regno += int_nregs;
3914 cum->sse_regno += sse_nregs;
3917 cum->words += words;
3921 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
3922 HOST_WIDE_INT words)
3924 /* Otherwise, this should be passed indirect. */
3925 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
3927 cum->words += words;
3936 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3937 tree type, int named ATTRIBUTE_UNUSED)
3939 HOST_WIDE_INT bytes, words;
3941 if (mode == BLKmode)
3942 bytes = int_size_in_bytes (type);
3944 bytes = GET_MODE_SIZE (mode);
3945 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3948 mode = type_natural_mode (type);
3950 if (TARGET_64BIT_MS_ABI)
3951 function_arg_advance_ms_64 (cum, bytes, words);
3952 else if (TARGET_64BIT)
3953 function_arg_advance_64 (cum, mode, type, words);
3955 function_arg_advance_32 (cum, mode, type, bytes, words);
3958 /* Define where to put the arguments to a function.
3959 Value is zero to push the argument on the stack,
3960 or a hard register in which to store the argument.
3962 MODE is the argument's machine mode.
3963 TYPE is the data type of the argument (as a tree).
3964 This is null for libcalls where that information may
3966 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3967 the preceding args and about the function being called.
3968 NAMED is nonzero if this argument is a named parameter
3969 (otherwise it is an extra parameter matching an ellipsis). */
3972 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3973 enum machine_mode orig_mode, tree type,
3974 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
3976 static bool warnedsse, warnedmmx;
3978 /* Avoid the AL settings for the Unix64 ABI. */
3979 if (mode == VOIDmode)
3995 if (words <= cum->nregs)
3997 int regno = cum->regno;
3999 /* Fastcall allocates the first two DWORD (SImode) or
4000 smaller arguments to ECX and EDX. */
4003 if (mode == BLKmode || mode == DImode)
4006 /* ECX not EAX is the first allocated register. */
4010 return gen_rtx_REG (mode, regno);
4015 if (cum->float_in_sse < 2)
4018 if (cum->float_in_sse < 1)
4028 if (!type || !AGGREGATE_TYPE_P (type))
4030 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4033 warning (0, "SSE vector argument without SSE enabled "
4037 return gen_reg_or_parallel (mode, orig_mode,
4038 cum->sse_regno + FIRST_SSE_REG);
4046 if (!type || !AGGREGATE_TYPE_P (type))
4048 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4051 warning (0, "MMX vector argument without MMX enabled "
4055 return gen_reg_or_parallel (mode, orig_mode,
4056 cum->mmx_regno + FIRST_MMX_REG);
4065 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4066 enum machine_mode orig_mode, tree type)
4068 /* Handle a hidden AL argument containing number of registers
4069 for varargs x86-64 functions. */
4070 if (mode == VOIDmode)
4071 return GEN_INT (cum->maybe_vaarg
4072 ? (cum->sse_nregs < 0
4077 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4079 &x86_64_int_parameter_registers [cum->regno],
4084 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4085 enum machine_mode orig_mode, int named)
4089 /* Avoid the AL settings for the Unix64 ABI. */
4090 if (mode == VOIDmode)
4093 /* If we've run out of registers, it goes on the stack. */
4094 if (cum->nregs == 0)
4097 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4099 /* Only floating point modes are passed in anything but integer regs. */
4100 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4103 regno = cum->regno + FIRST_SSE_REG;
4108 /* Unnamed floating parameters are passed in both the
4109 SSE and integer registers. */
4110 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4111 t2 = gen_rtx_REG (mode, regno);
4112 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4113 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4114 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4118 return gen_reg_or_parallel (mode, orig_mode, regno);
4122 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4123 tree type, int named)
4125 enum machine_mode mode = omode;
4126 HOST_WIDE_INT bytes, words;
4128 if (mode == BLKmode)
4129 bytes = int_size_in_bytes (type);
4131 bytes = GET_MODE_SIZE (mode);
4132 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4134 /* To simplify the code below, represent vector types with a vector mode
4135 even if MMX/SSE are not active. */
4136 if (type && TREE_CODE (type) == VECTOR_TYPE)
4137 mode = type_natural_mode (type);
4139 if (TARGET_64BIT_MS_ABI)
4140 return function_arg_ms_64 (cum, mode, omode, named);
4141 else if (TARGET_64BIT)
4142 return function_arg_64 (cum, mode, omode, type);
4144 return function_arg_32 (cum, mode, omode, type, bytes, words);
4147 /* A C expression that indicates when an argument must be passed by
4148 reference. If nonzero for an argument, a copy of that argument is
4149 made in memory and a pointer to the argument is passed instead of
4150 the argument itself. The pointer is passed in whatever way is
4151 appropriate for passing a pointer to that type. */
4154 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4155 enum machine_mode mode ATTRIBUTE_UNUSED,
4156 tree type, bool named ATTRIBUTE_UNUSED)
4158 if (TARGET_64BIT_MS_ABI)
4162 /* Arrays are passed by reference. */
4163 if (TREE_CODE (type) == ARRAY_TYPE)
4166 if (AGGREGATE_TYPE_P (type))
4168 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4169 are passed by reference. */
4170 int el2 = exact_log2 (int_size_in_bytes (type));
4171 return !(el2 >= 0 && el2 <= 3);
4175 /* __m128 is passed by reference. */
4176 /* ??? How to handle complex? For now treat them as structs,
4177 and pass them by reference if they're too large. */
4178 if (GET_MODE_SIZE (mode) > 8)
4181 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4187 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4188 ABI. Only called if TARGET_SSE. */
4190 contains_128bit_aligned_vector_p (tree type)
4192 enum machine_mode mode = TYPE_MODE (type);
4193 if (SSE_REG_MODE_P (mode)
4194 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4196 if (TYPE_ALIGN (type) < 128)
4199 if (AGGREGATE_TYPE_P (type))
4201 /* Walk the aggregates recursively. */
4202 switch (TREE_CODE (type))
4206 case QUAL_UNION_TYPE:
4210 /* Walk all the structure fields. */
4211 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4213 if (TREE_CODE (field) == FIELD_DECL
4214 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4221 /* Just for use if some languages passes arrays by value. */
4222 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4233 /* Gives the alignment boundary, in bits, of an argument with the
4234 specified mode and type. */
4237 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4241 align = TYPE_ALIGN (type);
4243 align = GET_MODE_ALIGNMENT (mode);
4244 if (align < PARM_BOUNDARY)
4245 align = PARM_BOUNDARY;
4248 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4249 make an exception for SSE modes since these require 128bit
4252 The handling here differs from field_alignment. ICC aligns MMX
4253 arguments to 4 byte boundaries, while structure fields are aligned
4254 to 8 byte boundaries. */
4256 align = PARM_BOUNDARY;
4259 if (!SSE_REG_MODE_P (mode))
4260 align = PARM_BOUNDARY;
4264 if (!contains_128bit_aligned_vector_p (type))
4265 align = PARM_BOUNDARY;
4273 /* Return true if N is a possible register number of function value. */
4276 ix86_function_value_regno_p (int regno)
4283 case FIRST_FLOAT_REG:
4284 if (TARGET_64BIT_MS_ABI)
4286 return TARGET_FLOAT_RETURNS_IN_80387;
4292 if (TARGET_MACHO || TARGET_64BIT)
4300 /* Define how to find the value returned by a function.
4301 VALTYPE is the data type of the value (as a tree).
4302 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4303 otherwise, FUNC is 0. */
4306 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4307 tree fntype, tree fn)
4311 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4312 we normally prevent this case when mmx is not available. However
4313 some ABIs may require the result to be returned like DImode. */
4314 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4315 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4317 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4318 we prevent this case when sse is not available. However some ABIs
4319 may require the result to be returned like integer TImode. */
4320 else if (mode == TImode
4321 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4322 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4324 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4325 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4326 regno = FIRST_FLOAT_REG;
4328 /* Most things go in %eax. */
4331 /* Override FP return register with %xmm0 for local functions when
4332 SSE math is enabled or for functions with sseregparm attribute. */
4333 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4335 int sse_level = ix86_function_sseregparm (fntype, fn);
4336 if ((sse_level >= 1 && mode == SFmode)
4337 || (sse_level == 2 && mode == DFmode))
4338 regno = FIRST_SSE_REG;
4341 return gen_rtx_REG (orig_mode, regno);
4345 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4350 /* Handle libcalls, which don't provide a type node. */
4351 if (valtype == NULL)
4363 return gen_rtx_REG (mode, FIRST_SSE_REG);
4366 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4370 return gen_rtx_REG (mode, 0);
4374 ret = construct_container (mode, orig_mode, valtype, 1,
4375 REGPARM_MAX, SSE_REGPARM_MAX,
4376 x86_64_int_return_registers, 0);
4378 /* For zero sized structures, construct_container returns NULL, but we
4379 need to keep rest of compiler happy by returning meaningful value. */
4381 ret = gen_rtx_REG (orig_mode, 0);
4387 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4389 unsigned int regno = 0;
4393 if (mode == SFmode || mode == DFmode)
4394 regno = FIRST_SSE_REG;
4395 else if (VECTOR_MODE_P (mode) || GET_MODE_SIZE (mode) == 16)
4396 regno = FIRST_SSE_REG;
4399 return gen_rtx_REG (orig_mode, regno);
4403 ix86_function_value_1 (tree valtype, tree fntype_or_decl,
4404 enum machine_mode orig_mode, enum machine_mode mode)
4409 if (fntype_or_decl && DECL_P (fntype_or_decl))
4410 fn = fntype_or_decl;
4411 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4413 if (TARGET_64BIT_MS_ABI)
4414 return function_value_ms_64 (orig_mode, mode);
4415 else if (TARGET_64BIT)
4416 return function_value_64 (orig_mode, mode, valtype);
4418 return function_value_32 (orig_mode, mode, fntype, fn);
4422 ix86_function_value (tree valtype, tree fntype_or_decl,
4423 bool outgoing ATTRIBUTE_UNUSED)
4425 enum machine_mode mode, orig_mode;
4427 orig_mode = TYPE_MODE (valtype);
4428 mode = type_natural_mode (valtype);
4429 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4433 ix86_libcall_value (enum machine_mode mode)
4435 return ix86_function_value_1 (NULL, NULL, mode, mode);
4438 /* Return true iff type is returned in memory. */
4441 return_in_memory_32 (tree type, enum machine_mode mode)
4445 if (mode == BLKmode)
4448 size = int_size_in_bytes (type);
4450 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4453 if (VECTOR_MODE_P (mode) || mode == TImode)
4455 /* User-created vectors small enough to fit in EAX. */
4459 /* MMX/3dNow values are returned in MM0,
4460 except when it doesn't exits. */
4462 return (TARGET_MMX ? 0 : 1);
4464 /* SSE values are returned in XMM0, except when it doesn't exist. */
4466 return (TARGET_SSE ? 0 : 1);
4481 return_in_memory_64 (tree type, enum machine_mode mode)
4483 int needed_intregs, needed_sseregs;
4484 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4488 return_in_memory_ms_64 (tree type, enum machine_mode mode)
4490 HOST_WIDE_INT size = int_size_in_bytes (type);
4492 /* __m128 and friends are returned in xmm0. */
4493 if (size == 16 && VECTOR_MODE_P (mode))
4496 /* Otherwise, the size must be exactly in [1248]. */
4497 return (size != 1 && size != 2 && size != 4 && size != 8);
4501 ix86_return_in_memory (tree type)
4503 enum machine_mode mode = type_natural_mode (type);
4505 if (TARGET_64BIT_MS_ABI)
4506 return return_in_memory_ms_64 (type, mode);
4507 else if (TARGET_64BIT)
4508 return return_in_memory_64 (type, mode);
4510 return return_in_memory_32 (type, mode);
4513 /* Return false iff TYPE is returned in memory. This version is used
4514 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4515 but differs notably in that when MMX is available, 8-byte vectors
4516 are returned in memory, rather than in MMX registers. */
4519 ix86_sol10_return_in_memory (tree type)
4522 enum machine_mode mode = type_natural_mode (type);
4525 return return_in_memory_64 (type, mode);
4527 if (mode == BLKmode)
4530 size = int_size_in_bytes (type);
4532 if (VECTOR_MODE_P (mode))
4534 /* Return in memory only if MMX registers *are* available. This
4535 seems backwards, but it is consistent with the existing
4542 else if (mode == TImode)
4544 else if (mode == XFmode)
4550 /* When returning SSE vector types, we have a choice of either
4551 (1) being abi incompatible with a -march switch, or
4552 (2) generating an error.
4553 Given no good solution, I think the safest thing is one warning.
4554 The user won't be able to use -Werror, but....
4556 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4557 called in response to actually generating a caller or callee that
4558 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4559 via aggregate_value_p for general type probing from tree-ssa. */
4562 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4564 static bool warnedsse, warnedmmx;
4566 if (!TARGET_64BIT && type)
4568 /* Look at the return type of the function, not the function type. */
4569 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4571 if (!TARGET_SSE && !warnedsse)
4574 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4577 warning (0, "SSE vector return without SSE enabled "
4582 if (!TARGET_MMX && !warnedmmx)
4584 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4587 warning (0, "MMX vector return without MMX enabled "
4597 /* Create the va_list data type. */
4600 ix86_build_builtin_va_list (void)
4602 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4604 /* For i386 we use plain pointer to argument area. */
4605 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4606 return build_pointer_type (char_type_node);
4608 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4609 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4611 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4612 unsigned_type_node);
4613 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4614 unsigned_type_node);
4615 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4617 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4620 va_list_gpr_counter_field = f_gpr;
4621 va_list_fpr_counter_field = f_fpr;
4623 DECL_FIELD_CONTEXT (f_gpr) = record;
4624 DECL_FIELD_CONTEXT (f_fpr) = record;
4625 DECL_FIELD_CONTEXT (f_ovf) = record;
4626 DECL_FIELD_CONTEXT (f_sav) = record;
4628 TREE_CHAIN (record) = type_decl;
4629 TYPE_NAME (record) = type_decl;
4630 TYPE_FIELDS (record) = f_gpr;
4631 TREE_CHAIN (f_gpr) = f_fpr;
4632 TREE_CHAIN (f_fpr) = f_ovf;
4633 TREE_CHAIN (f_ovf) = f_sav;
4635 layout_type (record);
4637 /* The correct type is an array type of one element. */
4638 return build_array_type (record, build_index_type (size_zero_node));
4641 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4644 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
4654 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4657 /* Indicate to allocate space on the stack for varargs save area. */
4658 ix86_save_varrargs_registers = 1;
4659 cfun->stack_alignment_needed = 128;
4661 save_area = frame_pointer_rtx;
4662 set = get_varargs_alias_set ();
4664 for (i = cum->regno;
4666 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
4669 mem = gen_rtx_MEM (Pmode,
4670 plus_constant (save_area, i * UNITS_PER_WORD));
4671 MEM_NOTRAP_P (mem) = 1;
4672 set_mem_alias_set (mem, set);
4673 emit_move_insn (mem, gen_rtx_REG (Pmode,
4674 x86_64_int_parameter_registers[i]));
4677 if (cum->sse_nregs && cfun->va_list_fpr_size)
4679 /* Now emit code to save SSE registers. The AX parameter contains number
4680 of SSE parameter registers used to call this function. We use
4681 sse_prologue_save insn template that produces computed jump across
4682 SSE saves. We need some preparation work to get this working. */
4684 label = gen_label_rtx ();
4685 label_ref = gen_rtx_LABEL_REF (Pmode, label);
4687 /* Compute address to jump to :
4688 label - 5*eax + nnamed_sse_arguments*5 */
4689 tmp_reg = gen_reg_rtx (Pmode);
4690 nsse_reg = gen_reg_rtx (Pmode);
4691 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
4692 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4693 gen_rtx_MULT (Pmode, nsse_reg,
4698 gen_rtx_CONST (DImode,
4699 gen_rtx_PLUS (DImode,
4701 GEN_INT (cum->sse_regno * 4))));
4703 emit_move_insn (nsse_reg, label_ref);
4704 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
4706 /* Compute address of memory block we save into. We always use pointer
4707 pointing 127 bytes after first byte to store - this is needed to keep
4708 instruction size limited by 4 bytes. */
4709 tmp_reg = gen_reg_rtx (Pmode);
4710 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4711 plus_constant (save_area,
4712 8 * REGPARM_MAX + 127)));
4713 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
4714 MEM_NOTRAP_P (mem) = 1;
4715 set_mem_alias_set (mem, set);
4716 set_mem_align (mem, BITS_PER_WORD);
4718 /* And finally do the dirty job! */
4719 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
4720 GEN_INT (cum->sse_regno), label));
4725 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
4727 int set = get_varargs_alias_set ();
4730 for (i = cum->regno; i < REGPARM_MAX; i++)
4734 mem = gen_rtx_MEM (Pmode,
4735 plus_constant (virtual_incoming_args_rtx,
4736 i * UNITS_PER_WORD));
4737 MEM_NOTRAP_P (mem) = 1;
4738 set_mem_alias_set (mem, set);
4740 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
4741 emit_move_insn (mem, reg);
4746 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4747 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4750 CUMULATIVE_ARGS next_cum;
4754 /* This argument doesn't appear to be used anymore. Which is good,
4755 because the old code here didn't suppress rtl generation. */
4756 gcc_assert (!no_rtl);
4761 fntype = TREE_TYPE (current_function_decl);
4762 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
4763 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4764 != void_type_node));
4766 /* For varargs, we do not want to skip the dummy va_dcl argument.
4767 For stdargs, we do want to skip the last named argument. */
4770 function_arg_advance (&next_cum, mode, type, 1);
4772 if (TARGET_64BIT_MS_ABI)
4773 setup_incoming_varargs_ms_64 (&next_cum);
4775 setup_incoming_varargs_64 (&next_cum);
4778 /* Implement va_start. */
4781 ix86_va_start (tree valist, rtx nextarg)
4783 HOST_WIDE_INT words, n_gpr, n_fpr;
4784 tree f_gpr, f_fpr, f_ovf, f_sav;
4785 tree gpr, fpr, ovf, sav, t;
4788 /* Only 64bit target needs something special. */
4789 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4791 std_expand_builtin_va_start (valist, nextarg);
4795 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4796 f_fpr = TREE_CHAIN (f_gpr);
4797 f_ovf = TREE_CHAIN (f_fpr);
4798 f_sav = TREE_CHAIN (f_ovf);
4800 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4801 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4802 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4803 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4804 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4806 /* Count number of gp and fp argument registers used. */
4807 words = current_function_args_info.words;
4808 n_gpr = current_function_args_info.regno;
4809 n_fpr = current_function_args_info.sse_regno;
4811 if (cfun->va_list_gpr_size)
4813 type = TREE_TYPE (gpr);
4814 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
4815 build_int_cst (type, n_gpr * 8));
4816 TREE_SIDE_EFFECTS (t) = 1;
4817 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4820 if (cfun->va_list_fpr_size)
4822 type = TREE_TYPE (fpr);
4823 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
4824 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
4825 TREE_SIDE_EFFECTS (t) = 1;
4826 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4829 /* Find the overflow area. */
4830 type = TREE_TYPE (ovf);
4831 t = make_tree (type, virtual_incoming_args_rtx);
4833 t = build2 (POINTER_PLUS_EXPR, type, t,
4834 size_int (words * UNITS_PER_WORD));
4835 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
4836 TREE_SIDE_EFFECTS (t) = 1;
4837 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4839 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
4841 /* Find the register save area.
4842 Prologue of the function save it right above stack frame. */
4843 type = TREE_TYPE (sav);
4844 t = make_tree (type, frame_pointer_rtx);
4845 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
4846 TREE_SIDE_EFFECTS (t) = 1;
4847 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4851 /* Implement va_arg. */
4854 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4856 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
4857 tree f_gpr, f_fpr, f_ovf, f_sav;
4858 tree gpr, fpr, ovf, sav, t;
4860 tree lab_false, lab_over = NULL_TREE;
4865 enum machine_mode nat_mode;
4867 /* Only 64bit target needs something special. */
4868 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4869 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4871 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4872 f_fpr = TREE_CHAIN (f_gpr);
4873 f_ovf = TREE_CHAIN (f_fpr);
4874 f_sav = TREE_CHAIN (f_ovf);
4876 valist = build_va_arg_indirect_ref (valist);
4877 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4878 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4879 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4880 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4882 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
4884 type = build_pointer_type (type);
4885 size = int_size_in_bytes (type);
4886 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4888 nat_mode = type_natural_mode (type);
4889 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
4890 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
4892 /* Pull the value out of the saved registers. */
4894 addr = create_tmp_var (ptr_type_node, "addr");
4895 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
4899 int needed_intregs, needed_sseregs;
4901 tree int_addr, sse_addr;
4903 lab_false = create_artificial_label ();
4904 lab_over = create_artificial_label ();
4906 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
4908 need_temp = (!REG_P (container)
4909 && ((needed_intregs && TYPE_ALIGN (type) > 64)
4910 || TYPE_ALIGN (type) > 128));
4912 /* In case we are passing structure, verify that it is consecutive block
4913 on the register save area. If not we need to do moves. */
4914 if (!need_temp && !REG_P (container))
4916 /* Verify that all registers are strictly consecutive */
4917 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
4921 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4923 rtx slot = XVECEXP (container, 0, i);
4924 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
4925 || INTVAL (XEXP (slot, 1)) != i * 16)
4933 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4935 rtx slot = XVECEXP (container, 0, i);
4936 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
4937 || INTVAL (XEXP (slot, 1)) != i * 8)
4949 int_addr = create_tmp_var (ptr_type_node, "int_addr");
4950 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
4951 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
4952 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
4955 /* First ensure that we fit completely in registers. */
4958 t = build_int_cst (TREE_TYPE (gpr),
4959 (REGPARM_MAX - needed_intregs + 1) * 8);
4960 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
4961 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4962 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4963 gimplify_and_add (t, pre_p);
4967 t = build_int_cst (TREE_TYPE (fpr),
4968 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
4970 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
4971 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4972 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4973 gimplify_and_add (t, pre_p);
4976 /* Compute index to start of area used for integer regs. */
4979 /* int_addr = gpr + sav; */
4980 t = fold_convert (sizetype, gpr);
4981 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
4982 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
4983 gimplify_and_add (t, pre_p);
4987 /* sse_addr = fpr + sav; */
4988 t = fold_convert (sizetype, fpr);
4989 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
4990 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
4991 gimplify_and_add (t, pre_p);
4996 tree temp = create_tmp_var (type, "va_arg_tmp");
4999 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5000 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5001 gimplify_and_add (t, pre_p);
5003 for (i = 0; i < XVECLEN (container, 0); i++)
5005 rtx slot = XVECEXP (container, 0, i);
5006 rtx reg = XEXP (slot, 0);
5007 enum machine_mode mode = GET_MODE (reg);
5008 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5009 tree addr_type = build_pointer_type (piece_type);
5012 tree dest_addr, dest;
5014 if (SSE_REGNO_P (REGNO (reg)))
5016 src_addr = sse_addr;
5017 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5021 src_addr = int_addr;
5022 src_offset = REGNO (reg) * 8;
5024 src_addr = fold_convert (addr_type, src_addr);
5025 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5026 build_int_cst (addr_type, src_offset));
5027 src = build_va_arg_indirect_ref (src_addr);
5029 dest_addr = fold_convert (addr_type, addr);
5030 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5031 build_int_cst (addr_type, INTVAL (XEXP (slot, 1))));
5032 dest = build_va_arg_indirect_ref (dest_addr);
5034 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5035 gimplify_and_add (t, pre_p);
5041 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5042 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5043 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5044 gimplify_and_add (t, pre_p);
5048 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5049 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5050 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5051 gimplify_and_add (t, pre_p);
5054 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5055 gimplify_and_add (t, pre_p);
5057 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5058 append_to_statement_list (t, pre_p);
5061 /* ... otherwise out of the overflow area. */
5063 /* Care for on-stack alignment if needed. */
5064 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5065 || integer_zerop (TYPE_SIZE (type)))
5069 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5070 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5071 size_int (align - 1));
5072 t = fold_convert (sizetype, t);
5073 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5075 t = fold_convert (TREE_TYPE (ovf), t);
5077 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5079 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5080 gimplify_and_add (t2, pre_p);
5082 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5083 size_int (rsize * UNITS_PER_WORD));
5084 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5085 gimplify_and_add (t, pre_p);
5089 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5090 append_to_statement_list (t, pre_p);
5093 ptrtype = build_pointer_type (type);
5094 addr = fold_convert (ptrtype, addr);
5097 addr = build_va_arg_indirect_ref (addr);
5098 return build_va_arg_indirect_ref (addr);
5101 /* Return nonzero if OPNUM's MEM should be matched
5102 in movabs* patterns. */
5105 ix86_check_movabs (rtx insn, int opnum)
5109 set = PATTERN (insn);
5110 if (GET_CODE (set) == PARALLEL)
5111 set = XVECEXP (set, 0, 0);
5112 gcc_assert (GET_CODE (set) == SET);
5113 mem = XEXP (set, opnum);
5114 while (GET_CODE (mem) == SUBREG)
5115 mem = SUBREG_REG (mem);
5116 gcc_assert (MEM_P (mem));
5117 return (volatile_ok || !MEM_VOLATILE_P (mem));
5120 /* Initialize the table of extra 80387 mathematical constants. */
5123 init_ext_80387_constants (void)
5125 static const char * cst[5] =
5127 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5128 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5129 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5130 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5131 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5135 for (i = 0; i < 5; i++)
5137 real_from_string (&ext_80387_constants_table[i], cst[i]);
5138 /* Ensure each constant is rounded to XFmode precision. */
5139 real_convert (&ext_80387_constants_table[i],
5140 XFmode, &ext_80387_constants_table[i]);
5143 ext_80387_constants_init = 1;
5146 /* Return true if the constant is something that can be loaded with
5147 a special instruction. */
5150 standard_80387_constant_p (rtx x)
5152 enum machine_mode mode = GET_MODE (x);
5156 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5159 if (x == CONST0_RTX (mode))
5161 if (x == CONST1_RTX (mode))
5164 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5166 /* For XFmode constants, try to find a special 80387 instruction when
5167 optimizing for size or on those CPUs that benefit from them. */
5169 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5173 if (! ext_80387_constants_init)
5174 init_ext_80387_constants ();
5176 for (i = 0; i < 5; i++)
5177 if (real_identical (&r, &ext_80387_constants_table[i]))
5181 /* Load of the constant -0.0 or -1.0 will be split as
5182 fldz;fchs or fld1;fchs sequence. */
5183 if (real_isnegzero (&r))
5185 if (real_identical (&r, &dconstm1))
5191 /* Return the opcode of the special instruction to be used to load
5195 standard_80387_constant_opcode (rtx x)
5197 switch (standard_80387_constant_p (x))
5221 /* Return the CONST_DOUBLE representing the 80387 constant that is
5222 loaded by the specified special instruction. The argument IDX
5223 matches the return value from standard_80387_constant_p. */
5226 standard_80387_constant_rtx (int idx)
5230 if (! ext_80387_constants_init)
5231 init_ext_80387_constants ();
5247 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5251 /* Return 1 if mode is a valid mode for sse. */
5253 standard_sse_mode_p (enum machine_mode mode)
5270 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5273 standard_sse_constant_p (rtx x)
5275 enum machine_mode mode = GET_MODE (x);
5277 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5279 if (vector_all_ones_operand (x, mode)
5280 && standard_sse_mode_p (mode))
5281 return TARGET_SSE2 ? 2 : -1;
5286 /* Return the opcode of the special instruction to be used to load
5290 standard_sse_constant_opcode (rtx insn, rtx x)
5292 switch (standard_sse_constant_p (x))
5295 if (get_attr_mode (insn) == MODE_V4SF)
5296 return "xorps\t%0, %0";
5297 else if (get_attr_mode (insn) == MODE_V2DF)
5298 return "xorpd\t%0, %0";
5300 return "pxor\t%0, %0";
5302 return "pcmpeqd\t%0, %0";
5307 /* Returns 1 if OP contains a symbol reference */
5310 symbolic_reference_mentioned_p (rtx op)
5315 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5318 fmt = GET_RTX_FORMAT (GET_CODE (op));
5319 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5325 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5326 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5330 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5337 /* Return 1 if it is appropriate to emit `ret' instructions in the
5338 body of a function. Do this only if the epilogue is simple, needing a
5339 couple of insns. Prior to reloading, we can't tell how many registers
5340 must be saved, so return 0 then. Return 0 if there is no frame
5341 marker to de-allocate. */
5344 ix86_can_use_return_insn_p (void)
5346 struct ix86_frame frame;
5348 if (! reload_completed || frame_pointer_needed)
5351 /* Don't allow more than 32 pop, since that's all we can do
5352 with one instruction. */
5353 if (current_function_pops_args
5354 && current_function_args_size >= 32768)
5357 ix86_compute_frame_layout (&frame);
5358 return frame.to_allocate == 0 && frame.nregs == 0;
5361 /* Value should be nonzero if functions must have frame pointers.
5362 Zero means the frame pointer need not be set up (and parms may
5363 be accessed via the stack pointer) in functions that seem suitable. */
5366 ix86_frame_pointer_required (void)
5368 /* If we accessed previous frames, then the generated code expects
5369 to be able to access the saved ebp value in our frame. */
5370 if (cfun->machine->accesses_prev_frame)
5373 /* Several x86 os'es need a frame pointer for other reasons,
5374 usually pertaining to setjmp. */
5375 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5378 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5379 the frame pointer by default. Turn it back on now if we've not
5380 got a leaf function. */
5381 if (TARGET_OMIT_LEAF_FRAME_POINTER
5382 && (!current_function_is_leaf
5383 || ix86_current_function_calls_tls_descriptor))
5386 if (current_function_profile)
5392 /* Record that the current function accesses previous call frames. */
5395 ix86_setup_frame_addresses (void)
5397 cfun->machine->accesses_prev_frame = 1;
5400 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5401 # define USE_HIDDEN_LINKONCE 1
5403 # define USE_HIDDEN_LINKONCE 0
5406 static int pic_labels_used;
5408 /* Fills in the label name that should be used for a pc thunk for
5409 the given register. */
5412 get_pc_thunk_name (char name[32], unsigned int regno)
5414 gcc_assert (!TARGET_64BIT);
5416 if (USE_HIDDEN_LINKONCE)
5417 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5419 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5423 /* This function generates code for -fpic that loads %ebx with
5424 the return address of the caller and then returns. */
5427 ix86_file_end (void)
5432 for (regno = 0; regno < 8; ++regno)
5436 if (! ((pic_labels_used >> regno) & 1))
5439 get_pc_thunk_name (name, regno);
5444 switch_to_section (darwin_sections[text_coal_section]);
5445 fputs ("\t.weak_definition\t", asm_out_file);
5446 assemble_name (asm_out_file, name);
5447 fputs ("\n\t.private_extern\t", asm_out_file);
5448 assemble_name (asm_out_file, name);
5449 fputs ("\n", asm_out_file);
5450 ASM_OUTPUT_LABEL (asm_out_file, name);
5454 if (USE_HIDDEN_LINKONCE)
5458 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5460 TREE_PUBLIC (decl) = 1;
5461 TREE_STATIC (decl) = 1;
5462 DECL_ONE_ONLY (decl) = 1;
5464 (*targetm.asm_out.unique_section) (decl, 0);
5465 switch_to_section (get_named_section (decl, NULL, 0));
5467 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5468 fputs ("\t.hidden\t", asm_out_file);
5469 assemble_name (asm_out_file, name);
5470 fputc ('\n', asm_out_file);
5471 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5475 switch_to_section (text_section);
5476 ASM_OUTPUT_LABEL (asm_out_file, name);
5479 xops[0] = gen_rtx_REG (SImode, regno);
5480 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5481 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5482 output_asm_insn ("ret", xops);
5485 if (NEED_INDICATE_EXEC_STACK)
5486 file_end_indicate_exec_stack ();
5489 /* Emit code for the SET_GOT patterns. */
5492 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5498 if (TARGET_VXWORKS_RTP && flag_pic)
5500 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5501 xops[2] = gen_rtx_MEM (Pmode,
5502 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5503 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5505 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5506 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5507 an unadorned address. */
5508 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5509 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5510 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5514 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5516 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5518 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5521 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5523 output_asm_insn ("call\t%a2", xops);
5526 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5527 is what will be referenced by the Mach-O PIC subsystem. */
5529 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5532 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5533 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5536 output_asm_insn ("pop{l}\t%0", xops);
5541 get_pc_thunk_name (name, REGNO (dest));
5542 pic_labels_used |= 1 << REGNO (dest);
5544 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5545 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5546 output_asm_insn ("call\t%X2", xops);
5547 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5548 is what will be referenced by the Mach-O PIC subsystem. */
5551 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5553 targetm.asm_out.internal_label (asm_out_file, "L",
5554 CODE_LABEL_NUMBER (label));
5561 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5562 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5564 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5569 /* Generate an "push" pattern for input ARG. */
5574 return gen_rtx_SET (VOIDmode,
5576 gen_rtx_PRE_DEC (Pmode,
5577 stack_pointer_rtx)),
5581 /* Return >= 0 if there is an unused call-clobbered register available
5582 for the entire function. */
5585 ix86_select_alt_pic_regnum (void)
5587 if (current_function_is_leaf && !current_function_profile
5588 && !ix86_current_function_calls_tls_descriptor)
5591 for (i = 2; i >= 0; --i)
5592 if (!df_regs_ever_live_p (i))
5596 return INVALID_REGNUM;
5599 /* Return 1 if we need to save REGNO. */
5601 ix86_save_reg (unsigned int regno, int maybe_eh_return)
5603 if (pic_offset_table_rtx
5604 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
5605 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
5606 || current_function_profile
5607 || current_function_calls_eh_return
5608 || current_function_uses_const_pool))
5610 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
5615 if (current_function_calls_eh_return && maybe_eh_return)
5620 unsigned test = EH_RETURN_DATA_REGNO (i);
5621 if (test == INVALID_REGNUM)
5628 if (cfun->machine->force_align_arg_pointer
5629 && regno == REGNO (cfun->machine->force_align_arg_pointer))
5632 return (df_regs_ever_live_p (regno)
5633 && !call_used_regs[regno]
5634 && !fixed_regs[regno]
5635 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
5638 /* Return number of registers to be saved on the stack. */
5641 ix86_nsaved_regs (void)
5646 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
5647 if (ix86_save_reg (regno, true))
5652 /* Return the offset between two registers, one to be eliminated, and the other
5653 its replacement, at the start of a routine. */
5656 ix86_initial_elimination_offset (int from, int to)
5658 struct ix86_frame frame;
5659 ix86_compute_frame_layout (&frame);
5661 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
5662 return frame.hard_frame_pointer_offset;
5663 else if (from == FRAME_POINTER_REGNUM
5664 && to == HARD_FRAME_POINTER_REGNUM)
5665 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
5668 gcc_assert (to == STACK_POINTER_REGNUM);
5670 if (from == ARG_POINTER_REGNUM)
5671 return frame.stack_pointer_offset;
5673 gcc_assert (from == FRAME_POINTER_REGNUM);
5674 return frame.stack_pointer_offset - frame.frame_pointer_offset;
5678 /* Fill structure ix86_frame about frame of currently computed function. */
5681 ix86_compute_frame_layout (struct ix86_frame *frame)
5683 HOST_WIDE_INT total_size;
5684 unsigned int stack_alignment_needed;
5685 HOST_WIDE_INT offset;
5686 unsigned int preferred_alignment;
5687 HOST_WIDE_INT size = get_frame_size ();
5689 frame->nregs = ix86_nsaved_regs ();
5692 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
5693 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
5695 /* During reload iteration the amount of registers saved can change.
5696 Recompute the value as needed. Do not recompute when amount of registers
5697 didn't change as reload does multiple calls to the function and does not
5698 expect the decision to change within single iteration. */
5700 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
5702 int count = frame->nregs;
5704 cfun->machine->use_fast_prologue_epilogue_nregs = count;
5705 /* The fast prologue uses move instead of push to save registers. This
5706 is significantly longer, but also executes faster as modern hardware
5707 can execute the moves in parallel, but can't do that for push/pop.
5709 Be careful about choosing what prologue to emit: When function takes
5710 many instructions to execute we may use slow version as well as in
5711 case function is known to be outside hot spot (this is known with
5712 feedback only). Weight the size of function by number of registers
5713 to save as it is cheap to use one or two push instructions but very
5714 slow to use many of them. */
5716 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
5717 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
5718 || (flag_branch_probabilities
5719 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
5720 cfun->machine->use_fast_prologue_epilogue = false;
5722 cfun->machine->use_fast_prologue_epilogue
5723 = !expensive_function_p (count);
5725 if (TARGET_PROLOGUE_USING_MOVE
5726 && cfun->machine->use_fast_prologue_epilogue)
5727 frame->save_regs_using_mov = true;
5729 frame->save_regs_using_mov = false;
5732 /* Skip return address and saved base pointer. */
5733 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
5735 frame->hard_frame_pointer_offset = offset;
5737 /* Do some sanity checking of stack_alignment_needed and
5738 preferred_alignment, since i386 port is the only using those features
5739 that may break easily. */
5741 gcc_assert (!size || stack_alignment_needed);
5742 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
5743 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5744 gcc_assert (stack_alignment_needed
5745 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5747 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
5748 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
5750 /* Register save area */
5751 offset += frame->nregs * UNITS_PER_WORD;
5754 if (ix86_save_varrargs_registers)
5756 offset += X86_64_VARARGS_SIZE;
5757 frame->va_arg_size = X86_64_VARARGS_SIZE;
5760 frame->va_arg_size = 0;
5762 /* Align start of frame for local function. */
5763 frame->padding1 = ((offset + stack_alignment_needed - 1)
5764 & -stack_alignment_needed) - offset;
5766 offset += frame->padding1;
5768 /* Frame pointer points here. */
5769 frame->frame_pointer_offset = offset;
5773 /* Add outgoing arguments area. Can be skipped if we eliminated
5774 all the function calls as dead code.
5775 Skipping is however impossible when function calls alloca. Alloca
5776 expander assumes that last current_function_outgoing_args_size
5777 of stack frame are unused. */
5778 if (ACCUMULATE_OUTGOING_ARGS
5779 && (!current_function_is_leaf || current_function_calls_alloca
5780 || ix86_current_function_calls_tls_descriptor))
5782 offset += current_function_outgoing_args_size;
5783 frame->outgoing_arguments_size = current_function_outgoing_args_size;
5786 frame->outgoing_arguments_size = 0;
5788 /* Align stack boundary. Only needed if we're calling another function
5790 if (!current_function_is_leaf || current_function_calls_alloca
5791 || ix86_current_function_calls_tls_descriptor)
5792 frame->padding2 = ((offset + preferred_alignment - 1)
5793 & -preferred_alignment) - offset;
5795 frame->padding2 = 0;
5797 offset += frame->padding2;
5799 /* We've reached end of stack frame. */
5800 frame->stack_pointer_offset = offset;
5802 /* Size prologue needs to allocate. */
5803 frame->to_allocate =
5804 (size + frame->padding1 + frame->padding2
5805 + frame->outgoing_arguments_size + frame->va_arg_size);
5807 if ((!frame->to_allocate && frame->nregs <= 1)
5808 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
5809 frame->save_regs_using_mov = false;
5811 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
5812 && current_function_is_leaf
5813 && !ix86_current_function_calls_tls_descriptor)
5815 frame->red_zone_size = frame->to_allocate;
5816 if (frame->save_regs_using_mov)
5817 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
5818 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
5819 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
5822 frame->red_zone_size = 0;
5823 frame->to_allocate -= frame->red_zone_size;
5824 frame->stack_pointer_offset -= frame->red_zone_size;
5826 fprintf (stderr, "\n");
5827 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
5828 fprintf (stderr, "size: %ld\n", (long)size);
5829 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
5830 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
5831 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
5832 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
5833 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
5834 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
5835 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
5836 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
5837 (long)frame->hard_frame_pointer_offset);
5838 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
5839 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
5840 fprintf (stderr, "current_function_calls_alloca: %ld\n", (long)current_function_calls_alloca);
5841 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
5845 /* Emit code to save registers in the prologue. */
5848 ix86_emit_save_regs (void)
5853 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
5854 if (ix86_save_reg (regno, true))
5856 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
5857 RTX_FRAME_RELATED_P (insn) = 1;
5861 /* Emit code to save registers using MOV insns. First register
5862 is restored from POINTER + OFFSET. */
5864 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
5869 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5870 if (ix86_save_reg (regno, true))
5872 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
5874 gen_rtx_REG (Pmode, regno));
5875 RTX_FRAME_RELATED_P (insn) = 1;
5876 offset += UNITS_PER_WORD;
5880 /* Expand prologue or epilogue stack adjustment.
5881 The pattern exist to put a dependency on all ebp-based memory accesses.
5882 STYLE should be negative if instructions should be marked as frame related,
5883 zero if %r11 register is live and cannot be freely used and positive
5887 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
5892 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
5893 else if (x86_64_immediate_operand (offset, DImode))
5894 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
5898 /* r11 is used by indirect sibcall return as well, set before the
5899 epilogue and used after the epilogue. ATM indirect sibcall
5900 shouldn't be used together with huge frame sizes in one
5901 function because of the frame_size check in sibcall.c. */
5903 r11 = gen_rtx_REG (DImode, R11_REG);
5904 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
5906 RTX_FRAME_RELATED_P (insn) = 1;
5907 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
5911 RTX_FRAME_RELATED_P (insn) = 1;
5914 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
5917 ix86_internal_arg_pointer (void)
5919 bool has_force_align_arg_pointer =
5920 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
5921 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
5922 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
5923 && DECL_NAME (current_function_decl)
5924 && MAIN_NAME_P (DECL_NAME (current_function_decl))
5925 && DECL_FILE_SCOPE_P (current_function_decl))
5926 || ix86_force_align_arg_pointer
5927 || has_force_align_arg_pointer)
5929 /* Nested functions can't realign the stack due to a register
5931 if (DECL_CONTEXT (current_function_decl)
5932 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
5934 if (ix86_force_align_arg_pointer)
5935 warning (0, "-mstackrealign ignored for nested functions");
5936 if (has_force_align_arg_pointer)
5937 error ("%s not supported for nested functions",
5938 ix86_force_align_arg_pointer_string);
5939 return virtual_incoming_args_rtx;
5941 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, 2);
5942 return copy_to_reg (cfun->machine->force_align_arg_pointer);
5945 return virtual_incoming_args_rtx;
5948 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
5949 This is called from dwarf2out.c to emit call frame instructions
5950 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
5952 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
5954 rtx unspec = SET_SRC (pattern);
5955 gcc_assert (GET_CODE (unspec) == UNSPEC);
5959 case UNSPEC_REG_SAVE:
5960 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
5961 SET_DEST (pattern));
5963 case UNSPEC_DEF_CFA:
5964 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
5965 INTVAL (XVECEXP (unspec, 0, 0)));
5972 /* Expand the prologue into a bunch of separate insns. */
5975 ix86_expand_prologue (void)
5979 struct ix86_frame frame;
5980 HOST_WIDE_INT allocate;
5982 ix86_compute_frame_layout (&frame);
5984 if (cfun->machine->force_align_arg_pointer)
5988 /* Grab the argument pointer. */
5989 x = plus_constant (stack_pointer_rtx, 4);
5990 y = cfun->machine->force_align_arg_pointer;
5991 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
5992 RTX_FRAME_RELATED_P (insn) = 1;
5994 /* The unwind info consists of two parts: install the fafp as the cfa,
5995 and record the fafp as the "save register" of the stack pointer.
5996 The later is there in order that the unwinder can see where it
5997 should restore the stack pointer across the and insn. */
5998 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
5999 x = gen_rtx_SET (VOIDmode, y, x);
6000 RTX_FRAME_RELATED_P (x) = 1;
6001 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6003 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6004 RTX_FRAME_RELATED_P (y) = 1;
6005 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6006 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6007 REG_NOTES (insn) = x;
6009 /* Align the stack. */
6010 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6013 /* And here we cheat like madmen with the unwind info. We force the
6014 cfa register back to sp+4, which is exactly what it was at the
6015 start of the function. Re-pushing the return address results in
6016 the return at the same spot relative to the cfa, and thus is
6017 correct wrt the unwind info. */
6018 x = cfun->machine->force_align_arg_pointer;
6019 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6020 insn = emit_insn (gen_push (x));
6021 RTX_FRAME_RELATED_P (insn) = 1;
6024 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6025 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6026 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6027 REG_NOTES (insn) = x;
6030 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6031 slower on all targets. Also sdb doesn't like it. */
6033 if (frame_pointer_needed)
6035 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6036 RTX_FRAME_RELATED_P (insn) = 1;
6038 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6039 RTX_FRAME_RELATED_P (insn) = 1;
6042 allocate = frame.to_allocate;
6044 if (!frame.save_regs_using_mov)
6045 ix86_emit_save_regs ();
6047 allocate += frame.nregs * UNITS_PER_WORD;
6049 /* When using red zone we may start register saving before allocating
6050 the stack frame saving one cycle of the prologue. */
6051 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
6052 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6053 : stack_pointer_rtx,
6054 -frame.nregs * UNITS_PER_WORD);
6058 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6059 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6060 GEN_INT (-allocate), -1);
6063 /* Only valid for Win32. */
6064 rtx eax = gen_rtx_REG (Pmode, 0);
6068 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
6070 if (TARGET_64BIT_MS_ABI)
6073 eax_live = ix86_eax_live_at_start_p ();
6077 emit_insn (gen_push (eax));
6078 allocate -= UNITS_PER_WORD;
6081 emit_move_insn (eax, GEN_INT (allocate));
6084 insn = gen_allocate_stack_worker_64 (eax);
6086 insn = gen_allocate_stack_worker_32 (eax);
6087 insn = emit_insn (insn);
6088 RTX_FRAME_RELATED_P (insn) = 1;
6089 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6090 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6091 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6092 t, REG_NOTES (insn));
6096 if (frame_pointer_needed)
6097 t = plus_constant (hard_frame_pointer_rtx,
6100 - frame.nregs * UNITS_PER_WORD);
6102 t = plus_constant (stack_pointer_rtx, allocate);
6103 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6107 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
6109 if (!frame_pointer_needed || !frame.to_allocate)
6110 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6112 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6113 -frame.nregs * UNITS_PER_WORD);
6116 pic_reg_used = false;
6117 if (pic_offset_table_rtx
6118 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6119 || current_function_profile))
6121 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6123 if (alt_pic_reg_used != INVALID_REGNUM)
6124 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6126 pic_reg_used = true;
6133 if (ix86_cmodel == CM_LARGE_PIC)
6135 rtx tmp_reg = gen_rtx_REG (DImode,
6136 FIRST_REX_INT_REG + 3 /* R11 */);
6137 rtx label = gen_label_rtx ();
6139 LABEL_PRESERVE_P (label) = 1;
6140 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6141 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6142 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6143 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6144 pic_offset_table_rtx, tmp_reg));
6147 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6150 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6153 /* Prevent function calls from be scheduled before the call to mcount.
6154 In the pic_reg_used case, make sure that the got load isn't deleted. */
6155 if (current_function_profile)
6158 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6159 emit_insn (gen_blockage ());
6163 /* Emit code to restore saved registers using MOV insns. First register
6164 is restored from POINTER + OFFSET. */
6166 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6167 int maybe_eh_return)
6170 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6172 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6173 if (ix86_save_reg (regno, maybe_eh_return))
6175 /* Ensure that adjust_address won't be forced to produce pointer
6176 out of range allowed by x86-64 instruction set. */
6177 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6181 r11 = gen_rtx_REG (DImode, R11_REG);
6182 emit_move_insn (r11, GEN_INT (offset));
6183 emit_insn (gen_adddi3 (r11, r11, pointer));
6184 base_address = gen_rtx_MEM (Pmode, r11);
6187 emit_move_insn (gen_rtx_REG (Pmode, regno),
6188 adjust_address (base_address, Pmode, offset));
6189 offset += UNITS_PER_WORD;
6193 /* Restore function stack, frame, and registers. */
6196 ix86_expand_epilogue (int style)
6199 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6200 struct ix86_frame frame;
6201 HOST_WIDE_INT offset;
6203 ix86_compute_frame_layout (&frame);
6205 /* Calculate start of saved registers relative to ebp. Special care
6206 must be taken for the normal return case of a function using
6207 eh_return: the eax and edx registers are marked as saved, but not
6208 restored along this path. */
6209 offset = frame.nregs;
6210 if (current_function_calls_eh_return && style != 2)
6212 offset *= -UNITS_PER_WORD;
6214 /* If we're only restoring one register and sp is not valid then
6215 using a move instruction to restore the register since it's
6216 less work than reloading sp and popping the register.
6218 The default code result in stack adjustment using add/lea instruction,
6219 while this code results in LEAVE instruction (or discrete equivalent),
6220 so it is profitable in some other cases as well. Especially when there
6221 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6222 and there is exactly one register to pop. This heuristic may need some
6223 tuning in future. */
6224 if ((!sp_valid && frame.nregs <= 1)
6225 || (TARGET_EPILOGUE_USING_MOVE
6226 && cfun->machine->use_fast_prologue_epilogue
6227 && (frame.nregs > 1 || frame.to_allocate))
6228 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6229 || (frame_pointer_needed && TARGET_USE_LEAVE
6230 && cfun->machine->use_fast_prologue_epilogue
6231 && frame.nregs == 1)
6232 || current_function_calls_eh_return)
6234 /* Restore registers. We can use ebp or esp to address the memory
6235 locations. If both are available, default to ebp, since offsets
6236 are known to be small. Only exception is esp pointing directly to the
6237 end of block of saved registers, where we may simplify addressing
6240 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6241 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6242 frame.to_allocate, style == 2);
6244 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6245 offset, style == 2);
6247 /* eh_return epilogues need %ecx added to the stack pointer. */
6250 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6252 if (frame_pointer_needed)
6254 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6255 tmp = plus_constant (tmp, UNITS_PER_WORD);
6256 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6258 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6259 emit_move_insn (hard_frame_pointer_rtx, tmp);
6261 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6266 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6267 tmp = plus_constant (tmp, (frame.to_allocate
6268 + frame.nregs * UNITS_PER_WORD));
6269 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6272 else if (!frame_pointer_needed)
6273 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6274 GEN_INT (frame.to_allocate
6275 + frame.nregs * UNITS_PER_WORD),
6277 /* If not an i386, mov & pop is faster than "leave". */
6278 else if (TARGET_USE_LEAVE || optimize_size
6279 || !cfun->machine->use_fast_prologue_epilogue)
6280 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6283 pro_epilogue_adjust_stack (stack_pointer_rtx,
6284 hard_frame_pointer_rtx,
6287 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6289 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6294 /* First step is to deallocate the stack frame so that we can
6295 pop the registers. */
6298 gcc_assert (frame_pointer_needed);
6299 pro_epilogue_adjust_stack (stack_pointer_rtx,
6300 hard_frame_pointer_rtx,
6301 GEN_INT (offset), style);
6303 else if (frame.to_allocate)
6304 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6305 GEN_INT (frame.to_allocate), style);
6307 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6308 if (ix86_save_reg (regno, false))
6311 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6313 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6315 if (frame_pointer_needed)
6317 /* Leave results in shorter dependency chains on CPUs that are
6318 able to grok it fast. */
6319 if (TARGET_USE_LEAVE)
6320 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6321 else if (TARGET_64BIT)
6322 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6324 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6328 if (cfun->machine->force_align_arg_pointer)
6330 emit_insn (gen_addsi3 (stack_pointer_rtx,
6331 cfun->machine->force_align_arg_pointer,
6335 /* Sibcall epilogues don't want a return instruction. */
6339 if (current_function_pops_args && current_function_args_size)
6341 rtx popc = GEN_INT (current_function_pops_args);
6343 /* i386 can only pop 64K bytes. If asked to pop more, pop
6344 return address, do explicit add, and jump indirectly to the
6347 if (current_function_pops_args >= 65536)
6349 rtx ecx = gen_rtx_REG (SImode, 2);
6351 /* There is no "pascal" calling convention in any 64bit ABI. */
6352 gcc_assert (!TARGET_64BIT);
6354 emit_insn (gen_popsi1 (ecx));
6355 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6356 emit_jump_insn (gen_return_indirect_internal (ecx));
6359 emit_jump_insn (gen_return_pop_internal (popc));
6362 emit_jump_insn (gen_return_internal ());
6365 /* Reset from the function's potential modifications. */
6368 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6369 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6371 if (pic_offset_table_rtx)
6372 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6374 /* Mach-O doesn't support labels at the end of objects, so if
6375 it looks like we might want one, insert a NOP. */
6377 rtx insn = get_last_insn ();
6380 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6381 insn = PREV_INSN (insn);
6385 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6386 fputs ("\tnop\n", file);
6392 /* Extract the parts of an RTL expression that is a valid memory address
6393 for an instruction. Return 0 if the structure of the address is
6394 grossly off. Return -1 if the address contains ASHIFT, so it is not
6395 strictly valid, but still used for computing length of lea instruction. */
6398 ix86_decompose_address (rtx addr, struct ix86_address *out)
6400 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6401 rtx base_reg, index_reg;
6402 HOST_WIDE_INT scale = 1;
6403 rtx scale_rtx = NULL_RTX;
6405 enum ix86_address_seg seg = SEG_DEFAULT;
6407 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6409 else if (GET_CODE (addr) == PLUS)
6419 addends[n++] = XEXP (op, 1);
6422 while (GET_CODE (op) == PLUS);
6427 for (i = n; i >= 0; --i)
6430 switch (GET_CODE (op))
6435 index = XEXP (op, 0);
6436 scale_rtx = XEXP (op, 1);
6440 if (XINT (op, 1) == UNSPEC_TP
6441 && TARGET_TLS_DIRECT_SEG_REFS
6442 && seg == SEG_DEFAULT)
6443 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6472 else if (GET_CODE (addr) == MULT)
6474 index = XEXP (addr, 0); /* index*scale */
6475 scale_rtx = XEXP (addr, 1);
6477 else if (GET_CODE (addr) == ASHIFT)
6481 /* We're called for lea too, which implements ashift on occasion. */
6482 index = XEXP (addr, 0);
6483 tmp = XEXP (addr, 1);
6484 if (!CONST_INT_P (tmp))
6486 scale = INTVAL (tmp);
6487 if ((unsigned HOST_WIDE_INT) scale > 3)
6493 disp = addr; /* displacement */
6495 /* Extract the integral value of scale. */
6498 if (!CONST_INT_P (scale_rtx))
6500 scale = INTVAL (scale_rtx);
6503 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6504 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6506 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6507 if (base_reg && index_reg && scale == 1
6508 && (index_reg == arg_pointer_rtx
6509 || index_reg == frame_pointer_rtx
6510 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6513 tmp = base, base = index, index = tmp;
6514 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6517 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6518 if ((base_reg == hard_frame_pointer_rtx
6519 || base_reg == frame_pointer_rtx
6520 || base_reg == arg_pointer_rtx) && !disp)
6523 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6524 Avoid this by transforming to [%esi+0]. */
6525 if (ix86_tune == PROCESSOR_K6 && !optimize_size
6526 && base_reg && !index_reg && !disp
6528 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6531 /* Special case: encode reg+reg instead of reg*2. */
6532 if (!base && index && scale && scale == 2)
6533 base = index, base_reg = index_reg, scale = 1;
6535 /* Special case: scaling cannot be encoded without base or displacement. */
6536 if (!base && !disp && index && scale != 1)
6548 /* Return cost of the memory address x.
6549 For i386, it is better to use a complex address than let gcc copy
6550 the address into a reg and make a new pseudo. But not if the address
6551 requires to two regs - that would mean more pseudos with longer
6554 ix86_address_cost (rtx x)
6556 struct ix86_address parts;
6558 int ok = ix86_decompose_address (x, &parts);
6562 if (parts.base && GET_CODE (parts.base) == SUBREG)
6563 parts.base = SUBREG_REG (parts.base);
6564 if (parts.index && GET_CODE (parts.index) == SUBREG)
6565 parts.index = SUBREG_REG (parts.index);
6567 /* More complex memory references are better. */
6568 if (parts.disp && parts.disp != const0_rtx)
6570 if (parts.seg != SEG_DEFAULT)
6573 /* Attempt to minimize number of registers in the address. */
6575 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6577 && (!REG_P (parts.index)
6578 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6582 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
6584 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
6585 && parts.base != parts.index)
6588 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6589 since it's predecode logic can't detect the length of instructions
6590 and it degenerates to vector decoded. Increase cost of such
6591 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6592 to split such addresses or even refuse such addresses at all.
6594 Following addressing modes are affected:
6599 The first and last case may be avoidable by explicitly coding the zero in
6600 memory address, but I don't have AMD-K6 machine handy to check this
6604 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
6605 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
6606 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
6612 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6613 this is used for to form addresses to local data when -fPIC is in
6617 darwin_local_data_pic (rtx disp)
6619 if (GET_CODE (disp) == MINUS)
6621 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
6622 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
6623 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
6625 const char *sym_name = XSTR (XEXP (disp, 1), 0);
6626 if (! strcmp (sym_name, "<pic base>"))
6634 /* Determine if a given RTX is a valid constant. We already know this
6635 satisfies CONSTANT_P. */
6638 legitimate_constant_p (rtx x)
6640 switch (GET_CODE (x))
6645 if (GET_CODE (x) == PLUS)
6647 if (!CONST_INT_P (XEXP (x, 1)))
6652 if (TARGET_MACHO && darwin_local_data_pic (x))
6655 /* Only some unspecs are valid as "constants". */
6656 if (GET_CODE (x) == UNSPEC)
6657 switch (XINT (x, 1))
6662 return TARGET_64BIT;
6665 x = XVECEXP (x, 0, 0);
6666 return (GET_CODE (x) == SYMBOL_REF
6667 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6669 x = XVECEXP (x, 0, 0);
6670 return (GET_CODE (x) == SYMBOL_REF
6671 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
6676 /* We must have drilled down to a symbol. */
6677 if (GET_CODE (x) == LABEL_REF)
6679 if (GET_CODE (x) != SYMBOL_REF)
6684 /* TLS symbols are never valid. */
6685 if (SYMBOL_REF_TLS_MODEL (x))
6688 /* DLLIMPORT symbols are never valid. */
6689 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
6690 && SYMBOL_REF_DLLIMPORT_P (x))
6695 if (GET_MODE (x) == TImode
6696 && x != CONST0_RTX (TImode)
6702 if (x == CONST0_RTX (GET_MODE (x)))
6710 /* Otherwise we handle everything else in the move patterns. */
6714 /* Determine if it's legal to put X into the constant pool. This
6715 is not possible for the address of thread-local symbols, which
6716 is checked above. */
6719 ix86_cannot_force_const_mem (rtx x)
6721 /* We can always put integral constants and vectors in memory. */
6722 switch (GET_CODE (x))
6732 return !legitimate_constant_p (x);
6735 /* Determine if a given RTX is a valid constant address. */
6738 constant_address_p (rtx x)
6740 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
6743 /* Nonzero if the constant value X is a legitimate general operand
6744 when generating PIC code. It is given that flag_pic is on and
6745 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
6748 legitimate_pic_operand_p (rtx x)
6752 switch (GET_CODE (x))
6755 inner = XEXP (x, 0);
6756 if (GET_CODE (inner) == PLUS
6757 && CONST_INT_P (XEXP (inner, 1)))
6758 inner = XEXP (inner, 0);
6760 /* Only some unspecs are valid as "constants". */
6761 if (GET_CODE (inner) == UNSPEC)
6762 switch (XINT (inner, 1))
6767 return TARGET_64BIT;
6769 x = XVECEXP (inner, 0, 0);
6770 return (GET_CODE (x) == SYMBOL_REF
6771 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6779 return legitimate_pic_address_disp_p (x);
6786 /* Determine if a given CONST RTX is a valid memory displacement
6790 legitimate_pic_address_disp_p (rtx disp)
6794 /* In 64bit mode we can allow direct addresses of symbols and labels
6795 when they are not dynamic symbols. */
6798 rtx op0 = disp, op1;
6800 switch (GET_CODE (disp))
6806 if (GET_CODE (XEXP (disp, 0)) != PLUS)
6808 op0 = XEXP (XEXP (disp, 0), 0);
6809 op1 = XEXP (XEXP (disp, 0), 1);
6810 if (!CONST_INT_P (op1)
6811 || INTVAL (op1) >= 16*1024*1024
6812 || INTVAL (op1) < -16*1024*1024)
6814 if (GET_CODE (op0) == LABEL_REF)
6816 if (GET_CODE (op0) != SYMBOL_REF)
6821 /* TLS references should always be enclosed in UNSPEC. */
6822 if (SYMBOL_REF_TLS_MODEL (op0))
6824 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
6825 && ix86_cmodel != CM_LARGE_PIC)
6833 if (GET_CODE (disp) != CONST)
6835 disp = XEXP (disp, 0);
6839 /* We are unsafe to allow PLUS expressions. This limit allowed distance
6840 of GOT tables. We should not need these anyway. */
6841 if (GET_CODE (disp) != UNSPEC
6842 || (XINT (disp, 1) != UNSPEC_GOTPCREL
6843 && XINT (disp, 1) != UNSPEC_GOTOFF
6844 && XINT (disp, 1) != UNSPEC_PLTOFF))
6847 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
6848 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
6854 if (GET_CODE (disp) == PLUS)
6856 if (!CONST_INT_P (XEXP (disp, 1)))
6858 disp = XEXP (disp, 0);
6862 if (TARGET_MACHO && darwin_local_data_pic (disp))
6865 if (GET_CODE (disp) != UNSPEC)
6868 switch (XINT (disp, 1))
6873 /* We need to check for both symbols and labels because VxWorks loads
6874 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
6876 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
6877 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
6879 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
6880 While ABI specify also 32bit relocation but we don't produce it in
6881 small PIC model at all. */
6882 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
6883 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
6885 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
6887 case UNSPEC_GOTTPOFF:
6888 case UNSPEC_GOTNTPOFF:
6889 case UNSPEC_INDNTPOFF:
6892 disp = XVECEXP (disp, 0, 0);
6893 return (GET_CODE (disp) == SYMBOL_REF
6894 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
6896 disp = XVECEXP (disp, 0, 0);
6897 return (GET_CODE (disp) == SYMBOL_REF
6898 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
6900 disp = XVECEXP (disp, 0, 0);
6901 return (GET_CODE (disp) == SYMBOL_REF
6902 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
6908 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
6909 memory address for an instruction. The MODE argument is the machine mode
6910 for the MEM expression that wants to use this address.
6912 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
6913 convert common non-canonical forms to canonical form so that they will
6917 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
6918 rtx addr, int strict)
6920 struct ix86_address parts;
6921 rtx base, index, disp;
6922 HOST_WIDE_INT scale;
6923 const char *reason = NULL;
6924 rtx reason_rtx = NULL_RTX;
6926 if (ix86_decompose_address (addr, &parts) <= 0)
6928 reason = "decomposition failed";
6933 index = parts.index;
6935 scale = parts.scale;
6937 /* Validate base register.
6939 Don't allow SUBREG's that span more than a word here. It can lead to spill
6940 failures when the base is one word out of a two word structure, which is
6941 represented internally as a DImode int. */
6950 else if (GET_CODE (base) == SUBREG
6951 && REG_P (SUBREG_REG (base))
6952 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
6954 reg = SUBREG_REG (base);
6957 reason = "base is not a register";
6961 if (GET_MODE (base) != Pmode)
6963 reason = "base is not in Pmode";
6967 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
6968 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
6970 reason = "base is not valid";
6975 /* Validate index register.
6977 Don't allow SUBREG's that span more than a word here -- same as above. */
6986 else if (GET_CODE (index) == SUBREG
6987 && REG_P (SUBREG_REG (index))
6988 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
6990 reg = SUBREG_REG (index);
6993 reason = "index is not a register";
6997 if (GET_MODE (index) != Pmode)
6999 reason = "index is not in Pmode";
7003 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7004 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7006 reason = "index is not valid";
7011 /* Validate scale factor. */
7014 reason_rtx = GEN_INT (scale);
7017 reason = "scale without index";
7021 if (scale != 2 && scale != 4 && scale != 8)
7023 reason = "scale is not a valid multiplier";
7028 /* Validate displacement. */
7033 if (GET_CODE (disp) == CONST
7034 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7035 switch (XINT (XEXP (disp, 0), 1))
7037 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7038 used. While ABI specify also 32bit relocations, we don't produce
7039 them at all and use IP relative instead. */
7042 gcc_assert (flag_pic);
7044 goto is_legitimate_pic;
7045 reason = "64bit address unspec";
7048 case UNSPEC_GOTPCREL:
7049 gcc_assert (flag_pic);
7050 goto is_legitimate_pic;
7052 case UNSPEC_GOTTPOFF:
7053 case UNSPEC_GOTNTPOFF:
7054 case UNSPEC_INDNTPOFF:
7060 reason = "invalid address unspec";
7064 else if (SYMBOLIC_CONST (disp)
7068 && MACHOPIC_INDIRECT
7069 && !machopic_operand_p (disp)
7075 if (TARGET_64BIT && (index || base))
7077 /* foo@dtpoff(%rX) is ok. */
7078 if (GET_CODE (disp) != CONST
7079 || GET_CODE (XEXP (disp, 0)) != PLUS
7080 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7081 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7082 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7083 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7085 reason = "non-constant pic memory reference";
7089 else if (! legitimate_pic_address_disp_p (disp))
7091 reason = "displacement is an invalid pic construct";
7095 /* This code used to verify that a symbolic pic displacement
7096 includes the pic_offset_table_rtx register.
7098 While this is good idea, unfortunately these constructs may
7099 be created by "adds using lea" optimization for incorrect
7108 This code is nonsensical, but results in addressing
7109 GOT table with pic_offset_table_rtx base. We can't
7110 just refuse it easily, since it gets matched by
7111 "addsi3" pattern, that later gets split to lea in the
7112 case output register differs from input. While this
7113 can be handled by separate addsi pattern for this case
7114 that never results in lea, this seems to be easier and
7115 correct fix for crash to disable this test. */
7117 else if (GET_CODE (disp) != LABEL_REF
7118 && !CONST_INT_P (disp)
7119 && (GET_CODE (disp) != CONST
7120 || !legitimate_constant_p (disp))
7121 && (GET_CODE (disp) != SYMBOL_REF
7122 || !legitimate_constant_p (disp)))
7124 reason = "displacement is not constant";
7127 else if (TARGET_64BIT
7128 && !x86_64_immediate_operand (disp, VOIDmode))
7130 reason = "displacement is out of range";
7135 /* Everything looks valid. */
7142 /* Return a unique alias set for the GOT. */
7144 static HOST_WIDE_INT
7145 ix86_GOT_alias_set (void)
7147 static HOST_WIDE_INT set = -1;
7149 set = new_alias_set ();
7153 /* Return a legitimate reference for ORIG (an address) using the
7154 register REG. If REG is 0, a new pseudo is generated.
7156 There are two types of references that must be handled:
7158 1. Global data references must load the address from the GOT, via
7159 the PIC reg. An insn is emitted to do this load, and the reg is
7162 2. Static data references, constant pool addresses, and code labels
7163 compute the address as an offset from the GOT, whose base is in
7164 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7165 differentiate them from global data objects. The returned
7166 address is the PIC reg + an unspec constant.
7168 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7169 reg also appears in the address. */
7172 legitimize_pic_address (rtx orig, rtx reg)
7179 if (TARGET_MACHO && !TARGET_64BIT)
7182 reg = gen_reg_rtx (Pmode);
7183 /* Use the generic Mach-O PIC machinery. */
7184 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7188 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7190 else if (TARGET_64BIT
7191 && ix86_cmodel != CM_SMALL_PIC
7192 && gotoff_operand (addr, Pmode))
7195 /* This symbol may be referenced via a displacement from the PIC
7196 base address (@GOTOFF). */
7198 if (reload_in_progress)
7199 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7200 if (GET_CODE (addr) == CONST)
7201 addr = XEXP (addr, 0);
7202 if (GET_CODE (addr) == PLUS)
7204 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7206 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7209 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7210 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7212 tmpreg = gen_reg_rtx (Pmode);
7215 emit_move_insn (tmpreg, new_rtx);
7219 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7220 tmpreg, 1, OPTAB_DIRECT);
7223 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7225 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7227 /* This symbol may be referenced via a displacement from the PIC
7228 base address (@GOTOFF). */
7230 if (reload_in_progress)
7231 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7232 if (GET_CODE (addr) == CONST)
7233 addr = XEXP (addr, 0);
7234 if (GET_CODE (addr) == PLUS)
7236 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7238 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7241 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7242 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7243 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7247 emit_move_insn (reg, new_rtx);
7251 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7252 /* We can't use @GOTOFF for text labels on VxWorks;
7253 see gotoff_operand. */
7254 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7256 /* Given that we've already handled dllimport variables separately
7257 in legitimize_address, and all other variables should satisfy
7258 legitimate_pic_address_disp_p, we should never arrive here. */
7259 gcc_assert (!TARGET_64BIT_MS_ABI);
7261 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7263 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7264 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7265 new_rtx = gen_const_mem (Pmode, new_rtx);
7266 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7269 reg = gen_reg_rtx (Pmode);
7270 /* Use directly gen_movsi, otherwise the address is loaded
7271 into register for CSE. We don't want to CSE this addresses,
7272 instead we CSE addresses from the GOT table, so skip this. */
7273 emit_insn (gen_movsi (reg, new_rtx));
7278 /* This symbol must be referenced via a load from the
7279 Global Offset Table (@GOT). */
7281 if (reload_in_progress)
7282 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7283 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7284 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7286 new_rtx = force_reg (Pmode, new_rtx);
7287 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7288 new_rtx = gen_const_mem (Pmode, new_rtx);
7289 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7292 reg = gen_reg_rtx (Pmode);
7293 emit_move_insn (reg, new_rtx);
7299 if (CONST_INT_P (addr)
7300 && !x86_64_immediate_operand (addr, VOIDmode))
7304 emit_move_insn (reg, addr);
7308 new_rtx = force_reg (Pmode, addr);
7310 else if (GET_CODE (addr) == CONST)
7312 addr = XEXP (addr, 0);
7314 /* We must match stuff we generate before. Assume the only
7315 unspecs that can get here are ours. Not that we could do
7316 anything with them anyway.... */
7317 if (GET_CODE (addr) == UNSPEC
7318 || (GET_CODE (addr) == PLUS
7319 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7321 gcc_assert (GET_CODE (addr) == PLUS);
7323 if (GET_CODE (addr) == PLUS)
7325 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7327 /* Check first to see if this is a constant offset from a @GOTOFF
7328 symbol reference. */
7329 if (gotoff_operand (op0, Pmode)
7330 && CONST_INT_P (op1))
7334 if (reload_in_progress)
7335 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7336 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7338 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7339 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7340 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7344 emit_move_insn (reg, new_rtx);
7350 if (INTVAL (op1) < -16*1024*1024
7351 || INTVAL (op1) >= 16*1024*1024)
7353 if (!x86_64_immediate_operand (op1, Pmode))
7354 op1 = force_reg (Pmode, op1);
7355 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7361 base = legitimize_pic_address (XEXP (addr, 0), reg);
7362 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7363 base == reg ? NULL_RTX : reg);
7365 if (CONST_INT_P (new_rtx))
7366 new_rtx = plus_constant (base, INTVAL (new_rtx));
7369 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7371 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7372 new_rtx = XEXP (new_rtx, 1);
7374 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7382 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7385 get_thread_pointer (int to_reg)
7389 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7393 reg = gen_reg_rtx (Pmode);
7394 insn = gen_rtx_SET (VOIDmode, reg, tp);
7395 insn = emit_insn (insn);
7400 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7401 false if we expect this to be used for a memory address and true if
7402 we expect to load the address into a register. */
7405 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7407 rtx dest, base, off, pic, tp;
7412 case TLS_MODEL_GLOBAL_DYNAMIC:
7413 dest = gen_reg_rtx (Pmode);
7414 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7416 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7418 rtx rax = gen_rtx_REG (Pmode, 0), insns;
7421 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7422 insns = get_insns ();
7425 CONST_OR_PURE_CALL_P (insns) = 1;
7426 emit_libcall_block (insns, dest, rax, x);
7428 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7429 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7431 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7433 if (TARGET_GNU2_TLS)
7435 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7437 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7441 case TLS_MODEL_LOCAL_DYNAMIC:
7442 base = gen_reg_rtx (Pmode);
7443 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7445 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7447 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
7450 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7451 insns = get_insns ();
7454 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7455 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7456 CONST_OR_PURE_CALL_P (insns) = 1;
7457 emit_libcall_block (insns, base, rax, note);
7459 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7460 emit_insn (gen_tls_local_dynamic_base_64 (base));
7462 emit_insn (gen_tls_local_dynamic_base_32 (base));
7464 if (TARGET_GNU2_TLS)
7466 rtx x = ix86_tls_module_base ();
7468 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7469 gen_rtx_MINUS (Pmode, x, tp));
7472 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7473 off = gen_rtx_CONST (Pmode, off);
7475 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7477 if (TARGET_GNU2_TLS)
7479 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7481 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7486 case TLS_MODEL_INITIAL_EXEC:
7490 type = UNSPEC_GOTNTPOFF;
7494 if (reload_in_progress)
7495 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7496 pic = pic_offset_table_rtx;
7497 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7499 else if (!TARGET_ANY_GNU_TLS)
7501 pic = gen_reg_rtx (Pmode);
7502 emit_insn (gen_set_got (pic));
7503 type = UNSPEC_GOTTPOFF;
7508 type = UNSPEC_INDNTPOFF;
7511 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7512 off = gen_rtx_CONST (Pmode, off);
7514 off = gen_rtx_PLUS (Pmode, pic, off);
7515 off = gen_const_mem (Pmode, off);
7516 set_mem_alias_set (off, ix86_GOT_alias_set ());
7518 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7520 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7521 off = force_reg (Pmode, off);
7522 return gen_rtx_PLUS (Pmode, base, off);
7526 base = get_thread_pointer (true);
7527 dest = gen_reg_rtx (Pmode);
7528 emit_insn (gen_subsi3 (dest, base, off));
7532 case TLS_MODEL_LOCAL_EXEC:
7533 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7534 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7535 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7536 off = gen_rtx_CONST (Pmode, off);
7538 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7540 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7541 return gen_rtx_PLUS (Pmode, base, off);
7545 base = get_thread_pointer (true);
7546 dest = gen_reg_rtx (Pmode);
7547 emit_insn (gen_subsi3 (dest, base, off));
7558 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7561 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
7562 htab_t dllimport_map;
7565 get_dllimport_decl (tree decl)
7567 struct tree_map *h, in;
7571 size_t namelen, prefixlen;
7577 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
7579 in.hash = htab_hash_pointer (decl);
7580 in.base.from = decl;
7581 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
7582 h = (struct tree_map *) *loc;
7586 *loc = h = GGC_NEW (struct tree_map);
7588 h->base.from = decl;
7589 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
7590 DECL_ARTIFICIAL (to) = 1;
7591 DECL_IGNORED_P (to) = 1;
7592 DECL_EXTERNAL (to) = 1;
7593 TREE_READONLY (to) = 1;
7595 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
7596 name = targetm.strip_name_encoding (name);
7597 if (name[0] == FASTCALL_PREFIX)
7603 prefix = "*__imp__";
7605 namelen = strlen (name);
7606 prefixlen = strlen (prefix);
7607 imp_name = (char *) alloca (namelen + prefixlen + 1);
7608 memcpy (imp_name, prefix, prefixlen);
7609 memcpy (imp_name + prefixlen, name, namelen + 1);
7611 name = ggc_alloc_string (imp_name, namelen + prefixlen);
7612 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
7613 SET_SYMBOL_REF_DECL (rtl, to);
7614 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
7616 rtl = gen_const_mem (Pmode, rtl);
7617 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
7619 SET_DECL_RTL (to, rtl);
7624 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
7625 true if we require the result be a register. */
7628 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
7633 gcc_assert (SYMBOL_REF_DECL (symbol));
7634 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
7636 x = DECL_RTL (imp_decl);
7638 x = force_reg (Pmode, x);
7642 /* Try machine-dependent ways of modifying an illegitimate address
7643 to be legitimate. If we find one, return the new, valid address.
7644 This macro is used in only one place: `memory_address' in explow.c.
7646 OLDX is the address as it was before break_out_memory_refs was called.
7647 In some cases it is useful to look at this to decide what needs to be done.
7649 MODE and WIN are passed so that this macro can use
7650 GO_IF_LEGITIMATE_ADDRESS.
7652 It is always safe for this macro to do nothing. It exists to recognize
7653 opportunities to optimize the output.
7655 For the 80386, we handle X+REG by loading X into a register R and
7656 using R+REG. R will go in a general reg and indexing will be used.
7657 However, if REG is a broken-out memory address or multiplication,
7658 nothing needs to be done because REG can certainly go in a general reg.
7660 When -fpic is used, special handling is needed for symbolic references.
7661 See comments by legitimize_pic_address in i386.c for details. */
7664 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
7669 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
7671 return legitimize_tls_address (x, (enum tls_model) log, false);
7672 if (GET_CODE (x) == CONST
7673 && GET_CODE (XEXP (x, 0)) == PLUS
7674 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7675 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
7677 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
7678 (enum tls_model) log, false);
7679 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
7682 if (flag_pic && SYMBOLIC_CONST (x))
7683 return legitimize_pic_address (x, 0);
7685 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
7687 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
7688 return legitimize_dllimport_symbol (x, true);
7689 if (GET_CODE (x) == CONST
7690 && GET_CODE (XEXP (x, 0)) == PLUS
7691 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7692 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
7694 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
7695 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
7699 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
7700 if (GET_CODE (x) == ASHIFT
7701 && CONST_INT_P (XEXP (x, 1))
7702 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
7705 log = INTVAL (XEXP (x, 1));
7706 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
7707 GEN_INT (1 << log));
7710 if (GET_CODE (x) == PLUS)
7712 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
7714 if (GET_CODE (XEXP (x, 0)) == ASHIFT
7715 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7716 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
7719 log = INTVAL (XEXP (XEXP (x, 0), 1));
7720 XEXP (x, 0) = gen_rtx_MULT (Pmode,
7721 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
7722 GEN_INT (1 << log));
7725 if (GET_CODE (XEXP (x, 1)) == ASHIFT
7726 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
7727 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
7730 log = INTVAL (XEXP (XEXP (x, 1), 1));
7731 XEXP (x, 1) = gen_rtx_MULT (Pmode,
7732 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
7733 GEN_INT (1 << log));
7736 /* Put multiply first if it isn't already. */
7737 if (GET_CODE (XEXP (x, 1)) == MULT)
7739 rtx tmp = XEXP (x, 0);
7740 XEXP (x, 0) = XEXP (x, 1);
7745 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
7746 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
7747 created by virtual register instantiation, register elimination, and
7748 similar optimizations. */
7749 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
7752 x = gen_rtx_PLUS (Pmode,
7753 gen_rtx_PLUS (Pmode, XEXP (x, 0),
7754 XEXP (XEXP (x, 1), 0)),
7755 XEXP (XEXP (x, 1), 1));
7759 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
7760 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
7761 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
7762 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
7763 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
7764 && CONSTANT_P (XEXP (x, 1)))
7767 rtx other = NULL_RTX;
7769 if (CONST_INT_P (XEXP (x, 1)))
7771 constant = XEXP (x, 1);
7772 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
7774 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
7776 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
7777 other = XEXP (x, 1);
7785 x = gen_rtx_PLUS (Pmode,
7786 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
7787 XEXP (XEXP (XEXP (x, 0), 1), 0)),
7788 plus_constant (other, INTVAL (constant)));
7792 if (changed && legitimate_address_p (mode, x, FALSE))
7795 if (GET_CODE (XEXP (x, 0)) == MULT)
7798 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
7801 if (GET_CODE (XEXP (x, 1)) == MULT)
7804 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
7808 && REG_P (XEXP (x, 1))
7809 && REG_P (XEXP (x, 0)))
7812 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
7815 x = legitimize_pic_address (x, 0);
7818 if (changed && legitimate_address_p (mode, x, FALSE))
7821 if (REG_P (XEXP (x, 0)))
7823 rtx temp = gen_reg_rtx (Pmode);
7824 rtx val = force_operand (XEXP (x, 1), temp);
7826 emit_move_insn (temp, val);
7832 else if (REG_P (XEXP (x, 1)))
7834 rtx temp = gen_reg_rtx (Pmode);
7835 rtx val = force_operand (XEXP (x, 0), temp);
7837 emit_move_insn (temp, val);
7847 /* Print an integer constant expression in assembler syntax. Addition
7848 and subtraction are the only arithmetic that may appear in these
7849 expressions. FILE is the stdio stream to write to, X is the rtx, and
7850 CODE is the operand print code from the output string. */
7853 output_pic_addr_const (FILE *file, rtx x, int code)
7857 switch (GET_CODE (x))
7860 gcc_assert (flag_pic);
7865 if (! TARGET_MACHO || TARGET_64BIT)
7866 output_addr_const (file, x);
7869 const char *name = XSTR (x, 0);
7871 /* Mark the decl as referenced so that cgraph will
7872 output the function. */
7873 if (SYMBOL_REF_DECL (x))
7874 mark_decl_referenced (SYMBOL_REF_DECL (x));
7877 if (MACHOPIC_INDIRECT
7878 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
7879 name = machopic_indirection_name (x, /*stub_p=*/true);
7881 assemble_name (file, name);
7883 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
7884 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
7885 fputs ("@PLT", file);
7892 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
7893 assemble_name (asm_out_file, buf);
7897 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7901 /* This used to output parentheses around the expression,
7902 but that does not work on the 386 (either ATT or BSD assembler). */
7903 output_pic_addr_const (file, XEXP (x, 0), code);
7907 if (GET_MODE (x) == VOIDmode)
7909 /* We can use %d if the number is <32 bits and positive. */
7910 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
7911 fprintf (file, "0x%lx%08lx",
7912 (unsigned long) CONST_DOUBLE_HIGH (x),
7913 (unsigned long) CONST_DOUBLE_LOW (x));
7915 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
7918 /* We can't handle floating point constants;
7919 PRINT_OPERAND must handle them. */
7920 output_operand_lossage ("floating constant misused");
7924 /* Some assemblers need integer constants to appear first. */
7925 if (CONST_INT_P (XEXP (x, 0)))
7927 output_pic_addr_const (file, XEXP (x, 0), code);
7929 output_pic_addr_const (file, XEXP (x, 1), code);
7933 gcc_assert (CONST_INT_P (XEXP (x, 1)));
7934 output_pic_addr_const (file, XEXP (x, 1), code);
7936 output_pic_addr_const (file, XEXP (x, 0), code);
7942 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
7943 output_pic_addr_const (file, XEXP (x, 0), code);
7945 output_pic_addr_const (file, XEXP (x, 1), code);
7947 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
7951 gcc_assert (XVECLEN (x, 0) == 1);
7952 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
7953 switch (XINT (x, 1))
7956 fputs ("@GOT", file);
7959 fputs ("@GOTOFF", file);
7962 fputs ("@PLTOFF", file);
7964 case UNSPEC_GOTPCREL:
7965 fputs ("@GOTPCREL(%rip)", file);
7967 case UNSPEC_GOTTPOFF:
7968 /* FIXME: This might be @TPOFF in Sun ld too. */
7969 fputs ("@GOTTPOFF", file);
7972 fputs ("@TPOFF", file);
7976 fputs ("@TPOFF", file);
7978 fputs ("@NTPOFF", file);
7981 fputs ("@DTPOFF", file);
7983 case UNSPEC_GOTNTPOFF:
7985 fputs ("@GOTTPOFF(%rip)", file);
7987 fputs ("@GOTNTPOFF", file);
7989 case UNSPEC_INDNTPOFF:
7990 fputs ("@INDNTPOFF", file);
7993 output_operand_lossage ("invalid UNSPEC as operand");
7999 output_operand_lossage ("invalid expression as operand");
8003 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8004 We need to emit DTP-relative relocations. */
8006 static void ATTRIBUTE_UNUSED
8007 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8009 fputs (ASM_LONG, file);
8010 output_addr_const (file, x);
8011 fputs ("@DTPOFF", file);
8017 fputs (", 0", file);
8024 /* In the name of slightly smaller debug output, and to cater to
8025 general assembler lossage, recognize PIC+GOTOFF and turn it back
8026 into a direct symbol reference.
8028 On Darwin, this is necessary to avoid a crash, because Darwin
8029 has a different PIC label for each routine but the DWARF debugging
8030 information is not associated with any particular routine, so it's
8031 necessary to remove references to the PIC label from RTL stored by
8032 the DWARF output code. */
8035 ix86_delegitimize_address (rtx orig_x)
8038 /* reg_addend is NULL or a multiple of some register. */
8039 rtx reg_addend = NULL_RTX;
8040 /* const_addend is NULL or a const_int. */
8041 rtx const_addend = NULL_RTX;
8042 /* This is the result, or NULL. */
8043 rtx result = NULL_RTX;
8050 if (GET_CODE (x) != CONST
8051 || GET_CODE (XEXP (x, 0)) != UNSPEC
8052 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8055 return XVECEXP (XEXP (x, 0), 0, 0);
8058 if (GET_CODE (x) != PLUS
8059 || GET_CODE (XEXP (x, 1)) != CONST)
8062 if (REG_P (XEXP (x, 0))
8063 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8064 /* %ebx + GOT/GOTOFF */
8066 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8068 /* %ebx + %reg * scale + GOT/GOTOFF */
8069 reg_addend = XEXP (x, 0);
8070 if (REG_P (XEXP (reg_addend, 0))
8071 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8072 reg_addend = XEXP (reg_addend, 1);
8073 else if (REG_P (XEXP (reg_addend, 1))
8074 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8075 reg_addend = XEXP (reg_addend, 0);
8078 if (!REG_P (reg_addend)
8079 && GET_CODE (reg_addend) != MULT
8080 && GET_CODE (reg_addend) != ASHIFT)
8086 x = XEXP (XEXP (x, 1), 0);
8087 if (GET_CODE (x) == PLUS
8088 && CONST_INT_P (XEXP (x, 1)))
8090 const_addend = XEXP (x, 1);
8094 if (GET_CODE (x) == UNSPEC
8095 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8096 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8097 result = XVECEXP (x, 0, 0);
8099 if (TARGET_MACHO && darwin_local_data_pic (x)
8101 result = XEXP (x, 0);
8107 result = gen_rtx_PLUS (Pmode, result, const_addend);
8109 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8113 /* If X is a machine specific address (i.e. a symbol or label being
8114 referenced as a displacement from the GOT implemented using an
8115 UNSPEC), then return the base term. Otherwise return X. */
8118 ix86_find_base_term (rtx x)
8124 if (GET_CODE (x) != CONST)
8127 if (GET_CODE (term) == PLUS
8128 && (CONST_INT_P (XEXP (term, 1))
8129 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8130 term = XEXP (term, 0);
8131 if (GET_CODE (term) != UNSPEC
8132 || XINT (term, 1) != UNSPEC_GOTPCREL)
8135 term = XVECEXP (term, 0, 0);
8137 if (GET_CODE (term) != SYMBOL_REF
8138 && GET_CODE (term) != LABEL_REF)
8144 term = ix86_delegitimize_address (x);
8146 if (GET_CODE (term) != SYMBOL_REF
8147 && GET_CODE (term) != LABEL_REF)
8154 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8159 if (mode == CCFPmode || mode == CCFPUmode)
8161 enum rtx_code second_code, bypass_code;
8162 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8163 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8164 code = ix86_fp_compare_code_to_integer (code);
8168 code = reverse_condition (code);
8219 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8223 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8224 Those same assemblers have the same but opposite lossage on cmov. */
8225 gcc_assert (mode == CCmode);
8226 suffix = fp ? "nbe" : "a";
8246 gcc_assert (mode == CCmode);
8268 gcc_assert (mode == CCmode);
8269 suffix = fp ? "nb" : "ae";
8272 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8276 gcc_assert (mode == CCmode);
8280 suffix = fp ? "u" : "p";
8283 suffix = fp ? "nu" : "np";
8288 fputs (suffix, file);
8291 /* Print the name of register X to FILE based on its machine mode and number.
8292 If CODE is 'w', pretend the mode is HImode.
8293 If CODE is 'b', pretend the mode is QImode.
8294 If CODE is 'k', pretend the mode is SImode.
8295 If CODE is 'q', pretend the mode is DImode.
8296 If CODE is 'h', pretend the reg is the 'high' byte register.
8297 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8300 print_reg (rtx x, int code, FILE *file)
8302 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
8303 && REGNO (x) != FRAME_POINTER_REGNUM
8304 && REGNO (x) != FLAGS_REG
8305 && REGNO (x) != FPSR_REG
8306 && REGNO (x) != FPCR_REG);
8308 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
8311 if (code == 'w' || MMX_REG_P (x))
8313 else if (code == 'b')
8315 else if (code == 'k')
8317 else if (code == 'q')
8319 else if (code == 'y')
8321 else if (code == 'h')
8324 code = GET_MODE_SIZE (GET_MODE (x));
8326 /* Irritatingly, AMD extended registers use different naming convention
8327 from the normal registers. */
8328 if (REX_INT_REG_P (x))
8330 gcc_assert (TARGET_64BIT);
8334 error ("extended registers have no high halves");
8337 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8340 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8343 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8346 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8349 error ("unsupported operand size for extended register");
8357 if (STACK_TOP_P (x))
8359 fputs ("st(0)", file);
8366 if (! ANY_FP_REG_P (x))
8367 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8372 fputs (hi_reg_name[REGNO (x)], file);
8375 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8377 fputs (qi_reg_name[REGNO (x)], file);
8380 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8382 fputs (qi_high_reg_name[REGNO (x)], file);
8389 /* Locate some local-dynamic symbol still in use by this function
8390 so that we can print its name in some tls_local_dynamic_base
8394 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8398 if (GET_CODE (x) == SYMBOL_REF
8399 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8401 cfun->machine->some_ld_name = XSTR (x, 0);
8409 get_some_local_dynamic_name (void)
8413 if (cfun->machine->some_ld_name)
8414 return cfun->machine->some_ld_name;
8416 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8418 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8419 return cfun->machine->some_ld_name;
8425 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8426 C -- print opcode suffix for set/cmov insn.
8427 c -- like C, but print reversed condition
8428 F,f -- likewise, but for floating-point.
8429 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8431 R -- print the prefix for register names.
8432 z -- print the opcode suffix for the size of the current operand.
8433 * -- print a star (in certain assembler syntax)
8434 A -- print an absolute memory reference.
8435 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8436 s -- print a shift double count, followed by the assemblers argument
8438 b -- print the QImode name of the register for the indicated operand.
8439 %b0 would print %al if operands[0] is reg 0.
8440 w -- likewise, print the HImode name of the register.
8441 k -- likewise, print the SImode name of the register.
8442 q -- likewise, print the DImode name of the register.
8443 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8444 y -- print "st(0)" instead of "st" as a register.
8445 D -- print condition for SSE cmp instruction.
8446 P -- if PIC, print an @PLT suffix.
8447 X -- don't print any sort of PIC '@' suffix for a symbol.
8448 & -- print some in-use local-dynamic symbol name.
8449 H -- print a memory address offset by 8; used for sse high-parts
8453 print_operand (FILE *file, rtx x, int code)
8460 if (ASSEMBLER_DIALECT == ASM_ATT)
8465 assemble_name (file, get_some_local_dynamic_name ());
8469 switch (ASSEMBLER_DIALECT)
8476 /* Intel syntax. For absolute addresses, registers should not
8477 be surrounded by braces. */
8481 PRINT_OPERAND (file, x, 0);
8491 PRINT_OPERAND (file, x, 0);
8496 if (ASSEMBLER_DIALECT == ASM_ATT)
8501 if (ASSEMBLER_DIALECT == ASM_ATT)
8506 if (ASSEMBLER_DIALECT == ASM_ATT)
8511 if (ASSEMBLER_DIALECT == ASM_ATT)
8516 if (ASSEMBLER_DIALECT == ASM_ATT)
8521 if (ASSEMBLER_DIALECT == ASM_ATT)
8526 /* 387 opcodes don't get size suffixes if the operands are
8528 if (STACK_REG_P (x))
8531 /* Likewise if using Intel opcodes. */
8532 if (ASSEMBLER_DIALECT == ASM_INTEL)
8535 /* This is the size of op from size of operand. */
8536 switch (GET_MODE_SIZE (GET_MODE (x)))
8545 #ifdef HAVE_GAS_FILDS_FISTS
8555 if (GET_MODE (x) == SFmode)
8570 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
8572 #ifdef GAS_MNEMONICS
8598 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
8600 PRINT_OPERAND (file, x, 0);
8606 /* Little bit of braindamage here. The SSE compare instructions
8607 does use completely different names for the comparisons that the
8608 fp conditional moves. */
8609 switch (GET_CODE (x))
8624 fputs ("unord", file);
8628 fputs ("neq", file);
8632 fputs ("nlt", file);
8636 fputs ("nle", file);
8639 fputs ("ord", file);
8646 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8647 if (ASSEMBLER_DIALECT == ASM_ATT)
8649 switch (GET_MODE (x))
8651 case HImode: putc ('w', file); break;
8653 case SFmode: putc ('l', file); break;
8655 case DFmode: putc ('q', file); break;
8656 default: gcc_unreachable ();
8663 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
8666 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8667 if (ASSEMBLER_DIALECT == ASM_ATT)
8670 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
8673 /* Like above, but reverse condition */
8675 /* Check to see if argument to %c is really a constant
8676 and not a condition code which needs to be reversed. */
8677 if (!COMPARISON_P (x))
8679 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
8682 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
8685 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8686 if (ASSEMBLER_DIALECT == ASM_ATT)
8689 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
8693 /* It doesn't actually matter what mode we use here, as we're
8694 only going to use this for printing. */
8695 x = adjust_address_nv (x, DImode, 8);
8702 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
8705 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
8708 int pred_val = INTVAL (XEXP (x, 0));
8710 if (pred_val < REG_BR_PROB_BASE * 45 / 100
8711 || pred_val > REG_BR_PROB_BASE * 55 / 100)
8713 int taken = pred_val > REG_BR_PROB_BASE / 2;
8714 int cputaken = final_forward_branch_p (current_output_insn) == 0;
8716 /* Emit hints only in the case default branch prediction
8717 heuristics would fail. */
8718 if (taken != cputaken)
8720 /* We use 3e (DS) prefix for taken branches and
8721 2e (CS) prefix for not taken branches. */
8723 fputs ("ds ; ", file);
8725 fputs ("cs ; ", file);
8732 output_operand_lossage ("invalid operand code '%c'", code);
8737 print_reg (x, code, file);
8741 /* No `byte ptr' prefix for call instructions. */
8742 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
8745 switch (GET_MODE_SIZE (GET_MODE (x)))
8747 case 1: size = "BYTE"; break;
8748 case 2: size = "WORD"; break;
8749 case 4: size = "DWORD"; break;
8750 case 8: size = "QWORD"; break;
8751 case 12: size = "XWORD"; break;
8752 case 16: size = "XMMWORD"; break;
8757 /* Check for explicit size override (codes 'b', 'w' and 'k') */
8760 else if (code == 'w')
8762 else if (code == 'k')
8766 fputs (" PTR ", file);
8770 /* Avoid (%rip) for call operands. */
8771 if (CONSTANT_ADDRESS_P (x) && code == 'P'
8772 && !CONST_INT_P (x))
8773 output_addr_const (file, x);
8774 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
8775 output_operand_lossage ("invalid constraints for operand");
8780 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
8785 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8786 REAL_VALUE_TO_TARGET_SINGLE (r, l);
8788 if (ASSEMBLER_DIALECT == ASM_ATT)
8790 fprintf (file, "0x%08lx", l);
8793 /* These float cases don't actually occur as immediate operands. */
8794 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
8798 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
8799 fprintf (file, "%s", dstr);
8802 else if (GET_CODE (x) == CONST_DOUBLE
8803 && GET_MODE (x) == XFmode)
8807 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
8808 fprintf (file, "%s", dstr);
8813 /* We have patterns that allow zero sets of memory, for instance.
8814 In 64-bit mode, we should probably support all 8-byte vectors,
8815 since we can in fact encode that into an immediate. */
8816 if (GET_CODE (x) == CONST_VECTOR)
8818 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
8824 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
8826 if (ASSEMBLER_DIALECT == ASM_ATT)
8829 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
8830 || GET_CODE (x) == LABEL_REF)
8832 if (ASSEMBLER_DIALECT == ASM_ATT)
8835 fputs ("OFFSET FLAT:", file);
8838 if (CONST_INT_P (x))
8839 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8841 output_pic_addr_const (file, x, code);
8843 output_addr_const (file, x);
8847 /* Print a memory operand whose address is ADDR. */
8850 print_operand_address (FILE *file, rtx addr)
8852 struct ix86_address parts;
8853 rtx base, index, disp;
8855 int ok = ix86_decompose_address (addr, &parts);
8860 index = parts.index;
8862 scale = parts.scale;
8870 if (USER_LABEL_PREFIX[0] == 0)
8872 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
8878 if (!base && !index)
8880 /* Displacement only requires special attention. */
8882 if (CONST_INT_P (disp))
8884 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
8886 if (USER_LABEL_PREFIX[0] == 0)
8888 fputs ("ds:", file);
8890 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
8893 output_pic_addr_const (file, disp, 0);
8895 output_addr_const (file, disp);
8897 /* Use one byte shorter RIP relative addressing for 64bit mode. */
8900 if (GET_CODE (disp) == CONST
8901 && GET_CODE (XEXP (disp, 0)) == PLUS
8902 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
8903 disp = XEXP (XEXP (disp, 0), 0);
8904 if (GET_CODE (disp) == LABEL_REF
8905 || (GET_CODE (disp) == SYMBOL_REF
8906 && SYMBOL_REF_TLS_MODEL (disp) == 0))
8907 fputs ("(%rip)", file);
8912 if (ASSEMBLER_DIALECT == ASM_ATT)
8917 output_pic_addr_const (file, disp, 0);
8918 else if (GET_CODE (disp) == LABEL_REF)
8919 output_asm_label (disp);
8921 output_addr_const (file, disp);
8926 print_reg (base, 0, file);
8930 print_reg (index, 0, file);
8932 fprintf (file, ",%d", scale);
8938 rtx offset = NULL_RTX;
8942 /* Pull out the offset of a symbol; print any symbol itself. */
8943 if (GET_CODE (disp) == CONST
8944 && GET_CODE (XEXP (disp, 0)) == PLUS
8945 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
8947 offset = XEXP (XEXP (disp, 0), 1);
8948 disp = gen_rtx_CONST (VOIDmode,
8949 XEXP (XEXP (disp, 0), 0));
8953 output_pic_addr_const (file, disp, 0);
8954 else if (GET_CODE (disp) == LABEL_REF)
8955 output_asm_label (disp);
8956 else if (CONST_INT_P (disp))
8959 output_addr_const (file, disp);
8965 print_reg (base, 0, file);
8968 if (INTVAL (offset) >= 0)
8970 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8974 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8981 print_reg (index, 0, file);
8983 fprintf (file, "*%d", scale);
8991 output_addr_const_extra (FILE *file, rtx x)
8995 if (GET_CODE (x) != UNSPEC)
8998 op = XVECEXP (x, 0, 0);
8999 switch (XINT (x, 1))
9001 case UNSPEC_GOTTPOFF:
9002 output_addr_const (file, op);
9003 /* FIXME: This might be @TPOFF in Sun ld. */
9004 fputs ("@GOTTPOFF", file);
9007 output_addr_const (file, op);
9008 fputs ("@TPOFF", file);
9011 output_addr_const (file, op);
9013 fputs ("@TPOFF", file);
9015 fputs ("@NTPOFF", file);
9018 output_addr_const (file, op);
9019 fputs ("@DTPOFF", file);
9021 case UNSPEC_GOTNTPOFF:
9022 output_addr_const (file, op);
9024 fputs ("@GOTTPOFF(%rip)", file);
9026 fputs ("@GOTNTPOFF", file);
9028 case UNSPEC_INDNTPOFF:
9029 output_addr_const (file, op);
9030 fputs ("@INDNTPOFF", file);
9040 /* Split one or more DImode RTL references into pairs of SImode
9041 references. The RTL can be REG, offsettable MEM, integer constant, or
9042 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9043 split and "num" is its length. lo_half and hi_half are output arrays
9044 that parallel "operands". */
9047 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9051 rtx op = operands[num];
9053 /* simplify_subreg refuse to split volatile memory addresses,
9054 but we still have to handle it. */
9057 lo_half[num] = adjust_address (op, SImode, 0);
9058 hi_half[num] = adjust_address (op, SImode, 4);
9062 lo_half[num] = simplify_gen_subreg (SImode, op,
9063 GET_MODE (op) == VOIDmode
9064 ? DImode : GET_MODE (op), 0);
9065 hi_half[num] = simplify_gen_subreg (SImode, op,
9066 GET_MODE (op) == VOIDmode
9067 ? DImode : GET_MODE (op), 4);
9071 /* Split one or more TImode RTL references into pairs of DImode
9072 references. The RTL can be REG, offsettable MEM, integer constant, or
9073 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9074 split and "num" is its length. lo_half and hi_half are output arrays
9075 that parallel "operands". */
9078 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9082 rtx op = operands[num];
9084 /* simplify_subreg refuse to split volatile memory addresses, but we
9085 still have to handle it. */
9088 lo_half[num] = adjust_address (op, DImode, 0);
9089 hi_half[num] = adjust_address (op, DImode, 8);
9093 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9094 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9099 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9100 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9101 is the expression of the binary operation. The output may either be
9102 emitted here, or returned to the caller, like all output_* functions.
9104 There is no guarantee that the operands are the same mode, as they
9105 might be within FLOAT or FLOAT_EXTEND expressions. */
9107 #ifndef SYSV386_COMPAT
9108 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9109 wants to fix the assemblers because that causes incompatibility
9110 with gcc. No-one wants to fix gcc because that causes
9111 incompatibility with assemblers... You can use the option of
9112 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9113 #define SYSV386_COMPAT 1
9117 output_387_binary_op (rtx insn, rtx *operands)
9119 static char buf[30];
9122 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9124 #ifdef ENABLE_CHECKING
9125 /* Even if we do not want to check the inputs, this documents input
9126 constraints. Which helps in understanding the following code. */
9127 if (STACK_REG_P (operands[0])
9128 && ((REG_P (operands[1])
9129 && REGNO (operands[0]) == REGNO (operands[1])
9130 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9131 || (REG_P (operands[2])
9132 && REGNO (operands[0]) == REGNO (operands[2])
9133 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9134 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9137 gcc_assert (is_sse);
9140 switch (GET_CODE (operands[3]))
9143 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9144 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9152 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9153 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9161 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9162 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9170 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9171 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9185 if (GET_MODE (operands[0]) == SFmode)
9186 strcat (buf, "ss\t{%2, %0|%0, %2}");
9188 strcat (buf, "sd\t{%2, %0|%0, %2}");
9193 switch (GET_CODE (operands[3]))
9197 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9199 rtx temp = operands[2];
9200 operands[2] = operands[1];
9204 /* know operands[0] == operands[1]. */
9206 if (MEM_P (operands[2]))
9212 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9214 if (STACK_TOP_P (operands[0]))
9215 /* How is it that we are storing to a dead operand[2]?
9216 Well, presumably operands[1] is dead too. We can't
9217 store the result to st(0) as st(0) gets popped on this
9218 instruction. Instead store to operands[2] (which I
9219 think has to be st(1)). st(1) will be popped later.
9220 gcc <= 2.8.1 didn't have this check and generated
9221 assembly code that the Unixware assembler rejected. */
9222 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9224 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9228 if (STACK_TOP_P (operands[0]))
9229 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9231 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9236 if (MEM_P (operands[1]))
9242 if (MEM_P (operands[2]))
9248 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9251 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9252 derived assemblers, confusingly reverse the direction of
9253 the operation for fsub{r} and fdiv{r} when the
9254 destination register is not st(0). The Intel assembler
9255 doesn't have this brain damage. Read !SYSV386_COMPAT to
9256 figure out what the hardware really does. */
9257 if (STACK_TOP_P (operands[0]))
9258 p = "{p\t%0, %2|rp\t%2, %0}";
9260 p = "{rp\t%2, %0|p\t%0, %2}";
9262 if (STACK_TOP_P (operands[0]))
9263 /* As above for fmul/fadd, we can't store to st(0). */
9264 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9266 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9271 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9274 if (STACK_TOP_P (operands[0]))
9275 p = "{rp\t%0, %1|p\t%1, %0}";
9277 p = "{p\t%1, %0|rp\t%0, %1}";
9279 if (STACK_TOP_P (operands[0]))
9280 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9282 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9287 if (STACK_TOP_P (operands[0]))
9289 if (STACK_TOP_P (operands[1]))
9290 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9292 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9295 else if (STACK_TOP_P (operands[1]))
9298 p = "{\t%1, %0|r\t%0, %1}";
9300 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9306 p = "{r\t%2, %0|\t%0, %2}";
9308 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9321 /* Return needed mode for entity in optimize_mode_switching pass. */
9324 ix86_mode_needed (int entity, rtx insn)
9326 enum attr_i387_cw mode;
9328 /* The mode UNINITIALIZED is used to store control word after a
9329 function call or ASM pattern. The mode ANY specify that function
9330 has no requirements on the control word and make no changes in the
9331 bits we are interested in. */
9334 || (NONJUMP_INSN_P (insn)
9335 && (asm_noperands (PATTERN (insn)) >= 0
9336 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9337 return I387_CW_UNINITIALIZED;
9339 if (recog_memoized (insn) < 0)
9342 mode = get_attr_i387_cw (insn);
9347 if (mode == I387_CW_TRUNC)
9352 if (mode == I387_CW_FLOOR)
9357 if (mode == I387_CW_CEIL)
9362 if (mode == I387_CW_MASK_PM)
9373 /* Output code to initialize control word copies used by trunc?f?i and
9374 rounding patterns. CURRENT_MODE is set to current control word,
9375 while NEW_MODE is set to new control word. */
9378 emit_i387_cw_initialization (int mode)
9380 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9383 enum ix86_stack_slot slot;
9385 rtx reg = gen_reg_rtx (HImode);
9387 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9388 emit_move_insn (reg, copy_rtx (stored_mode));
9390 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9395 /* round toward zero (truncate) */
9396 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9397 slot = SLOT_CW_TRUNC;
9401 /* round down toward -oo */
9402 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9403 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9404 slot = SLOT_CW_FLOOR;
9408 /* round up toward +oo */
9409 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9410 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9411 slot = SLOT_CW_CEIL;
9414 case I387_CW_MASK_PM:
9415 /* mask precision exception for nearbyint() */
9416 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9417 slot = SLOT_CW_MASK_PM;
9429 /* round toward zero (truncate) */
9430 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9431 slot = SLOT_CW_TRUNC;
9435 /* round down toward -oo */
9436 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9437 slot = SLOT_CW_FLOOR;
9441 /* round up toward +oo */
9442 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9443 slot = SLOT_CW_CEIL;
9446 case I387_CW_MASK_PM:
9447 /* mask precision exception for nearbyint() */
9448 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9449 slot = SLOT_CW_MASK_PM;
9457 gcc_assert (slot < MAX_386_STACK_LOCALS);
9459 new_mode = assign_386_stack_local (HImode, slot);
9460 emit_move_insn (new_mode, reg);
9463 /* Output code for INSN to convert a float to a signed int. OPERANDS
9464 are the insn operands. The output may be [HSD]Imode and the input
9465 operand may be [SDX]Fmode. */
9468 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
9470 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9471 int dimode_p = GET_MODE (operands[0]) == DImode;
9472 int round_mode = get_attr_i387_cw (insn);
9474 /* Jump through a hoop or two for DImode, since the hardware has no
9475 non-popping instruction. We used to do this a different way, but
9476 that was somewhat fragile and broke with post-reload splitters. */
9477 if ((dimode_p || fisttp) && !stack_top_dies)
9478 output_asm_insn ("fld\t%y1", operands);
9480 gcc_assert (STACK_TOP_P (operands[1]));
9481 gcc_assert (MEM_P (operands[0]));
9482 gcc_assert (GET_MODE (operands[1]) != TFmode);
9485 output_asm_insn ("fisttp%z0\t%0", operands);
9488 if (round_mode != I387_CW_ANY)
9489 output_asm_insn ("fldcw\t%3", operands);
9490 if (stack_top_dies || dimode_p)
9491 output_asm_insn ("fistp%z0\t%0", operands);
9493 output_asm_insn ("fist%z0\t%0", operands);
9494 if (round_mode != I387_CW_ANY)
9495 output_asm_insn ("fldcw\t%2", operands);
9501 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9502 have the values zero or one, indicates the ffreep insn's operand
9503 from the OPERANDS array. */
9506 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
9508 if (TARGET_USE_FFREEP)
9509 #if HAVE_AS_IX86_FFREEP
9510 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
9513 static char retval[] = ".word\t0xc_df";
9514 int regno = REGNO (operands[opno]);
9516 gcc_assert (FP_REGNO_P (regno));
9518 retval[9] = '0' + (regno - FIRST_STACK_REG);
9523 return opno ? "fstp\t%y1" : "fstp\t%y0";
9527 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9528 should be used. UNORDERED_P is true when fucom should be used. */
9531 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
9534 rtx cmp_op0, cmp_op1;
9535 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
9539 cmp_op0 = operands[0];
9540 cmp_op1 = operands[1];
9544 cmp_op0 = operands[1];
9545 cmp_op1 = operands[2];
9550 if (GET_MODE (operands[0]) == SFmode)
9552 return "ucomiss\t{%1, %0|%0, %1}";
9554 return "comiss\t{%1, %0|%0, %1}";
9557 return "ucomisd\t{%1, %0|%0, %1}";
9559 return "comisd\t{%1, %0|%0, %1}";
9562 gcc_assert (STACK_TOP_P (cmp_op0));
9564 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9566 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
9570 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
9571 return output_387_ffreep (operands, 1);
9574 return "ftst\n\tfnstsw\t%0";
9577 if (STACK_REG_P (cmp_op1)
9579 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
9580 && REGNO (cmp_op1) != FIRST_STACK_REG)
9582 /* If both the top of the 387 stack dies, and the other operand
9583 is also a stack register that dies, then this must be a
9584 `fcompp' float compare */
9588 /* There is no double popping fcomi variant. Fortunately,
9589 eflags is immune from the fstp's cc clobbering. */
9591 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
9593 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
9594 return output_387_ffreep (operands, 0);
9599 return "fucompp\n\tfnstsw\t%0";
9601 return "fcompp\n\tfnstsw\t%0";
9606 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
9608 static const char * const alt[16] =
9610 "fcom%z2\t%y2\n\tfnstsw\t%0",
9611 "fcomp%z2\t%y2\n\tfnstsw\t%0",
9612 "fucom%z2\t%y2\n\tfnstsw\t%0",
9613 "fucomp%z2\t%y2\n\tfnstsw\t%0",
9615 "ficom%z2\t%y2\n\tfnstsw\t%0",
9616 "ficomp%z2\t%y2\n\tfnstsw\t%0",
9620 "fcomi\t{%y1, %0|%0, %y1}",
9621 "fcomip\t{%y1, %0|%0, %y1}",
9622 "fucomi\t{%y1, %0|%0, %y1}",
9623 "fucomip\t{%y1, %0|%0, %y1}",
9634 mask = eflags_p << 3;
9635 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
9636 mask |= unordered_p << 1;
9637 mask |= stack_top_dies;
9639 gcc_assert (mask < 16);
9648 ix86_output_addr_vec_elt (FILE *file, int value)
9650 const char *directive = ASM_LONG;
9654 directive = ASM_QUAD;
9656 gcc_assert (!TARGET_64BIT);
9659 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
9663 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
9665 const char *directive = ASM_LONG;
9668 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
9669 directive = ASM_QUAD;
9671 gcc_assert (!TARGET_64BIT);
9673 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
9674 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
9675 fprintf (file, "%s%s%d-%s%d\n",
9676 directive, LPREFIX, value, LPREFIX, rel);
9677 else if (HAVE_AS_GOTOFF_IN_DATA)
9678 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
9680 else if (TARGET_MACHO)
9682 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
9683 machopic_output_function_base_name (file);
9684 fprintf(file, "\n");
9688 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
9689 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
9692 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
9696 ix86_expand_clear (rtx dest)
9700 /* We play register width games, which are only valid after reload. */
9701 gcc_assert (reload_completed);
9703 /* Avoid HImode and its attendant prefix byte. */
9704 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
9705 dest = gen_rtx_REG (SImode, REGNO (dest));
9706 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
9708 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
9709 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
9711 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
9712 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
9718 /* X is an unchanging MEM. If it is a constant pool reference, return
9719 the constant pool rtx, else NULL. */
9722 maybe_get_pool_constant (rtx x)
9724 x = ix86_delegitimize_address (XEXP (x, 0));
9726 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
9727 return get_pool_constant (x);
9733 ix86_expand_move (enum machine_mode mode, rtx operands[])
9735 int strict = (reload_in_progress || reload_completed);
9737 enum tls_model model;
9742 if (GET_CODE (op1) == SYMBOL_REF)
9744 model = SYMBOL_REF_TLS_MODEL (op1);
9747 op1 = legitimize_tls_address (op1, model, true);
9748 op1 = force_operand (op1, op0);
9752 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9753 && SYMBOL_REF_DLLIMPORT_P (op1))
9754 op1 = legitimize_dllimport_symbol (op1, false);
9756 else if (GET_CODE (op1) == CONST
9757 && GET_CODE (XEXP (op1, 0)) == PLUS
9758 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
9760 rtx addend = XEXP (XEXP (op1, 0), 1);
9761 rtx symbol = XEXP (XEXP (op1, 0), 0);
9764 model = SYMBOL_REF_TLS_MODEL (symbol);
9766 tmp = legitimize_tls_address (symbol, model, true);
9767 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9768 && SYMBOL_REF_DLLIMPORT_P (symbol))
9769 tmp = legitimize_dllimport_symbol (symbol, true);
9773 tmp = force_operand (tmp, NULL);
9774 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
9775 op0, 1, OPTAB_DIRECT);
9781 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
9783 if (TARGET_MACHO && !TARGET_64BIT)
9788 rtx temp = ((reload_in_progress
9789 || ((op0 && REG_P (op0))
9791 ? op0 : gen_reg_rtx (Pmode));
9792 op1 = machopic_indirect_data_reference (op1, temp);
9793 op1 = machopic_legitimize_pic_address (op1, mode,
9794 temp == op1 ? 0 : temp);
9796 else if (MACHOPIC_INDIRECT)
9797 op1 = machopic_indirect_data_reference (op1, 0);
9805 op1 = force_reg (Pmode, op1);
9806 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
9808 rtx reg = no_new_pseudos ? op0 : NULL_RTX;
9809 op1 = legitimize_pic_address (op1, reg);
9818 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
9819 || !push_operand (op0, mode))
9821 op1 = force_reg (mode, op1);
9823 if (push_operand (op0, mode)
9824 && ! general_no_elim_operand (op1, mode))
9825 op1 = copy_to_mode_reg (mode, op1);
9827 /* Force large constants in 64bit compilation into register
9828 to get them CSEed. */
9829 if (TARGET_64BIT && mode == DImode
9830 && immediate_operand (op1, mode)
9831 && !x86_64_zext_immediate_operand (op1, VOIDmode)
9832 && !register_operand (op0, mode)
9833 && optimize && !reload_completed && !reload_in_progress)
9834 op1 = copy_to_mode_reg (mode, op1);
9836 if (FLOAT_MODE_P (mode))
9838 /* If we are loading a floating point constant to a register,
9839 force the value to memory now, since we'll get better code
9840 out the back end. */
9844 else if (GET_CODE (op1) == CONST_DOUBLE)
9846 op1 = validize_mem (force_const_mem (mode, op1));
9847 if (!register_operand (op0, mode))
9849 rtx temp = gen_reg_rtx (mode);
9850 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
9851 emit_move_insn (op0, temp);
9858 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
9862 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
9864 rtx op0 = operands[0], op1 = operands[1];
9865 unsigned int align = GET_MODE_ALIGNMENT (mode);
9867 /* Force constants other than zero into memory. We do not know how
9868 the instructions used to build constants modify the upper 64 bits
9869 of the register, once we have that information we may be able
9870 to handle some of them more efficiently. */
9871 if ((reload_in_progress | reload_completed) == 0
9872 && register_operand (op0, mode)
9873 && (CONSTANT_P (op1)
9874 || (GET_CODE (op1) == SUBREG
9875 && CONSTANT_P (SUBREG_REG (op1))))
9876 && standard_sse_constant_p (op1) <= 0)
9877 op1 = validize_mem (force_const_mem (mode, op1));
9879 /* TDmode values are passed as TImode on the stack. Timode values
9880 are moved via xmm registers, and moving them to stack can result in
9881 unaligned memory access. Use ix86_expand_vector_move_misalign()
9882 if memory operand is not aligned correctly. */
9884 && (mode == TImode) && !TARGET_64BIT
9885 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
9886 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
9890 /* ix86_expand_vector_move_misalign() does not like constants ... */
9891 if (CONSTANT_P (op1)
9892 || (GET_CODE (op1) == SUBREG
9893 && CONSTANT_P (SUBREG_REG (op1))))
9894 op1 = validize_mem (force_const_mem (mode, op1));
9896 /* ... nor both arguments in memory. */
9897 if (!register_operand (op0, mode)
9898 && !register_operand (op1, mode))
9899 op1 = force_reg (mode, op1);
9901 tmp[0] = op0; tmp[1] = op1;
9902 ix86_expand_vector_move_misalign (mode, tmp);
9906 /* Make operand1 a register if it isn't already. */
9908 && !register_operand (op0, mode)
9909 && !register_operand (op1, mode))
9911 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
9915 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
9918 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
9919 straight to ix86_expand_vector_move. */
9920 /* Code generation for scalar reg-reg moves of single and double precision data:
9921 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
9925 if (x86_sse_partial_reg_dependency == true)
9930 Code generation for scalar loads of double precision data:
9931 if (x86_sse_split_regs == true)
9932 movlpd mem, reg (gas syntax)
9936 Code generation for unaligned packed loads of single precision data
9937 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
9938 if (x86_sse_unaligned_move_optimal)
9941 if (x86_sse_partial_reg_dependency == true)
9953 Code generation for unaligned packed loads of double precision data
9954 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
9955 if (x86_sse_unaligned_move_optimal)
9958 if (x86_sse_split_regs == true)
9971 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
9980 /* If we're optimizing for size, movups is the smallest. */
9983 op0 = gen_lowpart (V4SFmode, op0);
9984 op1 = gen_lowpart (V4SFmode, op1);
9985 emit_insn (gen_sse_movups (op0, op1));
9989 /* ??? If we have typed data, then it would appear that using
9990 movdqu is the only way to get unaligned data loaded with
9992 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
9994 op0 = gen_lowpart (V16QImode, op0);
9995 op1 = gen_lowpart (V16QImode, op1);
9996 emit_insn (gen_sse2_movdqu (op0, op1));
10000 if (TARGET_SSE2 && mode == V2DFmode)
10004 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10006 op0 = gen_lowpart (V2DFmode, op0);
10007 op1 = gen_lowpart (V2DFmode, op1);
10008 emit_insn (gen_sse2_movupd (op0, op1));
10012 /* When SSE registers are split into halves, we can avoid
10013 writing to the top half twice. */
10014 if (TARGET_SSE_SPLIT_REGS)
10016 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10021 /* ??? Not sure about the best option for the Intel chips.
10022 The following would seem to satisfy; the register is
10023 entirely cleared, breaking the dependency chain. We
10024 then store to the upper half, with a dependency depth
10025 of one. A rumor has it that Intel recommends two movsd
10026 followed by an unpacklpd, but this is unconfirmed. And
10027 given that the dependency depth of the unpacklpd would
10028 still be one, I'm not sure why this would be better. */
10029 zero = CONST0_RTX (V2DFmode);
10032 m = adjust_address (op1, DFmode, 0);
10033 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10034 m = adjust_address (op1, DFmode, 8);
10035 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10039 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10041 op0 = gen_lowpart (V4SFmode, op0);
10042 op1 = gen_lowpart (V4SFmode, op1);
10043 emit_insn (gen_sse_movups (op0, op1));
10047 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10048 emit_move_insn (op0, CONST0_RTX (mode));
10050 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10052 if (mode != V4SFmode)
10053 op0 = gen_lowpart (V4SFmode, op0);
10054 m = adjust_address (op1, V2SFmode, 0);
10055 emit_insn (gen_sse_loadlps (op0, op0, m));
10056 m = adjust_address (op1, V2SFmode, 8);
10057 emit_insn (gen_sse_loadhps (op0, op0, m));
10060 else if (MEM_P (op0))
10062 /* If we're optimizing for size, movups is the smallest. */
10065 op0 = gen_lowpart (V4SFmode, op0);
10066 op1 = gen_lowpart (V4SFmode, op1);
10067 emit_insn (gen_sse_movups (op0, op1));
10071 /* ??? Similar to above, only less clear because of quote
10072 typeless stores unquote. */
10073 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10074 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10076 op0 = gen_lowpart (V16QImode, op0);
10077 op1 = gen_lowpart (V16QImode, op1);
10078 emit_insn (gen_sse2_movdqu (op0, op1));
10082 if (TARGET_SSE2 && mode == V2DFmode)
10084 m = adjust_address (op0, DFmode, 0);
10085 emit_insn (gen_sse2_storelpd (m, op1));
10086 m = adjust_address (op0, DFmode, 8);
10087 emit_insn (gen_sse2_storehpd (m, op1));
10091 if (mode != V4SFmode)
10092 op1 = gen_lowpart (V4SFmode, op1);
10093 m = adjust_address (op0, V2SFmode, 0);
10094 emit_insn (gen_sse_storelps (m, op1));
10095 m = adjust_address (op0, V2SFmode, 8);
10096 emit_insn (gen_sse_storehps (m, op1));
10100 gcc_unreachable ();
10103 /* Expand a push in MODE. This is some mode for which we do not support
10104 proper push instructions, at least from the registers that we expect
10105 the value to live in. */
10108 ix86_expand_push (enum machine_mode mode, rtx x)
10112 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10113 GEN_INT (-GET_MODE_SIZE (mode)),
10114 stack_pointer_rtx, 1, OPTAB_DIRECT);
10115 if (tmp != stack_pointer_rtx)
10116 emit_move_insn (stack_pointer_rtx, tmp);
10118 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10119 emit_move_insn (tmp, x);
10122 /* Helper function of ix86_fixup_binary_operands to canonicalize
10123 operand order. Returns true if the operands should be swapped. */
10126 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10129 rtx dst = operands[0];
10130 rtx src1 = operands[1];
10131 rtx src2 = operands[2];
10133 /* If the operation is not commutative, we can't do anything. */
10134 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10137 /* Highest priority is that src1 should match dst. */
10138 if (rtx_equal_p (dst, src1))
10140 if (rtx_equal_p (dst, src2))
10143 /* Next highest priority is that immediate constants come second. */
10144 if (immediate_operand (src2, mode))
10146 if (immediate_operand (src1, mode))
10149 /* Lowest priority is that memory references should come second. */
10159 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10160 destination to use for the operation. If different from the true
10161 destination in operands[0], a copy operation will be required. */
10164 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10167 rtx dst = operands[0];
10168 rtx src1 = operands[1];
10169 rtx src2 = operands[2];
10171 /* Canonicalize operand order. */
10172 if (ix86_swap_binary_operands_p (code, mode, operands))
10179 /* Both source operands cannot be in memory. */
10180 if (MEM_P (src1) && MEM_P (src2))
10182 /* Optimization: Only read from memory once. */
10183 if (rtx_equal_p (src1, src2))
10185 src2 = force_reg (mode, src2);
10189 src2 = force_reg (mode, src2);
10192 /* If the destination is memory, and we do not have matching source
10193 operands, do things in registers. */
10194 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10195 dst = gen_reg_rtx (mode);
10197 /* Source 1 cannot be a constant. */
10198 if (CONSTANT_P (src1))
10199 src1 = force_reg (mode, src1);
10201 /* Source 1 cannot be a non-matching memory. */
10202 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10203 src1 = force_reg (mode, src1);
10205 operands[1] = src1;
10206 operands[2] = src2;
10210 /* Similarly, but assume that the destination has already been
10211 set up properly. */
10214 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10215 enum machine_mode mode, rtx operands[])
10217 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10218 gcc_assert (dst == operands[0]);
10221 /* Attempt to expand a binary operator. Make the expansion closer to the
10222 actual machine, then just general_operand, which will allow 3 separate
10223 memory references (one output, two input) in a single insn. */
10226 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10229 rtx src1, src2, dst, op, clob;
10231 dst = ix86_fixup_binary_operands (code, mode, operands);
10232 src1 = operands[1];
10233 src2 = operands[2];
10235 /* Emit the instruction. */
10237 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10238 if (reload_in_progress)
10240 /* Reload doesn't know about the flags register, and doesn't know that
10241 it doesn't want to clobber it. We can only do this with PLUS. */
10242 gcc_assert (code == PLUS);
10247 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10248 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10251 /* Fix up the destination if needed. */
10252 if (dst != operands[0])
10253 emit_move_insn (operands[0], dst);
10256 /* Return TRUE or FALSE depending on whether the binary operator meets the
10257 appropriate constraints. */
10260 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10263 rtx dst = operands[0];
10264 rtx src1 = operands[1];
10265 rtx src2 = operands[2];
10267 /* Both source operands cannot be in memory. */
10268 if (MEM_P (src1) && MEM_P (src2))
10271 /* Canonicalize operand order for commutative operators. */
10272 if (ix86_swap_binary_operands_p (code, mode, operands))
10279 /* If the destination is memory, we must have a matching source operand. */
10280 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10283 /* Source 1 cannot be a constant. */
10284 if (CONSTANT_P (src1))
10287 /* Source 1 cannot be a non-matching memory. */
10288 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10294 /* Attempt to expand a unary operator. Make the expansion closer to the
10295 actual machine, then just general_operand, which will allow 2 separate
10296 memory references (one output, one input) in a single insn. */
10299 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10302 int matching_memory;
10303 rtx src, dst, op, clob;
10308 /* If the destination is memory, and we do not have matching source
10309 operands, do things in registers. */
10310 matching_memory = 0;
10313 if (rtx_equal_p (dst, src))
10314 matching_memory = 1;
10316 dst = gen_reg_rtx (mode);
10319 /* When source operand is memory, destination must match. */
10320 if (MEM_P (src) && !matching_memory)
10321 src = force_reg (mode, src);
10323 /* Emit the instruction. */
10325 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10326 if (reload_in_progress || code == NOT)
10328 /* Reload doesn't know about the flags register, and doesn't know that
10329 it doesn't want to clobber it. */
10330 gcc_assert (code == NOT);
10335 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10336 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10339 /* Fix up the destination if needed. */
10340 if (dst != operands[0])
10341 emit_move_insn (operands[0], dst);
10344 /* Return TRUE or FALSE depending on whether the unary operator meets the
10345 appropriate constraints. */
10348 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10349 enum machine_mode mode ATTRIBUTE_UNUSED,
10350 rtx operands[2] ATTRIBUTE_UNUSED)
10352 /* If one of operands is memory, source and destination must match. */
10353 if ((MEM_P (operands[0])
10354 || MEM_P (operands[1]))
10355 && ! rtx_equal_p (operands[0], operands[1]))
10360 /* Post-reload splitter for converting an SF or DFmode value in an
10361 SSE register into an unsigned SImode. */
10364 ix86_split_convert_uns_si_sse (rtx operands[])
10366 enum machine_mode vecmode;
10367 rtx value, large, zero_or_two31, input, two31, x;
10369 large = operands[1];
10370 zero_or_two31 = operands[2];
10371 input = operands[3];
10372 two31 = operands[4];
10373 vecmode = GET_MODE (large);
10374 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10376 /* Load up the value into the low element. We must ensure that the other
10377 elements are valid floats -- zero is the easiest such value. */
10380 if (vecmode == V4SFmode)
10381 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10383 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10387 input = gen_rtx_REG (vecmode, REGNO (input));
10388 emit_move_insn (value, CONST0_RTX (vecmode));
10389 if (vecmode == V4SFmode)
10390 emit_insn (gen_sse_movss (value, value, input));
10392 emit_insn (gen_sse2_movsd (value, value, input));
10395 emit_move_insn (large, two31);
10396 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10398 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10399 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10401 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10402 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10404 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10405 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10407 large = gen_rtx_REG (V4SImode, REGNO (large));
10408 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10410 x = gen_rtx_REG (V4SImode, REGNO (value));
10411 if (vecmode == V4SFmode)
10412 emit_insn (gen_sse2_cvttps2dq (x, value));
10414 emit_insn (gen_sse2_cvttpd2dq (x, value));
10417 emit_insn (gen_xorv4si3 (value, value, large));
10420 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10421 Expects the 64-bit DImode to be supplied in a pair of integral
10422 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10423 -mfpmath=sse, !optimize_size only. */
10426 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10428 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10429 rtx int_xmm, fp_xmm;
10430 rtx biases, exponents;
10433 int_xmm = gen_reg_rtx (V4SImode);
10434 if (TARGET_INTER_UNIT_MOVES)
10435 emit_insn (gen_movdi_to_sse (int_xmm, input));
10436 else if (TARGET_SSE_SPLIT_REGS)
10438 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10439 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10443 x = gen_reg_rtx (V2DImode);
10444 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10445 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10448 x = gen_rtx_CONST_VECTOR (V4SImode,
10449 gen_rtvec (4, GEN_INT (0x43300000UL),
10450 GEN_INT (0x45300000UL),
10451 const0_rtx, const0_rtx));
10452 exponents = validize_mem (force_const_mem (V4SImode, x));
10454 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10455 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10457 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10458 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10459 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10460 (0x1.0p84 + double(fp_value_hi_xmm)).
10461 Note these exponents differ by 32. */
10463 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
10465 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10466 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10467 real_ldexp (&bias_lo_rvt, &dconst1, 52);
10468 real_ldexp (&bias_hi_rvt, &dconst1, 84);
10469 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
10470 x = const_double_from_real_value (bias_hi_rvt, DFmode);
10471 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
10472 biases = validize_mem (force_const_mem (V2DFmode, biases));
10473 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
10475 /* Add the upper and lower DFmode values together. */
10477 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
10480 x = copy_to_mode_reg (V2DFmode, fp_xmm);
10481 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
10482 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
10485 ix86_expand_vector_extract (false, target, fp_xmm, 0);
10488 /* Convert an unsigned SImode value into a DFmode. Only currently used
10489 for SSE, but applicable anywhere. */
10492 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
10494 REAL_VALUE_TYPE TWO31r;
10497 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
10498 NULL, 1, OPTAB_DIRECT);
10500 fp = gen_reg_rtx (DFmode);
10501 emit_insn (gen_floatsidf2 (fp, x));
10503 real_ldexp (&TWO31r, &dconst1, 31);
10504 x = const_double_from_real_value (TWO31r, DFmode);
10506 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
10508 emit_move_insn (target, x);
10511 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10512 32-bit mode; otherwise we have a direct convert instruction. */
10515 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
10517 REAL_VALUE_TYPE TWO32r;
10518 rtx fp_lo, fp_hi, x;
10520 fp_lo = gen_reg_rtx (DFmode);
10521 fp_hi = gen_reg_rtx (DFmode);
10523 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
10525 real_ldexp (&TWO32r, &dconst1, 32);
10526 x = const_double_from_real_value (TWO32r, DFmode);
10527 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
10529 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
10531 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
10534 emit_move_insn (target, x);
10537 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10538 For x86_32, -mfpmath=sse, !optimize_size only. */
10540 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
10542 REAL_VALUE_TYPE ONE16r;
10543 rtx fp_hi, fp_lo, int_hi, int_lo, x;
10545 real_ldexp (&ONE16r, &dconst1, 16);
10546 x = const_double_from_real_value (ONE16r, SFmode);
10547 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
10548 NULL, 0, OPTAB_DIRECT);
10549 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
10550 NULL, 0, OPTAB_DIRECT);
10551 fp_hi = gen_reg_rtx (SFmode);
10552 fp_lo = gen_reg_rtx (SFmode);
10553 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
10554 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
10555 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
10557 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
10559 if (!rtx_equal_p (target, fp_hi))
10560 emit_move_insn (target, fp_hi);
10563 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10564 then replicate the value for all elements of the vector
10568 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
10575 v = gen_rtvec (4, value, value, value, value);
10576 return gen_rtx_CONST_VECTOR (V4SImode, v);
10580 v = gen_rtvec (2, value, value);
10581 return gen_rtx_CONST_VECTOR (V2DImode, v);
10585 v = gen_rtvec (4, value, value, value, value);
10587 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
10588 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
10589 return gen_rtx_CONST_VECTOR (V4SFmode, v);
10593 v = gen_rtvec (2, value, value);
10595 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
10596 return gen_rtx_CONST_VECTOR (V2DFmode, v);
10599 gcc_unreachable ();
10603 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
10604 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
10605 for an SSE register. If VECT is true, then replicate the mask for
10606 all elements of the vector register. If INVERT is true, then create
10607 a mask excluding the sign bit. */
10610 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
10612 enum machine_mode vec_mode, imode;
10613 HOST_WIDE_INT hi, lo;
10618 /* Find the sign bit, sign extended to 2*HWI. */
10624 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
10625 lo = 0x80000000, hi = lo < 0;
10631 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
10632 if (HOST_BITS_PER_WIDE_INT >= 64)
10633 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
10635 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
10641 vec_mode = VOIDmode;
10642 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
10643 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
10647 gcc_unreachable ();
10651 lo = ~lo, hi = ~hi;
10653 /* Force this value into the low part of a fp vector constant. */
10654 mask = immed_double_const (lo, hi, imode);
10655 mask = gen_lowpart (mode, mask);
10657 if (vec_mode == VOIDmode)
10658 return force_reg (mode, mask);
10660 v = ix86_build_const_vector (mode, vect, mask);
10661 return force_reg (vec_mode, v);
10664 /* Generate code for floating point ABS or NEG. */
10667 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
10670 rtx mask, set, use, clob, dst, src;
10671 bool matching_memory;
10672 bool use_sse = false;
10673 bool vector_mode = VECTOR_MODE_P (mode);
10674 enum machine_mode elt_mode = mode;
10678 elt_mode = GET_MODE_INNER (mode);
10681 else if (mode == TFmode)
10683 else if (TARGET_SSE_MATH)
10684 use_sse = SSE_FLOAT_MODE_P (mode);
10686 /* NEG and ABS performed with SSE use bitwise mask operations.
10687 Create the appropriate mask now. */
10689 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
10696 /* If the destination is memory, and we don't have matching source
10697 operands or we're using the x87, do things in registers. */
10698 matching_memory = false;
10701 if (use_sse && rtx_equal_p (dst, src))
10702 matching_memory = true;
10704 dst = gen_reg_rtx (mode);
10706 if (MEM_P (src) && !matching_memory)
10707 src = force_reg (mode, src);
10711 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
10712 set = gen_rtx_SET (VOIDmode, dst, set);
10717 set = gen_rtx_fmt_e (code, mode, src);
10718 set = gen_rtx_SET (VOIDmode, dst, set);
10721 use = gen_rtx_USE (VOIDmode, mask);
10722 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10723 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10724 gen_rtvec (3, set, use, clob)));
10730 if (dst != operands[0])
10731 emit_move_insn (operands[0], dst);
10734 /* Expand a copysign operation. Special case operand 0 being a constant. */
10737 ix86_expand_copysign (rtx operands[])
10739 enum machine_mode mode, vmode;
10740 rtx dest, op0, op1, mask, nmask;
10742 dest = operands[0];
10746 mode = GET_MODE (dest);
10747 vmode = mode == SFmode ? V4SFmode : V2DFmode;
10749 if (GET_CODE (op0) == CONST_DOUBLE)
10751 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
10753 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
10754 op0 = simplify_unary_operation (ABS, mode, op0, mode);
10756 if (mode == SFmode || mode == DFmode)
10758 if (op0 == CONST0_RTX (mode))
10759 op0 = CONST0_RTX (vmode);
10764 if (mode == SFmode)
10765 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
10766 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
10768 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
10769 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
10773 mask = ix86_build_signbit_mask (mode, 0, 0);
10775 if (mode == SFmode)
10776 copysign_insn = gen_copysignsf3_const;
10777 else if (mode == DFmode)
10778 copysign_insn = gen_copysigndf3_const;
10780 copysign_insn = gen_copysigntf3_const;
10782 emit_insn (copysign_insn (dest, op0, op1, mask));
10786 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
10788 nmask = ix86_build_signbit_mask (mode, 0, 1);
10789 mask = ix86_build_signbit_mask (mode, 0, 0);
10791 if (mode == SFmode)
10792 copysign_insn = gen_copysignsf3_var;
10793 else if (mode == DFmode)
10794 copysign_insn = gen_copysigndf3_var;
10796 copysign_insn = gen_copysigntf3_var;
10798 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
10802 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
10803 be a constant, and so has already been expanded into a vector constant. */
10806 ix86_split_copysign_const (rtx operands[])
10808 enum machine_mode mode, vmode;
10809 rtx dest, op0, op1, mask, x;
10811 dest = operands[0];
10814 mask = operands[3];
10816 mode = GET_MODE (dest);
10817 vmode = GET_MODE (mask);
10819 dest = simplify_gen_subreg (vmode, dest, mode, 0);
10820 x = gen_rtx_AND (vmode, dest, mask);
10821 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10823 if (op0 != CONST0_RTX (vmode))
10825 x = gen_rtx_IOR (vmode, dest, op0);
10826 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10830 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
10831 so we have to do two masks. */
10834 ix86_split_copysign_var (rtx operands[])
10836 enum machine_mode mode, vmode;
10837 rtx dest, scratch, op0, op1, mask, nmask, x;
10839 dest = operands[0];
10840 scratch = operands[1];
10843 nmask = operands[4];
10844 mask = operands[5];
10846 mode = GET_MODE (dest);
10847 vmode = GET_MODE (mask);
10849 if (rtx_equal_p (op0, op1))
10851 /* Shouldn't happen often (it's useless, obviously), but when it does
10852 we'd generate incorrect code if we continue below. */
10853 emit_move_insn (dest, op0);
10857 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
10859 gcc_assert (REGNO (op1) == REGNO (scratch));
10861 x = gen_rtx_AND (vmode, scratch, mask);
10862 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
10865 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
10866 x = gen_rtx_NOT (vmode, dest);
10867 x = gen_rtx_AND (vmode, x, op0);
10868 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10872 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
10874 x = gen_rtx_AND (vmode, scratch, mask);
10876 else /* alternative 2,4 */
10878 gcc_assert (REGNO (mask) == REGNO (scratch));
10879 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
10880 x = gen_rtx_AND (vmode, scratch, op1);
10882 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
10884 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
10886 dest = simplify_gen_subreg (vmode, op0, mode, 0);
10887 x = gen_rtx_AND (vmode, dest, nmask);
10889 else /* alternative 3,4 */
10891 gcc_assert (REGNO (nmask) == REGNO (dest));
10893 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
10894 x = gen_rtx_AND (vmode, dest, op0);
10896 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10899 x = gen_rtx_IOR (vmode, dest, scratch);
10900 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10903 /* Return TRUE or FALSE depending on whether the first SET in INSN
10904 has source and destination with matching CC modes, and that the
10905 CC mode is at least as constrained as REQ_MODE. */
10908 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
10911 enum machine_mode set_mode;
10913 set = PATTERN (insn);
10914 if (GET_CODE (set) == PARALLEL)
10915 set = XVECEXP (set, 0, 0);
10916 gcc_assert (GET_CODE (set) == SET);
10917 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
10919 set_mode = GET_MODE (SET_DEST (set));
10923 if (req_mode != CCNOmode
10924 && (req_mode != CCmode
10925 || XEXP (SET_SRC (set), 1) != const0_rtx))
10929 if (req_mode == CCGCmode)
10933 if (req_mode == CCGOCmode || req_mode == CCNOmode)
10937 if (req_mode == CCZmode)
10944 gcc_unreachable ();
10947 return (GET_MODE (SET_SRC (set)) == set_mode);
10950 /* Generate insn patterns to do an integer compare of OPERANDS. */
10953 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
10955 enum machine_mode cmpmode;
10958 cmpmode = SELECT_CC_MODE (code, op0, op1);
10959 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
10961 /* This is very simple, but making the interface the same as in the
10962 FP case makes the rest of the code easier. */
10963 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
10964 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
10966 /* Return the test that should be put into the flags user, i.e.
10967 the bcc, scc, or cmov instruction. */
10968 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
10971 /* Figure out whether to use ordered or unordered fp comparisons.
10972 Return the appropriate mode to use. */
10975 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
10977 /* ??? In order to make all comparisons reversible, we do all comparisons
10978 non-trapping when compiling for IEEE. Once gcc is able to distinguish
10979 all forms trapping and nontrapping comparisons, we can make inequality
10980 comparisons trapping again, since it results in better code when using
10981 FCOM based compares. */
10982 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
10986 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
10988 enum machine_mode mode = GET_MODE (op0);
10990 if (SCALAR_FLOAT_MODE_P (mode))
10992 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
10993 return ix86_fp_compare_mode (code);
10998 /* Only zero flag is needed. */
10999 case EQ: /* ZF=0 */
11000 case NE: /* ZF!=0 */
11002 /* Codes needing carry flag. */
11003 case GEU: /* CF=0 */
11004 case GTU: /* CF=0 & ZF=0 */
11005 case LTU: /* CF=1 */
11006 case LEU: /* CF=1 | ZF=1 */
11008 /* Codes possibly doable only with sign flag when
11009 comparing against zero. */
11010 case GE: /* SF=OF or SF=0 */
11011 case LT: /* SF<>OF or SF=1 */
11012 if (op1 == const0_rtx)
11015 /* For other cases Carry flag is not required. */
11017 /* Codes doable only with sign flag when comparing
11018 against zero, but we miss jump instruction for it
11019 so we need to use relational tests against overflow
11020 that thus needs to be zero. */
11021 case GT: /* ZF=0 & SF=OF */
11022 case LE: /* ZF=1 | SF<>OF */
11023 if (op1 == const0_rtx)
11027 /* strcmp pattern do (use flags) and combine may ask us for proper
11032 gcc_unreachable ();
11036 /* Return the fixed registers used for condition codes. */
11039 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11046 /* If two condition code modes are compatible, return a condition code
11047 mode which is compatible with both. Otherwise, return
11050 static enum machine_mode
11051 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11056 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11059 if ((m1 == CCGCmode && m2 == CCGOCmode)
11060 || (m1 == CCGOCmode && m2 == CCGCmode))
11066 gcc_unreachable ();
11096 /* These are only compatible with themselves, which we already
11102 /* Split comparison code CODE into comparisons we can do using branch
11103 instructions. BYPASS_CODE is comparison code for branch that will
11104 branch around FIRST_CODE and SECOND_CODE. If some of branches
11105 is not required, set value to UNKNOWN.
11106 We never require more than two branches. */
11109 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11110 enum rtx_code *first_code,
11111 enum rtx_code *second_code)
11113 *first_code = code;
11114 *bypass_code = UNKNOWN;
11115 *second_code = UNKNOWN;
11117 /* The fcomi comparison sets flags as follows:
11127 case GT: /* GTU - CF=0 & ZF=0 */
11128 case GE: /* GEU - CF=0 */
11129 case ORDERED: /* PF=0 */
11130 case UNORDERED: /* PF=1 */
11131 case UNEQ: /* EQ - ZF=1 */
11132 case UNLT: /* LTU - CF=1 */
11133 case UNLE: /* LEU - CF=1 | ZF=1 */
11134 case LTGT: /* EQ - ZF=0 */
11136 case LT: /* LTU - CF=1 - fails on unordered */
11137 *first_code = UNLT;
11138 *bypass_code = UNORDERED;
11140 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11141 *first_code = UNLE;
11142 *bypass_code = UNORDERED;
11144 case EQ: /* EQ - ZF=1 - fails on unordered */
11145 *first_code = UNEQ;
11146 *bypass_code = UNORDERED;
11148 case NE: /* NE - ZF=0 - fails on unordered */
11149 *first_code = LTGT;
11150 *second_code = UNORDERED;
11152 case UNGE: /* GEU - CF=0 - fails on unordered */
11154 *second_code = UNORDERED;
11156 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11158 *second_code = UNORDERED;
11161 gcc_unreachable ();
11163 if (!TARGET_IEEE_FP)
11165 *second_code = UNKNOWN;
11166 *bypass_code = UNKNOWN;
11170 /* Return cost of comparison done fcom + arithmetics operations on AX.
11171 All following functions do use number of instructions as a cost metrics.
11172 In future this should be tweaked to compute bytes for optimize_size and
11173 take into account performance of various instructions on various CPUs. */
11175 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11177 if (!TARGET_IEEE_FP)
11179 /* The cost of code output by ix86_expand_fp_compare. */
11203 gcc_unreachable ();
11207 /* Return cost of comparison done using fcomi operation.
11208 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11210 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11212 enum rtx_code bypass_code, first_code, second_code;
11213 /* Return arbitrarily high cost when instruction is not supported - this
11214 prevents gcc from using it. */
11217 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11218 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11221 /* Return cost of comparison done using sahf operation.
11222 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11224 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11226 enum rtx_code bypass_code, first_code, second_code;
11227 /* Return arbitrarily high cost when instruction is not preferred - this
11228 avoids gcc from using it. */
11229 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11231 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11232 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11235 /* Compute cost of the comparison done using any method.
11236 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11238 ix86_fp_comparison_cost (enum rtx_code code)
11240 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11243 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11244 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11246 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11247 if (min > sahf_cost)
11249 if (min > fcomi_cost)
11254 /* Return true if we should use an FCOMI instruction for this
11258 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11260 enum rtx_code swapped_code = swap_condition (code);
11262 return ((ix86_fp_comparison_cost (code)
11263 == ix86_fp_comparison_fcomi_cost (code))
11264 || (ix86_fp_comparison_cost (swapped_code)
11265 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11268 /* Swap, force into registers, or otherwise massage the two operands
11269 to a fp comparison. The operands are updated in place; the new
11270 comparison code is returned. */
11272 static enum rtx_code
11273 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11275 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11276 rtx op0 = *pop0, op1 = *pop1;
11277 enum machine_mode op_mode = GET_MODE (op0);
11278 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11280 /* All of the unordered compare instructions only work on registers.
11281 The same is true of the fcomi compare instructions. The XFmode
11282 compare instructions require registers except when comparing
11283 against zero or when converting operand 1 from fixed point to
11287 && (fpcmp_mode == CCFPUmode
11288 || (op_mode == XFmode
11289 && ! (standard_80387_constant_p (op0) == 1
11290 || standard_80387_constant_p (op1) == 1)
11291 && GET_CODE (op1) != FLOAT)
11292 || ix86_use_fcomi_compare (code)))
11294 op0 = force_reg (op_mode, op0);
11295 op1 = force_reg (op_mode, op1);
11299 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11300 things around if they appear profitable, otherwise force op0
11301 into a register. */
11303 if (standard_80387_constant_p (op0) == 0
11305 && ! (standard_80387_constant_p (op1) == 0
11309 tmp = op0, op0 = op1, op1 = tmp;
11310 code = swap_condition (code);
11314 op0 = force_reg (op_mode, op0);
11316 if (CONSTANT_P (op1))
11318 int tmp = standard_80387_constant_p (op1);
11320 op1 = validize_mem (force_const_mem (op_mode, op1));
11324 op1 = force_reg (op_mode, op1);
11327 op1 = force_reg (op_mode, op1);
11331 /* Try to rearrange the comparison to make it cheaper. */
11332 if (ix86_fp_comparison_cost (code)
11333 > ix86_fp_comparison_cost (swap_condition (code))
11334 && (REG_P (op1) || !no_new_pseudos))
11337 tmp = op0, op0 = op1, op1 = tmp;
11338 code = swap_condition (code);
11340 op0 = force_reg (op_mode, op0);
11348 /* Convert comparison codes we use to represent FP comparison to integer
11349 code that will result in proper branch. Return UNKNOWN if no such code
11353 ix86_fp_compare_code_to_integer (enum rtx_code code)
11382 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11385 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11386 rtx *second_test, rtx *bypass_test)
11388 enum machine_mode fpcmp_mode, intcmp_mode;
11390 int cost = ix86_fp_comparison_cost (code);
11391 enum rtx_code bypass_code, first_code, second_code;
11393 fpcmp_mode = ix86_fp_compare_mode (code);
11394 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11397 *second_test = NULL_RTX;
11399 *bypass_test = NULL_RTX;
11401 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11403 /* Do fcomi/sahf based test when profitable. */
11404 if ((TARGET_CMOVE || TARGET_SAHF)
11405 && (bypass_code == UNKNOWN || bypass_test)
11406 && (second_code == UNKNOWN || second_test)
11407 && ix86_fp_comparison_arithmetics_cost (code) > cost)
11411 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11412 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11418 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11419 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11421 scratch = gen_reg_rtx (HImode);
11422 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11423 emit_insn (gen_x86_sahf_1 (scratch));
11426 /* The FP codes work out to act like unsigned. */
11427 intcmp_mode = fpcmp_mode;
11429 if (bypass_code != UNKNOWN)
11430 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11431 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11433 if (second_code != UNKNOWN)
11434 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11435 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11440 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11441 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11442 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11444 scratch = gen_reg_rtx (HImode);
11445 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11447 /* In the unordered case, we have to check C2 for NaN's, which
11448 doesn't happen to work out to anything nice combination-wise.
11449 So do some bit twiddling on the value we've got in AH to come
11450 up with an appropriate set of condition codes. */
11452 intcmp_mode = CCNOmode;
11457 if (code == GT || !TARGET_IEEE_FP)
11459 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11464 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11465 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11466 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
11467 intcmp_mode = CCmode;
11473 if (code == LT && TARGET_IEEE_FP)
11475 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11476 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
11477 intcmp_mode = CCmode;
11482 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
11488 if (code == GE || !TARGET_IEEE_FP)
11490 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
11495 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11496 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11503 if (code == LE && TARGET_IEEE_FP)
11505 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11506 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11507 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11508 intcmp_mode = CCmode;
11513 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11519 if (code == EQ && TARGET_IEEE_FP)
11521 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11522 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11523 intcmp_mode = CCmode;
11528 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11535 if (code == NE && TARGET_IEEE_FP)
11537 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11538 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11544 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11550 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11554 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11559 gcc_unreachable ();
11563 /* Return the test that should be put into the flags user, i.e.
11564 the bcc, scc, or cmov instruction. */
11565 return gen_rtx_fmt_ee (code, VOIDmode,
11566 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11571 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
11574 op0 = ix86_compare_op0;
11575 op1 = ix86_compare_op1;
11578 *second_test = NULL_RTX;
11580 *bypass_test = NULL_RTX;
11582 if (ix86_compare_emitted)
11584 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
11585 ix86_compare_emitted = NULL_RTX;
11587 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
11589 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
11590 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
11591 second_test, bypass_test);
11594 ret = ix86_expand_int_compare (code, op0, op1);
11599 /* Return true if the CODE will result in nontrivial jump sequence. */
11601 ix86_fp_jump_nontrivial_p (enum rtx_code code)
11603 enum rtx_code bypass_code, first_code, second_code;
11606 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11607 return bypass_code != UNKNOWN || second_code != UNKNOWN;
11611 ix86_expand_branch (enum rtx_code code, rtx label)
11615 /* If we have emitted a compare insn, go straight to simple.
11616 ix86_expand_compare won't emit anything if ix86_compare_emitted
11618 if (ix86_compare_emitted)
11621 switch (GET_MODE (ix86_compare_op0))
11627 tmp = ix86_expand_compare (code, NULL, NULL);
11628 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11629 gen_rtx_LABEL_REF (VOIDmode, label),
11631 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11640 enum rtx_code bypass_code, first_code, second_code;
11642 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
11643 &ix86_compare_op1);
11645 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11647 /* Check whether we will use the natural sequence with one jump. If
11648 so, we can expand jump early. Otherwise delay expansion by
11649 creating compound insn to not confuse optimizers. */
11650 if (bypass_code == UNKNOWN && second_code == UNKNOWN
11653 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
11654 gen_rtx_LABEL_REF (VOIDmode, label),
11655 pc_rtx, NULL_RTX, NULL_RTX);
11659 tmp = gen_rtx_fmt_ee (code, VOIDmode,
11660 ix86_compare_op0, ix86_compare_op1);
11661 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11662 gen_rtx_LABEL_REF (VOIDmode, label),
11664 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
11666 use_fcomi = ix86_use_fcomi_compare (code);
11667 vec = rtvec_alloc (3 + !use_fcomi);
11668 RTVEC_ELT (vec, 0) = tmp;
11670 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
11672 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
11675 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
11677 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
11686 /* Expand DImode branch into multiple compare+branch. */
11688 rtx lo[2], hi[2], label2;
11689 enum rtx_code code1, code2, code3;
11690 enum machine_mode submode;
11692 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
11694 tmp = ix86_compare_op0;
11695 ix86_compare_op0 = ix86_compare_op1;
11696 ix86_compare_op1 = tmp;
11697 code = swap_condition (code);
11699 if (GET_MODE (ix86_compare_op0) == DImode)
11701 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
11702 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
11707 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
11708 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
11712 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
11713 avoid two branches. This costs one extra insn, so disable when
11714 optimizing for size. */
11716 if ((code == EQ || code == NE)
11718 || hi[1] == const0_rtx || lo[1] == const0_rtx))
11723 if (hi[1] != const0_rtx)
11724 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
11725 NULL_RTX, 0, OPTAB_WIDEN);
11728 if (lo[1] != const0_rtx)
11729 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
11730 NULL_RTX, 0, OPTAB_WIDEN);
11732 tmp = expand_binop (submode, ior_optab, xor1, xor0,
11733 NULL_RTX, 0, OPTAB_WIDEN);
11735 ix86_compare_op0 = tmp;
11736 ix86_compare_op1 = const0_rtx;
11737 ix86_expand_branch (code, label);
11741 /* Otherwise, if we are doing less-than or greater-or-equal-than,
11742 op1 is a constant and the low word is zero, then we can just
11743 examine the high word. */
11745 if (CONST_INT_P (hi[1]) && lo[1] == const0_rtx)
11748 case LT: case LTU: case GE: case GEU:
11749 ix86_compare_op0 = hi[0];
11750 ix86_compare_op1 = hi[1];
11751 ix86_expand_branch (code, label);
11757 /* Otherwise, we need two or three jumps. */
11759 label2 = gen_label_rtx ();
11762 code2 = swap_condition (code);
11763 code3 = unsigned_condition (code);
11767 case LT: case GT: case LTU: case GTU:
11770 case LE: code1 = LT; code2 = GT; break;
11771 case GE: code1 = GT; code2 = LT; break;
11772 case LEU: code1 = LTU; code2 = GTU; break;
11773 case GEU: code1 = GTU; code2 = LTU; break;
11775 case EQ: code1 = UNKNOWN; code2 = NE; break;
11776 case NE: code2 = UNKNOWN; break;
11779 gcc_unreachable ();
11784 * if (hi(a) < hi(b)) goto true;
11785 * if (hi(a) > hi(b)) goto false;
11786 * if (lo(a) < lo(b)) goto true;
11790 ix86_compare_op0 = hi[0];
11791 ix86_compare_op1 = hi[1];
11793 if (code1 != UNKNOWN)
11794 ix86_expand_branch (code1, label);
11795 if (code2 != UNKNOWN)
11796 ix86_expand_branch (code2, label2);
11798 ix86_compare_op0 = lo[0];
11799 ix86_compare_op1 = lo[1];
11800 ix86_expand_branch (code3, label);
11802 if (code2 != UNKNOWN)
11803 emit_label (label2);
11808 gcc_unreachable ();
11812 /* Split branch based on floating point condition. */
11814 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
11815 rtx target1, rtx target2, rtx tmp, rtx pushed)
11817 rtx second, bypass;
11818 rtx label = NULL_RTX;
11820 int bypass_probability = -1, second_probability = -1, probability = -1;
11823 if (target2 != pc_rtx)
11826 code = reverse_condition_maybe_unordered (code);
11831 condition = ix86_expand_fp_compare (code, op1, op2,
11832 tmp, &second, &bypass);
11834 /* Remove pushed operand from stack. */
11836 ix86_free_from_memory (GET_MODE (pushed));
11838 if (split_branch_probability >= 0)
11840 /* Distribute the probabilities across the jumps.
11841 Assume the BYPASS and SECOND to be always test
11843 probability = split_branch_probability;
11845 /* Value of 1 is low enough to make no need for probability
11846 to be updated. Later we may run some experiments and see
11847 if unordered values are more frequent in practice. */
11849 bypass_probability = 1;
11851 second_probability = 1;
11853 if (bypass != NULL_RTX)
11855 label = gen_label_rtx ();
11856 i = emit_jump_insn (gen_rtx_SET
11858 gen_rtx_IF_THEN_ELSE (VOIDmode,
11860 gen_rtx_LABEL_REF (VOIDmode,
11863 if (bypass_probability >= 0)
11865 = gen_rtx_EXPR_LIST (REG_BR_PROB,
11866 GEN_INT (bypass_probability),
11869 i = emit_jump_insn (gen_rtx_SET
11871 gen_rtx_IF_THEN_ELSE (VOIDmode,
11872 condition, target1, target2)));
11873 if (probability >= 0)
11875 = gen_rtx_EXPR_LIST (REG_BR_PROB,
11876 GEN_INT (probability),
11878 if (second != NULL_RTX)
11880 i = emit_jump_insn (gen_rtx_SET
11882 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
11884 if (second_probability >= 0)
11886 = gen_rtx_EXPR_LIST (REG_BR_PROB,
11887 GEN_INT (second_probability),
11890 if (label != NULL_RTX)
11891 emit_label (label);
11895 ix86_expand_setcc (enum rtx_code code, rtx dest)
11897 rtx ret, tmp, tmpreg, equiv;
11898 rtx second_test, bypass_test;
11900 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
11901 return 0; /* FAIL */
11903 gcc_assert (GET_MODE (dest) == QImode);
11905 ret = ix86_expand_compare (code, &second_test, &bypass_test);
11906 PUT_MODE (ret, QImode);
11911 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
11912 if (bypass_test || second_test)
11914 rtx test = second_test;
11916 rtx tmp2 = gen_reg_rtx (QImode);
11919 gcc_assert (!second_test);
11920 test = bypass_test;
11922 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
11924 PUT_MODE (test, QImode);
11925 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
11928 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
11930 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
11933 /* Attach a REG_EQUAL note describing the comparison result. */
11934 if (ix86_compare_op0 && ix86_compare_op1)
11936 equiv = simplify_gen_relational (code, QImode,
11937 GET_MODE (ix86_compare_op0),
11938 ix86_compare_op0, ix86_compare_op1);
11939 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
11942 return 1; /* DONE */
11945 /* Expand comparison setting or clearing carry flag. Return true when
11946 successful and set pop for the operation. */
11948 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
11950 enum machine_mode mode =
11951 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
11953 /* Do not handle DImode compares that go through special path.
11954 Also we can't deal with FP compares yet. This is possible to add. */
11955 if (mode == (TARGET_64BIT ? TImode : DImode))
11958 if (SCALAR_FLOAT_MODE_P (mode))
11960 rtx second_test = NULL, bypass_test = NULL;
11961 rtx compare_op, compare_seq;
11963 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11965 /* Shortcut: following common codes never translate
11966 into carry flag compares. */
11967 if (code == EQ || code == NE || code == UNEQ || code == LTGT
11968 || code == ORDERED || code == UNORDERED)
11971 /* These comparisons require zero flag; swap operands so they won't. */
11972 if ((code == GT || code == UNLE || code == LE || code == UNGT)
11973 && !TARGET_IEEE_FP)
11978 code = swap_condition (code);
11981 /* Try to expand the comparison and verify that we end up with carry flag
11982 based comparison. This is fails to be true only when we decide to expand
11983 comparison using arithmetic that is not too common scenario. */
11985 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
11986 &second_test, &bypass_test);
11987 compare_seq = get_insns ();
11990 if (second_test || bypass_test)
11992 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11993 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11994 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
11996 code = GET_CODE (compare_op);
11997 if (code != LTU && code != GEU)
11999 emit_insn (compare_seq);
12003 if (!INTEGRAL_MODE_P (mode))
12011 /* Convert a==0 into (unsigned)a<1. */
12014 if (op1 != const0_rtx)
12017 code = (code == EQ ? LTU : GEU);
12020 /* Convert a>b into b<a or a>=b-1. */
12023 if (CONST_INT_P (op1))
12025 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12026 /* Bail out on overflow. We still can swap operands but that
12027 would force loading of the constant into register. */
12028 if (op1 == const0_rtx
12029 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12031 code = (code == GTU ? GEU : LTU);
12038 code = (code == GTU ? LTU : GEU);
12042 /* Convert a>=0 into (unsigned)a<0x80000000. */
12045 if (mode == DImode || op1 != const0_rtx)
12047 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12048 code = (code == LT ? GEU : LTU);
12052 if (mode == DImode || op1 != constm1_rtx)
12054 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12055 code = (code == LE ? GEU : LTU);
12061 /* Swapping operands may cause constant to appear as first operand. */
12062 if (!nonimmediate_operand (op0, VOIDmode))
12064 if (no_new_pseudos)
12066 op0 = force_reg (mode, op0);
12068 ix86_compare_op0 = op0;
12069 ix86_compare_op1 = op1;
12070 *pop = ix86_expand_compare (code, NULL, NULL);
12071 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12076 ix86_expand_int_movcc (rtx operands[])
12078 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12079 rtx compare_seq, compare_op;
12080 rtx second_test, bypass_test;
12081 enum machine_mode mode = GET_MODE (operands[0]);
12082 bool sign_bit_compare_p = false;;
12085 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12086 compare_seq = get_insns ();
12089 compare_code = GET_CODE (compare_op);
12091 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12092 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12093 sign_bit_compare_p = true;
12095 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12096 HImode insns, we'd be swallowed in word prefix ops. */
12098 if ((mode != HImode || TARGET_FAST_PREFIX)
12099 && (mode != (TARGET_64BIT ? TImode : DImode))
12100 && CONST_INT_P (operands[2])
12101 && CONST_INT_P (operands[3]))
12103 rtx out = operands[0];
12104 HOST_WIDE_INT ct = INTVAL (operands[2]);
12105 HOST_WIDE_INT cf = INTVAL (operands[3]);
12106 HOST_WIDE_INT diff;
12109 /* Sign bit compares are better done using shifts than we do by using
12111 if (sign_bit_compare_p
12112 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12113 ix86_compare_op1, &compare_op))
12115 /* Detect overlap between destination and compare sources. */
12118 if (!sign_bit_compare_p)
12120 bool fpcmp = false;
12122 compare_code = GET_CODE (compare_op);
12124 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12125 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12128 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12131 /* To simplify rest of code, restrict to the GEU case. */
12132 if (compare_code == LTU)
12134 HOST_WIDE_INT tmp = ct;
12137 compare_code = reverse_condition (compare_code);
12138 code = reverse_condition (code);
12143 PUT_CODE (compare_op,
12144 reverse_condition_maybe_unordered
12145 (GET_CODE (compare_op)));
12147 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12151 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12152 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12153 tmp = gen_reg_rtx (mode);
12155 if (mode == DImode)
12156 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12158 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12162 if (code == GT || code == GE)
12163 code = reverse_condition (code);
12166 HOST_WIDE_INT tmp = ct;
12171 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12172 ix86_compare_op1, VOIDmode, 0, -1);
12185 tmp = expand_simple_binop (mode, PLUS,
12187 copy_rtx (tmp), 1, OPTAB_DIRECT);
12198 tmp = expand_simple_binop (mode, IOR,
12200 copy_rtx (tmp), 1, OPTAB_DIRECT);
12202 else if (diff == -1 && ct)
12212 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12214 tmp = expand_simple_binop (mode, PLUS,
12215 copy_rtx (tmp), GEN_INT (cf),
12216 copy_rtx (tmp), 1, OPTAB_DIRECT);
12224 * andl cf - ct, dest
12234 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12237 tmp = expand_simple_binop (mode, AND,
12239 gen_int_mode (cf - ct, mode),
12240 copy_rtx (tmp), 1, OPTAB_DIRECT);
12242 tmp = expand_simple_binop (mode, PLUS,
12243 copy_rtx (tmp), GEN_INT (ct),
12244 copy_rtx (tmp), 1, OPTAB_DIRECT);
12247 if (!rtx_equal_p (tmp, out))
12248 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12250 return 1; /* DONE */
12255 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12258 tmp = ct, ct = cf, cf = tmp;
12261 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12263 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12265 /* We may be reversing unordered compare to normal compare, that
12266 is not valid in general (we may convert non-trapping condition
12267 to trapping one), however on i386 we currently emit all
12268 comparisons unordered. */
12269 compare_code = reverse_condition_maybe_unordered (compare_code);
12270 code = reverse_condition_maybe_unordered (code);
12274 compare_code = reverse_condition (compare_code);
12275 code = reverse_condition (code);
12279 compare_code = UNKNOWN;
12280 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12281 && CONST_INT_P (ix86_compare_op1))
12283 if (ix86_compare_op1 == const0_rtx
12284 && (code == LT || code == GE))
12285 compare_code = code;
12286 else if (ix86_compare_op1 == constm1_rtx)
12290 else if (code == GT)
12295 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12296 if (compare_code != UNKNOWN
12297 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12298 && (cf == -1 || ct == -1))
12300 /* If lea code below could be used, only optimize
12301 if it results in a 2 insn sequence. */
12303 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12304 || diff == 3 || diff == 5 || diff == 9)
12305 || (compare_code == LT && ct == -1)
12306 || (compare_code == GE && cf == -1))
12309 * notl op1 (if necessary)
12317 code = reverse_condition (code);
12320 out = emit_store_flag (out, code, ix86_compare_op0,
12321 ix86_compare_op1, VOIDmode, 0, -1);
12323 out = expand_simple_binop (mode, IOR,
12325 out, 1, OPTAB_DIRECT);
12326 if (out != operands[0])
12327 emit_move_insn (operands[0], out);
12329 return 1; /* DONE */
12334 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12335 || diff == 3 || diff == 5 || diff == 9)
12336 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12338 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12344 * lea cf(dest*(ct-cf)),dest
12348 * This also catches the degenerate setcc-only case.
12354 out = emit_store_flag (out, code, ix86_compare_op0,
12355 ix86_compare_op1, VOIDmode, 0, 1);
12358 /* On x86_64 the lea instruction operates on Pmode, so we need
12359 to get arithmetics done in proper mode to match. */
12361 tmp = copy_rtx (out);
12365 out1 = copy_rtx (out);
12366 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12370 tmp = gen_rtx_PLUS (mode, tmp, out1);
12376 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12379 if (!rtx_equal_p (tmp, out))
12382 out = force_operand (tmp, copy_rtx (out));
12384 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12386 if (!rtx_equal_p (out, operands[0]))
12387 emit_move_insn (operands[0], copy_rtx (out));
12389 return 1; /* DONE */
12393 * General case: Jumpful:
12394 * xorl dest,dest cmpl op1, op2
12395 * cmpl op1, op2 movl ct, dest
12396 * setcc dest jcc 1f
12397 * decl dest movl cf, dest
12398 * andl (cf-ct),dest 1:
12401 * Size 20. Size 14.
12403 * This is reasonably steep, but branch mispredict costs are
12404 * high on modern cpus, so consider failing only if optimizing
12408 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12409 && BRANCH_COST >= 2)
12413 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12418 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12420 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12422 /* We may be reversing unordered compare to normal compare,
12423 that is not valid in general (we may convert non-trapping
12424 condition to trapping one), however on i386 we currently
12425 emit all comparisons unordered. */
12426 code = reverse_condition_maybe_unordered (code);
12430 code = reverse_condition (code);
12431 if (compare_code != UNKNOWN)
12432 compare_code = reverse_condition (compare_code);
12436 if (compare_code != UNKNOWN)
12438 /* notl op1 (if needed)
12443 For x < 0 (resp. x <= -1) there will be no notl,
12444 so if possible swap the constants to get rid of the
12446 True/false will be -1/0 while code below (store flag
12447 followed by decrement) is 0/-1, so the constants need
12448 to be exchanged once more. */
12450 if (compare_code == GE || !cf)
12452 code = reverse_condition (code);
12457 HOST_WIDE_INT tmp = cf;
12462 out = emit_store_flag (out, code, ix86_compare_op0,
12463 ix86_compare_op1, VOIDmode, 0, -1);
12467 out = emit_store_flag (out, code, ix86_compare_op0,
12468 ix86_compare_op1, VOIDmode, 0, 1);
12470 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
12471 copy_rtx (out), 1, OPTAB_DIRECT);
12474 out = expand_simple_binop (mode, AND, copy_rtx (out),
12475 gen_int_mode (cf - ct, mode),
12476 copy_rtx (out), 1, OPTAB_DIRECT);
12478 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
12479 copy_rtx (out), 1, OPTAB_DIRECT);
12480 if (!rtx_equal_p (out, operands[0]))
12481 emit_move_insn (operands[0], copy_rtx (out));
12483 return 1; /* DONE */
12487 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12489 /* Try a few things more with specific constants and a variable. */
12492 rtx var, orig_out, out, tmp;
12494 if (BRANCH_COST <= 2)
12495 return 0; /* FAIL */
12497 /* If one of the two operands is an interesting constant, load a
12498 constant with the above and mask it in with a logical operation. */
12500 if (CONST_INT_P (operands[2]))
12503 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
12504 operands[3] = constm1_rtx, op = and_optab;
12505 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
12506 operands[3] = const0_rtx, op = ior_optab;
12508 return 0; /* FAIL */
12510 else if (CONST_INT_P (operands[3]))
12513 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
12514 operands[2] = constm1_rtx, op = and_optab;
12515 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
12516 operands[2] = const0_rtx, op = ior_optab;
12518 return 0; /* FAIL */
12521 return 0; /* FAIL */
12523 orig_out = operands[0];
12524 tmp = gen_reg_rtx (mode);
12527 /* Recurse to get the constant loaded. */
12528 if (ix86_expand_int_movcc (operands) == 0)
12529 return 0; /* FAIL */
12531 /* Mask in the interesting variable. */
12532 out = expand_binop (mode, op, var, tmp, orig_out, 0,
12534 if (!rtx_equal_p (out, orig_out))
12535 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
12537 return 1; /* DONE */
12541 * For comparison with above,
12551 if (! nonimmediate_operand (operands[2], mode))
12552 operands[2] = force_reg (mode, operands[2]);
12553 if (! nonimmediate_operand (operands[3], mode))
12554 operands[3] = force_reg (mode, operands[3]);
12556 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12558 rtx tmp = gen_reg_rtx (mode);
12559 emit_move_insn (tmp, operands[3]);
12562 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
12564 rtx tmp = gen_reg_rtx (mode);
12565 emit_move_insn (tmp, operands[2]);
12569 if (! register_operand (operands[2], VOIDmode)
12571 || ! register_operand (operands[3], VOIDmode)))
12572 operands[2] = force_reg (mode, operands[2]);
12575 && ! register_operand (operands[3], VOIDmode))
12576 operands[3] = force_reg (mode, operands[3]);
12578 emit_insn (compare_seq);
12579 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12580 gen_rtx_IF_THEN_ELSE (mode,
12581 compare_op, operands[2],
12584 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
12585 gen_rtx_IF_THEN_ELSE (mode,
12587 copy_rtx (operands[3]),
12588 copy_rtx (operands[0]))));
12590 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
12591 gen_rtx_IF_THEN_ELSE (mode,
12593 copy_rtx (operands[2]),
12594 copy_rtx (operands[0]))));
12596 return 1; /* DONE */
12599 /* Swap, force into registers, or otherwise massage the two operands
12600 to an sse comparison with a mask result. Thus we differ a bit from
12601 ix86_prepare_fp_compare_args which expects to produce a flags result.
12603 The DEST operand exists to help determine whether to commute commutative
12604 operators. The POP0/POP1 operands are updated in place. The new
12605 comparison code is returned, or UNKNOWN if not implementable. */
12607 static enum rtx_code
12608 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
12609 rtx *pop0, rtx *pop1)
12617 /* We have no LTGT as an operator. We could implement it with
12618 NE & ORDERED, but this requires an extra temporary. It's
12619 not clear that it's worth it. */
12626 /* These are supported directly. */
12633 /* For commutative operators, try to canonicalize the destination
12634 operand to be first in the comparison - this helps reload to
12635 avoid extra moves. */
12636 if (!dest || !rtx_equal_p (dest, *pop1))
12644 /* These are not supported directly. Swap the comparison operands
12645 to transform into something that is supported. */
12649 code = swap_condition (code);
12653 gcc_unreachable ();
12659 /* Detect conditional moves that exactly match min/max operational
12660 semantics. Note that this is IEEE safe, as long as we don't
12661 interchange the operands.
12663 Returns FALSE if this conditional move doesn't match a MIN/MAX,
12664 and TRUE if the operation is successful and instructions are emitted. */
12667 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
12668 rtx cmp_op1, rtx if_true, rtx if_false)
12670 enum machine_mode mode;
12676 else if (code == UNGE)
12679 if_true = if_false;
12685 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
12687 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
12692 mode = GET_MODE (dest);
12694 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
12695 but MODE may be a vector mode and thus not appropriate. */
12696 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
12698 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
12701 if_true = force_reg (mode, if_true);
12702 v = gen_rtvec (2, if_true, if_false);
12703 tmp = gen_rtx_UNSPEC (mode, v, u);
12707 code = is_min ? SMIN : SMAX;
12708 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
12711 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
12715 /* Expand an sse vector comparison. Return the register with the result. */
12718 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
12719 rtx op_true, rtx op_false)
12721 enum machine_mode mode = GET_MODE (dest);
12724 cmp_op0 = force_reg (mode, cmp_op0);
12725 if (!nonimmediate_operand (cmp_op1, mode))
12726 cmp_op1 = force_reg (mode, cmp_op1);
12729 || reg_overlap_mentioned_p (dest, op_true)
12730 || reg_overlap_mentioned_p (dest, op_false))
12731 dest = gen_reg_rtx (mode);
12733 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
12734 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12739 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
12740 operations. This is used for both scalar and vector conditional moves. */
12743 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
12745 enum machine_mode mode = GET_MODE (dest);
12748 if (op_false == CONST0_RTX (mode))
12750 op_true = force_reg (mode, op_true);
12751 x = gen_rtx_AND (mode, cmp, op_true);
12752 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12754 else if (op_true == CONST0_RTX (mode))
12756 op_false = force_reg (mode, op_false);
12757 x = gen_rtx_NOT (mode, cmp);
12758 x = gen_rtx_AND (mode, x, op_false);
12759 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12763 op_true = force_reg (mode, op_true);
12764 op_false = force_reg (mode, op_false);
12766 t2 = gen_reg_rtx (mode);
12768 t3 = gen_reg_rtx (mode);
12772 x = gen_rtx_AND (mode, op_true, cmp);
12773 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
12775 x = gen_rtx_NOT (mode, cmp);
12776 x = gen_rtx_AND (mode, x, op_false);
12777 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
12779 x = gen_rtx_IOR (mode, t3, t2);
12780 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12784 /* Expand a floating-point conditional move. Return true if successful. */
12787 ix86_expand_fp_movcc (rtx operands[])
12789 enum machine_mode mode = GET_MODE (operands[0]);
12790 enum rtx_code code = GET_CODE (operands[1]);
12791 rtx tmp, compare_op, second_test, bypass_test;
12793 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
12795 enum machine_mode cmode;
12797 /* Since we've no cmove for sse registers, don't force bad register
12798 allocation just to gain access to it. Deny movcc when the
12799 comparison mode doesn't match the move mode. */
12800 cmode = GET_MODE (ix86_compare_op0);
12801 if (cmode == VOIDmode)
12802 cmode = GET_MODE (ix86_compare_op1);
12806 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
12808 &ix86_compare_op1);
12809 if (code == UNKNOWN)
12812 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
12813 ix86_compare_op1, operands[2],
12817 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
12818 ix86_compare_op1, operands[2], operands[3]);
12819 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
12823 /* The floating point conditional move instructions don't directly
12824 support conditions resulting from a signed integer comparison. */
12826 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12828 /* The floating point conditional move instructions don't directly
12829 support signed integer comparisons. */
12831 if (!fcmov_comparison_operator (compare_op, VOIDmode))
12833 gcc_assert (!second_test && !bypass_test);
12834 tmp = gen_reg_rtx (QImode);
12835 ix86_expand_setcc (code, tmp);
12837 ix86_compare_op0 = tmp;
12838 ix86_compare_op1 = const0_rtx;
12839 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12841 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12843 tmp = gen_reg_rtx (mode);
12844 emit_move_insn (tmp, operands[3]);
12847 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
12849 tmp = gen_reg_rtx (mode);
12850 emit_move_insn (tmp, operands[2]);
12854 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12855 gen_rtx_IF_THEN_ELSE (mode, compare_op,
12856 operands[2], operands[3])));
12858 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12859 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
12860 operands[3], operands[0])));
12862 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12863 gen_rtx_IF_THEN_ELSE (mode, second_test,
12864 operands[2], operands[0])));
12869 /* Expand a floating-point vector conditional move; a vcond operation
12870 rather than a movcc operation. */
12873 ix86_expand_fp_vcond (rtx operands[])
12875 enum rtx_code code = GET_CODE (operands[3]);
12878 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
12879 &operands[4], &operands[5]);
12880 if (code == UNKNOWN)
12883 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
12884 operands[5], operands[1], operands[2]))
12887 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
12888 operands[1], operands[2]);
12889 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
12893 /* Expand a signed/unsigned integral vector conditional move. */
12896 ix86_expand_int_vcond (rtx operands[])
12898 enum machine_mode mode = GET_MODE (operands[0]);
12899 enum rtx_code code = GET_CODE (operands[3]);
12900 bool negate = false;
12903 cop0 = operands[4];
12904 cop1 = operands[5];
12906 /* Canonicalize the comparison to EQ, GT, GTU. */
12917 code = reverse_condition (code);
12923 code = reverse_condition (code);
12929 code = swap_condition (code);
12930 x = cop0, cop0 = cop1, cop1 = x;
12934 gcc_unreachable ();
12937 /* Only SSE4.1/SSE4.2 supports V2DImode. */
12938 if (mode == V2DImode)
12943 /* SSE4.1 supports EQ. */
12944 if (!TARGET_SSE4_1)
12950 /* SSE4.2 supports GT/GTU. */
12951 if (!TARGET_SSE4_2)
12956 gcc_unreachable ();
12960 /* Unsigned parallel compare is not supported by the hardware. Play some
12961 tricks to turn this into a signed comparison against 0. */
12964 cop0 = force_reg (mode, cop0);
12973 /* Perform a parallel modulo subtraction. */
12974 t1 = gen_reg_rtx (mode);
12975 emit_insn ((mode == V4SImode
12977 : gen_subv2di3) (t1, cop0, cop1));
12979 /* Extract the original sign bit of op0. */
12980 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
12982 t2 = gen_reg_rtx (mode);
12983 emit_insn ((mode == V4SImode
12985 : gen_andv2di3) (t2, cop0, mask));
12987 /* XOR it back into the result of the subtraction. This results
12988 in the sign bit set iff we saw unsigned underflow. */
12989 x = gen_reg_rtx (mode);
12990 emit_insn ((mode == V4SImode
12992 : gen_xorv2di3) (x, t1, t2));
13000 /* Perform a parallel unsigned saturating subtraction. */
13001 x = gen_reg_rtx (mode);
13002 emit_insn (gen_rtx_SET (VOIDmode, x,
13003 gen_rtx_US_MINUS (mode, cop0, cop1)));
13010 gcc_unreachable ();
13014 cop1 = CONST0_RTX (mode);
13017 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13018 operands[1+negate], operands[2-negate]);
13020 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13021 operands[2-negate]);
13025 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13026 true if we should do zero extension, else sign extension. HIGH_P is
13027 true if we want the N/2 high elements, else the low elements. */
13030 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13032 enum machine_mode imode = GET_MODE (operands[1]);
13033 rtx (*unpack)(rtx, rtx, rtx);
13040 unpack = gen_vec_interleave_highv16qi;
13042 unpack = gen_vec_interleave_lowv16qi;
13046 unpack = gen_vec_interleave_highv8hi;
13048 unpack = gen_vec_interleave_lowv8hi;
13052 unpack = gen_vec_interleave_highv4si;
13054 unpack = gen_vec_interleave_lowv4si;
13057 gcc_unreachable ();
13060 dest = gen_lowpart (imode, operands[0]);
13063 se = force_reg (imode, CONST0_RTX (imode));
13065 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13066 operands[1], pc_rtx, pc_rtx);
13068 emit_insn (unpack (dest, operands[1], se));
13071 /* This function performs the same task as ix86_expand_sse_unpack,
13072 but with SSE4.1 instructions. */
13075 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13077 enum machine_mode imode = GET_MODE (operands[1]);
13078 rtx (*unpack)(rtx, rtx);
13085 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13087 unpack = gen_sse4_1_extendv8qiv8hi2;
13091 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13093 unpack = gen_sse4_1_extendv4hiv4si2;
13097 unpack = gen_sse4_1_zero_extendv2siv2di2;
13099 unpack = gen_sse4_1_extendv2siv2di2;
13102 gcc_unreachable ();
13105 dest = operands[0];
13108 /* Shift higher 8 bytes to lower 8 bytes. */
13109 src = gen_reg_rtx (imode);
13110 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13111 gen_lowpart (TImode, operands[1]),
13117 emit_insn (unpack (dest, src));
13120 /* Expand conditional increment or decrement using adb/sbb instructions.
13121 The default case using setcc followed by the conditional move can be
13122 done by generic code. */
13124 ix86_expand_int_addcc (rtx operands[])
13126 enum rtx_code code = GET_CODE (operands[1]);
13128 rtx val = const0_rtx;
13129 bool fpcmp = false;
13130 enum machine_mode mode = GET_MODE (operands[0]);
13132 if (operands[3] != const1_rtx
13133 && operands[3] != constm1_rtx)
13135 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13136 ix86_compare_op1, &compare_op))
13138 code = GET_CODE (compare_op);
13140 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13141 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13144 code = ix86_fp_compare_code_to_integer (code);
13151 PUT_CODE (compare_op,
13152 reverse_condition_maybe_unordered
13153 (GET_CODE (compare_op)));
13155 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
13157 PUT_MODE (compare_op, mode);
13159 /* Construct either adc or sbb insn. */
13160 if ((code == LTU) == (operands[3] == constm1_rtx))
13162 switch (GET_MODE (operands[0]))
13165 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
13168 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
13171 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
13174 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13177 gcc_unreachable ();
13182 switch (GET_MODE (operands[0]))
13185 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
13188 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
13191 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
13194 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13197 gcc_unreachable ();
13200 return 1; /* DONE */
13204 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
13205 works for floating pointer parameters and nonoffsetable memories.
13206 For pushes, it returns just stack offsets; the values will be saved
13207 in the right order. Maximally three parts are generated. */
13210 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
13215 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
13217 size = (GET_MODE_SIZE (mode) + 4) / 8;
13219 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
13220 gcc_assert (size >= 2 && size <= 3);
13222 /* Optimize constant pool reference to immediates. This is used by fp
13223 moves, that force all constants to memory to allow combining. */
13224 if (MEM_P (operand) && MEM_READONLY_P (operand))
13226 rtx tmp = maybe_get_pool_constant (operand);
13231 if (MEM_P (operand) && !offsettable_memref_p (operand))
13233 /* The only non-offsetable memories we handle are pushes. */
13234 int ok = push_operand (operand, VOIDmode);
13238 operand = copy_rtx (operand);
13239 PUT_MODE (operand, Pmode);
13240 parts[0] = parts[1] = parts[2] = operand;
13244 if (GET_CODE (operand) == CONST_VECTOR)
13246 enum machine_mode imode = int_mode_for_mode (mode);
13247 /* Caution: if we looked through a constant pool memory above,
13248 the operand may actually have a different mode now. That's
13249 ok, since we want to pun this all the way back to an integer. */
13250 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
13251 gcc_assert (operand != NULL);
13257 if (mode == DImode)
13258 split_di (&operand, 1, &parts[0], &parts[1]);
13261 if (REG_P (operand))
13263 gcc_assert (reload_completed);
13264 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
13265 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
13267 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
13269 else if (offsettable_memref_p (operand))
13271 operand = adjust_address (operand, SImode, 0);
13272 parts[0] = operand;
13273 parts[1] = adjust_address (operand, SImode, 4);
13275 parts[2] = adjust_address (operand, SImode, 8);
13277 else if (GET_CODE (operand) == CONST_DOUBLE)
13282 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13286 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
13287 parts[2] = gen_int_mode (l[2], SImode);
13290 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
13293 gcc_unreachable ();
13295 parts[1] = gen_int_mode (l[1], SImode);
13296 parts[0] = gen_int_mode (l[0], SImode);
13299 gcc_unreachable ();
13304 if (mode == TImode)
13305 split_ti (&operand, 1, &parts[0], &parts[1]);
13306 if (mode == XFmode || mode == TFmode)
13308 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
13309 if (REG_P (operand))
13311 gcc_assert (reload_completed);
13312 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
13313 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
13315 else if (offsettable_memref_p (operand))
13317 operand = adjust_address (operand, DImode, 0);
13318 parts[0] = operand;
13319 parts[1] = adjust_address (operand, upper_mode, 8);
13321 else if (GET_CODE (operand) == CONST_DOUBLE)
13326 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13327 real_to_target (l, &r, mode);
13329 /* Do not use shift by 32 to avoid warning on 32bit systems. */
13330 if (HOST_BITS_PER_WIDE_INT >= 64)
13333 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
13334 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
13337 parts[0] = immed_double_const (l[0], l[1], DImode);
13339 if (upper_mode == SImode)
13340 parts[1] = gen_int_mode (l[2], SImode);
13341 else if (HOST_BITS_PER_WIDE_INT >= 64)
13344 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
13345 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
13348 parts[1] = immed_double_const (l[2], l[3], DImode);
13351 gcc_unreachable ();
13358 /* Emit insns to perform a move or push of DI, DF, and XF values.
13359 Return false when normal moves are needed; true when all required
13360 insns have been emitted. Operands 2-4 contain the input values
13361 int the correct order; operands 5-7 contain the output values. */
13364 ix86_split_long_move (rtx operands[])
13369 int collisions = 0;
13370 enum machine_mode mode = GET_MODE (operands[0]);
13372 /* The DFmode expanders may ask us to move double.
13373 For 64bit target this is single move. By hiding the fact
13374 here we simplify i386.md splitters. */
13375 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
13377 /* Optimize constant pool reference to immediates. This is used by
13378 fp moves, that force all constants to memory to allow combining. */
13380 if (MEM_P (operands[1])
13381 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13382 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
13383 operands[1] = get_pool_constant (XEXP (operands[1], 0));
13384 if (push_operand (operands[0], VOIDmode))
13386 operands[0] = copy_rtx (operands[0]);
13387 PUT_MODE (operands[0], Pmode);
13390 operands[0] = gen_lowpart (DImode, operands[0]);
13391 operands[1] = gen_lowpart (DImode, operands[1]);
13392 emit_move_insn (operands[0], operands[1]);
13396 /* The only non-offsettable memory we handle is push. */
13397 if (push_operand (operands[0], VOIDmode))
13400 gcc_assert (!MEM_P (operands[0])
13401 || offsettable_memref_p (operands[0]));
13403 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
13404 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
13406 /* When emitting push, take care for source operands on the stack. */
13407 if (push && MEM_P (operands[1])
13408 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
13411 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
13412 XEXP (part[1][2], 0));
13413 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
13414 XEXP (part[1][1], 0));
13417 /* We need to do copy in the right order in case an address register
13418 of the source overlaps the destination. */
13419 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
13421 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
13423 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
13426 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
13429 /* Collision in the middle part can be handled by reordering. */
13430 if (collisions == 1 && nparts == 3
13431 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
13434 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
13435 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
13438 /* If there are more collisions, we can't handle it by reordering.
13439 Do an lea to the last part and use only one colliding move. */
13440 else if (collisions > 1)
13446 base = part[0][nparts - 1];
13448 /* Handle the case when the last part isn't valid for lea.
13449 Happens in 64-bit mode storing the 12-byte XFmode. */
13450 if (GET_MODE (base) != Pmode)
13451 base = gen_rtx_REG (Pmode, REGNO (base));
13453 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
13454 part[1][0] = replace_equiv_address (part[1][0], base);
13455 part[1][1] = replace_equiv_address (part[1][1],
13456 plus_constant (base, UNITS_PER_WORD));
13458 part[1][2] = replace_equiv_address (part[1][2],
13459 plus_constant (base, 8));
13469 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
13470 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
13471 emit_move_insn (part[0][2], part[1][2]);
13476 /* In 64bit mode we don't have 32bit push available. In case this is
13477 register, it is OK - we will just use larger counterpart. We also
13478 retype memory - these comes from attempt to avoid REX prefix on
13479 moving of second half of TFmode value. */
13480 if (GET_MODE (part[1][1]) == SImode)
13482 switch (GET_CODE (part[1][1]))
13485 part[1][1] = adjust_address (part[1][1], DImode, 0);
13489 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
13493 gcc_unreachable ();
13496 if (GET_MODE (part[1][0]) == SImode)
13497 part[1][0] = part[1][1];
13500 emit_move_insn (part[0][1], part[1][1]);
13501 emit_move_insn (part[0][0], part[1][0]);
13505 /* Choose correct order to not overwrite the source before it is copied. */
13506 if ((REG_P (part[0][0])
13507 && REG_P (part[1][1])
13508 && (REGNO (part[0][0]) == REGNO (part[1][1])
13510 && REGNO (part[0][0]) == REGNO (part[1][2]))))
13512 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
13516 operands[2] = part[0][2];
13517 operands[3] = part[0][1];
13518 operands[4] = part[0][0];
13519 operands[5] = part[1][2];
13520 operands[6] = part[1][1];
13521 operands[7] = part[1][0];
13525 operands[2] = part[0][1];
13526 operands[3] = part[0][0];
13527 operands[5] = part[1][1];
13528 operands[6] = part[1][0];
13535 operands[2] = part[0][0];
13536 operands[3] = part[0][1];
13537 operands[4] = part[0][2];
13538 operands[5] = part[1][0];
13539 operands[6] = part[1][1];
13540 operands[7] = part[1][2];
13544 operands[2] = part[0][0];
13545 operands[3] = part[0][1];
13546 operands[5] = part[1][0];
13547 operands[6] = part[1][1];
13551 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
13554 if (CONST_INT_P (operands[5])
13555 && operands[5] != const0_rtx
13556 && REG_P (operands[2]))
13558 if (CONST_INT_P (operands[6])
13559 && INTVAL (operands[6]) == INTVAL (operands[5]))
13560 operands[6] = operands[2];
13563 && CONST_INT_P (operands[7])
13564 && INTVAL (operands[7]) == INTVAL (operands[5]))
13565 operands[7] = operands[2];
13569 && CONST_INT_P (operands[6])
13570 && operands[6] != const0_rtx
13571 && REG_P (operands[3])
13572 && CONST_INT_P (operands[7])
13573 && INTVAL (operands[7]) == INTVAL (operands[6]))
13574 operands[7] = operands[3];
13577 emit_move_insn (operands[2], operands[5]);
13578 emit_move_insn (operands[3], operands[6]);
13580 emit_move_insn (operands[4], operands[7]);
13585 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
13586 left shift by a constant, either using a single shift or
13587 a sequence of add instructions. */
13590 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
13594 emit_insn ((mode == DImode
13596 : gen_adddi3) (operand, operand, operand));
13598 else if (!optimize_size
13599 && count * ix86_cost->add <= ix86_cost->shift_const)
13602 for (i=0; i<count; i++)
13604 emit_insn ((mode == DImode
13606 : gen_adddi3) (operand, operand, operand));
13610 emit_insn ((mode == DImode
13612 : gen_ashldi3) (operand, operand, GEN_INT (count)));
13616 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
13618 rtx low[2], high[2];
13620 const int single_width = mode == DImode ? 32 : 64;
13622 if (CONST_INT_P (operands[2]))
13624 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
13625 count = INTVAL (operands[2]) & (single_width * 2 - 1);
13627 if (count >= single_width)
13629 emit_move_insn (high[0], low[1]);
13630 emit_move_insn (low[0], const0_rtx);
13632 if (count > single_width)
13633 ix86_expand_ashl_const (high[0], count - single_width, mode);
13637 if (!rtx_equal_p (operands[0], operands[1]))
13638 emit_move_insn (operands[0], operands[1]);
13639 emit_insn ((mode == DImode
13641 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
13642 ix86_expand_ashl_const (low[0], count, mode);
13647 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13649 if (operands[1] == const1_rtx)
13651 /* Assuming we've chosen a QImode capable registers, then 1 << N
13652 can be done with two 32/64-bit shifts, no branches, no cmoves. */
13653 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
13655 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
13657 ix86_expand_clear (low[0]);
13658 ix86_expand_clear (high[0]);
13659 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
13661 d = gen_lowpart (QImode, low[0]);
13662 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
13663 s = gen_rtx_EQ (QImode, flags, const0_rtx);
13664 emit_insn (gen_rtx_SET (VOIDmode, d, s));
13666 d = gen_lowpart (QImode, high[0]);
13667 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
13668 s = gen_rtx_NE (QImode, flags, const0_rtx);
13669 emit_insn (gen_rtx_SET (VOIDmode, d, s));
13672 /* Otherwise, we can get the same results by manually performing
13673 a bit extract operation on bit 5/6, and then performing the two
13674 shifts. The two methods of getting 0/1 into low/high are exactly
13675 the same size. Avoiding the shift in the bit extract case helps
13676 pentium4 a bit; no one else seems to care much either way. */
13681 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
13682 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
13684 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
13685 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
13687 emit_insn ((mode == DImode
13689 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
13690 emit_insn ((mode == DImode
13692 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
13693 emit_move_insn (low[0], high[0]);
13694 emit_insn ((mode == DImode
13696 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
13699 emit_insn ((mode == DImode
13701 : gen_ashldi3) (low[0], low[0], operands[2]));
13702 emit_insn ((mode == DImode
13704 : gen_ashldi3) (high[0], high[0], operands[2]));
13708 if (operands[1] == constm1_rtx)
13710 /* For -1 << N, we can avoid the shld instruction, because we
13711 know that we're shifting 0...31/63 ones into a -1. */
13712 emit_move_insn (low[0], constm1_rtx);
13714 emit_move_insn (high[0], low[0]);
13716 emit_move_insn (high[0], constm1_rtx);
13720 if (!rtx_equal_p (operands[0], operands[1]))
13721 emit_move_insn (operands[0], operands[1]);
13723 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13724 emit_insn ((mode == DImode
13726 : gen_x86_64_shld) (high[0], low[0], operands[2]));
13729 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
13731 if (TARGET_CMOVE && scratch)
13733 ix86_expand_clear (scratch);
13734 emit_insn ((mode == DImode
13735 ? gen_x86_shift_adj_1
13736 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
13739 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
13743 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
13745 rtx low[2], high[2];
13747 const int single_width = mode == DImode ? 32 : 64;
13749 if (CONST_INT_P (operands[2]))
13751 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
13752 count = INTVAL (operands[2]) & (single_width * 2 - 1);
13754 if (count == single_width * 2 - 1)
13756 emit_move_insn (high[0], high[1]);
13757 emit_insn ((mode == DImode
13759 : gen_ashrdi3) (high[0], high[0],
13760 GEN_INT (single_width - 1)));
13761 emit_move_insn (low[0], high[0]);
13764 else if (count >= single_width)
13766 emit_move_insn (low[0], high[1]);
13767 emit_move_insn (high[0], low[0]);
13768 emit_insn ((mode == DImode
13770 : gen_ashrdi3) (high[0], high[0],
13771 GEN_INT (single_width - 1)));
13772 if (count > single_width)
13773 emit_insn ((mode == DImode
13775 : gen_ashrdi3) (low[0], low[0],
13776 GEN_INT (count - single_width)));
13780 if (!rtx_equal_p (operands[0], operands[1]))
13781 emit_move_insn (operands[0], operands[1]);
13782 emit_insn ((mode == DImode
13784 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
13785 emit_insn ((mode == DImode
13787 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
13792 if (!rtx_equal_p (operands[0], operands[1]))
13793 emit_move_insn (operands[0], operands[1]);
13795 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13797 emit_insn ((mode == DImode
13799 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
13800 emit_insn ((mode == DImode
13802 : gen_ashrdi3) (high[0], high[0], operands[2]));
13804 if (TARGET_CMOVE && scratch)
13806 emit_move_insn (scratch, high[0]);
13807 emit_insn ((mode == DImode
13809 : gen_ashrdi3) (scratch, scratch,
13810 GEN_INT (single_width - 1)));
13811 emit_insn ((mode == DImode
13812 ? gen_x86_shift_adj_1
13813 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
13817 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
13822 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
13824 rtx low[2], high[2];
13826 const int single_width = mode == DImode ? 32 : 64;
13828 if (CONST_INT_P (operands[2]))
13830 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
13831 count = INTVAL (operands[2]) & (single_width * 2 - 1);
13833 if (count >= single_width)
13835 emit_move_insn (low[0], high[1]);
13836 ix86_expand_clear (high[0]);
13838 if (count > single_width)
13839 emit_insn ((mode == DImode
13841 : gen_lshrdi3) (low[0], low[0],
13842 GEN_INT (count - single_width)));
13846 if (!rtx_equal_p (operands[0], operands[1]))
13847 emit_move_insn (operands[0], operands[1]);
13848 emit_insn ((mode == DImode
13850 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
13851 emit_insn ((mode == DImode
13853 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
13858 if (!rtx_equal_p (operands[0], operands[1]))
13859 emit_move_insn (operands[0], operands[1]);
13861 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13863 emit_insn ((mode == DImode
13865 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
13866 emit_insn ((mode == DImode
13868 : gen_lshrdi3) (high[0], high[0], operands[2]));
13870 /* Heh. By reversing the arguments, we can reuse this pattern. */
13871 if (TARGET_CMOVE && scratch)
13873 ix86_expand_clear (scratch);
13874 emit_insn ((mode == DImode
13875 ? gen_x86_shift_adj_1
13876 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
13880 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
13884 /* Predict just emitted jump instruction to be taken with probability PROB. */
13886 predict_jump (int prob)
13888 rtx insn = get_last_insn ();
13889 gcc_assert (JUMP_P (insn));
13891 = gen_rtx_EXPR_LIST (REG_BR_PROB,
13896 /* Helper function for the string operations below. Dest VARIABLE whether
13897 it is aligned to VALUE bytes. If true, jump to the label. */
13899 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
13901 rtx label = gen_label_rtx ();
13902 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
13903 if (GET_MODE (variable) == DImode)
13904 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
13906 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
13907 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
13910 predict_jump (REG_BR_PROB_BASE * 50 / 100);
13912 predict_jump (REG_BR_PROB_BASE * 90 / 100);
13916 /* Adjust COUNTER by the VALUE. */
13918 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
13920 if (GET_MODE (countreg) == DImode)
13921 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
13923 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
13926 /* Zero extend possibly SImode EXP to Pmode register. */
13928 ix86_zero_extend_to_Pmode (rtx exp)
13931 if (GET_MODE (exp) == VOIDmode)
13932 return force_reg (Pmode, exp);
13933 if (GET_MODE (exp) == Pmode)
13934 return copy_to_mode_reg (Pmode, exp);
13935 r = gen_reg_rtx (Pmode);
13936 emit_insn (gen_zero_extendsidi2 (r, exp));
13940 /* Divide COUNTREG by SCALE. */
13942 scale_counter (rtx countreg, int scale)
13945 rtx piece_size_mask;
13949 if (CONST_INT_P (countreg))
13950 return GEN_INT (INTVAL (countreg) / scale);
13951 gcc_assert (REG_P (countreg));
13953 piece_size_mask = GEN_INT (scale - 1);
13954 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
13955 GEN_INT (exact_log2 (scale)),
13956 NULL, 1, OPTAB_DIRECT);
13960 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
13961 DImode for constant loop counts. */
13963 static enum machine_mode
13964 counter_mode (rtx count_exp)
13966 if (GET_MODE (count_exp) != VOIDmode)
13967 return GET_MODE (count_exp);
13968 if (GET_CODE (count_exp) != CONST_INT)
13970 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
13975 /* When SRCPTR is non-NULL, output simple loop to move memory
13976 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
13977 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
13978 equivalent loop to set memory by VALUE (supposed to be in MODE).
13980 The size is rounded down to whole number of chunk size moved at once.
13981 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
13985 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
13986 rtx destptr, rtx srcptr, rtx value,
13987 rtx count, enum machine_mode mode, int unroll,
13990 rtx out_label, top_label, iter, tmp;
13991 enum machine_mode iter_mode = counter_mode (count);
13992 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
13993 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
13999 top_label = gen_label_rtx ();
14000 out_label = gen_label_rtx ();
14001 iter = gen_reg_rtx (iter_mode);
14003 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14004 NULL, 1, OPTAB_DIRECT);
14005 /* Those two should combine. */
14006 if (piece_size == const1_rtx)
14008 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14010 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14012 emit_move_insn (iter, const0_rtx);
14014 emit_label (top_label);
14016 tmp = convert_modes (Pmode, iter_mode, iter, true);
14017 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14018 destmem = change_address (destmem, mode, x_addr);
14022 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14023 srcmem = change_address (srcmem, mode, y_addr);
14025 /* When unrolling for chips that reorder memory reads and writes,
14026 we can save registers by using single temporary.
14027 Also using 4 temporaries is overkill in 32bit mode. */
14028 if (!TARGET_64BIT && 0)
14030 for (i = 0; i < unroll; i++)
14035 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14037 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14039 emit_move_insn (destmem, srcmem);
14045 gcc_assert (unroll <= 4);
14046 for (i = 0; i < unroll; i++)
14048 tmpreg[i] = gen_reg_rtx (mode);
14052 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14054 emit_move_insn (tmpreg[i], srcmem);
14056 for (i = 0; i < unroll; i++)
14061 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14063 emit_move_insn (destmem, tmpreg[i]);
14068 for (i = 0; i < unroll; i++)
14072 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14073 emit_move_insn (destmem, value);
14076 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14077 true, OPTAB_LIB_WIDEN);
14079 emit_move_insn (iter, tmp);
14081 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14083 if (expected_size != -1)
14085 expected_size /= GET_MODE_SIZE (mode) * unroll;
14086 if (expected_size == 0)
14088 else if (expected_size > REG_BR_PROB_BASE)
14089 predict_jump (REG_BR_PROB_BASE - 1);
14091 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14094 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14095 iter = ix86_zero_extend_to_Pmode (iter);
14096 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14097 true, OPTAB_LIB_WIDEN);
14098 if (tmp != destptr)
14099 emit_move_insn (destptr, tmp);
14102 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14103 true, OPTAB_LIB_WIDEN);
14105 emit_move_insn (srcptr, tmp);
14107 emit_label (out_label);
14110 /* Output "rep; mov" instruction.
14111 Arguments have same meaning as for previous function */
14113 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
14114 rtx destptr, rtx srcptr,
14116 enum machine_mode mode)
14122 /* If the size is known, it is shorter to use rep movs. */
14123 if (mode == QImode && CONST_INT_P (count)
14124 && !(INTVAL (count) & 3))
14127 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14128 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14129 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
14130 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
14131 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14132 if (mode != QImode)
14134 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14135 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14136 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14137 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
14138 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14139 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
14143 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14144 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
14146 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
14150 /* Output "rep; stos" instruction.
14151 Arguments have same meaning as for previous function */
14153 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
14155 enum machine_mode mode)
14160 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14161 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14162 value = force_reg (mode, gen_lowpart (mode, value));
14163 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14164 if (mode != QImode)
14166 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14167 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14168 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14171 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14172 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
14176 emit_strmov (rtx destmem, rtx srcmem,
14177 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
14179 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
14180 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
14181 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14184 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
14186 expand_movmem_epilogue (rtx destmem, rtx srcmem,
14187 rtx destptr, rtx srcptr, rtx count, int max_size)
14190 if (CONST_INT_P (count))
14192 HOST_WIDE_INT countval = INTVAL (count);
14195 if ((countval & 0x10) && max_size > 16)
14199 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14200 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
14203 gcc_unreachable ();
14206 if ((countval & 0x08) && max_size > 8)
14209 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14212 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14213 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
14217 if ((countval & 0x04) && max_size > 4)
14219 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14222 if ((countval & 0x02) && max_size > 2)
14224 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14227 if ((countval & 0x01) && max_size > 1)
14229 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14236 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14237 count, 1, OPTAB_DIRECT);
14238 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14239 count, QImode, 1, 4);
14243 /* When there are stringops, we can cheaply increase dest and src pointers.
14244 Otherwise we save code size by maintaining offset (zero is readily
14245 available from preceding rep operation) and using x86 addressing modes.
14247 if (TARGET_SINGLE_STRINGOP)
14251 rtx label = ix86_expand_aligntest (count, 4, true);
14252 src = change_address (srcmem, SImode, srcptr);
14253 dest = change_address (destmem, SImode, destptr);
14254 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14255 emit_label (label);
14256 LABEL_NUSES (label) = 1;
14260 rtx label = ix86_expand_aligntest (count, 2, true);
14261 src = change_address (srcmem, HImode, srcptr);
14262 dest = change_address (destmem, HImode, destptr);
14263 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14264 emit_label (label);
14265 LABEL_NUSES (label) = 1;
14269 rtx label = ix86_expand_aligntest (count, 1, true);
14270 src = change_address (srcmem, QImode, srcptr);
14271 dest = change_address (destmem, QImode, destptr);
14272 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14273 emit_label (label);
14274 LABEL_NUSES (label) = 1;
14279 rtx offset = force_reg (Pmode, const0_rtx);
14284 rtx label = ix86_expand_aligntest (count, 4, true);
14285 src = change_address (srcmem, SImode, srcptr);
14286 dest = change_address (destmem, SImode, destptr);
14287 emit_move_insn (dest, src);
14288 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
14289 true, OPTAB_LIB_WIDEN);
14291 emit_move_insn (offset, tmp);
14292 emit_label (label);
14293 LABEL_NUSES (label) = 1;
14297 rtx label = ix86_expand_aligntest (count, 2, true);
14298 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14299 src = change_address (srcmem, HImode, tmp);
14300 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14301 dest = change_address (destmem, HImode, tmp);
14302 emit_move_insn (dest, src);
14303 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
14304 true, OPTAB_LIB_WIDEN);
14306 emit_move_insn (offset, tmp);
14307 emit_label (label);
14308 LABEL_NUSES (label) = 1;
14312 rtx label = ix86_expand_aligntest (count, 1, true);
14313 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14314 src = change_address (srcmem, QImode, tmp);
14315 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14316 dest = change_address (destmem, QImode, tmp);
14317 emit_move_insn (dest, src);
14318 emit_label (label);
14319 LABEL_NUSES (label) = 1;
14324 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14326 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
14327 rtx count, int max_size)
14330 expand_simple_binop (counter_mode (count), AND, count,
14331 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
14332 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
14333 gen_lowpart (QImode, value), count, QImode,
14337 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14339 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
14343 if (CONST_INT_P (count))
14345 HOST_WIDE_INT countval = INTVAL (count);
14348 if ((countval & 0x10) && max_size > 16)
14352 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14353 emit_insn (gen_strset (destptr, dest, value));
14354 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
14355 emit_insn (gen_strset (destptr, dest, value));
14358 gcc_unreachable ();
14361 if ((countval & 0x08) && max_size > 8)
14365 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14366 emit_insn (gen_strset (destptr, dest, value));
14370 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
14371 emit_insn (gen_strset (destptr, dest, value));
14372 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
14373 emit_insn (gen_strset (destptr, dest, value));
14377 if ((countval & 0x04) && max_size > 4)
14379 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
14380 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
14383 if ((countval & 0x02) && max_size > 2)
14385 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
14386 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
14389 if ((countval & 0x01) && max_size > 1)
14391 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
14392 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
14399 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
14404 rtx label = ix86_expand_aligntest (count, 16, true);
14407 dest = change_address (destmem, DImode, destptr);
14408 emit_insn (gen_strset (destptr, dest, value));
14409 emit_insn (gen_strset (destptr, dest, value));
14413 dest = change_address (destmem, SImode, destptr);
14414 emit_insn (gen_strset (destptr, dest, value));
14415 emit_insn (gen_strset (destptr, dest, value));
14416 emit_insn (gen_strset (destptr, dest, value));
14417 emit_insn (gen_strset (destptr, dest, value));
14419 emit_label (label);
14420 LABEL_NUSES (label) = 1;
14424 rtx label = ix86_expand_aligntest (count, 8, true);
14427 dest = change_address (destmem, DImode, destptr);
14428 emit_insn (gen_strset (destptr, dest, value));
14432 dest = change_address (destmem, SImode, destptr);
14433 emit_insn (gen_strset (destptr, dest, value));
14434 emit_insn (gen_strset (destptr, dest, value));
14436 emit_label (label);
14437 LABEL_NUSES (label) = 1;
14441 rtx label = ix86_expand_aligntest (count, 4, true);
14442 dest = change_address (destmem, SImode, destptr);
14443 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
14444 emit_label (label);
14445 LABEL_NUSES (label) = 1;
14449 rtx label = ix86_expand_aligntest (count, 2, true);
14450 dest = change_address (destmem, HImode, destptr);
14451 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
14452 emit_label (label);
14453 LABEL_NUSES (label) = 1;
14457 rtx label = ix86_expand_aligntest (count, 1, true);
14458 dest = change_address (destmem, QImode, destptr);
14459 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
14460 emit_label (label);
14461 LABEL_NUSES (label) = 1;
14465 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
14466 DESIRED_ALIGNMENT. */
14468 expand_movmem_prologue (rtx destmem, rtx srcmem,
14469 rtx destptr, rtx srcptr, rtx count,
14470 int align, int desired_alignment)
14472 if (align <= 1 && desired_alignment > 1)
14474 rtx label = ix86_expand_aligntest (destptr, 1, false);
14475 srcmem = change_address (srcmem, QImode, srcptr);
14476 destmem = change_address (destmem, QImode, destptr);
14477 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
14478 ix86_adjust_counter (count, 1);
14479 emit_label (label);
14480 LABEL_NUSES (label) = 1;
14482 if (align <= 2 && desired_alignment > 2)
14484 rtx label = ix86_expand_aligntest (destptr, 2, false);
14485 srcmem = change_address (srcmem, HImode, srcptr);
14486 destmem = change_address (destmem, HImode, destptr);
14487 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
14488 ix86_adjust_counter (count, 2);
14489 emit_label (label);
14490 LABEL_NUSES (label) = 1;
14492 if (align <= 4 && desired_alignment > 4)
14494 rtx label = ix86_expand_aligntest (destptr, 4, false);
14495 srcmem = change_address (srcmem, SImode, srcptr);
14496 destmem = change_address (destmem, SImode, destptr);
14497 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
14498 ix86_adjust_counter (count, 4);
14499 emit_label (label);
14500 LABEL_NUSES (label) = 1;
14502 gcc_assert (desired_alignment <= 8);
14505 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
14506 DESIRED_ALIGNMENT. */
14508 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
14509 int align, int desired_alignment)
14511 if (align <= 1 && desired_alignment > 1)
14513 rtx label = ix86_expand_aligntest (destptr, 1, false);
14514 destmem = change_address (destmem, QImode, destptr);
14515 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
14516 ix86_adjust_counter (count, 1);
14517 emit_label (label);
14518 LABEL_NUSES (label) = 1;
14520 if (align <= 2 && desired_alignment > 2)
14522 rtx label = ix86_expand_aligntest (destptr, 2, false);
14523 destmem = change_address (destmem, HImode, destptr);
14524 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
14525 ix86_adjust_counter (count, 2);
14526 emit_label (label);
14527 LABEL_NUSES (label) = 1;
14529 if (align <= 4 && desired_alignment > 4)
14531 rtx label = ix86_expand_aligntest (destptr, 4, false);
14532 destmem = change_address (destmem, SImode, destptr);
14533 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
14534 ix86_adjust_counter (count, 4);
14535 emit_label (label);
14536 LABEL_NUSES (label) = 1;
14538 gcc_assert (desired_alignment <= 8);
14541 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
14542 static enum stringop_alg
14543 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
14544 int *dynamic_check)
14546 const struct stringop_algs * algs;
14548 *dynamic_check = -1;
14550 algs = &ix86_cost->memset[TARGET_64BIT != 0];
14552 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
14553 if (stringop_alg != no_stringop)
14554 return stringop_alg;
14555 /* rep; movq or rep; movl is the smallest variant. */
14556 else if (optimize_size)
14558 if (!count || (count & 3))
14559 return rep_prefix_1_byte;
14561 return rep_prefix_4_byte;
14563 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
14565 else if (expected_size != -1 && expected_size < 4)
14566 return loop_1_byte;
14567 else if (expected_size != -1)
14570 enum stringop_alg alg = libcall;
14571 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
14573 gcc_assert (algs->size[i].max);
14574 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
14576 if (algs->size[i].alg != libcall)
14577 alg = algs->size[i].alg;
14578 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
14579 last non-libcall inline algorithm. */
14580 if (TARGET_INLINE_ALL_STRINGOPS)
14582 /* When the current size is best to be copied by a libcall,
14583 but we are still forced to inline, run the heuristic bellow
14584 that will pick code for medium sized blocks. */
14585 if (alg != libcall)
14590 return algs->size[i].alg;
14593 gcc_assert (TARGET_INLINE_ALL_STRINGOPS);
14595 /* When asked to inline the call anyway, try to pick meaningful choice.
14596 We look for maximal size of block that is faster to copy by hand and
14597 take blocks of at most of that size guessing that average size will
14598 be roughly half of the block.
14600 If this turns out to be bad, we might simply specify the preferred
14601 choice in ix86_costs. */
14602 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
14603 && algs->unknown_size == libcall)
14606 enum stringop_alg alg;
14609 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
14610 if (algs->size[i].alg != libcall && algs->size[i].alg)
14611 max = algs->size[i].max;
14614 alg = decide_alg (count, max / 2, memset, dynamic_check);
14615 gcc_assert (*dynamic_check == -1);
14616 gcc_assert (alg != libcall);
14617 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
14618 *dynamic_check = max;
14621 return algs->unknown_size;
14624 /* Decide on alignment. We know that the operand is already aligned to ALIGN
14625 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
14627 decide_alignment (int align,
14628 enum stringop_alg alg,
14631 int desired_align = 0;
14635 gcc_unreachable ();
14637 case unrolled_loop:
14638 desired_align = GET_MODE_SIZE (Pmode);
14640 case rep_prefix_8_byte:
14643 case rep_prefix_4_byte:
14644 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14645 copying whole cacheline at once. */
14646 if (TARGET_PENTIUMPRO)
14651 case rep_prefix_1_byte:
14652 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14653 copying whole cacheline at once. */
14654 if (TARGET_PENTIUMPRO)
14668 if (desired_align < align)
14669 desired_align = align;
14670 if (expected_size != -1 && expected_size < 4)
14671 desired_align = align;
14672 return desired_align;
14675 /* Return the smallest power of 2 greater than VAL. */
14677 smallest_pow2_greater_than (int val)
14685 /* Expand string move (memcpy) operation. Use i386 string operations when
14686 profitable. expand_clrmem contains similar code. The code depends upon
14687 architecture, block size and alignment, but always has the same
14690 1) Prologue guard: Conditional that jumps up to epilogues for small
14691 blocks that can be handled by epilogue alone. This is faster but
14692 also needed for correctness, since prologue assume the block is larger
14693 than the desired alignment.
14695 Optional dynamic check for size and libcall for large
14696 blocks is emitted here too, with -minline-stringops-dynamically.
14698 2) Prologue: copy first few bytes in order to get destination aligned
14699 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
14700 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
14701 We emit either a jump tree on power of two sized blocks, or a byte loop.
14703 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
14704 with specified algorithm.
14706 4) Epilogue: code copying tail of the block that is too small to be
14707 handled by main body (or up to size guarded by prologue guard). */
14710 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
14711 rtx expected_align_exp, rtx expected_size_exp)
14717 rtx jump_around_label = NULL;
14718 HOST_WIDE_INT align = 1;
14719 unsigned HOST_WIDE_INT count = 0;
14720 HOST_WIDE_INT expected_size = -1;
14721 int size_needed = 0, epilogue_size_needed;
14722 int desired_align = 0;
14723 enum stringop_alg alg;
14726 if (CONST_INT_P (align_exp))
14727 align = INTVAL (align_exp);
14728 /* i386 can do misaligned access on reasonably increased cost. */
14729 if (CONST_INT_P (expected_align_exp)
14730 && INTVAL (expected_align_exp) > align)
14731 align = INTVAL (expected_align_exp);
14732 if (CONST_INT_P (count_exp))
14733 count = expected_size = INTVAL (count_exp);
14734 if (CONST_INT_P (expected_size_exp) && count == 0)
14735 expected_size = INTVAL (expected_size_exp);
14737 /* Step 0: Decide on preferred algorithm, desired alignment and
14738 size of chunks to be copied by main loop. */
14740 alg = decide_alg (count, expected_size, false, &dynamic_check);
14741 desired_align = decide_alignment (align, alg, expected_size);
14743 if (!TARGET_ALIGN_STRINGOPS)
14744 align = desired_align;
14746 if (alg == libcall)
14748 gcc_assert (alg != no_stringop);
14750 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
14751 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
14752 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
14757 gcc_unreachable ();
14759 size_needed = GET_MODE_SIZE (Pmode);
14761 case unrolled_loop:
14762 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
14764 case rep_prefix_8_byte:
14767 case rep_prefix_4_byte:
14770 case rep_prefix_1_byte:
14776 epilogue_size_needed = size_needed;
14778 /* Step 1: Prologue guard. */
14780 /* Alignment code needs count to be in register. */
14781 if (CONST_INT_P (count_exp) && desired_align > align)
14783 enum machine_mode mode = SImode;
14784 if (TARGET_64BIT && (count & ~0xffffffff))
14786 count_exp = force_reg (mode, count_exp);
14788 gcc_assert (desired_align >= 1 && align >= 1);
14790 /* Ensure that alignment prologue won't copy past end of block. */
14791 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
14793 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
14794 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
14795 Make sure it is power of 2. */
14796 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
14798 label = gen_label_rtx ();
14799 emit_cmp_and_jump_insns (count_exp,
14800 GEN_INT (epilogue_size_needed),
14801 LTU, 0, counter_mode (count_exp), 1, label);
14802 if (GET_CODE (count_exp) == CONST_INT)
14804 else if (expected_size == -1 || expected_size < epilogue_size_needed)
14805 predict_jump (REG_BR_PROB_BASE * 60 / 100);
14807 predict_jump (REG_BR_PROB_BASE * 20 / 100);
14809 /* Emit code to decide on runtime whether library call or inline should be
14811 if (dynamic_check != -1)
14813 rtx hot_label = gen_label_rtx ();
14814 jump_around_label = gen_label_rtx ();
14815 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
14816 LEU, 0, GET_MODE (count_exp), 1, hot_label);
14817 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14818 emit_block_move_via_libcall (dst, src, count_exp, false);
14819 emit_jump (jump_around_label);
14820 emit_label (hot_label);
14823 /* Step 2: Alignment prologue. */
14825 if (desired_align > align)
14827 /* Except for the first move in epilogue, we no longer know
14828 constant offset in aliasing info. It don't seems to worth
14829 the pain to maintain it for the first move, so throw away
14831 src = change_address (src, BLKmode, srcreg);
14832 dst = change_address (dst, BLKmode, destreg);
14833 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
14836 if (label && size_needed == 1)
14838 emit_label (label);
14839 LABEL_NUSES (label) = 1;
14843 /* Step 3: Main loop. */
14849 gcc_unreachable ();
14851 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
14852 count_exp, QImode, 1, expected_size);
14855 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
14856 count_exp, Pmode, 1, expected_size);
14858 case unrolled_loop:
14859 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
14860 registers for 4 temporaries anyway. */
14861 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
14862 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
14865 case rep_prefix_8_byte:
14866 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
14869 case rep_prefix_4_byte:
14870 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
14873 case rep_prefix_1_byte:
14874 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
14878 /* Adjust properly the offset of src and dest memory for aliasing. */
14879 if (CONST_INT_P (count_exp))
14881 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
14882 (count / size_needed) * size_needed);
14883 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
14884 (count / size_needed) * size_needed);
14888 src = change_address (src, BLKmode, srcreg);
14889 dst = change_address (dst, BLKmode, destreg);
14892 /* Step 4: Epilogue to copy the remaining bytes. */
14896 /* When the main loop is done, COUNT_EXP might hold original count,
14897 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
14898 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
14899 bytes. Compensate if needed. */
14901 if (size_needed < epilogue_size_needed)
14904 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
14905 GEN_INT (size_needed - 1), count_exp, 1,
14907 if (tmp != count_exp)
14908 emit_move_insn (count_exp, tmp);
14910 emit_label (label);
14911 LABEL_NUSES (label) = 1;
14914 if (count_exp != const0_rtx && epilogue_size_needed > 1)
14915 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
14916 epilogue_size_needed);
14917 if (jump_around_label)
14918 emit_label (jump_around_label);
14922 /* Helper function for memcpy. For QImode value 0xXY produce
14923 0xXYXYXYXY of wide specified by MODE. This is essentially
14924 a * 0x10101010, but we can do slightly better than
14925 synth_mult by unwinding the sequence by hand on CPUs with
14928 promote_duplicated_reg (enum machine_mode mode, rtx val)
14930 enum machine_mode valmode = GET_MODE (val);
14932 int nops = mode == DImode ? 3 : 2;
14934 gcc_assert (mode == SImode || mode == DImode);
14935 if (val == const0_rtx)
14936 return copy_to_mode_reg (mode, const0_rtx);
14937 if (CONST_INT_P (val))
14939 HOST_WIDE_INT v = INTVAL (val) & 255;
14943 if (mode == DImode)
14944 v |= (v << 16) << 16;
14945 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
14948 if (valmode == VOIDmode)
14950 if (valmode != QImode)
14951 val = gen_lowpart (QImode, val);
14952 if (mode == QImode)
14954 if (!TARGET_PARTIAL_REG_STALL)
14956 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
14957 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
14958 <= (ix86_cost->shift_const + ix86_cost->add) * nops
14959 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
14961 rtx reg = convert_modes (mode, QImode, val, true);
14962 tmp = promote_duplicated_reg (mode, const1_rtx);
14963 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
14968 rtx reg = convert_modes (mode, QImode, val, true);
14970 if (!TARGET_PARTIAL_REG_STALL)
14971 if (mode == SImode)
14972 emit_insn (gen_movsi_insv_1 (reg, reg));
14974 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
14977 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
14978 NULL, 1, OPTAB_DIRECT);
14980 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
14982 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
14983 NULL, 1, OPTAB_DIRECT);
14984 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
14985 if (mode == SImode)
14987 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
14988 NULL, 1, OPTAB_DIRECT);
14989 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
14994 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
14995 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
14996 alignment from ALIGN to DESIRED_ALIGN. */
14998 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15003 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15004 promoted_val = promote_duplicated_reg (DImode, val);
15005 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15006 promoted_val = promote_duplicated_reg (SImode, val);
15007 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15008 promoted_val = promote_duplicated_reg (HImode, val);
15010 promoted_val = val;
15012 return promoted_val;
15015 /* Expand string clear operation (bzero). Use i386 string operations when
15016 profitable. See expand_movmem comment for explanation of individual
15017 steps performed. */
15019 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15020 rtx expected_align_exp, rtx expected_size_exp)
15025 rtx jump_around_label = NULL;
15026 HOST_WIDE_INT align = 1;
15027 unsigned HOST_WIDE_INT count = 0;
15028 HOST_WIDE_INT expected_size = -1;
15029 int size_needed = 0, epilogue_size_needed;
15030 int desired_align = 0;
15031 enum stringop_alg alg;
15032 rtx promoted_val = NULL;
15033 bool force_loopy_epilogue = false;
15036 if (CONST_INT_P (align_exp))
15037 align = INTVAL (align_exp);
15038 /* i386 can do misaligned access on reasonably increased cost. */
15039 if (CONST_INT_P (expected_align_exp)
15040 && INTVAL (expected_align_exp) > align)
15041 align = INTVAL (expected_align_exp);
15042 if (CONST_INT_P (count_exp))
15043 count = expected_size = INTVAL (count_exp);
15044 if (CONST_INT_P (expected_size_exp) && count == 0)
15045 expected_size = INTVAL (expected_size_exp);
15047 /* Step 0: Decide on preferred algorithm, desired alignment and
15048 size of chunks to be copied by main loop. */
15050 alg = decide_alg (count, expected_size, true, &dynamic_check);
15051 desired_align = decide_alignment (align, alg, expected_size);
15053 if (!TARGET_ALIGN_STRINGOPS)
15054 align = desired_align;
15056 if (alg == libcall)
15058 gcc_assert (alg != no_stringop);
15060 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
15061 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15066 gcc_unreachable ();
15068 size_needed = GET_MODE_SIZE (Pmode);
15070 case unrolled_loop:
15071 size_needed = GET_MODE_SIZE (Pmode) * 4;
15073 case rep_prefix_8_byte:
15076 case rep_prefix_4_byte:
15079 case rep_prefix_1_byte:
15084 epilogue_size_needed = size_needed;
15086 /* Step 1: Prologue guard. */
15088 /* Alignment code needs count to be in register. */
15089 if (CONST_INT_P (count_exp) && desired_align > align)
15091 enum machine_mode mode = SImode;
15092 if (TARGET_64BIT && (count & ~0xffffffff))
15094 count_exp = force_reg (mode, count_exp);
15096 /* Do the cheap promotion to allow better CSE across the
15097 main loop and epilogue (ie one load of the big constant in the
15098 front of all code. */
15099 if (CONST_INT_P (val_exp))
15100 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15101 desired_align, align);
15102 /* Ensure that alignment prologue won't copy past end of block. */
15103 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15105 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15106 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15107 Make sure it is power of 2. */
15108 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15110 /* To improve performance of small blocks, we jump around the VAL
15111 promoting mode. This mean that if the promoted VAL is not constant,
15112 we might not use it in the epilogue and have to use byte
15114 if (epilogue_size_needed > 2 && !promoted_val)
15115 force_loopy_epilogue = true;
15116 label = gen_label_rtx ();
15117 emit_cmp_and_jump_insns (count_exp,
15118 GEN_INT (epilogue_size_needed),
15119 LTU, 0, counter_mode (count_exp), 1, label);
15120 if (GET_CODE (count_exp) == CONST_INT)
15122 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
15123 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15125 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15127 if (dynamic_check != -1)
15129 rtx hot_label = gen_label_rtx ();
15130 jump_around_label = gen_label_rtx ();
15131 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15132 LEU, 0, counter_mode (count_exp), 1, hot_label);
15133 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15134 set_storage_via_libcall (dst, count_exp, val_exp, false);
15135 emit_jump (jump_around_label);
15136 emit_label (hot_label);
15139 /* Step 2: Alignment prologue. */
15141 /* Do the expensive promotion once we branched off the small blocks. */
15143 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15144 desired_align, align);
15145 gcc_assert (desired_align >= 1 && align >= 1);
15147 if (desired_align > align)
15149 /* Except for the first move in epilogue, we no longer know
15150 constant offset in aliasing info. It don't seems to worth
15151 the pain to maintain it for the first move, so throw away
15153 dst = change_address (dst, BLKmode, destreg);
15154 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
15157 if (label && size_needed == 1)
15159 emit_label (label);
15160 LABEL_NUSES (label) = 1;
15164 /* Step 3: Main loop. */
15170 gcc_unreachable ();
15172 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15173 count_exp, QImode, 1, expected_size);
15176 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15177 count_exp, Pmode, 1, expected_size);
15179 case unrolled_loop:
15180 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15181 count_exp, Pmode, 4, expected_size);
15183 case rep_prefix_8_byte:
15184 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15187 case rep_prefix_4_byte:
15188 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15191 case rep_prefix_1_byte:
15192 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15196 /* Adjust properly the offset of src and dest memory for aliasing. */
15197 if (CONST_INT_P (count_exp))
15198 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15199 (count / size_needed) * size_needed);
15201 dst = change_address (dst, BLKmode, destreg);
15203 /* Step 4: Epilogue to copy the remaining bytes. */
15207 /* When the main loop is done, COUNT_EXP might hold original count,
15208 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15209 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15210 bytes. Compensate if needed. */
15212 if (size_needed < desired_align - align)
15215 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15216 GEN_INT (size_needed - 1), count_exp, 1,
15218 size_needed = desired_align - align + 1;
15219 if (tmp != count_exp)
15220 emit_move_insn (count_exp, tmp);
15222 emit_label (label);
15223 LABEL_NUSES (label) = 1;
15225 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15227 if (force_loopy_epilogue)
15228 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
15231 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
15234 if (jump_around_label)
15235 emit_label (jump_around_label);
15239 /* Expand the appropriate insns for doing strlen if not just doing
15242 out = result, initialized with the start address
15243 align_rtx = alignment of the address.
15244 scratch = scratch register, initialized with the startaddress when
15245 not aligned, otherwise undefined
15247 This is just the body. It needs the initializations mentioned above and
15248 some address computing at the end. These things are done in i386.md. */
15251 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
15255 rtx align_2_label = NULL_RTX;
15256 rtx align_3_label = NULL_RTX;
15257 rtx align_4_label = gen_label_rtx ();
15258 rtx end_0_label = gen_label_rtx ();
15260 rtx tmpreg = gen_reg_rtx (SImode);
15261 rtx scratch = gen_reg_rtx (SImode);
15265 if (CONST_INT_P (align_rtx))
15266 align = INTVAL (align_rtx);
15268 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
15270 /* Is there a known alignment and is it less than 4? */
15273 rtx scratch1 = gen_reg_rtx (Pmode);
15274 emit_move_insn (scratch1, out);
15275 /* Is there a known alignment and is it not 2? */
15278 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
15279 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
15281 /* Leave just the 3 lower bits. */
15282 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
15283 NULL_RTX, 0, OPTAB_WIDEN);
15285 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15286 Pmode, 1, align_4_label);
15287 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
15288 Pmode, 1, align_2_label);
15289 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
15290 Pmode, 1, align_3_label);
15294 /* Since the alignment is 2, we have to check 2 or 0 bytes;
15295 check if is aligned to 4 - byte. */
15297 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
15298 NULL_RTX, 0, OPTAB_WIDEN);
15300 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15301 Pmode, 1, align_4_label);
15304 mem = change_address (src, QImode, out);
15306 /* Now compare the bytes. */
15308 /* Compare the first n unaligned byte on a byte per byte basis. */
15309 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
15310 QImode, 1, end_0_label);
15312 /* Increment the address. */
15314 emit_insn (gen_adddi3 (out, out, const1_rtx));
15316 emit_insn (gen_addsi3 (out, out, const1_rtx));
15318 /* Not needed with an alignment of 2 */
15321 emit_label (align_2_label);
15323 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
15327 emit_insn (gen_adddi3 (out, out, const1_rtx));
15329 emit_insn (gen_addsi3 (out, out, const1_rtx));
15331 emit_label (align_3_label);
15334 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
15338 emit_insn (gen_adddi3 (out, out, const1_rtx));
15340 emit_insn (gen_addsi3 (out, out, const1_rtx));
15343 /* Generate loop to check 4 bytes at a time. It is not a good idea to
15344 align this loop. It gives only huge programs, but does not help to
15346 emit_label (align_4_label);
15348 mem = change_address (src, SImode, out);
15349 emit_move_insn (scratch, mem);
15351 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
15353 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
15355 /* This formula yields a nonzero result iff one of the bytes is zero.
15356 This saves three branches inside loop and many cycles. */
15358 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
15359 emit_insn (gen_one_cmplsi2 (scratch, scratch));
15360 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
15361 emit_insn (gen_andsi3 (tmpreg, tmpreg,
15362 gen_int_mode (0x80808080, SImode)));
15363 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
15368 rtx reg = gen_reg_rtx (SImode);
15369 rtx reg2 = gen_reg_rtx (Pmode);
15370 emit_move_insn (reg, tmpreg);
15371 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
15373 /* If zero is not in the first two bytes, move two bytes forward. */
15374 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
15375 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15376 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15377 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
15378 gen_rtx_IF_THEN_ELSE (SImode, tmp,
15381 /* Emit lea manually to avoid clobbering of flags. */
15382 emit_insn (gen_rtx_SET (SImode, reg2,
15383 gen_rtx_PLUS (Pmode, out, const2_rtx)));
15385 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15386 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15387 emit_insn (gen_rtx_SET (VOIDmode, out,
15388 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
15395 rtx end_2_label = gen_label_rtx ();
15396 /* Is zero in the first two bytes? */
15398 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
15399 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15400 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15401 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15402 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
15404 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15405 JUMP_LABEL (tmp) = end_2_label;
15407 /* Not in the first two. Move two bytes forward. */
15408 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
15410 emit_insn (gen_adddi3 (out, out, const2_rtx));
15412 emit_insn (gen_addsi3 (out, out, const2_rtx));
15414 emit_label (end_2_label);
15418 /* Avoid branch in fixing the byte. */
15419 tmpreg = gen_lowpart (QImode, tmpreg);
15420 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
15421 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
15423 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
15425 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
15427 emit_label (end_0_label);
15430 /* Expand strlen. */
15433 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
15435 rtx addr, scratch1, scratch2, scratch3, scratch4;
15437 /* The generic case of strlen expander is long. Avoid it's
15438 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
15440 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
15441 && !TARGET_INLINE_ALL_STRINGOPS
15443 && (!CONST_INT_P (align) || INTVAL (align) < 4))
15446 addr = force_reg (Pmode, XEXP (src, 0));
15447 scratch1 = gen_reg_rtx (Pmode);
15449 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
15452 /* Well it seems that some optimizer does not combine a call like
15453 foo(strlen(bar), strlen(bar));
15454 when the move and the subtraction is done here. It does calculate
15455 the length just once when these instructions are done inside of
15456 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
15457 often used and I use one fewer register for the lifetime of
15458 output_strlen_unroll() this is better. */
15460 emit_move_insn (out, addr);
15462 ix86_expand_strlensi_unroll_1 (out, src, align);
15464 /* strlensi_unroll_1 returns the address of the zero at the end of
15465 the string, like memchr(), so compute the length by subtracting
15466 the start address. */
15468 emit_insn (gen_subdi3 (out, out, addr));
15470 emit_insn (gen_subsi3 (out, out, addr));
15475 scratch2 = gen_reg_rtx (Pmode);
15476 scratch3 = gen_reg_rtx (Pmode);
15477 scratch4 = force_reg (Pmode, constm1_rtx);
15479 emit_move_insn (scratch3, addr);
15480 eoschar = force_reg (QImode, eoschar);
15482 src = replace_equiv_address_nv (src, scratch3);
15484 /* If .md starts supporting :P, this can be done in .md. */
15485 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
15486 scratch4), UNSPEC_SCAS);
15487 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
15490 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
15491 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
15495 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
15496 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
15502 /* For given symbol (function) construct code to compute address of it's PLT
15503 entry in large x86-64 PIC model. */
15505 construct_plt_address (rtx symbol)
15507 rtx tmp = gen_reg_rtx (Pmode);
15508 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
15510 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15511 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
15513 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
15514 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
15519 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
15520 rtx callarg2 ATTRIBUTE_UNUSED,
15521 rtx pop, int sibcall)
15523 rtx use = NULL, call;
15525 if (pop == const0_rtx)
15527 gcc_assert (!TARGET_64BIT || !pop);
15529 if (TARGET_MACHO && !TARGET_64BIT)
15532 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
15533 fnaddr = machopic_indirect_call_target (fnaddr);
15538 /* Static functions and indirect calls don't need the pic register. */
15539 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
15540 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
15541 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
15542 use_reg (&use, pic_offset_table_rtx);
15545 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
15547 rtx al = gen_rtx_REG (QImode, 0);
15548 emit_move_insn (al, callarg2);
15549 use_reg (&use, al);
15552 if (ix86_cmodel == CM_LARGE_PIC
15553 && GET_CODE (fnaddr) == MEM
15554 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
15555 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
15556 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
15557 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
15559 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
15560 fnaddr = gen_rtx_MEM (QImode, fnaddr);
15562 if (sibcall && TARGET_64BIT
15563 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
15566 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
15567 fnaddr = gen_rtx_REG (Pmode, R11_REG);
15568 emit_move_insn (fnaddr, addr);
15569 fnaddr = gen_rtx_MEM (QImode, fnaddr);
15572 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
15574 call = gen_rtx_SET (VOIDmode, retval, call);
15577 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
15578 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
15579 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
15582 call = emit_call_insn (call);
15584 CALL_INSN_FUNCTION_USAGE (call) = use;
15588 /* Clear stack slot assignments remembered from previous functions.
15589 This is called from INIT_EXPANDERS once before RTL is emitted for each
15592 static struct machine_function *
15593 ix86_init_machine_status (void)
15595 struct machine_function *f;
15597 f = GGC_CNEW (struct machine_function);
15598 f->use_fast_prologue_epilogue_nregs = -1;
15599 f->tls_descriptor_call_expanded_p = 0;
15604 /* Return a MEM corresponding to a stack slot with mode MODE.
15605 Allocate a new slot if necessary.
15607 The RTL for a function can have several slots available: N is
15608 which slot to use. */
15611 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
15613 struct stack_local_entry *s;
15615 gcc_assert (n < MAX_386_STACK_LOCALS);
15617 for (s = ix86_stack_locals; s; s = s->next)
15618 if (s->mode == mode && s->n == n)
15619 return copy_rtx (s->rtl);
15621 s = (struct stack_local_entry *)
15622 ggc_alloc (sizeof (struct stack_local_entry));
15625 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
15627 s->next = ix86_stack_locals;
15628 ix86_stack_locals = s;
15632 /* Construct the SYMBOL_REF for the tls_get_addr function. */
15634 static GTY(()) rtx ix86_tls_symbol;
15636 ix86_tls_get_addr (void)
15639 if (!ix86_tls_symbol)
15641 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
15642 (TARGET_ANY_GNU_TLS
15644 ? "___tls_get_addr"
15645 : "__tls_get_addr");
15648 return ix86_tls_symbol;
15651 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
15653 static GTY(()) rtx ix86_tls_module_base_symbol;
15655 ix86_tls_module_base (void)
15658 if (!ix86_tls_module_base_symbol)
15660 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
15661 "_TLS_MODULE_BASE_");
15662 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
15663 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
15666 return ix86_tls_module_base_symbol;
15669 /* Calculate the length of the memory address in the instruction
15670 encoding. Does not include the one-byte modrm, opcode, or prefix. */
15673 memory_address_length (rtx addr)
15675 struct ix86_address parts;
15676 rtx base, index, disp;
15680 if (GET_CODE (addr) == PRE_DEC
15681 || GET_CODE (addr) == POST_INC
15682 || GET_CODE (addr) == PRE_MODIFY
15683 || GET_CODE (addr) == POST_MODIFY)
15686 ok = ix86_decompose_address (addr, &parts);
15689 if (parts.base && GET_CODE (parts.base) == SUBREG)
15690 parts.base = SUBREG_REG (parts.base);
15691 if (parts.index && GET_CODE (parts.index) == SUBREG)
15692 parts.index = SUBREG_REG (parts.index);
15695 index = parts.index;
15700 - esp as the base always wants an index,
15701 - ebp as the base always wants a displacement. */
15703 /* Register Indirect. */
15704 if (base && !index && !disp)
15706 /* esp (for its index) and ebp (for its displacement) need
15707 the two-byte modrm form. */
15708 if (addr == stack_pointer_rtx
15709 || addr == arg_pointer_rtx
15710 || addr == frame_pointer_rtx
15711 || addr == hard_frame_pointer_rtx)
15715 /* Direct Addressing. */
15716 else if (disp && !base && !index)
15721 /* Find the length of the displacement constant. */
15724 if (base && satisfies_constraint_K (disp))
15729 /* ebp always wants a displacement. */
15730 else if (base == hard_frame_pointer_rtx)
15733 /* An index requires the two-byte modrm form.... */
15735 /* ...like esp, which always wants an index. */
15736 || base == stack_pointer_rtx
15737 || base == arg_pointer_rtx
15738 || base == frame_pointer_rtx)
15745 /* Compute default value for "length_immediate" attribute. When SHORTFORM
15746 is set, expect that insn have 8bit immediate alternative. */
15748 ix86_attr_length_immediate_default (rtx insn, int shortform)
15752 extract_insn_cached (insn);
15753 for (i = recog_data.n_operands - 1; i >= 0; --i)
15754 if (CONSTANT_P (recog_data.operand[i]))
15757 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
15761 switch (get_attr_mode (insn))
15772 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
15777 fatal_insn ("unknown insn mode", insn);
15783 /* Compute default value for "length_address" attribute. */
15785 ix86_attr_length_address_default (rtx insn)
15789 if (get_attr_type (insn) == TYPE_LEA)
15791 rtx set = PATTERN (insn);
15793 if (GET_CODE (set) == PARALLEL)
15794 set = XVECEXP (set, 0, 0);
15796 gcc_assert (GET_CODE (set) == SET);
15798 return memory_address_length (SET_SRC (set));
15801 extract_insn_cached (insn);
15802 for (i = recog_data.n_operands - 1; i >= 0; --i)
15803 if (MEM_P (recog_data.operand[i]))
15805 return memory_address_length (XEXP (recog_data.operand[i], 0));
15811 /* Return the maximum number of instructions a cpu can issue. */
15814 ix86_issue_rate (void)
15818 case PROCESSOR_PENTIUM:
15822 case PROCESSOR_PENTIUMPRO:
15823 case PROCESSOR_PENTIUM4:
15824 case PROCESSOR_ATHLON:
15826 case PROCESSOR_AMDFAM10:
15827 case PROCESSOR_NOCONA:
15828 case PROCESSOR_GENERIC32:
15829 case PROCESSOR_GENERIC64:
15832 case PROCESSOR_CORE2:
15840 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
15841 by DEP_INSN and nothing set by DEP_INSN. */
15844 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
15848 /* Simplify the test for uninteresting insns. */
15849 if (insn_type != TYPE_SETCC
15850 && insn_type != TYPE_ICMOV
15851 && insn_type != TYPE_FCMOV
15852 && insn_type != TYPE_IBR)
15855 if ((set = single_set (dep_insn)) != 0)
15857 set = SET_DEST (set);
15860 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
15861 && XVECLEN (PATTERN (dep_insn), 0) == 2
15862 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
15863 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
15865 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
15866 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
15871 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
15874 /* This test is true if the dependent insn reads the flags but
15875 not any other potentially set register. */
15876 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
15879 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
15885 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
15886 address with operands set by DEP_INSN. */
15889 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
15893 if (insn_type == TYPE_LEA
15896 addr = PATTERN (insn);
15898 if (GET_CODE (addr) == PARALLEL)
15899 addr = XVECEXP (addr, 0, 0);
15901 gcc_assert (GET_CODE (addr) == SET);
15903 addr = SET_SRC (addr);
15908 extract_insn_cached (insn);
15909 for (i = recog_data.n_operands - 1; i >= 0; --i)
15910 if (MEM_P (recog_data.operand[i]))
15912 addr = XEXP (recog_data.operand[i], 0);
15919 return modified_in_p (addr, dep_insn);
15923 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
15925 enum attr_type insn_type, dep_insn_type;
15926 enum attr_memory memory;
15928 int dep_insn_code_number;
15930 /* Anti and output dependencies have zero cost on all CPUs. */
15931 if (REG_NOTE_KIND (link) != 0)
15934 dep_insn_code_number = recog_memoized (dep_insn);
15936 /* If we can't recognize the insns, we can't really do anything. */
15937 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
15940 insn_type = get_attr_type (insn);
15941 dep_insn_type = get_attr_type (dep_insn);
15945 case PROCESSOR_PENTIUM:
15946 /* Address Generation Interlock adds a cycle of latency. */
15947 if (ix86_agi_dependent (insn, dep_insn, insn_type))
15950 /* ??? Compares pair with jump/setcc. */
15951 if (ix86_flags_dependent (insn, dep_insn, insn_type))
15954 /* Floating point stores require value to be ready one cycle earlier. */
15955 if (insn_type == TYPE_FMOV
15956 && get_attr_memory (insn) == MEMORY_STORE
15957 && !ix86_agi_dependent (insn, dep_insn, insn_type))
15961 case PROCESSOR_PENTIUMPRO:
15962 memory = get_attr_memory (insn);
15964 /* INT->FP conversion is expensive. */
15965 if (get_attr_fp_int_src (dep_insn))
15968 /* There is one cycle extra latency between an FP op and a store. */
15969 if (insn_type == TYPE_FMOV
15970 && (set = single_set (dep_insn)) != NULL_RTX
15971 && (set2 = single_set (insn)) != NULL_RTX
15972 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
15973 && MEM_P (SET_DEST (set2)))
15976 /* Show ability of reorder buffer to hide latency of load by executing
15977 in parallel with previous instruction in case
15978 previous instruction is not needed to compute the address. */
15979 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
15980 && !ix86_agi_dependent (insn, dep_insn, insn_type))
15982 /* Claim moves to take one cycle, as core can issue one load
15983 at time and the next load can start cycle later. */
15984 if (dep_insn_type == TYPE_IMOV
15985 || dep_insn_type == TYPE_FMOV)
15993 memory = get_attr_memory (insn);
15995 /* The esp dependency is resolved before the instruction is really
15997 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
15998 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16001 /* INT->FP conversion is expensive. */
16002 if (get_attr_fp_int_src (dep_insn))
16005 /* Show ability of reorder buffer to hide latency of load by executing
16006 in parallel with previous instruction in case
16007 previous instruction is not needed to compute the address. */
16008 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16009 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16011 /* Claim moves to take one cycle, as core can issue one load
16012 at time and the next load can start cycle later. */
16013 if (dep_insn_type == TYPE_IMOV
16014 || dep_insn_type == TYPE_FMOV)
16023 case PROCESSOR_ATHLON:
16025 case PROCESSOR_AMDFAM10:
16026 case PROCESSOR_GENERIC32:
16027 case PROCESSOR_GENERIC64:
16028 memory = get_attr_memory (insn);
16030 /* Show ability of reorder buffer to hide latency of load by executing
16031 in parallel with previous instruction in case
16032 previous instruction is not needed to compute the address. */
16033 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16034 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16036 enum attr_unit unit = get_attr_unit (insn);
16039 /* Because of the difference between the length of integer and
16040 floating unit pipeline preparation stages, the memory operands
16041 for floating point are cheaper.
16043 ??? For Athlon it the difference is most probably 2. */
16044 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16047 loadcost = TARGET_ATHLON ? 2 : 0;
16049 if (cost >= loadcost)
16062 /* How many alternative schedules to try. This should be as wide as the
16063 scheduling freedom in the DFA, but no wider. Making this value too
16064 large results extra work for the scheduler. */
16067 ia32_multipass_dfa_lookahead (void)
16069 if (ix86_tune == PROCESSOR_PENTIUM)
16072 if (ix86_tune == PROCESSOR_PENTIUMPRO
16073 || ix86_tune == PROCESSOR_K6)
16081 /* Compute the alignment given to a constant that is being placed in memory.
16082 EXP is the constant and ALIGN is the alignment that the object would
16084 The value of this function is used instead of that alignment to align
16088 ix86_constant_alignment (tree exp, int align)
16090 if (TREE_CODE (exp) == REAL_CST)
16092 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
16094 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
16097 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
16098 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
16099 return BITS_PER_WORD;
16104 /* Compute the alignment for a static variable.
16105 TYPE is the data type, and ALIGN is the alignment that
16106 the object would ordinarily have. The value of this function is used
16107 instead of that alignment to align the object. */
16110 ix86_data_alignment (tree type, int align)
16112 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
16114 if (AGGREGATE_TYPE_P (type)
16115 && TYPE_SIZE (type)
16116 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16117 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
16118 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
16119 && align < max_align)
16122 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16123 to 16byte boundary. */
16126 if (AGGREGATE_TYPE_P (type)
16127 && TYPE_SIZE (type)
16128 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16129 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
16130 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16134 if (TREE_CODE (type) == ARRAY_TYPE)
16136 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16138 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16141 else if (TREE_CODE (type) == COMPLEX_TYPE)
16144 if (TYPE_MODE (type) == DCmode && align < 64)
16146 if (TYPE_MODE (type) == XCmode && align < 128)
16149 else if ((TREE_CODE (type) == RECORD_TYPE
16150 || TREE_CODE (type) == UNION_TYPE
16151 || TREE_CODE (type) == QUAL_UNION_TYPE)
16152 && TYPE_FIELDS (type))
16154 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16156 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16159 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16160 || TREE_CODE (type) == INTEGER_TYPE)
16162 if (TYPE_MODE (type) == DFmode && align < 64)
16164 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16171 /* Compute the alignment for a local variable.
16172 TYPE is the data type, and ALIGN is the alignment that
16173 the object would ordinarily have. The value of this macro is used
16174 instead of that alignment to align the object. */
16177 ix86_local_alignment (tree type, int align)
16179 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16180 to 16byte boundary. */
16183 if (AGGREGATE_TYPE_P (type)
16184 && TYPE_SIZE (type)
16185 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16186 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
16187 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16190 if (TREE_CODE (type) == ARRAY_TYPE)
16192 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16194 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16197 else if (TREE_CODE (type) == COMPLEX_TYPE)
16199 if (TYPE_MODE (type) == DCmode && align < 64)
16201 if (TYPE_MODE (type) == XCmode && align < 128)
16204 else if ((TREE_CODE (type) == RECORD_TYPE
16205 || TREE_CODE (type) == UNION_TYPE
16206 || TREE_CODE (type) == QUAL_UNION_TYPE)
16207 && TYPE_FIELDS (type))
16209 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16211 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16214 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16215 || TREE_CODE (type) == INTEGER_TYPE)
16218 if (TYPE_MODE (type) == DFmode && align < 64)
16220 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16226 /* Emit RTL insns to initialize the variable parts of a trampoline.
16227 FNADDR is an RTX for the address of the function's pure code.
16228 CXT is an RTX for the static chain value for the function. */
16230 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
16234 /* Compute offset from the end of the jmp to the target function. */
16235 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
16236 plus_constant (tramp, 10),
16237 NULL_RTX, 1, OPTAB_DIRECT);
16238 emit_move_insn (gen_rtx_MEM (QImode, tramp),
16239 gen_int_mode (0xb9, QImode));
16240 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
16241 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
16242 gen_int_mode (0xe9, QImode));
16243 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
16248 /* Try to load address using shorter movl instead of movabs.
16249 We may want to support movq for kernel mode, but kernel does not use
16250 trampolines at the moment. */
16251 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
16253 fnaddr = copy_to_mode_reg (DImode, fnaddr);
16254 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16255 gen_int_mode (0xbb41, HImode));
16256 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
16257 gen_lowpart (SImode, fnaddr));
16262 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16263 gen_int_mode (0xbb49, HImode));
16264 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16268 /* Load static chain using movabs to r10. */
16269 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16270 gen_int_mode (0xba49, HImode));
16271 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16274 /* Jump to the r11 */
16275 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16276 gen_int_mode (0xff49, HImode));
16277 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
16278 gen_int_mode (0xe3, QImode));
16280 gcc_assert (offset <= TRAMPOLINE_SIZE);
16283 #ifdef ENABLE_EXECUTE_STACK
16284 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
16285 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
16289 /* Codes for all the SSE/MMX builtins. */
16292 IX86_BUILTIN_ADDPS,
16293 IX86_BUILTIN_ADDSS,
16294 IX86_BUILTIN_DIVPS,
16295 IX86_BUILTIN_DIVSS,
16296 IX86_BUILTIN_MULPS,
16297 IX86_BUILTIN_MULSS,
16298 IX86_BUILTIN_SUBPS,
16299 IX86_BUILTIN_SUBSS,
16301 IX86_BUILTIN_CMPEQPS,
16302 IX86_BUILTIN_CMPLTPS,
16303 IX86_BUILTIN_CMPLEPS,
16304 IX86_BUILTIN_CMPGTPS,
16305 IX86_BUILTIN_CMPGEPS,
16306 IX86_BUILTIN_CMPNEQPS,
16307 IX86_BUILTIN_CMPNLTPS,
16308 IX86_BUILTIN_CMPNLEPS,
16309 IX86_BUILTIN_CMPNGTPS,
16310 IX86_BUILTIN_CMPNGEPS,
16311 IX86_BUILTIN_CMPORDPS,
16312 IX86_BUILTIN_CMPUNORDPS,
16313 IX86_BUILTIN_CMPEQSS,
16314 IX86_BUILTIN_CMPLTSS,
16315 IX86_BUILTIN_CMPLESS,
16316 IX86_BUILTIN_CMPNEQSS,
16317 IX86_BUILTIN_CMPNLTSS,
16318 IX86_BUILTIN_CMPNLESS,
16319 IX86_BUILTIN_CMPNGTSS,
16320 IX86_BUILTIN_CMPNGESS,
16321 IX86_BUILTIN_CMPORDSS,
16322 IX86_BUILTIN_CMPUNORDSS,
16324 IX86_BUILTIN_COMIEQSS,
16325 IX86_BUILTIN_COMILTSS,
16326 IX86_BUILTIN_COMILESS,
16327 IX86_BUILTIN_COMIGTSS,
16328 IX86_BUILTIN_COMIGESS,
16329 IX86_BUILTIN_COMINEQSS,
16330 IX86_BUILTIN_UCOMIEQSS,
16331 IX86_BUILTIN_UCOMILTSS,
16332 IX86_BUILTIN_UCOMILESS,
16333 IX86_BUILTIN_UCOMIGTSS,
16334 IX86_BUILTIN_UCOMIGESS,
16335 IX86_BUILTIN_UCOMINEQSS,
16337 IX86_BUILTIN_CVTPI2PS,
16338 IX86_BUILTIN_CVTPS2PI,
16339 IX86_BUILTIN_CVTSI2SS,
16340 IX86_BUILTIN_CVTSI642SS,
16341 IX86_BUILTIN_CVTSS2SI,
16342 IX86_BUILTIN_CVTSS2SI64,
16343 IX86_BUILTIN_CVTTPS2PI,
16344 IX86_BUILTIN_CVTTSS2SI,
16345 IX86_BUILTIN_CVTTSS2SI64,
16347 IX86_BUILTIN_MAXPS,
16348 IX86_BUILTIN_MAXSS,
16349 IX86_BUILTIN_MINPS,
16350 IX86_BUILTIN_MINSS,
16352 IX86_BUILTIN_LOADUPS,
16353 IX86_BUILTIN_STOREUPS,
16354 IX86_BUILTIN_MOVSS,
16356 IX86_BUILTIN_MOVHLPS,
16357 IX86_BUILTIN_MOVLHPS,
16358 IX86_BUILTIN_LOADHPS,
16359 IX86_BUILTIN_LOADLPS,
16360 IX86_BUILTIN_STOREHPS,
16361 IX86_BUILTIN_STORELPS,
16363 IX86_BUILTIN_MASKMOVQ,
16364 IX86_BUILTIN_MOVMSKPS,
16365 IX86_BUILTIN_PMOVMSKB,
16367 IX86_BUILTIN_MOVNTPS,
16368 IX86_BUILTIN_MOVNTQ,
16370 IX86_BUILTIN_LOADDQU,
16371 IX86_BUILTIN_STOREDQU,
16373 IX86_BUILTIN_PACKSSWB,
16374 IX86_BUILTIN_PACKSSDW,
16375 IX86_BUILTIN_PACKUSWB,
16377 IX86_BUILTIN_PADDB,
16378 IX86_BUILTIN_PADDW,
16379 IX86_BUILTIN_PADDD,
16380 IX86_BUILTIN_PADDQ,
16381 IX86_BUILTIN_PADDSB,
16382 IX86_BUILTIN_PADDSW,
16383 IX86_BUILTIN_PADDUSB,
16384 IX86_BUILTIN_PADDUSW,
16385 IX86_BUILTIN_PSUBB,
16386 IX86_BUILTIN_PSUBW,
16387 IX86_BUILTIN_PSUBD,
16388 IX86_BUILTIN_PSUBQ,
16389 IX86_BUILTIN_PSUBSB,
16390 IX86_BUILTIN_PSUBSW,
16391 IX86_BUILTIN_PSUBUSB,
16392 IX86_BUILTIN_PSUBUSW,
16395 IX86_BUILTIN_PANDN,
16399 IX86_BUILTIN_PAVGB,
16400 IX86_BUILTIN_PAVGW,
16402 IX86_BUILTIN_PCMPEQB,
16403 IX86_BUILTIN_PCMPEQW,
16404 IX86_BUILTIN_PCMPEQD,
16405 IX86_BUILTIN_PCMPGTB,
16406 IX86_BUILTIN_PCMPGTW,
16407 IX86_BUILTIN_PCMPGTD,
16409 IX86_BUILTIN_PMADDWD,
16411 IX86_BUILTIN_PMAXSW,
16412 IX86_BUILTIN_PMAXUB,
16413 IX86_BUILTIN_PMINSW,
16414 IX86_BUILTIN_PMINUB,
16416 IX86_BUILTIN_PMULHUW,
16417 IX86_BUILTIN_PMULHW,
16418 IX86_BUILTIN_PMULLW,
16420 IX86_BUILTIN_PSADBW,
16421 IX86_BUILTIN_PSHUFW,
16423 IX86_BUILTIN_PSLLW,
16424 IX86_BUILTIN_PSLLD,
16425 IX86_BUILTIN_PSLLQ,
16426 IX86_BUILTIN_PSRAW,
16427 IX86_BUILTIN_PSRAD,
16428 IX86_BUILTIN_PSRLW,
16429 IX86_BUILTIN_PSRLD,
16430 IX86_BUILTIN_PSRLQ,
16431 IX86_BUILTIN_PSLLWI,
16432 IX86_BUILTIN_PSLLDI,
16433 IX86_BUILTIN_PSLLQI,
16434 IX86_BUILTIN_PSRAWI,
16435 IX86_BUILTIN_PSRADI,
16436 IX86_BUILTIN_PSRLWI,
16437 IX86_BUILTIN_PSRLDI,
16438 IX86_BUILTIN_PSRLQI,
16440 IX86_BUILTIN_PUNPCKHBW,
16441 IX86_BUILTIN_PUNPCKHWD,
16442 IX86_BUILTIN_PUNPCKHDQ,
16443 IX86_BUILTIN_PUNPCKLBW,
16444 IX86_BUILTIN_PUNPCKLWD,
16445 IX86_BUILTIN_PUNPCKLDQ,
16447 IX86_BUILTIN_SHUFPS,
16449 IX86_BUILTIN_RCPPS,
16450 IX86_BUILTIN_RCPSS,
16451 IX86_BUILTIN_RSQRTPS,
16452 IX86_BUILTIN_RSQRTSS,
16453 IX86_BUILTIN_RSQRTF,
16454 IX86_BUILTIN_SQRTPS,
16455 IX86_BUILTIN_SQRTSS,
16457 IX86_BUILTIN_UNPCKHPS,
16458 IX86_BUILTIN_UNPCKLPS,
16460 IX86_BUILTIN_ANDPS,
16461 IX86_BUILTIN_ANDNPS,
16463 IX86_BUILTIN_XORPS,
16466 IX86_BUILTIN_LDMXCSR,
16467 IX86_BUILTIN_STMXCSR,
16468 IX86_BUILTIN_SFENCE,
16470 /* 3DNow! Original */
16471 IX86_BUILTIN_FEMMS,
16472 IX86_BUILTIN_PAVGUSB,
16473 IX86_BUILTIN_PF2ID,
16474 IX86_BUILTIN_PFACC,
16475 IX86_BUILTIN_PFADD,
16476 IX86_BUILTIN_PFCMPEQ,
16477 IX86_BUILTIN_PFCMPGE,
16478 IX86_BUILTIN_PFCMPGT,
16479 IX86_BUILTIN_PFMAX,
16480 IX86_BUILTIN_PFMIN,
16481 IX86_BUILTIN_PFMUL,
16482 IX86_BUILTIN_PFRCP,
16483 IX86_BUILTIN_PFRCPIT1,
16484 IX86_BUILTIN_PFRCPIT2,
16485 IX86_BUILTIN_PFRSQIT1,
16486 IX86_BUILTIN_PFRSQRT,
16487 IX86_BUILTIN_PFSUB,
16488 IX86_BUILTIN_PFSUBR,
16489 IX86_BUILTIN_PI2FD,
16490 IX86_BUILTIN_PMULHRW,
16492 /* 3DNow! Athlon Extensions */
16493 IX86_BUILTIN_PF2IW,
16494 IX86_BUILTIN_PFNACC,
16495 IX86_BUILTIN_PFPNACC,
16496 IX86_BUILTIN_PI2FW,
16497 IX86_BUILTIN_PSWAPDSI,
16498 IX86_BUILTIN_PSWAPDSF,
16501 IX86_BUILTIN_ADDPD,
16502 IX86_BUILTIN_ADDSD,
16503 IX86_BUILTIN_DIVPD,
16504 IX86_BUILTIN_DIVSD,
16505 IX86_BUILTIN_MULPD,
16506 IX86_BUILTIN_MULSD,
16507 IX86_BUILTIN_SUBPD,
16508 IX86_BUILTIN_SUBSD,
16510 IX86_BUILTIN_CMPEQPD,
16511 IX86_BUILTIN_CMPLTPD,
16512 IX86_BUILTIN_CMPLEPD,
16513 IX86_BUILTIN_CMPGTPD,
16514 IX86_BUILTIN_CMPGEPD,
16515 IX86_BUILTIN_CMPNEQPD,
16516 IX86_BUILTIN_CMPNLTPD,
16517 IX86_BUILTIN_CMPNLEPD,
16518 IX86_BUILTIN_CMPNGTPD,
16519 IX86_BUILTIN_CMPNGEPD,
16520 IX86_BUILTIN_CMPORDPD,
16521 IX86_BUILTIN_CMPUNORDPD,
16522 IX86_BUILTIN_CMPEQSD,
16523 IX86_BUILTIN_CMPLTSD,
16524 IX86_BUILTIN_CMPLESD,
16525 IX86_BUILTIN_CMPNEQSD,
16526 IX86_BUILTIN_CMPNLTSD,
16527 IX86_BUILTIN_CMPNLESD,
16528 IX86_BUILTIN_CMPORDSD,
16529 IX86_BUILTIN_CMPUNORDSD,
16531 IX86_BUILTIN_COMIEQSD,
16532 IX86_BUILTIN_COMILTSD,
16533 IX86_BUILTIN_COMILESD,
16534 IX86_BUILTIN_COMIGTSD,
16535 IX86_BUILTIN_COMIGESD,
16536 IX86_BUILTIN_COMINEQSD,
16537 IX86_BUILTIN_UCOMIEQSD,
16538 IX86_BUILTIN_UCOMILTSD,
16539 IX86_BUILTIN_UCOMILESD,
16540 IX86_BUILTIN_UCOMIGTSD,
16541 IX86_BUILTIN_UCOMIGESD,
16542 IX86_BUILTIN_UCOMINEQSD,
16544 IX86_BUILTIN_MAXPD,
16545 IX86_BUILTIN_MAXSD,
16546 IX86_BUILTIN_MINPD,
16547 IX86_BUILTIN_MINSD,
16549 IX86_BUILTIN_ANDPD,
16550 IX86_BUILTIN_ANDNPD,
16552 IX86_BUILTIN_XORPD,
16554 IX86_BUILTIN_SQRTPD,
16555 IX86_BUILTIN_SQRTSD,
16557 IX86_BUILTIN_UNPCKHPD,
16558 IX86_BUILTIN_UNPCKLPD,
16560 IX86_BUILTIN_SHUFPD,
16562 IX86_BUILTIN_LOADUPD,
16563 IX86_BUILTIN_STOREUPD,
16564 IX86_BUILTIN_MOVSD,
16566 IX86_BUILTIN_LOADHPD,
16567 IX86_BUILTIN_LOADLPD,
16569 IX86_BUILTIN_CVTDQ2PD,
16570 IX86_BUILTIN_CVTDQ2PS,
16572 IX86_BUILTIN_CVTPD2DQ,
16573 IX86_BUILTIN_CVTPD2PI,
16574 IX86_BUILTIN_CVTPD2PS,
16575 IX86_BUILTIN_CVTTPD2DQ,
16576 IX86_BUILTIN_CVTTPD2PI,
16578 IX86_BUILTIN_CVTPI2PD,
16579 IX86_BUILTIN_CVTSI2SD,
16580 IX86_BUILTIN_CVTSI642SD,
16582 IX86_BUILTIN_CVTSD2SI,
16583 IX86_BUILTIN_CVTSD2SI64,
16584 IX86_BUILTIN_CVTSD2SS,
16585 IX86_BUILTIN_CVTSS2SD,
16586 IX86_BUILTIN_CVTTSD2SI,
16587 IX86_BUILTIN_CVTTSD2SI64,
16589 IX86_BUILTIN_CVTPS2DQ,
16590 IX86_BUILTIN_CVTPS2PD,
16591 IX86_BUILTIN_CVTTPS2DQ,
16593 IX86_BUILTIN_MOVNTI,
16594 IX86_BUILTIN_MOVNTPD,
16595 IX86_BUILTIN_MOVNTDQ,
16598 IX86_BUILTIN_MASKMOVDQU,
16599 IX86_BUILTIN_MOVMSKPD,
16600 IX86_BUILTIN_PMOVMSKB128,
16602 IX86_BUILTIN_PACKSSWB128,
16603 IX86_BUILTIN_PACKSSDW128,
16604 IX86_BUILTIN_PACKUSWB128,
16606 IX86_BUILTIN_PADDB128,
16607 IX86_BUILTIN_PADDW128,
16608 IX86_BUILTIN_PADDD128,
16609 IX86_BUILTIN_PADDQ128,
16610 IX86_BUILTIN_PADDSB128,
16611 IX86_BUILTIN_PADDSW128,
16612 IX86_BUILTIN_PADDUSB128,
16613 IX86_BUILTIN_PADDUSW128,
16614 IX86_BUILTIN_PSUBB128,
16615 IX86_BUILTIN_PSUBW128,
16616 IX86_BUILTIN_PSUBD128,
16617 IX86_BUILTIN_PSUBQ128,
16618 IX86_BUILTIN_PSUBSB128,
16619 IX86_BUILTIN_PSUBSW128,
16620 IX86_BUILTIN_PSUBUSB128,
16621 IX86_BUILTIN_PSUBUSW128,
16623 IX86_BUILTIN_PAND128,
16624 IX86_BUILTIN_PANDN128,
16625 IX86_BUILTIN_POR128,
16626 IX86_BUILTIN_PXOR128,
16628 IX86_BUILTIN_PAVGB128,
16629 IX86_BUILTIN_PAVGW128,
16631 IX86_BUILTIN_PCMPEQB128,
16632 IX86_BUILTIN_PCMPEQW128,
16633 IX86_BUILTIN_PCMPEQD128,
16634 IX86_BUILTIN_PCMPGTB128,
16635 IX86_BUILTIN_PCMPGTW128,
16636 IX86_BUILTIN_PCMPGTD128,
16638 IX86_BUILTIN_PMADDWD128,
16640 IX86_BUILTIN_PMAXSW128,
16641 IX86_BUILTIN_PMAXUB128,
16642 IX86_BUILTIN_PMINSW128,
16643 IX86_BUILTIN_PMINUB128,
16645 IX86_BUILTIN_PMULUDQ,
16646 IX86_BUILTIN_PMULUDQ128,
16647 IX86_BUILTIN_PMULHUW128,
16648 IX86_BUILTIN_PMULHW128,
16649 IX86_BUILTIN_PMULLW128,
16651 IX86_BUILTIN_PSADBW128,
16652 IX86_BUILTIN_PSHUFHW,
16653 IX86_BUILTIN_PSHUFLW,
16654 IX86_BUILTIN_PSHUFD,
16656 IX86_BUILTIN_PSLLDQI128,
16657 IX86_BUILTIN_PSLLWI128,
16658 IX86_BUILTIN_PSLLDI128,
16659 IX86_BUILTIN_PSLLQI128,
16660 IX86_BUILTIN_PSRAWI128,
16661 IX86_BUILTIN_PSRADI128,
16662 IX86_BUILTIN_PSRLDQI128,
16663 IX86_BUILTIN_PSRLWI128,
16664 IX86_BUILTIN_PSRLDI128,
16665 IX86_BUILTIN_PSRLQI128,
16667 IX86_BUILTIN_PSLLDQ128,
16668 IX86_BUILTIN_PSLLW128,
16669 IX86_BUILTIN_PSLLD128,
16670 IX86_BUILTIN_PSLLQ128,
16671 IX86_BUILTIN_PSRAW128,
16672 IX86_BUILTIN_PSRAD128,
16673 IX86_BUILTIN_PSRLW128,
16674 IX86_BUILTIN_PSRLD128,
16675 IX86_BUILTIN_PSRLQ128,
16677 IX86_BUILTIN_PUNPCKHBW128,
16678 IX86_BUILTIN_PUNPCKHWD128,
16679 IX86_BUILTIN_PUNPCKHDQ128,
16680 IX86_BUILTIN_PUNPCKHQDQ128,
16681 IX86_BUILTIN_PUNPCKLBW128,
16682 IX86_BUILTIN_PUNPCKLWD128,
16683 IX86_BUILTIN_PUNPCKLDQ128,
16684 IX86_BUILTIN_PUNPCKLQDQ128,
16686 IX86_BUILTIN_CLFLUSH,
16687 IX86_BUILTIN_MFENCE,
16688 IX86_BUILTIN_LFENCE,
16690 /* Prescott New Instructions. */
16691 IX86_BUILTIN_ADDSUBPS,
16692 IX86_BUILTIN_HADDPS,
16693 IX86_BUILTIN_HSUBPS,
16694 IX86_BUILTIN_MOVSHDUP,
16695 IX86_BUILTIN_MOVSLDUP,
16696 IX86_BUILTIN_ADDSUBPD,
16697 IX86_BUILTIN_HADDPD,
16698 IX86_BUILTIN_HSUBPD,
16699 IX86_BUILTIN_LDDQU,
16701 IX86_BUILTIN_MONITOR,
16702 IX86_BUILTIN_MWAIT,
16705 IX86_BUILTIN_PHADDW,
16706 IX86_BUILTIN_PHADDD,
16707 IX86_BUILTIN_PHADDSW,
16708 IX86_BUILTIN_PHSUBW,
16709 IX86_BUILTIN_PHSUBD,
16710 IX86_BUILTIN_PHSUBSW,
16711 IX86_BUILTIN_PMADDUBSW,
16712 IX86_BUILTIN_PMULHRSW,
16713 IX86_BUILTIN_PSHUFB,
16714 IX86_BUILTIN_PSIGNB,
16715 IX86_BUILTIN_PSIGNW,
16716 IX86_BUILTIN_PSIGND,
16717 IX86_BUILTIN_PALIGNR,
16718 IX86_BUILTIN_PABSB,
16719 IX86_BUILTIN_PABSW,
16720 IX86_BUILTIN_PABSD,
16722 IX86_BUILTIN_PHADDW128,
16723 IX86_BUILTIN_PHADDD128,
16724 IX86_BUILTIN_PHADDSW128,
16725 IX86_BUILTIN_PHSUBW128,
16726 IX86_BUILTIN_PHSUBD128,
16727 IX86_BUILTIN_PHSUBSW128,
16728 IX86_BUILTIN_PMADDUBSW128,
16729 IX86_BUILTIN_PMULHRSW128,
16730 IX86_BUILTIN_PSHUFB128,
16731 IX86_BUILTIN_PSIGNB128,
16732 IX86_BUILTIN_PSIGNW128,
16733 IX86_BUILTIN_PSIGND128,
16734 IX86_BUILTIN_PALIGNR128,
16735 IX86_BUILTIN_PABSB128,
16736 IX86_BUILTIN_PABSW128,
16737 IX86_BUILTIN_PABSD128,
16739 /* AMDFAM10 - SSE4A New Instructions. */
16740 IX86_BUILTIN_MOVNTSD,
16741 IX86_BUILTIN_MOVNTSS,
16742 IX86_BUILTIN_EXTRQI,
16743 IX86_BUILTIN_EXTRQ,
16744 IX86_BUILTIN_INSERTQI,
16745 IX86_BUILTIN_INSERTQ,
16748 IX86_BUILTIN_BLENDPD,
16749 IX86_BUILTIN_BLENDPS,
16750 IX86_BUILTIN_BLENDVPD,
16751 IX86_BUILTIN_BLENDVPS,
16752 IX86_BUILTIN_PBLENDVB128,
16753 IX86_BUILTIN_PBLENDW128,
16758 IX86_BUILTIN_INSERTPS128,
16760 IX86_BUILTIN_MOVNTDQA,
16761 IX86_BUILTIN_MPSADBW128,
16762 IX86_BUILTIN_PACKUSDW128,
16763 IX86_BUILTIN_PCMPEQQ,
16764 IX86_BUILTIN_PHMINPOSUW128,
16766 IX86_BUILTIN_PMAXSB128,
16767 IX86_BUILTIN_PMAXSD128,
16768 IX86_BUILTIN_PMAXUD128,
16769 IX86_BUILTIN_PMAXUW128,
16771 IX86_BUILTIN_PMINSB128,
16772 IX86_BUILTIN_PMINSD128,
16773 IX86_BUILTIN_PMINUD128,
16774 IX86_BUILTIN_PMINUW128,
16776 IX86_BUILTIN_PMOVSXBW128,
16777 IX86_BUILTIN_PMOVSXBD128,
16778 IX86_BUILTIN_PMOVSXBQ128,
16779 IX86_BUILTIN_PMOVSXWD128,
16780 IX86_BUILTIN_PMOVSXWQ128,
16781 IX86_BUILTIN_PMOVSXDQ128,
16783 IX86_BUILTIN_PMOVZXBW128,
16784 IX86_BUILTIN_PMOVZXBD128,
16785 IX86_BUILTIN_PMOVZXBQ128,
16786 IX86_BUILTIN_PMOVZXWD128,
16787 IX86_BUILTIN_PMOVZXWQ128,
16788 IX86_BUILTIN_PMOVZXDQ128,
16790 IX86_BUILTIN_PMULDQ128,
16791 IX86_BUILTIN_PMULLD128,
16793 IX86_BUILTIN_ROUNDPD,
16794 IX86_BUILTIN_ROUNDPS,
16795 IX86_BUILTIN_ROUNDSD,
16796 IX86_BUILTIN_ROUNDSS,
16798 IX86_BUILTIN_PTESTZ,
16799 IX86_BUILTIN_PTESTC,
16800 IX86_BUILTIN_PTESTNZC,
16802 IX86_BUILTIN_VEC_INIT_V2SI,
16803 IX86_BUILTIN_VEC_INIT_V4HI,
16804 IX86_BUILTIN_VEC_INIT_V8QI,
16805 IX86_BUILTIN_VEC_EXT_V2DF,
16806 IX86_BUILTIN_VEC_EXT_V2DI,
16807 IX86_BUILTIN_VEC_EXT_V4SF,
16808 IX86_BUILTIN_VEC_EXT_V4SI,
16809 IX86_BUILTIN_VEC_EXT_V8HI,
16810 IX86_BUILTIN_VEC_EXT_V2SI,
16811 IX86_BUILTIN_VEC_EXT_V4HI,
16812 IX86_BUILTIN_VEC_EXT_V16QI,
16813 IX86_BUILTIN_VEC_SET_V2DI,
16814 IX86_BUILTIN_VEC_SET_V4SF,
16815 IX86_BUILTIN_VEC_SET_V4SI,
16816 IX86_BUILTIN_VEC_SET_V8HI,
16817 IX86_BUILTIN_VEC_SET_V4HI,
16818 IX86_BUILTIN_VEC_SET_V16QI,
16821 IX86_BUILTIN_CRC32QI,
16822 IX86_BUILTIN_CRC32HI,
16823 IX86_BUILTIN_CRC32SI,
16824 IX86_BUILTIN_CRC32DI,
16826 IX86_BUILTIN_PCMPESTRI128,
16827 IX86_BUILTIN_PCMPESTRM128,
16828 IX86_BUILTIN_PCMPESTRA128,
16829 IX86_BUILTIN_PCMPESTRC128,
16830 IX86_BUILTIN_PCMPESTRO128,
16831 IX86_BUILTIN_PCMPESTRS128,
16832 IX86_BUILTIN_PCMPESTRZ128,
16833 IX86_BUILTIN_PCMPISTRI128,
16834 IX86_BUILTIN_PCMPISTRM128,
16835 IX86_BUILTIN_PCMPISTRA128,
16836 IX86_BUILTIN_PCMPISTRC128,
16837 IX86_BUILTIN_PCMPISTRO128,
16838 IX86_BUILTIN_PCMPISTRS128,
16839 IX86_BUILTIN_PCMPISTRZ128,
16841 IX86_BUILTIN_PCMPGTQ,
16843 /* TFmode support builtins. */
16845 IX86_BUILTIN_FABSQ,
16846 IX86_BUILTIN_COPYSIGNQ,
16851 /* Table for the ix86 builtin decls. */
16852 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
16854 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
16855 * if the target_flags include one of MASK. Stores the function decl
16856 * in the ix86_builtins array.
16857 * Returns the function decl or NULL_TREE, if the builtin was not added. */
16860 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
16862 tree decl = NULL_TREE;
16864 if (mask & ix86_isa_flags
16865 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
16867 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
16869 ix86_builtins[(int) code] = decl;
16875 /* Like def_builtin, but also marks the function decl "const". */
16878 def_builtin_const (int mask, const char *name, tree type,
16879 enum ix86_builtins code)
16881 tree decl = def_builtin (mask, name, type, code);
16883 TREE_READONLY (decl) = 1;
16887 /* Bits for builtin_description.flag. */
16889 /* Set when we don't support the comparison natively, and should
16890 swap_comparison in order to support it. */
16891 #define BUILTIN_DESC_SWAP_OPERANDS 1
16893 struct builtin_description
16895 const unsigned int mask;
16896 const enum insn_code icode;
16897 const char *const name;
16898 const enum ix86_builtins code;
16899 const enum rtx_code comparison;
16903 static const struct builtin_description bdesc_comi[] =
16905 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
16906 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
16907 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
16908 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
16909 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
16910 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
16911 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
16912 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
16913 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
16914 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
16915 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
16916 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
16917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
16918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
16919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
16920 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
16921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
16922 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
16923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
16924 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
16925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
16926 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
16927 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
16928 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
16931 static const struct builtin_description bdesc_ptest[] =
16934 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
16935 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
16936 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
16939 static const struct builtin_description bdesc_pcmpestr[] =
16942 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
16943 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
16944 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
16945 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
16946 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
16947 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
16948 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
16951 static const struct builtin_description bdesc_pcmpistr[] =
16954 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
16955 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
16956 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
16957 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
16958 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
16959 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
16960 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
16963 static const struct builtin_description bdesc_crc32[] =
16966 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32qi, 0, IX86_BUILTIN_CRC32QI, UNKNOWN, 0 },
16967 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, 0, IX86_BUILTIN_CRC32HI, UNKNOWN, 0 },
16968 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, 0, IX86_BUILTIN_CRC32SI, UNKNOWN, 0 },
16969 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32di, 0, IX86_BUILTIN_CRC32DI, UNKNOWN, 0 },
16972 /* SSE builtins with 3 arguments and the last argument must be an immediate or xmm0. */
16973 static const struct builtin_description bdesc_sse_3arg[] =
16976 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, 0 },
16977 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, 0 },
16978 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, 0 },
16979 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, 0 },
16980 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, 0 },
16981 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, 0 },
16982 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, 0 },
16983 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, 0 },
16984 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, 0 },
16985 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, 0 },
16986 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundsd, 0, IX86_BUILTIN_ROUNDSD, UNKNOWN, 0 },
16987 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundss, 0, IX86_BUILTIN_ROUNDSS, UNKNOWN, 0 },
16990 static const struct builtin_description bdesc_2arg[] =
16993 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, 0 },
16994 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, 0 },
16995 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, 0 },
16996 { OPTION_MASK_ISA_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
16997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, 0 },
16998 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, 0 },
16999 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, 0 },
17000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, 0 },
17002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
17003 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
17004 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
17005 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, BUILTIN_DESC_SWAP_OPERANDS },
17006 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, BUILTIN_DESC_SWAP_OPERANDS },
17007 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
17008 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
17009 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
17010 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
17011 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17012 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
17014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
17015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
17016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
17017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
17018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
17019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
17020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
17021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
17025 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, 0 },
17026 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, 0 },
17027 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, 0 },
17028 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, 0 },
17030 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, 0 },
17031 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, 0 },
17032 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, 0 },
17033 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, 0 },
17035 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, 0 },
17036 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, 0 },
17037 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, 0 },
17038 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, 0 },
17039 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, 0 },
17042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, 0 },
17043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, 0 },
17044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, 0 },
17045 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, 0 },
17046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, 0 },
17047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, 0 },
17048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, 0 },
17049 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, 0 },
17051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, 0 },
17052 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, 0 },
17053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, 0 },
17054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, 0 },
17055 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, 0 },
17056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, 0 },
17057 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, 0 },
17058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, 0 },
17060 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, 0 },
17061 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, 0 },
17062 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, 0 },
17064 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, 0 },
17065 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, 0 },
17066 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, 0 },
17067 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, 0 },
17069 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, 0 },
17070 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, 0 },
17072 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, 0 },
17073 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, 0 },
17074 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, 0 },
17075 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, 0 },
17076 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, 0 },
17077 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, 0 },
17079 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, 0 },
17080 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, 0 },
17081 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, 0 },
17082 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, 0 },
17084 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, 0 },
17085 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, 0 },
17086 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, 0 },
17087 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, 0 },
17088 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, 0 },
17089 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, 0 },
17092 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, UNKNOWN, 0 },
17093 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, UNKNOWN, 0 },
17094 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, UNKNOWN, 0 },
17096 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, UNKNOWN, 0 },
17097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, UNKNOWN, 0 },
17098 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, UNKNOWN, 0 },
17100 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, UNKNOWN, 0 },
17101 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, UNKNOWN, 0 },
17102 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, UNKNOWN, 0 },
17103 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, UNKNOWN, 0 },
17104 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, UNKNOWN, 0 },
17105 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, UNKNOWN, 0 },
17107 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, UNKNOWN, 0 },
17108 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, UNKNOWN, 0 },
17109 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, UNKNOWN, 0 },
17110 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, UNKNOWN, 0 },
17111 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, UNKNOWN, 0 },
17112 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, UNKNOWN, 0 },
17114 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, UNKNOWN, 0 },
17115 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, UNKNOWN, 0 },
17116 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, UNKNOWN, 0 },
17117 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, UNKNOWN, 0 },
17119 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, UNKNOWN, 0 },
17120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, UNKNOWN, 0 },
17123 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, 0 },
17124 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, 0 },
17125 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, 0 },
17126 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, 0 },
17127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, 0 },
17128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, 0 },
17129 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, 0 },
17130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, 0 },
17132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
17133 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
17134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
17135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, BUILTIN_DESC_SWAP_OPERANDS },
17136 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, BUILTIN_DESC_SWAP_OPERANDS },
17137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
17138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
17139 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
17140 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
17141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
17144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
17145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
17146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
17147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
17148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
17149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
17150 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
17151 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
17153 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, 0 },
17154 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, 0 },
17155 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, 0 },
17156 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, 0 },
17158 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, 0 },
17159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, 0 },
17160 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, 0 },
17161 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, 0 },
17163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, 0 },
17164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, 0 },
17165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, 0 },
17168 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, 0 },
17169 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, 0 },
17170 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, 0 },
17171 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, 0 },
17172 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, 0 },
17173 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, 0 },
17174 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, 0 },
17175 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, 0 },
17177 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, 0 },
17178 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, 0 },
17179 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, 0 },
17180 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, 0 },
17181 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, 0 },
17182 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, 0 },
17183 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, 0 },
17184 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, 0 },
17186 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, 0 },
17187 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN, 0 },
17189 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, 0 },
17190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, 0 },
17191 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, 0 },
17192 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, 0 },
17194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, 0 },
17195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, 0 },
17197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, 0 },
17198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, 0 },
17199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, 0 },
17200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, 0 },
17201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, 0 },
17202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, 0 },
17204 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, 0 },
17205 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, 0 },
17206 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, 0 },
17207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, 0 },
17209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, 0 },
17210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, 0 },
17211 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, 0 },
17212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, 0 },
17213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, 0 },
17214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, 0 },
17215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, 0 },
17216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, 0 },
17218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, 0 },
17219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, 0 },
17220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, 0 },
17222 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, 0 },
17223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, UNKNOWN, 0 },
17225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 },
17226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, UNKNOWN, 0 },
17228 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, UNKNOWN, 0 },
17229 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, UNKNOWN, 0 },
17230 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, UNKNOWN, 0 },
17232 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, UNKNOWN, 0 },
17233 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, UNKNOWN, 0 },
17234 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, UNKNOWN, 0 },
17236 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, UNKNOWN, 0 },
17237 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, UNKNOWN, 0 },
17239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, UNKNOWN, 0 },
17241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, UNKNOWN, 0 },
17242 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, UNKNOWN, 0 },
17243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, UNKNOWN, 0 },
17244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, UNKNOWN, 0 },
17247 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, 0 },
17248 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, 0 },
17249 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, 0 },
17250 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, 0 },
17251 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, 0 },
17252 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, 0 },
17255 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, 0 },
17256 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, 0 },
17257 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, 0 },
17258 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, 0 },
17259 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, 0 },
17260 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, 0 },
17261 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, 0 },
17262 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, 0 },
17263 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, 0 },
17264 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, 0 },
17265 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, 0 },
17266 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, 0 },
17267 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, 0 },
17268 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, 0 },
17269 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, 0 },
17270 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, 0 },
17271 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, 0 },
17272 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, 0 },
17273 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, 0 },
17274 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, 0 },
17275 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, 0 },
17276 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, 0 },
17277 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, 0 },
17278 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, 0 },
17281 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, 0 },
17282 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, 0 },
17283 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, 0 },
17284 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, 0 },
17285 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, 0 },
17286 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, 0 },
17287 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, 0 },
17288 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, 0 },
17289 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, 0 },
17290 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, 0 },
17291 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, 0, IX86_BUILTIN_PMULDQ128, UNKNOWN, 0 },
17292 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, 0 },
17295 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, 0 },
17298 static const struct builtin_description bdesc_1arg[] =
17300 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, UNKNOWN, 0 },
17301 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, UNKNOWN, 0 },
17303 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, UNKNOWN, 0 },
17304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, UNKNOWN, 0 },
17305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, UNKNOWN, 0 },
17307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, UNKNOWN, 0 },
17308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, UNKNOWN, 0 },
17309 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, UNKNOWN, 0 },
17310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, UNKNOWN, 0 },
17311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, UNKNOWN, 0 },
17312 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, 0 },
17314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, UNKNOWN, 0 },
17315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, UNKNOWN, 0 },
17317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, UNKNOWN, 0 },
17319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, UNKNOWN, 0 },
17320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, UNKNOWN, 0 },
17322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, UNKNOWN, 0 },
17323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, UNKNOWN, 0 },
17324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, UNKNOWN, 0 },
17325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, 0 },
17326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, UNKNOWN, 0 },
17328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, UNKNOWN, 0 },
17330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, UNKNOWN, 0 },
17331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, UNKNOWN, 0 },
17332 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, UNKNOWN, 0 },
17333 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, 0 },
17335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, UNKNOWN, 0 },
17336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, UNKNOWN, 0 },
17337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, 0 },
17340 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, 0 },
17341 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, 0 },
17344 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, 0 },
17345 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, 0 },
17346 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, 0 },
17347 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, 0 },
17348 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, 0 },
17349 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, 0 },
17352 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVSXBW128, UNKNOWN, 0 },
17353 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVSXBD128, UNKNOWN, 0 },
17354 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, 0 },
17355 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVSXWD128, UNKNOWN, 0 },
17356 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, 0 },
17357 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, 0, IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, 0 },
17358 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVZXBW128, UNKNOWN, 0 },
17359 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVZXBD128, UNKNOWN, 0 },
17360 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, 0 },
17361 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVZXWD128, UNKNOWN, 0 },
17362 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, 0 },
17363 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, 0, IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, 0 },
17364 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, 0 },
17366 /* Fake 1 arg builtins with a constant smaller than 8 bits as the 2nd arg. */
17367 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, 0, IX86_BUILTIN_ROUNDPD, UNKNOWN, 0 },
17368 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, 0, IX86_BUILTIN_ROUNDPS, UNKNOWN, 0 },
17371 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
17372 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
17375 ix86_init_mmx_sse_builtins (void)
17377 const struct builtin_description * d;
17380 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
17381 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
17382 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
17383 tree V2DI_type_node
17384 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
17385 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
17386 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
17387 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
17388 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
17389 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
17390 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
17392 tree pchar_type_node = build_pointer_type (char_type_node);
17393 tree pcchar_type_node = build_pointer_type (
17394 build_type_variant (char_type_node, 1, 0));
17395 tree pfloat_type_node = build_pointer_type (float_type_node);
17396 tree pcfloat_type_node = build_pointer_type (
17397 build_type_variant (float_type_node, 1, 0));
17398 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
17399 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
17400 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
17403 tree int_ftype_v4sf_v4sf
17404 = build_function_type_list (integer_type_node,
17405 V4SF_type_node, V4SF_type_node, NULL_TREE);
17406 tree v4si_ftype_v4sf_v4sf
17407 = build_function_type_list (V4SI_type_node,
17408 V4SF_type_node, V4SF_type_node, NULL_TREE);
17409 /* MMX/SSE/integer conversions. */
17410 tree int_ftype_v4sf
17411 = build_function_type_list (integer_type_node,
17412 V4SF_type_node, NULL_TREE);
17413 tree int64_ftype_v4sf
17414 = build_function_type_list (long_long_integer_type_node,
17415 V4SF_type_node, NULL_TREE);
17416 tree int_ftype_v8qi
17417 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
17418 tree v4sf_ftype_v4sf_int
17419 = build_function_type_list (V4SF_type_node,
17420 V4SF_type_node, integer_type_node, NULL_TREE);
17421 tree v4sf_ftype_v4sf_int64
17422 = build_function_type_list (V4SF_type_node,
17423 V4SF_type_node, long_long_integer_type_node,
17425 tree v4sf_ftype_v4sf_v2si
17426 = build_function_type_list (V4SF_type_node,
17427 V4SF_type_node, V2SI_type_node, NULL_TREE);
17429 /* Miscellaneous. */
17430 tree v8qi_ftype_v4hi_v4hi
17431 = build_function_type_list (V8QI_type_node,
17432 V4HI_type_node, V4HI_type_node, NULL_TREE);
17433 tree v4hi_ftype_v2si_v2si
17434 = build_function_type_list (V4HI_type_node,
17435 V2SI_type_node, V2SI_type_node, NULL_TREE);
17436 tree v4sf_ftype_v4sf_v4sf_int
17437 = build_function_type_list (V4SF_type_node,
17438 V4SF_type_node, V4SF_type_node,
17439 integer_type_node, NULL_TREE);
17440 tree v2si_ftype_v4hi_v4hi
17441 = build_function_type_list (V2SI_type_node,
17442 V4HI_type_node, V4HI_type_node, NULL_TREE);
17443 tree v4hi_ftype_v4hi_int
17444 = build_function_type_list (V4HI_type_node,
17445 V4HI_type_node, integer_type_node, NULL_TREE);
17446 tree v4hi_ftype_v4hi_di
17447 = build_function_type_list (V4HI_type_node,
17448 V4HI_type_node, long_long_unsigned_type_node,
17450 tree v2si_ftype_v2si_di
17451 = build_function_type_list (V2SI_type_node,
17452 V2SI_type_node, long_long_unsigned_type_node,
17454 tree void_ftype_void
17455 = build_function_type (void_type_node, void_list_node);
17456 tree void_ftype_unsigned
17457 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
17458 tree void_ftype_unsigned_unsigned
17459 = build_function_type_list (void_type_node, unsigned_type_node,
17460 unsigned_type_node, NULL_TREE);
17461 tree void_ftype_pcvoid_unsigned_unsigned
17462 = build_function_type_list (void_type_node, const_ptr_type_node,
17463 unsigned_type_node, unsigned_type_node,
17465 tree unsigned_ftype_void
17466 = build_function_type (unsigned_type_node, void_list_node);
17467 tree v2si_ftype_v4sf
17468 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
17469 /* Loads/stores. */
17470 tree void_ftype_v8qi_v8qi_pchar
17471 = build_function_type_list (void_type_node,
17472 V8QI_type_node, V8QI_type_node,
17473 pchar_type_node, NULL_TREE);
17474 tree v4sf_ftype_pcfloat
17475 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
17476 /* @@@ the type is bogus */
17477 tree v4sf_ftype_v4sf_pv2si
17478 = build_function_type_list (V4SF_type_node,
17479 V4SF_type_node, pv2si_type_node, NULL_TREE);
17480 tree void_ftype_pv2si_v4sf
17481 = build_function_type_list (void_type_node,
17482 pv2si_type_node, V4SF_type_node, NULL_TREE);
17483 tree void_ftype_pfloat_v4sf
17484 = build_function_type_list (void_type_node,
17485 pfloat_type_node, V4SF_type_node, NULL_TREE);
17486 tree void_ftype_pdi_di
17487 = build_function_type_list (void_type_node,
17488 pdi_type_node, long_long_unsigned_type_node,
17490 tree void_ftype_pv2di_v2di
17491 = build_function_type_list (void_type_node,
17492 pv2di_type_node, V2DI_type_node, NULL_TREE);
17493 /* Normal vector unops. */
17494 tree v4sf_ftype_v4sf
17495 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
17496 tree v16qi_ftype_v16qi
17497 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
17498 tree v8hi_ftype_v8hi
17499 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
17500 tree v4si_ftype_v4si
17501 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
17502 tree v8qi_ftype_v8qi
17503 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
17504 tree v4hi_ftype_v4hi
17505 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
17507 /* Normal vector binops. */
17508 tree v4sf_ftype_v4sf_v4sf
17509 = build_function_type_list (V4SF_type_node,
17510 V4SF_type_node, V4SF_type_node, NULL_TREE);
17511 tree v8qi_ftype_v8qi_v8qi
17512 = build_function_type_list (V8QI_type_node,
17513 V8QI_type_node, V8QI_type_node, NULL_TREE);
17514 tree v4hi_ftype_v4hi_v4hi
17515 = build_function_type_list (V4HI_type_node,
17516 V4HI_type_node, V4HI_type_node, NULL_TREE);
17517 tree v2si_ftype_v2si_v2si
17518 = build_function_type_list (V2SI_type_node,
17519 V2SI_type_node, V2SI_type_node, NULL_TREE);
17520 tree di_ftype_di_di
17521 = build_function_type_list (long_long_unsigned_type_node,
17522 long_long_unsigned_type_node,
17523 long_long_unsigned_type_node, NULL_TREE);
17525 tree di_ftype_di_di_int
17526 = build_function_type_list (long_long_unsigned_type_node,
17527 long_long_unsigned_type_node,
17528 long_long_unsigned_type_node,
17529 integer_type_node, NULL_TREE);
17531 tree v2si_ftype_v2sf
17532 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
17533 tree v2sf_ftype_v2si
17534 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
17535 tree v2si_ftype_v2si
17536 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
17537 tree v2sf_ftype_v2sf
17538 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
17539 tree v2sf_ftype_v2sf_v2sf
17540 = build_function_type_list (V2SF_type_node,
17541 V2SF_type_node, V2SF_type_node, NULL_TREE);
17542 tree v2si_ftype_v2sf_v2sf
17543 = build_function_type_list (V2SI_type_node,
17544 V2SF_type_node, V2SF_type_node, NULL_TREE);
17545 tree pint_type_node = build_pointer_type (integer_type_node);
17546 tree pdouble_type_node = build_pointer_type (double_type_node);
17547 tree pcdouble_type_node = build_pointer_type (
17548 build_type_variant (double_type_node, 1, 0));
17549 tree int_ftype_v2df_v2df
17550 = build_function_type_list (integer_type_node,
17551 V2DF_type_node, V2DF_type_node, NULL_TREE);
17553 tree void_ftype_pcvoid
17554 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
17555 tree v4sf_ftype_v4si
17556 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
17557 tree v4si_ftype_v4sf
17558 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
17559 tree v2df_ftype_v4si
17560 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
17561 tree v4si_ftype_v2df
17562 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
17563 tree v2si_ftype_v2df
17564 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
17565 tree v4sf_ftype_v2df
17566 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
17567 tree v2df_ftype_v2si
17568 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
17569 tree v2df_ftype_v4sf
17570 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
17571 tree int_ftype_v2df
17572 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
17573 tree int64_ftype_v2df
17574 = build_function_type_list (long_long_integer_type_node,
17575 V2DF_type_node, NULL_TREE);
17576 tree v2df_ftype_v2df_int
17577 = build_function_type_list (V2DF_type_node,
17578 V2DF_type_node, integer_type_node, NULL_TREE);
17579 tree v2df_ftype_v2df_int64
17580 = build_function_type_list (V2DF_type_node,
17581 V2DF_type_node, long_long_integer_type_node,
17583 tree v4sf_ftype_v4sf_v2df
17584 = build_function_type_list (V4SF_type_node,
17585 V4SF_type_node, V2DF_type_node, NULL_TREE);
17586 tree v2df_ftype_v2df_v4sf
17587 = build_function_type_list (V2DF_type_node,
17588 V2DF_type_node, V4SF_type_node, NULL_TREE);
17589 tree v2df_ftype_v2df_v2df_int
17590 = build_function_type_list (V2DF_type_node,
17591 V2DF_type_node, V2DF_type_node,
17594 tree v2df_ftype_v2df_pcdouble
17595 = build_function_type_list (V2DF_type_node,
17596 V2DF_type_node, pcdouble_type_node, NULL_TREE);
17597 tree void_ftype_pdouble_v2df
17598 = build_function_type_list (void_type_node,
17599 pdouble_type_node, V2DF_type_node, NULL_TREE);
17600 tree void_ftype_pint_int
17601 = build_function_type_list (void_type_node,
17602 pint_type_node, integer_type_node, NULL_TREE);
17603 tree void_ftype_v16qi_v16qi_pchar
17604 = build_function_type_list (void_type_node,
17605 V16QI_type_node, V16QI_type_node,
17606 pchar_type_node, NULL_TREE);
17607 tree v2df_ftype_pcdouble
17608 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
17609 tree v2df_ftype_v2df_v2df
17610 = build_function_type_list (V2DF_type_node,
17611 V2DF_type_node, V2DF_type_node, NULL_TREE);
17612 tree v16qi_ftype_v16qi_v16qi
17613 = build_function_type_list (V16QI_type_node,
17614 V16QI_type_node, V16QI_type_node, NULL_TREE);
17615 tree v8hi_ftype_v8hi_v8hi
17616 = build_function_type_list (V8HI_type_node,
17617 V8HI_type_node, V8HI_type_node, NULL_TREE);
17618 tree v4si_ftype_v4si_v4si
17619 = build_function_type_list (V4SI_type_node,
17620 V4SI_type_node, V4SI_type_node, NULL_TREE);
17621 tree v2di_ftype_v2di_v2di
17622 = build_function_type_list (V2DI_type_node,
17623 V2DI_type_node, V2DI_type_node, NULL_TREE);
17624 tree v2di_ftype_v2df_v2df
17625 = build_function_type_list (V2DI_type_node,
17626 V2DF_type_node, V2DF_type_node, NULL_TREE);
17627 tree v2df_ftype_v2df
17628 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
17629 tree v2di_ftype_v2di_int
17630 = build_function_type_list (V2DI_type_node,
17631 V2DI_type_node, integer_type_node, NULL_TREE);
17632 tree v2di_ftype_v2di_v2di_int
17633 = build_function_type_list (V2DI_type_node, V2DI_type_node,
17634 V2DI_type_node, integer_type_node, NULL_TREE);
17635 tree v4si_ftype_v4si_int
17636 = build_function_type_list (V4SI_type_node,
17637 V4SI_type_node, integer_type_node, NULL_TREE);
17638 tree v8hi_ftype_v8hi_int
17639 = build_function_type_list (V8HI_type_node,
17640 V8HI_type_node, integer_type_node, NULL_TREE);
17641 tree v4si_ftype_v8hi_v8hi
17642 = build_function_type_list (V4SI_type_node,
17643 V8HI_type_node, V8HI_type_node, NULL_TREE);
17644 tree di_ftype_v8qi_v8qi
17645 = build_function_type_list (long_long_unsigned_type_node,
17646 V8QI_type_node, V8QI_type_node, NULL_TREE);
17647 tree di_ftype_v2si_v2si
17648 = build_function_type_list (long_long_unsigned_type_node,
17649 V2SI_type_node, V2SI_type_node, NULL_TREE);
17650 tree v2di_ftype_v16qi_v16qi
17651 = build_function_type_list (V2DI_type_node,
17652 V16QI_type_node, V16QI_type_node, NULL_TREE);
17653 tree v2di_ftype_v4si_v4si
17654 = build_function_type_list (V2DI_type_node,
17655 V4SI_type_node, V4SI_type_node, NULL_TREE);
17656 tree int_ftype_v16qi
17657 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
17658 tree v16qi_ftype_pcchar
17659 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
17660 tree void_ftype_pchar_v16qi
17661 = build_function_type_list (void_type_node,
17662 pchar_type_node, V16QI_type_node, NULL_TREE);
17664 tree v2di_ftype_v2di_unsigned_unsigned
17665 = build_function_type_list (V2DI_type_node, V2DI_type_node,
17666 unsigned_type_node, unsigned_type_node,
17668 tree v2di_ftype_v2di_v2di_unsigned_unsigned
17669 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
17670 unsigned_type_node, unsigned_type_node,
17672 tree v2di_ftype_v2di_v16qi
17673 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
17675 tree v2df_ftype_v2df_v2df_v2df
17676 = build_function_type_list (V2DF_type_node,
17677 V2DF_type_node, V2DF_type_node,
17678 V2DF_type_node, NULL_TREE);
17679 tree v4sf_ftype_v4sf_v4sf_v4sf
17680 = build_function_type_list (V4SF_type_node,
17681 V4SF_type_node, V4SF_type_node,
17682 V4SF_type_node, NULL_TREE);
17683 tree v8hi_ftype_v16qi
17684 = build_function_type_list (V8HI_type_node, V16QI_type_node,
17686 tree v4si_ftype_v16qi
17687 = build_function_type_list (V4SI_type_node, V16QI_type_node,
17689 tree v2di_ftype_v16qi
17690 = build_function_type_list (V2DI_type_node, V16QI_type_node,
17692 tree v4si_ftype_v8hi
17693 = build_function_type_list (V4SI_type_node, V8HI_type_node,
17695 tree v2di_ftype_v8hi
17696 = build_function_type_list (V2DI_type_node, V8HI_type_node,
17698 tree v2di_ftype_v4si
17699 = build_function_type_list (V2DI_type_node, V4SI_type_node,
17701 tree v2di_ftype_pv2di
17702 = build_function_type_list (V2DI_type_node, pv2di_type_node,
17704 tree v16qi_ftype_v16qi_v16qi_int
17705 = build_function_type_list (V16QI_type_node, V16QI_type_node,
17706 V16QI_type_node, integer_type_node,
17708 tree v16qi_ftype_v16qi_v16qi_v16qi
17709 = build_function_type_list (V16QI_type_node, V16QI_type_node,
17710 V16QI_type_node, V16QI_type_node,
17712 tree v8hi_ftype_v8hi_v8hi_int
17713 = build_function_type_list (V8HI_type_node, V8HI_type_node,
17714 V8HI_type_node, integer_type_node,
17716 tree v4si_ftype_v4si_v4si_int
17717 = build_function_type_list (V4SI_type_node, V4SI_type_node,
17718 V4SI_type_node, integer_type_node,
17720 tree int_ftype_v2di_v2di
17721 = build_function_type_list (integer_type_node,
17722 V2DI_type_node, V2DI_type_node,
17724 tree int_ftype_v16qi_int_v16qi_int_int
17725 = build_function_type_list (integer_type_node,
17732 tree v16qi_ftype_v16qi_int_v16qi_int_int
17733 = build_function_type_list (V16QI_type_node,
17740 tree int_ftype_v16qi_v16qi_int
17741 = build_function_type_list (integer_type_node,
17748 /* The __float80 type. */
17749 if (TYPE_MODE (long_double_type_node) == XFmode)
17750 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
17754 /* The __float80 type. */
17755 tree float80_type_node = make_node (REAL_TYPE);
17757 TYPE_PRECISION (float80_type_node) = 80;
17758 layout_type (float80_type_node);
17759 (*lang_hooks.types.register_builtin_type) (float80_type_node,
17765 tree float128_type_node = make_node (REAL_TYPE);
17767 TYPE_PRECISION (float128_type_node) = 128;
17768 layout_type (float128_type_node);
17769 (*lang_hooks.types.register_builtin_type) (float128_type_node,
17772 /* TFmode support builtins. */
17773 ftype = build_function_type (float128_type_node,
17775 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
17777 ftype = build_function_type_list (float128_type_node,
17778 float128_type_node,
17780 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
17782 ftype = build_function_type_list (float128_type_node,
17783 float128_type_node,
17784 float128_type_node,
17786 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
17789 /* Add all SSE builtins that are more or less simple operations on
17791 for (i = 0, d = bdesc_sse_3arg;
17792 i < ARRAY_SIZE (bdesc_sse_3arg);
17795 /* Use one of the operands; the target can have a different mode for
17796 mask-generating compares. */
17797 enum machine_mode mode;
17802 mode = insn_data[d->icode].operand[1].mode;
17807 type = v16qi_ftype_v16qi_v16qi_int;
17810 type = v8hi_ftype_v8hi_v8hi_int;
17813 type = v4si_ftype_v4si_v4si_int;
17816 type = v2di_ftype_v2di_v2di_int;
17819 type = v2df_ftype_v2df_v2df_int;
17822 type = v4sf_ftype_v4sf_v4sf_int;
17825 gcc_unreachable ();
17828 /* Override for variable blends. */
17831 case CODE_FOR_sse4_1_blendvpd:
17832 type = v2df_ftype_v2df_v2df_v2df;
17834 case CODE_FOR_sse4_1_blendvps:
17835 type = v4sf_ftype_v4sf_v4sf_v4sf;
17837 case CODE_FOR_sse4_1_pblendvb:
17838 type = v16qi_ftype_v16qi_v16qi_v16qi;
17844 def_builtin (d->mask, d->name, type, d->code);
17847 /* Add all builtins that are more or less simple operations on two
17849 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17851 /* Use one of the operands; the target can have a different mode for
17852 mask-generating compares. */
17853 enum machine_mode mode;
17858 mode = insn_data[d->icode].operand[1].mode;
17863 type = v16qi_ftype_v16qi_v16qi;
17866 type = v8hi_ftype_v8hi_v8hi;
17869 type = v4si_ftype_v4si_v4si;
17872 type = v2di_ftype_v2di_v2di;
17875 type = v2df_ftype_v2df_v2df;
17878 type = v4sf_ftype_v4sf_v4sf;
17881 type = v8qi_ftype_v8qi_v8qi;
17884 type = v4hi_ftype_v4hi_v4hi;
17887 type = v2si_ftype_v2si_v2si;
17890 type = di_ftype_di_di;
17894 gcc_unreachable ();
17897 /* Override for comparisons. */
17898 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
17899 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
17900 type = v4si_ftype_v4sf_v4sf;
17902 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
17903 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
17904 type = v2di_ftype_v2df_v2df;
17906 def_builtin (d->mask, d->name, type, d->code);
17909 /* Add all builtins that are more or less simple operations on 1 operand. */
17910 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17912 enum machine_mode mode;
17917 mode = insn_data[d->icode].operand[1].mode;
17922 type = v16qi_ftype_v16qi;
17925 type = v8hi_ftype_v8hi;
17928 type = v4si_ftype_v4si;
17931 type = v2df_ftype_v2df;
17934 type = v4sf_ftype_v4sf;
17937 type = v8qi_ftype_v8qi;
17940 type = v4hi_ftype_v4hi;
17943 type = v2si_ftype_v2si;
17950 def_builtin (d->mask, d->name, type, d->code);
17953 /* pcmpestr[im] insns. */
17954 for (i = 0, d = bdesc_pcmpestr;
17955 i < ARRAY_SIZE (bdesc_pcmpestr);
17958 if (d->code == IX86_BUILTIN_PCMPESTRM128)
17959 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
17961 ftype = int_ftype_v16qi_int_v16qi_int_int;
17962 def_builtin (d->mask, d->name, ftype, d->code);
17965 /* pcmpistr[im] insns. */
17966 for (i = 0, d = bdesc_pcmpistr;
17967 i < ARRAY_SIZE (bdesc_pcmpistr);
17970 if (d->code == IX86_BUILTIN_PCMPISTRM128)
17971 ftype = v16qi_ftype_v16qi_v16qi_int;
17973 ftype = int_ftype_v16qi_v16qi_int;
17974 def_builtin (d->mask, d->name, ftype, d->code);
17977 /* Add the remaining MMX insns with somewhat more complicated types. */
17978 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
17979 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
17980 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
17981 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
17983 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
17984 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
17985 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
17987 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
17988 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
17990 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
17991 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
17993 /* comi/ucomi insns. */
17994 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
17995 if (d->mask == OPTION_MASK_ISA_SSE2)
17996 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
17998 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
18001 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
18002 def_builtin (d->mask, d->name, int_ftype_v2di_v2di, d->code);
18004 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
18005 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
18006 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
18008 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
18009 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
18010 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
18011 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
18012 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
18013 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
18014 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
18015 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
18016 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
18017 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
18018 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
18020 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
18022 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
18023 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
18025 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
18026 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
18027 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
18028 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
18030 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
18031 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
18032 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
18033 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
18035 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
18037 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
18039 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
18040 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
18041 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
18042 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
18043 ftype = build_function_type_list (float_type_node,
18046 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtf", ftype, IX86_BUILTIN_RSQRTF);
18047 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
18048 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
18050 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
18052 /* Original 3DNow! */
18053 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
18054 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
18055 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
18056 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
18057 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
18058 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
18059 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
18060 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
18061 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
18062 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
18063 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
18064 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
18065 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
18066 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
18067 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
18068 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
18069 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
18070 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
18071 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
18072 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
18074 /* 3DNow! extension as used in the Athlon CPU. */
18075 def_builtin (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
18076 def_builtin (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
18077 def_builtin (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
18078 def_builtin (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
18079 def_builtin (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
18080 def_builtin (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
18083 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
18085 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
18086 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
18088 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
18089 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
18091 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
18092 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
18093 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
18094 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
18095 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
18097 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
18098 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
18099 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
18100 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
18102 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
18103 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
18105 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
18107 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
18108 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
18110 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
18111 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
18112 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
18113 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
18114 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
18116 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
18118 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
18119 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
18120 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
18121 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
18123 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
18124 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
18125 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
18127 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
18128 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
18129 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
18130 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
18132 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
18133 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
18134 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
18136 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
18137 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
18139 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
18140 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
18142 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
18143 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
18144 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
18145 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
18146 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
18147 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
18148 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
18150 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
18151 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
18152 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
18153 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
18154 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
18155 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
18156 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
18158 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
18159 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
18160 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
18161 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
18163 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
18165 /* Prescott New Instructions. */
18166 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
18167 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
18168 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
18171 def_builtin (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
18172 def_builtin (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int, IX86_BUILTIN_PALIGNR);
18175 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_movntdqa", v2di_ftype_pv2di, IX86_BUILTIN_MOVNTDQA);
18176 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVSXBW128);
18177 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVSXBD128);
18178 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVSXBQ128);
18179 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVSXWD128);
18180 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVSXWQ128);
18181 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVSXDQ128);
18182 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVZXBW128);
18183 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVZXBD128);
18184 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVZXBQ128);
18185 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVZXWD128);
18186 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVZXWQ128);
18187 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVZXDQ128);
18188 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmuldq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULDQ128);
18189 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_roundpd", v2df_ftype_v2df_int, IX86_BUILTIN_ROUNDPD);
18190 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_roundps", v4sf_ftype_v4sf_int, IX86_BUILTIN_ROUNDPS);
18191 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_roundsd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_ROUNDSD);
18192 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_roundss", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_ROUNDSS);
18195 ftype = build_function_type_list (unsigned_type_node,
18196 unsigned_type_node,
18197 unsigned_char_type_node,
18199 def_builtin (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32qi", ftype, IX86_BUILTIN_CRC32QI);
18200 ftype = build_function_type_list (unsigned_type_node,
18201 unsigned_type_node,
18202 short_unsigned_type_node,
18204 def_builtin (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32hi", ftype, IX86_BUILTIN_CRC32HI);
18205 ftype = build_function_type_list (unsigned_type_node,
18206 unsigned_type_node,
18207 unsigned_type_node,
18209 def_builtin (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32si", ftype, IX86_BUILTIN_CRC32SI);
18210 ftype = build_function_type_list (long_long_unsigned_type_node,
18211 long_long_unsigned_type_node,
18212 long_long_unsigned_type_node,
18214 def_builtin (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32di", ftype, IX86_BUILTIN_CRC32DI);
18216 /* AMDFAM10 SSE4A New built-ins */
18217 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntsd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTSD);
18218 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntss", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTSS);
18219 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrqi", v2di_ftype_v2di_unsigned_unsigned, IX86_BUILTIN_EXTRQI);
18220 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrq", v2di_ftype_v2di_v16qi, IX86_BUILTIN_EXTRQ);
18221 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertqi", v2di_ftype_v2di_v2di_unsigned_unsigned, IX86_BUILTIN_INSERTQI);
18222 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertq", v2di_ftype_v2di_v2di, IX86_BUILTIN_INSERTQ);
18224 /* Access to the vec_init patterns. */
18225 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
18226 integer_type_node, NULL_TREE);
18227 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
18229 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
18230 short_integer_type_node,
18231 short_integer_type_node,
18232 short_integer_type_node, NULL_TREE);
18233 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
18235 ftype = build_function_type_list (V8QI_type_node, char_type_node,
18236 char_type_node, char_type_node,
18237 char_type_node, char_type_node,
18238 char_type_node, char_type_node,
18239 char_type_node, NULL_TREE);
18240 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
18242 /* Access to the vec_extract patterns. */
18243 ftype = build_function_type_list (double_type_node, V2DF_type_node,
18244 integer_type_node, NULL_TREE);
18245 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
18247 ftype = build_function_type_list (long_long_integer_type_node,
18248 V2DI_type_node, integer_type_node,
18250 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
18252 ftype = build_function_type_list (float_type_node, V4SF_type_node,
18253 integer_type_node, NULL_TREE);
18254 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
18256 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
18257 integer_type_node, NULL_TREE);
18258 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
18260 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
18261 integer_type_node, NULL_TREE);
18262 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
18264 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
18265 integer_type_node, NULL_TREE);
18266 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
18268 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
18269 integer_type_node, NULL_TREE);
18270 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
18272 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
18273 integer_type_node, NULL_TREE);
18274 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
18276 /* Access to the vec_set patterns. */
18277 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
18279 integer_type_node, NULL_TREE);
18280 def_builtin (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
18282 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
18284 integer_type_node, NULL_TREE);
18285 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
18287 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
18289 integer_type_node, NULL_TREE);
18290 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
18292 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
18294 integer_type_node, NULL_TREE);
18295 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
18297 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
18299 integer_type_node, NULL_TREE);
18300 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
18302 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
18304 integer_type_node, NULL_TREE);
18305 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
18309 ix86_init_builtins (void)
18312 ix86_init_mmx_sse_builtins ();
18315 /* Errors in the source file can cause expand_expr to return const0_rtx
18316 where we expect a vector. To avoid crashing, use one of the vector
18317 clear instructions. */
18319 safe_vector_operand (rtx x, enum machine_mode mode)
18321 if (x == const0_rtx)
18322 x = CONST0_RTX (mode);
18326 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
18327 4 operands. The third argument must be a constant smaller than 8
18331 ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
18335 tree arg0 = CALL_EXPR_ARG (exp, 0);
18336 tree arg1 = CALL_EXPR_ARG (exp, 1);
18337 tree arg2 = CALL_EXPR_ARG (exp, 2);
18338 rtx op0 = expand_normal (arg0);
18339 rtx op1 = expand_normal (arg1);
18340 rtx op2 = expand_normal (arg2);
18341 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18342 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
18343 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
18344 enum machine_mode mode3 = insn_data[icode].operand[3].mode;
18346 if (VECTOR_MODE_P (mode1))
18347 op0 = safe_vector_operand (op0, mode1);
18348 if (VECTOR_MODE_P (mode2))
18349 op1 = safe_vector_operand (op1, mode2);
18350 if (VECTOR_MODE_P (mode3))
18351 op2 = safe_vector_operand (op2, mode3);
18355 || GET_MODE (target) != tmode
18356 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18357 target = gen_reg_rtx (tmode);
18359 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
18360 op0 = copy_to_mode_reg (mode1, op0);
18361 if ((optimize && !register_operand (op1, mode2))
18362 || !(*insn_data[icode].operand[2].predicate) (op1, mode2))
18363 op1 = copy_to_mode_reg (mode2, op1);
18365 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
18368 case CODE_FOR_sse4_1_blendvpd:
18369 case CODE_FOR_sse4_1_blendvps:
18370 case CODE_FOR_sse4_1_pblendvb:
18371 op2 = copy_to_mode_reg (mode3, op2);
18374 case CODE_FOR_sse4_1_roundsd:
18375 case CODE_FOR_sse4_1_roundss:
18376 error ("the third argument must be a 4-bit immediate");
18380 error ("the third argument must be an 8-bit immediate");
18384 pat = GEN_FCN (icode) (target, op0, op1, op2);
18391 /* Subroutine of ix86_expand_builtin to take care of crc32 insns. */
18394 ix86_expand_crc32 (enum insn_code icode, tree exp, rtx target)
18397 tree arg0 = CALL_EXPR_ARG (exp, 0);
18398 tree arg1 = CALL_EXPR_ARG (exp, 1);
18399 rtx op0 = expand_normal (arg0);
18400 rtx op1 = expand_normal (arg1);
18401 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18402 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18403 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
18407 || GET_MODE (target) != tmode
18408 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18409 target = gen_reg_rtx (tmode);
18411 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
18412 op0 = copy_to_mode_reg (mode0, op0);
18413 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
18415 op1 = copy_to_reg (op1);
18416 op1 = simplify_gen_subreg (mode1, op1, GET_MODE (op1), 0);
18419 pat = GEN_FCN (icode) (target, op0, op1);
18426 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
18429 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
18432 tree arg0 = CALL_EXPR_ARG (exp, 0);
18433 tree arg1 = CALL_EXPR_ARG (exp, 1);
18434 rtx op0 = expand_normal (arg0);
18435 rtx op1 = expand_normal (arg1);
18436 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18437 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18438 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
18440 if (VECTOR_MODE_P (mode0))
18441 op0 = safe_vector_operand (op0, mode0);
18442 if (VECTOR_MODE_P (mode1))
18443 op1 = safe_vector_operand (op1, mode1);
18445 if (optimize || !target
18446 || GET_MODE (target) != tmode
18447 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18448 target = gen_reg_rtx (tmode);
18450 if (GET_MODE (op1) == SImode && mode1 == TImode)
18452 rtx x = gen_reg_rtx (V4SImode);
18453 emit_insn (gen_sse2_loadd (x, op1));
18454 op1 = gen_lowpart (TImode, x);
18457 /* The insn must want input operands in the same modes as the
18459 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
18460 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
18462 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
18463 op0 = copy_to_mode_reg (mode0, op0);
18464 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
18465 op1 = copy_to_mode_reg (mode1, op1);
18467 /* ??? Using ix86_fixup_binary_operands is problematic when
18468 we've got mismatched modes. Fake it. */
18474 if (tmode == mode0 && tmode == mode1)
18476 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
18480 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
18482 op0 = force_reg (mode0, op0);
18483 op1 = force_reg (mode1, op1);
18484 target = gen_reg_rtx (tmode);
18487 pat = GEN_FCN (icode) (target, op0, op1);
18494 /* Subroutine of ix86_expand_builtin to take care of stores. */
18497 ix86_expand_store_builtin (enum insn_code icode, tree exp)
18500 tree arg0 = CALL_EXPR_ARG (exp, 0);
18501 tree arg1 = CALL_EXPR_ARG (exp, 1);
18502 rtx op0 = expand_normal (arg0);
18503 rtx op1 = expand_normal (arg1);
18504 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
18505 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
18507 if (VECTOR_MODE_P (mode1))
18508 op1 = safe_vector_operand (op1, mode1);
18510 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
18511 op1 = copy_to_mode_reg (mode1, op1);
18513 pat = GEN_FCN (icode) (op0, op1);
18519 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
18522 ix86_expand_unop_builtin (enum insn_code icode, tree exp,
18523 rtx target, int do_load)
18526 tree arg0 = CALL_EXPR_ARG (exp, 0);
18527 rtx op0 = expand_normal (arg0);
18528 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18529 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18531 if (optimize || !target
18532 || GET_MODE (target) != tmode
18533 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18534 target = gen_reg_rtx (tmode);
18536 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
18539 if (VECTOR_MODE_P (mode0))
18540 op0 = safe_vector_operand (op0, mode0);
18542 if ((optimize && !register_operand (op0, mode0))
18543 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
18544 op0 = copy_to_mode_reg (mode0, op0);
18549 case CODE_FOR_sse4_1_roundpd:
18550 case CODE_FOR_sse4_1_roundps:
18552 tree arg1 = CALL_EXPR_ARG (exp, 1);
18553 rtx op1 = expand_normal (arg1);
18554 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
18556 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
18558 error ("the second argument must be a 4-bit immediate");
18561 pat = GEN_FCN (icode) (target, op0, op1);
18565 pat = GEN_FCN (icode) (target, op0);
18575 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
18576 sqrtss, rsqrtss, rcpss. */
18579 ix86_expand_unop1_builtin (enum insn_code icode, tree exp, rtx target)
18582 tree arg0 = CALL_EXPR_ARG (exp, 0);
18583 rtx op1, op0 = expand_normal (arg0);
18584 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18585 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18587 if (optimize || !target
18588 || GET_MODE (target) != tmode
18589 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18590 target = gen_reg_rtx (tmode);
18592 if (VECTOR_MODE_P (mode0))
18593 op0 = safe_vector_operand (op0, mode0);
18595 if ((optimize && !register_operand (op0, mode0))
18596 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
18597 op0 = copy_to_mode_reg (mode0, op0);
18600 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
18601 op1 = copy_to_mode_reg (mode0, op1);
18603 pat = GEN_FCN (icode) (target, op0, op1);
18610 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
18613 ix86_expand_sse_compare (const struct builtin_description *d, tree exp,
18617 tree arg0 = CALL_EXPR_ARG (exp, 0);
18618 tree arg1 = CALL_EXPR_ARG (exp, 1);
18619 rtx op0 = expand_normal (arg0);
18620 rtx op1 = expand_normal (arg1);
18622 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
18623 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
18624 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
18625 enum rtx_code comparison = d->comparison;
18627 if (VECTOR_MODE_P (mode0))
18628 op0 = safe_vector_operand (op0, mode0);
18629 if (VECTOR_MODE_P (mode1))
18630 op1 = safe_vector_operand (op1, mode1);
18632 /* Swap operands if we have a comparison that isn't available in
18634 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
18636 rtx tmp = gen_reg_rtx (mode1);
18637 emit_move_insn (tmp, op1);
18642 if (optimize || !target
18643 || GET_MODE (target) != tmode
18644 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
18645 target = gen_reg_rtx (tmode);
18647 if ((optimize && !register_operand (op0, mode0))
18648 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
18649 op0 = copy_to_mode_reg (mode0, op0);
18650 if ((optimize && !register_operand (op1, mode1))
18651 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
18652 op1 = copy_to_mode_reg (mode1, op1);
18654 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
18655 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
18662 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
18665 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
18669 tree arg0 = CALL_EXPR_ARG (exp, 0);
18670 tree arg1 = CALL_EXPR_ARG (exp, 1);
18671 rtx op0 = expand_normal (arg0);
18672 rtx op1 = expand_normal (arg1);
18673 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
18674 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
18675 enum rtx_code comparison = d->comparison;
18677 if (VECTOR_MODE_P (mode0))
18678 op0 = safe_vector_operand (op0, mode0);
18679 if (VECTOR_MODE_P (mode1))
18680 op1 = safe_vector_operand (op1, mode1);
18682 /* Swap operands if we have a comparison that isn't available in
18684 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
18691 target = gen_reg_rtx (SImode);
18692 emit_move_insn (target, const0_rtx);
18693 target = gen_rtx_SUBREG (QImode, target, 0);
18695 if ((optimize && !register_operand (op0, mode0))
18696 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
18697 op0 = copy_to_mode_reg (mode0, op0);
18698 if ((optimize && !register_operand (op1, mode1))
18699 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
18700 op1 = copy_to_mode_reg (mode1, op1);
18702 pat = GEN_FCN (d->icode) (op0, op1);
18706 emit_insn (gen_rtx_SET (VOIDmode,
18707 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
18708 gen_rtx_fmt_ee (comparison, QImode,
18712 return SUBREG_REG (target);
18715 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
18718 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
18722 tree arg0 = CALL_EXPR_ARG (exp, 0);
18723 tree arg1 = CALL_EXPR_ARG (exp, 1);
18724 rtx op0 = expand_normal (arg0);
18725 rtx op1 = expand_normal (arg1);
18726 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
18727 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
18728 enum rtx_code comparison = d->comparison;
18730 if (VECTOR_MODE_P (mode0))
18731 op0 = safe_vector_operand (op0, mode0);
18732 if (VECTOR_MODE_P (mode1))
18733 op1 = safe_vector_operand (op1, mode1);
18735 target = gen_reg_rtx (SImode);
18736 emit_move_insn (target, const0_rtx);
18737 target = gen_rtx_SUBREG (QImode, target, 0);
18739 if ((optimize && !register_operand (op0, mode0))
18740 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
18741 op0 = copy_to_mode_reg (mode0, op0);
18742 if ((optimize && !register_operand (op1, mode1))
18743 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
18744 op1 = copy_to_mode_reg (mode1, op1);
18746 pat = GEN_FCN (d->icode) (op0, op1);
18750 emit_insn (gen_rtx_SET (VOIDmode,
18751 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
18752 gen_rtx_fmt_ee (comparison, QImode,
18756 return SUBREG_REG (target);
18759 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
18762 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
18763 tree exp, rtx target)
18766 tree arg0 = CALL_EXPR_ARG (exp, 0);
18767 tree arg1 = CALL_EXPR_ARG (exp, 1);
18768 tree arg2 = CALL_EXPR_ARG (exp, 2);
18769 tree arg3 = CALL_EXPR_ARG (exp, 3);
18770 tree arg4 = CALL_EXPR_ARG (exp, 4);
18771 rtx scratch0, scratch1;
18772 rtx op0 = expand_normal (arg0);
18773 rtx op1 = expand_normal (arg1);
18774 rtx op2 = expand_normal (arg2);
18775 rtx op3 = expand_normal (arg3);
18776 rtx op4 = expand_normal (arg4);
18777 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
18779 tmode0 = insn_data[d->icode].operand[0].mode;
18780 tmode1 = insn_data[d->icode].operand[1].mode;
18781 modev2 = insn_data[d->icode].operand[2].mode;
18782 modei3 = insn_data[d->icode].operand[3].mode;
18783 modev4 = insn_data[d->icode].operand[4].mode;
18784 modei5 = insn_data[d->icode].operand[5].mode;
18785 modeimm = insn_data[d->icode].operand[6].mode;
18787 if (VECTOR_MODE_P (modev2))
18788 op0 = safe_vector_operand (op0, modev2);
18789 if (VECTOR_MODE_P (modev4))
18790 op2 = safe_vector_operand (op2, modev4);
18792 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
18793 op0 = copy_to_mode_reg (modev2, op0);
18794 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
18795 op1 = copy_to_mode_reg (modei3, op1);
18796 if ((optimize && !register_operand (op2, modev4))
18797 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
18798 op2 = copy_to_mode_reg (modev4, op2);
18799 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
18800 op3 = copy_to_mode_reg (modei5, op3);
18802 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
18804 error ("the fifth argument must be a 8-bit immediate");
18808 if (d->code == IX86_BUILTIN_PCMPESTRI128)
18810 if (optimize || !target
18811 || GET_MODE (target) != tmode0
18812 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
18813 target = gen_reg_rtx (tmode0);
18815 scratch1 = gen_reg_rtx (tmode1);
18817 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
18819 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
18821 if (optimize || !target
18822 || GET_MODE (target) != tmode1
18823 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
18824 target = gen_reg_rtx (tmode1);
18826 scratch0 = gen_reg_rtx (tmode0);
18828 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
18832 gcc_assert (d->flag);
18834 scratch0 = gen_reg_rtx (tmode0);
18835 scratch1 = gen_reg_rtx (tmode1);
18837 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
18847 target = gen_reg_rtx (SImode);
18848 emit_move_insn (target, const0_rtx);
18849 target = gen_rtx_SUBREG (QImode, target, 0);
18852 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
18853 gen_rtx_fmt_ee (EQ, QImode,
18854 gen_rtx_REG ((enum machine_mode) d->flag,
18857 return SUBREG_REG (target);
18864 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
18867 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
18868 tree exp, rtx target)
18871 tree arg0 = CALL_EXPR_ARG (exp, 0);
18872 tree arg1 = CALL_EXPR_ARG (exp, 1);
18873 tree arg2 = CALL_EXPR_ARG (exp, 2);
18874 rtx scratch0, scratch1;
18875 rtx op0 = expand_normal (arg0);
18876 rtx op1 = expand_normal (arg1);
18877 rtx op2 = expand_normal (arg2);
18878 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
18880 tmode0 = insn_data[d->icode].operand[0].mode;
18881 tmode1 = insn_data[d->icode].operand[1].mode;
18882 modev2 = insn_data[d->icode].operand[2].mode;
18883 modev3 = insn_data[d->icode].operand[3].mode;
18884 modeimm = insn_data[d->icode].operand[4].mode;
18886 if (VECTOR_MODE_P (modev2))
18887 op0 = safe_vector_operand (op0, modev2);
18888 if (VECTOR_MODE_P (modev3))
18889 op1 = safe_vector_operand (op1, modev3);
18891 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
18892 op0 = copy_to_mode_reg (modev2, op0);
18893 if ((optimize && !register_operand (op1, modev3))
18894 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
18895 op1 = copy_to_mode_reg (modev3, op1);
18897 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
18899 error ("the third argument must be a 8-bit immediate");
18903 if (d->code == IX86_BUILTIN_PCMPISTRI128)
18905 if (optimize || !target
18906 || GET_MODE (target) != tmode0
18907 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
18908 target = gen_reg_rtx (tmode0);
18910 scratch1 = gen_reg_rtx (tmode1);
18912 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
18914 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
18916 if (optimize || !target
18917 || GET_MODE (target) != tmode1
18918 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
18919 target = gen_reg_rtx (tmode1);
18921 scratch0 = gen_reg_rtx (tmode0);
18923 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
18927 gcc_assert (d->flag);
18929 scratch0 = gen_reg_rtx (tmode0);
18930 scratch1 = gen_reg_rtx (tmode1);
18932 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
18942 target = gen_reg_rtx (SImode);
18943 emit_move_insn (target, const0_rtx);
18944 target = gen_rtx_SUBREG (QImode, target, 0);
18947 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
18948 gen_rtx_fmt_ee (EQ, QImode,
18949 gen_rtx_REG ((enum machine_mode) d->flag,
18952 return SUBREG_REG (target);
18958 /* Return the integer constant in ARG. Constrain it to be in the range
18959 of the subparts of VEC_TYPE; issue an error if not. */
18962 get_element_number (tree vec_type, tree arg)
18964 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
18966 if (!host_integerp (arg, 1)
18967 || (elt = tree_low_cst (arg, 1), elt > max))
18969 error ("selector must be an integer constant in the range 0..%wi", max);
18976 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
18977 ix86_expand_vector_init. We DO have language-level syntax for this, in
18978 the form of (type){ init-list }. Except that since we can't place emms
18979 instructions from inside the compiler, we can't allow the use of MMX
18980 registers unless the user explicitly asks for it. So we do *not* define
18981 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
18982 we have builtins invoked by mmintrin.h that gives us license to emit
18983 these sorts of instructions. */
18986 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
18988 enum machine_mode tmode = TYPE_MODE (type);
18989 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
18990 int i, n_elt = GET_MODE_NUNITS (tmode);
18991 rtvec v = rtvec_alloc (n_elt);
18993 gcc_assert (VECTOR_MODE_P (tmode));
18994 gcc_assert (call_expr_nargs (exp) == n_elt);
18996 for (i = 0; i < n_elt; ++i)
18998 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
18999 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
19002 if (!target || !register_operand (target, tmode))
19003 target = gen_reg_rtx (tmode);
19005 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
19009 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
19010 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
19011 had a language-level syntax for referencing vector elements. */
19014 ix86_expand_vec_ext_builtin (tree exp, rtx target)
19016 enum machine_mode tmode, mode0;
19021 arg0 = CALL_EXPR_ARG (exp, 0);
19022 arg1 = CALL_EXPR_ARG (exp, 1);
19024 op0 = expand_normal (arg0);
19025 elt = get_element_number (TREE_TYPE (arg0), arg1);
19027 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
19028 mode0 = TYPE_MODE (TREE_TYPE (arg0));
19029 gcc_assert (VECTOR_MODE_P (mode0));
19031 op0 = force_reg (mode0, op0);
19033 if (optimize || !target || !register_operand (target, tmode))
19034 target = gen_reg_rtx (tmode);
19036 ix86_expand_vector_extract (true, target, op0, elt);
19041 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
19042 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
19043 a language-level syntax for referencing vector elements. */
19046 ix86_expand_vec_set_builtin (tree exp)
19048 enum machine_mode tmode, mode1;
19049 tree arg0, arg1, arg2;
19051 rtx op0, op1, target;
19053 arg0 = CALL_EXPR_ARG (exp, 0);
19054 arg1 = CALL_EXPR_ARG (exp, 1);
19055 arg2 = CALL_EXPR_ARG (exp, 2);
19057 tmode = TYPE_MODE (TREE_TYPE (arg0));
19058 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
19059 gcc_assert (VECTOR_MODE_P (tmode));
19061 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
19062 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
19063 elt = get_element_number (TREE_TYPE (arg0), arg2);
19065 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
19066 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
19068 op0 = force_reg (tmode, op0);
19069 op1 = force_reg (mode1, op1);
19071 /* OP0 is the source of these builtin functions and shouldn't be
19072 modified. Create a copy, use it and return it as target. */
19073 target = gen_reg_rtx (tmode);
19074 emit_move_insn (target, op0);
19075 ix86_expand_vector_set (true, target, op1, elt);
19080 /* Expand an expression EXP that calls a built-in function,
19081 with result going to TARGET if that's convenient
19082 (and in mode MODE if that's convenient).
19083 SUBTARGET may be used as the target for computing one of EXP's operands.
19084 IGNORE is nonzero if the value is to be ignored. */
19087 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
19088 enum machine_mode mode ATTRIBUTE_UNUSED,
19089 int ignore ATTRIBUTE_UNUSED)
19091 const struct builtin_description *d;
19093 enum insn_code icode;
19094 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
19095 tree arg0, arg1, arg2, arg3;
19096 rtx op0, op1, op2, op3, pat;
19097 enum machine_mode tmode, mode0, mode1, mode2, mode3, mode4;
19098 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
19102 case IX86_BUILTIN_EMMS:
19103 emit_insn (gen_mmx_emms ());
19106 case IX86_BUILTIN_SFENCE:
19107 emit_insn (gen_sse_sfence ());
19110 case IX86_BUILTIN_MASKMOVQ:
19111 case IX86_BUILTIN_MASKMOVDQU:
19112 icode = (fcode == IX86_BUILTIN_MASKMOVQ
19113 ? CODE_FOR_mmx_maskmovq
19114 : CODE_FOR_sse2_maskmovdqu);
19115 /* Note the arg order is different from the operand order. */
19116 arg1 = CALL_EXPR_ARG (exp, 0);
19117 arg2 = CALL_EXPR_ARG (exp, 1);
19118 arg0 = CALL_EXPR_ARG (exp, 2);
19119 op0 = expand_normal (arg0);
19120 op1 = expand_normal (arg1);
19121 op2 = expand_normal (arg2);
19122 mode0 = insn_data[icode].operand[0].mode;
19123 mode1 = insn_data[icode].operand[1].mode;
19124 mode2 = insn_data[icode].operand[2].mode;
19126 op0 = force_reg (Pmode, op0);
19127 op0 = gen_rtx_MEM (mode1, op0);
19129 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
19130 op0 = copy_to_mode_reg (mode0, op0);
19131 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
19132 op1 = copy_to_mode_reg (mode1, op1);
19133 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
19134 op2 = copy_to_mode_reg (mode2, op2);
19135 pat = GEN_FCN (icode) (op0, op1, op2);
19141 case IX86_BUILTIN_RSQRTF:
19142 return ix86_expand_unop1_builtin (CODE_FOR_rsqrtsf2, exp, target);
19144 case IX86_BUILTIN_SQRTSS:
19145 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, exp, target);
19146 case IX86_BUILTIN_RSQRTSS:
19147 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, exp, target);
19148 case IX86_BUILTIN_RCPSS:
19149 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, exp, target);
19151 case IX86_BUILTIN_LOADUPS:
19152 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, exp, target, 1);
19154 case IX86_BUILTIN_STOREUPS:
19155 return ix86_expand_store_builtin (CODE_FOR_sse_movups, exp);
19157 case IX86_BUILTIN_LOADHPS:
19158 case IX86_BUILTIN_LOADLPS:
19159 case IX86_BUILTIN_LOADHPD:
19160 case IX86_BUILTIN_LOADLPD:
19161 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
19162 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
19163 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
19164 : CODE_FOR_sse2_loadlpd);
19165 arg0 = CALL_EXPR_ARG (exp, 0);
19166 arg1 = CALL_EXPR_ARG (exp, 1);
19167 op0 = expand_normal (arg0);
19168 op1 = expand_normal (arg1);
19169 tmode = insn_data[icode].operand[0].mode;
19170 mode0 = insn_data[icode].operand[1].mode;
19171 mode1 = insn_data[icode].operand[2].mode;
19173 op0 = force_reg (mode0, op0);
19174 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
19175 if (optimize || target == 0
19176 || GET_MODE (target) != tmode
19177 || !register_operand (target, tmode))
19178 target = gen_reg_rtx (tmode);
19179 pat = GEN_FCN (icode) (target, op0, op1);
19185 case IX86_BUILTIN_STOREHPS:
19186 case IX86_BUILTIN_STORELPS:
19187 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
19188 : CODE_FOR_sse_storelps);
19189 arg0 = CALL_EXPR_ARG (exp, 0);
19190 arg1 = CALL_EXPR_ARG (exp, 1);
19191 op0 = expand_normal (arg0);
19192 op1 = expand_normal (arg1);
19193 mode0 = insn_data[icode].operand[0].mode;
19194 mode1 = insn_data[icode].operand[1].mode;
19196 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
19197 op1 = force_reg (mode1, op1);
19199 pat = GEN_FCN (icode) (op0, op1);
19205 case IX86_BUILTIN_MOVNTPS:
19206 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, exp);
19207 case IX86_BUILTIN_MOVNTQ:
19208 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, exp);
19210 case IX86_BUILTIN_LDMXCSR:
19211 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
19212 target = assign_386_stack_local (SImode, SLOT_TEMP);
19213 emit_move_insn (target, op0);
19214 emit_insn (gen_sse_ldmxcsr (target));
19217 case IX86_BUILTIN_STMXCSR:
19218 target = assign_386_stack_local (SImode, SLOT_TEMP);
19219 emit_insn (gen_sse_stmxcsr (target));
19220 return copy_to_mode_reg (SImode, target);
19222 case IX86_BUILTIN_SHUFPS:
19223 case IX86_BUILTIN_SHUFPD:
19224 icode = (fcode == IX86_BUILTIN_SHUFPS
19225 ? CODE_FOR_sse_shufps
19226 : CODE_FOR_sse2_shufpd);
19227 arg0 = CALL_EXPR_ARG (exp, 0);
19228 arg1 = CALL_EXPR_ARG (exp, 1);
19229 arg2 = CALL_EXPR_ARG (exp, 2);
19230 op0 = expand_normal (arg0);
19231 op1 = expand_normal (arg1);
19232 op2 = expand_normal (arg2);
19233 tmode = insn_data[icode].operand[0].mode;
19234 mode0 = insn_data[icode].operand[1].mode;
19235 mode1 = insn_data[icode].operand[2].mode;
19236 mode2 = insn_data[icode].operand[3].mode;
19238 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
19239 op0 = copy_to_mode_reg (mode0, op0);
19240 if ((optimize && !register_operand (op1, mode1))
19241 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
19242 op1 = copy_to_mode_reg (mode1, op1);
19243 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
19245 /* @@@ better error message */
19246 error ("mask must be an immediate");
19247 return gen_reg_rtx (tmode);
19249 if (optimize || target == 0
19250 || GET_MODE (target) != tmode
19251 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19252 target = gen_reg_rtx (tmode);
19253 pat = GEN_FCN (icode) (target, op0, op1, op2);
19259 case IX86_BUILTIN_PSHUFW:
19260 case IX86_BUILTIN_PSHUFD:
19261 case IX86_BUILTIN_PSHUFHW:
19262 case IX86_BUILTIN_PSHUFLW:
19263 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
19264 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
19265 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
19266 : CODE_FOR_mmx_pshufw);
19267 arg0 = CALL_EXPR_ARG (exp, 0);
19268 arg1 = CALL_EXPR_ARG (exp, 1);
19269 op0 = expand_normal (arg0);
19270 op1 = expand_normal (arg1);
19271 tmode = insn_data[icode].operand[0].mode;
19272 mode1 = insn_data[icode].operand[1].mode;
19273 mode2 = insn_data[icode].operand[2].mode;
19275 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19276 op0 = copy_to_mode_reg (mode1, op0);
19277 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19279 /* @@@ better error message */
19280 error ("mask must be an immediate");
19284 || GET_MODE (target) != tmode
19285 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19286 target = gen_reg_rtx (tmode);
19287 pat = GEN_FCN (icode) (target, op0, op1);
19293 case IX86_BUILTIN_PSLLWI128:
19294 icode = CODE_FOR_ashlv8hi3;
19296 case IX86_BUILTIN_PSLLDI128:
19297 icode = CODE_FOR_ashlv4si3;
19299 case IX86_BUILTIN_PSLLQI128:
19300 icode = CODE_FOR_ashlv2di3;
19302 case IX86_BUILTIN_PSRAWI128:
19303 icode = CODE_FOR_ashrv8hi3;
19305 case IX86_BUILTIN_PSRADI128:
19306 icode = CODE_FOR_ashrv4si3;
19308 case IX86_BUILTIN_PSRLWI128:
19309 icode = CODE_FOR_lshrv8hi3;
19311 case IX86_BUILTIN_PSRLDI128:
19312 icode = CODE_FOR_lshrv4si3;
19314 case IX86_BUILTIN_PSRLQI128:
19315 icode = CODE_FOR_lshrv2di3;
19318 arg0 = CALL_EXPR_ARG (exp, 0);
19319 arg1 = CALL_EXPR_ARG (exp, 1);
19320 op0 = expand_normal (arg0);
19321 op1 = expand_normal (arg1);
19323 if (!CONST_INT_P (op1))
19325 error ("shift must be an immediate");
19328 if (INTVAL (op1) < 0 || INTVAL (op1) > 255)
19329 op1 = GEN_INT (255);
19331 tmode = insn_data[icode].operand[0].mode;
19332 mode1 = insn_data[icode].operand[1].mode;
19333 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19334 op0 = copy_to_reg (op0);
19336 target = gen_reg_rtx (tmode);
19337 pat = GEN_FCN (icode) (target, op0, op1);
19343 case IX86_BUILTIN_PSLLW128:
19344 icode = CODE_FOR_ashlv8hi3;
19346 case IX86_BUILTIN_PSLLD128:
19347 icode = CODE_FOR_ashlv4si3;
19349 case IX86_BUILTIN_PSLLQ128:
19350 icode = CODE_FOR_ashlv2di3;
19352 case IX86_BUILTIN_PSRAW128:
19353 icode = CODE_FOR_ashrv8hi3;
19355 case IX86_BUILTIN_PSRAD128:
19356 icode = CODE_FOR_ashrv4si3;
19358 case IX86_BUILTIN_PSRLW128:
19359 icode = CODE_FOR_lshrv8hi3;
19361 case IX86_BUILTIN_PSRLD128:
19362 icode = CODE_FOR_lshrv4si3;
19364 case IX86_BUILTIN_PSRLQ128:
19365 icode = CODE_FOR_lshrv2di3;
19368 arg0 = CALL_EXPR_ARG (exp, 0);
19369 arg1 = CALL_EXPR_ARG (exp, 1);
19370 op0 = expand_normal (arg0);
19371 op1 = expand_normal (arg1);
19373 tmode = insn_data[icode].operand[0].mode;
19374 mode1 = insn_data[icode].operand[1].mode;
19376 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19377 op0 = copy_to_reg (op0);
19379 op1 = simplify_gen_subreg (TImode, op1, GET_MODE (op1), 0);
19380 if (! (*insn_data[icode].operand[2].predicate) (op1, TImode))
19381 op1 = copy_to_reg (op1);
19383 target = gen_reg_rtx (tmode);
19384 pat = GEN_FCN (icode) (target, op0, op1);
19390 case IX86_BUILTIN_PSLLDQI128:
19391 case IX86_BUILTIN_PSRLDQI128:
19392 icode = (fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
19393 : CODE_FOR_sse2_lshrti3);
19394 arg0 = CALL_EXPR_ARG (exp, 0);
19395 arg1 = CALL_EXPR_ARG (exp, 1);
19396 op0 = expand_normal (arg0);
19397 op1 = expand_normal (arg1);
19398 tmode = insn_data[icode].operand[0].mode;
19399 mode1 = insn_data[icode].operand[1].mode;
19400 mode2 = insn_data[icode].operand[2].mode;
19402 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19404 op0 = copy_to_reg (op0);
19405 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
19407 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19409 error ("shift must be an immediate");
19412 target = gen_reg_rtx (V2DImode);
19413 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0),
19420 case IX86_BUILTIN_FEMMS:
19421 emit_insn (gen_mmx_femms ());
19424 case IX86_BUILTIN_PAVGUSB:
19425 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, exp, target);
19427 case IX86_BUILTIN_PF2ID:
19428 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, exp, target, 0);
19430 case IX86_BUILTIN_PFACC:
19431 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, exp, target);
19433 case IX86_BUILTIN_PFADD:
19434 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, exp, target);
19436 case IX86_BUILTIN_PFCMPEQ:
19437 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, exp, target);
19439 case IX86_BUILTIN_PFCMPGE:
19440 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, exp, target);
19442 case IX86_BUILTIN_PFCMPGT:
19443 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, exp, target);
19445 case IX86_BUILTIN_PFMAX:
19446 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, exp, target);
19448 case IX86_BUILTIN_PFMIN:
19449 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, exp, target);
19451 case IX86_BUILTIN_PFMUL:
19452 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, exp, target);
19454 case IX86_BUILTIN_PFRCP:
19455 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, exp, target, 0);
19457 case IX86_BUILTIN_PFRCPIT1:
19458 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, exp, target);
19460 case IX86_BUILTIN_PFRCPIT2:
19461 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, exp, target);
19463 case IX86_BUILTIN_PFRSQIT1:
19464 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, exp, target);
19466 case IX86_BUILTIN_PFRSQRT:
19467 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, exp, target, 0);
19469 case IX86_BUILTIN_PFSUB:
19470 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, exp, target);
19472 case IX86_BUILTIN_PFSUBR:
19473 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, exp, target);
19475 case IX86_BUILTIN_PI2FD:
19476 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, exp, target, 0);
19478 case IX86_BUILTIN_PMULHRW:
19479 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, exp, target);
19481 case IX86_BUILTIN_PF2IW:
19482 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, exp, target, 0);
19484 case IX86_BUILTIN_PFNACC:
19485 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, exp, target);
19487 case IX86_BUILTIN_PFPNACC:
19488 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, exp, target);
19490 case IX86_BUILTIN_PI2FW:
19491 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, exp, target, 0);
19493 case IX86_BUILTIN_PSWAPDSI:
19494 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, exp, target, 0);
19496 case IX86_BUILTIN_PSWAPDSF:
19497 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, exp, target, 0);
19499 case IX86_BUILTIN_SQRTSD:
19500 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, exp, target);
19501 case IX86_BUILTIN_LOADUPD:
19502 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, exp, target, 1);
19503 case IX86_BUILTIN_STOREUPD:
19504 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, exp);
19506 case IX86_BUILTIN_MFENCE:
19507 emit_insn (gen_sse2_mfence ());
19509 case IX86_BUILTIN_LFENCE:
19510 emit_insn (gen_sse2_lfence ());
19513 case IX86_BUILTIN_CLFLUSH:
19514 arg0 = CALL_EXPR_ARG (exp, 0);
19515 op0 = expand_normal (arg0);
19516 icode = CODE_FOR_sse2_clflush;
19517 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
19518 op0 = copy_to_mode_reg (Pmode, op0);
19520 emit_insn (gen_sse2_clflush (op0));
19523 case IX86_BUILTIN_MOVNTPD:
19524 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, exp);
19525 case IX86_BUILTIN_MOVNTDQ:
19526 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, exp);
19527 case IX86_BUILTIN_MOVNTI:
19528 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, exp);
19530 case IX86_BUILTIN_LOADDQU:
19531 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, exp, target, 1);
19532 case IX86_BUILTIN_STOREDQU:
19533 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, exp);
19535 case IX86_BUILTIN_MONITOR:
19536 arg0 = CALL_EXPR_ARG (exp, 0);
19537 arg1 = CALL_EXPR_ARG (exp, 1);
19538 arg2 = CALL_EXPR_ARG (exp, 2);
19539 op0 = expand_normal (arg0);
19540 op1 = expand_normal (arg1);
19541 op2 = expand_normal (arg2);
19543 op0 = copy_to_mode_reg (Pmode, op0);
19545 op1 = copy_to_mode_reg (SImode, op1);
19547 op2 = copy_to_mode_reg (SImode, op2);
19549 emit_insn (gen_sse3_monitor (op0, op1, op2));
19551 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
19554 case IX86_BUILTIN_MWAIT:
19555 arg0 = CALL_EXPR_ARG (exp, 0);
19556 arg1 = CALL_EXPR_ARG (exp, 1);
19557 op0 = expand_normal (arg0);
19558 op1 = expand_normal (arg1);
19560 op0 = copy_to_mode_reg (SImode, op0);
19562 op1 = copy_to_mode_reg (SImode, op1);
19563 emit_insn (gen_sse3_mwait (op0, op1));
19566 case IX86_BUILTIN_LDDQU:
19567 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, exp,
19570 case IX86_BUILTIN_PALIGNR:
19571 case IX86_BUILTIN_PALIGNR128:
19572 if (fcode == IX86_BUILTIN_PALIGNR)
19574 icode = CODE_FOR_ssse3_palignrdi;
19579 icode = CODE_FOR_ssse3_palignrti;
19582 arg0 = CALL_EXPR_ARG (exp, 0);
19583 arg1 = CALL_EXPR_ARG (exp, 1);
19584 arg2 = CALL_EXPR_ARG (exp, 2);
19585 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
19586 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
19587 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
19588 tmode = insn_data[icode].operand[0].mode;
19589 mode1 = insn_data[icode].operand[1].mode;
19590 mode2 = insn_data[icode].operand[2].mode;
19591 mode3 = insn_data[icode].operand[3].mode;
19593 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19595 op0 = copy_to_reg (op0);
19596 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
19598 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19600 op1 = copy_to_reg (op1);
19601 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
19603 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19605 error ("shift must be an immediate");
19608 target = gen_reg_rtx (mode);
19609 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
19616 case IX86_BUILTIN_MOVNTDQA:
19617 return ix86_expand_unop_builtin (CODE_FOR_sse4_1_movntdqa, exp,
19620 case IX86_BUILTIN_MOVNTSD:
19621 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv2df, exp);
19623 case IX86_BUILTIN_MOVNTSS:
19624 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv4sf, exp);
19626 case IX86_BUILTIN_INSERTQ:
19627 case IX86_BUILTIN_EXTRQ:
19628 icode = (fcode == IX86_BUILTIN_EXTRQ
19629 ? CODE_FOR_sse4a_extrq
19630 : CODE_FOR_sse4a_insertq);
19631 arg0 = CALL_EXPR_ARG (exp, 0);
19632 arg1 = CALL_EXPR_ARG (exp, 1);
19633 op0 = expand_normal (arg0);
19634 op1 = expand_normal (arg1);
19635 tmode = insn_data[icode].operand[0].mode;
19636 mode1 = insn_data[icode].operand[1].mode;
19637 mode2 = insn_data[icode].operand[2].mode;
19638 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19639 op0 = copy_to_mode_reg (mode1, op0);
19640 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19641 op1 = copy_to_mode_reg (mode2, op1);
19642 if (optimize || target == 0
19643 || GET_MODE (target) != tmode
19644 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19645 target = gen_reg_rtx (tmode);
19646 pat = GEN_FCN (icode) (target, op0, op1);
19652 case IX86_BUILTIN_EXTRQI:
19653 icode = CODE_FOR_sse4a_extrqi;
19654 arg0 = CALL_EXPR_ARG (exp, 0);
19655 arg1 = CALL_EXPR_ARG (exp, 1);
19656 arg2 = CALL_EXPR_ARG (exp, 2);
19657 op0 = expand_normal (arg0);
19658 op1 = expand_normal (arg1);
19659 op2 = expand_normal (arg2);
19660 tmode = insn_data[icode].operand[0].mode;
19661 mode1 = insn_data[icode].operand[1].mode;
19662 mode2 = insn_data[icode].operand[2].mode;
19663 mode3 = insn_data[icode].operand[3].mode;
19664 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19665 op0 = copy_to_mode_reg (mode1, op0);
19666 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19668 error ("index mask must be an immediate");
19669 return gen_reg_rtx (tmode);
19671 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19673 error ("length mask must be an immediate");
19674 return gen_reg_rtx (tmode);
19676 if (optimize || target == 0
19677 || GET_MODE (target) != tmode
19678 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19679 target = gen_reg_rtx (tmode);
19680 pat = GEN_FCN (icode) (target, op0, op1, op2);
19686 case IX86_BUILTIN_INSERTQI:
19687 icode = CODE_FOR_sse4a_insertqi;
19688 arg0 = CALL_EXPR_ARG (exp, 0);
19689 arg1 = CALL_EXPR_ARG (exp, 1);
19690 arg2 = CALL_EXPR_ARG (exp, 2);
19691 arg3 = CALL_EXPR_ARG (exp, 3);
19692 op0 = expand_normal (arg0);
19693 op1 = expand_normal (arg1);
19694 op2 = expand_normal (arg2);
19695 op3 = expand_normal (arg3);
19696 tmode = insn_data[icode].operand[0].mode;
19697 mode1 = insn_data[icode].operand[1].mode;
19698 mode2 = insn_data[icode].operand[2].mode;
19699 mode3 = insn_data[icode].operand[3].mode;
19700 mode4 = insn_data[icode].operand[4].mode;
19702 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19703 op0 = copy_to_mode_reg (mode1, op0);
19705 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19706 op1 = copy_to_mode_reg (mode2, op1);
19708 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19710 error ("index mask must be an immediate");
19711 return gen_reg_rtx (tmode);
19713 if (! (*insn_data[icode].operand[4].predicate) (op3, mode4))
19715 error ("length mask must be an immediate");
19716 return gen_reg_rtx (tmode);
19718 if (optimize || target == 0
19719 || GET_MODE (target) != tmode
19720 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19721 target = gen_reg_rtx (tmode);
19722 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
19728 case IX86_BUILTIN_VEC_INIT_V2SI:
19729 case IX86_BUILTIN_VEC_INIT_V4HI:
19730 case IX86_BUILTIN_VEC_INIT_V8QI:
19731 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
19733 case IX86_BUILTIN_VEC_EXT_V2DF:
19734 case IX86_BUILTIN_VEC_EXT_V2DI:
19735 case IX86_BUILTIN_VEC_EXT_V4SF:
19736 case IX86_BUILTIN_VEC_EXT_V4SI:
19737 case IX86_BUILTIN_VEC_EXT_V8HI:
19738 case IX86_BUILTIN_VEC_EXT_V2SI:
19739 case IX86_BUILTIN_VEC_EXT_V4HI:
19740 case IX86_BUILTIN_VEC_EXT_V16QI:
19741 return ix86_expand_vec_ext_builtin (exp, target);
19743 case IX86_BUILTIN_VEC_SET_V2DI:
19744 case IX86_BUILTIN_VEC_SET_V4SF:
19745 case IX86_BUILTIN_VEC_SET_V4SI:
19746 case IX86_BUILTIN_VEC_SET_V8HI:
19747 case IX86_BUILTIN_VEC_SET_V4HI:
19748 case IX86_BUILTIN_VEC_SET_V16QI:
19749 return ix86_expand_vec_set_builtin (exp);
19751 case IX86_BUILTIN_INFQ:
19753 REAL_VALUE_TYPE inf;
19757 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
19759 tmp = validize_mem (force_const_mem (mode, tmp));
19762 target = gen_reg_rtx (mode);
19764 emit_move_insn (target, tmp);
19768 case IX86_BUILTIN_FABSQ:
19769 return ix86_expand_unop_builtin (CODE_FOR_abstf2, exp, target, 0);
19771 case IX86_BUILTIN_COPYSIGNQ:
19772 return ix86_expand_binop_builtin (CODE_FOR_copysigntf3, exp, target);
19778 for (i = 0, d = bdesc_sse_3arg;
19779 i < ARRAY_SIZE (bdesc_sse_3arg);
19781 if (d->code == fcode)
19782 return ix86_expand_sse_4_operands_builtin (d->icode, exp,
19785 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
19786 if (d->code == fcode)
19788 /* Compares are treated specially. */
19789 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
19790 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
19791 || d->icode == CODE_FOR_sse2_maskcmpv2df3
19792 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
19793 return ix86_expand_sse_compare (d, exp, target);
19795 return ix86_expand_binop_builtin (d->icode, exp, target);
19798 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
19799 if (d->code == fcode)
19800 return ix86_expand_unop_builtin (d->icode, exp, target, 0);
19802 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19803 if (d->code == fcode)
19804 return ix86_expand_sse_comi (d, exp, target);
19806 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
19807 if (d->code == fcode)
19808 return ix86_expand_sse_ptest (d, exp, target);
19810 for (i = 0, d = bdesc_crc32; i < ARRAY_SIZE (bdesc_crc32); i++, d++)
19811 if (d->code == fcode)
19812 return ix86_expand_crc32 (d->icode, exp, target);
19814 for (i = 0, d = bdesc_pcmpestr;
19815 i < ARRAY_SIZE (bdesc_pcmpestr);
19817 if (d->code == fcode)
19818 return ix86_expand_sse_pcmpestr (d, exp, target);
19820 for (i = 0, d = bdesc_pcmpistr;
19821 i < ARRAY_SIZE (bdesc_pcmpistr);
19823 if (d->code == fcode)
19824 return ix86_expand_sse_pcmpistr (d, exp, target);
19826 gcc_unreachable ();
19829 /* Returns a function decl for a vectorized version of the builtin function
19830 with builtin function code FN and the result vector type TYPE, or NULL_TREE
19831 if it is not available. */
19834 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
19837 enum machine_mode in_mode, out_mode;
19840 if (TREE_CODE (type_out) != VECTOR_TYPE
19841 || TREE_CODE (type_in) != VECTOR_TYPE)
19844 out_mode = TYPE_MODE (TREE_TYPE (type_out));
19845 out_n = TYPE_VECTOR_SUBPARTS (type_out);
19846 in_mode = TYPE_MODE (TREE_TYPE (type_in));
19847 in_n = TYPE_VECTOR_SUBPARTS (type_in);
19851 case BUILT_IN_SQRT:
19852 if (out_mode == DFmode && out_n == 2
19853 && in_mode == DFmode && in_n == 2)
19854 return ix86_builtins[IX86_BUILTIN_SQRTPD];
19857 case BUILT_IN_SQRTF:
19858 if (out_mode == SFmode && out_n == 4
19859 && in_mode == SFmode && in_n == 4)
19860 return ix86_builtins[IX86_BUILTIN_SQRTPS];
19863 case BUILT_IN_LRINTF:
19864 if (out_mode == SImode && out_n == 4
19865 && in_mode == SFmode && in_n == 4)
19866 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
19876 /* Returns a decl of a function that implements conversion of the
19877 input vector of type TYPE, or NULL_TREE if it is not available. */
19880 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
19882 if (TREE_CODE (type) != VECTOR_TYPE)
19888 switch (TYPE_MODE (type))
19891 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
19896 case FIX_TRUNC_EXPR:
19897 switch (TYPE_MODE (type))
19900 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
19910 /* Returns a code for a target-specific builtin that implements
19911 reciprocal of the function, or NULL_TREE if not available. */
19914 ix86_builtin_reciprocal (unsigned int code, bool sqrt ATTRIBUTE_UNUSED)
19916 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
19917 && flag_finite_math_only && !flag_trapping_math
19918 && flag_unsafe_math_optimizations))
19923 /* Sqrt to rsqrt conversion. */
19924 case BUILT_IN_SQRTF:
19925 return ix86_builtins[IX86_BUILTIN_RSQRTF];
19927 /* Vectorized version of sqrt to rsqrt conversion. */
19928 case IX86_BUILTIN_SQRTPS:
19929 return ix86_builtins[IX86_BUILTIN_RSQRTPS];
19936 /* Store OPERAND to the memory after reload is completed. This means
19937 that we can't easily use assign_stack_local. */
19939 ix86_force_to_memory (enum machine_mode mode, rtx operand)
19943 gcc_assert (reload_completed);
19944 if (TARGET_RED_ZONE)
19946 result = gen_rtx_MEM (mode,
19947 gen_rtx_PLUS (Pmode,
19949 GEN_INT (-RED_ZONE_SIZE)));
19950 emit_move_insn (result, operand);
19952 else if (!TARGET_RED_ZONE && TARGET_64BIT)
19958 operand = gen_lowpart (DImode, operand);
19962 gen_rtx_SET (VOIDmode,
19963 gen_rtx_MEM (DImode,
19964 gen_rtx_PRE_DEC (DImode,
19965 stack_pointer_rtx)),
19969 gcc_unreachable ();
19971 result = gen_rtx_MEM (mode, stack_pointer_rtx);
19980 split_di (&operand, 1, operands, operands + 1);
19982 gen_rtx_SET (VOIDmode,
19983 gen_rtx_MEM (SImode,
19984 gen_rtx_PRE_DEC (Pmode,
19985 stack_pointer_rtx)),
19988 gen_rtx_SET (VOIDmode,
19989 gen_rtx_MEM (SImode,
19990 gen_rtx_PRE_DEC (Pmode,
19991 stack_pointer_rtx)),
19996 /* Store HImodes as SImodes. */
19997 operand = gen_lowpart (SImode, operand);
20001 gen_rtx_SET (VOIDmode,
20002 gen_rtx_MEM (GET_MODE (operand),
20003 gen_rtx_PRE_DEC (SImode,
20004 stack_pointer_rtx)),
20008 gcc_unreachable ();
20010 result = gen_rtx_MEM (mode, stack_pointer_rtx);
20015 /* Free operand from the memory. */
20017 ix86_free_from_memory (enum machine_mode mode)
20019 if (!TARGET_RED_ZONE)
20023 if (mode == DImode || TARGET_64BIT)
20027 /* Use LEA to deallocate stack space. In peephole2 it will be converted
20028 to pop or add instruction if registers are available. */
20029 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
20030 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
20035 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
20036 QImode must go into class Q_REGS.
20037 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
20038 movdf to do mem-to-mem moves through integer regs. */
20040 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
20042 enum machine_mode mode = GET_MODE (x);
20044 /* We're only allowed to return a subclass of CLASS. Many of the
20045 following checks fail for NO_REGS, so eliminate that early. */
20046 if (regclass == NO_REGS)
20049 /* All classes can load zeros. */
20050 if (x == CONST0_RTX (mode))
20053 /* Force constants into memory if we are loading a (nonzero) constant into
20054 an MMX or SSE register. This is because there are no MMX/SSE instructions
20055 to load from a constant. */
20057 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
20060 /* Prefer SSE regs only, if we can use them for math. */
20061 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
20062 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
20064 /* Floating-point constants need more complex checks. */
20065 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
20067 /* General regs can load everything. */
20068 if (reg_class_subset_p (regclass, GENERAL_REGS))
20071 /* Floats can load 0 and 1 plus some others. Note that we eliminated
20072 zero above. We only want to wind up preferring 80387 registers if
20073 we plan on doing computation with them. */
20075 && standard_80387_constant_p (x))
20077 /* Limit class to non-sse. */
20078 if (regclass == FLOAT_SSE_REGS)
20080 if (regclass == FP_TOP_SSE_REGS)
20082 if (regclass == FP_SECOND_SSE_REGS)
20083 return FP_SECOND_REG;
20084 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
20091 /* Generally when we see PLUS here, it's the function invariant
20092 (plus soft-fp const_int). Which can only be computed into general
20094 if (GET_CODE (x) == PLUS)
20095 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
20097 /* QImode constants are easy to load, but non-constant QImode data
20098 must go into Q_REGS. */
20099 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
20101 if (reg_class_subset_p (regclass, Q_REGS))
20103 if (reg_class_subset_p (Q_REGS, regclass))
20111 /* Discourage putting floating-point values in SSE registers unless
20112 SSE math is being used, and likewise for the 387 registers. */
20114 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
20116 enum machine_mode mode = GET_MODE (x);
20118 /* Restrict the output reload class to the register bank that we are doing
20119 math on. If we would like not to return a subset of CLASS, reject this
20120 alternative: if reload cannot do this, it will still use its choice. */
20121 mode = GET_MODE (x);
20122 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
20123 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
20125 if (X87_FLOAT_MODE_P (mode))
20127 if (regclass == FP_TOP_SSE_REGS)
20129 else if (regclass == FP_SECOND_SSE_REGS)
20130 return FP_SECOND_REG;
20132 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
20138 /* If we are copying between general and FP registers, we need a memory
20139 location. The same is true for SSE and MMX registers.
20141 The macro can't work reliably when one of the CLASSES is class containing
20142 registers from multiple units (SSE, MMX, integer). We avoid this by never
20143 combining those units in single alternative in the machine description.
20144 Ensure that this constraint holds to avoid unexpected surprises.
20146 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
20147 enforce these sanity checks. */
20150 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
20151 enum machine_mode mode, int strict)
20153 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
20154 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
20155 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
20156 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
20157 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
20158 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
20160 gcc_assert (!strict);
20164 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
20167 /* ??? This is a lie. We do have moves between mmx/general, and for
20168 mmx/sse2. But by saying we need secondary memory we discourage the
20169 register allocator from using the mmx registers unless needed. */
20170 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
20173 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
20175 /* SSE1 doesn't have any direct moves from other classes. */
20179 /* If the target says that inter-unit moves are more expensive
20180 than moving through memory, then don't generate them. */
20181 if (!TARGET_INTER_UNIT_MOVES)
20184 /* Between SSE and general, we have moves no larger than word size. */
20185 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
20192 /* Return true if the registers in CLASS cannot represent the change from
20193 modes FROM to TO. */
20196 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
20197 enum reg_class regclass)
20202 /* x87 registers can't do subreg at all, as all values are reformatted
20203 to extended precision. */
20204 if (MAYBE_FLOAT_CLASS_P (regclass))
20207 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
20209 /* Vector registers do not support QI or HImode loads. If we don't
20210 disallow a change to these modes, reload will assume it's ok to
20211 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
20212 the vec_dupv4hi pattern. */
20213 if (GET_MODE_SIZE (from) < 4)
20216 /* Vector registers do not support subreg with nonzero offsets, which
20217 are otherwise valid for integer registers. Since we can't see
20218 whether we have a nonzero offset from here, prohibit all
20219 nonparadoxical subregs changing size. */
20220 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
20227 /* Return the cost of moving data from a register in class CLASS1 to
20228 one in class CLASS2.
20230 It is not required that the cost always equal 2 when FROM is the same as TO;
20231 on some machines it is expensive to move between registers if they are not
20232 general registers. */
20235 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
20236 enum reg_class class2)
20238 /* In case we require secondary memory, compute cost of the store followed
20239 by load. In order to avoid bad register allocation choices, we need
20240 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
20242 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
20246 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
20247 MEMORY_MOVE_COST (mode, class1, 1));
20248 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
20249 MEMORY_MOVE_COST (mode, class2, 1));
20251 /* In case of copying from general_purpose_register we may emit multiple
20252 stores followed by single load causing memory size mismatch stall.
20253 Count this as arbitrarily high cost of 20. */
20254 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
20257 /* In the case of FP/MMX moves, the registers actually overlap, and we
20258 have to switch modes in order to treat them differently. */
20259 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
20260 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
20266 /* Moves between SSE/MMX and integer unit are expensive. */
20267 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
20268 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
20269 return ix86_cost->mmxsse_to_integer;
20270 if (MAYBE_FLOAT_CLASS_P (class1))
20271 return ix86_cost->fp_move;
20272 if (MAYBE_SSE_CLASS_P (class1))
20273 return ix86_cost->sse_move;
20274 if (MAYBE_MMX_CLASS_P (class1))
20275 return ix86_cost->mmx_move;
20279 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
20282 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
20284 /* Flags and only flags can only hold CCmode values. */
20285 if (CC_REGNO_P (regno))
20286 return GET_MODE_CLASS (mode) == MODE_CC;
20287 if (GET_MODE_CLASS (mode) == MODE_CC
20288 || GET_MODE_CLASS (mode) == MODE_RANDOM
20289 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
20291 if (FP_REGNO_P (regno))
20292 return VALID_FP_MODE_P (mode);
20293 if (SSE_REGNO_P (regno))
20295 /* We implement the move patterns for all vector modes into and
20296 out of SSE registers, even when no operation instructions
20298 return (VALID_SSE_REG_MODE (mode)
20299 || VALID_SSE2_REG_MODE (mode)
20300 || VALID_MMX_REG_MODE (mode)
20301 || VALID_MMX_REG_MODE_3DNOW (mode));
20303 if (MMX_REGNO_P (regno))
20305 /* We implement the move patterns for 3DNOW modes even in MMX mode,
20306 so if the register is available at all, then we can move data of
20307 the given mode into or out of it. */
20308 return (VALID_MMX_REG_MODE (mode)
20309 || VALID_MMX_REG_MODE_3DNOW (mode));
20312 if (mode == QImode)
20314 /* Take care for QImode values - they can be in non-QI regs,
20315 but then they do cause partial register stalls. */
20316 if (regno < 4 || TARGET_64BIT)
20318 if (!TARGET_PARTIAL_REG_STALL)
20320 return reload_in_progress || reload_completed;
20322 /* We handle both integer and floats in the general purpose registers. */
20323 else if (VALID_INT_MODE_P (mode))
20325 else if (VALID_FP_MODE_P (mode))
20327 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
20328 on to use that value in smaller contexts, this can easily force a
20329 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
20330 supporting DImode, allow it. */
20331 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
20337 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
20338 tieable integer mode. */
20341 ix86_tieable_integer_mode_p (enum machine_mode mode)
20350 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
20353 return TARGET_64BIT;
20360 /* Return true if MODE1 is accessible in a register that can hold MODE2
20361 without copying. That is, all register classes that can hold MODE2
20362 can also hold MODE1. */
20365 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
20367 if (mode1 == mode2)
20370 if (ix86_tieable_integer_mode_p (mode1)
20371 && ix86_tieable_integer_mode_p (mode2))
20374 /* MODE2 being XFmode implies fp stack or general regs, which means we
20375 can tie any smaller floating point modes to it. Note that we do not
20376 tie this with TFmode. */
20377 if (mode2 == XFmode)
20378 return mode1 == SFmode || mode1 == DFmode;
20380 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
20381 that we can tie it with SFmode. */
20382 if (mode2 == DFmode)
20383 return mode1 == SFmode;
20385 /* If MODE2 is only appropriate for an SSE register, then tie with
20386 any other mode acceptable to SSE registers. */
20387 if (GET_MODE_SIZE (mode2) == 16
20388 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
20389 return (GET_MODE_SIZE (mode1) == 16
20390 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
20392 /* If MODE2 is appropriate for an MMX register, then tie
20393 with any other mode acceptable to MMX registers. */
20394 if (GET_MODE_SIZE (mode2) == 8
20395 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
20396 return (GET_MODE_SIZE (mode1) == 8
20397 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
20402 /* Return the cost of moving data of mode M between a
20403 register and memory. A value of 2 is the default; this cost is
20404 relative to those in `REGISTER_MOVE_COST'.
20406 If moving between registers and memory is more expensive than
20407 between two registers, you should define this macro to express the
20410 Model also increased moving costs of QImode registers in non
20414 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
20416 if (FLOAT_CLASS_P (regclass))
20433 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
20435 if (SSE_CLASS_P (regclass))
20438 switch (GET_MODE_SIZE (mode))
20452 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
20454 if (MMX_CLASS_P (regclass))
20457 switch (GET_MODE_SIZE (mode))
20468 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
20470 switch (GET_MODE_SIZE (mode))
20474 return (Q_CLASS_P (regclass) ? ix86_cost->int_load[0]
20475 : ix86_cost->movzbl_load);
20477 return (Q_CLASS_P (regclass) ? ix86_cost->int_store[0]
20478 : ix86_cost->int_store[0] + 4);
20481 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
20483 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
20484 if (mode == TFmode)
20486 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
20487 * (((int) GET_MODE_SIZE (mode)
20488 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
20492 /* Compute a (partial) cost for rtx X. Return true if the complete
20493 cost has been computed, and false if subexpressions should be
20494 scanned. In either case, *TOTAL contains the cost result. */
20497 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
20499 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
20500 enum machine_mode mode = GET_MODE (x);
20508 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
20510 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
20512 else if (flag_pic && SYMBOLIC_CONST (x)
20514 || (!GET_CODE (x) != LABEL_REF
20515 && (GET_CODE (x) != SYMBOL_REF
20516 || !SYMBOL_REF_LOCAL_P (x)))))
20523 if (mode == VOIDmode)
20526 switch (standard_80387_constant_p (x))
20531 default: /* Other constants */
20536 /* Start with (MEM (SYMBOL_REF)), since that's where
20537 it'll probably end up. Add a penalty for size. */
20538 *total = (COSTS_N_INSNS (1)
20539 + (flag_pic != 0 && !TARGET_64BIT)
20540 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
20546 /* The zero extensions is often completely free on x86_64, so make
20547 it as cheap as possible. */
20548 if (TARGET_64BIT && mode == DImode
20549 && GET_MODE (XEXP (x, 0)) == SImode)
20551 else if (TARGET_ZERO_EXTEND_WITH_AND)
20552 *total = ix86_cost->add;
20554 *total = ix86_cost->movzx;
20558 *total = ix86_cost->movsx;
20562 if (CONST_INT_P (XEXP (x, 1))
20563 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
20565 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
20568 *total = ix86_cost->add;
20571 if ((value == 2 || value == 3)
20572 && ix86_cost->lea <= ix86_cost->shift_const)
20574 *total = ix86_cost->lea;
20584 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
20586 if (CONST_INT_P (XEXP (x, 1)))
20588 if (INTVAL (XEXP (x, 1)) > 32)
20589 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
20591 *total = ix86_cost->shift_const * 2;
20595 if (GET_CODE (XEXP (x, 1)) == AND)
20596 *total = ix86_cost->shift_var * 2;
20598 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
20603 if (CONST_INT_P (XEXP (x, 1)))
20604 *total = ix86_cost->shift_const;
20606 *total = ix86_cost->shift_var;
20611 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20613 /* ??? SSE scalar cost should be used here. */
20614 *total = ix86_cost->fmul;
20617 else if (X87_FLOAT_MODE_P (mode))
20619 *total = ix86_cost->fmul;
20622 else if (FLOAT_MODE_P (mode))
20624 /* ??? SSE vector cost should be used here. */
20625 *total = ix86_cost->fmul;
20630 rtx op0 = XEXP (x, 0);
20631 rtx op1 = XEXP (x, 1);
20633 if (CONST_INT_P (XEXP (x, 1)))
20635 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
20636 for (nbits = 0; value != 0; value &= value - 1)
20640 /* This is arbitrary. */
20643 /* Compute costs correctly for widening multiplication. */
20644 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
20645 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
20646 == GET_MODE_SIZE (mode))
20648 int is_mulwiden = 0;
20649 enum machine_mode inner_mode = GET_MODE (op0);
20651 if (GET_CODE (op0) == GET_CODE (op1))
20652 is_mulwiden = 1, op1 = XEXP (op1, 0);
20653 else if (CONST_INT_P (op1))
20655 if (GET_CODE (op0) == SIGN_EXTEND)
20656 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
20659 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
20663 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
20666 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
20667 + nbits * ix86_cost->mult_bit
20668 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
20677 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20678 /* ??? SSE cost should be used here. */
20679 *total = ix86_cost->fdiv;
20680 else if (X87_FLOAT_MODE_P (mode))
20681 *total = ix86_cost->fdiv;
20682 else if (FLOAT_MODE_P (mode))
20683 /* ??? SSE vector cost should be used here. */
20684 *total = ix86_cost->fdiv;
20686 *total = ix86_cost->divide[MODE_INDEX (mode)];
20690 if (GET_MODE_CLASS (mode) == MODE_INT
20691 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
20693 if (GET_CODE (XEXP (x, 0)) == PLUS
20694 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
20695 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
20696 && CONSTANT_P (XEXP (x, 1)))
20698 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
20699 if (val == 2 || val == 4 || val == 8)
20701 *total = ix86_cost->lea;
20702 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
20703 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
20705 *total += rtx_cost (XEXP (x, 1), outer_code);
20709 else if (GET_CODE (XEXP (x, 0)) == MULT
20710 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
20712 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
20713 if (val == 2 || val == 4 || val == 8)
20715 *total = ix86_cost->lea;
20716 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
20717 *total += rtx_cost (XEXP (x, 1), outer_code);
20721 else if (GET_CODE (XEXP (x, 0)) == PLUS)
20723 *total = ix86_cost->lea;
20724 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
20725 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
20726 *total += rtx_cost (XEXP (x, 1), outer_code);
20733 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20735 /* ??? SSE cost should be used here. */
20736 *total = ix86_cost->fadd;
20739 else if (X87_FLOAT_MODE_P (mode))
20741 *total = ix86_cost->fadd;
20744 else if (FLOAT_MODE_P (mode))
20746 /* ??? SSE vector cost should be used here. */
20747 *total = ix86_cost->fadd;
20755 if (!TARGET_64BIT && mode == DImode)
20757 *total = (ix86_cost->add * 2
20758 + (rtx_cost (XEXP (x, 0), outer_code)
20759 << (GET_MODE (XEXP (x, 0)) != DImode))
20760 + (rtx_cost (XEXP (x, 1), outer_code)
20761 << (GET_MODE (XEXP (x, 1)) != DImode)));
20767 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20769 /* ??? SSE cost should be used here. */
20770 *total = ix86_cost->fchs;
20773 else if (X87_FLOAT_MODE_P (mode))
20775 *total = ix86_cost->fchs;
20778 else if (FLOAT_MODE_P (mode))
20780 /* ??? SSE vector cost should be used here. */
20781 *total = ix86_cost->fchs;
20787 if (!TARGET_64BIT && mode == DImode)
20788 *total = ix86_cost->add * 2;
20790 *total = ix86_cost->add;
20794 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
20795 && XEXP (XEXP (x, 0), 1) == const1_rtx
20796 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
20797 && XEXP (x, 1) == const0_rtx)
20799 /* This kind of construct is implemented using test[bwl].
20800 Treat it as if we had an AND. */
20801 *total = (ix86_cost->add
20802 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
20803 + rtx_cost (const1_rtx, outer_code));
20809 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
20814 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20815 /* ??? SSE cost should be used here. */
20816 *total = ix86_cost->fabs;
20817 else if (X87_FLOAT_MODE_P (mode))
20818 *total = ix86_cost->fabs;
20819 else if (FLOAT_MODE_P (mode))
20820 /* ??? SSE vector cost should be used here. */
20821 *total = ix86_cost->fabs;
20825 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20826 /* ??? SSE cost should be used here. */
20827 *total = ix86_cost->fsqrt;
20828 else if (X87_FLOAT_MODE_P (mode))
20829 *total = ix86_cost->fsqrt;
20830 else if (FLOAT_MODE_P (mode))
20831 /* ??? SSE vector cost should be used here. */
20832 *total = ix86_cost->fsqrt;
20836 if (XINT (x, 1) == UNSPEC_TP)
20847 static int current_machopic_label_num;
20849 /* Given a symbol name and its associated stub, write out the
20850 definition of the stub. */
20853 machopic_output_stub (FILE *file, const char *symb, const char *stub)
20855 unsigned int length;
20856 char *binder_name, *symbol_name, lazy_ptr_name[32];
20857 int label = ++current_machopic_label_num;
20859 /* For 64-bit we shouldn't get here. */
20860 gcc_assert (!TARGET_64BIT);
20862 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20863 symb = (*targetm.strip_name_encoding) (symb);
20865 length = strlen (stub);
20866 binder_name = alloca (length + 32);
20867 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
20869 length = strlen (symb);
20870 symbol_name = alloca (length + 32);
20871 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
20873 sprintf (lazy_ptr_name, "L%d$lz", label);
20876 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
20878 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
20880 fprintf (file, "%s:\n", stub);
20881 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20885 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
20886 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
20887 fprintf (file, "\tjmp\t*%%edx\n");
20890 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
20892 fprintf (file, "%s:\n", binder_name);
20896 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
20897 fprintf (file, "\tpushl\t%%eax\n");
20900 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
20902 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
20904 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
20905 fprintf (file, "%s:\n", lazy_ptr_name);
20906 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20907 fprintf (file, "\t.long %s\n", binder_name);
20911 darwin_x86_file_end (void)
20913 darwin_file_end ();
20916 #endif /* TARGET_MACHO */
20918 /* Order the registers for register allocator. */
20921 x86_order_regs_for_local_alloc (void)
20926 /* First allocate the local general purpose registers. */
20927 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
20928 if (GENERAL_REGNO_P (i) && call_used_regs[i])
20929 reg_alloc_order [pos++] = i;
20931 /* Global general purpose registers. */
20932 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
20933 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
20934 reg_alloc_order [pos++] = i;
20936 /* x87 registers come first in case we are doing FP math
20938 if (!TARGET_SSE_MATH)
20939 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
20940 reg_alloc_order [pos++] = i;
20942 /* SSE registers. */
20943 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
20944 reg_alloc_order [pos++] = i;
20945 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
20946 reg_alloc_order [pos++] = i;
20948 /* x87 registers. */
20949 if (TARGET_SSE_MATH)
20950 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
20951 reg_alloc_order [pos++] = i;
20953 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
20954 reg_alloc_order [pos++] = i;
20956 /* Initialize the rest of array as we do not allocate some registers
20958 while (pos < FIRST_PSEUDO_REGISTER)
20959 reg_alloc_order [pos++] = 0;
20962 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20963 struct attribute_spec.handler. */
20965 ix86_handle_struct_attribute (tree *node, tree name,
20966 tree args ATTRIBUTE_UNUSED,
20967 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
20970 if (DECL_P (*node))
20972 if (TREE_CODE (*node) == TYPE_DECL)
20973 type = &TREE_TYPE (*node);
20978 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
20979 || TREE_CODE (*type) == UNION_TYPE)))
20981 warning (OPT_Wattributes, "%qs attribute ignored",
20982 IDENTIFIER_POINTER (name));
20983 *no_add_attrs = true;
20986 else if ((is_attribute_p ("ms_struct", name)
20987 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
20988 || ((is_attribute_p ("gcc_struct", name)
20989 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
20991 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
20992 IDENTIFIER_POINTER (name));
20993 *no_add_attrs = true;
21000 ix86_ms_bitfield_layout_p (tree record_type)
21002 return (TARGET_MS_BITFIELD_LAYOUT &&
21003 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
21004 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
21007 /* Returns an expression indicating where the this parameter is
21008 located on entry to the FUNCTION. */
21011 x86_this_parameter (tree function)
21013 tree type = TREE_TYPE (function);
21014 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
21018 const int *parm_regs;
21020 if (TARGET_64BIT_MS_ABI)
21021 parm_regs = x86_64_ms_abi_int_parameter_registers;
21023 parm_regs = x86_64_int_parameter_registers;
21024 return gen_rtx_REG (DImode, parm_regs[aggr]);
21027 if (ix86_function_regparm (type, function) > 0
21028 && !type_has_variadic_args_p (type))
21031 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
21033 return gen_rtx_REG (SImode, regno);
21036 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
21039 /* Determine whether x86_output_mi_thunk can succeed. */
21042 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
21043 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
21044 HOST_WIDE_INT vcall_offset, tree function)
21046 /* 64-bit can handle anything. */
21050 /* For 32-bit, everything's fine if we have one free register. */
21051 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
21054 /* Need a free register for vcall_offset. */
21058 /* Need a free register for GOT references. */
21059 if (flag_pic && !(*targetm.binds_local_p) (function))
21062 /* Otherwise ok. */
21066 /* Output the assembler code for a thunk function. THUNK_DECL is the
21067 declaration for the thunk function itself, FUNCTION is the decl for
21068 the target function. DELTA is an immediate constant offset to be
21069 added to THIS. If VCALL_OFFSET is nonzero, the word at
21070 *(*this + vcall_offset) should be added to THIS. */
21073 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
21074 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
21075 HOST_WIDE_INT vcall_offset, tree function)
21078 rtx this_param = x86_this_parameter (function);
21081 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
21082 pull it in now and let DELTA benefit. */
21083 if (REG_P (this_param))
21084 this_reg = this_param;
21085 else if (vcall_offset)
21087 /* Put the this parameter into %eax. */
21088 xops[0] = this_param;
21089 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
21090 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
21093 this_reg = NULL_RTX;
21095 /* Adjust the this parameter by a fixed constant. */
21098 xops[0] = GEN_INT (delta);
21099 xops[1] = this_reg ? this_reg : this_param;
21102 if (!x86_64_general_operand (xops[0], DImode))
21104 tmp = gen_rtx_REG (DImode, R10_REG);
21106 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
21108 xops[1] = this_param;
21110 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
21113 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
21116 /* Adjust the this parameter by a value stored in the vtable. */
21120 tmp = gen_rtx_REG (DImode, R10_REG);
21123 int tmp_regno = 2 /* ECX */;
21124 if (lookup_attribute ("fastcall",
21125 TYPE_ATTRIBUTES (TREE_TYPE (function))))
21126 tmp_regno = 0 /* EAX */;
21127 tmp = gen_rtx_REG (SImode, tmp_regno);
21130 xops[0] = gen_rtx_MEM (Pmode, this_reg);
21133 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
21135 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
21137 /* Adjust the this parameter. */
21138 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
21139 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
21141 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
21142 xops[0] = GEN_INT (vcall_offset);
21144 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
21145 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
21147 xops[1] = this_reg;
21149 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
21151 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
21154 /* If necessary, drop THIS back to its stack slot. */
21155 if (this_reg && this_reg != this_param)
21157 xops[0] = this_reg;
21158 xops[1] = this_param;
21159 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
21162 xops[0] = XEXP (DECL_RTL (function), 0);
21165 if (!flag_pic || (*targetm.binds_local_p) (function))
21166 output_asm_insn ("jmp\t%P0", xops);
21167 /* All thunks should be in the same object as their target,
21168 and thus binds_local_p should be true. */
21169 else if (TARGET_64BIT_MS_ABI)
21170 gcc_unreachable ();
21173 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
21174 tmp = gen_rtx_CONST (Pmode, tmp);
21175 tmp = gen_rtx_MEM (QImode, tmp);
21177 output_asm_insn ("jmp\t%A0", xops);
21182 if (!flag_pic || (*targetm.binds_local_p) (function))
21183 output_asm_insn ("jmp\t%P0", xops);
21188 rtx sym_ref = XEXP (DECL_RTL (function), 0);
21189 tmp = (gen_rtx_SYMBOL_REF
21191 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
21192 tmp = gen_rtx_MEM (QImode, tmp);
21194 output_asm_insn ("jmp\t%0", xops);
21197 #endif /* TARGET_MACHO */
21199 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
21200 output_set_got (tmp, NULL_RTX);
21203 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
21204 output_asm_insn ("jmp\t{*}%1", xops);
21210 x86_file_start (void)
21212 default_file_start ();
21214 darwin_file_start ();
21216 if (X86_FILE_START_VERSION_DIRECTIVE)
21217 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
21218 if (X86_FILE_START_FLTUSED)
21219 fputs ("\t.global\t__fltused\n", asm_out_file);
21220 if (ix86_asm_dialect == ASM_INTEL)
21221 fputs ("\t.intel_syntax\n", asm_out_file);
21225 x86_field_alignment (tree field, int computed)
21227 enum machine_mode mode;
21228 tree type = TREE_TYPE (field);
21230 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
21232 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
21233 ? get_inner_array_type (type) : type);
21234 if (mode == DFmode || mode == DCmode
21235 || GET_MODE_CLASS (mode) == MODE_INT
21236 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
21237 return MIN (32, computed);
21241 /* Output assembler code to FILE to increment profiler label # LABELNO
21242 for profiling a function entry. */
21244 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
21248 #ifndef NO_PROFILE_COUNTERS
21249 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
21252 if (!TARGET_64BIT_MS_ABI && flag_pic)
21253 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
21255 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
21259 #ifndef NO_PROFILE_COUNTERS
21260 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
21261 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
21263 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
21267 #ifndef NO_PROFILE_COUNTERS
21268 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
21269 PROFILE_COUNT_REGISTER);
21271 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
21275 /* We don't have exact information about the insn sizes, but we may assume
21276 quite safely that we are informed about all 1 byte insns and memory
21277 address sizes. This is enough to eliminate unnecessary padding in
21281 min_insn_size (rtx insn)
21285 if (!INSN_P (insn) || !active_insn_p (insn))
21288 /* Discard alignments we've emit and jump instructions. */
21289 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
21290 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
21293 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
21294 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
21297 /* Important case - calls are always 5 bytes.
21298 It is common to have many calls in the row. */
21300 && symbolic_reference_mentioned_p (PATTERN (insn))
21301 && !SIBLING_CALL_P (insn))
21303 if (get_attr_length (insn) <= 1)
21306 /* For normal instructions we may rely on the sizes of addresses
21307 and the presence of symbol to require 4 bytes of encoding.
21308 This is not the case for jumps where references are PC relative. */
21309 if (!JUMP_P (insn))
21311 l = get_attr_length_address (insn);
21312 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
21321 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
21325 ix86_avoid_jump_misspredicts (void)
21327 rtx insn, start = get_insns ();
21328 int nbytes = 0, njumps = 0;
21331 /* Look for all minimal intervals of instructions containing 4 jumps.
21332 The intervals are bounded by START and INSN. NBYTES is the total
21333 size of instructions in the interval including INSN and not including
21334 START. When the NBYTES is smaller than 16 bytes, it is possible
21335 that the end of START and INSN ends up in the same 16byte page.
21337 The smallest offset in the page INSN can start is the case where START
21338 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
21339 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
21341 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
21344 nbytes += min_insn_size (insn);
21346 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
21347 INSN_UID (insn), min_insn_size (insn));
21349 && GET_CODE (PATTERN (insn)) != ADDR_VEC
21350 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
21358 start = NEXT_INSN (start);
21359 if ((JUMP_P (start)
21360 && GET_CODE (PATTERN (start)) != ADDR_VEC
21361 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
21363 njumps--, isjump = 1;
21366 nbytes -= min_insn_size (start);
21368 gcc_assert (njumps >= 0);
21370 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
21371 INSN_UID (start), INSN_UID (insn), nbytes);
21373 if (njumps == 3 && isjump && nbytes < 16)
21375 int padsize = 15 - nbytes + min_insn_size (insn);
21378 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
21379 INSN_UID (insn), padsize);
21380 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
21385 /* AMD Athlon works faster
21386 when RET is not destination of conditional jump or directly preceded
21387 by other jump instruction. We avoid the penalty by inserting NOP just
21388 before the RET instructions in such cases. */
21390 ix86_pad_returns (void)
21395 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
21397 basic_block bb = e->src;
21398 rtx ret = BB_END (bb);
21400 bool replace = false;
21402 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
21403 || !maybe_hot_bb_p (bb))
21405 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
21406 if (active_insn_p (prev) || LABEL_P (prev))
21408 if (prev && LABEL_P (prev))
21413 FOR_EACH_EDGE (e, ei, bb->preds)
21414 if (EDGE_FREQUENCY (e) && e->src->index >= 0
21415 && !(e->flags & EDGE_FALLTHRU))
21420 prev = prev_active_insn (ret);
21422 && ((JUMP_P (prev) && any_condjump_p (prev))
21425 /* Empty functions get branch mispredict even when the jump destination
21426 is not visible to us. */
21427 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
21432 emit_insn_before (gen_return_internal_long (), ret);
21438 /* Implement machine specific optimizations. We implement padding of returns
21439 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
21443 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
21444 ix86_pad_returns ();
21445 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
21446 ix86_avoid_jump_misspredicts ();
21449 /* Return nonzero when QImode register that must be represented via REX prefix
21452 x86_extended_QIreg_mentioned_p (rtx insn)
21455 extract_insn_cached (insn);
21456 for (i = 0; i < recog_data.n_operands; i++)
21457 if (REG_P (recog_data.operand[i])
21458 && REGNO (recog_data.operand[i]) >= 4)
21463 /* Return nonzero when P points to register encoded via REX prefix.
21464 Called via for_each_rtx. */
21466 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
21468 unsigned int regno;
21471 regno = REGNO (*p);
21472 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
21475 /* Return true when INSN mentions register that must be encoded using REX
21478 x86_extended_reg_mentioned_p (rtx insn)
21480 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
21483 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
21484 optabs would emit if we didn't have TFmode patterns. */
21487 x86_emit_floatuns (rtx operands[2])
21489 rtx neglab, donelab, i0, i1, f0, in, out;
21490 enum machine_mode mode, inmode;
21492 inmode = GET_MODE (operands[1]);
21493 gcc_assert (inmode == SImode || inmode == DImode);
21496 in = force_reg (inmode, operands[1]);
21497 mode = GET_MODE (out);
21498 neglab = gen_label_rtx ();
21499 donelab = gen_label_rtx ();
21500 f0 = gen_reg_rtx (mode);
21502 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
21504 expand_float (out, in, 0);
21506 emit_jump_insn (gen_jump (donelab));
21509 emit_label (neglab);
21511 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
21513 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
21515 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
21517 expand_float (f0, i0, 0);
21519 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
21521 emit_label (donelab);
21524 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
21525 with all elements equal to VAR. Return true if successful. */
21528 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
21529 rtx target, rtx val)
21531 enum machine_mode smode, wsmode, wvmode;
21546 val = force_reg (GET_MODE_INNER (mode), val);
21547 x = gen_rtx_VEC_DUPLICATE (mode, val);
21548 emit_insn (gen_rtx_SET (VOIDmode, target, x));
21554 if (TARGET_SSE || TARGET_3DNOW_A)
21556 val = gen_lowpart (SImode, val);
21557 x = gen_rtx_TRUNCATE (HImode, val);
21558 x = gen_rtx_VEC_DUPLICATE (mode, x);
21559 emit_insn (gen_rtx_SET (VOIDmode, target, x));
21581 /* Extend HImode to SImode using a paradoxical SUBREG. */
21582 tmp1 = gen_reg_rtx (SImode);
21583 emit_move_insn (tmp1, gen_lowpart (SImode, val));
21584 /* Insert the SImode value as low element of V4SImode vector. */
21585 tmp2 = gen_reg_rtx (V4SImode);
21586 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
21587 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
21588 CONST0_RTX (V4SImode),
21590 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
21591 /* Cast the V4SImode vector back to a V8HImode vector. */
21592 tmp1 = gen_reg_rtx (V8HImode);
21593 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
21594 /* Duplicate the low short through the whole low SImode word. */
21595 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
21596 /* Cast the V8HImode vector back to a V4SImode vector. */
21597 tmp2 = gen_reg_rtx (V4SImode);
21598 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
21599 /* Replicate the low element of the V4SImode vector. */
21600 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
21601 /* Cast the V2SImode back to V8HImode, and store in target. */
21602 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
21613 /* Extend QImode to SImode using a paradoxical SUBREG. */
21614 tmp1 = gen_reg_rtx (SImode);
21615 emit_move_insn (tmp1, gen_lowpart (SImode, val));
21616 /* Insert the SImode value as low element of V4SImode vector. */
21617 tmp2 = gen_reg_rtx (V4SImode);
21618 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
21619 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
21620 CONST0_RTX (V4SImode),
21622 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
21623 /* Cast the V4SImode vector back to a V16QImode vector. */
21624 tmp1 = gen_reg_rtx (V16QImode);
21625 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
21626 /* Duplicate the low byte through the whole low SImode word. */
21627 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
21628 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
21629 /* Cast the V16QImode vector back to a V4SImode vector. */
21630 tmp2 = gen_reg_rtx (V4SImode);
21631 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
21632 /* Replicate the low element of the V4SImode vector. */
21633 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
21634 /* Cast the V2SImode back to V16QImode, and store in target. */
21635 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
21643 /* Replicate the value once into the next wider mode and recurse. */
21644 val = convert_modes (wsmode, smode, val, true);
21645 x = expand_simple_binop (wsmode, ASHIFT, val,
21646 GEN_INT (GET_MODE_BITSIZE (smode)),
21647 NULL_RTX, 1, OPTAB_LIB_WIDEN);
21648 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
21650 x = gen_reg_rtx (wvmode);
21651 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
21652 gcc_unreachable ();
21653 emit_move_insn (target, gen_lowpart (mode, x));
21661 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
21662 whose ONE_VAR element is VAR, and other elements are zero. Return true
21666 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
21667 rtx target, rtx var, int one_var)
21669 enum machine_mode vsimode;
21685 var = force_reg (GET_MODE_INNER (mode), var);
21686 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
21687 emit_insn (gen_rtx_SET (VOIDmode, target, x));
21692 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
21693 new_target = gen_reg_rtx (mode);
21695 new_target = target;
21696 var = force_reg (GET_MODE_INNER (mode), var);
21697 x = gen_rtx_VEC_DUPLICATE (mode, var);
21698 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
21699 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
21702 /* We need to shuffle the value to the correct position, so
21703 create a new pseudo to store the intermediate result. */
21705 /* With SSE2, we can use the integer shuffle insns. */
21706 if (mode != V4SFmode && TARGET_SSE2)
21708 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
21710 GEN_INT (one_var == 1 ? 0 : 1),
21711 GEN_INT (one_var == 2 ? 0 : 1),
21712 GEN_INT (one_var == 3 ? 0 : 1)));
21713 if (target != new_target)
21714 emit_move_insn (target, new_target);
21718 /* Otherwise convert the intermediate result to V4SFmode and
21719 use the SSE1 shuffle instructions. */
21720 if (mode != V4SFmode)
21722 tmp = gen_reg_rtx (V4SFmode);
21723 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
21728 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
21730 GEN_INT (one_var == 1 ? 0 : 1),
21731 GEN_INT (one_var == 2 ? 0+4 : 1+4),
21732 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
21734 if (mode != V4SFmode)
21735 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
21736 else if (tmp != target)
21737 emit_move_insn (target, tmp);
21739 else if (target != new_target)
21740 emit_move_insn (target, new_target);
21745 vsimode = V4SImode;
21751 vsimode = V2SImode;
21757 /* Zero extend the variable element to SImode and recurse. */
21758 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
21760 x = gen_reg_rtx (vsimode);
21761 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
21763 gcc_unreachable ();
21765 emit_move_insn (target, gen_lowpart (mode, x));
21773 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
21774 consisting of the values in VALS. It is known that all elements
21775 except ONE_VAR are constants. Return true if successful. */
21778 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
21779 rtx target, rtx vals, int one_var)
21781 rtx var = XVECEXP (vals, 0, one_var);
21782 enum machine_mode wmode;
21785 const_vec = copy_rtx (vals);
21786 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
21787 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
21795 /* For the two element vectors, it's just as easy to use
21796 the general case. */
21812 /* There's no way to set one QImode entry easily. Combine
21813 the variable value with its adjacent constant value, and
21814 promote to an HImode set. */
21815 x = XVECEXP (vals, 0, one_var ^ 1);
21818 var = convert_modes (HImode, QImode, var, true);
21819 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
21820 NULL_RTX, 1, OPTAB_LIB_WIDEN);
21821 x = GEN_INT (INTVAL (x) & 0xff);
21825 var = convert_modes (HImode, QImode, var, true);
21826 x = gen_int_mode (INTVAL (x) << 8, HImode);
21828 if (x != const0_rtx)
21829 var = expand_simple_binop (HImode, IOR, var, x, var,
21830 1, OPTAB_LIB_WIDEN);
21832 x = gen_reg_rtx (wmode);
21833 emit_move_insn (x, gen_lowpart (wmode, const_vec));
21834 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
21836 emit_move_insn (target, gen_lowpart (mode, x));
21843 emit_move_insn (target, const_vec);
21844 ix86_expand_vector_set (mmx_ok, target, var, one_var);
21848 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
21849 all values variable, and none identical. */
21852 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
21853 rtx target, rtx vals)
21855 enum machine_mode half_mode = GET_MODE_INNER (mode);
21856 rtx op0 = NULL, op1 = NULL;
21857 bool use_vec_concat = false;
21863 if (!mmx_ok && !TARGET_SSE)
21869 /* For the two element vectors, we always implement VEC_CONCAT. */
21870 op0 = XVECEXP (vals, 0, 0);
21871 op1 = XVECEXP (vals, 0, 1);
21872 use_vec_concat = true;
21876 half_mode = V2SFmode;
21879 half_mode = V2SImode;
21885 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
21886 Recurse to load the two halves. */
21888 op0 = gen_reg_rtx (half_mode);
21889 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
21890 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
21892 op1 = gen_reg_rtx (half_mode);
21893 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
21894 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
21896 use_vec_concat = true;
21907 gcc_unreachable ();
21910 if (use_vec_concat)
21912 if (!register_operand (op0, half_mode))
21913 op0 = force_reg (half_mode, op0);
21914 if (!register_operand (op1, half_mode))
21915 op1 = force_reg (half_mode, op1);
21917 emit_insn (gen_rtx_SET (VOIDmode, target,
21918 gen_rtx_VEC_CONCAT (mode, op0, op1)));
21922 int i, j, n_elts, n_words, n_elt_per_word;
21923 enum machine_mode inner_mode;
21924 rtx words[4], shift;
21926 inner_mode = GET_MODE_INNER (mode);
21927 n_elts = GET_MODE_NUNITS (mode);
21928 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
21929 n_elt_per_word = n_elts / n_words;
21930 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
21932 for (i = 0; i < n_words; ++i)
21934 rtx word = NULL_RTX;
21936 for (j = 0; j < n_elt_per_word; ++j)
21938 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
21939 elt = convert_modes (word_mode, inner_mode, elt, true);
21945 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
21946 word, 1, OPTAB_LIB_WIDEN);
21947 word = expand_simple_binop (word_mode, IOR, word, elt,
21948 word, 1, OPTAB_LIB_WIDEN);
21956 emit_move_insn (target, gen_lowpart (mode, words[0]));
21957 else if (n_words == 2)
21959 rtx tmp = gen_reg_rtx (mode);
21960 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
21961 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
21962 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
21963 emit_move_insn (target, tmp);
21965 else if (n_words == 4)
21967 rtx tmp = gen_reg_rtx (V4SImode);
21968 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
21969 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
21970 emit_move_insn (target, gen_lowpart (mode, tmp));
21973 gcc_unreachable ();
21977 /* Initialize vector TARGET via VALS. Suppress the use of MMX
21978 instructions unless MMX_OK is true. */
21981 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
21983 enum machine_mode mode = GET_MODE (target);
21984 enum machine_mode inner_mode = GET_MODE_INNER (mode);
21985 int n_elts = GET_MODE_NUNITS (mode);
21986 int n_var = 0, one_var = -1;
21987 bool all_same = true, all_const_zero = true;
21991 for (i = 0; i < n_elts; ++i)
21993 x = XVECEXP (vals, 0, i);
21994 if (!CONSTANT_P (x))
21995 n_var++, one_var = i;
21996 else if (x != CONST0_RTX (inner_mode))
21997 all_const_zero = false;
21998 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
22002 /* Constants are best loaded from the constant pool. */
22005 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
22009 /* If all values are identical, broadcast the value. */
22011 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
22012 XVECEXP (vals, 0, 0)))
22015 /* Values where only one field is non-constant are best loaded from
22016 the pool and overwritten via move later. */
22020 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
22021 XVECEXP (vals, 0, one_var),
22025 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
22029 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
22033 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
22035 enum machine_mode mode = GET_MODE (target);
22036 enum machine_mode inner_mode = GET_MODE_INNER (mode);
22037 bool use_vec_merge = false;
22046 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
22047 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
22049 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
22051 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
22052 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
22058 use_vec_merge = TARGET_SSE4_1;
22066 /* For the two element vectors, we implement a VEC_CONCAT with
22067 the extraction of the other element. */
22069 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
22070 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
22073 op0 = val, op1 = tmp;
22075 op0 = tmp, op1 = val;
22077 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
22078 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
22083 use_vec_merge = TARGET_SSE4_1;
22090 use_vec_merge = true;
22094 /* tmp = target = A B C D */
22095 tmp = copy_to_reg (target);
22096 /* target = A A B B */
22097 emit_insn (gen_sse_unpcklps (target, target, target));
22098 /* target = X A B B */
22099 ix86_expand_vector_set (false, target, val, 0);
22100 /* target = A X C D */
22101 emit_insn (gen_sse_shufps_1 (target, target, tmp,
22102 GEN_INT (1), GEN_INT (0),
22103 GEN_INT (2+4), GEN_INT (3+4)));
22107 /* tmp = target = A B C D */
22108 tmp = copy_to_reg (target);
22109 /* tmp = X B C D */
22110 ix86_expand_vector_set (false, tmp, val, 0);
22111 /* target = A B X D */
22112 emit_insn (gen_sse_shufps_1 (target, target, tmp,
22113 GEN_INT (0), GEN_INT (1),
22114 GEN_INT (0+4), GEN_INT (3+4)));
22118 /* tmp = target = A B C D */
22119 tmp = copy_to_reg (target);
22120 /* tmp = X B C D */
22121 ix86_expand_vector_set (false, tmp, val, 0);
22122 /* target = A B X D */
22123 emit_insn (gen_sse_shufps_1 (target, target, tmp,
22124 GEN_INT (0), GEN_INT (1),
22125 GEN_INT (2+4), GEN_INT (0+4)));
22129 gcc_unreachable ();
22134 use_vec_merge = TARGET_SSE4_1;
22138 /* Element 0 handled by vec_merge below. */
22141 use_vec_merge = true;
22147 /* With SSE2, use integer shuffles to swap element 0 and ELT,
22148 store into element 0, then shuffle them back. */
22152 order[0] = GEN_INT (elt);
22153 order[1] = const1_rtx;
22154 order[2] = const2_rtx;
22155 order[3] = GEN_INT (3);
22156 order[elt] = const0_rtx;
22158 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
22159 order[1], order[2], order[3]));
22161 ix86_expand_vector_set (false, target, val, 0);
22163 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
22164 order[1], order[2], order[3]));
22168 /* For SSE1, we have to reuse the V4SF code. */
22169 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
22170 gen_lowpart (SFmode, val), elt);
22175 use_vec_merge = TARGET_SSE2;
22178 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
22182 use_vec_merge = TARGET_SSE4_1;
22192 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
22193 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
22194 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
22198 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
22200 emit_move_insn (mem, target);
22202 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
22203 emit_move_insn (tmp, val);
22205 emit_move_insn (target, mem);
22210 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
22212 enum machine_mode mode = GET_MODE (vec);
22213 enum machine_mode inner_mode = GET_MODE_INNER (mode);
22214 bool use_vec_extr = false;
22227 use_vec_extr = true;
22231 use_vec_extr = TARGET_SSE4_1;
22243 tmp = gen_reg_rtx (mode);
22244 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
22245 GEN_INT (elt), GEN_INT (elt),
22246 GEN_INT (elt+4), GEN_INT (elt+4)));
22250 tmp = gen_reg_rtx (mode);
22251 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
22255 gcc_unreachable ();
22258 use_vec_extr = true;
22263 use_vec_extr = TARGET_SSE4_1;
22277 tmp = gen_reg_rtx (mode);
22278 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
22279 GEN_INT (elt), GEN_INT (elt),
22280 GEN_INT (elt), GEN_INT (elt)));
22284 tmp = gen_reg_rtx (mode);
22285 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
22289 gcc_unreachable ();
22292 use_vec_extr = true;
22297 /* For SSE1, we have to reuse the V4SF code. */
22298 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
22299 gen_lowpart (V4SFmode, vec), elt);
22305 use_vec_extr = TARGET_SSE2;
22308 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
22312 use_vec_extr = TARGET_SSE4_1;
22316 /* ??? Could extract the appropriate HImode element and shift. */
22323 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
22324 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
22326 /* Let the rtl optimizers know about the zero extension performed. */
22327 if (inner_mode == QImode || inner_mode == HImode)
22329 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
22330 target = gen_lowpart (SImode, target);
22333 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
22337 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
22339 emit_move_insn (mem, vec);
22341 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
22342 emit_move_insn (target, tmp);
22346 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
22347 pattern to reduce; DEST is the destination; IN is the input vector. */
22350 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
22352 rtx tmp1, tmp2, tmp3;
22354 tmp1 = gen_reg_rtx (V4SFmode);
22355 tmp2 = gen_reg_rtx (V4SFmode);
22356 tmp3 = gen_reg_rtx (V4SFmode);
22358 emit_insn (gen_sse_movhlps (tmp1, in, in));
22359 emit_insn (fn (tmp2, tmp1, in));
22361 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
22362 GEN_INT (1), GEN_INT (1),
22363 GEN_INT (1+4), GEN_INT (1+4)));
22364 emit_insn (fn (dest, tmp2, tmp3));
22367 /* Target hook for scalar_mode_supported_p. */
22369 ix86_scalar_mode_supported_p (enum machine_mode mode)
22371 if (DECIMAL_FLOAT_MODE_P (mode))
22373 else if (mode == TFmode)
22374 return TARGET_64BIT;
22376 return default_scalar_mode_supported_p (mode);
22379 /* Implements target hook vector_mode_supported_p. */
22381 ix86_vector_mode_supported_p (enum machine_mode mode)
22383 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
22385 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
22387 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
22389 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
22394 /* Worker function for TARGET_MD_ASM_CLOBBERS.
22396 We do this in the new i386 backend to maintain source compatibility
22397 with the old cc0-based compiler. */
22400 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
22401 tree inputs ATTRIBUTE_UNUSED,
22404 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
22406 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
22411 /* Implements target vector targetm.asm.encode_section_info. This
22412 is not used by netware. */
22414 static void ATTRIBUTE_UNUSED
22415 ix86_encode_section_info (tree decl, rtx rtl, int first)
22417 default_encode_section_info (decl, rtl, first);
22419 if (TREE_CODE (decl) == VAR_DECL
22420 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
22421 && ix86_in_large_data_p (decl))
22422 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
22425 /* Worker function for REVERSE_CONDITION. */
22428 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
22430 return (mode != CCFPmode && mode != CCFPUmode
22431 ? reverse_condition (code)
22432 : reverse_condition_maybe_unordered (code));
22435 /* Output code to perform an x87 FP register move, from OPERANDS[1]
22439 output_387_reg_move (rtx insn, rtx *operands)
22441 if (REG_P (operands[0]))
22443 if (REG_P (operands[1])
22444 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
22446 if (REGNO (operands[0]) == FIRST_STACK_REG)
22447 return output_387_ffreep (operands, 0);
22448 return "fstp\t%y0";
22450 if (STACK_TOP_P (operands[0]))
22451 return "fld%z1\t%y1";
22454 else if (MEM_P (operands[0]))
22456 gcc_assert (REG_P (operands[1]));
22457 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
22458 return "fstp%z0\t%y0";
22461 /* There is no non-popping store to memory for XFmode.
22462 So if we need one, follow the store with a load. */
22463 if (GET_MODE (operands[0]) == XFmode)
22464 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
22466 return "fst%z0\t%y0";
22473 /* Output code to perform a conditional jump to LABEL, if C2 flag in
22474 FP status register is set. */
22477 ix86_emit_fp_unordered_jump (rtx label)
22479 rtx reg = gen_reg_rtx (HImode);
22482 emit_insn (gen_x86_fnstsw_1 (reg));
22484 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
22486 emit_insn (gen_x86_sahf_1 (reg));
22488 temp = gen_rtx_REG (CCmode, FLAGS_REG);
22489 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
22493 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
22495 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
22496 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
22499 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
22500 gen_rtx_LABEL_REF (VOIDmode, label),
22502 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
22504 emit_jump_insn (temp);
22505 predict_jump (REG_BR_PROB_BASE * 10 / 100);
22508 /* Output code to perform a log1p XFmode calculation. */
22510 void ix86_emit_i387_log1p (rtx op0, rtx op1)
22512 rtx label1 = gen_label_rtx ();
22513 rtx label2 = gen_label_rtx ();
22515 rtx tmp = gen_reg_rtx (XFmode);
22516 rtx tmp2 = gen_reg_rtx (XFmode);
22518 emit_insn (gen_absxf2 (tmp, op1));
22519 emit_insn (gen_cmpxf (tmp,
22520 CONST_DOUBLE_FROM_REAL_VALUE (
22521 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
22523 emit_jump_insn (gen_bge (label1));
22525 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
22526 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
22527 emit_jump (label2);
22529 emit_label (label1);
22530 emit_move_insn (tmp, CONST1_RTX (XFmode));
22531 emit_insn (gen_addxf3 (tmp, op1, tmp));
22532 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
22533 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
22535 emit_label (label2);
22538 /* Output code to perform a Newton-Rhapson approximation of a single precision
22539 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
22541 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
22543 rtx x0, x1, e0, e1, two;
22545 x0 = gen_reg_rtx (mode);
22546 e0 = gen_reg_rtx (mode);
22547 e1 = gen_reg_rtx (mode);
22548 x1 = gen_reg_rtx (mode);
22550 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
22552 if (VECTOR_MODE_P (mode))
22553 two = ix86_build_const_vector (SFmode, true, two);
22555 two = force_reg (mode, two);
22557 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
22559 /* x0 = 1./b estimate */
22560 emit_insn (gen_rtx_SET (VOIDmode, x0,
22561 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
22564 emit_insn (gen_rtx_SET (VOIDmode, e0,
22565 gen_rtx_MULT (mode, x0, b)));
22567 emit_insn (gen_rtx_SET (VOIDmode, e1,
22568 gen_rtx_MINUS (mode, two, e0)));
22570 emit_insn (gen_rtx_SET (VOIDmode, x1,
22571 gen_rtx_MULT (mode, x0, e1)));
22573 emit_insn (gen_rtx_SET (VOIDmode, res,
22574 gen_rtx_MULT (mode, a, x1)));
22577 /* Output code to perform a Newton-Rhapson approximation of a
22578 single precision floating point [reciprocal] square root. */
22580 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
22583 rtx x0, e0, e1, e2, e3, three, half;
22585 x0 = gen_reg_rtx (mode);
22586 e0 = gen_reg_rtx (mode);
22587 e1 = gen_reg_rtx (mode);
22588 e2 = gen_reg_rtx (mode);
22589 e3 = gen_reg_rtx (mode);
22591 three = CONST_DOUBLE_FROM_REAL_VALUE (dconst3, SFmode);
22592 half = CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode);
22594 if (VECTOR_MODE_P (mode))
22596 three = ix86_build_const_vector (SFmode, true, three);
22597 half = ix86_build_const_vector (SFmode, true, half);
22600 three = force_reg (mode, three);
22601 half = force_reg (mode, half);
22603 /* sqrt(a) = 0.5 * a * rsqrtss(a) * (3.0 - a * rsqrtss(a) * rsqrtss(a))
22604 1.0 / sqrt(a) = 0.5 * rsqrtss(a) * (3.0 - a * rsqrtss(a) * rsqrtss(a)) */
22606 /* x0 = 1./sqrt(a) estimate */
22607 emit_insn (gen_rtx_SET (VOIDmode, x0,
22608 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
22611 emit_insn (gen_rtx_SET (VOIDmode, e0,
22612 gen_rtx_MULT (mode, x0, a)));
22614 emit_insn (gen_rtx_SET (VOIDmode, e1,
22615 gen_rtx_MULT (mode, e0, x0)));
22617 emit_insn (gen_rtx_SET (VOIDmode, e2,
22618 gen_rtx_MINUS (mode, three, e1)));
22621 emit_insn (gen_rtx_SET (VOIDmode, e3,
22622 gen_rtx_MULT (mode, half, x0)));
22625 emit_insn (gen_rtx_SET (VOIDmode, e3,
22626 gen_rtx_MULT (mode, half, e0)));
22627 /* ret = e2 * e3 */
22628 emit_insn (gen_rtx_SET (VOIDmode, res,
22629 gen_rtx_MULT (mode, e2, e3)));
22632 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
22634 static void ATTRIBUTE_UNUSED
22635 i386_solaris_elf_named_section (const char *name, unsigned int flags,
22638 /* With Binutils 2.15, the "@unwind" marker must be specified on
22639 every occurrence of the ".eh_frame" section, not just the first
22642 && strcmp (name, ".eh_frame") == 0)
22644 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
22645 flags & SECTION_WRITE ? "aw" : "a");
22648 default_elf_asm_named_section (name, flags, decl);
22651 /* Return the mangling of TYPE if it is an extended fundamental type. */
22653 static const char *
22654 ix86_mangle_fundamental_type (tree type)
22656 switch (TYPE_MODE (type))
22659 /* __float128 is "g". */
22662 /* "long double" or __float80 is "e". */
22669 /* For 32-bit code we can save PIC register setup by using
22670 __stack_chk_fail_local hidden function instead of calling
22671 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
22672 register, so it is better to call __stack_chk_fail directly. */
22675 ix86_stack_protect_fail (void)
22677 return TARGET_64BIT
22678 ? default_external_stack_protect_fail ()
22679 : default_hidden_stack_protect_fail ();
22682 /* Select a format to encode pointers in exception handling data. CODE
22683 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
22684 true if the symbol may be affected by dynamic relocations.
22686 ??? All x86 object file formats are capable of representing this.
22687 After all, the relocation needed is the same as for the call insn.
22688 Whether or not a particular assembler allows us to enter such, I
22689 guess we'll have to see. */
22691 asm_preferred_eh_data_format (int code, int global)
22695 int type = DW_EH_PE_sdata8;
22697 || ix86_cmodel == CM_SMALL_PIC
22698 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
22699 type = DW_EH_PE_sdata4;
22700 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
22702 if (ix86_cmodel == CM_SMALL
22703 || (ix86_cmodel == CM_MEDIUM && code))
22704 return DW_EH_PE_udata4;
22705 return DW_EH_PE_absptr;
22708 /* Expand copysign from SIGN to the positive value ABS_VALUE
22709 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
22712 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
22714 enum machine_mode mode = GET_MODE (sign);
22715 rtx sgn = gen_reg_rtx (mode);
22716 if (mask == NULL_RTX)
22718 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
22719 if (!VECTOR_MODE_P (mode))
22721 /* We need to generate a scalar mode mask in this case. */
22722 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
22723 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
22724 mask = gen_reg_rtx (mode);
22725 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
22729 mask = gen_rtx_NOT (mode, mask);
22730 emit_insn (gen_rtx_SET (VOIDmode, sgn,
22731 gen_rtx_AND (mode, mask, sign)));
22732 emit_insn (gen_rtx_SET (VOIDmode, result,
22733 gen_rtx_IOR (mode, abs_value, sgn)));
22736 /* Expand fabs (OP0) and return a new rtx that holds the result. The
22737 mask for masking out the sign-bit is stored in *SMASK, if that is
22740 ix86_expand_sse_fabs (rtx op0, rtx *smask)
22742 enum machine_mode mode = GET_MODE (op0);
22745 xa = gen_reg_rtx (mode);
22746 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
22747 if (!VECTOR_MODE_P (mode))
22749 /* We need to generate a scalar mode mask in this case. */
22750 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
22751 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
22752 mask = gen_reg_rtx (mode);
22753 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
22755 emit_insn (gen_rtx_SET (VOIDmode, xa,
22756 gen_rtx_AND (mode, op0, mask)));
22764 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
22765 swapping the operands if SWAP_OPERANDS is true. The expanded
22766 code is a forward jump to a newly created label in case the
22767 comparison is true. The generated label rtx is returned. */
22769 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
22770 bool swap_operands)
22781 label = gen_label_rtx ();
22782 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
22783 emit_insn (gen_rtx_SET (VOIDmode, tmp,
22784 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
22785 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
22786 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
22787 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
22788 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
22789 JUMP_LABEL (tmp) = label;
22794 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
22795 using comparison code CODE. Operands are swapped for the comparison if
22796 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
22798 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
22799 bool swap_operands)
22801 enum machine_mode mode = GET_MODE (op0);
22802 rtx mask = gen_reg_rtx (mode);
22811 if (mode == DFmode)
22812 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
22813 gen_rtx_fmt_ee (code, mode, op0, op1)));
22815 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
22816 gen_rtx_fmt_ee (code, mode, op0, op1)));
22821 /* Generate and return a rtx of mode MODE for 2**n where n is the number
22822 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
22824 ix86_gen_TWO52 (enum machine_mode mode)
22826 REAL_VALUE_TYPE TWO52r;
22829 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
22830 TWO52 = const_double_from_real_value (TWO52r, mode);
22831 TWO52 = force_reg (mode, TWO52);
22836 /* Expand SSE sequence for computing lround from OP1 storing
22839 ix86_expand_lround (rtx op0, rtx op1)
22841 /* C code for the stuff we're doing below:
22842 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
22845 enum machine_mode mode = GET_MODE (op1);
22846 const struct real_format *fmt;
22847 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
22850 /* load nextafter (0.5, 0.0) */
22851 fmt = REAL_MODE_FORMAT (mode);
22852 real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
22853 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
22855 /* adj = copysign (0.5, op1) */
22856 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
22857 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
22859 /* adj = op1 + adj */
22860 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
22862 /* op0 = (imode)adj */
22863 expand_fix (op0, adj, 0);
22866 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
22869 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
22871 /* C code for the stuff we're doing below (for do_floor):
22873 xi -= (double)xi > op1 ? 1 : 0;
22876 enum machine_mode fmode = GET_MODE (op1);
22877 enum machine_mode imode = GET_MODE (op0);
22878 rtx ireg, freg, label, tmp;
22880 /* reg = (long)op1 */
22881 ireg = gen_reg_rtx (imode);
22882 expand_fix (ireg, op1, 0);
22884 /* freg = (double)reg */
22885 freg = gen_reg_rtx (fmode);
22886 expand_float (freg, ireg, 0);
22888 /* ireg = (freg > op1) ? ireg - 1 : ireg */
22889 label = ix86_expand_sse_compare_and_jump (UNLE,
22890 freg, op1, !do_floor);
22891 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
22892 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
22893 emit_move_insn (ireg, tmp);
22895 emit_label (label);
22896 LABEL_NUSES (label) = 1;
22898 emit_move_insn (op0, ireg);
22901 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
22902 result in OPERAND0. */
22904 ix86_expand_rint (rtx operand0, rtx operand1)
22906 /* C code for the stuff we're doing below:
22907 xa = fabs (operand1);
22908 if (!isless (xa, 2**52))
22910 xa = xa + 2**52 - 2**52;
22911 return copysign (xa, operand1);
22913 enum machine_mode mode = GET_MODE (operand0);
22914 rtx res, xa, label, TWO52, mask;
22916 res = gen_reg_rtx (mode);
22917 emit_move_insn (res, operand1);
22919 /* xa = abs (operand1) */
22920 xa = ix86_expand_sse_fabs (res, &mask);
22922 /* if (!isless (xa, TWO52)) goto label; */
22923 TWO52 = ix86_gen_TWO52 (mode);
22924 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22926 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
22927 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
22929 ix86_sse_copysign_to_positive (res, xa, res, mask);
22931 emit_label (label);
22932 LABEL_NUSES (label) = 1;
22934 emit_move_insn (operand0, res);
22937 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
22940 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
22942 /* C code for the stuff we expand below.
22943 double xa = fabs (x), x2;
22944 if (!isless (xa, TWO52))
22946 xa = xa + TWO52 - TWO52;
22947 x2 = copysign (xa, x);
22956 enum machine_mode mode = GET_MODE (operand0);
22957 rtx xa, TWO52, tmp, label, one, res, mask;
22959 TWO52 = ix86_gen_TWO52 (mode);
22961 /* Temporary for holding the result, initialized to the input
22962 operand to ease control flow. */
22963 res = gen_reg_rtx (mode);
22964 emit_move_insn (res, operand1);
22966 /* xa = abs (operand1) */
22967 xa = ix86_expand_sse_fabs (res, &mask);
22969 /* if (!isless (xa, TWO52)) goto label; */
22970 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22972 /* xa = xa + TWO52 - TWO52; */
22973 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
22974 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
22976 /* xa = copysign (xa, operand1) */
22977 ix86_sse_copysign_to_positive (xa, xa, res, mask);
22979 /* generate 1.0 or -1.0 */
22980 one = force_reg (mode,
22981 const_double_from_real_value (do_floor
22982 ? dconst1 : dconstm1, mode));
22984 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
22985 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
22986 emit_insn (gen_rtx_SET (VOIDmode, tmp,
22987 gen_rtx_AND (mode, one, tmp)));
22988 /* We always need to subtract here to preserve signed zero. */
22989 tmp = expand_simple_binop (mode, MINUS,
22990 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
22991 emit_move_insn (res, tmp);
22993 emit_label (label);
22994 LABEL_NUSES (label) = 1;
22996 emit_move_insn (operand0, res);
22999 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
23002 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
23004 /* C code for the stuff we expand below.
23005 double xa = fabs (x), x2;
23006 if (!isless (xa, TWO52))
23008 x2 = (double)(long)x;
23015 if (HONOR_SIGNED_ZEROS (mode))
23016 return copysign (x2, x);
23019 enum machine_mode mode = GET_MODE (operand0);
23020 rtx xa, xi, TWO52, tmp, label, one, res, mask;
23022 TWO52 = ix86_gen_TWO52 (mode);
23024 /* Temporary for holding the result, initialized to the input
23025 operand to ease control flow. */
23026 res = gen_reg_rtx (mode);
23027 emit_move_insn (res, operand1);
23029 /* xa = abs (operand1) */
23030 xa = ix86_expand_sse_fabs (res, &mask);
23032 /* if (!isless (xa, TWO52)) goto label; */
23033 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
23035 /* xa = (double)(long)x */
23036 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
23037 expand_fix (xi, res, 0);
23038 expand_float (xa, xi, 0);
23041 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
23043 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
23044 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
23045 emit_insn (gen_rtx_SET (VOIDmode, tmp,
23046 gen_rtx_AND (mode, one, tmp)));
23047 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
23048 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
23049 emit_move_insn (res, tmp);
23051 if (HONOR_SIGNED_ZEROS (mode))
23052 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
23054 emit_label (label);
23055 LABEL_NUSES (label) = 1;
23057 emit_move_insn (operand0, res);
23060 /* Expand SSE sequence for computing round from OPERAND1 storing
23061 into OPERAND0. Sequence that works without relying on DImode truncation
23062 via cvttsd2siq that is only available on 64bit targets. */
23064 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
23066 /* C code for the stuff we expand below.
23067 double xa = fabs (x), xa2, x2;
23068 if (!isless (xa, TWO52))
23070 Using the absolute value and copying back sign makes
23071 -0.0 -> -0.0 correct.
23072 xa2 = xa + TWO52 - TWO52;
23077 else if (dxa > 0.5)
23079 x2 = copysign (xa2, x);
23082 enum machine_mode mode = GET_MODE (operand0);
23083 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
23085 TWO52 = ix86_gen_TWO52 (mode);
23087 /* Temporary for holding the result, initialized to the input
23088 operand to ease control flow. */
23089 res = gen_reg_rtx (mode);
23090 emit_move_insn (res, operand1);
23092 /* xa = abs (operand1) */
23093 xa = ix86_expand_sse_fabs (res, &mask);
23095 /* if (!isless (xa, TWO52)) goto label; */
23096 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
23098 /* xa2 = xa + TWO52 - TWO52; */
23099 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
23100 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
23102 /* dxa = xa2 - xa; */
23103 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
23105 /* generate 0.5, 1.0 and -0.5 */
23106 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
23107 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
23108 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
23112 tmp = gen_reg_rtx (mode);
23113 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
23114 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
23115 emit_insn (gen_rtx_SET (VOIDmode, tmp,
23116 gen_rtx_AND (mode, one, tmp)));
23117 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
23118 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
23119 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
23120 emit_insn (gen_rtx_SET (VOIDmode, tmp,
23121 gen_rtx_AND (mode, one, tmp)));
23122 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
23124 /* res = copysign (xa2, operand1) */
23125 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
23127 emit_label (label);
23128 LABEL_NUSES (label) = 1;
23130 emit_move_insn (operand0, res);
23133 /* Expand SSE sequence for computing trunc from OPERAND1 storing
23136 ix86_expand_trunc (rtx operand0, rtx operand1)
23138 /* C code for SSE variant we expand below.
23139 double xa = fabs (x), x2;
23140 if (!isless (xa, TWO52))
23142 x2 = (double)(long)x;
23143 if (HONOR_SIGNED_ZEROS (mode))
23144 return copysign (x2, x);
23147 enum machine_mode mode = GET_MODE (operand0);
23148 rtx xa, xi, TWO52, label, res, mask;
23150 TWO52 = ix86_gen_TWO52 (mode);
23152 /* Temporary for holding the result, initialized to the input
23153 operand to ease control flow. */
23154 res = gen_reg_rtx (mode);
23155 emit_move_insn (res, operand1);
23157 /* xa = abs (operand1) */
23158 xa = ix86_expand_sse_fabs (res, &mask);
23160 /* if (!isless (xa, TWO52)) goto label; */
23161 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
23163 /* x = (double)(long)x */
23164 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
23165 expand_fix (xi, res, 0);
23166 expand_float (res, xi, 0);
23168 if (HONOR_SIGNED_ZEROS (mode))
23169 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
23171 emit_label (label);
23172 LABEL_NUSES (label) = 1;
23174 emit_move_insn (operand0, res);
23177 /* Expand SSE sequence for computing trunc from OPERAND1 storing
23180 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
23182 enum machine_mode mode = GET_MODE (operand0);
23183 rtx xa, mask, TWO52, label, one, res, smask, tmp;
23185 /* C code for SSE variant we expand below.
23186 double xa = fabs (x), x2;
23187 if (!isless (xa, TWO52))
23189 xa2 = xa + TWO52 - TWO52;
23193 x2 = copysign (xa2, x);
23197 TWO52 = ix86_gen_TWO52 (mode);
23199 /* Temporary for holding the result, initialized to the input
23200 operand to ease control flow. */
23201 res = gen_reg_rtx (mode);
23202 emit_move_insn (res, operand1);
23204 /* xa = abs (operand1) */
23205 xa = ix86_expand_sse_fabs (res, &smask);
23207 /* if (!isless (xa, TWO52)) goto label; */
23208 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
23210 /* res = xa + TWO52 - TWO52; */
23211 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
23212 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
23213 emit_move_insn (res, tmp);
23216 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
23218 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
23219 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
23220 emit_insn (gen_rtx_SET (VOIDmode, mask,
23221 gen_rtx_AND (mode, mask, one)));
23222 tmp = expand_simple_binop (mode, MINUS,
23223 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
23224 emit_move_insn (res, tmp);
23226 /* res = copysign (res, operand1) */
23227 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
23229 emit_label (label);
23230 LABEL_NUSES (label) = 1;
23232 emit_move_insn (operand0, res);
23235 /* Expand SSE sequence for computing round from OPERAND1 storing
23238 ix86_expand_round (rtx operand0, rtx operand1)
23240 /* C code for the stuff we're doing below:
23241 double xa = fabs (x);
23242 if (!isless (xa, TWO52))
23244 xa = (double)(long)(xa + nextafter (0.5, 0.0));
23245 return copysign (xa, x);
23247 enum machine_mode mode = GET_MODE (operand0);
23248 rtx res, TWO52, xa, label, xi, half, mask;
23249 const struct real_format *fmt;
23250 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
23252 /* Temporary for holding the result, initialized to the input
23253 operand to ease control flow. */
23254 res = gen_reg_rtx (mode);
23255 emit_move_insn (res, operand1);
23257 TWO52 = ix86_gen_TWO52 (mode);
23258 xa = ix86_expand_sse_fabs (res, &mask);
23259 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
23261 /* load nextafter (0.5, 0.0) */
23262 fmt = REAL_MODE_FORMAT (mode);
23263 real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
23264 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
23266 /* xa = xa + 0.5 */
23267 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
23268 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
23270 /* xa = (double)(int64_t)xa */
23271 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
23272 expand_fix (xi, xa, 0);
23273 expand_float (xa, xi, 0);
23275 /* res = copysign (xa, operand1) */
23276 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
23278 emit_label (label);
23279 LABEL_NUSES (label) = 1;
23281 emit_move_insn (operand0, res);
23285 /* Table of valid machine attributes. */
23286 static const struct attribute_spec ix86_attribute_table[] =
23288 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
23289 /* Stdcall attribute says callee is responsible for popping arguments
23290 if they are not variable. */
23291 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
23292 /* Fastcall attribute says callee is responsible for popping arguments
23293 if they are not variable. */
23294 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
23295 /* Cdecl attribute says the callee is a normal C declaration */
23296 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
23297 /* Regparm attribute specifies how many integer arguments are to be
23298 passed in registers. */
23299 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
23300 /* Sseregparm attribute says we are using x86_64 calling conventions
23301 for FP arguments. */
23302 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
23303 /* force_align_arg_pointer says this function realigns the stack at entry. */
23304 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
23305 false, true, true, ix86_handle_cconv_attribute },
23306 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
23307 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
23308 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
23309 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
23311 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
23312 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
23313 #ifdef SUBTARGET_ATTRIBUTE_TABLE
23314 SUBTARGET_ATTRIBUTE_TABLE,
23316 { NULL, 0, 0, false, false, false, NULL }
23319 /* Initialize the GCC target structure. */
23320 #undef TARGET_ATTRIBUTE_TABLE
23321 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
23322 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
23323 # undef TARGET_MERGE_DECL_ATTRIBUTES
23324 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
23327 #undef TARGET_COMP_TYPE_ATTRIBUTES
23328 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
23330 #undef TARGET_INIT_BUILTINS
23331 #define TARGET_INIT_BUILTINS ix86_init_builtins
23332 #undef TARGET_EXPAND_BUILTIN
23333 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
23335 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
23336 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
23337 ix86_builtin_vectorized_function
23339 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
23340 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
23342 #undef TARGET_BUILTIN_RECIPROCAL
23343 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
23345 #undef TARGET_ASM_FUNCTION_EPILOGUE
23346 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
23348 #undef TARGET_ENCODE_SECTION_INFO
23349 #ifndef SUBTARGET_ENCODE_SECTION_INFO
23350 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
23352 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
23355 #undef TARGET_ASM_OPEN_PAREN
23356 #define TARGET_ASM_OPEN_PAREN ""
23357 #undef TARGET_ASM_CLOSE_PAREN
23358 #define TARGET_ASM_CLOSE_PAREN ""
23360 #undef TARGET_ASM_ALIGNED_HI_OP
23361 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
23362 #undef TARGET_ASM_ALIGNED_SI_OP
23363 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
23365 #undef TARGET_ASM_ALIGNED_DI_OP
23366 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
23369 #undef TARGET_ASM_UNALIGNED_HI_OP
23370 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
23371 #undef TARGET_ASM_UNALIGNED_SI_OP
23372 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
23373 #undef TARGET_ASM_UNALIGNED_DI_OP
23374 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
23376 #undef TARGET_SCHED_ADJUST_COST
23377 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
23378 #undef TARGET_SCHED_ISSUE_RATE
23379 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
23380 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
23381 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
23382 ia32_multipass_dfa_lookahead
23384 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
23385 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
23388 #undef TARGET_HAVE_TLS
23389 #define TARGET_HAVE_TLS true
23391 #undef TARGET_CANNOT_FORCE_CONST_MEM
23392 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
23393 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
23394 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
23396 #undef TARGET_DELEGITIMIZE_ADDRESS
23397 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
23399 #undef TARGET_MS_BITFIELD_LAYOUT_P
23400 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
23403 #undef TARGET_BINDS_LOCAL_P
23404 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
23406 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
23407 #undef TARGET_BINDS_LOCAL_P
23408 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
23411 #undef TARGET_ASM_OUTPUT_MI_THUNK
23412 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
23413 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
23414 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
23416 #undef TARGET_ASM_FILE_START
23417 #define TARGET_ASM_FILE_START x86_file_start
23419 #undef TARGET_DEFAULT_TARGET_FLAGS
23420 #define TARGET_DEFAULT_TARGET_FLAGS \
23422 | TARGET_SUBTARGET_DEFAULT \
23423 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
23425 #undef TARGET_HANDLE_OPTION
23426 #define TARGET_HANDLE_OPTION ix86_handle_option
23428 #undef TARGET_RTX_COSTS
23429 #define TARGET_RTX_COSTS ix86_rtx_costs
23430 #undef TARGET_ADDRESS_COST
23431 #define TARGET_ADDRESS_COST ix86_address_cost
23433 #undef TARGET_FIXED_CONDITION_CODE_REGS
23434 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
23435 #undef TARGET_CC_MODES_COMPATIBLE
23436 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
23438 #undef TARGET_MACHINE_DEPENDENT_REORG
23439 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
23441 #undef TARGET_BUILD_BUILTIN_VA_LIST
23442 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
23444 #undef TARGET_MD_ASM_CLOBBERS
23445 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
23447 #undef TARGET_PROMOTE_PROTOTYPES
23448 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
23449 #undef TARGET_STRUCT_VALUE_RTX
23450 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
23451 #undef TARGET_SETUP_INCOMING_VARARGS
23452 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
23453 #undef TARGET_MUST_PASS_IN_STACK
23454 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
23455 #undef TARGET_PASS_BY_REFERENCE
23456 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
23457 #undef TARGET_INTERNAL_ARG_POINTER
23458 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
23459 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
23460 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
23461 #undef TARGET_STRICT_ARGUMENT_NAMING
23462 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
23464 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
23465 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
23467 #undef TARGET_SCALAR_MODE_SUPPORTED_P
23468 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
23470 #undef TARGET_VECTOR_MODE_SUPPORTED_P
23471 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
23474 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
23475 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
23478 #ifdef SUBTARGET_INSERT_ATTRIBUTES
23479 #undef TARGET_INSERT_ATTRIBUTES
23480 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
23483 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
23484 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
23486 #undef TARGET_STACK_PROTECT_FAIL
23487 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
23489 #undef TARGET_FUNCTION_VALUE
23490 #define TARGET_FUNCTION_VALUE ix86_function_value
23492 struct gcc_target targetm = TARGET_INITIALIZER;
23494 #include "gt-i386.h"
OSDN Git Service
