1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #include "tm-constrs.h"
56 static int x86_builtin_vectorization_cost (bool);
58 #ifndef CHECK_STACK_LIMIT
59 #define CHECK_STACK_LIMIT (-1)
62 /* Return index of given mode in mult and division cost tables. */
63 #define MODE_INDEX(mode) \
64 ((mode) == QImode ? 0 \
65 : (mode) == HImode ? 1 \
66 : (mode) == SImode ? 2 \
67 : (mode) == DImode ? 3 \
70 /* Processor costs (relative to an add) */
71 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
72 #define COSTS_N_BYTES(N) ((N) * 2)
74 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
77 struct processor_costs size_cost = { /* costs for tuning for size */
78 COSTS_N_BYTES (2), /* cost of an add instruction */
79 COSTS_N_BYTES (3), /* cost of a lea instruction */
80 COSTS_N_BYTES (2), /* variable shift costs */
81 COSTS_N_BYTES (3), /* constant shift costs */
82 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
83 COSTS_N_BYTES (3), /* HI */
84 COSTS_N_BYTES (3), /* SI */
85 COSTS_N_BYTES (3), /* DI */
86 COSTS_N_BYTES (5)}, /* other */
87 0, /* cost of multiply per each bit set */
88 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
89 COSTS_N_BYTES (3), /* HI */
90 COSTS_N_BYTES (3), /* SI */
91 COSTS_N_BYTES (3), /* DI */
92 COSTS_N_BYTES (5)}, /* other */
93 COSTS_N_BYTES (3), /* cost of movsx */
94 COSTS_N_BYTES (3), /* cost of movzx */
97 2, /* cost for loading QImode using movzbl */
98 {2, 2, 2}, /* cost of loading integer registers
99 in QImode, HImode and SImode.
100 Relative to reg-reg move (2). */
101 {2, 2, 2}, /* cost of storing integer registers */
102 2, /* cost of reg,reg fld/fst */
103 {2, 2, 2}, /* cost of loading fp registers
104 in SFmode, DFmode and XFmode */
105 {2, 2, 2}, /* cost of storing fp registers
106 in SFmode, DFmode and XFmode */
107 3, /* cost of moving MMX register */
108 {3, 3}, /* cost of loading MMX registers
109 in SImode and DImode */
110 {3, 3}, /* cost of storing MMX registers
111 in SImode and DImode */
112 3, /* cost of moving SSE register */
113 {3, 3, 3}, /* cost of loading SSE registers
114 in SImode, DImode and TImode */
115 {3, 3, 3}, /* cost of storing SSE registers
116 in SImode, DImode and TImode */
117 3, /* MMX or SSE register to integer */
118 0, /* size of l1 cache */
119 0, /* size of l2 cache */
120 0, /* size of prefetch block */
121 0, /* number of parallel prefetches */
123 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
124 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
125 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
126 COSTS_N_BYTES (2), /* cost of FABS instruction. */
127 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
128 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
129 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
130 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 1, /* scalar_stmt_cost. */
134 1, /* scalar load_cost. */
135 1, /* scalar_store_cost. */
136 1, /* vec_stmt_cost. */
137 1, /* vec_to_scalar_cost. */
138 1, /* scalar_to_vec_cost. */
139 1, /* vec_align_load_cost. */
140 1, /* vec_unalign_load_cost. */
141 1, /* vec_store_cost. */
142 1, /* cond_taken_branch_cost. */
143 1, /* cond_not_taken_branch_cost. */
146 /* Processor costs (relative to an add) */
148 struct processor_costs i386_cost = { /* 386 specific costs */
149 COSTS_N_INSNS (1), /* cost of an add instruction */
150 COSTS_N_INSNS (1), /* cost of a lea instruction */
151 COSTS_N_INSNS (3), /* variable shift costs */
152 COSTS_N_INSNS (2), /* constant shift costs */
153 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
154 COSTS_N_INSNS (6), /* HI */
155 COSTS_N_INSNS (6), /* SI */
156 COSTS_N_INSNS (6), /* DI */
157 COSTS_N_INSNS (6)}, /* other */
158 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
159 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
160 COSTS_N_INSNS (23), /* HI */
161 COSTS_N_INSNS (23), /* SI */
162 COSTS_N_INSNS (23), /* DI */
163 COSTS_N_INSNS (23)}, /* other */
164 COSTS_N_INSNS (3), /* cost of movsx */
165 COSTS_N_INSNS (2), /* cost of movzx */
166 15, /* "large" insn */
168 4, /* cost for loading QImode using movzbl */
169 {2, 4, 2}, /* cost of loading integer registers
170 in QImode, HImode and SImode.
171 Relative to reg-reg move (2). */
172 {2, 4, 2}, /* cost of storing integer registers */
173 2, /* cost of reg,reg fld/fst */
174 {8, 8, 8}, /* cost of loading fp registers
175 in SFmode, DFmode and XFmode */
176 {8, 8, 8}, /* cost of storing fp registers
177 in SFmode, DFmode and XFmode */
178 2, /* cost of moving MMX register */
179 {4, 8}, /* cost of loading MMX registers
180 in SImode and DImode */
181 {4, 8}, /* cost of storing MMX registers
182 in SImode and DImode */
183 2, /* cost of moving SSE register */
184 {4, 8, 16}, /* cost of loading SSE registers
185 in SImode, DImode and TImode */
186 {4, 8, 16}, /* cost of storing SSE registers
187 in SImode, DImode and TImode */
188 3, /* MMX or SSE register to integer */
189 0, /* size of l1 cache */
190 0, /* size of l2 cache */
191 0, /* size of prefetch block */
192 0, /* number of parallel prefetches */
194 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
195 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
196 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
197 COSTS_N_INSNS (22), /* cost of FABS instruction. */
198 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
199 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
200 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
201 DUMMY_STRINGOP_ALGS},
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 1, /* scalar_stmt_cost. */
205 1, /* scalar load_cost. */
206 1, /* scalar_store_cost. */
207 1, /* vec_stmt_cost. */
208 1, /* vec_to_scalar_cost. */
209 1, /* scalar_to_vec_cost. */
210 1, /* vec_align_load_cost. */
211 2, /* vec_unalign_load_cost. */
212 1, /* vec_store_cost. */
213 3, /* cond_taken_branch_cost. */
214 1, /* cond_not_taken_branch_cost. */
218 struct processor_costs i486_cost = { /* 486 specific costs */
219 COSTS_N_INSNS (1), /* cost of an add instruction */
220 COSTS_N_INSNS (1), /* cost of a lea instruction */
221 COSTS_N_INSNS (3), /* variable shift costs */
222 COSTS_N_INSNS (2), /* constant shift costs */
223 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
224 COSTS_N_INSNS (12), /* HI */
225 COSTS_N_INSNS (12), /* SI */
226 COSTS_N_INSNS (12), /* DI */
227 COSTS_N_INSNS (12)}, /* other */
228 1, /* cost of multiply per each bit set */
229 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
230 COSTS_N_INSNS (40), /* HI */
231 COSTS_N_INSNS (40), /* SI */
232 COSTS_N_INSNS (40), /* DI */
233 COSTS_N_INSNS (40)}, /* other */
234 COSTS_N_INSNS (3), /* cost of movsx */
235 COSTS_N_INSNS (2), /* cost of movzx */
236 15, /* "large" insn */
238 4, /* cost for loading QImode using movzbl */
239 {2, 4, 2}, /* cost of loading integer registers
240 in QImode, HImode and SImode.
241 Relative to reg-reg move (2). */
242 {2, 4, 2}, /* cost of storing integer registers */
243 2, /* cost of reg,reg fld/fst */
244 {8, 8, 8}, /* cost of loading fp registers
245 in SFmode, DFmode and XFmode */
246 {8, 8, 8}, /* cost of storing fp registers
247 in SFmode, DFmode and XFmode */
248 2, /* cost of moving MMX register */
249 {4, 8}, /* cost of loading MMX registers
250 in SImode and DImode */
251 {4, 8}, /* cost of storing MMX registers
252 in SImode and DImode */
253 2, /* cost of moving SSE register */
254 {4, 8, 16}, /* cost of loading SSE registers
255 in SImode, DImode and TImode */
256 {4, 8, 16}, /* cost of storing SSE registers
257 in SImode, DImode and TImode */
258 3, /* MMX or SSE register to integer */
259 4, /* size of l1 cache. 486 has 8kB cache
260 shared for code and data, so 4kB is
261 not really precise. */
262 4, /* size of l2 cache */
263 0, /* size of prefetch block */
264 0, /* number of parallel prefetches */
266 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
267 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
268 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
269 COSTS_N_INSNS (3), /* cost of FABS instruction. */
270 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
271 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
272 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
273 DUMMY_STRINGOP_ALGS},
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 1, /* scalar_stmt_cost. */
277 1, /* scalar load_cost. */
278 1, /* scalar_store_cost. */
279 1, /* vec_stmt_cost. */
280 1, /* vec_to_scalar_cost. */
281 1, /* scalar_to_vec_cost. */
282 1, /* vec_align_load_cost. */
283 2, /* vec_unalign_load_cost. */
284 1, /* vec_store_cost. */
285 3, /* cond_taken_branch_cost. */
286 1, /* cond_not_taken_branch_cost. */
290 struct processor_costs pentium_cost = {
291 COSTS_N_INSNS (1), /* cost of an add instruction */
292 COSTS_N_INSNS (1), /* cost of a lea instruction */
293 COSTS_N_INSNS (4), /* variable shift costs */
294 COSTS_N_INSNS (1), /* constant shift costs */
295 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
296 COSTS_N_INSNS (11), /* HI */
297 COSTS_N_INSNS (11), /* SI */
298 COSTS_N_INSNS (11), /* DI */
299 COSTS_N_INSNS (11)}, /* other */
300 0, /* cost of multiply per each bit set */
301 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
302 COSTS_N_INSNS (25), /* HI */
303 COSTS_N_INSNS (25), /* SI */
304 COSTS_N_INSNS (25), /* DI */
305 COSTS_N_INSNS (25)}, /* other */
306 COSTS_N_INSNS (3), /* cost of movsx */
307 COSTS_N_INSNS (2), /* cost of movzx */
308 8, /* "large" insn */
310 6, /* cost for loading QImode using movzbl */
311 {2, 4, 2}, /* cost of loading integer registers
312 in QImode, HImode and SImode.
313 Relative to reg-reg move (2). */
314 {2, 4, 2}, /* cost of storing integer registers */
315 2, /* cost of reg,reg fld/fst */
316 {2, 2, 6}, /* cost of loading fp registers
317 in SFmode, DFmode and XFmode */
318 {4, 4, 6}, /* cost of storing fp registers
319 in SFmode, DFmode and XFmode */
320 8, /* cost of moving MMX register */
321 {8, 8}, /* cost of loading MMX registers
322 in SImode and DImode */
323 {8, 8}, /* cost of storing MMX registers
324 in SImode and DImode */
325 2, /* cost of moving SSE register */
326 {4, 8, 16}, /* cost of loading SSE registers
327 in SImode, DImode and TImode */
328 {4, 8, 16}, /* cost of storing SSE registers
329 in SImode, DImode and TImode */
330 3, /* MMX or SSE register to integer */
331 8, /* size of l1 cache. */
332 8, /* size of l2 cache */
333 0, /* size of prefetch block */
334 0, /* number of parallel prefetches */
336 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
337 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
338 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
339 COSTS_N_INSNS (1), /* cost of FABS instruction. */
340 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
341 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
342 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
343 DUMMY_STRINGOP_ALGS},
344 {{libcall, {{-1, rep_prefix_4_byte}}},
345 DUMMY_STRINGOP_ALGS},
346 1, /* scalar_stmt_cost. */
347 1, /* scalar load_cost. */
348 1, /* scalar_store_cost. */
349 1, /* vec_stmt_cost. */
350 1, /* vec_to_scalar_cost. */
351 1, /* scalar_to_vec_cost. */
352 1, /* vec_align_load_cost. */
353 2, /* vec_unalign_load_cost. */
354 1, /* vec_store_cost. */
355 3, /* cond_taken_branch_cost. */
356 1, /* cond_not_taken_branch_cost. */
360 struct processor_costs pentiumpro_cost = {
361 COSTS_N_INSNS (1), /* cost of an add instruction */
362 COSTS_N_INSNS (1), /* cost of a lea instruction */
363 COSTS_N_INSNS (1), /* variable shift costs */
364 COSTS_N_INSNS (1), /* constant shift costs */
365 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
366 COSTS_N_INSNS (4), /* HI */
367 COSTS_N_INSNS (4), /* SI */
368 COSTS_N_INSNS (4), /* DI */
369 COSTS_N_INSNS (4)}, /* other */
370 0, /* cost of multiply per each bit set */
371 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
372 COSTS_N_INSNS (17), /* HI */
373 COSTS_N_INSNS (17), /* SI */
374 COSTS_N_INSNS (17), /* DI */
375 COSTS_N_INSNS (17)}, /* other */
376 COSTS_N_INSNS (1), /* cost of movsx */
377 COSTS_N_INSNS (1), /* cost of movzx */
378 8, /* "large" insn */
380 2, /* cost for loading QImode using movzbl */
381 {4, 4, 4}, /* cost of loading integer registers
382 in QImode, HImode and SImode.
383 Relative to reg-reg move (2). */
384 {2, 2, 2}, /* cost of storing integer registers */
385 2, /* cost of reg,reg fld/fst */
386 {2, 2, 6}, /* cost of loading fp registers
387 in SFmode, DFmode and XFmode */
388 {4, 4, 6}, /* cost of storing fp registers
389 in SFmode, DFmode and XFmode */
390 2, /* cost of moving MMX register */
391 {2, 2}, /* cost of loading MMX registers
392 in SImode and DImode */
393 {2, 2}, /* cost of storing MMX registers
394 in SImode and DImode */
395 2, /* cost of moving SSE register */
396 {2, 2, 8}, /* cost of loading SSE registers
397 in SImode, DImode and TImode */
398 {2, 2, 8}, /* cost of storing SSE registers
399 in SImode, DImode and TImode */
400 3, /* MMX or SSE register to integer */
401 8, /* size of l1 cache. */
402 256, /* size of l2 cache */
403 32, /* size of prefetch block */
404 6, /* number of parallel prefetches */
406 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
407 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
408 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
409 COSTS_N_INSNS (2), /* cost of FABS instruction. */
410 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
411 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
412 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
413 the alignment). For small blocks inline loop is still a noticeable win, for bigger
414 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
415 more expensive startup time in CPU, but after 4K the difference is down in the noise.
417 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
418 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
419 DUMMY_STRINGOP_ALGS},
420 {{rep_prefix_4_byte, {{1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, libcall}}},
422 DUMMY_STRINGOP_ALGS},
423 1, /* scalar_stmt_cost. */
424 1, /* scalar load_cost. */
425 1, /* scalar_store_cost. */
426 1, /* vec_stmt_cost. */
427 1, /* vec_to_scalar_cost. */
428 1, /* scalar_to_vec_cost. */
429 1, /* vec_align_load_cost. */
430 2, /* vec_unalign_load_cost. */
431 1, /* vec_store_cost. */
432 3, /* cond_taken_branch_cost. */
433 1, /* cond_not_taken_branch_cost. */
437 struct processor_costs geode_cost = {
438 COSTS_N_INSNS (1), /* cost of an add instruction */
439 COSTS_N_INSNS (1), /* cost of a lea instruction */
440 COSTS_N_INSNS (2), /* variable shift costs */
441 COSTS_N_INSNS (1), /* constant shift costs */
442 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
443 COSTS_N_INSNS (4), /* HI */
444 COSTS_N_INSNS (7), /* SI */
445 COSTS_N_INSNS (7), /* DI */
446 COSTS_N_INSNS (7)}, /* other */
447 0, /* cost of multiply per each bit set */
448 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
449 COSTS_N_INSNS (23), /* HI */
450 COSTS_N_INSNS (39), /* SI */
451 COSTS_N_INSNS (39), /* DI */
452 COSTS_N_INSNS (39)}, /* other */
453 COSTS_N_INSNS (1), /* cost of movsx */
454 COSTS_N_INSNS (1), /* cost of movzx */
455 8, /* "large" insn */
457 1, /* cost for loading QImode using movzbl */
458 {1, 1, 1}, /* cost of loading integer registers
459 in QImode, HImode and SImode.
460 Relative to reg-reg move (2). */
461 {1, 1, 1}, /* cost of storing integer registers */
462 1, /* cost of reg,reg fld/fst */
463 {1, 1, 1}, /* cost of loading fp registers
464 in SFmode, DFmode and XFmode */
465 {4, 6, 6}, /* cost of storing fp registers
466 in SFmode, DFmode and XFmode */
468 1, /* cost of moving MMX register */
469 {1, 1}, /* cost of loading MMX registers
470 in SImode and DImode */
471 {1, 1}, /* cost of storing MMX registers
472 in SImode and DImode */
473 1, /* cost of moving SSE register */
474 {1, 1, 1}, /* cost of loading SSE registers
475 in SImode, DImode and TImode */
476 {1, 1, 1}, /* cost of storing SSE registers
477 in SImode, DImode and TImode */
478 1, /* MMX or SSE register to integer */
479 64, /* size of l1 cache. */
480 128, /* size of l2 cache. */
481 32, /* size of prefetch block */
482 1, /* number of parallel prefetches */
484 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
485 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
486 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
487 COSTS_N_INSNS (1), /* cost of FABS instruction. */
488 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
489 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
490 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
491 DUMMY_STRINGOP_ALGS},
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 1, /* scalar_stmt_cost. */
495 1, /* scalar load_cost. */
496 1, /* scalar_store_cost. */
497 1, /* vec_stmt_cost. */
498 1, /* vec_to_scalar_cost. */
499 1, /* scalar_to_vec_cost. */
500 1, /* vec_align_load_cost. */
501 2, /* vec_unalign_load_cost. */
502 1, /* vec_store_cost. */
503 3, /* cond_taken_branch_cost. */
504 1, /* cond_not_taken_branch_cost. */
508 struct processor_costs k6_cost = {
509 COSTS_N_INSNS (1), /* cost of an add instruction */
510 COSTS_N_INSNS (2), /* cost of a lea instruction */
511 COSTS_N_INSNS (1), /* variable shift costs */
512 COSTS_N_INSNS (1), /* constant shift costs */
513 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
514 COSTS_N_INSNS (3), /* HI */
515 COSTS_N_INSNS (3), /* SI */
516 COSTS_N_INSNS (3), /* DI */
517 COSTS_N_INSNS (3)}, /* other */
518 0, /* cost of multiply per each bit set */
519 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
520 COSTS_N_INSNS (18), /* HI */
521 COSTS_N_INSNS (18), /* SI */
522 COSTS_N_INSNS (18), /* DI */
523 COSTS_N_INSNS (18)}, /* other */
524 COSTS_N_INSNS (2), /* cost of movsx */
525 COSTS_N_INSNS (2), /* cost of movzx */
526 8, /* "large" insn */
528 3, /* cost for loading QImode using movzbl */
529 {4, 5, 4}, /* cost of loading integer registers
530 in QImode, HImode and SImode.
531 Relative to reg-reg move (2). */
532 {2, 3, 2}, /* cost of storing integer registers */
533 4, /* cost of reg,reg fld/fst */
534 {6, 6, 6}, /* cost of loading fp registers
535 in SFmode, DFmode and XFmode */
536 {4, 4, 4}, /* cost of storing fp registers
537 in SFmode, DFmode and XFmode */
538 2, /* cost of moving MMX register */
539 {2, 2}, /* cost of loading MMX registers
540 in SImode and DImode */
541 {2, 2}, /* cost of storing MMX registers
542 in SImode and DImode */
543 2, /* cost of moving SSE register */
544 {2, 2, 8}, /* cost of loading SSE registers
545 in SImode, DImode and TImode */
546 {2, 2, 8}, /* cost of storing SSE registers
547 in SImode, DImode and TImode */
548 6, /* MMX or SSE register to integer */
549 32, /* size of l1 cache. */
550 32, /* size of l2 cache. Some models
551 have integrated l2 cache, but
552 optimizing for k6 is not important
553 enough to worry about that. */
554 32, /* size of prefetch block */
555 1, /* number of parallel prefetches */
557 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
558 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
559 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
560 COSTS_N_INSNS (2), /* cost of FABS instruction. */
561 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
562 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
563 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
564 DUMMY_STRINGOP_ALGS},
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 1, /* scalar_stmt_cost. */
568 1, /* scalar load_cost. */
569 1, /* scalar_store_cost. */
570 1, /* vec_stmt_cost. */
571 1, /* vec_to_scalar_cost. */
572 1, /* scalar_to_vec_cost. */
573 1, /* vec_align_load_cost. */
574 2, /* vec_unalign_load_cost. */
575 1, /* vec_store_cost. */
576 3, /* cond_taken_branch_cost. */
577 1, /* cond_not_taken_branch_cost. */
581 struct processor_costs athlon_cost = {
582 COSTS_N_INSNS (1), /* cost of an add instruction */
583 COSTS_N_INSNS (2), /* cost of a lea instruction */
584 COSTS_N_INSNS (1), /* variable shift costs */
585 COSTS_N_INSNS (1), /* constant shift costs */
586 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
587 COSTS_N_INSNS (5), /* HI */
588 COSTS_N_INSNS (5), /* SI */
589 COSTS_N_INSNS (5), /* DI */
590 COSTS_N_INSNS (5)}, /* other */
591 0, /* cost of multiply per each bit set */
592 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
593 COSTS_N_INSNS (26), /* HI */
594 COSTS_N_INSNS (42), /* SI */
595 COSTS_N_INSNS (74), /* DI */
596 COSTS_N_INSNS (74)}, /* other */
597 COSTS_N_INSNS (1), /* cost of movsx */
598 COSTS_N_INSNS (1), /* cost of movzx */
599 8, /* "large" insn */
601 4, /* cost for loading QImode using movzbl */
602 {3, 4, 3}, /* cost of loading integer registers
603 in QImode, HImode and SImode.
604 Relative to reg-reg move (2). */
605 {3, 4, 3}, /* cost of storing integer registers */
606 4, /* cost of reg,reg fld/fst */
607 {4, 4, 12}, /* cost of loading fp registers
608 in SFmode, DFmode and XFmode */
609 {6, 6, 8}, /* cost of storing fp registers
610 in SFmode, DFmode and XFmode */
611 2, /* cost of moving MMX register */
612 {4, 4}, /* cost of loading MMX registers
613 in SImode and DImode */
614 {4, 4}, /* cost of storing MMX registers
615 in SImode and DImode */
616 2, /* cost of moving SSE register */
617 {4, 4, 6}, /* cost of loading SSE registers
618 in SImode, DImode and TImode */
619 {4, 4, 5}, /* cost of storing SSE registers
620 in SImode, DImode and TImode */
621 5, /* MMX or SSE register to integer */
622 64, /* size of l1 cache. */
623 256, /* size of l2 cache. */
624 64, /* size of prefetch block */
625 6, /* number of parallel prefetches */
627 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
628 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
629 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
630 COSTS_N_INSNS (2), /* cost of FABS instruction. */
631 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
632 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
633 /* For some reason, Athlon deals better with REP prefix (relative to loops)
634 compared to K8. Alignment becomes important after 8 bytes for memcpy and
635 128 bytes for memset. */
636 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
637 DUMMY_STRINGOP_ALGS},
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 1, /* scalar_stmt_cost. */
641 1, /* scalar load_cost. */
642 1, /* scalar_store_cost. */
643 1, /* vec_stmt_cost. */
644 1, /* vec_to_scalar_cost. */
645 1, /* scalar_to_vec_cost. */
646 1, /* vec_align_load_cost. */
647 2, /* vec_unalign_load_cost. */
648 1, /* vec_store_cost. */
649 3, /* cond_taken_branch_cost. */
650 1, /* cond_not_taken_branch_cost. */
654 struct processor_costs k8_cost = {
655 COSTS_N_INSNS (1), /* cost of an add instruction */
656 COSTS_N_INSNS (2), /* cost of a lea instruction */
657 COSTS_N_INSNS (1), /* variable shift costs */
658 COSTS_N_INSNS (1), /* constant shift costs */
659 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
660 COSTS_N_INSNS (4), /* HI */
661 COSTS_N_INSNS (3), /* SI */
662 COSTS_N_INSNS (4), /* DI */
663 COSTS_N_INSNS (5)}, /* other */
664 0, /* cost of multiply per each bit set */
665 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
666 COSTS_N_INSNS (26), /* HI */
667 COSTS_N_INSNS (42), /* SI */
668 COSTS_N_INSNS (74), /* DI */
669 COSTS_N_INSNS (74)}, /* other */
670 COSTS_N_INSNS (1), /* cost of movsx */
671 COSTS_N_INSNS (1), /* cost of movzx */
672 8, /* "large" insn */
674 4, /* cost for loading QImode using movzbl */
675 {3, 4, 3}, /* cost of loading integer registers
676 in QImode, HImode and SImode.
677 Relative to reg-reg move (2). */
678 {3, 4, 3}, /* cost of storing integer registers */
679 4, /* cost of reg,reg fld/fst */
680 {4, 4, 12}, /* cost of loading fp registers
681 in SFmode, DFmode and XFmode */
682 {6, 6, 8}, /* cost of storing fp registers
683 in SFmode, DFmode and XFmode */
684 2, /* cost of moving MMX register */
685 {3, 3}, /* cost of loading MMX registers
686 in SImode and DImode */
687 {4, 4}, /* cost of storing MMX registers
688 in SImode and DImode */
689 2, /* cost of moving SSE register */
690 {4, 3, 6}, /* cost of loading SSE registers
691 in SImode, DImode and TImode */
692 {4, 4, 5}, /* cost of storing SSE registers
693 in SImode, DImode and TImode */
694 5, /* MMX or SSE register to integer */
695 64, /* size of l1 cache. */
696 512, /* size of l2 cache. */
697 64, /* size of prefetch block */
698 /* New AMD processors never drop prefetches; if they cannot be performed
699 immediately, they are queued. We set number of simultaneous prefetches
700 to a large constant to reflect this (it probably is not a good idea not
701 to limit number of prefetches at all, as their execution also takes some
703 100, /* number of parallel prefetches */
705 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
706 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
707 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
708 COSTS_N_INSNS (2), /* cost of FABS instruction. */
709 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
710 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
711 /* K8 has optimized REP instruction for medium sized blocks, but for very small
712 blocks it is better to use loop. For large blocks, libcall can do
713 nontemporary accesses and beat inline considerably. */
714 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
715 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
716 {{libcall, {{8, loop}, {24, unrolled_loop},
717 {2048, rep_prefix_4_byte}, {-1, libcall}}},
718 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 4, /* scalar_stmt_cost. */
720 2, /* scalar load_cost. */
721 2, /* scalar_store_cost. */
722 5, /* vec_stmt_cost. */
723 0, /* vec_to_scalar_cost. */
724 2, /* scalar_to_vec_cost. */
725 2, /* vec_align_load_cost. */
726 3, /* vec_unalign_load_cost. */
727 3, /* vec_store_cost. */
728 3, /* cond_taken_branch_cost. */
729 2, /* cond_not_taken_branch_cost. */
732 struct processor_costs amdfam10_cost = {
733 COSTS_N_INSNS (1), /* cost of an add instruction */
734 COSTS_N_INSNS (2), /* cost of a lea instruction */
735 COSTS_N_INSNS (1), /* variable shift costs */
736 COSTS_N_INSNS (1), /* constant shift costs */
737 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
738 COSTS_N_INSNS (4), /* HI */
739 COSTS_N_INSNS (3), /* SI */
740 COSTS_N_INSNS (4), /* DI */
741 COSTS_N_INSNS (5)}, /* other */
742 0, /* cost of multiply per each bit set */
743 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
744 COSTS_N_INSNS (35), /* HI */
745 COSTS_N_INSNS (51), /* SI */
746 COSTS_N_INSNS (83), /* DI */
747 COSTS_N_INSNS (83)}, /* other */
748 COSTS_N_INSNS (1), /* cost of movsx */
749 COSTS_N_INSNS (1), /* cost of movzx */
750 8, /* "large" insn */
752 4, /* cost for loading QImode using movzbl */
753 {3, 4, 3}, /* cost of loading integer registers
754 in QImode, HImode and SImode.
755 Relative to reg-reg move (2). */
756 {3, 4, 3}, /* cost of storing integer registers */
757 4, /* cost of reg,reg fld/fst */
758 {4, 4, 12}, /* cost of loading fp registers
759 in SFmode, DFmode and XFmode */
760 {6, 6, 8}, /* cost of storing fp registers
761 in SFmode, DFmode and XFmode */
762 2, /* cost of moving MMX register */
763 {3, 3}, /* cost of loading MMX registers
764 in SImode and DImode */
765 {4, 4}, /* cost of storing MMX registers
766 in SImode and DImode */
767 2, /* cost of moving SSE register */
768 {4, 4, 3}, /* cost of loading SSE registers
769 in SImode, DImode and TImode */
770 {4, 4, 5}, /* cost of storing SSE registers
771 in SImode, DImode and TImode */
772 3, /* MMX or SSE register to integer */
774 MOVD reg64, xmmreg Double FSTORE 4
775 MOVD reg32, xmmreg Double FSTORE 4
777 MOVD reg64, xmmreg Double FADD 3
779 MOVD reg32, xmmreg Double FADD 3
781 64, /* size of l1 cache. */
782 512, /* size of l2 cache. */
783 64, /* size of prefetch block */
784 /* New AMD processors never drop prefetches; if they cannot be performed
785 immediately, they are queued. We set number of simultaneous prefetches
786 to a large constant to reflect this (it probably is not a good idea not
787 to limit number of prefetches at all, as their execution also takes some
789 100, /* number of parallel prefetches */
791 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
792 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
793 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
794 COSTS_N_INSNS (2), /* cost of FABS instruction. */
795 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
796 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
798 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
799 very small blocks it is better to use loop. For large blocks, libcall can
800 do nontemporary accesses and beat inline considerably. */
801 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
802 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
803 {{libcall, {{8, loop}, {24, unrolled_loop},
804 {2048, rep_prefix_4_byte}, {-1, libcall}}},
805 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 4, /* scalar_stmt_cost. */
807 2, /* scalar load_cost. */
808 2, /* scalar_store_cost. */
809 6, /* vec_stmt_cost. */
810 0, /* vec_to_scalar_cost. */
811 2, /* scalar_to_vec_cost. */
812 2, /* vec_align_load_cost. */
813 2, /* vec_unalign_load_cost. */
814 2, /* vec_store_cost. */
815 2, /* cond_taken_branch_cost. */
816 1, /* cond_not_taken_branch_cost. */
820 struct processor_costs pentium4_cost = {
821 COSTS_N_INSNS (1), /* cost of an add instruction */
822 COSTS_N_INSNS (3), /* cost of a lea instruction */
823 COSTS_N_INSNS (4), /* variable shift costs */
824 COSTS_N_INSNS (4), /* constant shift costs */
825 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
826 COSTS_N_INSNS (15), /* HI */
827 COSTS_N_INSNS (15), /* SI */
828 COSTS_N_INSNS (15), /* DI */
829 COSTS_N_INSNS (15)}, /* other */
830 0, /* cost of multiply per each bit set */
831 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
832 COSTS_N_INSNS (56), /* HI */
833 COSTS_N_INSNS (56), /* SI */
834 COSTS_N_INSNS (56), /* DI */
835 COSTS_N_INSNS (56)}, /* other */
836 COSTS_N_INSNS (1), /* cost of movsx */
837 COSTS_N_INSNS (1), /* cost of movzx */
838 16, /* "large" insn */
840 2, /* cost for loading QImode using movzbl */
841 {4, 5, 4}, /* cost of loading integer registers
842 in QImode, HImode and SImode.
843 Relative to reg-reg move (2). */
844 {2, 3, 2}, /* cost of storing integer registers */
845 2, /* cost of reg,reg fld/fst */
846 {2, 2, 6}, /* cost of loading fp registers
847 in SFmode, DFmode and XFmode */
848 {4, 4, 6}, /* cost of storing fp registers
849 in SFmode, DFmode and XFmode */
850 2, /* cost of moving MMX register */
851 {2, 2}, /* cost of loading MMX registers
852 in SImode and DImode */
853 {2, 2}, /* cost of storing MMX registers
854 in SImode and DImode */
855 12, /* cost of moving SSE register */
856 {12, 12, 12}, /* cost of loading SSE registers
857 in SImode, DImode and TImode */
858 {2, 2, 8}, /* cost of storing SSE registers
859 in SImode, DImode and TImode */
860 10, /* MMX or SSE register to integer */
861 8, /* size of l1 cache. */
862 256, /* size of l2 cache. */
863 64, /* size of prefetch block */
864 6, /* number of parallel prefetches */
866 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
867 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
868 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
869 COSTS_N_INSNS (2), /* cost of FABS instruction. */
870 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
871 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
872 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
873 DUMMY_STRINGOP_ALGS},
874 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
876 DUMMY_STRINGOP_ALGS},
877 1, /* scalar_stmt_cost. */
878 1, /* scalar load_cost. */
879 1, /* scalar_store_cost. */
880 1, /* vec_stmt_cost. */
881 1, /* vec_to_scalar_cost. */
882 1, /* scalar_to_vec_cost. */
883 1, /* vec_align_load_cost. */
884 2, /* vec_unalign_load_cost. */
885 1, /* vec_store_cost. */
886 3, /* cond_taken_branch_cost. */
887 1, /* cond_not_taken_branch_cost. */
891 struct processor_costs nocona_cost = {
892 COSTS_N_INSNS (1), /* cost of an add instruction */
893 COSTS_N_INSNS (1), /* cost of a lea instruction */
894 COSTS_N_INSNS (1), /* variable shift costs */
895 COSTS_N_INSNS (1), /* constant shift costs */
896 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
897 COSTS_N_INSNS (10), /* HI */
898 COSTS_N_INSNS (10), /* SI */
899 COSTS_N_INSNS (10), /* DI */
900 COSTS_N_INSNS (10)}, /* other */
901 0, /* cost of multiply per each bit set */
902 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
903 COSTS_N_INSNS (66), /* HI */
904 COSTS_N_INSNS (66), /* SI */
905 COSTS_N_INSNS (66), /* DI */
906 COSTS_N_INSNS (66)}, /* other */
907 COSTS_N_INSNS (1), /* cost of movsx */
908 COSTS_N_INSNS (1), /* cost of movzx */
909 16, /* "large" insn */
911 4, /* cost for loading QImode using movzbl */
912 {4, 4, 4}, /* cost of loading integer registers
913 in QImode, HImode and SImode.
914 Relative to reg-reg move (2). */
915 {4, 4, 4}, /* cost of storing integer registers */
916 3, /* cost of reg,reg fld/fst */
917 {12, 12, 12}, /* cost of loading fp registers
918 in SFmode, DFmode and XFmode */
919 {4, 4, 4}, /* cost of storing fp registers
920 in SFmode, DFmode and XFmode */
921 6, /* cost of moving MMX register */
922 {12, 12}, /* cost of loading MMX registers
923 in SImode and DImode */
924 {12, 12}, /* cost of storing MMX registers
925 in SImode and DImode */
926 6, /* cost of moving SSE register */
927 {12, 12, 12}, /* cost of loading SSE registers
928 in SImode, DImode and TImode */
929 {12, 12, 12}, /* cost of storing SSE registers
930 in SImode, DImode and TImode */
931 8, /* MMX or SSE register to integer */
932 8, /* size of l1 cache. */
933 1024, /* size of l2 cache. */
934 128, /* size of prefetch block */
935 8, /* number of parallel prefetches */
937 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
938 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
939 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
940 COSTS_N_INSNS (3), /* cost of FABS instruction. */
941 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
942 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
943 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
944 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
945 {100000, unrolled_loop}, {-1, libcall}}}},
946 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
948 {libcall, {{24, loop}, {64, unrolled_loop},
949 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
950 1, /* scalar_stmt_cost. */
951 1, /* scalar load_cost. */
952 1, /* scalar_store_cost. */
953 1, /* vec_stmt_cost. */
954 1, /* vec_to_scalar_cost. */
955 1, /* scalar_to_vec_cost. */
956 1, /* vec_align_load_cost. */
957 2, /* vec_unalign_load_cost. */
958 1, /* vec_store_cost. */
959 3, /* cond_taken_branch_cost. */
960 1, /* cond_not_taken_branch_cost. */
964 struct processor_costs core2_cost = {
965 COSTS_N_INSNS (1), /* cost of an add instruction */
966 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
967 COSTS_N_INSNS (1), /* variable shift costs */
968 COSTS_N_INSNS (1), /* constant shift costs */
969 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
970 COSTS_N_INSNS (3), /* HI */
971 COSTS_N_INSNS (3), /* SI */
972 COSTS_N_INSNS (3), /* DI */
973 COSTS_N_INSNS (3)}, /* other */
974 0, /* cost of multiply per each bit set */
975 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
976 COSTS_N_INSNS (22), /* HI */
977 COSTS_N_INSNS (22), /* SI */
978 COSTS_N_INSNS (22), /* DI */
979 COSTS_N_INSNS (22)}, /* other */
980 COSTS_N_INSNS (1), /* cost of movsx */
981 COSTS_N_INSNS (1), /* cost of movzx */
982 8, /* "large" insn */
984 2, /* cost for loading QImode using movzbl */
985 {6, 6, 6}, /* cost of loading integer registers
986 in QImode, HImode and SImode.
987 Relative to reg-reg move (2). */
988 {4, 4, 4}, /* cost of storing integer registers */
989 2, /* cost of reg,reg fld/fst */
990 {6, 6, 6}, /* cost of loading fp registers
991 in SFmode, DFmode and XFmode */
992 {4, 4, 4}, /* cost of loading integer registers */
993 2, /* cost of moving MMX register */
994 {6, 6}, /* cost of loading MMX registers
995 in SImode and DImode */
996 {4, 4}, /* cost of storing MMX registers
997 in SImode and DImode */
998 2, /* cost of moving SSE register */
999 {6, 6, 6}, /* cost of loading SSE registers
1000 in SImode, DImode and TImode */
1001 {4, 4, 4}, /* cost of storing SSE registers
1002 in SImode, DImode and TImode */
1003 2, /* MMX or SSE register to integer */
1004 32, /* size of l1 cache. */
1005 2048, /* size of l2 cache. */
1006 128, /* size of prefetch block */
1007 8, /* number of parallel prefetches */
1008 3, /* Branch cost */
1009 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1010 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1011 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1012 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1013 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1014 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1015 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1016 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1017 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1018 {{libcall, {{8, loop}, {15, unrolled_loop},
1019 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1020 {libcall, {{24, loop}, {32, unrolled_loop},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 1, /* scalar_stmt_cost. */
1023 1, /* scalar load_cost. */
1024 1, /* scalar_store_cost. */
1025 1, /* vec_stmt_cost. */
1026 1, /* vec_to_scalar_cost. */
1027 1, /* scalar_to_vec_cost. */
1028 1, /* vec_align_load_cost. */
1029 2, /* vec_unalign_load_cost. */
1030 1, /* vec_store_cost. */
1031 3, /* cond_taken_branch_cost. */
1032 1, /* cond_not_taken_branch_cost. */
1035 /* Generic64 should produce code tuned for Nocona and K8. */
1037 struct processor_costs generic64_cost = {
1038 COSTS_N_INSNS (1), /* cost of an add instruction */
1039 /* On all chips taken into consideration lea is 2 cycles and more. With
1040 this cost however our current implementation of synth_mult results in
1041 use of unnecessary temporary registers causing regression on several
1042 SPECfp benchmarks. */
1043 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1044 COSTS_N_INSNS (1), /* variable shift costs */
1045 COSTS_N_INSNS (1), /* constant shift costs */
1046 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1047 COSTS_N_INSNS (4), /* HI */
1048 COSTS_N_INSNS (3), /* SI */
1049 COSTS_N_INSNS (4), /* DI */
1050 COSTS_N_INSNS (2)}, /* other */
1051 0, /* cost of multiply per each bit set */
1052 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1053 COSTS_N_INSNS (26), /* HI */
1054 COSTS_N_INSNS (42), /* SI */
1055 COSTS_N_INSNS (74), /* DI */
1056 COSTS_N_INSNS (74)}, /* other */
1057 COSTS_N_INSNS (1), /* cost of movsx */
1058 COSTS_N_INSNS (1), /* cost of movzx */
1059 8, /* "large" insn */
1060 17, /* MOVE_RATIO */
1061 4, /* cost for loading QImode using movzbl */
1062 {4, 4, 4}, /* cost of loading integer registers
1063 in QImode, HImode and SImode.
1064 Relative to reg-reg move (2). */
1065 {4, 4, 4}, /* cost of storing integer registers */
1066 4, /* cost of reg,reg fld/fst */
1067 {12, 12, 12}, /* cost of loading fp registers
1068 in SFmode, DFmode and XFmode */
1069 {6, 6, 8}, /* cost of storing fp registers
1070 in SFmode, DFmode and XFmode */
1071 2, /* cost of moving MMX register */
1072 {8, 8}, /* cost of loading MMX registers
1073 in SImode and DImode */
1074 {8, 8}, /* cost of storing MMX registers
1075 in SImode and DImode */
1076 2, /* cost of moving SSE register */
1077 {8, 8, 8}, /* cost of loading SSE registers
1078 in SImode, DImode and TImode */
1079 {8, 8, 8}, /* cost of storing SSE registers
1080 in SImode, DImode and TImode */
1081 5, /* MMX or SSE register to integer */
1082 32, /* size of l1 cache. */
1083 512, /* size of l2 cache. */
1084 64, /* size of prefetch block */
1085 6, /* number of parallel prefetches */
1086 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1087 is increased to perhaps more appropriate value of 5. */
1088 3, /* Branch cost */
1089 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1090 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1091 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1092 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1093 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1094 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1095 {DUMMY_STRINGOP_ALGS,
1096 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 1, /* scalar_stmt_cost. */
1100 1, /* scalar load_cost. */
1101 1, /* scalar_store_cost. */
1102 1, /* vec_stmt_cost. */
1103 1, /* vec_to_scalar_cost. */
1104 1, /* scalar_to_vec_cost. */
1105 1, /* vec_align_load_cost. */
1106 2, /* vec_unalign_load_cost. */
1107 1, /* vec_store_cost. */
1108 3, /* cond_taken_branch_cost. */
1109 1, /* cond_not_taken_branch_cost. */
1112 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1114 struct processor_costs generic32_cost = {
1115 COSTS_N_INSNS (1), /* cost of an add instruction */
1116 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1117 COSTS_N_INSNS (1), /* variable shift costs */
1118 COSTS_N_INSNS (1), /* constant shift costs */
1119 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1120 COSTS_N_INSNS (4), /* HI */
1121 COSTS_N_INSNS (3), /* SI */
1122 COSTS_N_INSNS (4), /* DI */
1123 COSTS_N_INSNS (2)}, /* other */
1124 0, /* cost of multiply per each bit set */
1125 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1126 COSTS_N_INSNS (26), /* HI */
1127 COSTS_N_INSNS (42), /* SI */
1128 COSTS_N_INSNS (74), /* DI */
1129 COSTS_N_INSNS (74)}, /* other */
1130 COSTS_N_INSNS (1), /* cost of movsx */
1131 COSTS_N_INSNS (1), /* cost of movzx */
1132 8, /* "large" insn */
1133 17, /* MOVE_RATIO */
1134 4, /* cost for loading QImode using movzbl */
1135 {4, 4, 4}, /* cost of loading integer registers
1136 in QImode, HImode and SImode.
1137 Relative to reg-reg move (2). */
1138 {4, 4, 4}, /* cost of storing integer registers */
1139 4, /* cost of reg,reg fld/fst */
1140 {12, 12, 12}, /* cost of loading fp registers
1141 in SFmode, DFmode and XFmode */
1142 {6, 6, 8}, /* cost of storing fp registers
1143 in SFmode, DFmode and XFmode */
1144 2, /* cost of moving MMX register */
1145 {8, 8}, /* cost of loading MMX registers
1146 in SImode and DImode */
1147 {8, 8}, /* cost of storing MMX registers
1148 in SImode and DImode */
1149 2, /* cost of moving SSE register */
1150 {8, 8, 8}, /* cost of loading SSE registers
1151 in SImode, DImode and TImode */
1152 {8, 8, 8}, /* cost of storing SSE registers
1153 in SImode, DImode and TImode */
1154 5, /* MMX or SSE register to integer */
1155 32, /* size of l1 cache. */
1156 256, /* size of l2 cache. */
1157 64, /* size of prefetch block */
1158 6, /* number of parallel prefetches */
1159 3, /* Branch cost */
1160 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1161 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1162 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1163 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1164 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1165 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1166 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1167 DUMMY_STRINGOP_ALGS},
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 1, /* scalar_stmt_cost. */
1171 1, /* scalar load_cost. */
1172 1, /* scalar_store_cost. */
1173 1, /* vec_stmt_cost. */
1174 1, /* vec_to_scalar_cost. */
1175 1, /* scalar_to_vec_cost. */
1176 1, /* vec_align_load_cost. */
1177 2, /* vec_unalign_load_cost. */
1178 1, /* vec_store_cost. */
1179 3, /* cond_taken_branch_cost. */
1180 1, /* cond_not_taken_branch_cost. */
1183 const struct processor_costs *ix86_cost = &pentium_cost;
1185 /* Processor feature/optimization bitmasks. */
1186 #define m_386 (1<<PROCESSOR_I386)
1187 #define m_486 (1<<PROCESSOR_I486)
1188 #define m_PENT (1<<PROCESSOR_PENTIUM)
1189 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1190 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1191 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1192 #define m_CORE2 (1<<PROCESSOR_CORE2)
1194 #define m_GEODE (1<<PROCESSOR_GEODE)
1195 #define m_K6 (1<<PROCESSOR_K6)
1196 #define m_K6_GEODE (m_K6 | m_GEODE)
1197 #define m_K8 (1<<PROCESSOR_K8)
1198 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1199 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1200 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1201 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1203 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1204 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1206 /* Generic instruction choice should be common subset of supported CPUs
1207 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1208 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1210 /* Feature tests against the various tunings. */
1211 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1212 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1213 negatively, so enabling for Generic64 seems like good code size
1214 tradeoff. We can't enable it for 32bit generic because it does not
1215 work well with PPro base chips. */
1216 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1218 /* X86_TUNE_PUSH_MEMORY */
1219 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1220 | m_NOCONA | m_CORE2 | m_GENERIC,
1222 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1225 /* X86_TUNE_USE_BIT_TEST */
1228 /* X86_TUNE_UNROLL_STRLEN */
1229 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1231 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1232 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1234 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1235 on simulation result. But after P4 was made, no performance benefit
1236 was observed with branch hints. It also increases the code size.
1237 As a result, icc never generates branch hints. */
1240 /* X86_TUNE_DOUBLE_WITH_ADD */
1243 /* X86_TUNE_USE_SAHF */
1244 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1245 | m_NOCONA | m_CORE2 | m_GENERIC,
1247 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1248 partial dependencies. */
1249 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1250 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1252 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1253 register stalls on Generic32 compilation setting as well. However
1254 in current implementation the partial register stalls are not eliminated
1255 very well - they can be introduced via subregs synthesized by combine
1256 and can happen in caller/callee saving sequences. Because this option
1257 pays back little on PPro based chips and is in conflict with partial reg
1258 dependencies used by Athlon/P4 based chips, it is better to leave it off
1259 for generic32 for now. */
1262 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1263 m_CORE2 | m_GENERIC,
1265 /* X86_TUNE_USE_HIMODE_FIOP */
1266 m_386 | m_486 | m_K6_GEODE,
1268 /* X86_TUNE_USE_SIMODE_FIOP */
1269 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1271 /* X86_TUNE_USE_MOV0 */
1274 /* X86_TUNE_USE_CLTD */
1275 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1277 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1280 /* X86_TUNE_SPLIT_LONG_MOVES */
1283 /* X86_TUNE_READ_MODIFY_WRITE */
1286 /* X86_TUNE_READ_MODIFY */
1289 /* X86_TUNE_PROMOTE_QIMODE */
1290 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1291 | m_GENERIC /* | m_PENT4 ? */,
1293 /* X86_TUNE_FAST_PREFIX */
1294 ~(m_PENT | m_486 | m_386),
1296 /* X86_TUNE_SINGLE_STRINGOP */
1297 m_386 | m_PENT4 | m_NOCONA,
1299 /* X86_TUNE_QIMODE_MATH */
1302 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1303 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1304 might be considered for Generic32 if our scheme for avoiding partial
1305 stalls was more effective. */
1308 /* X86_TUNE_PROMOTE_QI_REGS */
1311 /* X86_TUNE_PROMOTE_HI_REGS */
1314 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1315 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1317 /* X86_TUNE_ADD_ESP_8 */
1318 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1319 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1321 /* X86_TUNE_SUB_ESP_4 */
1322 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1324 /* X86_TUNE_SUB_ESP_8 */
1325 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1326 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1328 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1329 for DFmode copies */
1330 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1331 | m_GENERIC | m_GEODE),
1333 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1334 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1336 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1337 conflict here in between PPro/Pentium4 based chips that thread 128bit
1338 SSE registers as single units versus K8 based chips that divide SSE
1339 registers to two 64bit halves. This knob promotes all store destinations
1340 to be 128bit to allow register renaming on 128bit SSE units, but usually
1341 results in one extra microop on 64bit SSE units. Experimental results
1342 shows that disabling this option on P4 brings over 20% SPECfp regression,
1343 while enabling it on K8 brings roughly 2.4% regression that can be partly
1344 masked by careful scheduling of moves. */
1345 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1347 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1350 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1351 are resolved on SSE register parts instead of whole registers, so we may
1352 maintain just lower part of scalar values in proper format leaving the
1353 upper part undefined. */
1356 /* X86_TUNE_SSE_TYPELESS_STORES */
1359 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1360 m_PPRO | m_PENT4 | m_NOCONA,
1362 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1363 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1365 /* X86_TUNE_PROLOGUE_USING_MOVE */
1366 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1368 /* X86_TUNE_EPILOGUE_USING_MOVE */
1369 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1371 /* X86_TUNE_SHIFT1 */
1374 /* X86_TUNE_USE_FFREEP */
1377 /* X86_TUNE_INTER_UNIT_MOVES */
1378 ~(m_AMD_MULTIPLE | m_GENERIC),
1380 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1383 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1384 than 4 branch instructions in the 16 byte window. */
1385 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1387 /* X86_TUNE_SCHEDULE */
1388 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1390 /* X86_TUNE_USE_BT */
1393 /* X86_TUNE_USE_INCDEC */
1394 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1396 /* X86_TUNE_PAD_RETURNS */
1397 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1399 /* X86_TUNE_EXT_80387_CONSTANTS */
1400 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1402 /* X86_TUNE_SHORTEN_X87_SSE */
1405 /* X86_TUNE_AVOID_VECTOR_DECODE */
1408 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1409 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1412 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1413 vector path on AMD machines. */
1414 m_K8 | m_GENERIC64 | m_AMDFAM10,
1416 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1418 m_K8 | m_GENERIC64 | m_AMDFAM10,
1420 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1424 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1425 but one byte longer. */
1428 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1429 operand that cannot be represented using a modRM byte. The XOR
1430 replacement is long decoded, so this split helps here as well. */
1433 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1434 from integer to FP. */
1438 /* Feature tests against the various architecture variations. */
1439 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1440 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1441 ~(m_386 | m_486 | m_PENT | m_K6),
1443 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1446 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1449 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1452 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1456 static const unsigned int x86_accumulate_outgoing_args
1457 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1459 static const unsigned int x86_arch_always_fancy_math_387
1460 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1461 | m_NOCONA | m_CORE2 | m_GENERIC;
1463 static enum stringop_alg stringop_alg = no_stringop;
1465 /* In case the average insn count for single function invocation is
1466 lower than this constant, emit fast (but longer) prologue and
1468 #define FAST_PROLOGUE_INSN_COUNT 20
1470 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1471 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1472 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1473 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1475 /* Array of the smallest class containing reg number REGNO, indexed by
1476 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1478 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1480 /* ax, dx, cx, bx */
1481 AREG, DREG, CREG, BREG,
1482 /* si, di, bp, sp */
1483 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1485 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1486 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1489 /* flags, fpsr, fpcr, frame */
1490 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1492 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1495 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1498 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1499 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1500 /* SSE REX registers */
1501 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1505 /* The "default" register map used in 32bit mode. */
1507 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1509 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1510 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1511 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1512 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1513 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1514 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1515 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1518 static int const x86_64_int_parameter_registers[6] =
1520 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1521 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1524 static int const x86_64_ms_abi_int_parameter_registers[4] =
1526 2 /*RCX*/, 1 /*RDX*/,
1527 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1530 static int const x86_64_int_return_registers[4] =
1532 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1535 /* The "default" register map used in 64bit mode. */
1536 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1538 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1539 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1540 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1541 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1542 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1543 8,9,10,11,12,13,14,15, /* extended integer registers */
1544 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1547 /* Define the register numbers to be used in Dwarf debugging information.
1548 The SVR4 reference port C compiler uses the following register numbers
1549 in its Dwarf output code:
1550 0 for %eax (gcc regno = 0)
1551 1 for %ecx (gcc regno = 2)
1552 2 for %edx (gcc regno = 1)
1553 3 for %ebx (gcc regno = 3)
1554 4 for %esp (gcc regno = 7)
1555 5 for %ebp (gcc regno = 6)
1556 6 for %esi (gcc regno = 4)
1557 7 for %edi (gcc regno = 5)
1558 The following three DWARF register numbers are never generated by
1559 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1560 believes these numbers have these meanings.
1561 8 for %eip (no gcc equivalent)
1562 9 for %eflags (gcc regno = 17)
1563 10 for %trapno (no gcc equivalent)
1564 It is not at all clear how we should number the FP stack registers
1565 for the x86 architecture. If the version of SDB on x86/svr4 were
1566 a bit less brain dead with respect to floating-point then we would
1567 have a precedent to follow with respect to DWARF register numbers
1568 for x86 FP registers, but the SDB on x86/svr4 is so completely
1569 broken with respect to FP registers that it is hardly worth thinking
1570 of it as something to strive for compatibility with.
1571 The version of x86/svr4 SDB I have at the moment does (partially)
1572 seem to believe that DWARF register number 11 is associated with
1573 the x86 register %st(0), but that's about all. Higher DWARF
1574 register numbers don't seem to be associated with anything in
1575 particular, and even for DWARF regno 11, SDB only seems to under-
1576 stand that it should say that a variable lives in %st(0) (when
1577 asked via an `=' command) if we said it was in DWARF regno 11,
1578 but SDB still prints garbage when asked for the value of the
1579 variable in question (via a `/' command).
1580 (Also note that the labels SDB prints for various FP stack regs
1581 when doing an `x' command are all wrong.)
1582 Note that these problems generally don't affect the native SVR4
1583 C compiler because it doesn't allow the use of -O with -g and
1584 because when it is *not* optimizing, it allocates a memory
1585 location for each floating-point variable, and the memory
1586 location is what gets described in the DWARF AT_location
1587 attribute for the variable in question.
1588 Regardless of the severe mental illness of the x86/svr4 SDB, we
1589 do something sensible here and we use the following DWARF
1590 register numbers. Note that these are all stack-top-relative
1592 11 for %st(0) (gcc regno = 8)
1593 12 for %st(1) (gcc regno = 9)
1594 13 for %st(2) (gcc regno = 10)
1595 14 for %st(3) (gcc regno = 11)
1596 15 for %st(4) (gcc regno = 12)
1597 16 for %st(5) (gcc regno = 13)
1598 17 for %st(6) (gcc regno = 14)
1599 18 for %st(7) (gcc regno = 15)
1601 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1603 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1604 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1605 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1606 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1607 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1608 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1609 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1612 /* Test and compare insns in i386.md store the information needed to
1613 generate branch and scc insns here. */
1615 rtx ix86_compare_op0 = NULL_RTX;
1616 rtx ix86_compare_op1 = NULL_RTX;
1617 rtx ix86_compare_emitted = NULL_RTX;
1619 /* Size of the register save area. */
1620 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1622 /* Define the structure for the machine field in struct function. */
1624 struct stack_local_entry GTY(())
1626 unsigned short mode;
1629 struct stack_local_entry *next;
1632 /* Structure describing stack frame layout.
1633 Stack grows downward:
1639 saved frame pointer if frame_pointer_needed
1640 <- HARD_FRAME_POINTER
1645 [va_arg registers] (
1646 > to_allocate <- FRAME_POINTER
1656 HOST_WIDE_INT frame;
1658 int outgoing_arguments_size;
1661 HOST_WIDE_INT to_allocate;
1662 /* The offsets relative to ARG_POINTER. */
1663 HOST_WIDE_INT frame_pointer_offset;
1664 HOST_WIDE_INT hard_frame_pointer_offset;
1665 HOST_WIDE_INT stack_pointer_offset;
1667 /* When save_regs_using_mov is set, emit prologue using
1668 move instead of push instructions. */
1669 bool save_regs_using_mov;
1672 /* Code model option. */
1673 enum cmodel ix86_cmodel;
1675 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1677 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1679 /* Which unit we are generating floating point math for. */
1680 enum fpmath_unit ix86_fpmath;
1682 /* Which cpu are we scheduling for. */
1683 enum processor_type ix86_tune;
1685 /* Which instruction set architecture to use. */
1686 enum processor_type ix86_arch;
1688 /* true if sse prefetch instruction is not NOOP. */
1689 int x86_prefetch_sse;
1691 /* ix86_regparm_string as a number */
1692 static int ix86_regparm;
1694 /* -mstackrealign option */
1695 extern int ix86_force_align_arg_pointer;
1696 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1698 /* Preferred alignment for stack boundary in bits. */
1699 unsigned int ix86_preferred_stack_boundary;
1701 /* Values 1-5: see jump.c */
1702 int ix86_branch_cost;
1704 /* Variables which are this size or smaller are put in the data/bss
1705 or ldata/lbss sections. */
1707 int ix86_section_threshold = 65536;
1709 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1710 char internal_label_prefix[16];
1711 int internal_label_prefix_len;
1713 /* Fence to use after loop using movnt. */
1716 /* Register class used for passing given 64bit part of the argument.
1717 These represent classes as documented by the PS ABI, with the exception
1718 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1719 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1721 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1722 whenever possible (upper half does contain padding). */
1723 enum x86_64_reg_class
1726 X86_64_INTEGER_CLASS,
1727 X86_64_INTEGERSI_CLASS,
1734 X86_64_COMPLEX_X87_CLASS,
1737 static const char * const x86_64_reg_class_name[] =
1739 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1740 "sseup", "x87", "x87up", "cplx87", "no"
1743 #define MAX_CLASSES 4
1745 /* Table of constants used by fldpi, fldln2, etc.... */
1746 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1747 static bool ext_80387_constants_init = 0;
1750 static struct machine_function * ix86_init_machine_status (void);
1751 static rtx ix86_function_value (const_tree, const_tree, bool);
1752 static int ix86_function_regparm (const_tree, const_tree);
1753 static void ix86_compute_frame_layout (struct ix86_frame *);
1754 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1758 /* The svr4 ABI for the i386 says that records and unions are returned
1760 #ifndef DEFAULT_PCC_STRUCT_RETURN
1761 #define DEFAULT_PCC_STRUCT_RETURN 1
1764 /* Bit flags that specify the ISA we are compiling for. */
1765 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1767 /* A mask of ix86_isa_flags that includes bit X if X
1768 was set or cleared on the command line. */
1769 static int ix86_isa_flags_explicit;
1771 /* Define a set of ISAs which are available when a given ISA is
1772 enabled. MMX and SSE ISAs are handled separately. */
1774 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1775 #define OPTION_MASK_ISA_3DNOW_SET \
1776 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1778 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1779 #define OPTION_MASK_ISA_SSE2_SET \
1780 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1781 #define OPTION_MASK_ISA_SSE3_SET \
1782 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1783 #define OPTION_MASK_ISA_SSSE3_SET \
1784 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1785 #define OPTION_MASK_ISA_SSE4_1_SET \
1786 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1787 #define OPTION_MASK_ISA_SSE4_2_SET \
1788 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1790 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1792 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1794 #define OPTION_MASK_ISA_SSE4A_SET \
1795 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1796 #define OPTION_MASK_ISA_SSE5_SET \
1797 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1799 /* Define a set of ISAs which aren't available when a given ISA is
1800 disabled. MMX and SSE ISAs are handled separately. */
1802 #define OPTION_MASK_ISA_MMX_UNSET \
1803 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1804 #define OPTION_MASK_ISA_3DNOW_UNSET \
1805 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1806 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1808 #define OPTION_MASK_ISA_SSE_UNSET \
1809 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1810 #define OPTION_MASK_ISA_SSE2_UNSET \
1811 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1812 #define OPTION_MASK_ISA_SSE3_UNSET \
1813 (OPTION_MASK_ISA_SSE3 \
1814 | OPTION_MASK_ISA_SSSE3_UNSET \
1815 | OPTION_MASK_ISA_SSE4A_UNSET )
1816 #define OPTION_MASK_ISA_SSSE3_UNSET \
1817 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1818 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1819 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1820 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1822 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1824 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1826 #define OPTION_MASK_ISA_SSE4A_UNSET \
1827 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1829 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1831 /* Vectorization library interface and handlers. */
1832 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1833 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1835 /* Implement TARGET_HANDLE_OPTION. */
1838 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1845 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1846 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1850 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1851 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1858 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1859 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1863 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1864 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1874 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
1875 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
1879 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1880 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1887 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
1888 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
1892 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1893 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1900 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
1901 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
1905 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1906 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1913 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
1914 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
1918 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1919 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1926 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
1927 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
1931 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1932 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1939 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
1940 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
1944 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1945 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1950 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1951 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1955 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1956 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1962 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1963 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1967 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1968 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1975 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
1976 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
1980 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
1981 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
1990 /* Sometimes certain combinations of command options do not make
1991 sense on a particular target machine. You can define a macro
1992 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1993 defined, is executed once just after all the command options have
1996 Don't use this macro to turn on various extra optimizations for
1997 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2000 override_options (void)
2003 int ix86_tune_defaulted = 0;
2004 int ix86_arch_specified = 0;
2005 unsigned int ix86_arch_mask, ix86_tune_mask;
2007 /* Comes from final.c -- no real reason to change it. */
2008 #define MAX_CODE_ALIGN 16
2012 const struct processor_costs *cost; /* Processor costs */
2013 const int align_loop; /* Default alignments. */
2014 const int align_loop_max_skip;
2015 const int align_jump;
2016 const int align_jump_max_skip;
2017 const int align_func;
2019 const processor_target_table[PROCESSOR_max] =
2021 {&i386_cost, 4, 3, 4, 3, 4},
2022 {&i486_cost, 16, 15, 16, 15, 16},
2023 {&pentium_cost, 16, 7, 16, 7, 16},
2024 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2025 {&geode_cost, 0, 0, 0, 0, 0},
2026 {&k6_cost, 32, 7, 32, 7, 32},
2027 {&athlon_cost, 16, 7, 16, 7, 16},
2028 {&pentium4_cost, 0, 0, 0, 0, 0},
2029 {&k8_cost, 16, 7, 16, 7, 16},
2030 {&nocona_cost, 0, 0, 0, 0, 0},
2031 {&core2_cost, 16, 10, 16, 10, 16},
2032 {&generic32_cost, 16, 7, 16, 7, 16},
2033 {&generic64_cost, 16, 10, 16, 10, 16},
2034 {&amdfam10_cost, 32, 24, 32, 7, 32}
2037 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2068 PTA_PREFETCH_SSE = 1 << 4,
2070 PTA_3DNOW_A = 1 << 6,
2074 PTA_POPCNT = 1 << 10,
2076 PTA_SSE4A = 1 << 12,
2077 PTA_NO_SAHF = 1 << 13,
2078 PTA_SSE4_1 = 1 << 14,
2079 PTA_SSE4_2 = 1 << 15,
2085 const char *const name; /* processor name or nickname. */
2086 const enum processor_type processor;
2087 const unsigned /*enum pta_flags*/ flags;
2089 const processor_alias_table[] =
2091 {"i386", PROCESSOR_I386, 0},
2092 {"i486", PROCESSOR_I486, 0},
2093 {"i586", PROCESSOR_PENTIUM, 0},
2094 {"pentium", PROCESSOR_PENTIUM, 0},
2095 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2096 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2097 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2098 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2099 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2100 {"i686", PROCESSOR_PENTIUMPRO, 0},
2101 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2102 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2103 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2104 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2105 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2106 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2107 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2108 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2109 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2110 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2111 | PTA_CX16 | PTA_NO_SAHF)},
2112 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2113 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2116 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2117 |PTA_PREFETCH_SSE)},
2118 {"k6", PROCESSOR_K6, PTA_MMX},
2119 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2120 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2121 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2122 | PTA_PREFETCH_SSE)},
2123 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2124 | PTA_PREFETCH_SSE)},
2125 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2127 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2129 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2131 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2132 | PTA_MMX | PTA_SSE | PTA_SSE2
2134 {"k8", PROCESSOR_K8, (PTA_64BIT
2135 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2136 | PTA_SSE | PTA_SSE2
2138 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2139 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2140 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2142 {"opteron", PROCESSOR_K8, (PTA_64BIT
2143 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2144 | PTA_SSE | PTA_SSE2
2146 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2147 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2148 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2150 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2151 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2152 | PTA_SSE | PTA_SSE2
2154 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2155 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2156 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2158 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2159 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2160 | PTA_SSE | PTA_SSE2
2162 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2163 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2164 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2166 | PTA_CX16 | PTA_ABM)},
2167 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2168 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2169 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2171 | PTA_CX16 | PTA_ABM)},
2172 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2173 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2176 int const pta_size = ARRAY_SIZE (processor_alias_table);
2178 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2179 SUBTARGET_OVERRIDE_OPTIONS;
2182 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2183 SUBSUBTARGET_OVERRIDE_OPTIONS;
2186 /* -fPIC is the default for x86_64. */
2187 if (TARGET_MACHO && TARGET_64BIT)
2190 /* Set the default values for switches whose default depends on TARGET_64BIT
2191 in case they weren't overwritten by command line options. */
2194 /* Mach-O doesn't support omitting the frame pointer for now. */
2195 if (flag_omit_frame_pointer == 2)
2196 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2197 if (flag_asynchronous_unwind_tables == 2)
2198 flag_asynchronous_unwind_tables = 1;
2199 if (flag_pcc_struct_return == 2)
2200 flag_pcc_struct_return = 0;
2204 if (flag_omit_frame_pointer == 2)
2205 flag_omit_frame_pointer = 0;
2206 if (flag_asynchronous_unwind_tables == 2)
2207 flag_asynchronous_unwind_tables = 0;
2208 if (flag_pcc_struct_return == 2)
2209 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2212 /* Need to check -mtune=generic first. */
2213 if (ix86_tune_string)
2215 if (!strcmp (ix86_tune_string, "generic")
2216 || !strcmp (ix86_tune_string, "i686")
2217 /* As special support for cross compilers we read -mtune=native
2218 as -mtune=generic. With native compilers we won't see the
2219 -mtune=native, as it was changed by the driver. */
2220 || !strcmp (ix86_tune_string, "native"))
2223 ix86_tune_string = "generic64";
2225 ix86_tune_string = "generic32";
2227 else if (!strncmp (ix86_tune_string, "generic", 7))
2228 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2232 if (ix86_arch_string)
2233 ix86_tune_string = ix86_arch_string;
2234 if (!ix86_tune_string)
2236 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2237 ix86_tune_defaulted = 1;
2240 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2241 need to use a sensible tune option. */
2242 if (!strcmp (ix86_tune_string, "generic")
2243 || !strcmp (ix86_tune_string, "x86-64")
2244 || !strcmp (ix86_tune_string, "i686"))
2247 ix86_tune_string = "generic64";
2249 ix86_tune_string = "generic32";
2252 if (ix86_stringop_string)
2254 if (!strcmp (ix86_stringop_string, "rep_byte"))
2255 stringop_alg = rep_prefix_1_byte;
2256 else if (!strcmp (ix86_stringop_string, "libcall"))
2257 stringop_alg = libcall;
2258 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2259 stringop_alg = rep_prefix_4_byte;
2260 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2261 stringop_alg = rep_prefix_8_byte;
2262 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2263 stringop_alg = loop_1_byte;
2264 else if (!strcmp (ix86_stringop_string, "loop"))
2265 stringop_alg = loop;
2266 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2267 stringop_alg = unrolled_loop;
2269 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2271 if (!strcmp (ix86_tune_string, "x86-64"))
2272 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2273 "-mtune=generic instead as appropriate.");
2275 if (!ix86_arch_string)
2276 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2278 ix86_arch_specified = 1;
2280 if (!strcmp (ix86_arch_string, "generic"))
2281 error ("generic CPU can be used only for -mtune= switch");
2282 if (!strncmp (ix86_arch_string, "generic", 7))
2283 error ("bad value (%s) for -march= switch", ix86_arch_string);
2285 if (ix86_cmodel_string != 0)
2287 if (!strcmp (ix86_cmodel_string, "small"))
2288 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2289 else if (!strcmp (ix86_cmodel_string, "medium"))
2290 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2291 else if (!strcmp (ix86_cmodel_string, "large"))
2292 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2294 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2295 else if (!strcmp (ix86_cmodel_string, "32"))
2296 ix86_cmodel = CM_32;
2297 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2298 ix86_cmodel = CM_KERNEL;
2300 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2304 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
2305 use of rip-relative addressing. This eliminates fixups that
2306 would otherwise be needed if this object is to be placed in a
2307 DLL, and is essentially just as efficient as direct addressing. */
2308 if (TARGET_64BIT_MS_ABI)
2309 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2310 else if (TARGET_64BIT)
2311 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2313 ix86_cmodel = CM_32;
2315 if (ix86_asm_string != 0)
2318 && !strcmp (ix86_asm_string, "intel"))
2319 ix86_asm_dialect = ASM_INTEL;
2320 else if (!strcmp (ix86_asm_string, "att"))
2321 ix86_asm_dialect = ASM_ATT;
2323 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2325 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2326 error ("code model %qs not supported in the %s bit mode",
2327 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2328 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2329 sorry ("%i-bit mode not compiled in",
2330 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2332 for (i = 0; i < pta_size; i++)
2333 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2335 ix86_arch = processor_alias_table[i].processor;
2336 /* Default cpu tuning to the architecture. */
2337 ix86_tune = ix86_arch;
2339 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2340 error ("CPU you selected does not support x86-64 "
2343 if (processor_alias_table[i].flags & PTA_MMX
2344 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2345 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2346 if (processor_alias_table[i].flags & PTA_3DNOW
2347 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2348 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2349 if (processor_alias_table[i].flags & PTA_3DNOW_A
2350 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2351 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2352 if (processor_alias_table[i].flags & PTA_SSE
2353 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2354 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2355 if (processor_alias_table[i].flags & PTA_SSE2
2356 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2357 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2358 if (processor_alias_table[i].flags & PTA_SSE3
2359 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2360 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2361 if (processor_alias_table[i].flags & PTA_SSSE3
2362 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2363 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2364 if (processor_alias_table[i].flags & PTA_SSE4_1
2365 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2366 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2367 if (processor_alias_table[i].flags & PTA_SSE4_2
2368 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2369 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2370 if (processor_alias_table[i].flags & PTA_SSE4A
2371 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2372 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2373 if (processor_alias_table[i].flags & PTA_SSE5
2374 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2375 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2377 if (processor_alias_table[i].flags & PTA_ABM)
2379 if (processor_alias_table[i].flags & PTA_CX16)
2380 x86_cmpxchg16b = true;
2381 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2383 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2384 x86_prefetch_sse = true;
2385 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
2392 error ("bad value (%s) for -march= switch", ix86_arch_string);
2394 ix86_arch_mask = 1u << ix86_arch;
2395 for (i = 0; i < X86_ARCH_LAST; ++i)
2396 ix86_arch_features[i] &= ix86_arch_mask;
2398 for (i = 0; i < pta_size; i++)
2399 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2401 ix86_tune = processor_alias_table[i].processor;
2402 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2404 if (ix86_tune_defaulted)
2406 ix86_tune_string = "x86-64";
2407 for (i = 0; i < pta_size; i++)
2408 if (! strcmp (ix86_tune_string,
2409 processor_alias_table[i].name))
2411 ix86_tune = processor_alias_table[i].processor;
2414 error ("CPU you selected does not support x86-64 "
2417 /* Intel CPUs have always interpreted SSE prefetch instructions as
2418 NOPs; so, we can enable SSE prefetch instructions even when
2419 -mtune (rather than -march) points us to a processor that has them.
2420 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2421 higher processors. */
2423 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2424 x86_prefetch_sse = true;
2428 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2430 ix86_tune_mask = 1u << ix86_tune;
2431 for (i = 0; i < X86_TUNE_LAST; ++i)
2432 ix86_tune_features[i] &= ix86_tune_mask;
2435 ix86_cost = &size_cost;
2437 ix86_cost = processor_target_table[ix86_tune].cost;
2439 /* Arrange to set up i386_stack_locals for all functions. */
2440 init_machine_status = ix86_init_machine_status;
2442 /* Validate -mregparm= value. */
2443 if (ix86_regparm_string)
2446 warning (0, "-mregparm is ignored in 64-bit mode");
2447 i = atoi (ix86_regparm_string);
2448 if (i < 0 || i > REGPARM_MAX)
2449 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2454 ix86_regparm = REGPARM_MAX;
2456 /* If the user has provided any of the -malign-* options,
2457 warn and use that value only if -falign-* is not set.
2458 Remove this code in GCC 3.2 or later. */
2459 if (ix86_align_loops_string)
2461 warning (0, "-malign-loops is obsolete, use -falign-loops");
2462 if (align_loops == 0)
2464 i = atoi (ix86_align_loops_string);
2465 if (i < 0 || i > MAX_CODE_ALIGN)
2466 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2468 align_loops = 1 << i;
2472 if (ix86_align_jumps_string)
2474 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2475 if (align_jumps == 0)
2477 i = atoi (ix86_align_jumps_string);
2478 if (i < 0 || i > MAX_CODE_ALIGN)
2479 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2481 align_jumps = 1 << i;
2485 if (ix86_align_funcs_string)
2487 warning (0, "-malign-functions is obsolete, use -falign-functions");
2488 if (align_functions == 0)
2490 i = atoi (ix86_align_funcs_string);
2491 if (i < 0 || i > MAX_CODE_ALIGN)
2492 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2494 align_functions = 1 << i;
2498 /* Default align_* from the processor table. */
2499 if (align_loops == 0)
2501 align_loops = processor_target_table[ix86_tune].align_loop;
2502 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2504 if (align_jumps == 0)
2506 align_jumps = processor_target_table[ix86_tune].align_jump;
2507 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2509 if (align_functions == 0)
2511 align_functions = processor_target_table[ix86_tune].align_func;
2514 /* Validate -mbranch-cost= value, or provide default. */
2515 ix86_branch_cost = ix86_cost->branch_cost;
2516 if (ix86_branch_cost_string)
2518 i = atoi (ix86_branch_cost_string);
2520 error ("-mbranch-cost=%d is not between 0 and 5", i);
2522 ix86_branch_cost = i;
2524 if (ix86_section_threshold_string)
2526 i = atoi (ix86_section_threshold_string);
2528 error ("-mlarge-data-threshold=%d is negative", i);
2530 ix86_section_threshold = i;
2533 if (ix86_tls_dialect_string)
2535 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2536 ix86_tls_dialect = TLS_DIALECT_GNU;
2537 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2538 ix86_tls_dialect = TLS_DIALECT_GNU2;
2539 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2540 ix86_tls_dialect = TLS_DIALECT_SUN;
2542 error ("bad value (%s) for -mtls-dialect= switch",
2543 ix86_tls_dialect_string);
2546 if (ix87_precision_string)
2548 i = atoi (ix87_precision_string);
2549 if (i != 32 && i != 64 && i != 80)
2550 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2555 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2557 /* Enable by default the SSE and MMX builtins. Do allow the user to
2558 explicitly disable any of these. In particular, disabling SSE and
2559 MMX for kernel code is extremely useful. */
2560 if (!ix86_arch_specified)
2562 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2563 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2566 warning (0, "-mrtd is ignored in 64bit mode");
2570 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2572 if (!ix86_arch_specified)
2574 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2576 /* i386 ABI does not specify red zone. It still makes sense to use it
2577 when programmer takes care to stack from being destroyed. */
2578 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2579 target_flags |= MASK_NO_RED_ZONE;
2582 /* Keep nonleaf frame pointers. */
2583 if (flag_omit_frame_pointer)
2584 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2585 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2586 flag_omit_frame_pointer = 1;
2588 /* If we're doing fast math, we don't care about comparison order
2589 wrt NaNs. This lets us use a shorter comparison sequence. */
2590 if (flag_finite_math_only)
2591 target_flags &= ~MASK_IEEE_FP;
2593 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2594 since the insns won't need emulation. */
2595 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2596 target_flags &= ~MASK_NO_FANCY_MATH_387;
2598 /* Likewise, if the target doesn't have a 387, or we've specified
2599 software floating point, don't use 387 inline intrinsics. */
2601 target_flags |= MASK_NO_FANCY_MATH_387;
2603 /* Turn on MMX builtins for -msse. */
2606 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2607 x86_prefetch_sse = true;
2610 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2611 if (TARGET_SSE4_2 || TARGET_ABM)
2614 /* Validate -mpreferred-stack-boundary= value, or provide default.
2615 The default of 128 bits is for Pentium III's SSE __m128. We can't
2616 change it because of optimize_size. Otherwise, we can't mix object
2617 files compiled with -Os and -On. */
2618 ix86_preferred_stack_boundary = 128;
2619 if (ix86_preferred_stack_boundary_string)
2621 i = atoi (ix86_preferred_stack_boundary_string);
2622 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2623 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2624 TARGET_64BIT ? 4 : 2);
2626 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2629 /* Accept -msseregparm only if at least SSE support is enabled. */
2630 if (TARGET_SSEREGPARM
2632 error ("-msseregparm used without SSE enabled");
2634 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2635 if (ix86_fpmath_string != 0)
2637 if (! strcmp (ix86_fpmath_string, "387"))
2638 ix86_fpmath = FPMATH_387;
2639 else if (! strcmp (ix86_fpmath_string, "sse"))
2643 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2644 ix86_fpmath = FPMATH_387;
2647 ix86_fpmath = FPMATH_SSE;
2649 else if (! strcmp (ix86_fpmath_string, "387,sse")
2650 || ! strcmp (ix86_fpmath_string, "sse,387"))
2654 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2655 ix86_fpmath = FPMATH_387;
2657 else if (!TARGET_80387)
2659 warning (0, "387 instruction set disabled, using SSE arithmetics");
2660 ix86_fpmath = FPMATH_SSE;
2663 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2666 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2669 /* If the i387 is disabled, then do not return values in it. */
2671 target_flags &= ~MASK_FLOAT_RETURNS;
2673 /* Use external vectorized library in vectorizing intrinsics. */
2674 if (ix86_veclibabi_string)
2676 if (strcmp (ix86_veclibabi_string, "acml") == 0)
2677 ix86_veclib_handler = ix86_veclibabi_acml;
2679 error ("unknown vectorization library ABI type (%s) for "
2680 "-mveclibabi= switch", ix86_veclibabi_string);
2683 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2684 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2686 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2688 /* ??? Unwind info is not correct around the CFG unless either a frame
2689 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2690 unwind info generation to be aware of the CFG and propagating states
2692 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2693 || flag_exceptions || flag_non_call_exceptions)
2694 && flag_omit_frame_pointer
2695 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2697 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2698 warning (0, "unwind tables currently require either a frame pointer "
2699 "or -maccumulate-outgoing-args for correctness");
2700 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2703 /* If stack probes are required, the space used for large function
2704 arguments on the stack must also be probed, so enable
2705 -maccumulate-outgoing-args so this happens in the prologue. */
2706 if (TARGET_STACK_PROBE
2707 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2709 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2710 warning (0, "stack probing requires -maccumulate-outgoing-args "
2712 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2715 /* For sane SSE instruction set generation we need fcomi instruction.
2716 It is safe to enable all CMOVE instructions. */
2720 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2723 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2724 p = strchr (internal_label_prefix, 'X');
2725 internal_label_prefix_len = p - internal_label_prefix;
2729 /* When scheduling description is not available, disable scheduler pass
2730 so it won't slow down the compilation and make x87 code slower. */
2731 if (!TARGET_SCHEDULE)
2732 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2734 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2735 set_param_value ("simultaneous-prefetches",
2736 ix86_cost->simultaneous_prefetches);
2737 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2738 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2739 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
2740 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
2741 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
2742 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
2744 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
2745 can be optimized to ap = __builtin_next_arg (0). */
2746 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
2747 targetm.expand_builtin_va_start = NULL;
2750 /* Return true if this goes in large data/bss. */
2753 ix86_in_large_data_p (tree exp)
2755 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2758 /* Functions are never large data. */
2759 if (TREE_CODE (exp) == FUNCTION_DECL)
2762 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2764 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2765 if (strcmp (section, ".ldata") == 0
2766 || strcmp (section, ".lbss") == 0)
2772 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2774 /* If this is an incomplete type with size 0, then we can't put it
2775 in data because it might be too big when completed. */
2776 if (!size || size > ix86_section_threshold)
2783 /* Switch to the appropriate section for output of DECL.
2784 DECL is either a `VAR_DECL' node or a constant of some sort.
2785 RELOC indicates whether forming the initial value of DECL requires
2786 link-time relocations. */
2788 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2792 x86_64_elf_select_section (tree decl, int reloc,
2793 unsigned HOST_WIDE_INT align)
2795 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2796 && ix86_in_large_data_p (decl))
2798 const char *sname = NULL;
2799 unsigned int flags = SECTION_WRITE;
2800 switch (categorize_decl_for_section (decl, reloc))
2805 case SECCAT_DATA_REL:
2806 sname = ".ldata.rel";
2808 case SECCAT_DATA_REL_LOCAL:
2809 sname = ".ldata.rel.local";
2811 case SECCAT_DATA_REL_RO:
2812 sname = ".ldata.rel.ro";
2814 case SECCAT_DATA_REL_RO_LOCAL:
2815 sname = ".ldata.rel.ro.local";
2819 flags |= SECTION_BSS;
2822 case SECCAT_RODATA_MERGE_STR:
2823 case SECCAT_RODATA_MERGE_STR_INIT:
2824 case SECCAT_RODATA_MERGE_CONST:
2828 case SECCAT_SRODATA:
2835 /* We don't split these for medium model. Place them into
2836 default sections and hope for best. */
2841 /* We might get called with string constants, but get_named_section
2842 doesn't like them as they are not DECLs. Also, we need to set
2843 flags in that case. */
2845 return get_section (sname, flags, NULL);
2846 return get_named_section (decl, sname, reloc);
2849 return default_elf_select_section (decl, reloc, align);
2852 /* Build up a unique section name, expressed as a
2853 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2854 RELOC indicates whether the initial value of EXP requires
2855 link-time relocations. */
2857 static void ATTRIBUTE_UNUSED
2858 x86_64_elf_unique_section (tree decl, int reloc)
2860 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2861 && ix86_in_large_data_p (decl))
2863 const char *prefix = NULL;
2864 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2865 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2867 switch (categorize_decl_for_section (decl, reloc))
2870 case SECCAT_DATA_REL:
2871 case SECCAT_DATA_REL_LOCAL:
2872 case SECCAT_DATA_REL_RO:
2873 case SECCAT_DATA_REL_RO_LOCAL:
2874 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2877 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2880 case SECCAT_RODATA_MERGE_STR:
2881 case SECCAT_RODATA_MERGE_STR_INIT:
2882 case SECCAT_RODATA_MERGE_CONST:
2883 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2885 case SECCAT_SRODATA:
2892 /* We don't split these for medium model. Place them into
2893 default sections and hope for best. */
2901 plen = strlen (prefix);
2903 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2904 name = targetm.strip_name_encoding (name);
2905 nlen = strlen (name);
2907 string = (char *) alloca (nlen + plen + 1);
2908 memcpy (string, prefix, plen);
2909 memcpy (string + plen, name, nlen + 1);
2911 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2915 default_unique_section (decl, reloc);
2918 #ifdef COMMON_ASM_OP
2919 /* This says how to output assembler code to declare an
2920 uninitialized external linkage data object.
2922 For medium model x86-64 we need to use .largecomm opcode for
2925 x86_elf_aligned_common (FILE *file,
2926 const char *name, unsigned HOST_WIDE_INT size,
2929 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2930 && size > (unsigned int)ix86_section_threshold)
2931 fprintf (file, ".largecomm\t");
2933 fprintf (file, "%s", COMMON_ASM_OP);
2934 assemble_name (file, name);
2935 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2936 size, align / BITS_PER_UNIT);
2940 /* Utility function for targets to use in implementing
2941 ASM_OUTPUT_ALIGNED_BSS. */
2944 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2945 const char *name, unsigned HOST_WIDE_INT size,
2948 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2949 && size > (unsigned int)ix86_section_threshold)
2950 switch_to_section (get_named_section (decl, ".lbss", 0));
2952 switch_to_section (bss_section);
2953 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2954 #ifdef ASM_DECLARE_OBJECT_NAME
2955 last_assemble_variable_decl = decl;
2956 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2958 /* Standard thing is just output label for the object. */
2959 ASM_OUTPUT_LABEL (file, name);
2960 #endif /* ASM_DECLARE_OBJECT_NAME */
2961 ASM_OUTPUT_SKIP (file, size ? size : 1);
2965 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2967 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2968 make the problem with not enough registers even worse. */
2969 #ifdef INSN_SCHEDULING
2971 flag_schedule_insns = 0;
2975 /* The Darwin libraries never set errno, so we might as well
2976 avoid calling them when that's the only reason we would. */
2977 flag_errno_math = 0;
2979 /* The default values of these switches depend on the TARGET_64BIT
2980 that is not known at this moment. Mark these values with 2 and
2981 let user the to override these. In case there is no command line option
2982 specifying them, we will set the defaults in override_options. */
2984 flag_omit_frame_pointer = 2;
2985 flag_pcc_struct_return = 2;
2986 flag_asynchronous_unwind_tables = 2;
2987 flag_vect_cost_model = 1;
2988 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2989 SUBTARGET_OPTIMIZATION_OPTIONS;
2993 /* Decide whether we can make a sibling call to a function. DECL is the
2994 declaration of the function being targeted by the call and EXP is the
2995 CALL_EXPR representing the call. */
2998 ix86_function_ok_for_sibcall (tree decl, tree exp)
3003 /* If we are generating position-independent code, we cannot sibcall
3004 optimize any indirect call, or a direct call to a global function,
3005 as the PLT requires %ebx be live. */
3006 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
3013 func = TREE_TYPE (CALL_EXPR_FN (exp));
3014 if (POINTER_TYPE_P (func))
3015 func = TREE_TYPE (func);
3018 /* Check that the return value locations are the same. Like
3019 if we are returning floats on the 80387 register stack, we cannot
3020 make a sibcall from a function that doesn't return a float to a
3021 function that does or, conversely, from a function that does return
3022 a float to a function that doesn't; the necessary stack adjustment
3023 would not be executed. This is also the place we notice
3024 differences in the return value ABI. Note that it is ok for one
3025 of the functions to have void return type as long as the return
3026 value of the other is passed in a register. */
3027 a = ix86_function_value (TREE_TYPE (exp), func, false);
3028 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
3030 if (STACK_REG_P (a) || STACK_REG_P (b))
3032 if (!rtx_equal_p (a, b))
3035 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
3037 else if (!rtx_equal_p (a, b))
3040 /* If this call is indirect, we'll need to be able to use a call-clobbered
3041 register for the address of the target function. Make sure that all
3042 such registers are not used for passing parameters. */
3043 if (!decl && !TARGET_64BIT)
3047 /* We're looking at the CALL_EXPR, we need the type of the function. */
3048 type = CALL_EXPR_FN (exp); /* pointer expression */
3049 type = TREE_TYPE (type); /* pointer type */
3050 type = TREE_TYPE (type); /* function type */
3052 if (ix86_function_regparm (type, NULL) >= 3)
3054 /* ??? Need to count the actual number of registers to be used,
3055 not the possible number of registers. Fix later. */
3060 /* Dllimport'd functions are also called indirectly. */
3061 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
3062 && decl && DECL_DLLIMPORT_P (decl)
3063 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
3066 /* If we forced aligned the stack, then sibcalling would unalign the
3067 stack, which may break the called function. */
3068 if (cfun->machine->force_align_arg_pointer)
3071 /* Otherwise okay. That also includes certain types of indirect calls. */
3075 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
3076 calling convention attributes;
3077 arguments as in struct attribute_spec.handler. */
3080 ix86_handle_cconv_attribute (tree *node, tree name,
3082 int flags ATTRIBUTE_UNUSED,
3085 if (TREE_CODE (*node) != FUNCTION_TYPE
3086 && TREE_CODE (*node) != METHOD_TYPE
3087 && TREE_CODE (*node) != FIELD_DECL
3088 && TREE_CODE (*node) != TYPE_DECL)
3090 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3091 IDENTIFIER_POINTER (name));
3092 *no_add_attrs = true;
3096 /* Can combine regparm with all attributes but fastcall. */
3097 if (is_attribute_p ("regparm", name))
3101 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3103 error ("fastcall and regparm attributes are not compatible");
3106 cst = TREE_VALUE (args);
3107 if (TREE_CODE (cst) != INTEGER_CST)
3109 warning (OPT_Wattributes,
3110 "%qs attribute requires an integer constant argument",
3111 IDENTIFIER_POINTER (name));
3112 *no_add_attrs = true;
3114 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
3116 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
3117 IDENTIFIER_POINTER (name), REGPARM_MAX);
3118 *no_add_attrs = true;
3122 && lookup_attribute (ix86_force_align_arg_pointer_string,
3123 TYPE_ATTRIBUTES (*node))
3124 && compare_tree_int (cst, REGPARM_MAX-1))
3126 error ("%s functions limited to %d register parameters",
3127 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
3135 /* Do not warn when emulating the MS ABI. */
3136 if (!TARGET_64BIT_MS_ABI)
3137 warning (OPT_Wattributes, "%qs attribute ignored",
3138 IDENTIFIER_POINTER (name));
3139 *no_add_attrs = true;
3143 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
3144 if (is_attribute_p ("fastcall", name))
3146 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3148 error ("fastcall and cdecl attributes are not compatible");
3150 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3152 error ("fastcall and stdcall attributes are not compatible");
3154 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
3156 error ("fastcall and regparm attributes are not compatible");
3160 /* Can combine stdcall with fastcall (redundant), regparm and
3162 else if (is_attribute_p ("stdcall", name))
3164 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3166 error ("stdcall and cdecl attributes are not compatible");
3168 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3170 error ("stdcall and fastcall attributes are not compatible");
3174 /* Can combine cdecl with regparm and sseregparm. */
3175 else if (is_attribute_p ("cdecl", name))
3177 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3179 error ("stdcall and cdecl attributes are not compatible");
3181 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3183 error ("fastcall and cdecl attributes are not compatible");
3187 /* Can combine sseregparm with all attributes. */
3192 /* Return 0 if the attributes for two types are incompatible, 1 if they
3193 are compatible, and 2 if they are nearly compatible (which causes a
3194 warning to be generated). */
3197 ix86_comp_type_attributes (const_tree type1, const_tree type2)
3199 /* Check for mismatch of non-default calling convention. */
3200 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
3202 if (TREE_CODE (type1) != FUNCTION_TYPE
3203 && TREE_CODE (type1) != METHOD_TYPE)
3206 /* Check for mismatched fastcall/regparm types. */
3207 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
3208 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
3209 || (ix86_function_regparm (type1, NULL)
3210 != ix86_function_regparm (type2, NULL)))
3213 /* Check for mismatched sseregparm types. */
3214 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
3215 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
3218 /* Check for mismatched return types (cdecl vs stdcall). */
3219 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
3220 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
3226 /* Return the regparm value for a function with the indicated TYPE and DECL.
3227 DECL may be NULL when calling function indirectly
3228 or considering a libcall. */
3231 ix86_function_regparm (const_tree type, const_tree decl)
3234 int regparm = ix86_regparm;
3239 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
3241 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
3243 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
3246 /* Use register calling convention for local functions when possible. */
3247 if (decl && TREE_CODE (decl) == FUNCTION_DECL
3248 && flag_unit_at_a_time && !profile_flag)
3250 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3251 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3254 int local_regparm, globals = 0, regno;
3257 /* Make sure no regparm register is taken by a
3258 fixed register variable. */
3259 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
3260 if (fixed_regs[local_regparm])
3263 /* We can't use regparm(3) for nested functions as these use
3264 static chain pointer in third argument. */
3265 if (local_regparm == 3
3266 && (decl_function_context (decl)
3267 || ix86_force_align_arg_pointer)
3268 && !DECL_NO_STATIC_CHAIN (decl))
3271 /* If the function realigns its stackpointer, the prologue will
3272 clobber %ecx. If we've already generated code for the callee,
3273 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
3274 scanning the attributes for the self-realigning property. */
3275 f = DECL_STRUCT_FUNCTION (decl);
3276 if (local_regparm == 3
3277 && (f ? !!f->machine->force_align_arg_pointer
3278 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
3279 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
3282 /* Each fixed register usage increases register pressure,
3283 so less registers should be used for argument passing.
3284 This functionality can be overriden by an explicit
3286 for (regno = 0; regno <= DI_REG; regno++)
3287 if (fixed_regs[regno])
3291 = globals < local_regparm ? local_regparm - globals : 0;
3293 if (local_regparm > regparm)
3294 regparm = local_regparm;
3301 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3302 DFmode (2) arguments in SSE registers for a function with the
3303 indicated TYPE and DECL. DECL may be NULL when calling function
3304 indirectly or considering a libcall. Otherwise return 0. */
3307 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
3309 gcc_assert (!TARGET_64BIT);
3311 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3312 by the sseregparm attribute. */
3313 if (TARGET_SSEREGPARM
3314 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
3321 error ("Calling %qD with attribute sseregparm without "
3322 "SSE/SSE2 enabled", decl);
3324 error ("Calling %qT with attribute sseregparm without "
3325 "SSE/SSE2 enabled", type);
3333 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3334 (and DFmode for SSE2) arguments in SSE registers. */
3335 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3337 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3338 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3340 return TARGET_SSE2 ? 2 : 1;
3346 /* Return true if EAX is live at the start of the function. Used by
3347 ix86_expand_prologue to determine if we need special help before
3348 calling allocate_stack_worker. */
3351 ix86_eax_live_at_start_p (void)
3353 /* Cheat. Don't bother working forward from ix86_function_regparm
3354 to the function type to whether an actual argument is located in
3355 eax. Instead just look at cfg info, which is still close enough
3356 to correct at this point. This gives false positives for broken
3357 functions that might use uninitialized data that happens to be
3358 allocated in eax, but who cares? */
3359 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3362 /* Value is the number of bytes of arguments automatically
3363 popped when returning from a subroutine call.
3364 FUNDECL is the declaration node of the function (as a tree),
3365 FUNTYPE is the data type of the function (as a tree),
3366 or for a library call it is an identifier node for the subroutine name.
3367 SIZE is the number of bytes of arguments passed on the stack.
3369 On the 80386, the RTD insn may be used to pop them if the number
3370 of args is fixed, but if the number is variable then the caller
3371 must pop them all. RTD can't be used for library calls now
3372 because the library is compiled with the Unix compiler.
3373 Use of RTD is a selectable option, since it is incompatible with
3374 standard Unix calling sequences. If the option is not selected,
3375 the caller must always pop the args.
3377 The attribute stdcall is equivalent to RTD on a per module basis. */
3380 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3384 /* None of the 64-bit ABIs pop arguments. */
3388 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3390 /* Cdecl functions override -mrtd, and never pop the stack. */
3391 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3393 /* Stdcall and fastcall functions will pop the stack if not
3395 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3396 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3399 if (rtd && ! stdarg_p (funtype))
3403 /* Lose any fake structure return argument if it is passed on the stack. */
3404 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3405 && !KEEP_AGGREGATE_RETURN_POINTER)
3407 int nregs = ix86_function_regparm (funtype, fundecl);
3409 return GET_MODE_SIZE (Pmode);
3415 /* Argument support functions. */
3417 /* Return true when register may be used to pass function parameters. */
3419 ix86_function_arg_regno_p (int regno)
3422 const int *parm_regs;
3427 return (regno < REGPARM_MAX
3428 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3430 return (regno < REGPARM_MAX
3431 || (TARGET_MMX && MMX_REGNO_P (regno)
3432 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3433 || (TARGET_SSE && SSE_REGNO_P (regno)
3434 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3439 if (SSE_REGNO_P (regno) && TARGET_SSE)
3444 if (TARGET_SSE && SSE_REGNO_P (regno)
3445 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3449 /* RAX is used as hidden argument to va_arg functions. */
3450 if (!TARGET_64BIT_MS_ABI && regno == AX_REG)
3453 if (TARGET_64BIT_MS_ABI)
3454 parm_regs = x86_64_ms_abi_int_parameter_registers;
3456 parm_regs = x86_64_int_parameter_registers;
3457 for (i = 0; i < REGPARM_MAX; i++)
3458 if (regno == parm_regs[i])
3463 /* Return if we do not know how to pass TYPE solely in registers. */
3466 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
3468 if (must_pass_in_stack_var_size_or_pad (mode, type))
3471 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3472 The layout_type routine is crafty and tries to trick us into passing
3473 currently unsupported vector types on the stack by using TImode. */
3474 return (!TARGET_64BIT && mode == TImode
3475 && type && TREE_CODE (type) != VECTOR_TYPE);
3478 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3479 for a call to a function whose data type is FNTYPE.
3480 For a library call, FNTYPE is 0. */
3483 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3484 tree fntype, /* tree ptr for function decl */
3485 rtx libname, /* SYMBOL_REF of library name or 0 */
3488 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
3489 memset (cum, 0, sizeof (*cum));
3491 /* Set up the number of registers to use for passing arguments. */
3492 cum->nregs = ix86_regparm;
3494 cum->sse_nregs = SSE_REGPARM_MAX;
3496 cum->mmx_nregs = MMX_REGPARM_MAX;
3497 cum->warn_sse = true;
3498 cum->warn_mmx = true;
3500 /* Because type might mismatch in between caller and callee, we need to
3501 use actual type of function for local calls.
3502 FIXME: cgraph_analyze can be told to actually record if function uses
3503 va_start so for local functions maybe_vaarg can be made aggressive
3505 FIXME: once typesytem is fixed, we won't need this code anymore. */
3507 fntype = TREE_TYPE (fndecl);
3508 cum->maybe_vaarg = (fntype
3509 ? (!prototype_p (fntype) || stdarg_p (fntype))
3514 /* If there are variable arguments, then we won't pass anything
3515 in registers in 32-bit mode. */
3516 if (cum->maybe_vaarg)
3526 /* Use ecx and edx registers if function has fastcall attribute,
3527 else look for regparm information. */
3530 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3536 cum->nregs = ix86_function_regparm (fntype, fndecl);
3539 /* Set up the number of SSE registers used for passing SFmode
3540 and DFmode arguments. Warn for mismatching ABI. */
3541 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
3545 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3546 But in the case of vector types, it is some vector mode.
3548 When we have only some of our vector isa extensions enabled, then there
3549 are some modes for which vector_mode_supported_p is false. For these
3550 modes, the generic vector support in gcc will choose some non-vector mode
3551 in order to implement the type. By computing the natural mode, we'll
3552 select the proper ABI location for the operand and not depend on whatever
3553 the middle-end decides to do with these vector types. */
3555 static enum machine_mode
3556 type_natural_mode (const_tree type)
3558 enum machine_mode mode = TYPE_MODE (type);
3560 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3562 HOST_WIDE_INT size = int_size_in_bytes (type);
3563 if ((size == 8 || size == 16)
3564 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3565 && TYPE_VECTOR_SUBPARTS (type) > 1)
3567 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3569 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3570 mode = MIN_MODE_VECTOR_FLOAT;
3572 mode = MIN_MODE_VECTOR_INT;
3574 /* Get the mode which has this inner mode and number of units. */
3575 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3576 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3577 && GET_MODE_INNER (mode) == innermode)
3587 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3588 this may not agree with the mode that the type system has chosen for the
3589 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3590 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3593 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3598 if (orig_mode != BLKmode)
3599 tmp = gen_rtx_REG (orig_mode, regno);
3602 tmp = gen_rtx_REG (mode, regno);
3603 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3604 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3610 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3611 of this code is to classify each 8bytes of incoming argument by the register
3612 class and assign registers accordingly. */
3614 /* Return the union class of CLASS1 and CLASS2.
3615 See the x86-64 PS ABI for details. */
3617 static enum x86_64_reg_class
3618 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3620 /* Rule #1: If both classes are equal, this is the resulting class. */
3621 if (class1 == class2)
3624 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3626 if (class1 == X86_64_NO_CLASS)
3628 if (class2 == X86_64_NO_CLASS)
3631 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3632 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3633 return X86_64_MEMORY_CLASS;
3635 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3636 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3637 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3638 return X86_64_INTEGERSI_CLASS;
3639 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3640 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3641 return X86_64_INTEGER_CLASS;
3643 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3645 if (class1 == X86_64_X87_CLASS
3646 || class1 == X86_64_X87UP_CLASS
3647 || class1 == X86_64_COMPLEX_X87_CLASS
3648 || class2 == X86_64_X87_CLASS
3649 || class2 == X86_64_X87UP_CLASS
3650 || class2 == X86_64_COMPLEX_X87_CLASS)
3651 return X86_64_MEMORY_CLASS;
3653 /* Rule #6: Otherwise class SSE is used. */
3654 return X86_64_SSE_CLASS;
3657 /* Classify the argument of type TYPE and mode MODE.
3658 CLASSES will be filled by the register class used to pass each word
3659 of the operand. The number of words is returned. In case the parameter
3660 should be passed in memory, 0 is returned. As a special case for zero
3661 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3663 BIT_OFFSET is used internally for handling records and specifies offset
3664 of the offset in bits modulo 256 to avoid overflow cases.
3666 See the x86-64 PS ABI for details.
3670 classify_argument (enum machine_mode mode, const_tree type,
3671 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3673 HOST_WIDE_INT bytes =
3674 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3675 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3677 /* Variable sized entities are always passed/returned in memory. */
3681 if (mode != VOIDmode
3682 && targetm.calls.must_pass_in_stack (mode, type))
3685 if (type && AGGREGATE_TYPE_P (type))
3689 enum x86_64_reg_class subclasses[MAX_CLASSES];
3691 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3695 for (i = 0; i < words; i++)
3696 classes[i] = X86_64_NO_CLASS;
3698 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3699 signalize memory class, so handle it as special case. */
3702 classes[0] = X86_64_NO_CLASS;
3706 /* Classify each field of record and merge classes. */
3707 switch (TREE_CODE (type))
3710 /* And now merge the fields of structure. */
3711 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3713 if (TREE_CODE (field) == FIELD_DECL)
3717 if (TREE_TYPE (field) == error_mark_node)
3720 /* Bitfields are always classified as integer. Handle them
3721 early, since later code would consider them to be
3722 misaligned integers. */
3723 if (DECL_BIT_FIELD (field))
3725 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3726 i < ((int_bit_position (field) + (bit_offset % 64))
3727 + tree_low_cst (DECL_SIZE (field), 0)
3730 merge_classes (X86_64_INTEGER_CLASS,
3735 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3736 TREE_TYPE (field), subclasses,
3737 (int_bit_position (field)
3738 + bit_offset) % 256);
3741 for (i = 0; i < num; i++)
3744 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3746 merge_classes (subclasses[i], classes[i + pos]);
3754 /* Arrays are handled as small records. */
3757 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3758 TREE_TYPE (type), subclasses, bit_offset);
3762 /* The partial classes are now full classes. */
3763 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3764 subclasses[0] = X86_64_SSE_CLASS;
3765 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3766 subclasses[0] = X86_64_INTEGER_CLASS;
3768 for (i = 0; i < words; i++)
3769 classes[i] = subclasses[i % num];
3774 case QUAL_UNION_TYPE:
3775 /* Unions are similar to RECORD_TYPE but offset is always 0.
3777 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3779 if (TREE_CODE (field) == FIELD_DECL)
3783 if (TREE_TYPE (field) == error_mark_node)
3786 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3787 TREE_TYPE (field), subclasses,
3791 for (i = 0; i < num; i++)
3792 classes[i] = merge_classes (subclasses[i], classes[i]);
3801 /* Final merger cleanup. */
3802 for (i = 0; i < words; i++)
3804 /* If one class is MEMORY, everything should be passed in
3806 if (classes[i] == X86_64_MEMORY_CLASS)
3809 /* The X86_64_SSEUP_CLASS should be always preceded by
3810 X86_64_SSE_CLASS. */
3811 if (classes[i] == X86_64_SSEUP_CLASS
3812 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3813 classes[i] = X86_64_SSE_CLASS;
3815 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3816 if (classes[i] == X86_64_X87UP_CLASS
3817 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3818 classes[i] = X86_64_SSE_CLASS;
3823 /* Compute alignment needed. We align all types to natural boundaries with
3824 exception of XFmode that is aligned to 64bits. */
3825 if (mode != VOIDmode && mode != BLKmode)
3827 int mode_alignment = GET_MODE_BITSIZE (mode);
3830 mode_alignment = 128;
3831 else if (mode == XCmode)
3832 mode_alignment = 256;
3833 if (COMPLEX_MODE_P (mode))
3834 mode_alignment /= 2;
3835 /* Misaligned fields are always returned in memory. */
3836 if (bit_offset % mode_alignment)
3840 /* for V1xx modes, just use the base mode */
3841 if (VECTOR_MODE_P (mode) && mode != V1DImode
3842 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3843 mode = GET_MODE_INNER (mode);
3845 /* Classification of atomic types. */
3850 classes[0] = X86_64_SSE_CLASS;
3853 classes[0] = X86_64_SSE_CLASS;
3854 classes[1] = X86_64_SSEUP_CLASS;
3863 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3864 classes[0] = X86_64_INTEGERSI_CLASS;
3866 classes[0] = X86_64_INTEGER_CLASS;
3870 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3875 if (!(bit_offset % 64))
3876 classes[0] = X86_64_SSESF_CLASS;
3878 classes[0] = X86_64_SSE_CLASS;
3881 classes[0] = X86_64_SSEDF_CLASS;
3884 classes[0] = X86_64_X87_CLASS;
3885 classes[1] = X86_64_X87UP_CLASS;
3888 classes[0] = X86_64_SSE_CLASS;
3889 classes[1] = X86_64_SSEUP_CLASS;
3892 classes[0] = X86_64_SSE_CLASS;
3895 classes[0] = X86_64_SSEDF_CLASS;
3896 classes[1] = X86_64_SSEDF_CLASS;
3899 classes[0] = X86_64_COMPLEX_X87_CLASS;
3902 /* This modes is larger than 16 bytes. */
3910 classes[0] = X86_64_SSE_CLASS;
3911 classes[1] = X86_64_SSEUP_CLASS;
3918 classes[0] = X86_64_SSE_CLASS;
3924 gcc_assert (VECTOR_MODE_P (mode));
3929 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3931 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3932 classes[0] = X86_64_INTEGERSI_CLASS;
3934 classes[0] = X86_64_INTEGER_CLASS;
3935 classes[1] = X86_64_INTEGER_CLASS;
3936 return 1 + (bytes > 8);
3940 /* Examine the argument and return set number of register required in each
3941 class. Return 0 iff parameter should be passed in memory. */
3943 examine_argument (enum machine_mode mode, const_tree type, int in_return,
3944 int *int_nregs, int *sse_nregs)
3946 enum x86_64_reg_class regclass[MAX_CLASSES];
3947 int n = classify_argument (mode, type, regclass, 0);
3953 for (n--; n >= 0; n--)
3954 switch (regclass[n])
3956 case X86_64_INTEGER_CLASS:
3957 case X86_64_INTEGERSI_CLASS:
3960 case X86_64_SSE_CLASS:
3961 case X86_64_SSESF_CLASS:
3962 case X86_64_SSEDF_CLASS:
3965 case X86_64_NO_CLASS:
3966 case X86_64_SSEUP_CLASS:
3968 case X86_64_X87_CLASS:
3969 case X86_64_X87UP_CLASS:
3973 case X86_64_COMPLEX_X87_CLASS:
3974 return in_return ? 2 : 0;
3975 case X86_64_MEMORY_CLASS:
3981 /* Construct container for the argument used by GCC interface. See
3982 FUNCTION_ARG for the detailed description. */
3985 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3986 const_tree type, int in_return, int nintregs, int nsseregs,
3987 const int *intreg, int sse_regno)
3989 /* The following variables hold the static issued_error state. */
3990 static bool issued_sse_arg_error;
3991 static bool issued_sse_ret_error;
3992 static bool issued_x87_ret_error;
3994 enum machine_mode tmpmode;
3996 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3997 enum x86_64_reg_class regclass[MAX_CLASSES];
4001 int needed_sseregs, needed_intregs;
4002 rtx exp[MAX_CLASSES];
4005 n = classify_argument (mode, type, regclass, 0);
4008 if (!examine_argument (mode, type, in_return, &needed_intregs,
4011 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
4014 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
4015 some less clueful developer tries to use floating-point anyway. */
4016 if (needed_sseregs && !TARGET_SSE)
4020 if (!issued_sse_ret_error)
4022 error ("SSE register return with SSE disabled");
4023 issued_sse_ret_error = true;
4026 else if (!issued_sse_arg_error)
4028 error ("SSE register argument with SSE disabled");
4029 issued_sse_arg_error = true;
4034 /* Likewise, error if the ABI requires us to return values in the
4035 x87 registers and the user specified -mno-80387. */
4036 if (!TARGET_80387 && in_return)
4037 for (i = 0; i < n; i++)
4038 if (regclass[i] == X86_64_X87_CLASS
4039 || regclass[i] == X86_64_X87UP_CLASS
4040 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
4042 if (!issued_x87_ret_error)
4044 error ("x87 register return with x87 disabled");
4045 issued_x87_ret_error = true;
4050 /* First construct simple cases. Avoid SCmode, since we want to use
4051 single register to pass this type. */
4052 if (n == 1 && mode != SCmode)
4053 switch (regclass[0])
4055 case X86_64_INTEGER_CLASS:
4056 case X86_64_INTEGERSI_CLASS:
4057 return gen_rtx_REG (mode, intreg[0]);
4058 case X86_64_SSE_CLASS:
4059 case X86_64_SSESF_CLASS:
4060 case X86_64_SSEDF_CLASS:
4061 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
4062 case X86_64_X87_CLASS:
4063 case X86_64_COMPLEX_X87_CLASS:
4064 return gen_rtx_REG (mode, FIRST_STACK_REG);
4065 case X86_64_NO_CLASS:
4066 /* Zero sized array, struct or class. */
4071 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
4072 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
4073 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
4076 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
4077 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
4078 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
4079 && regclass[1] == X86_64_INTEGER_CLASS
4080 && (mode == CDImode || mode == TImode || mode == TFmode)
4081 && intreg[0] + 1 == intreg[1])
4082 return gen_rtx_REG (mode, intreg[0]);
4084 /* Otherwise figure out the entries of the PARALLEL. */
4085 for (i = 0; i < n; i++)
4087 switch (regclass[i])
4089 case X86_64_NO_CLASS:
4091 case X86_64_INTEGER_CLASS:
4092 case X86_64_INTEGERSI_CLASS:
4093 /* Merge TImodes on aligned occasions here too. */
4094 if (i * 8 + 8 > bytes)
4095 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
4096 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
4100 /* We've requested 24 bytes we don't have mode for. Use DImode. */
4101 if (tmpmode == BLKmode)
4103 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4104 gen_rtx_REG (tmpmode, *intreg),
4108 case X86_64_SSESF_CLASS:
4109 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4110 gen_rtx_REG (SFmode,
4111 SSE_REGNO (sse_regno)),
4115 case X86_64_SSEDF_CLASS:
4116 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4117 gen_rtx_REG (DFmode,
4118 SSE_REGNO (sse_regno)),
4122 case X86_64_SSE_CLASS:
4123 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
4127 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4128 gen_rtx_REG (tmpmode,
4129 SSE_REGNO (sse_regno)),
4131 if (tmpmode == TImode)
4140 /* Empty aligned struct, union or class. */
4144 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
4145 for (i = 0; i < nexps; i++)
4146 XVECEXP (ret, 0, i) = exp [i];
4150 /* Update the data in CUM to advance over an argument of mode MODE
4151 and data type TYPE. (TYPE is null for libcalls where that information
4152 may not be available.) */
4155 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4156 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4172 cum->words += words;
4173 cum->nregs -= words;
4174 cum->regno += words;
4176 if (cum->nregs <= 0)
4184 if (cum->float_in_sse < 2)
4187 if (cum->float_in_sse < 1)
4198 if (!type || !AGGREGATE_TYPE_P (type))
4200 cum->sse_words += words;
4201 cum->sse_nregs -= 1;
4202 cum->sse_regno += 1;
4203 if (cum->sse_nregs <= 0)
4216 if (!type || !AGGREGATE_TYPE_P (type))
4218 cum->mmx_words += words;
4219 cum->mmx_nregs -= 1;
4220 cum->mmx_regno += 1;
4221 if (cum->mmx_nregs <= 0)
4232 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4233 tree type, HOST_WIDE_INT words)
4235 int int_nregs, sse_nregs;
4237 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
4238 cum->words += words;
4239 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
4241 cum->nregs -= int_nregs;
4242 cum->sse_nregs -= sse_nregs;
4243 cum->regno += int_nregs;
4244 cum->sse_regno += sse_nregs;
4247 cum->words += words;
4251 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
4252 HOST_WIDE_INT words)
4254 /* Otherwise, this should be passed indirect. */
4255 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
4257 cum->words += words;
4266 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4267 tree type, int named ATTRIBUTE_UNUSED)
4269 HOST_WIDE_INT bytes, words;
4271 if (mode == BLKmode)
4272 bytes = int_size_in_bytes (type);
4274 bytes = GET_MODE_SIZE (mode);
4275 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4278 mode = type_natural_mode (type);
4280 if (TARGET_64BIT_MS_ABI)
4281 function_arg_advance_ms_64 (cum, bytes, words);
4282 else if (TARGET_64BIT)
4283 function_arg_advance_64 (cum, mode, type, words);
4285 function_arg_advance_32 (cum, mode, type, bytes, words);
4288 /* Define where to put the arguments to a function.
4289 Value is zero to push the argument on the stack,
4290 or a hard register in which to store the argument.
4292 MODE is the argument's machine mode.
4293 TYPE is the data type of the argument (as a tree).
4294 This is null for libcalls where that information may
4296 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4297 the preceding args and about the function being called.
4298 NAMED is nonzero if this argument is a named parameter
4299 (otherwise it is an extra parameter matching an ellipsis). */
4302 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4303 enum machine_mode orig_mode, tree type,
4304 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4306 static bool warnedsse, warnedmmx;
4308 /* Avoid the AL settings for the Unix64 ABI. */
4309 if (mode == VOIDmode)
4325 if (words <= cum->nregs)
4327 int regno = cum->regno;
4329 /* Fastcall allocates the first two DWORD (SImode) or
4330 smaller arguments to ECX and EDX if it isn't an
4336 || (type && AGGREGATE_TYPE_P (type)))
4339 /* ECX not EAX is the first allocated register. */
4340 if (regno == AX_REG)
4343 return gen_rtx_REG (mode, regno);
4348 if (cum->float_in_sse < 2)
4351 if (cum->float_in_sse < 1)
4361 if (!type || !AGGREGATE_TYPE_P (type))
4363 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4366 warning (0, "SSE vector argument without SSE enabled "
4370 return gen_reg_or_parallel (mode, orig_mode,
4371 cum->sse_regno + FIRST_SSE_REG);
4380 if (!type || !AGGREGATE_TYPE_P (type))
4382 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4385 warning (0, "MMX vector argument without MMX enabled "
4389 return gen_reg_or_parallel (mode, orig_mode,
4390 cum->mmx_regno + FIRST_MMX_REG);
4399 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4400 enum machine_mode orig_mode, tree type)
4402 /* Handle a hidden AL argument containing number of registers
4403 for varargs x86-64 functions. */
4404 if (mode == VOIDmode)
4405 return GEN_INT (cum->maybe_vaarg
4406 ? (cum->sse_nregs < 0
4411 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4413 &x86_64_int_parameter_registers [cum->regno],
4418 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4419 enum machine_mode orig_mode, int named)
4423 /* Avoid the AL settings for the Unix64 ABI. */
4424 if (mode == VOIDmode)
4427 /* If we've run out of registers, it goes on the stack. */
4428 if (cum->nregs == 0)
4431 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4433 /* Only floating point modes are passed in anything but integer regs. */
4434 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4437 regno = cum->regno + FIRST_SSE_REG;
4442 /* Unnamed floating parameters are passed in both the
4443 SSE and integer registers. */
4444 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4445 t2 = gen_rtx_REG (mode, regno);
4446 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4447 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4448 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4452 return gen_reg_or_parallel (mode, orig_mode, regno);
4456 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4457 tree type, int named)
4459 enum machine_mode mode = omode;
4460 HOST_WIDE_INT bytes, words;
4462 if (mode == BLKmode)
4463 bytes = int_size_in_bytes (type);
4465 bytes = GET_MODE_SIZE (mode);
4466 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4468 /* To simplify the code below, represent vector types with a vector mode
4469 even if MMX/SSE are not active. */
4470 if (type && TREE_CODE (type) == VECTOR_TYPE)
4471 mode = type_natural_mode (type);
4473 if (TARGET_64BIT_MS_ABI)
4474 return function_arg_ms_64 (cum, mode, omode, named);
4475 else if (TARGET_64BIT)
4476 return function_arg_64 (cum, mode, omode, type);
4478 return function_arg_32 (cum, mode, omode, type, bytes, words);
4481 /* A C expression that indicates when an argument must be passed by
4482 reference. If nonzero for an argument, a copy of that argument is
4483 made in memory and a pointer to the argument is passed instead of
4484 the argument itself. The pointer is passed in whatever way is
4485 appropriate for passing a pointer to that type. */
4488 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4489 enum machine_mode mode ATTRIBUTE_UNUSED,
4490 const_tree type, bool named ATTRIBUTE_UNUSED)
4492 if (TARGET_64BIT_MS_ABI)
4496 /* Arrays are passed by reference. */
4497 if (TREE_CODE (type) == ARRAY_TYPE)
4500 if (AGGREGATE_TYPE_P (type))
4502 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4503 are passed by reference. */
4504 int el2 = exact_log2 (int_size_in_bytes (type));
4505 return !(el2 >= 0 && el2 <= 3);
4509 /* __m128 is passed by reference. */
4510 /* ??? How to handle complex? For now treat them as structs,
4511 and pass them by reference if they're too large. */
4512 if (GET_MODE_SIZE (mode) > 8)
4515 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4521 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4522 ABI. Only called if TARGET_SSE. */
4524 contains_128bit_aligned_vector_p (tree type)
4526 enum machine_mode mode = TYPE_MODE (type);
4527 if (SSE_REG_MODE_P (mode)
4528 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4530 if (TYPE_ALIGN (type) < 128)
4533 if (AGGREGATE_TYPE_P (type))
4535 /* Walk the aggregates recursively. */
4536 switch (TREE_CODE (type))
4540 case QUAL_UNION_TYPE:
4544 /* Walk all the structure fields. */
4545 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4547 if (TREE_CODE (field) == FIELD_DECL
4548 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4555 /* Just for use if some languages passes arrays by value. */
4556 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4567 /* Gives the alignment boundary, in bits, of an argument with the
4568 specified mode and type. */
4571 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4575 align = TYPE_ALIGN (type);
4577 align = GET_MODE_ALIGNMENT (mode);
4578 if (align < PARM_BOUNDARY)
4579 align = PARM_BOUNDARY;
4582 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4583 make an exception for SSE modes since these require 128bit
4586 The handling here differs from field_alignment. ICC aligns MMX
4587 arguments to 4 byte boundaries, while structure fields are aligned
4588 to 8 byte boundaries. */
4590 align = PARM_BOUNDARY;
4593 if (!SSE_REG_MODE_P (mode))
4594 align = PARM_BOUNDARY;
4598 if (!contains_128bit_aligned_vector_p (type))
4599 align = PARM_BOUNDARY;
4602 if (align > BIGGEST_ALIGNMENT)
4603 align = BIGGEST_ALIGNMENT;
4607 /* Return true if N is a possible register number of function value. */
4610 ix86_function_value_regno_p (int regno)
4617 case FIRST_FLOAT_REG:
4618 if (TARGET_64BIT_MS_ABI)
4620 return TARGET_FLOAT_RETURNS_IN_80387;
4626 if (TARGET_MACHO || TARGET_64BIT)
4634 /* Define how to find the value returned by a function.
4635 VALTYPE is the data type of the value (as a tree).
4636 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4637 otherwise, FUNC is 0. */
4640 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4641 const_tree fntype, const_tree fn)
4645 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4646 we normally prevent this case when mmx is not available. However
4647 some ABIs may require the result to be returned like DImode. */
4648 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4649 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4651 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4652 we prevent this case when sse is not available. However some ABIs
4653 may require the result to be returned like integer TImode. */
4654 else if (mode == TImode
4655 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4656 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4658 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4659 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4660 regno = FIRST_FLOAT_REG;
4662 /* Most things go in %eax. */
4665 /* Override FP return register with %xmm0 for local functions when
4666 SSE math is enabled or for functions with sseregparm attribute. */
4667 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4669 int sse_level = ix86_function_sseregparm (fntype, fn, false);
4670 if ((sse_level >= 1 && mode == SFmode)
4671 || (sse_level == 2 && mode == DFmode))
4672 regno = FIRST_SSE_REG;
4675 return gen_rtx_REG (orig_mode, regno);
4679 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4684 /* Handle libcalls, which don't provide a type node. */
4685 if (valtype == NULL)
4697 return gen_rtx_REG (mode, FIRST_SSE_REG);
4700 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4704 return gen_rtx_REG (mode, AX_REG);
4708 ret = construct_container (mode, orig_mode, valtype, 1,
4709 REGPARM_MAX, SSE_REGPARM_MAX,
4710 x86_64_int_return_registers, 0);
4712 /* For zero sized structures, construct_container returns NULL, but we
4713 need to keep rest of compiler happy by returning meaningful value. */
4715 ret = gen_rtx_REG (orig_mode, AX_REG);
4721 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4723 unsigned int regno = AX_REG;
4727 if (mode == SFmode || mode == DFmode)
4728 regno = FIRST_SSE_REG;
4729 else if (VECTOR_MODE_P (mode) || GET_MODE_SIZE (mode) == 16)
4730 regno = FIRST_SSE_REG;
4733 return gen_rtx_REG (orig_mode, regno);
4737 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
4738 enum machine_mode orig_mode, enum machine_mode mode)
4740 const_tree fn, fntype;
4743 if (fntype_or_decl && DECL_P (fntype_or_decl))
4744 fn = fntype_or_decl;
4745 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4747 if (TARGET_64BIT_MS_ABI)
4748 return function_value_ms_64 (orig_mode, mode);
4749 else if (TARGET_64BIT)
4750 return function_value_64 (orig_mode, mode, valtype);
4752 return function_value_32 (orig_mode, mode, fntype, fn);
4756 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
4757 bool outgoing ATTRIBUTE_UNUSED)
4759 enum machine_mode mode, orig_mode;
4761 orig_mode = TYPE_MODE (valtype);
4762 mode = type_natural_mode (valtype);
4763 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4767 ix86_libcall_value (enum machine_mode mode)
4769 return ix86_function_value_1 (NULL, NULL, mode, mode);
4772 /* Return true iff type is returned in memory. */
4775 return_in_memory_32 (const_tree type, enum machine_mode mode)
4779 if (mode == BLKmode)
4782 size = int_size_in_bytes (type);
4784 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4787 if (VECTOR_MODE_P (mode) || mode == TImode)
4789 /* User-created vectors small enough to fit in EAX. */
4793 /* MMX/3dNow values are returned in MM0,
4794 except when it doesn't exits. */
4796 return (TARGET_MMX ? 0 : 1);
4798 /* SSE values are returned in XMM0, except when it doesn't exist. */
4800 return (TARGET_SSE ? 0 : 1);
4815 return_in_memory_64 (const_tree type, enum machine_mode mode)
4817 int needed_intregs, needed_sseregs;
4818 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4822 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
4824 HOST_WIDE_INT size = int_size_in_bytes (type);
4826 /* __m128 and friends are returned in xmm0. */
4827 if (!COMPLEX_MODE_P (mode) && size == 16 && VECTOR_MODE_P (mode))
4830 /* Otherwise, the size must be exactly in [1248]. But not for complex. */
4831 return (size != 1 && size != 2 && size != 4 && size != 8)
4832 || COMPLEX_MODE_P (mode);
4836 ix86_return_in_memory (const_tree type)
4838 const enum machine_mode mode = type_natural_mode (type);
4840 if (TARGET_64BIT_MS_ABI)
4841 return return_in_memory_ms_64 (type, mode);
4842 else if (TARGET_64BIT)
4843 return return_in_memory_64 (type, mode);
4845 return return_in_memory_32 (type, mode);
4848 /* Return false iff TYPE is returned in memory. This version is used
4849 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4850 but differs notably in that when MMX is available, 8-byte vectors
4851 are returned in memory, rather than in MMX registers. */
4854 ix86_sol10_return_in_memory (const_tree type)
4857 enum machine_mode mode = type_natural_mode (type);
4860 return return_in_memory_64 (type, mode);
4862 if (mode == BLKmode)
4865 size = int_size_in_bytes (type);
4867 if (VECTOR_MODE_P (mode))
4869 /* Return in memory only if MMX registers *are* available. This
4870 seems backwards, but it is consistent with the existing
4877 else if (mode == TImode)
4879 else if (mode == XFmode)
4885 /* When returning SSE vector types, we have a choice of either
4886 (1) being abi incompatible with a -march switch, or
4887 (2) generating an error.
4888 Given no good solution, I think the safest thing is one warning.
4889 The user won't be able to use -Werror, but....
4891 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4892 called in response to actually generating a caller or callee that
4893 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4894 via aggregate_value_p for general type probing from tree-ssa. */
4897 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4899 static bool warnedsse, warnedmmx;
4901 if (!TARGET_64BIT && type)
4903 /* Look at the return type of the function, not the function type. */
4904 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4906 if (!TARGET_SSE && !warnedsse)
4909 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4912 warning (0, "SSE vector return without SSE enabled "
4917 if (!TARGET_MMX && !warnedmmx)
4919 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4922 warning (0, "MMX vector return without MMX enabled "
4932 /* Create the va_list data type. */
4935 ix86_build_builtin_va_list (void)
4937 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4939 /* For i386 we use plain pointer to argument area. */
4940 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4941 return build_pointer_type (char_type_node);
4943 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4944 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4946 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4947 unsigned_type_node);
4948 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4949 unsigned_type_node);
4950 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4952 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4955 va_list_gpr_counter_field = f_gpr;
4956 va_list_fpr_counter_field = f_fpr;
4958 DECL_FIELD_CONTEXT (f_gpr) = record;
4959 DECL_FIELD_CONTEXT (f_fpr) = record;
4960 DECL_FIELD_CONTEXT (f_ovf) = record;
4961 DECL_FIELD_CONTEXT (f_sav) = record;
4963 TREE_CHAIN (record) = type_decl;
4964 TYPE_NAME (record) = type_decl;
4965 TYPE_FIELDS (record) = f_gpr;
4966 TREE_CHAIN (f_gpr) = f_fpr;
4967 TREE_CHAIN (f_fpr) = f_ovf;
4968 TREE_CHAIN (f_ovf) = f_sav;
4970 layout_type (record);
4972 /* The correct type is an array type of one element. */
4973 return build_array_type (record, build_index_type (size_zero_node));
4976 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4979 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
4989 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4992 /* Indicate to allocate space on the stack for varargs save area. */
4993 ix86_save_varrargs_registers = 1;
4994 /* We need 16-byte stack alignment to save SSE registers. If user
4995 asked for lower preferred_stack_boundary, lets just hope that he knows
4996 what he is doing and won't varargs SSE values.
4998 We also may end up assuming that only 64bit values are stored in SSE
4999 register let some floating point program work. */
5000 if (ix86_preferred_stack_boundary >= BIGGEST_ALIGNMENT)
5001 cfun->stack_alignment_needed = BIGGEST_ALIGNMENT;
5003 save_area = frame_pointer_rtx;
5004 set = get_varargs_alias_set ();
5006 for (i = cum->regno;
5008 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
5011 mem = gen_rtx_MEM (Pmode,
5012 plus_constant (save_area, i * UNITS_PER_WORD));
5013 MEM_NOTRAP_P (mem) = 1;
5014 set_mem_alias_set (mem, set);
5015 emit_move_insn (mem, gen_rtx_REG (Pmode,
5016 x86_64_int_parameter_registers[i]));
5019 if (cum->sse_nregs && cfun->va_list_fpr_size)
5021 /* Now emit code to save SSE registers. The AX parameter contains number
5022 of SSE parameter registers used to call this function. We use
5023 sse_prologue_save insn template that produces computed jump across
5024 SSE saves. We need some preparation work to get this working. */
5026 label = gen_label_rtx ();
5027 label_ref = gen_rtx_LABEL_REF (Pmode, label);
5029 /* Compute address to jump to :
5030 label - 5*eax + nnamed_sse_arguments*5 */
5031 tmp_reg = gen_reg_rtx (Pmode);
5032 nsse_reg = gen_reg_rtx (Pmode);
5033 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
5034 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5035 gen_rtx_MULT (Pmode, nsse_reg,
5040 gen_rtx_CONST (DImode,
5041 gen_rtx_PLUS (DImode,
5043 GEN_INT (cum->sse_regno * 4))));
5045 emit_move_insn (nsse_reg, label_ref);
5046 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
5048 /* Compute address of memory block we save into. We always use pointer
5049 pointing 127 bytes after first byte to store - this is needed to keep
5050 instruction size limited by 4 bytes. */
5051 tmp_reg = gen_reg_rtx (Pmode);
5052 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5053 plus_constant (save_area,
5054 8 * REGPARM_MAX + 127)));
5055 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
5056 MEM_NOTRAP_P (mem) = 1;
5057 set_mem_alias_set (mem, set);
5058 set_mem_align (mem, BITS_PER_WORD);
5060 /* And finally do the dirty job! */
5061 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
5062 GEN_INT (cum->sse_regno), label));
5067 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
5069 alias_set_type set = get_varargs_alias_set ();
5072 for (i = cum->regno; i < REGPARM_MAX; i++)
5076 mem = gen_rtx_MEM (Pmode,
5077 plus_constant (virtual_incoming_args_rtx,
5078 i * UNITS_PER_WORD));
5079 MEM_NOTRAP_P (mem) = 1;
5080 set_mem_alias_set (mem, set);
5082 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
5083 emit_move_insn (mem, reg);
5088 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5089 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5092 CUMULATIVE_ARGS next_cum;
5095 /* This argument doesn't appear to be used anymore. Which is good,
5096 because the old code here didn't suppress rtl generation. */
5097 gcc_assert (!no_rtl);
5102 fntype = TREE_TYPE (current_function_decl);
5104 /* For varargs, we do not want to skip the dummy va_dcl argument.
5105 For stdargs, we do want to skip the last named argument. */
5107 if (stdarg_p (fntype))
5108 function_arg_advance (&next_cum, mode, type, 1);
5110 if (TARGET_64BIT_MS_ABI)
5111 setup_incoming_varargs_ms_64 (&next_cum);
5113 setup_incoming_varargs_64 (&next_cum);
5116 /* Implement va_start. */
5119 ix86_va_start (tree valist, rtx nextarg)
5121 HOST_WIDE_INT words, n_gpr, n_fpr;
5122 tree f_gpr, f_fpr, f_ovf, f_sav;
5123 tree gpr, fpr, ovf, sav, t;
5126 /* Only 64bit target needs something special. */
5127 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5129 std_expand_builtin_va_start (valist, nextarg);
5133 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5134 f_fpr = TREE_CHAIN (f_gpr);
5135 f_ovf = TREE_CHAIN (f_fpr);
5136 f_sav = TREE_CHAIN (f_ovf);
5138 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5139 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5140 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5141 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5142 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5144 /* Count number of gp and fp argument registers used. */
5145 words = current_function_args_info.words;
5146 n_gpr = current_function_args_info.regno;
5147 n_fpr = current_function_args_info.sse_regno;
5149 if (cfun->va_list_gpr_size)
5151 type = TREE_TYPE (gpr);
5152 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
5153 build_int_cst (type, n_gpr * 8));
5154 TREE_SIDE_EFFECTS (t) = 1;
5155 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5158 if (cfun->va_list_fpr_size)
5160 type = TREE_TYPE (fpr);
5161 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
5162 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
5163 TREE_SIDE_EFFECTS (t) = 1;
5164 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5167 /* Find the overflow area. */
5168 type = TREE_TYPE (ovf);
5169 t = make_tree (type, virtual_incoming_args_rtx);
5171 t = build2 (POINTER_PLUS_EXPR, type, t,
5172 size_int (words * UNITS_PER_WORD));
5173 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
5174 TREE_SIDE_EFFECTS (t) = 1;
5175 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5177 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
5179 /* Find the register save area.
5180 Prologue of the function save it right above stack frame. */
5181 type = TREE_TYPE (sav);
5182 t = make_tree (type, frame_pointer_rtx);
5183 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
5184 TREE_SIDE_EFFECTS (t) = 1;
5185 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5189 /* Implement va_arg. */
5192 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5194 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
5195 tree f_gpr, f_fpr, f_ovf, f_sav;
5196 tree gpr, fpr, ovf, sav, t;
5198 tree lab_false, lab_over = NULL_TREE;
5203 enum machine_mode nat_mode;
5205 /* Only 64bit target needs something special. */
5206 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5207 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5209 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5210 f_fpr = TREE_CHAIN (f_gpr);
5211 f_ovf = TREE_CHAIN (f_fpr);
5212 f_sav = TREE_CHAIN (f_ovf);
5214 valist = build_va_arg_indirect_ref (valist);
5215 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5216 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5217 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5218 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5220 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5222 type = build_pointer_type (type);
5223 size = int_size_in_bytes (type);
5224 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5226 nat_mode = type_natural_mode (type);
5227 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
5228 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
5230 /* Pull the value out of the saved registers. */
5232 addr = create_tmp_var (ptr_type_node, "addr");
5233 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5237 int needed_intregs, needed_sseregs;
5239 tree int_addr, sse_addr;
5241 lab_false = create_artificial_label ();
5242 lab_over = create_artificial_label ();
5244 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
5246 need_temp = (!REG_P (container)
5247 && ((needed_intregs && TYPE_ALIGN (type) > 64)
5248 || TYPE_ALIGN (type) > 128));
5250 /* In case we are passing structure, verify that it is consecutive block
5251 on the register save area. If not we need to do moves. */
5252 if (!need_temp && !REG_P (container))
5254 /* Verify that all registers are strictly consecutive */
5255 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
5259 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5261 rtx slot = XVECEXP (container, 0, i);
5262 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
5263 || INTVAL (XEXP (slot, 1)) != i * 16)
5271 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5273 rtx slot = XVECEXP (container, 0, i);
5274 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
5275 || INTVAL (XEXP (slot, 1)) != i * 8)
5287 int_addr = create_tmp_var (ptr_type_node, "int_addr");
5288 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
5289 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
5290 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
5293 /* First ensure that we fit completely in registers. */
5296 t = build_int_cst (TREE_TYPE (gpr),
5297 (REGPARM_MAX - needed_intregs + 1) * 8);
5298 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
5299 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5300 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5301 gimplify_and_add (t, pre_p);
5305 t = build_int_cst (TREE_TYPE (fpr),
5306 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
5308 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
5309 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5310 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5311 gimplify_and_add (t, pre_p);
5314 /* Compute index to start of area used for integer regs. */
5317 /* int_addr = gpr + sav; */
5318 t = fold_convert (sizetype, gpr);
5319 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5320 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
5321 gimplify_and_add (t, pre_p);
5325 /* sse_addr = fpr + sav; */
5326 t = fold_convert (sizetype, fpr);
5327 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5328 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
5329 gimplify_and_add (t, pre_p);
5334 tree temp = create_tmp_var (type, "va_arg_tmp");
5337 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5338 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5339 gimplify_and_add (t, pre_p);
5341 for (i = 0; i < XVECLEN (container, 0); i++)
5343 rtx slot = XVECEXP (container, 0, i);
5344 rtx reg = XEXP (slot, 0);
5345 enum machine_mode mode = GET_MODE (reg);
5346 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5347 tree addr_type = build_pointer_type (piece_type);
5350 tree dest_addr, dest;
5352 if (SSE_REGNO_P (REGNO (reg)))
5354 src_addr = sse_addr;
5355 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5359 src_addr = int_addr;
5360 src_offset = REGNO (reg) * 8;
5362 src_addr = fold_convert (addr_type, src_addr);
5363 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5364 size_int (src_offset));
5365 src = build_va_arg_indirect_ref (src_addr);
5367 dest_addr = fold_convert (addr_type, addr);
5368 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5369 size_int (INTVAL (XEXP (slot, 1))));
5370 dest = build_va_arg_indirect_ref (dest_addr);
5372 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5373 gimplify_and_add (t, pre_p);
5379 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5380 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5381 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5382 gimplify_and_add (t, pre_p);
5386 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5387 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5388 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5389 gimplify_and_add (t, pre_p);
5392 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5393 gimplify_and_add (t, pre_p);
5395 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5396 append_to_statement_list (t, pre_p);
5399 /* ... otherwise out of the overflow area. */
5401 /* Care for on-stack alignment if needed. */
5402 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5403 || integer_zerop (TYPE_SIZE (type)))
5407 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5408 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5409 size_int (align - 1));
5410 t = fold_convert (sizetype, t);
5411 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5413 t = fold_convert (TREE_TYPE (ovf), t);
5415 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5417 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5418 gimplify_and_add (t2, pre_p);
5420 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5421 size_int (rsize * UNITS_PER_WORD));
5422 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5423 gimplify_and_add (t, pre_p);
5427 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5428 append_to_statement_list (t, pre_p);
5431 ptrtype = build_pointer_type (type);
5432 addr = fold_convert (ptrtype, addr);
5435 addr = build_va_arg_indirect_ref (addr);
5436 return build_va_arg_indirect_ref (addr);
5439 /* Return nonzero if OPNUM's MEM should be matched
5440 in movabs* patterns. */
5443 ix86_check_movabs (rtx insn, int opnum)
5447 set = PATTERN (insn);
5448 if (GET_CODE (set) == PARALLEL)
5449 set = XVECEXP (set, 0, 0);
5450 gcc_assert (GET_CODE (set) == SET);
5451 mem = XEXP (set, opnum);
5452 while (GET_CODE (mem) == SUBREG)
5453 mem = SUBREG_REG (mem);
5454 gcc_assert (MEM_P (mem));
5455 return (volatile_ok || !MEM_VOLATILE_P (mem));
5458 /* Initialize the table of extra 80387 mathematical constants. */
5461 init_ext_80387_constants (void)
5463 static const char * cst[5] =
5465 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5466 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5467 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5468 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5469 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5473 for (i = 0; i < 5; i++)
5475 real_from_string (&ext_80387_constants_table[i], cst[i]);
5476 /* Ensure each constant is rounded to XFmode precision. */
5477 real_convert (&ext_80387_constants_table[i],
5478 XFmode, &ext_80387_constants_table[i]);
5481 ext_80387_constants_init = 1;
5484 /* Return true if the constant is something that can be loaded with
5485 a special instruction. */
5488 standard_80387_constant_p (rtx x)
5490 enum machine_mode mode = GET_MODE (x);
5494 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5497 if (x == CONST0_RTX (mode))
5499 if (x == CONST1_RTX (mode))
5502 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5504 /* For XFmode constants, try to find a special 80387 instruction when
5505 optimizing for size or on those CPUs that benefit from them. */
5507 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5511 if (! ext_80387_constants_init)
5512 init_ext_80387_constants ();
5514 for (i = 0; i < 5; i++)
5515 if (real_identical (&r, &ext_80387_constants_table[i]))
5519 /* Load of the constant -0.0 or -1.0 will be split as
5520 fldz;fchs or fld1;fchs sequence. */
5521 if (real_isnegzero (&r))
5523 if (real_identical (&r, &dconstm1))
5529 /* Return the opcode of the special instruction to be used to load
5533 standard_80387_constant_opcode (rtx x)
5535 switch (standard_80387_constant_p (x))
5559 /* Return the CONST_DOUBLE representing the 80387 constant that is
5560 loaded by the specified special instruction. The argument IDX
5561 matches the return value from standard_80387_constant_p. */
5564 standard_80387_constant_rtx (int idx)
5568 if (! ext_80387_constants_init)
5569 init_ext_80387_constants ();
5585 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5589 /* Return 1 if mode is a valid mode for sse. */
5591 standard_sse_mode_p (enum machine_mode mode)
5608 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5611 standard_sse_constant_p (rtx x)
5613 enum machine_mode mode = GET_MODE (x);
5615 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5617 if (vector_all_ones_operand (x, mode)
5618 && standard_sse_mode_p (mode))
5619 return TARGET_SSE2 ? 2 : -1;
5624 /* Return the opcode of the special instruction to be used to load
5628 standard_sse_constant_opcode (rtx insn, rtx x)
5630 switch (standard_sse_constant_p (x))
5633 if (get_attr_mode (insn) == MODE_V4SF)
5634 return "xorps\t%0, %0";
5635 else if (get_attr_mode (insn) == MODE_V2DF)
5636 return "xorpd\t%0, %0";
5638 return "pxor\t%0, %0";
5640 return "pcmpeqd\t%0, %0";
5645 /* Returns 1 if OP contains a symbol reference */
5648 symbolic_reference_mentioned_p (rtx op)
5653 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5656 fmt = GET_RTX_FORMAT (GET_CODE (op));
5657 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5663 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5664 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5668 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5675 /* Return 1 if it is appropriate to emit `ret' instructions in the
5676 body of a function. Do this only if the epilogue is simple, needing a
5677 couple of insns. Prior to reloading, we can't tell how many registers
5678 must be saved, so return 0 then. Return 0 if there is no frame
5679 marker to de-allocate. */
5682 ix86_can_use_return_insn_p (void)
5684 struct ix86_frame frame;
5686 if (! reload_completed || frame_pointer_needed)
5689 /* Don't allow more than 32 pop, since that's all we can do
5690 with one instruction. */
5691 if (current_function_pops_args
5692 && current_function_args_size >= 32768)
5695 ix86_compute_frame_layout (&frame);
5696 return frame.to_allocate == 0 && frame.nregs == 0;
5699 /* Value should be nonzero if functions must have frame pointers.
5700 Zero means the frame pointer need not be set up (and parms may
5701 be accessed via the stack pointer) in functions that seem suitable. */
5704 ix86_frame_pointer_required (void)
5706 /* If we accessed previous frames, then the generated code expects
5707 to be able to access the saved ebp value in our frame. */
5708 if (cfun->machine->accesses_prev_frame)
5711 /* Several x86 os'es need a frame pointer for other reasons,
5712 usually pertaining to setjmp. */
5713 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5716 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5717 the frame pointer by default. Turn it back on now if we've not
5718 got a leaf function. */
5719 if (TARGET_OMIT_LEAF_FRAME_POINTER
5720 && (!current_function_is_leaf
5721 || ix86_current_function_calls_tls_descriptor))
5724 if (current_function_profile)
5730 /* Record that the current function accesses previous call frames. */
5733 ix86_setup_frame_addresses (void)
5735 cfun->machine->accesses_prev_frame = 1;
5738 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5739 # define USE_HIDDEN_LINKONCE 1
5741 # define USE_HIDDEN_LINKONCE 0
5744 static int pic_labels_used;
5746 /* Fills in the label name that should be used for a pc thunk for
5747 the given register. */
5750 get_pc_thunk_name (char name[32], unsigned int regno)
5752 gcc_assert (!TARGET_64BIT);
5754 if (USE_HIDDEN_LINKONCE)
5755 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5757 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5761 /* This function generates code for -fpic that loads %ebx with
5762 the return address of the caller and then returns. */
5765 ix86_file_end (void)
5770 for (regno = 0; regno < 8; ++regno)
5774 if (! ((pic_labels_used >> regno) & 1))
5777 get_pc_thunk_name (name, regno);
5782 switch_to_section (darwin_sections[text_coal_section]);
5783 fputs ("\t.weak_definition\t", asm_out_file);
5784 assemble_name (asm_out_file, name);
5785 fputs ("\n\t.private_extern\t", asm_out_file);
5786 assemble_name (asm_out_file, name);
5787 fputs ("\n", asm_out_file);
5788 ASM_OUTPUT_LABEL (asm_out_file, name);
5792 if (USE_HIDDEN_LINKONCE)
5796 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5798 TREE_PUBLIC (decl) = 1;
5799 TREE_STATIC (decl) = 1;
5800 DECL_ONE_ONLY (decl) = 1;
5802 (*targetm.asm_out.unique_section) (decl, 0);
5803 switch_to_section (get_named_section (decl, NULL, 0));
5805 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5806 fputs ("\t.hidden\t", asm_out_file);
5807 assemble_name (asm_out_file, name);
5808 fputc ('\n', asm_out_file);
5809 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5813 switch_to_section (text_section);
5814 ASM_OUTPUT_LABEL (asm_out_file, name);
5817 xops[0] = gen_rtx_REG (SImode, regno);
5818 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5819 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5820 output_asm_insn ("ret", xops);
5823 if (NEED_INDICATE_EXEC_STACK)
5824 file_end_indicate_exec_stack ();
5827 /* Emit code for the SET_GOT patterns. */
5830 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5836 if (TARGET_VXWORKS_RTP && flag_pic)
5838 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5839 xops[2] = gen_rtx_MEM (Pmode,
5840 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5841 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5843 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5844 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5845 an unadorned address. */
5846 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5847 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5848 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5852 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5854 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5856 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5859 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5861 output_asm_insn ("call\t%a2", xops);
5864 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5865 is what will be referenced by the Mach-O PIC subsystem. */
5867 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5870 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5871 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5874 output_asm_insn ("pop{l}\t%0", xops);
5879 get_pc_thunk_name (name, REGNO (dest));
5880 pic_labels_used |= 1 << REGNO (dest);
5882 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5883 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5884 output_asm_insn ("call\t%X2", xops);
5885 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5886 is what will be referenced by the Mach-O PIC subsystem. */
5889 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5891 targetm.asm_out.internal_label (asm_out_file, "L",
5892 CODE_LABEL_NUMBER (label));
5899 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5900 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5902 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5907 /* Generate an "push" pattern for input ARG. */
5912 return gen_rtx_SET (VOIDmode,
5914 gen_rtx_PRE_DEC (Pmode,
5915 stack_pointer_rtx)),
5919 /* Return >= 0 if there is an unused call-clobbered register available
5920 for the entire function. */
5923 ix86_select_alt_pic_regnum (void)
5925 if (current_function_is_leaf && !current_function_profile
5926 && !ix86_current_function_calls_tls_descriptor)
5929 for (i = 2; i >= 0; --i)
5930 if (!df_regs_ever_live_p (i))
5934 return INVALID_REGNUM;
5937 /* Return 1 if we need to save REGNO. */
5939 ix86_save_reg (unsigned int regno, int maybe_eh_return)
5941 if (pic_offset_table_rtx
5942 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
5943 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
5944 || current_function_profile
5945 || current_function_calls_eh_return
5946 || current_function_uses_const_pool))
5948 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
5953 if (current_function_calls_eh_return && maybe_eh_return)
5958 unsigned test = EH_RETURN_DATA_REGNO (i);
5959 if (test == INVALID_REGNUM)
5966 if (cfun->machine->force_align_arg_pointer
5967 && regno == REGNO (cfun->machine->force_align_arg_pointer))
5970 return (df_regs_ever_live_p (regno)
5971 && !call_used_regs[regno]
5972 && !fixed_regs[regno]
5973 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
5976 /* Return number of registers to be saved on the stack. */
5979 ix86_nsaved_regs (void)
5984 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
5985 if (ix86_save_reg (regno, true))
5990 /* Return the offset between two registers, one to be eliminated, and the other
5991 its replacement, at the start of a routine. */
5994 ix86_initial_elimination_offset (int from, int to)
5996 struct ix86_frame frame;
5997 ix86_compute_frame_layout (&frame);
5999 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
6000 return frame.hard_frame_pointer_offset;
6001 else if (from == FRAME_POINTER_REGNUM
6002 && to == HARD_FRAME_POINTER_REGNUM)
6003 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
6006 gcc_assert (to == STACK_POINTER_REGNUM);
6008 if (from == ARG_POINTER_REGNUM)
6009 return frame.stack_pointer_offset;
6011 gcc_assert (from == FRAME_POINTER_REGNUM);
6012 return frame.stack_pointer_offset - frame.frame_pointer_offset;
6016 /* Fill structure ix86_frame about frame of currently computed function. */
6019 ix86_compute_frame_layout (struct ix86_frame *frame)
6021 HOST_WIDE_INT total_size;
6022 unsigned int stack_alignment_needed;
6023 HOST_WIDE_INT offset;
6024 unsigned int preferred_alignment;
6025 HOST_WIDE_INT size = get_frame_size ();
6027 frame->nregs = ix86_nsaved_regs ();
6030 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
6031 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
6033 /* During reload iteration the amount of registers saved can change.
6034 Recompute the value as needed. Do not recompute when amount of registers
6035 didn't change as reload does multiple calls to the function and does not
6036 expect the decision to change within single iteration. */
6038 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
6040 int count = frame->nregs;
6042 cfun->machine->use_fast_prologue_epilogue_nregs = count;
6043 /* The fast prologue uses move instead of push to save registers. This
6044 is significantly longer, but also executes faster as modern hardware
6045 can execute the moves in parallel, but can't do that for push/pop.
6047 Be careful about choosing what prologue to emit: When function takes
6048 many instructions to execute we may use slow version as well as in
6049 case function is known to be outside hot spot (this is known with
6050 feedback only). Weight the size of function by number of registers
6051 to save as it is cheap to use one or two push instructions but very
6052 slow to use many of them. */
6054 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
6055 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
6056 || (flag_branch_probabilities
6057 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
6058 cfun->machine->use_fast_prologue_epilogue = false;
6060 cfun->machine->use_fast_prologue_epilogue
6061 = !expensive_function_p (count);
6063 if (TARGET_PROLOGUE_USING_MOVE
6064 && cfun->machine->use_fast_prologue_epilogue)
6065 frame->save_regs_using_mov = true;
6067 frame->save_regs_using_mov = false;
6070 /* Skip return address and saved base pointer. */
6071 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
6073 frame->hard_frame_pointer_offset = offset;
6075 /* Do some sanity checking of stack_alignment_needed and
6076 preferred_alignment, since i386 port is the only using those features
6077 that may break easily. */
6079 gcc_assert (!size || stack_alignment_needed);
6080 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
6081 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6082 gcc_assert (stack_alignment_needed
6083 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6085 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
6086 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
6088 /* Register save area */
6089 offset += frame->nregs * UNITS_PER_WORD;
6092 if (ix86_save_varrargs_registers)
6094 offset += X86_64_VARARGS_SIZE;
6095 frame->va_arg_size = X86_64_VARARGS_SIZE;
6098 frame->va_arg_size = 0;
6100 /* Align start of frame for local function. */
6101 frame->padding1 = ((offset + stack_alignment_needed - 1)
6102 & -stack_alignment_needed) - offset;
6104 offset += frame->padding1;
6106 /* Frame pointer points here. */
6107 frame->frame_pointer_offset = offset;
6111 /* Add outgoing arguments area. Can be skipped if we eliminated
6112 all the function calls as dead code.
6113 Skipping is however impossible when function calls alloca. Alloca
6114 expander assumes that last current_function_outgoing_args_size
6115 of stack frame are unused. */
6116 if (ACCUMULATE_OUTGOING_ARGS
6117 && (!current_function_is_leaf || current_function_calls_alloca
6118 || ix86_current_function_calls_tls_descriptor))
6120 offset += current_function_outgoing_args_size;
6121 frame->outgoing_arguments_size = current_function_outgoing_args_size;
6124 frame->outgoing_arguments_size = 0;
6126 /* Align stack boundary. Only needed if we're calling another function
6128 if (!current_function_is_leaf || current_function_calls_alloca
6129 || ix86_current_function_calls_tls_descriptor)
6130 frame->padding2 = ((offset + preferred_alignment - 1)
6131 & -preferred_alignment) - offset;
6133 frame->padding2 = 0;
6135 offset += frame->padding2;
6137 /* We've reached end of stack frame. */
6138 frame->stack_pointer_offset = offset;
6140 /* Size prologue needs to allocate. */
6141 frame->to_allocate =
6142 (size + frame->padding1 + frame->padding2
6143 + frame->outgoing_arguments_size + frame->va_arg_size);
6145 if ((!frame->to_allocate && frame->nregs <= 1)
6146 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
6147 frame->save_regs_using_mov = false;
6149 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
6150 && current_function_is_leaf
6151 && !ix86_current_function_calls_tls_descriptor)
6153 frame->red_zone_size = frame->to_allocate;
6154 if (frame->save_regs_using_mov)
6155 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
6156 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
6157 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
6160 frame->red_zone_size = 0;
6161 frame->to_allocate -= frame->red_zone_size;
6162 frame->stack_pointer_offset -= frame->red_zone_size;
6164 fprintf (stderr, "\n");
6165 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
6166 fprintf (stderr, "size: %ld\n", (long)size);
6167 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
6168 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
6169 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
6170 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
6171 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
6172 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
6173 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
6174 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
6175 (long)frame->hard_frame_pointer_offset);
6176 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
6177 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
6178 fprintf (stderr, "current_function_calls_alloca: %ld\n", (long)current_function_calls_alloca);
6179 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
6183 /* Emit code to save registers in the prologue. */
6186 ix86_emit_save_regs (void)
6191 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
6192 if (ix86_save_reg (regno, true))
6194 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
6195 RTX_FRAME_RELATED_P (insn) = 1;
6199 /* Emit code to save registers using MOV insns. First register
6200 is restored from POINTER + OFFSET. */
6202 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
6207 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6208 if (ix86_save_reg (regno, true))
6210 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
6212 gen_rtx_REG (Pmode, regno));
6213 RTX_FRAME_RELATED_P (insn) = 1;
6214 offset += UNITS_PER_WORD;
6218 /* Expand prologue or epilogue stack adjustment.
6219 The pattern exist to put a dependency on all ebp-based memory accesses.
6220 STYLE should be negative if instructions should be marked as frame related,
6221 zero if %r11 register is live and cannot be freely used and positive
6225 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
6230 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
6231 else if (x86_64_immediate_operand (offset, DImode))
6232 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
6236 /* r11 is used by indirect sibcall return as well, set before the
6237 epilogue and used after the epilogue. ATM indirect sibcall
6238 shouldn't be used together with huge frame sizes in one
6239 function because of the frame_size check in sibcall.c. */
6241 r11 = gen_rtx_REG (DImode, R11_REG);
6242 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
6244 RTX_FRAME_RELATED_P (insn) = 1;
6245 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
6249 RTX_FRAME_RELATED_P (insn) = 1;
6252 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
6255 ix86_internal_arg_pointer (void)
6257 bool has_force_align_arg_pointer =
6258 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
6259 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
6260 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
6261 && DECL_NAME (current_function_decl)
6262 && MAIN_NAME_P (DECL_NAME (current_function_decl))
6263 && DECL_FILE_SCOPE_P (current_function_decl))
6264 || ix86_force_align_arg_pointer
6265 || has_force_align_arg_pointer)
6267 /* Nested functions can't realign the stack due to a register
6269 if (DECL_CONTEXT (current_function_decl)
6270 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
6272 if (ix86_force_align_arg_pointer)
6273 warning (0, "-mstackrealign ignored for nested functions");
6274 if (has_force_align_arg_pointer)
6275 error ("%s not supported for nested functions",
6276 ix86_force_align_arg_pointer_string);
6277 return virtual_incoming_args_rtx;
6279 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, CX_REG);
6280 return copy_to_reg (cfun->machine->force_align_arg_pointer);
6283 return virtual_incoming_args_rtx;
6286 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
6287 This is called from dwarf2out.c to emit call frame instructions
6288 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
6290 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
6292 rtx unspec = SET_SRC (pattern);
6293 gcc_assert (GET_CODE (unspec) == UNSPEC);
6297 case UNSPEC_REG_SAVE:
6298 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
6299 SET_DEST (pattern));
6301 case UNSPEC_DEF_CFA:
6302 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
6303 INTVAL (XVECEXP (unspec, 0, 0)));
6310 /* Expand the prologue into a bunch of separate insns. */
6313 ix86_expand_prologue (void)
6317 struct ix86_frame frame;
6318 HOST_WIDE_INT allocate;
6320 ix86_compute_frame_layout (&frame);
6322 if (cfun->machine->force_align_arg_pointer)
6326 /* Grab the argument pointer. */
6327 x = plus_constant (stack_pointer_rtx, 4);
6328 y = cfun->machine->force_align_arg_pointer;
6329 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
6330 RTX_FRAME_RELATED_P (insn) = 1;
6332 /* The unwind info consists of two parts: install the fafp as the cfa,
6333 and record the fafp as the "save register" of the stack pointer.
6334 The later is there in order that the unwinder can see where it
6335 should restore the stack pointer across the and insn. */
6336 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
6337 x = gen_rtx_SET (VOIDmode, y, x);
6338 RTX_FRAME_RELATED_P (x) = 1;
6339 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6341 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6342 RTX_FRAME_RELATED_P (y) = 1;
6343 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6344 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6345 REG_NOTES (insn) = x;
6347 /* Align the stack. */
6348 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6351 /* And here we cheat like madmen with the unwind info. We force the
6352 cfa register back to sp+4, which is exactly what it was at the
6353 start of the function. Re-pushing the return address results in
6354 the return at the same spot relative to the cfa, and thus is
6355 correct wrt the unwind info. */
6356 x = cfun->machine->force_align_arg_pointer;
6357 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6358 insn = emit_insn (gen_push (x));
6359 RTX_FRAME_RELATED_P (insn) = 1;
6362 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6363 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6364 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6365 REG_NOTES (insn) = x;
6368 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6369 slower on all targets. Also sdb doesn't like it. */
6371 if (frame_pointer_needed)
6373 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6374 RTX_FRAME_RELATED_P (insn) = 1;
6376 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6377 RTX_FRAME_RELATED_P (insn) = 1;
6380 allocate = frame.to_allocate;
6382 if (!frame.save_regs_using_mov)
6383 ix86_emit_save_regs ();
6385 allocate += frame.nregs * UNITS_PER_WORD;
6387 /* When using red zone we may start register saving before allocating
6388 the stack frame saving one cycle of the prologue. However I will
6389 avoid doing this if I am going to have to probe the stack since
6390 at least on x86_64 the stack probe can turn into a call that clobbers
6391 a red zone location */
6392 if (TARGET_RED_ZONE && frame.save_regs_using_mov
6393 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
6394 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6395 : stack_pointer_rtx,
6396 -frame.nregs * UNITS_PER_WORD);
6400 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6401 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6402 GEN_INT (-allocate), -1);
6405 /* Only valid for Win32. */
6406 rtx eax = gen_rtx_REG (Pmode, AX_REG);
6410 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
6412 if (TARGET_64BIT_MS_ABI)
6415 eax_live = ix86_eax_live_at_start_p ();
6419 emit_insn (gen_push (eax));
6420 allocate -= UNITS_PER_WORD;
6423 emit_move_insn (eax, GEN_INT (allocate));
6426 insn = gen_allocate_stack_worker_64 (eax);
6428 insn = gen_allocate_stack_worker_32 (eax);
6429 insn = emit_insn (insn);
6430 RTX_FRAME_RELATED_P (insn) = 1;
6431 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6432 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6433 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6434 t, REG_NOTES (insn));
6438 if (frame_pointer_needed)
6439 t = plus_constant (hard_frame_pointer_rtx,
6442 - frame.nregs * UNITS_PER_WORD);
6444 t = plus_constant (stack_pointer_rtx, allocate);
6445 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6449 if (frame.save_regs_using_mov
6450 && !(TARGET_RED_ZONE
6451 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
6453 if (!frame_pointer_needed || !frame.to_allocate)
6454 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6456 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6457 -frame.nregs * UNITS_PER_WORD);
6460 pic_reg_used = false;
6461 if (pic_offset_table_rtx
6462 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6463 || current_function_profile))
6465 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6467 if (alt_pic_reg_used != INVALID_REGNUM)
6468 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6470 pic_reg_used = true;
6477 if (ix86_cmodel == CM_LARGE_PIC)
6479 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
6480 rtx label = gen_label_rtx ();
6482 LABEL_PRESERVE_P (label) = 1;
6483 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6484 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6485 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6486 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6487 pic_offset_table_rtx, tmp_reg));
6490 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6493 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6496 /* Prevent function calls from being scheduled before the call to mcount.
6497 In the pic_reg_used case, make sure that the got load isn't deleted. */
6498 if (current_function_profile)
6501 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6502 emit_insn (gen_blockage ());
6506 /* Emit code to restore saved registers using MOV insns. First register
6507 is restored from POINTER + OFFSET. */
6509 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6510 int maybe_eh_return)
6513 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6515 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6516 if (ix86_save_reg (regno, maybe_eh_return))
6518 /* Ensure that adjust_address won't be forced to produce pointer
6519 out of range allowed by x86-64 instruction set. */
6520 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6524 r11 = gen_rtx_REG (DImode, R11_REG);
6525 emit_move_insn (r11, GEN_INT (offset));
6526 emit_insn (gen_adddi3 (r11, r11, pointer));
6527 base_address = gen_rtx_MEM (Pmode, r11);
6530 emit_move_insn (gen_rtx_REG (Pmode, regno),
6531 adjust_address (base_address, Pmode, offset));
6532 offset += UNITS_PER_WORD;
6536 /* Restore function stack, frame, and registers. */
6539 ix86_expand_epilogue (int style)
6542 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6543 struct ix86_frame frame;
6544 HOST_WIDE_INT offset;
6546 ix86_compute_frame_layout (&frame);
6548 /* Calculate start of saved registers relative to ebp. Special care
6549 must be taken for the normal return case of a function using
6550 eh_return: the eax and edx registers are marked as saved, but not
6551 restored along this path. */
6552 offset = frame.nregs;
6553 if (current_function_calls_eh_return && style != 2)
6555 offset *= -UNITS_PER_WORD;
6557 /* If we're only restoring one register and sp is not valid then
6558 using a move instruction to restore the register since it's
6559 less work than reloading sp and popping the register.
6561 The default code result in stack adjustment using add/lea instruction,
6562 while this code results in LEAVE instruction (or discrete equivalent),
6563 so it is profitable in some other cases as well. Especially when there
6564 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6565 and there is exactly one register to pop. This heuristic may need some
6566 tuning in future. */
6567 if ((!sp_valid && frame.nregs <= 1)
6568 || (TARGET_EPILOGUE_USING_MOVE
6569 && cfun->machine->use_fast_prologue_epilogue
6570 && (frame.nregs > 1 || frame.to_allocate))
6571 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6572 || (frame_pointer_needed && TARGET_USE_LEAVE
6573 && cfun->machine->use_fast_prologue_epilogue
6574 && frame.nregs == 1)
6575 || current_function_calls_eh_return)
6577 /* Restore registers. We can use ebp or esp to address the memory
6578 locations. If both are available, default to ebp, since offsets
6579 are known to be small. Only exception is esp pointing directly to the
6580 end of block of saved registers, where we may simplify addressing
6583 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6584 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6585 frame.to_allocate, style == 2);
6587 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6588 offset, style == 2);
6590 /* eh_return epilogues need %ecx added to the stack pointer. */
6593 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6595 if (frame_pointer_needed)
6597 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6598 tmp = plus_constant (tmp, UNITS_PER_WORD);
6599 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6601 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6602 emit_move_insn (hard_frame_pointer_rtx, tmp);
6604 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6609 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6610 tmp = plus_constant (tmp, (frame.to_allocate
6611 + frame.nregs * UNITS_PER_WORD));
6612 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6615 else if (!frame_pointer_needed)
6616 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6617 GEN_INT (frame.to_allocate
6618 + frame.nregs * UNITS_PER_WORD),
6620 /* If not an i386, mov & pop is faster than "leave". */
6621 else if (TARGET_USE_LEAVE || optimize_size
6622 || !cfun->machine->use_fast_prologue_epilogue)
6623 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6626 pro_epilogue_adjust_stack (stack_pointer_rtx,
6627 hard_frame_pointer_rtx,
6630 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6632 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6637 /* First step is to deallocate the stack frame so that we can
6638 pop the registers. */
6641 gcc_assert (frame_pointer_needed);
6642 pro_epilogue_adjust_stack (stack_pointer_rtx,
6643 hard_frame_pointer_rtx,
6644 GEN_INT (offset), style);
6646 else if (frame.to_allocate)
6647 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6648 GEN_INT (frame.to_allocate), style);
6650 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6651 if (ix86_save_reg (regno, false))
6654 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6656 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6658 if (frame_pointer_needed)
6660 /* Leave results in shorter dependency chains on CPUs that are
6661 able to grok it fast. */
6662 if (TARGET_USE_LEAVE)
6663 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6664 else if (TARGET_64BIT)
6665 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6667 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6671 if (cfun->machine->force_align_arg_pointer)
6673 emit_insn (gen_addsi3 (stack_pointer_rtx,
6674 cfun->machine->force_align_arg_pointer,
6678 /* Sibcall epilogues don't want a return instruction. */
6682 if (current_function_pops_args && current_function_args_size)
6684 rtx popc = GEN_INT (current_function_pops_args);
6686 /* i386 can only pop 64K bytes. If asked to pop more, pop
6687 return address, do explicit add, and jump indirectly to the
6690 if (current_function_pops_args >= 65536)
6692 rtx ecx = gen_rtx_REG (SImode, CX_REG);
6694 /* There is no "pascal" calling convention in any 64bit ABI. */
6695 gcc_assert (!TARGET_64BIT);
6697 emit_insn (gen_popsi1 (ecx));
6698 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6699 emit_jump_insn (gen_return_indirect_internal (ecx));
6702 emit_jump_insn (gen_return_pop_internal (popc));
6705 emit_jump_insn (gen_return_internal ());
6708 /* Reset from the function's potential modifications. */
6711 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6712 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6714 if (pic_offset_table_rtx)
6715 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6717 /* Mach-O doesn't support labels at the end of objects, so if
6718 it looks like we might want one, insert a NOP. */
6720 rtx insn = get_last_insn ();
6723 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6724 insn = PREV_INSN (insn);
6728 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6729 fputs ("\tnop\n", file);
6735 /* Extract the parts of an RTL expression that is a valid memory address
6736 for an instruction. Return 0 if the structure of the address is
6737 grossly off. Return -1 if the address contains ASHIFT, so it is not
6738 strictly valid, but still used for computing length of lea instruction. */
6741 ix86_decompose_address (rtx addr, struct ix86_address *out)
6743 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6744 rtx base_reg, index_reg;
6745 HOST_WIDE_INT scale = 1;
6746 rtx scale_rtx = NULL_RTX;
6748 enum ix86_address_seg seg = SEG_DEFAULT;
6750 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6752 else if (GET_CODE (addr) == PLUS)
6762 addends[n++] = XEXP (op, 1);
6765 while (GET_CODE (op) == PLUS);
6770 for (i = n; i >= 0; --i)
6773 switch (GET_CODE (op))
6778 index = XEXP (op, 0);
6779 scale_rtx = XEXP (op, 1);
6783 if (XINT (op, 1) == UNSPEC_TP
6784 && TARGET_TLS_DIRECT_SEG_REFS
6785 && seg == SEG_DEFAULT)
6786 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6815 else if (GET_CODE (addr) == MULT)
6817 index = XEXP (addr, 0); /* index*scale */
6818 scale_rtx = XEXP (addr, 1);
6820 else if (GET_CODE (addr) == ASHIFT)
6824 /* We're called for lea too, which implements ashift on occasion. */
6825 index = XEXP (addr, 0);
6826 tmp = XEXP (addr, 1);
6827 if (!CONST_INT_P (tmp))
6829 scale = INTVAL (tmp);
6830 if ((unsigned HOST_WIDE_INT) scale > 3)
6836 disp = addr; /* displacement */
6838 /* Extract the integral value of scale. */
6841 if (!CONST_INT_P (scale_rtx))
6843 scale = INTVAL (scale_rtx);
6846 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6847 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6849 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6850 if (base_reg && index_reg && scale == 1
6851 && (index_reg == arg_pointer_rtx
6852 || index_reg == frame_pointer_rtx
6853 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6856 tmp = base, base = index, index = tmp;
6857 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6860 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6861 if ((base_reg == hard_frame_pointer_rtx
6862 || base_reg == frame_pointer_rtx
6863 || base_reg == arg_pointer_rtx) && !disp)
6866 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6867 Avoid this by transforming to [%esi+0]. */
6868 if (TARGET_K6 && !optimize_size
6869 && base_reg && !index_reg && !disp
6871 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6874 /* Special case: encode reg+reg instead of reg*2. */
6875 if (!base && index && scale && scale == 2)
6876 base = index, base_reg = index_reg, scale = 1;
6878 /* Special case: scaling cannot be encoded without base or displacement. */
6879 if (!base && !disp && index && scale != 1)
6891 /* Return cost of the memory address x.
6892 For i386, it is better to use a complex address than let gcc copy
6893 the address into a reg and make a new pseudo. But not if the address
6894 requires to two regs - that would mean more pseudos with longer
6897 ix86_address_cost (rtx x)
6899 struct ix86_address parts;
6901 int ok = ix86_decompose_address (x, &parts);
6905 if (parts.base && GET_CODE (parts.base) == SUBREG)
6906 parts.base = SUBREG_REG (parts.base);
6907 if (parts.index && GET_CODE (parts.index) == SUBREG)
6908 parts.index = SUBREG_REG (parts.index);
6910 /* Attempt to minimize number of registers in the address. */
6912 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6914 && (!REG_P (parts.index)
6915 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6919 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
6921 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
6922 && parts.base != parts.index)
6925 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6926 since it's predecode logic can't detect the length of instructions
6927 and it degenerates to vector decoded. Increase cost of such
6928 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6929 to split such addresses or even refuse such addresses at all.
6931 Following addressing modes are affected:
6936 The first and last case may be avoidable by explicitly coding the zero in
6937 memory address, but I don't have AMD-K6 machine handy to check this
6941 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
6942 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
6943 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
6949 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6950 this is used for to form addresses to local data when -fPIC is in
6954 darwin_local_data_pic (rtx disp)
6956 if (GET_CODE (disp) == MINUS)
6958 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
6959 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
6960 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
6962 const char *sym_name = XSTR (XEXP (disp, 1), 0);
6963 if (! strcmp (sym_name, "<pic base>"))
6971 /* Determine if a given RTX is a valid constant. We already know this
6972 satisfies CONSTANT_P. */
6975 legitimate_constant_p (rtx x)
6977 switch (GET_CODE (x))
6982 if (GET_CODE (x) == PLUS)
6984 if (!CONST_INT_P (XEXP (x, 1)))
6989 if (TARGET_MACHO && darwin_local_data_pic (x))
6992 /* Only some unspecs are valid as "constants". */
6993 if (GET_CODE (x) == UNSPEC)
6994 switch (XINT (x, 1))
6999 return TARGET_64BIT;
7002 x = XVECEXP (x, 0, 0);
7003 return (GET_CODE (x) == SYMBOL_REF
7004 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7006 x = XVECEXP (x, 0, 0);
7007 return (GET_CODE (x) == SYMBOL_REF
7008 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
7013 /* We must have drilled down to a symbol. */
7014 if (GET_CODE (x) == LABEL_REF)
7016 if (GET_CODE (x) != SYMBOL_REF)
7021 /* TLS symbols are never valid. */
7022 if (SYMBOL_REF_TLS_MODEL (x))
7025 /* DLLIMPORT symbols are never valid. */
7026 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
7027 && SYMBOL_REF_DLLIMPORT_P (x))
7032 if (GET_MODE (x) == TImode
7033 && x != CONST0_RTX (TImode)
7039 if (x == CONST0_RTX (GET_MODE (x)))
7047 /* Otherwise we handle everything else in the move patterns. */
7051 /* Determine if it's legal to put X into the constant pool. This
7052 is not possible for the address of thread-local symbols, which
7053 is checked above. */
7056 ix86_cannot_force_const_mem (rtx x)
7058 /* We can always put integral constants and vectors in memory. */
7059 switch (GET_CODE (x))
7069 return !legitimate_constant_p (x);
7072 /* Determine if a given RTX is a valid constant address. */
7075 constant_address_p (rtx x)
7077 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
7080 /* Nonzero if the constant value X is a legitimate general operand
7081 when generating PIC code. It is given that flag_pic is on and
7082 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
7085 legitimate_pic_operand_p (rtx x)
7089 switch (GET_CODE (x))
7092 inner = XEXP (x, 0);
7093 if (GET_CODE (inner) == PLUS
7094 && CONST_INT_P (XEXP (inner, 1)))
7095 inner = XEXP (inner, 0);
7097 /* Only some unspecs are valid as "constants". */
7098 if (GET_CODE (inner) == UNSPEC)
7099 switch (XINT (inner, 1))
7104 return TARGET_64BIT;
7106 x = XVECEXP (inner, 0, 0);
7107 return (GET_CODE (x) == SYMBOL_REF
7108 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7116 return legitimate_pic_address_disp_p (x);
7123 /* Determine if a given CONST RTX is a valid memory displacement
7127 legitimate_pic_address_disp_p (rtx disp)
7131 /* In 64bit mode we can allow direct addresses of symbols and labels
7132 when they are not dynamic symbols. */
7135 rtx op0 = disp, op1;
7137 switch (GET_CODE (disp))
7143 if (GET_CODE (XEXP (disp, 0)) != PLUS)
7145 op0 = XEXP (XEXP (disp, 0), 0);
7146 op1 = XEXP (XEXP (disp, 0), 1);
7147 if (!CONST_INT_P (op1)
7148 || INTVAL (op1) >= 16*1024*1024
7149 || INTVAL (op1) < -16*1024*1024)
7151 if (GET_CODE (op0) == LABEL_REF)
7153 if (GET_CODE (op0) != SYMBOL_REF)
7158 /* TLS references should always be enclosed in UNSPEC. */
7159 if (SYMBOL_REF_TLS_MODEL (op0))
7161 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
7162 && ix86_cmodel != CM_LARGE_PIC)
7170 if (GET_CODE (disp) != CONST)
7172 disp = XEXP (disp, 0);
7176 /* We are unsafe to allow PLUS expressions. This limit allowed distance
7177 of GOT tables. We should not need these anyway. */
7178 if (GET_CODE (disp) != UNSPEC
7179 || (XINT (disp, 1) != UNSPEC_GOTPCREL
7180 && XINT (disp, 1) != UNSPEC_GOTOFF
7181 && XINT (disp, 1) != UNSPEC_PLTOFF))
7184 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
7185 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
7191 if (GET_CODE (disp) == PLUS)
7193 if (!CONST_INT_P (XEXP (disp, 1)))
7195 disp = XEXP (disp, 0);
7199 if (TARGET_MACHO && darwin_local_data_pic (disp))
7202 if (GET_CODE (disp) != UNSPEC)
7205 switch (XINT (disp, 1))
7210 /* We need to check for both symbols and labels because VxWorks loads
7211 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
7213 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7214 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
7216 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
7217 While ABI specify also 32bit relocation but we don't produce it in
7218 small PIC model at all. */
7219 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7220 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
7222 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
7224 case UNSPEC_GOTTPOFF:
7225 case UNSPEC_GOTNTPOFF:
7226 case UNSPEC_INDNTPOFF:
7229 disp = XVECEXP (disp, 0, 0);
7230 return (GET_CODE (disp) == SYMBOL_REF
7231 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
7233 disp = XVECEXP (disp, 0, 0);
7234 return (GET_CODE (disp) == SYMBOL_REF
7235 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
7237 disp = XVECEXP (disp, 0, 0);
7238 return (GET_CODE (disp) == SYMBOL_REF
7239 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
7245 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
7246 memory address for an instruction. The MODE argument is the machine mode
7247 for the MEM expression that wants to use this address.
7249 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
7250 convert common non-canonical forms to canonical form so that they will
7254 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
7255 rtx addr, int strict)
7257 struct ix86_address parts;
7258 rtx base, index, disp;
7259 HOST_WIDE_INT scale;
7260 const char *reason = NULL;
7261 rtx reason_rtx = NULL_RTX;
7263 if (ix86_decompose_address (addr, &parts) <= 0)
7265 reason = "decomposition failed";
7270 index = parts.index;
7272 scale = parts.scale;
7274 /* Validate base register.
7276 Don't allow SUBREG's that span more than a word here. It can lead to spill
7277 failures when the base is one word out of a two word structure, which is
7278 represented internally as a DImode int. */
7287 else if (GET_CODE (base) == SUBREG
7288 && REG_P (SUBREG_REG (base))
7289 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
7291 reg = SUBREG_REG (base);
7294 reason = "base is not a register";
7298 if (GET_MODE (base) != Pmode)
7300 reason = "base is not in Pmode";
7304 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
7305 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
7307 reason = "base is not valid";
7312 /* Validate index register.
7314 Don't allow SUBREG's that span more than a word here -- same as above. */
7323 else if (GET_CODE (index) == SUBREG
7324 && REG_P (SUBREG_REG (index))
7325 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
7327 reg = SUBREG_REG (index);
7330 reason = "index is not a register";
7334 if (GET_MODE (index) != Pmode)
7336 reason = "index is not in Pmode";
7340 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7341 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7343 reason = "index is not valid";
7348 /* Validate scale factor. */
7351 reason_rtx = GEN_INT (scale);
7354 reason = "scale without index";
7358 if (scale != 2 && scale != 4 && scale != 8)
7360 reason = "scale is not a valid multiplier";
7365 /* Validate displacement. */
7370 if (GET_CODE (disp) == CONST
7371 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7372 switch (XINT (XEXP (disp, 0), 1))
7374 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7375 used. While ABI specify also 32bit relocations, we don't produce
7376 them at all and use IP relative instead. */
7379 gcc_assert (flag_pic);
7381 goto is_legitimate_pic;
7382 reason = "64bit address unspec";
7385 case UNSPEC_GOTPCREL:
7386 gcc_assert (flag_pic);
7387 goto is_legitimate_pic;
7389 case UNSPEC_GOTTPOFF:
7390 case UNSPEC_GOTNTPOFF:
7391 case UNSPEC_INDNTPOFF:
7397 reason = "invalid address unspec";
7401 else if (SYMBOLIC_CONST (disp)
7405 && MACHOPIC_INDIRECT
7406 && !machopic_operand_p (disp)
7412 if (TARGET_64BIT && (index || base))
7414 /* foo@dtpoff(%rX) is ok. */
7415 if (GET_CODE (disp) != CONST
7416 || GET_CODE (XEXP (disp, 0)) != PLUS
7417 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7418 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7419 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7420 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7422 reason = "non-constant pic memory reference";
7426 else if (! legitimate_pic_address_disp_p (disp))
7428 reason = "displacement is an invalid pic construct";
7432 /* This code used to verify that a symbolic pic displacement
7433 includes the pic_offset_table_rtx register.
7435 While this is good idea, unfortunately these constructs may
7436 be created by "adds using lea" optimization for incorrect
7445 This code is nonsensical, but results in addressing
7446 GOT table with pic_offset_table_rtx base. We can't
7447 just refuse it easily, since it gets matched by
7448 "addsi3" pattern, that later gets split to lea in the
7449 case output register differs from input. While this
7450 can be handled by separate addsi pattern for this case
7451 that never results in lea, this seems to be easier and
7452 correct fix for crash to disable this test. */
7454 else if (GET_CODE (disp) != LABEL_REF
7455 && !CONST_INT_P (disp)
7456 && (GET_CODE (disp) != CONST
7457 || !legitimate_constant_p (disp))
7458 && (GET_CODE (disp) != SYMBOL_REF
7459 || !legitimate_constant_p (disp)))
7461 reason = "displacement is not constant";
7464 else if (TARGET_64BIT
7465 && !x86_64_immediate_operand (disp, VOIDmode))
7467 reason = "displacement is out of range";
7472 /* Everything looks valid. */
7479 /* Return a unique alias set for the GOT. */
7481 static alias_set_type
7482 ix86_GOT_alias_set (void)
7484 static alias_set_type set = -1;
7486 set = new_alias_set ();
7490 /* Return a legitimate reference for ORIG (an address) using the
7491 register REG. If REG is 0, a new pseudo is generated.
7493 There are two types of references that must be handled:
7495 1. Global data references must load the address from the GOT, via
7496 the PIC reg. An insn is emitted to do this load, and the reg is
7499 2. Static data references, constant pool addresses, and code labels
7500 compute the address as an offset from the GOT, whose base is in
7501 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7502 differentiate them from global data objects. The returned
7503 address is the PIC reg + an unspec constant.
7505 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7506 reg also appears in the address. */
7509 legitimize_pic_address (rtx orig, rtx reg)
7516 if (TARGET_MACHO && !TARGET_64BIT)
7519 reg = gen_reg_rtx (Pmode);
7520 /* Use the generic Mach-O PIC machinery. */
7521 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7525 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7527 else if (TARGET_64BIT
7528 && ix86_cmodel != CM_SMALL_PIC
7529 && gotoff_operand (addr, Pmode))
7532 /* This symbol may be referenced via a displacement from the PIC
7533 base address (@GOTOFF). */
7535 if (reload_in_progress)
7536 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7537 if (GET_CODE (addr) == CONST)
7538 addr = XEXP (addr, 0);
7539 if (GET_CODE (addr) == PLUS)
7541 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7543 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7546 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7547 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7549 tmpreg = gen_reg_rtx (Pmode);
7552 emit_move_insn (tmpreg, new_rtx);
7556 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7557 tmpreg, 1, OPTAB_DIRECT);
7560 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7562 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7564 /* This symbol may be referenced via a displacement from the PIC
7565 base address (@GOTOFF). */
7567 if (reload_in_progress)
7568 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7569 if (GET_CODE (addr) == CONST)
7570 addr = XEXP (addr, 0);
7571 if (GET_CODE (addr) == PLUS)
7573 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7575 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7578 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7579 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7580 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7584 emit_move_insn (reg, new_rtx);
7588 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7589 /* We can't use @GOTOFF for text labels on VxWorks;
7590 see gotoff_operand. */
7591 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7593 /* Given that we've already handled dllimport variables separately
7594 in legitimize_address, and all other variables should satisfy
7595 legitimate_pic_address_disp_p, we should never arrive here. */
7596 gcc_assert (!TARGET_64BIT_MS_ABI);
7598 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7600 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7601 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7602 new_rtx = gen_const_mem (Pmode, new_rtx);
7603 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7606 reg = gen_reg_rtx (Pmode);
7607 /* Use directly gen_movsi, otherwise the address is loaded
7608 into register for CSE. We don't want to CSE this addresses,
7609 instead we CSE addresses from the GOT table, so skip this. */
7610 emit_insn (gen_movsi (reg, new_rtx));
7615 /* This symbol must be referenced via a load from the
7616 Global Offset Table (@GOT). */
7618 if (reload_in_progress)
7619 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7620 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7621 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7623 new_rtx = force_reg (Pmode, new_rtx);
7624 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7625 new_rtx = gen_const_mem (Pmode, new_rtx);
7626 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7629 reg = gen_reg_rtx (Pmode);
7630 emit_move_insn (reg, new_rtx);
7636 if (CONST_INT_P (addr)
7637 && !x86_64_immediate_operand (addr, VOIDmode))
7641 emit_move_insn (reg, addr);
7645 new_rtx = force_reg (Pmode, addr);
7647 else if (GET_CODE (addr) == CONST)
7649 addr = XEXP (addr, 0);
7651 /* We must match stuff we generate before. Assume the only
7652 unspecs that can get here are ours. Not that we could do
7653 anything with them anyway.... */
7654 if (GET_CODE (addr) == UNSPEC
7655 || (GET_CODE (addr) == PLUS
7656 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7658 gcc_assert (GET_CODE (addr) == PLUS);
7660 if (GET_CODE (addr) == PLUS)
7662 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7664 /* Check first to see if this is a constant offset from a @GOTOFF
7665 symbol reference. */
7666 if (gotoff_operand (op0, Pmode)
7667 && CONST_INT_P (op1))
7671 if (reload_in_progress)
7672 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7673 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7675 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7676 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7677 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7681 emit_move_insn (reg, new_rtx);
7687 if (INTVAL (op1) < -16*1024*1024
7688 || INTVAL (op1) >= 16*1024*1024)
7690 if (!x86_64_immediate_operand (op1, Pmode))
7691 op1 = force_reg (Pmode, op1);
7692 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7698 base = legitimize_pic_address (XEXP (addr, 0), reg);
7699 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7700 base == reg ? NULL_RTX : reg);
7702 if (CONST_INT_P (new_rtx))
7703 new_rtx = plus_constant (base, INTVAL (new_rtx));
7706 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7708 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7709 new_rtx = XEXP (new_rtx, 1);
7711 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7719 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7722 get_thread_pointer (int to_reg)
7726 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7730 reg = gen_reg_rtx (Pmode);
7731 insn = gen_rtx_SET (VOIDmode, reg, tp);
7732 insn = emit_insn (insn);
7737 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7738 false if we expect this to be used for a memory address and true if
7739 we expect to load the address into a register. */
7742 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7744 rtx dest, base, off, pic, tp;
7749 case TLS_MODEL_GLOBAL_DYNAMIC:
7750 dest = gen_reg_rtx (Pmode);
7751 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7753 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7755 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
7758 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7759 insns = get_insns ();
7762 CONST_OR_PURE_CALL_P (insns) = 1;
7763 emit_libcall_block (insns, dest, rax, x);
7765 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7766 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7768 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7770 if (TARGET_GNU2_TLS)
7772 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7774 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7778 case TLS_MODEL_LOCAL_DYNAMIC:
7779 base = gen_reg_rtx (Pmode);
7780 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7782 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7784 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
7787 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7788 insns = get_insns ();
7791 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7792 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7793 CONST_OR_PURE_CALL_P (insns) = 1;
7794 emit_libcall_block (insns, base, rax, note);
7796 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7797 emit_insn (gen_tls_local_dynamic_base_64 (base));
7799 emit_insn (gen_tls_local_dynamic_base_32 (base));
7801 if (TARGET_GNU2_TLS)
7803 rtx x = ix86_tls_module_base ();
7805 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7806 gen_rtx_MINUS (Pmode, x, tp));
7809 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7810 off = gen_rtx_CONST (Pmode, off);
7812 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7814 if (TARGET_GNU2_TLS)
7816 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7818 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7823 case TLS_MODEL_INITIAL_EXEC:
7827 type = UNSPEC_GOTNTPOFF;
7831 if (reload_in_progress)
7832 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7833 pic = pic_offset_table_rtx;
7834 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7836 else if (!TARGET_ANY_GNU_TLS)
7838 pic = gen_reg_rtx (Pmode);
7839 emit_insn (gen_set_got (pic));
7840 type = UNSPEC_GOTTPOFF;
7845 type = UNSPEC_INDNTPOFF;
7848 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7849 off = gen_rtx_CONST (Pmode, off);
7851 off = gen_rtx_PLUS (Pmode, pic, off);
7852 off = gen_const_mem (Pmode, off);
7853 set_mem_alias_set (off, ix86_GOT_alias_set ());
7855 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7857 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7858 off = force_reg (Pmode, off);
7859 return gen_rtx_PLUS (Pmode, base, off);
7863 base = get_thread_pointer (true);
7864 dest = gen_reg_rtx (Pmode);
7865 emit_insn (gen_subsi3 (dest, base, off));
7869 case TLS_MODEL_LOCAL_EXEC:
7870 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7871 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7872 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7873 off = gen_rtx_CONST (Pmode, off);
7875 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7877 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7878 return gen_rtx_PLUS (Pmode, base, off);
7882 base = get_thread_pointer (true);
7883 dest = gen_reg_rtx (Pmode);
7884 emit_insn (gen_subsi3 (dest, base, off));
7895 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7898 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
7899 htab_t dllimport_map;
7902 get_dllimport_decl (tree decl)
7904 struct tree_map *h, in;
7908 size_t namelen, prefixlen;
7914 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
7916 in.hash = htab_hash_pointer (decl);
7917 in.base.from = decl;
7918 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
7919 h = (struct tree_map *) *loc;
7923 *loc = h = GGC_NEW (struct tree_map);
7925 h->base.from = decl;
7926 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
7927 DECL_ARTIFICIAL (to) = 1;
7928 DECL_IGNORED_P (to) = 1;
7929 DECL_EXTERNAL (to) = 1;
7930 TREE_READONLY (to) = 1;
7932 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
7933 name = targetm.strip_name_encoding (name);
7934 prefix = name[0] == FASTCALL_PREFIX ? "*__imp_": "*__imp__";
7935 namelen = strlen (name);
7936 prefixlen = strlen (prefix);
7937 imp_name = (char *) alloca (namelen + prefixlen + 1);
7938 memcpy (imp_name, prefix, prefixlen);
7939 memcpy (imp_name + prefixlen, name, namelen + 1);
7941 name = ggc_alloc_string (imp_name, namelen + prefixlen);
7942 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
7943 SET_SYMBOL_REF_DECL (rtl, to);
7944 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
7946 rtl = gen_const_mem (Pmode, rtl);
7947 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
7949 SET_DECL_RTL (to, rtl);
7950 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
7955 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
7956 true if we require the result be a register. */
7959 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
7964 gcc_assert (SYMBOL_REF_DECL (symbol));
7965 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
7967 x = DECL_RTL (imp_decl);
7969 x = force_reg (Pmode, x);
7973 /* Try machine-dependent ways of modifying an illegitimate address
7974 to be legitimate. If we find one, return the new, valid address.
7975 This macro is used in only one place: `memory_address' in explow.c.
7977 OLDX is the address as it was before break_out_memory_refs was called.
7978 In some cases it is useful to look at this to decide what needs to be done.
7980 MODE and WIN are passed so that this macro can use
7981 GO_IF_LEGITIMATE_ADDRESS.
7983 It is always safe for this macro to do nothing. It exists to recognize
7984 opportunities to optimize the output.
7986 For the 80386, we handle X+REG by loading X into a register R and
7987 using R+REG. R will go in a general reg and indexing will be used.
7988 However, if REG is a broken-out memory address or multiplication,
7989 nothing needs to be done because REG can certainly go in a general reg.
7991 When -fpic is used, special handling is needed for symbolic references.
7992 See comments by legitimize_pic_address in i386.c for details. */
7995 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
8000 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
8002 return legitimize_tls_address (x, (enum tls_model) log, false);
8003 if (GET_CODE (x) == CONST
8004 && GET_CODE (XEXP (x, 0)) == PLUS
8005 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8006 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
8008 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
8009 (enum tls_model) log, false);
8010 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8013 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
8015 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
8016 return legitimize_dllimport_symbol (x, true);
8017 if (GET_CODE (x) == CONST
8018 && GET_CODE (XEXP (x, 0)) == PLUS
8019 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8020 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
8022 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
8023 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8027 if (flag_pic && SYMBOLIC_CONST (x))
8028 return legitimize_pic_address (x, 0);
8030 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
8031 if (GET_CODE (x) == ASHIFT
8032 && CONST_INT_P (XEXP (x, 1))
8033 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
8036 log = INTVAL (XEXP (x, 1));
8037 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
8038 GEN_INT (1 << log));
8041 if (GET_CODE (x) == PLUS)
8043 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
8045 if (GET_CODE (XEXP (x, 0)) == ASHIFT
8046 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8047 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
8050 log = INTVAL (XEXP (XEXP (x, 0), 1));
8051 XEXP (x, 0) = gen_rtx_MULT (Pmode,
8052 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
8053 GEN_INT (1 << log));
8056 if (GET_CODE (XEXP (x, 1)) == ASHIFT
8057 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
8058 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
8061 log = INTVAL (XEXP (XEXP (x, 1), 1));
8062 XEXP (x, 1) = gen_rtx_MULT (Pmode,
8063 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
8064 GEN_INT (1 << log));
8067 /* Put multiply first if it isn't already. */
8068 if (GET_CODE (XEXP (x, 1)) == MULT)
8070 rtx tmp = XEXP (x, 0);
8071 XEXP (x, 0) = XEXP (x, 1);
8076 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
8077 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
8078 created by virtual register instantiation, register elimination, and
8079 similar optimizations. */
8080 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
8083 x = gen_rtx_PLUS (Pmode,
8084 gen_rtx_PLUS (Pmode, XEXP (x, 0),
8085 XEXP (XEXP (x, 1), 0)),
8086 XEXP (XEXP (x, 1), 1));
8090 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
8091 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
8092 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
8093 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
8094 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
8095 && CONSTANT_P (XEXP (x, 1)))
8098 rtx other = NULL_RTX;
8100 if (CONST_INT_P (XEXP (x, 1)))
8102 constant = XEXP (x, 1);
8103 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
8105 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
8107 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
8108 other = XEXP (x, 1);
8116 x = gen_rtx_PLUS (Pmode,
8117 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
8118 XEXP (XEXP (XEXP (x, 0), 1), 0)),
8119 plus_constant (other, INTVAL (constant)));
8123 if (changed && legitimate_address_p (mode, x, FALSE))
8126 if (GET_CODE (XEXP (x, 0)) == MULT)
8129 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
8132 if (GET_CODE (XEXP (x, 1)) == MULT)
8135 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
8139 && REG_P (XEXP (x, 1))
8140 && REG_P (XEXP (x, 0)))
8143 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
8146 x = legitimize_pic_address (x, 0);
8149 if (changed && legitimate_address_p (mode, x, FALSE))
8152 if (REG_P (XEXP (x, 0)))
8154 rtx temp = gen_reg_rtx (Pmode);
8155 rtx val = force_operand (XEXP (x, 1), temp);
8157 emit_move_insn (temp, val);
8163 else if (REG_P (XEXP (x, 1)))
8165 rtx temp = gen_reg_rtx (Pmode);
8166 rtx val = force_operand (XEXP (x, 0), temp);
8168 emit_move_insn (temp, val);
8178 /* Print an integer constant expression in assembler syntax. Addition
8179 and subtraction are the only arithmetic that may appear in these
8180 expressions. FILE is the stdio stream to write to, X is the rtx, and
8181 CODE is the operand print code from the output string. */
8184 output_pic_addr_const (FILE *file, rtx x, int code)
8188 switch (GET_CODE (x))
8191 gcc_assert (flag_pic);
8196 if (! TARGET_MACHO || TARGET_64BIT)
8197 output_addr_const (file, x);
8200 const char *name = XSTR (x, 0);
8202 /* Mark the decl as referenced so that cgraph will
8203 output the function. */
8204 if (SYMBOL_REF_DECL (x))
8205 mark_decl_referenced (SYMBOL_REF_DECL (x));
8208 if (MACHOPIC_INDIRECT
8209 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
8210 name = machopic_indirection_name (x, /*stub_p=*/true);
8212 assemble_name (file, name);
8214 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
8215 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
8216 fputs ("@PLT", file);
8223 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
8224 assemble_name (asm_out_file, buf);
8228 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8232 /* This used to output parentheses around the expression,
8233 but that does not work on the 386 (either ATT or BSD assembler). */
8234 output_pic_addr_const (file, XEXP (x, 0), code);
8238 if (GET_MODE (x) == VOIDmode)
8240 /* We can use %d if the number is <32 bits and positive. */
8241 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
8242 fprintf (file, "0x%lx%08lx",
8243 (unsigned long) CONST_DOUBLE_HIGH (x),
8244 (unsigned long) CONST_DOUBLE_LOW (x));
8246 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
8249 /* We can't handle floating point constants;
8250 PRINT_OPERAND must handle them. */
8251 output_operand_lossage ("floating constant misused");
8255 /* Some assemblers need integer constants to appear first. */
8256 if (CONST_INT_P (XEXP (x, 0)))
8258 output_pic_addr_const (file, XEXP (x, 0), code);
8260 output_pic_addr_const (file, XEXP (x, 1), code);
8264 gcc_assert (CONST_INT_P (XEXP (x, 1)));
8265 output_pic_addr_const (file, XEXP (x, 1), code);
8267 output_pic_addr_const (file, XEXP (x, 0), code);
8273 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
8274 output_pic_addr_const (file, XEXP (x, 0), code);
8276 output_pic_addr_const (file, XEXP (x, 1), code);
8278 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
8282 gcc_assert (XVECLEN (x, 0) == 1);
8283 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
8284 switch (XINT (x, 1))
8287 fputs ("@GOT", file);
8290 fputs ("@GOTOFF", file);
8293 fputs ("@PLTOFF", file);
8295 case UNSPEC_GOTPCREL:
8296 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8297 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
8299 case UNSPEC_GOTTPOFF:
8300 /* FIXME: This might be @TPOFF in Sun ld too. */
8301 fputs ("@GOTTPOFF", file);
8304 fputs ("@TPOFF", file);
8308 fputs ("@TPOFF", file);
8310 fputs ("@NTPOFF", file);
8313 fputs ("@DTPOFF", file);
8315 case UNSPEC_GOTNTPOFF:
8317 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8318 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
8320 fputs ("@GOTNTPOFF", file);
8322 case UNSPEC_INDNTPOFF:
8323 fputs ("@INDNTPOFF", file);
8326 output_operand_lossage ("invalid UNSPEC as operand");
8332 output_operand_lossage ("invalid expression as operand");
8336 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8337 We need to emit DTP-relative relocations. */
8339 static void ATTRIBUTE_UNUSED
8340 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8342 fputs (ASM_LONG, file);
8343 output_addr_const (file, x);
8344 fputs ("@DTPOFF", file);
8350 fputs (", 0", file);
8357 /* In the name of slightly smaller debug output, and to cater to
8358 general assembler lossage, recognize PIC+GOTOFF and turn it back
8359 into a direct symbol reference.
8361 On Darwin, this is necessary to avoid a crash, because Darwin
8362 has a different PIC label for each routine but the DWARF debugging
8363 information is not associated with any particular routine, so it's
8364 necessary to remove references to the PIC label from RTL stored by
8365 the DWARF output code. */
8368 ix86_delegitimize_address (rtx orig_x)
8371 /* reg_addend is NULL or a multiple of some register. */
8372 rtx reg_addend = NULL_RTX;
8373 /* const_addend is NULL or a const_int. */
8374 rtx const_addend = NULL_RTX;
8375 /* This is the result, or NULL. */
8376 rtx result = NULL_RTX;
8383 if (GET_CODE (x) != CONST
8384 || GET_CODE (XEXP (x, 0)) != UNSPEC
8385 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8388 return XVECEXP (XEXP (x, 0), 0, 0);
8391 if (GET_CODE (x) != PLUS
8392 || GET_CODE (XEXP (x, 1)) != CONST)
8395 if (REG_P (XEXP (x, 0))
8396 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8397 /* %ebx + GOT/GOTOFF */
8399 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8401 /* %ebx + %reg * scale + GOT/GOTOFF */
8402 reg_addend = XEXP (x, 0);
8403 if (REG_P (XEXP (reg_addend, 0))
8404 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8405 reg_addend = XEXP (reg_addend, 1);
8406 else if (REG_P (XEXP (reg_addend, 1))
8407 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8408 reg_addend = XEXP (reg_addend, 0);
8411 if (!REG_P (reg_addend)
8412 && GET_CODE (reg_addend) != MULT
8413 && GET_CODE (reg_addend) != ASHIFT)
8419 x = XEXP (XEXP (x, 1), 0);
8420 if (GET_CODE (x) == PLUS
8421 && CONST_INT_P (XEXP (x, 1)))
8423 const_addend = XEXP (x, 1);
8427 if (GET_CODE (x) == UNSPEC
8428 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8429 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8430 result = XVECEXP (x, 0, 0);
8432 if (TARGET_MACHO && darwin_local_data_pic (x)
8434 result = XEXP (x, 0);
8440 result = gen_rtx_PLUS (Pmode, result, const_addend);
8442 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8446 /* If X is a machine specific address (i.e. a symbol or label being
8447 referenced as a displacement from the GOT implemented using an
8448 UNSPEC), then return the base term. Otherwise return X. */
8451 ix86_find_base_term (rtx x)
8457 if (GET_CODE (x) != CONST)
8460 if (GET_CODE (term) == PLUS
8461 && (CONST_INT_P (XEXP (term, 1))
8462 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8463 term = XEXP (term, 0);
8464 if (GET_CODE (term) != UNSPEC
8465 || XINT (term, 1) != UNSPEC_GOTPCREL)
8468 term = XVECEXP (term, 0, 0);
8470 if (GET_CODE (term) != SYMBOL_REF
8471 && GET_CODE (term) != LABEL_REF)
8477 term = ix86_delegitimize_address (x);
8479 if (GET_CODE (term) != SYMBOL_REF
8480 && GET_CODE (term) != LABEL_REF)
8487 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8492 if (mode == CCFPmode || mode == CCFPUmode)
8494 enum rtx_code second_code, bypass_code;
8495 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8496 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8497 code = ix86_fp_compare_code_to_integer (code);
8501 code = reverse_condition (code);
8552 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8556 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8557 Those same assemblers have the same but opposite lossage on cmov. */
8559 suffix = fp ? "nbe" : "a";
8560 else if (mode == CCCmode)
8583 gcc_assert (mode == CCmode || mode == CCCmode);
8605 gcc_assert (mode == CCmode || mode == CCCmode);
8606 suffix = fp ? "nb" : "ae";
8609 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8616 else if (mode == CCCmode)
8617 suffix = fp ? "nb" : "ae";
8622 suffix = fp ? "u" : "p";
8625 suffix = fp ? "nu" : "np";
8630 fputs (suffix, file);
8633 /* Print the name of register X to FILE based on its machine mode and number.
8634 If CODE is 'w', pretend the mode is HImode.
8635 If CODE is 'b', pretend the mode is QImode.
8636 If CODE is 'k', pretend the mode is SImode.
8637 If CODE is 'q', pretend the mode is DImode.
8638 If CODE is 'h', pretend the reg is the 'high' byte register.
8639 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8642 print_reg (rtx x, int code, FILE *file)
8644 gcc_assert (x == pc_rtx
8645 || (REGNO (x) != ARG_POINTER_REGNUM
8646 && REGNO (x) != FRAME_POINTER_REGNUM
8647 && REGNO (x) != FLAGS_REG
8648 && REGNO (x) != FPSR_REG
8649 && REGNO (x) != FPCR_REG));
8651 if (ASSEMBLER_DIALECT == ASM_ATT)
8656 gcc_assert (TARGET_64BIT);
8657 fputs ("rip", file);
8661 if (code == 'w' || MMX_REG_P (x))
8663 else if (code == 'b')
8665 else if (code == 'k')
8667 else if (code == 'q')
8669 else if (code == 'y')
8671 else if (code == 'h')
8674 code = GET_MODE_SIZE (GET_MODE (x));
8676 /* Irritatingly, AMD extended registers use different naming convention
8677 from the normal registers. */
8678 if (REX_INT_REG_P (x))
8680 gcc_assert (TARGET_64BIT);
8684 error ("extended registers have no high halves");
8687 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8690 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8693 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8696 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8699 error ("unsupported operand size for extended register");
8707 if (STACK_TOP_P (x))
8709 fputs ("st(0)", file);
8716 if (! ANY_FP_REG_P (x))
8717 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8722 fputs (hi_reg_name[REGNO (x)], file);
8725 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8727 fputs (qi_reg_name[REGNO (x)], file);
8730 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8732 fputs (qi_high_reg_name[REGNO (x)], file);
8739 /* Locate some local-dynamic symbol still in use by this function
8740 so that we can print its name in some tls_local_dynamic_base
8744 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8748 if (GET_CODE (x) == SYMBOL_REF
8749 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8751 cfun->machine->some_ld_name = XSTR (x, 0);
8759 get_some_local_dynamic_name (void)
8763 if (cfun->machine->some_ld_name)
8764 return cfun->machine->some_ld_name;
8766 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8768 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8769 return cfun->machine->some_ld_name;
8775 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8776 C -- print opcode suffix for set/cmov insn.
8777 c -- like C, but print reversed condition
8778 F,f -- likewise, but for floating-point.
8779 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8781 R -- print the prefix for register names.
8782 z -- print the opcode suffix for the size of the current operand.
8783 * -- print a star (in certain assembler syntax)
8784 A -- print an absolute memory reference.
8785 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8786 s -- print a shift double count, followed by the assemblers argument
8788 b -- print the QImode name of the register for the indicated operand.
8789 %b0 would print %al if operands[0] is reg 0.
8790 w -- likewise, print the HImode name of the register.
8791 k -- likewise, print the SImode name of the register.
8792 q -- likewise, print the DImode name of the register.
8793 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8794 y -- print "st(0)" instead of "st" as a register.
8795 D -- print condition for SSE cmp instruction.
8796 P -- if PIC, print an @PLT suffix.
8797 X -- don't print any sort of PIC '@' suffix for a symbol.
8798 & -- print some in-use local-dynamic symbol name.
8799 H -- print a memory address offset by 8; used for sse high-parts
8800 Y -- print condition for SSE5 com* instruction.
8801 + -- print a branch hint as 'cs' or 'ds' prefix
8802 ; -- print a semicolon (after prefixes due to bug in older gas).
8806 print_operand (FILE *file, rtx x, int code)
8813 if (ASSEMBLER_DIALECT == ASM_ATT)
8818 assemble_name (file, get_some_local_dynamic_name ());
8822 switch (ASSEMBLER_DIALECT)
8829 /* Intel syntax. For absolute addresses, registers should not
8830 be surrounded by braces. */
8834 PRINT_OPERAND (file, x, 0);
8844 PRINT_OPERAND (file, x, 0);
8849 if (ASSEMBLER_DIALECT == ASM_ATT)
8854 if (ASSEMBLER_DIALECT == ASM_ATT)
8859 if (ASSEMBLER_DIALECT == ASM_ATT)
8864 if (ASSEMBLER_DIALECT == ASM_ATT)
8869 if (ASSEMBLER_DIALECT == ASM_ATT)
8874 if (ASSEMBLER_DIALECT == ASM_ATT)
8879 /* 387 opcodes don't get size suffixes if the operands are
8881 if (STACK_REG_P (x))
8884 /* Likewise if using Intel opcodes. */
8885 if (ASSEMBLER_DIALECT == ASM_INTEL)
8888 /* This is the size of op from size of operand. */
8889 switch (GET_MODE_SIZE (GET_MODE (x)))
8898 #ifdef HAVE_GAS_FILDS_FISTS
8908 if (GET_MODE (x) == SFmode)
8923 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
8925 #ifdef GAS_MNEMONICS
8951 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
8953 PRINT_OPERAND (file, x, 0);
8959 /* Little bit of braindamage here. The SSE compare instructions
8960 does use completely different names for the comparisons that the
8961 fp conditional moves. */
8962 switch (GET_CODE (x))
8977 fputs ("unord", file);
8981 fputs ("neq", file);
8985 fputs ("nlt", file);
8989 fputs ("nle", file);
8992 fputs ("ord", file);
8999 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9000 if (ASSEMBLER_DIALECT == ASM_ATT)
9002 switch (GET_MODE (x))
9004 case HImode: putc ('w', file); break;
9006 case SFmode: putc ('l', file); break;
9008 case DFmode: putc ('q', file); break;
9009 default: gcc_unreachable ();
9016 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
9019 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9020 if (ASSEMBLER_DIALECT == ASM_ATT)
9023 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
9026 /* Like above, but reverse condition */
9028 /* Check to see if argument to %c is really a constant
9029 and not a condition code which needs to be reversed. */
9030 if (!COMPARISON_P (x))
9032 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
9035 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
9038 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9039 if (ASSEMBLER_DIALECT == ASM_ATT)
9042 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
9046 /* It doesn't actually matter what mode we use here, as we're
9047 only going to use this for printing. */
9048 x = adjust_address_nv (x, DImode, 8);
9055 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
9058 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
9061 int pred_val = INTVAL (XEXP (x, 0));
9063 if (pred_val < REG_BR_PROB_BASE * 45 / 100
9064 || pred_val > REG_BR_PROB_BASE * 55 / 100)
9066 int taken = pred_val > REG_BR_PROB_BASE / 2;
9067 int cputaken = final_forward_branch_p (current_output_insn) == 0;
9069 /* Emit hints only in the case default branch prediction
9070 heuristics would fail. */
9071 if (taken != cputaken)
9073 /* We use 3e (DS) prefix for taken branches and
9074 2e (CS) prefix for not taken branches. */
9076 fputs ("ds ; ", file);
9078 fputs ("cs ; ", file);
9086 switch (GET_CODE (x))
9089 fputs ("neq", file);
9096 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
9100 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
9111 fputs ("unord", file);
9114 fputs ("ord", file);
9117 fputs ("ueq", file);
9120 fputs ("nlt", file);
9123 fputs ("nle", file);
9126 fputs ("ule", file);
9129 fputs ("ult", file);
9132 fputs ("une", file);
9141 fputs (" ; ", file);
9148 output_operand_lossage ("invalid operand code '%c'", code);
9153 print_reg (x, code, file);
9157 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
9158 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
9159 && GET_MODE (x) != BLKmode)
9162 switch (GET_MODE_SIZE (GET_MODE (x)))
9164 case 1: size = "BYTE"; break;
9165 case 2: size = "WORD"; break;
9166 case 4: size = "DWORD"; break;
9167 case 8: size = "QWORD"; break;
9168 case 12: size = "XWORD"; break;
9170 if (GET_MODE (x) == XFmode)
9179 /* Check for explicit size override (codes 'b', 'w' and 'k') */
9182 else if (code == 'w')
9184 else if (code == 'k')
9188 fputs (" PTR ", file);
9192 /* Avoid (%rip) for call operands. */
9193 if (CONSTANT_ADDRESS_P (x) && code == 'P'
9194 && !CONST_INT_P (x))
9195 output_addr_const (file, x);
9196 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
9197 output_operand_lossage ("invalid constraints for operand");
9202 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9207 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9208 REAL_VALUE_TO_TARGET_SINGLE (r, l);
9210 if (ASSEMBLER_DIALECT == ASM_ATT)
9212 fprintf (file, "0x%08lx", l);
9215 /* These float cases don't actually occur as immediate operands. */
9216 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9220 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9221 fprintf (file, "%s", dstr);
9224 else if (GET_CODE (x) == CONST_DOUBLE
9225 && GET_MODE (x) == XFmode)
9229 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9230 fprintf (file, "%s", dstr);
9235 /* We have patterns that allow zero sets of memory, for instance.
9236 In 64-bit mode, we should probably support all 8-byte vectors,
9237 since we can in fact encode that into an immediate. */
9238 if (GET_CODE (x) == CONST_VECTOR)
9240 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
9246 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
9248 if (ASSEMBLER_DIALECT == ASM_ATT)
9251 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
9252 || GET_CODE (x) == LABEL_REF)
9254 if (ASSEMBLER_DIALECT == ASM_ATT)
9257 fputs ("OFFSET FLAT:", file);
9260 if (CONST_INT_P (x))
9261 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9263 output_pic_addr_const (file, x, code);
9265 output_addr_const (file, x);
9269 /* Print a memory operand whose address is ADDR. */
9272 print_operand_address (FILE *file, rtx addr)
9274 struct ix86_address parts;
9275 rtx base, index, disp;
9277 int ok = ix86_decompose_address (addr, &parts);
9282 index = parts.index;
9284 scale = parts.scale;
9292 if (ASSEMBLER_DIALECT == ASM_ATT)
9294 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
9300 /* Use one byte shorter RIP relative addressing for 64bit mode. */
9301 if (TARGET_64BIT && !base && !index)
9305 if (GET_CODE (disp) == CONST
9306 && GET_CODE (XEXP (disp, 0)) == PLUS
9307 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9308 symbol = XEXP (XEXP (disp, 0), 0);
9310 if (GET_CODE (symbol) == LABEL_REF
9311 || (GET_CODE (symbol) == SYMBOL_REF
9312 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
9315 if (!base && !index)
9317 /* Displacement only requires special attention. */
9319 if (CONST_INT_P (disp))
9321 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
9322 fputs ("ds:", file);
9323 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
9326 output_pic_addr_const (file, disp, 0);
9328 output_addr_const (file, disp);
9332 if (ASSEMBLER_DIALECT == ASM_ATT)
9337 output_pic_addr_const (file, disp, 0);
9338 else if (GET_CODE (disp) == LABEL_REF)
9339 output_asm_label (disp);
9341 output_addr_const (file, disp);
9346 print_reg (base, 0, file);
9350 print_reg (index, 0, file);
9352 fprintf (file, ",%d", scale);
9358 rtx offset = NULL_RTX;
9362 /* Pull out the offset of a symbol; print any symbol itself. */
9363 if (GET_CODE (disp) == CONST
9364 && GET_CODE (XEXP (disp, 0)) == PLUS
9365 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9367 offset = XEXP (XEXP (disp, 0), 1);
9368 disp = gen_rtx_CONST (VOIDmode,
9369 XEXP (XEXP (disp, 0), 0));
9373 output_pic_addr_const (file, disp, 0);
9374 else if (GET_CODE (disp) == LABEL_REF)
9375 output_asm_label (disp);
9376 else if (CONST_INT_P (disp))
9379 output_addr_const (file, disp);
9385 print_reg (base, 0, file);
9388 if (INTVAL (offset) >= 0)
9390 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9394 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9401 print_reg (index, 0, file);
9403 fprintf (file, "*%d", scale);
9411 output_addr_const_extra (FILE *file, rtx x)
9415 if (GET_CODE (x) != UNSPEC)
9418 op = XVECEXP (x, 0, 0);
9419 switch (XINT (x, 1))
9421 case UNSPEC_GOTTPOFF:
9422 output_addr_const (file, op);
9423 /* FIXME: This might be @TPOFF in Sun ld. */
9424 fputs ("@GOTTPOFF", file);
9427 output_addr_const (file, op);
9428 fputs ("@TPOFF", file);
9431 output_addr_const (file, op);
9433 fputs ("@TPOFF", file);
9435 fputs ("@NTPOFF", file);
9438 output_addr_const (file, op);
9439 fputs ("@DTPOFF", file);
9441 case UNSPEC_GOTNTPOFF:
9442 output_addr_const (file, op);
9444 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9445 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
9447 fputs ("@GOTNTPOFF", file);
9449 case UNSPEC_INDNTPOFF:
9450 output_addr_const (file, op);
9451 fputs ("@INDNTPOFF", file);
9461 /* Split one or more DImode RTL references into pairs of SImode
9462 references. The RTL can be REG, offsettable MEM, integer constant, or
9463 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9464 split and "num" is its length. lo_half and hi_half are output arrays
9465 that parallel "operands". */
9468 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9472 rtx op = operands[num];
9474 /* simplify_subreg refuse to split volatile memory addresses,
9475 but we still have to handle it. */
9478 lo_half[num] = adjust_address (op, SImode, 0);
9479 hi_half[num] = adjust_address (op, SImode, 4);
9483 lo_half[num] = simplify_gen_subreg (SImode, op,
9484 GET_MODE (op) == VOIDmode
9485 ? DImode : GET_MODE (op), 0);
9486 hi_half[num] = simplify_gen_subreg (SImode, op,
9487 GET_MODE (op) == VOIDmode
9488 ? DImode : GET_MODE (op), 4);
9492 /* Split one or more TImode RTL references into pairs of DImode
9493 references. The RTL can be REG, offsettable MEM, integer constant, or
9494 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9495 split and "num" is its length. lo_half and hi_half are output arrays
9496 that parallel "operands". */
9499 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9503 rtx op = operands[num];
9505 /* simplify_subreg refuse to split volatile memory addresses, but we
9506 still have to handle it. */
9509 lo_half[num] = adjust_address (op, DImode, 0);
9510 hi_half[num] = adjust_address (op, DImode, 8);
9514 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9515 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9520 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9521 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9522 is the expression of the binary operation. The output may either be
9523 emitted here, or returned to the caller, like all output_* functions.
9525 There is no guarantee that the operands are the same mode, as they
9526 might be within FLOAT or FLOAT_EXTEND expressions. */
9528 #ifndef SYSV386_COMPAT
9529 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9530 wants to fix the assemblers because that causes incompatibility
9531 with gcc. No-one wants to fix gcc because that causes
9532 incompatibility with assemblers... You can use the option of
9533 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9534 #define SYSV386_COMPAT 1
9538 output_387_binary_op (rtx insn, rtx *operands)
9540 static char buf[30];
9543 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9545 #ifdef ENABLE_CHECKING
9546 /* Even if we do not want to check the inputs, this documents input
9547 constraints. Which helps in understanding the following code. */
9548 if (STACK_REG_P (operands[0])
9549 && ((REG_P (operands[1])
9550 && REGNO (operands[0]) == REGNO (operands[1])
9551 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9552 || (REG_P (operands[2])
9553 && REGNO (operands[0]) == REGNO (operands[2])
9554 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9555 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9558 gcc_assert (is_sse);
9561 switch (GET_CODE (operands[3]))
9564 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9565 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9573 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9574 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9582 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9583 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9591 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9592 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9606 if (GET_MODE (operands[0]) == SFmode)
9607 strcat (buf, "ss\t{%2, %0|%0, %2}");
9609 strcat (buf, "sd\t{%2, %0|%0, %2}");
9614 switch (GET_CODE (operands[3]))
9618 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9620 rtx temp = operands[2];
9621 operands[2] = operands[1];
9625 /* know operands[0] == operands[1]. */
9627 if (MEM_P (operands[2]))
9633 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9635 if (STACK_TOP_P (operands[0]))
9636 /* How is it that we are storing to a dead operand[2]?
9637 Well, presumably operands[1] is dead too. We can't
9638 store the result to st(0) as st(0) gets popped on this
9639 instruction. Instead store to operands[2] (which I
9640 think has to be st(1)). st(1) will be popped later.
9641 gcc <= 2.8.1 didn't have this check and generated
9642 assembly code that the Unixware assembler rejected. */
9643 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9645 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9649 if (STACK_TOP_P (operands[0]))
9650 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9652 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9657 if (MEM_P (operands[1]))
9663 if (MEM_P (operands[2]))
9669 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9672 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9673 derived assemblers, confusingly reverse the direction of
9674 the operation for fsub{r} and fdiv{r} when the
9675 destination register is not st(0). The Intel assembler
9676 doesn't have this brain damage. Read !SYSV386_COMPAT to
9677 figure out what the hardware really does. */
9678 if (STACK_TOP_P (operands[0]))
9679 p = "{p\t%0, %2|rp\t%2, %0}";
9681 p = "{rp\t%2, %0|p\t%0, %2}";
9683 if (STACK_TOP_P (operands[0]))
9684 /* As above for fmul/fadd, we can't store to st(0). */
9685 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9687 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9692 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9695 if (STACK_TOP_P (operands[0]))
9696 p = "{rp\t%0, %1|p\t%1, %0}";
9698 p = "{p\t%1, %0|rp\t%0, %1}";
9700 if (STACK_TOP_P (operands[0]))
9701 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9703 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9708 if (STACK_TOP_P (operands[0]))
9710 if (STACK_TOP_P (operands[1]))
9711 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9713 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9716 else if (STACK_TOP_P (operands[1]))
9719 p = "{\t%1, %0|r\t%0, %1}";
9721 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9727 p = "{r\t%2, %0|\t%0, %2}";
9729 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9742 /* Return needed mode for entity in optimize_mode_switching pass. */
9745 ix86_mode_needed (int entity, rtx insn)
9747 enum attr_i387_cw mode;
9749 /* The mode UNINITIALIZED is used to store control word after a
9750 function call or ASM pattern. The mode ANY specify that function
9751 has no requirements on the control word and make no changes in the
9752 bits we are interested in. */
9755 || (NONJUMP_INSN_P (insn)
9756 && (asm_noperands (PATTERN (insn)) >= 0
9757 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9758 return I387_CW_UNINITIALIZED;
9760 if (recog_memoized (insn) < 0)
9763 mode = get_attr_i387_cw (insn);
9768 if (mode == I387_CW_TRUNC)
9773 if (mode == I387_CW_FLOOR)
9778 if (mode == I387_CW_CEIL)
9783 if (mode == I387_CW_MASK_PM)
9794 /* Output code to initialize control word copies used by trunc?f?i and
9795 rounding patterns. CURRENT_MODE is set to current control word,
9796 while NEW_MODE is set to new control word. */
9799 emit_i387_cw_initialization (int mode)
9801 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9804 enum ix86_stack_slot slot;
9806 rtx reg = gen_reg_rtx (HImode);
9808 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9809 emit_move_insn (reg, copy_rtx (stored_mode));
9811 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9816 /* round toward zero (truncate) */
9817 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9818 slot = SLOT_CW_TRUNC;
9822 /* round down toward -oo */
9823 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9824 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9825 slot = SLOT_CW_FLOOR;
9829 /* round up toward +oo */
9830 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9831 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9832 slot = SLOT_CW_CEIL;
9835 case I387_CW_MASK_PM:
9836 /* mask precision exception for nearbyint() */
9837 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9838 slot = SLOT_CW_MASK_PM;
9850 /* round toward zero (truncate) */
9851 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9852 slot = SLOT_CW_TRUNC;
9856 /* round down toward -oo */
9857 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9858 slot = SLOT_CW_FLOOR;
9862 /* round up toward +oo */
9863 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9864 slot = SLOT_CW_CEIL;
9867 case I387_CW_MASK_PM:
9868 /* mask precision exception for nearbyint() */
9869 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9870 slot = SLOT_CW_MASK_PM;
9878 gcc_assert (slot < MAX_386_STACK_LOCALS);
9880 new_mode = assign_386_stack_local (HImode, slot);
9881 emit_move_insn (new_mode, reg);
9884 /* Output code for INSN to convert a float to a signed int. OPERANDS
9885 are the insn operands. The output may be [HSD]Imode and the input
9886 operand may be [SDX]Fmode. */
9889 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
9891 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9892 int dimode_p = GET_MODE (operands[0]) == DImode;
9893 int round_mode = get_attr_i387_cw (insn);
9895 /* Jump through a hoop or two for DImode, since the hardware has no
9896 non-popping instruction. We used to do this a different way, but
9897 that was somewhat fragile and broke with post-reload splitters. */
9898 if ((dimode_p || fisttp) && !stack_top_dies)
9899 output_asm_insn ("fld\t%y1", operands);
9901 gcc_assert (STACK_TOP_P (operands[1]));
9902 gcc_assert (MEM_P (operands[0]));
9903 gcc_assert (GET_MODE (operands[1]) != TFmode);
9906 output_asm_insn ("fisttp%z0\t%0", operands);
9909 if (round_mode != I387_CW_ANY)
9910 output_asm_insn ("fldcw\t%3", operands);
9911 if (stack_top_dies || dimode_p)
9912 output_asm_insn ("fistp%z0\t%0", operands);
9914 output_asm_insn ("fist%z0\t%0", operands);
9915 if (round_mode != I387_CW_ANY)
9916 output_asm_insn ("fldcw\t%2", operands);
9922 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9923 have the values zero or one, indicates the ffreep insn's operand
9924 from the OPERANDS array. */
9927 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
9929 if (TARGET_USE_FFREEP)
9930 #if HAVE_AS_IX86_FFREEP
9931 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
9934 static char retval[] = ".word\t0xc_df";
9935 int regno = REGNO (operands[opno]);
9937 gcc_assert (FP_REGNO_P (regno));
9939 retval[9] = '0' + (regno - FIRST_STACK_REG);
9944 return opno ? "fstp\t%y1" : "fstp\t%y0";
9948 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9949 should be used. UNORDERED_P is true when fucom should be used. */
9952 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
9955 rtx cmp_op0, cmp_op1;
9956 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
9960 cmp_op0 = operands[0];
9961 cmp_op1 = operands[1];
9965 cmp_op0 = operands[1];
9966 cmp_op1 = operands[2];
9971 if (GET_MODE (operands[0]) == SFmode)
9973 return "ucomiss\t{%1, %0|%0, %1}";
9975 return "comiss\t{%1, %0|%0, %1}";
9978 return "ucomisd\t{%1, %0|%0, %1}";
9980 return "comisd\t{%1, %0|%0, %1}";
9983 gcc_assert (STACK_TOP_P (cmp_op0));
9985 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9987 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
9991 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
9992 return output_387_ffreep (operands, 1);
9995 return "ftst\n\tfnstsw\t%0";
9998 if (STACK_REG_P (cmp_op1)
10000 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
10001 && REGNO (cmp_op1) != FIRST_STACK_REG)
10003 /* If both the top of the 387 stack dies, and the other operand
10004 is also a stack register that dies, then this must be a
10005 `fcompp' float compare */
10009 /* There is no double popping fcomi variant. Fortunately,
10010 eflags is immune from the fstp's cc clobbering. */
10012 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
10014 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
10015 return output_387_ffreep (operands, 0);
10020 return "fucompp\n\tfnstsw\t%0";
10022 return "fcompp\n\tfnstsw\t%0";
10027 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
10029 static const char * const alt[16] =
10031 "fcom%z2\t%y2\n\tfnstsw\t%0",
10032 "fcomp%z2\t%y2\n\tfnstsw\t%0",
10033 "fucom%z2\t%y2\n\tfnstsw\t%0",
10034 "fucomp%z2\t%y2\n\tfnstsw\t%0",
10036 "ficom%z2\t%y2\n\tfnstsw\t%0",
10037 "ficomp%z2\t%y2\n\tfnstsw\t%0",
10041 "fcomi\t{%y1, %0|%0, %y1}",
10042 "fcomip\t{%y1, %0|%0, %y1}",
10043 "fucomi\t{%y1, %0|%0, %y1}",
10044 "fucomip\t{%y1, %0|%0, %y1}",
10055 mask = eflags_p << 3;
10056 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
10057 mask |= unordered_p << 1;
10058 mask |= stack_top_dies;
10060 gcc_assert (mask < 16);
10069 ix86_output_addr_vec_elt (FILE *file, int value)
10071 const char *directive = ASM_LONG;
10075 directive = ASM_QUAD;
10077 gcc_assert (!TARGET_64BIT);
10080 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
10084 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
10086 const char *directive = ASM_LONG;
10089 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
10090 directive = ASM_QUAD;
10092 gcc_assert (!TARGET_64BIT);
10094 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
10095 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
10096 fprintf (file, "%s%s%d-%s%d\n",
10097 directive, LPREFIX, value, LPREFIX, rel);
10098 else if (HAVE_AS_GOTOFF_IN_DATA)
10099 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
10101 else if (TARGET_MACHO)
10103 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
10104 machopic_output_function_base_name (file);
10105 fprintf(file, "\n");
10109 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
10110 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
10113 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
10117 ix86_expand_clear (rtx dest)
10121 /* We play register width games, which are only valid after reload. */
10122 gcc_assert (reload_completed);
10124 /* Avoid HImode and its attendant prefix byte. */
10125 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
10126 dest = gen_rtx_REG (SImode, REGNO (dest));
10127 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
10129 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
10130 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
10132 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10133 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
10139 /* X is an unchanging MEM. If it is a constant pool reference, return
10140 the constant pool rtx, else NULL. */
10143 maybe_get_pool_constant (rtx x)
10145 x = ix86_delegitimize_address (XEXP (x, 0));
10147 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
10148 return get_pool_constant (x);
10154 ix86_expand_move (enum machine_mode mode, rtx operands[])
10157 enum tls_model model;
10162 if (GET_CODE (op1) == SYMBOL_REF)
10164 model = SYMBOL_REF_TLS_MODEL (op1);
10167 op1 = legitimize_tls_address (op1, model, true);
10168 op1 = force_operand (op1, op0);
10172 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10173 && SYMBOL_REF_DLLIMPORT_P (op1))
10174 op1 = legitimize_dllimport_symbol (op1, false);
10176 else if (GET_CODE (op1) == CONST
10177 && GET_CODE (XEXP (op1, 0)) == PLUS
10178 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
10180 rtx addend = XEXP (XEXP (op1, 0), 1);
10181 rtx symbol = XEXP (XEXP (op1, 0), 0);
10184 model = SYMBOL_REF_TLS_MODEL (symbol);
10186 tmp = legitimize_tls_address (symbol, model, true);
10187 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10188 && SYMBOL_REF_DLLIMPORT_P (symbol))
10189 tmp = legitimize_dllimport_symbol (symbol, true);
10193 tmp = force_operand (tmp, NULL);
10194 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
10195 op0, 1, OPTAB_DIRECT);
10201 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
10203 if (TARGET_MACHO && !TARGET_64BIT)
10208 rtx temp = ((reload_in_progress
10209 || ((op0 && REG_P (op0))
10211 ? op0 : gen_reg_rtx (Pmode));
10212 op1 = machopic_indirect_data_reference (op1, temp);
10213 op1 = machopic_legitimize_pic_address (op1, mode,
10214 temp == op1 ? 0 : temp);
10216 else if (MACHOPIC_INDIRECT)
10217 op1 = machopic_indirect_data_reference (op1, 0);
10225 op1 = force_reg (Pmode, op1);
10226 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
10228 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
10229 op1 = legitimize_pic_address (op1, reg);
10238 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
10239 || !push_operand (op0, mode))
10241 op1 = force_reg (mode, op1);
10243 if (push_operand (op0, mode)
10244 && ! general_no_elim_operand (op1, mode))
10245 op1 = copy_to_mode_reg (mode, op1);
10247 /* Force large constants in 64bit compilation into register
10248 to get them CSEed. */
10249 if (can_create_pseudo_p ()
10250 && (mode == DImode) && TARGET_64BIT
10251 && immediate_operand (op1, mode)
10252 && !x86_64_zext_immediate_operand (op1, VOIDmode)
10253 && !register_operand (op0, mode)
10255 op1 = copy_to_mode_reg (mode, op1);
10257 if (can_create_pseudo_p ()
10258 && FLOAT_MODE_P (mode)
10259 && GET_CODE (op1) == CONST_DOUBLE)
10261 /* If we are loading a floating point constant to a register,
10262 force the value to memory now, since we'll get better code
10263 out the back end. */
10265 op1 = validize_mem (force_const_mem (mode, op1));
10266 if (!register_operand (op0, mode))
10268 rtx temp = gen_reg_rtx (mode);
10269 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
10270 emit_move_insn (op0, temp);
10276 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10280 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
10282 rtx op0 = operands[0], op1 = operands[1];
10283 unsigned int align = GET_MODE_ALIGNMENT (mode);
10285 /* Force constants other than zero into memory. We do not know how
10286 the instructions used to build constants modify the upper 64 bits
10287 of the register, once we have that information we may be able
10288 to handle some of them more efficiently. */
10289 if (can_create_pseudo_p ()
10290 && register_operand (op0, mode)
10291 && (CONSTANT_P (op1)
10292 || (GET_CODE (op1) == SUBREG
10293 && CONSTANT_P (SUBREG_REG (op1))))
10294 && standard_sse_constant_p (op1) <= 0)
10295 op1 = validize_mem (force_const_mem (mode, op1));
10297 /* TDmode values are passed as TImode on the stack. TImode values
10298 are moved via xmm registers, and moving them to stack can result in
10299 unaligned memory access. Use ix86_expand_vector_move_misalign()
10300 if memory operand is not aligned correctly. */
10301 if (can_create_pseudo_p ()
10302 && (mode == TImode) && !TARGET_64BIT
10303 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
10304 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
10308 /* ix86_expand_vector_move_misalign() does not like constants ... */
10309 if (CONSTANT_P (op1)
10310 || (GET_CODE (op1) == SUBREG
10311 && CONSTANT_P (SUBREG_REG (op1))))
10312 op1 = validize_mem (force_const_mem (mode, op1));
10314 /* ... nor both arguments in memory. */
10315 if (!register_operand (op0, mode)
10316 && !register_operand (op1, mode))
10317 op1 = force_reg (mode, op1);
10319 tmp[0] = op0; tmp[1] = op1;
10320 ix86_expand_vector_move_misalign (mode, tmp);
10324 /* Make operand1 a register if it isn't already. */
10325 if (can_create_pseudo_p ()
10326 && !register_operand (op0, mode)
10327 && !register_operand (op1, mode))
10329 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
10333 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10336 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
10337 straight to ix86_expand_vector_move. */
10338 /* Code generation for scalar reg-reg moves of single and double precision data:
10339 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
10343 if (x86_sse_partial_reg_dependency == true)
10348 Code generation for scalar loads of double precision data:
10349 if (x86_sse_split_regs == true)
10350 movlpd mem, reg (gas syntax)
10354 Code generation for unaligned packed loads of single precision data
10355 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
10356 if (x86_sse_unaligned_move_optimal)
10359 if (x86_sse_partial_reg_dependency == true)
10371 Code generation for unaligned packed loads of double precision data
10372 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
10373 if (x86_sse_unaligned_move_optimal)
10376 if (x86_sse_split_regs == true)
10389 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
10398 /* If we're optimizing for size, movups is the smallest. */
10401 op0 = gen_lowpart (V4SFmode, op0);
10402 op1 = gen_lowpart (V4SFmode, op1);
10403 emit_insn (gen_sse_movups (op0, op1));
10407 /* ??? If we have typed data, then it would appear that using
10408 movdqu is the only way to get unaligned data loaded with
10410 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10412 op0 = gen_lowpart (V16QImode, op0);
10413 op1 = gen_lowpart (V16QImode, op1);
10414 emit_insn (gen_sse2_movdqu (op0, op1));
10418 if (TARGET_SSE2 && mode == V2DFmode)
10422 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10424 op0 = gen_lowpart (V2DFmode, op0);
10425 op1 = gen_lowpart (V2DFmode, op1);
10426 emit_insn (gen_sse2_movupd (op0, op1));
10430 /* When SSE registers are split into halves, we can avoid
10431 writing to the top half twice. */
10432 if (TARGET_SSE_SPLIT_REGS)
10434 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10439 /* ??? Not sure about the best option for the Intel chips.
10440 The following would seem to satisfy; the register is
10441 entirely cleared, breaking the dependency chain. We
10442 then store to the upper half, with a dependency depth
10443 of one. A rumor has it that Intel recommends two movsd
10444 followed by an unpacklpd, but this is unconfirmed. And
10445 given that the dependency depth of the unpacklpd would
10446 still be one, I'm not sure why this would be better. */
10447 zero = CONST0_RTX (V2DFmode);
10450 m = adjust_address (op1, DFmode, 0);
10451 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10452 m = adjust_address (op1, DFmode, 8);
10453 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10457 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10459 op0 = gen_lowpart (V4SFmode, op0);
10460 op1 = gen_lowpart (V4SFmode, op1);
10461 emit_insn (gen_sse_movups (op0, op1));
10465 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10466 emit_move_insn (op0, CONST0_RTX (mode));
10468 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10470 if (mode != V4SFmode)
10471 op0 = gen_lowpart (V4SFmode, op0);
10472 m = adjust_address (op1, V2SFmode, 0);
10473 emit_insn (gen_sse_loadlps (op0, op0, m));
10474 m = adjust_address (op1, V2SFmode, 8);
10475 emit_insn (gen_sse_loadhps (op0, op0, m));
10478 else if (MEM_P (op0))
10480 /* If we're optimizing for size, movups is the smallest. */
10483 op0 = gen_lowpart (V4SFmode, op0);
10484 op1 = gen_lowpart (V4SFmode, op1);
10485 emit_insn (gen_sse_movups (op0, op1));
10489 /* ??? Similar to above, only less clear because of quote
10490 typeless stores unquote. */
10491 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10492 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10494 op0 = gen_lowpart (V16QImode, op0);
10495 op1 = gen_lowpart (V16QImode, op1);
10496 emit_insn (gen_sse2_movdqu (op0, op1));
10500 if (TARGET_SSE2 && mode == V2DFmode)
10502 m = adjust_address (op0, DFmode, 0);
10503 emit_insn (gen_sse2_storelpd (m, op1));
10504 m = adjust_address (op0, DFmode, 8);
10505 emit_insn (gen_sse2_storehpd (m, op1));
10509 if (mode != V4SFmode)
10510 op1 = gen_lowpart (V4SFmode, op1);
10511 m = adjust_address (op0, V2SFmode, 0);
10512 emit_insn (gen_sse_storelps (m, op1));
10513 m = adjust_address (op0, V2SFmode, 8);
10514 emit_insn (gen_sse_storehps (m, op1));
10518 gcc_unreachable ();
10521 /* Expand a push in MODE. This is some mode for which we do not support
10522 proper push instructions, at least from the registers that we expect
10523 the value to live in. */
10526 ix86_expand_push (enum machine_mode mode, rtx x)
10530 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10531 GEN_INT (-GET_MODE_SIZE (mode)),
10532 stack_pointer_rtx, 1, OPTAB_DIRECT);
10533 if (tmp != stack_pointer_rtx)
10534 emit_move_insn (stack_pointer_rtx, tmp);
10536 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10537 emit_move_insn (tmp, x);
10540 /* Helper function of ix86_fixup_binary_operands to canonicalize
10541 operand order. Returns true if the operands should be swapped. */
10544 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10547 rtx dst = operands[0];
10548 rtx src1 = operands[1];
10549 rtx src2 = operands[2];
10551 /* If the operation is not commutative, we can't do anything. */
10552 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10555 /* Highest priority is that src1 should match dst. */
10556 if (rtx_equal_p (dst, src1))
10558 if (rtx_equal_p (dst, src2))
10561 /* Next highest priority is that immediate constants come second. */
10562 if (immediate_operand (src2, mode))
10564 if (immediate_operand (src1, mode))
10567 /* Lowest priority is that memory references should come second. */
10577 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10578 destination to use for the operation. If different from the true
10579 destination in operands[0], a copy operation will be required. */
10582 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10585 rtx dst = operands[0];
10586 rtx src1 = operands[1];
10587 rtx src2 = operands[2];
10589 /* Canonicalize operand order. */
10590 if (ix86_swap_binary_operands_p (code, mode, operands))
10597 /* Both source operands cannot be in memory. */
10598 if (MEM_P (src1) && MEM_P (src2))
10600 /* Optimization: Only read from memory once. */
10601 if (rtx_equal_p (src1, src2))
10603 src2 = force_reg (mode, src2);
10607 src2 = force_reg (mode, src2);
10610 /* If the destination is memory, and we do not have matching source
10611 operands, do things in registers. */
10612 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10613 dst = gen_reg_rtx (mode);
10615 /* Source 1 cannot be a constant. */
10616 if (CONSTANT_P (src1))
10617 src1 = force_reg (mode, src1);
10619 /* Source 1 cannot be a non-matching memory. */
10620 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10621 src1 = force_reg (mode, src1);
10623 operands[1] = src1;
10624 operands[2] = src2;
10628 /* Similarly, but assume that the destination has already been
10629 set up properly. */
10632 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10633 enum machine_mode mode, rtx operands[])
10635 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10636 gcc_assert (dst == operands[0]);
10639 /* Attempt to expand a binary operator. Make the expansion closer to the
10640 actual machine, then just general_operand, which will allow 3 separate
10641 memory references (one output, two input) in a single insn. */
10644 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10647 rtx src1, src2, dst, op, clob;
10649 dst = ix86_fixup_binary_operands (code, mode, operands);
10650 src1 = operands[1];
10651 src2 = operands[2];
10653 /* Emit the instruction. */
10655 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10656 if (reload_in_progress)
10658 /* Reload doesn't know about the flags register, and doesn't know that
10659 it doesn't want to clobber it. We can only do this with PLUS. */
10660 gcc_assert (code == PLUS);
10665 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10666 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10669 /* Fix up the destination if needed. */
10670 if (dst != operands[0])
10671 emit_move_insn (operands[0], dst);
10674 /* Return TRUE or FALSE depending on whether the binary operator meets the
10675 appropriate constraints. */
10678 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10681 rtx dst = operands[0];
10682 rtx src1 = operands[1];
10683 rtx src2 = operands[2];
10685 /* Both source operands cannot be in memory. */
10686 if (MEM_P (src1) && MEM_P (src2))
10689 /* Canonicalize operand order for commutative operators. */
10690 if (ix86_swap_binary_operands_p (code, mode, operands))
10697 /* If the destination is memory, we must have a matching source operand. */
10698 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10701 /* Source 1 cannot be a constant. */
10702 if (CONSTANT_P (src1))
10705 /* Source 1 cannot be a non-matching memory. */
10706 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10712 /* Attempt to expand a unary operator. Make the expansion closer to the
10713 actual machine, then just general_operand, which will allow 2 separate
10714 memory references (one output, one input) in a single insn. */
10717 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10720 int matching_memory;
10721 rtx src, dst, op, clob;
10726 /* If the destination is memory, and we do not have matching source
10727 operands, do things in registers. */
10728 matching_memory = 0;
10731 if (rtx_equal_p (dst, src))
10732 matching_memory = 1;
10734 dst = gen_reg_rtx (mode);
10737 /* When source operand is memory, destination must match. */
10738 if (MEM_P (src) && !matching_memory)
10739 src = force_reg (mode, src);
10741 /* Emit the instruction. */
10743 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10744 if (reload_in_progress || code == NOT)
10746 /* Reload doesn't know about the flags register, and doesn't know that
10747 it doesn't want to clobber it. */
10748 gcc_assert (code == NOT);
10753 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10754 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10757 /* Fix up the destination if needed. */
10758 if (dst != operands[0])
10759 emit_move_insn (operands[0], dst);
10762 /* Return TRUE or FALSE depending on whether the unary operator meets the
10763 appropriate constraints. */
10766 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10767 enum machine_mode mode ATTRIBUTE_UNUSED,
10768 rtx operands[2] ATTRIBUTE_UNUSED)
10770 /* If one of operands is memory, source and destination must match. */
10771 if ((MEM_P (operands[0])
10772 || MEM_P (operands[1]))
10773 && ! rtx_equal_p (operands[0], operands[1]))
10778 /* Post-reload splitter for converting an SF or DFmode value in an
10779 SSE register into an unsigned SImode. */
10782 ix86_split_convert_uns_si_sse (rtx operands[])
10784 enum machine_mode vecmode;
10785 rtx value, large, zero_or_two31, input, two31, x;
10787 large = operands[1];
10788 zero_or_two31 = operands[2];
10789 input = operands[3];
10790 two31 = operands[4];
10791 vecmode = GET_MODE (large);
10792 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10794 /* Load up the value into the low element. We must ensure that the other
10795 elements are valid floats -- zero is the easiest such value. */
10798 if (vecmode == V4SFmode)
10799 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10801 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10805 input = gen_rtx_REG (vecmode, REGNO (input));
10806 emit_move_insn (value, CONST0_RTX (vecmode));
10807 if (vecmode == V4SFmode)
10808 emit_insn (gen_sse_movss (value, value, input));
10810 emit_insn (gen_sse2_movsd (value, value, input));
10813 emit_move_insn (large, two31);
10814 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10816 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10817 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10819 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10820 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10822 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10823 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10825 large = gen_rtx_REG (V4SImode, REGNO (large));
10826 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10828 x = gen_rtx_REG (V4SImode, REGNO (value));
10829 if (vecmode == V4SFmode)
10830 emit_insn (gen_sse2_cvttps2dq (x, value));
10832 emit_insn (gen_sse2_cvttpd2dq (x, value));
10835 emit_insn (gen_xorv4si3 (value, value, large));
10838 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10839 Expects the 64-bit DImode to be supplied in a pair of integral
10840 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10841 -mfpmath=sse, !optimize_size only. */
10844 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10846 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10847 rtx int_xmm, fp_xmm;
10848 rtx biases, exponents;
10851 int_xmm = gen_reg_rtx (V4SImode);
10852 if (TARGET_INTER_UNIT_MOVES)
10853 emit_insn (gen_movdi_to_sse (int_xmm, input));
10854 else if (TARGET_SSE_SPLIT_REGS)
10856 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10857 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10861 x = gen_reg_rtx (V2DImode);
10862 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10863 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10866 x = gen_rtx_CONST_VECTOR (V4SImode,
10867 gen_rtvec (4, GEN_INT (0x43300000UL),
10868 GEN_INT (0x45300000UL),
10869 const0_rtx, const0_rtx));
10870 exponents = validize_mem (force_const_mem (V4SImode, x));
10872 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10873 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10875 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10876 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10877 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10878 (0x1.0p84 + double(fp_value_hi_xmm)).
10879 Note these exponents differ by 32. */
10881 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
10883 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10884 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10885 real_ldexp (&bias_lo_rvt, &dconst1, 52);
10886 real_ldexp (&bias_hi_rvt, &dconst1, 84);
10887 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
10888 x = const_double_from_real_value (bias_hi_rvt, DFmode);
10889 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
10890 biases = validize_mem (force_const_mem (V2DFmode, biases));
10891 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
10893 /* Add the upper and lower DFmode values together. */
10895 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
10898 x = copy_to_mode_reg (V2DFmode, fp_xmm);
10899 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
10900 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
10903 ix86_expand_vector_extract (false, target, fp_xmm, 0);
10906 /* Not used, but eases macroization of patterns. */
10908 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
10909 rtx input ATTRIBUTE_UNUSED)
10911 gcc_unreachable ();
10914 /* Convert an unsigned SImode value into a DFmode. Only currently used
10915 for SSE, but applicable anywhere. */
10918 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
10920 REAL_VALUE_TYPE TWO31r;
10923 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
10924 NULL, 1, OPTAB_DIRECT);
10926 fp = gen_reg_rtx (DFmode);
10927 emit_insn (gen_floatsidf2 (fp, x));
10929 real_ldexp (&TWO31r, &dconst1, 31);
10930 x = const_double_from_real_value (TWO31r, DFmode);
10932 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
10934 emit_move_insn (target, x);
10937 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10938 32-bit mode; otherwise we have a direct convert instruction. */
10941 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
10943 REAL_VALUE_TYPE TWO32r;
10944 rtx fp_lo, fp_hi, x;
10946 fp_lo = gen_reg_rtx (DFmode);
10947 fp_hi = gen_reg_rtx (DFmode);
10949 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
10951 real_ldexp (&TWO32r, &dconst1, 32);
10952 x = const_double_from_real_value (TWO32r, DFmode);
10953 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
10955 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
10957 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
10960 emit_move_insn (target, x);
10963 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10964 For x86_32, -mfpmath=sse, !optimize_size only. */
10966 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
10968 REAL_VALUE_TYPE ONE16r;
10969 rtx fp_hi, fp_lo, int_hi, int_lo, x;
10971 real_ldexp (&ONE16r, &dconst1, 16);
10972 x = const_double_from_real_value (ONE16r, SFmode);
10973 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
10974 NULL, 0, OPTAB_DIRECT);
10975 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
10976 NULL, 0, OPTAB_DIRECT);
10977 fp_hi = gen_reg_rtx (SFmode);
10978 fp_lo = gen_reg_rtx (SFmode);
10979 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
10980 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
10981 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
10983 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
10985 if (!rtx_equal_p (target, fp_hi))
10986 emit_move_insn (target, fp_hi);
10989 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10990 then replicate the value for all elements of the vector
10994 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
11001 v = gen_rtvec (4, value, value, value, value);
11002 return gen_rtx_CONST_VECTOR (V4SImode, v);
11006 v = gen_rtvec (2, value, value);
11007 return gen_rtx_CONST_VECTOR (V2DImode, v);
11011 v = gen_rtvec (4, value, value, value, value);
11013 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
11014 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11015 return gen_rtx_CONST_VECTOR (V4SFmode, v);
11019 v = gen_rtvec (2, value, value);
11021 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
11022 return gen_rtx_CONST_VECTOR (V2DFmode, v);
11025 gcc_unreachable ();
11029 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
11030 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
11031 for an SSE register. If VECT is true, then replicate the mask for
11032 all elements of the vector register. If INVERT is true, then create
11033 a mask excluding the sign bit. */
11036 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
11038 enum machine_mode vec_mode, imode;
11039 HOST_WIDE_INT hi, lo;
11044 /* Find the sign bit, sign extended to 2*HWI. */
11050 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
11051 lo = 0x80000000, hi = lo < 0;
11057 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
11058 if (HOST_BITS_PER_WIDE_INT >= 64)
11059 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
11061 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
11067 vec_mode = VOIDmode;
11068 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
11069 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
11073 gcc_unreachable ();
11077 lo = ~lo, hi = ~hi;
11079 /* Force this value into the low part of a fp vector constant. */
11080 mask = immed_double_const (lo, hi, imode);
11081 mask = gen_lowpart (mode, mask);
11083 if (vec_mode == VOIDmode)
11084 return force_reg (mode, mask);
11086 v = ix86_build_const_vector (mode, vect, mask);
11087 return force_reg (vec_mode, v);
11090 /* Generate code for floating point ABS or NEG. */
11093 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
11096 rtx mask, set, use, clob, dst, src;
11097 bool use_sse = false;
11098 bool vector_mode = VECTOR_MODE_P (mode);
11099 enum machine_mode elt_mode = mode;
11103 elt_mode = GET_MODE_INNER (mode);
11106 else if (mode == TFmode)
11108 else if (TARGET_SSE_MATH)
11109 use_sse = SSE_FLOAT_MODE_P (mode);
11111 /* NEG and ABS performed with SSE use bitwise mask operations.
11112 Create the appropriate mask now. */
11114 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
11123 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
11124 set = gen_rtx_SET (VOIDmode, dst, set);
11129 set = gen_rtx_fmt_e (code, mode, src);
11130 set = gen_rtx_SET (VOIDmode, dst, set);
11133 use = gen_rtx_USE (VOIDmode, mask);
11134 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11135 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11136 gen_rtvec (3, set, use, clob)));
11143 /* Expand a copysign operation. Special case operand 0 being a constant. */
11146 ix86_expand_copysign (rtx operands[])
11148 enum machine_mode mode, vmode;
11149 rtx dest, op0, op1, mask, nmask;
11151 dest = operands[0];
11155 mode = GET_MODE (dest);
11156 vmode = mode == SFmode ? V4SFmode : V2DFmode;
11158 if (GET_CODE (op0) == CONST_DOUBLE)
11160 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
11162 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
11163 op0 = simplify_unary_operation (ABS, mode, op0, mode);
11165 if (mode == SFmode || mode == DFmode)
11167 if (op0 == CONST0_RTX (mode))
11168 op0 = CONST0_RTX (vmode);
11173 if (mode == SFmode)
11174 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
11175 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11177 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
11178 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
11182 mask = ix86_build_signbit_mask (mode, 0, 0);
11184 if (mode == SFmode)
11185 copysign_insn = gen_copysignsf3_const;
11186 else if (mode == DFmode)
11187 copysign_insn = gen_copysigndf3_const;
11189 copysign_insn = gen_copysigntf3_const;
11191 emit_insn (copysign_insn (dest, op0, op1, mask));
11195 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
11197 nmask = ix86_build_signbit_mask (mode, 0, 1);
11198 mask = ix86_build_signbit_mask (mode, 0, 0);
11200 if (mode == SFmode)
11201 copysign_insn = gen_copysignsf3_var;
11202 else if (mode == DFmode)
11203 copysign_insn = gen_copysigndf3_var;
11205 copysign_insn = gen_copysigntf3_var;
11207 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
11211 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
11212 be a constant, and so has already been expanded into a vector constant. */
11215 ix86_split_copysign_const (rtx operands[])
11217 enum machine_mode mode, vmode;
11218 rtx dest, op0, op1, mask, x;
11220 dest = operands[0];
11223 mask = operands[3];
11225 mode = GET_MODE (dest);
11226 vmode = GET_MODE (mask);
11228 dest = simplify_gen_subreg (vmode, dest, mode, 0);
11229 x = gen_rtx_AND (vmode, dest, mask);
11230 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11232 if (op0 != CONST0_RTX (vmode))
11234 x = gen_rtx_IOR (vmode, dest, op0);
11235 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11239 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
11240 so we have to do two masks. */
11243 ix86_split_copysign_var (rtx operands[])
11245 enum machine_mode mode, vmode;
11246 rtx dest, scratch, op0, op1, mask, nmask, x;
11248 dest = operands[0];
11249 scratch = operands[1];
11252 nmask = operands[4];
11253 mask = operands[5];
11255 mode = GET_MODE (dest);
11256 vmode = GET_MODE (mask);
11258 if (rtx_equal_p (op0, op1))
11260 /* Shouldn't happen often (it's useless, obviously), but when it does
11261 we'd generate incorrect code if we continue below. */
11262 emit_move_insn (dest, op0);
11266 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
11268 gcc_assert (REGNO (op1) == REGNO (scratch));
11270 x = gen_rtx_AND (vmode, scratch, mask);
11271 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11274 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11275 x = gen_rtx_NOT (vmode, dest);
11276 x = gen_rtx_AND (vmode, x, op0);
11277 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11281 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
11283 x = gen_rtx_AND (vmode, scratch, mask);
11285 else /* alternative 2,4 */
11287 gcc_assert (REGNO (mask) == REGNO (scratch));
11288 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
11289 x = gen_rtx_AND (vmode, scratch, op1);
11291 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11293 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
11295 dest = simplify_gen_subreg (vmode, op0, mode, 0);
11296 x = gen_rtx_AND (vmode, dest, nmask);
11298 else /* alternative 3,4 */
11300 gcc_assert (REGNO (nmask) == REGNO (dest));
11302 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11303 x = gen_rtx_AND (vmode, dest, op0);
11305 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11308 x = gen_rtx_IOR (vmode, dest, scratch);
11309 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11312 /* Return TRUE or FALSE depending on whether the first SET in INSN
11313 has source and destination with matching CC modes, and that the
11314 CC mode is at least as constrained as REQ_MODE. */
11317 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
11320 enum machine_mode set_mode;
11322 set = PATTERN (insn);
11323 if (GET_CODE (set) == PARALLEL)
11324 set = XVECEXP (set, 0, 0);
11325 gcc_assert (GET_CODE (set) == SET);
11326 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
11328 set_mode = GET_MODE (SET_DEST (set));
11332 if (req_mode != CCNOmode
11333 && (req_mode != CCmode
11334 || XEXP (SET_SRC (set), 1) != const0_rtx))
11338 if (req_mode == CCGCmode)
11342 if (req_mode == CCGOCmode || req_mode == CCNOmode)
11346 if (req_mode == CCZmode)
11353 gcc_unreachable ();
11356 return (GET_MODE (SET_SRC (set)) == set_mode);
11359 /* Generate insn patterns to do an integer compare of OPERANDS. */
11362 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
11364 enum machine_mode cmpmode;
11367 cmpmode = SELECT_CC_MODE (code, op0, op1);
11368 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
11370 /* This is very simple, but making the interface the same as in the
11371 FP case makes the rest of the code easier. */
11372 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
11373 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
11375 /* Return the test that should be put into the flags user, i.e.
11376 the bcc, scc, or cmov instruction. */
11377 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
11380 /* Figure out whether to use ordered or unordered fp comparisons.
11381 Return the appropriate mode to use. */
11384 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
11386 /* ??? In order to make all comparisons reversible, we do all comparisons
11387 non-trapping when compiling for IEEE. Once gcc is able to distinguish
11388 all forms trapping and nontrapping comparisons, we can make inequality
11389 comparisons trapping again, since it results in better code when using
11390 FCOM based compares. */
11391 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
11395 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
11397 enum machine_mode mode = GET_MODE (op0);
11399 if (SCALAR_FLOAT_MODE_P (mode))
11401 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11402 return ix86_fp_compare_mode (code);
11407 /* Only zero flag is needed. */
11408 case EQ: /* ZF=0 */
11409 case NE: /* ZF!=0 */
11411 /* Codes needing carry flag. */
11412 case GEU: /* CF=0 */
11413 case LTU: /* CF=1 */
11414 /* Detect overflow checks. They need just the carry flag. */
11415 if (GET_CODE (op0) == PLUS
11416 && rtx_equal_p (op1, XEXP (op0, 0)))
11420 case GTU: /* CF=0 & ZF=0 */
11421 case LEU: /* CF=1 | ZF=1 */
11422 /* Detect overflow checks. They need just the carry flag. */
11423 if (GET_CODE (op0) == MINUS
11424 && rtx_equal_p (op1, XEXP (op0, 0)))
11428 /* Codes possibly doable only with sign flag when
11429 comparing against zero. */
11430 case GE: /* SF=OF or SF=0 */
11431 case LT: /* SF<>OF or SF=1 */
11432 if (op1 == const0_rtx)
11435 /* For other cases Carry flag is not required. */
11437 /* Codes doable only with sign flag when comparing
11438 against zero, but we miss jump instruction for it
11439 so we need to use relational tests against overflow
11440 that thus needs to be zero. */
11441 case GT: /* ZF=0 & SF=OF */
11442 case LE: /* ZF=1 | SF<>OF */
11443 if (op1 == const0_rtx)
11447 /* strcmp pattern do (use flags) and combine may ask us for proper
11452 gcc_unreachable ();
11456 /* Return the fixed registers used for condition codes. */
11459 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11466 /* If two condition code modes are compatible, return a condition code
11467 mode which is compatible with both. Otherwise, return
11470 static enum machine_mode
11471 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11476 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11479 if ((m1 == CCGCmode && m2 == CCGOCmode)
11480 || (m1 == CCGOCmode && m2 == CCGCmode))
11486 gcc_unreachable ();
11516 /* These are only compatible with themselves, which we already
11522 /* Split comparison code CODE into comparisons we can do using branch
11523 instructions. BYPASS_CODE is comparison code for branch that will
11524 branch around FIRST_CODE and SECOND_CODE. If some of branches
11525 is not required, set value to UNKNOWN.
11526 We never require more than two branches. */
11529 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11530 enum rtx_code *first_code,
11531 enum rtx_code *second_code)
11533 *first_code = code;
11534 *bypass_code = UNKNOWN;
11535 *second_code = UNKNOWN;
11537 /* The fcomi comparison sets flags as follows:
11547 case GT: /* GTU - CF=0 & ZF=0 */
11548 case GE: /* GEU - CF=0 */
11549 case ORDERED: /* PF=0 */
11550 case UNORDERED: /* PF=1 */
11551 case UNEQ: /* EQ - ZF=1 */
11552 case UNLT: /* LTU - CF=1 */
11553 case UNLE: /* LEU - CF=1 | ZF=1 */
11554 case LTGT: /* EQ - ZF=0 */
11556 case LT: /* LTU - CF=1 - fails on unordered */
11557 *first_code = UNLT;
11558 *bypass_code = UNORDERED;
11560 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11561 *first_code = UNLE;
11562 *bypass_code = UNORDERED;
11564 case EQ: /* EQ - ZF=1 - fails on unordered */
11565 *first_code = UNEQ;
11566 *bypass_code = UNORDERED;
11568 case NE: /* NE - ZF=0 - fails on unordered */
11569 *first_code = LTGT;
11570 *second_code = UNORDERED;
11572 case UNGE: /* GEU - CF=0 - fails on unordered */
11574 *second_code = UNORDERED;
11576 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11578 *second_code = UNORDERED;
11581 gcc_unreachable ();
11583 if (!TARGET_IEEE_FP)
11585 *second_code = UNKNOWN;
11586 *bypass_code = UNKNOWN;
11590 /* Return cost of comparison done fcom + arithmetics operations on AX.
11591 All following functions do use number of instructions as a cost metrics.
11592 In future this should be tweaked to compute bytes for optimize_size and
11593 take into account performance of various instructions on various CPUs. */
11595 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11597 if (!TARGET_IEEE_FP)
11599 /* The cost of code output by ix86_expand_fp_compare. */
11623 gcc_unreachable ();
11627 /* Return cost of comparison done using fcomi operation.
11628 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11630 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11632 enum rtx_code bypass_code, first_code, second_code;
11633 /* Return arbitrarily high cost when instruction is not supported - this
11634 prevents gcc from using it. */
11637 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11638 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11641 /* Return cost of comparison done using sahf operation.
11642 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11644 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11646 enum rtx_code bypass_code, first_code, second_code;
11647 /* Return arbitrarily high cost when instruction is not preferred - this
11648 avoids gcc from using it. */
11649 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11651 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11652 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11655 /* Compute cost of the comparison done using any method.
11656 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11658 ix86_fp_comparison_cost (enum rtx_code code)
11660 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11663 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11664 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11666 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11667 if (min > sahf_cost)
11669 if (min > fcomi_cost)
11674 /* Return true if we should use an FCOMI instruction for this
11678 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11680 enum rtx_code swapped_code = swap_condition (code);
11682 return ((ix86_fp_comparison_cost (code)
11683 == ix86_fp_comparison_fcomi_cost (code))
11684 || (ix86_fp_comparison_cost (swapped_code)
11685 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11688 /* Swap, force into registers, or otherwise massage the two operands
11689 to a fp comparison. The operands are updated in place; the new
11690 comparison code is returned. */
11692 static enum rtx_code
11693 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11695 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11696 rtx op0 = *pop0, op1 = *pop1;
11697 enum machine_mode op_mode = GET_MODE (op0);
11698 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11700 /* All of the unordered compare instructions only work on registers.
11701 The same is true of the fcomi compare instructions. The XFmode
11702 compare instructions require registers except when comparing
11703 against zero or when converting operand 1 from fixed point to
11707 && (fpcmp_mode == CCFPUmode
11708 || (op_mode == XFmode
11709 && ! (standard_80387_constant_p (op0) == 1
11710 || standard_80387_constant_p (op1) == 1)
11711 && GET_CODE (op1) != FLOAT)
11712 || ix86_use_fcomi_compare (code)))
11714 op0 = force_reg (op_mode, op0);
11715 op1 = force_reg (op_mode, op1);
11719 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11720 things around if they appear profitable, otherwise force op0
11721 into a register. */
11723 if (standard_80387_constant_p (op0) == 0
11725 && ! (standard_80387_constant_p (op1) == 0
11729 tmp = op0, op0 = op1, op1 = tmp;
11730 code = swap_condition (code);
11734 op0 = force_reg (op_mode, op0);
11736 if (CONSTANT_P (op1))
11738 int tmp = standard_80387_constant_p (op1);
11740 op1 = validize_mem (force_const_mem (op_mode, op1));
11744 op1 = force_reg (op_mode, op1);
11747 op1 = force_reg (op_mode, op1);
11751 /* Try to rearrange the comparison to make it cheaper. */
11752 if (ix86_fp_comparison_cost (code)
11753 > ix86_fp_comparison_cost (swap_condition (code))
11754 && (REG_P (op1) || can_create_pseudo_p ()))
11757 tmp = op0, op0 = op1, op1 = tmp;
11758 code = swap_condition (code);
11760 op0 = force_reg (op_mode, op0);
11768 /* Convert comparison codes we use to represent FP comparison to integer
11769 code that will result in proper branch. Return UNKNOWN if no such code
11773 ix86_fp_compare_code_to_integer (enum rtx_code code)
11802 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11805 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11806 rtx *second_test, rtx *bypass_test)
11808 enum machine_mode fpcmp_mode, intcmp_mode;
11810 int cost = ix86_fp_comparison_cost (code);
11811 enum rtx_code bypass_code, first_code, second_code;
11813 fpcmp_mode = ix86_fp_compare_mode (code);
11814 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11817 *second_test = NULL_RTX;
11819 *bypass_test = NULL_RTX;
11821 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11823 /* Do fcomi/sahf based test when profitable. */
11824 if (ix86_fp_comparison_arithmetics_cost (code) > cost
11825 && (bypass_code == UNKNOWN || bypass_test)
11826 && (second_code == UNKNOWN || second_test))
11828 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11829 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11835 gcc_assert (TARGET_SAHF);
11838 scratch = gen_reg_rtx (HImode);
11839 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
11841 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
11844 /* The FP codes work out to act like unsigned. */
11845 intcmp_mode = fpcmp_mode;
11847 if (bypass_code != UNKNOWN)
11848 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11849 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11851 if (second_code != UNKNOWN)
11852 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11853 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11858 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11859 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11860 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11862 scratch = gen_reg_rtx (HImode);
11863 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11865 /* In the unordered case, we have to check C2 for NaN's, which
11866 doesn't happen to work out to anything nice combination-wise.
11867 So do some bit twiddling on the value we've got in AH to come
11868 up with an appropriate set of condition codes. */
11870 intcmp_mode = CCNOmode;
11875 if (code == GT || !TARGET_IEEE_FP)
11877 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11882 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11883 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11884 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
11885 intcmp_mode = CCmode;
11891 if (code == LT && TARGET_IEEE_FP)
11893 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11894 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
11895 intcmp_mode = CCmode;
11900 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
11906 if (code == GE || !TARGET_IEEE_FP)
11908 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
11913 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11914 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11921 if (code == LE && TARGET_IEEE_FP)
11923 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11924 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11925 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11926 intcmp_mode = CCmode;
11931 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11937 if (code == EQ && TARGET_IEEE_FP)
11939 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11940 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11941 intcmp_mode = CCmode;
11946 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11953 if (code == NE && TARGET_IEEE_FP)
11955 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11956 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11962 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11968 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11972 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11977 gcc_unreachable ();
11981 /* Return the test that should be put into the flags user, i.e.
11982 the bcc, scc, or cmov instruction. */
11983 return gen_rtx_fmt_ee (code, VOIDmode,
11984 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11989 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
11992 op0 = ix86_compare_op0;
11993 op1 = ix86_compare_op1;
11996 *second_test = NULL_RTX;
11998 *bypass_test = NULL_RTX;
12000 if (ix86_compare_emitted)
12002 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
12003 ix86_compare_emitted = NULL_RTX;
12005 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
12007 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
12008 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12009 second_test, bypass_test);
12012 ret = ix86_expand_int_compare (code, op0, op1);
12017 /* Return true if the CODE will result in nontrivial jump sequence. */
12019 ix86_fp_jump_nontrivial_p (enum rtx_code code)
12021 enum rtx_code bypass_code, first_code, second_code;
12024 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12025 return bypass_code != UNKNOWN || second_code != UNKNOWN;
12029 ix86_expand_branch (enum rtx_code code, rtx label)
12033 /* If we have emitted a compare insn, go straight to simple.
12034 ix86_expand_compare won't emit anything if ix86_compare_emitted
12036 if (ix86_compare_emitted)
12039 switch (GET_MODE (ix86_compare_op0))
12045 tmp = ix86_expand_compare (code, NULL, NULL);
12046 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12047 gen_rtx_LABEL_REF (VOIDmode, label),
12049 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12058 enum rtx_code bypass_code, first_code, second_code;
12060 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
12061 &ix86_compare_op1);
12063 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12065 /* Check whether we will use the natural sequence with one jump. If
12066 so, we can expand jump early. Otherwise delay expansion by
12067 creating compound insn to not confuse optimizers. */
12068 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
12070 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
12071 gen_rtx_LABEL_REF (VOIDmode, label),
12072 pc_rtx, NULL_RTX, NULL_RTX);
12076 tmp = gen_rtx_fmt_ee (code, VOIDmode,
12077 ix86_compare_op0, ix86_compare_op1);
12078 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12079 gen_rtx_LABEL_REF (VOIDmode, label),
12081 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
12083 use_fcomi = ix86_use_fcomi_compare (code);
12084 vec = rtvec_alloc (3 + !use_fcomi);
12085 RTVEC_ELT (vec, 0) = tmp;
12087 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
12089 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
12092 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
12094 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12103 /* Expand DImode branch into multiple compare+branch. */
12105 rtx lo[2], hi[2], label2;
12106 enum rtx_code code1, code2, code3;
12107 enum machine_mode submode;
12109 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
12111 tmp = ix86_compare_op0;
12112 ix86_compare_op0 = ix86_compare_op1;
12113 ix86_compare_op1 = tmp;
12114 code = swap_condition (code);
12116 if (GET_MODE (ix86_compare_op0) == DImode)
12118 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
12119 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
12124 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
12125 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
12129 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
12130 avoid two branches. This costs one extra insn, so disable when
12131 optimizing for size. */
12133 if ((code == EQ || code == NE)
12135 || hi[1] == const0_rtx || lo[1] == const0_rtx))
12140 if (hi[1] != const0_rtx)
12141 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
12142 NULL_RTX, 0, OPTAB_WIDEN);
12145 if (lo[1] != const0_rtx)
12146 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
12147 NULL_RTX, 0, OPTAB_WIDEN);
12149 tmp = expand_binop (submode, ior_optab, xor1, xor0,
12150 NULL_RTX, 0, OPTAB_WIDEN);
12152 ix86_compare_op0 = tmp;
12153 ix86_compare_op1 = const0_rtx;
12154 ix86_expand_branch (code, label);
12158 /* Otherwise, if we are doing less-than or greater-or-equal-than,
12159 op1 is a constant and the low word is zero, then we can just
12160 examine the high word. Similarly for low word -1 and
12161 less-or-equal-than or greater-than. */
12163 if (CONST_INT_P (hi[1]))
12166 case LT: case LTU: case GE: case GEU:
12167 if (lo[1] == const0_rtx)
12169 ix86_compare_op0 = hi[0];
12170 ix86_compare_op1 = hi[1];
12171 ix86_expand_branch (code, label);
12175 case LE: case LEU: case GT: case GTU:
12176 if (lo[1] == constm1_rtx)
12178 ix86_compare_op0 = hi[0];
12179 ix86_compare_op1 = hi[1];
12180 ix86_expand_branch (code, label);
12188 /* Otherwise, we need two or three jumps. */
12190 label2 = gen_label_rtx ();
12193 code2 = swap_condition (code);
12194 code3 = unsigned_condition (code);
12198 case LT: case GT: case LTU: case GTU:
12201 case LE: code1 = LT; code2 = GT; break;
12202 case GE: code1 = GT; code2 = LT; break;
12203 case LEU: code1 = LTU; code2 = GTU; break;
12204 case GEU: code1 = GTU; code2 = LTU; break;
12206 case EQ: code1 = UNKNOWN; code2 = NE; break;
12207 case NE: code2 = UNKNOWN; break;
12210 gcc_unreachable ();
12215 * if (hi(a) < hi(b)) goto true;
12216 * if (hi(a) > hi(b)) goto false;
12217 * if (lo(a) < lo(b)) goto true;
12221 ix86_compare_op0 = hi[0];
12222 ix86_compare_op1 = hi[1];
12224 if (code1 != UNKNOWN)
12225 ix86_expand_branch (code1, label);
12226 if (code2 != UNKNOWN)
12227 ix86_expand_branch (code2, label2);
12229 ix86_compare_op0 = lo[0];
12230 ix86_compare_op1 = lo[1];
12231 ix86_expand_branch (code3, label);
12233 if (code2 != UNKNOWN)
12234 emit_label (label2);
12239 gcc_unreachable ();
12243 /* Split branch based on floating point condition. */
12245 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
12246 rtx target1, rtx target2, rtx tmp, rtx pushed)
12248 rtx second, bypass;
12249 rtx label = NULL_RTX;
12251 int bypass_probability = -1, second_probability = -1, probability = -1;
12254 if (target2 != pc_rtx)
12257 code = reverse_condition_maybe_unordered (code);
12262 condition = ix86_expand_fp_compare (code, op1, op2,
12263 tmp, &second, &bypass);
12265 /* Remove pushed operand from stack. */
12267 ix86_free_from_memory (GET_MODE (pushed));
12269 if (split_branch_probability >= 0)
12271 /* Distribute the probabilities across the jumps.
12272 Assume the BYPASS and SECOND to be always test
12274 probability = split_branch_probability;
12276 /* Value of 1 is low enough to make no need for probability
12277 to be updated. Later we may run some experiments and see
12278 if unordered values are more frequent in practice. */
12280 bypass_probability = 1;
12282 second_probability = 1;
12284 if (bypass != NULL_RTX)
12286 label = gen_label_rtx ();
12287 i = emit_jump_insn (gen_rtx_SET
12289 gen_rtx_IF_THEN_ELSE (VOIDmode,
12291 gen_rtx_LABEL_REF (VOIDmode,
12294 if (bypass_probability >= 0)
12296 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12297 GEN_INT (bypass_probability),
12300 i = emit_jump_insn (gen_rtx_SET
12302 gen_rtx_IF_THEN_ELSE (VOIDmode,
12303 condition, target1, target2)));
12304 if (probability >= 0)
12306 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12307 GEN_INT (probability),
12309 if (second != NULL_RTX)
12311 i = emit_jump_insn (gen_rtx_SET
12313 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
12315 if (second_probability >= 0)
12317 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12318 GEN_INT (second_probability),
12321 if (label != NULL_RTX)
12322 emit_label (label);
12326 ix86_expand_setcc (enum rtx_code code, rtx dest)
12328 rtx ret, tmp, tmpreg, equiv;
12329 rtx second_test, bypass_test;
12331 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
12332 return 0; /* FAIL */
12334 gcc_assert (GET_MODE (dest) == QImode);
12336 ret = ix86_expand_compare (code, &second_test, &bypass_test);
12337 PUT_MODE (ret, QImode);
12342 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
12343 if (bypass_test || second_test)
12345 rtx test = second_test;
12347 rtx tmp2 = gen_reg_rtx (QImode);
12350 gcc_assert (!second_test);
12351 test = bypass_test;
12353 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
12355 PUT_MODE (test, QImode);
12356 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
12359 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
12361 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
12364 /* Attach a REG_EQUAL note describing the comparison result. */
12365 if (ix86_compare_op0 && ix86_compare_op1)
12367 equiv = simplify_gen_relational (code, QImode,
12368 GET_MODE (ix86_compare_op0),
12369 ix86_compare_op0, ix86_compare_op1);
12370 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
12373 return 1; /* DONE */
12376 /* Expand comparison setting or clearing carry flag. Return true when
12377 successful and set pop for the operation. */
12379 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
12381 enum machine_mode mode =
12382 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
12384 /* Do not handle DImode compares that go through special path. */
12385 if (mode == (TARGET_64BIT ? TImode : DImode))
12388 if (SCALAR_FLOAT_MODE_P (mode))
12390 rtx second_test = NULL, bypass_test = NULL;
12391 rtx compare_op, compare_seq;
12393 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12395 /* Shortcut: following common codes never translate
12396 into carry flag compares. */
12397 if (code == EQ || code == NE || code == UNEQ || code == LTGT
12398 || code == ORDERED || code == UNORDERED)
12401 /* These comparisons require zero flag; swap operands so they won't. */
12402 if ((code == GT || code == UNLE || code == LE || code == UNGT)
12403 && !TARGET_IEEE_FP)
12408 code = swap_condition (code);
12411 /* Try to expand the comparison and verify that we end up with
12412 carry flag based comparison. This fails to be true only when
12413 we decide to expand comparison using arithmetic that is not
12414 too common scenario. */
12416 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12417 &second_test, &bypass_test);
12418 compare_seq = get_insns ();
12421 if (second_test || bypass_test)
12424 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12425 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12426 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
12428 code = GET_CODE (compare_op);
12430 if (code != LTU && code != GEU)
12433 emit_insn (compare_seq);
12438 if (!INTEGRAL_MODE_P (mode))
12447 /* Convert a==0 into (unsigned)a<1. */
12450 if (op1 != const0_rtx)
12453 code = (code == EQ ? LTU : GEU);
12456 /* Convert a>b into b<a or a>=b-1. */
12459 if (CONST_INT_P (op1))
12461 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12462 /* Bail out on overflow. We still can swap operands but that
12463 would force loading of the constant into register. */
12464 if (op1 == const0_rtx
12465 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12467 code = (code == GTU ? GEU : LTU);
12474 code = (code == GTU ? LTU : GEU);
12478 /* Convert a>=0 into (unsigned)a<0x80000000. */
12481 if (mode == DImode || op1 != const0_rtx)
12483 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12484 code = (code == LT ? GEU : LTU);
12488 if (mode == DImode || op1 != constm1_rtx)
12490 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12491 code = (code == LE ? GEU : LTU);
12497 /* Swapping operands may cause constant to appear as first operand. */
12498 if (!nonimmediate_operand (op0, VOIDmode))
12500 if (!can_create_pseudo_p ())
12502 op0 = force_reg (mode, op0);
12504 ix86_compare_op0 = op0;
12505 ix86_compare_op1 = op1;
12506 *pop = ix86_expand_compare (code, NULL, NULL);
12507 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12512 ix86_expand_int_movcc (rtx operands[])
12514 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12515 rtx compare_seq, compare_op;
12516 rtx second_test, bypass_test;
12517 enum machine_mode mode = GET_MODE (operands[0]);
12518 bool sign_bit_compare_p = false;;
12521 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12522 compare_seq = get_insns ();
12525 compare_code = GET_CODE (compare_op);
12527 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12528 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12529 sign_bit_compare_p = true;
12531 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12532 HImode insns, we'd be swallowed in word prefix ops. */
12534 if ((mode != HImode || TARGET_FAST_PREFIX)
12535 && (mode != (TARGET_64BIT ? TImode : DImode))
12536 && CONST_INT_P (operands[2])
12537 && CONST_INT_P (operands[3]))
12539 rtx out = operands[0];
12540 HOST_WIDE_INT ct = INTVAL (operands[2]);
12541 HOST_WIDE_INT cf = INTVAL (operands[3]);
12542 HOST_WIDE_INT diff;
12545 /* Sign bit compares are better done using shifts than we do by using
12547 if (sign_bit_compare_p
12548 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12549 ix86_compare_op1, &compare_op))
12551 /* Detect overlap between destination and compare sources. */
12554 if (!sign_bit_compare_p)
12556 bool fpcmp = false;
12558 compare_code = GET_CODE (compare_op);
12560 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12561 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12564 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12567 /* To simplify rest of code, restrict to the GEU case. */
12568 if (compare_code == LTU)
12570 HOST_WIDE_INT tmp = ct;
12573 compare_code = reverse_condition (compare_code);
12574 code = reverse_condition (code);
12579 PUT_CODE (compare_op,
12580 reverse_condition_maybe_unordered
12581 (GET_CODE (compare_op)));
12583 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12587 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12588 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12589 tmp = gen_reg_rtx (mode);
12591 if (mode == DImode)
12592 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12594 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12598 if (code == GT || code == GE)
12599 code = reverse_condition (code);
12602 HOST_WIDE_INT tmp = ct;
12607 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12608 ix86_compare_op1, VOIDmode, 0, -1);
12621 tmp = expand_simple_binop (mode, PLUS,
12623 copy_rtx (tmp), 1, OPTAB_DIRECT);
12634 tmp = expand_simple_binop (mode, IOR,
12636 copy_rtx (tmp), 1, OPTAB_DIRECT);
12638 else if (diff == -1 && ct)
12648 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12650 tmp = expand_simple_binop (mode, PLUS,
12651 copy_rtx (tmp), GEN_INT (cf),
12652 copy_rtx (tmp), 1, OPTAB_DIRECT);
12660 * andl cf - ct, dest
12670 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12673 tmp = expand_simple_binop (mode, AND,
12675 gen_int_mode (cf - ct, mode),
12676 copy_rtx (tmp), 1, OPTAB_DIRECT);
12678 tmp = expand_simple_binop (mode, PLUS,
12679 copy_rtx (tmp), GEN_INT (ct),
12680 copy_rtx (tmp), 1, OPTAB_DIRECT);
12683 if (!rtx_equal_p (tmp, out))
12684 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12686 return 1; /* DONE */
12691 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12694 tmp = ct, ct = cf, cf = tmp;
12697 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12699 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12701 /* We may be reversing unordered compare to normal compare, that
12702 is not valid in general (we may convert non-trapping condition
12703 to trapping one), however on i386 we currently emit all
12704 comparisons unordered. */
12705 compare_code = reverse_condition_maybe_unordered (compare_code);
12706 code = reverse_condition_maybe_unordered (code);
12710 compare_code = reverse_condition (compare_code);
12711 code = reverse_condition (code);
12715 compare_code = UNKNOWN;
12716 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12717 && CONST_INT_P (ix86_compare_op1))
12719 if (ix86_compare_op1 == const0_rtx
12720 && (code == LT || code == GE))
12721 compare_code = code;
12722 else if (ix86_compare_op1 == constm1_rtx)
12726 else if (code == GT)
12731 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12732 if (compare_code != UNKNOWN
12733 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12734 && (cf == -1 || ct == -1))
12736 /* If lea code below could be used, only optimize
12737 if it results in a 2 insn sequence. */
12739 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12740 || diff == 3 || diff == 5 || diff == 9)
12741 || (compare_code == LT && ct == -1)
12742 || (compare_code == GE && cf == -1))
12745 * notl op1 (if necessary)
12753 code = reverse_condition (code);
12756 out = emit_store_flag (out, code, ix86_compare_op0,
12757 ix86_compare_op1, VOIDmode, 0, -1);
12759 out = expand_simple_binop (mode, IOR,
12761 out, 1, OPTAB_DIRECT);
12762 if (out != operands[0])
12763 emit_move_insn (operands[0], out);
12765 return 1; /* DONE */
12770 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12771 || diff == 3 || diff == 5 || diff == 9)
12772 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12774 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12780 * lea cf(dest*(ct-cf)),dest
12784 * This also catches the degenerate setcc-only case.
12790 out = emit_store_flag (out, code, ix86_compare_op0,
12791 ix86_compare_op1, VOIDmode, 0, 1);
12794 /* On x86_64 the lea instruction operates on Pmode, so we need
12795 to get arithmetics done in proper mode to match. */
12797 tmp = copy_rtx (out);
12801 out1 = copy_rtx (out);
12802 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12806 tmp = gen_rtx_PLUS (mode, tmp, out1);
12812 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12815 if (!rtx_equal_p (tmp, out))
12818 out = force_operand (tmp, copy_rtx (out));
12820 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12822 if (!rtx_equal_p (out, operands[0]))
12823 emit_move_insn (operands[0], copy_rtx (out));
12825 return 1; /* DONE */
12829 * General case: Jumpful:
12830 * xorl dest,dest cmpl op1, op2
12831 * cmpl op1, op2 movl ct, dest
12832 * setcc dest jcc 1f
12833 * decl dest movl cf, dest
12834 * andl (cf-ct),dest 1:
12837 * Size 20. Size 14.
12839 * This is reasonably steep, but branch mispredict costs are
12840 * high on modern cpus, so consider failing only if optimizing
12844 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12845 && BRANCH_COST >= 2)
12849 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12854 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12856 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12858 /* We may be reversing unordered compare to normal compare,
12859 that is not valid in general (we may convert non-trapping
12860 condition to trapping one), however on i386 we currently
12861 emit all comparisons unordered. */
12862 code = reverse_condition_maybe_unordered (code);
12866 code = reverse_condition (code);
12867 if (compare_code != UNKNOWN)
12868 compare_code = reverse_condition (compare_code);
12872 if (compare_code != UNKNOWN)
12874 /* notl op1 (if needed)
12879 For x < 0 (resp. x <= -1) there will be no notl,
12880 so if possible swap the constants to get rid of the
12882 True/false will be -1/0 while code below (store flag
12883 followed by decrement) is 0/-1, so the constants need
12884 to be exchanged once more. */
12886 if (compare_code == GE || !cf)
12888 code = reverse_condition (code);
12893 HOST_WIDE_INT tmp = cf;
12898 out = emit_store_flag (out, code, ix86_compare_op0,
12899 ix86_compare_op1, VOIDmode, 0, -1);
12903 out = emit_store_flag (out, code, ix86_compare_op0,
12904 ix86_compare_op1, VOIDmode, 0, 1);
12906 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
12907 copy_rtx (out), 1, OPTAB_DIRECT);
12910 out = expand_simple_binop (mode, AND, copy_rtx (out),
12911 gen_int_mode (cf - ct, mode),
12912 copy_rtx (out), 1, OPTAB_DIRECT);
12914 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
12915 copy_rtx (out), 1, OPTAB_DIRECT);
12916 if (!rtx_equal_p (out, operands[0]))
12917 emit_move_insn (operands[0], copy_rtx (out));
12919 return 1; /* DONE */
12923 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12925 /* Try a few things more with specific constants and a variable. */
12928 rtx var, orig_out, out, tmp;
12930 if (BRANCH_COST <= 2)
12931 return 0; /* FAIL */
12933 /* If one of the two operands is an interesting constant, load a
12934 constant with the above and mask it in with a logical operation. */
12936 if (CONST_INT_P (operands[2]))
12939 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
12940 operands[3] = constm1_rtx, op = and_optab;
12941 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
12942 operands[3] = const0_rtx, op = ior_optab;
12944 return 0; /* FAIL */
12946 else if (CONST_INT_P (operands[3]))
12949 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
12950 operands[2] = constm1_rtx, op = and_optab;
12951 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
12952 operands[2] = const0_rtx, op = ior_optab;
12954 return 0; /* FAIL */
12957 return 0; /* FAIL */
12959 orig_out = operands[0];
12960 tmp = gen_reg_rtx (mode);
12963 /* Recurse to get the constant loaded. */
12964 if (ix86_expand_int_movcc (operands) == 0)
12965 return 0; /* FAIL */
12967 /* Mask in the interesting variable. */
12968 out = expand_binop (mode, op, var, tmp, orig_out, 0,
12970 if (!rtx_equal_p (out, orig_out))
12971 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
12973 return 1; /* DONE */
12977 * For comparison with above,
12987 if (! nonimmediate_operand (operands[2], mode))
12988 operands[2] = force_reg (mode, operands[2]);
12989 if (! nonimmediate_operand (operands[3], mode))
12990 operands[3] = force_reg (mode, operands[3]);
12992 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12994 rtx tmp = gen_reg_rtx (mode);
12995 emit_move_insn (tmp, operands[3]);
12998 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13000 rtx tmp = gen_reg_rtx (mode);
13001 emit_move_insn (tmp, operands[2]);
13005 if (! register_operand (operands[2], VOIDmode)
13007 || ! register_operand (operands[3], VOIDmode)))
13008 operands[2] = force_reg (mode, operands[2]);
13011 && ! register_operand (operands[3], VOIDmode))
13012 operands[3] = force_reg (mode, operands[3]);
13014 emit_insn (compare_seq);
13015 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13016 gen_rtx_IF_THEN_ELSE (mode,
13017 compare_op, operands[2],
13020 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13021 gen_rtx_IF_THEN_ELSE (mode,
13023 copy_rtx (operands[3]),
13024 copy_rtx (operands[0]))));
13026 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13027 gen_rtx_IF_THEN_ELSE (mode,
13029 copy_rtx (operands[2]),
13030 copy_rtx (operands[0]))));
13032 return 1; /* DONE */
13035 /* Swap, force into registers, or otherwise massage the two operands
13036 to an sse comparison with a mask result. Thus we differ a bit from
13037 ix86_prepare_fp_compare_args which expects to produce a flags result.
13039 The DEST operand exists to help determine whether to commute commutative
13040 operators. The POP0/POP1 operands are updated in place. The new
13041 comparison code is returned, or UNKNOWN if not implementable. */
13043 static enum rtx_code
13044 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
13045 rtx *pop0, rtx *pop1)
13053 /* We have no LTGT as an operator. We could implement it with
13054 NE & ORDERED, but this requires an extra temporary. It's
13055 not clear that it's worth it. */
13062 /* These are supported directly. */
13069 /* For commutative operators, try to canonicalize the destination
13070 operand to be first in the comparison - this helps reload to
13071 avoid extra moves. */
13072 if (!dest || !rtx_equal_p (dest, *pop1))
13080 /* These are not supported directly. Swap the comparison operands
13081 to transform into something that is supported. */
13085 code = swap_condition (code);
13089 gcc_unreachable ();
13095 /* Detect conditional moves that exactly match min/max operational
13096 semantics. Note that this is IEEE safe, as long as we don't
13097 interchange the operands.
13099 Returns FALSE if this conditional move doesn't match a MIN/MAX,
13100 and TRUE if the operation is successful and instructions are emitted. */
13103 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
13104 rtx cmp_op1, rtx if_true, rtx if_false)
13106 enum machine_mode mode;
13112 else if (code == UNGE)
13115 if_true = if_false;
13121 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
13123 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
13128 mode = GET_MODE (dest);
13130 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
13131 but MODE may be a vector mode and thus not appropriate. */
13132 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
13134 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
13137 if_true = force_reg (mode, if_true);
13138 v = gen_rtvec (2, if_true, if_false);
13139 tmp = gen_rtx_UNSPEC (mode, v, u);
13143 code = is_min ? SMIN : SMAX;
13144 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
13147 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
13151 /* Expand an sse vector comparison. Return the register with the result. */
13154 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
13155 rtx op_true, rtx op_false)
13157 enum machine_mode mode = GET_MODE (dest);
13160 cmp_op0 = force_reg (mode, cmp_op0);
13161 if (!nonimmediate_operand (cmp_op1, mode))
13162 cmp_op1 = force_reg (mode, cmp_op1);
13165 || reg_overlap_mentioned_p (dest, op_true)
13166 || reg_overlap_mentioned_p (dest, op_false))
13167 dest = gen_reg_rtx (mode);
13169 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
13170 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13175 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
13176 operations. This is used for both scalar and vector conditional moves. */
13179 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
13181 enum machine_mode mode = GET_MODE (dest);
13186 rtx pcmov = gen_rtx_SET (mode, dest,
13187 gen_rtx_IF_THEN_ELSE (mode, cmp,
13192 else if (op_false == CONST0_RTX (mode))
13194 op_true = force_reg (mode, op_true);
13195 x = gen_rtx_AND (mode, cmp, op_true);
13196 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13198 else if (op_true == CONST0_RTX (mode))
13200 op_false = force_reg (mode, op_false);
13201 x = gen_rtx_NOT (mode, cmp);
13202 x = gen_rtx_AND (mode, x, op_false);
13203 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13207 op_true = force_reg (mode, op_true);
13208 op_false = force_reg (mode, op_false);
13210 t2 = gen_reg_rtx (mode);
13212 t3 = gen_reg_rtx (mode);
13216 x = gen_rtx_AND (mode, op_true, cmp);
13217 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
13219 x = gen_rtx_NOT (mode, cmp);
13220 x = gen_rtx_AND (mode, x, op_false);
13221 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
13223 x = gen_rtx_IOR (mode, t3, t2);
13224 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13228 /* Expand a floating-point conditional move. Return true if successful. */
13231 ix86_expand_fp_movcc (rtx operands[])
13233 enum machine_mode mode = GET_MODE (operands[0]);
13234 enum rtx_code code = GET_CODE (operands[1]);
13235 rtx tmp, compare_op, second_test, bypass_test;
13237 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
13239 enum machine_mode cmode;
13241 /* Since we've no cmove for sse registers, don't force bad register
13242 allocation just to gain access to it. Deny movcc when the
13243 comparison mode doesn't match the move mode. */
13244 cmode = GET_MODE (ix86_compare_op0);
13245 if (cmode == VOIDmode)
13246 cmode = GET_MODE (ix86_compare_op1);
13250 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13252 &ix86_compare_op1);
13253 if (code == UNKNOWN)
13256 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
13257 ix86_compare_op1, operands[2],
13261 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
13262 ix86_compare_op1, operands[2], operands[3]);
13263 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
13267 /* The floating point conditional move instructions don't directly
13268 support conditions resulting from a signed integer comparison. */
13270 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13272 /* The floating point conditional move instructions don't directly
13273 support signed integer comparisons. */
13275 if (!fcmov_comparison_operator (compare_op, VOIDmode))
13277 gcc_assert (!second_test && !bypass_test);
13278 tmp = gen_reg_rtx (QImode);
13279 ix86_expand_setcc (code, tmp);
13281 ix86_compare_op0 = tmp;
13282 ix86_compare_op1 = const0_rtx;
13283 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13285 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13287 tmp = gen_reg_rtx (mode);
13288 emit_move_insn (tmp, operands[3]);
13291 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13293 tmp = gen_reg_rtx (mode);
13294 emit_move_insn (tmp, operands[2]);
13298 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13299 gen_rtx_IF_THEN_ELSE (mode, compare_op,
13300 operands[2], operands[3])));
13302 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13303 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
13304 operands[3], operands[0])));
13306 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13307 gen_rtx_IF_THEN_ELSE (mode, second_test,
13308 operands[2], operands[0])));
13313 /* Expand a floating-point vector conditional move; a vcond operation
13314 rather than a movcc operation. */
13317 ix86_expand_fp_vcond (rtx operands[])
13319 enum rtx_code code = GET_CODE (operands[3]);
13322 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13323 &operands[4], &operands[5]);
13324 if (code == UNKNOWN)
13327 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
13328 operands[5], operands[1], operands[2]))
13331 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
13332 operands[1], operands[2]);
13333 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
13337 /* Expand a signed/unsigned integral vector conditional move. */
13340 ix86_expand_int_vcond (rtx operands[])
13342 enum machine_mode mode = GET_MODE (operands[0]);
13343 enum rtx_code code = GET_CODE (operands[3]);
13344 bool negate = false;
13347 cop0 = operands[4];
13348 cop1 = operands[5];
13350 /* Canonicalize the comparison to EQ, GT, GTU. */
13361 code = reverse_condition (code);
13367 code = reverse_condition (code);
13373 code = swap_condition (code);
13374 x = cop0, cop0 = cop1, cop1 = x;
13378 gcc_unreachable ();
13381 /* Only SSE4.1/SSE4.2 supports V2DImode. */
13382 if (mode == V2DImode)
13387 /* SSE4.1 supports EQ. */
13388 if (!TARGET_SSE4_1)
13394 /* SSE4.2 supports GT/GTU. */
13395 if (!TARGET_SSE4_2)
13400 gcc_unreachable ();
13404 /* Unsigned parallel compare is not supported by the hardware. Play some
13405 tricks to turn this into a signed comparison against 0. */
13408 cop0 = force_reg (mode, cop0);
13417 /* Perform a parallel modulo subtraction. */
13418 t1 = gen_reg_rtx (mode);
13419 emit_insn ((mode == V4SImode
13421 : gen_subv2di3) (t1, cop0, cop1));
13423 /* Extract the original sign bit of op0. */
13424 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
13426 t2 = gen_reg_rtx (mode);
13427 emit_insn ((mode == V4SImode
13429 : gen_andv2di3) (t2, cop0, mask));
13431 /* XOR it back into the result of the subtraction. This results
13432 in the sign bit set iff we saw unsigned underflow. */
13433 x = gen_reg_rtx (mode);
13434 emit_insn ((mode == V4SImode
13436 : gen_xorv2di3) (x, t1, t2));
13444 /* Perform a parallel unsigned saturating subtraction. */
13445 x = gen_reg_rtx (mode);
13446 emit_insn (gen_rtx_SET (VOIDmode, x,
13447 gen_rtx_US_MINUS (mode, cop0, cop1)));
13454 gcc_unreachable ();
13458 cop1 = CONST0_RTX (mode);
13461 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13462 operands[1+negate], operands[2-negate]);
13464 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13465 operands[2-negate]);
13469 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13470 true if we should do zero extension, else sign extension. HIGH_P is
13471 true if we want the N/2 high elements, else the low elements. */
13474 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13476 enum machine_mode imode = GET_MODE (operands[1]);
13477 rtx (*unpack)(rtx, rtx, rtx);
13484 unpack = gen_vec_interleave_highv16qi;
13486 unpack = gen_vec_interleave_lowv16qi;
13490 unpack = gen_vec_interleave_highv8hi;
13492 unpack = gen_vec_interleave_lowv8hi;
13496 unpack = gen_vec_interleave_highv4si;
13498 unpack = gen_vec_interleave_lowv4si;
13501 gcc_unreachable ();
13504 dest = gen_lowpart (imode, operands[0]);
13507 se = force_reg (imode, CONST0_RTX (imode));
13509 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13510 operands[1], pc_rtx, pc_rtx);
13512 emit_insn (unpack (dest, operands[1], se));
13515 /* This function performs the same task as ix86_expand_sse_unpack,
13516 but with SSE4.1 instructions. */
13519 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13521 enum machine_mode imode = GET_MODE (operands[1]);
13522 rtx (*unpack)(rtx, rtx);
13529 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13531 unpack = gen_sse4_1_extendv8qiv8hi2;
13535 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13537 unpack = gen_sse4_1_extendv4hiv4si2;
13541 unpack = gen_sse4_1_zero_extendv2siv2di2;
13543 unpack = gen_sse4_1_extendv2siv2di2;
13546 gcc_unreachable ();
13549 dest = operands[0];
13552 /* Shift higher 8 bytes to lower 8 bytes. */
13553 src = gen_reg_rtx (imode);
13554 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13555 gen_lowpart (TImode, operands[1]),
13561 emit_insn (unpack (dest, src));
13564 /* This function performs the same task as ix86_expand_sse_unpack,
13565 but with amdfam15 instructions. */
13567 #define PPERM_SRC 0x00 /* copy source */
13568 #define PPERM_INVERT 0x20 /* invert source */
13569 #define PPERM_REVERSE 0x40 /* bit reverse source */
13570 #define PPERM_REV_INV 0x60 /* bit reverse & invert src */
13571 #define PPERM_ZERO 0x80 /* all 0's */
13572 #define PPERM_ONES 0xa0 /* all 1's */
13573 #define PPERM_SIGN 0xc0 /* propagate sign bit */
13574 #define PPERM_INV_SIGN 0xe0 /* invert & propagate sign */
13576 #define PPERM_SRC1 0x00 /* use first source byte */
13577 #define PPERM_SRC2 0x10 /* use second source byte */
13580 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13582 enum machine_mode imode = GET_MODE (operands[1]);
13583 int pperm_bytes[16];
13585 int h = (high_p) ? 8 : 0;
13588 rtvec v = rtvec_alloc (16);
13591 rtx op0 = operands[0], op1 = operands[1];
13596 vs = rtvec_alloc (8);
13597 h2 = (high_p) ? 8 : 0;
13598 for (i = 0; i < 8; i++)
13600 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
13601 pperm_bytes[2*i+1] = ((unsigned_p)
13603 : PPERM_SIGN | PPERM_SRC2 | i | h);
13606 for (i = 0; i < 16; i++)
13607 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13609 for (i = 0; i < 8; i++)
13610 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13612 p = gen_rtx_PARALLEL (VOIDmode, vs);
13613 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13615 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
13617 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
13621 vs = rtvec_alloc (4);
13622 h2 = (high_p) ? 4 : 0;
13623 for (i = 0; i < 4; i++)
13625 sign_extend = ((unsigned_p)
13627 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
13628 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
13629 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
13630 pperm_bytes[4*i+2] = sign_extend;
13631 pperm_bytes[4*i+3] = sign_extend;
13634 for (i = 0; i < 16; i++)
13635 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13637 for (i = 0; i < 4; i++)
13638 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13640 p = gen_rtx_PARALLEL (VOIDmode, vs);
13641 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13643 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
13645 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
13649 vs = rtvec_alloc (2);
13650 h2 = (high_p) ? 2 : 0;
13651 for (i = 0; i < 2; i++)
13653 sign_extend = ((unsigned_p)
13655 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
13656 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
13657 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
13658 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
13659 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
13660 pperm_bytes[8*i+4] = sign_extend;
13661 pperm_bytes[8*i+5] = sign_extend;
13662 pperm_bytes[8*i+6] = sign_extend;
13663 pperm_bytes[8*i+7] = sign_extend;
13666 for (i = 0; i < 16; i++)
13667 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13669 for (i = 0; i < 2; i++)
13670 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13672 p = gen_rtx_PARALLEL (VOIDmode, vs);
13673 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13675 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
13677 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
13681 gcc_unreachable ();
13687 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
13688 next narrower integer vector type */
13690 ix86_expand_sse5_pack (rtx operands[3])
13692 enum machine_mode imode = GET_MODE (operands[0]);
13693 int pperm_bytes[16];
13695 rtvec v = rtvec_alloc (16);
13697 rtx op0 = operands[0];
13698 rtx op1 = operands[1];
13699 rtx op2 = operands[2];
13704 for (i = 0; i < 8; i++)
13706 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
13707 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
13710 for (i = 0; i < 16; i++)
13711 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13713 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13714 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
13718 for (i = 0; i < 4; i++)
13720 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
13721 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
13722 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
13723 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
13726 for (i = 0; i < 16; i++)
13727 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13729 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13730 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
13734 for (i = 0; i < 2; i++)
13736 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
13737 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
13738 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
13739 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
13740 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
13741 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
13742 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
13743 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
13746 for (i = 0; i < 16; i++)
13747 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13749 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13750 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
13754 gcc_unreachable ();
13760 /* Expand conditional increment or decrement using adb/sbb instructions.
13761 The default case using setcc followed by the conditional move can be
13762 done by generic code. */
13764 ix86_expand_int_addcc (rtx operands[])
13766 enum rtx_code code = GET_CODE (operands[1]);
13768 rtx val = const0_rtx;
13769 bool fpcmp = false;
13770 enum machine_mode mode = GET_MODE (operands[0]);
13772 if (operands[3] != const1_rtx
13773 && operands[3] != constm1_rtx)
13775 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13776 ix86_compare_op1, &compare_op))
13778 code = GET_CODE (compare_op);
13780 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13781 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13784 code = ix86_fp_compare_code_to_integer (code);
13791 PUT_CODE (compare_op,
13792 reverse_condition_maybe_unordered
13793 (GET_CODE (compare_op)));
13795 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
13797 PUT_MODE (compare_op, mode);
13799 /* Construct either adc or sbb insn. */
13800 if ((code == LTU) == (operands[3] == constm1_rtx))
13802 switch (GET_MODE (operands[0]))
13805 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
13808 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
13811 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
13814 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13817 gcc_unreachable ();
13822 switch (GET_MODE (operands[0]))
13825 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
13828 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
13831 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
13834 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13837 gcc_unreachable ();
13840 return 1; /* DONE */
13844 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
13845 works for floating pointer parameters and nonoffsetable memories.
13846 For pushes, it returns just stack offsets; the values will be saved
13847 in the right order. Maximally three parts are generated. */
13850 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
13855 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
13857 size = (GET_MODE_SIZE (mode) + 4) / 8;
13859 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
13860 gcc_assert (size >= 2 && size <= 3);
13862 /* Optimize constant pool reference to immediates. This is used by fp
13863 moves, that force all constants to memory to allow combining. */
13864 if (MEM_P (operand) && MEM_READONLY_P (operand))
13866 rtx tmp = maybe_get_pool_constant (operand);
13871 if (MEM_P (operand) && !offsettable_memref_p (operand))
13873 /* The only non-offsetable memories we handle are pushes. */
13874 int ok = push_operand (operand, VOIDmode);
13878 operand = copy_rtx (operand);
13879 PUT_MODE (operand, Pmode);
13880 parts[0] = parts[1] = parts[2] = operand;
13884 if (GET_CODE (operand) == CONST_VECTOR)
13886 enum machine_mode imode = int_mode_for_mode (mode);
13887 /* Caution: if we looked through a constant pool memory above,
13888 the operand may actually have a different mode now. That's
13889 ok, since we want to pun this all the way back to an integer. */
13890 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
13891 gcc_assert (operand != NULL);
13897 if (mode == DImode)
13898 split_di (&operand, 1, &parts[0], &parts[1]);
13901 if (REG_P (operand))
13903 gcc_assert (reload_completed);
13904 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
13905 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
13907 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
13909 else if (offsettable_memref_p (operand))
13911 operand = adjust_address (operand, SImode, 0);
13912 parts[0] = operand;
13913 parts[1] = adjust_address (operand, SImode, 4);
13915 parts[2] = adjust_address (operand, SImode, 8);
13917 else if (GET_CODE (operand) == CONST_DOUBLE)
13922 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13926 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
13927 parts[2] = gen_int_mode (l[2], SImode);
13930 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
13933 gcc_unreachable ();
13935 parts[1] = gen_int_mode (l[1], SImode);
13936 parts[0] = gen_int_mode (l[0], SImode);
13939 gcc_unreachable ();
13944 if (mode == TImode)
13945 split_ti (&operand, 1, &parts[0], &parts[1]);
13946 if (mode == XFmode || mode == TFmode)
13948 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
13949 if (REG_P (operand))
13951 gcc_assert (reload_completed);
13952 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
13953 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
13955 else if (offsettable_memref_p (operand))
13957 operand = adjust_address (operand, DImode, 0);
13958 parts[0] = operand;
13959 parts[1] = adjust_address (operand, upper_mode, 8);
13961 else if (GET_CODE (operand) == CONST_DOUBLE)
13966 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13967 real_to_target (l, &r, mode);
13969 /* Do not use shift by 32 to avoid warning on 32bit systems. */
13970 if (HOST_BITS_PER_WIDE_INT >= 64)
13973 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
13974 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
13977 parts[0] = immed_double_const (l[0], l[1], DImode);
13979 if (upper_mode == SImode)
13980 parts[1] = gen_int_mode (l[2], SImode);
13981 else if (HOST_BITS_PER_WIDE_INT >= 64)
13984 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
13985 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
13988 parts[1] = immed_double_const (l[2], l[3], DImode);
13991 gcc_unreachable ();
13998 /* Emit insns to perform a move or push of DI, DF, and XF values.
13999 Return false when normal moves are needed; true when all required
14000 insns have been emitted. Operands 2-4 contain the input values
14001 int the correct order; operands 5-7 contain the output values. */
14004 ix86_split_long_move (rtx operands[])
14009 int collisions = 0;
14010 enum machine_mode mode = GET_MODE (operands[0]);
14012 /* The DFmode expanders may ask us to move double.
14013 For 64bit target this is single move. By hiding the fact
14014 here we simplify i386.md splitters. */
14015 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
14017 /* Optimize constant pool reference to immediates. This is used by
14018 fp moves, that force all constants to memory to allow combining. */
14020 if (MEM_P (operands[1])
14021 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
14022 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
14023 operands[1] = get_pool_constant (XEXP (operands[1], 0));
14024 if (push_operand (operands[0], VOIDmode))
14026 operands[0] = copy_rtx (operands[0]);
14027 PUT_MODE (operands[0], Pmode);
14030 operands[0] = gen_lowpart (DImode, operands[0]);
14031 operands[1] = gen_lowpart (DImode, operands[1]);
14032 emit_move_insn (operands[0], operands[1]);
14036 /* The only non-offsettable memory we handle is push. */
14037 if (push_operand (operands[0], VOIDmode))
14040 gcc_assert (!MEM_P (operands[0])
14041 || offsettable_memref_p (operands[0]));
14043 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
14044 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
14046 /* When emitting push, take care for source operands on the stack. */
14047 if (push && MEM_P (operands[1])
14048 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
14051 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
14052 XEXP (part[1][2], 0));
14053 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
14054 XEXP (part[1][1], 0));
14057 /* We need to do copy in the right order in case an address register
14058 of the source overlaps the destination. */
14059 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
14061 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
14063 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14066 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
14069 /* Collision in the middle part can be handled by reordering. */
14070 if (collisions == 1 && nparts == 3
14071 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14074 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
14075 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
14078 /* If there are more collisions, we can't handle it by reordering.
14079 Do an lea to the last part and use only one colliding move. */
14080 else if (collisions > 1)
14086 base = part[0][nparts - 1];
14088 /* Handle the case when the last part isn't valid for lea.
14089 Happens in 64-bit mode storing the 12-byte XFmode. */
14090 if (GET_MODE (base) != Pmode)
14091 base = gen_rtx_REG (Pmode, REGNO (base));
14093 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
14094 part[1][0] = replace_equiv_address (part[1][0], base);
14095 part[1][1] = replace_equiv_address (part[1][1],
14096 plus_constant (base, UNITS_PER_WORD));
14098 part[1][2] = replace_equiv_address (part[1][2],
14099 plus_constant (base, 8));
14109 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
14110 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
14111 emit_move_insn (part[0][2], part[1][2]);
14116 /* In 64bit mode we don't have 32bit push available. In case this is
14117 register, it is OK - we will just use larger counterpart. We also
14118 retype memory - these comes from attempt to avoid REX prefix on
14119 moving of second half of TFmode value. */
14120 if (GET_MODE (part[1][1]) == SImode)
14122 switch (GET_CODE (part[1][1]))
14125 part[1][1] = adjust_address (part[1][1], DImode, 0);
14129 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
14133 gcc_unreachable ();
14136 if (GET_MODE (part[1][0]) == SImode)
14137 part[1][0] = part[1][1];
14140 emit_move_insn (part[0][1], part[1][1]);
14141 emit_move_insn (part[0][0], part[1][0]);
14145 /* Choose correct order to not overwrite the source before it is copied. */
14146 if ((REG_P (part[0][0])
14147 && REG_P (part[1][1])
14148 && (REGNO (part[0][0]) == REGNO (part[1][1])
14150 && REGNO (part[0][0]) == REGNO (part[1][2]))))
14152 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
14156 operands[2] = part[0][2];
14157 operands[3] = part[0][1];
14158 operands[4] = part[0][0];
14159 operands[5] = part[1][2];
14160 operands[6] = part[1][1];
14161 operands[7] = part[1][0];
14165 operands[2] = part[0][1];
14166 operands[3] = part[0][0];
14167 operands[5] = part[1][1];
14168 operands[6] = part[1][0];
14175 operands[2] = part[0][0];
14176 operands[3] = part[0][1];
14177 operands[4] = part[0][2];
14178 operands[5] = part[1][0];
14179 operands[6] = part[1][1];
14180 operands[7] = part[1][2];
14184 operands[2] = part[0][0];
14185 operands[3] = part[0][1];
14186 operands[5] = part[1][0];
14187 operands[6] = part[1][1];
14191 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
14194 if (CONST_INT_P (operands[5])
14195 && operands[5] != const0_rtx
14196 && REG_P (operands[2]))
14198 if (CONST_INT_P (operands[6])
14199 && INTVAL (operands[6]) == INTVAL (operands[5]))
14200 operands[6] = operands[2];
14203 && CONST_INT_P (operands[7])
14204 && INTVAL (operands[7]) == INTVAL (operands[5]))
14205 operands[7] = operands[2];
14209 && CONST_INT_P (operands[6])
14210 && operands[6] != const0_rtx
14211 && REG_P (operands[3])
14212 && CONST_INT_P (operands[7])
14213 && INTVAL (operands[7]) == INTVAL (operands[6]))
14214 operands[7] = operands[3];
14217 emit_move_insn (operands[2], operands[5]);
14218 emit_move_insn (operands[3], operands[6]);
14220 emit_move_insn (operands[4], operands[7]);
14225 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
14226 left shift by a constant, either using a single shift or
14227 a sequence of add instructions. */
14230 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
14234 emit_insn ((mode == DImode
14236 : gen_adddi3) (operand, operand, operand));
14238 else if (!optimize_size
14239 && count * ix86_cost->add <= ix86_cost->shift_const)
14242 for (i=0; i<count; i++)
14244 emit_insn ((mode == DImode
14246 : gen_adddi3) (operand, operand, operand));
14250 emit_insn ((mode == DImode
14252 : gen_ashldi3) (operand, operand, GEN_INT (count)));
14256 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
14258 rtx low[2], high[2];
14260 const int single_width = mode == DImode ? 32 : 64;
14262 if (CONST_INT_P (operands[2]))
14264 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14265 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14267 if (count >= single_width)
14269 emit_move_insn (high[0], low[1]);
14270 emit_move_insn (low[0], const0_rtx);
14272 if (count > single_width)
14273 ix86_expand_ashl_const (high[0], count - single_width, mode);
14277 if (!rtx_equal_p (operands[0], operands[1]))
14278 emit_move_insn (operands[0], operands[1]);
14279 emit_insn ((mode == DImode
14281 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
14282 ix86_expand_ashl_const (low[0], count, mode);
14287 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14289 if (operands[1] == const1_rtx)
14291 /* Assuming we've chosen a QImode capable registers, then 1 << N
14292 can be done with two 32/64-bit shifts, no branches, no cmoves. */
14293 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
14295 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
14297 ix86_expand_clear (low[0]);
14298 ix86_expand_clear (high[0]);
14299 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
14301 d = gen_lowpart (QImode, low[0]);
14302 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14303 s = gen_rtx_EQ (QImode, flags, const0_rtx);
14304 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14306 d = gen_lowpart (QImode, high[0]);
14307 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14308 s = gen_rtx_NE (QImode, flags, const0_rtx);
14309 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14312 /* Otherwise, we can get the same results by manually performing
14313 a bit extract operation on bit 5/6, and then performing the two
14314 shifts. The two methods of getting 0/1 into low/high are exactly
14315 the same size. Avoiding the shift in the bit extract case helps
14316 pentium4 a bit; no one else seems to care much either way. */
14321 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
14322 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
14324 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
14325 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
14327 emit_insn ((mode == DImode
14329 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
14330 emit_insn ((mode == DImode
14332 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
14333 emit_move_insn (low[0], high[0]);
14334 emit_insn ((mode == DImode
14336 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
14339 emit_insn ((mode == DImode
14341 : gen_ashldi3) (low[0], low[0], operands[2]));
14342 emit_insn ((mode == DImode
14344 : gen_ashldi3) (high[0], high[0], operands[2]));
14348 if (operands[1] == constm1_rtx)
14350 /* For -1 << N, we can avoid the shld instruction, because we
14351 know that we're shifting 0...31/63 ones into a -1. */
14352 emit_move_insn (low[0], constm1_rtx);
14354 emit_move_insn (high[0], low[0]);
14356 emit_move_insn (high[0], constm1_rtx);
14360 if (!rtx_equal_p (operands[0], operands[1]))
14361 emit_move_insn (operands[0], operands[1]);
14363 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14364 emit_insn ((mode == DImode
14366 : gen_x86_64_shld) (high[0], low[0], operands[2]));
14369 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
14371 if (TARGET_CMOVE && scratch)
14373 ix86_expand_clear (scratch);
14374 emit_insn ((mode == DImode
14375 ? gen_x86_shift_adj_1
14376 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
14379 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
14383 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
14385 rtx low[2], high[2];
14387 const int single_width = mode == DImode ? 32 : 64;
14389 if (CONST_INT_P (operands[2]))
14391 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14392 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14394 if (count == single_width * 2 - 1)
14396 emit_move_insn (high[0], high[1]);
14397 emit_insn ((mode == DImode
14399 : gen_ashrdi3) (high[0], high[0],
14400 GEN_INT (single_width - 1)));
14401 emit_move_insn (low[0], high[0]);
14404 else if (count >= single_width)
14406 emit_move_insn (low[0], high[1]);
14407 emit_move_insn (high[0], low[0]);
14408 emit_insn ((mode == DImode
14410 : gen_ashrdi3) (high[0], high[0],
14411 GEN_INT (single_width - 1)));
14412 if (count > single_width)
14413 emit_insn ((mode == DImode
14415 : gen_ashrdi3) (low[0], low[0],
14416 GEN_INT (count - single_width)));
14420 if (!rtx_equal_p (operands[0], operands[1]))
14421 emit_move_insn (operands[0], operands[1]);
14422 emit_insn ((mode == DImode
14424 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14425 emit_insn ((mode == DImode
14427 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
14432 if (!rtx_equal_p (operands[0], operands[1]))
14433 emit_move_insn (operands[0], operands[1]);
14435 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14437 emit_insn ((mode == DImode
14439 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14440 emit_insn ((mode == DImode
14442 : gen_ashrdi3) (high[0], high[0], operands[2]));
14444 if (TARGET_CMOVE && scratch)
14446 emit_move_insn (scratch, high[0]);
14447 emit_insn ((mode == DImode
14449 : gen_ashrdi3) (scratch, scratch,
14450 GEN_INT (single_width - 1)));
14451 emit_insn ((mode == DImode
14452 ? gen_x86_shift_adj_1
14453 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14457 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
14462 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
14464 rtx low[2], high[2];
14466 const int single_width = mode == DImode ? 32 : 64;
14468 if (CONST_INT_P (operands[2]))
14470 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14471 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14473 if (count >= single_width)
14475 emit_move_insn (low[0], high[1]);
14476 ix86_expand_clear (high[0]);
14478 if (count > single_width)
14479 emit_insn ((mode == DImode
14481 : gen_lshrdi3) (low[0], low[0],
14482 GEN_INT (count - single_width)));
14486 if (!rtx_equal_p (operands[0], operands[1]))
14487 emit_move_insn (operands[0], operands[1]);
14488 emit_insn ((mode == DImode
14490 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14491 emit_insn ((mode == DImode
14493 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
14498 if (!rtx_equal_p (operands[0], operands[1]))
14499 emit_move_insn (operands[0], operands[1]);
14501 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14503 emit_insn ((mode == DImode
14505 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14506 emit_insn ((mode == DImode
14508 : gen_lshrdi3) (high[0], high[0], operands[2]));
14510 /* Heh. By reversing the arguments, we can reuse this pattern. */
14511 if (TARGET_CMOVE && scratch)
14513 ix86_expand_clear (scratch);
14514 emit_insn ((mode == DImode
14515 ? gen_x86_shift_adj_1
14516 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14520 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
14524 /* Predict just emitted jump instruction to be taken with probability PROB. */
14526 predict_jump (int prob)
14528 rtx insn = get_last_insn ();
14529 gcc_assert (JUMP_P (insn));
14531 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14536 /* Helper function for the string operations below. Dest VARIABLE whether
14537 it is aligned to VALUE bytes. If true, jump to the label. */
14539 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
14541 rtx label = gen_label_rtx ();
14542 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
14543 if (GET_MODE (variable) == DImode)
14544 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
14546 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
14547 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
14550 predict_jump (REG_BR_PROB_BASE * 50 / 100);
14552 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14556 /* Adjust COUNTER by the VALUE. */
14558 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
14560 if (GET_MODE (countreg) == DImode)
14561 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
14563 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
14566 /* Zero extend possibly SImode EXP to Pmode register. */
14568 ix86_zero_extend_to_Pmode (rtx exp)
14571 if (GET_MODE (exp) == VOIDmode)
14572 return force_reg (Pmode, exp);
14573 if (GET_MODE (exp) == Pmode)
14574 return copy_to_mode_reg (Pmode, exp);
14575 r = gen_reg_rtx (Pmode);
14576 emit_insn (gen_zero_extendsidi2 (r, exp));
14580 /* Divide COUNTREG by SCALE. */
14582 scale_counter (rtx countreg, int scale)
14585 rtx piece_size_mask;
14589 if (CONST_INT_P (countreg))
14590 return GEN_INT (INTVAL (countreg) / scale);
14591 gcc_assert (REG_P (countreg));
14593 piece_size_mask = GEN_INT (scale - 1);
14594 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
14595 GEN_INT (exact_log2 (scale)),
14596 NULL, 1, OPTAB_DIRECT);
14600 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
14601 DImode for constant loop counts. */
14603 static enum machine_mode
14604 counter_mode (rtx count_exp)
14606 if (GET_MODE (count_exp) != VOIDmode)
14607 return GET_MODE (count_exp);
14608 if (GET_CODE (count_exp) != CONST_INT)
14610 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
14615 /* When SRCPTR is non-NULL, output simple loop to move memory
14616 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
14617 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
14618 equivalent loop to set memory by VALUE (supposed to be in MODE).
14620 The size is rounded down to whole number of chunk size moved at once.
14621 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
14625 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
14626 rtx destptr, rtx srcptr, rtx value,
14627 rtx count, enum machine_mode mode, int unroll,
14630 rtx out_label, top_label, iter, tmp;
14631 enum machine_mode iter_mode = counter_mode (count);
14632 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
14633 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
14639 top_label = gen_label_rtx ();
14640 out_label = gen_label_rtx ();
14641 iter = gen_reg_rtx (iter_mode);
14643 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14644 NULL, 1, OPTAB_DIRECT);
14645 /* Those two should combine. */
14646 if (piece_size == const1_rtx)
14648 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14650 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14652 emit_move_insn (iter, const0_rtx);
14654 emit_label (top_label);
14656 tmp = convert_modes (Pmode, iter_mode, iter, true);
14657 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14658 destmem = change_address (destmem, mode, x_addr);
14662 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14663 srcmem = change_address (srcmem, mode, y_addr);
14665 /* When unrolling for chips that reorder memory reads and writes,
14666 we can save registers by using single temporary.
14667 Also using 4 temporaries is overkill in 32bit mode. */
14668 if (!TARGET_64BIT && 0)
14670 for (i = 0; i < unroll; i++)
14675 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14677 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14679 emit_move_insn (destmem, srcmem);
14685 gcc_assert (unroll <= 4);
14686 for (i = 0; i < unroll; i++)
14688 tmpreg[i] = gen_reg_rtx (mode);
14692 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14694 emit_move_insn (tmpreg[i], srcmem);
14696 for (i = 0; i < unroll; i++)
14701 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14703 emit_move_insn (destmem, tmpreg[i]);
14708 for (i = 0; i < unroll; i++)
14712 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14713 emit_move_insn (destmem, value);
14716 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14717 true, OPTAB_LIB_WIDEN);
14719 emit_move_insn (iter, tmp);
14721 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14723 if (expected_size != -1)
14725 expected_size /= GET_MODE_SIZE (mode) * unroll;
14726 if (expected_size == 0)
14728 else if (expected_size > REG_BR_PROB_BASE)
14729 predict_jump (REG_BR_PROB_BASE - 1);
14731 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14734 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14735 iter = ix86_zero_extend_to_Pmode (iter);
14736 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14737 true, OPTAB_LIB_WIDEN);
14738 if (tmp != destptr)
14739 emit_move_insn (destptr, tmp);
14742 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14743 true, OPTAB_LIB_WIDEN);
14745 emit_move_insn (srcptr, tmp);
14747 emit_label (out_label);
14750 /* Output "rep; mov" instruction.
14751 Arguments have same meaning as for previous function */
14753 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
14754 rtx destptr, rtx srcptr,
14756 enum machine_mode mode)
14762 /* If the size is known, it is shorter to use rep movs. */
14763 if (mode == QImode && CONST_INT_P (count)
14764 && !(INTVAL (count) & 3))
14767 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14768 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14769 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
14770 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
14771 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14772 if (mode != QImode)
14774 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14775 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14776 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14777 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
14778 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14779 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
14783 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14784 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
14786 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
14790 /* Output "rep; stos" instruction.
14791 Arguments have same meaning as for previous function */
14793 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
14795 enum machine_mode mode)
14800 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14801 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14802 value = force_reg (mode, gen_lowpart (mode, value));
14803 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14804 if (mode != QImode)
14806 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14807 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14808 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14811 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14812 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
14816 emit_strmov (rtx destmem, rtx srcmem,
14817 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
14819 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
14820 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
14821 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14824 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
14826 expand_movmem_epilogue (rtx destmem, rtx srcmem,
14827 rtx destptr, rtx srcptr, rtx count, int max_size)
14830 if (CONST_INT_P (count))
14832 HOST_WIDE_INT countval = INTVAL (count);
14835 if ((countval & 0x10) && max_size > 16)
14839 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14840 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
14843 gcc_unreachable ();
14846 if ((countval & 0x08) && max_size > 8)
14849 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14852 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14853 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
14857 if ((countval & 0x04) && max_size > 4)
14859 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14862 if ((countval & 0x02) && max_size > 2)
14864 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14867 if ((countval & 0x01) && max_size > 1)
14869 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14876 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14877 count, 1, OPTAB_DIRECT);
14878 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14879 count, QImode, 1, 4);
14883 /* When there are stringops, we can cheaply increase dest and src pointers.
14884 Otherwise we save code size by maintaining offset (zero is readily
14885 available from preceding rep operation) and using x86 addressing modes.
14887 if (TARGET_SINGLE_STRINGOP)
14891 rtx label = ix86_expand_aligntest (count, 4, true);
14892 src = change_address (srcmem, SImode, srcptr);
14893 dest = change_address (destmem, SImode, destptr);
14894 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14895 emit_label (label);
14896 LABEL_NUSES (label) = 1;
14900 rtx label = ix86_expand_aligntest (count, 2, true);
14901 src = change_address (srcmem, HImode, srcptr);
14902 dest = change_address (destmem, HImode, destptr);
14903 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14904 emit_label (label);
14905 LABEL_NUSES (label) = 1;
14909 rtx label = ix86_expand_aligntest (count, 1, true);
14910 src = change_address (srcmem, QImode, srcptr);
14911 dest = change_address (destmem, QImode, destptr);
14912 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14913 emit_label (label);
14914 LABEL_NUSES (label) = 1;
14919 rtx offset = force_reg (Pmode, const0_rtx);
14924 rtx label = ix86_expand_aligntest (count, 4, true);
14925 src = change_address (srcmem, SImode, srcptr);
14926 dest = change_address (destmem, SImode, destptr);
14927 emit_move_insn (dest, src);
14928 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
14929 true, OPTAB_LIB_WIDEN);
14931 emit_move_insn (offset, tmp);
14932 emit_label (label);
14933 LABEL_NUSES (label) = 1;
14937 rtx label = ix86_expand_aligntest (count, 2, true);
14938 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14939 src = change_address (srcmem, HImode, tmp);
14940 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14941 dest = change_address (destmem, HImode, tmp);
14942 emit_move_insn (dest, src);
14943 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
14944 true, OPTAB_LIB_WIDEN);
14946 emit_move_insn (offset, tmp);
14947 emit_label (label);
14948 LABEL_NUSES (label) = 1;
14952 rtx label = ix86_expand_aligntest (count, 1, true);
14953 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14954 src = change_address (srcmem, QImode, tmp);
14955 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14956 dest = change_address (destmem, QImode, tmp);
14957 emit_move_insn (dest, src);
14958 emit_label (label);
14959 LABEL_NUSES (label) = 1;
14964 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14966 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
14967 rtx count, int max_size)
14970 expand_simple_binop (counter_mode (count), AND, count,
14971 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
14972 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
14973 gen_lowpart (QImode, value), count, QImode,
14977 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14979 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
14983 if (CONST_INT_P (count))
14985 HOST_WIDE_INT countval = INTVAL (count);
14988 if ((countval & 0x10) && max_size > 16)
14992 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14993 emit_insn (gen_strset (destptr, dest, value));
14994 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
14995 emit_insn (gen_strset (destptr, dest, value));
14998 gcc_unreachable ();
15001 if ((countval & 0x08) && max_size > 8)
15005 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15006 emit_insn (gen_strset (destptr, dest, value));
15010 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15011 emit_insn (gen_strset (destptr, dest, value));
15012 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
15013 emit_insn (gen_strset (destptr, dest, value));
15017 if ((countval & 0x04) && max_size > 4)
15019 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15020 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15023 if ((countval & 0x02) && max_size > 2)
15025 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
15026 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15029 if ((countval & 0x01) && max_size > 1)
15031 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
15032 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15039 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
15044 rtx label = ix86_expand_aligntest (count, 16, true);
15047 dest = change_address (destmem, DImode, destptr);
15048 emit_insn (gen_strset (destptr, dest, value));
15049 emit_insn (gen_strset (destptr, dest, value));
15053 dest = change_address (destmem, SImode, destptr);
15054 emit_insn (gen_strset (destptr, dest, value));
15055 emit_insn (gen_strset (destptr, dest, value));
15056 emit_insn (gen_strset (destptr, dest, value));
15057 emit_insn (gen_strset (destptr, dest, value));
15059 emit_label (label);
15060 LABEL_NUSES (label) = 1;
15064 rtx label = ix86_expand_aligntest (count, 8, true);
15067 dest = change_address (destmem, DImode, destptr);
15068 emit_insn (gen_strset (destptr, dest, value));
15072 dest = change_address (destmem, SImode, destptr);
15073 emit_insn (gen_strset (destptr, dest, value));
15074 emit_insn (gen_strset (destptr, dest, value));
15076 emit_label (label);
15077 LABEL_NUSES (label) = 1;
15081 rtx label = ix86_expand_aligntest (count, 4, true);
15082 dest = change_address (destmem, SImode, destptr);
15083 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15084 emit_label (label);
15085 LABEL_NUSES (label) = 1;
15089 rtx label = ix86_expand_aligntest (count, 2, true);
15090 dest = change_address (destmem, HImode, destptr);
15091 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15092 emit_label (label);
15093 LABEL_NUSES (label) = 1;
15097 rtx label = ix86_expand_aligntest (count, 1, true);
15098 dest = change_address (destmem, QImode, destptr);
15099 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15100 emit_label (label);
15101 LABEL_NUSES (label) = 1;
15105 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
15106 DESIRED_ALIGNMENT. */
15108 expand_movmem_prologue (rtx destmem, rtx srcmem,
15109 rtx destptr, rtx srcptr, rtx count,
15110 int align, int desired_alignment)
15112 if (align <= 1 && desired_alignment > 1)
15114 rtx label = ix86_expand_aligntest (destptr, 1, false);
15115 srcmem = change_address (srcmem, QImode, srcptr);
15116 destmem = change_address (destmem, QImode, destptr);
15117 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15118 ix86_adjust_counter (count, 1);
15119 emit_label (label);
15120 LABEL_NUSES (label) = 1;
15122 if (align <= 2 && desired_alignment > 2)
15124 rtx label = ix86_expand_aligntest (destptr, 2, false);
15125 srcmem = change_address (srcmem, HImode, srcptr);
15126 destmem = change_address (destmem, HImode, destptr);
15127 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15128 ix86_adjust_counter (count, 2);
15129 emit_label (label);
15130 LABEL_NUSES (label) = 1;
15132 if (align <= 4 && desired_alignment > 4)
15134 rtx label = ix86_expand_aligntest (destptr, 4, false);
15135 srcmem = change_address (srcmem, SImode, srcptr);
15136 destmem = change_address (destmem, SImode, destptr);
15137 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15138 ix86_adjust_counter (count, 4);
15139 emit_label (label);
15140 LABEL_NUSES (label) = 1;
15142 gcc_assert (desired_alignment <= 8);
15145 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
15146 DESIRED_ALIGNMENT. */
15148 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
15149 int align, int desired_alignment)
15151 if (align <= 1 && desired_alignment > 1)
15153 rtx label = ix86_expand_aligntest (destptr, 1, false);
15154 destmem = change_address (destmem, QImode, destptr);
15155 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
15156 ix86_adjust_counter (count, 1);
15157 emit_label (label);
15158 LABEL_NUSES (label) = 1;
15160 if (align <= 2 && desired_alignment > 2)
15162 rtx label = ix86_expand_aligntest (destptr, 2, false);
15163 destmem = change_address (destmem, HImode, destptr);
15164 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
15165 ix86_adjust_counter (count, 2);
15166 emit_label (label);
15167 LABEL_NUSES (label) = 1;
15169 if (align <= 4 && desired_alignment > 4)
15171 rtx label = ix86_expand_aligntest (destptr, 4, false);
15172 destmem = change_address (destmem, SImode, destptr);
15173 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
15174 ix86_adjust_counter (count, 4);
15175 emit_label (label);
15176 LABEL_NUSES (label) = 1;
15178 gcc_assert (desired_alignment <= 8);
15181 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
15182 static enum stringop_alg
15183 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
15184 int *dynamic_check)
15186 const struct stringop_algs * algs;
15187 /* Algorithms using the rep prefix want at least edi and ecx;
15188 additionally, memset wants eax and memcpy wants esi. Don't
15189 consider such algorithms if the user has appropriated those
15190 registers for their own purposes. */
15191 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
15193 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
15195 #define ALG_USABLE_P(alg) (rep_prefix_usable \
15196 || (alg != rep_prefix_1_byte \
15197 && alg != rep_prefix_4_byte \
15198 && alg != rep_prefix_8_byte))
15200 *dynamic_check = -1;
15202 algs = &ix86_cost->memset[TARGET_64BIT != 0];
15204 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
15205 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
15206 return stringop_alg;
15207 /* rep; movq or rep; movl is the smallest variant. */
15208 else if (optimize_size)
15210 if (!count || (count & 3))
15211 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
15213 return rep_prefix_usable ? rep_prefix_4_byte : loop;
15215 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
15217 else if (expected_size != -1 && expected_size < 4)
15218 return loop_1_byte;
15219 else if (expected_size != -1)
15222 enum stringop_alg alg = libcall;
15223 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15225 /* We get here if the algorithms that were not libcall-based
15226 were rep-prefix based and we are unable to use rep prefixes
15227 based on global register usage. Break out of the loop and
15228 use the heuristic below. */
15229 if (algs->size[i].max == 0)
15231 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
15233 enum stringop_alg candidate = algs->size[i].alg;
15235 if (candidate != libcall && ALG_USABLE_P (candidate))
15237 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
15238 last non-libcall inline algorithm. */
15239 if (TARGET_INLINE_ALL_STRINGOPS)
15241 /* When the current size is best to be copied by a libcall,
15242 but we are still forced to inline, run the heuristic below
15243 that will pick code for medium sized blocks. */
15244 if (alg != libcall)
15248 else if (ALG_USABLE_P (candidate))
15252 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
15254 /* When asked to inline the call anyway, try to pick meaningful choice.
15255 We look for maximal size of block that is faster to copy by hand and
15256 take blocks of at most of that size guessing that average size will
15257 be roughly half of the block.
15259 If this turns out to be bad, we might simply specify the preferred
15260 choice in ix86_costs. */
15261 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15262 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
15265 enum stringop_alg alg;
15267 bool any_alg_usable_p = true;
15269 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15271 enum stringop_alg candidate = algs->size[i].alg;
15272 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
15274 if (candidate != libcall && candidate
15275 && ALG_USABLE_P (candidate))
15276 max = algs->size[i].max;
15278 /* If there aren't any usable algorithms, then recursing on
15279 smaller sizes isn't going to find anything. Just return the
15280 simple byte-at-a-time copy loop. */
15281 if (!any_alg_usable_p)
15283 /* Pick something reasonable. */
15284 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15285 *dynamic_check = 128;
15286 return loop_1_byte;
15290 alg = decide_alg (count, max / 2, memset, dynamic_check);
15291 gcc_assert (*dynamic_check == -1);
15292 gcc_assert (alg != libcall);
15293 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15294 *dynamic_check = max;
15297 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
15298 #undef ALG_USABLE_P
15301 /* Decide on alignment. We know that the operand is already aligned to ALIGN
15302 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
15304 decide_alignment (int align,
15305 enum stringop_alg alg,
15308 int desired_align = 0;
15312 gcc_unreachable ();
15314 case unrolled_loop:
15315 desired_align = GET_MODE_SIZE (Pmode);
15317 case rep_prefix_8_byte:
15320 case rep_prefix_4_byte:
15321 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15322 copying whole cacheline at once. */
15323 if (TARGET_PENTIUMPRO)
15328 case rep_prefix_1_byte:
15329 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15330 copying whole cacheline at once. */
15331 if (TARGET_PENTIUMPRO)
15345 if (desired_align < align)
15346 desired_align = align;
15347 if (expected_size != -1 && expected_size < 4)
15348 desired_align = align;
15349 return desired_align;
15352 /* Return the smallest power of 2 greater than VAL. */
15354 smallest_pow2_greater_than (int val)
15362 /* Expand string move (memcpy) operation. Use i386 string operations when
15363 profitable. expand_setmem contains similar code. The code depends upon
15364 architecture, block size and alignment, but always has the same
15367 1) Prologue guard: Conditional that jumps up to epilogues for small
15368 blocks that can be handled by epilogue alone. This is faster but
15369 also needed for correctness, since prologue assume the block is larger
15370 than the desired alignment.
15372 Optional dynamic check for size and libcall for large
15373 blocks is emitted here too, with -minline-stringops-dynamically.
15375 2) Prologue: copy first few bytes in order to get destination aligned
15376 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
15377 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
15378 We emit either a jump tree on power of two sized blocks, or a byte loop.
15380 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
15381 with specified algorithm.
15383 4) Epilogue: code copying tail of the block that is too small to be
15384 handled by main body (or up to size guarded by prologue guard). */
15387 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
15388 rtx expected_align_exp, rtx expected_size_exp)
15394 rtx jump_around_label = NULL;
15395 HOST_WIDE_INT align = 1;
15396 unsigned HOST_WIDE_INT count = 0;
15397 HOST_WIDE_INT expected_size = -1;
15398 int size_needed = 0, epilogue_size_needed;
15399 int desired_align = 0;
15400 enum stringop_alg alg;
15403 if (CONST_INT_P (align_exp))
15404 align = INTVAL (align_exp);
15405 /* i386 can do misaligned access on reasonably increased cost. */
15406 if (CONST_INT_P (expected_align_exp)
15407 && INTVAL (expected_align_exp) > align)
15408 align = INTVAL (expected_align_exp);
15409 if (CONST_INT_P (count_exp))
15410 count = expected_size = INTVAL (count_exp);
15411 if (CONST_INT_P (expected_size_exp) && count == 0)
15412 expected_size = INTVAL (expected_size_exp);
15414 /* Make sure we don't need to care about overflow later on. */
15415 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15418 /* Step 0: Decide on preferred algorithm, desired alignment and
15419 size of chunks to be copied by main loop. */
15421 alg = decide_alg (count, expected_size, false, &dynamic_check);
15422 desired_align = decide_alignment (align, alg, expected_size);
15424 if (!TARGET_ALIGN_STRINGOPS)
15425 align = desired_align;
15427 if (alg == libcall)
15429 gcc_assert (alg != no_stringop);
15431 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
15432 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15433 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
15438 gcc_unreachable ();
15440 size_needed = GET_MODE_SIZE (Pmode);
15442 case unrolled_loop:
15443 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
15445 case rep_prefix_8_byte:
15448 case rep_prefix_4_byte:
15451 case rep_prefix_1_byte:
15457 epilogue_size_needed = size_needed;
15459 /* Step 1: Prologue guard. */
15461 /* Alignment code needs count to be in register. */
15462 if (CONST_INT_P (count_exp) && desired_align > align)
15463 count_exp = force_reg (counter_mode (count_exp), count_exp);
15464 gcc_assert (desired_align >= 1 && align >= 1);
15466 /* Ensure that alignment prologue won't copy past end of block. */
15467 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15469 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15470 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15471 Make sure it is power of 2. */
15472 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15474 if (CONST_INT_P (count_exp))
15476 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
15481 label = gen_label_rtx ();
15482 emit_cmp_and_jump_insns (count_exp,
15483 GEN_INT (epilogue_size_needed),
15484 LTU, 0, counter_mode (count_exp), 1, label);
15485 if (expected_size == -1 || expected_size < epilogue_size_needed)
15486 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15488 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15492 /* Emit code to decide on runtime whether library call or inline should be
15494 if (dynamic_check != -1)
15496 if (CONST_INT_P (count_exp))
15498 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
15500 emit_block_move_via_libcall (dst, src, count_exp, false);
15501 count_exp = const0_rtx;
15507 rtx hot_label = gen_label_rtx ();
15508 jump_around_label = gen_label_rtx ();
15509 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15510 LEU, 0, GET_MODE (count_exp), 1, hot_label);
15511 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15512 emit_block_move_via_libcall (dst, src, count_exp, false);
15513 emit_jump (jump_around_label);
15514 emit_label (hot_label);
15518 /* Step 2: Alignment prologue. */
15520 if (desired_align > align)
15522 /* Except for the first move in epilogue, we no longer know
15523 constant offset in aliasing info. It don't seems to worth
15524 the pain to maintain it for the first move, so throw away
15526 src = change_address (src, BLKmode, srcreg);
15527 dst = change_address (dst, BLKmode, destreg);
15528 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
15531 if (label && size_needed == 1)
15533 emit_label (label);
15534 LABEL_NUSES (label) = 1;
15538 /* Step 3: Main loop. */
15544 gcc_unreachable ();
15546 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15547 count_exp, QImode, 1, expected_size);
15550 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15551 count_exp, Pmode, 1, expected_size);
15553 case unrolled_loop:
15554 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
15555 registers for 4 temporaries anyway. */
15556 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15557 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
15560 case rep_prefix_8_byte:
15561 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15564 case rep_prefix_4_byte:
15565 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15568 case rep_prefix_1_byte:
15569 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15573 /* Adjust properly the offset of src and dest memory for aliasing. */
15574 if (CONST_INT_P (count_exp))
15576 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
15577 (count / size_needed) * size_needed);
15578 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15579 (count / size_needed) * size_needed);
15583 src = change_address (src, BLKmode, srcreg);
15584 dst = change_address (dst, BLKmode, destreg);
15587 /* Step 4: Epilogue to copy the remaining bytes. */
15591 /* When the main loop is done, COUNT_EXP might hold original count,
15592 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15593 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15594 bytes. Compensate if needed. */
15596 if (size_needed < epilogue_size_needed)
15599 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15600 GEN_INT (size_needed - 1), count_exp, 1,
15602 if (tmp != count_exp)
15603 emit_move_insn (count_exp, tmp);
15605 emit_label (label);
15606 LABEL_NUSES (label) = 1;
15609 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15610 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
15611 epilogue_size_needed);
15612 if (jump_around_label)
15613 emit_label (jump_around_label);
15617 /* Helper function for memcpy. For QImode value 0xXY produce
15618 0xXYXYXYXY of wide specified by MODE. This is essentially
15619 a * 0x10101010, but we can do slightly better than
15620 synth_mult by unwinding the sequence by hand on CPUs with
15623 promote_duplicated_reg (enum machine_mode mode, rtx val)
15625 enum machine_mode valmode = GET_MODE (val);
15627 int nops = mode == DImode ? 3 : 2;
15629 gcc_assert (mode == SImode || mode == DImode);
15630 if (val == const0_rtx)
15631 return copy_to_mode_reg (mode, const0_rtx);
15632 if (CONST_INT_P (val))
15634 HOST_WIDE_INT v = INTVAL (val) & 255;
15638 if (mode == DImode)
15639 v |= (v << 16) << 16;
15640 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
15643 if (valmode == VOIDmode)
15645 if (valmode != QImode)
15646 val = gen_lowpart (QImode, val);
15647 if (mode == QImode)
15649 if (!TARGET_PARTIAL_REG_STALL)
15651 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
15652 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
15653 <= (ix86_cost->shift_const + ix86_cost->add) * nops
15654 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
15656 rtx reg = convert_modes (mode, QImode, val, true);
15657 tmp = promote_duplicated_reg (mode, const1_rtx);
15658 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
15663 rtx reg = convert_modes (mode, QImode, val, true);
15665 if (!TARGET_PARTIAL_REG_STALL)
15666 if (mode == SImode)
15667 emit_insn (gen_movsi_insv_1 (reg, reg));
15669 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
15672 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
15673 NULL, 1, OPTAB_DIRECT);
15675 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15677 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
15678 NULL, 1, OPTAB_DIRECT);
15679 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15680 if (mode == SImode)
15682 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
15683 NULL, 1, OPTAB_DIRECT);
15684 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15689 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
15690 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
15691 alignment from ALIGN to DESIRED_ALIGN. */
15693 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15698 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15699 promoted_val = promote_duplicated_reg (DImode, val);
15700 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15701 promoted_val = promote_duplicated_reg (SImode, val);
15702 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15703 promoted_val = promote_duplicated_reg (HImode, val);
15705 promoted_val = val;
15707 return promoted_val;
15710 /* Expand string clear operation (bzero). Use i386 string operations when
15711 profitable. See expand_movmem comment for explanation of individual
15712 steps performed. */
15714 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15715 rtx expected_align_exp, rtx expected_size_exp)
15720 rtx jump_around_label = NULL;
15721 HOST_WIDE_INT align = 1;
15722 unsigned HOST_WIDE_INT count = 0;
15723 HOST_WIDE_INT expected_size = -1;
15724 int size_needed = 0, epilogue_size_needed;
15725 int desired_align = 0;
15726 enum stringop_alg alg;
15727 rtx promoted_val = NULL;
15728 bool force_loopy_epilogue = false;
15731 if (CONST_INT_P (align_exp))
15732 align = INTVAL (align_exp);
15733 /* i386 can do misaligned access on reasonably increased cost. */
15734 if (CONST_INT_P (expected_align_exp)
15735 && INTVAL (expected_align_exp) > align)
15736 align = INTVAL (expected_align_exp);
15737 if (CONST_INT_P (count_exp))
15738 count = expected_size = INTVAL (count_exp);
15739 if (CONST_INT_P (expected_size_exp) && count == 0)
15740 expected_size = INTVAL (expected_size_exp);
15742 /* Make sure we don't need to care about overflow later on. */
15743 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15746 /* Step 0: Decide on preferred algorithm, desired alignment and
15747 size of chunks to be copied by main loop. */
15749 alg = decide_alg (count, expected_size, true, &dynamic_check);
15750 desired_align = decide_alignment (align, alg, expected_size);
15752 if (!TARGET_ALIGN_STRINGOPS)
15753 align = desired_align;
15755 if (alg == libcall)
15757 gcc_assert (alg != no_stringop);
15759 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
15760 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15765 gcc_unreachable ();
15767 size_needed = GET_MODE_SIZE (Pmode);
15769 case unrolled_loop:
15770 size_needed = GET_MODE_SIZE (Pmode) * 4;
15772 case rep_prefix_8_byte:
15775 case rep_prefix_4_byte:
15778 case rep_prefix_1_byte:
15783 epilogue_size_needed = size_needed;
15785 /* Step 1: Prologue guard. */
15787 /* Alignment code needs count to be in register. */
15788 if (CONST_INT_P (count_exp) && desired_align > align)
15790 enum machine_mode mode = SImode;
15791 if (TARGET_64BIT && (count & ~0xffffffff))
15793 count_exp = force_reg (mode, count_exp);
15795 /* Do the cheap promotion to allow better CSE across the
15796 main loop and epilogue (ie one load of the big constant in the
15797 front of all code. */
15798 if (CONST_INT_P (val_exp))
15799 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15800 desired_align, align);
15801 /* Ensure that alignment prologue won't copy past end of block. */
15802 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15804 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15805 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15806 Make sure it is power of 2. */
15807 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15809 /* To improve performance of small blocks, we jump around the VAL
15810 promoting mode. This mean that if the promoted VAL is not constant,
15811 we might not use it in the epilogue and have to use byte
15813 if (epilogue_size_needed > 2 && !promoted_val)
15814 force_loopy_epilogue = true;
15815 label = gen_label_rtx ();
15816 emit_cmp_and_jump_insns (count_exp,
15817 GEN_INT (epilogue_size_needed),
15818 LTU, 0, counter_mode (count_exp), 1, label);
15819 if (GET_CODE (count_exp) == CONST_INT)
15821 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
15822 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15824 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15826 if (dynamic_check != -1)
15828 rtx hot_label = gen_label_rtx ();
15829 jump_around_label = gen_label_rtx ();
15830 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15831 LEU, 0, counter_mode (count_exp), 1, hot_label);
15832 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15833 set_storage_via_libcall (dst, count_exp, val_exp, false);
15834 emit_jump (jump_around_label);
15835 emit_label (hot_label);
15838 /* Step 2: Alignment prologue. */
15840 /* Do the expensive promotion once we branched off the small blocks. */
15842 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15843 desired_align, align);
15844 gcc_assert (desired_align >= 1 && align >= 1);
15846 if (desired_align > align)
15848 /* Except for the first move in epilogue, we no longer know
15849 constant offset in aliasing info. It don't seems to worth
15850 the pain to maintain it for the first move, so throw away
15852 dst = change_address (dst, BLKmode, destreg);
15853 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
15856 if (label && size_needed == 1)
15858 emit_label (label);
15859 LABEL_NUSES (label) = 1;
15863 /* Step 3: Main loop. */
15869 gcc_unreachable ();
15871 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15872 count_exp, QImode, 1, expected_size);
15875 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15876 count_exp, Pmode, 1, expected_size);
15878 case unrolled_loop:
15879 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15880 count_exp, Pmode, 4, expected_size);
15882 case rep_prefix_8_byte:
15883 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15886 case rep_prefix_4_byte:
15887 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15890 case rep_prefix_1_byte:
15891 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15895 /* Adjust properly the offset of src and dest memory for aliasing. */
15896 if (CONST_INT_P (count_exp))
15897 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15898 (count / size_needed) * size_needed);
15900 dst = change_address (dst, BLKmode, destreg);
15902 /* Step 4: Epilogue to copy the remaining bytes. */
15906 /* When the main loop is done, COUNT_EXP might hold original count,
15907 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15908 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15909 bytes. Compensate if needed. */
15911 if (size_needed < desired_align - align)
15914 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15915 GEN_INT (size_needed - 1), count_exp, 1,
15917 size_needed = desired_align - align + 1;
15918 if (tmp != count_exp)
15919 emit_move_insn (count_exp, tmp);
15921 emit_label (label);
15922 LABEL_NUSES (label) = 1;
15924 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15926 if (force_loopy_epilogue)
15927 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
15930 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
15933 if (jump_around_label)
15934 emit_label (jump_around_label);
15938 /* Expand the appropriate insns for doing strlen if not just doing
15941 out = result, initialized with the start address
15942 align_rtx = alignment of the address.
15943 scratch = scratch register, initialized with the startaddress when
15944 not aligned, otherwise undefined
15946 This is just the body. It needs the initializations mentioned above and
15947 some address computing at the end. These things are done in i386.md. */
15950 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
15954 rtx align_2_label = NULL_RTX;
15955 rtx align_3_label = NULL_RTX;
15956 rtx align_4_label = gen_label_rtx ();
15957 rtx end_0_label = gen_label_rtx ();
15959 rtx tmpreg = gen_reg_rtx (SImode);
15960 rtx scratch = gen_reg_rtx (SImode);
15964 if (CONST_INT_P (align_rtx))
15965 align = INTVAL (align_rtx);
15967 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
15969 /* Is there a known alignment and is it less than 4? */
15972 rtx scratch1 = gen_reg_rtx (Pmode);
15973 emit_move_insn (scratch1, out);
15974 /* Is there a known alignment and is it not 2? */
15977 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
15978 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
15980 /* Leave just the 3 lower bits. */
15981 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
15982 NULL_RTX, 0, OPTAB_WIDEN);
15984 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15985 Pmode, 1, align_4_label);
15986 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
15987 Pmode, 1, align_2_label);
15988 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
15989 Pmode, 1, align_3_label);
15993 /* Since the alignment is 2, we have to check 2 or 0 bytes;
15994 check if is aligned to 4 - byte. */
15996 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
15997 NULL_RTX, 0, OPTAB_WIDEN);
15999 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16000 Pmode, 1, align_4_label);
16003 mem = change_address (src, QImode, out);
16005 /* Now compare the bytes. */
16007 /* Compare the first n unaligned byte on a byte per byte basis. */
16008 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
16009 QImode, 1, end_0_label);
16011 /* Increment the address. */
16013 emit_insn (gen_adddi3 (out, out, const1_rtx));
16015 emit_insn (gen_addsi3 (out, out, const1_rtx));
16017 /* Not needed with an alignment of 2 */
16020 emit_label (align_2_label);
16022 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16026 emit_insn (gen_adddi3 (out, out, const1_rtx));
16028 emit_insn (gen_addsi3 (out, out, const1_rtx));
16030 emit_label (align_3_label);
16033 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16037 emit_insn (gen_adddi3 (out, out, const1_rtx));
16039 emit_insn (gen_addsi3 (out, out, const1_rtx));
16042 /* Generate loop to check 4 bytes at a time. It is not a good idea to
16043 align this loop. It gives only huge programs, but does not help to
16045 emit_label (align_4_label);
16047 mem = change_address (src, SImode, out);
16048 emit_move_insn (scratch, mem);
16050 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
16052 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
16054 /* This formula yields a nonzero result iff one of the bytes is zero.
16055 This saves three branches inside loop and many cycles. */
16057 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
16058 emit_insn (gen_one_cmplsi2 (scratch, scratch));
16059 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
16060 emit_insn (gen_andsi3 (tmpreg, tmpreg,
16061 gen_int_mode (0x80808080, SImode)));
16062 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
16067 rtx reg = gen_reg_rtx (SImode);
16068 rtx reg2 = gen_reg_rtx (Pmode);
16069 emit_move_insn (reg, tmpreg);
16070 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
16072 /* If zero is not in the first two bytes, move two bytes forward. */
16073 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16074 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16075 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16076 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
16077 gen_rtx_IF_THEN_ELSE (SImode, tmp,
16080 /* Emit lea manually to avoid clobbering of flags. */
16081 emit_insn (gen_rtx_SET (SImode, reg2,
16082 gen_rtx_PLUS (Pmode, out, const2_rtx)));
16084 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16085 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16086 emit_insn (gen_rtx_SET (VOIDmode, out,
16087 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
16094 rtx end_2_label = gen_label_rtx ();
16095 /* Is zero in the first two bytes? */
16097 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16098 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16099 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
16100 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
16101 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
16103 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
16104 JUMP_LABEL (tmp) = end_2_label;
16106 /* Not in the first two. Move two bytes forward. */
16107 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
16109 emit_insn (gen_adddi3 (out, out, const2_rtx));
16111 emit_insn (gen_addsi3 (out, out, const2_rtx));
16113 emit_label (end_2_label);
16117 /* Avoid branch in fixing the byte. */
16118 tmpreg = gen_lowpart (QImode, tmpreg);
16119 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
16120 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16122 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
16124 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
16126 emit_label (end_0_label);
16129 /* Expand strlen. */
16132 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
16134 rtx addr, scratch1, scratch2, scratch3, scratch4;
16136 /* The generic case of strlen expander is long. Avoid it's
16137 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
16139 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16140 && !TARGET_INLINE_ALL_STRINGOPS
16142 && (!CONST_INT_P (align) || INTVAL (align) < 4))
16145 addr = force_reg (Pmode, XEXP (src, 0));
16146 scratch1 = gen_reg_rtx (Pmode);
16148 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16151 /* Well it seems that some optimizer does not combine a call like
16152 foo(strlen(bar), strlen(bar));
16153 when the move and the subtraction is done here. It does calculate
16154 the length just once when these instructions are done inside of
16155 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
16156 often used and I use one fewer register for the lifetime of
16157 output_strlen_unroll() this is better. */
16159 emit_move_insn (out, addr);
16161 ix86_expand_strlensi_unroll_1 (out, src, align);
16163 /* strlensi_unroll_1 returns the address of the zero at the end of
16164 the string, like memchr(), so compute the length by subtracting
16165 the start address. */
16167 emit_insn (gen_subdi3 (out, out, addr));
16169 emit_insn (gen_subsi3 (out, out, addr));
16175 /* Can't use this if the user has appropriated eax, ecx, or edi. */
16176 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
16179 scratch2 = gen_reg_rtx (Pmode);
16180 scratch3 = gen_reg_rtx (Pmode);
16181 scratch4 = force_reg (Pmode, constm1_rtx);
16183 emit_move_insn (scratch3, addr);
16184 eoschar = force_reg (QImode, eoschar);
16186 src = replace_equiv_address_nv (src, scratch3);
16188 /* If .md starts supporting :P, this can be done in .md. */
16189 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
16190 scratch4), UNSPEC_SCAS);
16191 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
16194 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
16195 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
16199 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
16200 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
16206 /* For given symbol (function) construct code to compute address of it's PLT
16207 entry in large x86-64 PIC model. */
16209 construct_plt_address (rtx symbol)
16211 rtx tmp = gen_reg_rtx (Pmode);
16212 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
16214 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16215 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
16217 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
16218 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
16223 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
16224 rtx callarg2 ATTRIBUTE_UNUSED,
16225 rtx pop, int sibcall)
16227 rtx use = NULL, call;
16229 if (pop == const0_rtx)
16231 gcc_assert (!TARGET_64BIT || !pop);
16233 if (TARGET_MACHO && !TARGET_64BIT)
16236 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
16237 fnaddr = machopic_indirect_call_target (fnaddr);
16242 /* Static functions and indirect calls don't need the pic register. */
16243 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
16244 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16245 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
16246 use_reg (&use, pic_offset_table_rtx);
16249 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
16251 rtx al = gen_rtx_REG (QImode, AX_REG);
16252 emit_move_insn (al, callarg2);
16253 use_reg (&use, al);
16256 if (ix86_cmodel == CM_LARGE_PIC
16257 && GET_CODE (fnaddr) == MEM
16258 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16259 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
16260 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
16261 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
16263 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16264 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16266 if (sibcall && TARGET_64BIT
16267 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
16270 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16271 fnaddr = gen_rtx_REG (Pmode, R11_REG);
16272 emit_move_insn (fnaddr, addr);
16273 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16276 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
16278 call = gen_rtx_SET (VOIDmode, retval, call);
16281 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
16282 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
16283 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
16286 call = emit_call_insn (call);
16288 CALL_INSN_FUNCTION_USAGE (call) = use;
16292 /* Clear stack slot assignments remembered from previous functions.
16293 This is called from INIT_EXPANDERS once before RTL is emitted for each
16296 static struct machine_function *
16297 ix86_init_machine_status (void)
16299 struct machine_function *f;
16301 f = GGC_CNEW (struct machine_function);
16302 f->use_fast_prologue_epilogue_nregs = -1;
16303 f->tls_descriptor_call_expanded_p = 0;
16308 /* Return a MEM corresponding to a stack slot with mode MODE.
16309 Allocate a new slot if necessary.
16311 The RTL for a function can have several slots available: N is
16312 which slot to use. */
16315 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
16317 struct stack_local_entry *s;
16319 gcc_assert (n < MAX_386_STACK_LOCALS);
16321 /* Virtual slot is valid only before vregs are instantiated. */
16322 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
16324 for (s = ix86_stack_locals; s; s = s->next)
16325 if (s->mode == mode && s->n == n)
16326 return copy_rtx (s->rtl);
16328 s = (struct stack_local_entry *)
16329 ggc_alloc (sizeof (struct stack_local_entry));
16332 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16334 s->next = ix86_stack_locals;
16335 ix86_stack_locals = s;
16339 /* Construct the SYMBOL_REF for the tls_get_addr function. */
16341 static GTY(()) rtx ix86_tls_symbol;
16343 ix86_tls_get_addr (void)
16346 if (!ix86_tls_symbol)
16348 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
16349 (TARGET_ANY_GNU_TLS
16351 ? "___tls_get_addr"
16352 : "__tls_get_addr");
16355 return ix86_tls_symbol;
16358 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
16360 static GTY(()) rtx ix86_tls_module_base_symbol;
16362 ix86_tls_module_base (void)
16365 if (!ix86_tls_module_base_symbol)
16367 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
16368 "_TLS_MODULE_BASE_");
16369 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
16370 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
16373 return ix86_tls_module_base_symbol;
16376 /* Calculate the length of the memory address in the instruction
16377 encoding. Does not include the one-byte modrm, opcode, or prefix. */
16380 memory_address_length (rtx addr)
16382 struct ix86_address parts;
16383 rtx base, index, disp;
16387 if (GET_CODE (addr) == PRE_DEC
16388 || GET_CODE (addr) == POST_INC
16389 || GET_CODE (addr) == PRE_MODIFY
16390 || GET_CODE (addr) == POST_MODIFY)
16393 ok = ix86_decompose_address (addr, &parts);
16396 if (parts.base && GET_CODE (parts.base) == SUBREG)
16397 parts.base = SUBREG_REG (parts.base);
16398 if (parts.index && GET_CODE (parts.index) == SUBREG)
16399 parts.index = SUBREG_REG (parts.index);
16402 index = parts.index;
16407 - esp as the base always wants an index,
16408 - ebp as the base always wants a displacement. */
16410 /* Register Indirect. */
16411 if (base && !index && !disp)
16413 /* esp (for its index) and ebp (for its displacement) need
16414 the two-byte modrm form. */
16415 if (addr == stack_pointer_rtx
16416 || addr == arg_pointer_rtx
16417 || addr == frame_pointer_rtx
16418 || addr == hard_frame_pointer_rtx)
16422 /* Direct Addressing. */
16423 else if (disp && !base && !index)
16428 /* Find the length of the displacement constant. */
16431 if (base && satisfies_constraint_K (disp))
16436 /* ebp always wants a displacement. */
16437 else if (base == hard_frame_pointer_rtx)
16440 /* An index requires the two-byte modrm form.... */
16442 /* ...like esp, which always wants an index. */
16443 || base == stack_pointer_rtx
16444 || base == arg_pointer_rtx
16445 || base == frame_pointer_rtx)
16452 /* Compute default value for "length_immediate" attribute. When SHORTFORM
16453 is set, expect that insn have 8bit immediate alternative. */
16455 ix86_attr_length_immediate_default (rtx insn, int shortform)
16459 extract_insn_cached (insn);
16460 for (i = recog_data.n_operands - 1; i >= 0; --i)
16461 if (CONSTANT_P (recog_data.operand[i]))
16464 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
16468 switch (get_attr_mode (insn))
16479 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
16484 fatal_insn ("unknown insn mode", insn);
16490 /* Compute default value for "length_address" attribute. */
16492 ix86_attr_length_address_default (rtx insn)
16496 if (get_attr_type (insn) == TYPE_LEA)
16498 rtx set = PATTERN (insn);
16500 if (GET_CODE (set) == PARALLEL)
16501 set = XVECEXP (set, 0, 0);
16503 gcc_assert (GET_CODE (set) == SET);
16505 return memory_address_length (SET_SRC (set));
16508 extract_insn_cached (insn);
16509 for (i = recog_data.n_operands - 1; i >= 0; --i)
16510 if (MEM_P (recog_data.operand[i]))
16512 return memory_address_length (XEXP (recog_data.operand[i], 0));
16518 /* Return the maximum number of instructions a cpu can issue. */
16521 ix86_issue_rate (void)
16525 case PROCESSOR_PENTIUM:
16529 case PROCESSOR_PENTIUMPRO:
16530 case PROCESSOR_PENTIUM4:
16531 case PROCESSOR_ATHLON:
16533 case PROCESSOR_AMDFAM10:
16534 case PROCESSOR_NOCONA:
16535 case PROCESSOR_GENERIC32:
16536 case PROCESSOR_GENERIC64:
16539 case PROCESSOR_CORE2:
16547 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
16548 by DEP_INSN and nothing set by DEP_INSN. */
16551 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16555 /* Simplify the test for uninteresting insns. */
16556 if (insn_type != TYPE_SETCC
16557 && insn_type != TYPE_ICMOV
16558 && insn_type != TYPE_FCMOV
16559 && insn_type != TYPE_IBR)
16562 if ((set = single_set (dep_insn)) != 0)
16564 set = SET_DEST (set);
16567 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
16568 && XVECLEN (PATTERN (dep_insn), 0) == 2
16569 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
16570 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
16572 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16573 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16578 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
16581 /* This test is true if the dependent insn reads the flags but
16582 not any other potentially set register. */
16583 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
16586 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
16592 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
16593 address with operands set by DEP_INSN. */
16596 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16600 if (insn_type == TYPE_LEA
16603 addr = PATTERN (insn);
16605 if (GET_CODE (addr) == PARALLEL)
16606 addr = XVECEXP (addr, 0, 0);
16608 gcc_assert (GET_CODE (addr) == SET);
16610 addr = SET_SRC (addr);
16615 extract_insn_cached (insn);
16616 for (i = recog_data.n_operands - 1; i >= 0; --i)
16617 if (MEM_P (recog_data.operand[i]))
16619 addr = XEXP (recog_data.operand[i], 0);
16626 return modified_in_p (addr, dep_insn);
16630 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16632 enum attr_type insn_type, dep_insn_type;
16633 enum attr_memory memory;
16635 int dep_insn_code_number;
16637 /* Anti and output dependencies have zero cost on all CPUs. */
16638 if (REG_NOTE_KIND (link) != 0)
16641 dep_insn_code_number = recog_memoized (dep_insn);
16643 /* If we can't recognize the insns, we can't really do anything. */
16644 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
16647 insn_type = get_attr_type (insn);
16648 dep_insn_type = get_attr_type (dep_insn);
16652 case PROCESSOR_PENTIUM:
16653 /* Address Generation Interlock adds a cycle of latency. */
16654 if (ix86_agi_dependent (insn, dep_insn, insn_type))
16657 /* ??? Compares pair with jump/setcc. */
16658 if (ix86_flags_dependent (insn, dep_insn, insn_type))
16661 /* Floating point stores require value to be ready one cycle earlier. */
16662 if (insn_type == TYPE_FMOV
16663 && get_attr_memory (insn) == MEMORY_STORE
16664 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16668 case PROCESSOR_PENTIUMPRO:
16669 memory = get_attr_memory (insn);
16671 /* INT->FP conversion is expensive. */
16672 if (get_attr_fp_int_src (dep_insn))
16675 /* There is one cycle extra latency between an FP op and a store. */
16676 if (insn_type == TYPE_FMOV
16677 && (set = single_set (dep_insn)) != NULL_RTX
16678 && (set2 = single_set (insn)) != NULL_RTX
16679 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
16680 && MEM_P (SET_DEST (set2)))
16683 /* Show ability of reorder buffer to hide latency of load by executing
16684 in parallel with previous instruction in case
16685 previous instruction is not needed to compute the address. */
16686 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16687 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16689 /* Claim moves to take one cycle, as core can issue one load
16690 at time and the next load can start cycle later. */
16691 if (dep_insn_type == TYPE_IMOV
16692 || dep_insn_type == TYPE_FMOV)
16700 memory = get_attr_memory (insn);
16702 /* The esp dependency is resolved before the instruction is really
16704 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
16705 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16708 /* INT->FP conversion is expensive. */
16709 if (get_attr_fp_int_src (dep_insn))
16712 /* Show ability of reorder buffer to hide latency of load by executing
16713 in parallel with previous instruction in case
16714 previous instruction is not needed to compute the address. */
16715 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16716 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16718 /* Claim moves to take one cycle, as core can issue one load
16719 at time and the next load can start cycle later. */
16720 if (dep_insn_type == TYPE_IMOV
16721 || dep_insn_type == TYPE_FMOV)
16730 case PROCESSOR_ATHLON:
16732 case PROCESSOR_AMDFAM10:
16733 case PROCESSOR_GENERIC32:
16734 case PROCESSOR_GENERIC64:
16735 memory = get_attr_memory (insn);
16737 /* Show ability of reorder buffer to hide latency of load by executing
16738 in parallel with previous instruction in case
16739 previous instruction is not needed to compute the address. */
16740 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16741 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16743 enum attr_unit unit = get_attr_unit (insn);
16746 /* Because of the difference between the length of integer and
16747 floating unit pipeline preparation stages, the memory operands
16748 for floating point are cheaper.
16750 ??? For Athlon it the difference is most probably 2. */
16751 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16754 loadcost = TARGET_ATHLON ? 2 : 0;
16756 if (cost >= loadcost)
16769 /* How many alternative schedules to try. This should be as wide as the
16770 scheduling freedom in the DFA, but no wider. Making this value too
16771 large results extra work for the scheduler. */
16774 ia32_multipass_dfa_lookahead (void)
16778 case PROCESSOR_PENTIUM:
16781 case PROCESSOR_PENTIUMPRO:
16791 /* Compute the alignment given to a constant that is being placed in memory.
16792 EXP is the constant and ALIGN is the alignment that the object would
16794 The value of this function is used instead of that alignment to align
16798 ix86_constant_alignment (tree exp, int align)
16800 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
16801 || TREE_CODE (exp) == INTEGER_CST)
16803 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
16805 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
16808 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
16809 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
16810 return BITS_PER_WORD;
16815 /* Compute the alignment for a static variable.
16816 TYPE is the data type, and ALIGN is the alignment that
16817 the object would ordinarily have. The value of this function is used
16818 instead of that alignment to align the object. */
16821 ix86_data_alignment (tree type, int align)
16823 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
16825 if (AGGREGATE_TYPE_P (type)
16826 && TYPE_SIZE (type)
16827 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16828 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
16829 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
16830 && align < max_align)
16833 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16834 to 16byte boundary. */
16837 if (AGGREGATE_TYPE_P (type)
16838 && TYPE_SIZE (type)
16839 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16840 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
16841 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16845 if (TREE_CODE (type) == ARRAY_TYPE)
16847 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16849 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16852 else if (TREE_CODE (type) == COMPLEX_TYPE)
16855 if (TYPE_MODE (type) == DCmode && align < 64)
16857 if (TYPE_MODE (type) == XCmode && align < 128)
16860 else if ((TREE_CODE (type) == RECORD_TYPE
16861 || TREE_CODE (type) == UNION_TYPE
16862 || TREE_CODE (type) == QUAL_UNION_TYPE)
16863 && TYPE_FIELDS (type))
16865 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16867 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16870 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16871 || TREE_CODE (type) == INTEGER_TYPE)
16873 if (TYPE_MODE (type) == DFmode && align < 64)
16875 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16882 /* Compute the alignment for a local variable.
16883 TYPE is the data type, and ALIGN is the alignment that
16884 the object would ordinarily have. The value of this macro is used
16885 instead of that alignment to align the object. */
16888 ix86_local_alignment (tree type, int align)
16890 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16891 to 16byte boundary. */
16894 if (AGGREGATE_TYPE_P (type)
16895 && TYPE_SIZE (type)
16896 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16897 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
16898 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16901 if (TREE_CODE (type) == ARRAY_TYPE)
16903 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16905 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16908 else if (TREE_CODE (type) == COMPLEX_TYPE)
16910 if (TYPE_MODE (type) == DCmode && align < 64)
16912 if (TYPE_MODE (type) == XCmode && align < 128)
16915 else if ((TREE_CODE (type) == RECORD_TYPE
16916 || TREE_CODE (type) == UNION_TYPE
16917 || TREE_CODE (type) == QUAL_UNION_TYPE)
16918 && TYPE_FIELDS (type))
16920 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16922 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16925 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16926 || TREE_CODE (type) == INTEGER_TYPE)
16929 if (TYPE_MODE (type) == DFmode && align < 64)
16931 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16937 /* Emit RTL insns to initialize the variable parts of a trampoline.
16938 FNADDR is an RTX for the address of the function's pure code.
16939 CXT is an RTX for the static chain value for the function. */
16941 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
16945 /* Compute offset from the end of the jmp to the target function. */
16946 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
16947 plus_constant (tramp, 10),
16948 NULL_RTX, 1, OPTAB_DIRECT);
16949 emit_move_insn (gen_rtx_MEM (QImode, tramp),
16950 gen_int_mode (0xb9, QImode));
16951 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
16952 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
16953 gen_int_mode (0xe9, QImode));
16954 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
16959 /* Try to load address using shorter movl instead of movabs.
16960 We may want to support movq for kernel mode, but kernel does not use
16961 trampolines at the moment. */
16962 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
16964 fnaddr = copy_to_mode_reg (DImode, fnaddr);
16965 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16966 gen_int_mode (0xbb41, HImode));
16967 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
16968 gen_lowpart (SImode, fnaddr));
16973 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16974 gen_int_mode (0xbb49, HImode));
16975 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16979 /* Load static chain using movabs to r10. */
16980 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16981 gen_int_mode (0xba49, HImode));
16982 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16985 /* Jump to the r11 */
16986 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16987 gen_int_mode (0xff49, HImode));
16988 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
16989 gen_int_mode (0xe3, QImode));
16991 gcc_assert (offset <= TRAMPOLINE_SIZE);
16994 #ifdef ENABLE_EXECUTE_STACK
16995 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
16996 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
17000 /* Codes for all the SSE/MMX builtins. */
17003 IX86_BUILTIN_ADDPS,
17004 IX86_BUILTIN_ADDSS,
17005 IX86_BUILTIN_DIVPS,
17006 IX86_BUILTIN_DIVSS,
17007 IX86_BUILTIN_MULPS,
17008 IX86_BUILTIN_MULSS,
17009 IX86_BUILTIN_SUBPS,
17010 IX86_BUILTIN_SUBSS,
17012 IX86_BUILTIN_CMPEQPS,
17013 IX86_BUILTIN_CMPLTPS,
17014 IX86_BUILTIN_CMPLEPS,
17015 IX86_BUILTIN_CMPGTPS,
17016 IX86_BUILTIN_CMPGEPS,
17017 IX86_BUILTIN_CMPNEQPS,
17018 IX86_BUILTIN_CMPNLTPS,
17019 IX86_BUILTIN_CMPNLEPS,
17020 IX86_BUILTIN_CMPNGTPS,
17021 IX86_BUILTIN_CMPNGEPS,
17022 IX86_BUILTIN_CMPORDPS,
17023 IX86_BUILTIN_CMPUNORDPS,
17024 IX86_BUILTIN_CMPEQSS,
17025 IX86_BUILTIN_CMPLTSS,
17026 IX86_BUILTIN_CMPLESS,
17027 IX86_BUILTIN_CMPNEQSS,
17028 IX86_BUILTIN_CMPNLTSS,
17029 IX86_BUILTIN_CMPNLESS,
17030 IX86_BUILTIN_CMPNGTSS,
17031 IX86_BUILTIN_CMPNGESS,
17032 IX86_BUILTIN_CMPORDSS,
17033 IX86_BUILTIN_CMPUNORDSS,
17035 IX86_BUILTIN_COMIEQSS,
17036 IX86_BUILTIN_COMILTSS,
17037 IX86_BUILTIN_COMILESS,
17038 IX86_BUILTIN_COMIGTSS,
17039 IX86_BUILTIN_COMIGESS,
17040 IX86_BUILTIN_COMINEQSS,
17041 IX86_BUILTIN_UCOMIEQSS,
17042 IX86_BUILTIN_UCOMILTSS,
17043 IX86_BUILTIN_UCOMILESS,
17044 IX86_BUILTIN_UCOMIGTSS,
17045 IX86_BUILTIN_UCOMIGESS,
17046 IX86_BUILTIN_UCOMINEQSS,
17048 IX86_BUILTIN_CVTPI2PS,
17049 IX86_BUILTIN_CVTPS2PI,
17050 IX86_BUILTIN_CVTSI2SS,
17051 IX86_BUILTIN_CVTSI642SS,
17052 IX86_BUILTIN_CVTSS2SI,
17053 IX86_BUILTIN_CVTSS2SI64,
17054 IX86_BUILTIN_CVTTPS2PI,
17055 IX86_BUILTIN_CVTTSS2SI,
17056 IX86_BUILTIN_CVTTSS2SI64,
17058 IX86_BUILTIN_MAXPS,
17059 IX86_BUILTIN_MAXSS,
17060 IX86_BUILTIN_MINPS,
17061 IX86_BUILTIN_MINSS,
17063 IX86_BUILTIN_LOADUPS,
17064 IX86_BUILTIN_STOREUPS,
17065 IX86_BUILTIN_MOVSS,
17067 IX86_BUILTIN_MOVHLPS,
17068 IX86_BUILTIN_MOVLHPS,
17069 IX86_BUILTIN_LOADHPS,
17070 IX86_BUILTIN_LOADLPS,
17071 IX86_BUILTIN_STOREHPS,
17072 IX86_BUILTIN_STORELPS,
17074 IX86_BUILTIN_MASKMOVQ,
17075 IX86_BUILTIN_MOVMSKPS,
17076 IX86_BUILTIN_PMOVMSKB,
17078 IX86_BUILTIN_MOVNTPS,
17079 IX86_BUILTIN_MOVNTQ,
17081 IX86_BUILTIN_LOADDQU,
17082 IX86_BUILTIN_STOREDQU,
17084 IX86_BUILTIN_PACKSSWB,
17085 IX86_BUILTIN_PACKSSDW,
17086 IX86_BUILTIN_PACKUSWB,
17088 IX86_BUILTIN_PADDB,
17089 IX86_BUILTIN_PADDW,
17090 IX86_BUILTIN_PADDD,
17091 IX86_BUILTIN_PADDQ,
17092 IX86_BUILTIN_PADDSB,
17093 IX86_BUILTIN_PADDSW,
17094 IX86_BUILTIN_PADDUSB,
17095 IX86_BUILTIN_PADDUSW,
17096 IX86_BUILTIN_PSUBB,
17097 IX86_BUILTIN_PSUBW,
17098 IX86_BUILTIN_PSUBD,
17099 IX86_BUILTIN_PSUBQ,
17100 IX86_BUILTIN_PSUBSB,
17101 IX86_BUILTIN_PSUBSW,
17102 IX86_BUILTIN_PSUBUSB,
17103 IX86_BUILTIN_PSUBUSW,
17106 IX86_BUILTIN_PANDN,
17110 IX86_BUILTIN_PAVGB,
17111 IX86_BUILTIN_PAVGW,
17113 IX86_BUILTIN_PCMPEQB,
17114 IX86_BUILTIN_PCMPEQW,
17115 IX86_BUILTIN_PCMPEQD,
17116 IX86_BUILTIN_PCMPGTB,
17117 IX86_BUILTIN_PCMPGTW,
17118 IX86_BUILTIN_PCMPGTD,
17120 IX86_BUILTIN_PMADDWD,
17122 IX86_BUILTIN_PMAXSW,
17123 IX86_BUILTIN_PMAXUB,
17124 IX86_BUILTIN_PMINSW,
17125 IX86_BUILTIN_PMINUB,
17127 IX86_BUILTIN_PMULHUW,
17128 IX86_BUILTIN_PMULHW,
17129 IX86_BUILTIN_PMULLW,
17131 IX86_BUILTIN_PSADBW,
17132 IX86_BUILTIN_PSHUFW,
17134 IX86_BUILTIN_PSLLW,
17135 IX86_BUILTIN_PSLLD,
17136 IX86_BUILTIN_PSLLQ,
17137 IX86_BUILTIN_PSRAW,
17138 IX86_BUILTIN_PSRAD,
17139 IX86_BUILTIN_PSRLW,
17140 IX86_BUILTIN_PSRLD,
17141 IX86_BUILTIN_PSRLQ,
17142 IX86_BUILTIN_PSLLWI,
17143 IX86_BUILTIN_PSLLDI,
17144 IX86_BUILTIN_PSLLQI,
17145 IX86_BUILTIN_PSRAWI,
17146 IX86_BUILTIN_PSRADI,
17147 IX86_BUILTIN_PSRLWI,
17148 IX86_BUILTIN_PSRLDI,
17149 IX86_BUILTIN_PSRLQI,
17151 IX86_BUILTIN_PUNPCKHBW,
17152 IX86_BUILTIN_PUNPCKHWD,
17153 IX86_BUILTIN_PUNPCKHDQ,
17154 IX86_BUILTIN_PUNPCKLBW,
17155 IX86_BUILTIN_PUNPCKLWD,
17156 IX86_BUILTIN_PUNPCKLDQ,
17158 IX86_BUILTIN_SHUFPS,
17160 IX86_BUILTIN_RCPPS,
17161 IX86_BUILTIN_RCPSS,
17162 IX86_BUILTIN_RSQRTPS,
17163 IX86_BUILTIN_RSQRTPS_NR,
17164 IX86_BUILTIN_RSQRTSS,
17165 IX86_BUILTIN_RSQRTF,
17166 IX86_BUILTIN_SQRTPS,
17167 IX86_BUILTIN_SQRTPS_NR,
17168 IX86_BUILTIN_SQRTSS,
17170 IX86_BUILTIN_UNPCKHPS,
17171 IX86_BUILTIN_UNPCKLPS,
17173 IX86_BUILTIN_ANDPS,
17174 IX86_BUILTIN_ANDNPS,
17176 IX86_BUILTIN_XORPS,
17179 IX86_BUILTIN_LDMXCSR,
17180 IX86_BUILTIN_STMXCSR,
17181 IX86_BUILTIN_SFENCE,
17183 /* 3DNow! Original */
17184 IX86_BUILTIN_FEMMS,
17185 IX86_BUILTIN_PAVGUSB,
17186 IX86_BUILTIN_PF2ID,
17187 IX86_BUILTIN_PFACC,
17188 IX86_BUILTIN_PFADD,
17189 IX86_BUILTIN_PFCMPEQ,
17190 IX86_BUILTIN_PFCMPGE,
17191 IX86_BUILTIN_PFCMPGT,
17192 IX86_BUILTIN_PFMAX,
17193 IX86_BUILTIN_PFMIN,
17194 IX86_BUILTIN_PFMUL,
17195 IX86_BUILTIN_PFRCP,
17196 IX86_BUILTIN_PFRCPIT1,
17197 IX86_BUILTIN_PFRCPIT2,
17198 IX86_BUILTIN_PFRSQIT1,
17199 IX86_BUILTIN_PFRSQRT,
17200 IX86_BUILTIN_PFSUB,
17201 IX86_BUILTIN_PFSUBR,
17202 IX86_BUILTIN_PI2FD,
17203 IX86_BUILTIN_PMULHRW,
17205 /* 3DNow! Athlon Extensions */
17206 IX86_BUILTIN_PF2IW,
17207 IX86_BUILTIN_PFNACC,
17208 IX86_BUILTIN_PFPNACC,
17209 IX86_BUILTIN_PI2FW,
17210 IX86_BUILTIN_PSWAPDSI,
17211 IX86_BUILTIN_PSWAPDSF,
17214 IX86_BUILTIN_ADDPD,
17215 IX86_BUILTIN_ADDSD,
17216 IX86_BUILTIN_DIVPD,
17217 IX86_BUILTIN_DIVSD,
17218 IX86_BUILTIN_MULPD,
17219 IX86_BUILTIN_MULSD,
17220 IX86_BUILTIN_SUBPD,
17221 IX86_BUILTIN_SUBSD,
17223 IX86_BUILTIN_CMPEQPD,
17224 IX86_BUILTIN_CMPLTPD,
17225 IX86_BUILTIN_CMPLEPD,
17226 IX86_BUILTIN_CMPGTPD,
17227 IX86_BUILTIN_CMPGEPD,
17228 IX86_BUILTIN_CMPNEQPD,
17229 IX86_BUILTIN_CMPNLTPD,
17230 IX86_BUILTIN_CMPNLEPD,
17231 IX86_BUILTIN_CMPNGTPD,
17232 IX86_BUILTIN_CMPNGEPD,
17233 IX86_BUILTIN_CMPORDPD,
17234 IX86_BUILTIN_CMPUNORDPD,
17235 IX86_BUILTIN_CMPEQSD,
17236 IX86_BUILTIN_CMPLTSD,
17237 IX86_BUILTIN_CMPLESD,
17238 IX86_BUILTIN_CMPNEQSD,
17239 IX86_BUILTIN_CMPNLTSD,
17240 IX86_BUILTIN_CMPNLESD,
17241 IX86_BUILTIN_CMPORDSD,
17242 IX86_BUILTIN_CMPUNORDSD,
17244 IX86_BUILTIN_COMIEQSD,
17245 IX86_BUILTIN_COMILTSD,
17246 IX86_BUILTIN_COMILESD,
17247 IX86_BUILTIN_COMIGTSD,
17248 IX86_BUILTIN_COMIGESD,
17249 IX86_BUILTIN_COMINEQSD,
17250 IX86_BUILTIN_UCOMIEQSD,
17251 IX86_BUILTIN_UCOMILTSD,
17252 IX86_BUILTIN_UCOMILESD,
17253 IX86_BUILTIN_UCOMIGTSD,
17254 IX86_BUILTIN_UCOMIGESD,
17255 IX86_BUILTIN_UCOMINEQSD,
17257 IX86_BUILTIN_MAXPD,
17258 IX86_BUILTIN_MAXSD,
17259 IX86_BUILTIN_MINPD,
17260 IX86_BUILTIN_MINSD,
17262 IX86_BUILTIN_ANDPD,
17263 IX86_BUILTIN_ANDNPD,
17265 IX86_BUILTIN_XORPD,
17267 IX86_BUILTIN_SQRTPD,
17268 IX86_BUILTIN_SQRTSD,
17270 IX86_BUILTIN_UNPCKHPD,
17271 IX86_BUILTIN_UNPCKLPD,
17273 IX86_BUILTIN_SHUFPD,
17275 IX86_BUILTIN_LOADUPD,
17276 IX86_BUILTIN_STOREUPD,
17277 IX86_BUILTIN_MOVSD,
17279 IX86_BUILTIN_LOADHPD,
17280 IX86_BUILTIN_LOADLPD,
17282 IX86_BUILTIN_CVTDQ2PD,
17283 IX86_BUILTIN_CVTDQ2PS,
17285 IX86_BUILTIN_CVTPD2DQ,
17286 IX86_BUILTIN_CVTPD2PI,
17287 IX86_BUILTIN_CVTPD2PS,
17288 IX86_BUILTIN_CVTTPD2DQ,
17289 IX86_BUILTIN_CVTTPD2PI,
17291 IX86_BUILTIN_CVTPI2PD,
17292 IX86_BUILTIN_CVTSI2SD,
17293 IX86_BUILTIN_CVTSI642SD,
17295 IX86_BUILTIN_CVTSD2SI,
17296 IX86_BUILTIN_CVTSD2SI64,
17297 IX86_BUILTIN_CVTSD2SS,
17298 IX86_BUILTIN_CVTSS2SD,
17299 IX86_BUILTIN_CVTTSD2SI,
17300 IX86_BUILTIN_CVTTSD2SI64,
17302 IX86_BUILTIN_CVTPS2DQ,
17303 IX86_BUILTIN_CVTPS2PD,
17304 IX86_BUILTIN_CVTTPS2DQ,
17306 IX86_BUILTIN_MOVNTI,
17307 IX86_BUILTIN_MOVNTPD,
17308 IX86_BUILTIN_MOVNTDQ,
17311 IX86_BUILTIN_MASKMOVDQU,
17312 IX86_BUILTIN_MOVMSKPD,
17313 IX86_BUILTIN_PMOVMSKB128,
17315 IX86_BUILTIN_PACKSSWB128,
17316 IX86_BUILTIN_PACKSSDW128,
17317 IX86_BUILTIN_PACKUSWB128,
17319 IX86_BUILTIN_PADDB128,
17320 IX86_BUILTIN_PADDW128,
17321 IX86_BUILTIN_PADDD128,
17322 IX86_BUILTIN_PADDQ128,
17323 IX86_BUILTIN_PADDSB128,
17324 IX86_BUILTIN_PADDSW128,
17325 IX86_BUILTIN_PADDUSB128,
17326 IX86_BUILTIN_PADDUSW128,
17327 IX86_BUILTIN_PSUBB128,
17328 IX86_BUILTIN_PSUBW128,
17329 IX86_BUILTIN_PSUBD128,
17330 IX86_BUILTIN_PSUBQ128,
17331 IX86_BUILTIN_PSUBSB128,
17332 IX86_BUILTIN_PSUBSW128,
17333 IX86_BUILTIN_PSUBUSB128,
17334 IX86_BUILTIN_PSUBUSW128,
17336 IX86_BUILTIN_PAND128,
17337 IX86_BUILTIN_PANDN128,
17338 IX86_BUILTIN_POR128,
17339 IX86_BUILTIN_PXOR128,
17341 IX86_BUILTIN_PAVGB128,
17342 IX86_BUILTIN_PAVGW128,
17344 IX86_BUILTIN_PCMPEQB128,
17345 IX86_BUILTIN_PCMPEQW128,
17346 IX86_BUILTIN_PCMPEQD128,
17347 IX86_BUILTIN_PCMPGTB128,
17348 IX86_BUILTIN_PCMPGTW128,
17349 IX86_BUILTIN_PCMPGTD128,
17351 IX86_BUILTIN_PMADDWD128,
17353 IX86_BUILTIN_PMAXSW128,
17354 IX86_BUILTIN_PMAXUB128,
17355 IX86_BUILTIN_PMINSW128,
17356 IX86_BUILTIN_PMINUB128,
17358 IX86_BUILTIN_PMULUDQ,
17359 IX86_BUILTIN_PMULUDQ128,
17360 IX86_BUILTIN_PMULHUW128,
17361 IX86_BUILTIN_PMULHW128,
17362 IX86_BUILTIN_PMULLW128,
17364 IX86_BUILTIN_PSADBW128,
17365 IX86_BUILTIN_PSHUFHW,
17366 IX86_BUILTIN_PSHUFLW,
17367 IX86_BUILTIN_PSHUFD,
17369 IX86_BUILTIN_PSLLDQI128,
17370 IX86_BUILTIN_PSLLWI128,
17371 IX86_BUILTIN_PSLLDI128,
17372 IX86_BUILTIN_PSLLQI128,
17373 IX86_BUILTIN_PSRAWI128,
17374 IX86_BUILTIN_PSRADI128,
17375 IX86_BUILTIN_PSRLDQI128,
17376 IX86_BUILTIN_PSRLWI128,
17377 IX86_BUILTIN_PSRLDI128,
17378 IX86_BUILTIN_PSRLQI128,
17380 IX86_BUILTIN_PSLLDQ128,
17381 IX86_BUILTIN_PSLLW128,
17382 IX86_BUILTIN_PSLLD128,
17383 IX86_BUILTIN_PSLLQ128,
17384 IX86_BUILTIN_PSRAW128,
17385 IX86_BUILTIN_PSRAD128,
17386 IX86_BUILTIN_PSRLW128,
17387 IX86_BUILTIN_PSRLD128,
17388 IX86_BUILTIN_PSRLQ128,
17390 IX86_BUILTIN_PUNPCKHBW128,
17391 IX86_BUILTIN_PUNPCKHWD128,
17392 IX86_BUILTIN_PUNPCKHDQ128,
17393 IX86_BUILTIN_PUNPCKHQDQ128,
17394 IX86_BUILTIN_PUNPCKLBW128,
17395 IX86_BUILTIN_PUNPCKLWD128,
17396 IX86_BUILTIN_PUNPCKLDQ128,
17397 IX86_BUILTIN_PUNPCKLQDQ128,
17399 IX86_BUILTIN_CLFLUSH,
17400 IX86_BUILTIN_MFENCE,
17401 IX86_BUILTIN_LFENCE,
17403 /* Prescott New Instructions. */
17404 IX86_BUILTIN_ADDSUBPS,
17405 IX86_BUILTIN_HADDPS,
17406 IX86_BUILTIN_HSUBPS,
17407 IX86_BUILTIN_MOVSHDUP,
17408 IX86_BUILTIN_MOVSLDUP,
17409 IX86_BUILTIN_ADDSUBPD,
17410 IX86_BUILTIN_HADDPD,
17411 IX86_BUILTIN_HSUBPD,
17412 IX86_BUILTIN_LDDQU,
17414 IX86_BUILTIN_MONITOR,
17415 IX86_BUILTIN_MWAIT,
17418 IX86_BUILTIN_PHADDW,
17419 IX86_BUILTIN_PHADDD,
17420 IX86_BUILTIN_PHADDSW,
17421 IX86_BUILTIN_PHSUBW,
17422 IX86_BUILTIN_PHSUBD,
17423 IX86_BUILTIN_PHSUBSW,
17424 IX86_BUILTIN_PMADDUBSW,
17425 IX86_BUILTIN_PMULHRSW,
17426 IX86_BUILTIN_PSHUFB,
17427 IX86_BUILTIN_PSIGNB,
17428 IX86_BUILTIN_PSIGNW,
17429 IX86_BUILTIN_PSIGND,
17430 IX86_BUILTIN_PALIGNR,
17431 IX86_BUILTIN_PABSB,
17432 IX86_BUILTIN_PABSW,
17433 IX86_BUILTIN_PABSD,
17435 IX86_BUILTIN_PHADDW128,
17436 IX86_BUILTIN_PHADDD128,
17437 IX86_BUILTIN_PHADDSW128,
17438 IX86_BUILTIN_PHSUBW128,
17439 IX86_BUILTIN_PHSUBD128,
17440 IX86_BUILTIN_PHSUBSW128,
17441 IX86_BUILTIN_PMADDUBSW128,
17442 IX86_BUILTIN_PMULHRSW128,
17443 IX86_BUILTIN_PSHUFB128,
17444 IX86_BUILTIN_PSIGNB128,
17445 IX86_BUILTIN_PSIGNW128,
17446 IX86_BUILTIN_PSIGND128,
17447 IX86_BUILTIN_PALIGNR128,
17448 IX86_BUILTIN_PABSB128,
17449 IX86_BUILTIN_PABSW128,
17450 IX86_BUILTIN_PABSD128,
17452 /* AMDFAM10 - SSE4A New Instructions. */
17453 IX86_BUILTIN_MOVNTSD,
17454 IX86_BUILTIN_MOVNTSS,
17455 IX86_BUILTIN_EXTRQI,
17456 IX86_BUILTIN_EXTRQ,
17457 IX86_BUILTIN_INSERTQI,
17458 IX86_BUILTIN_INSERTQ,
17461 IX86_BUILTIN_BLENDPD,
17462 IX86_BUILTIN_BLENDPS,
17463 IX86_BUILTIN_BLENDVPD,
17464 IX86_BUILTIN_BLENDVPS,
17465 IX86_BUILTIN_PBLENDVB128,
17466 IX86_BUILTIN_PBLENDW128,
17471 IX86_BUILTIN_INSERTPS128,
17473 IX86_BUILTIN_MOVNTDQA,
17474 IX86_BUILTIN_MPSADBW128,
17475 IX86_BUILTIN_PACKUSDW128,
17476 IX86_BUILTIN_PCMPEQQ,
17477 IX86_BUILTIN_PHMINPOSUW128,
17479 IX86_BUILTIN_PMAXSB128,
17480 IX86_BUILTIN_PMAXSD128,
17481 IX86_BUILTIN_PMAXUD128,
17482 IX86_BUILTIN_PMAXUW128,
17484 IX86_BUILTIN_PMINSB128,
17485 IX86_BUILTIN_PMINSD128,
17486 IX86_BUILTIN_PMINUD128,
17487 IX86_BUILTIN_PMINUW128,
17489 IX86_BUILTIN_PMOVSXBW128,
17490 IX86_BUILTIN_PMOVSXBD128,
17491 IX86_BUILTIN_PMOVSXBQ128,
17492 IX86_BUILTIN_PMOVSXWD128,
17493 IX86_BUILTIN_PMOVSXWQ128,
17494 IX86_BUILTIN_PMOVSXDQ128,
17496 IX86_BUILTIN_PMOVZXBW128,
17497 IX86_BUILTIN_PMOVZXBD128,
17498 IX86_BUILTIN_PMOVZXBQ128,
17499 IX86_BUILTIN_PMOVZXWD128,
17500 IX86_BUILTIN_PMOVZXWQ128,
17501 IX86_BUILTIN_PMOVZXDQ128,
17503 IX86_BUILTIN_PMULDQ128,
17504 IX86_BUILTIN_PMULLD128,
17506 IX86_BUILTIN_ROUNDPD,
17507 IX86_BUILTIN_ROUNDPS,
17508 IX86_BUILTIN_ROUNDSD,
17509 IX86_BUILTIN_ROUNDSS,
17511 IX86_BUILTIN_PTESTZ,
17512 IX86_BUILTIN_PTESTC,
17513 IX86_BUILTIN_PTESTNZC,
17515 IX86_BUILTIN_VEC_INIT_V2SI,
17516 IX86_BUILTIN_VEC_INIT_V4HI,
17517 IX86_BUILTIN_VEC_INIT_V8QI,
17518 IX86_BUILTIN_VEC_EXT_V2DF,
17519 IX86_BUILTIN_VEC_EXT_V2DI,
17520 IX86_BUILTIN_VEC_EXT_V4SF,
17521 IX86_BUILTIN_VEC_EXT_V4SI,
17522 IX86_BUILTIN_VEC_EXT_V8HI,
17523 IX86_BUILTIN_VEC_EXT_V2SI,
17524 IX86_BUILTIN_VEC_EXT_V4HI,
17525 IX86_BUILTIN_VEC_EXT_V16QI,
17526 IX86_BUILTIN_VEC_SET_V2DI,
17527 IX86_BUILTIN_VEC_SET_V4SF,
17528 IX86_BUILTIN_VEC_SET_V4SI,
17529 IX86_BUILTIN_VEC_SET_V8HI,
17530 IX86_BUILTIN_VEC_SET_V4HI,
17531 IX86_BUILTIN_VEC_SET_V16QI,
17533 IX86_BUILTIN_VEC_PACK_SFIX,
17536 IX86_BUILTIN_CRC32QI,
17537 IX86_BUILTIN_CRC32HI,
17538 IX86_BUILTIN_CRC32SI,
17539 IX86_BUILTIN_CRC32DI,
17541 IX86_BUILTIN_PCMPESTRI128,
17542 IX86_BUILTIN_PCMPESTRM128,
17543 IX86_BUILTIN_PCMPESTRA128,
17544 IX86_BUILTIN_PCMPESTRC128,
17545 IX86_BUILTIN_PCMPESTRO128,
17546 IX86_BUILTIN_PCMPESTRS128,
17547 IX86_BUILTIN_PCMPESTRZ128,
17548 IX86_BUILTIN_PCMPISTRI128,
17549 IX86_BUILTIN_PCMPISTRM128,
17550 IX86_BUILTIN_PCMPISTRA128,
17551 IX86_BUILTIN_PCMPISTRC128,
17552 IX86_BUILTIN_PCMPISTRO128,
17553 IX86_BUILTIN_PCMPISTRS128,
17554 IX86_BUILTIN_PCMPISTRZ128,
17556 IX86_BUILTIN_PCMPGTQ,
17558 /* TFmode support builtins. */
17560 IX86_BUILTIN_FABSQ,
17561 IX86_BUILTIN_COPYSIGNQ,
17563 /* SSE5 instructions */
17564 IX86_BUILTIN_FMADDSS,
17565 IX86_BUILTIN_FMADDSD,
17566 IX86_BUILTIN_FMADDPS,
17567 IX86_BUILTIN_FMADDPD,
17568 IX86_BUILTIN_FMSUBSS,
17569 IX86_BUILTIN_FMSUBSD,
17570 IX86_BUILTIN_FMSUBPS,
17571 IX86_BUILTIN_FMSUBPD,
17572 IX86_BUILTIN_FNMADDSS,
17573 IX86_BUILTIN_FNMADDSD,
17574 IX86_BUILTIN_FNMADDPS,
17575 IX86_BUILTIN_FNMADDPD,
17576 IX86_BUILTIN_FNMSUBSS,
17577 IX86_BUILTIN_FNMSUBSD,
17578 IX86_BUILTIN_FNMSUBPS,
17579 IX86_BUILTIN_FNMSUBPD,
17580 IX86_BUILTIN_PCMOV_V2DI,
17581 IX86_BUILTIN_PCMOV_V4SI,
17582 IX86_BUILTIN_PCMOV_V8HI,
17583 IX86_BUILTIN_PCMOV_V16QI,
17584 IX86_BUILTIN_PCMOV_V4SF,
17585 IX86_BUILTIN_PCMOV_V2DF,
17586 IX86_BUILTIN_PPERM,
17587 IX86_BUILTIN_PERMPS,
17588 IX86_BUILTIN_PERMPD,
17589 IX86_BUILTIN_PMACSSWW,
17590 IX86_BUILTIN_PMACSWW,
17591 IX86_BUILTIN_PMACSSWD,
17592 IX86_BUILTIN_PMACSWD,
17593 IX86_BUILTIN_PMACSSDD,
17594 IX86_BUILTIN_PMACSDD,
17595 IX86_BUILTIN_PMACSSDQL,
17596 IX86_BUILTIN_PMACSSDQH,
17597 IX86_BUILTIN_PMACSDQL,
17598 IX86_BUILTIN_PMACSDQH,
17599 IX86_BUILTIN_PMADCSSWD,
17600 IX86_BUILTIN_PMADCSWD,
17601 IX86_BUILTIN_PHADDBW,
17602 IX86_BUILTIN_PHADDBD,
17603 IX86_BUILTIN_PHADDBQ,
17604 IX86_BUILTIN_PHADDWD,
17605 IX86_BUILTIN_PHADDWQ,
17606 IX86_BUILTIN_PHADDDQ,
17607 IX86_BUILTIN_PHADDUBW,
17608 IX86_BUILTIN_PHADDUBD,
17609 IX86_BUILTIN_PHADDUBQ,
17610 IX86_BUILTIN_PHADDUWD,
17611 IX86_BUILTIN_PHADDUWQ,
17612 IX86_BUILTIN_PHADDUDQ,
17613 IX86_BUILTIN_PHSUBBW,
17614 IX86_BUILTIN_PHSUBWD,
17615 IX86_BUILTIN_PHSUBDQ,
17616 IX86_BUILTIN_PROTB,
17617 IX86_BUILTIN_PROTW,
17618 IX86_BUILTIN_PROTD,
17619 IX86_BUILTIN_PROTQ,
17620 IX86_BUILTIN_PROTB_IMM,
17621 IX86_BUILTIN_PROTW_IMM,
17622 IX86_BUILTIN_PROTD_IMM,
17623 IX86_BUILTIN_PROTQ_IMM,
17624 IX86_BUILTIN_PSHLB,
17625 IX86_BUILTIN_PSHLW,
17626 IX86_BUILTIN_PSHLD,
17627 IX86_BUILTIN_PSHLQ,
17628 IX86_BUILTIN_PSHAB,
17629 IX86_BUILTIN_PSHAW,
17630 IX86_BUILTIN_PSHAD,
17631 IX86_BUILTIN_PSHAQ,
17632 IX86_BUILTIN_FRCZSS,
17633 IX86_BUILTIN_FRCZSD,
17634 IX86_BUILTIN_FRCZPS,
17635 IX86_BUILTIN_FRCZPD,
17636 IX86_BUILTIN_CVTPH2PS,
17637 IX86_BUILTIN_CVTPS2PH,
17639 IX86_BUILTIN_COMEQSS,
17640 IX86_BUILTIN_COMNESS,
17641 IX86_BUILTIN_COMLTSS,
17642 IX86_BUILTIN_COMLESS,
17643 IX86_BUILTIN_COMGTSS,
17644 IX86_BUILTIN_COMGESS,
17645 IX86_BUILTIN_COMUEQSS,
17646 IX86_BUILTIN_COMUNESS,
17647 IX86_BUILTIN_COMULTSS,
17648 IX86_BUILTIN_COMULESS,
17649 IX86_BUILTIN_COMUGTSS,
17650 IX86_BUILTIN_COMUGESS,
17651 IX86_BUILTIN_COMORDSS,
17652 IX86_BUILTIN_COMUNORDSS,
17653 IX86_BUILTIN_COMFALSESS,
17654 IX86_BUILTIN_COMTRUESS,
17656 IX86_BUILTIN_COMEQSD,
17657 IX86_BUILTIN_COMNESD,
17658 IX86_BUILTIN_COMLTSD,
17659 IX86_BUILTIN_COMLESD,
17660 IX86_BUILTIN_COMGTSD,
17661 IX86_BUILTIN_COMGESD,
17662 IX86_BUILTIN_COMUEQSD,
17663 IX86_BUILTIN_COMUNESD,
17664 IX86_BUILTIN_COMULTSD,
17665 IX86_BUILTIN_COMULESD,
17666 IX86_BUILTIN_COMUGTSD,
17667 IX86_BUILTIN_COMUGESD,
17668 IX86_BUILTIN_COMORDSD,
17669 IX86_BUILTIN_COMUNORDSD,
17670 IX86_BUILTIN_COMFALSESD,
17671 IX86_BUILTIN_COMTRUESD,
17673 IX86_BUILTIN_COMEQPS,
17674 IX86_BUILTIN_COMNEPS,
17675 IX86_BUILTIN_COMLTPS,
17676 IX86_BUILTIN_COMLEPS,
17677 IX86_BUILTIN_COMGTPS,
17678 IX86_BUILTIN_COMGEPS,
17679 IX86_BUILTIN_COMUEQPS,
17680 IX86_BUILTIN_COMUNEPS,
17681 IX86_BUILTIN_COMULTPS,
17682 IX86_BUILTIN_COMULEPS,
17683 IX86_BUILTIN_COMUGTPS,
17684 IX86_BUILTIN_COMUGEPS,
17685 IX86_BUILTIN_COMORDPS,
17686 IX86_BUILTIN_COMUNORDPS,
17687 IX86_BUILTIN_COMFALSEPS,
17688 IX86_BUILTIN_COMTRUEPS,
17690 IX86_BUILTIN_COMEQPD,
17691 IX86_BUILTIN_COMNEPD,
17692 IX86_BUILTIN_COMLTPD,
17693 IX86_BUILTIN_COMLEPD,
17694 IX86_BUILTIN_COMGTPD,
17695 IX86_BUILTIN_COMGEPD,
17696 IX86_BUILTIN_COMUEQPD,
17697 IX86_BUILTIN_COMUNEPD,
17698 IX86_BUILTIN_COMULTPD,
17699 IX86_BUILTIN_COMULEPD,
17700 IX86_BUILTIN_COMUGTPD,
17701 IX86_BUILTIN_COMUGEPD,
17702 IX86_BUILTIN_COMORDPD,
17703 IX86_BUILTIN_COMUNORDPD,
17704 IX86_BUILTIN_COMFALSEPD,
17705 IX86_BUILTIN_COMTRUEPD,
17707 IX86_BUILTIN_PCOMEQUB,
17708 IX86_BUILTIN_PCOMNEUB,
17709 IX86_BUILTIN_PCOMLTUB,
17710 IX86_BUILTIN_PCOMLEUB,
17711 IX86_BUILTIN_PCOMGTUB,
17712 IX86_BUILTIN_PCOMGEUB,
17713 IX86_BUILTIN_PCOMFALSEUB,
17714 IX86_BUILTIN_PCOMTRUEUB,
17715 IX86_BUILTIN_PCOMEQUW,
17716 IX86_BUILTIN_PCOMNEUW,
17717 IX86_BUILTIN_PCOMLTUW,
17718 IX86_BUILTIN_PCOMLEUW,
17719 IX86_BUILTIN_PCOMGTUW,
17720 IX86_BUILTIN_PCOMGEUW,
17721 IX86_BUILTIN_PCOMFALSEUW,
17722 IX86_BUILTIN_PCOMTRUEUW,
17723 IX86_BUILTIN_PCOMEQUD,
17724 IX86_BUILTIN_PCOMNEUD,
17725 IX86_BUILTIN_PCOMLTUD,
17726 IX86_BUILTIN_PCOMLEUD,
17727 IX86_BUILTIN_PCOMGTUD,
17728 IX86_BUILTIN_PCOMGEUD,
17729 IX86_BUILTIN_PCOMFALSEUD,
17730 IX86_BUILTIN_PCOMTRUEUD,
17731 IX86_BUILTIN_PCOMEQUQ,
17732 IX86_BUILTIN_PCOMNEUQ,
17733 IX86_BUILTIN_PCOMLTUQ,
17734 IX86_BUILTIN_PCOMLEUQ,
17735 IX86_BUILTIN_PCOMGTUQ,
17736 IX86_BUILTIN_PCOMGEUQ,
17737 IX86_BUILTIN_PCOMFALSEUQ,
17738 IX86_BUILTIN_PCOMTRUEUQ,
17740 IX86_BUILTIN_PCOMEQB,
17741 IX86_BUILTIN_PCOMNEB,
17742 IX86_BUILTIN_PCOMLTB,
17743 IX86_BUILTIN_PCOMLEB,
17744 IX86_BUILTIN_PCOMGTB,
17745 IX86_BUILTIN_PCOMGEB,
17746 IX86_BUILTIN_PCOMFALSEB,
17747 IX86_BUILTIN_PCOMTRUEB,
17748 IX86_BUILTIN_PCOMEQW,
17749 IX86_BUILTIN_PCOMNEW,
17750 IX86_BUILTIN_PCOMLTW,
17751 IX86_BUILTIN_PCOMLEW,
17752 IX86_BUILTIN_PCOMGTW,
17753 IX86_BUILTIN_PCOMGEW,
17754 IX86_BUILTIN_PCOMFALSEW,
17755 IX86_BUILTIN_PCOMTRUEW,
17756 IX86_BUILTIN_PCOMEQD,
17757 IX86_BUILTIN_PCOMNED,
17758 IX86_BUILTIN_PCOMLTD,
17759 IX86_BUILTIN_PCOMLED,
17760 IX86_BUILTIN_PCOMGTD,
17761 IX86_BUILTIN_PCOMGED,
17762 IX86_BUILTIN_PCOMFALSED,
17763 IX86_BUILTIN_PCOMTRUED,
17764 IX86_BUILTIN_PCOMEQQ,
17765 IX86_BUILTIN_PCOMNEQ,
17766 IX86_BUILTIN_PCOMLTQ,
17767 IX86_BUILTIN_PCOMLEQ,
17768 IX86_BUILTIN_PCOMGTQ,
17769 IX86_BUILTIN_PCOMGEQ,
17770 IX86_BUILTIN_PCOMFALSEQ,
17771 IX86_BUILTIN_PCOMTRUEQ,
17776 /* Table for the ix86 builtin decls. */
17777 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
17779 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
17780 * if the target_flags include one of MASK. Stores the function decl
17781 * in the ix86_builtins array.
17782 * Returns the function decl or NULL_TREE, if the builtin was not added. */
17785 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
17787 tree decl = NULL_TREE;
17789 if (mask & ix86_isa_flags
17790 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
17792 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
17794 ix86_builtins[(int) code] = decl;
17800 /* Like def_builtin, but also marks the function decl "const". */
17803 def_builtin_const (int mask, const char *name, tree type,
17804 enum ix86_builtins code)
17806 tree decl = def_builtin (mask, name, type, code);
17808 TREE_READONLY (decl) = 1;
17812 /* Bits for builtin_description.flag. */
17814 /* Set when we don't support the comparison natively, and should
17815 swap_comparison in order to support it. */
17816 #define BUILTIN_DESC_SWAP_OPERANDS 1
17818 struct builtin_description
17820 const unsigned int mask;
17821 const enum insn_code icode;
17822 const char *const name;
17823 const enum ix86_builtins code;
17824 const enum rtx_code comparison;
17828 static const struct builtin_description bdesc_comi[] =
17830 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
17831 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
17832 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
17833 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
17834 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
17835 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
17836 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
17837 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
17838 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
17839 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
17840 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
17841 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
17842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
17843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
17844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
17845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
17846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
17847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
17848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
17849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
17850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
17851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
17852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
17853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
17856 static const struct builtin_description bdesc_ptest[] =
17859 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
17860 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
17861 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
17864 static const struct builtin_description bdesc_pcmpestr[] =
17867 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
17868 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
17869 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
17870 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
17871 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
17872 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
17873 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
17876 static const struct builtin_description bdesc_pcmpistr[] =
17879 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
17880 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
17881 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
17882 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
17883 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
17884 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
17885 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
17888 static const struct builtin_description bdesc_crc32[] =
17891 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32qi, 0, IX86_BUILTIN_CRC32QI, UNKNOWN, 0 },
17892 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, 0, IX86_BUILTIN_CRC32HI, UNKNOWN, 0 },
17893 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, 0, IX86_BUILTIN_CRC32SI, UNKNOWN, 0 },
17894 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32di, 0, IX86_BUILTIN_CRC32DI, UNKNOWN, 0 },
17897 /* SSE builtins with 3 arguments and the last argument must be an immediate or xmm0. */
17898 static const struct builtin_description bdesc_sse_3arg[] =
17901 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, 0 },
17902 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, 0 },
17903 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, 0 },
17904 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, 0 },
17905 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, 0 },
17906 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, 0 },
17907 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, 0 },
17908 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, 0 },
17909 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, 0 },
17910 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, 0 },
17911 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, 0, IX86_BUILTIN_ROUNDSD, UNKNOWN, 0 },
17912 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, 0, IX86_BUILTIN_ROUNDSS, UNKNOWN, 0 },
17915 static const struct builtin_description bdesc_2arg[] =
17918 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, 0 },
17919 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, 0 },
17920 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, 0 },
17921 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
17922 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, 0 },
17923 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, 0 },
17924 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, 0 },
17925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, 0 },
17927 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
17928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
17929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
17930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, BUILTIN_DESC_SWAP_OPERANDS },
17931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, BUILTIN_DESC_SWAP_OPERANDS },
17932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
17933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
17934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
17935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
17936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
17939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
17940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
17941 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
17942 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
17943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
17944 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
17945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
17946 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17947 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
17950 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, 0 },
17951 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, 0 },
17952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, 0 },
17953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, 0 },
17955 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, 0 },
17956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, 0 },
17957 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, 0 },
17958 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, 0 },
17960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, 0 },
17961 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, 0 },
17962 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, 0 },
17963 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, 0 },
17964 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, 0 },
17967 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, 0 },
17968 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, 0 },
17969 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, 0 },
17970 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, 0 },
17971 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, 0 },
17972 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, 0 },
17973 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, 0 },
17974 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, 0 },
17976 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, 0 },
17977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, 0 },
17978 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, 0 },
17979 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, 0 },
17980 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, 0 },
17981 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, 0 },
17982 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, 0 },
17983 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, 0 },
17985 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, 0 },
17986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, 0 },
17987 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, 0 },
17989 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, 0 },
17990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, 0 },
17991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, 0 },
17992 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, 0 },
17994 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, 0 },
17995 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, 0 },
17997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, 0 },
17998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, 0 },
17999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, 0 },
18000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, 0 },
18001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, 0 },
18002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, 0 },
18004 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, 0 },
18005 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, 0 },
18006 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, 0 },
18007 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, 0 },
18009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, 0 },
18010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, 0 },
18011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, 0 },
18012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, 0 },
18013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, 0 },
18014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, 0 },
18017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, UNKNOWN, 0 },
18018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, UNKNOWN, 0 },
18019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, UNKNOWN, 0 },
18021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, UNKNOWN, 0 },
18022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, UNKNOWN, 0 },
18023 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, UNKNOWN, 0 },
18025 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, UNKNOWN, 0 },
18026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, UNKNOWN, 0 },
18029 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, 0 },
18030 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, 0 },
18031 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, 0 },
18032 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, 0 },
18033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, 0 },
18034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, 0 },
18035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, 0 },
18036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, 0 },
18038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
18039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
18040 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
18041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, BUILTIN_DESC_SWAP_OPERANDS },
18042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, BUILTIN_DESC_SWAP_OPERANDS },
18043 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
18044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
18045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
18046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
18047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
18048 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
18049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
18050 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
18051 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
18052 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
18053 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
18054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
18055 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
18056 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
18057 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
18059 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, 0 },
18060 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, 0 },
18061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, 0 },
18062 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, 0 },
18064 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, 0 },
18065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, 0 },
18066 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, 0 },
18067 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, 0 },
18069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, 0 },
18070 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, 0 },
18071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, 0 },
18073 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, 0 },
18076 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, 0 },
18077 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, 0 },
18078 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, 0 },
18079 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, 0 },
18080 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, 0 },
18081 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, 0 },
18082 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, 0 },
18083 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, 0 },
18085 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, 0 },
18086 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, 0 },
18087 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, 0 },
18088 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, 0 },
18089 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, 0 },
18090 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, 0 },
18091 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, 0 },
18092 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, 0 },
18094 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, 0 },
18095 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN, 0 },
18097 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, 0 },
18098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, 0 },
18099 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, 0 },
18100 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, 0 },
18102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, 0 },
18103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, 0 },
18105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, 0 },
18106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, 0 },
18107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, 0 },
18108 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, 0 },
18109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, 0 },
18110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, 0 },
18112 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, 0 },
18113 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, 0 },
18114 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, 0 },
18115 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, 0 },
18117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, 0 },
18118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, 0 },
18119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, 0 },
18120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, 0 },
18121 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, 0 },
18122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, 0 },
18123 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, 0 },
18124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, 0 },
18126 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, 0 },
18127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, 0 },
18128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, 0 },
18130 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, 0 },
18131 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, UNKNOWN, 0 },
18133 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 },
18134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, UNKNOWN, 0 },
18136 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, UNKNOWN, 0 },
18138 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, UNKNOWN, 0 },
18139 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, UNKNOWN, 0 },
18140 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, UNKNOWN, 0 },
18141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, UNKNOWN, 0 },
18144 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, 0 },
18145 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, 0 },
18146 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, 0 },
18147 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, 0 },
18148 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, 0 },
18149 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, 0 },
18152 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, 0 },
18153 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, 0 },
18154 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, 0 },
18155 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, 0 },
18156 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, 0 },
18157 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, 0 },
18158 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, 0 },
18159 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, 0 },
18160 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, 0 },
18161 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, 0 },
18162 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, 0 },
18163 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, 0 },
18164 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, 0 },
18165 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, 0 },
18166 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, 0 },
18167 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, 0 },
18168 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, 0 },
18169 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, 0 },
18170 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, 0 },
18171 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, 0 },
18172 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, 0 },
18173 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, 0 },
18174 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, 0 },
18175 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, 0 },
18178 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, 0 },
18179 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, 0 },
18180 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, 0 },
18181 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, 0 },
18182 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, 0 },
18183 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, 0 },
18184 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, 0 },
18185 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, 0 },
18186 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, 0 },
18187 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, 0 },
18188 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, 0, IX86_BUILTIN_PMULDQ128, UNKNOWN, 0 },
18189 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, 0 },
18192 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, 0 },
18195 static const struct builtin_description bdesc_1arg[] =
18198 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, UNKNOWN, 0 },
18199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, UNKNOWN, 0 },
18201 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, UNKNOWN, 0 },
18202 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS_NR, UNKNOWN, 0 },
18203 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, UNKNOWN, 0 },
18204 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, 0 },
18205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, UNKNOWN, 0 },
18207 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, UNKNOWN, 0 },
18208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, UNKNOWN, 0 },
18209 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, UNKNOWN, 0 },
18210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, UNKNOWN, 0 },
18211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, UNKNOWN, 0 },
18212 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, 0 },
18215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, UNKNOWN, 0 },
18216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, UNKNOWN, 0 },
18218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, UNKNOWN, 0 },
18220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, UNKNOWN, 0 },
18221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, UNKNOWN, 0 },
18223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, UNKNOWN, 0 },
18224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, UNKNOWN, 0 },
18225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, UNKNOWN, 0 },
18226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, 0 },
18227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, UNKNOWN, 0 },
18229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, UNKNOWN, 0 },
18231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, UNKNOWN, 0 },
18232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, UNKNOWN, 0 },
18233 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, UNKNOWN, 0 },
18234 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, 0 },
18236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, UNKNOWN, 0 },
18237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, UNKNOWN, 0 },
18238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, 0 },
18241 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, 0 },
18242 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, 0 },
18245 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, 0 },
18246 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, 0 },
18247 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, 0 },
18248 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, 0 },
18249 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, 0 },
18250 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, 0 },
18253 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVSXBW128, UNKNOWN, 0 },
18254 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVSXBD128, UNKNOWN, 0 },
18255 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, 0 },
18256 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVSXWD128, UNKNOWN, 0 },
18257 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, 0 },
18258 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, 0, IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, 0 },
18259 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVZXBW128, UNKNOWN, 0 },
18260 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVZXBD128, UNKNOWN, 0 },
18261 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, 0 },
18262 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVZXWD128, UNKNOWN, 0 },
18263 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, 0 },
18264 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, 0, IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, 0 },
18265 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, 0 },
18267 /* Fake 1 arg builtins with a constant smaller than 8 bits as the 2nd arg. */
18268 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, 0, IX86_BUILTIN_ROUNDPD, UNKNOWN, 0 },
18269 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, 0, IX86_BUILTIN_ROUNDPS, UNKNOWN, 0 },
18273 enum multi_arg_type {
18283 MULTI_ARG_3_PERMPS,
18284 MULTI_ARG_3_PERMPD,
18291 MULTI_ARG_2_DI_IMM,
18292 MULTI_ARG_2_SI_IMM,
18293 MULTI_ARG_2_HI_IMM,
18294 MULTI_ARG_2_QI_IMM,
18295 MULTI_ARG_2_SF_CMP,
18296 MULTI_ARG_2_DF_CMP,
18297 MULTI_ARG_2_DI_CMP,
18298 MULTI_ARG_2_SI_CMP,
18299 MULTI_ARG_2_HI_CMP,
18300 MULTI_ARG_2_QI_CMP,
18323 static const struct builtin_description bdesc_multi_arg[] =
18325 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
18326 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
18327 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
18328 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
18329 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
18330 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
18331 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
18332 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
18333 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
18334 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
18335 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
18336 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
18337 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
18338 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
18339 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
18340 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
18341 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18342 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18343 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
18344 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
18345 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
18346 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
18347 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
18348 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
18349 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
18350 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
18351 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
18352 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
18353 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18354 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
18355 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
18356 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
18357 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18358 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18359 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18360 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18361 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18362 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
18363 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
18364 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
18365 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
18366 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
18367 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
18368 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
18369 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
18370 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
18371 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
18372 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
18373 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
18374 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
18375 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
18376 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
18377 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
18378 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
18379 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
18380 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
18381 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
18382 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
18383 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
18384 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
18385 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
18386 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
18387 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
18388 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
18389 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
18390 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
18391 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
18392 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
18393 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
18394 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
18395 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
18396 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
18397 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
18398 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
18399 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
18401 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
18402 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18403 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18404 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
18405 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
18406 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
18407 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
18408 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18409 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18410 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18411 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18412 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18413 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18414 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18415 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18416 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18418 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
18419 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18420 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18421 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
18422 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
18423 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
18424 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
18425 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18426 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18427 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18428 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18429 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18430 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18431 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18432 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18433 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18435 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
18436 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18437 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18438 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
18439 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
18440 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
18441 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
18442 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18443 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18444 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18445 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18446 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18447 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18448 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18449 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18450 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18452 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
18453 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18454 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18455 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
18456 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
18457 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
18458 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
18459 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18460 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18461 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18462 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18463 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18464 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18465 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18466 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18467 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18469 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
18470 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18471 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18472 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
18473 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
18474 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
18475 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
18477 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
18478 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18479 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18480 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
18481 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
18482 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
18483 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
18485 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
18486 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18487 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18488 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
18489 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
18490 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
18491 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
18493 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18494 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18495 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18496 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
18497 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
18498 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
18499 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
18501 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
18502 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18503 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18504 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
18505 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
18506 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
18507 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
18509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
18510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18512 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
18513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
18514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
18515 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
18517 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
18518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18520 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
18521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
18522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
18523 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
18525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
18529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
18530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
18531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
18533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
18534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
18535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
18536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
18537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
18538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
18539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
18540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
18542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18561 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
18562 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
18565 ix86_init_mmx_sse_builtins (void)
18567 const struct builtin_description * d;
18570 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
18571 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
18572 tree V1DI_type_node
18573 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
18574 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
18575 tree V2DI_type_node
18576 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
18577 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
18578 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
18579 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
18580 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
18581 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
18582 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
18584 tree pchar_type_node = build_pointer_type (char_type_node);
18585 tree pcchar_type_node = build_pointer_type (
18586 build_type_variant (char_type_node, 1, 0));
18587 tree pfloat_type_node = build_pointer_type (float_type_node);
18588 tree pcfloat_type_node = build_pointer_type (
18589 build_type_variant (float_type_node, 1, 0));
18590 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
18591 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
18592 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
18595 tree int_ftype_v4sf_v4sf
18596 = build_function_type_list (integer_type_node,
18597 V4SF_type_node, V4SF_type_node, NULL_TREE);
18598 tree v4si_ftype_v4sf_v4sf
18599 = build_function_type_list (V4SI_type_node,
18600 V4SF_type_node, V4SF_type_node, NULL_TREE);
18601 /* MMX/SSE/integer conversions. */
18602 tree int_ftype_v4sf
18603 = build_function_type_list (integer_type_node,
18604 V4SF_type_node, NULL_TREE);
18605 tree int64_ftype_v4sf
18606 = build_function_type_list (long_long_integer_type_node,
18607 V4SF_type_node, NULL_TREE);
18608 tree int_ftype_v8qi
18609 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
18610 tree v4sf_ftype_v4sf_int
18611 = build_function_type_list (V4SF_type_node,
18612 V4SF_type_node, integer_type_node, NULL_TREE);
18613 tree v4sf_ftype_v4sf_int64
18614 = build_function_type_list (V4SF_type_node,
18615 V4SF_type_node, long_long_integer_type_node,
18617 tree v4sf_ftype_v4sf_v2si
18618 = build_function_type_list (V4SF_type_node,
18619 V4SF_type_node, V2SI_type_node, NULL_TREE);
18621 /* Miscellaneous. */
18622 tree v8qi_ftype_v4hi_v4hi
18623 = build_function_type_list (V8QI_type_node,
18624 V4HI_type_node, V4HI_type_node, NULL_TREE);
18625 tree v4hi_ftype_v2si_v2si
18626 = build_function_type_list (V4HI_type_node,
18627 V2SI_type_node, V2SI_type_node, NULL_TREE);
18628 tree v4sf_ftype_v4sf_v4sf_int
18629 = build_function_type_list (V4SF_type_node,
18630 V4SF_type_node, V4SF_type_node,
18631 integer_type_node, NULL_TREE);
18632 tree v2si_ftype_v4hi_v4hi
18633 = build_function_type_list (V2SI_type_node,
18634 V4HI_type_node, V4HI_type_node, NULL_TREE);
18635 tree v4hi_ftype_v4hi_int
18636 = build_function_type_list (V4HI_type_node,
18637 V4HI_type_node, integer_type_node, NULL_TREE);
18638 tree v2si_ftype_v2si_int
18639 = build_function_type_list (V2SI_type_node,
18640 V2SI_type_node, integer_type_node, NULL_TREE);
18641 tree v1di_ftype_v1di_int
18642 = build_function_type_list (V1DI_type_node,
18643 V1DI_type_node, integer_type_node, NULL_TREE);
18645 tree void_ftype_void
18646 = build_function_type (void_type_node, void_list_node);
18647 tree void_ftype_unsigned
18648 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
18649 tree void_ftype_unsigned_unsigned
18650 = build_function_type_list (void_type_node, unsigned_type_node,
18651 unsigned_type_node, NULL_TREE);
18652 tree void_ftype_pcvoid_unsigned_unsigned
18653 = build_function_type_list (void_type_node, const_ptr_type_node,
18654 unsigned_type_node, unsigned_type_node,
18656 tree unsigned_ftype_void
18657 = build_function_type (unsigned_type_node, void_list_node);
18658 tree v2si_ftype_v4sf
18659 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
18660 /* Loads/stores. */
18661 tree void_ftype_v8qi_v8qi_pchar
18662 = build_function_type_list (void_type_node,
18663 V8QI_type_node, V8QI_type_node,
18664 pchar_type_node, NULL_TREE);
18665 tree v4sf_ftype_pcfloat
18666 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
18667 /* @@@ the type is bogus */
18668 tree v4sf_ftype_v4sf_pv2si
18669 = build_function_type_list (V4SF_type_node,
18670 V4SF_type_node, pv2si_type_node, NULL_TREE);
18671 tree void_ftype_pv2si_v4sf
18672 = build_function_type_list (void_type_node,
18673 pv2si_type_node, V4SF_type_node, NULL_TREE);
18674 tree void_ftype_pfloat_v4sf
18675 = build_function_type_list (void_type_node,
18676 pfloat_type_node, V4SF_type_node, NULL_TREE);
18677 tree void_ftype_pdi_di
18678 = build_function_type_list (void_type_node,
18679 pdi_type_node, long_long_unsigned_type_node,
18681 tree void_ftype_pv2di_v2di
18682 = build_function_type_list (void_type_node,
18683 pv2di_type_node, V2DI_type_node, NULL_TREE);
18684 /* Normal vector unops. */
18685 tree v4sf_ftype_v4sf
18686 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
18687 tree v16qi_ftype_v16qi
18688 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
18689 tree v8hi_ftype_v8hi
18690 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
18691 tree v4si_ftype_v4si
18692 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
18693 tree v8qi_ftype_v8qi
18694 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
18695 tree v4hi_ftype_v4hi
18696 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
18698 /* Normal vector binops. */
18699 tree v4sf_ftype_v4sf_v4sf
18700 = build_function_type_list (V4SF_type_node,
18701 V4SF_type_node, V4SF_type_node, NULL_TREE);
18702 tree v8qi_ftype_v8qi_v8qi
18703 = build_function_type_list (V8QI_type_node,
18704 V8QI_type_node, V8QI_type_node, NULL_TREE);
18705 tree v4hi_ftype_v4hi_v4hi
18706 = build_function_type_list (V4HI_type_node,
18707 V4HI_type_node, V4HI_type_node, NULL_TREE);
18708 tree v2si_ftype_v2si_v2si
18709 = build_function_type_list (V2SI_type_node,
18710 V2SI_type_node, V2SI_type_node, NULL_TREE);
18711 tree v1di_ftype_v1di_v1di
18712 = build_function_type_list (V1DI_type_node,
18713 V1DI_type_node, V1DI_type_node, NULL_TREE);
18715 tree di_ftype_di_di_int
18716 = build_function_type_list (long_long_unsigned_type_node,
18717 long_long_unsigned_type_node,
18718 long_long_unsigned_type_node,
18719 integer_type_node, NULL_TREE);
18721 tree v2si_ftype_v2sf
18722 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
18723 tree v2sf_ftype_v2si
18724 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
18725 tree v2si_ftype_v2si
18726 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
18727 tree v2sf_ftype_v2sf
18728 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
18729 tree v2sf_ftype_v2sf_v2sf
18730 = build_function_type_list (V2SF_type_node,
18731 V2SF_type_node, V2SF_type_node, NULL_TREE);
18732 tree v2si_ftype_v2sf_v2sf
18733 = build_function_type_list (V2SI_type_node,
18734 V2SF_type_node, V2SF_type_node, NULL_TREE);
18735 tree pint_type_node = build_pointer_type (integer_type_node);
18736 tree pdouble_type_node = build_pointer_type (double_type_node);
18737 tree pcdouble_type_node = build_pointer_type (
18738 build_type_variant (double_type_node, 1, 0));
18739 tree int_ftype_v2df_v2df
18740 = build_function_type_list (integer_type_node,
18741 V2DF_type_node, V2DF_type_node, NULL_TREE);
18743 tree void_ftype_pcvoid
18744 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
18745 tree v4sf_ftype_v4si
18746 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
18747 tree v4si_ftype_v4sf
18748 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
18749 tree v2df_ftype_v4si
18750 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
18751 tree v4si_ftype_v2df
18752 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
18753 tree v4si_ftype_v2df_v2df
18754 = build_function_type_list (V4SI_type_node,
18755 V2DF_type_node, V2DF_type_node, NULL_TREE);
18756 tree v2si_ftype_v2df
18757 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
18758 tree v4sf_ftype_v2df
18759 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
18760 tree v2df_ftype_v2si
18761 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
18762 tree v2df_ftype_v4sf
18763 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
18764 tree int_ftype_v2df
18765 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
18766 tree int64_ftype_v2df
18767 = build_function_type_list (long_long_integer_type_node,
18768 V2DF_type_node, NULL_TREE);
18769 tree v2df_ftype_v2df_int
18770 = build_function_type_list (V2DF_type_node,
18771 V2DF_type_node, integer_type_node, NULL_TREE);
18772 tree v2df_ftype_v2df_int64
18773 = build_function_type_list (V2DF_type_node,
18774 V2DF_type_node, long_long_integer_type_node,
18776 tree v4sf_ftype_v4sf_v2df
18777 = build_function_type_list (V4SF_type_node,
18778 V4SF_type_node, V2DF_type_node, NULL_TREE);
18779 tree v2df_ftype_v2df_v4sf
18780 = build_function_type_list (V2DF_type_node,
18781 V2DF_type_node, V4SF_type_node, NULL_TREE);
18782 tree v2df_ftype_v2df_v2df_int
18783 = build_function_type_list (V2DF_type_node,
18784 V2DF_type_node, V2DF_type_node,
18787 tree v2df_ftype_v2df_pcdouble
18788 = build_function_type_list (V2DF_type_node,
18789 V2DF_type_node, pcdouble_type_node, NULL_TREE);
18790 tree void_ftype_pdouble_v2df
18791 = build_function_type_list (void_type_node,
18792 pdouble_type_node, V2DF_type_node, NULL_TREE);
18793 tree void_ftype_pint_int
18794 = build_function_type_list (void_type_node,
18795 pint_type_node, integer_type_node, NULL_TREE);
18796 tree void_ftype_v16qi_v16qi_pchar
18797 = build_function_type_list (void_type_node,
18798 V16QI_type_node, V16QI_type_node,
18799 pchar_type_node, NULL_TREE);
18800 tree v2df_ftype_pcdouble
18801 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
18802 tree v2df_ftype_v2df_v2df
18803 = build_function_type_list (V2DF_type_node,
18804 V2DF_type_node, V2DF_type_node, NULL_TREE);
18805 tree v16qi_ftype_v16qi_v16qi
18806 = build_function_type_list (V16QI_type_node,
18807 V16QI_type_node, V16QI_type_node, NULL_TREE);
18808 tree v8hi_ftype_v8hi_v8hi
18809 = build_function_type_list (V8HI_type_node,
18810 V8HI_type_node, V8HI_type_node, NULL_TREE);
18811 tree v4si_ftype_v4si_v4si
18812 = build_function_type_list (V4SI_type_node,
18813 V4SI_type_node, V4SI_type_node, NULL_TREE);
18814 tree v2di_ftype_v2di_v2di
18815 = build_function_type_list (V2DI_type_node,
18816 V2DI_type_node, V2DI_type_node, NULL_TREE);
18817 tree v2di_ftype_v2df_v2df
18818 = build_function_type_list (V2DI_type_node,
18819 V2DF_type_node, V2DF_type_node, NULL_TREE);
18820 tree v2df_ftype_v2df
18821 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
18822 tree v2di_ftype_v2di_int
18823 = build_function_type_list (V2DI_type_node,
18824 V2DI_type_node, integer_type_node, NULL_TREE);
18825 tree v2di_ftype_v2di_v2di_int
18826 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18827 V2DI_type_node, integer_type_node, NULL_TREE);
18828 tree v4si_ftype_v4si_int
18829 = build_function_type_list (V4SI_type_node,
18830 V4SI_type_node, integer_type_node, NULL_TREE);
18831 tree v8hi_ftype_v8hi_int
18832 = build_function_type_list (V8HI_type_node,
18833 V8HI_type_node, integer_type_node, NULL_TREE);
18834 tree v4si_ftype_v8hi_v8hi
18835 = build_function_type_list (V4SI_type_node,
18836 V8HI_type_node, V8HI_type_node, NULL_TREE);
18837 tree v1di_ftype_v8qi_v8qi
18838 = build_function_type_list (V1DI_type_node,
18839 V8QI_type_node, V8QI_type_node, NULL_TREE);
18840 tree v1di_ftype_v2si_v2si
18841 = build_function_type_list (V1DI_type_node,
18842 V2SI_type_node, V2SI_type_node, NULL_TREE);
18843 tree v2di_ftype_v16qi_v16qi
18844 = build_function_type_list (V2DI_type_node,
18845 V16QI_type_node, V16QI_type_node, NULL_TREE);
18846 tree v2di_ftype_v4si_v4si
18847 = build_function_type_list (V2DI_type_node,
18848 V4SI_type_node, V4SI_type_node, NULL_TREE);
18849 tree int_ftype_v16qi
18850 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
18851 tree v16qi_ftype_pcchar
18852 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
18853 tree void_ftype_pchar_v16qi
18854 = build_function_type_list (void_type_node,
18855 pchar_type_node, V16QI_type_node, NULL_TREE);
18857 tree v2di_ftype_v2di_unsigned_unsigned
18858 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18859 unsigned_type_node, unsigned_type_node,
18861 tree v2di_ftype_v2di_v2di_unsigned_unsigned
18862 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
18863 unsigned_type_node, unsigned_type_node,
18865 tree v2di_ftype_v2di_v16qi
18866 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
18868 tree v2df_ftype_v2df_v2df_v2df
18869 = build_function_type_list (V2DF_type_node,
18870 V2DF_type_node, V2DF_type_node,
18871 V2DF_type_node, NULL_TREE);
18872 tree v4sf_ftype_v4sf_v4sf_v4sf
18873 = build_function_type_list (V4SF_type_node,
18874 V4SF_type_node, V4SF_type_node,
18875 V4SF_type_node, NULL_TREE);
18876 tree v8hi_ftype_v16qi
18877 = build_function_type_list (V8HI_type_node, V16QI_type_node,
18879 tree v4si_ftype_v16qi
18880 = build_function_type_list (V4SI_type_node, V16QI_type_node,
18882 tree v2di_ftype_v16qi
18883 = build_function_type_list (V2DI_type_node, V16QI_type_node,
18885 tree v4si_ftype_v8hi
18886 = build_function_type_list (V4SI_type_node, V8HI_type_node,
18888 tree v2di_ftype_v8hi
18889 = build_function_type_list (V2DI_type_node, V8HI_type_node,
18891 tree v2di_ftype_v4si
18892 = build_function_type_list (V2DI_type_node, V4SI_type_node,
18894 tree v2di_ftype_pv2di
18895 = build_function_type_list (V2DI_type_node, pv2di_type_node,
18897 tree v16qi_ftype_v16qi_v16qi_int
18898 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18899 V16QI_type_node, integer_type_node,
18901 tree v16qi_ftype_v16qi_v16qi_v16qi
18902 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18903 V16QI_type_node, V16QI_type_node,
18905 tree v8hi_ftype_v8hi_v8hi_int
18906 = build_function_type_list (V8HI_type_node, V8HI_type_node,
18907 V8HI_type_node, integer_type_node,
18909 tree v4si_ftype_v4si_v4si_int
18910 = build_function_type_list (V4SI_type_node, V4SI_type_node,
18911 V4SI_type_node, integer_type_node,
18913 tree int_ftype_v2di_v2di
18914 = build_function_type_list (integer_type_node,
18915 V2DI_type_node, V2DI_type_node,
18917 tree int_ftype_v16qi_int_v16qi_int_int
18918 = build_function_type_list (integer_type_node,
18925 tree v16qi_ftype_v16qi_int_v16qi_int_int
18926 = build_function_type_list (V16QI_type_node,
18933 tree int_ftype_v16qi_v16qi_int
18934 = build_function_type_list (integer_type_node,
18940 /* SSE5 instructions */
18941 tree v2di_ftype_v2di_v2di_v2di
18942 = build_function_type_list (V2DI_type_node,
18948 tree v4si_ftype_v4si_v4si_v4si
18949 = build_function_type_list (V4SI_type_node,
18955 tree v4si_ftype_v4si_v4si_v2di
18956 = build_function_type_list (V4SI_type_node,
18962 tree v8hi_ftype_v8hi_v8hi_v8hi
18963 = build_function_type_list (V8HI_type_node,
18969 tree v8hi_ftype_v8hi_v8hi_v4si
18970 = build_function_type_list (V8HI_type_node,
18976 tree v2df_ftype_v2df_v2df_v16qi
18977 = build_function_type_list (V2DF_type_node,
18983 tree v4sf_ftype_v4sf_v4sf_v16qi
18984 = build_function_type_list (V4SF_type_node,
18990 tree v2di_ftype_v2di_si
18991 = build_function_type_list (V2DI_type_node,
18996 tree v4si_ftype_v4si_si
18997 = build_function_type_list (V4SI_type_node,
19002 tree v8hi_ftype_v8hi_si
19003 = build_function_type_list (V8HI_type_node,
19008 tree v16qi_ftype_v16qi_si
19009 = build_function_type_list (V16QI_type_node,
19013 tree v4sf_ftype_v4hi
19014 = build_function_type_list (V4SF_type_node,
19018 tree v4hi_ftype_v4sf
19019 = build_function_type_list (V4HI_type_node,
19023 tree v2di_ftype_v2di
19024 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
19028 /* The __float80 type. */
19029 if (TYPE_MODE (long_double_type_node) == XFmode)
19030 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
19034 /* The __float80 type. */
19035 tree float80_type_node = make_node (REAL_TYPE);
19037 TYPE_PRECISION (float80_type_node) = 80;
19038 layout_type (float80_type_node);
19039 (*lang_hooks.types.register_builtin_type) (float80_type_node,
19045 tree float128_type_node = make_node (REAL_TYPE);
19047 TYPE_PRECISION (float128_type_node) = 128;
19048 layout_type (float128_type_node);
19049 (*lang_hooks.types.register_builtin_type) (float128_type_node,
19052 /* TFmode support builtins. */
19053 ftype = build_function_type (float128_type_node,
19055 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
19057 ftype = build_function_type_list (float128_type_node,
19058 float128_type_node,
19060 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
19062 ftype = build_function_type_list (float128_type_node,
19063 float128_type_node,
19064 float128_type_node,
19066 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
19069 /* Add all SSE builtins that are more or less simple operations on
19071 for (i = 0, d = bdesc_sse_3arg;
19072 i < ARRAY_SIZE (bdesc_sse_3arg);
19075 /* Use one of the operands; the target can have a different mode for
19076 mask-generating compares. */
19077 enum machine_mode mode;
19082 mode = insn_data[d->icode].operand[1].mode;
19087 type = v16qi_ftype_v16qi_v16qi_int;
19090 type = v8hi_ftype_v8hi_v8hi_int;
19093 type = v4si_ftype_v4si_v4si_int;
19096 type = v2di_ftype_v2di_v2di_int;
19099 type = v2df_ftype_v2df_v2df_int;
19102 type = v4sf_ftype_v4sf_v4sf_int;
19105 gcc_unreachable ();
19108 /* Override for variable blends. */
19111 case CODE_FOR_sse4_1_blendvpd:
19112 type = v2df_ftype_v2df_v2df_v2df;
19114 case CODE_FOR_sse4_1_blendvps:
19115 type = v4sf_ftype_v4sf_v4sf_v4sf;
19117 case CODE_FOR_sse4_1_pblendvb:
19118 type = v16qi_ftype_v16qi_v16qi_v16qi;
19124 def_builtin_const (d->mask, d->name, type, d->code);
19127 /* Add all builtins that are more or less simple operations on two
19129 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
19131 /* Use one of the operands; the target can have a different mode for
19132 mask-generating compares. */
19133 enum machine_mode mode;
19138 mode = insn_data[d->icode].operand[1].mode;
19143 type = v16qi_ftype_v16qi_v16qi;
19146 type = v8hi_ftype_v8hi_v8hi;
19149 type = v4si_ftype_v4si_v4si;
19152 type = v2di_ftype_v2di_v2di;
19155 type = v2df_ftype_v2df_v2df;
19158 type = v4sf_ftype_v4sf_v4sf;
19161 type = v8qi_ftype_v8qi_v8qi;
19164 type = v4hi_ftype_v4hi_v4hi;
19167 type = v2si_ftype_v2si_v2si;
19170 type = v1di_ftype_v1di_v1di;
19174 gcc_unreachable ();
19177 /* Override for comparisons. */
19178 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
19179 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
19180 type = v4si_ftype_v4sf_v4sf;
19182 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
19183 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
19184 type = v2di_ftype_v2df_v2df;
19186 if (d->icode == CODE_FOR_vec_pack_sfix_v2df)
19187 type = v4si_ftype_v2df_v2df;
19189 def_builtin_const (d->mask, d->name, type, d->code);
19192 /* Add all builtins that are more or less simple operations on 1 operand. */
19193 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
19195 enum machine_mode mode;
19200 mode = insn_data[d->icode].operand[1].mode;
19205 type = v16qi_ftype_v16qi;
19208 type = v8hi_ftype_v8hi;
19211 type = v4si_ftype_v4si;
19214 type = v2df_ftype_v2df;
19217 type = v4sf_ftype_v4sf;
19220 type = v8qi_ftype_v8qi;
19223 type = v4hi_ftype_v4hi;
19226 type = v2si_ftype_v2si;
19233 def_builtin_const (d->mask, d->name, type, d->code);
19236 /* pcmpestr[im] insns. */
19237 for (i = 0, d = bdesc_pcmpestr;
19238 i < ARRAY_SIZE (bdesc_pcmpestr);
19241 if (d->code == IX86_BUILTIN_PCMPESTRM128)
19242 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
19244 ftype = int_ftype_v16qi_int_v16qi_int_int;
19245 def_builtin_const (d->mask, d->name, ftype, d->code);
19248 /* pcmpistr[im] insns. */
19249 for (i = 0, d = bdesc_pcmpistr;
19250 i < ARRAY_SIZE (bdesc_pcmpistr);
19253 if (d->code == IX86_BUILTIN_PCMPISTRM128)
19254 ftype = v16qi_ftype_v16qi_v16qi_int;
19256 ftype = int_ftype_v16qi_v16qi_int;
19257 def_builtin_const (d->mask, d->name, ftype, d->code);
19260 /* Add the remaining MMX insns with somewhat more complicated types. */
19261 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
19263 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSLLWI);
19264 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSLLDI);
19265 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSLLQI);
19266 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSLLW);
19267 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSLLD);
19268 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSLLQ);
19270 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRLWI);
19271 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRLDI);
19272 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSRLQI);
19273 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRLW);
19274 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRLD);
19275 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSRLQ);
19277 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrawi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRAWI);
19278 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psradi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRADI);
19279 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRAW);
19280 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRAD);
19282 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
19283 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
19285 /* comi/ucomi insns. */
19286 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19287 if (d->mask == OPTION_MASK_ISA_SSE2)
19288 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
19290 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
19293 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
19294 def_builtin_const (d->mask, d->name, int_ftype_v2di_v2di, d->code);
19296 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
19297 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
19298 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
19300 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
19301 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
19302 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
19303 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
19304 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
19305 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
19306 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
19307 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
19308 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
19309 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
19310 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
19312 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
19314 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
19315 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
19317 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
19318 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
19319 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
19320 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
19322 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
19323 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
19324 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
19325 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
19327 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
19329 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", v1di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
19331 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
19332 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
19333 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
19334 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS_NR);
19335 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
19336 ftype = build_function_type_list (float_type_node,
19339 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtf", ftype, IX86_BUILTIN_RSQRTF);
19340 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
19341 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps_nr", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS_NR);
19342 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
19344 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
19346 /* Original 3DNow! */
19347 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
19348 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
19349 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
19350 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
19351 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
19352 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
19353 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
19354 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
19355 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
19356 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
19357 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
19358 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
19359 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
19360 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
19361 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
19362 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
19363 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
19364 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
19365 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
19366 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
19368 /* 3DNow! extension as used in the Athlon CPU. */
19369 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
19370 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
19371 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
19372 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
19373 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
19374 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
19377 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
19379 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
19380 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
19382 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
19383 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
19385 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
19386 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
19387 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
19388 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
19389 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
19391 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
19392 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
19393 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
19394 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
19396 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
19397 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
19399 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
19401 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
19402 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
19404 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
19405 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
19406 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
19407 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
19408 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
19410 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
19412 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
19413 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
19414 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
19415 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
19417 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
19418 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
19419 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
19421 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
19422 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
19423 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
19424 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
19426 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
19427 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
19428 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
19430 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
19431 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
19433 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", v1di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
19434 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
19436 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
19437 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
19438 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
19439 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
19440 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
19441 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
19442 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
19444 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
19445 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
19446 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
19447 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
19448 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
19449 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
19450 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
19452 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
19453 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
19454 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
19455 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
19457 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
19459 /* Prescott New Instructions. */
19460 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
19461 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
19462 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
19465 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
19466 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int, IX86_BUILTIN_PALIGNR);
19469 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_movntdqa", v2di_ftype_pv2di, IX86_BUILTIN_MOVNTDQA);
19470 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVSXBW128);
19471 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVSXBD128);
19472 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVSXBQ128);
19473 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVSXWD128);
19474 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVSXWQ128);
19475 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVSXDQ128);
19476 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVZXBW128);
19477 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVZXBD128);
19478 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVZXBQ128);
19479 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVZXWD128);
19480 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVZXWQ128);
19481 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVZXDQ128);
19482 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmuldq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULDQ128);
19484 /* SSE4.1 and SSE5 */
19485 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundpd", v2df_ftype_v2df_int, IX86_BUILTIN_ROUNDPD);
19486 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundps", v4sf_ftype_v4sf_int, IX86_BUILTIN_ROUNDPS);
19487 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundsd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_ROUNDSD);
19488 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundss", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_ROUNDSS);
19491 ftype = build_function_type_list (unsigned_type_node,
19492 unsigned_type_node,
19493 unsigned_char_type_node,
19495 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32qi", ftype, IX86_BUILTIN_CRC32QI);
19496 ftype = build_function_type_list (unsigned_type_node,
19497 unsigned_type_node,
19498 short_unsigned_type_node,
19500 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32hi", ftype, IX86_BUILTIN_CRC32HI);
19501 ftype = build_function_type_list (unsigned_type_node,
19502 unsigned_type_node,
19503 unsigned_type_node,
19505 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32si", ftype, IX86_BUILTIN_CRC32SI);
19506 ftype = build_function_type_list (long_long_unsigned_type_node,
19507 long_long_unsigned_type_node,
19508 long_long_unsigned_type_node,
19510 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32di", ftype, IX86_BUILTIN_CRC32DI);
19512 /* AMDFAM10 SSE4A New built-ins */
19513 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntsd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTSD);
19514 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntss", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTSS);
19515 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrqi", v2di_ftype_v2di_unsigned_unsigned, IX86_BUILTIN_EXTRQI);
19516 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrq", v2di_ftype_v2di_v16qi, IX86_BUILTIN_EXTRQ);
19517 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertqi", v2di_ftype_v2di_v2di_unsigned_unsigned, IX86_BUILTIN_INSERTQI);
19518 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertq", v2di_ftype_v2di_v2di, IX86_BUILTIN_INSERTQ);
19520 /* Access to the vec_init patterns. */
19521 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
19522 integer_type_node, NULL_TREE);
19523 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
19525 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
19526 short_integer_type_node,
19527 short_integer_type_node,
19528 short_integer_type_node, NULL_TREE);
19529 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
19531 ftype = build_function_type_list (V8QI_type_node, char_type_node,
19532 char_type_node, char_type_node,
19533 char_type_node, char_type_node,
19534 char_type_node, char_type_node,
19535 char_type_node, NULL_TREE);
19536 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
19538 /* Access to the vec_extract patterns. */
19539 ftype = build_function_type_list (double_type_node, V2DF_type_node,
19540 integer_type_node, NULL_TREE);
19541 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
19543 ftype = build_function_type_list (long_long_integer_type_node,
19544 V2DI_type_node, integer_type_node,
19546 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
19548 ftype = build_function_type_list (float_type_node, V4SF_type_node,
19549 integer_type_node, NULL_TREE);
19550 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
19552 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
19553 integer_type_node, NULL_TREE);
19554 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
19556 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
19557 integer_type_node, NULL_TREE);
19558 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
19560 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
19561 integer_type_node, NULL_TREE);
19562 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
19564 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
19565 integer_type_node, NULL_TREE);
19566 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
19568 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
19569 integer_type_node, NULL_TREE);
19570 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
19572 /* Access to the vec_set patterns. */
19573 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
19575 integer_type_node, NULL_TREE);
19576 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
19578 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
19580 integer_type_node, NULL_TREE);
19581 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
19583 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
19585 integer_type_node, NULL_TREE);
19586 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
19588 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
19590 integer_type_node, NULL_TREE);
19591 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
19593 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
19595 integer_type_node, NULL_TREE);
19596 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
19598 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
19600 integer_type_node, NULL_TREE);
19601 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
19603 /* Add SSE5 multi-arg argument instructions */
19604 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
19606 tree mtype = NULL_TREE;
19611 switch ((enum multi_arg_type)d->flag)
19613 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
19614 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
19615 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
19616 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
19617 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
19618 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
19619 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
19620 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
19621 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
19622 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
19623 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
19624 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
19625 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
19626 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
19627 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
19628 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
19629 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
19630 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
19631 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
19632 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
19633 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
19634 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
19635 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
19636 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
19637 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
19638 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
19639 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
19640 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
19641 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
19642 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
19643 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
19644 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
19645 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
19646 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
19647 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
19648 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
19649 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
19650 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
19651 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
19652 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
19653 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
19654 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
19655 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
19656 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
19657 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
19658 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
19659 case MULTI_ARG_UNKNOWN:
19661 gcc_unreachable ();
19665 def_builtin_const (d->mask, d->name, mtype, d->code);
19670 ix86_init_builtins (void)
19673 ix86_init_mmx_sse_builtins ();
19676 /* Errors in the source file can cause expand_expr to return const0_rtx
19677 where we expect a vector. To avoid crashing, use one of the vector
19678 clear instructions. */
19680 safe_vector_operand (rtx x, enum machine_mode mode)
19682 if (x == const0_rtx)
19683 x = CONST0_RTX (mode);
19687 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
19688 4 operands. The third argument must be a constant smaller than 8
19692 ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
19696 tree arg0 = CALL_EXPR_ARG (exp, 0);
19697 tree arg1 = CALL_EXPR_ARG (exp, 1);
19698 tree arg2 = CALL_EXPR_ARG (exp, 2);
19699 rtx op0 = expand_normal (arg0);
19700 rtx op1 = expand_normal (arg1);
19701 rtx op2 = expand_normal (arg2);
19702 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19703 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
19704 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
19705 enum machine_mode mode3 = insn_data[icode].operand[3].mode;
19707 if (VECTOR_MODE_P (mode1))
19708 op0 = safe_vector_operand (op0, mode1);
19709 if (VECTOR_MODE_P (mode2))
19710 op1 = safe_vector_operand (op1, mode2);
19711 if (VECTOR_MODE_P (mode3))
19712 op2 = safe_vector_operand (op2, mode3);
19716 || GET_MODE (target) != tmode
19717 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19718 target = gen_reg_rtx (tmode);
19720 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19721 op0 = copy_to_mode_reg (mode1, op0);
19722 if ((optimize && !register_operand (op1, mode2))
19723 || !(*insn_data[icode].operand[2].predicate) (op1, mode2))
19724 op1 = copy_to_mode_reg (mode2, op1);
19726 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19729 case CODE_FOR_sse4_1_blendvpd:
19730 case CODE_FOR_sse4_1_blendvps:
19731 case CODE_FOR_sse4_1_pblendvb:
19732 op2 = copy_to_mode_reg (mode3, op2);
19735 case CODE_FOR_sse4_1_roundsd:
19736 case CODE_FOR_sse4_1_roundss:
19737 error ("the third argument must be a 4-bit immediate");
19741 error ("the third argument must be an 8-bit immediate");
19745 pat = GEN_FCN (icode) (target, op0, op1, op2);
19752 /* Subroutine of ix86_expand_builtin to take care of crc32 insns. */
19755 ix86_expand_crc32 (enum insn_code icode, tree exp, rtx target)
19758 tree arg0 = CALL_EXPR_ARG (exp, 0);
19759 tree arg1 = CALL_EXPR_ARG (exp, 1);
19760 rtx op0 = expand_normal (arg0);
19761 rtx op1 = expand_normal (arg1);
19762 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19763 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19764 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19768 || GET_MODE (target) != tmode
19769 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19770 target = gen_reg_rtx (tmode);
19772 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19773 op0 = copy_to_mode_reg (mode0, op0);
19774 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19776 op1 = copy_to_reg (op1);
19777 op1 = simplify_gen_subreg (mode1, op1, GET_MODE (op1), 0);
19780 pat = GEN_FCN (icode) (target, op0, op1);
19787 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
19790 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
19793 tree arg0 = CALL_EXPR_ARG (exp, 0);
19794 tree arg1 = CALL_EXPR_ARG (exp, 1);
19795 rtx op0 = expand_normal (arg0);
19796 rtx op1 = expand_normal (arg1);
19797 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19798 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19799 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19801 if (VECTOR_MODE_P (mode0))
19802 op0 = safe_vector_operand (op0, mode0);
19803 if (VECTOR_MODE_P (mode1))
19804 op1 = safe_vector_operand (op1, mode1);
19806 if (optimize || !target
19807 || GET_MODE (target) != tmode
19808 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19809 target = gen_reg_rtx (tmode);
19811 if (GET_MODE (op1) == SImode && mode1 == TImode)
19813 rtx x = gen_reg_rtx (V4SImode);
19814 emit_insn (gen_sse2_loadd (x, op1));
19815 op1 = gen_lowpart (TImode, x);
19818 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19819 op0 = copy_to_mode_reg (mode0, op0);
19820 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19821 op1 = copy_to_mode_reg (mode1, op1);
19823 /* ??? Using ix86_fixup_binary_operands is problematic when
19824 we've got mismatched modes. Fake it. */
19830 if (tmode == mode0 && tmode == mode1)
19832 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
19836 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
19838 op0 = force_reg (mode0, op0);
19839 op1 = force_reg (mode1, op1);
19840 target = gen_reg_rtx (tmode);
19843 pat = GEN_FCN (icode) (target, op0, op1);
19850 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
19853 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
19854 enum multi_arg_type m_type,
19855 enum insn_code sub_code)
19860 bool comparison_p = false;
19862 bool last_arg_constant = false;
19863 int num_memory = 0;
19866 enum machine_mode mode;
19869 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19873 case MULTI_ARG_3_SF:
19874 case MULTI_ARG_3_DF:
19875 case MULTI_ARG_3_DI:
19876 case MULTI_ARG_3_SI:
19877 case MULTI_ARG_3_SI_DI:
19878 case MULTI_ARG_3_HI:
19879 case MULTI_ARG_3_HI_SI:
19880 case MULTI_ARG_3_QI:
19881 case MULTI_ARG_3_PERMPS:
19882 case MULTI_ARG_3_PERMPD:
19886 case MULTI_ARG_2_SF:
19887 case MULTI_ARG_2_DF:
19888 case MULTI_ARG_2_DI:
19889 case MULTI_ARG_2_SI:
19890 case MULTI_ARG_2_HI:
19891 case MULTI_ARG_2_QI:
19895 case MULTI_ARG_2_DI_IMM:
19896 case MULTI_ARG_2_SI_IMM:
19897 case MULTI_ARG_2_HI_IMM:
19898 case MULTI_ARG_2_QI_IMM:
19900 last_arg_constant = true;
19903 case MULTI_ARG_1_SF:
19904 case MULTI_ARG_1_DF:
19905 case MULTI_ARG_1_DI:
19906 case MULTI_ARG_1_SI:
19907 case MULTI_ARG_1_HI:
19908 case MULTI_ARG_1_QI:
19909 case MULTI_ARG_1_SI_DI:
19910 case MULTI_ARG_1_HI_DI:
19911 case MULTI_ARG_1_HI_SI:
19912 case MULTI_ARG_1_QI_DI:
19913 case MULTI_ARG_1_QI_SI:
19914 case MULTI_ARG_1_QI_HI:
19915 case MULTI_ARG_1_PH2PS:
19916 case MULTI_ARG_1_PS2PH:
19920 case MULTI_ARG_2_SF_CMP:
19921 case MULTI_ARG_2_DF_CMP:
19922 case MULTI_ARG_2_DI_CMP:
19923 case MULTI_ARG_2_SI_CMP:
19924 case MULTI_ARG_2_HI_CMP:
19925 case MULTI_ARG_2_QI_CMP:
19927 comparison_p = true;
19930 case MULTI_ARG_2_SF_TF:
19931 case MULTI_ARG_2_DF_TF:
19932 case MULTI_ARG_2_DI_TF:
19933 case MULTI_ARG_2_SI_TF:
19934 case MULTI_ARG_2_HI_TF:
19935 case MULTI_ARG_2_QI_TF:
19940 case MULTI_ARG_UNKNOWN:
19942 gcc_unreachable ();
19945 if (optimize || !target
19946 || GET_MODE (target) != tmode
19947 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19948 target = gen_reg_rtx (tmode);
19950 gcc_assert (nargs <= 4);
19952 for (i = 0; i < nargs; i++)
19954 tree arg = CALL_EXPR_ARG (exp, i);
19955 rtx op = expand_normal (arg);
19956 int adjust = (comparison_p) ? 1 : 0;
19957 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
19959 if (last_arg_constant && i == nargs-1)
19961 if (GET_CODE (op) != CONST_INT)
19963 error ("last argument must be an immediate");
19964 return gen_reg_rtx (tmode);
19969 if (VECTOR_MODE_P (mode))
19970 op = safe_vector_operand (op, mode);
19972 /* If we aren't optimizing, only allow one memory operand to be
19974 if (memory_operand (op, mode))
19977 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
19980 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
19982 op = force_reg (mode, op);
19986 args[i].mode = mode;
19992 pat = GEN_FCN (icode) (target, args[0].op);
19997 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
19998 GEN_INT ((int)sub_code));
19999 else if (! comparison_p)
20000 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
20003 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
20007 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
20012 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
20016 gcc_unreachable ();
20026 /* Subroutine of ix86_expand_builtin to take care of stores. */
20029 ix86_expand_store_builtin (enum insn_code icode, tree exp)
20032 tree arg0 = CALL_EXPR_ARG (exp, 0);
20033 tree arg1 = CALL_EXPR_ARG (exp, 1);
20034 rtx op0 = expand_normal (arg0);
20035 rtx op1 = expand_normal (arg1);
20036 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
20037 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
20039 if (VECTOR_MODE_P (mode1))
20040 op1 = safe_vector_operand (op1, mode1);
20042 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20043 op1 = copy_to_mode_reg (mode1, op1);
20045 pat = GEN_FCN (icode) (op0, op1);
20051 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
20054 ix86_expand_unop_builtin (enum insn_code icode, tree exp,
20055 rtx target, int do_load)
20058 tree arg0 = CALL_EXPR_ARG (exp, 0);
20059 rtx op0 = expand_normal (arg0);
20060 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20061 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20063 if (optimize || !target
20064 || GET_MODE (target) != tmode
20065 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20066 target = gen_reg_rtx (tmode);
20068 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20071 if (VECTOR_MODE_P (mode0))
20072 op0 = safe_vector_operand (op0, mode0);
20074 if ((optimize && !register_operand (op0, mode0))
20075 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20076 op0 = copy_to_mode_reg (mode0, op0);
20081 case CODE_FOR_sse4_1_roundpd:
20082 case CODE_FOR_sse4_1_roundps:
20084 tree arg1 = CALL_EXPR_ARG (exp, 1);
20085 rtx op1 = expand_normal (arg1);
20086 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20088 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
20090 error ("the second argument must be a 4-bit immediate");
20093 pat = GEN_FCN (icode) (target, op0, op1);
20097 pat = GEN_FCN (icode) (target, op0);
20107 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
20108 sqrtss, rsqrtss, rcpss. */
20111 ix86_expand_unop1_builtin (enum insn_code icode, tree exp, rtx target)
20114 tree arg0 = CALL_EXPR_ARG (exp, 0);
20115 rtx op1, op0 = expand_normal (arg0);
20116 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20117 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20119 if (optimize || !target
20120 || GET_MODE (target) != tmode
20121 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20122 target = gen_reg_rtx (tmode);
20124 if (VECTOR_MODE_P (mode0))
20125 op0 = safe_vector_operand (op0, mode0);
20127 if ((optimize && !register_operand (op0, mode0))
20128 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20129 op0 = copy_to_mode_reg (mode0, op0);
20132 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
20133 op1 = copy_to_mode_reg (mode0, op1);
20135 pat = GEN_FCN (icode) (target, op0, op1);
20142 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
20145 ix86_expand_sse_compare (const struct builtin_description *d, tree exp,
20149 tree arg0 = CALL_EXPR_ARG (exp, 0);
20150 tree arg1 = CALL_EXPR_ARG (exp, 1);
20151 rtx op0 = expand_normal (arg0);
20152 rtx op1 = expand_normal (arg1);
20154 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
20155 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
20156 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
20157 enum rtx_code comparison = d->comparison;
20159 if (VECTOR_MODE_P (mode0))
20160 op0 = safe_vector_operand (op0, mode0);
20161 if (VECTOR_MODE_P (mode1))
20162 op1 = safe_vector_operand (op1, mode1);
20164 /* Swap operands if we have a comparison that isn't available in
20166 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20168 rtx tmp = gen_reg_rtx (mode1);
20169 emit_move_insn (tmp, op1);
20174 if (optimize || !target
20175 || GET_MODE (target) != tmode
20176 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
20177 target = gen_reg_rtx (tmode);
20179 if ((optimize && !register_operand (op0, mode0))
20180 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
20181 op0 = copy_to_mode_reg (mode0, op0);
20182 if ((optimize && !register_operand (op1, mode1))
20183 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
20184 op1 = copy_to_mode_reg (mode1, op1);
20186 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
20187 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
20194 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
20197 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
20201 tree arg0 = CALL_EXPR_ARG (exp, 0);
20202 tree arg1 = CALL_EXPR_ARG (exp, 1);
20203 rtx op0 = expand_normal (arg0);
20204 rtx op1 = expand_normal (arg1);
20205 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20206 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20207 enum rtx_code comparison = d->comparison;
20209 if (VECTOR_MODE_P (mode0))
20210 op0 = safe_vector_operand (op0, mode0);
20211 if (VECTOR_MODE_P (mode1))
20212 op1 = safe_vector_operand (op1, mode1);
20214 /* Swap operands if we have a comparison that isn't available in
20216 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20223 target = gen_reg_rtx (SImode);
20224 emit_move_insn (target, const0_rtx);
20225 target = gen_rtx_SUBREG (QImode, target, 0);
20227 if ((optimize && !register_operand (op0, mode0))
20228 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20229 op0 = copy_to_mode_reg (mode0, op0);
20230 if ((optimize && !register_operand (op1, mode1))
20231 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20232 op1 = copy_to_mode_reg (mode1, op1);
20234 pat = GEN_FCN (d->icode) (op0, op1);
20238 emit_insn (gen_rtx_SET (VOIDmode,
20239 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20240 gen_rtx_fmt_ee (comparison, QImode,
20244 return SUBREG_REG (target);
20247 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
20250 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
20254 tree arg0 = CALL_EXPR_ARG (exp, 0);
20255 tree arg1 = CALL_EXPR_ARG (exp, 1);
20256 rtx op0 = expand_normal (arg0);
20257 rtx op1 = expand_normal (arg1);
20258 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20259 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20260 enum rtx_code comparison = d->comparison;
20262 if (VECTOR_MODE_P (mode0))
20263 op0 = safe_vector_operand (op0, mode0);
20264 if (VECTOR_MODE_P (mode1))
20265 op1 = safe_vector_operand (op1, mode1);
20267 target = gen_reg_rtx (SImode);
20268 emit_move_insn (target, const0_rtx);
20269 target = gen_rtx_SUBREG (QImode, target, 0);
20271 if ((optimize && !register_operand (op0, mode0))
20272 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20273 op0 = copy_to_mode_reg (mode0, op0);
20274 if ((optimize && !register_operand (op1, mode1))
20275 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20276 op1 = copy_to_mode_reg (mode1, op1);
20278 pat = GEN_FCN (d->icode) (op0, op1);
20282 emit_insn (gen_rtx_SET (VOIDmode,
20283 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20284 gen_rtx_fmt_ee (comparison, QImode,
20288 return SUBREG_REG (target);
20291 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
20294 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
20295 tree exp, rtx target)
20298 tree arg0 = CALL_EXPR_ARG (exp, 0);
20299 tree arg1 = CALL_EXPR_ARG (exp, 1);
20300 tree arg2 = CALL_EXPR_ARG (exp, 2);
20301 tree arg3 = CALL_EXPR_ARG (exp, 3);
20302 tree arg4 = CALL_EXPR_ARG (exp, 4);
20303 rtx scratch0, scratch1;
20304 rtx op0 = expand_normal (arg0);
20305 rtx op1 = expand_normal (arg1);
20306 rtx op2 = expand_normal (arg2);
20307 rtx op3 = expand_normal (arg3);
20308 rtx op4 = expand_normal (arg4);
20309 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
20311 tmode0 = insn_data[d->icode].operand[0].mode;
20312 tmode1 = insn_data[d->icode].operand[1].mode;
20313 modev2 = insn_data[d->icode].operand[2].mode;
20314 modei3 = insn_data[d->icode].operand[3].mode;
20315 modev4 = insn_data[d->icode].operand[4].mode;
20316 modei5 = insn_data[d->icode].operand[5].mode;
20317 modeimm = insn_data[d->icode].operand[6].mode;
20319 if (VECTOR_MODE_P (modev2))
20320 op0 = safe_vector_operand (op0, modev2);
20321 if (VECTOR_MODE_P (modev4))
20322 op2 = safe_vector_operand (op2, modev4);
20324 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20325 op0 = copy_to_mode_reg (modev2, op0);
20326 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
20327 op1 = copy_to_mode_reg (modei3, op1);
20328 if ((optimize && !register_operand (op2, modev4))
20329 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
20330 op2 = copy_to_mode_reg (modev4, op2);
20331 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
20332 op3 = copy_to_mode_reg (modei5, op3);
20334 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
20336 error ("the fifth argument must be a 8-bit immediate");
20340 if (d->code == IX86_BUILTIN_PCMPESTRI128)
20342 if (optimize || !target
20343 || GET_MODE (target) != tmode0
20344 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20345 target = gen_reg_rtx (tmode0);
20347 scratch1 = gen_reg_rtx (tmode1);
20349 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
20351 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
20353 if (optimize || !target
20354 || GET_MODE (target) != tmode1
20355 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20356 target = gen_reg_rtx (tmode1);
20358 scratch0 = gen_reg_rtx (tmode0);
20360 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
20364 gcc_assert (d->flag);
20366 scratch0 = gen_reg_rtx (tmode0);
20367 scratch1 = gen_reg_rtx (tmode1);
20369 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
20379 target = gen_reg_rtx (SImode);
20380 emit_move_insn (target, const0_rtx);
20381 target = gen_rtx_SUBREG (QImode, target, 0);
20384 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20385 gen_rtx_fmt_ee (EQ, QImode,
20386 gen_rtx_REG ((enum machine_mode) d->flag,
20389 return SUBREG_REG (target);
20396 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
20399 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
20400 tree exp, rtx target)
20403 tree arg0 = CALL_EXPR_ARG (exp, 0);
20404 tree arg1 = CALL_EXPR_ARG (exp, 1);
20405 tree arg2 = CALL_EXPR_ARG (exp, 2);
20406 rtx scratch0, scratch1;
20407 rtx op0 = expand_normal (arg0);
20408 rtx op1 = expand_normal (arg1);
20409 rtx op2 = expand_normal (arg2);
20410 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
20412 tmode0 = insn_data[d->icode].operand[0].mode;
20413 tmode1 = insn_data[d->icode].operand[1].mode;
20414 modev2 = insn_data[d->icode].operand[2].mode;
20415 modev3 = insn_data[d->icode].operand[3].mode;
20416 modeimm = insn_data[d->icode].operand[4].mode;
20418 if (VECTOR_MODE_P (modev2))
20419 op0 = safe_vector_operand (op0, modev2);
20420 if (VECTOR_MODE_P (modev3))
20421 op1 = safe_vector_operand (op1, modev3);
20423 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20424 op0 = copy_to_mode_reg (modev2, op0);
20425 if ((optimize && !register_operand (op1, modev3))
20426 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
20427 op1 = copy_to_mode_reg (modev3, op1);
20429 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
20431 error ("the third argument must be a 8-bit immediate");
20435 if (d->code == IX86_BUILTIN_PCMPISTRI128)
20437 if (optimize || !target
20438 || GET_MODE (target) != tmode0
20439 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20440 target = gen_reg_rtx (tmode0);
20442 scratch1 = gen_reg_rtx (tmode1);
20444 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
20446 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
20448 if (optimize || !target
20449 || GET_MODE (target) != tmode1
20450 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20451 target = gen_reg_rtx (tmode1);
20453 scratch0 = gen_reg_rtx (tmode0);
20455 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
20459 gcc_assert (d->flag);
20461 scratch0 = gen_reg_rtx (tmode0);
20462 scratch1 = gen_reg_rtx (tmode1);
20464 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
20474 target = gen_reg_rtx (SImode);
20475 emit_move_insn (target, const0_rtx);
20476 target = gen_rtx_SUBREG (QImode, target, 0);
20479 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20480 gen_rtx_fmt_ee (EQ, QImode,
20481 gen_rtx_REG ((enum machine_mode) d->flag,
20484 return SUBREG_REG (target);
20490 /* Return the integer constant in ARG. Constrain it to be in the range
20491 of the subparts of VEC_TYPE; issue an error if not. */
20494 get_element_number (tree vec_type, tree arg)
20496 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
20498 if (!host_integerp (arg, 1)
20499 || (elt = tree_low_cst (arg, 1), elt > max))
20501 error ("selector must be an integer constant in the range 0..%wi", max);
20508 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20509 ix86_expand_vector_init. We DO have language-level syntax for this, in
20510 the form of (type){ init-list }. Except that since we can't place emms
20511 instructions from inside the compiler, we can't allow the use of MMX
20512 registers unless the user explicitly asks for it. So we do *not* define
20513 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
20514 we have builtins invoked by mmintrin.h that gives us license to emit
20515 these sorts of instructions. */
20518 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
20520 enum machine_mode tmode = TYPE_MODE (type);
20521 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
20522 int i, n_elt = GET_MODE_NUNITS (tmode);
20523 rtvec v = rtvec_alloc (n_elt);
20525 gcc_assert (VECTOR_MODE_P (tmode));
20526 gcc_assert (call_expr_nargs (exp) == n_elt);
20528 for (i = 0; i < n_elt; ++i)
20530 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
20531 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
20534 if (!target || !register_operand (target, tmode))
20535 target = gen_reg_rtx (tmode);
20537 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
20541 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20542 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
20543 had a language-level syntax for referencing vector elements. */
20546 ix86_expand_vec_ext_builtin (tree exp, rtx target)
20548 enum machine_mode tmode, mode0;
20553 arg0 = CALL_EXPR_ARG (exp, 0);
20554 arg1 = CALL_EXPR_ARG (exp, 1);
20556 op0 = expand_normal (arg0);
20557 elt = get_element_number (TREE_TYPE (arg0), arg1);
20559 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20560 mode0 = TYPE_MODE (TREE_TYPE (arg0));
20561 gcc_assert (VECTOR_MODE_P (mode0));
20563 op0 = force_reg (mode0, op0);
20565 if (optimize || !target || !register_operand (target, tmode))
20566 target = gen_reg_rtx (tmode);
20568 ix86_expand_vector_extract (true, target, op0, elt);
20573 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20574 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
20575 a language-level syntax for referencing vector elements. */
20578 ix86_expand_vec_set_builtin (tree exp)
20580 enum machine_mode tmode, mode1;
20581 tree arg0, arg1, arg2;
20583 rtx op0, op1, target;
20585 arg0 = CALL_EXPR_ARG (exp, 0);
20586 arg1 = CALL_EXPR_ARG (exp, 1);
20587 arg2 = CALL_EXPR_ARG (exp, 2);
20589 tmode = TYPE_MODE (TREE_TYPE (arg0));
20590 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20591 gcc_assert (VECTOR_MODE_P (tmode));
20593 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
20594 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
20595 elt = get_element_number (TREE_TYPE (arg0), arg2);
20597 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
20598 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
20600 op0 = force_reg (tmode, op0);
20601 op1 = force_reg (mode1, op1);
20603 /* OP0 is the source of these builtin functions and shouldn't be
20604 modified. Create a copy, use it and return it as target. */
20605 target = gen_reg_rtx (tmode);
20606 emit_move_insn (target, op0);
20607 ix86_expand_vector_set (true, target, op1, elt);
20612 /* Expand an expression EXP that calls a built-in function,
20613 with result going to TARGET if that's convenient
20614 (and in mode MODE if that's convenient).
20615 SUBTARGET may be used as the target for computing one of EXP's operands.
20616 IGNORE is nonzero if the value is to be ignored. */
20619 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
20620 enum machine_mode mode ATTRIBUTE_UNUSED,
20621 int ignore ATTRIBUTE_UNUSED)
20623 const struct builtin_description *d;
20625 enum insn_code icode;
20626 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
20627 tree arg0, arg1, arg2, arg3;
20628 rtx op0, op1, op2, op3, pat;
20629 enum machine_mode tmode, mode0, mode1, mode2, mode3, mode4;
20630 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
20634 case IX86_BUILTIN_EMMS:
20635 emit_insn (gen_mmx_emms ());
20638 case IX86_BUILTIN_SFENCE:
20639 emit_insn (gen_sse_sfence ());
20642 case IX86_BUILTIN_MASKMOVQ:
20643 case IX86_BUILTIN_MASKMOVDQU:
20644 icode = (fcode == IX86_BUILTIN_MASKMOVQ
20645 ? CODE_FOR_mmx_maskmovq
20646 : CODE_FOR_sse2_maskmovdqu);
20647 /* Note the arg order is different from the operand order. */
20648 arg1 = CALL_EXPR_ARG (exp, 0);
20649 arg2 = CALL_EXPR_ARG (exp, 1);
20650 arg0 = CALL_EXPR_ARG (exp, 2);
20651 op0 = expand_normal (arg0);
20652 op1 = expand_normal (arg1);
20653 op2 = expand_normal (arg2);
20654 mode0 = insn_data[icode].operand[0].mode;
20655 mode1 = insn_data[icode].operand[1].mode;
20656 mode2 = insn_data[icode].operand[2].mode;
20658 op0 = force_reg (Pmode, op0);
20659 op0 = gen_rtx_MEM (mode1, op0);
20661 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
20662 op0 = copy_to_mode_reg (mode0, op0);
20663 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
20664 op1 = copy_to_mode_reg (mode1, op1);
20665 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
20666 op2 = copy_to_mode_reg (mode2, op2);
20667 pat = GEN_FCN (icode) (op0, op1, op2);
20673 case IX86_BUILTIN_RSQRTF:
20674 return ix86_expand_unop1_builtin (CODE_FOR_rsqrtsf2, exp, target);
20676 case IX86_BUILTIN_SQRTSS:
20677 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, exp, target);
20678 case IX86_BUILTIN_RSQRTSS:
20679 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, exp, target);
20680 case IX86_BUILTIN_RCPSS:
20681 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, exp, target);
20683 case IX86_BUILTIN_LOADUPS:
20684 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, exp, target, 1);
20686 case IX86_BUILTIN_STOREUPS:
20687 return ix86_expand_store_builtin (CODE_FOR_sse_movups, exp);
20689 case IX86_BUILTIN_LOADHPS:
20690 case IX86_BUILTIN_LOADLPS:
20691 case IX86_BUILTIN_LOADHPD:
20692 case IX86_BUILTIN_LOADLPD:
20693 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
20694 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
20695 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
20696 : CODE_FOR_sse2_loadlpd);
20697 arg0 = CALL_EXPR_ARG (exp, 0);
20698 arg1 = CALL_EXPR_ARG (exp, 1);
20699 op0 = expand_normal (arg0);
20700 op1 = expand_normal (arg1);
20701 tmode = insn_data[icode].operand[0].mode;
20702 mode0 = insn_data[icode].operand[1].mode;
20703 mode1 = insn_data[icode].operand[2].mode;
20705 op0 = force_reg (mode0, op0);
20706 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
20707 if (optimize || target == 0
20708 || GET_MODE (target) != tmode
20709 || !register_operand (target, tmode))
20710 target = gen_reg_rtx (tmode);
20711 pat = GEN_FCN (icode) (target, op0, op1);
20717 case IX86_BUILTIN_STOREHPS:
20718 case IX86_BUILTIN_STORELPS:
20719 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
20720 : CODE_FOR_sse_storelps);
20721 arg0 = CALL_EXPR_ARG (exp, 0);
20722 arg1 = CALL_EXPR_ARG (exp, 1);
20723 op0 = expand_normal (arg0);
20724 op1 = expand_normal (arg1);
20725 mode0 = insn_data[icode].operand[0].mode;
20726 mode1 = insn_data[icode].operand[1].mode;
20728 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20729 op1 = force_reg (mode1, op1);
20731 pat = GEN_FCN (icode) (op0, op1);
20737 case IX86_BUILTIN_MOVNTPS:
20738 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, exp);
20739 case IX86_BUILTIN_MOVNTQ:
20740 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, exp);
20742 case IX86_BUILTIN_LDMXCSR:
20743 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
20744 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20745 emit_move_insn (target, op0);
20746 emit_insn (gen_sse_ldmxcsr (target));
20749 case IX86_BUILTIN_STMXCSR:
20750 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20751 emit_insn (gen_sse_stmxcsr (target));
20752 return copy_to_mode_reg (SImode, target);
20754 case IX86_BUILTIN_SHUFPS:
20755 case IX86_BUILTIN_SHUFPD:
20756 icode = (fcode == IX86_BUILTIN_SHUFPS
20757 ? CODE_FOR_sse_shufps
20758 : CODE_FOR_sse2_shufpd);
20759 arg0 = CALL_EXPR_ARG (exp, 0);
20760 arg1 = CALL_EXPR_ARG (exp, 1);
20761 arg2 = CALL_EXPR_ARG (exp, 2);
20762 op0 = expand_normal (arg0);
20763 op1 = expand_normal (arg1);
20764 op2 = expand_normal (arg2);
20765 tmode = insn_data[icode].operand[0].mode;
20766 mode0 = insn_data[icode].operand[1].mode;
20767 mode1 = insn_data[icode].operand[2].mode;
20768 mode2 = insn_data[icode].operand[3].mode;
20770 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20771 op0 = copy_to_mode_reg (mode0, op0);
20772 if ((optimize && !register_operand (op1, mode1))
20773 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
20774 op1 = copy_to_mode_reg (mode1, op1);
20775 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
20777 /* @@@ better error message */
20778 error ("mask must be an immediate");
20779 return gen_reg_rtx (tmode);
20781 if (optimize || target == 0
20782 || GET_MODE (target) != tmode
20783 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20784 target = gen_reg_rtx (tmode);
20785 pat = GEN_FCN (icode) (target, op0, op1, op2);
20791 case IX86_BUILTIN_PSHUFW:
20792 case IX86_BUILTIN_PSHUFD:
20793 case IX86_BUILTIN_PSHUFHW:
20794 case IX86_BUILTIN_PSHUFLW:
20795 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
20796 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
20797 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
20798 : CODE_FOR_mmx_pshufw);
20799 arg0 = CALL_EXPR_ARG (exp, 0);
20800 arg1 = CALL_EXPR_ARG (exp, 1);
20801 op0 = expand_normal (arg0);
20802 op1 = expand_normal (arg1);
20803 tmode = insn_data[icode].operand[0].mode;
20804 mode1 = insn_data[icode].operand[1].mode;
20805 mode2 = insn_data[icode].operand[2].mode;
20807 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20808 op0 = copy_to_mode_reg (mode1, op0);
20809 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20811 /* @@@ better error message */
20812 error ("mask must be an immediate");
20816 || GET_MODE (target) != tmode
20817 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20818 target = gen_reg_rtx (tmode);
20819 pat = GEN_FCN (icode) (target, op0, op1);
20825 case IX86_BUILTIN_PSLLW:
20826 case IX86_BUILTIN_PSLLWI:
20827 icode = CODE_FOR_mmx_ashlv4hi3;
20829 case IX86_BUILTIN_PSLLD:
20830 case IX86_BUILTIN_PSLLDI:
20831 icode = CODE_FOR_mmx_ashlv2si3;
20833 case IX86_BUILTIN_PSLLQ:
20834 case IX86_BUILTIN_PSLLQI:
20835 icode = CODE_FOR_mmx_ashlv1di3;
20837 case IX86_BUILTIN_PSRAW:
20838 case IX86_BUILTIN_PSRAWI:
20839 icode = CODE_FOR_mmx_ashrv4hi3;
20841 case IX86_BUILTIN_PSRAD:
20842 case IX86_BUILTIN_PSRADI:
20843 icode = CODE_FOR_mmx_ashrv2si3;
20845 case IX86_BUILTIN_PSRLW:
20846 case IX86_BUILTIN_PSRLWI:
20847 icode = CODE_FOR_mmx_lshrv4hi3;
20849 case IX86_BUILTIN_PSRLD:
20850 case IX86_BUILTIN_PSRLDI:
20851 icode = CODE_FOR_mmx_lshrv2si3;
20853 case IX86_BUILTIN_PSRLQ:
20854 case IX86_BUILTIN_PSRLQI:
20855 icode = CODE_FOR_mmx_lshrv1di3;
20858 case IX86_BUILTIN_PSLLW128:
20859 case IX86_BUILTIN_PSLLWI128:
20860 icode = CODE_FOR_ashlv8hi3;
20862 case IX86_BUILTIN_PSLLD128:
20863 case IX86_BUILTIN_PSLLDI128:
20864 icode = CODE_FOR_ashlv4si3;
20866 case IX86_BUILTIN_PSLLQ128:
20867 case IX86_BUILTIN_PSLLQI128:
20868 icode = CODE_FOR_ashlv2di3;
20870 case IX86_BUILTIN_PSRAW128:
20871 case IX86_BUILTIN_PSRAWI128:
20872 icode = CODE_FOR_ashrv8hi3;
20874 case IX86_BUILTIN_PSRAD128:
20875 case IX86_BUILTIN_PSRADI128:
20876 icode = CODE_FOR_ashrv4si3;
20878 case IX86_BUILTIN_PSRLW128:
20879 case IX86_BUILTIN_PSRLWI128:
20880 icode = CODE_FOR_lshrv8hi3;
20882 case IX86_BUILTIN_PSRLD128:
20883 case IX86_BUILTIN_PSRLDI128:
20884 icode = CODE_FOR_lshrv4si3;
20886 case IX86_BUILTIN_PSRLQ128:
20887 case IX86_BUILTIN_PSRLQI128:
20888 icode = CODE_FOR_lshrv2di3;
20891 arg0 = CALL_EXPR_ARG (exp, 0);
20892 arg1 = CALL_EXPR_ARG (exp, 1);
20893 op0 = expand_normal (arg0);
20894 op1 = expand_normal (arg1);
20896 tmode = insn_data[icode].operand[0].mode;
20897 mode1 = insn_data[icode].operand[1].mode;
20899 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20900 op0 = copy_to_reg (op0);
20902 if (!CONST_INT_P (op1))
20903 op1 = simplify_gen_subreg (SImode, op1, GET_MODE (op1), 0);
20905 if (! (*insn_data[icode].operand[2].predicate) (op1, SImode))
20906 op1 = copy_to_reg (op1);
20908 target = gen_reg_rtx (tmode);
20909 pat = GEN_FCN (icode) (target, op0, op1);
20915 case IX86_BUILTIN_PSLLDQI128:
20916 case IX86_BUILTIN_PSRLDQI128:
20917 icode = (fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
20918 : CODE_FOR_sse2_lshrti3);
20919 arg0 = CALL_EXPR_ARG (exp, 0);
20920 arg1 = CALL_EXPR_ARG (exp, 1);
20921 op0 = expand_normal (arg0);
20922 op1 = expand_normal (arg1);
20923 tmode = insn_data[icode].operand[0].mode;
20924 mode1 = insn_data[icode].operand[1].mode;
20925 mode2 = insn_data[icode].operand[2].mode;
20927 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20929 op0 = copy_to_reg (op0);
20930 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
20932 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20934 error ("shift must be an immediate");
20937 target = gen_reg_rtx (V2DImode);
20938 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0),
20945 case IX86_BUILTIN_FEMMS:
20946 emit_insn (gen_mmx_femms ());
20949 case IX86_BUILTIN_PAVGUSB:
20950 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, exp, target);
20952 case IX86_BUILTIN_PF2ID:
20953 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, exp, target, 0);
20955 case IX86_BUILTIN_PFACC:
20956 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, exp, target);
20958 case IX86_BUILTIN_PFADD:
20959 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, exp, target);
20961 case IX86_BUILTIN_PFCMPEQ:
20962 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, exp, target);
20964 case IX86_BUILTIN_PFCMPGE:
20965 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, exp, target);
20967 case IX86_BUILTIN_PFCMPGT:
20968 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, exp, target);
20970 case IX86_BUILTIN_PFMAX:
20971 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, exp, target);
20973 case IX86_BUILTIN_PFMIN:
20974 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, exp, target);
20976 case IX86_BUILTIN_PFMUL:
20977 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, exp, target);
20979 case IX86_BUILTIN_PFRCP:
20980 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, exp, target, 0);
20982 case IX86_BUILTIN_PFRCPIT1:
20983 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, exp, target);
20985 case IX86_BUILTIN_PFRCPIT2:
20986 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, exp, target);
20988 case IX86_BUILTIN_PFRSQIT1:
20989 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, exp, target);
20991 case IX86_BUILTIN_PFRSQRT:
20992 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, exp, target, 0);
20994 case IX86_BUILTIN_PFSUB:
20995 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, exp, target);
20997 case IX86_BUILTIN_PFSUBR:
20998 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, exp, target);
21000 case IX86_BUILTIN_PI2FD:
21001 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, exp, target, 0);
21003 case IX86_BUILTIN_PMULHRW:
21004 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, exp, target);
21006 case IX86_BUILTIN_PF2IW:
21007 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, exp, target, 0);
21009 case IX86_BUILTIN_PFNACC:
21010 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, exp, target);
21012 case IX86_BUILTIN_PFPNACC:
21013 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, exp, target);
21015 case IX86_BUILTIN_PI2FW:
21016 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, exp, target, 0);
21018 case IX86_BUILTIN_PSWAPDSI:
21019 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, exp, target, 0);
21021 case IX86_BUILTIN_PSWAPDSF:
21022 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, exp, target, 0);
21024 case IX86_BUILTIN_SQRTSD:
21025 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, exp, target);
21026 case IX86_BUILTIN_LOADUPD:
21027 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, exp, target, 1);
21028 case IX86_BUILTIN_STOREUPD:
21029 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, exp);
21031 case IX86_BUILTIN_MFENCE:
21032 emit_insn (gen_sse2_mfence ());
21034 case IX86_BUILTIN_LFENCE:
21035 emit_insn (gen_sse2_lfence ());
21038 case IX86_BUILTIN_CLFLUSH:
21039 arg0 = CALL_EXPR_ARG (exp, 0);
21040 op0 = expand_normal (arg0);
21041 icode = CODE_FOR_sse2_clflush;
21042 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
21043 op0 = copy_to_mode_reg (Pmode, op0);
21045 emit_insn (gen_sse2_clflush (op0));
21048 case IX86_BUILTIN_MOVNTPD:
21049 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, exp);
21050 case IX86_BUILTIN_MOVNTDQ:
21051 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, exp);
21052 case IX86_BUILTIN_MOVNTI:
21053 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, exp);
21055 case IX86_BUILTIN_LOADDQU:
21056 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, exp, target, 1);
21057 case IX86_BUILTIN_STOREDQU:
21058 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, exp);
21060 case IX86_BUILTIN_MONITOR:
21061 arg0 = CALL_EXPR_ARG (exp, 0);
21062 arg1 = CALL_EXPR_ARG (exp, 1);
21063 arg2 = CALL_EXPR_ARG (exp, 2);
21064 op0 = expand_normal (arg0);
21065 op1 = expand_normal (arg1);
21066 op2 = expand_normal (arg2);
21068 op0 = copy_to_mode_reg (Pmode, op0);
21070 op1 = copy_to_mode_reg (SImode, op1);
21072 op2 = copy_to_mode_reg (SImode, op2);
21074 emit_insn (gen_sse3_monitor (op0, op1, op2));
21076 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
21079 case IX86_BUILTIN_MWAIT:
21080 arg0 = CALL_EXPR_ARG (exp, 0);
21081 arg1 = CALL_EXPR_ARG (exp, 1);
21082 op0 = expand_normal (arg0);
21083 op1 = expand_normal (arg1);
21085 op0 = copy_to_mode_reg (SImode, op0);
21087 op1 = copy_to_mode_reg (SImode, op1);
21088 emit_insn (gen_sse3_mwait (op0, op1));
21091 case IX86_BUILTIN_LDDQU:
21092 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, exp,
21095 case IX86_BUILTIN_PALIGNR:
21096 case IX86_BUILTIN_PALIGNR128:
21097 if (fcode == IX86_BUILTIN_PALIGNR)
21099 icode = CODE_FOR_ssse3_palignrdi;
21104 icode = CODE_FOR_ssse3_palignrti;
21107 arg0 = CALL_EXPR_ARG (exp, 0);
21108 arg1 = CALL_EXPR_ARG (exp, 1);
21109 arg2 = CALL_EXPR_ARG (exp, 2);
21110 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21111 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21112 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21113 tmode = insn_data[icode].operand[0].mode;
21114 mode1 = insn_data[icode].operand[1].mode;
21115 mode2 = insn_data[icode].operand[2].mode;
21116 mode3 = insn_data[icode].operand[3].mode;
21118 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21120 op0 = copy_to_reg (op0);
21121 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
21123 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21125 op1 = copy_to_reg (op1);
21126 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
21128 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21130 error ("shift must be an immediate");
21133 target = gen_reg_rtx (mode);
21134 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
21141 case IX86_BUILTIN_MOVNTDQA:
21142 return ix86_expand_unop_builtin (CODE_FOR_sse4_1_movntdqa, exp,
21145 case IX86_BUILTIN_MOVNTSD:
21146 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv2df, exp);
21148 case IX86_BUILTIN_MOVNTSS:
21149 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv4sf, exp);
21151 case IX86_BUILTIN_INSERTQ:
21152 case IX86_BUILTIN_EXTRQ:
21153 icode = (fcode == IX86_BUILTIN_EXTRQ
21154 ? CODE_FOR_sse4a_extrq
21155 : CODE_FOR_sse4a_insertq);
21156 arg0 = CALL_EXPR_ARG (exp, 0);
21157 arg1 = CALL_EXPR_ARG (exp, 1);
21158 op0 = expand_normal (arg0);
21159 op1 = expand_normal (arg1);
21160 tmode = insn_data[icode].operand[0].mode;
21161 mode1 = insn_data[icode].operand[1].mode;
21162 mode2 = insn_data[icode].operand[2].mode;
21163 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21164 op0 = copy_to_mode_reg (mode1, op0);
21165 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21166 op1 = copy_to_mode_reg (mode2, op1);
21167 if (optimize || target == 0
21168 || GET_MODE (target) != tmode
21169 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21170 target = gen_reg_rtx (tmode);
21171 pat = GEN_FCN (icode) (target, op0, op1);
21177 case IX86_BUILTIN_EXTRQI:
21178 icode = CODE_FOR_sse4a_extrqi;
21179 arg0 = CALL_EXPR_ARG (exp, 0);
21180 arg1 = CALL_EXPR_ARG (exp, 1);
21181 arg2 = CALL_EXPR_ARG (exp, 2);
21182 op0 = expand_normal (arg0);
21183 op1 = expand_normal (arg1);
21184 op2 = expand_normal (arg2);
21185 tmode = insn_data[icode].operand[0].mode;
21186 mode1 = insn_data[icode].operand[1].mode;
21187 mode2 = insn_data[icode].operand[2].mode;
21188 mode3 = insn_data[icode].operand[3].mode;
21189 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21190 op0 = copy_to_mode_reg (mode1, op0);
21191 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21193 error ("index mask must be an immediate");
21194 return gen_reg_rtx (tmode);
21196 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21198 error ("length mask must be an immediate");
21199 return gen_reg_rtx (tmode);
21201 if (optimize || target == 0
21202 || GET_MODE (target) != tmode
21203 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21204 target = gen_reg_rtx (tmode);
21205 pat = GEN_FCN (icode) (target, op0, op1, op2);
21211 case IX86_BUILTIN_INSERTQI:
21212 icode = CODE_FOR_sse4a_insertqi;
21213 arg0 = CALL_EXPR_ARG (exp, 0);
21214 arg1 = CALL_EXPR_ARG (exp, 1);
21215 arg2 = CALL_EXPR_ARG (exp, 2);
21216 arg3 = CALL_EXPR_ARG (exp, 3);
21217 op0 = expand_normal (arg0);
21218 op1 = expand_normal (arg1);
21219 op2 = expand_normal (arg2);
21220 op3 = expand_normal (arg3);
21221 tmode = insn_data[icode].operand[0].mode;
21222 mode1 = insn_data[icode].operand[1].mode;
21223 mode2 = insn_data[icode].operand[2].mode;
21224 mode3 = insn_data[icode].operand[3].mode;
21225 mode4 = insn_data[icode].operand[4].mode;
21227 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21228 op0 = copy_to_mode_reg (mode1, op0);
21230 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21231 op1 = copy_to_mode_reg (mode2, op1);
21233 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21235 error ("index mask must be an immediate");
21236 return gen_reg_rtx (tmode);
21238 if (! (*insn_data[icode].operand[4].predicate) (op3, mode4))
21240 error ("length mask must be an immediate");
21241 return gen_reg_rtx (tmode);
21243 if (optimize || target == 0
21244 || GET_MODE (target) != tmode
21245 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21246 target = gen_reg_rtx (tmode);
21247 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
21253 case IX86_BUILTIN_VEC_INIT_V2SI:
21254 case IX86_BUILTIN_VEC_INIT_V4HI:
21255 case IX86_BUILTIN_VEC_INIT_V8QI:
21256 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
21258 case IX86_BUILTIN_VEC_EXT_V2DF:
21259 case IX86_BUILTIN_VEC_EXT_V2DI:
21260 case IX86_BUILTIN_VEC_EXT_V4SF:
21261 case IX86_BUILTIN_VEC_EXT_V4SI:
21262 case IX86_BUILTIN_VEC_EXT_V8HI:
21263 case IX86_BUILTIN_VEC_EXT_V2SI:
21264 case IX86_BUILTIN_VEC_EXT_V4HI:
21265 case IX86_BUILTIN_VEC_EXT_V16QI:
21266 return ix86_expand_vec_ext_builtin (exp, target);
21268 case IX86_BUILTIN_VEC_SET_V2DI:
21269 case IX86_BUILTIN_VEC_SET_V4SF:
21270 case IX86_BUILTIN_VEC_SET_V4SI:
21271 case IX86_BUILTIN_VEC_SET_V8HI:
21272 case IX86_BUILTIN_VEC_SET_V4HI:
21273 case IX86_BUILTIN_VEC_SET_V16QI:
21274 return ix86_expand_vec_set_builtin (exp);
21276 case IX86_BUILTIN_INFQ:
21278 REAL_VALUE_TYPE inf;
21282 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
21284 tmp = validize_mem (force_const_mem (mode, tmp));
21287 target = gen_reg_rtx (mode);
21289 emit_move_insn (target, tmp);
21293 case IX86_BUILTIN_FABSQ:
21294 return ix86_expand_unop_builtin (CODE_FOR_abstf2, exp, target, 0);
21296 case IX86_BUILTIN_COPYSIGNQ:
21297 return ix86_expand_binop_builtin (CODE_FOR_copysigntf3, exp, target);
21303 for (i = 0, d = bdesc_sse_3arg;
21304 i < ARRAY_SIZE (bdesc_sse_3arg);
21306 if (d->code == fcode)
21307 return ix86_expand_sse_4_operands_builtin (d->icode, exp,
21310 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
21311 if (d->code == fcode)
21313 /* Compares are treated specially. */
21314 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
21315 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
21316 || d->icode == CODE_FOR_sse2_maskcmpv2df3
21317 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
21318 return ix86_expand_sse_compare (d, exp, target);
21320 return ix86_expand_binop_builtin (d->icode, exp, target);
21323 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
21324 if (d->code == fcode)
21325 return ix86_expand_unop_builtin (d->icode, exp, target, 0);
21327 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21328 if (d->code == fcode)
21329 return ix86_expand_sse_comi (d, exp, target);
21331 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
21332 if (d->code == fcode)
21333 return ix86_expand_sse_ptest (d, exp, target);
21335 for (i = 0, d = bdesc_crc32; i < ARRAY_SIZE (bdesc_crc32); i++, d++)
21336 if (d->code == fcode)
21337 return ix86_expand_crc32 (d->icode, exp, target);
21339 for (i = 0, d = bdesc_pcmpestr;
21340 i < ARRAY_SIZE (bdesc_pcmpestr);
21342 if (d->code == fcode)
21343 return ix86_expand_sse_pcmpestr (d, exp, target);
21345 for (i = 0, d = bdesc_pcmpistr;
21346 i < ARRAY_SIZE (bdesc_pcmpistr);
21348 if (d->code == fcode)
21349 return ix86_expand_sse_pcmpistr (d, exp, target);
21351 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21352 if (d->code == fcode)
21353 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
21354 (enum multi_arg_type)d->flag,
21357 gcc_unreachable ();
21360 /* Returns a function decl for a vectorized version of the builtin function
21361 with builtin function code FN and the result vector type TYPE, or NULL_TREE
21362 if it is not available. */
21365 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
21368 enum machine_mode in_mode, out_mode;
21371 if (TREE_CODE (type_out) != VECTOR_TYPE
21372 || TREE_CODE (type_in) != VECTOR_TYPE)
21375 out_mode = TYPE_MODE (TREE_TYPE (type_out));
21376 out_n = TYPE_VECTOR_SUBPARTS (type_out);
21377 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21378 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21382 case BUILT_IN_SQRT:
21383 if (out_mode == DFmode && out_n == 2
21384 && in_mode == DFmode && in_n == 2)
21385 return ix86_builtins[IX86_BUILTIN_SQRTPD];
21388 case BUILT_IN_SQRTF:
21389 if (out_mode == SFmode && out_n == 4
21390 && in_mode == SFmode && in_n == 4)
21391 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
21394 case BUILT_IN_LRINT:
21395 if (out_mode == SImode && out_n == 4
21396 && in_mode == DFmode && in_n == 2)
21397 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
21400 case BUILT_IN_LRINTF:
21401 if (out_mode == SImode && out_n == 4
21402 && in_mode == SFmode && in_n == 4)
21403 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
21410 /* Dispatch to a handler for a vectorization library. */
21411 if (ix86_veclib_handler)
21412 return (*ix86_veclib_handler)(fn, type_out, type_in);
21417 /* Handler for an ACML-style interface to a library with vectorized
21421 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
21423 char name[20] = "__vr.._";
21424 tree fntype, new_fndecl, args;
21427 enum machine_mode el_mode, in_mode;
21430 /* The ACML is 64bits only and suitable for unsafe math only as
21431 it does not correctly support parts of IEEE with the required
21432 precision such as denormals. */
21434 || !flag_unsafe_math_optimizations)
21437 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21438 n = TYPE_VECTOR_SUBPARTS (type_out);
21439 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21440 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21441 if (el_mode != in_mode
21451 case BUILT_IN_LOG2:
21452 case BUILT_IN_LOG10:
21455 if (el_mode != DFmode
21460 case BUILT_IN_SINF:
21461 case BUILT_IN_COSF:
21462 case BUILT_IN_EXPF:
21463 case BUILT_IN_POWF:
21464 case BUILT_IN_LOGF:
21465 case BUILT_IN_LOG2F:
21466 case BUILT_IN_LOG10F:
21469 if (el_mode != SFmode
21478 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21479 sprintf (name + 7, "%s", bname+10);
21482 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21483 args = TREE_CHAIN (args))
21487 fntype = build_function_type_list (type_out, type_in, NULL);
21489 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21491 /* Build a function declaration for the vectorized function. */
21492 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21493 TREE_PUBLIC (new_fndecl) = 1;
21494 DECL_EXTERNAL (new_fndecl) = 1;
21495 DECL_IS_NOVOPS (new_fndecl) = 1;
21496 TREE_READONLY (new_fndecl) = 1;
21502 /* Returns a decl of a function that implements conversion of the
21503 input vector of type TYPE, or NULL_TREE if it is not available. */
21506 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
21508 if (TREE_CODE (type) != VECTOR_TYPE)
21514 switch (TYPE_MODE (type))
21517 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
21522 case FIX_TRUNC_EXPR:
21523 switch (TYPE_MODE (type))
21526 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
21536 /* Returns a code for a target-specific builtin that implements
21537 reciprocal of the function, or NULL_TREE if not available. */
21540 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
21541 bool sqrt ATTRIBUTE_UNUSED)
21543 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
21544 && flag_finite_math_only && !flag_trapping_math
21545 && flag_unsafe_math_optimizations))
21549 /* Machine dependent builtins. */
21552 /* Vectorized version of sqrt to rsqrt conversion. */
21553 case IX86_BUILTIN_SQRTPS_NR:
21554 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
21560 /* Normal builtins. */
21563 /* Sqrt to rsqrt conversion. */
21564 case BUILT_IN_SQRTF:
21565 return ix86_builtins[IX86_BUILTIN_RSQRTF];
21572 /* Store OPERAND to the memory after reload is completed. This means
21573 that we can't easily use assign_stack_local. */
21575 ix86_force_to_memory (enum machine_mode mode, rtx operand)
21579 gcc_assert (reload_completed);
21580 if (TARGET_RED_ZONE)
21582 result = gen_rtx_MEM (mode,
21583 gen_rtx_PLUS (Pmode,
21585 GEN_INT (-RED_ZONE_SIZE)));
21586 emit_move_insn (result, operand);
21588 else if (!TARGET_RED_ZONE && TARGET_64BIT)
21594 operand = gen_lowpart (DImode, operand);
21598 gen_rtx_SET (VOIDmode,
21599 gen_rtx_MEM (DImode,
21600 gen_rtx_PRE_DEC (DImode,
21601 stack_pointer_rtx)),
21605 gcc_unreachable ();
21607 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21616 split_di (&operand, 1, operands, operands + 1);
21618 gen_rtx_SET (VOIDmode,
21619 gen_rtx_MEM (SImode,
21620 gen_rtx_PRE_DEC (Pmode,
21621 stack_pointer_rtx)),
21624 gen_rtx_SET (VOIDmode,
21625 gen_rtx_MEM (SImode,
21626 gen_rtx_PRE_DEC (Pmode,
21627 stack_pointer_rtx)),
21632 /* Store HImodes as SImodes. */
21633 operand = gen_lowpart (SImode, operand);
21637 gen_rtx_SET (VOIDmode,
21638 gen_rtx_MEM (GET_MODE (operand),
21639 gen_rtx_PRE_DEC (SImode,
21640 stack_pointer_rtx)),
21644 gcc_unreachable ();
21646 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21651 /* Free operand from the memory. */
21653 ix86_free_from_memory (enum machine_mode mode)
21655 if (!TARGET_RED_ZONE)
21659 if (mode == DImode || TARGET_64BIT)
21663 /* Use LEA to deallocate stack space. In peephole2 it will be converted
21664 to pop or add instruction if registers are available. */
21665 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
21666 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21671 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
21672 QImode must go into class Q_REGS.
21673 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
21674 movdf to do mem-to-mem moves through integer regs. */
21676 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
21678 enum machine_mode mode = GET_MODE (x);
21680 /* We're only allowed to return a subclass of CLASS. Many of the
21681 following checks fail for NO_REGS, so eliminate that early. */
21682 if (regclass == NO_REGS)
21685 /* All classes can load zeros. */
21686 if (x == CONST0_RTX (mode))
21689 /* Force constants into memory if we are loading a (nonzero) constant into
21690 an MMX or SSE register. This is because there are no MMX/SSE instructions
21691 to load from a constant. */
21693 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
21696 /* Prefer SSE regs only, if we can use them for math. */
21697 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
21698 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
21700 /* Floating-point constants need more complex checks. */
21701 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
21703 /* General regs can load everything. */
21704 if (reg_class_subset_p (regclass, GENERAL_REGS))
21707 /* Floats can load 0 and 1 plus some others. Note that we eliminated
21708 zero above. We only want to wind up preferring 80387 registers if
21709 we plan on doing computation with them. */
21711 && standard_80387_constant_p (x))
21713 /* Limit class to non-sse. */
21714 if (regclass == FLOAT_SSE_REGS)
21716 if (regclass == FP_TOP_SSE_REGS)
21718 if (regclass == FP_SECOND_SSE_REGS)
21719 return FP_SECOND_REG;
21720 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
21727 /* Generally when we see PLUS here, it's the function invariant
21728 (plus soft-fp const_int). Which can only be computed into general
21730 if (GET_CODE (x) == PLUS)
21731 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
21733 /* QImode constants are easy to load, but non-constant QImode data
21734 must go into Q_REGS. */
21735 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
21737 if (reg_class_subset_p (regclass, Q_REGS))
21739 if (reg_class_subset_p (Q_REGS, regclass))
21747 /* Discourage putting floating-point values in SSE registers unless
21748 SSE math is being used, and likewise for the 387 registers. */
21750 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
21752 enum machine_mode mode = GET_MODE (x);
21754 /* Restrict the output reload class to the register bank that we are doing
21755 math on. If we would like not to return a subset of CLASS, reject this
21756 alternative: if reload cannot do this, it will still use its choice. */
21757 mode = GET_MODE (x);
21758 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
21759 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
21761 if (X87_FLOAT_MODE_P (mode))
21763 if (regclass == FP_TOP_SSE_REGS)
21765 else if (regclass == FP_SECOND_SSE_REGS)
21766 return FP_SECOND_REG;
21768 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
21774 /* If we are copying between general and FP registers, we need a memory
21775 location. The same is true for SSE and MMX registers.
21777 To optimize register_move_cost performance, allow inline variant.
21779 The macro can't work reliably when one of the CLASSES is class containing
21780 registers from multiple units (SSE, MMX, integer). We avoid this by never
21781 combining those units in single alternative in the machine description.
21782 Ensure that this constraint holds to avoid unexpected surprises.
21784 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
21785 enforce these sanity checks. */
21788 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21789 enum machine_mode mode, int strict)
21791 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
21792 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
21793 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
21794 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
21795 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
21796 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
21798 gcc_assert (!strict);
21802 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
21805 /* ??? This is a lie. We do have moves between mmx/general, and for
21806 mmx/sse2. But by saying we need secondary memory we discourage the
21807 register allocator from using the mmx registers unless needed. */
21808 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
21811 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
21813 /* SSE1 doesn't have any direct moves from other classes. */
21817 /* If the target says that inter-unit moves are more expensive
21818 than moving through memory, then don't generate them. */
21819 if (!TARGET_INTER_UNIT_MOVES)
21822 /* Between SSE and general, we have moves no larger than word size. */
21823 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
21831 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21832 enum machine_mode mode, int strict)
21834 return inline_secondary_memory_needed (class1, class2, mode, strict);
21837 /* Return true if the registers in CLASS cannot represent the change from
21838 modes FROM to TO. */
21841 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
21842 enum reg_class regclass)
21847 /* x87 registers can't do subreg at all, as all values are reformatted
21848 to extended precision. */
21849 if (MAYBE_FLOAT_CLASS_P (regclass))
21852 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
21854 /* Vector registers do not support QI or HImode loads. If we don't
21855 disallow a change to these modes, reload will assume it's ok to
21856 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
21857 the vec_dupv4hi pattern. */
21858 if (GET_MODE_SIZE (from) < 4)
21861 /* Vector registers do not support subreg with nonzero offsets, which
21862 are otherwise valid for integer registers. Since we can't see
21863 whether we have a nonzero offset from here, prohibit all
21864 nonparadoxical subregs changing size. */
21865 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
21872 /* Return the cost of moving data of mode M between a
21873 register and memory. A value of 2 is the default; this cost is
21874 relative to those in `REGISTER_MOVE_COST'.
21876 This function is used extensively by register_move_cost that is used to
21877 build tables at startup. Make it inline in this case.
21878 When IN is 2, return maximum of in and out move cost.
21880 If moving between registers and memory is more expensive than
21881 between two registers, you should define this macro to express the
21884 Model also increased moving costs of QImode registers in non
21888 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
21892 if (FLOAT_CLASS_P (regclass))
21910 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
21911 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
21913 if (SSE_CLASS_P (regclass))
21916 switch (GET_MODE_SIZE (mode))
21931 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
21932 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
21934 if (MMX_CLASS_P (regclass))
21937 switch (GET_MODE_SIZE (mode))
21949 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
21950 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
21952 switch (GET_MODE_SIZE (mode))
21955 if (Q_CLASS_P (regclass) || TARGET_64BIT)
21958 return ix86_cost->int_store[0];
21959 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
21960 cost = ix86_cost->movzbl_load;
21962 cost = ix86_cost->int_load[0];
21964 return MAX (cost, ix86_cost->int_store[0]);
21970 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
21972 return ix86_cost->movzbl_load;
21974 return ix86_cost->int_store[0] + 4;
21979 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
21980 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
21982 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
21983 if (mode == TFmode)
21986 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
21988 cost = ix86_cost->int_load[2];
21990 cost = ix86_cost->int_store[2];
21991 return (cost * (((int) GET_MODE_SIZE (mode)
21992 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
21997 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
21999 return inline_memory_move_cost (mode, regclass, in);
22003 /* Return the cost of moving data from a register in class CLASS1 to
22004 one in class CLASS2.
22006 It is not required that the cost always equal 2 when FROM is the same as TO;
22007 on some machines it is expensive to move between registers if they are not
22008 general registers. */
22011 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
22012 enum reg_class class2)
22014 /* In case we require secondary memory, compute cost of the store followed
22015 by load. In order to avoid bad register allocation choices, we need
22016 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
22018 if (inline_secondary_memory_needed (class1, class2, mode, 0))
22022 cost += inline_memory_move_cost (mode, class1, 2);
22023 cost += inline_memory_move_cost (mode, class2, 2);
22025 /* In case of copying from general_purpose_register we may emit multiple
22026 stores followed by single load causing memory size mismatch stall.
22027 Count this as arbitrarily high cost of 20. */
22028 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
22031 /* In the case of FP/MMX moves, the registers actually overlap, and we
22032 have to switch modes in order to treat them differently. */
22033 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
22034 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
22040 /* Moves between SSE/MMX and integer unit are expensive. */
22041 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
22042 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22044 /* ??? By keeping returned value relatively high, we limit the number
22045 of moves between integer and MMX/SSE registers for all targets.
22046 Additionally, high value prevents problem with x86_modes_tieable_p(),
22047 where integer modes in MMX/SSE registers are not tieable
22048 because of missing QImode and HImode moves to, from or between
22049 MMX/SSE registers. */
22050 return MAX (8, ix86_cost->mmxsse_to_integer);
22052 if (MAYBE_FLOAT_CLASS_P (class1))
22053 return ix86_cost->fp_move;
22054 if (MAYBE_SSE_CLASS_P (class1))
22055 return ix86_cost->sse_move;
22056 if (MAYBE_MMX_CLASS_P (class1))
22057 return ix86_cost->mmx_move;
22061 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
22064 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
22066 /* Flags and only flags can only hold CCmode values. */
22067 if (CC_REGNO_P (regno))
22068 return GET_MODE_CLASS (mode) == MODE_CC;
22069 if (GET_MODE_CLASS (mode) == MODE_CC
22070 || GET_MODE_CLASS (mode) == MODE_RANDOM
22071 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
22073 if (FP_REGNO_P (regno))
22074 return VALID_FP_MODE_P (mode);
22075 if (SSE_REGNO_P (regno))
22077 /* We implement the move patterns for all vector modes into and
22078 out of SSE registers, even when no operation instructions
22080 return (VALID_SSE_REG_MODE (mode)
22081 || VALID_SSE2_REG_MODE (mode)
22082 || VALID_MMX_REG_MODE (mode)
22083 || VALID_MMX_REG_MODE_3DNOW (mode));
22085 if (MMX_REGNO_P (regno))
22087 /* We implement the move patterns for 3DNOW modes even in MMX mode,
22088 so if the register is available at all, then we can move data of
22089 the given mode into or out of it. */
22090 return (VALID_MMX_REG_MODE (mode)
22091 || VALID_MMX_REG_MODE_3DNOW (mode));
22094 if (mode == QImode)
22096 /* Take care for QImode values - they can be in non-QI regs,
22097 but then they do cause partial register stalls. */
22098 if (regno < 4 || TARGET_64BIT)
22100 if (!TARGET_PARTIAL_REG_STALL)
22102 return reload_in_progress || reload_completed;
22104 /* We handle both integer and floats in the general purpose registers. */
22105 else if (VALID_INT_MODE_P (mode))
22107 else if (VALID_FP_MODE_P (mode))
22109 else if (VALID_DFP_MODE_P (mode))
22111 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
22112 on to use that value in smaller contexts, this can easily force a
22113 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
22114 supporting DImode, allow it. */
22115 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
22121 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
22122 tieable integer mode. */
22125 ix86_tieable_integer_mode_p (enum machine_mode mode)
22134 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
22137 return TARGET_64BIT;
22144 /* Return true if MODE1 is accessible in a register that can hold MODE2
22145 without copying. That is, all register classes that can hold MODE2
22146 can also hold MODE1. */
22149 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
22151 if (mode1 == mode2)
22154 if (ix86_tieable_integer_mode_p (mode1)
22155 && ix86_tieable_integer_mode_p (mode2))
22158 /* MODE2 being XFmode implies fp stack or general regs, which means we
22159 can tie any smaller floating point modes to it. Note that we do not
22160 tie this with TFmode. */
22161 if (mode2 == XFmode)
22162 return mode1 == SFmode || mode1 == DFmode;
22164 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
22165 that we can tie it with SFmode. */
22166 if (mode2 == DFmode)
22167 return mode1 == SFmode;
22169 /* If MODE2 is only appropriate for an SSE register, then tie with
22170 any other mode acceptable to SSE registers. */
22171 if (GET_MODE_SIZE (mode2) == 16
22172 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
22173 return (GET_MODE_SIZE (mode1) == 16
22174 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
22176 /* If MODE2 is appropriate for an MMX register, then tie
22177 with any other mode acceptable to MMX registers. */
22178 if (GET_MODE_SIZE (mode2) == 8
22179 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
22180 return (GET_MODE_SIZE (mode1) == 8
22181 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
22186 /* Compute a (partial) cost for rtx X. Return true if the complete
22187 cost has been computed, and false if subexpressions should be
22188 scanned. In either case, *TOTAL contains the cost result. */
22191 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
22193 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
22194 enum machine_mode mode = GET_MODE (x);
22202 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
22204 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
22206 else if (flag_pic && SYMBOLIC_CONST (x)
22208 || (!GET_CODE (x) != LABEL_REF
22209 && (GET_CODE (x) != SYMBOL_REF
22210 || !SYMBOL_REF_LOCAL_P (x)))))
22217 if (mode == VOIDmode)
22220 switch (standard_80387_constant_p (x))
22225 default: /* Other constants */
22230 /* Start with (MEM (SYMBOL_REF)), since that's where
22231 it'll probably end up. Add a penalty for size. */
22232 *total = (COSTS_N_INSNS (1)
22233 + (flag_pic != 0 && !TARGET_64BIT)
22234 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
22240 /* The zero extensions is often completely free on x86_64, so make
22241 it as cheap as possible. */
22242 if (TARGET_64BIT && mode == DImode
22243 && GET_MODE (XEXP (x, 0)) == SImode)
22245 else if (TARGET_ZERO_EXTEND_WITH_AND)
22246 *total = ix86_cost->add;
22248 *total = ix86_cost->movzx;
22252 *total = ix86_cost->movsx;
22256 if (CONST_INT_P (XEXP (x, 1))
22257 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
22259 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22262 *total = ix86_cost->add;
22265 if ((value == 2 || value == 3)
22266 && ix86_cost->lea <= ix86_cost->shift_const)
22268 *total = ix86_cost->lea;
22278 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
22280 if (CONST_INT_P (XEXP (x, 1)))
22282 if (INTVAL (XEXP (x, 1)) > 32)
22283 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
22285 *total = ix86_cost->shift_const * 2;
22289 if (GET_CODE (XEXP (x, 1)) == AND)
22290 *total = ix86_cost->shift_var * 2;
22292 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
22297 if (CONST_INT_P (XEXP (x, 1)))
22298 *total = ix86_cost->shift_const;
22300 *total = ix86_cost->shift_var;
22305 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22307 /* ??? SSE scalar cost should be used here. */
22308 *total = ix86_cost->fmul;
22311 else if (X87_FLOAT_MODE_P (mode))
22313 *total = ix86_cost->fmul;
22316 else if (FLOAT_MODE_P (mode))
22318 /* ??? SSE vector cost should be used here. */
22319 *total = ix86_cost->fmul;
22324 rtx op0 = XEXP (x, 0);
22325 rtx op1 = XEXP (x, 1);
22327 if (CONST_INT_P (XEXP (x, 1)))
22329 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22330 for (nbits = 0; value != 0; value &= value - 1)
22334 /* This is arbitrary. */
22337 /* Compute costs correctly for widening multiplication. */
22338 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
22339 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
22340 == GET_MODE_SIZE (mode))
22342 int is_mulwiden = 0;
22343 enum machine_mode inner_mode = GET_MODE (op0);
22345 if (GET_CODE (op0) == GET_CODE (op1))
22346 is_mulwiden = 1, op1 = XEXP (op1, 0);
22347 else if (CONST_INT_P (op1))
22349 if (GET_CODE (op0) == SIGN_EXTEND)
22350 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
22353 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
22357 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
22360 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
22361 + nbits * ix86_cost->mult_bit
22362 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
22371 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22372 /* ??? SSE cost should be used here. */
22373 *total = ix86_cost->fdiv;
22374 else if (X87_FLOAT_MODE_P (mode))
22375 *total = ix86_cost->fdiv;
22376 else if (FLOAT_MODE_P (mode))
22377 /* ??? SSE vector cost should be used here. */
22378 *total = ix86_cost->fdiv;
22380 *total = ix86_cost->divide[MODE_INDEX (mode)];
22384 if (GET_MODE_CLASS (mode) == MODE_INT
22385 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
22387 if (GET_CODE (XEXP (x, 0)) == PLUS
22388 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
22389 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
22390 && CONSTANT_P (XEXP (x, 1)))
22392 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
22393 if (val == 2 || val == 4 || val == 8)
22395 *total = ix86_cost->lea;
22396 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22397 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
22399 *total += rtx_cost (XEXP (x, 1), outer_code);
22403 else if (GET_CODE (XEXP (x, 0)) == MULT
22404 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
22406 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
22407 if (val == 2 || val == 4 || val == 8)
22409 *total = ix86_cost->lea;
22410 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22411 *total += rtx_cost (XEXP (x, 1), outer_code);
22415 else if (GET_CODE (XEXP (x, 0)) == PLUS)
22417 *total = ix86_cost->lea;
22418 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22419 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22420 *total += rtx_cost (XEXP (x, 1), outer_code);
22427 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22429 /* ??? SSE cost should be used here. */
22430 *total = ix86_cost->fadd;
22433 else if (X87_FLOAT_MODE_P (mode))
22435 *total = ix86_cost->fadd;
22438 else if (FLOAT_MODE_P (mode))
22440 /* ??? SSE vector cost should be used here. */
22441 *total = ix86_cost->fadd;
22449 if (!TARGET_64BIT && mode == DImode)
22451 *total = (ix86_cost->add * 2
22452 + (rtx_cost (XEXP (x, 0), outer_code)
22453 << (GET_MODE (XEXP (x, 0)) != DImode))
22454 + (rtx_cost (XEXP (x, 1), outer_code)
22455 << (GET_MODE (XEXP (x, 1)) != DImode)));
22461 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22463 /* ??? SSE cost should be used here. */
22464 *total = ix86_cost->fchs;
22467 else if (X87_FLOAT_MODE_P (mode))
22469 *total = ix86_cost->fchs;
22472 else if (FLOAT_MODE_P (mode))
22474 /* ??? SSE vector cost should be used here. */
22475 *total = ix86_cost->fchs;
22481 if (!TARGET_64BIT && mode == DImode)
22482 *total = ix86_cost->add * 2;
22484 *total = ix86_cost->add;
22488 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
22489 && XEXP (XEXP (x, 0), 1) == const1_rtx
22490 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
22491 && XEXP (x, 1) == const0_rtx)
22493 /* This kind of construct is implemented using test[bwl].
22494 Treat it as if we had an AND. */
22495 *total = (ix86_cost->add
22496 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
22497 + rtx_cost (const1_rtx, outer_code));
22503 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
22508 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22509 /* ??? SSE cost should be used here. */
22510 *total = ix86_cost->fabs;
22511 else if (X87_FLOAT_MODE_P (mode))
22512 *total = ix86_cost->fabs;
22513 else if (FLOAT_MODE_P (mode))
22514 /* ??? SSE vector cost should be used here. */
22515 *total = ix86_cost->fabs;
22519 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22520 /* ??? SSE cost should be used here. */
22521 *total = ix86_cost->fsqrt;
22522 else if (X87_FLOAT_MODE_P (mode))
22523 *total = ix86_cost->fsqrt;
22524 else if (FLOAT_MODE_P (mode))
22525 /* ??? SSE vector cost should be used here. */
22526 *total = ix86_cost->fsqrt;
22530 if (XINT (x, 1) == UNSPEC_TP)
22541 static int current_machopic_label_num;
22543 /* Given a symbol name and its associated stub, write out the
22544 definition of the stub. */
22547 machopic_output_stub (FILE *file, const char *symb, const char *stub)
22549 unsigned int length;
22550 char *binder_name, *symbol_name, lazy_ptr_name[32];
22551 int label = ++current_machopic_label_num;
22553 /* For 64-bit we shouldn't get here. */
22554 gcc_assert (!TARGET_64BIT);
22556 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
22557 symb = (*targetm.strip_name_encoding) (symb);
22559 length = strlen (stub);
22560 binder_name = alloca (length + 32);
22561 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
22563 length = strlen (symb);
22564 symbol_name = alloca (length + 32);
22565 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
22567 sprintf (lazy_ptr_name, "L%d$lz", label);
22570 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
22572 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
22574 fprintf (file, "%s:\n", stub);
22575 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22579 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
22580 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
22581 fprintf (file, "\tjmp\t*%%edx\n");
22584 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
22586 fprintf (file, "%s:\n", binder_name);
22590 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
22591 fprintf (file, "\tpushl\t%%eax\n");
22594 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
22596 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
22598 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
22599 fprintf (file, "%s:\n", lazy_ptr_name);
22600 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22601 fprintf (file, "\t.long %s\n", binder_name);
22605 darwin_x86_file_end (void)
22607 darwin_file_end ();
22610 #endif /* TARGET_MACHO */
22612 /* Order the registers for register allocator. */
22615 x86_order_regs_for_local_alloc (void)
22620 /* First allocate the local general purpose registers. */
22621 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22622 if (GENERAL_REGNO_P (i) && call_used_regs[i])
22623 reg_alloc_order [pos++] = i;
22625 /* Global general purpose registers. */
22626 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22627 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
22628 reg_alloc_order [pos++] = i;
22630 /* x87 registers come first in case we are doing FP math
22632 if (!TARGET_SSE_MATH)
22633 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22634 reg_alloc_order [pos++] = i;
22636 /* SSE registers. */
22637 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
22638 reg_alloc_order [pos++] = i;
22639 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
22640 reg_alloc_order [pos++] = i;
22642 /* x87 registers. */
22643 if (TARGET_SSE_MATH)
22644 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22645 reg_alloc_order [pos++] = i;
22647 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
22648 reg_alloc_order [pos++] = i;
22650 /* Initialize the rest of array as we do not allocate some registers
22652 while (pos < FIRST_PSEUDO_REGISTER)
22653 reg_alloc_order [pos++] = 0;
22656 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
22657 struct attribute_spec.handler. */
22659 ix86_handle_struct_attribute (tree *node, tree name,
22660 tree args ATTRIBUTE_UNUSED,
22661 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
22664 if (DECL_P (*node))
22666 if (TREE_CODE (*node) == TYPE_DECL)
22667 type = &TREE_TYPE (*node);
22672 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
22673 || TREE_CODE (*type) == UNION_TYPE)))
22675 warning (OPT_Wattributes, "%qs attribute ignored",
22676 IDENTIFIER_POINTER (name));
22677 *no_add_attrs = true;
22680 else if ((is_attribute_p ("ms_struct", name)
22681 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
22682 || ((is_attribute_p ("gcc_struct", name)
22683 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
22685 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
22686 IDENTIFIER_POINTER (name));
22687 *no_add_attrs = true;
22694 ix86_ms_bitfield_layout_p (const_tree record_type)
22696 return (TARGET_MS_BITFIELD_LAYOUT &&
22697 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
22698 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
22701 /* Returns an expression indicating where the this parameter is
22702 located on entry to the FUNCTION. */
22705 x86_this_parameter (tree function)
22707 tree type = TREE_TYPE (function);
22708 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
22713 const int *parm_regs;
22715 if (TARGET_64BIT_MS_ABI)
22716 parm_regs = x86_64_ms_abi_int_parameter_registers;
22718 parm_regs = x86_64_int_parameter_registers;
22719 return gen_rtx_REG (DImode, parm_regs[aggr]);
22722 nregs = ix86_function_regparm (type, function);
22724 if (nregs > 0 && !stdarg_p (type))
22728 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
22729 regno = aggr ? DX_REG : CX_REG;
22737 return gen_rtx_MEM (SImode,
22738 plus_constant (stack_pointer_rtx, 4));
22741 return gen_rtx_REG (SImode, regno);
22744 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
22747 /* Determine whether x86_output_mi_thunk can succeed. */
22750 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
22751 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
22752 HOST_WIDE_INT vcall_offset, const_tree function)
22754 /* 64-bit can handle anything. */
22758 /* For 32-bit, everything's fine if we have one free register. */
22759 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
22762 /* Need a free register for vcall_offset. */
22766 /* Need a free register for GOT references. */
22767 if (flag_pic && !(*targetm.binds_local_p) (function))
22770 /* Otherwise ok. */
22774 /* Output the assembler code for a thunk function. THUNK_DECL is the
22775 declaration for the thunk function itself, FUNCTION is the decl for
22776 the target function. DELTA is an immediate constant offset to be
22777 added to THIS. If VCALL_OFFSET is nonzero, the word at
22778 *(*this + vcall_offset) should be added to THIS. */
22781 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
22782 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
22783 HOST_WIDE_INT vcall_offset, tree function)
22786 rtx this_param = x86_this_parameter (function);
22789 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
22790 pull it in now and let DELTA benefit. */
22791 if (REG_P (this_param))
22792 this_reg = this_param;
22793 else if (vcall_offset)
22795 /* Put the this parameter into %eax. */
22796 xops[0] = this_param;
22797 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
22798 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22801 this_reg = NULL_RTX;
22803 /* Adjust the this parameter by a fixed constant. */
22806 xops[0] = GEN_INT (delta);
22807 xops[1] = this_reg ? this_reg : this_param;
22810 if (!x86_64_general_operand (xops[0], DImode))
22812 tmp = gen_rtx_REG (DImode, R10_REG);
22814 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
22816 xops[1] = this_param;
22818 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22821 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22824 /* Adjust the this parameter by a value stored in the vtable. */
22828 tmp = gen_rtx_REG (DImode, R10_REG);
22831 int tmp_regno = CX_REG;
22832 if (lookup_attribute ("fastcall",
22833 TYPE_ATTRIBUTES (TREE_TYPE (function))))
22834 tmp_regno = AX_REG;
22835 tmp = gen_rtx_REG (SImode, tmp_regno);
22838 xops[0] = gen_rtx_MEM (Pmode, this_reg);
22841 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22843 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22845 /* Adjust the this parameter. */
22846 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
22847 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
22849 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
22850 xops[0] = GEN_INT (vcall_offset);
22852 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22853 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
22855 xops[1] = this_reg;
22857 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22859 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22862 /* If necessary, drop THIS back to its stack slot. */
22863 if (this_reg && this_reg != this_param)
22865 xops[0] = this_reg;
22866 xops[1] = this_param;
22867 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22870 xops[0] = XEXP (DECL_RTL (function), 0);
22873 if (!flag_pic || (*targetm.binds_local_p) (function))
22874 output_asm_insn ("jmp\t%P0", xops);
22875 /* All thunks should be in the same object as their target,
22876 and thus binds_local_p should be true. */
22877 else if (TARGET_64BIT_MS_ABI)
22878 gcc_unreachable ();
22881 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
22882 tmp = gen_rtx_CONST (Pmode, tmp);
22883 tmp = gen_rtx_MEM (QImode, tmp);
22885 output_asm_insn ("jmp\t%A0", xops);
22890 if (!flag_pic || (*targetm.binds_local_p) (function))
22891 output_asm_insn ("jmp\t%P0", xops);
22896 rtx sym_ref = XEXP (DECL_RTL (function), 0);
22897 tmp = (gen_rtx_SYMBOL_REF
22899 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
22900 tmp = gen_rtx_MEM (QImode, tmp);
22902 output_asm_insn ("jmp\t%0", xops);
22905 #endif /* TARGET_MACHO */
22907 tmp = gen_rtx_REG (SImode, CX_REG);
22908 output_set_got (tmp, NULL_RTX);
22911 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
22912 output_asm_insn ("jmp\t{*}%1", xops);
22918 x86_file_start (void)
22920 default_file_start ();
22922 darwin_file_start ();
22924 if (X86_FILE_START_VERSION_DIRECTIVE)
22925 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
22926 if (X86_FILE_START_FLTUSED)
22927 fputs ("\t.global\t__fltused\n", asm_out_file);
22928 if (ix86_asm_dialect == ASM_INTEL)
22929 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
22933 x86_field_alignment (tree field, int computed)
22935 enum machine_mode mode;
22936 tree type = TREE_TYPE (field);
22938 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
22940 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
22941 ? get_inner_array_type (type) : type);
22942 if (mode == DFmode || mode == DCmode
22943 || GET_MODE_CLASS (mode) == MODE_INT
22944 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
22945 return MIN (32, computed);
22949 /* Output assembler code to FILE to increment profiler label # LABELNO
22950 for profiling a function entry. */
22952 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
22956 #ifndef NO_PROFILE_COUNTERS
22957 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
22960 if (!TARGET_64BIT_MS_ABI && flag_pic)
22961 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
22963 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
22967 #ifndef NO_PROFILE_COUNTERS
22968 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
22969 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
22971 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
22975 #ifndef NO_PROFILE_COUNTERS
22976 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
22977 PROFILE_COUNT_REGISTER);
22979 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
22983 /* We don't have exact information about the insn sizes, but we may assume
22984 quite safely that we are informed about all 1 byte insns and memory
22985 address sizes. This is enough to eliminate unnecessary padding in
22989 min_insn_size (rtx insn)
22993 if (!INSN_P (insn) || !active_insn_p (insn))
22996 /* Discard alignments we've emit and jump instructions. */
22997 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
22998 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
23001 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
23002 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
23005 /* Important case - calls are always 5 bytes.
23006 It is common to have many calls in the row. */
23008 && symbolic_reference_mentioned_p (PATTERN (insn))
23009 && !SIBLING_CALL_P (insn))
23011 if (get_attr_length (insn) <= 1)
23014 /* For normal instructions we may rely on the sizes of addresses
23015 and the presence of symbol to require 4 bytes of encoding.
23016 This is not the case for jumps where references are PC relative. */
23017 if (!JUMP_P (insn))
23019 l = get_attr_length_address (insn);
23020 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
23029 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
23033 ix86_avoid_jump_misspredicts (void)
23035 rtx insn, start = get_insns ();
23036 int nbytes = 0, njumps = 0;
23039 /* Look for all minimal intervals of instructions containing 4 jumps.
23040 The intervals are bounded by START and INSN. NBYTES is the total
23041 size of instructions in the interval including INSN and not including
23042 START. When the NBYTES is smaller than 16 bytes, it is possible
23043 that the end of START and INSN ends up in the same 16byte page.
23045 The smallest offset in the page INSN can start is the case where START
23046 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
23047 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
23049 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
23052 nbytes += min_insn_size (insn);
23054 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
23055 INSN_UID (insn), min_insn_size (insn));
23057 && GET_CODE (PATTERN (insn)) != ADDR_VEC
23058 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
23066 start = NEXT_INSN (start);
23067 if ((JUMP_P (start)
23068 && GET_CODE (PATTERN (start)) != ADDR_VEC
23069 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
23071 njumps--, isjump = 1;
23074 nbytes -= min_insn_size (start);
23076 gcc_assert (njumps >= 0);
23078 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
23079 INSN_UID (start), INSN_UID (insn), nbytes);
23081 if (njumps == 3 && isjump && nbytes < 16)
23083 int padsize = 15 - nbytes + min_insn_size (insn);
23086 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
23087 INSN_UID (insn), padsize);
23088 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
23093 /* AMD Athlon works faster
23094 when RET is not destination of conditional jump or directly preceded
23095 by other jump instruction. We avoid the penalty by inserting NOP just
23096 before the RET instructions in such cases. */
23098 ix86_pad_returns (void)
23103 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
23105 basic_block bb = e->src;
23106 rtx ret = BB_END (bb);
23108 bool replace = false;
23110 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
23111 || !maybe_hot_bb_p (bb))
23113 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
23114 if (active_insn_p (prev) || LABEL_P (prev))
23116 if (prev && LABEL_P (prev))
23121 FOR_EACH_EDGE (e, ei, bb->preds)
23122 if (EDGE_FREQUENCY (e) && e->src->index >= 0
23123 && !(e->flags & EDGE_FALLTHRU))
23128 prev = prev_active_insn (ret);
23130 && ((JUMP_P (prev) && any_condjump_p (prev))
23133 /* Empty functions get branch mispredict even when the jump destination
23134 is not visible to us. */
23135 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
23140 emit_insn_before (gen_return_internal_long (), ret);
23146 /* Implement machine specific optimizations. We implement padding of returns
23147 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
23151 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
23152 ix86_pad_returns ();
23153 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
23154 ix86_avoid_jump_misspredicts ();
23157 /* Return nonzero when QImode register that must be represented via REX prefix
23160 x86_extended_QIreg_mentioned_p (rtx insn)
23163 extract_insn_cached (insn);
23164 for (i = 0; i < recog_data.n_operands; i++)
23165 if (REG_P (recog_data.operand[i])
23166 && REGNO (recog_data.operand[i]) >= 4)
23171 /* Return nonzero when P points to register encoded via REX prefix.
23172 Called via for_each_rtx. */
23174 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
23176 unsigned int regno;
23179 regno = REGNO (*p);
23180 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
23183 /* Return true when INSN mentions register that must be encoded using REX
23186 x86_extended_reg_mentioned_p (rtx insn)
23188 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
23191 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
23192 optabs would emit if we didn't have TFmode patterns. */
23195 x86_emit_floatuns (rtx operands[2])
23197 rtx neglab, donelab, i0, i1, f0, in, out;
23198 enum machine_mode mode, inmode;
23200 inmode = GET_MODE (operands[1]);
23201 gcc_assert (inmode == SImode || inmode == DImode);
23204 in = force_reg (inmode, operands[1]);
23205 mode = GET_MODE (out);
23206 neglab = gen_label_rtx ();
23207 donelab = gen_label_rtx ();
23208 f0 = gen_reg_rtx (mode);
23210 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
23212 expand_float (out, in, 0);
23214 emit_jump_insn (gen_jump (donelab));
23217 emit_label (neglab);
23219 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
23221 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
23223 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
23225 expand_float (f0, i0, 0);
23227 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
23229 emit_label (donelab);
23232 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23233 with all elements equal to VAR. Return true if successful. */
23236 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
23237 rtx target, rtx val)
23239 enum machine_mode smode, wsmode, wvmode;
23254 val = force_reg (GET_MODE_INNER (mode), val);
23255 x = gen_rtx_VEC_DUPLICATE (mode, val);
23256 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23262 if (TARGET_SSE || TARGET_3DNOW_A)
23264 val = gen_lowpart (SImode, val);
23265 x = gen_rtx_TRUNCATE (HImode, val);
23266 x = gen_rtx_VEC_DUPLICATE (mode, x);
23267 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23289 /* Extend HImode to SImode using a paradoxical SUBREG. */
23290 tmp1 = gen_reg_rtx (SImode);
23291 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23292 /* Insert the SImode value as low element of V4SImode vector. */
23293 tmp2 = gen_reg_rtx (V4SImode);
23294 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23295 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23296 CONST0_RTX (V4SImode),
23298 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23299 /* Cast the V4SImode vector back to a V8HImode vector. */
23300 tmp1 = gen_reg_rtx (V8HImode);
23301 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
23302 /* Duplicate the low short through the whole low SImode word. */
23303 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
23304 /* Cast the V8HImode vector back to a V4SImode vector. */
23305 tmp2 = gen_reg_rtx (V4SImode);
23306 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23307 /* Replicate the low element of the V4SImode vector. */
23308 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23309 /* Cast the V2SImode back to V8HImode, and store in target. */
23310 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
23321 /* Extend QImode to SImode using a paradoxical SUBREG. */
23322 tmp1 = gen_reg_rtx (SImode);
23323 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23324 /* Insert the SImode value as low element of V4SImode vector. */
23325 tmp2 = gen_reg_rtx (V4SImode);
23326 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23327 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23328 CONST0_RTX (V4SImode),
23330 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23331 /* Cast the V4SImode vector back to a V16QImode vector. */
23332 tmp1 = gen_reg_rtx (V16QImode);
23333 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
23334 /* Duplicate the low byte through the whole low SImode word. */
23335 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23336 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23337 /* Cast the V16QImode vector back to a V4SImode vector. */
23338 tmp2 = gen_reg_rtx (V4SImode);
23339 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23340 /* Replicate the low element of the V4SImode vector. */
23341 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23342 /* Cast the V2SImode back to V16QImode, and store in target. */
23343 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
23351 /* Replicate the value once into the next wider mode and recurse. */
23352 val = convert_modes (wsmode, smode, val, true);
23353 x = expand_simple_binop (wsmode, ASHIFT, val,
23354 GEN_INT (GET_MODE_BITSIZE (smode)),
23355 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23356 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
23358 x = gen_reg_rtx (wvmode);
23359 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
23360 gcc_unreachable ();
23361 emit_move_insn (target, gen_lowpart (mode, x));
23369 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23370 whose ONE_VAR element is VAR, and other elements are zero. Return true
23374 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
23375 rtx target, rtx var, int one_var)
23377 enum machine_mode vsimode;
23393 var = force_reg (GET_MODE_INNER (mode), var);
23394 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
23395 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23400 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
23401 new_target = gen_reg_rtx (mode);
23403 new_target = target;
23404 var = force_reg (GET_MODE_INNER (mode), var);
23405 x = gen_rtx_VEC_DUPLICATE (mode, var);
23406 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
23407 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
23410 /* We need to shuffle the value to the correct position, so
23411 create a new pseudo to store the intermediate result. */
23413 /* With SSE2, we can use the integer shuffle insns. */
23414 if (mode != V4SFmode && TARGET_SSE2)
23416 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
23418 GEN_INT (one_var == 1 ? 0 : 1),
23419 GEN_INT (one_var == 2 ? 0 : 1),
23420 GEN_INT (one_var == 3 ? 0 : 1)));
23421 if (target != new_target)
23422 emit_move_insn (target, new_target);
23426 /* Otherwise convert the intermediate result to V4SFmode and
23427 use the SSE1 shuffle instructions. */
23428 if (mode != V4SFmode)
23430 tmp = gen_reg_rtx (V4SFmode);
23431 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
23436 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
23438 GEN_INT (one_var == 1 ? 0 : 1),
23439 GEN_INT (one_var == 2 ? 0+4 : 1+4),
23440 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
23442 if (mode != V4SFmode)
23443 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
23444 else if (tmp != target)
23445 emit_move_insn (target, tmp);
23447 else if (target != new_target)
23448 emit_move_insn (target, new_target);
23453 vsimode = V4SImode;
23459 vsimode = V2SImode;
23465 /* Zero extend the variable element to SImode and recurse. */
23466 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
23468 x = gen_reg_rtx (vsimode);
23469 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
23471 gcc_unreachable ();
23473 emit_move_insn (target, gen_lowpart (mode, x));
23481 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23482 consisting of the values in VALS. It is known that all elements
23483 except ONE_VAR are constants. Return true if successful. */
23486 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
23487 rtx target, rtx vals, int one_var)
23489 rtx var = XVECEXP (vals, 0, one_var);
23490 enum machine_mode wmode;
23493 const_vec = copy_rtx (vals);
23494 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
23495 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
23503 /* For the two element vectors, it's just as easy to use
23504 the general case. */
23520 /* There's no way to set one QImode entry easily. Combine
23521 the variable value with its adjacent constant value, and
23522 promote to an HImode set. */
23523 x = XVECEXP (vals, 0, one_var ^ 1);
23526 var = convert_modes (HImode, QImode, var, true);
23527 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
23528 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23529 x = GEN_INT (INTVAL (x) & 0xff);
23533 var = convert_modes (HImode, QImode, var, true);
23534 x = gen_int_mode (INTVAL (x) << 8, HImode);
23536 if (x != const0_rtx)
23537 var = expand_simple_binop (HImode, IOR, var, x, var,
23538 1, OPTAB_LIB_WIDEN);
23540 x = gen_reg_rtx (wmode);
23541 emit_move_insn (x, gen_lowpart (wmode, const_vec));
23542 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
23544 emit_move_insn (target, gen_lowpart (mode, x));
23551 emit_move_insn (target, const_vec);
23552 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23556 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
23557 all values variable, and none identical. */
23560 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
23561 rtx target, rtx vals)
23563 enum machine_mode half_mode = GET_MODE_INNER (mode);
23564 rtx op0 = NULL, op1 = NULL;
23565 bool use_vec_concat = false;
23571 if (!mmx_ok && !TARGET_SSE)
23577 /* For the two element vectors, we always implement VEC_CONCAT. */
23578 op0 = XVECEXP (vals, 0, 0);
23579 op1 = XVECEXP (vals, 0, 1);
23580 use_vec_concat = true;
23584 half_mode = V2SFmode;
23587 half_mode = V2SImode;
23593 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
23594 Recurse to load the two halves. */
23596 op0 = gen_reg_rtx (half_mode);
23597 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
23598 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
23600 op1 = gen_reg_rtx (half_mode);
23601 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
23602 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
23604 use_vec_concat = true;
23615 gcc_unreachable ();
23618 if (use_vec_concat)
23620 if (!register_operand (op0, half_mode))
23621 op0 = force_reg (half_mode, op0);
23622 if (!register_operand (op1, half_mode))
23623 op1 = force_reg (half_mode, op1);
23625 emit_insn (gen_rtx_SET (VOIDmode, target,
23626 gen_rtx_VEC_CONCAT (mode, op0, op1)));
23630 int i, j, n_elts, n_words, n_elt_per_word;
23631 enum machine_mode inner_mode;
23632 rtx words[4], shift;
23634 inner_mode = GET_MODE_INNER (mode);
23635 n_elts = GET_MODE_NUNITS (mode);
23636 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
23637 n_elt_per_word = n_elts / n_words;
23638 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
23640 for (i = 0; i < n_words; ++i)
23642 rtx word = NULL_RTX;
23644 for (j = 0; j < n_elt_per_word; ++j)
23646 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
23647 elt = convert_modes (word_mode, inner_mode, elt, true);
23653 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
23654 word, 1, OPTAB_LIB_WIDEN);
23655 word = expand_simple_binop (word_mode, IOR, word, elt,
23656 word, 1, OPTAB_LIB_WIDEN);
23664 emit_move_insn (target, gen_lowpart (mode, words[0]));
23665 else if (n_words == 2)
23667 rtx tmp = gen_reg_rtx (mode);
23668 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
23669 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
23670 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
23671 emit_move_insn (target, tmp);
23673 else if (n_words == 4)
23675 rtx tmp = gen_reg_rtx (V4SImode);
23676 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
23677 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
23678 emit_move_insn (target, gen_lowpart (mode, tmp));
23681 gcc_unreachable ();
23685 /* Initialize vector TARGET via VALS. Suppress the use of MMX
23686 instructions unless MMX_OK is true. */
23689 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
23691 enum machine_mode mode = GET_MODE (target);
23692 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23693 int n_elts = GET_MODE_NUNITS (mode);
23694 int n_var = 0, one_var = -1;
23695 bool all_same = true, all_const_zero = true;
23699 for (i = 0; i < n_elts; ++i)
23701 x = XVECEXP (vals, 0, i);
23702 if (!(CONST_INT_P (x)
23703 || GET_CODE (x) == CONST_DOUBLE
23704 || GET_CODE (x) == CONST_FIXED))
23705 n_var++, one_var = i;
23706 else if (x != CONST0_RTX (inner_mode))
23707 all_const_zero = false;
23708 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
23712 /* Constants are best loaded from the constant pool. */
23715 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
23719 /* If all values are identical, broadcast the value. */
23721 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
23722 XVECEXP (vals, 0, 0)))
23725 /* Values where only one field is non-constant are best loaded from
23726 the pool and overwritten via move later. */
23730 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
23731 XVECEXP (vals, 0, one_var),
23735 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
23739 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
23743 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
23745 enum machine_mode mode = GET_MODE (target);
23746 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23747 bool use_vec_merge = false;
23756 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
23757 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
23759 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
23761 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
23762 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23768 use_vec_merge = TARGET_SSE4_1;
23776 /* For the two element vectors, we implement a VEC_CONCAT with
23777 the extraction of the other element. */
23779 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
23780 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
23783 op0 = val, op1 = tmp;
23785 op0 = tmp, op1 = val;
23787 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
23788 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23793 use_vec_merge = TARGET_SSE4_1;
23800 use_vec_merge = true;
23804 /* tmp = target = A B C D */
23805 tmp = copy_to_reg (target);
23806 /* target = A A B B */
23807 emit_insn (gen_sse_unpcklps (target, target, target));
23808 /* target = X A B B */
23809 ix86_expand_vector_set (false, target, val, 0);
23810 /* target = A X C D */
23811 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23812 GEN_INT (1), GEN_INT (0),
23813 GEN_INT (2+4), GEN_INT (3+4)));
23817 /* tmp = target = A B C D */
23818 tmp = copy_to_reg (target);
23819 /* tmp = X B C D */
23820 ix86_expand_vector_set (false, tmp, val, 0);
23821 /* target = A B X D */
23822 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23823 GEN_INT (0), GEN_INT (1),
23824 GEN_INT (0+4), GEN_INT (3+4)));
23828 /* tmp = target = A B C D */
23829 tmp = copy_to_reg (target);
23830 /* tmp = X B C D */
23831 ix86_expand_vector_set (false, tmp, val, 0);
23832 /* target = A B X D */
23833 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23834 GEN_INT (0), GEN_INT (1),
23835 GEN_INT (2+4), GEN_INT (0+4)));
23839 gcc_unreachable ();
23844 use_vec_merge = TARGET_SSE4_1;
23848 /* Element 0 handled by vec_merge below. */
23851 use_vec_merge = true;
23857 /* With SSE2, use integer shuffles to swap element 0 and ELT,
23858 store into element 0, then shuffle them back. */
23862 order[0] = GEN_INT (elt);
23863 order[1] = const1_rtx;
23864 order[2] = const2_rtx;
23865 order[3] = GEN_INT (3);
23866 order[elt] = const0_rtx;
23868 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23869 order[1], order[2], order[3]));
23871 ix86_expand_vector_set (false, target, val, 0);
23873 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23874 order[1], order[2], order[3]));
23878 /* For SSE1, we have to reuse the V4SF code. */
23879 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
23880 gen_lowpart (SFmode, val), elt);
23885 use_vec_merge = TARGET_SSE2;
23888 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
23892 use_vec_merge = TARGET_SSE4_1;
23902 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
23903 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
23904 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23908 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
23910 emit_move_insn (mem, target);
23912 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
23913 emit_move_insn (tmp, val);
23915 emit_move_insn (target, mem);
23920 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
23922 enum machine_mode mode = GET_MODE (vec);
23923 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23924 bool use_vec_extr = false;
23937 use_vec_extr = true;
23941 use_vec_extr = TARGET_SSE4_1;
23953 tmp = gen_reg_rtx (mode);
23954 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
23955 GEN_INT (elt), GEN_INT (elt),
23956 GEN_INT (elt+4), GEN_INT (elt+4)));
23960 tmp = gen_reg_rtx (mode);
23961 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
23965 gcc_unreachable ();
23968 use_vec_extr = true;
23973 use_vec_extr = TARGET_SSE4_1;
23987 tmp = gen_reg_rtx (mode);
23988 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
23989 GEN_INT (elt), GEN_INT (elt),
23990 GEN_INT (elt), GEN_INT (elt)));
23994 tmp = gen_reg_rtx (mode);
23995 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
23999 gcc_unreachable ();
24002 use_vec_extr = true;
24007 /* For SSE1, we have to reuse the V4SF code. */
24008 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
24009 gen_lowpart (V4SFmode, vec), elt);
24015 use_vec_extr = TARGET_SSE2;
24018 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24022 use_vec_extr = TARGET_SSE4_1;
24026 /* ??? Could extract the appropriate HImode element and shift. */
24033 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
24034 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
24036 /* Let the rtl optimizers know about the zero extension performed. */
24037 if (inner_mode == QImode || inner_mode == HImode)
24039 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
24040 target = gen_lowpart (SImode, target);
24043 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24047 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24049 emit_move_insn (mem, vec);
24051 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24052 emit_move_insn (target, tmp);
24056 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
24057 pattern to reduce; DEST is the destination; IN is the input vector. */
24060 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
24062 rtx tmp1, tmp2, tmp3;
24064 tmp1 = gen_reg_rtx (V4SFmode);
24065 tmp2 = gen_reg_rtx (V4SFmode);
24066 tmp3 = gen_reg_rtx (V4SFmode);
24068 emit_insn (gen_sse_movhlps (tmp1, in, in));
24069 emit_insn (fn (tmp2, tmp1, in));
24071 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
24072 GEN_INT (1), GEN_INT (1),
24073 GEN_INT (1+4), GEN_INT (1+4)));
24074 emit_insn (fn (dest, tmp2, tmp3));
24077 /* Target hook for scalar_mode_supported_p. */
24079 ix86_scalar_mode_supported_p (enum machine_mode mode)
24081 if (DECIMAL_FLOAT_MODE_P (mode))
24083 else if (mode == TFmode)
24084 return TARGET_64BIT;
24086 return default_scalar_mode_supported_p (mode);
24089 /* Implements target hook vector_mode_supported_p. */
24091 ix86_vector_mode_supported_p (enum machine_mode mode)
24093 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
24095 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
24097 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
24099 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
24104 /* Target hook for c_mode_for_suffix. */
24105 static enum machine_mode
24106 ix86_c_mode_for_suffix (char suffix)
24108 if (TARGET_64BIT && suffix == 'q')
24110 if (TARGET_MMX && suffix == 'w')
24116 /* Worker function for TARGET_MD_ASM_CLOBBERS.
24118 We do this in the new i386 backend to maintain source compatibility
24119 with the old cc0-based compiler. */
24122 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
24123 tree inputs ATTRIBUTE_UNUSED,
24126 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
24128 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
24133 /* Implements target vector targetm.asm.encode_section_info. This
24134 is not used by netware. */
24136 static void ATTRIBUTE_UNUSED
24137 ix86_encode_section_info (tree decl, rtx rtl, int first)
24139 default_encode_section_info (decl, rtl, first);
24141 if (TREE_CODE (decl) == VAR_DECL
24142 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
24143 && ix86_in_large_data_p (decl))
24144 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
24147 /* Worker function for REVERSE_CONDITION. */
24150 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
24152 return (mode != CCFPmode && mode != CCFPUmode
24153 ? reverse_condition (code)
24154 : reverse_condition_maybe_unordered (code));
24157 /* Output code to perform an x87 FP register move, from OPERANDS[1]
24161 output_387_reg_move (rtx insn, rtx *operands)
24163 if (REG_P (operands[0]))
24165 if (REG_P (operands[1])
24166 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24168 if (REGNO (operands[0]) == FIRST_STACK_REG)
24169 return output_387_ffreep (operands, 0);
24170 return "fstp\t%y0";
24172 if (STACK_TOP_P (operands[0]))
24173 return "fld%z1\t%y1";
24176 else if (MEM_P (operands[0]))
24178 gcc_assert (REG_P (operands[1]));
24179 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24180 return "fstp%z0\t%y0";
24183 /* There is no non-popping store to memory for XFmode.
24184 So if we need one, follow the store with a load. */
24185 if (GET_MODE (operands[0]) == XFmode)
24186 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
24188 return "fst%z0\t%y0";
24195 /* Output code to perform a conditional jump to LABEL, if C2 flag in
24196 FP status register is set. */
24199 ix86_emit_fp_unordered_jump (rtx label)
24201 rtx reg = gen_reg_rtx (HImode);
24204 emit_insn (gen_x86_fnstsw_1 (reg));
24206 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
24208 emit_insn (gen_x86_sahf_1 (reg));
24210 temp = gen_rtx_REG (CCmode, FLAGS_REG);
24211 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
24215 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
24217 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
24218 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
24221 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
24222 gen_rtx_LABEL_REF (VOIDmode, label),
24224 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
24226 emit_jump_insn (temp);
24227 predict_jump (REG_BR_PROB_BASE * 10 / 100);
24230 /* Output code to perform a log1p XFmode calculation. */
24232 void ix86_emit_i387_log1p (rtx op0, rtx op1)
24234 rtx label1 = gen_label_rtx ();
24235 rtx label2 = gen_label_rtx ();
24237 rtx tmp = gen_reg_rtx (XFmode);
24238 rtx tmp2 = gen_reg_rtx (XFmode);
24240 emit_insn (gen_absxf2 (tmp, op1));
24241 emit_insn (gen_cmpxf (tmp,
24242 CONST_DOUBLE_FROM_REAL_VALUE (
24243 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
24245 emit_jump_insn (gen_bge (label1));
24247 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24248 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
24249 emit_jump (label2);
24251 emit_label (label1);
24252 emit_move_insn (tmp, CONST1_RTX (XFmode));
24253 emit_insn (gen_addxf3 (tmp, op1, tmp));
24254 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24255 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
24257 emit_label (label2);
24260 /* Output code to perform a Newton-Rhapson approximation of a single precision
24261 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
24263 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
24265 rtx x0, x1, e0, e1, two;
24267 x0 = gen_reg_rtx (mode);
24268 e0 = gen_reg_rtx (mode);
24269 e1 = gen_reg_rtx (mode);
24270 x1 = gen_reg_rtx (mode);
24272 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
24274 if (VECTOR_MODE_P (mode))
24275 two = ix86_build_const_vector (SFmode, true, two);
24277 two = force_reg (mode, two);
24279 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
24281 /* x0 = rcp(b) estimate */
24282 emit_insn (gen_rtx_SET (VOIDmode, x0,
24283 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
24286 emit_insn (gen_rtx_SET (VOIDmode, e0,
24287 gen_rtx_MULT (mode, x0, b)));
24289 emit_insn (gen_rtx_SET (VOIDmode, e1,
24290 gen_rtx_MINUS (mode, two, e0)));
24292 emit_insn (gen_rtx_SET (VOIDmode, x1,
24293 gen_rtx_MULT (mode, x0, e1)));
24295 emit_insn (gen_rtx_SET (VOIDmode, res,
24296 gen_rtx_MULT (mode, a, x1)));
24299 /* Output code to perform a Newton-Rhapson approximation of a
24300 single precision floating point [reciprocal] square root. */
24302 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
24305 rtx x0, e0, e1, e2, e3, mthree, mhalf;
24308 x0 = gen_reg_rtx (mode);
24309 e0 = gen_reg_rtx (mode);
24310 e1 = gen_reg_rtx (mode);
24311 e2 = gen_reg_rtx (mode);
24312 e3 = gen_reg_rtx (mode);
24314 real_arithmetic (&r, NEGATE_EXPR, &dconst3, NULL);
24315 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24317 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
24318 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24320 if (VECTOR_MODE_P (mode))
24322 mthree = ix86_build_const_vector (SFmode, true, mthree);
24323 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
24326 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
24327 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
24329 /* x0 = rsqrt(a) estimate */
24330 emit_insn (gen_rtx_SET (VOIDmode, x0,
24331 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
24334 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
24339 zero = gen_reg_rtx (mode);
24340 mask = gen_reg_rtx (mode);
24342 zero = force_reg (mode, CONST0_RTX(mode));
24343 emit_insn (gen_rtx_SET (VOIDmode, mask,
24344 gen_rtx_NE (mode, zero, a)));
24346 emit_insn (gen_rtx_SET (VOIDmode, x0,
24347 gen_rtx_AND (mode, x0, mask)));
24351 emit_insn (gen_rtx_SET (VOIDmode, e0,
24352 gen_rtx_MULT (mode, x0, a)));
24354 emit_insn (gen_rtx_SET (VOIDmode, e1,
24355 gen_rtx_MULT (mode, e0, x0)));
24358 mthree = force_reg (mode, mthree);
24359 emit_insn (gen_rtx_SET (VOIDmode, e2,
24360 gen_rtx_PLUS (mode, e1, mthree)));
24362 mhalf = force_reg (mode, mhalf);
24364 /* e3 = -.5 * x0 */
24365 emit_insn (gen_rtx_SET (VOIDmode, e3,
24366 gen_rtx_MULT (mode, x0, mhalf)));
24368 /* e3 = -.5 * e0 */
24369 emit_insn (gen_rtx_SET (VOIDmode, e3,
24370 gen_rtx_MULT (mode, e0, mhalf)));
24371 /* ret = e2 * e3 */
24372 emit_insn (gen_rtx_SET (VOIDmode, res,
24373 gen_rtx_MULT (mode, e2, e3)));
24376 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
24378 static void ATTRIBUTE_UNUSED
24379 i386_solaris_elf_named_section (const char *name, unsigned int flags,
24382 /* With Binutils 2.15, the "@unwind" marker must be specified on
24383 every occurrence of the ".eh_frame" section, not just the first
24386 && strcmp (name, ".eh_frame") == 0)
24388 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
24389 flags & SECTION_WRITE ? "aw" : "a");
24392 default_elf_asm_named_section (name, flags, decl);
24395 /* Return the mangling of TYPE if it is an extended fundamental type. */
24397 static const char *
24398 ix86_mangle_type (const_tree type)
24400 type = TYPE_MAIN_VARIANT (type);
24402 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24403 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24406 switch (TYPE_MODE (type))
24409 /* __float128 is "g". */
24412 /* "long double" or __float80 is "e". */
24419 /* For 32-bit code we can save PIC register setup by using
24420 __stack_chk_fail_local hidden function instead of calling
24421 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
24422 register, so it is better to call __stack_chk_fail directly. */
24425 ix86_stack_protect_fail (void)
24427 return TARGET_64BIT
24428 ? default_external_stack_protect_fail ()
24429 : default_hidden_stack_protect_fail ();
24432 /* Select a format to encode pointers in exception handling data. CODE
24433 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
24434 true if the symbol may be affected by dynamic relocations.
24436 ??? All x86 object file formats are capable of representing this.
24437 After all, the relocation needed is the same as for the call insn.
24438 Whether or not a particular assembler allows us to enter such, I
24439 guess we'll have to see. */
24441 asm_preferred_eh_data_format (int code, int global)
24445 int type = DW_EH_PE_sdata8;
24447 || ix86_cmodel == CM_SMALL_PIC
24448 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
24449 type = DW_EH_PE_sdata4;
24450 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
24452 if (ix86_cmodel == CM_SMALL
24453 || (ix86_cmodel == CM_MEDIUM && code))
24454 return DW_EH_PE_udata4;
24455 return DW_EH_PE_absptr;
24458 /* Expand copysign from SIGN to the positive value ABS_VALUE
24459 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
24462 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
24464 enum machine_mode mode = GET_MODE (sign);
24465 rtx sgn = gen_reg_rtx (mode);
24466 if (mask == NULL_RTX)
24468 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
24469 if (!VECTOR_MODE_P (mode))
24471 /* We need to generate a scalar mode mask in this case. */
24472 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24473 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24474 mask = gen_reg_rtx (mode);
24475 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24479 mask = gen_rtx_NOT (mode, mask);
24480 emit_insn (gen_rtx_SET (VOIDmode, sgn,
24481 gen_rtx_AND (mode, mask, sign)));
24482 emit_insn (gen_rtx_SET (VOIDmode, result,
24483 gen_rtx_IOR (mode, abs_value, sgn)));
24486 /* Expand fabs (OP0) and return a new rtx that holds the result. The
24487 mask for masking out the sign-bit is stored in *SMASK, if that is
24490 ix86_expand_sse_fabs (rtx op0, rtx *smask)
24492 enum machine_mode mode = GET_MODE (op0);
24495 xa = gen_reg_rtx (mode);
24496 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
24497 if (!VECTOR_MODE_P (mode))
24499 /* We need to generate a scalar mode mask in this case. */
24500 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24501 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24502 mask = gen_reg_rtx (mode);
24503 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24505 emit_insn (gen_rtx_SET (VOIDmode, xa,
24506 gen_rtx_AND (mode, op0, mask)));
24514 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
24515 swapping the operands if SWAP_OPERANDS is true. The expanded
24516 code is a forward jump to a newly created label in case the
24517 comparison is true. The generated label rtx is returned. */
24519 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
24520 bool swap_operands)
24531 label = gen_label_rtx ();
24532 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
24533 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24534 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
24535 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
24536 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
24537 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
24538 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
24539 JUMP_LABEL (tmp) = label;
24544 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
24545 using comparison code CODE. Operands are swapped for the comparison if
24546 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
24548 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
24549 bool swap_operands)
24551 enum machine_mode mode = GET_MODE (op0);
24552 rtx mask = gen_reg_rtx (mode);
24561 if (mode == DFmode)
24562 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
24563 gen_rtx_fmt_ee (code, mode, op0, op1)));
24565 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
24566 gen_rtx_fmt_ee (code, mode, op0, op1)));
24571 /* Generate and return a rtx of mode MODE for 2**n where n is the number
24572 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
24574 ix86_gen_TWO52 (enum machine_mode mode)
24576 REAL_VALUE_TYPE TWO52r;
24579 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
24580 TWO52 = const_double_from_real_value (TWO52r, mode);
24581 TWO52 = force_reg (mode, TWO52);
24586 /* Expand SSE sequence for computing lround from OP1 storing
24589 ix86_expand_lround (rtx op0, rtx op1)
24591 /* C code for the stuff we're doing below:
24592 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
24595 enum machine_mode mode = GET_MODE (op1);
24596 const struct real_format *fmt;
24597 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
24600 /* load nextafter (0.5, 0.0) */
24601 fmt = REAL_MODE_FORMAT (mode);
24602 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
24603 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
24605 /* adj = copysign (0.5, op1) */
24606 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
24607 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
24609 /* adj = op1 + adj */
24610 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
24612 /* op0 = (imode)adj */
24613 expand_fix (op0, adj, 0);
24616 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
24619 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
24621 /* C code for the stuff we're doing below (for do_floor):
24623 xi -= (double)xi > op1 ? 1 : 0;
24626 enum machine_mode fmode = GET_MODE (op1);
24627 enum machine_mode imode = GET_MODE (op0);
24628 rtx ireg, freg, label, tmp;
24630 /* reg = (long)op1 */
24631 ireg = gen_reg_rtx (imode);
24632 expand_fix (ireg, op1, 0);
24634 /* freg = (double)reg */
24635 freg = gen_reg_rtx (fmode);
24636 expand_float (freg, ireg, 0);
24638 /* ireg = (freg > op1) ? ireg - 1 : ireg */
24639 label = ix86_expand_sse_compare_and_jump (UNLE,
24640 freg, op1, !do_floor);
24641 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
24642 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
24643 emit_move_insn (ireg, tmp);
24645 emit_label (label);
24646 LABEL_NUSES (label) = 1;
24648 emit_move_insn (op0, ireg);
24651 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
24652 result in OPERAND0. */
24654 ix86_expand_rint (rtx operand0, rtx operand1)
24656 /* C code for the stuff we're doing below:
24657 xa = fabs (operand1);
24658 if (!isless (xa, 2**52))
24660 xa = xa + 2**52 - 2**52;
24661 return copysign (xa, operand1);
24663 enum machine_mode mode = GET_MODE (operand0);
24664 rtx res, xa, label, TWO52, mask;
24666 res = gen_reg_rtx (mode);
24667 emit_move_insn (res, operand1);
24669 /* xa = abs (operand1) */
24670 xa = ix86_expand_sse_fabs (res, &mask);
24672 /* if (!isless (xa, TWO52)) goto label; */
24673 TWO52 = ix86_gen_TWO52 (mode);
24674 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24676 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24677 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24679 ix86_sse_copysign_to_positive (res, xa, res, mask);
24681 emit_label (label);
24682 LABEL_NUSES (label) = 1;
24684 emit_move_insn (operand0, res);
24687 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24690 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
24692 /* C code for the stuff we expand below.
24693 double xa = fabs (x), x2;
24694 if (!isless (xa, TWO52))
24696 xa = xa + TWO52 - TWO52;
24697 x2 = copysign (xa, x);
24706 enum machine_mode mode = GET_MODE (operand0);
24707 rtx xa, TWO52, tmp, label, one, res, mask;
24709 TWO52 = ix86_gen_TWO52 (mode);
24711 /* Temporary for holding the result, initialized to the input
24712 operand to ease control flow. */
24713 res = gen_reg_rtx (mode);
24714 emit_move_insn (res, operand1);
24716 /* xa = abs (operand1) */
24717 xa = ix86_expand_sse_fabs (res, &mask);
24719 /* if (!isless (xa, TWO52)) goto label; */
24720 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24722 /* xa = xa + TWO52 - TWO52; */
24723 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24724 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24726 /* xa = copysign (xa, operand1) */
24727 ix86_sse_copysign_to_positive (xa, xa, res, mask);
24729 /* generate 1.0 or -1.0 */
24730 one = force_reg (mode,
24731 const_double_from_real_value (do_floor
24732 ? dconst1 : dconstm1, mode));
24734 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24735 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24736 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24737 gen_rtx_AND (mode, one, tmp)));
24738 /* We always need to subtract here to preserve signed zero. */
24739 tmp = expand_simple_binop (mode, MINUS,
24740 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24741 emit_move_insn (res, tmp);
24743 emit_label (label);
24744 LABEL_NUSES (label) = 1;
24746 emit_move_insn (operand0, res);
24749 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24752 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
24754 /* C code for the stuff we expand below.
24755 double xa = fabs (x), x2;
24756 if (!isless (xa, TWO52))
24758 x2 = (double)(long)x;
24765 if (HONOR_SIGNED_ZEROS (mode))
24766 return copysign (x2, x);
24769 enum machine_mode mode = GET_MODE (operand0);
24770 rtx xa, xi, TWO52, tmp, label, one, res, mask;
24772 TWO52 = ix86_gen_TWO52 (mode);
24774 /* Temporary for holding the result, initialized to the input
24775 operand to ease control flow. */
24776 res = gen_reg_rtx (mode);
24777 emit_move_insn (res, operand1);
24779 /* xa = abs (operand1) */
24780 xa = ix86_expand_sse_fabs (res, &mask);
24782 /* if (!isless (xa, TWO52)) goto label; */
24783 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24785 /* xa = (double)(long)x */
24786 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24787 expand_fix (xi, res, 0);
24788 expand_float (xa, xi, 0);
24791 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
24793 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24794 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24795 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24796 gen_rtx_AND (mode, one, tmp)));
24797 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
24798 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24799 emit_move_insn (res, tmp);
24801 if (HONOR_SIGNED_ZEROS (mode))
24802 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
24804 emit_label (label);
24805 LABEL_NUSES (label) = 1;
24807 emit_move_insn (operand0, res);
24810 /* Expand SSE sequence for computing round from OPERAND1 storing
24811 into OPERAND0. Sequence that works without relying on DImode truncation
24812 via cvttsd2siq that is only available on 64bit targets. */
24814 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
24816 /* C code for the stuff we expand below.
24817 double xa = fabs (x), xa2, x2;
24818 if (!isless (xa, TWO52))
24820 Using the absolute value and copying back sign makes
24821 -0.0 -> -0.0 correct.
24822 xa2 = xa + TWO52 - TWO52;
24827 else if (dxa > 0.5)
24829 x2 = copysign (xa2, x);
24832 enum machine_mode mode = GET_MODE (operand0);
24833 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
24835 TWO52 = ix86_gen_TWO52 (mode);
24837 /* Temporary for holding the result, initialized to the input
24838 operand to ease control flow. */
24839 res = gen_reg_rtx (mode);
24840 emit_move_insn (res, operand1);
24842 /* xa = abs (operand1) */
24843 xa = ix86_expand_sse_fabs (res, &mask);
24845 /* if (!isless (xa, TWO52)) goto label; */
24846 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24848 /* xa2 = xa + TWO52 - TWO52; */
24849 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24850 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
24852 /* dxa = xa2 - xa; */
24853 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
24855 /* generate 0.5, 1.0 and -0.5 */
24856 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
24857 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
24858 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
24862 tmp = gen_reg_rtx (mode);
24863 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
24864 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
24865 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24866 gen_rtx_AND (mode, one, tmp)));
24867 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24868 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
24869 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
24870 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24871 gen_rtx_AND (mode, one, tmp)));
24872 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24874 /* res = copysign (xa2, operand1) */
24875 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
24877 emit_label (label);
24878 LABEL_NUSES (label) = 1;
24880 emit_move_insn (operand0, res);
24883 /* Expand SSE sequence for computing trunc from OPERAND1 storing
24886 ix86_expand_trunc (rtx operand0, rtx operand1)
24888 /* C code for SSE variant we expand below.
24889 double xa = fabs (x), x2;
24890 if (!isless (xa, TWO52))
24892 x2 = (double)(long)x;
24893 if (HONOR_SIGNED_ZEROS (mode))
24894 return copysign (x2, x);
24897 enum machine_mode mode = GET_MODE (operand0);
24898 rtx xa, xi, TWO52, label, res, mask;
24900 TWO52 = ix86_gen_TWO52 (mode);
24902 /* Temporary for holding the result, initialized to the input
24903 operand to ease control flow. */
24904 res = gen_reg_rtx (mode);
24905 emit_move_insn (res, operand1);
24907 /* xa = abs (operand1) */
24908 xa = ix86_expand_sse_fabs (res, &mask);
24910 /* if (!isless (xa, TWO52)) goto label; */
24911 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24913 /* x = (double)(long)x */
24914 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24915 expand_fix (xi, res, 0);
24916 expand_float (res, xi, 0);
24918 if (HONOR_SIGNED_ZEROS (mode))
24919 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
24921 emit_label (label);
24922 LABEL_NUSES (label) = 1;
24924 emit_move_insn (operand0, res);
24927 /* Expand SSE sequence for computing trunc from OPERAND1 storing
24930 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
24932 enum machine_mode mode = GET_MODE (operand0);
24933 rtx xa, mask, TWO52, label, one, res, smask, tmp;
24935 /* C code for SSE variant we expand below.
24936 double xa = fabs (x), x2;
24937 if (!isless (xa, TWO52))
24939 xa2 = xa + TWO52 - TWO52;
24943 x2 = copysign (xa2, x);
24947 TWO52 = ix86_gen_TWO52 (mode);
24949 /* Temporary for holding the result, initialized to the input
24950 operand to ease control flow. */
24951 res = gen_reg_rtx (mode);
24952 emit_move_insn (res, operand1);
24954 /* xa = abs (operand1) */
24955 xa = ix86_expand_sse_fabs (res, &smask);
24957 /* if (!isless (xa, TWO52)) goto label; */
24958 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24960 /* res = xa + TWO52 - TWO52; */
24961 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24962 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
24963 emit_move_insn (res, tmp);
24966 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
24968 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
24969 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
24970 emit_insn (gen_rtx_SET (VOIDmode, mask,
24971 gen_rtx_AND (mode, mask, one)));
24972 tmp = expand_simple_binop (mode, MINUS,
24973 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
24974 emit_move_insn (res, tmp);
24976 /* res = copysign (res, operand1) */
24977 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
24979 emit_label (label);
24980 LABEL_NUSES (label) = 1;
24982 emit_move_insn (operand0, res);
24985 /* Expand SSE sequence for computing round from OPERAND1 storing
24988 ix86_expand_round (rtx operand0, rtx operand1)
24990 /* C code for the stuff we're doing below:
24991 double xa = fabs (x);
24992 if (!isless (xa, TWO52))
24994 xa = (double)(long)(xa + nextafter (0.5, 0.0));
24995 return copysign (xa, x);
24997 enum machine_mode mode = GET_MODE (operand0);
24998 rtx res, TWO52, xa, label, xi, half, mask;
24999 const struct real_format *fmt;
25000 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
25002 /* Temporary for holding the result, initialized to the input
25003 operand to ease control flow. */
25004 res = gen_reg_rtx (mode);
25005 emit_move_insn (res, operand1);
25007 TWO52 = ix86_gen_TWO52 (mode);
25008 xa = ix86_expand_sse_fabs (res, &mask);
25009 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25011 /* load nextafter (0.5, 0.0) */
25012 fmt = REAL_MODE_FORMAT (mode);
25013 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25014 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25016 /* xa = xa + 0.5 */
25017 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
25018 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
25020 /* xa = (double)(int64_t)xa */
25021 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25022 expand_fix (xi, xa, 0);
25023 expand_float (xa, xi, 0);
25025 /* res = copysign (xa, operand1) */
25026 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
25028 emit_label (label);
25029 LABEL_NUSES (label) = 1;
25031 emit_move_insn (operand0, res);
25035 /* Validate whether a SSE5 instruction is valid or not.
25036 OPERANDS is the array of operands.
25037 NUM is the number of operands.
25038 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
25039 NUM_MEMORY is the maximum number of memory operands to accept. */
25041 ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int num_memory)
25047 /* Count the number of memory arguments */
25050 for (i = 0; i < num; i++)
25052 enum machine_mode mode = GET_MODE (operands[i]);
25053 if (register_operand (operands[i], mode))
25056 else if (memory_operand (operands[i], mode))
25058 mem_mask |= (1 << i);
25064 rtx pattern = PATTERN (insn);
25066 /* allow 0 for pcmov */
25067 if (GET_CODE (pattern) != SET
25068 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
25070 || operands[i] != CONST0_RTX (mode))
25075 /* If there were no memory operations, allow the insn */
25079 /* Do not allow the destination register to be a memory operand. */
25080 else if (mem_mask & (1 << 0))
25083 /* If there are too many memory operations, disallow the instruction. While
25084 the hardware only allows 1 memory reference, before register allocation
25085 for some insns, we allow two memory operations sometimes in order to allow
25086 code like the following to be optimized:
25088 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
25090 or similar cases that are vectorized into using the fmaddss
25092 else if (mem_count > num_memory)
25095 /* Don't allow more than one memory operation if not optimizing. */
25096 else if (mem_count > 1 && !optimize)
25099 else if (num == 4 && mem_count == 1)
25101 /* formats (destination is the first argument), example fmaddss:
25102 xmm1, xmm1, xmm2, xmm3/mem
25103 xmm1, xmm1, xmm2/mem, xmm3
25104 xmm1, xmm2, xmm3/mem, xmm1
25105 xmm1, xmm2/mem, xmm3, xmm1 */
25107 return ((mem_mask == (1 << 1))
25108 || (mem_mask == (1 << 2))
25109 || (mem_mask == (1 << 3)));
25111 /* format, example pmacsdd:
25112 xmm1, xmm2, xmm3/mem, xmm1 */
25114 return (mem_mask == (1 << 2));
25117 else if (num == 4 && num_memory == 2)
25119 /* If there are two memory operations, we can load one of the memory ops
25120 into the destination register. This is for optimizing the
25121 multiply/add ops, which the combiner has optimized both the multiply
25122 and the add insns to have a memory operation. We have to be careful
25123 that the destination doesn't overlap with the inputs. */
25124 rtx op0 = operands[0];
25126 if (reg_mentioned_p (op0, operands[1])
25127 || reg_mentioned_p (op0, operands[2])
25128 || reg_mentioned_p (op0, operands[3]))
25131 /* formats (destination is the first argument), example fmaddss:
25132 xmm1, xmm1, xmm2, xmm3/mem
25133 xmm1, xmm1, xmm2/mem, xmm3
25134 xmm1, xmm2, xmm3/mem, xmm1
25135 xmm1, xmm2/mem, xmm3, xmm1
25137 For the oc0 case, we will load either operands[1] or operands[3] into
25138 operands[0], so any combination of 2 memory operands is ok. */
25142 /* format, example pmacsdd:
25143 xmm1, xmm2, xmm3/mem, xmm1
25145 For the integer multiply/add instructions be more restrictive and
25146 require operands[2] and operands[3] to be the memory operands. */
25148 return (mem_mask == ((1 << 2) | (1 << 3)));
25151 else if (num == 3 && num_memory == 1)
25153 /* formats, example protb:
25154 xmm1, xmm2, xmm3/mem
25155 xmm1, xmm2/mem, xmm3 */
25157 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
25159 /* format, example comeq:
25160 xmm1, xmm2, xmm3/mem */
25162 return (mem_mask == (1 << 2));
25166 gcc_unreachable ();
25172 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
25173 hardware will allow by using the destination register to load one of the
25174 memory operations. Presently this is used by the multiply/add routines to
25175 allow 2 memory references. */
25178 ix86_expand_sse5_multiple_memory (rtx operands[],
25180 enum machine_mode mode)
25182 rtx op0 = operands[0];
25184 || memory_operand (op0, mode)
25185 || reg_mentioned_p (op0, operands[1])
25186 || reg_mentioned_p (op0, operands[2])
25187 || reg_mentioned_p (op0, operands[3]))
25188 gcc_unreachable ();
25190 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
25191 the destination register. */
25192 if (memory_operand (operands[1], mode))
25194 emit_move_insn (op0, operands[1]);
25197 else if (memory_operand (operands[3], mode))
25199 emit_move_insn (op0, operands[3]);
25203 gcc_unreachable ();
25209 /* Table of valid machine attributes. */
25210 static const struct attribute_spec ix86_attribute_table[] =
25212 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
25213 /* Stdcall attribute says callee is responsible for popping arguments
25214 if they are not variable. */
25215 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25216 /* Fastcall attribute says callee is responsible for popping arguments
25217 if they are not variable. */
25218 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25219 /* Cdecl attribute says the callee is a normal C declaration */
25220 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25221 /* Regparm attribute specifies how many integer arguments are to be
25222 passed in registers. */
25223 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
25224 /* Sseregparm attribute says we are using x86_64 calling conventions
25225 for FP arguments. */
25226 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25227 /* force_align_arg_pointer says this function realigns the stack at entry. */
25228 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
25229 false, true, true, ix86_handle_cconv_attribute },
25230 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25231 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
25232 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
25233 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
25235 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25236 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25237 #ifdef SUBTARGET_ATTRIBUTE_TABLE
25238 SUBTARGET_ATTRIBUTE_TABLE,
25240 { NULL, 0, 0, false, false, false, NULL }
25243 /* Implement targetm.vectorize.builtin_vectorization_cost. */
25245 x86_builtin_vectorization_cost (bool runtime_test)
25247 /* If the branch of the runtime test is taken - i.e. - the vectorized
25248 version is skipped - this incurs a misprediction cost (because the
25249 vectorized version is expected to be the fall-through). So we subtract
25250 the latency of a mispredicted branch from the costs that are incured
25251 when the vectorized version is executed.
25253 TODO: The values in individual target tables have to be tuned or new
25254 fields may be needed. For eg. on K8, the default branch path is the
25255 not-taken path. If the taken path is predicted correctly, the minimum
25256 penalty of going down the taken-path is 1 cycle. If the taken-path is
25257 not predicted correctly, then the minimum penalty is 10 cycles. */
25261 return (-(ix86_cost->cond_taken_branch_cost));
25267 /* Initialize the GCC target structure. */
25268 #undef TARGET_ATTRIBUTE_TABLE
25269 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
25270 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25271 # undef TARGET_MERGE_DECL_ATTRIBUTES
25272 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
25275 #undef TARGET_COMP_TYPE_ATTRIBUTES
25276 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
25278 #undef TARGET_INIT_BUILTINS
25279 #define TARGET_INIT_BUILTINS ix86_init_builtins
25280 #undef TARGET_EXPAND_BUILTIN
25281 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
25283 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25284 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25285 ix86_builtin_vectorized_function
25287 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
25288 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
25290 #undef TARGET_BUILTIN_RECIPROCAL
25291 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
25293 #undef TARGET_ASM_FUNCTION_EPILOGUE
25294 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
25296 #undef TARGET_ENCODE_SECTION_INFO
25297 #ifndef SUBTARGET_ENCODE_SECTION_INFO
25298 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
25300 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
25303 #undef TARGET_ASM_OPEN_PAREN
25304 #define TARGET_ASM_OPEN_PAREN ""
25305 #undef TARGET_ASM_CLOSE_PAREN
25306 #define TARGET_ASM_CLOSE_PAREN ""
25308 #undef TARGET_ASM_ALIGNED_HI_OP
25309 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
25310 #undef TARGET_ASM_ALIGNED_SI_OP
25311 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
25313 #undef TARGET_ASM_ALIGNED_DI_OP
25314 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
25317 #undef TARGET_ASM_UNALIGNED_HI_OP
25318 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
25319 #undef TARGET_ASM_UNALIGNED_SI_OP
25320 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
25321 #undef TARGET_ASM_UNALIGNED_DI_OP
25322 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
25324 #undef TARGET_SCHED_ADJUST_COST
25325 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
25326 #undef TARGET_SCHED_ISSUE_RATE
25327 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
25328 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25329 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25330 ia32_multipass_dfa_lookahead
25332 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25333 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
25336 #undef TARGET_HAVE_TLS
25337 #define TARGET_HAVE_TLS true
25339 #undef TARGET_CANNOT_FORCE_CONST_MEM
25340 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
25341 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25342 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
25344 #undef TARGET_DELEGITIMIZE_ADDRESS
25345 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
25347 #undef TARGET_MS_BITFIELD_LAYOUT_P
25348 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
25351 #undef TARGET_BINDS_LOCAL_P
25352 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
25354 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25355 #undef TARGET_BINDS_LOCAL_P
25356 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
25359 #undef TARGET_ASM_OUTPUT_MI_THUNK
25360 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
25361 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25362 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
25364 #undef TARGET_ASM_FILE_START
25365 #define TARGET_ASM_FILE_START x86_file_start
25367 #undef TARGET_DEFAULT_TARGET_FLAGS
25368 #define TARGET_DEFAULT_TARGET_FLAGS \
25370 | TARGET_SUBTARGET_DEFAULT \
25371 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
25373 #undef TARGET_HANDLE_OPTION
25374 #define TARGET_HANDLE_OPTION ix86_handle_option
25376 #undef TARGET_RTX_COSTS
25377 #define TARGET_RTX_COSTS ix86_rtx_costs
25378 #undef TARGET_ADDRESS_COST
25379 #define TARGET_ADDRESS_COST ix86_address_cost
25381 #undef TARGET_FIXED_CONDITION_CODE_REGS
25382 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
25383 #undef TARGET_CC_MODES_COMPATIBLE
25384 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
25386 #undef TARGET_MACHINE_DEPENDENT_REORG
25387 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
25389 #undef TARGET_BUILD_BUILTIN_VA_LIST
25390 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
25392 #undef TARGET_EXPAND_BUILTIN_VA_START
25393 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
25395 #undef TARGET_MD_ASM_CLOBBERS
25396 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
25398 #undef TARGET_PROMOTE_PROTOTYPES
25399 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
25400 #undef TARGET_STRUCT_VALUE_RTX
25401 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
25402 #undef TARGET_SETUP_INCOMING_VARARGS
25403 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
25404 #undef TARGET_MUST_PASS_IN_STACK
25405 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
25406 #undef TARGET_PASS_BY_REFERENCE
25407 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
25408 #undef TARGET_INTERNAL_ARG_POINTER
25409 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
25410 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
25411 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
25412 #undef TARGET_STRICT_ARGUMENT_NAMING
25413 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
25415 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
25416 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
25418 #undef TARGET_SCALAR_MODE_SUPPORTED_P
25419 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
25421 #undef TARGET_VECTOR_MODE_SUPPORTED_P
25422 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
25424 #undef TARGET_C_MODE_FOR_SUFFIX
25425 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
25428 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
25429 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
25432 #ifdef SUBTARGET_INSERT_ATTRIBUTES
25433 #undef TARGET_INSERT_ATTRIBUTES
25434 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
25437 #undef TARGET_MANGLE_TYPE
25438 #define TARGET_MANGLE_TYPE ix86_mangle_type
25440 #undef TARGET_STACK_PROTECT_FAIL
25441 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
25443 #undef TARGET_FUNCTION_VALUE
25444 #define TARGET_FUNCTION_VALUE ix86_function_value
25446 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
25447 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
25449 struct gcc_target targetm = TARGET_INITIALIZER;
25451 #include "gt-i386.h"
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