1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1557 /* X86_ARCH_CALL_ESP: P6 processors will jump to the address after
1558 the decrement (so they will execute return address as code). See
1559 Pentium Pro errata 70, Pentium 2 errata A33, Pentium 3 errata E17. */
1560 ~(m_386 | m_486 | m_PENT | m_PPRO),
1563 static const unsigned int x86_accumulate_outgoing_args
1564 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1567 static const unsigned int x86_arch_always_fancy_math_387
1568 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1569 | m_NOCONA | m_CORE2 | m_GENERIC;
1571 static enum stringop_alg stringop_alg = no_stringop;
1573 /* In case the average insn count for single function invocation is
1574 lower than this constant, emit fast (but longer) prologue and
1576 #define FAST_PROLOGUE_INSN_COUNT 20
1578 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1579 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1580 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1581 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1583 /* Array of the smallest class containing reg number REGNO, indexed by
1584 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1586 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1588 /* ax, dx, cx, bx */
1589 AREG, DREG, CREG, BREG,
1590 /* si, di, bp, sp */
1591 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1593 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1594 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1597 /* flags, fpsr, fpcr, frame */
1598 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1600 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1603 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1606 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1607 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1608 /* SSE REX registers */
1609 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1613 /* The "default" register map used in 32bit mode. */
1615 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1617 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1618 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1619 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1620 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1621 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1622 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1623 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1626 /* The "default" register map used in 64bit mode. */
1628 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1630 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1631 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1632 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1633 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1634 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1635 8,9,10,11,12,13,14,15, /* extended integer registers */
1636 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1639 /* Define the register numbers to be used in Dwarf debugging information.
1640 The SVR4 reference port C compiler uses the following register numbers
1641 in its Dwarf output code:
1642 0 for %eax (gcc regno = 0)
1643 1 for %ecx (gcc regno = 2)
1644 2 for %edx (gcc regno = 1)
1645 3 for %ebx (gcc regno = 3)
1646 4 for %esp (gcc regno = 7)
1647 5 for %ebp (gcc regno = 6)
1648 6 for %esi (gcc regno = 4)
1649 7 for %edi (gcc regno = 5)
1650 The following three DWARF register numbers are never generated by
1651 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1652 believes these numbers have these meanings.
1653 8 for %eip (no gcc equivalent)
1654 9 for %eflags (gcc regno = 17)
1655 10 for %trapno (no gcc equivalent)
1656 It is not at all clear how we should number the FP stack registers
1657 for the x86 architecture. If the version of SDB on x86/svr4 were
1658 a bit less brain dead with respect to floating-point then we would
1659 have a precedent to follow with respect to DWARF register numbers
1660 for x86 FP registers, but the SDB on x86/svr4 is so completely
1661 broken with respect to FP registers that it is hardly worth thinking
1662 of it as something to strive for compatibility with.
1663 The version of x86/svr4 SDB I have at the moment does (partially)
1664 seem to believe that DWARF register number 11 is associated with
1665 the x86 register %st(0), but that's about all. Higher DWARF
1666 register numbers don't seem to be associated with anything in
1667 particular, and even for DWARF regno 11, SDB only seems to under-
1668 stand that it should say that a variable lives in %st(0) (when
1669 asked via an `=' command) if we said it was in DWARF regno 11,
1670 but SDB still prints garbage when asked for the value of the
1671 variable in question (via a `/' command).
1672 (Also note that the labels SDB prints for various FP stack regs
1673 when doing an `x' command are all wrong.)
1674 Note that these problems generally don't affect the native SVR4
1675 C compiler because it doesn't allow the use of -O with -g and
1676 because when it is *not* optimizing, it allocates a memory
1677 location for each floating-point variable, and the memory
1678 location is what gets described in the DWARF AT_location
1679 attribute for the variable in question.
1680 Regardless of the severe mental illness of the x86/svr4 SDB, we
1681 do something sensible here and we use the following DWARF
1682 register numbers. Note that these are all stack-top-relative
1684 11 for %st(0) (gcc regno = 8)
1685 12 for %st(1) (gcc regno = 9)
1686 13 for %st(2) (gcc regno = 10)
1687 14 for %st(3) (gcc regno = 11)
1688 15 for %st(4) (gcc regno = 12)
1689 16 for %st(5) (gcc regno = 13)
1690 17 for %st(6) (gcc regno = 14)
1691 18 for %st(7) (gcc regno = 15)
1693 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1695 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1696 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1697 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1698 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1699 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1700 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1701 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1704 /* Test and compare insns in i386.md store the information needed to
1705 generate branch and scc insns here. */
1707 rtx ix86_compare_op0 = NULL_RTX;
1708 rtx ix86_compare_op1 = NULL_RTX;
1710 /* Define parameter passing and return registers. */
1712 static int const x86_64_int_parameter_registers[6] =
1714 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1717 static int const x86_64_ms_abi_int_parameter_registers[4] =
1719 CX_REG, DX_REG, R8_REG, R9_REG
1722 static int const x86_64_int_return_registers[4] =
1724 AX_REG, DX_REG, DI_REG, SI_REG
1727 /* Define the structure for the machine field in struct function. */
1729 struct GTY(()) stack_local_entry {
1730 unsigned short mode;
1733 struct stack_local_entry *next;
1736 /* Structure describing stack frame layout.
1737 Stack grows downward:
1743 saved frame pointer if frame_pointer_needed
1744 <- HARD_FRAME_POINTER
1753 [va_arg registers] (
1754 > to_allocate <- FRAME_POINTER
1766 HOST_WIDE_INT frame;
1768 int outgoing_arguments_size;
1771 HOST_WIDE_INT to_allocate;
1772 /* The offsets relative to ARG_POINTER. */
1773 HOST_WIDE_INT frame_pointer_offset;
1774 HOST_WIDE_INT hard_frame_pointer_offset;
1775 HOST_WIDE_INT stack_pointer_offset;
1777 /* When save_regs_using_mov is set, emit prologue using
1778 move instead of push instructions. */
1779 bool save_regs_using_mov;
1782 /* Code model option. */
1783 enum cmodel ix86_cmodel;
1785 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1787 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1789 /* Which unit we are generating floating point math for. */
1790 enum fpmath_unit ix86_fpmath;
1792 /* Which cpu are we scheduling for. */
1793 enum attr_cpu ix86_schedule;
1795 /* Which cpu are we optimizing for. */
1796 enum processor_type ix86_tune;
1798 /* Which instruction set architecture to use. */
1799 enum processor_type ix86_arch;
1801 /* true if sse prefetch instruction is not NOOP. */
1802 int x86_prefetch_sse;
1804 /* ix86_regparm_string as a number */
1805 static int ix86_regparm;
1807 /* -mstackrealign option */
1808 extern int ix86_force_align_arg_pointer;
1809 static const char ix86_force_align_arg_pointer_string[]
1810 = "force_align_arg_pointer";
1812 static rtx (*ix86_gen_leave) (void);
1813 static rtx (*ix86_gen_pop1) (rtx);
1814 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1815 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1816 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1817 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1818 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1819 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1821 /* Preferred alignment for stack boundary in bits. */
1822 unsigned int ix86_preferred_stack_boundary;
1824 /* Alignment for incoming stack boundary in bits specified at
1826 static unsigned int ix86_user_incoming_stack_boundary;
1828 /* Default alignment for incoming stack boundary in bits. */
1829 static unsigned int ix86_default_incoming_stack_boundary;
1831 /* Alignment for incoming stack boundary in bits. */
1832 unsigned int ix86_incoming_stack_boundary;
1834 /* The abi used by target. */
1835 enum calling_abi ix86_abi;
1837 /* Values 1-5: see jump.c */
1838 int ix86_branch_cost;
1840 /* Calling abi specific va_list type nodes. */
1841 static GTY(()) tree sysv_va_list_type_node;
1842 static GTY(()) tree ms_va_list_type_node;
1844 /* Variables which are this size or smaller are put in the data/bss
1845 or ldata/lbss sections. */
1847 int ix86_section_threshold = 65536;
1849 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1850 char internal_label_prefix[16];
1851 int internal_label_prefix_len;
1853 /* Fence to use after loop using movnt. */
1856 /* Register class used for passing given 64bit part of the argument.
1857 These represent classes as documented by the PS ABI, with the exception
1858 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1859 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1861 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1862 whenever possible (upper half does contain padding). */
1863 enum x86_64_reg_class
1866 X86_64_INTEGER_CLASS,
1867 X86_64_INTEGERSI_CLASS,
1874 X86_64_COMPLEX_X87_CLASS,
1878 #define MAX_CLASSES 4
1880 /* Table of constants used by fldpi, fldln2, etc.... */
1881 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1882 static bool ext_80387_constants_init = 0;
1885 static struct machine_function * ix86_init_machine_status (void);
1886 static rtx ix86_function_value (const_tree, const_tree, bool);
1887 static rtx ix86_static_chain (const_tree, bool);
1888 static int ix86_function_regparm (const_tree, const_tree);
1889 static void ix86_compute_frame_layout (struct ix86_frame *);
1890 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1892 static void ix86_add_new_builtins (int);
1894 enum ix86_function_specific_strings
1896 IX86_FUNCTION_SPECIFIC_ARCH,
1897 IX86_FUNCTION_SPECIFIC_TUNE,
1898 IX86_FUNCTION_SPECIFIC_FPMATH,
1899 IX86_FUNCTION_SPECIFIC_MAX
1902 static char *ix86_target_string (int, int, const char *, const char *,
1903 const char *, bool);
1904 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1905 static void ix86_function_specific_save (struct cl_target_option *);
1906 static void ix86_function_specific_restore (struct cl_target_option *);
1907 static void ix86_function_specific_print (FILE *, int,
1908 struct cl_target_option *);
1909 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1910 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1911 static bool ix86_can_inline_p (tree, tree);
1912 static void ix86_set_current_function (tree);
1913 static unsigned int ix86_minimum_incoming_stack_boundary (bool);
1915 static enum calling_abi ix86_function_abi (const_tree);
1918 /* The svr4 ABI for the i386 says that records and unions are returned
1920 #ifndef DEFAULT_PCC_STRUCT_RETURN
1921 #define DEFAULT_PCC_STRUCT_RETURN 1
1924 /* Whether -mtune= or -march= were specified */
1925 static int ix86_tune_defaulted;
1926 static int ix86_arch_specified;
1928 /* Bit flags that specify the ISA we are compiling for. */
1929 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1931 /* A mask of ix86_isa_flags that includes bit X if X
1932 was set or cleared on the command line. */
1933 static int ix86_isa_flags_explicit;
1935 /* Define a set of ISAs which are available when a given ISA is
1936 enabled. MMX and SSE ISAs are handled separately. */
1938 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1939 #define OPTION_MASK_ISA_3DNOW_SET \
1940 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1942 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1943 #define OPTION_MASK_ISA_SSE2_SET \
1944 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1945 #define OPTION_MASK_ISA_SSE3_SET \
1946 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1947 #define OPTION_MASK_ISA_SSSE3_SET \
1948 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1949 #define OPTION_MASK_ISA_SSE4_1_SET \
1950 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1951 #define OPTION_MASK_ISA_SSE4_2_SET \
1952 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1953 #define OPTION_MASK_ISA_AVX_SET \
1954 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1955 #define OPTION_MASK_ISA_FMA_SET \
1956 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1958 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1960 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1962 #define OPTION_MASK_ISA_SSE4A_SET \
1963 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1964 #define OPTION_MASK_ISA_FMA4_SET \
1965 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
1966 | OPTION_MASK_ISA_AVX_SET)
1967 #define OPTION_MASK_ISA_XOP_SET \
1968 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
1969 #define OPTION_MASK_ISA_LWP_SET \
1972 /* AES and PCLMUL need SSE2 because they use xmm registers */
1973 #define OPTION_MASK_ISA_AES_SET \
1974 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1975 #define OPTION_MASK_ISA_PCLMUL_SET \
1976 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1978 #define OPTION_MASK_ISA_ABM_SET \
1979 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1981 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1982 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1983 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1984 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1985 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1987 /* Define a set of ISAs which aren't available when a given ISA is
1988 disabled. MMX and SSE ISAs are handled separately. */
1990 #define OPTION_MASK_ISA_MMX_UNSET \
1991 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1992 #define OPTION_MASK_ISA_3DNOW_UNSET \
1993 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1994 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1996 #define OPTION_MASK_ISA_SSE_UNSET \
1997 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1998 #define OPTION_MASK_ISA_SSE2_UNSET \
1999 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2000 #define OPTION_MASK_ISA_SSE3_UNSET \
2001 (OPTION_MASK_ISA_SSE3 \
2002 | OPTION_MASK_ISA_SSSE3_UNSET \
2003 | OPTION_MASK_ISA_SSE4A_UNSET )
2004 #define OPTION_MASK_ISA_SSSE3_UNSET \
2005 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2006 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2007 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2008 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2009 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2010 #define OPTION_MASK_ISA_AVX_UNSET \
2011 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2012 | OPTION_MASK_ISA_FMA4_UNSET)
2013 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2015 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2017 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2019 #define OPTION_MASK_ISA_SSE4A_UNSET \
2020 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2022 #define OPTION_MASK_ISA_FMA4_UNSET \
2023 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2024 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2025 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2027 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2028 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2029 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2030 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2031 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2032 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2033 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2034 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2036 /* Vectorization library interface and handlers. */
2037 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2038 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2039 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2041 /* Processor target table, indexed by processor number */
2044 const struct processor_costs *cost; /* Processor costs */
2045 const int align_loop; /* Default alignments. */
2046 const int align_loop_max_skip;
2047 const int align_jump;
2048 const int align_jump_max_skip;
2049 const int align_func;
2052 static const struct ptt processor_target_table[PROCESSOR_max] =
2054 {&i386_cost, 4, 3, 4, 3, 4},
2055 {&i486_cost, 16, 15, 16, 15, 16},
2056 {&pentium_cost, 16, 7, 16, 7, 16},
2057 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2058 {&geode_cost, 0, 0, 0, 0, 0},
2059 {&k6_cost, 32, 7, 32, 7, 32},
2060 {&athlon_cost, 16, 7, 16, 7, 16},
2061 {&pentium4_cost, 0, 0, 0, 0, 0},
2062 {&k8_cost, 16, 7, 16, 7, 16},
2063 {&nocona_cost, 0, 0, 0, 0, 0},
2064 {&core2_cost, 16, 10, 16, 10, 16},
2065 {&generic32_cost, 16, 7, 16, 7, 16},
2066 {&generic64_cost, 16, 10, 16, 10, 16},
2067 {&amdfam10_cost, 32, 24, 32, 7, 32},
2068 {&atom_cost, 16, 7, 16, 7, 16}
2071 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2097 /* Implement TARGET_HANDLE_OPTION. */
2100 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2107 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2108 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2112 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2113 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2120 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2121 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2125 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2136 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2141 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2149 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2154 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2162 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2167 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2175 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2180 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2188 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2193 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2201 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2206 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2207 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2214 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2219 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2220 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2227 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2228 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2232 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2233 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2238 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2239 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2243 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2244 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2250 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2251 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2255 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2256 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2263 ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
2264 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
2268 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
2269 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
2276 ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
2277 ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
2281 ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
2282 ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
2289 ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
2290 ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
2294 ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
2295 ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
2302 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2303 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2307 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2308 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2315 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2316 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2320 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2321 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2328 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2329 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2333 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2334 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2341 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2342 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2346 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2347 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2354 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2355 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2359 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2360 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2367 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2368 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2372 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2373 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2380 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2381 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2385 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2386 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2393 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2394 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2398 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2399 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2408 /* Return a string the documents the current -m options. The caller is
2409 responsible for freeing the string. */
2412 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2413 const char *fpmath, bool add_nl_p)
2415 struct ix86_target_opts
2417 const char *option; /* option string */
2418 int mask; /* isa mask options */
2421 /* This table is ordered so that options like -msse4.2 that imply
2422 preceding options while match those first. */
2423 static struct ix86_target_opts isa_opts[] =
2425 { "-m64", OPTION_MASK_ISA_64BIT },
2426 { "-mfma4", OPTION_MASK_ISA_FMA4 },
2427 { "-mxop", OPTION_MASK_ISA_XOP },
2428 { "-mlwp", OPTION_MASK_ISA_LWP },
2429 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2430 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2431 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2432 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2433 { "-msse3", OPTION_MASK_ISA_SSE3 },
2434 { "-msse2", OPTION_MASK_ISA_SSE2 },
2435 { "-msse", OPTION_MASK_ISA_SSE },
2436 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2437 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2438 { "-mmmx", OPTION_MASK_ISA_MMX },
2439 { "-mabm", OPTION_MASK_ISA_ABM },
2440 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2441 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2442 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2443 { "-maes", OPTION_MASK_ISA_AES },
2444 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2448 static struct ix86_target_opts flag_opts[] =
2450 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2451 { "-m80387", MASK_80387 },
2452 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2453 { "-malign-double", MASK_ALIGN_DOUBLE },
2454 { "-mcld", MASK_CLD },
2455 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2456 { "-mieee-fp", MASK_IEEE_FP },
2457 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2458 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2459 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2460 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2461 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2462 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2463 { "-mno-red-zone", MASK_NO_RED_ZONE },
2464 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2465 { "-mrecip", MASK_RECIP },
2466 { "-mrtd", MASK_RTD },
2467 { "-msseregparm", MASK_SSEREGPARM },
2468 { "-mstack-arg-probe", MASK_STACK_PROBE },
2469 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2472 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2475 char target_other[40];
2484 memset (opts, '\0', sizeof (opts));
2486 /* Add -march= option. */
2489 opts[num][0] = "-march=";
2490 opts[num++][1] = arch;
2493 /* Add -mtune= option. */
2496 opts[num][0] = "-mtune=";
2497 opts[num++][1] = tune;
2500 /* Pick out the options in isa options. */
2501 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2503 if ((isa & isa_opts[i].mask) != 0)
2505 opts[num++][0] = isa_opts[i].option;
2506 isa &= ~ isa_opts[i].mask;
2510 if (isa && add_nl_p)
2512 opts[num++][0] = isa_other;
2513 sprintf (isa_other, "(other isa: 0x%x)", isa);
2516 /* Add flag options. */
2517 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2519 if ((flags & flag_opts[i].mask) != 0)
2521 opts[num++][0] = flag_opts[i].option;
2522 flags &= ~ flag_opts[i].mask;
2526 if (flags && add_nl_p)
2528 opts[num++][0] = target_other;
2529 sprintf (target_other, "(other flags: 0x%x)", isa);
2532 /* Add -fpmath= option. */
2535 opts[num][0] = "-mfpmath=";
2536 opts[num++][1] = fpmath;
2543 gcc_assert (num < ARRAY_SIZE (opts));
2545 /* Size the string. */
2547 sep_len = (add_nl_p) ? 3 : 1;
2548 for (i = 0; i < num; i++)
2551 for (j = 0; j < 2; j++)
2553 len += strlen (opts[i][j]);
2556 /* Build the string. */
2557 ret = ptr = (char *) xmalloc (len);
2560 for (i = 0; i < num; i++)
2564 for (j = 0; j < 2; j++)
2565 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2572 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2580 for (j = 0; j < 2; j++)
2583 memcpy (ptr, opts[i][j], len2[j]);
2585 line_len += len2[j];
2590 gcc_assert (ret + len >= ptr);
2595 /* Function that is callable from the debugger to print the current
2598 ix86_debug_options (void)
2600 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2601 ix86_arch_string, ix86_tune_string,
2602 ix86_fpmath_string, true);
2606 fprintf (stderr, "%s\n\n", opts);
2610 fputs ("<no options>\n\n", stderr);
2615 /* Sometimes certain combinations of command options do not make
2616 sense on a particular target machine. You can define a macro
2617 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2618 defined, is executed once just after all the command options have
2621 Don't use this macro to turn on various extra optimizations for
2622 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2625 override_options (bool main_args_p)
2628 unsigned int ix86_arch_mask, ix86_tune_mask;
2633 /* Comes from final.c -- no real reason to change it. */
2634 #define MAX_CODE_ALIGN 16
2642 PTA_PREFETCH_SSE = 1 << 4,
2644 PTA_3DNOW_A = 1 << 6,
2648 PTA_POPCNT = 1 << 10,
2650 PTA_SSE4A = 1 << 12,
2651 PTA_NO_SAHF = 1 << 13,
2652 PTA_SSE4_1 = 1 << 14,
2653 PTA_SSE4_2 = 1 << 15,
2655 PTA_PCLMUL = 1 << 17,
2658 PTA_MOVBE = 1 << 20,
2666 const char *const name; /* processor name or nickname. */
2667 const enum processor_type processor;
2668 const enum attr_cpu schedule;
2669 const unsigned /*enum pta_flags*/ flags;
2671 const processor_alias_table[] =
2673 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2674 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2675 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2676 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2677 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2678 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2679 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2680 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2681 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2682 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2683 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2684 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2685 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2687 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2689 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2690 PTA_MMX | PTA_SSE | PTA_SSE2},
2691 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2692 PTA_MMX |PTA_SSE | PTA_SSE2},
2693 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2694 PTA_MMX | PTA_SSE | PTA_SSE2},
2695 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2696 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2697 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2698 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2699 | PTA_CX16 | PTA_NO_SAHF},
2700 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2701 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2702 | PTA_SSSE3 | PTA_CX16},
2703 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2704 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2705 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2706 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2707 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2708 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2709 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2710 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2711 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2712 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2713 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2714 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2715 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2716 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2717 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2718 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2719 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2720 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2721 {"x86-64", PROCESSOR_K8, CPU_K8,
2722 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2723 {"k8", PROCESSOR_K8, CPU_K8,
2724 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2725 | PTA_SSE2 | PTA_NO_SAHF},
2726 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2727 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2728 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2729 {"opteron", PROCESSOR_K8, CPU_K8,
2730 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2731 | PTA_SSE2 | PTA_NO_SAHF},
2732 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2733 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2734 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2735 {"athlon64", PROCESSOR_K8, CPU_K8,
2736 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2737 | PTA_SSE2 | PTA_NO_SAHF},
2738 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2739 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2740 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2741 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2742 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2743 | PTA_SSE2 | PTA_NO_SAHF},
2744 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2745 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2746 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2747 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2748 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2749 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2750 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2751 0 /* flags are only used for -march switch. */ },
2752 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2753 PTA_64BIT /* flags are only used for -march switch. */ },
2756 int const pta_size = ARRAY_SIZE (processor_alias_table);
2758 /* Set up prefix/suffix so the error messages refer to either the command
2759 line argument, or the attribute(target). */
2768 prefix = "option(\"";
2773 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2774 SUBTARGET_OVERRIDE_OPTIONS;
2777 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2778 SUBSUBTARGET_OVERRIDE_OPTIONS;
2781 /* -fPIC is the default for x86_64. */
2782 if (TARGET_MACHO && TARGET_64BIT)
2785 /* Set the default values for switches whose default depends on TARGET_64BIT
2786 in case they weren't overwritten by command line options. */
2789 /* Mach-O doesn't support omitting the frame pointer for now. */
2790 if (flag_omit_frame_pointer == 2)
2791 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2792 if (flag_asynchronous_unwind_tables == 2)
2793 flag_asynchronous_unwind_tables = 1;
2794 if (flag_pcc_struct_return == 2)
2795 flag_pcc_struct_return = 0;
2799 if (flag_omit_frame_pointer == 2)
2800 flag_omit_frame_pointer = 0;
2801 if (flag_asynchronous_unwind_tables == 2)
2802 flag_asynchronous_unwind_tables = 0;
2803 if (flag_pcc_struct_return == 2)
2804 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2807 /* Need to check -mtune=generic first. */
2808 if (ix86_tune_string)
2810 if (!strcmp (ix86_tune_string, "generic")
2811 || !strcmp (ix86_tune_string, "i686")
2812 /* As special support for cross compilers we read -mtune=native
2813 as -mtune=generic. With native compilers we won't see the
2814 -mtune=native, as it was changed by the driver. */
2815 || !strcmp (ix86_tune_string, "native"))
2818 ix86_tune_string = "generic64";
2820 ix86_tune_string = "generic32";
2822 /* If this call is for setting the option attribute, allow the
2823 generic32/generic64 that was previously set. */
2824 else if (!main_args_p
2825 && (!strcmp (ix86_tune_string, "generic32")
2826 || !strcmp (ix86_tune_string, "generic64")))
2828 else if (!strncmp (ix86_tune_string, "generic", 7))
2829 error ("bad value (%s) for %stune=%s %s",
2830 ix86_tune_string, prefix, suffix, sw);
2834 if (ix86_arch_string)
2835 ix86_tune_string = ix86_arch_string;
2836 if (!ix86_tune_string)
2838 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2839 ix86_tune_defaulted = 1;
2842 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2843 need to use a sensible tune option. */
2844 if (!strcmp (ix86_tune_string, "generic")
2845 || !strcmp (ix86_tune_string, "x86-64")
2846 || !strcmp (ix86_tune_string, "i686"))
2849 ix86_tune_string = "generic64";
2851 ix86_tune_string = "generic32";
2854 if (ix86_stringop_string)
2856 if (!strcmp (ix86_stringop_string, "rep_byte"))
2857 stringop_alg = rep_prefix_1_byte;
2858 else if (!strcmp (ix86_stringop_string, "libcall"))
2859 stringop_alg = libcall;
2860 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2861 stringop_alg = rep_prefix_4_byte;
2862 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2864 /* rep; movq isn't available in 32-bit code. */
2865 stringop_alg = rep_prefix_8_byte;
2866 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2867 stringop_alg = loop_1_byte;
2868 else if (!strcmp (ix86_stringop_string, "loop"))
2869 stringop_alg = loop;
2870 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2871 stringop_alg = unrolled_loop;
2873 error ("bad value (%s) for %sstringop-strategy=%s %s",
2874 ix86_stringop_string, prefix, suffix, sw);
2876 if (!strcmp (ix86_tune_string, "x86-64"))
2877 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2878 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2879 prefix, suffix, prefix, suffix, prefix, suffix);
2881 if (!ix86_arch_string)
2882 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2884 ix86_arch_specified = 1;
2886 if (!strcmp (ix86_arch_string, "generic"))
2887 error ("generic CPU can be used only for %stune=%s %s",
2888 prefix, suffix, sw);
2889 if (!strncmp (ix86_arch_string, "generic", 7))
2890 error ("bad value (%s) for %sarch=%s %s",
2891 ix86_arch_string, prefix, suffix, sw);
2893 /* Validate -mabi= value. */
2894 if (ix86_abi_string)
2896 if (strcmp (ix86_abi_string, "sysv") == 0)
2897 ix86_abi = SYSV_ABI;
2898 else if (strcmp (ix86_abi_string, "ms") == 0)
2901 error ("unknown ABI (%s) for %sabi=%s %s",
2902 ix86_abi_string, prefix, suffix, sw);
2905 ix86_abi = DEFAULT_ABI;
2907 if (ix86_cmodel_string != 0)
2909 if (!strcmp (ix86_cmodel_string, "small"))
2910 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2911 else if (!strcmp (ix86_cmodel_string, "medium"))
2912 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2913 else if (!strcmp (ix86_cmodel_string, "large"))
2914 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2916 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2917 else if (!strcmp (ix86_cmodel_string, "32"))
2918 ix86_cmodel = CM_32;
2919 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2920 ix86_cmodel = CM_KERNEL;
2922 error ("bad value (%s) for %scmodel=%s %s",
2923 ix86_cmodel_string, prefix, suffix, sw);
2927 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2928 use of rip-relative addressing. This eliminates fixups that
2929 would otherwise be needed if this object is to be placed in a
2930 DLL, and is essentially just as efficient as direct addressing. */
2931 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2932 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2933 else if (TARGET_64BIT)
2934 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2936 ix86_cmodel = CM_32;
2938 if (ix86_asm_string != 0)
2941 && !strcmp (ix86_asm_string, "intel"))
2942 ix86_asm_dialect = ASM_INTEL;
2943 else if (!strcmp (ix86_asm_string, "att"))
2944 ix86_asm_dialect = ASM_ATT;
2946 error ("bad value (%s) for %sasm=%s %s",
2947 ix86_asm_string, prefix, suffix, sw);
2949 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2950 error ("code model %qs not supported in the %s bit mode",
2951 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2952 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2953 sorry ("%i-bit mode not compiled in",
2954 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2956 for (i = 0; i < pta_size; i++)
2957 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2959 ix86_schedule = processor_alias_table[i].schedule;
2960 ix86_arch = processor_alias_table[i].processor;
2961 /* Default cpu tuning to the architecture. */
2962 ix86_tune = ix86_arch;
2964 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2965 error ("CPU you selected does not support x86-64 "
2968 if (processor_alias_table[i].flags & PTA_MMX
2969 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2970 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2971 if (processor_alias_table[i].flags & PTA_3DNOW
2972 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2973 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2974 if (processor_alias_table[i].flags & PTA_3DNOW_A
2975 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2976 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2977 if (processor_alias_table[i].flags & PTA_SSE
2978 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2979 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2980 if (processor_alias_table[i].flags & PTA_SSE2
2981 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2982 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2983 if (processor_alias_table[i].flags & PTA_SSE3
2984 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2985 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2986 if (processor_alias_table[i].flags & PTA_SSSE3
2987 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2988 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2989 if (processor_alias_table[i].flags & PTA_SSE4_1
2990 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2991 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2992 if (processor_alias_table[i].flags & PTA_SSE4_2
2993 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2994 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2995 if (processor_alias_table[i].flags & PTA_AVX
2996 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2997 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2998 if (processor_alias_table[i].flags & PTA_FMA
2999 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
3000 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
3001 if (processor_alias_table[i].flags & PTA_SSE4A
3002 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
3003 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
3004 if (processor_alias_table[i].flags & PTA_FMA4
3005 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
3006 ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
3007 if (processor_alias_table[i].flags & PTA_XOP
3008 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
3009 ix86_isa_flags |= OPTION_MASK_ISA_XOP;
3010 if (processor_alias_table[i].flags & PTA_LWP
3011 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
3012 ix86_isa_flags |= OPTION_MASK_ISA_LWP;
3013 if (processor_alias_table[i].flags & PTA_ABM
3014 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
3015 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
3016 if (processor_alias_table[i].flags & PTA_CX16
3017 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
3018 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
3019 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
3020 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
3021 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
3022 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
3023 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
3024 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
3025 if (processor_alias_table[i].flags & PTA_MOVBE
3026 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
3027 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
3028 if (processor_alias_table[i].flags & PTA_AES
3029 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
3030 ix86_isa_flags |= OPTION_MASK_ISA_AES;
3031 if (processor_alias_table[i].flags & PTA_PCLMUL
3032 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
3033 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
3034 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
3035 x86_prefetch_sse = true;
3041 error ("bad value (%s) for %sarch=%s %s",
3042 ix86_arch_string, prefix, suffix, sw);
3044 ix86_arch_mask = 1u << ix86_arch;
3045 for (i = 0; i < X86_ARCH_LAST; ++i)
3046 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3048 for (i = 0; i < pta_size; i++)
3049 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
3051 ix86_schedule = processor_alias_table[i].schedule;
3052 ix86_tune = processor_alias_table[i].processor;
3053 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
3055 if (ix86_tune_defaulted)
3057 ix86_tune_string = "x86-64";
3058 for (i = 0; i < pta_size; i++)
3059 if (! strcmp (ix86_tune_string,
3060 processor_alias_table[i].name))
3062 ix86_schedule = processor_alias_table[i].schedule;
3063 ix86_tune = processor_alias_table[i].processor;
3066 error ("CPU you selected does not support x86-64 "
3069 /* Intel CPUs have always interpreted SSE prefetch instructions as
3070 NOPs; so, we can enable SSE prefetch instructions even when
3071 -mtune (rather than -march) points us to a processor that has them.
3072 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3073 higher processors. */
3075 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3076 x86_prefetch_sse = true;
3080 error ("bad value (%s) for %stune=%s %s",
3081 ix86_tune_string, prefix, suffix, sw);
3083 ix86_tune_mask = 1u << ix86_tune;
3084 for (i = 0; i < X86_TUNE_LAST; ++i)
3085 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3088 ix86_cost = &ix86_size_cost;
3090 ix86_cost = processor_target_table[ix86_tune].cost;
3092 /* Arrange to set up i386_stack_locals for all functions. */
3093 init_machine_status = ix86_init_machine_status;
3095 /* Validate -mregparm= value. */
3096 if (ix86_regparm_string)
3099 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3100 i = atoi (ix86_regparm_string);
3101 if (i < 0 || i > REGPARM_MAX)
3102 error ("%sregparm=%d%s is not between 0 and %d",
3103 prefix, i, suffix, REGPARM_MAX);
3108 ix86_regparm = REGPARM_MAX;
3110 /* If the user has provided any of the -malign-* options,
3111 warn and use that value only if -falign-* is not set.
3112 Remove this code in GCC 3.2 or later. */
3113 if (ix86_align_loops_string)
3115 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3116 prefix, suffix, suffix);
3117 if (align_loops == 0)
3119 i = atoi (ix86_align_loops_string);
3120 if (i < 0 || i > MAX_CODE_ALIGN)
3121 error ("%salign-loops=%d%s is not between 0 and %d",
3122 prefix, i, suffix, MAX_CODE_ALIGN);
3124 align_loops = 1 << i;
3128 if (ix86_align_jumps_string)
3130 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3131 prefix, suffix, suffix);
3132 if (align_jumps == 0)
3134 i = atoi (ix86_align_jumps_string);
3135 if (i < 0 || i > MAX_CODE_ALIGN)
3136 error ("%salign-loops=%d%s is not between 0 and %d",
3137 prefix, i, suffix, MAX_CODE_ALIGN);
3139 align_jumps = 1 << i;
3143 if (ix86_align_funcs_string)
3145 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3146 prefix, suffix, suffix);
3147 if (align_functions == 0)
3149 i = atoi (ix86_align_funcs_string);
3150 if (i < 0 || i > MAX_CODE_ALIGN)
3151 error ("%salign-loops=%d%s is not between 0 and %d",
3152 prefix, i, suffix, MAX_CODE_ALIGN);
3154 align_functions = 1 << i;
3158 /* Default align_* from the processor table. */
3159 if (align_loops == 0)
3161 align_loops = processor_target_table[ix86_tune].align_loop;
3162 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3164 if (align_jumps == 0)
3166 align_jumps = processor_target_table[ix86_tune].align_jump;
3167 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3169 if (align_functions == 0)
3171 align_functions = processor_target_table[ix86_tune].align_func;
3174 /* Validate -mbranch-cost= value, or provide default. */
3175 ix86_branch_cost = ix86_cost->branch_cost;
3176 if (ix86_branch_cost_string)
3178 i = atoi (ix86_branch_cost_string);
3180 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3182 ix86_branch_cost = i;
3184 if (ix86_section_threshold_string)
3186 i = atoi (ix86_section_threshold_string);
3188 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3190 ix86_section_threshold = i;
3193 if (ix86_tls_dialect_string)
3195 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3196 ix86_tls_dialect = TLS_DIALECT_GNU;
3197 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3198 ix86_tls_dialect = TLS_DIALECT_GNU2;
3199 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3200 ix86_tls_dialect = TLS_DIALECT_SUN;
3202 error ("bad value (%s) for %stls-dialect=%s %s",
3203 ix86_tls_dialect_string, prefix, suffix, sw);
3206 if (ix87_precision_string)
3208 i = atoi (ix87_precision_string);
3209 if (i != 32 && i != 64 && i != 80)
3210 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3215 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3217 /* Enable by default the SSE and MMX builtins. Do allow the user to
3218 explicitly disable any of these. In particular, disabling SSE and
3219 MMX for kernel code is extremely useful. */
3220 if (!ix86_arch_specified)
3222 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3223 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3226 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3230 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3232 if (!ix86_arch_specified)
3234 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3236 /* i386 ABI does not specify red zone. It still makes sense to use it
3237 when programmer takes care to stack from being destroyed. */
3238 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3239 target_flags |= MASK_NO_RED_ZONE;
3242 /* Keep nonleaf frame pointers. */
3243 if (flag_omit_frame_pointer)
3244 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3245 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3246 flag_omit_frame_pointer = 1;
3248 /* If we're doing fast math, we don't care about comparison order
3249 wrt NaNs. This lets us use a shorter comparison sequence. */
3250 if (flag_finite_math_only)
3251 target_flags &= ~MASK_IEEE_FP;
3253 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3254 since the insns won't need emulation. */
3255 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3256 target_flags &= ~MASK_NO_FANCY_MATH_387;
3258 /* Likewise, if the target doesn't have a 387, or we've specified
3259 software floating point, don't use 387 inline intrinsics. */
3261 target_flags |= MASK_NO_FANCY_MATH_387;
3263 /* Turn on MMX builtins for -msse. */
3266 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3267 x86_prefetch_sse = true;
3270 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3271 if (TARGET_SSE4_2 || TARGET_ABM)
3272 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3274 /* Validate -mpreferred-stack-boundary= value or default it to
3275 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3276 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3277 if (ix86_preferred_stack_boundary_string)
3279 i = atoi (ix86_preferred_stack_boundary_string);
3280 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3281 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3282 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3284 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3287 /* Set the default value for -mstackrealign. */
3288 if (ix86_force_align_arg_pointer == -1)
3289 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3291 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3293 /* Validate -mincoming-stack-boundary= value or default it to
3294 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3295 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3296 if (ix86_incoming_stack_boundary_string)
3298 i = atoi (ix86_incoming_stack_boundary_string);
3299 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3300 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3301 i, TARGET_64BIT ? 4 : 2);
3304 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3305 ix86_incoming_stack_boundary
3306 = ix86_user_incoming_stack_boundary;
3310 /* Accept -msseregparm only if at least SSE support is enabled. */
3311 if (TARGET_SSEREGPARM
3313 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3315 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3316 if (ix86_fpmath_string != 0)
3318 if (! strcmp (ix86_fpmath_string, "387"))
3319 ix86_fpmath = FPMATH_387;
3320 else if (! strcmp (ix86_fpmath_string, "sse"))
3324 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3325 ix86_fpmath = FPMATH_387;
3328 ix86_fpmath = FPMATH_SSE;
3330 else if (! strcmp (ix86_fpmath_string, "387,sse")
3331 || ! strcmp (ix86_fpmath_string, "387+sse")
3332 || ! strcmp (ix86_fpmath_string, "sse,387")
3333 || ! strcmp (ix86_fpmath_string, "sse+387")
3334 || ! strcmp (ix86_fpmath_string, "both"))
3338 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3339 ix86_fpmath = FPMATH_387;
3341 else if (!TARGET_80387)
3343 warning (0, "387 instruction set disabled, using SSE arithmetics");
3344 ix86_fpmath = FPMATH_SSE;
3347 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3350 error ("bad value (%s) for %sfpmath=%s %s",
3351 ix86_fpmath_string, prefix, suffix, sw);
3354 /* If the i387 is disabled, then do not return values in it. */
3356 target_flags &= ~MASK_FLOAT_RETURNS;
3358 /* Use external vectorized library in vectorizing intrinsics. */
3359 if (ix86_veclibabi_string)
3361 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3362 ix86_veclib_handler = ix86_veclibabi_svml;
3363 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3364 ix86_veclib_handler = ix86_veclibabi_acml;
3366 error ("unknown vectorization library ABI type (%s) for "
3367 "%sveclibabi=%s %s", ix86_veclibabi_string,
3368 prefix, suffix, sw);
3371 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3372 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3374 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3376 /* ??? Unwind info is not correct around the CFG unless either a frame
3377 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3378 unwind info generation to be aware of the CFG and propagating states
3380 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3381 || flag_exceptions || flag_non_call_exceptions)
3382 && flag_omit_frame_pointer
3383 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3385 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3386 warning (0, "unwind tables currently require either a frame pointer "
3387 "or %saccumulate-outgoing-args%s for correctness",
3389 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3392 /* If stack probes are required, the space used for large function
3393 arguments on the stack must also be probed, so enable
3394 -maccumulate-outgoing-args so this happens in the prologue. */
3395 if (TARGET_STACK_PROBE
3396 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3398 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3399 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3400 "for correctness", prefix, suffix);
3401 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3404 /* For sane SSE instruction set generation we need fcomi instruction.
3405 It is safe to enable all CMOVE instructions. */
3409 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3412 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3413 p = strchr (internal_label_prefix, 'X');
3414 internal_label_prefix_len = p - internal_label_prefix;
3418 /* When scheduling description is not available, disable scheduler pass
3419 so it won't slow down the compilation and make x87 code slower. */
3420 if (!TARGET_SCHEDULE)
3421 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3423 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3424 set_param_value ("simultaneous-prefetches",
3425 ix86_cost->simultaneous_prefetches);
3426 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3427 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3428 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3429 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3430 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3431 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3433 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3434 can be optimized to ap = __builtin_next_arg (0). */
3436 targetm.expand_builtin_va_start = NULL;
3440 ix86_gen_leave = gen_leave_rex64;
3441 ix86_gen_pop1 = gen_popdi1;
3442 ix86_gen_add3 = gen_adddi3;
3443 ix86_gen_sub3 = gen_subdi3;
3444 ix86_gen_sub3_carry = gen_subdi3_carry;
3445 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3446 ix86_gen_monitor = gen_sse3_monitor64;
3447 ix86_gen_andsp = gen_anddi3;
3451 ix86_gen_leave = gen_leave;
3452 ix86_gen_pop1 = gen_popsi1;
3453 ix86_gen_add3 = gen_addsi3;
3454 ix86_gen_sub3 = gen_subsi3;
3455 ix86_gen_sub3_carry = gen_subsi3_carry;
3456 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3457 ix86_gen_monitor = gen_sse3_monitor;
3458 ix86_gen_andsp = gen_andsi3;
3462 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3464 target_flags |= MASK_CLD & ~target_flags_explicit;
3467 /* Save the initial options in case the user does function specific options */
3469 target_option_default_node = target_option_current_node
3470 = build_target_option_node ();
3473 /* Update register usage after having seen the compiler flags. */
3476 ix86_conditional_register_usage (void)
3481 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3483 if (fixed_regs[i] > 1)
3484 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3485 if (call_used_regs[i] > 1)
3486 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3489 /* The PIC register, if it exists, is fixed. */
3490 j = PIC_OFFSET_TABLE_REGNUM;
3491 if (j != INVALID_REGNUM)
3492 fixed_regs[j] = call_used_regs[j] = 1;
3494 /* The MS_ABI changes the set of call-used registers. */
3495 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3497 call_used_regs[SI_REG] = 0;
3498 call_used_regs[DI_REG] = 0;
3499 call_used_regs[XMM6_REG] = 0;
3500 call_used_regs[XMM7_REG] = 0;
3501 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3502 call_used_regs[i] = 0;
3505 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3506 other call-clobbered regs for 64-bit. */
3509 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3511 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3512 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3513 && call_used_regs[i])
3514 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3517 /* If MMX is disabled, squash the registers. */
3519 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3520 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3521 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3523 /* If SSE is disabled, squash the registers. */
3525 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3526 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3527 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3529 /* If the FPU is disabled, squash the registers. */
3530 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3531 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3532 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3533 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3535 /* If 32-bit, squash the 64-bit registers. */
3538 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3540 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3546 /* Save the current options */
3549 ix86_function_specific_save (struct cl_target_option *ptr)
3551 ptr->arch = ix86_arch;
3552 ptr->schedule = ix86_schedule;
3553 ptr->tune = ix86_tune;
3554 ptr->fpmath = ix86_fpmath;
3555 ptr->branch_cost = ix86_branch_cost;
3556 ptr->tune_defaulted = ix86_tune_defaulted;
3557 ptr->arch_specified = ix86_arch_specified;
3558 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3559 ptr->target_flags_explicit = target_flags_explicit;
3561 /* The fields are char but the variables are not; make sure the
3562 values fit in the fields. */
3563 gcc_assert (ptr->arch == ix86_arch);
3564 gcc_assert (ptr->schedule == ix86_schedule);
3565 gcc_assert (ptr->tune == ix86_tune);
3566 gcc_assert (ptr->fpmath == ix86_fpmath);
3567 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3570 /* Restore the current options */
3573 ix86_function_specific_restore (struct cl_target_option *ptr)
3575 enum processor_type old_tune = ix86_tune;
3576 enum processor_type old_arch = ix86_arch;
3577 unsigned int ix86_arch_mask, ix86_tune_mask;
3580 ix86_arch = (enum processor_type) ptr->arch;
3581 ix86_schedule = (enum attr_cpu) ptr->schedule;
3582 ix86_tune = (enum processor_type) ptr->tune;
3583 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3584 ix86_branch_cost = ptr->branch_cost;
3585 ix86_tune_defaulted = ptr->tune_defaulted;
3586 ix86_arch_specified = ptr->arch_specified;
3587 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3588 target_flags_explicit = ptr->target_flags_explicit;
3590 /* Recreate the arch feature tests if the arch changed */
3591 if (old_arch != ix86_arch)
3593 ix86_arch_mask = 1u << ix86_arch;
3594 for (i = 0; i < X86_ARCH_LAST; ++i)
3595 ix86_arch_features[i]
3596 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3599 /* Recreate the tune optimization tests */
3600 if (old_tune != ix86_tune)
3602 ix86_tune_mask = 1u << ix86_tune;
3603 for (i = 0; i < X86_TUNE_LAST; ++i)
3604 ix86_tune_features[i]
3605 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3609 /* Print the current options */
3612 ix86_function_specific_print (FILE *file, int indent,
3613 struct cl_target_option *ptr)
3616 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3617 NULL, NULL, NULL, false);
3619 fprintf (file, "%*sarch = %d (%s)\n",
3622 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3623 ? cpu_names[ptr->arch]
3626 fprintf (file, "%*stune = %d (%s)\n",
3629 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3630 ? cpu_names[ptr->tune]
3633 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3634 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3635 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3636 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3640 fprintf (file, "%*s%s\n", indent, "", target_string);
3641 free (target_string);
3646 /* Inner function to process the attribute((target(...))), take an argument and
3647 set the current options from the argument. If we have a list, recursively go
3651 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3656 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3657 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3658 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3659 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3674 enum ix86_opt_type type;
3679 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3680 IX86_ATTR_ISA ("abm", OPT_mabm),
3681 IX86_ATTR_ISA ("aes", OPT_maes),
3682 IX86_ATTR_ISA ("avx", OPT_mavx),
3683 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3684 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3685 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3686 IX86_ATTR_ISA ("sse", OPT_msse),
3687 IX86_ATTR_ISA ("sse2", OPT_msse2),
3688 IX86_ATTR_ISA ("sse3", OPT_msse3),
3689 IX86_ATTR_ISA ("sse4", OPT_msse4),
3690 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3691 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3692 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3693 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3694 IX86_ATTR_ISA ("fma4", OPT_mfma4),
3695 IX86_ATTR_ISA ("xop", OPT_mxop),
3696 IX86_ATTR_ISA ("lwp", OPT_mlwp),
3698 /* string options */
3699 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3700 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3701 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3704 IX86_ATTR_YES ("cld",
3708 IX86_ATTR_NO ("fancy-math-387",
3709 OPT_mfancy_math_387,
3710 MASK_NO_FANCY_MATH_387),
3712 IX86_ATTR_YES ("ieee-fp",
3716 IX86_ATTR_YES ("inline-all-stringops",
3717 OPT_minline_all_stringops,
3718 MASK_INLINE_ALL_STRINGOPS),
3720 IX86_ATTR_YES ("inline-stringops-dynamically",
3721 OPT_minline_stringops_dynamically,
3722 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3724 IX86_ATTR_NO ("align-stringops",
3725 OPT_mno_align_stringops,
3726 MASK_NO_ALIGN_STRINGOPS),
3728 IX86_ATTR_YES ("recip",
3734 /* If this is a list, recurse to get the options. */
3735 if (TREE_CODE (args) == TREE_LIST)
3739 for (; args; args = TREE_CHAIN (args))
3740 if (TREE_VALUE (args)
3741 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3747 else if (TREE_CODE (args) != STRING_CST)
3750 /* Handle multiple arguments separated by commas. */
3751 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3753 while (next_optstr && *next_optstr != '\0')
3755 char *p = next_optstr;
3757 char *comma = strchr (next_optstr, ',');
3758 const char *opt_string;
3759 size_t len, opt_len;
3764 enum ix86_opt_type type = ix86_opt_unknown;
3770 len = comma - next_optstr;
3771 next_optstr = comma + 1;
3779 /* Recognize no-xxx. */
3780 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3789 /* Find the option. */
3792 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3794 type = attrs[i].type;
3795 opt_len = attrs[i].len;
3796 if (ch == attrs[i].string[0]
3797 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3798 && memcmp (p, attrs[i].string, opt_len) == 0)
3801 mask = attrs[i].mask;
3802 opt_string = attrs[i].string;
3807 /* Process the option. */
3810 error ("attribute(target(\"%s\")) is unknown", orig_p);
3814 else if (type == ix86_opt_isa)
3815 ix86_handle_option (opt, p, opt_set_p);
3817 else if (type == ix86_opt_yes || type == ix86_opt_no)
3819 if (type == ix86_opt_no)
3820 opt_set_p = !opt_set_p;
3823 target_flags |= mask;
3825 target_flags &= ~mask;
3828 else if (type == ix86_opt_str)
3832 error ("option(\"%s\") was already specified", opt_string);
3836 p_strings[opt] = xstrdup (p + opt_len);
3846 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3849 ix86_valid_target_attribute_tree (tree args)
3851 const char *orig_arch_string = ix86_arch_string;
3852 const char *orig_tune_string = ix86_tune_string;
3853 const char *orig_fpmath_string = ix86_fpmath_string;
3854 int orig_tune_defaulted = ix86_tune_defaulted;
3855 int orig_arch_specified = ix86_arch_specified;
3856 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3859 struct cl_target_option *def
3860 = TREE_TARGET_OPTION (target_option_default_node);
3862 /* Process each of the options on the chain. */
3863 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3866 /* If the changed options are different from the default, rerun override_options,
3867 and then save the options away. The string options are are attribute options,
3868 and will be undone when we copy the save structure. */
3869 if (ix86_isa_flags != def->ix86_isa_flags
3870 || target_flags != def->target_flags
3871 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3872 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3873 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3875 /* If we are using the default tune= or arch=, undo the string assigned,
3876 and use the default. */
3877 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3878 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3879 else if (!orig_arch_specified)
3880 ix86_arch_string = NULL;
3882 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3883 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3884 else if (orig_tune_defaulted)
3885 ix86_tune_string = NULL;
3887 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3888 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3889 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3890 else if (!TARGET_64BIT && TARGET_SSE)
3891 ix86_fpmath_string = "sse,387";
3893 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3894 override_options (false);
3896 /* Add any builtin functions with the new isa if any. */
3897 ix86_add_new_builtins (ix86_isa_flags);
3899 /* Save the current options unless we are validating options for
3901 t = build_target_option_node ();
3903 ix86_arch_string = orig_arch_string;
3904 ix86_tune_string = orig_tune_string;
3905 ix86_fpmath_string = orig_fpmath_string;
3907 /* Free up memory allocated to hold the strings */
3908 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3909 if (option_strings[i])
3910 free (option_strings[i]);
3916 /* Hook to validate attribute((target("string"))). */
3919 ix86_valid_target_attribute_p (tree fndecl,
3920 tree ARG_UNUSED (name),
3922 int ARG_UNUSED (flags))
3924 struct cl_target_option cur_target;
3926 tree old_optimize = build_optimization_node ();
3927 tree new_target, new_optimize;
3928 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3930 /* If the function changed the optimization levels as well as setting target
3931 options, start with the optimizations specified. */
3932 if (func_optimize && func_optimize != old_optimize)
3933 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3935 /* The target attributes may also change some optimization flags, so update
3936 the optimization options if necessary. */
3937 cl_target_option_save (&cur_target);
3938 new_target = ix86_valid_target_attribute_tree (args);
3939 new_optimize = build_optimization_node ();
3946 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3948 if (old_optimize != new_optimize)
3949 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3952 cl_target_option_restore (&cur_target);
3954 if (old_optimize != new_optimize)
3955 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3961 /* Hook to determine if one function can safely inline another. */
3964 ix86_can_inline_p (tree caller, tree callee)
3967 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3968 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3970 /* If callee has no option attributes, then it is ok to inline. */
3974 /* If caller has no option attributes, but callee does then it is not ok to
3976 else if (!caller_tree)
3981 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3982 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3984 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3985 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3987 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3988 != callee_opts->ix86_isa_flags)
3991 /* See if we have the same non-isa options. */
3992 else if (caller_opts->target_flags != callee_opts->target_flags)
3995 /* See if arch, tune, etc. are the same. */
3996 else if (caller_opts->arch != callee_opts->arch)
3999 else if (caller_opts->tune != callee_opts->tune)
4002 else if (caller_opts->fpmath != callee_opts->fpmath)
4005 else if (caller_opts->branch_cost != callee_opts->branch_cost)
4016 /* Remember the last target of ix86_set_current_function. */
4017 static GTY(()) tree ix86_previous_fndecl;
4019 /* Establish appropriate back-end context for processing the function
4020 FNDECL. The argument might be NULL to indicate processing at top
4021 level, outside of any function scope. */
4023 ix86_set_current_function (tree fndecl)
4025 /* Only change the context if the function changes. This hook is called
4026 several times in the course of compiling a function, and we don't want to
4027 slow things down too much or call target_reinit when it isn't safe. */
4028 if (fndecl && fndecl != ix86_previous_fndecl)
4030 tree old_tree = (ix86_previous_fndecl
4031 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
4034 tree new_tree = (fndecl
4035 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
4038 ix86_previous_fndecl = fndecl;
4039 if (old_tree == new_tree)
4044 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
4050 struct cl_target_option *def
4051 = TREE_TARGET_OPTION (target_option_current_node);
4053 cl_target_option_restore (def);
4060 /* Return true if this goes in large data/bss. */
4063 ix86_in_large_data_p (tree exp)
4065 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
4068 /* Functions are never large data. */
4069 if (TREE_CODE (exp) == FUNCTION_DECL)
4072 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
4074 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
4075 if (strcmp (section, ".ldata") == 0
4076 || strcmp (section, ".lbss") == 0)
4082 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4084 /* If this is an incomplete type with size 0, then we can't put it
4085 in data because it might be too big when completed. */
4086 if (!size || size > ix86_section_threshold)
4093 /* Switch to the appropriate section for output of DECL.
4094 DECL is either a `VAR_DECL' node or a constant of some sort.
4095 RELOC indicates whether forming the initial value of DECL requires
4096 link-time relocations. */
4098 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4102 x86_64_elf_select_section (tree decl, int reloc,
4103 unsigned HOST_WIDE_INT align)
4105 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4106 && ix86_in_large_data_p (decl))
4108 const char *sname = NULL;
4109 unsigned int flags = SECTION_WRITE;
4110 switch (categorize_decl_for_section (decl, reloc))
4115 case SECCAT_DATA_REL:
4116 sname = ".ldata.rel";
4118 case SECCAT_DATA_REL_LOCAL:
4119 sname = ".ldata.rel.local";
4121 case SECCAT_DATA_REL_RO:
4122 sname = ".ldata.rel.ro";
4124 case SECCAT_DATA_REL_RO_LOCAL:
4125 sname = ".ldata.rel.ro.local";
4129 flags |= SECTION_BSS;
4132 case SECCAT_RODATA_MERGE_STR:
4133 case SECCAT_RODATA_MERGE_STR_INIT:
4134 case SECCAT_RODATA_MERGE_CONST:
4138 case SECCAT_SRODATA:
4145 /* We don't split these for medium model. Place them into
4146 default sections and hope for best. */
4148 case SECCAT_EMUTLS_VAR:
4149 case SECCAT_EMUTLS_TMPL:
4154 /* We might get called with string constants, but get_named_section
4155 doesn't like them as they are not DECLs. Also, we need to set
4156 flags in that case. */
4158 return get_section (sname, flags, NULL);
4159 return get_named_section (decl, sname, reloc);
4162 return default_elf_select_section (decl, reloc, align);
4165 /* Build up a unique section name, expressed as a
4166 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4167 RELOC indicates whether the initial value of EXP requires
4168 link-time relocations. */
4170 static void ATTRIBUTE_UNUSED
4171 x86_64_elf_unique_section (tree decl, int reloc)
4173 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4174 && ix86_in_large_data_p (decl))
4176 const char *prefix = NULL;
4177 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4178 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4180 switch (categorize_decl_for_section (decl, reloc))
4183 case SECCAT_DATA_REL:
4184 case SECCAT_DATA_REL_LOCAL:
4185 case SECCAT_DATA_REL_RO:
4186 case SECCAT_DATA_REL_RO_LOCAL:
4187 prefix = one_only ? ".ld" : ".ldata";
4190 prefix = one_only ? ".lb" : ".lbss";
4193 case SECCAT_RODATA_MERGE_STR:
4194 case SECCAT_RODATA_MERGE_STR_INIT:
4195 case SECCAT_RODATA_MERGE_CONST:
4196 prefix = one_only ? ".lr" : ".lrodata";
4198 case SECCAT_SRODATA:
4205 /* We don't split these for medium model. Place them into
4206 default sections and hope for best. */
4208 case SECCAT_EMUTLS_VAR:
4209 prefix = targetm.emutls.var_section;
4211 case SECCAT_EMUTLS_TMPL:
4212 prefix = targetm.emutls.tmpl_section;
4217 const char *name, *linkonce;
4220 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4221 name = targetm.strip_name_encoding (name);
4223 /* If we're using one_only, then there needs to be a .gnu.linkonce
4224 prefix to the section name. */
4225 linkonce = one_only ? ".gnu.linkonce" : "";
4227 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4229 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4233 default_unique_section (decl, reloc);
4236 #ifdef COMMON_ASM_OP
4237 /* This says how to output assembler code to declare an
4238 uninitialized external linkage data object.
4240 For medium model x86-64 we need to use .largecomm opcode for
4243 x86_elf_aligned_common (FILE *file,
4244 const char *name, unsigned HOST_WIDE_INT size,
4247 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4248 && size > (unsigned int)ix86_section_threshold)
4249 fputs (".largecomm\t", file);
4251 fputs (COMMON_ASM_OP, file);
4252 assemble_name (file, name);
4253 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4254 size, align / BITS_PER_UNIT);
4258 /* Utility function for targets to use in implementing
4259 ASM_OUTPUT_ALIGNED_BSS. */
4262 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4263 const char *name, unsigned HOST_WIDE_INT size,
4266 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4267 && size > (unsigned int)ix86_section_threshold)
4268 switch_to_section (get_named_section (decl, ".lbss", 0));
4270 switch_to_section (bss_section);
4271 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4272 #ifdef ASM_DECLARE_OBJECT_NAME
4273 last_assemble_variable_decl = decl;
4274 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4276 /* Standard thing is just output label for the object. */
4277 ASM_OUTPUT_LABEL (file, name);
4278 #endif /* ASM_DECLARE_OBJECT_NAME */
4279 ASM_OUTPUT_SKIP (file, size ? size : 1);
4283 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4285 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4286 make the problem with not enough registers even worse. */
4287 #ifdef INSN_SCHEDULING
4289 flag_schedule_insns = 0;
4293 /* The Darwin libraries never set errno, so we might as well
4294 avoid calling them when that's the only reason we would. */
4295 flag_errno_math = 0;
4297 /* The default values of these switches depend on the TARGET_64BIT
4298 that is not known at this moment. Mark these values with 2 and
4299 let user the to override these. In case there is no command line option
4300 specifying them, we will set the defaults in override_options. */
4302 flag_omit_frame_pointer = 2;
4303 flag_pcc_struct_return = 2;
4304 flag_asynchronous_unwind_tables = 2;
4305 flag_vect_cost_model = 1;
4306 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4307 SUBTARGET_OPTIMIZATION_OPTIONS;
4311 /* Decide whether we can make a sibling call to a function. DECL is the
4312 declaration of the function being targeted by the call and EXP is the
4313 CALL_EXPR representing the call. */
4316 ix86_function_ok_for_sibcall (tree decl, tree exp)
4318 tree type, decl_or_type;
4321 /* If we are generating position-independent code, we cannot sibcall
4322 optimize any indirect call, or a direct call to a global function,
4323 as the PLT requires %ebx be live. */
4324 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4327 /* If we need to align the outgoing stack, then sibcalling would
4328 unalign the stack, which may break the called function. */
4329 if (ix86_minimum_incoming_stack_boundary (true)
4330 < PREFERRED_STACK_BOUNDARY)
4335 decl_or_type = decl;
4336 type = TREE_TYPE (decl);
4340 /* We're looking at the CALL_EXPR, we need the type of the function. */
4341 type = CALL_EXPR_FN (exp); /* pointer expression */
4342 type = TREE_TYPE (type); /* pointer type */
4343 type = TREE_TYPE (type); /* function type */
4344 decl_or_type = type;
4347 /* Check that the return value locations are the same. Like
4348 if we are returning floats on the 80387 register stack, we cannot
4349 make a sibcall from a function that doesn't return a float to a
4350 function that does or, conversely, from a function that does return
4351 a float to a function that doesn't; the necessary stack adjustment
4352 would not be executed. This is also the place we notice
4353 differences in the return value ABI. Note that it is ok for one
4354 of the functions to have void return type as long as the return
4355 value of the other is passed in a register. */
4356 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4357 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4359 if (STACK_REG_P (a) || STACK_REG_P (b))
4361 if (!rtx_equal_p (a, b))
4364 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4366 else if (!rtx_equal_p (a, b))
4371 /* The SYSV ABI has more call-clobbered registers;
4372 disallow sibcalls from MS to SYSV. */
4373 if (cfun->machine->call_abi == MS_ABI
4374 && ix86_function_type_abi (type) == SYSV_ABI)
4379 /* If this call is indirect, we'll need to be able to use a
4380 call-clobbered register for the address of the target function.
4381 Make sure that all such registers are not used for passing
4382 parameters. Note that DLLIMPORT functions are indirect. */
4384 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4386 if (ix86_function_regparm (type, NULL) >= 3)
4388 /* ??? Need to count the actual number of registers to be used,
4389 not the possible number of registers. Fix later. */
4395 /* Otherwise okay. That also includes certain types of indirect calls. */
4399 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4400 calling convention attributes;
4401 arguments as in struct attribute_spec.handler. */
4404 ix86_handle_cconv_attribute (tree *node, tree name,
4406 int flags ATTRIBUTE_UNUSED,
4409 if (TREE_CODE (*node) != FUNCTION_TYPE
4410 && TREE_CODE (*node) != METHOD_TYPE
4411 && TREE_CODE (*node) != FIELD_DECL
4412 && TREE_CODE (*node) != TYPE_DECL)
4414 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4416 *no_add_attrs = true;
4420 /* Can combine regparm with all attributes but fastcall. */
4421 if (is_attribute_p ("regparm", name))
4425 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4427 error ("fastcall and regparm attributes are not compatible");
4430 cst = TREE_VALUE (args);
4431 if (TREE_CODE (cst) != INTEGER_CST)
4433 warning (OPT_Wattributes,
4434 "%qE attribute requires an integer constant argument",
4436 *no_add_attrs = true;
4438 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4440 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4442 *no_add_attrs = true;
4450 /* Do not warn when emulating the MS ABI. */
4451 if (TREE_CODE (*node) != FUNCTION_TYPE
4452 || ix86_function_type_abi (*node) != MS_ABI)
4453 warning (OPT_Wattributes, "%qE attribute ignored",
4455 *no_add_attrs = true;
4459 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4460 if (is_attribute_p ("fastcall", name))
4462 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4464 error ("fastcall and cdecl attributes are not compatible");
4466 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4468 error ("fastcall and stdcall attributes are not compatible");
4470 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4472 error ("fastcall and regparm attributes are not compatible");
4476 /* Can combine stdcall with fastcall (redundant), regparm and
4478 else if (is_attribute_p ("stdcall", name))
4480 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4482 error ("stdcall and cdecl attributes are not compatible");
4484 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4486 error ("stdcall and fastcall attributes are not compatible");
4490 /* Can combine cdecl with regparm and sseregparm. */
4491 else if (is_attribute_p ("cdecl", name))
4493 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4495 error ("stdcall and cdecl attributes are not compatible");
4497 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4499 error ("fastcall and cdecl attributes are not compatible");
4503 /* Can combine sseregparm with all attributes. */
4508 /* Return 0 if the attributes for two types are incompatible, 1 if they
4509 are compatible, and 2 if they are nearly compatible (which causes a
4510 warning to be generated). */
4513 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4515 /* Check for mismatch of non-default calling convention. */
4516 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4518 if (TREE_CODE (type1) != FUNCTION_TYPE
4519 && TREE_CODE (type1) != METHOD_TYPE)
4522 /* Check for mismatched fastcall/regparm types. */
4523 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4524 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4525 || (ix86_function_regparm (type1, NULL)
4526 != ix86_function_regparm (type2, NULL)))
4529 /* Check for mismatched sseregparm types. */
4530 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4531 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4534 /* Check for mismatched return types (cdecl vs stdcall). */
4535 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4536 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4542 /* Return the regparm value for a function with the indicated TYPE and DECL.
4543 DECL may be NULL when calling function indirectly
4544 or considering a libcall. */
4547 ix86_function_regparm (const_tree type, const_tree decl)
4553 return (ix86_function_type_abi (type) == SYSV_ABI
4554 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4556 regparm = ix86_regparm;
4557 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4560 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4564 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4567 /* Use register calling convention for local functions when possible. */
4569 && TREE_CODE (decl) == FUNCTION_DECL
4573 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4574 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE (decl));
4577 int local_regparm, globals = 0, regno;
4579 /* Make sure no regparm register is taken by a
4580 fixed register variable. */
4581 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4582 if (fixed_regs[local_regparm])
4585 /* We don't want to use regparm(3) for nested functions as
4586 these use a static chain pointer in the third argument. */
4587 if (local_regparm == 3 && DECL_STATIC_CHAIN (decl))
4590 /* Each fixed register usage increases register pressure,
4591 so less registers should be used for argument passing.
4592 This functionality can be overriden by an explicit
4594 for (regno = 0; regno <= DI_REG; regno++)
4595 if (fixed_regs[regno])
4599 = globals < local_regparm ? local_regparm - globals : 0;
4601 if (local_regparm > regparm)
4602 regparm = local_regparm;
4609 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4610 DFmode (2) arguments in SSE registers for a function with the
4611 indicated TYPE and DECL. DECL may be NULL when calling function
4612 indirectly or considering a libcall. Otherwise return 0. */
4615 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4617 gcc_assert (!TARGET_64BIT);
4619 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4620 by the sseregparm attribute. */
4621 if (TARGET_SSEREGPARM
4622 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4629 error ("Calling %qD with attribute sseregparm without "
4630 "SSE/SSE2 enabled", decl);
4632 error ("Calling %qT with attribute sseregparm without "
4633 "SSE/SSE2 enabled", type);
4641 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4642 (and DFmode for SSE2) arguments in SSE registers. */
4643 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4645 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4646 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4648 return TARGET_SSE2 ? 2 : 1;
4654 /* Return true if EAX is live at the start of the function. Used by
4655 ix86_expand_prologue to determine if we need special help before
4656 calling allocate_stack_worker. */
4659 ix86_eax_live_at_start_p (void)
4661 /* Cheat. Don't bother working forward from ix86_function_regparm
4662 to the function type to whether an actual argument is located in
4663 eax. Instead just look at cfg info, which is still close enough
4664 to correct at this point. This gives false positives for broken
4665 functions that might use uninitialized data that happens to be
4666 allocated in eax, but who cares? */
4667 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4670 /* Value is the number of bytes of arguments automatically
4671 popped when returning from a subroutine call.
4672 FUNDECL is the declaration node of the function (as a tree),
4673 FUNTYPE is the data type of the function (as a tree),
4674 or for a library call it is an identifier node for the subroutine name.
4675 SIZE is the number of bytes of arguments passed on the stack.
4677 On the 80386, the RTD insn may be used to pop them if the number
4678 of args is fixed, but if the number is variable then the caller
4679 must pop them all. RTD can't be used for library calls now
4680 because the library is compiled with the Unix compiler.
4681 Use of RTD is a selectable option, since it is incompatible with
4682 standard Unix calling sequences. If the option is not selected,
4683 the caller must always pop the args.
4685 The attribute stdcall is equivalent to RTD on a per module basis. */
4688 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4692 /* None of the 64-bit ABIs pop arguments. */
4696 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4698 /* Cdecl functions override -mrtd, and never pop the stack. */
4699 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4701 /* Stdcall and fastcall functions will pop the stack if not
4703 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4704 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4707 if (rtd && ! stdarg_p (funtype))
4711 /* Lose any fake structure return argument if it is passed on the stack. */
4712 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4713 && !KEEP_AGGREGATE_RETURN_POINTER)
4715 int nregs = ix86_function_regparm (funtype, fundecl);
4717 return GET_MODE_SIZE (Pmode);
4723 /* Argument support functions. */
4725 /* Return true when register may be used to pass function parameters. */
4727 ix86_function_arg_regno_p (int regno)
4730 const int *parm_regs;
4735 return (regno < REGPARM_MAX
4736 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4738 return (regno < REGPARM_MAX
4739 || (TARGET_MMX && MMX_REGNO_P (regno)
4740 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4741 || (TARGET_SSE && SSE_REGNO_P (regno)
4742 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4747 if (SSE_REGNO_P (regno) && TARGET_SSE)
4752 if (TARGET_SSE && SSE_REGNO_P (regno)
4753 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4757 /* TODO: The function should depend on current function ABI but
4758 builtins.c would need updating then. Therefore we use the
4761 /* RAX is used as hidden argument to va_arg functions. */
4762 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4765 if (ix86_abi == MS_ABI)
4766 parm_regs = x86_64_ms_abi_int_parameter_registers;
4768 parm_regs = x86_64_int_parameter_registers;
4769 for (i = 0; i < (ix86_abi == MS_ABI
4770 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4771 if (regno == parm_regs[i])
4776 /* Return if we do not know how to pass TYPE solely in registers. */
4779 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4781 if (must_pass_in_stack_var_size_or_pad (mode, type))
4784 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4785 The layout_type routine is crafty and tries to trick us into passing
4786 currently unsupported vector types on the stack by using TImode. */
4787 return (!TARGET_64BIT && mode == TImode
4788 && type && TREE_CODE (type) != VECTOR_TYPE);
4791 /* It returns the size, in bytes, of the area reserved for arguments passed
4792 in registers for the function represented by fndecl dependent to the used
4795 ix86_reg_parm_stack_space (const_tree fndecl)
4797 enum calling_abi call_abi = SYSV_ABI;
4798 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4799 call_abi = ix86_function_abi (fndecl);
4801 call_abi = ix86_function_type_abi (fndecl);
4802 if (call_abi == MS_ABI)
4807 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4810 ix86_function_type_abi (const_tree fntype)
4812 if (TARGET_64BIT && fntype != NULL)
4814 enum calling_abi abi = ix86_abi;
4815 if (abi == SYSV_ABI)
4817 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4820 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4828 ix86_function_ms_hook_prologue (const_tree fntype)
4832 if (lookup_attribute ("ms_hook_prologue", DECL_ATTRIBUTES (fntype)))
4834 if (decl_function_context (fntype) != NULL_TREE)
4836 error_at (DECL_SOURCE_LOCATION (fntype),
4837 "ms_hook_prologue is not compatible with nested function");
4846 static enum calling_abi
4847 ix86_function_abi (const_tree fndecl)
4851 return ix86_function_type_abi (TREE_TYPE (fndecl));
4854 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4857 ix86_cfun_abi (void)
4859 if (! cfun || ! TARGET_64BIT)
4861 return cfun->machine->call_abi;
4865 extern void init_regs (void);
4867 /* Implementation of call abi switching target hook. Specific to FNDECL
4868 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4869 for more details. */
4871 ix86_call_abi_override (const_tree fndecl)
4873 if (fndecl == NULL_TREE)
4874 cfun->machine->call_abi = ix86_abi;
4876 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4879 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4880 re-initialization of init_regs each time we switch function context since
4881 this is needed only during RTL expansion. */
4883 ix86_maybe_switch_abi (void)
4886 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4890 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4891 for a call to a function whose data type is FNTYPE.
4892 For a library call, FNTYPE is 0. */
4895 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4896 tree fntype, /* tree ptr for function decl */
4897 rtx libname, /* SYMBOL_REF of library name or 0 */
4900 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4901 memset (cum, 0, sizeof (*cum));
4904 cum->call_abi = ix86_function_abi (fndecl);
4906 cum->call_abi = ix86_function_type_abi (fntype);
4907 /* Set up the number of registers to use for passing arguments. */
4909 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4910 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4911 "or subtarget optimization implying it");
4912 cum->nregs = ix86_regparm;
4915 if (cum->call_abi != ix86_abi)
4916 cum->nregs = (ix86_abi != SYSV_ABI
4917 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4921 cum->sse_nregs = SSE_REGPARM_MAX;
4924 if (cum->call_abi != ix86_abi)
4925 cum->sse_nregs = (ix86_abi != SYSV_ABI
4926 ? X86_64_SSE_REGPARM_MAX
4927 : X86_64_MS_SSE_REGPARM_MAX);
4931 cum->mmx_nregs = MMX_REGPARM_MAX;
4932 cum->warn_avx = true;
4933 cum->warn_sse = true;
4934 cum->warn_mmx = true;
4936 /* Because type might mismatch in between caller and callee, we need to
4937 use actual type of function for local calls.
4938 FIXME: cgraph_analyze can be told to actually record if function uses
4939 va_start so for local functions maybe_vaarg can be made aggressive
4941 FIXME: once typesytem is fixed, we won't need this code anymore. */
4943 fntype = TREE_TYPE (fndecl);
4944 cum->maybe_vaarg = (fntype
4945 ? (!prototype_p (fntype) || stdarg_p (fntype))
4950 /* If there are variable arguments, then we won't pass anything
4951 in registers in 32-bit mode. */
4952 if (stdarg_p (fntype))
4963 /* Use ecx and edx registers if function has fastcall attribute,
4964 else look for regparm information. */
4967 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4973 cum->nregs = ix86_function_regparm (fntype, fndecl);
4976 /* Set up the number of SSE registers used for passing SFmode
4977 and DFmode arguments. Warn for mismatching ABI. */
4978 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4982 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4983 But in the case of vector types, it is some vector mode.
4985 When we have only some of our vector isa extensions enabled, then there
4986 are some modes for which vector_mode_supported_p is false. For these
4987 modes, the generic vector support in gcc will choose some non-vector mode
4988 in order to implement the type. By computing the natural mode, we'll
4989 select the proper ABI location for the operand and not depend on whatever
4990 the middle-end decides to do with these vector types.
4992 The midde-end can't deal with the vector types > 16 bytes. In this
4993 case, we return the original mode and warn ABI change if CUM isn't
4996 static enum machine_mode
4997 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4999 enum machine_mode mode = TYPE_MODE (type);
5001 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
5003 HOST_WIDE_INT size = int_size_in_bytes (type);
5004 if ((size == 8 || size == 16 || size == 32)
5005 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5006 && TYPE_VECTOR_SUBPARTS (type) > 1)
5008 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
5010 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5011 mode = MIN_MODE_VECTOR_FLOAT;
5013 mode = MIN_MODE_VECTOR_INT;
5015 /* Get the mode which has this inner mode and number of units. */
5016 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
5017 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
5018 && GET_MODE_INNER (mode) == innermode)
5020 if (size == 32 && !TARGET_AVX)
5022 static bool warnedavx;
5029 warning (0, "AVX vector argument without AVX "
5030 "enabled changes the ABI");
5032 return TYPE_MODE (type);
5045 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5046 this may not agree with the mode that the type system has chosen for the
5047 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5048 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5051 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
5056 if (orig_mode != BLKmode)
5057 tmp = gen_rtx_REG (orig_mode, regno);
5060 tmp = gen_rtx_REG (mode, regno);
5061 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
5062 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
5068 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5069 of this code is to classify each 8bytes of incoming argument by the register
5070 class and assign registers accordingly. */
5072 /* Return the union class of CLASS1 and CLASS2.
5073 See the x86-64 PS ABI for details. */
5075 static enum x86_64_reg_class
5076 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5078 /* Rule #1: If both classes are equal, this is the resulting class. */
5079 if (class1 == class2)
5082 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5084 if (class1 == X86_64_NO_CLASS)
5086 if (class2 == X86_64_NO_CLASS)
5089 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5090 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5091 return X86_64_MEMORY_CLASS;
5093 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5094 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5095 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5096 return X86_64_INTEGERSI_CLASS;
5097 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5098 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5099 return X86_64_INTEGER_CLASS;
5101 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5103 if (class1 == X86_64_X87_CLASS
5104 || class1 == X86_64_X87UP_CLASS
5105 || class1 == X86_64_COMPLEX_X87_CLASS
5106 || class2 == X86_64_X87_CLASS
5107 || class2 == X86_64_X87UP_CLASS
5108 || class2 == X86_64_COMPLEX_X87_CLASS)
5109 return X86_64_MEMORY_CLASS;
5111 /* Rule #6: Otherwise class SSE is used. */
5112 return X86_64_SSE_CLASS;
5115 /* Classify the argument of type TYPE and mode MODE.
5116 CLASSES will be filled by the register class used to pass each word
5117 of the operand. The number of words is returned. In case the parameter
5118 should be passed in memory, 0 is returned. As a special case for zero
5119 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5121 BIT_OFFSET is used internally for handling records and specifies offset
5122 of the offset in bits modulo 256 to avoid overflow cases.
5124 See the x86-64 PS ABI for details.
5128 classify_argument (enum machine_mode mode, const_tree type,
5129 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5131 HOST_WIDE_INT bytes =
5132 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5133 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5135 /* Variable sized entities are always passed/returned in memory. */
5139 if (mode != VOIDmode
5140 && targetm.calls.must_pass_in_stack (mode, type))
5143 if (type && AGGREGATE_TYPE_P (type))
5147 enum x86_64_reg_class subclasses[MAX_CLASSES];
5149 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5153 for (i = 0; i < words; i++)
5154 classes[i] = X86_64_NO_CLASS;
5156 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5157 signalize memory class, so handle it as special case. */
5160 classes[0] = X86_64_NO_CLASS;
5164 /* Classify each field of record and merge classes. */
5165 switch (TREE_CODE (type))
5168 /* And now merge the fields of structure. */
5169 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5171 if (TREE_CODE (field) == FIELD_DECL)
5175 if (TREE_TYPE (field) == error_mark_node)
5178 /* Bitfields are always classified as integer. Handle them
5179 early, since later code would consider them to be
5180 misaligned integers. */
5181 if (DECL_BIT_FIELD (field))
5183 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5184 i < ((int_bit_position (field) + (bit_offset % 64))
5185 + tree_low_cst (DECL_SIZE (field), 0)
5188 merge_classes (X86_64_INTEGER_CLASS,
5195 type = TREE_TYPE (field);
5197 /* Flexible array member is ignored. */
5198 if (TYPE_MODE (type) == BLKmode
5199 && TREE_CODE (type) == ARRAY_TYPE
5200 && TYPE_SIZE (type) == NULL_TREE
5201 && TYPE_DOMAIN (type) != NULL_TREE
5202 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5207 if (!warned && warn_psabi)
5210 inform (input_location,
5211 "The ABI of passing struct with"
5212 " a flexible array member has"
5213 " changed in GCC 4.4");
5217 num = classify_argument (TYPE_MODE (type), type,
5219 (int_bit_position (field)
5220 + bit_offset) % 256);
5223 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5224 for (i = 0; i < num && (i + pos) < words; i++)
5226 merge_classes (subclasses[i], classes[i + pos]);
5233 /* Arrays are handled as small records. */
5236 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5237 TREE_TYPE (type), subclasses, bit_offset);
5241 /* The partial classes are now full classes. */
5242 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5243 subclasses[0] = X86_64_SSE_CLASS;
5244 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5245 && !((bit_offset % 64) == 0 && bytes == 4))
5246 subclasses[0] = X86_64_INTEGER_CLASS;
5248 for (i = 0; i < words; i++)
5249 classes[i] = subclasses[i % num];
5254 case QUAL_UNION_TYPE:
5255 /* Unions are similar to RECORD_TYPE but offset is always 0.
5257 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5259 if (TREE_CODE (field) == FIELD_DECL)
5263 if (TREE_TYPE (field) == error_mark_node)
5266 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5267 TREE_TYPE (field), subclasses,
5271 for (i = 0; i < num; i++)
5272 classes[i] = merge_classes (subclasses[i], classes[i]);
5283 /* When size > 16 bytes, if the first one isn't
5284 X86_64_SSE_CLASS or any other ones aren't
5285 X86_64_SSEUP_CLASS, everything should be passed in
5287 if (classes[0] != X86_64_SSE_CLASS)
5290 for (i = 1; i < words; i++)
5291 if (classes[i] != X86_64_SSEUP_CLASS)
5295 /* Final merger cleanup. */
5296 for (i = 0; i < words; i++)
5298 /* If one class is MEMORY, everything should be passed in
5300 if (classes[i] == X86_64_MEMORY_CLASS)
5303 /* The X86_64_SSEUP_CLASS should be always preceded by
5304 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5305 if (classes[i] == X86_64_SSEUP_CLASS
5306 && classes[i - 1] != X86_64_SSE_CLASS
5307 && classes[i - 1] != X86_64_SSEUP_CLASS)
5309 /* The first one should never be X86_64_SSEUP_CLASS. */
5310 gcc_assert (i != 0);
5311 classes[i] = X86_64_SSE_CLASS;
5314 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5315 everything should be passed in memory. */
5316 if (classes[i] == X86_64_X87UP_CLASS
5317 && (classes[i - 1] != X86_64_X87_CLASS))
5321 /* The first one should never be X86_64_X87UP_CLASS. */
5322 gcc_assert (i != 0);
5323 if (!warned && warn_psabi)
5326 inform (input_location,
5327 "The ABI of passing union with long double"
5328 " has changed in GCC 4.4");
5336 /* Compute alignment needed. We align all types to natural boundaries with
5337 exception of XFmode that is aligned to 64bits. */
5338 if (mode != VOIDmode && mode != BLKmode)
5340 int mode_alignment = GET_MODE_BITSIZE (mode);
5343 mode_alignment = 128;
5344 else if (mode == XCmode)
5345 mode_alignment = 256;
5346 if (COMPLEX_MODE_P (mode))
5347 mode_alignment /= 2;
5348 /* Misaligned fields are always returned in memory. */
5349 if (bit_offset % mode_alignment)
5353 /* for V1xx modes, just use the base mode */
5354 if (VECTOR_MODE_P (mode) && mode != V1DImode
5355 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5356 mode = GET_MODE_INNER (mode);
5358 /* Classification of atomic types. */
5363 classes[0] = X86_64_SSE_CLASS;
5366 classes[0] = X86_64_SSE_CLASS;
5367 classes[1] = X86_64_SSEUP_CLASS;
5377 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5381 classes[0] = X86_64_INTEGERSI_CLASS;
5384 else if (size <= 64)
5386 classes[0] = X86_64_INTEGER_CLASS;
5389 else if (size <= 64+32)
5391 classes[0] = X86_64_INTEGER_CLASS;
5392 classes[1] = X86_64_INTEGERSI_CLASS;
5395 else if (size <= 64+64)
5397 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5405 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5409 /* OImode shouldn't be used directly. */
5414 if (!(bit_offset % 64))
5415 classes[0] = X86_64_SSESF_CLASS;
5417 classes[0] = X86_64_SSE_CLASS;
5420 classes[0] = X86_64_SSEDF_CLASS;
5423 classes[0] = X86_64_X87_CLASS;
5424 classes[1] = X86_64_X87UP_CLASS;
5427 classes[0] = X86_64_SSE_CLASS;
5428 classes[1] = X86_64_SSEUP_CLASS;
5431 classes[0] = X86_64_SSE_CLASS;
5432 if (!(bit_offset % 64))
5438 if (!warned && warn_psabi)
5441 inform (input_location,
5442 "The ABI of passing structure with complex float"
5443 " member has changed in GCC 4.4");
5445 classes[1] = X86_64_SSESF_CLASS;
5449 classes[0] = X86_64_SSEDF_CLASS;
5450 classes[1] = X86_64_SSEDF_CLASS;
5453 classes[0] = X86_64_COMPLEX_X87_CLASS;
5456 /* This modes is larger than 16 bytes. */
5464 classes[0] = X86_64_SSE_CLASS;
5465 classes[1] = X86_64_SSEUP_CLASS;
5466 classes[2] = X86_64_SSEUP_CLASS;
5467 classes[3] = X86_64_SSEUP_CLASS;
5475 classes[0] = X86_64_SSE_CLASS;
5476 classes[1] = X86_64_SSEUP_CLASS;
5483 classes[0] = X86_64_SSE_CLASS;
5489 gcc_assert (VECTOR_MODE_P (mode));
5494 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5496 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5497 classes[0] = X86_64_INTEGERSI_CLASS;
5499 classes[0] = X86_64_INTEGER_CLASS;
5500 classes[1] = X86_64_INTEGER_CLASS;
5501 return 1 + (bytes > 8);
5505 /* Examine the argument and return set number of register required in each
5506 class. Return 0 iff parameter should be passed in memory. */
5508 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5509 int *int_nregs, int *sse_nregs)
5511 enum x86_64_reg_class regclass[MAX_CLASSES];
5512 int n = classify_argument (mode, type, regclass, 0);
5518 for (n--; n >= 0; n--)
5519 switch (regclass[n])
5521 case X86_64_INTEGER_CLASS:
5522 case X86_64_INTEGERSI_CLASS:
5525 case X86_64_SSE_CLASS:
5526 case X86_64_SSESF_CLASS:
5527 case X86_64_SSEDF_CLASS:
5530 case X86_64_NO_CLASS:
5531 case X86_64_SSEUP_CLASS:
5533 case X86_64_X87_CLASS:
5534 case X86_64_X87UP_CLASS:
5538 case X86_64_COMPLEX_X87_CLASS:
5539 return in_return ? 2 : 0;
5540 case X86_64_MEMORY_CLASS:
5546 /* Construct container for the argument used by GCC interface. See
5547 FUNCTION_ARG for the detailed description. */
5550 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5551 const_tree type, int in_return, int nintregs, int nsseregs,
5552 const int *intreg, int sse_regno)
5554 /* The following variables hold the static issued_error state. */
5555 static bool issued_sse_arg_error;
5556 static bool issued_sse_ret_error;
5557 static bool issued_x87_ret_error;
5559 enum machine_mode tmpmode;
5561 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5562 enum x86_64_reg_class regclass[MAX_CLASSES];
5566 int needed_sseregs, needed_intregs;
5567 rtx exp[MAX_CLASSES];
5570 n = classify_argument (mode, type, regclass, 0);
5573 if (!examine_argument (mode, type, in_return, &needed_intregs,
5576 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5579 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5580 some less clueful developer tries to use floating-point anyway. */
5581 if (needed_sseregs && !TARGET_SSE)
5585 if (!issued_sse_ret_error)
5587 error ("SSE register return with SSE disabled");
5588 issued_sse_ret_error = true;
5591 else if (!issued_sse_arg_error)
5593 error ("SSE register argument with SSE disabled");
5594 issued_sse_arg_error = true;
5599 /* Likewise, error if the ABI requires us to return values in the
5600 x87 registers and the user specified -mno-80387. */
5601 if (!TARGET_80387 && in_return)
5602 for (i = 0; i < n; i++)
5603 if (regclass[i] == X86_64_X87_CLASS
5604 || regclass[i] == X86_64_X87UP_CLASS
5605 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5607 if (!issued_x87_ret_error)
5609 error ("x87 register return with x87 disabled");
5610 issued_x87_ret_error = true;
5615 /* First construct simple cases. Avoid SCmode, since we want to use
5616 single register to pass this type. */
5617 if (n == 1 && mode != SCmode)
5618 switch (regclass[0])
5620 case X86_64_INTEGER_CLASS:
5621 case X86_64_INTEGERSI_CLASS:
5622 return gen_rtx_REG (mode, intreg[0]);
5623 case X86_64_SSE_CLASS:
5624 case X86_64_SSESF_CLASS:
5625 case X86_64_SSEDF_CLASS:
5626 if (mode != BLKmode)
5627 return gen_reg_or_parallel (mode, orig_mode,
5628 SSE_REGNO (sse_regno));
5630 case X86_64_X87_CLASS:
5631 case X86_64_COMPLEX_X87_CLASS:
5632 return gen_rtx_REG (mode, FIRST_STACK_REG);
5633 case X86_64_NO_CLASS:
5634 /* Zero sized array, struct or class. */
5639 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5640 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5641 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5643 && regclass[0] == X86_64_SSE_CLASS
5644 && regclass[1] == X86_64_SSEUP_CLASS
5645 && regclass[2] == X86_64_SSEUP_CLASS
5646 && regclass[3] == X86_64_SSEUP_CLASS
5648 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5651 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5652 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5653 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5654 && regclass[1] == X86_64_INTEGER_CLASS
5655 && (mode == CDImode || mode == TImode || mode == TFmode)
5656 && intreg[0] + 1 == intreg[1])
5657 return gen_rtx_REG (mode, intreg[0]);
5659 /* Otherwise figure out the entries of the PARALLEL. */
5660 for (i = 0; i < n; i++)
5664 switch (regclass[i])
5666 case X86_64_NO_CLASS:
5668 case X86_64_INTEGER_CLASS:
5669 case X86_64_INTEGERSI_CLASS:
5670 /* Merge TImodes on aligned occasions here too. */
5671 if (i * 8 + 8 > bytes)
5672 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5673 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5677 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5678 if (tmpmode == BLKmode)
5680 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5681 gen_rtx_REG (tmpmode, *intreg),
5685 case X86_64_SSESF_CLASS:
5686 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5687 gen_rtx_REG (SFmode,
5688 SSE_REGNO (sse_regno)),
5692 case X86_64_SSEDF_CLASS:
5693 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5694 gen_rtx_REG (DFmode,
5695 SSE_REGNO (sse_regno)),
5699 case X86_64_SSE_CLASS:
5707 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5717 && regclass[1] == X86_64_SSEUP_CLASS
5718 && regclass[2] == X86_64_SSEUP_CLASS
5719 && regclass[3] == X86_64_SSEUP_CLASS);
5726 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5727 gen_rtx_REG (tmpmode,
5728 SSE_REGNO (sse_regno)),
5737 /* Empty aligned struct, union or class. */
5741 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5742 for (i = 0; i < nexps; i++)
5743 XVECEXP (ret, 0, i) = exp [i];
5747 /* Update the data in CUM to advance over an argument of mode MODE
5748 and data type TYPE. (TYPE is null for libcalls where that information
5749 may not be available.) */
5752 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5753 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5769 cum->words += words;
5770 cum->nregs -= words;
5771 cum->regno += words;
5773 if (cum->nregs <= 0)
5781 /* OImode shouldn't be used directly. */
5785 if (cum->float_in_sse < 2)
5788 if (cum->float_in_sse < 1)
5805 if (!type || !AGGREGATE_TYPE_P (type))
5807 cum->sse_words += words;
5808 cum->sse_nregs -= 1;
5809 cum->sse_regno += 1;
5810 if (cum->sse_nregs <= 0)
5823 if (!type || !AGGREGATE_TYPE_P (type))
5825 cum->mmx_words += words;
5826 cum->mmx_nregs -= 1;
5827 cum->mmx_regno += 1;
5828 if (cum->mmx_nregs <= 0)
5839 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5840 tree type, HOST_WIDE_INT words, int named)
5842 int int_nregs, sse_nregs;
5844 /* Unnamed 256bit vector mode parameters are passed on stack. */
5845 if (!named && VALID_AVX256_REG_MODE (mode))
5848 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5849 cum->words += words;
5850 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5852 cum->nregs -= int_nregs;
5853 cum->sse_nregs -= sse_nregs;
5854 cum->regno += int_nregs;
5855 cum->sse_regno += sse_nregs;
5858 cum->words += words;
5862 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5863 HOST_WIDE_INT words)
5865 /* Otherwise, this should be passed indirect. */
5866 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5868 cum->words += words;
5877 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5878 tree type, int named)
5880 HOST_WIDE_INT bytes, words;
5882 if (mode == BLKmode)
5883 bytes = int_size_in_bytes (type);
5885 bytes = GET_MODE_SIZE (mode);
5886 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5889 mode = type_natural_mode (type, NULL);
5891 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5892 function_arg_advance_ms_64 (cum, bytes, words);
5893 else if (TARGET_64BIT)
5894 function_arg_advance_64 (cum, mode, type, words, named);
5896 function_arg_advance_32 (cum, mode, type, bytes, words);
5899 /* Define where to put the arguments to a function.
5900 Value is zero to push the argument on the stack,
5901 or a hard register in which to store the argument.
5903 MODE is the argument's machine mode.
5904 TYPE is the data type of the argument (as a tree).
5905 This is null for libcalls where that information may
5907 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5908 the preceding args and about the function being called.
5909 NAMED is nonzero if this argument is a named parameter
5910 (otherwise it is an extra parameter matching an ellipsis). */
5913 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5914 enum machine_mode orig_mode, tree type,
5915 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5917 static bool warnedsse, warnedmmx;
5919 /* Avoid the AL settings for the Unix64 ABI. */
5920 if (mode == VOIDmode)
5936 if (words <= cum->nregs)
5938 int regno = cum->regno;
5940 /* Fastcall allocates the first two DWORD (SImode) or
5941 smaller arguments to ECX and EDX if it isn't an
5947 || (type && AGGREGATE_TYPE_P (type)))
5950 /* ECX not EAX is the first allocated register. */
5951 if (regno == AX_REG)
5954 return gen_rtx_REG (mode, regno);
5959 if (cum->float_in_sse < 2)
5962 if (cum->float_in_sse < 1)
5966 /* In 32bit, we pass TImode in xmm registers. */
5973 if (!type || !AGGREGATE_TYPE_P (type))
5975 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5978 warning (0, "SSE vector argument without SSE enabled "
5982 return gen_reg_or_parallel (mode, orig_mode,
5983 cum->sse_regno + FIRST_SSE_REG);
5988 /* OImode shouldn't be used directly. */
5997 if (!type || !AGGREGATE_TYPE_P (type))
6000 return gen_reg_or_parallel (mode, orig_mode,
6001 cum->sse_regno + FIRST_SSE_REG);
6010 if (!type || !AGGREGATE_TYPE_P (type))
6012 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
6015 warning (0, "MMX vector argument without MMX enabled "
6019 return gen_reg_or_parallel (mode, orig_mode,
6020 cum->mmx_regno + FIRST_MMX_REG);
6029 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6030 enum machine_mode orig_mode, tree type, int named)
6032 /* Handle a hidden AL argument containing number of registers
6033 for varargs x86-64 functions. */
6034 if (mode == VOIDmode)
6035 return GEN_INT (cum->maybe_vaarg
6036 ? (cum->sse_nregs < 0
6037 ? (cum->call_abi == ix86_abi
6039 : (ix86_abi != SYSV_ABI
6040 ? X86_64_SSE_REGPARM_MAX
6041 : X86_64_MS_SSE_REGPARM_MAX))
6056 /* Unnamed 256bit vector mode parameters are passed on stack. */
6062 return construct_container (mode, orig_mode, type, 0, cum->nregs,
6064 &x86_64_int_parameter_registers [cum->regno],
6069 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6070 enum machine_mode orig_mode, int named,
6071 HOST_WIDE_INT bytes)
6075 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6076 We use value of -2 to specify that current function call is MSABI. */
6077 if (mode == VOIDmode)
6078 return GEN_INT (-2);
6080 /* If we've run out of registers, it goes on the stack. */
6081 if (cum->nregs == 0)
6084 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6086 /* Only floating point modes are passed in anything but integer regs. */
6087 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6090 regno = cum->regno + FIRST_SSE_REG;
6095 /* Unnamed floating parameters are passed in both the
6096 SSE and integer registers. */
6097 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6098 t2 = gen_rtx_REG (mode, regno);
6099 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6100 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6101 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6104 /* Handle aggregated types passed in register. */
6105 if (orig_mode == BLKmode)
6107 if (bytes > 0 && bytes <= 8)
6108 mode = (bytes > 4 ? DImode : SImode);
6109 if (mode == BLKmode)
6113 return gen_reg_or_parallel (mode, orig_mode, regno);
6117 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6118 tree type, int named)
6120 enum machine_mode mode = omode;
6121 HOST_WIDE_INT bytes, words;
6123 if (mode == BLKmode)
6124 bytes = int_size_in_bytes (type);
6126 bytes = GET_MODE_SIZE (mode);
6127 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6129 /* To simplify the code below, represent vector types with a vector mode
6130 even if MMX/SSE are not active. */
6131 if (type && TREE_CODE (type) == VECTOR_TYPE)
6132 mode = type_natural_mode (type, cum);
6134 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6135 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6136 else if (TARGET_64BIT)
6137 return function_arg_64 (cum, mode, omode, type, named);
6139 return function_arg_32 (cum, mode, omode, type, bytes, words);
6142 /* A C expression that indicates when an argument must be passed by
6143 reference. If nonzero for an argument, a copy of that argument is
6144 made in memory and a pointer to the argument is passed instead of
6145 the argument itself. The pointer is passed in whatever way is
6146 appropriate for passing a pointer to that type. */
6149 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6150 enum machine_mode mode ATTRIBUTE_UNUSED,
6151 const_tree type, bool named ATTRIBUTE_UNUSED)
6153 /* See Windows x64 Software Convention. */
6154 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6156 int msize = (int) GET_MODE_SIZE (mode);
6159 /* Arrays are passed by reference. */
6160 if (TREE_CODE (type) == ARRAY_TYPE)
6163 if (AGGREGATE_TYPE_P (type))
6165 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6166 are passed by reference. */
6167 msize = int_size_in_bytes (type);
6171 /* __m128 is passed by reference. */
6173 case 1: case 2: case 4: case 8:
6179 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6185 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6188 contains_aligned_value_p (tree type)
6190 enum machine_mode mode = TYPE_MODE (type);
6191 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6195 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6197 if (TYPE_ALIGN (type) < 128)
6200 if (AGGREGATE_TYPE_P (type))
6202 /* Walk the aggregates recursively. */
6203 switch (TREE_CODE (type))
6207 case QUAL_UNION_TYPE:
6211 /* Walk all the structure fields. */
6212 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6214 if (TREE_CODE (field) == FIELD_DECL
6215 && contains_aligned_value_p (TREE_TYPE (field)))
6222 /* Just for use if some languages passes arrays by value. */
6223 if (contains_aligned_value_p (TREE_TYPE (type)))
6234 /* Gives the alignment boundary, in bits, of an argument with the
6235 specified mode and type. */
6238 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6243 /* Since canonical type is used for call, we convert it to
6244 canonical type if needed. */
6245 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6246 type = TYPE_CANONICAL (type);
6247 align = TYPE_ALIGN (type);
6250 align = GET_MODE_ALIGNMENT (mode);
6251 if (align < PARM_BOUNDARY)
6252 align = PARM_BOUNDARY;
6253 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6254 natural boundaries. */
6255 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6257 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6258 make an exception for SSE modes since these require 128bit
6261 The handling here differs from field_alignment. ICC aligns MMX
6262 arguments to 4 byte boundaries, while structure fields are aligned
6263 to 8 byte boundaries. */
6266 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6267 align = PARM_BOUNDARY;
6271 if (!contains_aligned_value_p (type))
6272 align = PARM_BOUNDARY;
6275 if (align > BIGGEST_ALIGNMENT)
6276 align = BIGGEST_ALIGNMENT;
6280 /* Return true if N is a possible register number of function value. */
6283 ix86_function_value_regno_p (int regno)
6290 case FIRST_FLOAT_REG:
6291 /* TODO: The function should depend on current function ABI but
6292 builtins.c would need updating then. Therefore we use the
6294 if (TARGET_64BIT && ix86_abi == MS_ABI)
6296 return TARGET_FLOAT_RETURNS_IN_80387;
6302 if (TARGET_MACHO || TARGET_64BIT)
6310 /* Define how to find the value returned by a function.
6311 VALTYPE is the data type of the value (as a tree).
6312 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6313 otherwise, FUNC is 0. */
6316 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6317 const_tree fntype, const_tree fn)
6321 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6322 we normally prevent this case when mmx is not available. However
6323 some ABIs may require the result to be returned like DImode. */
6324 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6325 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6327 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6328 we prevent this case when sse is not available. However some ABIs
6329 may require the result to be returned like integer TImode. */
6330 else if (mode == TImode
6331 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6332 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6334 /* 32-byte vector modes in %ymm0. */
6335 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6336 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6338 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6339 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6340 regno = FIRST_FLOAT_REG;
6342 /* Most things go in %eax. */
6345 /* Override FP return register with %xmm0 for local functions when
6346 SSE math is enabled or for functions with sseregparm attribute. */
6347 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6349 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6350 if ((sse_level >= 1 && mode == SFmode)
6351 || (sse_level == 2 && mode == DFmode))
6352 regno = FIRST_SSE_REG;
6355 /* OImode shouldn't be used directly. */
6356 gcc_assert (mode != OImode);
6358 return gen_rtx_REG (orig_mode, regno);
6362 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6367 /* Handle libcalls, which don't provide a type node. */
6368 if (valtype == NULL)
6380 return gen_rtx_REG (mode, FIRST_SSE_REG);
6383 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6387 return gen_rtx_REG (mode, AX_REG);
6391 ret = construct_container (mode, orig_mode, valtype, 1,
6392 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6393 x86_64_int_return_registers, 0);
6395 /* For zero sized structures, construct_container returns NULL, but we
6396 need to keep rest of compiler happy by returning meaningful value. */
6398 ret = gen_rtx_REG (orig_mode, AX_REG);
6404 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6406 unsigned int regno = AX_REG;
6410 switch (GET_MODE_SIZE (mode))
6413 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6414 && !COMPLEX_MODE_P (mode))
6415 regno = FIRST_SSE_REG;
6419 if (mode == SFmode || mode == DFmode)
6420 regno = FIRST_SSE_REG;
6426 return gen_rtx_REG (orig_mode, regno);
6430 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6431 enum machine_mode orig_mode, enum machine_mode mode)
6433 const_tree fn, fntype;
6436 if (fntype_or_decl && DECL_P (fntype_or_decl))
6437 fn = fntype_or_decl;
6438 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6440 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6441 return function_value_ms_64 (orig_mode, mode);
6442 else if (TARGET_64BIT)
6443 return function_value_64 (orig_mode, mode, valtype);
6445 return function_value_32 (orig_mode, mode, fntype, fn);
6449 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6450 bool outgoing ATTRIBUTE_UNUSED)
6452 enum machine_mode mode, orig_mode;
6454 orig_mode = TYPE_MODE (valtype);
6455 mode = type_natural_mode (valtype, NULL);
6456 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6460 ix86_libcall_value (enum machine_mode mode)
6462 return ix86_function_value_1 (NULL, NULL, mode, mode);
6465 /* Return true iff type is returned in memory. */
6467 static int ATTRIBUTE_UNUSED
6468 return_in_memory_32 (const_tree type, enum machine_mode mode)
6472 if (mode == BLKmode)
6475 size = int_size_in_bytes (type);
6477 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6480 if (VECTOR_MODE_P (mode) || mode == TImode)
6482 /* User-created vectors small enough to fit in EAX. */
6486 /* MMX/3dNow values are returned in MM0,
6487 except when it doesn't exits. */
6489 return (TARGET_MMX ? 0 : 1);
6491 /* SSE values are returned in XMM0, except when it doesn't exist. */
6493 return (TARGET_SSE ? 0 : 1);
6495 /* AVX values are returned in YMM0, except when it doesn't exist. */
6497 return TARGET_AVX ? 0 : 1;
6506 /* OImode shouldn't be used directly. */
6507 gcc_assert (mode != OImode);
6512 static int ATTRIBUTE_UNUSED
6513 return_in_memory_64 (const_tree type, enum machine_mode mode)
6515 int needed_intregs, needed_sseregs;
6516 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6519 static int ATTRIBUTE_UNUSED
6520 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6522 HOST_WIDE_INT size = int_size_in_bytes (type);
6524 /* __m128 is returned in xmm0. */
6525 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6526 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6529 /* Otherwise, the size must be exactly in [1248]. */
6530 return (size != 1 && size != 2 && size != 4 && size != 8);
6534 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6536 #ifdef SUBTARGET_RETURN_IN_MEMORY
6537 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6539 const enum machine_mode mode = type_natural_mode (type, NULL);
6543 if (ix86_function_type_abi (fntype) == MS_ABI)
6544 return return_in_memory_ms_64 (type, mode);
6546 return return_in_memory_64 (type, mode);
6549 return return_in_memory_32 (type, mode);
6553 /* Return false iff TYPE is returned in memory. This version is used
6554 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6555 but differs notably in that when MMX is available, 8-byte vectors
6556 are returned in memory, rather than in MMX registers. */
6559 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6562 enum machine_mode mode = type_natural_mode (type, NULL);
6565 return return_in_memory_64 (type, mode);
6567 if (mode == BLKmode)
6570 size = int_size_in_bytes (type);
6572 if (VECTOR_MODE_P (mode))
6574 /* Return in memory only if MMX registers *are* available. This
6575 seems backwards, but it is consistent with the existing
6582 else if (mode == TImode)
6584 else if (mode == XFmode)
6590 /* When returning SSE vector types, we have a choice of either
6591 (1) being abi incompatible with a -march switch, or
6592 (2) generating an error.
6593 Given no good solution, I think the safest thing is one warning.
6594 The user won't be able to use -Werror, but....
6596 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6597 called in response to actually generating a caller or callee that
6598 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6599 via aggregate_value_p for general type probing from tree-ssa. */
6602 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6604 static bool warnedsse, warnedmmx;
6606 if (!TARGET_64BIT && type)
6608 /* Look at the return type of the function, not the function type. */
6609 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6611 if (!TARGET_SSE && !warnedsse)
6614 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6617 warning (0, "SSE vector return without SSE enabled "
6622 if (!TARGET_MMX && !warnedmmx)
6624 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6627 warning (0, "MMX vector return without MMX enabled "
6637 /* Create the va_list data type. */
6639 /* Returns the calling convention specific va_list date type.
6640 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6643 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6645 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6647 /* For i386 we use plain pointer to argument area. */
6648 if (!TARGET_64BIT || abi == MS_ABI)
6649 return build_pointer_type (char_type_node);
6651 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6652 type_decl = build_decl (BUILTINS_LOCATION,
6653 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6655 f_gpr = build_decl (BUILTINS_LOCATION,
6656 FIELD_DECL, get_identifier ("gp_offset"),
6657 unsigned_type_node);
6658 f_fpr = build_decl (BUILTINS_LOCATION,
6659 FIELD_DECL, get_identifier ("fp_offset"),
6660 unsigned_type_node);
6661 f_ovf = build_decl (BUILTINS_LOCATION,
6662 FIELD_DECL, get_identifier ("overflow_arg_area"),
6664 f_sav = build_decl (BUILTINS_LOCATION,
6665 FIELD_DECL, get_identifier ("reg_save_area"),
6668 va_list_gpr_counter_field = f_gpr;
6669 va_list_fpr_counter_field = f_fpr;
6671 DECL_FIELD_CONTEXT (f_gpr) = record;
6672 DECL_FIELD_CONTEXT (f_fpr) = record;
6673 DECL_FIELD_CONTEXT (f_ovf) = record;
6674 DECL_FIELD_CONTEXT (f_sav) = record;
6676 TREE_CHAIN (record) = type_decl;
6677 TYPE_NAME (record) = type_decl;
6678 TYPE_FIELDS (record) = f_gpr;
6679 TREE_CHAIN (f_gpr) = f_fpr;
6680 TREE_CHAIN (f_fpr) = f_ovf;
6681 TREE_CHAIN (f_ovf) = f_sav;
6683 layout_type (record);
6685 /* The correct type is an array type of one element. */
6686 return build_array_type (record, build_index_type (size_zero_node));
6689 /* Setup the builtin va_list data type and for 64-bit the additional
6690 calling convention specific va_list data types. */
6693 ix86_build_builtin_va_list (void)
6695 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6697 /* Initialize abi specific va_list builtin types. */
6701 if (ix86_abi == MS_ABI)
6703 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6704 if (TREE_CODE (t) != RECORD_TYPE)
6705 t = build_variant_type_copy (t);
6706 sysv_va_list_type_node = t;
6711 if (TREE_CODE (t) != RECORD_TYPE)
6712 t = build_variant_type_copy (t);
6713 sysv_va_list_type_node = t;
6715 if (ix86_abi != MS_ABI)
6717 t = ix86_build_builtin_va_list_abi (MS_ABI);
6718 if (TREE_CODE (t) != RECORD_TYPE)
6719 t = build_variant_type_copy (t);
6720 ms_va_list_type_node = t;
6725 if (TREE_CODE (t) != RECORD_TYPE)
6726 t = build_variant_type_copy (t);
6727 ms_va_list_type_node = t;
6734 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6737 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6746 int regparm = ix86_regparm;
6748 if (cum->call_abi != ix86_abi)
6749 regparm = (ix86_abi != SYSV_ABI
6750 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6752 /* GPR size of varargs save area. */
6753 if (cfun->va_list_gpr_size)
6754 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6756 ix86_varargs_gpr_size = 0;
6758 /* FPR size of varargs save area. We don't need it if we don't pass
6759 anything in SSE registers. */
6760 if (cum->sse_nregs && cfun->va_list_fpr_size)
6761 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6763 ix86_varargs_fpr_size = 0;
6765 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6768 save_area = frame_pointer_rtx;
6769 set = get_varargs_alias_set ();
6771 for (i = cum->regno;
6773 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6776 mem = gen_rtx_MEM (Pmode,
6777 plus_constant (save_area, i * UNITS_PER_WORD));
6778 MEM_NOTRAP_P (mem) = 1;
6779 set_mem_alias_set (mem, set);
6780 emit_move_insn (mem, gen_rtx_REG (Pmode,
6781 x86_64_int_parameter_registers[i]));
6784 if (ix86_varargs_fpr_size)
6786 /* Now emit code to save SSE registers. The AX parameter contains number
6787 of SSE parameter registers used to call this function. We use
6788 sse_prologue_save insn template that produces computed jump across
6789 SSE saves. We need some preparation work to get this working. */
6791 label = gen_label_rtx ();
6792 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6794 /* Compute address to jump to :
6795 label - eax*4 + nnamed_sse_arguments*4 Or
6796 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6797 tmp_reg = gen_reg_rtx (Pmode);
6798 nsse_reg = gen_reg_rtx (Pmode);
6799 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6800 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6801 gen_rtx_MULT (Pmode, nsse_reg,
6804 /* vmovaps is one byte longer than movaps. */
6806 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6807 gen_rtx_PLUS (Pmode, tmp_reg,
6813 gen_rtx_CONST (DImode,
6814 gen_rtx_PLUS (DImode,
6816 GEN_INT (cum->sse_regno
6817 * (TARGET_AVX ? 5 : 4)))));
6819 emit_move_insn (nsse_reg, label_ref);
6820 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6822 /* Compute address of memory block we save into. We always use pointer
6823 pointing 127 bytes after first byte to store - this is needed to keep
6824 instruction size limited by 4 bytes (5 bytes for AVX) with one
6825 byte displacement. */
6826 tmp_reg = gen_reg_rtx (Pmode);
6827 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6828 plus_constant (save_area,
6829 ix86_varargs_gpr_size + 127)));
6830 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6831 MEM_NOTRAP_P (mem) = 1;
6832 set_mem_alias_set (mem, set);
6833 set_mem_align (mem, BITS_PER_WORD);
6835 /* And finally do the dirty job! */
6836 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6837 GEN_INT (cum->sse_regno), label));
6842 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6844 alias_set_type set = get_varargs_alias_set ();
6847 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6851 mem = gen_rtx_MEM (Pmode,
6852 plus_constant (virtual_incoming_args_rtx,
6853 i * UNITS_PER_WORD));
6854 MEM_NOTRAP_P (mem) = 1;
6855 set_mem_alias_set (mem, set);
6857 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6858 emit_move_insn (mem, reg);
6863 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6864 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6867 CUMULATIVE_ARGS next_cum;
6870 /* This argument doesn't appear to be used anymore. Which is good,
6871 because the old code here didn't suppress rtl generation. */
6872 gcc_assert (!no_rtl);
6877 fntype = TREE_TYPE (current_function_decl);
6879 /* For varargs, we do not want to skip the dummy va_dcl argument.
6880 For stdargs, we do want to skip the last named argument. */
6882 if (stdarg_p (fntype))
6883 function_arg_advance (&next_cum, mode, type, 1);
6885 if (cum->call_abi == MS_ABI)
6886 setup_incoming_varargs_ms_64 (&next_cum);
6888 setup_incoming_varargs_64 (&next_cum);
6891 /* Checks if TYPE is of kind va_list char *. */
6894 is_va_list_char_pointer (tree type)
6898 /* For 32-bit it is always true. */
6901 canonic = ix86_canonical_va_list_type (type);
6902 return (canonic == ms_va_list_type_node
6903 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6906 /* Implement va_start. */
6909 ix86_va_start (tree valist, rtx nextarg)
6911 HOST_WIDE_INT words, n_gpr, n_fpr;
6912 tree f_gpr, f_fpr, f_ovf, f_sav;
6913 tree gpr, fpr, ovf, sav, t;
6916 /* Only 64bit target needs something special. */
6917 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6919 std_expand_builtin_va_start (valist, nextarg);
6923 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6924 f_fpr = TREE_CHAIN (f_gpr);
6925 f_ovf = TREE_CHAIN (f_fpr);
6926 f_sav = TREE_CHAIN (f_ovf);
6928 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6929 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6930 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6931 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6932 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6934 /* Count number of gp and fp argument registers used. */
6935 words = crtl->args.info.words;
6936 n_gpr = crtl->args.info.regno;
6937 n_fpr = crtl->args.info.sse_regno;
6939 if (cfun->va_list_gpr_size)
6941 type = TREE_TYPE (gpr);
6942 t = build2 (MODIFY_EXPR, type,
6943 gpr, build_int_cst (type, n_gpr * 8));
6944 TREE_SIDE_EFFECTS (t) = 1;
6945 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6948 if (TARGET_SSE && cfun->va_list_fpr_size)
6950 type = TREE_TYPE (fpr);
6951 t = build2 (MODIFY_EXPR, type, fpr,
6952 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6953 TREE_SIDE_EFFECTS (t) = 1;
6954 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6957 /* Find the overflow area. */
6958 type = TREE_TYPE (ovf);
6959 t = make_tree (type, crtl->args.internal_arg_pointer);
6961 t = build2 (POINTER_PLUS_EXPR, type, t,
6962 size_int (words * UNITS_PER_WORD));
6963 t = build2 (MODIFY_EXPR, type, ovf, t);
6964 TREE_SIDE_EFFECTS (t) = 1;
6965 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6967 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6969 /* Find the register save area.
6970 Prologue of the function save it right above stack frame. */
6971 type = TREE_TYPE (sav);
6972 t = make_tree (type, frame_pointer_rtx);
6973 if (!ix86_varargs_gpr_size)
6974 t = build2 (POINTER_PLUS_EXPR, type, t,
6975 size_int (-8 * X86_64_REGPARM_MAX));
6976 t = build2 (MODIFY_EXPR, type, sav, t);
6977 TREE_SIDE_EFFECTS (t) = 1;
6978 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6982 /* Implement va_arg. */
6985 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6988 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6989 tree f_gpr, f_fpr, f_ovf, f_sav;
6990 tree gpr, fpr, ovf, sav, t;
6992 tree lab_false, lab_over = NULL_TREE;
6997 enum machine_mode nat_mode;
7000 /* Only 64bit target needs something special. */
7001 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
7002 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
7004 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
7005 f_fpr = TREE_CHAIN (f_gpr);
7006 f_ovf = TREE_CHAIN (f_fpr);
7007 f_sav = TREE_CHAIN (f_ovf);
7009 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
7010 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
7011 valist = build_va_arg_indirect_ref (valist);
7012 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7013 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7014 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7016 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
7018 type = build_pointer_type (type);
7019 size = int_size_in_bytes (type);
7020 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7022 nat_mode = type_natural_mode (type, NULL);
7031 /* Unnamed 256bit vector mode parameters are passed on stack. */
7032 if (ix86_cfun_abi () == SYSV_ABI)
7039 container = construct_container (nat_mode, TYPE_MODE (type),
7040 type, 0, X86_64_REGPARM_MAX,
7041 X86_64_SSE_REGPARM_MAX, intreg,
7046 /* Pull the value out of the saved registers. */
7048 addr = create_tmp_var (ptr_type_node, "addr");
7052 int needed_intregs, needed_sseregs;
7054 tree int_addr, sse_addr;
7056 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7057 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7059 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
7061 need_temp = (!REG_P (container)
7062 && ((needed_intregs && TYPE_ALIGN (type) > 64)
7063 || TYPE_ALIGN (type) > 128));
7065 /* In case we are passing structure, verify that it is consecutive block
7066 on the register save area. If not we need to do moves. */
7067 if (!need_temp && !REG_P (container))
7069 /* Verify that all registers are strictly consecutive */
7070 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7074 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7076 rtx slot = XVECEXP (container, 0, i);
7077 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7078 || INTVAL (XEXP (slot, 1)) != i * 16)
7086 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7088 rtx slot = XVECEXP (container, 0, i);
7089 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7090 || INTVAL (XEXP (slot, 1)) != i * 8)
7102 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7103 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7106 /* First ensure that we fit completely in registers. */
7109 t = build_int_cst (TREE_TYPE (gpr),
7110 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7111 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7112 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7113 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7114 gimplify_and_add (t, pre_p);
7118 t = build_int_cst (TREE_TYPE (fpr),
7119 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7120 + X86_64_REGPARM_MAX * 8);
7121 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7122 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7123 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7124 gimplify_and_add (t, pre_p);
7127 /* Compute index to start of area used for integer regs. */
7130 /* int_addr = gpr + sav; */
7131 t = fold_convert (sizetype, gpr);
7132 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7133 gimplify_assign (int_addr, t, pre_p);
7137 /* sse_addr = fpr + sav; */
7138 t = fold_convert (sizetype, fpr);
7139 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7140 gimplify_assign (sse_addr, t, pre_p);
7145 tree temp = create_tmp_var (type, "va_arg_tmp");
7148 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7149 gimplify_assign (addr, t, pre_p);
7151 for (i = 0; i < XVECLEN (container, 0); i++)
7153 rtx slot = XVECEXP (container, 0, i);
7154 rtx reg = XEXP (slot, 0);
7155 enum machine_mode mode = GET_MODE (reg);
7156 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7157 tree addr_type = build_pointer_type (piece_type);
7158 tree daddr_type = build_pointer_type_for_mode (piece_type,
7162 tree dest_addr, dest;
7164 if (SSE_REGNO_P (REGNO (reg)))
7166 src_addr = sse_addr;
7167 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7171 src_addr = int_addr;
7172 src_offset = REGNO (reg) * 8;
7174 src_addr = fold_convert (addr_type, src_addr);
7175 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7176 size_int (src_offset));
7177 src = build_va_arg_indirect_ref (src_addr);
7179 dest_addr = fold_convert (daddr_type, addr);
7180 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7181 size_int (INTVAL (XEXP (slot, 1))));
7182 dest = build_va_arg_indirect_ref (dest_addr);
7184 gimplify_assign (dest, src, pre_p);
7190 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7191 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7192 gimplify_assign (gpr, t, pre_p);
7197 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7198 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7199 gimplify_assign (fpr, t, pre_p);
7202 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7204 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7207 /* ... otherwise out of the overflow area. */
7209 /* When we align parameter on stack for caller, if the parameter
7210 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7211 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7212 here with caller. */
7213 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7214 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7215 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7217 /* Care for on-stack alignment if needed. */
7218 if (arg_boundary <= 64
7219 || integer_zerop (TYPE_SIZE (type)))
7223 HOST_WIDE_INT align = arg_boundary / 8;
7224 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7225 size_int (align - 1));
7226 t = fold_convert (sizetype, t);
7227 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7229 t = fold_convert (TREE_TYPE (ovf), t);
7231 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7232 gimplify_assign (addr, t, pre_p);
7234 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7235 size_int (rsize * UNITS_PER_WORD));
7236 gimplify_assign (unshare_expr (ovf), t, pre_p);
7239 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7241 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7242 addr = fold_convert (ptrtype, addr);
7245 addr = build_va_arg_indirect_ref (addr);
7246 return build_va_arg_indirect_ref (addr);
7249 /* Return nonzero if OPNUM's MEM should be matched
7250 in movabs* patterns. */
7253 ix86_check_movabs (rtx insn, int opnum)
7257 set = PATTERN (insn);
7258 if (GET_CODE (set) == PARALLEL)
7259 set = XVECEXP (set, 0, 0);
7260 gcc_assert (GET_CODE (set) == SET);
7261 mem = XEXP (set, opnum);
7262 while (GET_CODE (mem) == SUBREG)
7263 mem = SUBREG_REG (mem);
7264 gcc_assert (MEM_P (mem));
7265 return (volatile_ok || !MEM_VOLATILE_P (mem));
7268 /* Initialize the table of extra 80387 mathematical constants. */
7271 init_ext_80387_constants (void)
7273 static const char * cst[5] =
7275 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7276 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7277 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7278 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7279 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7283 for (i = 0; i < 5; i++)
7285 real_from_string (&ext_80387_constants_table[i], cst[i]);
7286 /* Ensure each constant is rounded to XFmode precision. */
7287 real_convert (&ext_80387_constants_table[i],
7288 XFmode, &ext_80387_constants_table[i]);
7291 ext_80387_constants_init = 1;
7294 /* Return true if the constant is something that can be loaded with
7295 a special instruction. */
7298 standard_80387_constant_p (rtx x)
7300 enum machine_mode mode = GET_MODE (x);
7304 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7307 if (x == CONST0_RTX (mode))
7309 if (x == CONST1_RTX (mode))
7312 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7314 /* For XFmode constants, try to find a special 80387 instruction when
7315 optimizing for size or on those CPUs that benefit from them. */
7317 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7321 if (! ext_80387_constants_init)
7322 init_ext_80387_constants ();
7324 for (i = 0; i < 5; i++)
7325 if (real_identical (&r, &ext_80387_constants_table[i]))
7329 /* Load of the constant -0.0 or -1.0 will be split as
7330 fldz;fchs or fld1;fchs sequence. */
7331 if (real_isnegzero (&r))
7333 if (real_identical (&r, &dconstm1))
7339 /* Return the opcode of the special instruction to be used to load
7343 standard_80387_constant_opcode (rtx x)
7345 switch (standard_80387_constant_p (x))
7369 /* Return the CONST_DOUBLE representing the 80387 constant that is
7370 loaded by the specified special instruction. The argument IDX
7371 matches the return value from standard_80387_constant_p. */
7374 standard_80387_constant_rtx (int idx)
7378 if (! ext_80387_constants_init)
7379 init_ext_80387_constants ();
7395 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7399 /* Return 1 if X is all 0s and 2 if x is all 1s
7400 in supported SSE vector mode. */
7403 standard_sse_constant_p (rtx x)
7405 enum machine_mode mode = GET_MODE (x);
7407 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7409 if (vector_all_ones_operand (x, mode))
7425 /* Return the opcode of the special instruction to be used to load
7429 standard_sse_constant_opcode (rtx insn, rtx x)
7431 switch (standard_sse_constant_p (x))
7434 switch (get_attr_mode (insn))
7437 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7439 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7441 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7443 return "vxorps\t%x0, %x0, %x0";
7445 return "vxorpd\t%x0, %x0, %x0";
7447 return "vpxor\t%x0, %x0, %x0";
7452 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7459 /* Returns 1 if OP contains a symbol reference */
7462 symbolic_reference_mentioned_p (rtx op)
7467 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7470 fmt = GET_RTX_FORMAT (GET_CODE (op));
7471 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7477 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7478 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7482 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7489 /* Return 1 if it is appropriate to emit `ret' instructions in the
7490 body of a function. Do this only if the epilogue is simple, needing a
7491 couple of insns. Prior to reloading, we can't tell how many registers
7492 must be saved, so return 0 then. Return 0 if there is no frame
7493 marker to de-allocate. */
7496 ix86_can_use_return_insn_p (void)
7498 struct ix86_frame frame;
7500 if (! reload_completed || frame_pointer_needed)
7503 /* Don't allow more than 32 pop, since that's all we can do
7504 with one instruction. */
7505 if (crtl->args.pops_args
7506 && crtl->args.size >= 32768)
7509 ix86_compute_frame_layout (&frame);
7510 return frame.to_allocate == 0 && frame.padding0 == 0
7511 && (frame.nregs + frame.nsseregs) == 0;
7514 /* Value should be nonzero if functions must have frame pointers.
7515 Zero means the frame pointer need not be set up (and parms may
7516 be accessed via the stack pointer) in functions that seem suitable. */
7519 ix86_frame_pointer_required (void)
7521 /* If we accessed previous frames, then the generated code expects
7522 to be able to access the saved ebp value in our frame. */
7523 if (cfun->machine->accesses_prev_frame)
7526 /* Several x86 os'es need a frame pointer for other reasons,
7527 usually pertaining to setjmp. */
7528 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7531 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7532 the frame pointer by default. Turn it back on now if we've not
7533 got a leaf function. */
7534 if (TARGET_OMIT_LEAF_FRAME_POINTER
7535 && (!current_function_is_leaf
7536 || ix86_current_function_calls_tls_descriptor))
7545 /* Record that the current function accesses previous call frames. */
7548 ix86_setup_frame_addresses (void)
7550 cfun->machine->accesses_prev_frame = 1;
7553 #ifndef USE_HIDDEN_LINKONCE
7554 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7555 # define USE_HIDDEN_LINKONCE 1
7557 # define USE_HIDDEN_LINKONCE 0
7561 static int pic_labels_used;
7563 /* Fills in the label name that should be used for a pc thunk for
7564 the given register. */
7567 get_pc_thunk_name (char name[32], unsigned int regno)
7569 gcc_assert (!TARGET_64BIT);
7571 if (USE_HIDDEN_LINKONCE)
7572 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7574 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7578 /* This function generates code for -fpic that loads %ebx with
7579 the return address of the caller and then returns. */
7582 ix86_file_end (void)
7587 for (regno = 0; regno < 8; ++regno)
7591 if (! ((pic_labels_used >> regno) & 1))
7594 get_pc_thunk_name (name, regno);
7599 switch_to_section (darwin_sections[text_coal_section]);
7600 fputs ("\t.weak_definition\t", asm_out_file);
7601 assemble_name (asm_out_file, name);
7602 fputs ("\n\t.private_extern\t", asm_out_file);
7603 assemble_name (asm_out_file, name);
7604 fputs ("\n", asm_out_file);
7605 ASM_OUTPUT_LABEL (asm_out_file, name);
7609 if (USE_HIDDEN_LINKONCE)
7613 decl = build_decl (BUILTINS_LOCATION,
7614 FUNCTION_DECL, get_identifier (name),
7616 TREE_PUBLIC (decl) = 1;
7617 TREE_STATIC (decl) = 1;
7618 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7620 (*targetm.asm_out.unique_section) (decl, 0);
7621 switch_to_section (get_named_section (decl, NULL, 0));
7623 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7624 fputs ("\t.hidden\t", asm_out_file);
7625 assemble_name (asm_out_file, name);
7626 putc ('\n', asm_out_file);
7627 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7631 switch_to_section (text_section);
7632 ASM_OUTPUT_LABEL (asm_out_file, name);
7635 xops[0] = gen_rtx_REG (Pmode, regno);
7636 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7637 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7638 output_asm_insn ("ret", xops);
7641 if (NEED_INDICATE_EXEC_STACK)
7642 file_end_indicate_exec_stack ();
7645 /* Emit code for the SET_GOT patterns. */
7648 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7654 if (TARGET_VXWORKS_RTP && flag_pic)
7656 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7657 xops[2] = gen_rtx_MEM (Pmode,
7658 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7659 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7661 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7662 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7663 an unadorned address. */
7664 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7665 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7666 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7670 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7672 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7674 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7677 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7679 output_asm_insn ("call\t%a2", xops);
7682 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7683 is what will be referenced by the Mach-O PIC subsystem. */
7685 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7688 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7689 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7692 output_asm_insn ("pop%z0\t%0", xops);
7697 get_pc_thunk_name (name, REGNO (dest));
7698 pic_labels_used |= 1 << REGNO (dest);
7700 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7701 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7702 output_asm_insn ("call\t%X2", xops);
7703 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7704 is what will be referenced by the Mach-O PIC subsystem. */
7707 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7709 targetm.asm_out.internal_label (asm_out_file, "L",
7710 CODE_LABEL_NUMBER (label));
7717 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7718 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7720 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7725 /* Generate an "push" pattern for input ARG. */
7730 if (ix86_cfa_state->reg == stack_pointer_rtx)
7731 ix86_cfa_state->offset += UNITS_PER_WORD;
7733 return gen_rtx_SET (VOIDmode,
7735 gen_rtx_PRE_DEC (Pmode,
7736 stack_pointer_rtx)),
7740 /* Return >= 0 if there is an unused call-clobbered register available
7741 for the entire function. */
7744 ix86_select_alt_pic_regnum (void)
7746 if (current_function_is_leaf && !crtl->profile
7747 && !ix86_current_function_calls_tls_descriptor)
7750 /* Can't use the same register for both PIC and DRAP. */
7752 drap = REGNO (crtl->drap_reg);
7755 for (i = 2; i >= 0; --i)
7756 if (i != drap && !df_regs_ever_live_p (i))
7760 return INVALID_REGNUM;
7763 /* Return 1 if we need to save REGNO. */
7765 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7767 if (pic_offset_table_rtx
7768 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7769 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7771 || crtl->calls_eh_return
7772 || crtl->uses_const_pool))
7774 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7779 if (crtl->calls_eh_return && maybe_eh_return)
7784 unsigned test = EH_RETURN_DATA_REGNO (i);
7785 if (test == INVALID_REGNUM)
7792 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7795 return (df_regs_ever_live_p (regno)
7796 && !call_used_regs[regno]
7797 && !fixed_regs[regno]
7798 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7801 /* Return number of saved general prupose registers. */
7804 ix86_nsaved_regs (void)
7809 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7810 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7815 /* Return number of saved SSE registrers. */
7818 ix86_nsaved_sseregs (void)
7823 if (ix86_cfun_abi () != MS_ABI)
7825 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7826 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7831 /* Given FROM and TO register numbers, say whether this elimination is
7832 allowed. If stack alignment is needed, we can only replace argument
7833 pointer with hard frame pointer, or replace frame pointer with stack
7834 pointer. Otherwise, frame pointer elimination is automatically
7835 handled and all other eliminations are valid. */
7838 ix86_can_eliminate (const int from, const int to)
7840 if (stack_realign_fp)
7841 return ((from == ARG_POINTER_REGNUM
7842 && to == HARD_FRAME_POINTER_REGNUM)
7843 || (from == FRAME_POINTER_REGNUM
7844 && to == STACK_POINTER_REGNUM));
7846 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7849 /* Return the offset between two registers, one to be eliminated, and the other
7850 its replacement, at the start of a routine. */
7853 ix86_initial_elimination_offset (int from, int to)
7855 struct ix86_frame frame;
7856 ix86_compute_frame_layout (&frame);
7858 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7859 return frame.hard_frame_pointer_offset;
7860 else if (from == FRAME_POINTER_REGNUM
7861 && to == HARD_FRAME_POINTER_REGNUM)
7862 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7865 gcc_assert (to == STACK_POINTER_REGNUM);
7867 if (from == ARG_POINTER_REGNUM)
7868 return frame.stack_pointer_offset;
7870 gcc_assert (from == FRAME_POINTER_REGNUM);
7871 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7875 /* In a dynamically-aligned function, we can't know the offset from
7876 stack pointer to frame pointer, so we must ensure that setjmp
7877 eliminates fp against the hard fp (%ebp) rather than trying to
7878 index from %esp up to the top of the frame across a gap that is
7879 of unknown (at compile-time) size. */
7881 ix86_builtin_setjmp_frame_value (void)
7883 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7886 /* Fill structure ix86_frame about frame of currently computed function. */
7889 ix86_compute_frame_layout (struct ix86_frame *frame)
7891 unsigned int stack_alignment_needed;
7892 HOST_WIDE_INT offset;
7893 unsigned int preferred_alignment;
7894 HOST_WIDE_INT size = get_frame_size ();
7896 frame->nregs = ix86_nsaved_regs ();
7897 frame->nsseregs = ix86_nsaved_sseregs ();
7899 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7900 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7902 /* MS ABI seem to require stack alignment to be always 16 except for function
7904 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7906 preferred_alignment = 16;
7907 stack_alignment_needed = 16;
7908 crtl->preferred_stack_boundary = 128;
7909 crtl->stack_alignment_needed = 128;
7912 gcc_assert (!size || stack_alignment_needed);
7913 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7914 gcc_assert (preferred_alignment <= stack_alignment_needed);
7916 /* During reload iteration the amount of registers saved can change.
7917 Recompute the value as needed. Do not recompute when amount of registers
7918 didn't change as reload does multiple calls to the function and does not
7919 expect the decision to change within single iteration. */
7920 if (!optimize_function_for_size_p (cfun)
7921 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7923 int count = frame->nregs;
7925 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7926 /* The fast prologue uses move instead of push to save registers. This
7927 is significantly longer, but also executes faster as modern hardware
7928 can execute the moves in parallel, but can't do that for push/pop.
7930 Be careful about choosing what prologue to emit: When function takes
7931 many instructions to execute we may use slow version as well as in
7932 case function is known to be outside hot spot (this is known with
7933 feedback only). Weight the size of function by number of registers
7934 to save as it is cheap to use one or two push instructions but very
7935 slow to use many of them. */
7937 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7938 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7939 || (flag_branch_probabilities
7940 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7941 cfun->machine->use_fast_prologue_epilogue = false;
7943 cfun->machine->use_fast_prologue_epilogue
7944 = !expensive_function_p (count);
7946 if (TARGET_PROLOGUE_USING_MOVE
7947 && cfun->machine->use_fast_prologue_epilogue)
7948 frame->save_regs_using_mov = true;
7950 frame->save_regs_using_mov = false;
7952 /* Skip return address. */
7953 offset = UNITS_PER_WORD;
7955 /* Skip pushed static chain. */
7956 if (ix86_static_chain_on_stack)
7957 offset += UNITS_PER_WORD;
7959 /* Skip saved base pointer. */
7960 if (frame_pointer_needed)
7961 offset += UNITS_PER_WORD;
7963 frame->hard_frame_pointer_offset = offset;
7965 /* Set offset to aligned because the realigned frame starts from
7967 if (stack_realign_fp)
7968 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7970 /* Register save area */
7971 offset += frame->nregs * UNITS_PER_WORD;
7973 /* Align SSE reg save area. */
7974 if (frame->nsseregs)
7975 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7977 frame->padding0 = 0;
7979 /* SSE register save area. */
7980 offset += frame->padding0 + frame->nsseregs * 16;
7983 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7984 offset += frame->va_arg_size;
7986 /* Align start of frame for local function. */
7987 frame->padding1 = ((offset + stack_alignment_needed - 1)
7988 & -stack_alignment_needed) - offset;
7990 offset += frame->padding1;
7992 /* Frame pointer points here. */
7993 frame->frame_pointer_offset = offset;
7997 /* Add outgoing arguments area. Can be skipped if we eliminated
7998 all the function calls as dead code.
7999 Skipping is however impossible when function calls alloca. Alloca
8000 expander assumes that last crtl->outgoing_args_size
8001 of stack frame are unused. */
8002 if (ACCUMULATE_OUTGOING_ARGS
8003 && (!current_function_is_leaf || cfun->calls_alloca
8004 || ix86_current_function_calls_tls_descriptor))
8006 offset += crtl->outgoing_args_size;
8007 frame->outgoing_arguments_size = crtl->outgoing_args_size;
8010 frame->outgoing_arguments_size = 0;
8012 /* Align stack boundary. Only needed if we're calling another function
8014 if (!current_function_is_leaf || cfun->calls_alloca
8015 || ix86_current_function_calls_tls_descriptor)
8016 frame->padding2 = ((offset + preferred_alignment - 1)
8017 & -preferred_alignment) - offset;
8019 frame->padding2 = 0;
8021 offset += frame->padding2;
8023 /* We've reached end of stack frame. */
8024 frame->stack_pointer_offset = offset;
8026 /* Size prologue needs to allocate. */
8027 frame->to_allocate =
8028 (size + frame->padding1 + frame->padding2
8029 + frame->outgoing_arguments_size + frame->va_arg_size);
8031 if ((!frame->to_allocate && frame->nregs <= 1)
8032 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
8033 frame->save_regs_using_mov = false;
8035 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8036 && current_function_sp_is_unchanging
8037 && current_function_is_leaf
8038 && !ix86_current_function_calls_tls_descriptor)
8040 frame->red_zone_size = frame->to_allocate;
8041 if (frame->save_regs_using_mov)
8042 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
8043 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
8044 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
8047 frame->red_zone_size = 0;
8048 frame->to_allocate -= frame->red_zone_size;
8049 frame->stack_pointer_offset -= frame->red_zone_size;
8052 /* Emit code to save registers in the prologue. */
8055 ix86_emit_save_regs (void)
8060 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
8061 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8063 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
8064 RTX_FRAME_RELATED_P (insn) = 1;
8068 /* Emit code to save registers using MOV insns. First register
8069 is restored from POINTER + OFFSET. */
8071 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8076 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8077 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8079 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8081 gen_rtx_REG (Pmode, regno));
8082 RTX_FRAME_RELATED_P (insn) = 1;
8083 offset += UNITS_PER_WORD;
8087 /* Emit code to save registers using MOV insns. First register
8088 is restored from POINTER + OFFSET. */
8090 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8096 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8097 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8099 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8100 set_mem_align (mem, 128);
8101 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8102 RTX_FRAME_RELATED_P (insn) = 1;
8107 static GTY(()) rtx queued_cfa_restores;
8109 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8110 manipulation insn. Don't add it if the previously
8111 saved value will be left untouched within stack red-zone till return,
8112 as unwinders can find the same value in the register and
8116 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8119 && !TARGET_64BIT_MS_ABI
8120 && red_offset + RED_ZONE_SIZE >= 0
8121 && crtl->args.pops_args < 65536)
8126 add_reg_note (insn, REG_CFA_RESTORE, reg);
8127 RTX_FRAME_RELATED_P (insn) = 1;
8131 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8134 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8137 ix86_add_queued_cfa_restore_notes (rtx insn)
8140 if (!queued_cfa_restores)
8142 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8144 XEXP (last, 1) = REG_NOTES (insn);
8145 REG_NOTES (insn) = queued_cfa_restores;
8146 queued_cfa_restores = NULL_RTX;
8147 RTX_FRAME_RELATED_P (insn) = 1;
8150 /* Expand prologue or epilogue stack adjustment.
8151 The pattern exist to put a dependency on all ebp-based memory accesses.
8152 STYLE should be negative if instructions should be marked as frame related,
8153 zero if %r11 register is live and cannot be freely used and positive
8157 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8158 int style, bool set_cfa)
8163 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8164 else if (x86_64_immediate_operand (offset, DImode))
8165 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8169 /* r11 is used by indirect sibcall return as well, set before the
8170 epilogue and used after the epilogue. ATM indirect sibcall
8171 shouldn't be used together with huge frame sizes in one
8172 function because of the frame_size check in sibcall.c. */
8174 r11 = gen_rtx_REG (DImode, R11_REG);
8175 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8177 RTX_FRAME_RELATED_P (insn) = 1;
8178 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8183 ix86_add_queued_cfa_restore_notes (insn);
8189 gcc_assert (ix86_cfa_state->reg == src);
8190 ix86_cfa_state->offset += INTVAL (offset);
8191 ix86_cfa_state->reg = dest;
8193 r = gen_rtx_PLUS (Pmode, src, offset);
8194 r = gen_rtx_SET (VOIDmode, dest, r);
8195 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8196 RTX_FRAME_RELATED_P (insn) = 1;
8199 RTX_FRAME_RELATED_P (insn) = 1;
8202 /* Find an available register to be used as dynamic realign argument
8203 pointer regsiter. Such a register will be written in prologue and
8204 used in begin of body, so it must not be
8205 1. parameter passing register.
8207 We reuse static-chain register if it is available. Otherwise, we
8208 use DI for i386 and R13 for x86-64. We chose R13 since it has
8211 Return: the regno of chosen register. */
8214 find_drap_reg (void)
8216 tree decl = cfun->decl;
8220 /* Use R13 for nested function or function need static chain.
8221 Since function with tail call may use any caller-saved
8222 registers in epilogue, DRAP must not use caller-saved
8223 register in such case. */
8224 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8231 /* Use DI for nested function or function need static chain.
8232 Since function with tail call may use any caller-saved
8233 registers in epilogue, DRAP must not use caller-saved
8234 register in such case. */
8235 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8238 /* Reuse static chain register if it isn't used for parameter
8240 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8241 && !lookup_attribute ("fastcall",
8242 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8249 /* Return minimum incoming stack alignment. */
8252 ix86_minimum_incoming_stack_boundary (bool sibcall)
8254 unsigned int incoming_stack_boundary;
8256 /* Prefer the one specified at command line. */
8257 if (ix86_user_incoming_stack_boundary)
8258 incoming_stack_boundary = ix86_user_incoming_stack_boundary;
8259 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8260 if -mstackrealign is used, it isn't used for sibcall check and
8261 estimated stack alignment is 128bit. */
8264 && ix86_force_align_arg_pointer
8265 && crtl->stack_alignment_estimated == 128)
8266 incoming_stack_boundary = MIN_STACK_BOUNDARY;
8268 incoming_stack_boundary = ix86_default_incoming_stack_boundary;
8270 /* Incoming stack alignment can be changed on individual functions
8271 via force_align_arg_pointer attribute. We use the smallest
8272 incoming stack boundary. */
8273 if (incoming_stack_boundary > MIN_STACK_BOUNDARY
8274 && lookup_attribute (ix86_force_align_arg_pointer_string,
8275 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8276 incoming_stack_boundary = MIN_STACK_BOUNDARY;
8278 /* The incoming stack frame has to be aligned at least at
8279 parm_stack_boundary. */
8280 if (incoming_stack_boundary < crtl->parm_stack_boundary)
8281 incoming_stack_boundary = crtl->parm_stack_boundary;
8283 /* Stack at entrance of main is aligned by runtime. We use the
8284 smallest incoming stack boundary. */
8285 if (incoming_stack_boundary > MAIN_STACK_BOUNDARY
8286 && DECL_NAME (current_function_decl)
8287 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8288 && DECL_FILE_SCOPE_P (current_function_decl))
8289 incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8291 return incoming_stack_boundary;
8294 /* Update incoming stack boundary and estimated stack alignment. */
8297 ix86_update_stack_boundary (void)
8299 ix86_incoming_stack_boundary
8300 = ix86_minimum_incoming_stack_boundary (false);
8302 /* x86_64 vararg needs 16byte stack alignment for register save
8306 && crtl->stack_alignment_estimated < 128)
8307 crtl->stack_alignment_estimated = 128;
8310 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8311 needed or an rtx for DRAP otherwise. */
8314 ix86_get_drap_rtx (void)
8316 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8317 crtl->need_drap = true;
8319 if (stack_realign_drap)
8321 /* Assign DRAP to vDRAP and returns vDRAP */
8322 unsigned int regno = find_drap_reg ();
8327 arg_ptr = gen_rtx_REG (Pmode, regno);
8328 crtl->drap_reg = arg_ptr;
8331 drap_vreg = copy_to_reg (arg_ptr);
8335 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8336 RTX_FRAME_RELATED_P (insn) = 1;
8343 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8346 ix86_internal_arg_pointer (void)
8348 return virtual_incoming_args_rtx;
8351 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8352 to be generated in correct form. */
8354 ix86_finalize_stack_realign_flags (void)
8356 /* Check if stack realign is really needed after reload, and
8357 stores result in cfun */
8358 unsigned int incoming_stack_boundary
8359 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8360 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8361 unsigned int stack_realign = (incoming_stack_boundary
8362 < (current_function_is_leaf
8363 ? crtl->max_used_stack_slot_alignment
8364 : crtl->stack_alignment_needed));
8366 if (crtl->stack_realign_finalized)
8368 /* After stack_realign_needed is finalized, we can't no longer
8370 gcc_assert (crtl->stack_realign_needed == stack_realign);
8374 crtl->stack_realign_needed = stack_realign;
8375 crtl->stack_realign_finalized = true;
8379 /* Expand the prologue into a bunch of separate insns. */
8382 ix86_expand_prologue (void)
8386 struct ix86_frame frame;
8387 HOST_WIDE_INT allocate;
8388 int gen_frame_pointer = frame_pointer_needed;
8390 ix86_finalize_stack_realign_flags ();
8392 /* DRAP should not coexist with stack_realign_fp */
8393 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8395 /* Initialize CFA state for before the prologue. */
8396 ix86_cfa_state->reg = stack_pointer_rtx;
8397 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8399 ix86_compute_frame_layout (&frame);
8401 if (ix86_function_ms_hook_prologue (current_function_decl))
8405 /* Make sure the function starts with
8406 8b ff movl.s %edi,%edi
8408 8b ec movl.s %esp,%ebp
8410 This matches the hookable function prologue in Win32 API
8411 functions in Microsoft Windows XP Service Pack 2 and newer.
8412 Wine uses this to enable Windows apps to hook the Win32 API
8413 functions provided by Wine. */
8414 insn = emit_insn (gen_vswapmov (gen_rtx_REG (SImode, DI_REG),
8415 gen_rtx_REG (SImode, DI_REG)));
8416 push = emit_insn (gen_push (hard_frame_pointer_rtx));
8417 mov = emit_insn (gen_vswapmov (hard_frame_pointer_rtx,
8418 stack_pointer_rtx));
8420 if (frame_pointer_needed && !(crtl->drap_reg
8421 && crtl->stack_realign_needed))
8423 /* The push %ebp and movl.s %esp, %ebp already set up
8424 the frame pointer. No need to do this again. */
8425 gen_frame_pointer = 0;
8426 RTX_FRAME_RELATED_P (push) = 1;
8427 RTX_FRAME_RELATED_P (mov) = 1;
8428 if (ix86_cfa_state->reg == stack_pointer_rtx)
8429 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8432 /* If the frame pointer is not needed, pop %ebp again. This
8433 could be optimized for cases where ebp needs to be backed up
8434 for some other reason. If stack realignment is needed, pop
8435 the base pointer again, align the stack, and later regenerate
8436 the frame pointer setup. The frame pointer generated by the
8437 hook prologue is not aligned, so it can't be used. */
8438 insn = emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8441 /* The first insn of a function that accepts its static chain on the
8442 stack is to push the register that would be filled in by a direct
8443 call. This insn will be skipped by the trampoline. */
8444 if (ix86_static_chain_on_stack)
8448 insn = emit_insn (gen_push (ix86_static_chain (cfun->decl, false)));
8449 emit_insn (gen_blockage ());
8451 /* We don't want to interpret this push insn as a register save,
8452 only as a stack adjustment. The real copy of the register as
8453 a save will be done later, if needed. */
8454 t = plus_constant (stack_pointer_rtx, -UNITS_PER_WORD);
8455 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8456 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8457 RTX_FRAME_RELATED_P (insn) = 1;
8460 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8461 of DRAP is needed and stack realignment is really needed after reload */
8462 if (crtl->drap_reg && crtl->stack_realign_needed)
8465 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8466 int param_ptr_offset = UNITS_PER_WORD;
8468 if (ix86_static_chain_on_stack)
8469 param_ptr_offset += UNITS_PER_WORD;
8470 if (!call_used_regs[REGNO (crtl->drap_reg)])
8471 param_ptr_offset += UNITS_PER_WORD;
8473 gcc_assert (stack_realign_drap);
8475 /* Grab the argument pointer. */
8476 x = plus_constant (stack_pointer_rtx, param_ptr_offset);
8479 /* Only need to push parameter pointer reg if it is caller
8481 if (!call_used_regs[REGNO (crtl->drap_reg)])
8483 /* Push arg pointer reg */
8484 insn = emit_insn (gen_push (y));
8485 RTX_FRAME_RELATED_P (insn) = 1;
8488 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8489 RTX_FRAME_RELATED_P (insn) = 1;
8490 ix86_cfa_state->reg = crtl->drap_reg;
8492 /* Align the stack. */
8493 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8495 GEN_INT (-align_bytes)));
8496 RTX_FRAME_RELATED_P (insn) = 1;
8498 /* Replicate the return address on the stack so that return
8499 address can be reached via (argp - 1) slot. This is needed
8500 to implement macro RETURN_ADDR_RTX and intrinsic function
8501 expand_builtin_return_addr etc. */
8503 x = gen_frame_mem (Pmode,
8504 plus_constant (x, -UNITS_PER_WORD));
8505 insn = emit_insn (gen_push (x));
8506 RTX_FRAME_RELATED_P (insn) = 1;
8509 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8510 slower on all targets. Also sdb doesn't like it. */
8512 if (gen_frame_pointer)
8514 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8515 RTX_FRAME_RELATED_P (insn) = 1;
8517 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8518 RTX_FRAME_RELATED_P (insn) = 1;
8520 if (ix86_cfa_state->reg == stack_pointer_rtx)
8521 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8524 if (stack_realign_fp)
8526 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8527 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8529 /* Align the stack. */
8530 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8532 GEN_INT (-align_bytes)));
8533 RTX_FRAME_RELATED_P (insn) = 1;
8536 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8538 if (!frame.save_regs_using_mov)
8539 ix86_emit_save_regs ();
8541 allocate += frame.nregs * UNITS_PER_WORD;
8543 /* When using red zone we may start register saving before allocating
8544 the stack frame saving one cycle of the prologue. However I will
8545 avoid doing this if I am going to have to probe the stack since
8546 at least on x86_64 the stack probe can turn into a call that clobbers
8547 a red zone location */
8548 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8549 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8550 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8551 && !crtl->stack_realign_needed)
8552 ? hard_frame_pointer_rtx
8553 : stack_pointer_rtx,
8554 -frame.nregs * UNITS_PER_WORD);
8558 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8559 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8560 GEN_INT (-allocate), -1,
8561 ix86_cfa_state->reg == stack_pointer_rtx);
8564 /* Only valid for Win32. */
8565 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8569 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8571 if (cfun->machine->call_abi == MS_ABI)
8574 eax_live = ix86_eax_live_at_start_p ();
8578 emit_insn (gen_push (eax));
8579 allocate -= UNITS_PER_WORD;
8582 emit_move_insn (eax, GEN_INT (allocate));
8585 insn = gen_allocate_stack_worker_64 (eax, eax);
8587 insn = gen_allocate_stack_worker_32 (eax, eax);
8588 insn = emit_insn (insn);
8590 if (ix86_cfa_state->reg == stack_pointer_rtx)
8592 ix86_cfa_state->offset += allocate;
8593 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8594 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8595 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8596 RTX_FRAME_RELATED_P (insn) = 1;
8601 if (frame_pointer_needed)
8602 t = plus_constant (hard_frame_pointer_rtx,
8605 - frame.nregs * UNITS_PER_WORD);
8607 t = plus_constant (stack_pointer_rtx, allocate);
8608 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8612 if (frame.save_regs_using_mov
8613 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8614 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8616 if (!frame_pointer_needed
8617 || !(frame.to_allocate + frame.padding0)
8618 || crtl->stack_realign_needed)
8619 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8621 + frame.nsseregs * 16 + frame.padding0);
8623 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8624 -frame.nregs * UNITS_PER_WORD);
8626 if (!frame_pointer_needed
8627 || !(frame.to_allocate + frame.padding0)
8628 || crtl->stack_realign_needed)
8629 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8632 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8633 - frame.nregs * UNITS_PER_WORD
8634 - frame.nsseregs * 16
8637 pic_reg_used = false;
8638 if (pic_offset_table_rtx
8639 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8642 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8644 if (alt_pic_reg_used != INVALID_REGNUM)
8645 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8647 pic_reg_used = true;
8654 if (ix86_cmodel == CM_LARGE_PIC)
8656 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8657 rtx label = gen_label_rtx ();
8659 LABEL_PRESERVE_P (label) = 1;
8660 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8661 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8662 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8663 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8664 pic_offset_table_rtx, tmp_reg));
8667 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8670 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8673 /* In the pic_reg_used case, make sure that the got load isn't deleted
8674 when mcount needs it. Blockage to avoid call movement across mcount
8675 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8677 if (crtl->profile && pic_reg_used)
8678 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8680 if (crtl->drap_reg && !crtl->stack_realign_needed)
8682 /* vDRAP is setup but after reload it turns out stack realign
8683 isn't necessary, here we will emit prologue to setup DRAP
8684 without stack realign adjustment */
8686 int drap_bp_offset = UNITS_PER_WORD * 2;
8688 if (ix86_static_chain_on_stack)
8689 drap_bp_offset += UNITS_PER_WORD;
8690 x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8691 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8694 /* Prevent instructions from being scheduled into register save push
8695 sequence when access to the redzone area is done through frame pointer.
8696 The offset between the frame pointer and the stack pointer is calculated
8697 relative to the value of the stack pointer at the end of the function
8698 prologue, and moving instructions that access redzone area via frame
8699 pointer inside push sequence violates this assumption. */
8700 if (frame_pointer_needed && frame.red_zone_size)
8701 emit_insn (gen_memory_blockage ());
8703 /* Emit cld instruction if stringops are used in the function. */
8704 if (TARGET_CLD && ix86_current_function_needs_cld)
8705 emit_insn (gen_cld ());
8708 /* Emit code to restore REG using a POP insn. */
8711 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8713 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8715 if (ix86_cfa_state->reg == crtl->drap_reg
8716 && REGNO (reg) == REGNO (crtl->drap_reg))
8718 /* Previously we'd represented the CFA as an expression
8719 like *(%ebp - 8). We've just popped that value from
8720 the stack, which means we need to reset the CFA to
8721 the drap register. This will remain until we restore
8722 the stack pointer. */
8723 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8724 RTX_FRAME_RELATED_P (insn) = 1;
8728 if (ix86_cfa_state->reg == stack_pointer_rtx)
8730 ix86_cfa_state->offset -= UNITS_PER_WORD;
8731 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8732 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8733 RTX_FRAME_RELATED_P (insn) = 1;
8736 /* When the frame pointer is the CFA, and we pop it, we are
8737 swapping back to the stack pointer as the CFA. This happens
8738 for stack frames that don't allocate other data, so we assume
8739 the stack pointer is now pointing at the return address, i.e.
8740 the function entry state, which makes the offset be 1 word. */
8741 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8742 && reg == hard_frame_pointer_rtx)
8744 ix86_cfa_state->reg = stack_pointer_rtx;
8745 ix86_cfa_state->offset -= UNITS_PER_WORD;
8747 add_reg_note (insn, REG_CFA_DEF_CFA,
8748 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8749 GEN_INT (ix86_cfa_state->offset)));
8750 RTX_FRAME_RELATED_P (insn) = 1;
8753 ix86_add_cfa_restore_note (insn, reg, red_offset);
8756 /* Emit code to restore saved registers using POP insns. */
8759 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8763 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8764 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8766 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8768 red_offset += UNITS_PER_WORD;
8772 /* Emit code and notes for the LEAVE instruction. */
8775 ix86_emit_leave (HOST_WIDE_INT red_offset)
8777 rtx insn = emit_insn (ix86_gen_leave ());
8779 ix86_add_queued_cfa_restore_notes (insn);
8781 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8783 ix86_cfa_state->reg = stack_pointer_rtx;
8784 ix86_cfa_state->offset -= UNITS_PER_WORD;
8786 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8787 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8788 RTX_FRAME_RELATED_P (insn) = 1;
8789 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8793 /* Emit code to restore saved registers using MOV insns. First register
8794 is restored from POINTER + OFFSET. */
8796 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8797 HOST_WIDE_INT red_offset,
8798 int maybe_eh_return)
8801 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8804 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8805 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8807 rtx reg = gen_rtx_REG (Pmode, regno);
8809 /* Ensure that adjust_address won't be forced to produce pointer
8810 out of range allowed by x86-64 instruction set. */
8811 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8815 r11 = gen_rtx_REG (DImode, R11_REG);
8816 emit_move_insn (r11, GEN_INT (offset));
8817 emit_insn (gen_adddi3 (r11, r11, pointer));
8818 base_address = gen_rtx_MEM (Pmode, r11);
8821 insn = emit_move_insn (reg,
8822 adjust_address (base_address, Pmode, offset));
8823 offset += UNITS_PER_WORD;
8825 if (ix86_cfa_state->reg == crtl->drap_reg
8826 && regno == REGNO (crtl->drap_reg))
8828 /* Previously we'd represented the CFA as an expression
8829 like *(%ebp - 8). We've just popped that value from
8830 the stack, which means we need to reset the CFA to
8831 the drap register. This will remain until we restore
8832 the stack pointer. */
8833 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8834 RTX_FRAME_RELATED_P (insn) = 1;
8837 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8839 red_offset += UNITS_PER_WORD;
8843 /* Emit code to restore saved registers using MOV insns. First register
8844 is restored from POINTER + OFFSET. */
8846 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8847 HOST_WIDE_INT red_offset,
8848 int maybe_eh_return)
8851 rtx base_address = gen_rtx_MEM (TImode, pointer);
8854 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8855 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8857 rtx reg = gen_rtx_REG (TImode, regno);
8859 /* Ensure that adjust_address won't be forced to produce pointer
8860 out of range allowed by x86-64 instruction set. */
8861 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8865 r11 = gen_rtx_REG (DImode, R11_REG);
8866 emit_move_insn (r11, GEN_INT (offset));
8867 emit_insn (gen_adddi3 (r11, r11, pointer));
8868 base_address = gen_rtx_MEM (TImode, r11);
8871 mem = adjust_address (base_address, TImode, offset);
8872 set_mem_align (mem, 128);
8873 insn = emit_move_insn (reg, mem);
8876 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8882 /* Restore function stack, frame, and registers. */
8885 ix86_expand_epilogue (int style)
8888 struct ix86_frame frame;
8889 HOST_WIDE_INT offset, red_offset;
8890 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8893 ix86_finalize_stack_realign_flags ();
8895 /* When stack is realigned, SP must be valid. */
8896 sp_valid = (!frame_pointer_needed
8897 || current_function_sp_is_unchanging
8898 || stack_realign_fp);
8900 ix86_compute_frame_layout (&frame);
8902 /* See the comment about red zone and frame
8903 pointer usage in ix86_expand_prologue. */
8904 if (frame_pointer_needed && frame.red_zone_size)
8905 emit_insn (gen_memory_blockage ());
8907 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8908 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8910 /* Calculate start of saved registers relative to ebp. Special care
8911 must be taken for the normal return case of a function using
8912 eh_return: the eax and edx registers are marked as saved, but not
8913 restored along this path. */
8914 offset = frame.nregs;
8915 if (crtl->calls_eh_return && style != 2)
8917 offset *= -UNITS_PER_WORD;
8918 offset -= frame.nsseregs * 16 + frame.padding0;
8920 /* Calculate start of saved registers relative to esp on entry of the
8921 function. When realigning stack, this needs to be the most negative
8922 value possible at runtime. */
8923 red_offset = offset;
8925 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8927 else if (stack_realign_fp)
8928 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8930 if (ix86_static_chain_on_stack)
8931 red_offset -= UNITS_PER_WORD;
8932 if (frame_pointer_needed)
8933 red_offset -= UNITS_PER_WORD;
8935 /* If we're only restoring one register and sp is not valid then
8936 using a move instruction to restore the register since it's
8937 less work than reloading sp and popping the register.
8939 The default code result in stack adjustment using add/lea instruction,
8940 while this code results in LEAVE instruction (or discrete equivalent),
8941 so it is profitable in some other cases as well. Especially when there
8942 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8943 and there is exactly one register to pop. This heuristic may need some
8944 tuning in future. */
8945 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8946 || (TARGET_EPILOGUE_USING_MOVE
8947 && cfun->machine->use_fast_prologue_epilogue
8948 && ((frame.nregs + frame.nsseregs) > 1
8949 || (frame.to_allocate + frame.padding0) != 0))
8950 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8951 && (frame.to_allocate + frame.padding0) != 0)
8952 || (frame_pointer_needed && TARGET_USE_LEAVE
8953 && cfun->machine->use_fast_prologue_epilogue
8954 && (frame.nregs + frame.nsseregs) == 1)
8955 || crtl->calls_eh_return)
8957 /* Restore registers. We can use ebp or esp to address the memory
8958 locations. If both are available, default to ebp, since offsets
8959 are known to be small. Only exception is esp pointing directly
8960 to the end of block of saved registers, where we may simplify
8963 If we are realigning stack with bp and sp, regs restore can't
8964 be addressed by bp. sp must be used instead. */
8966 if (!frame_pointer_needed
8967 || (sp_valid && !(frame.to_allocate + frame.padding0))
8968 || stack_realign_fp)
8970 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8971 frame.to_allocate, red_offset,
8973 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8975 + frame.nsseregs * 16
8978 + frame.nsseregs * 16
8979 + frame.padding0, style == 2);
8983 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8986 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8988 + frame.nsseregs * 16
8991 + frame.nsseregs * 16
8992 + frame.padding0, style == 2);
8995 red_offset -= offset;
8997 /* eh_return epilogues need %ecx added to the stack pointer. */
9000 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
9002 /* Stack align doesn't work with eh_return. */
9003 gcc_assert (!crtl->stack_realign_needed);
9004 /* Neither does regparm nested functions. */
9005 gcc_assert (!ix86_static_chain_on_stack);
9007 if (frame_pointer_needed)
9009 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
9010 tmp = plus_constant (tmp, UNITS_PER_WORD);
9011 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
9013 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
9014 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
9016 /* Note that we use SA as a temporary CFA, as the return
9017 address is at the proper place relative to it. We
9018 pretend this happens at the FP restore insn because
9019 prior to this insn the FP would be stored at the wrong
9020 offset relative to SA, and after this insn we have no
9021 other reasonable register to use for the CFA. We don't
9022 bother resetting the CFA to the SP for the duration of
9024 add_reg_note (tmp, REG_CFA_DEF_CFA,
9025 plus_constant (sa, UNITS_PER_WORD));
9026 ix86_add_queued_cfa_restore_notes (tmp);
9027 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
9028 RTX_FRAME_RELATED_P (tmp) = 1;
9029 ix86_cfa_state->reg = sa;
9030 ix86_cfa_state->offset = UNITS_PER_WORD;
9032 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
9033 const0_rtx, style, false);
9037 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
9038 tmp = plus_constant (tmp, (frame.to_allocate
9039 + frame.nregs * UNITS_PER_WORD
9040 + frame.nsseregs * 16
9042 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
9043 ix86_add_queued_cfa_restore_notes (tmp);
9045 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9046 if (ix86_cfa_state->offset != UNITS_PER_WORD)
9048 ix86_cfa_state->offset = UNITS_PER_WORD;
9049 add_reg_note (tmp, REG_CFA_DEF_CFA,
9050 plus_constant (stack_pointer_rtx,
9052 RTX_FRAME_RELATED_P (tmp) = 1;
9056 else if (!frame_pointer_needed)
9057 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9058 GEN_INT (frame.to_allocate
9059 + frame.nregs * UNITS_PER_WORD
9060 + frame.nsseregs * 16
9062 style, !using_drap);
9063 /* If not an i386, mov & pop is faster than "leave". */
9064 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
9065 || !cfun->machine->use_fast_prologue_epilogue)
9066 ix86_emit_leave (red_offset);
9069 pro_epilogue_adjust_stack (stack_pointer_rtx,
9070 hard_frame_pointer_rtx,
9071 const0_rtx, style, !using_drap);
9073 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
9078 /* First step is to deallocate the stack frame so that we can
9081 If we realign stack with frame pointer, then stack pointer
9082 won't be able to recover via lea $offset(%bp), %sp, because
9083 there is a padding area between bp and sp for realign.
9084 "add $to_allocate, %sp" must be used instead. */
9087 gcc_assert (frame_pointer_needed);
9088 gcc_assert (!stack_realign_fp);
9089 pro_epilogue_adjust_stack (stack_pointer_rtx,
9090 hard_frame_pointer_rtx,
9091 GEN_INT (offset), style, false);
9092 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9095 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9096 GEN_INT (frame.nsseregs * 16
9100 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
9102 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9103 frame.to_allocate, red_offset,
9105 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9106 GEN_INT (frame.to_allocate
9107 + frame.nsseregs * 16
9108 + frame.padding0), style,
9109 !using_drap && !frame_pointer_needed);
9112 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
9114 red_offset -= offset;
9116 if (frame_pointer_needed)
9118 /* Leave results in shorter dependency chains on CPUs that are
9119 able to grok it fast. */
9120 if (TARGET_USE_LEAVE)
9121 ix86_emit_leave (red_offset);
9124 /* For stack realigned really happens, recover stack
9125 pointer to hard frame pointer is a must, if not using
9127 if (stack_realign_fp)
9128 pro_epilogue_adjust_stack (stack_pointer_rtx,
9129 hard_frame_pointer_rtx,
9130 const0_rtx, style, !using_drap);
9131 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
9139 int param_ptr_offset = UNITS_PER_WORD;
9142 gcc_assert (stack_realign_drap);
9144 if (ix86_static_chain_on_stack)
9145 param_ptr_offset += UNITS_PER_WORD;
9146 if (!call_used_regs[REGNO (crtl->drap_reg)])
9147 param_ptr_offset += UNITS_PER_WORD;
9149 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
9151 GEN_INT (-param_ptr_offset)));
9153 ix86_cfa_state->reg = stack_pointer_rtx;
9154 ix86_cfa_state->offset = param_ptr_offset;
9156 add_reg_note (insn, REG_CFA_DEF_CFA,
9157 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9158 GEN_INT (ix86_cfa_state->offset)));
9159 RTX_FRAME_RELATED_P (insn) = 1;
9161 if (!call_used_regs[REGNO (crtl->drap_reg)])
9162 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9165 /* Remove the saved static chain from the stack. The use of ECX is
9166 merely as a scratch register, not as the actual static chain. */
9167 if (ix86_static_chain_on_stack)
9171 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9172 ix86_cfa_state->offset += UNITS_PER_WORD;
9174 r = gen_rtx_REG (Pmode, CX_REG);
9175 insn = emit_insn (ix86_gen_pop1 (r));
9177 r = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
9178 r = gen_rtx_SET (VOIDmode, stack_pointer_rtx, r);
9179 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
9180 RTX_FRAME_RELATED_P (insn) = 1;
9183 /* Sibcall epilogues don't want a return instruction. */
9186 *ix86_cfa_state = cfa_state_save;
9190 if (crtl->args.pops_args && crtl->args.size)
9192 rtx popc = GEN_INT (crtl->args.pops_args);
9194 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9195 address, do explicit add, and jump indirectly to the caller. */
9197 if (crtl->args.pops_args >= 65536)
9199 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9202 /* There is no "pascal" calling convention in any 64bit ABI. */
9203 gcc_assert (!TARGET_64BIT);
9205 insn = emit_insn (gen_popsi1 (ecx));
9206 ix86_cfa_state->offset -= UNITS_PER_WORD;
9208 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9209 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9210 add_reg_note (insn, REG_CFA_REGISTER,
9211 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9212 RTX_FRAME_RELATED_P (insn) = 1;
9214 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9216 emit_jump_insn (gen_return_indirect_internal (ecx));
9219 emit_jump_insn (gen_return_pop_internal (popc));
9222 emit_jump_insn (gen_return_internal ());
9224 /* Restore the state back to the state from the prologue,
9225 so that it's correct for the next epilogue. */
9226 *ix86_cfa_state = cfa_state_save;
9229 /* Reset from the function's potential modifications. */
9232 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9233 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9235 if (pic_offset_table_rtx)
9236 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9238 /* Mach-O doesn't support labels at the end of objects, so if
9239 it looks like we might want one, insert a NOP. */
9241 rtx insn = get_last_insn ();
9244 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9245 insn = PREV_INSN (insn);
9249 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9250 fputs ("\tnop\n", file);
9256 /* Extract the parts of an RTL expression that is a valid memory address
9257 for an instruction. Return 0 if the structure of the address is
9258 grossly off. Return -1 if the address contains ASHIFT, so it is not
9259 strictly valid, but still used for computing length of lea instruction. */
9262 ix86_decompose_address (rtx addr, struct ix86_address *out)
9264 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9265 rtx base_reg, index_reg;
9266 HOST_WIDE_INT scale = 1;
9267 rtx scale_rtx = NULL_RTX;
9269 enum ix86_address_seg seg = SEG_DEFAULT;
9271 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9273 else if (GET_CODE (addr) == PLUS)
9283 addends[n++] = XEXP (op, 1);
9286 while (GET_CODE (op) == PLUS);
9291 for (i = n; i >= 0; --i)
9294 switch (GET_CODE (op))
9299 index = XEXP (op, 0);
9300 scale_rtx = XEXP (op, 1);
9304 if (XINT (op, 1) == UNSPEC_TP
9305 && TARGET_TLS_DIRECT_SEG_REFS
9306 && seg == SEG_DEFAULT)
9307 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9336 else if (GET_CODE (addr) == MULT)
9338 index = XEXP (addr, 0); /* index*scale */
9339 scale_rtx = XEXP (addr, 1);
9341 else if (GET_CODE (addr) == ASHIFT)
9345 /* We're called for lea too, which implements ashift on occasion. */
9346 index = XEXP (addr, 0);
9347 tmp = XEXP (addr, 1);
9348 if (!CONST_INT_P (tmp))
9350 scale = INTVAL (tmp);
9351 if ((unsigned HOST_WIDE_INT) scale > 3)
9357 disp = addr; /* displacement */
9359 /* Extract the integral value of scale. */
9362 if (!CONST_INT_P (scale_rtx))
9364 scale = INTVAL (scale_rtx);
9367 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9368 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9370 /* Avoid useless 0 displacement. */
9371 if (disp == const0_rtx && (base || index))
9374 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9375 if (base_reg && index_reg && scale == 1
9376 && (index_reg == arg_pointer_rtx
9377 || index_reg == frame_pointer_rtx
9378 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9381 tmp = base, base = index, index = tmp;
9382 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9385 /* Special case: %ebp cannot be encoded as a base without a displacement.
9389 && (base_reg == hard_frame_pointer_rtx
9390 || base_reg == frame_pointer_rtx
9391 || base_reg == arg_pointer_rtx
9392 || (REG_P (base_reg)
9393 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9394 || REGNO (base_reg) == R13_REG))))
9397 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9398 Avoid this by transforming to [%esi+0].
9399 Reload calls address legitimization without cfun defined, so we need
9400 to test cfun for being non-NULL. */
9401 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9402 && base_reg && !index_reg && !disp
9404 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9407 /* Special case: encode reg+reg instead of reg*2. */
9408 if (!base && index && scale == 2)
9409 base = index, base_reg = index_reg, scale = 1;
9411 /* Special case: scaling cannot be encoded without base or displacement. */
9412 if (!base && !disp && index && scale != 1)
9424 /* Return cost of the memory address x.
9425 For i386, it is better to use a complex address than let gcc copy
9426 the address into a reg and make a new pseudo. But not if the address
9427 requires to two regs - that would mean more pseudos with longer
9430 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9432 struct ix86_address parts;
9434 int ok = ix86_decompose_address (x, &parts);
9438 if (parts.base && GET_CODE (parts.base) == SUBREG)
9439 parts.base = SUBREG_REG (parts.base);
9440 if (parts.index && GET_CODE (parts.index) == SUBREG)
9441 parts.index = SUBREG_REG (parts.index);
9443 /* Attempt to minimize number of registers in the address. */
9445 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9447 && (!REG_P (parts.index)
9448 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9452 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9454 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9455 && parts.base != parts.index)
9458 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9459 since it's predecode logic can't detect the length of instructions
9460 and it degenerates to vector decoded. Increase cost of such
9461 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9462 to split such addresses or even refuse such addresses at all.
9464 Following addressing modes are affected:
9469 The first and last case may be avoidable by explicitly coding the zero in
9470 memory address, but I don't have AMD-K6 machine handy to check this
9474 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9475 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9476 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9482 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9483 this is used for to form addresses to local data when -fPIC is in
9487 darwin_local_data_pic (rtx disp)
9489 return (GET_CODE (disp) == UNSPEC
9490 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9493 /* Determine if a given RTX is a valid constant. We already know this
9494 satisfies CONSTANT_P. */
9497 legitimate_constant_p (rtx x)
9499 switch (GET_CODE (x))
9504 if (GET_CODE (x) == PLUS)
9506 if (!CONST_INT_P (XEXP (x, 1)))
9511 if (TARGET_MACHO && darwin_local_data_pic (x))
9514 /* Only some unspecs are valid as "constants". */
9515 if (GET_CODE (x) == UNSPEC)
9516 switch (XINT (x, 1))
9521 return TARGET_64BIT;
9524 x = XVECEXP (x, 0, 0);
9525 return (GET_CODE (x) == SYMBOL_REF
9526 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9528 x = XVECEXP (x, 0, 0);
9529 return (GET_CODE (x) == SYMBOL_REF
9530 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9535 /* We must have drilled down to a symbol. */
9536 if (GET_CODE (x) == LABEL_REF)
9538 if (GET_CODE (x) != SYMBOL_REF)
9543 /* TLS symbols are never valid. */
9544 if (SYMBOL_REF_TLS_MODEL (x))
9547 /* DLLIMPORT symbols are never valid. */
9548 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9549 && SYMBOL_REF_DLLIMPORT_P (x))
9554 if (GET_MODE (x) == TImode
9555 && x != CONST0_RTX (TImode)
9561 if (!standard_sse_constant_p (x))
9568 /* Otherwise we handle everything else in the move patterns. */
9572 /* Determine if it's legal to put X into the constant pool. This
9573 is not possible for the address of thread-local symbols, which
9574 is checked above. */
9577 ix86_cannot_force_const_mem (rtx x)
9579 /* We can always put integral constants and vectors in memory. */
9580 switch (GET_CODE (x))
9590 return !legitimate_constant_p (x);
9594 /* Nonzero if the constant value X is a legitimate general operand
9595 when generating PIC code. It is given that flag_pic is on and
9596 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9599 legitimate_pic_operand_p (rtx x)
9603 switch (GET_CODE (x))
9606 inner = XEXP (x, 0);
9607 if (GET_CODE (inner) == PLUS
9608 && CONST_INT_P (XEXP (inner, 1)))
9609 inner = XEXP (inner, 0);
9611 /* Only some unspecs are valid as "constants". */
9612 if (GET_CODE (inner) == UNSPEC)
9613 switch (XINT (inner, 1))
9618 return TARGET_64BIT;
9620 x = XVECEXP (inner, 0, 0);
9621 return (GET_CODE (x) == SYMBOL_REF
9622 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9623 case UNSPEC_MACHOPIC_OFFSET:
9624 return legitimate_pic_address_disp_p (x);
9632 return legitimate_pic_address_disp_p (x);
9639 /* Determine if a given CONST RTX is a valid memory displacement
9643 legitimate_pic_address_disp_p (rtx disp)
9647 /* In 64bit mode we can allow direct addresses of symbols and labels
9648 when they are not dynamic symbols. */
9651 rtx op0 = disp, op1;
9653 switch (GET_CODE (disp))
9659 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9661 op0 = XEXP (XEXP (disp, 0), 0);
9662 op1 = XEXP (XEXP (disp, 0), 1);
9663 if (!CONST_INT_P (op1)
9664 || INTVAL (op1) >= 16*1024*1024
9665 || INTVAL (op1) < -16*1024*1024)
9667 if (GET_CODE (op0) == LABEL_REF)
9669 if (GET_CODE (op0) != SYMBOL_REF)
9674 /* TLS references should always be enclosed in UNSPEC. */
9675 if (SYMBOL_REF_TLS_MODEL (op0))
9677 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9678 && ix86_cmodel != CM_LARGE_PIC)
9686 if (GET_CODE (disp) != CONST)
9688 disp = XEXP (disp, 0);
9692 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9693 of GOT tables. We should not need these anyway. */
9694 if (GET_CODE (disp) != UNSPEC
9695 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9696 && XINT (disp, 1) != UNSPEC_GOTOFF
9697 && XINT (disp, 1) != UNSPEC_PLTOFF))
9700 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9701 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9707 if (GET_CODE (disp) == PLUS)
9709 if (!CONST_INT_P (XEXP (disp, 1)))
9711 disp = XEXP (disp, 0);
9715 if (TARGET_MACHO && darwin_local_data_pic (disp))
9718 if (GET_CODE (disp) != UNSPEC)
9721 switch (XINT (disp, 1))
9726 /* We need to check for both symbols and labels because VxWorks loads
9727 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9729 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9730 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9732 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9733 While ABI specify also 32bit relocation but we don't produce it in
9734 small PIC model at all. */
9735 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9736 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9738 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9740 case UNSPEC_GOTTPOFF:
9741 case UNSPEC_GOTNTPOFF:
9742 case UNSPEC_INDNTPOFF:
9745 disp = XVECEXP (disp, 0, 0);
9746 return (GET_CODE (disp) == SYMBOL_REF
9747 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9749 disp = XVECEXP (disp, 0, 0);
9750 return (GET_CODE (disp) == SYMBOL_REF
9751 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9753 disp = XVECEXP (disp, 0, 0);
9754 return (GET_CODE (disp) == SYMBOL_REF
9755 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9761 /* Recognizes RTL expressions that are valid memory addresses for an
9762 instruction. The MODE argument is the machine mode for the MEM
9763 expression that wants to use this address.
9765 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9766 convert common non-canonical forms to canonical form so that they will
9770 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9771 rtx addr, bool strict)
9773 struct ix86_address parts;
9774 rtx base, index, disp;
9775 HOST_WIDE_INT scale;
9777 if (ix86_decompose_address (addr, &parts) <= 0)
9778 /* Decomposition failed. */
9782 index = parts.index;
9784 scale = parts.scale;
9786 /* Validate base register.
9788 Don't allow SUBREG's that span more than a word here. It can lead to spill
9789 failures when the base is one word out of a two word structure, which is
9790 represented internally as a DImode int. */
9798 else if (GET_CODE (base) == SUBREG
9799 && REG_P (SUBREG_REG (base))
9800 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9802 reg = SUBREG_REG (base);
9804 /* Base is not a register. */
9807 if (GET_MODE (base) != Pmode)
9808 /* Base is not in Pmode. */
9811 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9812 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9813 /* Base is not valid. */
9817 /* Validate index register.
9819 Don't allow SUBREG's that span more than a word here -- same as above. */
9827 else if (GET_CODE (index) == SUBREG
9828 && REG_P (SUBREG_REG (index))
9829 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9831 reg = SUBREG_REG (index);
9833 /* Index is not a register. */
9836 if (GET_MODE (index) != Pmode)
9837 /* Index is not in Pmode. */
9840 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9841 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9842 /* Index is not valid. */
9846 /* Validate scale factor. */
9850 /* Scale without index. */
9853 if (scale != 2 && scale != 4 && scale != 8)
9854 /* Scale is not a valid multiplier. */
9858 /* Validate displacement. */
9861 if (GET_CODE (disp) == CONST
9862 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9863 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9864 switch (XINT (XEXP (disp, 0), 1))
9866 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9867 used. While ABI specify also 32bit relocations, we don't produce
9868 them at all and use IP relative instead. */
9871 gcc_assert (flag_pic);
9873 goto is_legitimate_pic;
9875 /* 64bit address unspec. */
9878 case UNSPEC_GOTPCREL:
9879 gcc_assert (flag_pic);
9880 goto is_legitimate_pic;
9882 case UNSPEC_GOTTPOFF:
9883 case UNSPEC_GOTNTPOFF:
9884 case UNSPEC_INDNTPOFF:
9890 /* Invalid address unspec. */
9894 else if (SYMBOLIC_CONST (disp)
9898 && MACHOPIC_INDIRECT
9899 && !machopic_operand_p (disp)
9905 if (TARGET_64BIT && (index || base))
9907 /* foo@dtpoff(%rX) is ok. */
9908 if (GET_CODE (disp) != CONST
9909 || GET_CODE (XEXP (disp, 0)) != PLUS
9910 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9911 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9912 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9913 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9914 /* Non-constant pic memory reference. */
9917 else if (! legitimate_pic_address_disp_p (disp))
9918 /* Displacement is an invalid pic construct. */
9921 /* This code used to verify that a symbolic pic displacement
9922 includes the pic_offset_table_rtx register.
9924 While this is good idea, unfortunately these constructs may
9925 be created by "adds using lea" optimization for incorrect
9934 This code is nonsensical, but results in addressing
9935 GOT table with pic_offset_table_rtx base. We can't
9936 just refuse it easily, since it gets matched by
9937 "addsi3" pattern, that later gets split to lea in the
9938 case output register differs from input. While this
9939 can be handled by separate addsi pattern for this case
9940 that never results in lea, this seems to be easier and
9941 correct fix for crash to disable this test. */
9943 else if (GET_CODE (disp) != LABEL_REF
9944 && !CONST_INT_P (disp)
9945 && (GET_CODE (disp) != CONST
9946 || !legitimate_constant_p (disp))
9947 && (GET_CODE (disp) != SYMBOL_REF
9948 || !legitimate_constant_p (disp)))
9949 /* Displacement is not constant. */
9951 else if (TARGET_64BIT
9952 && !x86_64_immediate_operand (disp, VOIDmode))
9953 /* Displacement is out of range. */
9957 /* Everything looks valid. */
9961 /* Determine if a given RTX is a valid constant address. */
9964 constant_address_p (rtx x)
9966 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9969 /* Return a unique alias set for the GOT. */
9971 static alias_set_type
9972 ix86_GOT_alias_set (void)
9974 static alias_set_type set = -1;
9976 set = new_alias_set ();
9980 /* Return a legitimate reference for ORIG (an address) using the
9981 register REG. If REG is 0, a new pseudo is generated.
9983 There are two types of references that must be handled:
9985 1. Global data references must load the address from the GOT, via
9986 the PIC reg. An insn is emitted to do this load, and the reg is
9989 2. Static data references, constant pool addresses, and code labels
9990 compute the address as an offset from the GOT, whose base is in
9991 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9992 differentiate them from global data objects. The returned
9993 address is the PIC reg + an unspec constant.
9995 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9996 reg also appears in the address. */
9999 legitimize_pic_address (rtx orig, rtx reg)
10002 rtx new_rtx = orig;
10006 if (TARGET_MACHO && !TARGET_64BIT)
10009 reg = gen_reg_rtx (Pmode);
10010 /* Use the generic Mach-O PIC machinery. */
10011 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
10015 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
10017 else if (TARGET_64BIT
10018 && ix86_cmodel != CM_SMALL_PIC
10019 && gotoff_operand (addr, Pmode))
10022 /* This symbol may be referenced via a displacement from the PIC
10023 base address (@GOTOFF). */
10025 if (reload_in_progress)
10026 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10027 if (GET_CODE (addr) == CONST)
10028 addr = XEXP (addr, 0);
10029 if (GET_CODE (addr) == PLUS)
10031 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
10033 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
10036 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
10037 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10039 tmpreg = gen_reg_rtx (Pmode);
10042 emit_move_insn (tmpreg, new_rtx);
10046 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
10047 tmpreg, 1, OPTAB_DIRECT);
10050 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
10052 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
10054 /* This symbol may be referenced via a displacement from the PIC
10055 base address (@GOTOFF). */
10057 if (reload_in_progress)
10058 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10059 if (GET_CODE (addr) == CONST)
10060 addr = XEXP (addr, 0);
10061 if (GET_CODE (addr) == PLUS)
10063 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
10065 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
10068 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
10069 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10070 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10074 emit_move_insn (reg, new_rtx);
10078 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
10079 /* We can't use @GOTOFF for text labels on VxWorks;
10080 see gotoff_operand. */
10081 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
10083 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10085 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
10086 return legitimize_dllimport_symbol (addr, true);
10087 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
10088 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
10089 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
10091 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
10092 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
10096 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
10098 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
10099 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10100 new_rtx = gen_const_mem (Pmode, new_rtx);
10101 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10104 reg = gen_reg_rtx (Pmode);
10105 /* Use directly gen_movsi, otherwise the address is loaded
10106 into register for CSE. We don't want to CSE this addresses,
10107 instead we CSE addresses from the GOT table, so skip this. */
10108 emit_insn (gen_movsi (reg, new_rtx));
10113 /* This symbol must be referenced via a load from the
10114 Global Offset Table (@GOT). */
10116 if (reload_in_progress)
10117 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10118 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
10119 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10121 new_rtx = force_reg (Pmode, new_rtx);
10122 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10123 new_rtx = gen_const_mem (Pmode, new_rtx);
10124 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10127 reg = gen_reg_rtx (Pmode);
10128 emit_move_insn (reg, new_rtx);
10134 if (CONST_INT_P (addr)
10135 && !x86_64_immediate_operand (addr, VOIDmode))
10139 emit_move_insn (reg, addr);
10143 new_rtx = force_reg (Pmode, addr);
10145 else if (GET_CODE (addr) == CONST)
10147 addr = XEXP (addr, 0);
10149 /* We must match stuff we generate before. Assume the only
10150 unspecs that can get here are ours. Not that we could do
10151 anything with them anyway.... */
10152 if (GET_CODE (addr) == UNSPEC
10153 || (GET_CODE (addr) == PLUS
10154 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10156 gcc_assert (GET_CODE (addr) == PLUS);
10158 if (GET_CODE (addr) == PLUS)
10160 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10162 /* Check first to see if this is a constant offset from a @GOTOFF
10163 symbol reference. */
10164 if (gotoff_operand (op0, Pmode)
10165 && CONST_INT_P (op1))
10169 if (reload_in_progress)
10170 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10171 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10173 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10174 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10175 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10179 emit_move_insn (reg, new_rtx);
10185 if (INTVAL (op1) < -16*1024*1024
10186 || INTVAL (op1) >= 16*1024*1024)
10188 if (!x86_64_immediate_operand (op1, Pmode))
10189 op1 = force_reg (Pmode, op1);
10190 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10196 base = legitimize_pic_address (XEXP (addr, 0), reg);
10197 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10198 base == reg ? NULL_RTX : reg);
10200 if (CONST_INT_P (new_rtx))
10201 new_rtx = plus_constant (base, INTVAL (new_rtx));
10204 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10206 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10207 new_rtx = XEXP (new_rtx, 1);
10209 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10217 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10220 get_thread_pointer (int to_reg)
10224 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10228 reg = gen_reg_rtx (Pmode);
10229 insn = gen_rtx_SET (VOIDmode, reg, tp);
10230 insn = emit_insn (insn);
10235 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10236 false if we expect this to be used for a memory address and true if
10237 we expect to load the address into a register. */
10240 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10242 rtx dest, base, off, pic, tp;
10247 case TLS_MODEL_GLOBAL_DYNAMIC:
10248 dest = gen_reg_rtx (Pmode);
10249 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10251 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10253 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10256 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10257 insns = get_insns ();
10260 RTL_CONST_CALL_P (insns) = 1;
10261 emit_libcall_block (insns, dest, rax, x);
10263 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10264 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10266 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10268 if (TARGET_GNU2_TLS)
10270 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10272 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10276 case TLS_MODEL_LOCAL_DYNAMIC:
10277 base = gen_reg_rtx (Pmode);
10278 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10280 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10282 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10285 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10286 insns = get_insns ();
10289 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10290 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10291 RTL_CONST_CALL_P (insns) = 1;
10292 emit_libcall_block (insns, base, rax, note);
10294 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10295 emit_insn (gen_tls_local_dynamic_base_64 (base));
10297 emit_insn (gen_tls_local_dynamic_base_32 (base));
10299 if (TARGET_GNU2_TLS)
10301 rtx x = ix86_tls_module_base ();
10303 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10304 gen_rtx_MINUS (Pmode, x, tp));
10307 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10308 off = gen_rtx_CONST (Pmode, off);
10310 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10312 if (TARGET_GNU2_TLS)
10314 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10316 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10321 case TLS_MODEL_INITIAL_EXEC:
10325 type = UNSPEC_GOTNTPOFF;
10329 if (reload_in_progress)
10330 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10331 pic = pic_offset_table_rtx;
10332 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10334 else if (!TARGET_ANY_GNU_TLS)
10336 pic = gen_reg_rtx (Pmode);
10337 emit_insn (gen_set_got (pic));
10338 type = UNSPEC_GOTTPOFF;
10343 type = UNSPEC_INDNTPOFF;
10346 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10347 off = gen_rtx_CONST (Pmode, off);
10349 off = gen_rtx_PLUS (Pmode, pic, off);
10350 off = gen_const_mem (Pmode, off);
10351 set_mem_alias_set (off, ix86_GOT_alias_set ());
10353 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10355 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10356 off = force_reg (Pmode, off);
10357 return gen_rtx_PLUS (Pmode, base, off);
10361 base = get_thread_pointer (true);
10362 dest = gen_reg_rtx (Pmode);
10363 emit_insn (gen_subsi3 (dest, base, off));
10367 case TLS_MODEL_LOCAL_EXEC:
10368 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10369 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10370 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10371 off = gen_rtx_CONST (Pmode, off);
10373 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10375 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10376 return gen_rtx_PLUS (Pmode, base, off);
10380 base = get_thread_pointer (true);
10381 dest = gen_reg_rtx (Pmode);
10382 emit_insn (gen_subsi3 (dest, base, off));
10387 gcc_unreachable ();
10393 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10396 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10397 htab_t dllimport_map;
10400 get_dllimport_decl (tree decl)
10402 struct tree_map *h, in;
10405 const char *prefix;
10406 size_t namelen, prefixlen;
10411 if (!dllimport_map)
10412 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10414 in.hash = htab_hash_pointer (decl);
10415 in.base.from = decl;
10416 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10417 h = (struct tree_map *) *loc;
10421 *loc = h = GGC_NEW (struct tree_map);
10423 h->base.from = decl;
10424 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10425 VAR_DECL, NULL, ptr_type_node);
10426 DECL_ARTIFICIAL (to) = 1;
10427 DECL_IGNORED_P (to) = 1;
10428 DECL_EXTERNAL (to) = 1;
10429 TREE_READONLY (to) = 1;
10431 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10432 name = targetm.strip_name_encoding (name);
10433 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10434 ? "*__imp_" : "*__imp__";
10435 namelen = strlen (name);
10436 prefixlen = strlen (prefix);
10437 imp_name = (char *) alloca (namelen + prefixlen + 1);
10438 memcpy (imp_name, prefix, prefixlen);
10439 memcpy (imp_name + prefixlen, name, namelen + 1);
10441 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10442 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10443 SET_SYMBOL_REF_DECL (rtl, to);
10444 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10446 rtl = gen_const_mem (Pmode, rtl);
10447 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10449 SET_DECL_RTL (to, rtl);
10450 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10455 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10456 true if we require the result be a register. */
10459 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10464 gcc_assert (SYMBOL_REF_DECL (symbol));
10465 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10467 x = DECL_RTL (imp_decl);
10469 x = force_reg (Pmode, x);
10473 /* Try machine-dependent ways of modifying an illegitimate address
10474 to be legitimate. If we find one, return the new, valid address.
10475 This macro is used in only one place: `memory_address' in explow.c.
10477 OLDX is the address as it was before break_out_memory_refs was called.
10478 In some cases it is useful to look at this to decide what needs to be done.
10480 It is always safe for this macro to do nothing. It exists to recognize
10481 opportunities to optimize the output.
10483 For the 80386, we handle X+REG by loading X into a register R and
10484 using R+REG. R will go in a general reg and indexing will be used.
10485 However, if REG is a broken-out memory address or multiplication,
10486 nothing needs to be done because REG can certainly go in a general reg.
10488 When -fpic is used, special handling is needed for symbolic references.
10489 See comments by legitimize_pic_address in i386.c for details. */
10492 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10493 enum machine_mode mode)
10498 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10500 return legitimize_tls_address (x, (enum tls_model) log, false);
10501 if (GET_CODE (x) == CONST
10502 && GET_CODE (XEXP (x, 0)) == PLUS
10503 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10504 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10506 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10507 (enum tls_model) log, false);
10508 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10511 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10513 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10514 return legitimize_dllimport_symbol (x, true);
10515 if (GET_CODE (x) == CONST
10516 && GET_CODE (XEXP (x, 0)) == PLUS
10517 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10518 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10520 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10521 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10525 if (flag_pic && SYMBOLIC_CONST (x))
10526 return legitimize_pic_address (x, 0);
10528 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10529 if (GET_CODE (x) == ASHIFT
10530 && CONST_INT_P (XEXP (x, 1))
10531 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10534 log = INTVAL (XEXP (x, 1));
10535 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10536 GEN_INT (1 << log));
10539 if (GET_CODE (x) == PLUS)
10541 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10543 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10544 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10545 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10548 log = INTVAL (XEXP (XEXP (x, 0), 1));
10549 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10550 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10551 GEN_INT (1 << log));
10554 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10555 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10556 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10559 log = INTVAL (XEXP (XEXP (x, 1), 1));
10560 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10561 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10562 GEN_INT (1 << log));
10565 /* Put multiply first if it isn't already. */
10566 if (GET_CODE (XEXP (x, 1)) == MULT)
10568 rtx tmp = XEXP (x, 0);
10569 XEXP (x, 0) = XEXP (x, 1);
10574 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10575 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10576 created by virtual register instantiation, register elimination, and
10577 similar optimizations. */
10578 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10581 x = gen_rtx_PLUS (Pmode,
10582 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10583 XEXP (XEXP (x, 1), 0)),
10584 XEXP (XEXP (x, 1), 1));
10588 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10589 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10590 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10591 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10592 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10593 && CONSTANT_P (XEXP (x, 1)))
10596 rtx other = NULL_RTX;
10598 if (CONST_INT_P (XEXP (x, 1)))
10600 constant = XEXP (x, 1);
10601 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10603 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10605 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10606 other = XEXP (x, 1);
10614 x = gen_rtx_PLUS (Pmode,
10615 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10616 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10617 plus_constant (other, INTVAL (constant)));
10621 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10624 if (GET_CODE (XEXP (x, 0)) == MULT)
10627 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10630 if (GET_CODE (XEXP (x, 1)) == MULT)
10633 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10637 && REG_P (XEXP (x, 1))
10638 && REG_P (XEXP (x, 0)))
10641 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10644 x = legitimize_pic_address (x, 0);
10647 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10650 if (REG_P (XEXP (x, 0)))
10652 rtx temp = gen_reg_rtx (Pmode);
10653 rtx val = force_operand (XEXP (x, 1), temp);
10655 emit_move_insn (temp, val);
10657 XEXP (x, 1) = temp;
10661 else if (REG_P (XEXP (x, 1)))
10663 rtx temp = gen_reg_rtx (Pmode);
10664 rtx val = force_operand (XEXP (x, 0), temp);
10666 emit_move_insn (temp, val);
10668 XEXP (x, 0) = temp;
10676 /* Print an integer constant expression in assembler syntax. Addition
10677 and subtraction are the only arithmetic that may appear in these
10678 expressions. FILE is the stdio stream to write to, X is the rtx, and
10679 CODE is the operand print code from the output string. */
10682 output_pic_addr_const (FILE *file, rtx x, int code)
10686 switch (GET_CODE (x))
10689 gcc_assert (flag_pic);
10694 if (! TARGET_MACHO || TARGET_64BIT)
10695 output_addr_const (file, x);
10698 const char *name = XSTR (x, 0);
10700 /* Mark the decl as referenced so that cgraph will
10701 output the function. */
10702 if (SYMBOL_REF_DECL (x))
10703 mark_decl_referenced (SYMBOL_REF_DECL (x));
10706 if (MACHOPIC_INDIRECT
10707 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10708 name = machopic_indirection_name (x, /*stub_p=*/true);
10710 assemble_name (file, name);
10712 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10713 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10714 fputs ("@PLT", file);
10721 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10722 assemble_name (asm_out_file, buf);
10726 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10730 /* This used to output parentheses around the expression,
10731 but that does not work on the 386 (either ATT or BSD assembler). */
10732 output_pic_addr_const (file, XEXP (x, 0), code);
10736 if (GET_MODE (x) == VOIDmode)
10738 /* We can use %d if the number is <32 bits and positive. */
10739 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10740 fprintf (file, "0x%lx%08lx",
10741 (unsigned long) CONST_DOUBLE_HIGH (x),
10742 (unsigned long) CONST_DOUBLE_LOW (x));
10744 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10747 /* We can't handle floating point constants;
10748 PRINT_OPERAND must handle them. */
10749 output_operand_lossage ("floating constant misused");
10753 /* Some assemblers need integer constants to appear first. */
10754 if (CONST_INT_P (XEXP (x, 0)))
10756 output_pic_addr_const (file, XEXP (x, 0), code);
10758 output_pic_addr_const (file, XEXP (x, 1), code);
10762 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10763 output_pic_addr_const (file, XEXP (x, 1), code);
10765 output_pic_addr_const (file, XEXP (x, 0), code);
10771 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10772 output_pic_addr_const (file, XEXP (x, 0), code);
10774 output_pic_addr_const (file, XEXP (x, 1), code);
10776 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10780 gcc_assert (XVECLEN (x, 0) == 1);
10781 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10782 switch (XINT (x, 1))
10785 fputs ("@GOT", file);
10787 case UNSPEC_GOTOFF:
10788 fputs ("@GOTOFF", file);
10790 case UNSPEC_PLTOFF:
10791 fputs ("@PLTOFF", file);
10793 case UNSPEC_GOTPCREL:
10794 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10795 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10797 case UNSPEC_GOTTPOFF:
10798 /* FIXME: This might be @TPOFF in Sun ld too. */
10799 fputs ("@GOTTPOFF", file);
10802 fputs ("@TPOFF", file);
10804 case UNSPEC_NTPOFF:
10806 fputs ("@TPOFF", file);
10808 fputs ("@NTPOFF", file);
10810 case UNSPEC_DTPOFF:
10811 fputs ("@DTPOFF", file);
10813 case UNSPEC_GOTNTPOFF:
10815 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10816 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10818 fputs ("@GOTNTPOFF", file);
10820 case UNSPEC_INDNTPOFF:
10821 fputs ("@INDNTPOFF", file);
10824 case UNSPEC_MACHOPIC_OFFSET:
10826 machopic_output_function_base_name (file);
10830 output_operand_lossage ("invalid UNSPEC as operand");
10836 output_operand_lossage ("invalid expression as operand");
10840 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10841 We need to emit DTP-relative relocations. */
10843 static void ATTRIBUTE_UNUSED
10844 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10846 fputs (ASM_LONG, file);
10847 output_addr_const (file, x);
10848 fputs ("@DTPOFF", file);
10854 fputs (", 0", file);
10857 gcc_unreachable ();
10861 /* Return true if X is a representation of the PIC register. This copes
10862 with calls from ix86_find_base_term, where the register might have
10863 been replaced by a cselib value. */
10866 ix86_pic_register_p (rtx x)
10868 if (GET_CODE (x) == VALUE && CSELIB_VAL_PTR (x))
10869 return (pic_offset_table_rtx
10870 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10872 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10875 /* In the name of slightly smaller debug output, and to cater to
10876 general assembler lossage, recognize PIC+GOTOFF and turn it back
10877 into a direct symbol reference.
10879 On Darwin, this is necessary to avoid a crash, because Darwin
10880 has a different PIC label for each routine but the DWARF debugging
10881 information is not associated with any particular routine, so it's
10882 necessary to remove references to the PIC label from RTL stored by
10883 the DWARF output code. */
10886 ix86_delegitimize_address (rtx x)
10888 rtx orig_x = delegitimize_mem_from_attrs (x);
10889 /* reg_addend is NULL or a multiple of some register. */
10890 rtx reg_addend = NULL_RTX;
10891 /* const_addend is NULL or a const_int. */
10892 rtx const_addend = NULL_RTX;
10893 /* This is the result, or NULL. */
10894 rtx result = NULL_RTX;
10903 if (GET_CODE (x) != CONST
10904 || GET_CODE (XEXP (x, 0)) != UNSPEC
10905 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10906 || !MEM_P (orig_x))
10908 return XVECEXP (XEXP (x, 0), 0, 0);
10911 if (GET_CODE (x) != PLUS
10912 || GET_CODE (XEXP (x, 1)) != CONST)
10915 if (ix86_pic_register_p (XEXP (x, 0)))
10916 /* %ebx + GOT/GOTOFF */
10918 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10920 /* %ebx + %reg * scale + GOT/GOTOFF */
10921 reg_addend = XEXP (x, 0);
10922 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10923 reg_addend = XEXP (reg_addend, 1);
10924 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10925 reg_addend = XEXP (reg_addend, 0);
10928 if (!REG_P (reg_addend)
10929 && GET_CODE (reg_addend) != MULT
10930 && GET_CODE (reg_addend) != ASHIFT)
10936 x = XEXP (XEXP (x, 1), 0);
10937 if (GET_CODE (x) == PLUS
10938 && CONST_INT_P (XEXP (x, 1)))
10940 const_addend = XEXP (x, 1);
10944 if (GET_CODE (x) == UNSPEC
10945 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10946 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10947 result = XVECEXP (x, 0, 0);
10949 if (TARGET_MACHO && darwin_local_data_pic (x)
10950 && !MEM_P (orig_x))
10951 result = XVECEXP (x, 0, 0);
10957 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10959 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10963 /* If X is a machine specific address (i.e. a symbol or label being
10964 referenced as a displacement from the GOT implemented using an
10965 UNSPEC), then return the base term. Otherwise return X. */
10968 ix86_find_base_term (rtx x)
10974 if (GET_CODE (x) != CONST)
10976 term = XEXP (x, 0);
10977 if (GET_CODE (term) == PLUS
10978 && (CONST_INT_P (XEXP (term, 1))
10979 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10980 term = XEXP (term, 0);
10981 if (GET_CODE (term) != UNSPEC
10982 || XINT (term, 1) != UNSPEC_GOTPCREL)
10985 return XVECEXP (term, 0, 0);
10988 return ix86_delegitimize_address (x);
10992 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10993 int fp, FILE *file)
10995 const char *suffix;
10997 if (mode == CCFPmode || mode == CCFPUmode)
10999 code = ix86_fp_compare_code_to_integer (code);
11003 code = reverse_condition (code);
11054 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
11058 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
11059 Those same assemblers have the same but opposite lossage on cmov. */
11060 if (mode == CCmode)
11061 suffix = fp ? "nbe" : "a";
11062 else if (mode == CCCmode)
11065 gcc_unreachable ();
11081 gcc_unreachable ();
11085 gcc_assert (mode == CCmode || mode == CCCmode);
11102 gcc_unreachable ();
11106 /* ??? As above. */
11107 gcc_assert (mode == CCmode || mode == CCCmode);
11108 suffix = fp ? "nb" : "ae";
11111 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
11115 /* ??? As above. */
11116 if (mode == CCmode)
11118 else if (mode == CCCmode)
11119 suffix = fp ? "nb" : "ae";
11121 gcc_unreachable ();
11124 suffix = fp ? "u" : "p";
11127 suffix = fp ? "nu" : "np";
11130 gcc_unreachable ();
11132 fputs (suffix, file);
11135 /* Print the name of register X to FILE based on its machine mode and number.
11136 If CODE is 'w', pretend the mode is HImode.
11137 If CODE is 'b', pretend the mode is QImode.
11138 If CODE is 'k', pretend the mode is SImode.
11139 If CODE is 'q', pretend the mode is DImode.
11140 If CODE is 'x', pretend the mode is V4SFmode.
11141 If CODE is 't', pretend the mode is V8SFmode.
11142 If CODE is 'h', pretend the reg is the 'high' byte register.
11143 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11144 If CODE is 'd', duplicate the operand for AVX instruction.
11148 print_reg (rtx x, int code, FILE *file)
11151 bool duplicated = code == 'd' && TARGET_AVX;
11153 gcc_assert (x == pc_rtx
11154 || (REGNO (x) != ARG_POINTER_REGNUM
11155 && REGNO (x) != FRAME_POINTER_REGNUM
11156 && REGNO (x) != FLAGS_REG
11157 && REGNO (x) != FPSR_REG
11158 && REGNO (x) != FPCR_REG));
11160 if (ASSEMBLER_DIALECT == ASM_ATT)
11165 gcc_assert (TARGET_64BIT);
11166 fputs ("rip", file);
11170 if (code == 'w' || MMX_REG_P (x))
11172 else if (code == 'b')
11174 else if (code == 'k')
11176 else if (code == 'q')
11178 else if (code == 'y')
11180 else if (code == 'h')
11182 else if (code == 'x')
11184 else if (code == 't')
11187 code = GET_MODE_SIZE (GET_MODE (x));
11189 /* Irritatingly, AMD extended registers use different naming convention
11190 from the normal registers. */
11191 if (REX_INT_REG_P (x))
11193 gcc_assert (TARGET_64BIT);
11197 error ("extended registers have no high halves");
11200 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11203 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11206 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11209 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11212 error ("unsupported operand size for extended register");
11222 if (STACK_TOP_P (x))
11231 if (! ANY_FP_REG_P (x))
11232 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11237 reg = hi_reg_name[REGNO (x)];
11240 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11242 reg = qi_reg_name[REGNO (x)];
11245 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11247 reg = qi_high_reg_name[REGNO (x)];
11252 gcc_assert (!duplicated);
11254 fputs (hi_reg_name[REGNO (x)] + 1, file);
11259 gcc_unreachable ();
11265 if (ASSEMBLER_DIALECT == ASM_ATT)
11266 fprintf (file, ", %%%s", reg);
11268 fprintf (file, ", %s", reg);
11272 /* Locate some local-dynamic symbol still in use by this function
11273 so that we can print its name in some tls_local_dynamic_base
11277 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11281 if (GET_CODE (x) == SYMBOL_REF
11282 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11284 cfun->machine->some_ld_name = XSTR (x, 0);
11291 static const char *
11292 get_some_local_dynamic_name (void)
11296 if (cfun->machine->some_ld_name)
11297 return cfun->machine->some_ld_name;
11299 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11301 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11302 return cfun->machine->some_ld_name;
11307 /* Meaning of CODE:
11308 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11309 C -- print opcode suffix for set/cmov insn.
11310 c -- like C, but print reversed condition
11311 E,e -- likewise, but for compare-and-branch fused insn.
11312 F,f -- likewise, but for floating-point.
11313 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11315 R -- print the prefix for register names.
11316 z -- print the opcode suffix for the size of the current operand.
11317 Z -- likewise, with special suffixes for x87 instructions.
11318 * -- print a star (in certain assembler syntax)
11319 A -- print an absolute memory reference.
11320 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11321 s -- print a shift double count, followed by the assemblers argument
11323 b -- print the QImode name of the register for the indicated operand.
11324 %b0 would print %al if operands[0] is reg 0.
11325 w -- likewise, print the HImode name of the register.
11326 k -- likewise, print the SImode name of the register.
11327 q -- likewise, print the DImode name of the register.
11328 x -- likewise, print the V4SFmode name of the register.
11329 t -- likewise, print the V8SFmode name of the register.
11330 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11331 y -- print "st(0)" instead of "st" as a register.
11332 d -- print duplicated register operand for AVX instruction.
11333 D -- print condition for SSE cmp instruction.
11334 P -- if PIC, print an @PLT suffix.
11335 X -- don't print any sort of PIC '@' suffix for a symbol.
11336 & -- print some in-use local-dynamic symbol name.
11337 H -- print a memory address offset by 8; used for sse high-parts
11338 Y -- print condition for XOP pcom* instruction.
11339 + -- print a branch hint as 'cs' or 'ds' prefix
11340 ; -- print a semicolon (after prefixes due to bug in older gas).
11344 print_operand (FILE *file, rtx x, int code)
11351 if (ASSEMBLER_DIALECT == ASM_ATT)
11357 const char *name = get_some_local_dynamic_name ();
11359 output_operand_lossage ("'%%&' used without any "
11360 "local dynamic TLS references");
11362 assemble_name (file, name);
11367 switch (ASSEMBLER_DIALECT)
11374 /* Intel syntax. For absolute addresses, registers should not
11375 be surrounded by braces. */
11379 PRINT_OPERAND (file, x, 0);
11386 gcc_unreachable ();
11389 PRINT_OPERAND (file, x, 0);
11394 if (ASSEMBLER_DIALECT == ASM_ATT)
11399 if (ASSEMBLER_DIALECT == ASM_ATT)
11404 if (ASSEMBLER_DIALECT == ASM_ATT)
11409 if (ASSEMBLER_DIALECT == ASM_ATT)
11414 if (ASSEMBLER_DIALECT == ASM_ATT)
11419 if (ASSEMBLER_DIALECT == ASM_ATT)
11424 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11426 /* Opcodes don't get size suffixes if using Intel opcodes. */
11427 if (ASSEMBLER_DIALECT == ASM_INTEL)
11430 switch (GET_MODE_SIZE (GET_MODE (x)))
11449 output_operand_lossage
11450 ("invalid operand size for operand code '%c'", code);
11455 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11457 (0, "non-integer operand used with operand code '%c'", code);
11461 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11462 if (ASSEMBLER_DIALECT == ASM_INTEL)
11465 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11467 switch (GET_MODE_SIZE (GET_MODE (x)))
11470 #ifdef HAVE_AS_IX86_FILDS
11480 #ifdef HAVE_AS_IX86_FILDQ
11483 fputs ("ll", file);
11491 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11493 /* 387 opcodes don't get size suffixes
11494 if the operands are registers. */
11495 if (STACK_REG_P (x))
11498 switch (GET_MODE_SIZE (GET_MODE (x)))
11519 output_operand_lossage
11520 ("invalid operand type used with operand code '%c'", code);
11524 output_operand_lossage
11525 ("invalid operand size for operand code '%c'", code);
11542 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11544 PRINT_OPERAND (file, x, 0);
11545 fputs (", ", file);
11550 /* Little bit of braindamage here. The SSE compare instructions
11551 does use completely different names for the comparisons that the
11552 fp conditional moves. */
11555 switch (GET_CODE (x))
11558 fputs ("eq", file);
11561 fputs ("eq_us", file);
11564 fputs ("lt", file);
11567 fputs ("nge", file);
11570 fputs ("le", file);
11573 fputs ("ngt", file);
11576 fputs ("unord", file);
11579 fputs ("neq", file);
11582 fputs ("neq_oq", file);
11585 fputs ("ge", file);
11588 fputs ("nlt", file);
11591 fputs ("gt", file);
11594 fputs ("nle", file);
11597 fputs ("ord", file);
11600 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11606 switch (GET_CODE (x))
11610 fputs ("eq", file);
11614 fputs ("lt", file);
11618 fputs ("le", file);
11621 fputs ("unord", file);
11625 fputs ("neq", file);
11629 fputs ("nlt", file);
11633 fputs ("nle", file);
11636 fputs ("ord", file);
11639 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11645 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11646 if (ASSEMBLER_DIALECT == ASM_ATT)
11648 switch (GET_MODE (x))
11650 case HImode: putc ('w', file); break;
11652 case SFmode: putc ('l', file); break;
11654 case DFmode: putc ('q', file); break;
11655 default: gcc_unreachable ();
11662 if (!COMPARISON_P (x))
11664 output_operand_lossage ("operand is neither a constant nor a "
11665 "condition code, invalid operand code "
11669 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11672 if (!COMPARISON_P (x))
11674 output_operand_lossage ("operand is neither a constant nor a "
11675 "condition code, invalid operand code "
11679 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11680 if (ASSEMBLER_DIALECT == ASM_ATT)
11683 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11686 /* Like above, but reverse condition */
11688 /* Check to see if argument to %c is really a constant
11689 and not a condition code which needs to be reversed. */
11690 if (!COMPARISON_P (x))
11692 output_operand_lossage ("operand is neither a constant nor a "
11693 "condition code, invalid operand "
11697 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11700 if (!COMPARISON_P (x))
11702 output_operand_lossage ("operand is neither a constant nor a "
11703 "condition code, invalid operand "
11707 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11708 if (ASSEMBLER_DIALECT == ASM_ATT)
11711 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11715 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11719 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11723 /* It doesn't actually matter what mode we use here, as we're
11724 only going to use this for printing. */
11725 x = adjust_address_nv (x, DImode, 8);
11733 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11736 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11739 int pred_val = INTVAL (XEXP (x, 0));
11741 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11742 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11744 int taken = pred_val > REG_BR_PROB_BASE / 2;
11745 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11747 /* Emit hints only in the case default branch prediction
11748 heuristics would fail. */
11749 if (taken != cputaken)
11751 /* We use 3e (DS) prefix for taken branches and
11752 2e (CS) prefix for not taken branches. */
11754 fputs ("ds ; ", file);
11756 fputs ("cs ; ", file);
11764 switch (GET_CODE (x))
11767 fputs ("neq", file);
11770 fputs ("eq", file);
11774 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11778 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11782 fputs ("le", file);
11786 fputs ("lt", file);
11789 fputs ("unord", file);
11792 fputs ("ord", file);
11795 fputs ("ueq", file);
11798 fputs ("nlt", file);
11801 fputs ("nle", file);
11804 fputs ("ule", file);
11807 fputs ("ult", file);
11810 fputs ("une", file);
11813 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11820 fputs (" ; ", file);
11827 output_operand_lossage ("invalid operand code '%c'", code);
11832 print_reg (x, code, file);
11834 else if (MEM_P (x))
11836 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11837 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11838 && GET_MODE (x) != BLKmode)
11841 switch (GET_MODE_SIZE (GET_MODE (x)))
11843 case 1: size = "BYTE"; break;
11844 case 2: size = "WORD"; break;
11845 case 4: size = "DWORD"; break;
11846 case 8: size = "QWORD"; break;
11847 case 12: size = "XWORD"; break;
11849 if (GET_MODE (x) == XFmode)
11855 gcc_unreachable ();
11858 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11861 else if (code == 'w')
11863 else if (code == 'k')
11866 fputs (size, file);
11867 fputs (" PTR ", file);
11871 /* Avoid (%rip) for call operands. */
11872 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11873 && !CONST_INT_P (x))
11874 output_addr_const (file, x);
11875 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11876 output_operand_lossage ("invalid constraints for operand");
11878 output_address (x);
11881 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11886 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11887 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11889 if (ASSEMBLER_DIALECT == ASM_ATT)
11891 fprintf (file, "0x%08lx", (long unsigned int) l);
11894 /* These float cases don't actually occur as immediate operands. */
11895 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11899 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11900 fputs (dstr, file);
11903 else if (GET_CODE (x) == CONST_DOUBLE
11904 && GET_MODE (x) == XFmode)
11908 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11909 fputs (dstr, file);
11914 /* We have patterns that allow zero sets of memory, for instance.
11915 In 64-bit mode, we should probably support all 8-byte vectors,
11916 since we can in fact encode that into an immediate. */
11917 if (GET_CODE (x) == CONST_VECTOR)
11919 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11925 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11927 if (ASSEMBLER_DIALECT == ASM_ATT)
11930 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11931 || GET_CODE (x) == LABEL_REF)
11933 if (ASSEMBLER_DIALECT == ASM_ATT)
11936 fputs ("OFFSET FLAT:", file);
11939 if (CONST_INT_P (x))
11940 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11942 output_pic_addr_const (file, x, code);
11944 output_addr_const (file, x);
11948 /* Print a memory operand whose address is ADDR. */
11951 print_operand_address (FILE *file, rtx addr)
11953 struct ix86_address parts;
11954 rtx base, index, disp;
11956 int ok = ix86_decompose_address (addr, &parts);
11961 index = parts.index;
11963 scale = parts.scale;
11971 if (ASSEMBLER_DIALECT == ASM_ATT)
11973 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11976 gcc_unreachable ();
11979 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11980 if (TARGET_64BIT && !base && !index)
11984 if (GET_CODE (disp) == CONST
11985 && GET_CODE (XEXP (disp, 0)) == PLUS
11986 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11987 symbol = XEXP (XEXP (disp, 0), 0);
11989 if (GET_CODE (symbol) == LABEL_REF
11990 || (GET_CODE (symbol) == SYMBOL_REF
11991 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11994 if (!base && !index)
11996 /* Displacement only requires special attention. */
11998 if (CONST_INT_P (disp))
12000 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
12001 fputs ("ds:", file);
12002 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
12005 output_pic_addr_const (file, disp, 0);
12007 output_addr_const (file, disp);
12011 if (ASSEMBLER_DIALECT == ASM_ATT)
12016 output_pic_addr_const (file, disp, 0);
12017 else if (GET_CODE (disp) == LABEL_REF)
12018 output_asm_label (disp);
12020 output_addr_const (file, disp);
12025 print_reg (base, 0, file);
12029 print_reg (index, 0, file);
12031 fprintf (file, ",%d", scale);
12037 rtx offset = NULL_RTX;
12041 /* Pull out the offset of a symbol; print any symbol itself. */
12042 if (GET_CODE (disp) == CONST
12043 && GET_CODE (XEXP (disp, 0)) == PLUS
12044 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
12046 offset = XEXP (XEXP (disp, 0), 1);
12047 disp = gen_rtx_CONST (VOIDmode,
12048 XEXP (XEXP (disp, 0), 0));
12052 output_pic_addr_const (file, disp, 0);
12053 else if (GET_CODE (disp) == LABEL_REF)
12054 output_asm_label (disp);
12055 else if (CONST_INT_P (disp))
12058 output_addr_const (file, disp);
12064 print_reg (base, 0, file);
12067 if (INTVAL (offset) >= 0)
12069 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
12073 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
12080 print_reg (index, 0, file);
12082 fprintf (file, "*%d", scale);
12090 output_addr_const_extra (FILE *file, rtx x)
12094 if (GET_CODE (x) != UNSPEC)
12097 op = XVECEXP (x, 0, 0);
12098 switch (XINT (x, 1))
12100 case UNSPEC_GOTTPOFF:
12101 output_addr_const (file, op);
12102 /* FIXME: This might be @TPOFF in Sun ld. */
12103 fputs ("@GOTTPOFF", file);
12106 output_addr_const (file, op);
12107 fputs ("@TPOFF", file);
12109 case UNSPEC_NTPOFF:
12110 output_addr_const (file, op);
12112 fputs ("@TPOFF", file);
12114 fputs ("@NTPOFF", file);
12116 case UNSPEC_DTPOFF:
12117 output_addr_const (file, op);
12118 fputs ("@DTPOFF", file);
12120 case UNSPEC_GOTNTPOFF:
12121 output_addr_const (file, op);
12123 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
12124 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
12126 fputs ("@GOTNTPOFF", file);
12128 case UNSPEC_INDNTPOFF:
12129 output_addr_const (file, op);
12130 fputs ("@INDNTPOFF", file);
12133 case UNSPEC_MACHOPIC_OFFSET:
12134 output_addr_const (file, op);
12136 machopic_output_function_base_name (file);
12147 /* Split one or more DImode RTL references into pairs of SImode
12148 references. The RTL can be REG, offsettable MEM, integer constant, or
12149 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12150 split and "num" is its length. lo_half and hi_half are output arrays
12151 that parallel "operands". */
12154 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12158 rtx op = operands[num];
12160 /* simplify_subreg refuse to split volatile memory addresses,
12161 but we still have to handle it. */
12164 lo_half[num] = adjust_address (op, SImode, 0);
12165 hi_half[num] = adjust_address (op, SImode, 4);
12169 lo_half[num] = simplify_gen_subreg (SImode, op,
12170 GET_MODE (op) == VOIDmode
12171 ? DImode : GET_MODE (op), 0);
12172 hi_half[num] = simplify_gen_subreg (SImode, op,
12173 GET_MODE (op) == VOIDmode
12174 ? DImode : GET_MODE (op), 4);
12178 /* Split one or more TImode RTL references into pairs of DImode
12179 references. The RTL can be REG, offsettable MEM, integer constant, or
12180 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12181 split and "num" is its length. lo_half and hi_half are output arrays
12182 that parallel "operands". */
12185 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12189 rtx op = operands[num];
12191 /* simplify_subreg refuse to split volatile memory addresses, but we
12192 still have to handle it. */
12195 lo_half[num] = adjust_address (op, DImode, 0);
12196 hi_half[num] = adjust_address (op, DImode, 8);
12200 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12201 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12206 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12207 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12208 is the expression of the binary operation. The output may either be
12209 emitted here, or returned to the caller, like all output_* functions.
12211 There is no guarantee that the operands are the same mode, as they
12212 might be within FLOAT or FLOAT_EXTEND expressions. */
12214 #ifndef SYSV386_COMPAT
12215 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12216 wants to fix the assemblers because that causes incompatibility
12217 with gcc. No-one wants to fix gcc because that causes
12218 incompatibility with assemblers... You can use the option of
12219 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12220 #define SYSV386_COMPAT 1
12224 output_387_binary_op (rtx insn, rtx *operands)
12226 static char buf[40];
12229 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12231 #ifdef ENABLE_CHECKING
12232 /* Even if we do not want to check the inputs, this documents input
12233 constraints. Which helps in understanding the following code. */
12234 if (STACK_REG_P (operands[0])
12235 && ((REG_P (operands[1])
12236 && REGNO (operands[0]) == REGNO (operands[1])
12237 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12238 || (REG_P (operands[2])
12239 && REGNO (operands[0]) == REGNO (operands[2])
12240 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12241 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12244 gcc_assert (is_sse);
12247 switch (GET_CODE (operands[3]))
12250 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12251 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12259 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12260 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12268 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12269 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12277 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12278 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12286 gcc_unreachable ();
12293 strcpy (buf, ssep);
12294 if (GET_MODE (operands[0]) == SFmode)
12295 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12297 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12301 strcpy (buf, ssep + 1);
12302 if (GET_MODE (operands[0]) == SFmode)
12303 strcat (buf, "ss\t{%2, %0|%0, %2}");
12305 strcat (buf, "sd\t{%2, %0|%0, %2}");
12311 switch (GET_CODE (operands[3]))
12315 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12317 rtx temp = operands[2];
12318 operands[2] = operands[1];
12319 operands[1] = temp;
12322 /* know operands[0] == operands[1]. */
12324 if (MEM_P (operands[2]))
12330 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12332 if (STACK_TOP_P (operands[0]))
12333 /* How is it that we are storing to a dead operand[2]?
12334 Well, presumably operands[1] is dead too. We can't
12335 store the result to st(0) as st(0) gets popped on this
12336 instruction. Instead store to operands[2] (which I
12337 think has to be st(1)). st(1) will be popped later.
12338 gcc <= 2.8.1 didn't have this check and generated
12339 assembly code that the Unixware assembler rejected. */
12340 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12342 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12346 if (STACK_TOP_P (operands[0]))
12347 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12349 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12354 if (MEM_P (operands[1]))
12360 if (MEM_P (operands[2]))
12366 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12369 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12370 derived assemblers, confusingly reverse the direction of
12371 the operation for fsub{r} and fdiv{r} when the
12372 destination register is not st(0). The Intel assembler
12373 doesn't have this brain damage. Read !SYSV386_COMPAT to
12374 figure out what the hardware really does. */
12375 if (STACK_TOP_P (operands[0]))
12376 p = "{p\t%0, %2|rp\t%2, %0}";
12378 p = "{rp\t%2, %0|p\t%0, %2}";
12380 if (STACK_TOP_P (operands[0]))
12381 /* As above for fmul/fadd, we can't store to st(0). */
12382 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12384 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12389 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12392 if (STACK_TOP_P (operands[0]))
12393 p = "{rp\t%0, %1|p\t%1, %0}";
12395 p = "{p\t%1, %0|rp\t%0, %1}";
12397 if (STACK_TOP_P (operands[0]))
12398 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12400 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12405 if (STACK_TOP_P (operands[0]))
12407 if (STACK_TOP_P (operands[1]))
12408 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12410 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12413 else if (STACK_TOP_P (operands[1]))
12416 p = "{\t%1, %0|r\t%0, %1}";
12418 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12424 p = "{r\t%2, %0|\t%0, %2}";
12426 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12432 gcc_unreachable ();
12439 /* Return needed mode for entity in optimize_mode_switching pass. */
12442 ix86_mode_needed (int entity, rtx insn)
12444 enum attr_i387_cw mode;
12446 /* The mode UNINITIALIZED is used to store control word after a
12447 function call or ASM pattern. The mode ANY specify that function
12448 has no requirements on the control word and make no changes in the
12449 bits we are interested in. */
12452 || (NONJUMP_INSN_P (insn)
12453 && (asm_noperands (PATTERN (insn)) >= 0
12454 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12455 return I387_CW_UNINITIALIZED;
12457 if (recog_memoized (insn) < 0)
12458 return I387_CW_ANY;
12460 mode = get_attr_i387_cw (insn);
12465 if (mode == I387_CW_TRUNC)
12470 if (mode == I387_CW_FLOOR)
12475 if (mode == I387_CW_CEIL)
12480 if (mode == I387_CW_MASK_PM)
12485 gcc_unreachable ();
12488 return I387_CW_ANY;
12491 /* Output code to initialize control word copies used by trunc?f?i and
12492 rounding patterns. CURRENT_MODE is set to current control word,
12493 while NEW_MODE is set to new control word. */
12496 emit_i387_cw_initialization (int mode)
12498 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12501 enum ix86_stack_slot slot;
12503 rtx reg = gen_reg_rtx (HImode);
12505 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12506 emit_move_insn (reg, copy_rtx (stored_mode));
12508 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12509 || optimize_function_for_size_p (cfun))
12513 case I387_CW_TRUNC:
12514 /* round toward zero (truncate) */
12515 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12516 slot = SLOT_CW_TRUNC;
12519 case I387_CW_FLOOR:
12520 /* round down toward -oo */
12521 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12522 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12523 slot = SLOT_CW_FLOOR;
12527 /* round up toward +oo */
12528 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12529 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12530 slot = SLOT_CW_CEIL;
12533 case I387_CW_MASK_PM:
12534 /* mask precision exception for nearbyint() */
12535 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12536 slot = SLOT_CW_MASK_PM;
12540 gcc_unreachable ();
12547 case I387_CW_TRUNC:
12548 /* round toward zero (truncate) */
12549 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12550 slot = SLOT_CW_TRUNC;
12553 case I387_CW_FLOOR:
12554 /* round down toward -oo */
12555 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12556 slot = SLOT_CW_FLOOR;
12560 /* round up toward +oo */
12561 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12562 slot = SLOT_CW_CEIL;
12565 case I387_CW_MASK_PM:
12566 /* mask precision exception for nearbyint() */
12567 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12568 slot = SLOT_CW_MASK_PM;
12572 gcc_unreachable ();
12576 gcc_assert (slot < MAX_386_STACK_LOCALS);
12578 new_mode = assign_386_stack_local (HImode, slot);
12579 emit_move_insn (new_mode, reg);
12582 /* Output code for INSN to convert a float to a signed int. OPERANDS
12583 are the insn operands. The output may be [HSD]Imode and the input
12584 operand may be [SDX]Fmode. */
12587 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12589 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12590 int dimode_p = GET_MODE (operands[0]) == DImode;
12591 int round_mode = get_attr_i387_cw (insn);
12593 /* Jump through a hoop or two for DImode, since the hardware has no
12594 non-popping instruction. We used to do this a different way, but
12595 that was somewhat fragile and broke with post-reload splitters. */
12596 if ((dimode_p || fisttp) && !stack_top_dies)
12597 output_asm_insn ("fld\t%y1", operands);
12599 gcc_assert (STACK_TOP_P (operands[1]));
12600 gcc_assert (MEM_P (operands[0]));
12601 gcc_assert (GET_MODE (operands[1]) != TFmode);
12604 output_asm_insn ("fisttp%Z0\t%0", operands);
12607 if (round_mode != I387_CW_ANY)
12608 output_asm_insn ("fldcw\t%3", operands);
12609 if (stack_top_dies || dimode_p)
12610 output_asm_insn ("fistp%Z0\t%0", operands);
12612 output_asm_insn ("fist%Z0\t%0", operands);
12613 if (round_mode != I387_CW_ANY)
12614 output_asm_insn ("fldcw\t%2", operands);
12620 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12621 have the values zero or one, indicates the ffreep insn's operand
12622 from the OPERANDS array. */
12624 static const char *
12625 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12627 if (TARGET_USE_FFREEP)
12628 #ifdef HAVE_AS_IX86_FFREEP
12629 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12632 static char retval[32];
12633 int regno = REGNO (operands[opno]);
12635 gcc_assert (FP_REGNO_P (regno));
12637 regno -= FIRST_STACK_REG;
12639 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12644 return opno ? "fstp\t%y1" : "fstp\t%y0";
12648 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12649 should be used. UNORDERED_P is true when fucom should be used. */
12652 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12654 int stack_top_dies;
12655 rtx cmp_op0, cmp_op1;
12656 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12660 cmp_op0 = operands[0];
12661 cmp_op1 = operands[1];
12665 cmp_op0 = operands[1];
12666 cmp_op1 = operands[2];
12671 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12672 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12673 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12674 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12676 if (GET_MODE (operands[0]) == SFmode)
12678 return &ucomiss[TARGET_AVX ? 0 : 1];
12680 return &comiss[TARGET_AVX ? 0 : 1];
12683 return &ucomisd[TARGET_AVX ? 0 : 1];
12685 return &comisd[TARGET_AVX ? 0 : 1];
12688 gcc_assert (STACK_TOP_P (cmp_op0));
12690 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12692 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12694 if (stack_top_dies)
12696 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12697 return output_387_ffreep (operands, 1);
12700 return "ftst\n\tfnstsw\t%0";
12703 if (STACK_REG_P (cmp_op1)
12705 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12706 && REGNO (cmp_op1) != FIRST_STACK_REG)
12708 /* If both the top of the 387 stack dies, and the other operand
12709 is also a stack register that dies, then this must be a
12710 `fcompp' float compare */
12714 /* There is no double popping fcomi variant. Fortunately,
12715 eflags is immune from the fstp's cc clobbering. */
12717 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12719 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12720 return output_387_ffreep (operands, 0);
12725 return "fucompp\n\tfnstsw\t%0";
12727 return "fcompp\n\tfnstsw\t%0";
12732 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12734 static const char * const alt[16] =
12736 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12737 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12738 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12739 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12741 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12742 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12746 "fcomi\t{%y1, %0|%0, %y1}",
12747 "fcomip\t{%y1, %0|%0, %y1}",
12748 "fucomi\t{%y1, %0|%0, %y1}",
12749 "fucomip\t{%y1, %0|%0, %y1}",
12760 mask = eflags_p << 3;
12761 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12762 mask |= unordered_p << 1;
12763 mask |= stack_top_dies;
12765 gcc_assert (mask < 16);
12774 ix86_output_addr_vec_elt (FILE *file, int value)
12776 const char *directive = ASM_LONG;
12780 directive = ASM_QUAD;
12782 gcc_assert (!TARGET_64BIT);
12785 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12789 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12791 const char *directive = ASM_LONG;
12794 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12795 directive = ASM_QUAD;
12797 gcc_assert (!TARGET_64BIT);
12799 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12800 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12801 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12802 directive, value, rel);
12803 else if (HAVE_AS_GOTOFF_IN_DATA)
12804 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12806 else if (TARGET_MACHO)
12808 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12809 machopic_output_function_base_name (file);
12814 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12815 GOT_SYMBOL_NAME, value);
12818 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12822 ix86_expand_clear (rtx dest)
12826 /* We play register width games, which are only valid after reload. */
12827 gcc_assert (reload_completed);
12829 /* Avoid HImode and its attendant prefix byte. */
12830 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12831 dest = gen_rtx_REG (SImode, REGNO (dest));
12832 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12834 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12835 if (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ())
12837 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12838 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12844 /* X is an unchanging MEM. If it is a constant pool reference, return
12845 the constant pool rtx, else NULL. */
12848 maybe_get_pool_constant (rtx x)
12850 x = ix86_delegitimize_address (XEXP (x, 0));
12852 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12853 return get_pool_constant (x);
12859 ix86_expand_move (enum machine_mode mode, rtx operands[])
12862 enum tls_model model;
12867 if (GET_CODE (op1) == SYMBOL_REF)
12869 model = SYMBOL_REF_TLS_MODEL (op1);
12872 op1 = legitimize_tls_address (op1, model, true);
12873 op1 = force_operand (op1, op0);
12877 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12878 && SYMBOL_REF_DLLIMPORT_P (op1))
12879 op1 = legitimize_dllimport_symbol (op1, false);
12881 else if (GET_CODE (op1) == CONST
12882 && GET_CODE (XEXP (op1, 0)) == PLUS
12883 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12885 rtx addend = XEXP (XEXP (op1, 0), 1);
12886 rtx symbol = XEXP (XEXP (op1, 0), 0);
12889 model = SYMBOL_REF_TLS_MODEL (symbol);
12891 tmp = legitimize_tls_address (symbol, model, true);
12892 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12893 && SYMBOL_REF_DLLIMPORT_P (symbol))
12894 tmp = legitimize_dllimport_symbol (symbol, true);
12898 tmp = force_operand (tmp, NULL);
12899 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12900 op0, 1, OPTAB_DIRECT);
12906 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12908 if (TARGET_MACHO && !TARGET_64BIT)
12913 rtx temp = ((reload_in_progress
12914 || ((op0 && REG_P (op0))
12916 ? op0 : gen_reg_rtx (Pmode));
12917 op1 = machopic_indirect_data_reference (op1, temp);
12918 op1 = machopic_legitimize_pic_address (op1, mode,
12919 temp == op1 ? 0 : temp);
12921 else if (MACHOPIC_INDIRECT)
12922 op1 = machopic_indirect_data_reference (op1, 0);
12930 op1 = force_reg (Pmode, op1);
12931 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12933 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12934 op1 = legitimize_pic_address (op1, reg);
12943 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12944 || !push_operand (op0, mode))
12946 op1 = force_reg (mode, op1);
12948 if (push_operand (op0, mode)
12949 && ! general_no_elim_operand (op1, mode))
12950 op1 = copy_to_mode_reg (mode, op1);
12952 /* Force large constants in 64bit compilation into register
12953 to get them CSEed. */
12954 if (can_create_pseudo_p ()
12955 && (mode == DImode) && TARGET_64BIT
12956 && immediate_operand (op1, mode)
12957 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12958 && !register_operand (op0, mode)
12960 op1 = copy_to_mode_reg (mode, op1);
12962 if (can_create_pseudo_p ()
12963 && FLOAT_MODE_P (mode)
12964 && GET_CODE (op1) == CONST_DOUBLE)
12966 /* If we are loading a floating point constant to a register,
12967 force the value to memory now, since we'll get better code
12968 out the back end. */
12970 op1 = validize_mem (force_const_mem (mode, op1));
12971 if (!register_operand (op0, mode))
12973 rtx temp = gen_reg_rtx (mode);
12974 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12975 emit_move_insn (op0, temp);
12981 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12985 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12987 rtx op0 = operands[0], op1 = operands[1];
12988 unsigned int align = GET_MODE_ALIGNMENT (mode);
12990 /* Force constants other than zero into memory. We do not know how
12991 the instructions used to build constants modify the upper 64 bits
12992 of the register, once we have that information we may be able
12993 to handle some of them more efficiently. */
12994 if (can_create_pseudo_p ()
12995 && register_operand (op0, mode)
12996 && (CONSTANT_P (op1)
12997 || (GET_CODE (op1) == SUBREG
12998 && CONSTANT_P (SUBREG_REG (op1))))
12999 && !standard_sse_constant_p (op1))
13000 op1 = validize_mem (force_const_mem (mode, op1));
13002 /* We need to check memory alignment for SSE mode since attribute
13003 can make operands unaligned. */
13004 if (can_create_pseudo_p ()
13005 && SSE_REG_MODE_P (mode)
13006 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
13007 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
13011 /* ix86_expand_vector_move_misalign() does not like constants ... */
13012 if (CONSTANT_P (op1)
13013 || (GET_CODE (op1) == SUBREG
13014 && CONSTANT_P (SUBREG_REG (op1))))
13015 op1 = validize_mem (force_const_mem (mode, op1));
13017 /* ... nor both arguments in memory. */
13018 if (!register_operand (op0, mode)
13019 && !register_operand (op1, mode))
13020 op1 = force_reg (mode, op1);
13022 tmp[0] = op0; tmp[1] = op1;
13023 ix86_expand_vector_move_misalign (mode, tmp);
13027 /* Make operand1 a register if it isn't already. */
13028 if (can_create_pseudo_p ()
13029 && !register_operand (op0, mode)
13030 && !register_operand (op1, mode))
13032 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
13036 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
13039 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
13040 straight to ix86_expand_vector_move. */
13041 /* Code generation for scalar reg-reg moves of single and double precision data:
13042 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
13046 if (x86_sse_partial_reg_dependency == true)
13051 Code generation for scalar loads of double precision data:
13052 if (x86_sse_split_regs == true)
13053 movlpd mem, reg (gas syntax)
13057 Code generation for unaligned packed loads of single precision data
13058 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
13059 if (x86_sse_unaligned_move_optimal)
13062 if (x86_sse_partial_reg_dependency == true)
13074 Code generation for unaligned packed loads of double precision data
13075 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
13076 if (x86_sse_unaligned_move_optimal)
13079 if (x86_sse_split_regs == true)
13092 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
13101 switch (GET_MODE_CLASS (mode))
13103 case MODE_VECTOR_INT:
13105 switch (GET_MODE_SIZE (mode))
13108 op0 = gen_lowpart (V16QImode, op0);
13109 op1 = gen_lowpart (V16QImode, op1);
13110 emit_insn (gen_avx_movdqu (op0, op1));
13113 op0 = gen_lowpart (V32QImode, op0);
13114 op1 = gen_lowpart (V32QImode, op1);
13115 emit_insn (gen_avx_movdqu256 (op0, op1));
13118 gcc_unreachable ();
13121 case MODE_VECTOR_FLOAT:
13122 op0 = gen_lowpart (mode, op0);
13123 op1 = gen_lowpart (mode, op1);
13128 emit_insn (gen_avx_movups (op0, op1));
13131 emit_insn (gen_avx_movups256 (op0, op1));
13134 emit_insn (gen_avx_movupd (op0, op1));
13137 emit_insn (gen_avx_movupd256 (op0, op1));
13140 gcc_unreachable ();
13145 gcc_unreachable ();
13153 /* If we're optimizing for size, movups is the smallest. */
13154 if (optimize_insn_for_size_p ())
13156 op0 = gen_lowpart (V4SFmode, op0);
13157 op1 = gen_lowpart (V4SFmode, op1);
13158 emit_insn (gen_sse_movups (op0, op1));
13162 /* ??? If we have typed data, then it would appear that using
13163 movdqu is the only way to get unaligned data loaded with
13165 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13167 op0 = gen_lowpart (V16QImode, op0);
13168 op1 = gen_lowpart (V16QImode, op1);
13169 emit_insn (gen_sse2_movdqu (op0, op1));
13173 if (TARGET_SSE2 && mode == V2DFmode)
13177 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13179 op0 = gen_lowpart (V2DFmode, op0);
13180 op1 = gen_lowpart (V2DFmode, op1);
13181 emit_insn (gen_sse2_movupd (op0, op1));
13185 /* When SSE registers are split into halves, we can avoid
13186 writing to the top half twice. */
13187 if (TARGET_SSE_SPLIT_REGS)
13189 emit_clobber (op0);
13194 /* ??? Not sure about the best option for the Intel chips.
13195 The following would seem to satisfy; the register is
13196 entirely cleared, breaking the dependency chain. We
13197 then store to the upper half, with a dependency depth
13198 of one. A rumor has it that Intel recommends two movsd
13199 followed by an unpacklpd, but this is unconfirmed. And
13200 given that the dependency depth of the unpacklpd would
13201 still be one, I'm not sure why this would be better. */
13202 zero = CONST0_RTX (V2DFmode);
13205 m = adjust_address (op1, DFmode, 0);
13206 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13207 m = adjust_address (op1, DFmode, 8);
13208 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13212 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13214 op0 = gen_lowpart (V4SFmode, op0);
13215 op1 = gen_lowpart (V4SFmode, op1);
13216 emit_insn (gen_sse_movups (op0, op1));
13220 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13221 emit_move_insn (op0, CONST0_RTX (mode));
13223 emit_clobber (op0);
13225 if (mode != V4SFmode)
13226 op0 = gen_lowpart (V4SFmode, op0);
13227 m = adjust_address (op1, V2SFmode, 0);
13228 emit_insn (gen_sse_loadlps (op0, op0, m));
13229 m = adjust_address (op1, V2SFmode, 8);
13230 emit_insn (gen_sse_loadhps (op0, op0, m));
13233 else if (MEM_P (op0))
13235 /* If we're optimizing for size, movups is the smallest. */
13236 if (optimize_insn_for_size_p ())
13238 op0 = gen_lowpart (V4SFmode, op0);
13239 op1 = gen_lowpart (V4SFmode, op1);
13240 emit_insn (gen_sse_movups (op0, op1));
13244 /* ??? Similar to above, only less clear because of quote
13245 typeless stores unquote. */
13246 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13247 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13249 op0 = gen_lowpart (V16QImode, op0);
13250 op1 = gen_lowpart (V16QImode, op1);
13251 emit_insn (gen_sse2_movdqu (op0, op1));
13255 if (TARGET_SSE2 && mode == V2DFmode)
13257 m = adjust_address (op0, DFmode, 0);
13258 emit_insn (gen_sse2_storelpd (m, op1));
13259 m = adjust_address (op0, DFmode, 8);
13260 emit_insn (gen_sse2_storehpd (m, op1));
13264 if (mode != V4SFmode)
13265 op1 = gen_lowpart (V4SFmode, op1);
13266 m = adjust_address (op0, V2SFmode, 0);
13267 emit_insn (gen_sse_storelps (m, op1));
13268 m = adjust_address (op0, V2SFmode, 8);
13269 emit_insn (gen_sse_storehps (m, op1));
13273 gcc_unreachable ();
13276 /* Expand a push in MODE. This is some mode for which we do not support
13277 proper push instructions, at least from the registers that we expect
13278 the value to live in. */
13281 ix86_expand_push (enum machine_mode mode, rtx x)
13285 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13286 GEN_INT (-GET_MODE_SIZE (mode)),
13287 stack_pointer_rtx, 1, OPTAB_DIRECT);
13288 if (tmp != stack_pointer_rtx)
13289 emit_move_insn (stack_pointer_rtx, tmp);
13291 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13293 /* When we push an operand onto stack, it has to be aligned at least
13294 at the function argument boundary. However since we don't have
13295 the argument type, we can't determine the actual argument
13297 emit_move_insn (tmp, x);
13300 /* Helper function of ix86_fixup_binary_operands to canonicalize
13301 operand order. Returns true if the operands should be swapped. */
13304 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13307 rtx dst = operands[0];
13308 rtx src1 = operands[1];
13309 rtx src2 = operands[2];
13311 /* If the operation is not commutative, we can't do anything. */
13312 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13315 /* Highest priority is that src1 should match dst. */
13316 if (rtx_equal_p (dst, src1))
13318 if (rtx_equal_p (dst, src2))
13321 /* Next highest priority is that immediate constants come second. */
13322 if (immediate_operand (src2, mode))
13324 if (immediate_operand (src1, mode))
13327 /* Lowest priority is that memory references should come second. */
13337 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13338 destination to use for the operation. If different from the true
13339 destination in operands[0], a copy operation will be required. */
13342 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13345 rtx dst = operands[0];
13346 rtx src1 = operands[1];
13347 rtx src2 = operands[2];
13349 /* Canonicalize operand order. */
13350 if (ix86_swap_binary_operands_p (code, mode, operands))
13354 /* It is invalid to swap operands of different modes. */
13355 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13362 /* Both source operands cannot be in memory. */
13363 if (MEM_P (src1) && MEM_P (src2))
13365 /* Optimization: Only read from memory once. */
13366 if (rtx_equal_p (src1, src2))
13368 src2 = force_reg (mode, src2);
13372 src2 = force_reg (mode, src2);
13375 /* If the destination is memory, and we do not have matching source
13376 operands, do things in registers. */
13377 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13378 dst = gen_reg_rtx (mode);
13380 /* Source 1 cannot be a constant. */
13381 if (CONSTANT_P (src1))
13382 src1 = force_reg (mode, src1);
13384 /* Source 1 cannot be a non-matching memory. */
13385 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13386 src1 = force_reg (mode, src1);
13388 operands[1] = src1;
13389 operands[2] = src2;
13393 /* Similarly, but assume that the destination has already been
13394 set up properly. */
13397 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13398 enum machine_mode mode, rtx operands[])
13400 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13401 gcc_assert (dst == operands[0]);
13404 /* Attempt to expand a binary operator. Make the expansion closer to the
13405 actual machine, then just general_operand, which will allow 3 separate
13406 memory references (one output, two input) in a single insn. */
13409 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13412 rtx src1, src2, dst, op, clob;
13414 dst = ix86_fixup_binary_operands (code, mode, operands);
13415 src1 = operands[1];
13416 src2 = operands[2];
13418 /* Emit the instruction. */
13420 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13421 if (reload_in_progress)
13423 /* Reload doesn't know about the flags register, and doesn't know that
13424 it doesn't want to clobber it. We can only do this with PLUS. */
13425 gcc_assert (code == PLUS);
13430 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13431 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13434 /* Fix up the destination if needed. */
13435 if (dst != operands[0])
13436 emit_move_insn (operands[0], dst);
13439 /* Return TRUE or FALSE depending on whether the binary operator meets the
13440 appropriate constraints. */
13443 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13446 rtx dst = operands[0];
13447 rtx src1 = operands[1];
13448 rtx src2 = operands[2];
13450 /* Both source operands cannot be in memory. */
13451 if (MEM_P (src1) && MEM_P (src2))
13454 /* Canonicalize operand order for commutative operators. */
13455 if (ix86_swap_binary_operands_p (code, mode, operands))
13462 /* If the destination is memory, we must have a matching source operand. */
13463 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13466 /* Source 1 cannot be a constant. */
13467 if (CONSTANT_P (src1))
13470 /* Source 1 cannot be a non-matching memory. */
13471 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13477 /* Attempt to expand a unary operator. Make the expansion closer to the
13478 actual machine, then just general_operand, which will allow 2 separate
13479 memory references (one output, one input) in a single insn. */
13482 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13485 int matching_memory;
13486 rtx src, dst, op, clob;
13491 /* If the destination is memory, and we do not have matching source
13492 operands, do things in registers. */
13493 matching_memory = 0;
13496 if (rtx_equal_p (dst, src))
13497 matching_memory = 1;
13499 dst = gen_reg_rtx (mode);
13502 /* When source operand is memory, destination must match. */
13503 if (MEM_P (src) && !matching_memory)
13504 src = force_reg (mode, src);
13506 /* Emit the instruction. */
13508 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13509 if (reload_in_progress || code == NOT)
13511 /* Reload doesn't know about the flags register, and doesn't know that
13512 it doesn't want to clobber it. */
13513 gcc_assert (code == NOT);
13518 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13519 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13522 /* Fix up the destination if needed. */
13523 if (dst != operands[0])
13524 emit_move_insn (operands[0], dst);
13527 #define LEA_SEARCH_THRESHOLD 12
13529 /* Search backward for non-agu definition of register number REGNO1
13530 or register number REGNO2 in INSN's basic block until
13531 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13532 2. Reach BB boundary, or
13533 3. Reach agu definition.
13534 Returns the distance between the non-agu definition point and INSN.
13535 If no definition point, returns -1. */
13538 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13541 basic_block bb = BLOCK_FOR_INSN (insn);
13544 enum attr_type insn_type;
13546 if (insn != BB_HEAD (bb))
13548 rtx prev = PREV_INSN (insn);
13549 while (prev && distance < LEA_SEARCH_THRESHOLD)
13554 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13555 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13556 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13557 && (regno1 == DF_REF_REGNO (*def_rec)
13558 || regno2 == DF_REF_REGNO (*def_rec)))
13560 insn_type = get_attr_type (prev);
13561 if (insn_type != TYPE_LEA)
13565 if (prev == BB_HEAD (bb))
13567 prev = PREV_INSN (prev);
13571 if (distance < LEA_SEARCH_THRESHOLD)
13575 bool simple_loop = false;
13577 FOR_EACH_EDGE (e, ei, bb->preds)
13580 simple_loop = true;
13586 rtx prev = BB_END (bb);
13589 && distance < LEA_SEARCH_THRESHOLD)
13594 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13595 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13596 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13597 && (regno1 == DF_REF_REGNO (*def_rec)
13598 || regno2 == DF_REF_REGNO (*def_rec)))
13600 insn_type = get_attr_type (prev);
13601 if (insn_type != TYPE_LEA)
13605 prev = PREV_INSN (prev);
13613 /* get_attr_type may modify recog data. We want to make sure
13614 that recog data is valid for instruction INSN, on which
13615 distance_non_agu_define is called. INSN is unchanged here. */
13616 extract_insn_cached (insn);
13620 /* Return the distance between INSN and the next insn that uses
13621 register number REGNO0 in memory address. Return -1 if no such
13622 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13625 distance_agu_use (unsigned int regno0, rtx insn)
13627 basic_block bb = BLOCK_FOR_INSN (insn);
13632 if (insn != BB_END (bb))
13634 rtx next = NEXT_INSN (insn);
13635 while (next && distance < LEA_SEARCH_THRESHOLD)
13641 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13642 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13643 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13644 && regno0 == DF_REF_REGNO (*use_rec))
13646 /* Return DISTANCE if OP0 is used in memory
13647 address in NEXT. */
13651 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13652 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13653 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13654 && regno0 == DF_REF_REGNO (*def_rec))
13656 /* Return -1 if OP0 is set in NEXT. */
13660 if (next == BB_END (bb))
13662 next = NEXT_INSN (next);
13666 if (distance < LEA_SEARCH_THRESHOLD)
13670 bool simple_loop = false;
13672 FOR_EACH_EDGE (e, ei, bb->succs)
13675 simple_loop = true;
13681 rtx next = BB_HEAD (bb);
13684 && distance < LEA_SEARCH_THRESHOLD)
13690 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13691 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13692 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13693 && regno0 == DF_REF_REGNO (*use_rec))
13695 /* Return DISTANCE if OP0 is used in memory
13696 address in NEXT. */
13700 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13701 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13702 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13703 && regno0 == DF_REF_REGNO (*def_rec))
13705 /* Return -1 if OP0 is set in NEXT. */
13710 next = NEXT_INSN (next);
13718 /* Define this macro to tune LEA priority vs ADD, it take effect when
13719 there is a dilemma of choicing LEA or ADD
13720 Negative value: ADD is more preferred than LEA
13722 Positive value: LEA is more preferred than ADD*/
13723 #define IX86_LEA_PRIORITY 2
13725 /* Return true if it is ok to optimize an ADD operation to LEA
13726 operation to avoid flag register consumation. For the processors
13727 like ATOM, if the destination register of LEA holds an actual
13728 address which will be used soon, LEA is better and otherwise ADD
13732 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13733 rtx insn, rtx operands[])
13735 unsigned int regno0 = true_regnum (operands[0]);
13736 unsigned int regno1 = true_regnum (operands[1]);
13737 unsigned int regno2;
13739 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13740 return regno0 != regno1;
13742 regno2 = true_regnum (operands[2]);
13744 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13745 if (regno0 != regno1 && regno0 != regno2)
13749 int dist_define, dist_use;
13750 dist_define = distance_non_agu_define (regno1, regno2, insn);
13751 if (dist_define <= 0)
13754 /* If this insn has both backward non-agu dependence and forward
13755 agu dependence, the one with short distance take effect. */
13756 dist_use = distance_agu_use (regno0, insn);
13758 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13765 /* Return true if destination reg of SET_BODY is shift count of
13769 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13775 /* Retrieve destination of SET_BODY. */
13776 switch (GET_CODE (set_body))
13779 set_dest = SET_DEST (set_body);
13780 if (!set_dest || !REG_P (set_dest))
13784 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13785 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13793 /* Retrieve shift count of USE_BODY. */
13794 switch (GET_CODE (use_body))
13797 shift_rtx = XEXP (use_body, 1);
13800 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13801 if (ix86_dep_by_shift_count_body (set_body,
13802 XVECEXP (use_body, 0, i)))
13810 && (GET_CODE (shift_rtx) == ASHIFT
13811 || GET_CODE (shift_rtx) == LSHIFTRT
13812 || GET_CODE (shift_rtx) == ASHIFTRT
13813 || GET_CODE (shift_rtx) == ROTATE
13814 || GET_CODE (shift_rtx) == ROTATERT))
13816 rtx shift_count = XEXP (shift_rtx, 1);
13818 /* Return true if shift count is dest of SET_BODY. */
13819 if (REG_P (shift_count)
13820 && true_regnum (set_dest) == true_regnum (shift_count))
13827 /* Return true if destination reg of SET_INSN is shift count of
13831 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13833 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13834 PATTERN (use_insn));
13837 /* Return TRUE or FALSE depending on whether the unary operator meets the
13838 appropriate constraints. */
13841 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13842 enum machine_mode mode ATTRIBUTE_UNUSED,
13843 rtx operands[2] ATTRIBUTE_UNUSED)
13845 /* If one of operands is memory, source and destination must match. */
13846 if ((MEM_P (operands[0])
13847 || MEM_P (operands[1]))
13848 && ! rtx_equal_p (operands[0], operands[1]))
13853 /* Post-reload splitter for converting an SF or DFmode value in an
13854 SSE register into an unsigned SImode. */
13857 ix86_split_convert_uns_si_sse (rtx operands[])
13859 enum machine_mode vecmode;
13860 rtx value, large, zero_or_two31, input, two31, x;
13862 large = operands[1];
13863 zero_or_two31 = operands[2];
13864 input = operands[3];
13865 two31 = operands[4];
13866 vecmode = GET_MODE (large);
13867 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13869 /* Load up the value into the low element. We must ensure that the other
13870 elements are valid floats -- zero is the easiest such value. */
13873 if (vecmode == V4SFmode)
13874 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13876 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13880 input = gen_rtx_REG (vecmode, REGNO (input));
13881 emit_move_insn (value, CONST0_RTX (vecmode));
13882 if (vecmode == V4SFmode)
13883 emit_insn (gen_sse_movss (value, value, input));
13885 emit_insn (gen_sse2_movsd (value, value, input));
13888 emit_move_insn (large, two31);
13889 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13891 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13892 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13894 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13895 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13897 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13898 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13900 large = gen_rtx_REG (V4SImode, REGNO (large));
13901 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13903 x = gen_rtx_REG (V4SImode, REGNO (value));
13904 if (vecmode == V4SFmode)
13905 emit_insn (gen_sse2_cvttps2dq (x, value));
13907 emit_insn (gen_sse2_cvttpd2dq (x, value));
13910 emit_insn (gen_xorv4si3 (value, value, large));
13913 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13914 Expects the 64-bit DImode to be supplied in a pair of integral
13915 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13916 -mfpmath=sse, !optimize_size only. */
13919 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13921 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13922 rtx int_xmm, fp_xmm;
13923 rtx biases, exponents;
13926 int_xmm = gen_reg_rtx (V4SImode);
13927 if (TARGET_INTER_UNIT_MOVES)
13928 emit_insn (gen_movdi_to_sse (int_xmm, input));
13929 else if (TARGET_SSE_SPLIT_REGS)
13931 emit_clobber (int_xmm);
13932 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13936 x = gen_reg_rtx (V2DImode);
13937 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13938 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13941 x = gen_rtx_CONST_VECTOR (V4SImode,
13942 gen_rtvec (4, GEN_INT (0x43300000UL),
13943 GEN_INT (0x45300000UL),
13944 const0_rtx, const0_rtx));
13945 exponents = validize_mem (force_const_mem (V4SImode, x));
13947 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13948 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13950 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13951 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13952 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13953 (0x1.0p84 + double(fp_value_hi_xmm)).
13954 Note these exponents differ by 32. */
13956 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13958 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13959 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13960 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13961 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13962 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13963 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13964 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13965 biases = validize_mem (force_const_mem (V2DFmode, biases));
13966 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13968 /* Add the upper and lower DFmode values together. */
13970 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13973 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13974 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13975 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13978 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13981 /* Not used, but eases macroization of patterns. */
13983 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13984 rtx input ATTRIBUTE_UNUSED)
13986 gcc_unreachable ();
13989 /* Convert an unsigned SImode value into a DFmode. Only currently used
13990 for SSE, but applicable anywhere. */
13993 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13995 REAL_VALUE_TYPE TWO31r;
13998 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13999 NULL, 1, OPTAB_DIRECT);
14001 fp = gen_reg_rtx (DFmode);
14002 emit_insn (gen_floatsidf2 (fp, x));
14004 real_ldexp (&TWO31r, &dconst1, 31);
14005 x = const_double_from_real_value (TWO31r, DFmode);
14007 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
14009 emit_move_insn (target, x);
14012 /* Convert a signed DImode value into a DFmode. Only used for SSE in
14013 32-bit mode; otherwise we have a direct convert instruction. */
14016 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
14018 REAL_VALUE_TYPE TWO32r;
14019 rtx fp_lo, fp_hi, x;
14021 fp_lo = gen_reg_rtx (DFmode);
14022 fp_hi = gen_reg_rtx (DFmode);
14024 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
14026 real_ldexp (&TWO32r, &dconst1, 32);
14027 x = const_double_from_real_value (TWO32r, DFmode);
14028 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
14030 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
14032 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
14035 emit_move_insn (target, x);
14038 /* Convert an unsigned SImode value into a SFmode, using only SSE.
14039 For x86_32, -mfpmath=sse, !optimize_size only. */
14041 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
14043 REAL_VALUE_TYPE ONE16r;
14044 rtx fp_hi, fp_lo, int_hi, int_lo, x;
14046 real_ldexp (&ONE16r, &dconst1, 16);
14047 x = const_double_from_real_value (ONE16r, SFmode);
14048 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
14049 NULL, 0, OPTAB_DIRECT);
14050 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
14051 NULL, 0, OPTAB_DIRECT);
14052 fp_hi = gen_reg_rtx (SFmode);
14053 fp_lo = gen_reg_rtx (SFmode);
14054 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
14055 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
14056 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
14058 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
14060 if (!rtx_equal_p (target, fp_hi))
14061 emit_move_insn (target, fp_hi);
14064 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
14065 then replicate the value for all elements of the vector
14069 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
14076 v = gen_rtvec (4, value, value, value, value);
14077 return gen_rtx_CONST_VECTOR (V4SImode, v);
14081 v = gen_rtvec (2, value, value);
14082 return gen_rtx_CONST_VECTOR (V2DImode, v);
14086 v = gen_rtvec (4, value, value, value, value);
14088 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
14089 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
14090 return gen_rtx_CONST_VECTOR (V4SFmode, v);
14094 v = gen_rtvec (2, value, value);
14096 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
14097 return gen_rtx_CONST_VECTOR (V2DFmode, v);
14100 gcc_unreachable ();
14104 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
14105 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
14106 for an SSE register. If VECT is true, then replicate the mask for
14107 all elements of the vector register. If INVERT is true, then create
14108 a mask excluding the sign bit. */
14111 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
14113 enum machine_mode vec_mode, imode;
14114 HOST_WIDE_INT hi, lo;
14119 /* Find the sign bit, sign extended to 2*HWI. */
14125 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
14126 lo = 0x80000000, hi = lo < 0;
14132 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
14133 if (HOST_BITS_PER_WIDE_INT >= 64)
14134 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
14136 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14141 vec_mode = VOIDmode;
14142 if (HOST_BITS_PER_WIDE_INT >= 64)
14145 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
14152 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14156 lo = ~lo, hi = ~hi;
14162 mask = immed_double_const (lo, hi, imode);
14164 vec = gen_rtvec (2, v, mask);
14165 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
14166 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
14173 gcc_unreachable ();
14177 lo = ~lo, hi = ~hi;
14179 /* Force this value into the low part of a fp vector constant. */
14180 mask = immed_double_const (lo, hi, imode);
14181 mask = gen_lowpart (mode, mask);
14183 if (vec_mode == VOIDmode)
14184 return force_reg (mode, mask);
14186 v = ix86_build_const_vector (mode, vect, mask);
14187 return force_reg (vec_mode, v);
14190 /* Generate code for floating point ABS or NEG. */
14193 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14196 rtx mask, set, use, clob, dst, src;
14197 bool use_sse = false;
14198 bool vector_mode = VECTOR_MODE_P (mode);
14199 enum machine_mode elt_mode = mode;
14203 elt_mode = GET_MODE_INNER (mode);
14206 else if (mode == TFmode)
14208 else if (TARGET_SSE_MATH)
14209 use_sse = SSE_FLOAT_MODE_P (mode);
14211 /* NEG and ABS performed with SSE use bitwise mask operations.
14212 Create the appropriate mask now. */
14214 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14223 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14224 set = gen_rtx_SET (VOIDmode, dst, set);
14229 set = gen_rtx_fmt_e (code, mode, src);
14230 set = gen_rtx_SET (VOIDmode, dst, set);
14233 use = gen_rtx_USE (VOIDmode, mask);
14234 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14235 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14236 gen_rtvec (3, set, use, clob)));
14243 /* Expand a copysign operation. Special case operand 0 being a constant. */
14246 ix86_expand_copysign (rtx operands[])
14248 enum machine_mode mode;
14249 rtx dest, op0, op1, mask, nmask;
14251 dest = operands[0];
14255 mode = GET_MODE (dest);
14257 if (GET_CODE (op0) == CONST_DOUBLE)
14259 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14261 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14262 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14264 if (mode == SFmode || mode == DFmode)
14266 enum machine_mode vmode;
14268 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14270 if (op0 == CONST0_RTX (mode))
14271 op0 = CONST0_RTX (vmode);
14274 rtx v = ix86_build_const_vector (mode, false, op0);
14276 op0 = force_reg (vmode, v);
14279 else if (op0 != CONST0_RTX (mode))
14280 op0 = force_reg (mode, op0);
14282 mask = ix86_build_signbit_mask (mode, 0, 0);
14284 if (mode == SFmode)
14285 copysign_insn = gen_copysignsf3_const;
14286 else if (mode == DFmode)
14287 copysign_insn = gen_copysigndf3_const;
14289 copysign_insn = gen_copysigntf3_const;
14291 emit_insn (copysign_insn (dest, op0, op1, mask));
14295 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14297 nmask = ix86_build_signbit_mask (mode, 0, 1);
14298 mask = ix86_build_signbit_mask (mode, 0, 0);
14300 if (mode == SFmode)
14301 copysign_insn = gen_copysignsf3_var;
14302 else if (mode == DFmode)
14303 copysign_insn = gen_copysigndf3_var;
14305 copysign_insn = gen_copysigntf3_var;
14307 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14311 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14312 be a constant, and so has already been expanded into a vector constant. */
14315 ix86_split_copysign_const (rtx operands[])
14317 enum machine_mode mode, vmode;
14318 rtx dest, op0, mask, x;
14320 dest = operands[0];
14322 mask = operands[3];
14324 mode = GET_MODE (dest);
14325 vmode = GET_MODE (mask);
14327 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14328 x = gen_rtx_AND (vmode, dest, mask);
14329 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14331 if (op0 != CONST0_RTX (vmode))
14333 x = gen_rtx_IOR (vmode, dest, op0);
14334 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14338 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14339 so we have to do two masks. */
14342 ix86_split_copysign_var (rtx operands[])
14344 enum machine_mode mode, vmode;
14345 rtx dest, scratch, op0, op1, mask, nmask, x;
14347 dest = operands[0];
14348 scratch = operands[1];
14351 nmask = operands[4];
14352 mask = operands[5];
14354 mode = GET_MODE (dest);
14355 vmode = GET_MODE (mask);
14357 if (rtx_equal_p (op0, op1))
14359 /* Shouldn't happen often (it's useless, obviously), but when it does
14360 we'd generate incorrect code if we continue below. */
14361 emit_move_insn (dest, op0);
14365 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14367 gcc_assert (REGNO (op1) == REGNO (scratch));
14369 x = gen_rtx_AND (vmode, scratch, mask);
14370 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14373 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14374 x = gen_rtx_NOT (vmode, dest);
14375 x = gen_rtx_AND (vmode, x, op0);
14376 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14380 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14382 x = gen_rtx_AND (vmode, scratch, mask);
14384 else /* alternative 2,4 */
14386 gcc_assert (REGNO (mask) == REGNO (scratch));
14387 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14388 x = gen_rtx_AND (vmode, scratch, op1);
14390 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14392 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14394 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14395 x = gen_rtx_AND (vmode, dest, nmask);
14397 else /* alternative 3,4 */
14399 gcc_assert (REGNO (nmask) == REGNO (dest));
14401 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14402 x = gen_rtx_AND (vmode, dest, op0);
14404 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14407 x = gen_rtx_IOR (vmode, dest, scratch);
14408 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14411 /* Return TRUE or FALSE depending on whether the first SET in INSN
14412 has source and destination with matching CC modes, and that the
14413 CC mode is at least as constrained as REQ_MODE. */
14416 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14419 enum machine_mode set_mode;
14421 set = PATTERN (insn);
14422 if (GET_CODE (set) == PARALLEL)
14423 set = XVECEXP (set, 0, 0);
14424 gcc_assert (GET_CODE (set) == SET);
14425 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14427 set_mode = GET_MODE (SET_DEST (set));
14431 if (req_mode != CCNOmode
14432 && (req_mode != CCmode
14433 || XEXP (SET_SRC (set), 1) != const0_rtx))
14437 if (req_mode == CCGCmode)
14441 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14445 if (req_mode == CCZmode)
14456 gcc_unreachable ();
14459 return (GET_MODE (SET_SRC (set)) == set_mode);
14462 /* Generate insn patterns to do an integer compare of OPERANDS. */
14465 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14467 enum machine_mode cmpmode;
14470 cmpmode = SELECT_CC_MODE (code, op0, op1);
14471 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14473 /* This is very simple, but making the interface the same as in the
14474 FP case makes the rest of the code easier. */
14475 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14476 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14478 /* Return the test that should be put into the flags user, i.e.
14479 the bcc, scc, or cmov instruction. */
14480 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14483 /* Figure out whether to use ordered or unordered fp comparisons.
14484 Return the appropriate mode to use. */
14487 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14489 /* ??? In order to make all comparisons reversible, we do all comparisons
14490 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14491 all forms trapping and nontrapping comparisons, we can make inequality
14492 comparisons trapping again, since it results in better code when using
14493 FCOM based compares. */
14494 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14498 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14500 enum machine_mode mode = GET_MODE (op0);
14502 if (SCALAR_FLOAT_MODE_P (mode))
14504 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14505 return ix86_fp_compare_mode (code);
14510 /* Only zero flag is needed. */
14511 case EQ: /* ZF=0 */
14512 case NE: /* ZF!=0 */
14514 /* Codes needing carry flag. */
14515 case GEU: /* CF=0 */
14516 case LTU: /* CF=1 */
14517 /* Detect overflow checks. They need just the carry flag. */
14518 if (GET_CODE (op0) == PLUS
14519 && rtx_equal_p (op1, XEXP (op0, 0)))
14523 case GTU: /* CF=0 & ZF=0 */
14524 case LEU: /* CF=1 | ZF=1 */
14525 /* Detect overflow checks. They need just the carry flag. */
14526 if (GET_CODE (op0) == MINUS
14527 && rtx_equal_p (op1, XEXP (op0, 0)))
14531 /* Codes possibly doable only with sign flag when
14532 comparing against zero. */
14533 case GE: /* SF=OF or SF=0 */
14534 case LT: /* SF<>OF or SF=1 */
14535 if (op1 == const0_rtx)
14538 /* For other cases Carry flag is not required. */
14540 /* Codes doable only with sign flag when comparing
14541 against zero, but we miss jump instruction for it
14542 so we need to use relational tests against overflow
14543 that thus needs to be zero. */
14544 case GT: /* ZF=0 & SF=OF */
14545 case LE: /* ZF=1 | SF<>OF */
14546 if (op1 == const0_rtx)
14550 /* strcmp pattern do (use flags) and combine may ask us for proper
14555 gcc_unreachable ();
14559 /* Return the fixed registers used for condition codes. */
14562 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14569 /* If two condition code modes are compatible, return a condition code
14570 mode which is compatible with both. Otherwise, return
14573 static enum machine_mode
14574 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14579 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14582 if ((m1 == CCGCmode && m2 == CCGOCmode)
14583 || (m1 == CCGOCmode && m2 == CCGCmode))
14589 gcc_unreachable ();
14619 /* These are only compatible with themselves, which we already
14626 /* Return a comparison we can do and that it is equivalent to
14627 swap_condition (code) apart possibly from orderedness.
14628 But, never change orderedness if TARGET_IEEE_FP, returning
14629 UNKNOWN in that case if necessary. */
14631 static enum rtx_code
14632 ix86_fp_swap_condition (enum rtx_code code)
14636 case GT: /* GTU - CF=0 & ZF=0 */
14637 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14638 case GE: /* GEU - CF=0 */
14639 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14640 case UNLT: /* LTU - CF=1 */
14641 return TARGET_IEEE_FP ? UNKNOWN : GT;
14642 case UNLE: /* LEU - CF=1 | ZF=1 */
14643 return TARGET_IEEE_FP ? UNKNOWN : GE;
14645 return swap_condition (code);
14649 /* Return cost of comparison CODE using the best strategy for performance.
14650 All following functions do use number of instructions as a cost metrics.
14651 In future this should be tweaked to compute bytes for optimize_size and
14652 take into account performance of various instructions on various CPUs. */
14655 ix86_fp_comparison_cost (enum rtx_code code)
14659 /* The cost of code using bit-twiddling on %ah. */
14676 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14680 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14683 gcc_unreachable ();
14686 switch (ix86_fp_comparison_strategy (code))
14688 case IX86_FPCMP_COMI:
14689 return arith_cost > 4 ? 3 : 2;
14690 case IX86_FPCMP_SAHF:
14691 return arith_cost > 4 ? 4 : 3;
14697 /* Return strategy to use for floating-point. We assume that fcomi is always
14698 preferrable where available, since that is also true when looking at size
14699 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14701 enum ix86_fpcmp_strategy
14702 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14704 /* Do fcomi/sahf based test when profitable. */
14707 return IX86_FPCMP_COMI;
14709 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14710 return IX86_FPCMP_SAHF;
14712 return IX86_FPCMP_ARITH;
14715 /* Swap, force into registers, or otherwise massage the two operands
14716 to a fp comparison. The operands are updated in place; the new
14717 comparison code is returned. */
14719 static enum rtx_code
14720 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14722 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14723 rtx op0 = *pop0, op1 = *pop1;
14724 enum machine_mode op_mode = GET_MODE (op0);
14725 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14727 /* All of the unordered compare instructions only work on registers.
14728 The same is true of the fcomi compare instructions. The XFmode
14729 compare instructions require registers except when comparing
14730 against zero or when converting operand 1 from fixed point to
14734 && (fpcmp_mode == CCFPUmode
14735 || (op_mode == XFmode
14736 && ! (standard_80387_constant_p (op0) == 1
14737 || standard_80387_constant_p (op1) == 1)
14738 && GET_CODE (op1) != FLOAT)
14739 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14741 op0 = force_reg (op_mode, op0);
14742 op1 = force_reg (op_mode, op1);
14746 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14747 things around if they appear profitable, otherwise force op0
14748 into a register. */
14750 if (standard_80387_constant_p (op0) == 0
14752 && ! (standard_80387_constant_p (op1) == 0
14755 enum rtx_code new_code = ix86_fp_swap_condition (code);
14756 if (new_code != UNKNOWN)
14759 tmp = op0, op0 = op1, op1 = tmp;
14765 op0 = force_reg (op_mode, op0);
14767 if (CONSTANT_P (op1))
14769 int tmp = standard_80387_constant_p (op1);
14771 op1 = validize_mem (force_const_mem (op_mode, op1));
14775 op1 = force_reg (op_mode, op1);
14778 op1 = force_reg (op_mode, op1);
14782 /* Try to rearrange the comparison to make it cheaper. */
14783 if (ix86_fp_comparison_cost (code)
14784 > ix86_fp_comparison_cost (swap_condition (code))
14785 && (REG_P (op1) || can_create_pseudo_p ()))
14788 tmp = op0, op0 = op1, op1 = tmp;
14789 code = swap_condition (code);
14791 op0 = force_reg (op_mode, op0);
14799 /* Convert comparison codes we use to represent FP comparison to integer
14800 code that will result in proper branch. Return UNKNOWN if no such code
14804 ix86_fp_compare_code_to_integer (enum rtx_code code)
14833 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14836 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14838 enum machine_mode fpcmp_mode, intcmp_mode;
14841 fpcmp_mode = ix86_fp_compare_mode (code);
14842 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14844 /* Do fcomi/sahf based test when profitable. */
14845 switch (ix86_fp_comparison_strategy (code))
14847 case IX86_FPCMP_COMI:
14848 intcmp_mode = fpcmp_mode;
14849 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14850 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14855 case IX86_FPCMP_SAHF:
14856 intcmp_mode = fpcmp_mode;
14857 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14858 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14862 scratch = gen_reg_rtx (HImode);
14863 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14864 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14867 case IX86_FPCMP_ARITH:
14868 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14869 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14870 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14872 scratch = gen_reg_rtx (HImode);
14873 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14875 /* In the unordered case, we have to check C2 for NaN's, which
14876 doesn't happen to work out to anything nice combination-wise.
14877 So do some bit twiddling on the value we've got in AH to come
14878 up with an appropriate set of condition codes. */
14880 intcmp_mode = CCNOmode;
14885 if (code == GT || !TARGET_IEEE_FP)
14887 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14892 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14893 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14894 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14895 intcmp_mode = CCmode;
14901 if (code == LT && TARGET_IEEE_FP)
14903 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14904 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14905 intcmp_mode = CCmode;
14910 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14916 if (code == GE || !TARGET_IEEE_FP)
14918 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14923 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14924 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14930 if (code == LE && TARGET_IEEE_FP)
14932 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14933 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14934 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14935 intcmp_mode = CCmode;
14940 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14946 if (code == EQ && TARGET_IEEE_FP)
14948 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14949 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14950 intcmp_mode = CCmode;
14955 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14961 if (code == NE && TARGET_IEEE_FP)
14963 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14964 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14970 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14976 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14980 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14985 gcc_unreachable ();
14993 /* Return the test that should be put into the flags user, i.e.
14994 the bcc, scc, or cmov instruction. */
14995 return gen_rtx_fmt_ee (code, VOIDmode,
14996 gen_rtx_REG (intcmp_mode, FLAGS_REG),
15001 ix86_expand_compare (enum rtx_code code)
15004 op0 = ix86_compare_op0;
15005 op1 = ix86_compare_op1;
15007 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
15008 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
15010 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
15012 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
15013 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15016 ret = ix86_expand_int_compare (code, op0, op1);
15022 ix86_expand_branch (enum rtx_code code, rtx label)
15026 switch (GET_MODE (ix86_compare_op0))
15035 tmp = ix86_expand_compare (code);
15036 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15037 gen_rtx_LABEL_REF (VOIDmode, label),
15039 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15046 /* Expand DImode branch into multiple compare+branch. */
15048 rtx lo[2], hi[2], label2;
15049 enum rtx_code code1, code2, code3;
15050 enum machine_mode submode;
15052 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
15054 tmp = ix86_compare_op0;
15055 ix86_compare_op0 = ix86_compare_op1;
15056 ix86_compare_op1 = tmp;
15057 code = swap_condition (code);
15059 if (GET_MODE (ix86_compare_op0) == DImode)
15061 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
15062 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
15067 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
15068 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
15072 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15073 avoid two branches. This costs one extra insn, so disable when
15074 optimizing for size. */
15076 if ((code == EQ || code == NE)
15077 && (!optimize_insn_for_size_p ()
15078 || hi[1] == const0_rtx || lo[1] == const0_rtx))
15083 if (hi[1] != const0_rtx)
15084 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
15085 NULL_RTX, 0, OPTAB_WIDEN);
15088 if (lo[1] != const0_rtx)
15089 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
15090 NULL_RTX, 0, OPTAB_WIDEN);
15092 tmp = expand_binop (submode, ior_optab, xor1, xor0,
15093 NULL_RTX, 0, OPTAB_WIDEN);
15095 ix86_compare_op0 = tmp;
15096 ix86_compare_op1 = const0_rtx;
15097 ix86_expand_branch (code, label);
15101 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15102 op1 is a constant and the low word is zero, then we can just
15103 examine the high word. Similarly for low word -1 and
15104 less-or-equal-than or greater-than. */
15106 if (CONST_INT_P (hi[1]))
15109 case LT: case LTU: case GE: case GEU:
15110 if (lo[1] == const0_rtx)
15112 ix86_compare_op0 = hi[0];
15113 ix86_compare_op1 = hi[1];
15114 ix86_expand_branch (code, label);
15118 case LE: case LEU: case GT: case GTU:
15119 if (lo[1] == constm1_rtx)
15121 ix86_compare_op0 = hi[0];
15122 ix86_compare_op1 = hi[1];
15123 ix86_expand_branch (code, label);
15131 /* Otherwise, we need two or three jumps. */
15133 label2 = gen_label_rtx ();
15136 code2 = swap_condition (code);
15137 code3 = unsigned_condition (code);
15141 case LT: case GT: case LTU: case GTU:
15144 case LE: code1 = LT; code2 = GT; break;
15145 case GE: code1 = GT; code2 = LT; break;
15146 case LEU: code1 = LTU; code2 = GTU; break;
15147 case GEU: code1 = GTU; code2 = LTU; break;
15149 case EQ: code1 = UNKNOWN; code2 = NE; break;
15150 case NE: code2 = UNKNOWN; break;
15153 gcc_unreachable ();
15158 * if (hi(a) < hi(b)) goto true;
15159 * if (hi(a) > hi(b)) goto false;
15160 * if (lo(a) < lo(b)) goto true;
15164 ix86_compare_op0 = hi[0];
15165 ix86_compare_op1 = hi[1];
15167 if (code1 != UNKNOWN)
15168 ix86_expand_branch (code1, label);
15169 if (code2 != UNKNOWN)
15170 ix86_expand_branch (code2, label2);
15172 ix86_compare_op0 = lo[0];
15173 ix86_compare_op1 = lo[1];
15174 ix86_expand_branch (code3, label);
15176 if (code2 != UNKNOWN)
15177 emit_label (label2);
15182 /* If we have already emitted a compare insn, go straight to simple.
15183 ix86_expand_compare won't emit anything if ix86_compare_emitted
15185 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
15190 /* Split branch based on floating point condition. */
15192 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
15193 rtx target1, rtx target2, rtx tmp, rtx pushed)
15198 if (target2 != pc_rtx)
15201 code = reverse_condition_maybe_unordered (code);
15206 condition = ix86_expand_fp_compare (code, op1, op2,
15209 /* Remove pushed operand from stack. */
15211 ix86_free_from_memory (GET_MODE (pushed));
15213 i = emit_jump_insn (gen_rtx_SET
15215 gen_rtx_IF_THEN_ELSE (VOIDmode,
15216 condition, target1, target2)));
15217 if (split_branch_probability >= 0)
15218 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15222 ix86_expand_setcc (enum rtx_code code, rtx dest)
15226 gcc_assert (GET_MODE (dest) == QImode);
15228 ret = ix86_expand_compare (code);
15229 PUT_MODE (ret, QImode);
15230 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15233 /* Expand comparison setting or clearing carry flag. Return true when
15234 successful and set pop for the operation. */
15236 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15238 enum machine_mode mode =
15239 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15241 /* Do not handle DImode compares that go through special path. */
15242 if (mode == (TARGET_64BIT ? TImode : DImode))
15245 if (SCALAR_FLOAT_MODE_P (mode))
15247 rtx compare_op, compare_seq;
15249 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15251 /* Shortcut: following common codes never translate
15252 into carry flag compares. */
15253 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15254 || code == ORDERED || code == UNORDERED)
15257 /* These comparisons require zero flag; swap operands so they won't. */
15258 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15259 && !TARGET_IEEE_FP)
15264 code = swap_condition (code);
15267 /* Try to expand the comparison and verify that we end up with
15268 carry flag based comparison. This fails to be true only when
15269 we decide to expand comparison using arithmetic that is not
15270 too common scenario. */
15272 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15273 compare_seq = get_insns ();
15276 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15277 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15278 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15280 code = GET_CODE (compare_op);
15282 if (code != LTU && code != GEU)
15285 emit_insn (compare_seq);
15290 if (!INTEGRAL_MODE_P (mode))
15299 /* Convert a==0 into (unsigned)a<1. */
15302 if (op1 != const0_rtx)
15305 code = (code == EQ ? LTU : GEU);
15308 /* Convert a>b into b<a or a>=b-1. */
15311 if (CONST_INT_P (op1))
15313 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15314 /* Bail out on overflow. We still can swap operands but that
15315 would force loading of the constant into register. */
15316 if (op1 == const0_rtx
15317 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15319 code = (code == GTU ? GEU : LTU);
15326 code = (code == GTU ? LTU : GEU);
15330 /* Convert a>=0 into (unsigned)a<0x80000000. */
15333 if (mode == DImode || op1 != const0_rtx)
15335 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15336 code = (code == LT ? GEU : LTU);
15340 if (mode == DImode || op1 != constm1_rtx)
15342 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15343 code = (code == LE ? GEU : LTU);
15349 /* Swapping operands may cause constant to appear as first operand. */
15350 if (!nonimmediate_operand (op0, VOIDmode))
15352 if (!can_create_pseudo_p ())
15354 op0 = force_reg (mode, op0);
15356 ix86_compare_op0 = op0;
15357 ix86_compare_op1 = op1;
15358 *pop = ix86_expand_compare (code);
15359 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15364 ix86_expand_int_movcc (rtx operands[])
15366 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15367 rtx compare_seq, compare_op;
15368 enum machine_mode mode = GET_MODE (operands[0]);
15369 bool sign_bit_compare_p = false;;
15372 ix86_compare_op0 = XEXP (operands[1], 0);
15373 ix86_compare_op1 = XEXP (operands[1], 1);
15374 compare_op = ix86_expand_compare (code);
15375 compare_seq = get_insns ();
15378 compare_code = GET_CODE (compare_op);
15380 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15381 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15382 sign_bit_compare_p = true;
15384 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15385 HImode insns, we'd be swallowed in word prefix ops. */
15387 if ((mode != HImode || TARGET_FAST_PREFIX)
15388 && (mode != (TARGET_64BIT ? TImode : DImode))
15389 && CONST_INT_P (operands[2])
15390 && CONST_INT_P (operands[3]))
15392 rtx out = operands[0];
15393 HOST_WIDE_INT ct = INTVAL (operands[2]);
15394 HOST_WIDE_INT cf = INTVAL (operands[3]);
15395 HOST_WIDE_INT diff;
15398 /* Sign bit compares are better done using shifts than we do by using
15400 if (sign_bit_compare_p
15401 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15402 ix86_compare_op1, &compare_op))
15404 /* Detect overlap between destination and compare sources. */
15407 if (!sign_bit_compare_p)
15409 bool fpcmp = false;
15411 compare_code = GET_CODE (compare_op);
15413 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15414 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15417 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15420 /* To simplify rest of code, restrict to the GEU case. */
15421 if (compare_code == LTU)
15423 HOST_WIDE_INT tmp = ct;
15426 compare_code = reverse_condition (compare_code);
15427 code = reverse_condition (code);
15432 PUT_CODE (compare_op,
15433 reverse_condition_maybe_unordered
15434 (GET_CODE (compare_op)));
15436 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15440 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15441 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15442 tmp = gen_reg_rtx (mode);
15444 if (mode == DImode)
15445 emit_insn (gen_x86_movdicc_0_m1 (tmp, compare_op));
15447 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
15452 if (code == GT || code == GE)
15453 code = reverse_condition (code);
15456 HOST_WIDE_INT tmp = ct;
15461 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15462 ix86_compare_op1, VOIDmode, 0, -1);
15475 tmp = expand_simple_binop (mode, PLUS,
15477 copy_rtx (tmp), 1, OPTAB_DIRECT);
15488 tmp = expand_simple_binop (mode, IOR,
15490 copy_rtx (tmp), 1, OPTAB_DIRECT);
15492 else if (diff == -1 && ct)
15502 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15504 tmp = expand_simple_binop (mode, PLUS,
15505 copy_rtx (tmp), GEN_INT (cf),
15506 copy_rtx (tmp), 1, OPTAB_DIRECT);
15514 * andl cf - ct, dest
15524 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15527 tmp = expand_simple_binop (mode, AND,
15529 gen_int_mode (cf - ct, mode),
15530 copy_rtx (tmp), 1, OPTAB_DIRECT);
15532 tmp = expand_simple_binop (mode, PLUS,
15533 copy_rtx (tmp), GEN_INT (ct),
15534 copy_rtx (tmp), 1, OPTAB_DIRECT);
15537 if (!rtx_equal_p (tmp, out))
15538 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15540 return 1; /* DONE */
15545 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15548 tmp = ct, ct = cf, cf = tmp;
15551 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15553 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15555 /* We may be reversing unordered compare to normal compare, that
15556 is not valid in general (we may convert non-trapping condition
15557 to trapping one), however on i386 we currently emit all
15558 comparisons unordered. */
15559 compare_code = reverse_condition_maybe_unordered (compare_code);
15560 code = reverse_condition_maybe_unordered (code);
15564 compare_code = reverse_condition (compare_code);
15565 code = reverse_condition (code);
15569 compare_code = UNKNOWN;
15570 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15571 && CONST_INT_P (ix86_compare_op1))
15573 if (ix86_compare_op1 == const0_rtx
15574 && (code == LT || code == GE))
15575 compare_code = code;
15576 else if (ix86_compare_op1 == constm1_rtx)
15580 else if (code == GT)
15585 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15586 if (compare_code != UNKNOWN
15587 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15588 && (cf == -1 || ct == -1))
15590 /* If lea code below could be used, only optimize
15591 if it results in a 2 insn sequence. */
15593 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15594 || diff == 3 || diff == 5 || diff == 9)
15595 || (compare_code == LT && ct == -1)
15596 || (compare_code == GE && cf == -1))
15599 * notl op1 (if necessary)
15607 code = reverse_condition (code);
15610 out = emit_store_flag (out, code, ix86_compare_op0,
15611 ix86_compare_op1, VOIDmode, 0, -1);
15613 out = expand_simple_binop (mode, IOR,
15615 out, 1, OPTAB_DIRECT);
15616 if (out != operands[0])
15617 emit_move_insn (operands[0], out);
15619 return 1; /* DONE */
15624 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15625 || diff == 3 || diff == 5 || diff == 9)
15626 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15628 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15634 * lea cf(dest*(ct-cf)),dest
15638 * This also catches the degenerate setcc-only case.
15644 out = emit_store_flag (out, code, ix86_compare_op0,
15645 ix86_compare_op1, VOIDmode, 0, 1);
15648 /* On x86_64 the lea instruction operates on Pmode, so we need
15649 to get arithmetics done in proper mode to match. */
15651 tmp = copy_rtx (out);
15655 out1 = copy_rtx (out);
15656 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15660 tmp = gen_rtx_PLUS (mode, tmp, out1);
15666 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15669 if (!rtx_equal_p (tmp, out))
15672 out = force_operand (tmp, copy_rtx (out));
15674 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15676 if (!rtx_equal_p (out, operands[0]))
15677 emit_move_insn (operands[0], copy_rtx (out));
15679 return 1; /* DONE */
15683 * General case: Jumpful:
15684 * xorl dest,dest cmpl op1, op2
15685 * cmpl op1, op2 movl ct, dest
15686 * setcc dest jcc 1f
15687 * decl dest movl cf, dest
15688 * andl (cf-ct),dest 1:
15691 * Size 20. Size 14.
15693 * This is reasonably steep, but branch mispredict costs are
15694 * high on modern cpus, so consider failing only if optimizing
15698 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15699 && BRANCH_COST (optimize_insn_for_speed_p (),
15704 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15709 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15711 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15713 /* We may be reversing unordered compare to normal compare,
15714 that is not valid in general (we may convert non-trapping
15715 condition to trapping one), however on i386 we currently
15716 emit all comparisons unordered. */
15717 code = reverse_condition_maybe_unordered (code);
15721 code = reverse_condition (code);
15722 if (compare_code != UNKNOWN)
15723 compare_code = reverse_condition (compare_code);
15727 if (compare_code != UNKNOWN)
15729 /* notl op1 (if needed)
15734 For x < 0 (resp. x <= -1) there will be no notl,
15735 so if possible swap the constants to get rid of the
15737 True/false will be -1/0 while code below (store flag
15738 followed by decrement) is 0/-1, so the constants need
15739 to be exchanged once more. */
15741 if (compare_code == GE || !cf)
15743 code = reverse_condition (code);
15748 HOST_WIDE_INT tmp = cf;
15753 out = emit_store_flag (out, code, ix86_compare_op0,
15754 ix86_compare_op1, VOIDmode, 0, -1);
15758 out = emit_store_flag (out, code, ix86_compare_op0,
15759 ix86_compare_op1, VOIDmode, 0, 1);
15761 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15762 copy_rtx (out), 1, OPTAB_DIRECT);
15765 out = expand_simple_binop (mode, AND, copy_rtx (out),
15766 gen_int_mode (cf - ct, mode),
15767 copy_rtx (out), 1, OPTAB_DIRECT);
15769 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15770 copy_rtx (out), 1, OPTAB_DIRECT);
15771 if (!rtx_equal_p (out, operands[0]))
15772 emit_move_insn (operands[0], copy_rtx (out));
15774 return 1; /* DONE */
15778 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15780 /* Try a few things more with specific constants and a variable. */
15783 rtx var, orig_out, out, tmp;
15785 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15786 return 0; /* FAIL */
15788 /* If one of the two operands is an interesting constant, load a
15789 constant with the above and mask it in with a logical operation. */
15791 if (CONST_INT_P (operands[2]))
15794 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15795 operands[3] = constm1_rtx, op = and_optab;
15796 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15797 operands[3] = const0_rtx, op = ior_optab;
15799 return 0; /* FAIL */
15801 else if (CONST_INT_P (operands[3]))
15804 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15805 operands[2] = constm1_rtx, op = and_optab;
15806 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15807 operands[2] = const0_rtx, op = ior_optab;
15809 return 0; /* FAIL */
15812 return 0; /* FAIL */
15814 orig_out = operands[0];
15815 tmp = gen_reg_rtx (mode);
15818 /* Recurse to get the constant loaded. */
15819 if (ix86_expand_int_movcc (operands) == 0)
15820 return 0; /* FAIL */
15822 /* Mask in the interesting variable. */
15823 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15825 if (!rtx_equal_p (out, orig_out))
15826 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15828 return 1; /* DONE */
15832 * For comparison with above,
15842 if (! nonimmediate_operand (operands[2], mode))
15843 operands[2] = force_reg (mode, operands[2]);
15844 if (! nonimmediate_operand (operands[3], mode))
15845 operands[3] = force_reg (mode, operands[3]);
15847 if (! register_operand (operands[2], VOIDmode)
15849 || ! register_operand (operands[3], VOIDmode)))
15850 operands[2] = force_reg (mode, operands[2]);
15853 && ! register_operand (operands[3], VOIDmode))
15854 operands[3] = force_reg (mode, operands[3]);
15856 emit_insn (compare_seq);
15857 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15858 gen_rtx_IF_THEN_ELSE (mode,
15859 compare_op, operands[2],
15862 return 1; /* DONE */
15865 /* Swap, force into registers, or otherwise massage the two operands
15866 to an sse comparison with a mask result. Thus we differ a bit from
15867 ix86_prepare_fp_compare_args which expects to produce a flags result.
15869 The DEST operand exists to help determine whether to commute commutative
15870 operators. The POP0/POP1 operands are updated in place. The new
15871 comparison code is returned, or UNKNOWN if not implementable. */
15873 static enum rtx_code
15874 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15875 rtx *pop0, rtx *pop1)
15883 /* We have no LTGT as an operator. We could implement it with
15884 NE & ORDERED, but this requires an extra temporary. It's
15885 not clear that it's worth it. */
15892 /* These are supported directly. */
15899 /* For commutative operators, try to canonicalize the destination
15900 operand to be first in the comparison - this helps reload to
15901 avoid extra moves. */
15902 if (!dest || !rtx_equal_p (dest, *pop1))
15910 /* These are not supported directly. Swap the comparison operands
15911 to transform into something that is supported. */
15915 code = swap_condition (code);
15919 gcc_unreachable ();
15925 /* Detect conditional moves that exactly match min/max operational
15926 semantics. Note that this is IEEE safe, as long as we don't
15927 interchange the operands.
15929 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15930 and TRUE if the operation is successful and instructions are emitted. */
15933 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15934 rtx cmp_op1, rtx if_true, rtx if_false)
15936 enum machine_mode mode;
15942 else if (code == UNGE)
15945 if_true = if_false;
15951 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15953 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15958 mode = GET_MODE (dest);
15960 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15961 but MODE may be a vector mode and thus not appropriate. */
15962 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15964 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15967 if_true = force_reg (mode, if_true);
15968 v = gen_rtvec (2, if_true, if_false);
15969 tmp = gen_rtx_UNSPEC (mode, v, u);
15973 code = is_min ? SMIN : SMAX;
15974 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15977 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15981 /* Expand an sse vector comparison. Return the register with the result. */
15984 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15985 rtx op_true, rtx op_false)
15987 enum machine_mode mode = GET_MODE (dest);
15990 cmp_op0 = force_reg (mode, cmp_op0);
15991 if (!nonimmediate_operand (cmp_op1, mode))
15992 cmp_op1 = force_reg (mode, cmp_op1);
15995 || reg_overlap_mentioned_p (dest, op_true)
15996 || reg_overlap_mentioned_p (dest, op_false))
15997 dest = gen_reg_rtx (mode);
15999 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
16000 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16005 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16006 operations. This is used for both scalar and vector conditional moves. */
16009 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
16011 enum machine_mode mode = GET_MODE (dest);
16014 if (op_false == CONST0_RTX (mode))
16016 op_true = force_reg (mode, op_true);
16017 x = gen_rtx_AND (mode, cmp, op_true);
16018 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16020 else if (op_true == CONST0_RTX (mode))
16022 op_false = force_reg (mode, op_false);
16023 x = gen_rtx_NOT (mode, cmp);
16024 x = gen_rtx_AND (mode, x, op_false);
16025 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16027 else if (TARGET_XOP)
16029 rtx pcmov = gen_rtx_SET (mode, dest,
16030 gen_rtx_IF_THEN_ELSE (mode, cmp,
16037 op_true = force_reg (mode, op_true);
16038 op_false = force_reg (mode, op_false);
16040 t2 = gen_reg_rtx (mode);
16042 t3 = gen_reg_rtx (mode);
16046 x = gen_rtx_AND (mode, op_true, cmp);
16047 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
16049 x = gen_rtx_NOT (mode, cmp);
16050 x = gen_rtx_AND (mode, x, op_false);
16051 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
16053 x = gen_rtx_IOR (mode, t3, t2);
16054 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16058 /* Expand a floating-point conditional move. Return true if successful. */
16061 ix86_expand_fp_movcc (rtx operands[])
16063 enum machine_mode mode = GET_MODE (operands[0]);
16064 enum rtx_code code = GET_CODE (operands[1]);
16065 rtx tmp, compare_op;
16067 ix86_compare_op0 = XEXP (operands[1], 0);
16068 ix86_compare_op1 = XEXP (operands[1], 1);
16069 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
16071 enum machine_mode cmode;
16073 /* Since we've no cmove for sse registers, don't force bad register
16074 allocation just to gain access to it. Deny movcc when the
16075 comparison mode doesn't match the move mode. */
16076 cmode = GET_MODE (ix86_compare_op0);
16077 if (cmode == VOIDmode)
16078 cmode = GET_MODE (ix86_compare_op1);
16082 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16084 &ix86_compare_op1);
16085 if (code == UNKNOWN)
16088 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
16089 ix86_compare_op1, operands[2],
16093 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
16094 ix86_compare_op1, operands[2], operands[3]);
16095 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
16099 /* The floating point conditional move instructions don't directly
16100 support conditions resulting from a signed integer comparison. */
16102 compare_op = ix86_expand_compare (code);
16103 if (!fcmov_comparison_operator (compare_op, VOIDmode))
16105 tmp = gen_reg_rtx (QImode);
16106 ix86_expand_setcc (code, tmp);
16108 ix86_compare_op0 = tmp;
16109 ix86_compare_op1 = const0_rtx;
16110 compare_op = ix86_expand_compare (code);
16113 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16114 gen_rtx_IF_THEN_ELSE (mode, compare_op,
16115 operands[2], operands[3])));
16120 /* Expand a floating-point vector conditional move; a vcond operation
16121 rather than a movcc operation. */
16124 ix86_expand_fp_vcond (rtx operands[])
16126 enum rtx_code code = GET_CODE (operands[3]);
16129 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16130 &operands[4], &operands[5]);
16131 if (code == UNKNOWN)
16134 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
16135 operands[5], operands[1], operands[2]))
16138 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
16139 operands[1], operands[2]);
16140 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
16144 /* Expand a signed/unsigned integral vector conditional move. */
16147 ix86_expand_int_vcond (rtx operands[])
16149 enum machine_mode mode = GET_MODE (operands[0]);
16150 enum rtx_code code = GET_CODE (operands[3]);
16151 bool negate = false;
16154 cop0 = operands[4];
16155 cop1 = operands[5];
16157 /* XOP supports all of the comparisons on all vector int types. */
16160 /* Canonicalize the comparison to EQ, GT, GTU. */
16171 code = reverse_condition (code);
16177 code = reverse_condition (code);
16183 code = swap_condition (code);
16184 x = cop0, cop0 = cop1, cop1 = x;
16188 gcc_unreachable ();
16191 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16192 if (mode == V2DImode)
16197 /* SSE4.1 supports EQ. */
16198 if (!TARGET_SSE4_1)
16204 /* SSE4.2 supports GT/GTU. */
16205 if (!TARGET_SSE4_2)
16210 gcc_unreachable ();
16214 /* Unsigned parallel compare is not supported by the hardware. Play some
16215 tricks to turn this into a signed comparison against 0. */
16218 cop0 = force_reg (mode, cop0);
16227 /* Perform a parallel modulo subtraction. */
16228 t1 = gen_reg_rtx (mode);
16229 emit_insn ((mode == V4SImode
16231 : gen_subv2di3) (t1, cop0, cop1));
16233 /* Extract the original sign bit of op0. */
16234 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16236 t2 = gen_reg_rtx (mode);
16237 emit_insn ((mode == V4SImode
16239 : gen_andv2di3) (t2, cop0, mask));
16241 /* XOR it back into the result of the subtraction. This results
16242 in the sign bit set iff we saw unsigned underflow. */
16243 x = gen_reg_rtx (mode);
16244 emit_insn ((mode == V4SImode
16246 : gen_xorv2di3) (x, t1, t2));
16254 /* Perform a parallel unsigned saturating subtraction. */
16255 x = gen_reg_rtx (mode);
16256 emit_insn (gen_rtx_SET (VOIDmode, x,
16257 gen_rtx_US_MINUS (mode, cop0, cop1)));
16264 gcc_unreachable ();
16268 cop1 = CONST0_RTX (mode);
16272 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16273 operands[1+negate], operands[2-negate]);
16275 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16276 operands[2-negate]);
16280 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16281 true if we should do zero extension, else sign extension. HIGH_P is
16282 true if we want the N/2 high elements, else the low elements. */
16285 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16287 enum machine_mode imode = GET_MODE (operands[1]);
16288 rtx (*unpack)(rtx, rtx, rtx);
16295 unpack = gen_vec_interleave_highv16qi;
16297 unpack = gen_vec_interleave_lowv16qi;
16301 unpack = gen_vec_interleave_highv8hi;
16303 unpack = gen_vec_interleave_lowv8hi;
16307 unpack = gen_vec_interleave_highv4si;
16309 unpack = gen_vec_interleave_lowv4si;
16312 gcc_unreachable ();
16315 dest = gen_lowpart (imode, operands[0]);
16318 se = force_reg (imode, CONST0_RTX (imode));
16320 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16321 operands[1], pc_rtx, pc_rtx);
16323 emit_insn (unpack (dest, operands[1], se));
16326 /* This function performs the same task as ix86_expand_sse_unpack,
16327 but with SSE4.1 instructions. */
16330 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16332 enum machine_mode imode = GET_MODE (operands[1]);
16333 rtx (*unpack)(rtx, rtx);
16340 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16342 unpack = gen_sse4_1_extendv8qiv8hi2;
16346 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16348 unpack = gen_sse4_1_extendv4hiv4si2;
16352 unpack = gen_sse4_1_zero_extendv2siv2di2;
16354 unpack = gen_sse4_1_extendv2siv2di2;
16357 gcc_unreachable ();
16360 dest = operands[0];
16363 /* Shift higher 8 bytes to lower 8 bytes. */
16364 src = gen_reg_rtx (imode);
16365 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16366 gen_lowpart (TImode, operands[1]),
16372 emit_insn (unpack (dest, src));
16375 /* Expand conditional increment or decrement using adb/sbb instructions.
16376 The default case using setcc followed by the conditional move can be
16377 done by generic code. */
16379 ix86_expand_int_addcc (rtx operands[])
16381 enum rtx_code code = GET_CODE (operands[1]);
16382 rtx (*insn)(rtx, rtx, rtx, rtx);
16384 rtx val = const0_rtx;
16385 bool fpcmp = false;
16386 enum machine_mode mode = GET_MODE (operands[0]);
16388 ix86_compare_op0 = XEXP (operands[1], 0);
16389 ix86_compare_op1 = XEXP (operands[1], 1);
16390 if (operands[3] != const1_rtx
16391 && operands[3] != constm1_rtx)
16393 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16394 ix86_compare_op1, &compare_op))
16396 code = GET_CODE (compare_op);
16398 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16399 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16402 code = ix86_fp_compare_code_to_integer (code);
16409 PUT_CODE (compare_op,
16410 reverse_condition_maybe_unordered
16411 (GET_CODE (compare_op)));
16413 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16415 PUT_MODE (compare_op, mode);
16417 /* Construct either adc or sbb insn. */
16418 if ((code == LTU) == (operands[3] == constm1_rtx))
16420 switch (GET_MODE (operands[0]))
16423 insn = gen_subqi3_carry;
16426 insn = gen_subhi3_carry;
16429 insn = gen_subsi3_carry;
16432 insn = gen_subdi3_carry;
16435 gcc_unreachable ();
16440 switch (GET_MODE (operands[0]))
16443 insn = gen_addqi3_carry;
16446 insn = gen_addhi3_carry;
16449 insn = gen_addsi3_carry;
16452 insn = gen_adddi3_carry;
16455 gcc_unreachable ();
16458 emit_insn (insn (operands[0], operands[2], val, compare_op));
16460 return 1; /* DONE */
16464 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16465 works for floating pointer parameters and nonoffsetable memories.
16466 For pushes, it returns just stack offsets; the values will be saved
16467 in the right order. Maximally three parts are generated. */
16470 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16475 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16477 size = (GET_MODE_SIZE (mode) + 4) / 8;
16479 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16480 gcc_assert (size >= 2 && size <= 4);
16482 /* Optimize constant pool reference to immediates. This is used by fp
16483 moves, that force all constants to memory to allow combining. */
16484 if (MEM_P (operand) && MEM_READONLY_P (operand))
16486 rtx tmp = maybe_get_pool_constant (operand);
16491 if (MEM_P (operand) && !offsettable_memref_p (operand))
16493 /* The only non-offsetable memories we handle are pushes. */
16494 int ok = push_operand (operand, VOIDmode);
16498 operand = copy_rtx (operand);
16499 PUT_MODE (operand, Pmode);
16500 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16504 if (GET_CODE (operand) == CONST_VECTOR)
16506 enum machine_mode imode = int_mode_for_mode (mode);
16507 /* Caution: if we looked through a constant pool memory above,
16508 the operand may actually have a different mode now. That's
16509 ok, since we want to pun this all the way back to an integer. */
16510 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16511 gcc_assert (operand != NULL);
16517 if (mode == DImode)
16518 split_di (&operand, 1, &parts[0], &parts[1]);
16523 if (REG_P (operand))
16525 gcc_assert (reload_completed);
16526 for (i = 0; i < size; i++)
16527 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16529 else if (offsettable_memref_p (operand))
16531 operand = adjust_address (operand, SImode, 0);
16532 parts[0] = operand;
16533 for (i = 1; i < size; i++)
16534 parts[i] = adjust_address (operand, SImode, 4 * i);
16536 else if (GET_CODE (operand) == CONST_DOUBLE)
16541 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16545 real_to_target (l, &r, mode);
16546 parts[3] = gen_int_mode (l[3], SImode);
16547 parts[2] = gen_int_mode (l[2], SImode);
16550 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16551 parts[2] = gen_int_mode (l[2], SImode);
16554 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16557 gcc_unreachable ();
16559 parts[1] = gen_int_mode (l[1], SImode);
16560 parts[0] = gen_int_mode (l[0], SImode);
16563 gcc_unreachable ();
16568 if (mode == TImode)
16569 split_ti (&operand, 1, &parts[0], &parts[1]);
16570 if (mode == XFmode || mode == TFmode)
16572 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16573 if (REG_P (operand))
16575 gcc_assert (reload_completed);
16576 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16577 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16579 else if (offsettable_memref_p (operand))
16581 operand = adjust_address (operand, DImode, 0);
16582 parts[0] = operand;
16583 parts[1] = adjust_address (operand, upper_mode, 8);
16585 else if (GET_CODE (operand) == CONST_DOUBLE)
16590 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16591 real_to_target (l, &r, mode);
16593 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16594 if (HOST_BITS_PER_WIDE_INT >= 64)
16597 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16598 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16601 parts[0] = immed_double_const (l[0], l[1], DImode);
16603 if (upper_mode == SImode)
16604 parts[1] = gen_int_mode (l[2], SImode);
16605 else if (HOST_BITS_PER_WIDE_INT >= 64)
16608 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16609 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16612 parts[1] = immed_double_const (l[2], l[3], DImode);
16615 gcc_unreachable ();
16622 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16623 Return false when normal moves are needed; true when all required
16624 insns have been emitted. Operands 2-4 contain the input values
16625 int the correct order; operands 5-7 contain the output values. */
16628 ix86_split_long_move (rtx operands[])
16633 int collisions = 0;
16634 enum machine_mode mode = GET_MODE (operands[0]);
16635 bool collisionparts[4];
16637 /* The DFmode expanders may ask us to move double.
16638 For 64bit target this is single move. By hiding the fact
16639 here we simplify i386.md splitters. */
16640 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16642 /* Optimize constant pool reference to immediates. This is used by
16643 fp moves, that force all constants to memory to allow combining. */
16645 if (MEM_P (operands[1])
16646 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16647 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16648 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16649 if (push_operand (operands[0], VOIDmode))
16651 operands[0] = copy_rtx (operands[0]);
16652 PUT_MODE (operands[0], Pmode);
16655 operands[0] = gen_lowpart (DImode, operands[0]);
16656 operands[1] = gen_lowpart (DImode, operands[1]);
16657 emit_move_insn (operands[0], operands[1]);
16661 /* The only non-offsettable memory we handle is push. */
16662 if (push_operand (operands[0], VOIDmode))
16665 gcc_assert (!MEM_P (operands[0])
16666 || offsettable_memref_p (operands[0]));
16668 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16669 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16671 /* When emitting push, take care for source operands on the stack. */
16672 if (push && MEM_P (operands[1])
16673 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16675 rtx src_base = XEXP (part[1][nparts - 1], 0);
16677 /* Compensate for the stack decrement by 4. */
16678 if (!TARGET_64BIT && nparts == 3
16679 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16680 src_base = plus_constant (src_base, 4);
16682 /* src_base refers to the stack pointer and is
16683 automatically decreased by emitted push. */
16684 for (i = 0; i < nparts; i++)
16685 part[1][i] = change_address (part[1][i],
16686 GET_MODE (part[1][i]), src_base);
16689 /* We need to do copy in the right order in case an address register
16690 of the source overlaps the destination. */
16691 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16695 for (i = 0; i < nparts; i++)
16698 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16699 if (collisionparts[i])
16703 /* Collision in the middle part can be handled by reordering. */
16704 if (collisions == 1 && nparts == 3 && collisionparts [1])
16706 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16707 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16709 else if (collisions == 1
16711 && (collisionparts [1] || collisionparts [2]))
16713 if (collisionparts [1])
16715 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16716 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16720 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16721 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16725 /* If there are more collisions, we can't handle it by reordering.
16726 Do an lea to the last part and use only one colliding move. */
16727 else if (collisions > 1)
16733 base = part[0][nparts - 1];
16735 /* Handle the case when the last part isn't valid for lea.
16736 Happens in 64-bit mode storing the 12-byte XFmode. */
16737 if (GET_MODE (base) != Pmode)
16738 base = gen_rtx_REG (Pmode, REGNO (base));
16740 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16741 part[1][0] = replace_equiv_address (part[1][0], base);
16742 for (i = 1; i < nparts; i++)
16744 tmp = plus_constant (base, UNITS_PER_WORD * i);
16745 part[1][i] = replace_equiv_address (part[1][i], tmp);
16756 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16757 emit_insn (gen_addsi3 (stack_pointer_rtx,
16758 stack_pointer_rtx, GEN_INT (-4)));
16759 emit_move_insn (part[0][2], part[1][2]);
16761 else if (nparts == 4)
16763 emit_move_insn (part[0][3], part[1][3]);
16764 emit_move_insn (part[0][2], part[1][2]);
16769 /* In 64bit mode we don't have 32bit push available. In case this is
16770 register, it is OK - we will just use larger counterpart. We also
16771 retype memory - these comes from attempt to avoid REX prefix on
16772 moving of second half of TFmode value. */
16773 if (GET_MODE (part[1][1]) == SImode)
16775 switch (GET_CODE (part[1][1]))
16778 part[1][1] = adjust_address (part[1][1], DImode, 0);
16782 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16786 gcc_unreachable ();
16789 if (GET_MODE (part[1][0]) == SImode)
16790 part[1][0] = part[1][1];
16793 emit_move_insn (part[0][1], part[1][1]);
16794 emit_move_insn (part[0][0], part[1][0]);
16798 /* Choose correct order to not overwrite the source before it is copied. */
16799 if ((REG_P (part[0][0])
16800 && REG_P (part[1][1])
16801 && (REGNO (part[0][0]) == REGNO (part[1][1])
16803 && REGNO (part[0][0]) == REGNO (part[1][2]))
16805 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16807 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16809 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16811 operands[2 + i] = part[0][j];
16812 operands[6 + i] = part[1][j];
16817 for (i = 0; i < nparts; i++)
16819 operands[2 + i] = part[0][i];
16820 operands[6 + i] = part[1][i];
16824 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16825 if (optimize_insn_for_size_p ())
16827 for (j = 0; j < nparts - 1; j++)
16828 if (CONST_INT_P (operands[6 + j])
16829 && operands[6 + j] != const0_rtx
16830 && REG_P (operands[2 + j]))
16831 for (i = j; i < nparts - 1; i++)
16832 if (CONST_INT_P (operands[7 + i])
16833 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16834 operands[7 + i] = operands[2 + j];
16837 for (i = 0; i < nparts; i++)
16838 emit_move_insn (operands[2 + i], operands[6 + i]);
16843 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16844 left shift by a constant, either using a single shift or
16845 a sequence of add instructions. */
16848 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16852 emit_insn ((mode == DImode
16854 : gen_adddi3) (operand, operand, operand));
16856 else if (!optimize_insn_for_size_p ()
16857 && count * ix86_cost->add <= ix86_cost->shift_const)
16860 for (i=0; i<count; i++)
16862 emit_insn ((mode == DImode
16864 : gen_adddi3) (operand, operand, operand));
16868 emit_insn ((mode == DImode
16870 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16874 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16876 rtx low[2], high[2];
16878 const int single_width = mode == DImode ? 32 : 64;
16880 if (CONST_INT_P (operands[2]))
16882 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16883 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16885 if (count >= single_width)
16887 emit_move_insn (high[0], low[1]);
16888 emit_move_insn (low[0], const0_rtx);
16890 if (count > single_width)
16891 ix86_expand_ashl_const (high[0], count - single_width, mode);
16895 if (!rtx_equal_p (operands[0], operands[1]))
16896 emit_move_insn (operands[0], operands[1]);
16897 emit_insn ((mode == DImode
16899 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16900 ix86_expand_ashl_const (low[0], count, mode);
16905 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16907 if (operands[1] == const1_rtx)
16909 /* Assuming we've chosen a QImode capable registers, then 1 << N
16910 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16911 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16913 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16915 ix86_expand_clear (low[0]);
16916 ix86_expand_clear (high[0]);
16917 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16919 d = gen_lowpart (QImode, low[0]);
16920 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16921 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16922 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16924 d = gen_lowpart (QImode, high[0]);
16925 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16926 s = gen_rtx_NE (QImode, flags, const0_rtx);
16927 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16930 /* Otherwise, we can get the same results by manually performing
16931 a bit extract operation on bit 5/6, and then performing the two
16932 shifts. The two methods of getting 0/1 into low/high are exactly
16933 the same size. Avoiding the shift in the bit extract case helps
16934 pentium4 a bit; no one else seems to care much either way. */
16939 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16940 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16942 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16943 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16945 emit_insn ((mode == DImode
16947 : gen_lshrdi3) (high[0], high[0],
16948 GEN_INT (mode == DImode ? 5 : 6)));
16949 emit_insn ((mode == DImode
16951 : gen_anddi3) (high[0], high[0], const1_rtx));
16952 emit_move_insn (low[0], high[0]);
16953 emit_insn ((mode == DImode
16955 : gen_xordi3) (low[0], low[0], const1_rtx));
16958 emit_insn ((mode == DImode
16960 : gen_ashldi3) (low[0], low[0], operands[2]));
16961 emit_insn ((mode == DImode
16963 : gen_ashldi3) (high[0], high[0], operands[2]));
16967 if (operands[1] == constm1_rtx)
16969 /* For -1 << N, we can avoid the shld instruction, because we
16970 know that we're shifting 0...31/63 ones into a -1. */
16971 emit_move_insn (low[0], constm1_rtx);
16972 if (optimize_insn_for_size_p ())
16973 emit_move_insn (high[0], low[0]);
16975 emit_move_insn (high[0], constm1_rtx);
16979 if (!rtx_equal_p (operands[0], operands[1]))
16980 emit_move_insn (operands[0], operands[1]);
16982 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16983 emit_insn ((mode == DImode
16985 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16988 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16990 if (TARGET_CMOVE && scratch)
16992 ix86_expand_clear (scratch);
16993 emit_insn ((mode == DImode
16994 ? gen_x86_shift_adj_1
16995 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16999 emit_insn ((mode == DImode
17000 ? gen_x86_shift_adj_2
17001 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
17005 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
17007 rtx low[2], high[2];
17009 const int single_width = mode == DImode ? 32 : 64;
17011 if (CONST_INT_P (operands[2]))
17013 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17014 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17016 if (count == single_width * 2 - 1)
17018 emit_move_insn (high[0], high[1]);
17019 emit_insn ((mode == DImode
17021 : gen_ashrdi3) (high[0], high[0],
17022 GEN_INT (single_width - 1)));
17023 emit_move_insn (low[0], high[0]);
17026 else if (count >= single_width)
17028 emit_move_insn (low[0], high[1]);
17029 emit_move_insn (high[0], low[0]);
17030 emit_insn ((mode == DImode
17032 : gen_ashrdi3) (high[0], high[0],
17033 GEN_INT (single_width - 1)));
17034 if (count > single_width)
17035 emit_insn ((mode == DImode
17037 : gen_ashrdi3) (low[0], low[0],
17038 GEN_INT (count - single_width)));
17042 if (!rtx_equal_p (operands[0], operands[1]))
17043 emit_move_insn (operands[0], operands[1]);
17044 emit_insn ((mode == DImode
17046 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17047 emit_insn ((mode == DImode
17049 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
17054 if (!rtx_equal_p (operands[0], operands[1]))
17055 emit_move_insn (operands[0], operands[1]);
17057 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17059 emit_insn ((mode == DImode
17061 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17062 emit_insn ((mode == DImode
17064 : gen_ashrdi3) (high[0], high[0], operands[2]));
17066 if (TARGET_CMOVE && scratch)
17068 emit_move_insn (scratch, high[0]);
17069 emit_insn ((mode == DImode
17071 : gen_ashrdi3) (scratch, scratch,
17072 GEN_INT (single_width - 1)));
17073 emit_insn ((mode == DImode
17074 ? gen_x86_shift_adj_1
17075 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17079 emit_insn ((mode == DImode
17080 ? gen_x86_shift_adj_3
17081 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
17086 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
17088 rtx low[2], high[2];
17090 const int single_width = mode == DImode ? 32 : 64;
17092 if (CONST_INT_P (operands[2]))
17094 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17095 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17097 if (count >= single_width)
17099 emit_move_insn (low[0], high[1]);
17100 ix86_expand_clear (high[0]);
17102 if (count > single_width)
17103 emit_insn ((mode == DImode
17105 : gen_lshrdi3) (low[0], low[0],
17106 GEN_INT (count - single_width)));
17110 if (!rtx_equal_p (operands[0], operands[1]))
17111 emit_move_insn (operands[0], operands[1]);
17112 emit_insn ((mode == DImode
17114 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17115 emit_insn ((mode == DImode
17117 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
17122 if (!rtx_equal_p (operands[0], operands[1]))
17123 emit_move_insn (operands[0], operands[1]);
17125 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17127 emit_insn ((mode == DImode
17129 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17130 emit_insn ((mode == DImode
17132 : gen_lshrdi3) (high[0], high[0], operands[2]));
17134 /* Heh. By reversing the arguments, we can reuse this pattern. */
17135 if (TARGET_CMOVE && scratch)
17137 ix86_expand_clear (scratch);
17138 emit_insn ((mode == DImode
17139 ? gen_x86_shift_adj_1
17140 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17144 emit_insn ((mode == DImode
17145 ? gen_x86_shift_adj_2
17146 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
17150 /* Predict just emitted jump instruction to be taken with probability PROB. */
17152 predict_jump (int prob)
17154 rtx insn = get_last_insn ();
17155 gcc_assert (JUMP_P (insn));
17156 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
17159 /* Helper function for the string operations below. Dest VARIABLE whether
17160 it is aligned to VALUE bytes. If true, jump to the label. */
17162 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
17164 rtx label = gen_label_rtx ();
17165 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
17166 if (GET_MODE (variable) == DImode)
17167 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
17169 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
17170 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
17173 predict_jump (REG_BR_PROB_BASE * 50 / 100);
17175 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17179 /* Adjust COUNTER by the VALUE. */
17181 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
17183 if (GET_MODE (countreg) == DImode)
17184 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
17186 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
17189 /* Zero extend possibly SImode EXP to Pmode register. */
17191 ix86_zero_extend_to_Pmode (rtx exp)
17194 if (GET_MODE (exp) == VOIDmode)
17195 return force_reg (Pmode, exp);
17196 if (GET_MODE (exp) == Pmode)
17197 return copy_to_mode_reg (Pmode, exp);
17198 r = gen_reg_rtx (Pmode);
17199 emit_insn (gen_zero_extendsidi2 (r, exp));
17203 /* Divide COUNTREG by SCALE. */
17205 scale_counter (rtx countreg, int scale)
17211 if (CONST_INT_P (countreg))
17212 return GEN_INT (INTVAL (countreg) / scale);
17213 gcc_assert (REG_P (countreg));
17215 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17216 GEN_INT (exact_log2 (scale)),
17217 NULL, 1, OPTAB_DIRECT);
17221 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17222 DImode for constant loop counts. */
17224 static enum machine_mode
17225 counter_mode (rtx count_exp)
17227 if (GET_MODE (count_exp) != VOIDmode)
17228 return GET_MODE (count_exp);
17229 if (!CONST_INT_P (count_exp))
17231 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17236 /* When SRCPTR is non-NULL, output simple loop to move memory
17237 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17238 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17239 equivalent loop to set memory by VALUE (supposed to be in MODE).
17241 The size is rounded down to whole number of chunk size moved at once.
17242 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17246 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17247 rtx destptr, rtx srcptr, rtx value,
17248 rtx count, enum machine_mode mode, int unroll,
17251 rtx out_label, top_label, iter, tmp;
17252 enum machine_mode iter_mode = counter_mode (count);
17253 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17254 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17260 top_label = gen_label_rtx ();
17261 out_label = gen_label_rtx ();
17262 iter = gen_reg_rtx (iter_mode);
17264 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17265 NULL, 1, OPTAB_DIRECT);
17266 /* Those two should combine. */
17267 if (piece_size == const1_rtx)
17269 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17271 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17273 emit_move_insn (iter, const0_rtx);
17275 emit_label (top_label);
17277 tmp = convert_modes (Pmode, iter_mode, iter, true);
17278 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17279 destmem = change_address (destmem, mode, x_addr);
17283 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17284 srcmem = change_address (srcmem, mode, y_addr);
17286 /* When unrolling for chips that reorder memory reads and writes,
17287 we can save registers by using single temporary.
17288 Also using 4 temporaries is overkill in 32bit mode. */
17289 if (!TARGET_64BIT && 0)
17291 for (i = 0; i < unroll; i++)
17296 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17298 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17300 emit_move_insn (destmem, srcmem);
17306 gcc_assert (unroll <= 4);
17307 for (i = 0; i < unroll; i++)
17309 tmpreg[i] = gen_reg_rtx (mode);
17313 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17315 emit_move_insn (tmpreg[i], srcmem);
17317 for (i = 0; i < unroll; i++)
17322 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17324 emit_move_insn (destmem, tmpreg[i]);
17329 for (i = 0; i < unroll; i++)
17333 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17334 emit_move_insn (destmem, value);
17337 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17338 true, OPTAB_LIB_WIDEN);
17340 emit_move_insn (iter, tmp);
17342 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17344 if (expected_size != -1)
17346 expected_size /= GET_MODE_SIZE (mode) * unroll;
17347 if (expected_size == 0)
17349 else if (expected_size > REG_BR_PROB_BASE)
17350 predict_jump (REG_BR_PROB_BASE - 1);
17352 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17355 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17356 iter = ix86_zero_extend_to_Pmode (iter);
17357 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17358 true, OPTAB_LIB_WIDEN);
17359 if (tmp != destptr)
17360 emit_move_insn (destptr, tmp);
17363 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17364 true, OPTAB_LIB_WIDEN);
17366 emit_move_insn (srcptr, tmp);
17368 emit_label (out_label);
17371 /* Output "rep; mov" instruction.
17372 Arguments have same meaning as for previous function */
17374 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17375 rtx destptr, rtx srcptr,
17377 enum machine_mode mode)
17383 /* If the size is known, it is shorter to use rep movs. */
17384 if (mode == QImode && CONST_INT_P (count)
17385 && !(INTVAL (count) & 3))
17388 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17389 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17390 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17391 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17392 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17393 if (mode != QImode)
17395 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17396 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17397 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17398 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17399 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17400 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17404 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17405 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17407 if (CONST_INT_P (count))
17409 count = GEN_INT (INTVAL (count)
17410 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17411 destmem = shallow_copy_rtx (destmem);
17412 srcmem = shallow_copy_rtx (srcmem);
17413 set_mem_size (destmem, count);
17414 set_mem_size (srcmem, count);
17418 if (MEM_SIZE (destmem))
17419 set_mem_size (destmem, NULL_RTX);
17420 if (MEM_SIZE (srcmem))
17421 set_mem_size (srcmem, NULL_RTX);
17423 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17427 /* Output "rep; stos" instruction.
17428 Arguments have same meaning as for previous function */
17430 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17431 rtx count, enum machine_mode mode,
17437 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17438 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17439 value = force_reg (mode, gen_lowpart (mode, value));
17440 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17441 if (mode != QImode)
17443 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17444 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17445 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17448 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17449 if (orig_value == const0_rtx && CONST_INT_P (count))
17451 count = GEN_INT (INTVAL (count)
17452 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17453 destmem = shallow_copy_rtx (destmem);
17454 set_mem_size (destmem, count);
17456 else if (MEM_SIZE (destmem))
17457 set_mem_size (destmem, NULL_RTX);
17458 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17462 emit_strmov (rtx destmem, rtx srcmem,
17463 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17465 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17466 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17467 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17470 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17472 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17473 rtx destptr, rtx srcptr, rtx count, int max_size)
17476 if (CONST_INT_P (count))
17478 HOST_WIDE_INT countval = INTVAL (count);
17481 if ((countval & 0x10) && max_size > 16)
17485 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17486 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17489 gcc_unreachable ();
17492 if ((countval & 0x08) && max_size > 8)
17495 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17498 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17499 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17503 if ((countval & 0x04) && max_size > 4)
17505 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17508 if ((countval & 0x02) && max_size > 2)
17510 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17513 if ((countval & 0x01) && max_size > 1)
17515 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17522 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17523 count, 1, OPTAB_DIRECT);
17524 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17525 count, QImode, 1, 4);
17529 /* When there are stringops, we can cheaply increase dest and src pointers.
17530 Otherwise we save code size by maintaining offset (zero is readily
17531 available from preceding rep operation) and using x86 addressing modes.
17533 if (TARGET_SINGLE_STRINGOP)
17537 rtx label = ix86_expand_aligntest (count, 4, true);
17538 src = change_address (srcmem, SImode, srcptr);
17539 dest = change_address (destmem, SImode, destptr);
17540 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17541 emit_label (label);
17542 LABEL_NUSES (label) = 1;
17546 rtx label = ix86_expand_aligntest (count, 2, true);
17547 src = change_address (srcmem, HImode, srcptr);
17548 dest = change_address (destmem, HImode, destptr);
17549 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17550 emit_label (label);
17551 LABEL_NUSES (label) = 1;
17555 rtx label = ix86_expand_aligntest (count, 1, true);
17556 src = change_address (srcmem, QImode, srcptr);
17557 dest = change_address (destmem, QImode, destptr);
17558 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17559 emit_label (label);
17560 LABEL_NUSES (label) = 1;
17565 rtx offset = force_reg (Pmode, const0_rtx);
17570 rtx label = ix86_expand_aligntest (count, 4, true);
17571 src = change_address (srcmem, SImode, srcptr);
17572 dest = change_address (destmem, SImode, destptr);
17573 emit_move_insn (dest, src);
17574 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17575 true, OPTAB_LIB_WIDEN);
17577 emit_move_insn (offset, tmp);
17578 emit_label (label);
17579 LABEL_NUSES (label) = 1;
17583 rtx label = ix86_expand_aligntest (count, 2, true);
17584 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17585 src = change_address (srcmem, HImode, tmp);
17586 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17587 dest = change_address (destmem, HImode, tmp);
17588 emit_move_insn (dest, src);
17589 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17590 true, OPTAB_LIB_WIDEN);
17592 emit_move_insn (offset, tmp);
17593 emit_label (label);
17594 LABEL_NUSES (label) = 1;
17598 rtx label = ix86_expand_aligntest (count, 1, true);
17599 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17600 src = change_address (srcmem, QImode, tmp);
17601 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17602 dest = change_address (destmem, QImode, tmp);
17603 emit_move_insn (dest, src);
17604 emit_label (label);
17605 LABEL_NUSES (label) = 1;
17610 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17612 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17613 rtx count, int max_size)
17616 expand_simple_binop (counter_mode (count), AND, count,
17617 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17618 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17619 gen_lowpart (QImode, value), count, QImode,
17623 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17625 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17629 if (CONST_INT_P (count))
17631 HOST_WIDE_INT countval = INTVAL (count);
17634 if ((countval & 0x10) && max_size > 16)
17638 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17639 emit_insn (gen_strset (destptr, dest, value));
17640 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17641 emit_insn (gen_strset (destptr, dest, value));
17644 gcc_unreachable ();
17647 if ((countval & 0x08) && max_size > 8)
17651 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17652 emit_insn (gen_strset (destptr, dest, value));
17656 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17657 emit_insn (gen_strset (destptr, dest, value));
17658 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17659 emit_insn (gen_strset (destptr, dest, value));
17663 if ((countval & 0x04) && max_size > 4)
17665 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17666 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17669 if ((countval & 0x02) && max_size > 2)
17671 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17672 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17675 if ((countval & 0x01) && max_size > 1)
17677 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17678 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17685 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17690 rtx label = ix86_expand_aligntest (count, 16, true);
17693 dest = change_address (destmem, DImode, destptr);
17694 emit_insn (gen_strset (destptr, dest, value));
17695 emit_insn (gen_strset (destptr, dest, value));
17699 dest = change_address (destmem, SImode, destptr);
17700 emit_insn (gen_strset (destptr, dest, value));
17701 emit_insn (gen_strset (destptr, dest, value));
17702 emit_insn (gen_strset (destptr, dest, value));
17703 emit_insn (gen_strset (destptr, dest, value));
17705 emit_label (label);
17706 LABEL_NUSES (label) = 1;
17710 rtx label = ix86_expand_aligntest (count, 8, true);
17713 dest = change_address (destmem, DImode, destptr);
17714 emit_insn (gen_strset (destptr, dest, value));
17718 dest = change_address (destmem, SImode, destptr);
17719 emit_insn (gen_strset (destptr, dest, value));
17720 emit_insn (gen_strset (destptr, dest, value));
17722 emit_label (label);
17723 LABEL_NUSES (label) = 1;
17727 rtx label = ix86_expand_aligntest (count, 4, true);
17728 dest = change_address (destmem, SImode, destptr);
17729 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17730 emit_label (label);
17731 LABEL_NUSES (label) = 1;
17735 rtx label = ix86_expand_aligntest (count, 2, true);
17736 dest = change_address (destmem, HImode, destptr);
17737 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17738 emit_label (label);
17739 LABEL_NUSES (label) = 1;
17743 rtx label = ix86_expand_aligntest (count, 1, true);
17744 dest = change_address (destmem, QImode, destptr);
17745 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17746 emit_label (label);
17747 LABEL_NUSES (label) = 1;
17751 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17752 DESIRED_ALIGNMENT. */
17754 expand_movmem_prologue (rtx destmem, rtx srcmem,
17755 rtx destptr, rtx srcptr, rtx count,
17756 int align, int desired_alignment)
17758 if (align <= 1 && desired_alignment > 1)
17760 rtx label = ix86_expand_aligntest (destptr, 1, false);
17761 srcmem = change_address (srcmem, QImode, srcptr);
17762 destmem = change_address (destmem, QImode, destptr);
17763 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17764 ix86_adjust_counter (count, 1);
17765 emit_label (label);
17766 LABEL_NUSES (label) = 1;
17768 if (align <= 2 && desired_alignment > 2)
17770 rtx label = ix86_expand_aligntest (destptr, 2, false);
17771 srcmem = change_address (srcmem, HImode, srcptr);
17772 destmem = change_address (destmem, HImode, destptr);
17773 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17774 ix86_adjust_counter (count, 2);
17775 emit_label (label);
17776 LABEL_NUSES (label) = 1;
17778 if (align <= 4 && desired_alignment > 4)
17780 rtx label = ix86_expand_aligntest (destptr, 4, false);
17781 srcmem = change_address (srcmem, SImode, srcptr);
17782 destmem = change_address (destmem, SImode, destptr);
17783 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17784 ix86_adjust_counter (count, 4);
17785 emit_label (label);
17786 LABEL_NUSES (label) = 1;
17788 gcc_assert (desired_alignment <= 8);
17791 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17792 ALIGN_BYTES is how many bytes need to be copied. */
17794 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17795 int desired_align, int align_bytes)
17798 rtx src_size, dst_size;
17800 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17801 if (src_align_bytes >= 0)
17802 src_align_bytes = desired_align - src_align_bytes;
17803 src_size = MEM_SIZE (src);
17804 dst_size = MEM_SIZE (dst);
17805 if (align_bytes & 1)
17807 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17808 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17810 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17812 if (align_bytes & 2)
17814 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17815 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17816 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17817 set_mem_align (dst, 2 * BITS_PER_UNIT);
17818 if (src_align_bytes >= 0
17819 && (src_align_bytes & 1) == (align_bytes & 1)
17820 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17821 set_mem_align (src, 2 * BITS_PER_UNIT);
17823 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17825 if (align_bytes & 4)
17827 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17828 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17829 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17830 set_mem_align (dst, 4 * BITS_PER_UNIT);
17831 if (src_align_bytes >= 0)
17833 unsigned int src_align = 0;
17834 if ((src_align_bytes & 3) == (align_bytes & 3))
17836 else if ((src_align_bytes & 1) == (align_bytes & 1))
17838 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17839 set_mem_align (src, src_align * BITS_PER_UNIT);
17842 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17844 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17845 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17846 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17847 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17848 if (src_align_bytes >= 0)
17850 unsigned int src_align = 0;
17851 if ((src_align_bytes & 7) == (align_bytes & 7))
17853 else if ((src_align_bytes & 3) == (align_bytes & 3))
17855 else if ((src_align_bytes & 1) == (align_bytes & 1))
17857 if (src_align > (unsigned int) desired_align)
17858 src_align = desired_align;
17859 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17860 set_mem_align (src, src_align * BITS_PER_UNIT);
17863 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17865 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17870 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17871 DESIRED_ALIGNMENT. */
17873 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17874 int align, int desired_alignment)
17876 if (align <= 1 && desired_alignment > 1)
17878 rtx label = ix86_expand_aligntest (destptr, 1, false);
17879 destmem = change_address (destmem, QImode, destptr);
17880 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17881 ix86_adjust_counter (count, 1);
17882 emit_label (label);
17883 LABEL_NUSES (label) = 1;
17885 if (align <= 2 && desired_alignment > 2)
17887 rtx label = ix86_expand_aligntest (destptr, 2, false);
17888 destmem = change_address (destmem, HImode, destptr);
17889 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17890 ix86_adjust_counter (count, 2);
17891 emit_label (label);
17892 LABEL_NUSES (label) = 1;
17894 if (align <= 4 && desired_alignment > 4)
17896 rtx label = ix86_expand_aligntest (destptr, 4, false);
17897 destmem = change_address (destmem, SImode, destptr);
17898 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17899 ix86_adjust_counter (count, 4);
17900 emit_label (label);
17901 LABEL_NUSES (label) = 1;
17903 gcc_assert (desired_alignment <= 8);
17906 /* Set enough from DST to align DST known to by aligned by ALIGN to
17907 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17909 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17910 int desired_align, int align_bytes)
17913 rtx dst_size = MEM_SIZE (dst);
17914 if (align_bytes & 1)
17916 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17918 emit_insn (gen_strset (destreg, dst,
17919 gen_lowpart (QImode, value)));
17921 if (align_bytes & 2)
17923 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17924 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17925 set_mem_align (dst, 2 * BITS_PER_UNIT);
17927 emit_insn (gen_strset (destreg, dst,
17928 gen_lowpart (HImode, value)));
17930 if (align_bytes & 4)
17932 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17933 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17934 set_mem_align (dst, 4 * BITS_PER_UNIT);
17936 emit_insn (gen_strset (destreg, dst,
17937 gen_lowpart (SImode, value)));
17939 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17940 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17941 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17943 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17947 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17948 static enum stringop_alg
17949 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17950 int *dynamic_check)
17952 const struct stringop_algs * algs;
17953 bool optimize_for_speed;
17954 /* Algorithms using the rep prefix want at least edi and ecx;
17955 additionally, memset wants eax and memcpy wants esi. Don't
17956 consider such algorithms if the user has appropriated those
17957 registers for their own purposes. */
17958 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17960 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17962 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17963 || (alg != rep_prefix_1_byte \
17964 && alg != rep_prefix_4_byte \
17965 && alg != rep_prefix_8_byte))
17966 const struct processor_costs *cost;
17968 /* Even if the string operation call is cold, we still might spend a lot
17969 of time processing large blocks. */
17970 if (optimize_function_for_size_p (cfun)
17971 || (optimize_insn_for_size_p ()
17972 && expected_size != -1 && expected_size < 256))
17973 optimize_for_speed = false;
17975 optimize_for_speed = true;
17977 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17979 *dynamic_check = -1;
17981 algs = &cost->memset[TARGET_64BIT != 0];
17983 algs = &cost->memcpy[TARGET_64BIT != 0];
17984 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17985 return stringop_alg;
17986 /* rep; movq or rep; movl is the smallest variant. */
17987 else if (!optimize_for_speed)
17989 if (!count || (count & 3))
17990 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17992 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17994 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17996 else if (expected_size != -1 && expected_size < 4)
17997 return loop_1_byte;
17998 else if (expected_size != -1)
18001 enum stringop_alg alg = libcall;
18002 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18004 /* We get here if the algorithms that were not libcall-based
18005 were rep-prefix based and we are unable to use rep prefixes
18006 based on global register usage. Break out of the loop and
18007 use the heuristic below. */
18008 if (algs->size[i].max == 0)
18010 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
18012 enum stringop_alg candidate = algs->size[i].alg;
18014 if (candidate != libcall && ALG_USABLE_P (candidate))
18016 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18017 last non-libcall inline algorithm. */
18018 if (TARGET_INLINE_ALL_STRINGOPS)
18020 /* When the current size is best to be copied by a libcall,
18021 but we are still forced to inline, run the heuristic below
18022 that will pick code for medium sized blocks. */
18023 if (alg != libcall)
18027 else if (ALG_USABLE_P (candidate))
18031 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
18033 /* When asked to inline the call anyway, try to pick meaningful choice.
18034 We look for maximal size of block that is faster to copy by hand and
18035 take blocks of at most of that size guessing that average size will
18036 be roughly half of the block.
18038 If this turns out to be bad, we might simply specify the preferred
18039 choice in ix86_costs. */
18040 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18041 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
18044 enum stringop_alg alg;
18046 bool any_alg_usable_p = true;
18048 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18050 enum stringop_alg candidate = algs->size[i].alg;
18051 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
18053 if (candidate != libcall && candidate
18054 && ALG_USABLE_P (candidate))
18055 max = algs->size[i].max;
18057 /* If there aren't any usable algorithms, then recursing on
18058 smaller sizes isn't going to find anything. Just return the
18059 simple byte-at-a-time copy loop. */
18060 if (!any_alg_usable_p)
18062 /* Pick something reasonable. */
18063 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18064 *dynamic_check = 128;
18065 return loop_1_byte;
18069 alg = decide_alg (count, max / 2, memset, dynamic_check);
18070 gcc_assert (*dynamic_check == -1);
18071 gcc_assert (alg != libcall);
18072 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18073 *dynamic_check = max;
18076 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
18077 #undef ALG_USABLE_P
18080 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18081 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18083 decide_alignment (int align,
18084 enum stringop_alg alg,
18087 int desired_align = 0;
18091 gcc_unreachable ();
18093 case unrolled_loop:
18094 desired_align = GET_MODE_SIZE (Pmode);
18096 case rep_prefix_8_byte:
18099 case rep_prefix_4_byte:
18100 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18101 copying whole cacheline at once. */
18102 if (TARGET_PENTIUMPRO)
18107 case rep_prefix_1_byte:
18108 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18109 copying whole cacheline at once. */
18110 if (TARGET_PENTIUMPRO)
18124 if (desired_align < align)
18125 desired_align = align;
18126 if (expected_size != -1 && expected_size < 4)
18127 desired_align = align;
18128 return desired_align;
18131 /* Return the smallest power of 2 greater than VAL. */
18133 smallest_pow2_greater_than (int val)
18141 /* Expand string move (memcpy) operation. Use i386 string operations when
18142 profitable. expand_setmem contains similar code. The code depends upon
18143 architecture, block size and alignment, but always has the same
18146 1) Prologue guard: Conditional that jumps up to epilogues for small
18147 blocks that can be handled by epilogue alone. This is faster but
18148 also needed for correctness, since prologue assume the block is larger
18149 than the desired alignment.
18151 Optional dynamic check for size and libcall for large
18152 blocks is emitted here too, with -minline-stringops-dynamically.
18154 2) Prologue: copy first few bytes in order to get destination aligned
18155 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18156 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18157 We emit either a jump tree on power of two sized blocks, or a byte loop.
18159 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18160 with specified algorithm.
18162 4) Epilogue: code copying tail of the block that is too small to be
18163 handled by main body (or up to size guarded by prologue guard). */
18166 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
18167 rtx expected_align_exp, rtx expected_size_exp)
18173 rtx jump_around_label = NULL;
18174 HOST_WIDE_INT align = 1;
18175 unsigned HOST_WIDE_INT count = 0;
18176 HOST_WIDE_INT expected_size = -1;
18177 int size_needed = 0, epilogue_size_needed;
18178 int desired_align = 0, align_bytes = 0;
18179 enum stringop_alg alg;
18181 bool need_zero_guard = false;
18183 if (CONST_INT_P (align_exp))
18184 align = INTVAL (align_exp);
18185 /* i386 can do misaligned access on reasonably increased cost. */
18186 if (CONST_INT_P (expected_align_exp)
18187 && INTVAL (expected_align_exp) > align)
18188 align = INTVAL (expected_align_exp);
18189 /* ALIGN is the minimum of destination and source alignment, but we care here
18190 just about destination alignment. */
18191 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
18192 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
18194 if (CONST_INT_P (count_exp))
18195 count = expected_size = INTVAL (count_exp);
18196 if (CONST_INT_P (expected_size_exp) && count == 0)
18197 expected_size = INTVAL (expected_size_exp);
18199 /* Make sure we don't need to care about overflow later on. */
18200 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18203 /* Step 0: Decide on preferred algorithm, desired alignment and
18204 size of chunks to be copied by main loop. */
18206 alg = decide_alg (count, expected_size, false, &dynamic_check);
18207 desired_align = decide_alignment (align, alg, expected_size);
18209 if (!TARGET_ALIGN_STRINGOPS)
18210 align = desired_align;
18212 if (alg == libcall)
18214 gcc_assert (alg != no_stringop);
18216 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18217 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18218 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18223 gcc_unreachable ();
18225 need_zero_guard = true;
18226 size_needed = GET_MODE_SIZE (Pmode);
18228 case unrolled_loop:
18229 need_zero_guard = true;
18230 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18232 case rep_prefix_8_byte:
18235 case rep_prefix_4_byte:
18238 case rep_prefix_1_byte:
18242 need_zero_guard = true;
18247 epilogue_size_needed = size_needed;
18249 /* Step 1: Prologue guard. */
18251 /* Alignment code needs count to be in register. */
18252 if (CONST_INT_P (count_exp) && desired_align > align)
18254 if (INTVAL (count_exp) > desired_align
18255 && INTVAL (count_exp) > size_needed)
18258 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18259 if (align_bytes <= 0)
18262 align_bytes = desired_align - align_bytes;
18264 if (align_bytes == 0)
18265 count_exp = force_reg (counter_mode (count_exp), count_exp);
18267 gcc_assert (desired_align >= 1 && align >= 1);
18269 /* Ensure that alignment prologue won't copy past end of block. */
18270 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18272 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18273 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18274 Make sure it is power of 2. */
18275 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18279 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18281 /* If main algorithm works on QImode, no epilogue is needed.
18282 For small sizes just don't align anything. */
18283 if (size_needed == 1)
18284 desired_align = align;
18291 label = gen_label_rtx ();
18292 emit_cmp_and_jump_insns (count_exp,
18293 GEN_INT (epilogue_size_needed),
18294 LTU, 0, counter_mode (count_exp), 1, label);
18295 if (expected_size == -1 || expected_size < epilogue_size_needed)
18296 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18298 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18302 /* Emit code to decide on runtime whether library call or inline should be
18304 if (dynamic_check != -1)
18306 if (CONST_INT_P (count_exp))
18308 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18310 emit_block_move_via_libcall (dst, src, count_exp, false);
18311 count_exp = const0_rtx;
18317 rtx hot_label = gen_label_rtx ();
18318 jump_around_label = gen_label_rtx ();
18319 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18320 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18321 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18322 emit_block_move_via_libcall (dst, src, count_exp, false);
18323 emit_jump (jump_around_label);
18324 emit_label (hot_label);
18328 /* Step 2: Alignment prologue. */
18330 if (desired_align > align)
18332 if (align_bytes == 0)
18334 /* Except for the first move in epilogue, we no longer know
18335 constant offset in aliasing info. It don't seems to worth
18336 the pain to maintain it for the first move, so throw away
18338 src = change_address (src, BLKmode, srcreg);
18339 dst = change_address (dst, BLKmode, destreg);
18340 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18345 /* If we know how many bytes need to be stored before dst is
18346 sufficiently aligned, maintain aliasing info accurately. */
18347 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18348 desired_align, align_bytes);
18349 count_exp = plus_constant (count_exp, -align_bytes);
18350 count -= align_bytes;
18352 if (need_zero_guard
18353 && (count < (unsigned HOST_WIDE_INT) size_needed
18354 || (align_bytes == 0
18355 && count < ((unsigned HOST_WIDE_INT) size_needed
18356 + desired_align - align))))
18358 /* It is possible that we copied enough so the main loop will not
18360 gcc_assert (size_needed > 1);
18361 if (label == NULL_RTX)
18362 label = gen_label_rtx ();
18363 emit_cmp_and_jump_insns (count_exp,
18364 GEN_INT (size_needed),
18365 LTU, 0, counter_mode (count_exp), 1, label);
18366 if (expected_size == -1
18367 || expected_size < (desired_align - align) / 2 + size_needed)
18368 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18370 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18373 if (label && size_needed == 1)
18375 emit_label (label);
18376 LABEL_NUSES (label) = 1;
18378 epilogue_size_needed = 1;
18380 else if (label == NULL_RTX)
18381 epilogue_size_needed = size_needed;
18383 /* Step 3: Main loop. */
18389 gcc_unreachable ();
18391 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18392 count_exp, QImode, 1, expected_size);
18395 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18396 count_exp, Pmode, 1, expected_size);
18398 case unrolled_loop:
18399 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18400 registers for 4 temporaries anyway. */
18401 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18402 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18405 case rep_prefix_8_byte:
18406 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18409 case rep_prefix_4_byte:
18410 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18413 case rep_prefix_1_byte:
18414 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18418 /* Adjust properly the offset of src and dest memory for aliasing. */
18419 if (CONST_INT_P (count_exp))
18421 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18422 (count / size_needed) * size_needed);
18423 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18424 (count / size_needed) * size_needed);
18428 src = change_address (src, BLKmode, srcreg);
18429 dst = change_address (dst, BLKmode, destreg);
18432 /* Step 4: Epilogue to copy the remaining bytes. */
18436 /* When the main loop is done, COUNT_EXP might hold original count,
18437 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18438 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18439 bytes. Compensate if needed. */
18441 if (size_needed < epilogue_size_needed)
18444 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18445 GEN_INT (size_needed - 1), count_exp, 1,
18447 if (tmp != count_exp)
18448 emit_move_insn (count_exp, tmp);
18450 emit_label (label);
18451 LABEL_NUSES (label) = 1;
18454 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18455 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18456 epilogue_size_needed);
18457 if (jump_around_label)
18458 emit_label (jump_around_label);
18462 /* Helper function for memcpy. For QImode value 0xXY produce
18463 0xXYXYXYXY of wide specified by MODE. This is essentially
18464 a * 0x10101010, but we can do slightly better than
18465 synth_mult by unwinding the sequence by hand on CPUs with
18468 promote_duplicated_reg (enum machine_mode mode, rtx val)
18470 enum machine_mode valmode = GET_MODE (val);
18472 int nops = mode == DImode ? 3 : 2;
18474 gcc_assert (mode == SImode || mode == DImode);
18475 if (val == const0_rtx)
18476 return copy_to_mode_reg (mode, const0_rtx);
18477 if (CONST_INT_P (val))
18479 HOST_WIDE_INT v = INTVAL (val) & 255;
18483 if (mode == DImode)
18484 v |= (v << 16) << 16;
18485 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18488 if (valmode == VOIDmode)
18490 if (valmode != QImode)
18491 val = gen_lowpart (QImode, val);
18492 if (mode == QImode)
18494 if (!TARGET_PARTIAL_REG_STALL)
18496 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18497 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18498 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18499 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18501 rtx reg = convert_modes (mode, QImode, val, true);
18502 tmp = promote_duplicated_reg (mode, const1_rtx);
18503 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18508 rtx reg = convert_modes (mode, QImode, val, true);
18510 if (!TARGET_PARTIAL_REG_STALL)
18511 if (mode == SImode)
18512 emit_insn (gen_movsi_insv_1 (reg, reg));
18514 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18517 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18518 NULL, 1, OPTAB_DIRECT);
18520 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18522 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18523 NULL, 1, OPTAB_DIRECT);
18524 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18525 if (mode == SImode)
18527 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18528 NULL, 1, OPTAB_DIRECT);
18529 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18534 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18535 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18536 alignment from ALIGN to DESIRED_ALIGN. */
18538 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18543 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18544 promoted_val = promote_duplicated_reg (DImode, val);
18545 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18546 promoted_val = promote_duplicated_reg (SImode, val);
18547 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18548 promoted_val = promote_duplicated_reg (HImode, val);
18550 promoted_val = val;
18552 return promoted_val;
18555 /* Expand string clear operation (bzero). Use i386 string operations when
18556 profitable. See expand_movmem comment for explanation of individual
18557 steps performed. */
18559 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18560 rtx expected_align_exp, rtx expected_size_exp)
18565 rtx jump_around_label = NULL;
18566 HOST_WIDE_INT align = 1;
18567 unsigned HOST_WIDE_INT count = 0;
18568 HOST_WIDE_INT expected_size = -1;
18569 int size_needed = 0, epilogue_size_needed;
18570 int desired_align = 0, align_bytes = 0;
18571 enum stringop_alg alg;
18572 rtx promoted_val = NULL;
18573 bool force_loopy_epilogue = false;
18575 bool need_zero_guard = false;
18577 if (CONST_INT_P (align_exp))
18578 align = INTVAL (align_exp);
18579 /* i386 can do misaligned access on reasonably increased cost. */
18580 if (CONST_INT_P (expected_align_exp)
18581 && INTVAL (expected_align_exp) > align)
18582 align = INTVAL (expected_align_exp);
18583 if (CONST_INT_P (count_exp))
18584 count = expected_size = INTVAL (count_exp);
18585 if (CONST_INT_P (expected_size_exp) && count == 0)
18586 expected_size = INTVAL (expected_size_exp);
18588 /* Make sure we don't need to care about overflow later on. */
18589 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18592 /* Step 0: Decide on preferred algorithm, desired alignment and
18593 size of chunks to be copied by main loop. */
18595 alg = decide_alg (count, expected_size, true, &dynamic_check);
18596 desired_align = decide_alignment (align, alg, expected_size);
18598 if (!TARGET_ALIGN_STRINGOPS)
18599 align = desired_align;
18601 if (alg == libcall)
18603 gcc_assert (alg != no_stringop);
18605 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18606 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18611 gcc_unreachable ();
18613 need_zero_guard = true;
18614 size_needed = GET_MODE_SIZE (Pmode);
18616 case unrolled_loop:
18617 need_zero_guard = true;
18618 size_needed = GET_MODE_SIZE (Pmode) * 4;
18620 case rep_prefix_8_byte:
18623 case rep_prefix_4_byte:
18626 case rep_prefix_1_byte:
18630 need_zero_guard = true;
18634 epilogue_size_needed = size_needed;
18636 /* Step 1: Prologue guard. */
18638 /* Alignment code needs count to be in register. */
18639 if (CONST_INT_P (count_exp) && desired_align > align)
18641 if (INTVAL (count_exp) > desired_align
18642 && INTVAL (count_exp) > size_needed)
18645 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18646 if (align_bytes <= 0)
18649 align_bytes = desired_align - align_bytes;
18651 if (align_bytes == 0)
18653 enum machine_mode mode = SImode;
18654 if (TARGET_64BIT && (count & ~0xffffffff))
18656 count_exp = force_reg (mode, count_exp);
18659 /* Do the cheap promotion to allow better CSE across the
18660 main loop and epilogue (ie one load of the big constant in the
18661 front of all code. */
18662 if (CONST_INT_P (val_exp))
18663 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18664 desired_align, align);
18665 /* Ensure that alignment prologue won't copy past end of block. */
18666 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18668 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18669 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18670 Make sure it is power of 2. */
18671 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18673 /* To improve performance of small blocks, we jump around the VAL
18674 promoting mode. This mean that if the promoted VAL is not constant,
18675 we might not use it in the epilogue and have to use byte
18677 if (epilogue_size_needed > 2 && !promoted_val)
18678 force_loopy_epilogue = true;
18681 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18683 /* If main algorithm works on QImode, no epilogue is needed.
18684 For small sizes just don't align anything. */
18685 if (size_needed == 1)
18686 desired_align = align;
18693 label = gen_label_rtx ();
18694 emit_cmp_and_jump_insns (count_exp,
18695 GEN_INT (epilogue_size_needed),
18696 LTU, 0, counter_mode (count_exp), 1, label);
18697 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18698 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18700 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18703 if (dynamic_check != -1)
18705 rtx hot_label = gen_label_rtx ();
18706 jump_around_label = gen_label_rtx ();
18707 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18708 LEU, 0, counter_mode (count_exp), 1, hot_label);
18709 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18710 set_storage_via_libcall (dst, count_exp, val_exp, false);
18711 emit_jump (jump_around_label);
18712 emit_label (hot_label);
18715 /* Step 2: Alignment prologue. */
18717 /* Do the expensive promotion once we branched off the small blocks. */
18719 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18720 desired_align, align);
18721 gcc_assert (desired_align >= 1 && align >= 1);
18723 if (desired_align > align)
18725 if (align_bytes == 0)
18727 /* Except for the first move in epilogue, we no longer know
18728 constant offset in aliasing info. It don't seems to worth
18729 the pain to maintain it for the first move, so throw away
18731 dst = change_address (dst, BLKmode, destreg);
18732 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18737 /* If we know how many bytes need to be stored before dst is
18738 sufficiently aligned, maintain aliasing info accurately. */
18739 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18740 desired_align, align_bytes);
18741 count_exp = plus_constant (count_exp, -align_bytes);
18742 count -= align_bytes;
18744 if (need_zero_guard
18745 && (count < (unsigned HOST_WIDE_INT) size_needed
18746 || (align_bytes == 0
18747 && count < ((unsigned HOST_WIDE_INT) size_needed
18748 + desired_align - align))))
18750 /* It is possible that we copied enough so the main loop will not
18752 gcc_assert (size_needed > 1);
18753 if (label == NULL_RTX)
18754 label = gen_label_rtx ();
18755 emit_cmp_and_jump_insns (count_exp,
18756 GEN_INT (size_needed),
18757 LTU, 0, counter_mode (count_exp), 1, label);
18758 if (expected_size == -1
18759 || expected_size < (desired_align - align) / 2 + size_needed)
18760 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18762 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18765 if (label && size_needed == 1)
18767 emit_label (label);
18768 LABEL_NUSES (label) = 1;
18770 promoted_val = val_exp;
18771 epilogue_size_needed = 1;
18773 else if (label == NULL_RTX)
18774 epilogue_size_needed = size_needed;
18776 /* Step 3: Main loop. */
18782 gcc_unreachable ();
18784 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18785 count_exp, QImode, 1, expected_size);
18788 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18789 count_exp, Pmode, 1, expected_size);
18791 case unrolled_loop:
18792 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18793 count_exp, Pmode, 4, expected_size);
18795 case rep_prefix_8_byte:
18796 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18799 case rep_prefix_4_byte:
18800 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18803 case rep_prefix_1_byte:
18804 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18808 /* Adjust properly the offset of src and dest memory for aliasing. */
18809 if (CONST_INT_P (count_exp))
18810 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18811 (count / size_needed) * size_needed);
18813 dst = change_address (dst, BLKmode, destreg);
18815 /* Step 4: Epilogue to copy the remaining bytes. */
18819 /* When the main loop is done, COUNT_EXP might hold original count,
18820 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18821 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18822 bytes. Compensate if needed. */
18824 if (size_needed < epilogue_size_needed)
18827 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18828 GEN_INT (size_needed - 1), count_exp, 1,
18830 if (tmp != count_exp)
18831 emit_move_insn (count_exp, tmp);
18833 emit_label (label);
18834 LABEL_NUSES (label) = 1;
18837 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18839 if (force_loopy_epilogue)
18840 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18841 epilogue_size_needed);
18843 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18844 epilogue_size_needed);
18846 if (jump_around_label)
18847 emit_label (jump_around_label);
18851 /* Expand the appropriate insns for doing strlen if not just doing
18854 out = result, initialized with the start address
18855 align_rtx = alignment of the address.
18856 scratch = scratch register, initialized with the startaddress when
18857 not aligned, otherwise undefined
18859 This is just the body. It needs the initializations mentioned above and
18860 some address computing at the end. These things are done in i386.md. */
18863 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18867 rtx align_2_label = NULL_RTX;
18868 rtx align_3_label = NULL_RTX;
18869 rtx align_4_label = gen_label_rtx ();
18870 rtx end_0_label = gen_label_rtx ();
18872 rtx tmpreg = gen_reg_rtx (SImode);
18873 rtx scratch = gen_reg_rtx (SImode);
18877 if (CONST_INT_P (align_rtx))
18878 align = INTVAL (align_rtx);
18880 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18882 /* Is there a known alignment and is it less than 4? */
18885 rtx scratch1 = gen_reg_rtx (Pmode);
18886 emit_move_insn (scratch1, out);
18887 /* Is there a known alignment and is it not 2? */
18890 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18891 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18893 /* Leave just the 3 lower bits. */
18894 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18895 NULL_RTX, 0, OPTAB_WIDEN);
18897 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18898 Pmode, 1, align_4_label);
18899 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18900 Pmode, 1, align_2_label);
18901 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18902 Pmode, 1, align_3_label);
18906 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18907 check if is aligned to 4 - byte. */
18909 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18910 NULL_RTX, 0, OPTAB_WIDEN);
18912 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18913 Pmode, 1, align_4_label);
18916 mem = change_address (src, QImode, out);
18918 /* Now compare the bytes. */
18920 /* Compare the first n unaligned byte on a byte per byte basis. */
18921 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18922 QImode, 1, end_0_label);
18924 /* Increment the address. */
18925 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18927 /* Not needed with an alignment of 2 */
18930 emit_label (align_2_label);
18932 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18935 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18937 emit_label (align_3_label);
18940 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18943 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18946 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18947 align this loop. It gives only huge programs, but does not help to
18949 emit_label (align_4_label);
18951 mem = change_address (src, SImode, out);
18952 emit_move_insn (scratch, mem);
18953 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18955 /* This formula yields a nonzero result iff one of the bytes is zero.
18956 This saves three branches inside loop and many cycles. */
18958 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18959 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18960 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18961 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18962 gen_int_mode (0x80808080, SImode)));
18963 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18968 rtx reg = gen_reg_rtx (SImode);
18969 rtx reg2 = gen_reg_rtx (Pmode);
18970 emit_move_insn (reg, tmpreg);
18971 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18973 /* If zero is not in the first two bytes, move two bytes forward. */
18974 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18975 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18976 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18977 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18978 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18981 /* Emit lea manually to avoid clobbering of flags. */
18982 emit_insn (gen_rtx_SET (SImode, reg2,
18983 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18985 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18986 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18987 emit_insn (gen_rtx_SET (VOIDmode, out,
18988 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18995 rtx end_2_label = gen_label_rtx ();
18996 /* Is zero in the first two bytes? */
18998 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18999 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
19000 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
19001 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
19002 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
19004 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
19005 JUMP_LABEL (tmp) = end_2_label;
19007 /* Not in the first two. Move two bytes forward. */
19008 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
19009 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
19011 emit_label (end_2_label);
19015 /* Avoid branch in fixing the byte. */
19016 tmpreg = gen_lowpart (QImode, tmpreg);
19017 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
19018 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
19019 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
19021 emit_label (end_0_label);
19024 /* Expand strlen. */
19027 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
19029 rtx addr, scratch1, scratch2, scratch3, scratch4;
19031 /* The generic case of strlen expander is long. Avoid it's
19032 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19034 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19035 && !TARGET_INLINE_ALL_STRINGOPS
19036 && !optimize_insn_for_size_p ()
19037 && (!CONST_INT_P (align) || INTVAL (align) < 4))
19040 addr = force_reg (Pmode, XEXP (src, 0));
19041 scratch1 = gen_reg_rtx (Pmode);
19043 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19044 && !optimize_insn_for_size_p ())
19046 /* Well it seems that some optimizer does not combine a call like
19047 foo(strlen(bar), strlen(bar));
19048 when the move and the subtraction is done here. It does calculate
19049 the length just once when these instructions are done inside of
19050 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19051 often used and I use one fewer register for the lifetime of
19052 output_strlen_unroll() this is better. */
19054 emit_move_insn (out, addr);
19056 ix86_expand_strlensi_unroll_1 (out, src, align);
19058 /* strlensi_unroll_1 returns the address of the zero at the end of
19059 the string, like memchr(), so compute the length by subtracting
19060 the start address. */
19061 emit_insn ((*ix86_gen_sub3) (out, out, addr));
19067 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19068 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
19071 scratch2 = gen_reg_rtx (Pmode);
19072 scratch3 = gen_reg_rtx (Pmode);
19073 scratch4 = force_reg (Pmode, constm1_rtx);
19075 emit_move_insn (scratch3, addr);
19076 eoschar = force_reg (QImode, eoschar);
19078 src = replace_equiv_address_nv (src, scratch3);
19080 /* If .md starts supporting :P, this can be done in .md. */
19081 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
19082 scratch4), UNSPEC_SCAS);
19083 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
19084 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
19085 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
19090 /* For given symbol (function) construct code to compute address of it's PLT
19091 entry in large x86-64 PIC model. */
19093 construct_plt_address (rtx symbol)
19095 rtx tmp = gen_reg_rtx (Pmode);
19096 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
19098 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
19099 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
19101 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
19102 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
19107 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
19109 rtx pop, int sibcall)
19111 rtx use = NULL, call;
19113 if (pop == const0_rtx)
19115 gcc_assert (!TARGET_64BIT || !pop);
19117 if (TARGET_MACHO && !TARGET_64BIT)
19120 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
19121 fnaddr = machopic_indirect_call_target (fnaddr);
19126 /* Static functions and indirect calls don't need the pic register. */
19127 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
19128 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19129 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
19130 use_reg (&use, pic_offset_table_rtx);
19133 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
19135 rtx al = gen_rtx_REG (QImode, AX_REG);
19136 emit_move_insn (al, callarg2);
19137 use_reg (&use, al);
19140 if (ix86_cmodel == CM_LARGE_PIC
19142 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19143 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
19144 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
19146 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
19147 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
19149 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19150 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19153 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
19155 call = gen_rtx_SET (VOIDmode, retval, call);
19158 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
19159 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
19160 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
19163 && ix86_cfun_abi () == MS_ABI
19164 && (!callarg2 || INTVAL (callarg2) != -2))
19166 /* We need to represent that SI and DI registers are clobbered
19168 static int clobbered_registers[] = {
19169 XMM6_REG, XMM7_REG, XMM8_REG,
19170 XMM9_REG, XMM10_REG, XMM11_REG,
19171 XMM12_REG, XMM13_REG, XMM14_REG,
19172 XMM15_REG, SI_REG, DI_REG
19175 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
19176 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
19177 UNSPEC_MS_TO_SYSV_CALL);
19181 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
19182 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
19185 (SSE_REGNO_P (clobbered_registers[i])
19187 clobbered_registers[i]));
19189 call = gen_rtx_PARALLEL (VOIDmode,
19190 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
19194 call = emit_call_insn (call);
19196 CALL_INSN_FUNCTION_USAGE (call) = use;
19200 /* Clear stack slot assignments remembered from previous functions.
19201 This is called from INIT_EXPANDERS once before RTL is emitted for each
19204 static struct machine_function *
19205 ix86_init_machine_status (void)
19207 struct machine_function *f;
19209 f = GGC_CNEW (struct machine_function);
19210 f->use_fast_prologue_epilogue_nregs = -1;
19211 f->tls_descriptor_call_expanded_p = 0;
19212 f->call_abi = ix86_abi;
19217 /* Return a MEM corresponding to a stack slot with mode MODE.
19218 Allocate a new slot if necessary.
19220 The RTL for a function can have several slots available: N is
19221 which slot to use. */
19224 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19226 struct stack_local_entry *s;
19228 gcc_assert (n < MAX_386_STACK_LOCALS);
19230 /* Virtual slot is valid only before vregs are instantiated. */
19231 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19233 for (s = ix86_stack_locals; s; s = s->next)
19234 if (s->mode == mode && s->n == n)
19235 return copy_rtx (s->rtl);
19237 s = (struct stack_local_entry *)
19238 ggc_alloc (sizeof (struct stack_local_entry));
19241 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19243 s->next = ix86_stack_locals;
19244 ix86_stack_locals = s;
19248 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19250 static GTY(()) rtx ix86_tls_symbol;
19252 ix86_tls_get_addr (void)
19255 if (!ix86_tls_symbol)
19257 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19258 (TARGET_ANY_GNU_TLS
19260 ? "___tls_get_addr"
19261 : "__tls_get_addr");
19264 return ix86_tls_symbol;
19267 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19269 static GTY(()) rtx ix86_tls_module_base_symbol;
19271 ix86_tls_module_base (void)
19274 if (!ix86_tls_module_base_symbol)
19276 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19277 "_TLS_MODULE_BASE_");
19278 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19279 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19282 return ix86_tls_module_base_symbol;
19285 /* Calculate the length of the memory address in the instruction
19286 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19289 memory_address_length (rtx addr)
19291 struct ix86_address parts;
19292 rtx base, index, disp;
19296 if (GET_CODE (addr) == PRE_DEC
19297 || GET_CODE (addr) == POST_INC
19298 || GET_CODE (addr) == PRE_MODIFY
19299 || GET_CODE (addr) == POST_MODIFY)
19302 ok = ix86_decompose_address (addr, &parts);
19305 if (parts.base && GET_CODE (parts.base) == SUBREG)
19306 parts.base = SUBREG_REG (parts.base);
19307 if (parts.index && GET_CODE (parts.index) == SUBREG)
19308 parts.index = SUBREG_REG (parts.index);
19311 index = parts.index;
19316 - esp as the base always wants an index,
19317 - ebp as the base always wants a displacement,
19318 - r12 as the base always wants an index,
19319 - r13 as the base always wants a displacement. */
19321 /* Register Indirect. */
19322 if (base && !index && !disp)
19324 /* esp (for its index) and ebp (for its displacement) need
19325 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19328 && (addr == arg_pointer_rtx
19329 || addr == frame_pointer_rtx
19330 || REGNO (addr) == SP_REG
19331 || REGNO (addr) == BP_REG
19332 || REGNO (addr) == R12_REG
19333 || REGNO (addr) == R13_REG))
19337 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19338 is not disp32, but disp32(%rip), so for disp32
19339 SIB byte is needed, unless print_operand_address
19340 optimizes it into disp32(%rip) or (%rip) is implied
19342 else if (disp && !base && !index)
19349 if (GET_CODE (disp) == CONST)
19350 symbol = XEXP (disp, 0);
19351 if (GET_CODE (symbol) == PLUS
19352 && CONST_INT_P (XEXP (symbol, 1)))
19353 symbol = XEXP (symbol, 0);
19355 if (GET_CODE (symbol) != LABEL_REF
19356 && (GET_CODE (symbol) != SYMBOL_REF
19357 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19358 && (GET_CODE (symbol) != UNSPEC
19359 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19360 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19367 /* Find the length of the displacement constant. */
19370 if (base && satisfies_constraint_K (disp))
19375 /* ebp always wants a displacement. Similarly r13. */
19376 else if (base && REG_P (base)
19377 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19380 /* An index requires the two-byte modrm form.... */
19382 /* ...like esp (or r12), which always wants an index. */
19383 || base == arg_pointer_rtx
19384 || base == frame_pointer_rtx
19385 || (base && REG_P (base)
19386 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19403 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19404 is set, expect that insn have 8bit immediate alternative. */
19406 ix86_attr_length_immediate_default (rtx insn, int shortform)
19410 extract_insn_cached (insn);
19411 for (i = recog_data.n_operands - 1; i >= 0; --i)
19412 if (CONSTANT_P (recog_data.operand[i]))
19414 enum attr_mode mode = get_attr_mode (insn);
19417 if (shortform && CONST_INT_P (recog_data.operand[i]))
19419 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19426 ival = trunc_int_for_mode (ival, HImode);
19429 ival = trunc_int_for_mode (ival, SImode);
19434 if (IN_RANGE (ival, -128, 127))
19451 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19456 fatal_insn ("unknown insn mode", insn);
19461 /* Compute default value for "length_address" attribute. */
19463 ix86_attr_length_address_default (rtx insn)
19467 if (get_attr_type (insn) == TYPE_LEA)
19469 rtx set = PATTERN (insn), addr;
19471 if (GET_CODE (set) == PARALLEL)
19472 set = XVECEXP (set, 0, 0);
19474 gcc_assert (GET_CODE (set) == SET);
19476 addr = SET_SRC (set);
19477 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19479 if (GET_CODE (addr) == ZERO_EXTEND)
19480 addr = XEXP (addr, 0);
19481 if (GET_CODE (addr) == SUBREG)
19482 addr = SUBREG_REG (addr);
19485 return memory_address_length (addr);
19488 extract_insn_cached (insn);
19489 for (i = recog_data.n_operands - 1; i >= 0; --i)
19490 if (MEM_P (recog_data.operand[i]))
19492 constrain_operands_cached (reload_completed);
19493 if (which_alternative != -1)
19495 const char *constraints = recog_data.constraints[i];
19496 int alt = which_alternative;
19498 while (*constraints == '=' || *constraints == '+')
19501 while (*constraints++ != ',')
19503 /* Skip ignored operands. */
19504 if (*constraints == 'X')
19507 return memory_address_length (XEXP (recog_data.operand[i], 0));
19512 /* Compute default value for "length_vex" attribute. It includes
19513 2 or 3 byte VEX prefix and 1 opcode byte. */
19516 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19521 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19522 byte VEX prefix. */
19523 if (!has_0f_opcode || has_vex_w)
19526 /* We can always use 2 byte VEX prefix in 32bit. */
19530 extract_insn_cached (insn);
19532 for (i = recog_data.n_operands - 1; i >= 0; --i)
19533 if (REG_P (recog_data.operand[i]))
19535 /* REX.W bit uses 3 byte VEX prefix. */
19536 if (GET_MODE (recog_data.operand[i]) == DImode
19537 && GENERAL_REG_P (recog_data.operand[i]))
19542 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19543 if (MEM_P (recog_data.operand[i])
19544 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19551 /* Return the maximum number of instructions a cpu can issue. */
19554 ix86_issue_rate (void)
19558 case PROCESSOR_PENTIUM:
19559 case PROCESSOR_ATOM:
19563 case PROCESSOR_PENTIUMPRO:
19564 case PROCESSOR_PENTIUM4:
19565 case PROCESSOR_ATHLON:
19567 case PROCESSOR_AMDFAM10:
19568 case PROCESSOR_NOCONA:
19569 case PROCESSOR_GENERIC32:
19570 case PROCESSOR_GENERIC64:
19573 case PROCESSOR_CORE2:
19581 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19582 by DEP_INSN and nothing set by DEP_INSN. */
19585 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19589 /* Simplify the test for uninteresting insns. */
19590 if (insn_type != TYPE_SETCC
19591 && insn_type != TYPE_ICMOV
19592 && insn_type != TYPE_FCMOV
19593 && insn_type != TYPE_IBR)
19596 if ((set = single_set (dep_insn)) != 0)
19598 set = SET_DEST (set);
19601 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19602 && XVECLEN (PATTERN (dep_insn), 0) == 2
19603 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19604 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19606 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19607 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19612 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19615 /* This test is true if the dependent insn reads the flags but
19616 not any other potentially set register. */
19617 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19620 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19626 /* Return true iff USE_INSN has a memory address with operands set by
19630 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19633 extract_insn_cached (use_insn);
19634 for (i = recog_data.n_operands - 1; i >= 0; --i)
19635 if (MEM_P (recog_data.operand[i]))
19637 rtx addr = XEXP (recog_data.operand[i], 0);
19638 return modified_in_p (addr, set_insn) != 0;
19644 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19646 enum attr_type insn_type, dep_insn_type;
19647 enum attr_memory memory;
19649 int dep_insn_code_number;
19651 /* Anti and output dependencies have zero cost on all CPUs. */
19652 if (REG_NOTE_KIND (link) != 0)
19655 dep_insn_code_number = recog_memoized (dep_insn);
19657 /* If we can't recognize the insns, we can't really do anything. */
19658 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19661 insn_type = get_attr_type (insn);
19662 dep_insn_type = get_attr_type (dep_insn);
19666 case PROCESSOR_PENTIUM:
19667 /* Address Generation Interlock adds a cycle of latency. */
19668 if (insn_type == TYPE_LEA)
19670 rtx addr = PATTERN (insn);
19672 if (GET_CODE (addr) == PARALLEL)
19673 addr = XVECEXP (addr, 0, 0);
19675 gcc_assert (GET_CODE (addr) == SET);
19677 addr = SET_SRC (addr);
19678 if (modified_in_p (addr, dep_insn))
19681 else if (ix86_agi_dependent (dep_insn, insn))
19684 /* ??? Compares pair with jump/setcc. */
19685 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19688 /* Floating point stores require value to be ready one cycle earlier. */
19689 if (insn_type == TYPE_FMOV
19690 && get_attr_memory (insn) == MEMORY_STORE
19691 && !ix86_agi_dependent (dep_insn, insn))
19695 case PROCESSOR_PENTIUMPRO:
19696 memory = get_attr_memory (insn);
19698 /* INT->FP conversion is expensive. */
19699 if (get_attr_fp_int_src (dep_insn))
19702 /* There is one cycle extra latency between an FP op and a store. */
19703 if (insn_type == TYPE_FMOV
19704 && (set = single_set (dep_insn)) != NULL_RTX
19705 && (set2 = single_set (insn)) != NULL_RTX
19706 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19707 && MEM_P (SET_DEST (set2)))
19710 /* Show ability of reorder buffer to hide latency of load by executing
19711 in parallel with previous instruction in case
19712 previous instruction is not needed to compute the address. */
19713 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19714 && !ix86_agi_dependent (dep_insn, insn))
19716 /* Claim moves to take one cycle, as core can issue one load
19717 at time and the next load can start cycle later. */
19718 if (dep_insn_type == TYPE_IMOV
19719 || dep_insn_type == TYPE_FMOV)
19727 memory = get_attr_memory (insn);
19729 /* The esp dependency is resolved before the instruction is really
19731 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19732 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19735 /* INT->FP conversion is expensive. */
19736 if (get_attr_fp_int_src (dep_insn))
19739 /* Show ability of reorder buffer to hide latency of load by executing
19740 in parallel with previous instruction in case
19741 previous instruction is not needed to compute the address. */
19742 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19743 && !ix86_agi_dependent (dep_insn, insn))
19745 /* Claim moves to take one cycle, as core can issue one load
19746 at time and the next load can start cycle later. */
19747 if (dep_insn_type == TYPE_IMOV
19748 || dep_insn_type == TYPE_FMOV)
19757 case PROCESSOR_ATHLON:
19759 case PROCESSOR_AMDFAM10:
19760 case PROCESSOR_ATOM:
19761 case PROCESSOR_GENERIC32:
19762 case PROCESSOR_GENERIC64:
19763 memory = get_attr_memory (insn);
19765 /* Show ability of reorder buffer to hide latency of load by executing
19766 in parallel with previous instruction in case
19767 previous instruction is not needed to compute the address. */
19768 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19769 && !ix86_agi_dependent (dep_insn, insn))
19771 enum attr_unit unit = get_attr_unit (insn);
19774 /* Because of the difference between the length of integer and
19775 floating unit pipeline preparation stages, the memory operands
19776 for floating point are cheaper.
19778 ??? For Athlon it the difference is most probably 2. */
19779 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19782 loadcost = TARGET_ATHLON ? 2 : 0;
19784 if (cost >= loadcost)
19797 /* How many alternative schedules to try. This should be as wide as the
19798 scheduling freedom in the DFA, but no wider. Making this value too
19799 large results extra work for the scheduler. */
19802 ia32_multipass_dfa_lookahead (void)
19806 case PROCESSOR_PENTIUM:
19809 case PROCESSOR_PENTIUMPRO:
19819 /* Compute the alignment given to a constant that is being placed in memory.
19820 EXP is the constant and ALIGN is the alignment that the object would
19822 The value of this function is used instead of that alignment to align
19826 ix86_constant_alignment (tree exp, int align)
19828 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19829 || TREE_CODE (exp) == INTEGER_CST)
19831 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19833 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19836 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19837 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19838 return BITS_PER_WORD;
19843 /* Compute the alignment for a static variable.
19844 TYPE is the data type, and ALIGN is the alignment that
19845 the object would ordinarily have. The value of this function is used
19846 instead of that alignment to align the object. */
19849 ix86_data_alignment (tree type, int align)
19851 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19853 if (AGGREGATE_TYPE_P (type)
19854 && TYPE_SIZE (type)
19855 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19856 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19857 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19858 && align < max_align)
19861 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19862 to 16byte boundary. */
19865 if (AGGREGATE_TYPE_P (type)
19866 && TYPE_SIZE (type)
19867 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19868 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19869 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19873 if (TREE_CODE (type) == ARRAY_TYPE)
19875 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19877 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19880 else if (TREE_CODE (type) == COMPLEX_TYPE)
19883 if (TYPE_MODE (type) == DCmode && align < 64)
19885 if ((TYPE_MODE (type) == XCmode
19886 || TYPE_MODE (type) == TCmode) && align < 128)
19889 else if ((TREE_CODE (type) == RECORD_TYPE
19890 || TREE_CODE (type) == UNION_TYPE
19891 || TREE_CODE (type) == QUAL_UNION_TYPE)
19892 && TYPE_FIELDS (type))
19894 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19896 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19899 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19900 || TREE_CODE (type) == INTEGER_TYPE)
19902 if (TYPE_MODE (type) == DFmode && align < 64)
19904 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19911 /* Compute the alignment for a local variable or a stack slot. EXP is
19912 the data type or decl itself, MODE is the widest mode available and
19913 ALIGN is the alignment that the object would ordinarily have. The
19914 value of this macro is used instead of that alignment to align the
19918 ix86_local_alignment (tree exp, enum machine_mode mode,
19919 unsigned int align)
19923 if (exp && DECL_P (exp))
19925 type = TREE_TYPE (exp);
19934 /* Don't do dynamic stack realignment for long long objects with
19935 -mpreferred-stack-boundary=2. */
19938 && ix86_preferred_stack_boundary < 64
19939 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19940 && (!type || !TYPE_USER_ALIGN (type))
19941 && (!decl || !DECL_USER_ALIGN (decl)))
19944 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19945 register in MODE. We will return the largest alignment of XF
19949 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19950 align = GET_MODE_ALIGNMENT (DFmode);
19954 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19955 to 16byte boundary. */
19958 if (AGGREGATE_TYPE_P (type)
19959 && TYPE_SIZE (type)
19960 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19961 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19962 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19965 if (TREE_CODE (type) == ARRAY_TYPE)
19967 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19969 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19972 else if (TREE_CODE (type) == COMPLEX_TYPE)
19974 if (TYPE_MODE (type) == DCmode && align < 64)
19976 if ((TYPE_MODE (type) == XCmode
19977 || TYPE_MODE (type) == TCmode) && align < 128)
19980 else if ((TREE_CODE (type) == RECORD_TYPE
19981 || TREE_CODE (type) == UNION_TYPE
19982 || TREE_CODE (type) == QUAL_UNION_TYPE)
19983 && TYPE_FIELDS (type))
19985 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19987 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19990 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19991 || TREE_CODE (type) == INTEGER_TYPE)
19994 if (TYPE_MODE (type) == DFmode && align < 64)
19996 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
20002 /* Compute the minimum required alignment for dynamic stack realignment
20003 purposes for a local variable, parameter or a stack slot. EXP is
20004 the data type or decl itself, MODE is its mode and ALIGN is the
20005 alignment that the object would ordinarily have. */
20008 ix86_minimum_alignment (tree exp, enum machine_mode mode,
20009 unsigned int align)
20013 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
20016 if (exp && DECL_P (exp))
20018 type = TREE_TYPE (exp);
20027 /* Don't do dynamic stack realignment for long long objects with
20028 -mpreferred-stack-boundary=2. */
20029 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
20030 && (!type || !TYPE_USER_ALIGN (type))
20031 && (!decl || !DECL_USER_ALIGN (decl)))
20037 /* Find a location for the static chain incoming to a nested function.
20038 This is a register, unless all free registers are used by arguments. */
20041 ix86_static_chain (const_tree fndecl, bool incoming_p)
20045 if (!DECL_STATIC_CHAIN (fndecl))
20050 /* We always use R10 in 64-bit mode. */
20056 /* By default in 32-bit mode we use ECX to pass the static chain. */
20059 fntype = TREE_TYPE (fndecl);
20060 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
20062 /* Fastcall functions use ecx/edx for arguments, which leaves
20063 us with EAX for the static chain. */
20066 else if (ix86_function_regparm (fntype, fndecl) == 3)
20068 /* For regparm 3, we have no free call-clobbered registers in
20069 which to store the static chain. In order to implement this,
20070 we have the trampoline push the static chain to the stack.
20071 However, we can't push a value below the return address when
20072 we call the nested function directly, so we have to use an
20073 alternate entry point. For this we use ESI, and have the
20074 alternate entry point push ESI, so that things appear the
20075 same once we're executing the nested function. */
20078 if (fndecl == current_function_decl)
20079 ix86_static_chain_on_stack = true;
20080 return gen_frame_mem (SImode,
20081 plus_constant (arg_pointer_rtx, -8));
20087 return gen_rtx_REG (Pmode, regno);
20090 /* Emit RTL insns to initialize the variable parts of a trampoline.
20091 FNDECL is the decl of the target address; M_TRAMP is a MEM for
20092 the trampoline, and CHAIN_VALUE is an RTX for the static chain
20093 to be passed to the target function. */
20096 ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
20100 fnaddr = XEXP (DECL_RTL (fndecl), 0);
20107 /* Depending on the static chain location, either load a register
20108 with a constant, or push the constant to the stack. All of the
20109 instructions are the same size. */
20110 chain = ix86_static_chain (fndecl, true);
20113 if (REGNO (chain) == CX_REG)
20115 else if (REGNO (chain) == AX_REG)
20118 gcc_unreachable ();
20123 mem = adjust_address (m_tramp, QImode, 0);
20124 emit_move_insn (mem, gen_int_mode (opcode, QImode));
20126 mem = adjust_address (m_tramp, SImode, 1);
20127 emit_move_insn (mem, chain_value);
20129 /* Compute offset from the end of the jmp to the target function.
20130 In the case in which the trampoline stores the static chain on
20131 the stack, we need to skip the first insn which pushes the
20132 (call-saved) register static chain; this push is 1 byte. */
20133 disp = expand_binop (SImode, sub_optab, fnaddr,
20134 plus_constant (XEXP (m_tramp, 0),
20135 MEM_P (chain) ? 9 : 10),
20136 NULL_RTX, 1, OPTAB_DIRECT);
20138 mem = adjust_address (m_tramp, QImode, 5);
20139 emit_move_insn (mem, gen_int_mode (0xe9, QImode));
20141 mem = adjust_address (m_tramp, SImode, 6);
20142 emit_move_insn (mem, disp);
20148 /* Load the function address to r11. Try to load address using
20149 the shorter movl instead of movabs. We may want to support
20150 movq for kernel mode, but kernel does not use trampolines at
20152 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
20154 fnaddr = copy_to_mode_reg (DImode, fnaddr);
20156 mem = adjust_address (m_tramp, HImode, offset);
20157 emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
20159 mem = adjust_address (m_tramp, SImode, offset + 2);
20160 emit_move_insn (mem, gen_lowpart (SImode, fnaddr));
20165 mem = adjust_address (m_tramp, HImode, offset);
20166 emit_move_insn (mem, gen_int_mode (0xbb49, HImode));
20168 mem = adjust_address (m_tramp, DImode, offset + 2);
20169 emit_move_insn (mem, fnaddr);
20173 /* Load static chain using movabs to r10. */
20174 mem = adjust_address (m_tramp, HImode, offset);
20175 emit_move_insn (mem, gen_int_mode (0xba49, HImode));
20177 mem = adjust_address (m_tramp, DImode, offset + 2);
20178 emit_move_insn (mem, chain_value);
20181 /* Jump to r11; the last (unused) byte is a nop, only there to
20182 pad the write out to a single 32-bit store. */
20183 mem = adjust_address (m_tramp, SImode, offset);
20184 emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
20187 gcc_assert (offset <= TRAMPOLINE_SIZE);
20190 #ifdef ENABLE_EXECUTE_STACK
20191 #ifdef CHECK_EXECUTE_STACK_ENABLED
20192 if (CHECK_EXECUTE_STACK_ENABLED)
20194 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
20195 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
20199 /* Codes for all the SSE/MMX builtins. */
20202 IX86_BUILTIN_ADDPS,
20203 IX86_BUILTIN_ADDSS,
20204 IX86_BUILTIN_DIVPS,
20205 IX86_BUILTIN_DIVSS,
20206 IX86_BUILTIN_MULPS,
20207 IX86_BUILTIN_MULSS,
20208 IX86_BUILTIN_SUBPS,
20209 IX86_BUILTIN_SUBSS,
20211 IX86_BUILTIN_CMPEQPS,
20212 IX86_BUILTIN_CMPLTPS,
20213 IX86_BUILTIN_CMPLEPS,
20214 IX86_BUILTIN_CMPGTPS,
20215 IX86_BUILTIN_CMPGEPS,
20216 IX86_BUILTIN_CMPNEQPS,
20217 IX86_BUILTIN_CMPNLTPS,
20218 IX86_BUILTIN_CMPNLEPS,
20219 IX86_BUILTIN_CMPNGTPS,
20220 IX86_BUILTIN_CMPNGEPS,
20221 IX86_BUILTIN_CMPORDPS,
20222 IX86_BUILTIN_CMPUNORDPS,
20223 IX86_BUILTIN_CMPEQSS,
20224 IX86_BUILTIN_CMPLTSS,
20225 IX86_BUILTIN_CMPLESS,
20226 IX86_BUILTIN_CMPNEQSS,
20227 IX86_BUILTIN_CMPNLTSS,
20228 IX86_BUILTIN_CMPNLESS,
20229 IX86_BUILTIN_CMPNGTSS,
20230 IX86_BUILTIN_CMPNGESS,
20231 IX86_BUILTIN_CMPORDSS,
20232 IX86_BUILTIN_CMPUNORDSS,
20234 IX86_BUILTIN_COMIEQSS,
20235 IX86_BUILTIN_COMILTSS,
20236 IX86_BUILTIN_COMILESS,
20237 IX86_BUILTIN_COMIGTSS,
20238 IX86_BUILTIN_COMIGESS,
20239 IX86_BUILTIN_COMINEQSS,
20240 IX86_BUILTIN_UCOMIEQSS,
20241 IX86_BUILTIN_UCOMILTSS,
20242 IX86_BUILTIN_UCOMILESS,
20243 IX86_BUILTIN_UCOMIGTSS,
20244 IX86_BUILTIN_UCOMIGESS,
20245 IX86_BUILTIN_UCOMINEQSS,
20247 IX86_BUILTIN_CVTPI2PS,
20248 IX86_BUILTIN_CVTPS2PI,
20249 IX86_BUILTIN_CVTSI2SS,
20250 IX86_BUILTIN_CVTSI642SS,
20251 IX86_BUILTIN_CVTSS2SI,
20252 IX86_BUILTIN_CVTSS2SI64,
20253 IX86_BUILTIN_CVTTPS2PI,
20254 IX86_BUILTIN_CVTTSS2SI,
20255 IX86_BUILTIN_CVTTSS2SI64,
20257 IX86_BUILTIN_MAXPS,
20258 IX86_BUILTIN_MAXSS,
20259 IX86_BUILTIN_MINPS,
20260 IX86_BUILTIN_MINSS,
20262 IX86_BUILTIN_LOADUPS,
20263 IX86_BUILTIN_STOREUPS,
20264 IX86_BUILTIN_MOVSS,
20266 IX86_BUILTIN_MOVHLPS,
20267 IX86_BUILTIN_MOVLHPS,
20268 IX86_BUILTIN_LOADHPS,
20269 IX86_BUILTIN_LOADLPS,
20270 IX86_BUILTIN_STOREHPS,
20271 IX86_BUILTIN_STORELPS,
20273 IX86_BUILTIN_MASKMOVQ,
20274 IX86_BUILTIN_MOVMSKPS,
20275 IX86_BUILTIN_PMOVMSKB,
20277 IX86_BUILTIN_MOVNTPS,
20278 IX86_BUILTIN_MOVNTQ,
20280 IX86_BUILTIN_LOADDQU,
20281 IX86_BUILTIN_STOREDQU,
20283 IX86_BUILTIN_PACKSSWB,
20284 IX86_BUILTIN_PACKSSDW,
20285 IX86_BUILTIN_PACKUSWB,
20287 IX86_BUILTIN_PADDB,
20288 IX86_BUILTIN_PADDW,
20289 IX86_BUILTIN_PADDD,
20290 IX86_BUILTIN_PADDQ,
20291 IX86_BUILTIN_PADDSB,
20292 IX86_BUILTIN_PADDSW,
20293 IX86_BUILTIN_PADDUSB,
20294 IX86_BUILTIN_PADDUSW,
20295 IX86_BUILTIN_PSUBB,
20296 IX86_BUILTIN_PSUBW,
20297 IX86_BUILTIN_PSUBD,
20298 IX86_BUILTIN_PSUBQ,
20299 IX86_BUILTIN_PSUBSB,
20300 IX86_BUILTIN_PSUBSW,
20301 IX86_BUILTIN_PSUBUSB,
20302 IX86_BUILTIN_PSUBUSW,
20305 IX86_BUILTIN_PANDN,
20309 IX86_BUILTIN_PAVGB,
20310 IX86_BUILTIN_PAVGW,
20312 IX86_BUILTIN_PCMPEQB,
20313 IX86_BUILTIN_PCMPEQW,
20314 IX86_BUILTIN_PCMPEQD,
20315 IX86_BUILTIN_PCMPGTB,
20316 IX86_BUILTIN_PCMPGTW,
20317 IX86_BUILTIN_PCMPGTD,
20319 IX86_BUILTIN_PMADDWD,
20321 IX86_BUILTIN_PMAXSW,
20322 IX86_BUILTIN_PMAXUB,
20323 IX86_BUILTIN_PMINSW,
20324 IX86_BUILTIN_PMINUB,
20326 IX86_BUILTIN_PMULHUW,
20327 IX86_BUILTIN_PMULHW,
20328 IX86_BUILTIN_PMULLW,
20330 IX86_BUILTIN_PSADBW,
20331 IX86_BUILTIN_PSHUFW,
20333 IX86_BUILTIN_PSLLW,
20334 IX86_BUILTIN_PSLLD,
20335 IX86_BUILTIN_PSLLQ,
20336 IX86_BUILTIN_PSRAW,
20337 IX86_BUILTIN_PSRAD,
20338 IX86_BUILTIN_PSRLW,
20339 IX86_BUILTIN_PSRLD,
20340 IX86_BUILTIN_PSRLQ,
20341 IX86_BUILTIN_PSLLWI,
20342 IX86_BUILTIN_PSLLDI,
20343 IX86_BUILTIN_PSLLQI,
20344 IX86_BUILTIN_PSRAWI,
20345 IX86_BUILTIN_PSRADI,
20346 IX86_BUILTIN_PSRLWI,
20347 IX86_BUILTIN_PSRLDI,
20348 IX86_BUILTIN_PSRLQI,
20350 IX86_BUILTIN_PUNPCKHBW,
20351 IX86_BUILTIN_PUNPCKHWD,
20352 IX86_BUILTIN_PUNPCKHDQ,
20353 IX86_BUILTIN_PUNPCKLBW,
20354 IX86_BUILTIN_PUNPCKLWD,
20355 IX86_BUILTIN_PUNPCKLDQ,
20357 IX86_BUILTIN_SHUFPS,
20359 IX86_BUILTIN_RCPPS,
20360 IX86_BUILTIN_RCPSS,
20361 IX86_BUILTIN_RSQRTPS,
20362 IX86_BUILTIN_RSQRTPS_NR,
20363 IX86_BUILTIN_RSQRTSS,
20364 IX86_BUILTIN_RSQRTF,
20365 IX86_BUILTIN_SQRTPS,
20366 IX86_BUILTIN_SQRTPS_NR,
20367 IX86_BUILTIN_SQRTSS,
20369 IX86_BUILTIN_UNPCKHPS,
20370 IX86_BUILTIN_UNPCKLPS,
20372 IX86_BUILTIN_ANDPS,
20373 IX86_BUILTIN_ANDNPS,
20375 IX86_BUILTIN_XORPS,
20378 IX86_BUILTIN_LDMXCSR,
20379 IX86_BUILTIN_STMXCSR,
20380 IX86_BUILTIN_SFENCE,
20382 /* 3DNow! Original */
20383 IX86_BUILTIN_FEMMS,
20384 IX86_BUILTIN_PAVGUSB,
20385 IX86_BUILTIN_PF2ID,
20386 IX86_BUILTIN_PFACC,
20387 IX86_BUILTIN_PFADD,
20388 IX86_BUILTIN_PFCMPEQ,
20389 IX86_BUILTIN_PFCMPGE,
20390 IX86_BUILTIN_PFCMPGT,
20391 IX86_BUILTIN_PFMAX,
20392 IX86_BUILTIN_PFMIN,
20393 IX86_BUILTIN_PFMUL,
20394 IX86_BUILTIN_PFRCP,
20395 IX86_BUILTIN_PFRCPIT1,
20396 IX86_BUILTIN_PFRCPIT2,
20397 IX86_BUILTIN_PFRSQIT1,
20398 IX86_BUILTIN_PFRSQRT,
20399 IX86_BUILTIN_PFSUB,
20400 IX86_BUILTIN_PFSUBR,
20401 IX86_BUILTIN_PI2FD,
20402 IX86_BUILTIN_PMULHRW,
20404 /* 3DNow! Athlon Extensions */
20405 IX86_BUILTIN_PF2IW,
20406 IX86_BUILTIN_PFNACC,
20407 IX86_BUILTIN_PFPNACC,
20408 IX86_BUILTIN_PI2FW,
20409 IX86_BUILTIN_PSWAPDSI,
20410 IX86_BUILTIN_PSWAPDSF,
20413 IX86_BUILTIN_ADDPD,
20414 IX86_BUILTIN_ADDSD,
20415 IX86_BUILTIN_DIVPD,
20416 IX86_BUILTIN_DIVSD,
20417 IX86_BUILTIN_MULPD,
20418 IX86_BUILTIN_MULSD,
20419 IX86_BUILTIN_SUBPD,
20420 IX86_BUILTIN_SUBSD,
20422 IX86_BUILTIN_CMPEQPD,
20423 IX86_BUILTIN_CMPLTPD,
20424 IX86_BUILTIN_CMPLEPD,
20425 IX86_BUILTIN_CMPGTPD,
20426 IX86_BUILTIN_CMPGEPD,
20427 IX86_BUILTIN_CMPNEQPD,
20428 IX86_BUILTIN_CMPNLTPD,
20429 IX86_BUILTIN_CMPNLEPD,
20430 IX86_BUILTIN_CMPNGTPD,
20431 IX86_BUILTIN_CMPNGEPD,
20432 IX86_BUILTIN_CMPORDPD,
20433 IX86_BUILTIN_CMPUNORDPD,
20434 IX86_BUILTIN_CMPEQSD,
20435 IX86_BUILTIN_CMPLTSD,
20436 IX86_BUILTIN_CMPLESD,
20437 IX86_BUILTIN_CMPNEQSD,
20438 IX86_BUILTIN_CMPNLTSD,
20439 IX86_BUILTIN_CMPNLESD,
20440 IX86_BUILTIN_CMPORDSD,
20441 IX86_BUILTIN_CMPUNORDSD,
20443 IX86_BUILTIN_COMIEQSD,
20444 IX86_BUILTIN_COMILTSD,
20445 IX86_BUILTIN_COMILESD,
20446 IX86_BUILTIN_COMIGTSD,
20447 IX86_BUILTIN_COMIGESD,
20448 IX86_BUILTIN_COMINEQSD,
20449 IX86_BUILTIN_UCOMIEQSD,
20450 IX86_BUILTIN_UCOMILTSD,
20451 IX86_BUILTIN_UCOMILESD,
20452 IX86_BUILTIN_UCOMIGTSD,
20453 IX86_BUILTIN_UCOMIGESD,
20454 IX86_BUILTIN_UCOMINEQSD,
20456 IX86_BUILTIN_MAXPD,
20457 IX86_BUILTIN_MAXSD,
20458 IX86_BUILTIN_MINPD,
20459 IX86_BUILTIN_MINSD,
20461 IX86_BUILTIN_ANDPD,
20462 IX86_BUILTIN_ANDNPD,
20464 IX86_BUILTIN_XORPD,
20466 IX86_BUILTIN_SQRTPD,
20467 IX86_BUILTIN_SQRTSD,
20469 IX86_BUILTIN_UNPCKHPD,
20470 IX86_BUILTIN_UNPCKLPD,
20472 IX86_BUILTIN_SHUFPD,
20474 IX86_BUILTIN_LOADUPD,
20475 IX86_BUILTIN_STOREUPD,
20476 IX86_BUILTIN_MOVSD,
20478 IX86_BUILTIN_LOADHPD,
20479 IX86_BUILTIN_LOADLPD,
20481 IX86_BUILTIN_CVTDQ2PD,
20482 IX86_BUILTIN_CVTDQ2PS,
20484 IX86_BUILTIN_CVTPD2DQ,
20485 IX86_BUILTIN_CVTPD2PI,
20486 IX86_BUILTIN_CVTPD2PS,
20487 IX86_BUILTIN_CVTTPD2DQ,
20488 IX86_BUILTIN_CVTTPD2PI,
20490 IX86_BUILTIN_CVTPI2PD,
20491 IX86_BUILTIN_CVTSI2SD,
20492 IX86_BUILTIN_CVTSI642SD,
20494 IX86_BUILTIN_CVTSD2SI,
20495 IX86_BUILTIN_CVTSD2SI64,
20496 IX86_BUILTIN_CVTSD2SS,
20497 IX86_BUILTIN_CVTSS2SD,
20498 IX86_BUILTIN_CVTTSD2SI,
20499 IX86_BUILTIN_CVTTSD2SI64,
20501 IX86_BUILTIN_CVTPS2DQ,
20502 IX86_BUILTIN_CVTPS2PD,
20503 IX86_BUILTIN_CVTTPS2DQ,
20505 IX86_BUILTIN_MOVNTI,
20506 IX86_BUILTIN_MOVNTPD,
20507 IX86_BUILTIN_MOVNTDQ,
20509 IX86_BUILTIN_MOVQ128,
20512 IX86_BUILTIN_MASKMOVDQU,
20513 IX86_BUILTIN_MOVMSKPD,
20514 IX86_BUILTIN_PMOVMSKB128,
20516 IX86_BUILTIN_PACKSSWB128,
20517 IX86_BUILTIN_PACKSSDW128,
20518 IX86_BUILTIN_PACKUSWB128,
20520 IX86_BUILTIN_PADDB128,
20521 IX86_BUILTIN_PADDW128,
20522 IX86_BUILTIN_PADDD128,
20523 IX86_BUILTIN_PADDQ128,
20524 IX86_BUILTIN_PADDSB128,
20525 IX86_BUILTIN_PADDSW128,
20526 IX86_BUILTIN_PADDUSB128,
20527 IX86_BUILTIN_PADDUSW128,
20528 IX86_BUILTIN_PSUBB128,
20529 IX86_BUILTIN_PSUBW128,
20530 IX86_BUILTIN_PSUBD128,
20531 IX86_BUILTIN_PSUBQ128,
20532 IX86_BUILTIN_PSUBSB128,
20533 IX86_BUILTIN_PSUBSW128,
20534 IX86_BUILTIN_PSUBUSB128,
20535 IX86_BUILTIN_PSUBUSW128,
20537 IX86_BUILTIN_PAND128,
20538 IX86_BUILTIN_PANDN128,
20539 IX86_BUILTIN_POR128,
20540 IX86_BUILTIN_PXOR128,
20542 IX86_BUILTIN_PAVGB128,
20543 IX86_BUILTIN_PAVGW128,
20545 IX86_BUILTIN_PCMPEQB128,
20546 IX86_BUILTIN_PCMPEQW128,
20547 IX86_BUILTIN_PCMPEQD128,
20548 IX86_BUILTIN_PCMPGTB128,
20549 IX86_BUILTIN_PCMPGTW128,
20550 IX86_BUILTIN_PCMPGTD128,
20552 IX86_BUILTIN_PMADDWD128,
20554 IX86_BUILTIN_PMAXSW128,
20555 IX86_BUILTIN_PMAXUB128,
20556 IX86_BUILTIN_PMINSW128,
20557 IX86_BUILTIN_PMINUB128,
20559 IX86_BUILTIN_PMULUDQ,
20560 IX86_BUILTIN_PMULUDQ128,
20561 IX86_BUILTIN_PMULHUW128,
20562 IX86_BUILTIN_PMULHW128,
20563 IX86_BUILTIN_PMULLW128,
20565 IX86_BUILTIN_PSADBW128,
20566 IX86_BUILTIN_PSHUFHW,
20567 IX86_BUILTIN_PSHUFLW,
20568 IX86_BUILTIN_PSHUFD,
20570 IX86_BUILTIN_PSLLDQI128,
20571 IX86_BUILTIN_PSLLWI128,
20572 IX86_BUILTIN_PSLLDI128,
20573 IX86_BUILTIN_PSLLQI128,
20574 IX86_BUILTIN_PSRAWI128,
20575 IX86_BUILTIN_PSRADI128,
20576 IX86_BUILTIN_PSRLDQI128,
20577 IX86_BUILTIN_PSRLWI128,
20578 IX86_BUILTIN_PSRLDI128,
20579 IX86_BUILTIN_PSRLQI128,
20581 IX86_BUILTIN_PSLLDQ128,
20582 IX86_BUILTIN_PSLLW128,
20583 IX86_BUILTIN_PSLLD128,
20584 IX86_BUILTIN_PSLLQ128,
20585 IX86_BUILTIN_PSRAW128,
20586 IX86_BUILTIN_PSRAD128,
20587 IX86_BUILTIN_PSRLW128,
20588 IX86_BUILTIN_PSRLD128,
20589 IX86_BUILTIN_PSRLQ128,
20591 IX86_BUILTIN_PUNPCKHBW128,
20592 IX86_BUILTIN_PUNPCKHWD128,
20593 IX86_BUILTIN_PUNPCKHDQ128,
20594 IX86_BUILTIN_PUNPCKHQDQ128,
20595 IX86_BUILTIN_PUNPCKLBW128,
20596 IX86_BUILTIN_PUNPCKLWD128,
20597 IX86_BUILTIN_PUNPCKLDQ128,
20598 IX86_BUILTIN_PUNPCKLQDQ128,
20600 IX86_BUILTIN_CLFLUSH,
20601 IX86_BUILTIN_MFENCE,
20602 IX86_BUILTIN_LFENCE,
20604 IX86_BUILTIN_BSRSI,
20605 IX86_BUILTIN_BSRDI,
20606 IX86_BUILTIN_RDPMC,
20607 IX86_BUILTIN_RDTSC,
20608 IX86_BUILTIN_RDTSCP,
20609 IX86_BUILTIN_ROLQI,
20610 IX86_BUILTIN_ROLHI,
20611 IX86_BUILTIN_RORQI,
20612 IX86_BUILTIN_RORHI,
20615 IX86_BUILTIN_ADDSUBPS,
20616 IX86_BUILTIN_HADDPS,
20617 IX86_BUILTIN_HSUBPS,
20618 IX86_BUILTIN_MOVSHDUP,
20619 IX86_BUILTIN_MOVSLDUP,
20620 IX86_BUILTIN_ADDSUBPD,
20621 IX86_BUILTIN_HADDPD,
20622 IX86_BUILTIN_HSUBPD,
20623 IX86_BUILTIN_LDDQU,
20625 IX86_BUILTIN_MONITOR,
20626 IX86_BUILTIN_MWAIT,
20629 IX86_BUILTIN_PHADDW,
20630 IX86_BUILTIN_PHADDD,
20631 IX86_BUILTIN_PHADDSW,
20632 IX86_BUILTIN_PHSUBW,
20633 IX86_BUILTIN_PHSUBD,
20634 IX86_BUILTIN_PHSUBSW,
20635 IX86_BUILTIN_PMADDUBSW,
20636 IX86_BUILTIN_PMULHRSW,
20637 IX86_BUILTIN_PSHUFB,
20638 IX86_BUILTIN_PSIGNB,
20639 IX86_BUILTIN_PSIGNW,
20640 IX86_BUILTIN_PSIGND,
20641 IX86_BUILTIN_PALIGNR,
20642 IX86_BUILTIN_PABSB,
20643 IX86_BUILTIN_PABSW,
20644 IX86_BUILTIN_PABSD,
20646 IX86_BUILTIN_PHADDW128,
20647 IX86_BUILTIN_PHADDD128,
20648 IX86_BUILTIN_PHADDSW128,
20649 IX86_BUILTIN_PHSUBW128,
20650 IX86_BUILTIN_PHSUBD128,
20651 IX86_BUILTIN_PHSUBSW128,
20652 IX86_BUILTIN_PMADDUBSW128,
20653 IX86_BUILTIN_PMULHRSW128,
20654 IX86_BUILTIN_PSHUFB128,
20655 IX86_BUILTIN_PSIGNB128,
20656 IX86_BUILTIN_PSIGNW128,
20657 IX86_BUILTIN_PSIGND128,
20658 IX86_BUILTIN_PALIGNR128,
20659 IX86_BUILTIN_PABSB128,
20660 IX86_BUILTIN_PABSW128,
20661 IX86_BUILTIN_PABSD128,
20663 /* AMDFAM10 - SSE4A New Instructions. */
20664 IX86_BUILTIN_MOVNTSD,
20665 IX86_BUILTIN_MOVNTSS,
20666 IX86_BUILTIN_EXTRQI,
20667 IX86_BUILTIN_EXTRQ,
20668 IX86_BUILTIN_INSERTQI,
20669 IX86_BUILTIN_INSERTQ,
20672 IX86_BUILTIN_BLENDPD,
20673 IX86_BUILTIN_BLENDPS,
20674 IX86_BUILTIN_BLENDVPD,
20675 IX86_BUILTIN_BLENDVPS,
20676 IX86_BUILTIN_PBLENDVB128,
20677 IX86_BUILTIN_PBLENDW128,
20682 IX86_BUILTIN_INSERTPS128,
20684 IX86_BUILTIN_MOVNTDQA,
20685 IX86_BUILTIN_MPSADBW128,
20686 IX86_BUILTIN_PACKUSDW128,
20687 IX86_BUILTIN_PCMPEQQ,
20688 IX86_BUILTIN_PHMINPOSUW128,
20690 IX86_BUILTIN_PMAXSB128,
20691 IX86_BUILTIN_PMAXSD128,
20692 IX86_BUILTIN_PMAXUD128,
20693 IX86_BUILTIN_PMAXUW128,
20695 IX86_BUILTIN_PMINSB128,
20696 IX86_BUILTIN_PMINSD128,
20697 IX86_BUILTIN_PMINUD128,
20698 IX86_BUILTIN_PMINUW128,
20700 IX86_BUILTIN_PMOVSXBW128,
20701 IX86_BUILTIN_PMOVSXBD128,
20702 IX86_BUILTIN_PMOVSXBQ128,
20703 IX86_BUILTIN_PMOVSXWD128,
20704 IX86_BUILTIN_PMOVSXWQ128,
20705 IX86_BUILTIN_PMOVSXDQ128,
20707 IX86_BUILTIN_PMOVZXBW128,
20708 IX86_BUILTIN_PMOVZXBD128,
20709 IX86_BUILTIN_PMOVZXBQ128,
20710 IX86_BUILTIN_PMOVZXWD128,
20711 IX86_BUILTIN_PMOVZXWQ128,
20712 IX86_BUILTIN_PMOVZXDQ128,
20714 IX86_BUILTIN_PMULDQ128,
20715 IX86_BUILTIN_PMULLD128,
20717 IX86_BUILTIN_ROUNDPD,
20718 IX86_BUILTIN_ROUNDPS,
20719 IX86_BUILTIN_ROUNDSD,
20720 IX86_BUILTIN_ROUNDSS,
20722 IX86_BUILTIN_PTESTZ,
20723 IX86_BUILTIN_PTESTC,
20724 IX86_BUILTIN_PTESTNZC,
20726 IX86_BUILTIN_VEC_INIT_V2SI,
20727 IX86_BUILTIN_VEC_INIT_V4HI,
20728 IX86_BUILTIN_VEC_INIT_V8QI,
20729 IX86_BUILTIN_VEC_EXT_V2DF,
20730 IX86_BUILTIN_VEC_EXT_V2DI,
20731 IX86_BUILTIN_VEC_EXT_V4SF,
20732 IX86_BUILTIN_VEC_EXT_V4SI,
20733 IX86_BUILTIN_VEC_EXT_V8HI,
20734 IX86_BUILTIN_VEC_EXT_V2SI,
20735 IX86_BUILTIN_VEC_EXT_V4HI,
20736 IX86_BUILTIN_VEC_EXT_V16QI,
20737 IX86_BUILTIN_VEC_SET_V2DI,
20738 IX86_BUILTIN_VEC_SET_V4SF,
20739 IX86_BUILTIN_VEC_SET_V4SI,
20740 IX86_BUILTIN_VEC_SET_V8HI,
20741 IX86_BUILTIN_VEC_SET_V4HI,
20742 IX86_BUILTIN_VEC_SET_V16QI,
20744 IX86_BUILTIN_VEC_PACK_SFIX,
20747 IX86_BUILTIN_CRC32QI,
20748 IX86_BUILTIN_CRC32HI,
20749 IX86_BUILTIN_CRC32SI,
20750 IX86_BUILTIN_CRC32DI,
20752 IX86_BUILTIN_PCMPESTRI128,
20753 IX86_BUILTIN_PCMPESTRM128,
20754 IX86_BUILTIN_PCMPESTRA128,
20755 IX86_BUILTIN_PCMPESTRC128,
20756 IX86_BUILTIN_PCMPESTRO128,
20757 IX86_BUILTIN_PCMPESTRS128,
20758 IX86_BUILTIN_PCMPESTRZ128,
20759 IX86_BUILTIN_PCMPISTRI128,
20760 IX86_BUILTIN_PCMPISTRM128,
20761 IX86_BUILTIN_PCMPISTRA128,
20762 IX86_BUILTIN_PCMPISTRC128,
20763 IX86_BUILTIN_PCMPISTRO128,
20764 IX86_BUILTIN_PCMPISTRS128,
20765 IX86_BUILTIN_PCMPISTRZ128,
20767 IX86_BUILTIN_PCMPGTQ,
20769 /* AES instructions */
20770 IX86_BUILTIN_AESENC128,
20771 IX86_BUILTIN_AESENCLAST128,
20772 IX86_BUILTIN_AESDEC128,
20773 IX86_BUILTIN_AESDECLAST128,
20774 IX86_BUILTIN_AESIMC128,
20775 IX86_BUILTIN_AESKEYGENASSIST128,
20777 /* PCLMUL instruction */
20778 IX86_BUILTIN_PCLMULQDQ128,
20781 IX86_BUILTIN_ADDPD256,
20782 IX86_BUILTIN_ADDPS256,
20783 IX86_BUILTIN_ADDSUBPD256,
20784 IX86_BUILTIN_ADDSUBPS256,
20785 IX86_BUILTIN_ANDPD256,
20786 IX86_BUILTIN_ANDPS256,
20787 IX86_BUILTIN_ANDNPD256,
20788 IX86_BUILTIN_ANDNPS256,
20789 IX86_BUILTIN_BLENDPD256,
20790 IX86_BUILTIN_BLENDPS256,
20791 IX86_BUILTIN_BLENDVPD256,
20792 IX86_BUILTIN_BLENDVPS256,
20793 IX86_BUILTIN_DIVPD256,
20794 IX86_BUILTIN_DIVPS256,
20795 IX86_BUILTIN_DPPS256,
20796 IX86_BUILTIN_HADDPD256,
20797 IX86_BUILTIN_HADDPS256,
20798 IX86_BUILTIN_HSUBPD256,
20799 IX86_BUILTIN_HSUBPS256,
20800 IX86_BUILTIN_MAXPD256,
20801 IX86_BUILTIN_MAXPS256,
20802 IX86_BUILTIN_MINPD256,
20803 IX86_BUILTIN_MINPS256,
20804 IX86_BUILTIN_MULPD256,
20805 IX86_BUILTIN_MULPS256,
20806 IX86_BUILTIN_ORPD256,
20807 IX86_BUILTIN_ORPS256,
20808 IX86_BUILTIN_SHUFPD256,
20809 IX86_BUILTIN_SHUFPS256,
20810 IX86_BUILTIN_SUBPD256,
20811 IX86_BUILTIN_SUBPS256,
20812 IX86_BUILTIN_XORPD256,
20813 IX86_BUILTIN_XORPS256,
20814 IX86_BUILTIN_CMPSD,
20815 IX86_BUILTIN_CMPSS,
20816 IX86_BUILTIN_CMPPD,
20817 IX86_BUILTIN_CMPPS,
20818 IX86_BUILTIN_CMPPD256,
20819 IX86_BUILTIN_CMPPS256,
20820 IX86_BUILTIN_CVTDQ2PD256,
20821 IX86_BUILTIN_CVTDQ2PS256,
20822 IX86_BUILTIN_CVTPD2PS256,
20823 IX86_BUILTIN_CVTPS2DQ256,
20824 IX86_BUILTIN_CVTPS2PD256,
20825 IX86_BUILTIN_CVTTPD2DQ256,
20826 IX86_BUILTIN_CVTPD2DQ256,
20827 IX86_BUILTIN_CVTTPS2DQ256,
20828 IX86_BUILTIN_EXTRACTF128PD256,
20829 IX86_BUILTIN_EXTRACTF128PS256,
20830 IX86_BUILTIN_EXTRACTF128SI256,
20831 IX86_BUILTIN_VZEROALL,
20832 IX86_BUILTIN_VZEROUPPER,
20833 IX86_BUILTIN_VZEROUPPER_REX64,
20834 IX86_BUILTIN_VPERMILVARPD,
20835 IX86_BUILTIN_VPERMILVARPS,
20836 IX86_BUILTIN_VPERMILVARPD256,
20837 IX86_BUILTIN_VPERMILVARPS256,
20838 IX86_BUILTIN_VPERMILPD,
20839 IX86_BUILTIN_VPERMILPS,
20840 IX86_BUILTIN_VPERMILPD256,
20841 IX86_BUILTIN_VPERMILPS256,
20842 IX86_BUILTIN_VPERM2F128PD256,
20843 IX86_BUILTIN_VPERM2F128PS256,
20844 IX86_BUILTIN_VPERM2F128SI256,
20845 IX86_BUILTIN_VBROADCASTSS,
20846 IX86_BUILTIN_VBROADCASTSD256,
20847 IX86_BUILTIN_VBROADCASTSS256,
20848 IX86_BUILTIN_VBROADCASTPD256,
20849 IX86_BUILTIN_VBROADCASTPS256,
20850 IX86_BUILTIN_VINSERTF128PD256,
20851 IX86_BUILTIN_VINSERTF128PS256,
20852 IX86_BUILTIN_VINSERTF128SI256,
20853 IX86_BUILTIN_LOADUPD256,
20854 IX86_BUILTIN_LOADUPS256,
20855 IX86_BUILTIN_STOREUPD256,
20856 IX86_BUILTIN_STOREUPS256,
20857 IX86_BUILTIN_LDDQU256,
20858 IX86_BUILTIN_MOVNTDQ256,
20859 IX86_BUILTIN_MOVNTPD256,
20860 IX86_BUILTIN_MOVNTPS256,
20861 IX86_BUILTIN_LOADDQU256,
20862 IX86_BUILTIN_STOREDQU256,
20863 IX86_BUILTIN_MASKLOADPD,
20864 IX86_BUILTIN_MASKLOADPS,
20865 IX86_BUILTIN_MASKSTOREPD,
20866 IX86_BUILTIN_MASKSTOREPS,
20867 IX86_BUILTIN_MASKLOADPD256,
20868 IX86_BUILTIN_MASKLOADPS256,
20869 IX86_BUILTIN_MASKSTOREPD256,
20870 IX86_BUILTIN_MASKSTOREPS256,
20871 IX86_BUILTIN_MOVSHDUP256,
20872 IX86_BUILTIN_MOVSLDUP256,
20873 IX86_BUILTIN_MOVDDUP256,
20875 IX86_BUILTIN_SQRTPD256,
20876 IX86_BUILTIN_SQRTPS256,
20877 IX86_BUILTIN_SQRTPS_NR256,
20878 IX86_BUILTIN_RSQRTPS256,
20879 IX86_BUILTIN_RSQRTPS_NR256,
20881 IX86_BUILTIN_RCPPS256,
20883 IX86_BUILTIN_ROUNDPD256,
20884 IX86_BUILTIN_ROUNDPS256,
20886 IX86_BUILTIN_UNPCKHPD256,
20887 IX86_BUILTIN_UNPCKLPD256,
20888 IX86_BUILTIN_UNPCKHPS256,
20889 IX86_BUILTIN_UNPCKLPS256,
20891 IX86_BUILTIN_SI256_SI,
20892 IX86_BUILTIN_PS256_PS,
20893 IX86_BUILTIN_PD256_PD,
20894 IX86_BUILTIN_SI_SI256,
20895 IX86_BUILTIN_PS_PS256,
20896 IX86_BUILTIN_PD_PD256,
20898 IX86_BUILTIN_VTESTZPD,
20899 IX86_BUILTIN_VTESTCPD,
20900 IX86_BUILTIN_VTESTNZCPD,
20901 IX86_BUILTIN_VTESTZPS,
20902 IX86_BUILTIN_VTESTCPS,
20903 IX86_BUILTIN_VTESTNZCPS,
20904 IX86_BUILTIN_VTESTZPD256,
20905 IX86_BUILTIN_VTESTCPD256,
20906 IX86_BUILTIN_VTESTNZCPD256,
20907 IX86_BUILTIN_VTESTZPS256,
20908 IX86_BUILTIN_VTESTCPS256,
20909 IX86_BUILTIN_VTESTNZCPS256,
20910 IX86_BUILTIN_PTESTZ256,
20911 IX86_BUILTIN_PTESTC256,
20912 IX86_BUILTIN_PTESTNZC256,
20914 IX86_BUILTIN_MOVMSKPD256,
20915 IX86_BUILTIN_MOVMSKPS256,
20917 /* TFmode support builtins. */
20919 IX86_BUILTIN_HUGE_VALQ,
20920 IX86_BUILTIN_FABSQ,
20921 IX86_BUILTIN_COPYSIGNQ,
20923 /* Vectorizer support builtins. */
20924 IX86_BUILTIN_CPYSGNPS,
20925 IX86_BUILTIN_CPYSGNPD,
20927 IX86_BUILTIN_CVTUDQ2PS,
20929 /* FMA4 and XOP instructions. */
20930 IX86_BUILTIN_VFMADDSS,
20931 IX86_BUILTIN_VFMADDSD,
20932 IX86_BUILTIN_VFMADDPS,
20933 IX86_BUILTIN_VFMADDPD,
20934 IX86_BUILTIN_VFMSUBSS,
20935 IX86_BUILTIN_VFMSUBSD,
20936 IX86_BUILTIN_VFMSUBPS,
20937 IX86_BUILTIN_VFMSUBPD,
20938 IX86_BUILTIN_VFMADDSUBPS,
20939 IX86_BUILTIN_VFMADDSUBPD,
20940 IX86_BUILTIN_VFMSUBADDPS,
20941 IX86_BUILTIN_VFMSUBADDPD,
20942 IX86_BUILTIN_VFNMADDSS,
20943 IX86_BUILTIN_VFNMADDSD,
20944 IX86_BUILTIN_VFNMADDPS,
20945 IX86_BUILTIN_VFNMADDPD,
20946 IX86_BUILTIN_VFNMSUBSS,
20947 IX86_BUILTIN_VFNMSUBSD,
20948 IX86_BUILTIN_VFNMSUBPS,
20949 IX86_BUILTIN_VFNMSUBPD,
20950 IX86_BUILTIN_VFMADDPS256,
20951 IX86_BUILTIN_VFMADDPD256,
20952 IX86_BUILTIN_VFMSUBPS256,
20953 IX86_BUILTIN_VFMSUBPD256,
20954 IX86_BUILTIN_VFMADDSUBPS256,
20955 IX86_BUILTIN_VFMADDSUBPD256,
20956 IX86_BUILTIN_VFMSUBADDPS256,
20957 IX86_BUILTIN_VFMSUBADDPD256,
20958 IX86_BUILTIN_VFNMADDPS256,
20959 IX86_BUILTIN_VFNMADDPD256,
20960 IX86_BUILTIN_VFNMSUBPS256,
20961 IX86_BUILTIN_VFNMSUBPD256,
20963 IX86_BUILTIN_VPCMOV,
20964 IX86_BUILTIN_VPCMOV_V2DI,
20965 IX86_BUILTIN_VPCMOV_V4SI,
20966 IX86_BUILTIN_VPCMOV_V8HI,
20967 IX86_BUILTIN_VPCMOV_V16QI,
20968 IX86_BUILTIN_VPCMOV_V4SF,
20969 IX86_BUILTIN_VPCMOV_V2DF,
20970 IX86_BUILTIN_VPCMOV256,
20971 IX86_BUILTIN_VPCMOV_V4DI256,
20972 IX86_BUILTIN_VPCMOV_V8SI256,
20973 IX86_BUILTIN_VPCMOV_V16HI256,
20974 IX86_BUILTIN_VPCMOV_V32QI256,
20975 IX86_BUILTIN_VPCMOV_V8SF256,
20976 IX86_BUILTIN_VPCMOV_V4DF256,
20978 IX86_BUILTIN_VPPERM,
20980 IX86_BUILTIN_VPMACSSWW,
20981 IX86_BUILTIN_VPMACSWW,
20982 IX86_BUILTIN_VPMACSSWD,
20983 IX86_BUILTIN_VPMACSWD,
20984 IX86_BUILTIN_VPMACSSDD,
20985 IX86_BUILTIN_VPMACSDD,
20986 IX86_BUILTIN_VPMACSSDQL,
20987 IX86_BUILTIN_VPMACSSDQH,
20988 IX86_BUILTIN_VPMACSDQL,
20989 IX86_BUILTIN_VPMACSDQH,
20990 IX86_BUILTIN_VPMADCSSWD,
20991 IX86_BUILTIN_VPMADCSWD,
20993 IX86_BUILTIN_VPHADDBW,
20994 IX86_BUILTIN_VPHADDBD,
20995 IX86_BUILTIN_VPHADDBQ,
20996 IX86_BUILTIN_VPHADDWD,
20997 IX86_BUILTIN_VPHADDWQ,
20998 IX86_BUILTIN_VPHADDDQ,
20999 IX86_BUILTIN_VPHADDUBW,
21000 IX86_BUILTIN_VPHADDUBD,
21001 IX86_BUILTIN_VPHADDUBQ,
21002 IX86_BUILTIN_VPHADDUWD,
21003 IX86_BUILTIN_VPHADDUWQ,
21004 IX86_BUILTIN_VPHADDUDQ,
21005 IX86_BUILTIN_VPHSUBBW,
21006 IX86_BUILTIN_VPHSUBWD,
21007 IX86_BUILTIN_VPHSUBDQ,
21009 IX86_BUILTIN_VPROTB,
21010 IX86_BUILTIN_VPROTW,
21011 IX86_BUILTIN_VPROTD,
21012 IX86_BUILTIN_VPROTQ,
21013 IX86_BUILTIN_VPROTB_IMM,
21014 IX86_BUILTIN_VPROTW_IMM,
21015 IX86_BUILTIN_VPROTD_IMM,
21016 IX86_BUILTIN_VPROTQ_IMM,
21018 IX86_BUILTIN_VPSHLB,
21019 IX86_BUILTIN_VPSHLW,
21020 IX86_BUILTIN_VPSHLD,
21021 IX86_BUILTIN_VPSHLQ,
21022 IX86_BUILTIN_VPSHAB,
21023 IX86_BUILTIN_VPSHAW,
21024 IX86_BUILTIN_VPSHAD,
21025 IX86_BUILTIN_VPSHAQ,
21027 IX86_BUILTIN_VFRCZSS,
21028 IX86_BUILTIN_VFRCZSD,
21029 IX86_BUILTIN_VFRCZPS,
21030 IX86_BUILTIN_VFRCZPD,
21031 IX86_BUILTIN_VFRCZPS256,
21032 IX86_BUILTIN_VFRCZPD256,
21034 IX86_BUILTIN_VPCOMEQUB,
21035 IX86_BUILTIN_VPCOMNEUB,
21036 IX86_BUILTIN_VPCOMLTUB,
21037 IX86_BUILTIN_VPCOMLEUB,
21038 IX86_BUILTIN_VPCOMGTUB,
21039 IX86_BUILTIN_VPCOMGEUB,
21040 IX86_BUILTIN_VPCOMFALSEUB,
21041 IX86_BUILTIN_VPCOMTRUEUB,
21043 IX86_BUILTIN_VPCOMEQUW,
21044 IX86_BUILTIN_VPCOMNEUW,
21045 IX86_BUILTIN_VPCOMLTUW,
21046 IX86_BUILTIN_VPCOMLEUW,
21047 IX86_BUILTIN_VPCOMGTUW,
21048 IX86_BUILTIN_VPCOMGEUW,
21049 IX86_BUILTIN_VPCOMFALSEUW,
21050 IX86_BUILTIN_VPCOMTRUEUW,
21052 IX86_BUILTIN_VPCOMEQUD,
21053 IX86_BUILTIN_VPCOMNEUD,
21054 IX86_BUILTIN_VPCOMLTUD,
21055 IX86_BUILTIN_VPCOMLEUD,
21056 IX86_BUILTIN_VPCOMGTUD,
21057 IX86_BUILTIN_VPCOMGEUD,
21058 IX86_BUILTIN_VPCOMFALSEUD,
21059 IX86_BUILTIN_VPCOMTRUEUD,
21061 IX86_BUILTIN_VPCOMEQUQ,
21062 IX86_BUILTIN_VPCOMNEUQ,
21063 IX86_BUILTIN_VPCOMLTUQ,
21064 IX86_BUILTIN_VPCOMLEUQ,
21065 IX86_BUILTIN_VPCOMGTUQ,
21066 IX86_BUILTIN_VPCOMGEUQ,
21067 IX86_BUILTIN_VPCOMFALSEUQ,
21068 IX86_BUILTIN_VPCOMTRUEUQ,
21070 IX86_BUILTIN_VPCOMEQB,
21071 IX86_BUILTIN_VPCOMNEB,
21072 IX86_BUILTIN_VPCOMLTB,
21073 IX86_BUILTIN_VPCOMLEB,
21074 IX86_BUILTIN_VPCOMGTB,
21075 IX86_BUILTIN_VPCOMGEB,
21076 IX86_BUILTIN_VPCOMFALSEB,
21077 IX86_BUILTIN_VPCOMTRUEB,
21079 IX86_BUILTIN_VPCOMEQW,
21080 IX86_BUILTIN_VPCOMNEW,
21081 IX86_BUILTIN_VPCOMLTW,
21082 IX86_BUILTIN_VPCOMLEW,
21083 IX86_BUILTIN_VPCOMGTW,
21084 IX86_BUILTIN_VPCOMGEW,
21085 IX86_BUILTIN_VPCOMFALSEW,
21086 IX86_BUILTIN_VPCOMTRUEW,
21088 IX86_BUILTIN_VPCOMEQD,
21089 IX86_BUILTIN_VPCOMNED,
21090 IX86_BUILTIN_VPCOMLTD,
21091 IX86_BUILTIN_VPCOMLED,
21092 IX86_BUILTIN_VPCOMGTD,
21093 IX86_BUILTIN_VPCOMGED,
21094 IX86_BUILTIN_VPCOMFALSED,
21095 IX86_BUILTIN_VPCOMTRUED,
21097 IX86_BUILTIN_VPCOMEQQ,
21098 IX86_BUILTIN_VPCOMNEQ,
21099 IX86_BUILTIN_VPCOMLTQ,
21100 IX86_BUILTIN_VPCOMLEQ,
21101 IX86_BUILTIN_VPCOMGTQ,
21102 IX86_BUILTIN_VPCOMGEQ,
21103 IX86_BUILTIN_VPCOMFALSEQ,
21104 IX86_BUILTIN_VPCOMTRUEQ,
21106 /* LWP instructions. */
21107 IX86_BUILTIN_LLWPCB16,
21108 IX86_BUILTIN_LLWPCB32,
21109 IX86_BUILTIN_LLWPCB64,
21110 IX86_BUILTIN_SLWPCB16,
21111 IX86_BUILTIN_SLWPCB32,
21112 IX86_BUILTIN_SLWPCB64,
21113 IX86_BUILTIN_LWPVAL16,
21114 IX86_BUILTIN_LWPVAL32,
21115 IX86_BUILTIN_LWPVAL64,
21116 IX86_BUILTIN_LWPINS16,
21117 IX86_BUILTIN_LWPINS32,
21118 IX86_BUILTIN_LWPINS64,
21123 /* Table for the ix86 builtin decls. */
21124 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
21126 /* Table of all of the builtin functions that are possible with different ISA's
21127 but are waiting to be built until a function is declared to use that
21129 struct GTY(()) builtin_isa {
21130 tree type; /* builtin type to use in the declaration */
21131 const char *name; /* function name */
21132 int isa; /* isa_flags this builtin is defined for */
21133 bool const_p; /* true if the declaration is constant */
21136 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
21139 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21140 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
21141 * function decl in the ix86_builtins array. Returns the function decl or
21142 * NULL_TREE, if the builtin was not added.
21144 * If the front end has a special hook for builtin functions, delay adding
21145 * builtin functions that aren't in the current ISA until the ISA is changed
21146 * with function specific optimization. Doing so, can save about 300K for the
21147 * default compiler. When the builtin is expanded, check at that time whether
21150 * If the front end doesn't have a special hook, record all builtins, even if
21151 * it isn't an instruction set in the current ISA in case the user uses
21152 * function specific options for a different ISA, so that we don't get scope
21153 * errors if a builtin is added in the middle of a function scope. */
21156 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
21158 tree decl = NULL_TREE;
21160 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
21162 ix86_builtins_isa[(int) code].isa = mask;
21164 if ((mask & ix86_isa_flags) != 0
21165 || (lang_hooks.builtin_function
21166 == lang_hooks.builtin_function_ext_scope))
21169 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
21171 ix86_builtins[(int) code] = decl;
21172 ix86_builtins_isa[(int) code].type = NULL_TREE;
21176 ix86_builtins[(int) code] = NULL_TREE;
21177 ix86_builtins_isa[(int) code].const_p = false;
21178 ix86_builtins_isa[(int) code].type = type;
21179 ix86_builtins_isa[(int) code].name = name;
21186 /* Like def_builtin, but also marks the function decl "const". */
21189 def_builtin_const (int mask, const char *name, tree type,
21190 enum ix86_builtins code)
21192 tree decl = def_builtin (mask, name, type, code);
21194 TREE_READONLY (decl) = 1;
21196 ix86_builtins_isa[(int) code].const_p = true;
21201 /* Add any new builtin functions for a given ISA that may not have been
21202 declared. This saves a bit of space compared to adding all of the
21203 declarations to the tree, even if we didn't use them. */
21206 ix86_add_new_builtins (int isa)
21211 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
21213 if ((ix86_builtins_isa[i].isa & isa) != 0
21214 && ix86_builtins_isa[i].type != NULL_TREE)
21216 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
21217 ix86_builtins_isa[i].type,
21218 i, BUILT_IN_MD, NULL,
21221 ix86_builtins[i] = decl;
21222 ix86_builtins_isa[i].type = NULL_TREE;
21223 if (ix86_builtins_isa[i].const_p)
21224 TREE_READONLY (decl) = 1;
21229 /* Bits for builtin_description.flag. */
21231 /* Set when we don't support the comparison natively, and should
21232 swap_comparison in order to support it. */
21233 #define BUILTIN_DESC_SWAP_OPERANDS 1
21235 struct builtin_description
21237 const unsigned int mask;
21238 const enum insn_code icode;
21239 const char *const name;
21240 const enum ix86_builtins code;
21241 const enum rtx_code comparison;
21245 static const struct builtin_description bdesc_comi[] =
21247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21273 static const struct builtin_description bdesc_pcmpestr[] =
21276 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21277 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21278 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21279 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21280 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21281 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21282 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21285 static const struct builtin_description bdesc_pcmpistr[] =
21288 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21289 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21290 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21291 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21292 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21293 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21294 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21297 /* Special builtin types */
21298 enum ix86_special_builtin_type
21300 SPECIAL_FTYPE_UNKNOWN,
21303 UINT64_FTYPE_PUNSIGNED,
21304 V32QI_FTYPE_PCCHAR,
21305 V16QI_FTYPE_PCCHAR,
21307 V8SF_FTYPE_PCFLOAT,
21309 V4DF_FTYPE_PCDOUBLE,
21310 V4SF_FTYPE_PCFLOAT,
21311 V2DF_FTYPE_PCDOUBLE,
21312 V8SF_FTYPE_PCV8SF_V8SF,
21313 V4DF_FTYPE_PCV4DF_V4DF,
21314 V4SF_FTYPE_V4SF_PCV2SF,
21315 V4SF_FTYPE_PCV4SF_V4SF,
21316 V2DF_FTYPE_V2DF_PCDOUBLE,
21317 V2DF_FTYPE_PCV2DF_V2DF,
21319 VOID_FTYPE_PV2SF_V4SF,
21320 VOID_FTYPE_PV4DI_V4DI,
21321 VOID_FTYPE_PV2DI_V2DI,
21322 VOID_FTYPE_PCHAR_V32QI,
21323 VOID_FTYPE_PCHAR_V16QI,
21324 VOID_FTYPE_PFLOAT_V8SF,
21325 VOID_FTYPE_PFLOAT_V4SF,
21326 VOID_FTYPE_PDOUBLE_V4DF,
21327 VOID_FTYPE_PDOUBLE_V2DF,
21329 VOID_FTYPE_PINT_INT,
21330 VOID_FTYPE_PV8SF_V8SF_V8SF,
21331 VOID_FTYPE_PV4DF_V4DF_V4DF,
21332 VOID_FTYPE_PV4SF_V4SF_V4SF,
21333 VOID_FTYPE_PV2DF_V2DF_V2DF,
21334 VOID_FTYPE_USHORT_UINT_USHORT,
21335 VOID_FTYPE_UINT_UINT_UINT,
21336 VOID_FTYPE_UINT64_UINT_UINT,
21337 UCHAR_FTYPE_USHORT_UINT_USHORT,
21338 UCHAR_FTYPE_UINT_UINT_UINT,
21339 UCHAR_FTYPE_UINT64_UINT_UINT
21342 /* Builtin types */
21343 enum ix86_builtin_type
21346 FLOAT128_FTYPE_FLOAT128,
21348 FLOAT128_FTYPE_FLOAT128_FLOAT128,
21349 INT_FTYPE_V8SF_V8SF_PTEST,
21350 INT_FTYPE_V4DI_V4DI_PTEST,
21351 INT_FTYPE_V4DF_V4DF_PTEST,
21352 INT_FTYPE_V4SF_V4SF_PTEST,
21353 INT_FTYPE_V2DI_V2DI_PTEST,
21354 INT_FTYPE_V2DF_V2DF_PTEST,
21389 V4SF_FTYPE_V4SF_VEC_MERGE,
21398 V2DF_FTYPE_V2DF_VEC_MERGE,
21409 V16QI_FTYPE_V16QI_V16QI,
21410 V16QI_FTYPE_V8HI_V8HI,
21411 V8QI_FTYPE_V8QI_V8QI,
21412 V8QI_FTYPE_V4HI_V4HI,
21413 V8HI_FTYPE_V8HI_V8HI,
21414 V8HI_FTYPE_V8HI_V8HI_COUNT,
21415 V8HI_FTYPE_V16QI_V16QI,
21416 V8HI_FTYPE_V4SI_V4SI,
21417 V8HI_FTYPE_V8HI_SI_COUNT,
21418 V8SF_FTYPE_V8SF_V8SF,
21419 V8SF_FTYPE_V8SF_V8SI,
21420 V4SI_FTYPE_V4SI_V4SI,
21421 V4SI_FTYPE_V4SI_V4SI_COUNT,
21422 V4SI_FTYPE_V8HI_V8HI,
21423 V4SI_FTYPE_V4SF_V4SF,
21424 V4SI_FTYPE_V2DF_V2DF,
21425 V4SI_FTYPE_V4SI_SI_COUNT,
21426 V4HI_FTYPE_V4HI_V4HI,
21427 V4HI_FTYPE_V4HI_V4HI_COUNT,
21428 V4HI_FTYPE_V8QI_V8QI,
21429 V4HI_FTYPE_V2SI_V2SI,
21430 V4HI_FTYPE_V4HI_SI_COUNT,
21431 V4DF_FTYPE_V4DF_V4DF,
21432 V4DF_FTYPE_V4DF_V4DI,
21433 V4SF_FTYPE_V4SF_V4SF,
21434 V4SF_FTYPE_V4SF_V4SF_SWAP,
21435 V4SF_FTYPE_V4SF_V4SI,
21436 V4SF_FTYPE_V4SF_V2SI,
21437 V4SF_FTYPE_V4SF_V2DF,
21438 V4SF_FTYPE_V4SF_DI,
21439 V4SF_FTYPE_V4SF_SI,
21440 V2DI_FTYPE_V2DI_V2DI,
21441 V2DI_FTYPE_V2DI_V2DI_COUNT,
21442 V2DI_FTYPE_V16QI_V16QI,
21443 V2DI_FTYPE_V4SI_V4SI,
21444 V2DI_FTYPE_V2DI_V16QI,
21445 V2DI_FTYPE_V2DF_V2DF,
21446 V2DI_FTYPE_V2DI_SI_COUNT,
21447 V2SI_FTYPE_V2SI_V2SI,
21448 V2SI_FTYPE_V2SI_V2SI_COUNT,
21449 V2SI_FTYPE_V4HI_V4HI,
21450 V2SI_FTYPE_V2SF_V2SF,
21451 V2SI_FTYPE_V2SI_SI_COUNT,
21452 V2DF_FTYPE_V2DF_V2DF,
21453 V2DF_FTYPE_V2DF_V2DF_SWAP,
21454 V2DF_FTYPE_V2DF_V4SF,
21455 V2DF_FTYPE_V2DF_V2DI,
21456 V2DF_FTYPE_V2DF_DI,
21457 V2DF_FTYPE_V2DF_SI,
21458 V2SF_FTYPE_V2SF_V2SF,
21459 V1DI_FTYPE_V1DI_V1DI,
21460 V1DI_FTYPE_V1DI_V1DI_COUNT,
21461 V1DI_FTYPE_V8QI_V8QI,
21462 V1DI_FTYPE_V2SI_V2SI,
21463 V1DI_FTYPE_V1DI_SI_COUNT,
21464 UINT64_FTYPE_UINT64_UINT64,
21465 UINT_FTYPE_UINT_UINT,
21466 UINT_FTYPE_UINT_USHORT,
21467 UINT_FTYPE_UINT_UCHAR,
21468 UINT16_FTYPE_UINT16_INT,
21469 UINT8_FTYPE_UINT8_INT,
21470 V8HI_FTYPE_V8HI_INT,
21471 V4SI_FTYPE_V4SI_INT,
21472 V4HI_FTYPE_V4HI_INT,
21473 V8SF_FTYPE_V8SF_INT,
21474 V4SI_FTYPE_V8SI_INT,
21475 V4SF_FTYPE_V8SF_INT,
21476 V2DF_FTYPE_V4DF_INT,
21477 V4DF_FTYPE_V4DF_INT,
21478 V4SF_FTYPE_V4SF_INT,
21479 V2DI_FTYPE_V2DI_INT,
21480 V2DI2TI_FTYPE_V2DI_INT,
21481 V2DF_FTYPE_V2DF_INT,
21482 V16QI_FTYPE_V16QI_V16QI_V16QI,
21483 V8SF_FTYPE_V8SF_V8SF_V8SF,
21484 V4DF_FTYPE_V4DF_V4DF_V4DF,
21485 V4SF_FTYPE_V4SF_V4SF_V4SF,
21486 V2DF_FTYPE_V2DF_V2DF_V2DF,
21487 V16QI_FTYPE_V16QI_V16QI_INT,
21488 V8SI_FTYPE_V8SI_V8SI_INT,
21489 V8SI_FTYPE_V8SI_V4SI_INT,
21490 V8HI_FTYPE_V8HI_V8HI_INT,
21491 V8SF_FTYPE_V8SF_V8SF_INT,
21492 V8SF_FTYPE_V8SF_V4SF_INT,
21493 V4SI_FTYPE_V4SI_V4SI_INT,
21494 V4DF_FTYPE_V4DF_V4DF_INT,
21495 V4DF_FTYPE_V4DF_V2DF_INT,
21496 V4SF_FTYPE_V4SF_V4SF_INT,
21497 V2DI_FTYPE_V2DI_V2DI_INT,
21498 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21499 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21500 V2DF_FTYPE_V2DF_V2DF_INT,
21501 V2DI_FTYPE_V2DI_UINT_UINT,
21502 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21505 /* Special builtins with variable number of arguments. */
21506 static const struct builtin_description bdesc_special_args[] =
21508 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21509 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21512 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21515 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21518 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21519 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21520 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21522 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21523 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21524 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21525 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21527 /* SSE or 3DNow!A */
21528 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21529 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21546 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21552 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21553 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21558 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21587 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbhi1, "__builtin_ia32_llwpcb16", IX86_BUILTIN_LLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID },
21588 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbsi1, "__builtin_ia32_llwpcb32", IX86_BUILTIN_LLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID },
21589 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbdi1, "__builtin_ia32_llwpcb64", IX86_BUILTIN_LLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID },
21591 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbhi1, "__builtin_ia32_slwpcb16", IX86_BUILTIN_SLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID },
21592 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbsi1, "__builtin_ia32_slwpcb32", IX86_BUILTIN_SLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID },
21593 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbdi1, "__builtin_ia32_slwpcb64", IX86_BUILTIN_SLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID },
21595 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalhi3, "__builtin_ia32_lwpval16", IX86_BUILTIN_LWPVAL16, UNKNOWN, (int) VOID_FTYPE_USHORT_UINT_USHORT },
21596 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
21597 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
21598 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinshi3, "__builtin_ia32_lwpins16", IX86_BUILTIN_LWPINS16, UNKNOWN, (int) UCHAR_FTYPE_USHORT_UINT_USHORT },
21599 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
21600 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
21604 /* Builtins with variable number of arguments. */
21605 static const struct builtin_description bdesc_args[] =
21607 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21608 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21609 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21610 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21611 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21612 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21613 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21616 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21617 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21618 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21619 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21620 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21621 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21623 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21624 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21625 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21626 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21627 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21628 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21629 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21630 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21632 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21633 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21635 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21636 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21637 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21638 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21640 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21641 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21642 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21643 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21644 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21645 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21647 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21648 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21649 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21650 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21651 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21652 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21654 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21655 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21656 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21658 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21660 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21661 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21662 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21663 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21664 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21665 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21667 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21668 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21669 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21670 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21671 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21672 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21674 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21675 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21676 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21677 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21680 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21681 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21682 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21683 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21685 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21686 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21687 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21688 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21689 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21690 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21691 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21692 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21693 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21694 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21695 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21696 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21697 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21698 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21699 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21702 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21703 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21704 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21705 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21706 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21707 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21710 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21711 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21712 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21713 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21714 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21715 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21716 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21717 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21718 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21719 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21720 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21721 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21723 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21725 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21726 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21727 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21728 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21729 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21730 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21731 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21732 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21734 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21736 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21737 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21738 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21739 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21740 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21741 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21742 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21745 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21757 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21758 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21759 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21760 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21762 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21764 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21765 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21767 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21775 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21776 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21777 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21779 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21782 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21783 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21785 /* SSE MMX or 3Dnow!A */
21786 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21787 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21788 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21790 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21791 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21792 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21793 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21795 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21796 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21798 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21801 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21803 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21804 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21805 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21813 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21819 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21820 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21821 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21824 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21827 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21828 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21829 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21830 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21857 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21858 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21859 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21860 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21862 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21863 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21864 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21865 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21867 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21873 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21875 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21876 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21877 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21878 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21879 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21880 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21881 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21882 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21893 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21894 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21896 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21898 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21899 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21902 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21906 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21911 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21912 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21913 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21914 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21920 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21922 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21926 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21927 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21929 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21930 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21932 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21935 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21937 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21938 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21943 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21944 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21945 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21946 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21947 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21948 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21950 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21951 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21952 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21953 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21954 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21955 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21956 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21958 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21959 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21960 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21961 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21969 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21970 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21972 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21975 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21976 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21979 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21980 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21982 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21983 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21984 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21985 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21986 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21987 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21990 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21991 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21992 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21993 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21994 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21995 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21997 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21998 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21999 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22000 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22001 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22002 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22003 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22004 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22005 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22006 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22007 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22008 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22009 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
22010 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
22011 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22012 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22013 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22014 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22015 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22016 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22017 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22018 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22019 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22020 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22023 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
22024 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
22027 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22028 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22029 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
22030 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
22031 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22032 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22033 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22034 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
22035 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22036 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
22038 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22039 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22040 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22041 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22042 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22043 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22044 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22045 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22046 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22047 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22048 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22049 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22050 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22052 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22053 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22054 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22056 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22057 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22058 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22059 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22060 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22061 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22062 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22063 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22066 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22067 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22068 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22069 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22071 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22072 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22073 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22076 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22077 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22078 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22079 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22080 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22083 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22084 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22085 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22086 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22089 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22090 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22092 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22093 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22094 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22095 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22098 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22101 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22102 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22103 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22104 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22105 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22106 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22107 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22108 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22109 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22111 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22112 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22113 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22114 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22115 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22116 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22117 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22118 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22119 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22120 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22121 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22122 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22123 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22124 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22125 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22126 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22130 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22134 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22139 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22141 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22142 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22146 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22147 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22148 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22149 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22150 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22151 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22152 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22153 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22154 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22155 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22157 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22160 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22163 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22164 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22165 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22166 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22168 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22169 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22170 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22172 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22173 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22174 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22175 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22176 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22180 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22183 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22185 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22189 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22190 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22192 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22195 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22197 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22198 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22199 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22200 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22202 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22204 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22205 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22207 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22211 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22212 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22215 /* FMA4 and XOP. */
22216 enum multi_arg_type {
22238 MULTI_ARG_2_DI_IMM,
22239 MULTI_ARG_2_SI_IMM,
22240 MULTI_ARG_2_HI_IMM,
22241 MULTI_ARG_2_QI_IMM,
22242 MULTI_ARG_2_DI_CMP,
22243 MULTI_ARG_2_SI_CMP,
22244 MULTI_ARG_2_HI_CMP,
22245 MULTI_ARG_2_QI_CMP,
22269 static const struct builtin_description bdesc_multi_arg[] =
22271 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22272 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22273 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22274 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22275 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22276 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22277 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22278 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22280 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22281 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22282 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22283 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22284 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22285 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22286 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22287 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22289 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22290 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22291 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22292 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22294 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22295 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22296 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22297 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22299 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22300 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22301 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22302 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22304 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22305 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22306 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22307 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
22320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
22321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
22322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22348 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22359 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
22362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
22364 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22380 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22464 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22465 in the current target ISA to allow the user to compile particular modules
22466 with different target specific options that differ from the command line
22469 ix86_init_mmx_sse_builtins (void)
22471 const struct builtin_description * d;
22474 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
22475 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
22476 tree V1DI_type_node
22477 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
22478 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
22479 tree V2DI_type_node
22480 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
22481 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
22482 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
22483 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
22484 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
22485 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
22486 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
22488 tree pchar_type_node = build_pointer_type (char_type_node);
22489 tree pcchar_type_node
22490 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
22491 tree pfloat_type_node = build_pointer_type (float_type_node);
22492 tree pcfloat_type_node
22493 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
22494 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
22495 tree pcv2sf_type_node
22496 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
22497 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
22498 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
22501 tree int_ftype_v4sf_v4sf
22502 = build_function_type_list (integer_type_node,
22503 V4SF_type_node, V4SF_type_node, NULL_TREE);
22504 tree v4si_ftype_v4sf_v4sf
22505 = build_function_type_list (V4SI_type_node,
22506 V4SF_type_node, V4SF_type_node, NULL_TREE);
22507 /* MMX/SSE/integer conversions. */
22508 tree int_ftype_v4sf
22509 = build_function_type_list (integer_type_node,
22510 V4SF_type_node, NULL_TREE);
22511 tree int64_ftype_v4sf
22512 = build_function_type_list (long_long_integer_type_node,
22513 V4SF_type_node, NULL_TREE);
22514 tree int_ftype_v8qi
22515 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
22516 tree v4sf_ftype_v4sf_int
22517 = build_function_type_list (V4SF_type_node,
22518 V4SF_type_node, integer_type_node, NULL_TREE);
22519 tree v4sf_ftype_v4sf_int64
22520 = build_function_type_list (V4SF_type_node,
22521 V4SF_type_node, long_long_integer_type_node,
22523 tree v4sf_ftype_v4sf_v2si
22524 = build_function_type_list (V4SF_type_node,
22525 V4SF_type_node, V2SI_type_node, NULL_TREE);
22527 /* Miscellaneous. */
22528 tree v8qi_ftype_v4hi_v4hi
22529 = build_function_type_list (V8QI_type_node,
22530 V4HI_type_node, V4HI_type_node, NULL_TREE);
22531 tree v4hi_ftype_v2si_v2si
22532 = build_function_type_list (V4HI_type_node,
22533 V2SI_type_node, V2SI_type_node, NULL_TREE);
22534 tree v4sf_ftype_v4sf_v4sf_int
22535 = build_function_type_list (V4SF_type_node,
22536 V4SF_type_node, V4SF_type_node,
22537 integer_type_node, NULL_TREE);
22538 tree v2si_ftype_v4hi_v4hi
22539 = build_function_type_list (V2SI_type_node,
22540 V4HI_type_node, V4HI_type_node, NULL_TREE);
22541 tree v4hi_ftype_v4hi_int
22542 = build_function_type_list (V4HI_type_node,
22543 V4HI_type_node, integer_type_node, NULL_TREE);
22544 tree v2si_ftype_v2si_int
22545 = build_function_type_list (V2SI_type_node,
22546 V2SI_type_node, integer_type_node, NULL_TREE);
22547 tree v1di_ftype_v1di_int
22548 = build_function_type_list (V1DI_type_node,
22549 V1DI_type_node, integer_type_node, NULL_TREE);
22551 tree void_ftype_void
22552 = build_function_type (void_type_node, void_list_node);
22553 tree void_ftype_unsigned
22554 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22555 tree void_ftype_unsigned_unsigned
22556 = build_function_type_list (void_type_node, unsigned_type_node,
22557 unsigned_type_node, NULL_TREE);
22558 tree void_ftype_pcvoid_unsigned_unsigned
22559 = build_function_type_list (void_type_node, const_ptr_type_node,
22560 unsigned_type_node, unsigned_type_node,
22562 tree unsigned_ftype_void
22563 = build_function_type (unsigned_type_node, void_list_node);
22564 tree v2si_ftype_v4sf
22565 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22566 /* Loads/stores. */
22567 tree void_ftype_v8qi_v8qi_pchar
22568 = build_function_type_list (void_type_node,
22569 V8QI_type_node, V8QI_type_node,
22570 pchar_type_node, NULL_TREE);
22571 tree v4sf_ftype_pcfloat
22572 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22573 tree v4sf_ftype_v4sf_pcv2sf
22574 = build_function_type_list (V4SF_type_node,
22575 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22576 tree void_ftype_pv2sf_v4sf
22577 = build_function_type_list (void_type_node,
22578 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22579 tree void_ftype_pfloat_v4sf
22580 = build_function_type_list (void_type_node,
22581 pfloat_type_node, V4SF_type_node, NULL_TREE);
22582 tree void_ftype_pdi_di
22583 = build_function_type_list (void_type_node,
22584 pdi_type_node, long_long_unsigned_type_node,
22586 tree void_ftype_pv2di_v2di
22587 = build_function_type_list (void_type_node,
22588 pv2di_type_node, V2DI_type_node, NULL_TREE);
22589 /* Normal vector unops. */
22590 tree v4sf_ftype_v4sf
22591 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22592 tree v16qi_ftype_v16qi
22593 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22594 tree v8hi_ftype_v8hi
22595 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22596 tree v4si_ftype_v4si
22597 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22598 tree v8qi_ftype_v8qi
22599 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22600 tree v4hi_ftype_v4hi
22601 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22603 /* Normal vector binops. */
22604 tree v4sf_ftype_v4sf_v4sf
22605 = build_function_type_list (V4SF_type_node,
22606 V4SF_type_node, V4SF_type_node, NULL_TREE);
22607 tree v8qi_ftype_v8qi_v8qi
22608 = build_function_type_list (V8QI_type_node,
22609 V8QI_type_node, V8QI_type_node, NULL_TREE);
22610 tree v4hi_ftype_v4hi_v4hi
22611 = build_function_type_list (V4HI_type_node,
22612 V4HI_type_node, V4HI_type_node, NULL_TREE);
22613 tree v2si_ftype_v2si_v2si
22614 = build_function_type_list (V2SI_type_node,
22615 V2SI_type_node, V2SI_type_node, NULL_TREE);
22616 tree v1di_ftype_v1di_v1di
22617 = build_function_type_list (V1DI_type_node,
22618 V1DI_type_node, V1DI_type_node, NULL_TREE);
22619 tree v1di_ftype_v1di_v1di_int
22620 = build_function_type_list (V1DI_type_node,
22621 V1DI_type_node, V1DI_type_node,
22622 integer_type_node, NULL_TREE);
22623 tree v2si_ftype_v2sf
22624 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22625 tree v2sf_ftype_v2si
22626 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22627 tree v2si_ftype_v2si
22628 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22629 tree v2sf_ftype_v2sf
22630 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22631 tree v2sf_ftype_v2sf_v2sf
22632 = build_function_type_list (V2SF_type_node,
22633 V2SF_type_node, V2SF_type_node, NULL_TREE);
22634 tree v2si_ftype_v2sf_v2sf
22635 = build_function_type_list (V2SI_type_node,
22636 V2SF_type_node, V2SF_type_node, NULL_TREE);
22637 tree pint_type_node = build_pointer_type (integer_type_node);
22638 tree pdouble_type_node = build_pointer_type (double_type_node);
22639 tree pcdouble_type_node = build_pointer_type (
22640 build_type_variant (double_type_node, 1, 0));
22641 tree int_ftype_v2df_v2df
22642 = build_function_type_list (integer_type_node,
22643 V2DF_type_node, V2DF_type_node, NULL_TREE);
22645 tree void_ftype_pcvoid
22646 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22647 tree v4sf_ftype_v4si
22648 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22649 tree v4si_ftype_v4sf
22650 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22651 tree v2df_ftype_v4si
22652 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22653 tree v4si_ftype_v2df
22654 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22655 tree v4si_ftype_v2df_v2df
22656 = build_function_type_list (V4SI_type_node,
22657 V2DF_type_node, V2DF_type_node, NULL_TREE);
22658 tree v2si_ftype_v2df
22659 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22660 tree v4sf_ftype_v2df
22661 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22662 tree v2df_ftype_v2si
22663 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22664 tree v2df_ftype_v4sf
22665 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22666 tree int_ftype_v2df
22667 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22668 tree int64_ftype_v2df
22669 = build_function_type_list (long_long_integer_type_node,
22670 V2DF_type_node, NULL_TREE);
22671 tree v2df_ftype_v2df_int
22672 = build_function_type_list (V2DF_type_node,
22673 V2DF_type_node, integer_type_node, NULL_TREE);
22674 tree v2df_ftype_v2df_int64
22675 = build_function_type_list (V2DF_type_node,
22676 V2DF_type_node, long_long_integer_type_node,
22678 tree v4sf_ftype_v4sf_v2df
22679 = build_function_type_list (V4SF_type_node,
22680 V4SF_type_node, V2DF_type_node, NULL_TREE);
22681 tree v2df_ftype_v2df_v4sf
22682 = build_function_type_list (V2DF_type_node,
22683 V2DF_type_node, V4SF_type_node, NULL_TREE);
22684 tree v2df_ftype_v2df_v2df_int
22685 = build_function_type_list (V2DF_type_node,
22686 V2DF_type_node, V2DF_type_node,
22689 tree v2df_ftype_v2df_pcdouble
22690 = build_function_type_list (V2DF_type_node,
22691 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22692 tree void_ftype_pdouble_v2df
22693 = build_function_type_list (void_type_node,
22694 pdouble_type_node, V2DF_type_node, NULL_TREE);
22695 tree void_ftype_pint_int
22696 = build_function_type_list (void_type_node,
22697 pint_type_node, integer_type_node, NULL_TREE);
22698 tree void_ftype_v16qi_v16qi_pchar
22699 = build_function_type_list (void_type_node,
22700 V16QI_type_node, V16QI_type_node,
22701 pchar_type_node, NULL_TREE);
22702 tree v2df_ftype_pcdouble
22703 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22704 tree v2df_ftype_v2df_v2df
22705 = build_function_type_list (V2DF_type_node,
22706 V2DF_type_node, V2DF_type_node, NULL_TREE);
22707 tree v16qi_ftype_v16qi_v16qi
22708 = build_function_type_list (V16QI_type_node,
22709 V16QI_type_node, V16QI_type_node, NULL_TREE);
22710 tree v8hi_ftype_v8hi_v8hi
22711 = build_function_type_list (V8HI_type_node,
22712 V8HI_type_node, V8HI_type_node, NULL_TREE);
22713 tree v4si_ftype_v4si_v4si
22714 = build_function_type_list (V4SI_type_node,
22715 V4SI_type_node, V4SI_type_node, NULL_TREE);
22716 tree v2di_ftype_v2di_v2di
22717 = build_function_type_list (V2DI_type_node,
22718 V2DI_type_node, V2DI_type_node, NULL_TREE);
22719 tree v2di_ftype_v2df_v2df
22720 = build_function_type_list (V2DI_type_node,
22721 V2DF_type_node, V2DF_type_node, NULL_TREE);
22722 tree v2df_ftype_v2df
22723 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22724 tree v2di_ftype_v2di_int
22725 = build_function_type_list (V2DI_type_node,
22726 V2DI_type_node, integer_type_node, NULL_TREE);
22727 tree v2di_ftype_v2di_v2di_int
22728 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22729 V2DI_type_node, integer_type_node, NULL_TREE);
22730 tree v4si_ftype_v4si_int
22731 = build_function_type_list (V4SI_type_node,
22732 V4SI_type_node, integer_type_node, NULL_TREE);
22733 tree v8hi_ftype_v8hi_int
22734 = build_function_type_list (V8HI_type_node,
22735 V8HI_type_node, integer_type_node, NULL_TREE);
22736 tree v4si_ftype_v8hi_v8hi
22737 = build_function_type_list (V4SI_type_node,
22738 V8HI_type_node, V8HI_type_node, NULL_TREE);
22739 tree v1di_ftype_v8qi_v8qi
22740 = build_function_type_list (V1DI_type_node,
22741 V8QI_type_node, V8QI_type_node, NULL_TREE);
22742 tree v1di_ftype_v2si_v2si
22743 = build_function_type_list (V1DI_type_node,
22744 V2SI_type_node, V2SI_type_node, NULL_TREE);
22745 tree v2di_ftype_v16qi_v16qi
22746 = build_function_type_list (V2DI_type_node,
22747 V16QI_type_node, V16QI_type_node, NULL_TREE);
22748 tree v2di_ftype_v4si_v4si
22749 = build_function_type_list (V2DI_type_node,
22750 V4SI_type_node, V4SI_type_node, NULL_TREE);
22751 tree int_ftype_v16qi
22752 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22753 tree v16qi_ftype_pcchar
22754 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22755 tree void_ftype_pchar_v16qi
22756 = build_function_type_list (void_type_node,
22757 pchar_type_node, V16QI_type_node, NULL_TREE);
22759 tree v2di_ftype_v2di_unsigned_unsigned
22760 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22761 unsigned_type_node, unsigned_type_node,
22763 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22764 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22765 unsigned_type_node, unsigned_type_node,
22767 tree v2di_ftype_v2di_v16qi
22768 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22770 tree v2df_ftype_v2df_v2df_v2df
22771 = build_function_type_list (V2DF_type_node,
22772 V2DF_type_node, V2DF_type_node,
22773 V2DF_type_node, NULL_TREE);
22774 tree v4sf_ftype_v4sf_v4sf_v4sf
22775 = build_function_type_list (V4SF_type_node,
22776 V4SF_type_node, V4SF_type_node,
22777 V4SF_type_node, NULL_TREE);
22778 tree v8hi_ftype_v16qi
22779 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22781 tree v4si_ftype_v16qi
22782 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22784 tree v2di_ftype_v16qi
22785 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22787 tree v4si_ftype_v8hi
22788 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22790 tree v2di_ftype_v8hi
22791 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22793 tree v2di_ftype_v4si
22794 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22796 tree v2di_ftype_pv2di
22797 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22799 tree v16qi_ftype_v16qi_v16qi_int
22800 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22801 V16QI_type_node, integer_type_node,
22803 tree v16qi_ftype_v16qi_v16qi_v16qi
22804 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22805 V16QI_type_node, V16QI_type_node,
22807 tree v8hi_ftype_v8hi_v8hi_int
22808 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22809 V8HI_type_node, integer_type_node,
22811 tree v4si_ftype_v4si_v4si_int
22812 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22813 V4SI_type_node, integer_type_node,
22815 tree int_ftype_v2di_v2di
22816 = build_function_type_list (integer_type_node,
22817 V2DI_type_node, V2DI_type_node,
22819 tree int_ftype_v16qi_int_v16qi_int_int
22820 = build_function_type_list (integer_type_node,
22827 tree v16qi_ftype_v16qi_int_v16qi_int_int
22828 = build_function_type_list (V16QI_type_node,
22835 tree int_ftype_v16qi_v16qi_int
22836 = build_function_type_list (integer_type_node,
22843 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22845 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22847 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22849 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22851 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22853 tree V16HI_type_node = build_vector_type_for_mode (intHI_type_node,
22855 tree v8sf_ftype_v8sf
22856 = build_function_type_list (V8SF_type_node,
22859 tree v8si_ftype_v8sf
22860 = build_function_type_list (V8SI_type_node,
22863 tree v8sf_ftype_v8si
22864 = build_function_type_list (V8SF_type_node,
22867 tree v4si_ftype_v4df
22868 = build_function_type_list (V4SI_type_node,
22871 tree v4df_ftype_v4df
22872 = build_function_type_list (V4DF_type_node,
22875 tree v4df_ftype_v4si
22876 = build_function_type_list (V4DF_type_node,
22879 tree v4df_ftype_v4sf
22880 = build_function_type_list (V4DF_type_node,
22883 tree v4sf_ftype_v4df
22884 = build_function_type_list (V4SF_type_node,
22887 tree v8sf_ftype_v8sf_v8sf
22888 = build_function_type_list (V8SF_type_node,
22889 V8SF_type_node, V8SF_type_node,
22891 tree v4df_ftype_v4df_v4df
22892 = build_function_type_list (V4DF_type_node,
22893 V4DF_type_node, V4DF_type_node,
22895 tree v8sf_ftype_v8sf_int
22896 = build_function_type_list (V8SF_type_node,
22897 V8SF_type_node, integer_type_node,
22899 tree v4si_ftype_v8si_int
22900 = build_function_type_list (V4SI_type_node,
22901 V8SI_type_node, integer_type_node,
22903 tree v4df_ftype_v4df_int
22904 = build_function_type_list (V4DF_type_node,
22905 V4DF_type_node, integer_type_node,
22907 tree v4sf_ftype_v8sf_int
22908 = build_function_type_list (V4SF_type_node,
22909 V8SF_type_node, integer_type_node,
22911 tree v2df_ftype_v4df_int
22912 = build_function_type_list (V2DF_type_node,
22913 V4DF_type_node, integer_type_node,
22915 tree v8sf_ftype_v8sf_v8sf_int
22916 = build_function_type_list (V8SF_type_node,
22917 V8SF_type_node, V8SF_type_node,
22920 tree v8sf_ftype_v8sf_v8sf_v8sf
22921 = build_function_type_list (V8SF_type_node,
22922 V8SF_type_node, V8SF_type_node,
22925 tree v4df_ftype_v4df_v4df_v4df
22926 = build_function_type_list (V4DF_type_node,
22927 V4DF_type_node, V4DF_type_node,
22930 tree v8si_ftype_v8si_v8si_int
22931 = build_function_type_list (V8SI_type_node,
22932 V8SI_type_node, V8SI_type_node,
22935 tree v4df_ftype_v4df_v4df_int
22936 = build_function_type_list (V4DF_type_node,
22937 V4DF_type_node, V4DF_type_node,
22940 tree v8sf_ftype_pcfloat
22941 = build_function_type_list (V8SF_type_node,
22944 tree v4df_ftype_pcdouble
22945 = build_function_type_list (V4DF_type_node,
22946 pcdouble_type_node,
22948 tree pcv4sf_type_node
22949 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22950 tree pcv2df_type_node
22951 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22952 tree v8sf_ftype_pcv4sf
22953 = build_function_type_list (V8SF_type_node,
22956 tree v4df_ftype_pcv2df
22957 = build_function_type_list (V4DF_type_node,
22960 tree v32qi_ftype_pcchar
22961 = build_function_type_list (V32QI_type_node,
22964 tree void_ftype_pchar_v32qi
22965 = build_function_type_list (void_type_node,
22966 pchar_type_node, V32QI_type_node,
22968 tree v8si_ftype_v8si_v4si_int
22969 = build_function_type_list (V8SI_type_node,
22970 V8SI_type_node, V4SI_type_node,
22973 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22974 tree void_ftype_pv4di_v4di
22975 = build_function_type_list (void_type_node,
22976 pv4di_type_node, V4DI_type_node,
22978 tree v8sf_ftype_v8sf_v4sf_int
22979 = build_function_type_list (V8SF_type_node,
22980 V8SF_type_node, V4SF_type_node,
22983 tree v4df_ftype_v4df_v2df_int
22984 = build_function_type_list (V4DF_type_node,
22985 V4DF_type_node, V2DF_type_node,
22988 tree void_ftype_pfloat_v8sf
22989 = build_function_type_list (void_type_node,
22990 pfloat_type_node, V8SF_type_node,
22992 tree void_ftype_pdouble_v4df
22993 = build_function_type_list (void_type_node,
22994 pdouble_type_node, V4DF_type_node,
22996 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22997 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22998 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22999 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
23000 tree pcv8sf_type_node
23001 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
23002 tree pcv4df_type_node
23003 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
23004 tree v8sf_ftype_pcv8sf_v8sf
23005 = build_function_type_list (V8SF_type_node,
23006 pcv8sf_type_node, V8SF_type_node,
23008 tree v4df_ftype_pcv4df_v4df
23009 = build_function_type_list (V4DF_type_node,
23010 pcv4df_type_node, V4DF_type_node,
23012 tree v4sf_ftype_pcv4sf_v4sf
23013 = build_function_type_list (V4SF_type_node,
23014 pcv4sf_type_node, V4SF_type_node,
23016 tree v2df_ftype_pcv2df_v2df
23017 = build_function_type_list (V2DF_type_node,
23018 pcv2df_type_node, V2DF_type_node,
23020 tree void_ftype_pv8sf_v8sf_v8sf
23021 = build_function_type_list (void_type_node,
23022 pv8sf_type_node, V8SF_type_node,
23025 tree void_ftype_pv4df_v4df_v4df
23026 = build_function_type_list (void_type_node,
23027 pv4df_type_node, V4DF_type_node,
23030 tree void_ftype_pv4sf_v4sf_v4sf
23031 = build_function_type_list (void_type_node,
23032 pv4sf_type_node, V4SF_type_node,
23035 tree void_ftype_pv2df_v2df_v2df
23036 = build_function_type_list (void_type_node,
23037 pv2df_type_node, V2DF_type_node,
23040 tree v4df_ftype_v2df
23041 = build_function_type_list (V4DF_type_node,
23044 tree v8sf_ftype_v4sf
23045 = build_function_type_list (V8SF_type_node,
23048 tree v8si_ftype_v4si
23049 = build_function_type_list (V8SI_type_node,
23052 tree v2df_ftype_v4df
23053 = build_function_type_list (V2DF_type_node,
23056 tree v4sf_ftype_v8sf
23057 = build_function_type_list (V4SF_type_node,
23060 tree v4si_ftype_v8si
23061 = build_function_type_list (V4SI_type_node,
23064 tree int_ftype_v4df
23065 = build_function_type_list (integer_type_node,
23068 tree int_ftype_v8sf
23069 = build_function_type_list (integer_type_node,
23072 tree int_ftype_v8sf_v8sf
23073 = build_function_type_list (integer_type_node,
23074 V8SF_type_node, V8SF_type_node,
23076 tree int_ftype_v4di_v4di
23077 = build_function_type_list (integer_type_node,
23078 V4DI_type_node, V4DI_type_node,
23080 tree int_ftype_v4df_v4df
23081 = build_function_type_list (integer_type_node,
23082 V4DF_type_node, V4DF_type_node,
23084 tree v8sf_ftype_v8sf_v8si
23085 = build_function_type_list (V8SF_type_node,
23086 V8SF_type_node, V8SI_type_node,
23088 tree v4df_ftype_v4df_v4di
23089 = build_function_type_list (V4DF_type_node,
23090 V4DF_type_node, V4DI_type_node,
23092 tree v4sf_ftype_v4sf_v4si
23093 = build_function_type_list (V4SF_type_node,
23094 V4SF_type_node, V4SI_type_node, NULL_TREE);
23095 tree v2df_ftype_v2df_v2di
23096 = build_function_type_list (V2DF_type_node,
23097 V2DF_type_node, V2DI_type_node, NULL_TREE);
23099 /* XOP instructions */
23100 tree v2di_ftype_v2di_v2di_v2di
23101 = build_function_type_list (V2DI_type_node,
23107 tree v4di_ftype_v4di_v4di_v4di
23108 = build_function_type_list (V4DI_type_node,
23114 tree v4si_ftype_v4si_v4si_v4si
23115 = build_function_type_list (V4SI_type_node,
23121 tree v8si_ftype_v8si_v8si_v8si
23122 = build_function_type_list (V8SI_type_node,
23128 tree v32qi_ftype_v32qi_v32qi_v32qi
23129 = build_function_type_list (V32QI_type_node,
23135 tree v4si_ftype_v4si_v4si_v2di
23136 = build_function_type_list (V4SI_type_node,
23142 tree v8hi_ftype_v8hi_v8hi_v8hi
23143 = build_function_type_list (V8HI_type_node,
23149 tree v16hi_ftype_v16hi_v16hi_v16hi
23150 = build_function_type_list (V16HI_type_node,
23156 tree v8hi_ftype_v8hi_v8hi_v4si
23157 = build_function_type_list (V8HI_type_node,
23163 tree v2di_ftype_v2di_si
23164 = build_function_type_list (V2DI_type_node,
23169 tree v4si_ftype_v4si_si
23170 = build_function_type_list (V4SI_type_node,
23175 tree v8hi_ftype_v8hi_si
23176 = build_function_type_list (V8HI_type_node,
23181 tree v16qi_ftype_v16qi_si
23182 = build_function_type_list (V16QI_type_node,
23187 tree v2di_ftype_v2di
23188 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
23190 tree v16qi_ftype_v8hi_v8hi
23191 = build_function_type_list (V16QI_type_node,
23192 V8HI_type_node, V8HI_type_node,
23194 tree v8hi_ftype_v4si_v4si
23195 = build_function_type_list (V8HI_type_node,
23196 V4SI_type_node, V4SI_type_node,
23198 tree v8hi_ftype_v16qi_v16qi
23199 = build_function_type_list (V8HI_type_node,
23200 V16QI_type_node, V16QI_type_node,
23202 tree v4hi_ftype_v8qi_v8qi
23203 = build_function_type_list (V4HI_type_node,
23204 V8QI_type_node, V8QI_type_node,
23206 tree unsigned_ftype_unsigned_uchar
23207 = build_function_type_list (unsigned_type_node,
23208 unsigned_type_node,
23209 unsigned_char_type_node,
23211 tree unsigned_ftype_unsigned_ushort
23212 = build_function_type_list (unsigned_type_node,
23213 unsigned_type_node,
23214 short_unsigned_type_node,
23216 tree unsigned_ftype_unsigned_unsigned
23217 = build_function_type_list (unsigned_type_node,
23218 unsigned_type_node,
23219 unsigned_type_node,
23221 tree uint64_ftype_uint64_uint64
23222 = build_function_type_list (long_long_unsigned_type_node,
23223 long_long_unsigned_type_node,
23224 long_long_unsigned_type_node,
23226 tree float_ftype_float
23227 = build_function_type_list (float_type_node,
23231 /* Integer intrinsics. */
23232 tree uint64_ftype_void
23233 = build_function_type (long_long_unsigned_type_node,
23236 = build_function_type_list (integer_type_node,
23237 integer_type_node, NULL_TREE);
23238 tree int64_ftype_int64
23239 = build_function_type_list (long_long_integer_type_node,
23240 long_long_integer_type_node,
23242 tree uint64_ftype_int
23243 = build_function_type_list (long_long_unsigned_type_node,
23244 integer_type_node, NULL_TREE);
23245 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
23246 tree uint64_ftype_punsigned
23247 = build_function_type_list (long_long_unsigned_type_node,
23248 punsigned_type_node, NULL_TREE);
23249 tree ushort_ftype_ushort_int
23250 = build_function_type_list (short_unsigned_type_node,
23251 short_unsigned_type_node,
23254 tree uchar_ftype_uchar_int
23255 = build_function_type_list (unsigned_char_type_node,
23256 unsigned_char_type_node,
23260 /* LWP instructions. */
23262 tree void_ftype_ushort_unsigned_ushort
23263 = build_function_type_list (void_type_node,
23264 short_unsigned_type_node,
23265 unsigned_type_node,
23266 short_unsigned_type_node,
23269 tree void_ftype_unsigned_unsigned_unsigned
23270 = build_function_type_list (void_type_node,
23271 unsigned_type_node,
23272 unsigned_type_node,
23273 unsigned_type_node,
23276 tree void_ftype_uint64_unsigned_unsigned
23277 = build_function_type_list (void_type_node,
23278 long_long_unsigned_type_node,
23279 unsigned_type_node,
23280 unsigned_type_node,
23283 tree uchar_ftype_ushort_unsigned_ushort
23284 = build_function_type_list (unsigned_char_type_node,
23285 short_unsigned_type_node,
23286 unsigned_type_node,
23287 short_unsigned_type_node,
23290 tree uchar_ftype_unsigned_unsigned_unsigned
23291 = build_function_type_list (unsigned_char_type_node,
23292 unsigned_type_node,
23293 unsigned_type_node,
23294 unsigned_type_node,
23297 tree uchar_ftype_uint64_unsigned_unsigned
23298 = build_function_type_list (unsigned_char_type_node,
23299 long_long_unsigned_type_node,
23300 unsigned_type_node,
23301 unsigned_type_node,
23306 /* Add all special builtins with variable number of operands. */
23307 for (i = 0, d = bdesc_special_args;
23308 i < ARRAY_SIZE (bdesc_special_args);
23316 switch ((enum ix86_special_builtin_type) d->flag)
23318 case VOID_FTYPE_VOID:
23319 type = void_ftype_void;
23321 case UINT64_FTYPE_VOID:
23322 type = uint64_ftype_void;
23324 case UINT64_FTYPE_PUNSIGNED:
23325 type = uint64_ftype_punsigned;
23327 case V32QI_FTYPE_PCCHAR:
23328 type = v32qi_ftype_pcchar;
23330 case V16QI_FTYPE_PCCHAR:
23331 type = v16qi_ftype_pcchar;
23333 case V8SF_FTYPE_PCV4SF:
23334 type = v8sf_ftype_pcv4sf;
23336 case V8SF_FTYPE_PCFLOAT:
23337 type = v8sf_ftype_pcfloat;
23339 case V4DF_FTYPE_PCV2DF:
23340 type = v4df_ftype_pcv2df;
23342 case V4DF_FTYPE_PCDOUBLE:
23343 type = v4df_ftype_pcdouble;
23345 case V4SF_FTYPE_PCFLOAT:
23346 type = v4sf_ftype_pcfloat;
23348 case V2DI_FTYPE_PV2DI:
23349 type = v2di_ftype_pv2di;
23351 case V2DF_FTYPE_PCDOUBLE:
23352 type = v2df_ftype_pcdouble;
23354 case V8SF_FTYPE_PCV8SF_V8SF:
23355 type = v8sf_ftype_pcv8sf_v8sf;
23357 case V4DF_FTYPE_PCV4DF_V4DF:
23358 type = v4df_ftype_pcv4df_v4df;
23360 case V4SF_FTYPE_V4SF_PCV2SF:
23361 type = v4sf_ftype_v4sf_pcv2sf;
23363 case V4SF_FTYPE_PCV4SF_V4SF:
23364 type = v4sf_ftype_pcv4sf_v4sf;
23366 case V2DF_FTYPE_V2DF_PCDOUBLE:
23367 type = v2df_ftype_v2df_pcdouble;
23369 case V2DF_FTYPE_PCV2DF_V2DF:
23370 type = v2df_ftype_pcv2df_v2df;
23372 case VOID_FTYPE_PV2SF_V4SF:
23373 type = void_ftype_pv2sf_v4sf;
23375 case VOID_FTYPE_PV4DI_V4DI:
23376 type = void_ftype_pv4di_v4di;
23378 case VOID_FTYPE_PV2DI_V2DI:
23379 type = void_ftype_pv2di_v2di;
23381 case VOID_FTYPE_PCHAR_V32QI:
23382 type = void_ftype_pchar_v32qi;
23384 case VOID_FTYPE_PCHAR_V16QI:
23385 type = void_ftype_pchar_v16qi;
23387 case VOID_FTYPE_PFLOAT_V8SF:
23388 type = void_ftype_pfloat_v8sf;
23390 case VOID_FTYPE_PFLOAT_V4SF:
23391 type = void_ftype_pfloat_v4sf;
23393 case VOID_FTYPE_PDOUBLE_V4DF:
23394 type = void_ftype_pdouble_v4df;
23396 case VOID_FTYPE_PDOUBLE_V2DF:
23397 type = void_ftype_pdouble_v2df;
23399 case VOID_FTYPE_PDI_DI:
23400 type = void_ftype_pdi_di;
23402 case VOID_FTYPE_PINT_INT:
23403 type = void_ftype_pint_int;
23405 case VOID_FTYPE_PV8SF_V8SF_V8SF:
23406 type = void_ftype_pv8sf_v8sf_v8sf;
23408 case VOID_FTYPE_PV4DF_V4DF_V4DF:
23409 type = void_ftype_pv4df_v4df_v4df;
23411 case VOID_FTYPE_PV4SF_V4SF_V4SF:
23412 type = void_ftype_pv4sf_v4sf_v4sf;
23414 case VOID_FTYPE_PV2DF_V2DF_V2DF:
23415 type = void_ftype_pv2df_v2df_v2df;
23417 case VOID_FTYPE_USHORT_UINT_USHORT:
23418 type = void_ftype_ushort_unsigned_ushort;
23420 case VOID_FTYPE_UINT_UINT_UINT:
23421 type = void_ftype_unsigned_unsigned_unsigned;
23423 case VOID_FTYPE_UINT64_UINT_UINT:
23424 type = void_ftype_uint64_unsigned_unsigned;
23426 case UCHAR_FTYPE_USHORT_UINT_USHORT:
23427 type = uchar_ftype_ushort_unsigned_ushort;
23429 case UCHAR_FTYPE_UINT_UINT_UINT:
23430 type = uchar_ftype_unsigned_unsigned_unsigned;
23432 case UCHAR_FTYPE_UINT64_UINT_UINT:
23433 type = uchar_ftype_uint64_unsigned_unsigned;
23437 gcc_unreachable ();
23440 def_builtin (d->mask, d->name, type, d->code);
23443 /* Add all builtins with variable number of operands. */
23444 for (i = 0, d = bdesc_args;
23445 i < ARRAY_SIZE (bdesc_args);
23453 switch ((enum ix86_builtin_type) d->flag)
23455 case FLOAT_FTYPE_FLOAT:
23456 type = float_ftype_float;
23458 case INT_FTYPE_V8SF_V8SF_PTEST:
23459 type = int_ftype_v8sf_v8sf;
23461 case INT_FTYPE_V4DI_V4DI_PTEST:
23462 type = int_ftype_v4di_v4di;
23464 case INT_FTYPE_V4DF_V4DF_PTEST:
23465 type = int_ftype_v4df_v4df;
23467 case INT_FTYPE_V4SF_V4SF_PTEST:
23468 type = int_ftype_v4sf_v4sf;
23470 case INT_FTYPE_V2DI_V2DI_PTEST:
23471 type = int_ftype_v2di_v2di;
23473 case INT_FTYPE_V2DF_V2DF_PTEST:
23474 type = int_ftype_v2df_v2df;
23476 case INT_FTYPE_INT:
23477 type = int_ftype_int;
23479 case UINT64_FTYPE_INT:
23480 type = uint64_ftype_int;
23482 case INT64_FTYPE_INT64:
23483 type = int64_ftype_int64;
23485 case INT64_FTYPE_V4SF:
23486 type = int64_ftype_v4sf;
23488 case INT64_FTYPE_V2DF:
23489 type = int64_ftype_v2df;
23491 case INT_FTYPE_V16QI:
23492 type = int_ftype_v16qi;
23494 case INT_FTYPE_V8QI:
23495 type = int_ftype_v8qi;
23497 case INT_FTYPE_V8SF:
23498 type = int_ftype_v8sf;
23500 case INT_FTYPE_V4DF:
23501 type = int_ftype_v4df;
23503 case INT_FTYPE_V4SF:
23504 type = int_ftype_v4sf;
23506 case INT_FTYPE_V2DF:
23507 type = int_ftype_v2df;
23509 case V16QI_FTYPE_V16QI:
23510 type = v16qi_ftype_v16qi;
23512 case V8SI_FTYPE_V8SF:
23513 type = v8si_ftype_v8sf;
23515 case V8SI_FTYPE_V4SI:
23516 type = v8si_ftype_v4si;
23518 case V8HI_FTYPE_V8HI:
23519 type = v8hi_ftype_v8hi;
23521 case V8HI_FTYPE_V16QI:
23522 type = v8hi_ftype_v16qi;
23524 case V8QI_FTYPE_V8QI:
23525 type = v8qi_ftype_v8qi;
23527 case V8SF_FTYPE_V8SF:
23528 type = v8sf_ftype_v8sf;
23530 case V8SF_FTYPE_V8SI:
23531 type = v8sf_ftype_v8si;
23533 case V8SF_FTYPE_V4SF:
23534 type = v8sf_ftype_v4sf;
23536 case V4SI_FTYPE_V4DF:
23537 type = v4si_ftype_v4df;
23539 case V4SI_FTYPE_V4SI:
23540 type = v4si_ftype_v4si;
23542 case V4SI_FTYPE_V16QI:
23543 type = v4si_ftype_v16qi;
23545 case V4SI_FTYPE_V8SI:
23546 type = v4si_ftype_v8si;
23548 case V4SI_FTYPE_V8HI:
23549 type = v4si_ftype_v8hi;
23551 case V4SI_FTYPE_V4SF:
23552 type = v4si_ftype_v4sf;
23554 case V4SI_FTYPE_V2DF:
23555 type = v4si_ftype_v2df;
23557 case V4HI_FTYPE_V4HI:
23558 type = v4hi_ftype_v4hi;
23560 case V4DF_FTYPE_V4DF:
23561 type = v4df_ftype_v4df;
23563 case V4DF_FTYPE_V4SI:
23564 type = v4df_ftype_v4si;
23566 case V4DF_FTYPE_V4SF:
23567 type = v4df_ftype_v4sf;
23569 case V4DF_FTYPE_V2DF:
23570 type = v4df_ftype_v2df;
23572 case V4SF_FTYPE_V4SF:
23573 case V4SF_FTYPE_V4SF_VEC_MERGE:
23574 type = v4sf_ftype_v4sf;
23576 case V4SF_FTYPE_V8SF:
23577 type = v4sf_ftype_v8sf;
23579 case V4SF_FTYPE_V4SI:
23580 type = v4sf_ftype_v4si;
23582 case V4SF_FTYPE_V4DF:
23583 type = v4sf_ftype_v4df;
23585 case V4SF_FTYPE_V2DF:
23586 type = v4sf_ftype_v2df;
23588 case V2DI_FTYPE_V2DI:
23589 type = v2di_ftype_v2di;
23591 case V2DI_FTYPE_V16QI:
23592 type = v2di_ftype_v16qi;
23594 case V2DI_FTYPE_V8HI:
23595 type = v2di_ftype_v8hi;
23597 case V2DI_FTYPE_V4SI:
23598 type = v2di_ftype_v4si;
23600 case V2SI_FTYPE_V2SI:
23601 type = v2si_ftype_v2si;
23603 case V2SI_FTYPE_V4SF:
23604 type = v2si_ftype_v4sf;
23606 case V2SI_FTYPE_V2DF:
23607 type = v2si_ftype_v2df;
23609 case V2SI_FTYPE_V2SF:
23610 type = v2si_ftype_v2sf;
23612 case V2DF_FTYPE_V4DF:
23613 type = v2df_ftype_v4df;
23615 case V2DF_FTYPE_V4SF:
23616 type = v2df_ftype_v4sf;
23618 case V2DF_FTYPE_V2DF:
23619 case V2DF_FTYPE_V2DF_VEC_MERGE:
23620 type = v2df_ftype_v2df;
23622 case V2DF_FTYPE_V2SI:
23623 type = v2df_ftype_v2si;
23625 case V2DF_FTYPE_V4SI:
23626 type = v2df_ftype_v4si;
23628 case V2SF_FTYPE_V2SF:
23629 type = v2sf_ftype_v2sf;
23631 case V2SF_FTYPE_V2SI:
23632 type = v2sf_ftype_v2si;
23634 case V16QI_FTYPE_V16QI_V16QI:
23635 type = v16qi_ftype_v16qi_v16qi;
23637 case V16QI_FTYPE_V8HI_V8HI:
23638 type = v16qi_ftype_v8hi_v8hi;
23640 case V8QI_FTYPE_V8QI_V8QI:
23641 type = v8qi_ftype_v8qi_v8qi;
23643 case V8QI_FTYPE_V4HI_V4HI:
23644 type = v8qi_ftype_v4hi_v4hi;
23646 case V8HI_FTYPE_V8HI_V8HI:
23647 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23648 type = v8hi_ftype_v8hi_v8hi;
23650 case V8HI_FTYPE_V16QI_V16QI:
23651 type = v8hi_ftype_v16qi_v16qi;
23653 case V8HI_FTYPE_V4SI_V4SI:
23654 type = v8hi_ftype_v4si_v4si;
23656 case V8HI_FTYPE_V8HI_SI_COUNT:
23657 type = v8hi_ftype_v8hi_int;
23659 case V8SF_FTYPE_V8SF_V8SF:
23660 type = v8sf_ftype_v8sf_v8sf;
23662 case V8SF_FTYPE_V8SF_V8SI:
23663 type = v8sf_ftype_v8sf_v8si;
23665 case V4SI_FTYPE_V4SI_V4SI:
23666 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23667 type = v4si_ftype_v4si_v4si;
23669 case V4SI_FTYPE_V8HI_V8HI:
23670 type = v4si_ftype_v8hi_v8hi;
23672 case V4SI_FTYPE_V4SF_V4SF:
23673 type = v4si_ftype_v4sf_v4sf;
23675 case V4SI_FTYPE_V2DF_V2DF:
23676 type = v4si_ftype_v2df_v2df;
23678 case V4SI_FTYPE_V4SI_SI_COUNT:
23679 type = v4si_ftype_v4si_int;
23681 case V4HI_FTYPE_V4HI_V4HI:
23682 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23683 type = v4hi_ftype_v4hi_v4hi;
23685 case V4HI_FTYPE_V8QI_V8QI:
23686 type = v4hi_ftype_v8qi_v8qi;
23688 case V4HI_FTYPE_V2SI_V2SI:
23689 type = v4hi_ftype_v2si_v2si;
23691 case V4HI_FTYPE_V4HI_SI_COUNT:
23692 type = v4hi_ftype_v4hi_int;
23694 case V4DF_FTYPE_V4DF_V4DF:
23695 type = v4df_ftype_v4df_v4df;
23697 case V4DF_FTYPE_V4DF_V4DI:
23698 type = v4df_ftype_v4df_v4di;
23700 case V4SF_FTYPE_V4SF_V4SF:
23701 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23702 type = v4sf_ftype_v4sf_v4sf;
23704 case V4SF_FTYPE_V4SF_V4SI:
23705 type = v4sf_ftype_v4sf_v4si;
23707 case V4SF_FTYPE_V4SF_V2SI:
23708 type = v4sf_ftype_v4sf_v2si;
23710 case V4SF_FTYPE_V4SF_V2DF:
23711 type = v4sf_ftype_v4sf_v2df;
23713 case V4SF_FTYPE_V4SF_DI:
23714 type = v4sf_ftype_v4sf_int64;
23716 case V4SF_FTYPE_V4SF_SI:
23717 type = v4sf_ftype_v4sf_int;
23719 case V2DI_FTYPE_V2DI_V2DI:
23720 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23721 type = v2di_ftype_v2di_v2di;
23723 case V2DI_FTYPE_V16QI_V16QI:
23724 type = v2di_ftype_v16qi_v16qi;
23726 case V2DI_FTYPE_V4SI_V4SI:
23727 type = v2di_ftype_v4si_v4si;
23729 case V2DI_FTYPE_V2DI_V16QI:
23730 type = v2di_ftype_v2di_v16qi;
23732 case V2DI_FTYPE_V2DF_V2DF:
23733 type = v2di_ftype_v2df_v2df;
23735 case V2DI_FTYPE_V2DI_SI_COUNT:
23736 type = v2di_ftype_v2di_int;
23738 case V2SI_FTYPE_V2SI_V2SI:
23739 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23740 type = v2si_ftype_v2si_v2si;
23742 case V2SI_FTYPE_V4HI_V4HI:
23743 type = v2si_ftype_v4hi_v4hi;
23745 case V2SI_FTYPE_V2SF_V2SF:
23746 type = v2si_ftype_v2sf_v2sf;
23748 case V2SI_FTYPE_V2SI_SI_COUNT:
23749 type = v2si_ftype_v2si_int;
23751 case V2DF_FTYPE_V2DF_V2DF:
23752 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23753 type = v2df_ftype_v2df_v2df;
23755 case V2DF_FTYPE_V2DF_V4SF:
23756 type = v2df_ftype_v2df_v4sf;
23758 case V2DF_FTYPE_V2DF_V2DI:
23759 type = v2df_ftype_v2df_v2di;
23761 case V2DF_FTYPE_V2DF_DI:
23762 type = v2df_ftype_v2df_int64;
23764 case V2DF_FTYPE_V2DF_SI:
23765 type = v2df_ftype_v2df_int;
23767 case V2SF_FTYPE_V2SF_V2SF:
23768 type = v2sf_ftype_v2sf_v2sf;
23770 case V1DI_FTYPE_V1DI_V1DI:
23771 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23772 type = v1di_ftype_v1di_v1di;
23774 case V1DI_FTYPE_V8QI_V8QI:
23775 type = v1di_ftype_v8qi_v8qi;
23777 case V1DI_FTYPE_V2SI_V2SI:
23778 type = v1di_ftype_v2si_v2si;
23780 case V1DI_FTYPE_V1DI_SI_COUNT:
23781 type = v1di_ftype_v1di_int;
23783 case UINT64_FTYPE_UINT64_UINT64:
23784 type = uint64_ftype_uint64_uint64;
23786 case UINT_FTYPE_UINT_UINT:
23787 type = unsigned_ftype_unsigned_unsigned;
23789 case UINT_FTYPE_UINT_USHORT:
23790 type = unsigned_ftype_unsigned_ushort;
23792 case UINT_FTYPE_UINT_UCHAR:
23793 type = unsigned_ftype_unsigned_uchar;
23795 case UINT16_FTYPE_UINT16_INT:
23796 type = ushort_ftype_ushort_int;
23798 case UINT8_FTYPE_UINT8_INT:
23799 type = uchar_ftype_uchar_int;
23801 case V8HI_FTYPE_V8HI_INT:
23802 type = v8hi_ftype_v8hi_int;
23804 case V8SF_FTYPE_V8SF_INT:
23805 type = v8sf_ftype_v8sf_int;
23807 case V4SI_FTYPE_V4SI_INT:
23808 type = v4si_ftype_v4si_int;
23810 case V4SI_FTYPE_V8SI_INT:
23811 type = v4si_ftype_v8si_int;
23813 case V4HI_FTYPE_V4HI_INT:
23814 type = v4hi_ftype_v4hi_int;
23816 case V4DF_FTYPE_V4DF_INT:
23817 type = v4df_ftype_v4df_int;
23819 case V4SF_FTYPE_V4SF_INT:
23820 type = v4sf_ftype_v4sf_int;
23822 case V4SF_FTYPE_V8SF_INT:
23823 type = v4sf_ftype_v8sf_int;
23825 case V2DI_FTYPE_V2DI_INT:
23826 case V2DI2TI_FTYPE_V2DI_INT:
23827 type = v2di_ftype_v2di_int;
23829 case V2DF_FTYPE_V2DF_INT:
23830 type = v2df_ftype_v2df_int;
23832 case V2DF_FTYPE_V4DF_INT:
23833 type = v2df_ftype_v4df_int;
23835 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23836 type = v16qi_ftype_v16qi_v16qi_v16qi;
23838 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23839 type = v8sf_ftype_v8sf_v8sf_v8sf;
23841 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23842 type = v4df_ftype_v4df_v4df_v4df;
23844 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23845 type = v4sf_ftype_v4sf_v4sf_v4sf;
23847 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23848 type = v2df_ftype_v2df_v2df_v2df;
23850 case V16QI_FTYPE_V16QI_V16QI_INT:
23851 type = v16qi_ftype_v16qi_v16qi_int;
23853 case V8SI_FTYPE_V8SI_V8SI_INT:
23854 type = v8si_ftype_v8si_v8si_int;
23856 case V8SI_FTYPE_V8SI_V4SI_INT:
23857 type = v8si_ftype_v8si_v4si_int;
23859 case V8HI_FTYPE_V8HI_V8HI_INT:
23860 type = v8hi_ftype_v8hi_v8hi_int;
23862 case V8SF_FTYPE_V8SF_V8SF_INT:
23863 type = v8sf_ftype_v8sf_v8sf_int;
23865 case V8SF_FTYPE_V8SF_V4SF_INT:
23866 type = v8sf_ftype_v8sf_v4sf_int;
23868 case V4SI_FTYPE_V4SI_V4SI_INT:
23869 type = v4si_ftype_v4si_v4si_int;
23871 case V4DF_FTYPE_V4DF_V4DF_INT:
23872 type = v4df_ftype_v4df_v4df_int;
23874 case V4DF_FTYPE_V4DF_V2DF_INT:
23875 type = v4df_ftype_v4df_v2df_int;
23877 case V4SF_FTYPE_V4SF_V4SF_INT:
23878 type = v4sf_ftype_v4sf_v4sf_int;
23880 case V2DI_FTYPE_V2DI_V2DI_INT:
23881 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23882 type = v2di_ftype_v2di_v2di_int;
23884 case V2DF_FTYPE_V2DF_V2DF_INT:
23885 type = v2df_ftype_v2df_v2df_int;
23887 case V2DI_FTYPE_V2DI_UINT_UINT:
23888 type = v2di_ftype_v2di_unsigned_unsigned;
23890 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23891 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23893 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23894 type = v1di_ftype_v1di_v1di_int;
23897 gcc_unreachable ();
23900 def_builtin_const (d->mask, d->name, type, d->code);
23903 /* pcmpestr[im] insns. */
23904 for (i = 0, d = bdesc_pcmpestr;
23905 i < ARRAY_SIZE (bdesc_pcmpestr);
23908 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23909 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23911 ftype = int_ftype_v16qi_int_v16qi_int_int;
23912 def_builtin_const (d->mask, d->name, ftype, d->code);
23915 /* pcmpistr[im] insns. */
23916 for (i = 0, d = bdesc_pcmpistr;
23917 i < ARRAY_SIZE (bdesc_pcmpistr);
23920 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23921 ftype = v16qi_ftype_v16qi_v16qi_int;
23923 ftype = int_ftype_v16qi_v16qi_int;
23924 def_builtin_const (d->mask, d->name, ftype, d->code);
23927 /* comi/ucomi insns. */
23928 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23929 if (d->mask == OPTION_MASK_ISA_SSE2)
23930 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23932 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23935 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23936 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23938 /* SSE or 3DNow!A */
23939 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23942 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23944 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23945 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23948 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23949 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23952 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23953 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23954 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23955 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23956 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23957 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23960 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23963 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23964 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23966 /* Access to the vec_init patterns. */
23967 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23968 integer_type_node, NULL_TREE);
23969 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23971 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23972 short_integer_type_node,
23973 short_integer_type_node,
23974 short_integer_type_node, NULL_TREE);
23975 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23977 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23978 char_type_node, char_type_node,
23979 char_type_node, char_type_node,
23980 char_type_node, char_type_node,
23981 char_type_node, NULL_TREE);
23982 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23984 /* Access to the vec_extract patterns. */
23985 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23986 integer_type_node, NULL_TREE);
23987 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23989 ftype = build_function_type_list (long_long_integer_type_node,
23990 V2DI_type_node, integer_type_node,
23992 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23994 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23995 integer_type_node, NULL_TREE);
23996 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23998 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23999 integer_type_node, NULL_TREE);
24000 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
24002 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
24003 integer_type_node, NULL_TREE);
24004 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
24006 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
24007 integer_type_node, NULL_TREE);
24008 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
24010 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
24011 integer_type_node, NULL_TREE);
24012 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
24014 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
24015 integer_type_node, NULL_TREE);
24016 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
24018 /* Access to the vec_set patterns. */
24019 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
24021 integer_type_node, NULL_TREE);
24022 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
24024 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
24026 integer_type_node, NULL_TREE);
24027 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
24029 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
24031 integer_type_node, NULL_TREE);
24032 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
24034 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
24036 integer_type_node, NULL_TREE);
24037 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
24039 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
24041 integer_type_node, NULL_TREE);
24042 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
24044 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
24046 integer_type_node, NULL_TREE);
24047 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
24048 /* Add FMA4 multi-arg argument instructions */
24049 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24051 tree mtype = NULL_TREE;
24056 switch ((enum multi_arg_type)d->flag)
24058 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
24059 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
24060 case MULTI_ARG_3_SF2: mtype = v8sf_ftype_v8sf_v8sf_v8sf; break;
24061 case MULTI_ARG_3_DF2: mtype = v4df_ftype_v4df_v4df_v4df; break;
24062 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
24063 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
24064 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
24065 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
24066 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
24067 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
24068 case MULTI_ARG_3_DI2: mtype = v4di_ftype_v4di_v4di_v4di; break;
24069 case MULTI_ARG_3_SI2: mtype = v8si_ftype_v8si_v8si_v8si; break;
24070 case MULTI_ARG_3_HI2: mtype = v16hi_ftype_v16hi_v16hi_v16hi; break;
24071 case MULTI_ARG_3_QI2: mtype = v32qi_ftype_v32qi_v32qi_v32qi; break;
24072 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
24073 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
24074 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
24075 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
24076 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
24077 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
24078 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
24079 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
24080 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
24081 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
24082 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
24083 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
24084 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
24085 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
24086 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
24087 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
24088 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
24089 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
24090 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
24091 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
24092 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
24093 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
24094 case MULTI_ARG_1_SF2: mtype = v8sf_ftype_v8sf; break;
24095 case MULTI_ARG_1_DF2: mtype = v4df_ftype_v4df; break;
24096 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
24097 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
24098 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
24099 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
24100 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
24101 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
24102 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
24103 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
24104 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
24105 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
24107 case MULTI_ARG_UNKNOWN:
24109 gcc_unreachable ();
24113 def_builtin_const (d->mask, d->name, mtype, d->code);
24117 /* Internal method for ix86_init_builtins. */
24120 ix86_init_builtins_va_builtins_abi (void)
24122 tree ms_va_ref, sysv_va_ref;
24123 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
24124 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
24125 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
24126 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
24130 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
24131 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
24132 ms_va_ref = build_reference_type (ms_va_list_type_node);
24134 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
24137 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24138 fnvoid_va_start_ms =
24139 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24140 fnvoid_va_end_sysv =
24141 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
24142 fnvoid_va_start_sysv =
24143 build_varargs_function_type_list (void_type_node, sysv_va_ref,
24145 fnvoid_va_copy_ms =
24146 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
24148 fnvoid_va_copy_sysv =
24149 build_function_type_list (void_type_node, sysv_va_ref,
24150 sysv_va_ref, NULL_TREE);
24152 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
24153 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
24154 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
24155 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
24156 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
24157 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
24158 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
24159 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24160 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
24161 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24162 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
24163 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24167 ix86_init_builtins (void)
24169 tree float128_type_node = make_node (REAL_TYPE);
24172 /* The __float80 type. */
24173 if (TYPE_MODE (long_double_type_node) == XFmode)
24174 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
24178 /* The __float80 type. */
24179 tree float80_type_node = make_node (REAL_TYPE);
24181 TYPE_PRECISION (float80_type_node) = 80;
24182 layout_type (float80_type_node);
24183 (*lang_hooks.types.register_builtin_type) (float80_type_node,
24187 /* The __float128 type. */
24188 TYPE_PRECISION (float128_type_node) = 128;
24189 layout_type (float128_type_node);
24190 (*lang_hooks.types.register_builtin_type) (float128_type_node,
24193 /* TFmode support builtins. */
24194 ftype = build_function_type (float128_type_node, void_list_node);
24195 decl = add_builtin_function ("__builtin_infq", ftype,
24196 IX86_BUILTIN_INFQ, BUILT_IN_MD,
24198 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
24200 decl = add_builtin_function ("__builtin_huge_valq", ftype,
24201 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
24203 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
24205 /* We will expand them to normal call if SSE2 isn't available since
24206 they are used by libgcc. */
24207 ftype = build_function_type_list (float128_type_node,
24208 float128_type_node,
24210 decl = add_builtin_function ("__builtin_fabsq", ftype,
24211 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
24212 "__fabstf2", NULL_TREE);
24213 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
24214 TREE_READONLY (decl) = 1;
24216 ftype = build_function_type_list (float128_type_node,
24217 float128_type_node,
24218 float128_type_node,
24220 decl = add_builtin_function ("__builtin_copysignq", ftype,
24221 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
24222 "__copysigntf3", NULL_TREE);
24223 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
24224 TREE_READONLY (decl) = 1;
24226 ix86_init_mmx_sse_builtins ();
24228 ix86_init_builtins_va_builtins_abi ();
24231 /* Return the ix86 builtin for CODE. */
24234 ix86_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
24236 if (code >= IX86_BUILTIN_MAX)
24237 return error_mark_node;
24239 return ix86_builtins[code];
24242 /* Errors in the source file can cause expand_expr to return const0_rtx
24243 where we expect a vector. To avoid crashing, use one of the vector
24244 clear instructions. */
24246 safe_vector_operand (rtx x, enum machine_mode mode)
24248 if (x == const0_rtx)
24249 x = CONST0_RTX (mode);
24253 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
24256 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
24259 tree arg0 = CALL_EXPR_ARG (exp, 0);
24260 tree arg1 = CALL_EXPR_ARG (exp, 1);
24261 rtx op0 = expand_normal (arg0);
24262 rtx op1 = expand_normal (arg1);
24263 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24264 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24265 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
24267 if (VECTOR_MODE_P (mode0))
24268 op0 = safe_vector_operand (op0, mode0);
24269 if (VECTOR_MODE_P (mode1))
24270 op1 = safe_vector_operand (op1, mode1);
24272 if (optimize || !target
24273 || GET_MODE (target) != tmode
24274 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24275 target = gen_reg_rtx (tmode);
24277 if (GET_MODE (op1) == SImode && mode1 == TImode)
24279 rtx x = gen_reg_rtx (V4SImode);
24280 emit_insn (gen_sse2_loadd (x, op1));
24281 op1 = gen_lowpart (TImode, x);
24284 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
24285 op0 = copy_to_mode_reg (mode0, op0);
24286 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
24287 op1 = copy_to_mode_reg (mode1, op1);
24289 pat = GEN_FCN (icode) (target, op0, op1);
24298 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
24301 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
24302 enum multi_arg_type m_type,
24303 enum rtx_code sub_code)
24308 bool comparison_p = false;
24310 bool last_arg_constant = false;
24311 int num_memory = 0;
24314 enum machine_mode mode;
24317 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24321 case MULTI_ARG_3_SF:
24322 case MULTI_ARG_3_DF:
24323 case MULTI_ARG_3_SF2:
24324 case MULTI_ARG_3_DF2:
24325 case MULTI_ARG_3_DI:
24326 case MULTI_ARG_3_SI:
24327 case MULTI_ARG_3_SI_DI:
24328 case MULTI_ARG_3_HI:
24329 case MULTI_ARG_3_HI_SI:
24330 case MULTI_ARG_3_QI:
24331 case MULTI_ARG_3_DI2:
24332 case MULTI_ARG_3_SI2:
24333 case MULTI_ARG_3_HI2:
24334 case MULTI_ARG_3_QI2:
24338 case MULTI_ARG_2_SF:
24339 case MULTI_ARG_2_DF:
24340 case MULTI_ARG_2_DI:
24341 case MULTI_ARG_2_SI:
24342 case MULTI_ARG_2_HI:
24343 case MULTI_ARG_2_QI:
24347 case MULTI_ARG_2_DI_IMM:
24348 case MULTI_ARG_2_SI_IMM:
24349 case MULTI_ARG_2_HI_IMM:
24350 case MULTI_ARG_2_QI_IMM:
24352 last_arg_constant = true;
24355 case MULTI_ARG_1_SF:
24356 case MULTI_ARG_1_DF:
24357 case MULTI_ARG_1_SF2:
24358 case MULTI_ARG_1_DF2:
24359 case MULTI_ARG_1_DI:
24360 case MULTI_ARG_1_SI:
24361 case MULTI_ARG_1_HI:
24362 case MULTI_ARG_1_QI:
24363 case MULTI_ARG_1_SI_DI:
24364 case MULTI_ARG_1_HI_DI:
24365 case MULTI_ARG_1_HI_SI:
24366 case MULTI_ARG_1_QI_DI:
24367 case MULTI_ARG_1_QI_SI:
24368 case MULTI_ARG_1_QI_HI:
24372 case MULTI_ARG_2_DI_CMP:
24373 case MULTI_ARG_2_SI_CMP:
24374 case MULTI_ARG_2_HI_CMP:
24375 case MULTI_ARG_2_QI_CMP:
24377 comparison_p = true;
24380 case MULTI_ARG_2_SF_TF:
24381 case MULTI_ARG_2_DF_TF:
24382 case MULTI_ARG_2_DI_TF:
24383 case MULTI_ARG_2_SI_TF:
24384 case MULTI_ARG_2_HI_TF:
24385 case MULTI_ARG_2_QI_TF:
24390 case MULTI_ARG_UNKNOWN:
24392 gcc_unreachable ();
24395 if (optimize || !target
24396 || GET_MODE (target) != tmode
24397 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24398 target = gen_reg_rtx (tmode);
24400 gcc_assert (nargs <= 4);
24402 for (i = 0; i < nargs; i++)
24404 tree arg = CALL_EXPR_ARG (exp, i);
24405 rtx op = expand_normal (arg);
24406 int adjust = (comparison_p) ? 1 : 0;
24407 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
24409 if (last_arg_constant && i == nargs-1)
24411 if (!CONST_INT_P (op))
24413 error ("last argument must be an immediate");
24414 return gen_reg_rtx (tmode);
24419 if (VECTOR_MODE_P (mode))
24420 op = safe_vector_operand (op, mode);
24422 /* If we aren't optimizing, only allow one memory operand to be
24424 if (memory_operand (op, mode))
24427 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
24430 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
24432 op = force_reg (mode, op);
24436 args[i].mode = mode;
24442 pat = GEN_FCN (icode) (target, args[0].op);
24447 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
24448 GEN_INT ((int)sub_code));
24449 else if (! comparison_p)
24450 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24453 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
24457 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
24462 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
24466 gcc_unreachable ();
24476 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
24477 insns with vec_merge. */
24480 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
24484 tree arg0 = CALL_EXPR_ARG (exp, 0);
24485 rtx op1, op0 = expand_normal (arg0);
24486 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24487 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24489 if (optimize || !target
24490 || GET_MODE (target) != tmode
24491 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24492 target = gen_reg_rtx (tmode);
24494 if (VECTOR_MODE_P (mode0))
24495 op0 = safe_vector_operand (op0, mode0);
24497 if ((optimize && !register_operand (op0, mode0))
24498 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
24499 op0 = copy_to_mode_reg (mode0, op0);
24502 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
24503 op1 = copy_to_mode_reg (mode0, op1);
24505 pat = GEN_FCN (icode) (target, op0, op1);
24512 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
24515 ix86_expand_sse_compare (const struct builtin_description *d,
24516 tree exp, rtx target, bool swap)
24519 tree arg0 = CALL_EXPR_ARG (exp, 0);
24520 tree arg1 = CALL_EXPR_ARG (exp, 1);
24521 rtx op0 = expand_normal (arg0);
24522 rtx op1 = expand_normal (arg1);
24524 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
24525 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
24526 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
24527 enum rtx_code comparison = d->comparison;
24529 if (VECTOR_MODE_P (mode0))
24530 op0 = safe_vector_operand (op0, mode0);
24531 if (VECTOR_MODE_P (mode1))
24532 op1 = safe_vector_operand (op1, mode1);
24534 /* Swap operands if we have a comparison that isn't available in
24538 rtx tmp = gen_reg_rtx (mode1);
24539 emit_move_insn (tmp, op1);
24544 if (optimize || !target
24545 || GET_MODE (target) != tmode
24546 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
24547 target = gen_reg_rtx (tmode);
24549 if ((optimize && !register_operand (op0, mode0))
24550 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
24551 op0 = copy_to_mode_reg (mode0, op0);
24552 if ((optimize && !register_operand (op1, mode1))
24553 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
24554 op1 = copy_to_mode_reg (mode1, op1);
24556 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
24557 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
24564 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
24567 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
24571 tree arg0 = CALL_EXPR_ARG (exp, 0);
24572 tree arg1 = CALL_EXPR_ARG (exp, 1);
24573 rtx op0 = expand_normal (arg0);
24574 rtx op1 = expand_normal (arg1);
24575 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24576 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24577 enum rtx_code comparison = d->comparison;
24579 if (VECTOR_MODE_P (mode0))
24580 op0 = safe_vector_operand (op0, mode0);
24581 if (VECTOR_MODE_P (mode1))
24582 op1 = safe_vector_operand (op1, mode1);
24584 /* Swap operands if we have a comparison that isn't available in
24586 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
24593 target = gen_reg_rtx (SImode);
24594 emit_move_insn (target, const0_rtx);
24595 target = gen_rtx_SUBREG (QImode, target, 0);
24597 if ((optimize && !register_operand (op0, mode0))
24598 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24599 op0 = copy_to_mode_reg (mode0, op0);
24600 if ((optimize && !register_operand (op1, mode1))
24601 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24602 op1 = copy_to_mode_reg (mode1, op1);
24604 pat = GEN_FCN (d->icode) (op0, op1);
24608 emit_insn (gen_rtx_SET (VOIDmode,
24609 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24610 gen_rtx_fmt_ee (comparison, QImode,
24614 return SUBREG_REG (target);
24617 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
24620 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
24624 tree arg0 = CALL_EXPR_ARG (exp, 0);
24625 tree arg1 = CALL_EXPR_ARG (exp, 1);
24626 rtx op0 = expand_normal (arg0);
24627 rtx op1 = expand_normal (arg1);
24628 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24629 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24630 enum rtx_code comparison = d->comparison;
24632 if (VECTOR_MODE_P (mode0))
24633 op0 = safe_vector_operand (op0, mode0);
24634 if (VECTOR_MODE_P (mode1))
24635 op1 = safe_vector_operand (op1, mode1);
24637 target = gen_reg_rtx (SImode);
24638 emit_move_insn (target, const0_rtx);
24639 target = gen_rtx_SUBREG (QImode, target, 0);
24641 if ((optimize && !register_operand (op0, mode0))
24642 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24643 op0 = copy_to_mode_reg (mode0, op0);
24644 if ((optimize && !register_operand (op1, mode1))
24645 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24646 op1 = copy_to_mode_reg (mode1, op1);
24648 pat = GEN_FCN (d->icode) (op0, op1);
24652 emit_insn (gen_rtx_SET (VOIDmode,
24653 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24654 gen_rtx_fmt_ee (comparison, QImode,
24658 return SUBREG_REG (target);
24661 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
24664 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
24665 tree exp, rtx target)
24668 tree arg0 = CALL_EXPR_ARG (exp, 0);
24669 tree arg1 = CALL_EXPR_ARG (exp, 1);
24670 tree arg2 = CALL_EXPR_ARG (exp, 2);
24671 tree arg3 = CALL_EXPR_ARG (exp, 3);
24672 tree arg4 = CALL_EXPR_ARG (exp, 4);
24673 rtx scratch0, scratch1;
24674 rtx op0 = expand_normal (arg0);
24675 rtx op1 = expand_normal (arg1);
24676 rtx op2 = expand_normal (arg2);
24677 rtx op3 = expand_normal (arg3);
24678 rtx op4 = expand_normal (arg4);
24679 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
24681 tmode0 = insn_data[d->icode].operand[0].mode;
24682 tmode1 = insn_data[d->icode].operand[1].mode;
24683 modev2 = insn_data[d->icode].operand[2].mode;
24684 modei3 = insn_data[d->icode].operand[3].mode;
24685 modev4 = insn_data[d->icode].operand[4].mode;
24686 modei5 = insn_data[d->icode].operand[5].mode;
24687 modeimm = insn_data[d->icode].operand[6].mode;
24689 if (VECTOR_MODE_P (modev2))
24690 op0 = safe_vector_operand (op0, modev2);
24691 if (VECTOR_MODE_P (modev4))
24692 op2 = safe_vector_operand (op2, modev4);
24694 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24695 op0 = copy_to_mode_reg (modev2, op0);
24696 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24697 op1 = copy_to_mode_reg (modei3, op1);
24698 if ((optimize && !register_operand (op2, modev4))
24699 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24700 op2 = copy_to_mode_reg (modev4, op2);
24701 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24702 op3 = copy_to_mode_reg (modei5, op3);
24704 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24706 error ("the fifth argument must be a 8-bit immediate");
24710 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24712 if (optimize || !target
24713 || GET_MODE (target) != tmode0
24714 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24715 target = gen_reg_rtx (tmode0);
24717 scratch1 = gen_reg_rtx (tmode1);
24719 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24721 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24723 if (optimize || !target
24724 || GET_MODE (target) != tmode1
24725 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24726 target = gen_reg_rtx (tmode1);
24728 scratch0 = gen_reg_rtx (tmode0);
24730 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24734 gcc_assert (d->flag);
24736 scratch0 = gen_reg_rtx (tmode0);
24737 scratch1 = gen_reg_rtx (tmode1);
24739 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24749 target = gen_reg_rtx (SImode);
24750 emit_move_insn (target, const0_rtx);
24751 target = gen_rtx_SUBREG (QImode, target, 0);
24754 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24755 gen_rtx_fmt_ee (EQ, QImode,
24756 gen_rtx_REG ((enum machine_mode) d->flag,
24759 return SUBREG_REG (target);
24766 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24769 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24770 tree exp, rtx target)
24773 tree arg0 = CALL_EXPR_ARG (exp, 0);
24774 tree arg1 = CALL_EXPR_ARG (exp, 1);
24775 tree arg2 = CALL_EXPR_ARG (exp, 2);
24776 rtx scratch0, scratch1;
24777 rtx op0 = expand_normal (arg0);
24778 rtx op1 = expand_normal (arg1);
24779 rtx op2 = expand_normal (arg2);
24780 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24782 tmode0 = insn_data[d->icode].operand[0].mode;
24783 tmode1 = insn_data[d->icode].operand[1].mode;
24784 modev2 = insn_data[d->icode].operand[2].mode;
24785 modev3 = insn_data[d->icode].operand[3].mode;
24786 modeimm = insn_data[d->icode].operand[4].mode;
24788 if (VECTOR_MODE_P (modev2))
24789 op0 = safe_vector_operand (op0, modev2);
24790 if (VECTOR_MODE_P (modev3))
24791 op1 = safe_vector_operand (op1, modev3);
24793 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24794 op0 = copy_to_mode_reg (modev2, op0);
24795 if ((optimize && !register_operand (op1, modev3))
24796 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24797 op1 = copy_to_mode_reg (modev3, op1);
24799 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24801 error ("the third argument must be a 8-bit immediate");
24805 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24807 if (optimize || !target
24808 || GET_MODE (target) != tmode0
24809 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24810 target = gen_reg_rtx (tmode0);
24812 scratch1 = gen_reg_rtx (tmode1);
24814 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24816 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24818 if (optimize || !target
24819 || GET_MODE (target) != tmode1
24820 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24821 target = gen_reg_rtx (tmode1);
24823 scratch0 = gen_reg_rtx (tmode0);
24825 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24829 gcc_assert (d->flag);
24831 scratch0 = gen_reg_rtx (tmode0);
24832 scratch1 = gen_reg_rtx (tmode1);
24834 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24844 target = gen_reg_rtx (SImode);
24845 emit_move_insn (target, const0_rtx);
24846 target = gen_rtx_SUBREG (QImode, target, 0);
24849 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24850 gen_rtx_fmt_ee (EQ, QImode,
24851 gen_rtx_REG ((enum machine_mode) d->flag,
24854 return SUBREG_REG (target);
24860 /* Subroutine of ix86_expand_builtin to take care of insns with
24861 variable number of operands. */
24864 ix86_expand_args_builtin (const struct builtin_description *d,
24865 tree exp, rtx target)
24867 rtx pat, real_target;
24868 unsigned int i, nargs;
24869 unsigned int nargs_constant = 0;
24870 int num_memory = 0;
24874 enum machine_mode mode;
24876 bool last_arg_count = false;
24877 enum insn_code icode = d->icode;
24878 const struct insn_data *insn_p = &insn_data[icode];
24879 enum machine_mode tmode = insn_p->operand[0].mode;
24880 enum machine_mode rmode = VOIDmode;
24882 enum rtx_code comparison = d->comparison;
24884 switch ((enum ix86_builtin_type) d->flag)
24886 case INT_FTYPE_V8SF_V8SF_PTEST:
24887 case INT_FTYPE_V4DI_V4DI_PTEST:
24888 case INT_FTYPE_V4DF_V4DF_PTEST:
24889 case INT_FTYPE_V4SF_V4SF_PTEST:
24890 case INT_FTYPE_V2DI_V2DI_PTEST:
24891 case INT_FTYPE_V2DF_V2DF_PTEST:
24892 return ix86_expand_sse_ptest (d, exp, target);
24893 case FLOAT128_FTYPE_FLOAT128:
24894 case FLOAT_FTYPE_FLOAT:
24895 case INT_FTYPE_INT:
24896 case UINT64_FTYPE_INT:
24897 case INT64_FTYPE_INT64:
24898 case INT64_FTYPE_V4SF:
24899 case INT64_FTYPE_V2DF:
24900 case INT_FTYPE_V16QI:
24901 case INT_FTYPE_V8QI:
24902 case INT_FTYPE_V8SF:
24903 case INT_FTYPE_V4DF:
24904 case INT_FTYPE_V4SF:
24905 case INT_FTYPE_V2DF:
24906 case V16QI_FTYPE_V16QI:
24907 case V8SI_FTYPE_V8SF:
24908 case V8SI_FTYPE_V4SI:
24909 case V8HI_FTYPE_V8HI:
24910 case V8HI_FTYPE_V16QI:
24911 case V8QI_FTYPE_V8QI:
24912 case V8SF_FTYPE_V8SF:
24913 case V8SF_FTYPE_V8SI:
24914 case V8SF_FTYPE_V4SF:
24915 case V4SI_FTYPE_V4SI:
24916 case V4SI_FTYPE_V16QI:
24917 case V4SI_FTYPE_V4SF:
24918 case V4SI_FTYPE_V8SI:
24919 case V4SI_FTYPE_V8HI:
24920 case V4SI_FTYPE_V4DF:
24921 case V4SI_FTYPE_V2DF:
24922 case V4HI_FTYPE_V4HI:
24923 case V4DF_FTYPE_V4DF:
24924 case V4DF_FTYPE_V4SI:
24925 case V4DF_FTYPE_V4SF:
24926 case V4DF_FTYPE_V2DF:
24927 case V4SF_FTYPE_V4SF:
24928 case V4SF_FTYPE_V4SI:
24929 case V4SF_FTYPE_V8SF:
24930 case V4SF_FTYPE_V4DF:
24931 case V4SF_FTYPE_V2DF:
24932 case V2DI_FTYPE_V2DI:
24933 case V2DI_FTYPE_V16QI:
24934 case V2DI_FTYPE_V8HI:
24935 case V2DI_FTYPE_V4SI:
24936 case V2DF_FTYPE_V2DF:
24937 case V2DF_FTYPE_V4SI:
24938 case V2DF_FTYPE_V4DF:
24939 case V2DF_FTYPE_V4SF:
24940 case V2DF_FTYPE_V2SI:
24941 case V2SI_FTYPE_V2SI:
24942 case V2SI_FTYPE_V4SF:
24943 case V2SI_FTYPE_V2SF:
24944 case V2SI_FTYPE_V2DF:
24945 case V2SF_FTYPE_V2SF:
24946 case V2SF_FTYPE_V2SI:
24949 case V4SF_FTYPE_V4SF_VEC_MERGE:
24950 case V2DF_FTYPE_V2DF_VEC_MERGE:
24951 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24952 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24953 case V16QI_FTYPE_V16QI_V16QI:
24954 case V16QI_FTYPE_V8HI_V8HI:
24955 case V8QI_FTYPE_V8QI_V8QI:
24956 case V8QI_FTYPE_V4HI_V4HI:
24957 case V8HI_FTYPE_V8HI_V8HI:
24958 case V8HI_FTYPE_V16QI_V16QI:
24959 case V8HI_FTYPE_V4SI_V4SI:
24960 case V8SF_FTYPE_V8SF_V8SF:
24961 case V8SF_FTYPE_V8SF_V8SI:
24962 case V4SI_FTYPE_V4SI_V4SI:
24963 case V4SI_FTYPE_V8HI_V8HI:
24964 case V4SI_FTYPE_V4SF_V4SF:
24965 case V4SI_FTYPE_V2DF_V2DF:
24966 case V4HI_FTYPE_V4HI_V4HI:
24967 case V4HI_FTYPE_V8QI_V8QI:
24968 case V4HI_FTYPE_V2SI_V2SI:
24969 case V4DF_FTYPE_V4DF_V4DF:
24970 case V4DF_FTYPE_V4DF_V4DI:
24971 case V4SF_FTYPE_V4SF_V4SF:
24972 case V4SF_FTYPE_V4SF_V4SI:
24973 case V4SF_FTYPE_V4SF_V2SI:
24974 case V4SF_FTYPE_V4SF_V2DF:
24975 case V4SF_FTYPE_V4SF_DI:
24976 case V4SF_FTYPE_V4SF_SI:
24977 case V2DI_FTYPE_V2DI_V2DI:
24978 case V2DI_FTYPE_V16QI_V16QI:
24979 case V2DI_FTYPE_V4SI_V4SI:
24980 case V2DI_FTYPE_V2DI_V16QI:
24981 case V2DI_FTYPE_V2DF_V2DF:
24982 case V2SI_FTYPE_V2SI_V2SI:
24983 case V2SI_FTYPE_V4HI_V4HI:
24984 case V2SI_FTYPE_V2SF_V2SF:
24985 case V2DF_FTYPE_V2DF_V2DF:
24986 case V2DF_FTYPE_V2DF_V4SF:
24987 case V2DF_FTYPE_V2DF_V2DI:
24988 case V2DF_FTYPE_V2DF_DI:
24989 case V2DF_FTYPE_V2DF_SI:
24990 case V2SF_FTYPE_V2SF_V2SF:
24991 case V1DI_FTYPE_V1DI_V1DI:
24992 case V1DI_FTYPE_V8QI_V8QI:
24993 case V1DI_FTYPE_V2SI_V2SI:
24994 if (comparison == UNKNOWN)
24995 return ix86_expand_binop_builtin (icode, exp, target);
24998 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24999 case V2DF_FTYPE_V2DF_V2DF_SWAP:
25000 gcc_assert (comparison != UNKNOWN);
25004 case V8HI_FTYPE_V8HI_V8HI_COUNT:
25005 case V8HI_FTYPE_V8HI_SI_COUNT:
25006 case V4SI_FTYPE_V4SI_V4SI_COUNT:
25007 case V4SI_FTYPE_V4SI_SI_COUNT:
25008 case V4HI_FTYPE_V4HI_V4HI_COUNT:
25009 case V4HI_FTYPE_V4HI_SI_COUNT:
25010 case V2DI_FTYPE_V2DI_V2DI_COUNT:
25011 case V2DI_FTYPE_V2DI_SI_COUNT:
25012 case V2SI_FTYPE_V2SI_V2SI_COUNT:
25013 case V2SI_FTYPE_V2SI_SI_COUNT:
25014 case V1DI_FTYPE_V1DI_V1DI_COUNT:
25015 case V1DI_FTYPE_V1DI_SI_COUNT:
25017 last_arg_count = true;
25019 case UINT64_FTYPE_UINT64_UINT64:
25020 case UINT_FTYPE_UINT_UINT:
25021 case UINT_FTYPE_UINT_USHORT:
25022 case UINT_FTYPE_UINT_UCHAR:
25023 case UINT16_FTYPE_UINT16_INT:
25024 case UINT8_FTYPE_UINT8_INT:
25027 case V2DI2TI_FTYPE_V2DI_INT:
25030 nargs_constant = 1;
25032 case V8HI_FTYPE_V8HI_INT:
25033 case V8SF_FTYPE_V8SF_INT:
25034 case V4SI_FTYPE_V4SI_INT:
25035 case V4SI_FTYPE_V8SI_INT:
25036 case V4HI_FTYPE_V4HI_INT:
25037 case V4DF_FTYPE_V4DF_INT:
25038 case V4SF_FTYPE_V4SF_INT:
25039 case V4SF_FTYPE_V8SF_INT:
25040 case V2DI_FTYPE_V2DI_INT:
25041 case V2DF_FTYPE_V2DF_INT:
25042 case V2DF_FTYPE_V4DF_INT:
25044 nargs_constant = 1;
25046 case V16QI_FTYPE_V16QI_V16QI_V16QI:
25047 case V8SF_FTYPE_V8SF_V8SF_V8SF:
25048 case V4DF_FTYPE_V4DF_V4DF_V4DF:
25049 case V4SF_FTYPE_V4SF_V4SF_V4SF:
25050 case V2DF_FTYPE_V2DF_V2DF_V2DF:
25053 case V16QI_FTYPE_V16QI_V16QI_INT:
25054 case V8HI_FTYPE_V8HI_V8HI_INT:
25055 case V8SI_FTYPE_V8SI_V8SI_INT:
25056 case V8SI_FTYPE_V8SI_V4SI_INT:
25057 case V8SF_FTYPE_V8SF_V8SF_INT:
25058 case V8SF_FTYPE_V8SF_V4SF_INT:
25059 case V4SI_FTYPE_V4SI_V4SI_INT:
25060 case V4DF_FTYPE_V4DF_V4DF_INT:
25061 case V4DF_FTYPE_V4DF_V2DF_INT:
25062 case V4SF_FTYPE_V4SF_V4SF_INT:
25063 case V2DI_FTYPE_V2DI_V2DI_INT:
25064 case V2DF_FTYPE_V2DF_V2DF_INT:
25066 nargs_constant = 1;
25068 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
25071 nargs_constant = 1;
25073 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
25076 nargs_constant = 1;
25078 case V2DI_FTYPE_V2DI_UINT_UINT:
25080 nargs_constant = 2;
25082 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
25084 nargs_constant = 2;
25087 gcc_unreachable ();
25090 gcc_assert (nargs <= ARRAY_SIZE (args));
25092 if (comparison != UNKNOWN)
25094 gcc_assert (nargs == 2);
25095 return ix86_expand_sse_compare (d, exp, target, swap);
25098 if (rmode == VOIDmode || rmode == tmode)
25102 || GET_MODE (target) != tmode
25103 || ! (*insn_p->operand[0].predicate) (target, tmode))
25104 target = gen_reg_rtx (tmode);
25105 real_target = target;
25109 target = gen_reg_rtx (rmode);
25110 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
25113 for (i = 0; i < nargs; i++)
25115 tree arg = CALL_EXPR_ARG (exp, i);
25116 rtx op = expand_normal (arg);
25117 enum machine_mode mode = insn_p->operand[i + 1].mode;
25118 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
25120 if (last_arg_count && (i + 1) == nargs)
25122 /* SIMD shift insns take either an 8-bit immediate or
25123 register as count. But builtin functions take int as
25124 count. If count doesn't match, we put it in register. */
25127 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
25128 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
25129 op = copy_to_reg (op);
25132 else if ((nargs - i) <= nargs_constant)
25137 case CODE_FOR_sse4_1_roundpd:
25138 case CODE_FOR_sse4_1_roundps:
25139 case CODE_FOR_sse4_1_roundsd:
25140 case CODE_FOR_sse4_1_roundss:
25141 case CODE_FOR_sse4_1_blendps:
25142 case CODE_FOR_avx_blendpd256:
25143 case CODE_FOR_avx_vpermilv4df:
25144 case CODE_FOR_avx_roundpd256:
25145 case CODE_FOR_avx_roundps256:
25146 error ("the last argument must be a 4-bit immediate");
25149 case CODE_FOR_sse4_1_blendpd:
25150 case CODE_FOR_avx_vpermilv2df:
25151 error ("the last argument must be a 2-bit immediate");
25154 case CODE_FOR_avx_vextractf128v4df:
25155 case CODE_FOR_avx_vextractf128v8sf:
25156 case CODE_FOR_avx_vextractf128v8si:
25157 case CODE_FOR_avx_vinsertf128v4df:
25158 case CODE_FOR_avx_vinsertf128v8sf:
25159 case CODE_FOR_avx_vinsertf128v8si:
25160 error ("the last argument must be a 1-bit immediate");
25163 case CODE_FOR_avx_cmpsdv2df3:
25164 case CODE_FOR_avx_cmpssv4sf3:
25165 case CODE_FOR_avx_cmppdv2df3:
25166 case CODE_FOR_avx_cmppsv4sf3:
25167 case CODE_FOR_avx_cmppdv4df3:
25168 case CODE_FOR_avx_cmppsv8sf3:
25169 error ("the last argument must be a 5-bit immediate");
25173 switch (nargs_constant)
25176 if ((nargs - i) == nargs_constant)
25178 error ("the next to last argument must be an 8-bit immediate");
25182 error ("the last argument must be an 8-bit immediate");
25185 gcc_unreachable ();
25192 if (VECTOR_MODE_P (mode))
25193 op = safe_vector_operand (op, mode);
25195 /* If we aren't optimizing, only allow one memory operand to
25197 if (memory_operand (op, mode))
25200 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
25202 if (optimize || !match || num_memory > 1)
25203 op = copy_to_mode_reg (mode, op);
25207 op = copy_to_reg (op);
25208 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
25213 args[i].mode = mode;
25219 pat = GEN_FCN (icode) (real_target, args[0].op);
25222 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
25225 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25229 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25230 args[2].op, args[3].op);
25233 gcc_unreachable ();
25243 /* Subroutine of ix86_expand_builtin to take care of special insns
25244 with variable number of operands. */
25247 ix86_expand_special_args_builtin (const struct builtin_description *d,
25248 tree exp, rtx target)
25252 unsigned int i, nargs, arg_adjust, memory;
25256 enum machine_mode mode;
25258 enum insn_code icode = d->icode;
25259 bool last_arg_constant = false;
25260 const struct insn_data *insn_p = &insn_data[icode];
25261 enum machine_mode tmode = insn_p->operand[0].mode;
25262 enum { load, store } klass;
25264 switch ((enum ix86_special_builtin_type) d->flag)
25266 case VOID_FTYPE_VOID:
25267 emit_insn (GEN_FCN (icode) (target));
25269 case UINT64_FTYPE_VOID:
25274 case UINT64_FTYPE_PUNSIGNED:
25275 case V2DI_FTYPE_PV2DI:
25276 case V32QI_FTYPE_PCCHAR:
25277 case V16QI_FTYPE_PCCHAR:
25278 case V8SF_FTYPE_PCV4SF:
25279 case V8SF_FTYPE_PCFLOAT:
25280 case V4SF_FTYPE_PCFLOAT:
25281 case V4DF_FTYPE_PCV2DF:
25282 case V4DF_FTYPE_PCDOUBLE:
25283 case V2DF_FTYPE_PCDOUBLE:
25288 case VOID_FTYPE_PV2SF_V4SF:
25289 case VOID_FTYPE_PV4DI_V4DI:
25290 case VOID_FTYPE_PV2DI_V2DI:
25291 case VOID_FTYPE_PCHAR_V32QI:
25292 case VOID_FTYPE_PCHAR_V16QI:
25293 case VOID_FTYPE_PFLOAT_V8SF:
25294 case VOID_FTYPE_PFLOAT_V4SF:
25295 case VOID_FTYPE_PDOUBLE_V4DF:
25296 case VOID_FTYPE_PDOUBLE_V2DF:
25297 case VOID_FTYPE_PDI_DI:
25298 case VOID_FTYPE_PINT_INT:
25301 /* Reserve memory operand for target. */
25302 memory = ARRAY_SIZE (args);
25304 case V4SF_FTYPE_V4SF_PCV2SF:
25305 case V2DF_FTYPE_V2DF_PCDOUBLE:
25310 case V8SF_FTYPE_PCV8SF_V8SF:
25311 case V4DF_FTYPE_PCV4DF_V4DF:
25312 case V4SF_FTYPE_PCV4SF_V4SF:
25313 case V2DF_FTYPE_PCV2DF_V2DF:
25318 case VOID_FTYPE_PV8SF_V8SF_V8SF:
25319 case VOID_FTYPE_PV4DF_V4DF_V4DF:
25320 case VOID_FTYPE_PV4SF_V4SF_V4SF:
25321 case VOID_FTYPE_PV2DF_V2DF_V2DF:
25324 /* Reserve memory operand for target. */
25325 memory = ARRAY_SIZE (args);
25327 case VOID_FTYPE_USHORT_UINT_USHORT:
25328 case VOID_FTYPE_UINT_UINT_UINT:
25329 case VOID_FTYPE_UINT64_UINT_UINT:
25330 case UCHAR_FTYPE_USHORT_UINT_USHORT:
25331 case UCHAR_FTYPE_UINT_UINT_UINT:
25332 case UCHAR_FTYPE_UINT64_UINT_UINT:
25338 gcc_unreachable ();
25341 gcc_assert (nargs <= ARRAY_SIZE (args));
25343 if (klass == store)
25345 arg = CALL_EXPR_ARG (exp, 0);
25346 op = expand_normal (arg);
25347 gcc_assert (target == 0);
25348 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
25356 || GET_MODE (target) != tmode
25357 || ! (*insn_p->operand[0].predicate) (target, tmode))
25358 target = gen_reg_rtx (tmode);
25361 for (i = 0; i < nargs; i++)
25363 enum machine_mode mode = insn_p->operand[i + 1].mode;
25366 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
25367 op = expand_normal (arg);
25368 match = (*insn_p->operand[i + 1].predicate) (op, mode);
25370 if (last_arg_constant && (i + 1) == nargs)
25376 error ("the last argument must be an 8-bit immediate");
25384 /* This must be the memory operand. */
25385 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
25386 gcc_assert (GET_MODE (op) == mode
25387 || GET_MODE (op) == VOIDmode);
25391 /* This must be register. */
25392 if (VECTOR_MODE_P (mode))
25393 op = safe_vector_operand (op, mode);
25395 gcc_assert (GET_MODE (op) == mode
25396 || GET_MODE (op) == VOIDmode);
25397 op = copy_to_mode_reg (mode, op);
25402 args[i].mode = mode;
25408 pat = GEN_FCN (icode) (target);
25411 pat = GEN_FCN (icode) (target, args[0].op);
25414 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
25417 gcc_unreachable ();
25423 return klass == store ? 0 : target;
25426 /* Return the integer constant in ARG. Constrain it to be in the range
25427 of the subparts of VEC_TYPE; issue an error if not. */
25430 get_element_number (tree vec_type, tree arg)
25432 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
25434 if (!host_integerp (arg, 1)
25435 || (elt = tree_low_cst (arg, 1), elt > max))
25437 error ("selector must be an integer constant in the range 0..%wi", max);
25444 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25445 ix86_expand_vector_init. We DO have language-level syntax for this, in
25446 the form of (type){ init-list }. Except that since we can't place emms
25447 instructions from inside the compiler, we can't allow the use of MMX
25448 registers unless the user explicitly asks for it. So we do *not* define
25449 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
25450 we have builtins invoked by mmintrin.h that gives us license to emit
25451 these sorts of instructions. */
25454 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
25456 enum machine_mode tmode = TYPE_MODE (type);
25457 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
25458 int i, n_elt = GET_MODE_NUNITS (tmode);
25459 rtvec v = rtvec_alloc (n_elt);
25461 gcc_assert (VECTOR_MODE_P (tmode));
25462 gcc_assert (call_expr_nargs (exp) == n_elt);
25464 for (i = 0; i < n_elt; ++i)
25466 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
25467 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
25470 if (!target || !register_operand (target, tmode))
25471 target = gen_reg_rtx (tmode);
25473 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
25477 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25478 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
25479 had a language-level syntax for referencing vector elements. */
25482 ix86_expand_vec_ext_builtin (tree exp, rtx target)
25484 enum machine_mode tmode, mode0;
25489 arg0 = CALL_EXPR_ARG (exp, 0);
25490 arg1 = CALL_EXPR_ARG (exp, 1);
25492 op0 = expand_normal (arg0);
25493 elt = get_element_number (TREE_TYPE (arg0), arg1);
25495 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25496 mode0 = TYPE_MODE (TREE_TYPE (arg0));
25497 gcc_assert (VECTOR_MODE_P (mode0));
25499 op0 = force_reg (mode0, op0);
25501 if (optimize || !target || !register_operand (target, tmode))
25502 target = gen_reg_rtx (tmode);
25504 ix86_expand_vector_extract (true, target, op0, elt);
25509 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25510 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
25511 a language-level syntax for referencing vector elements. */
25514 ix86_expand_vec_set_builtin (tree exp)
25516 enum machine_mode tmode, mode1;
25517 tree arg0, arg1, arg2;
25519 rtx op0, op1, target;
25521 arg0 = CALL_EXPR_ARG (exp, 0);
25522 arg1 = CALL_EXPR_ARG (exp, 1);
25523 arg2 = CALL_EXPR_ARG (exp, 2);
25525 tmode = TYPE_MODE (TREE_TYPE (arg0));
25526 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25527 gcc_assert (VECTOR_MODE_P (tmode));
25529 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
25530 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
25531 elt = get_element_number (TREE_TYPE (arg0), arg2);
25533 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
25534 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
25536 op0 = force_reg (tmode, op0);
25537 op1 = force_reg (mode1, op1);
25539 /* OP0 is the source of these builtin functions and shouldn't be
25540 modified. Create a copy, use it and return it as target. */
25541 target = gen_reg_rtx (tmode);
25542 emit_move_insn (target, op0);
25543 ix86_expand_vector_set (true, target, op1, elt);
25548 /* Expand an expression EXP that calls a built-in function,
25549 with result going to TARGET if that's convenient
25550 (and in mode MODE if that's convenient).
25551 SUBTARGET may be used as the target for computing one of EXP's operands.
25552 IGNORE is nonzero if the value is to be ignored. */
25555 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
25556 enum machine_mode mode ATTRIBUTE_UNUSED,
25557 int ignore ATTRIBUTE_UNUSED)
25559 const struct builtin_description *d;
25561 enum insn_code icode;
25562 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
25563 tree arg0, arg1, arg2;
25564 rtx op0, op1, op2, pat;
25565 enum machine_mode mode0, mode1, mode2;
25566 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
25568 /* Determine whether the builtin function is available under the current ISA.
25569 Originally the builtin was not created if it wasn't applicable to the
25570 current ISA based on the command line switches. With function specific
25571 options, we need to check in the context of the function making the call
25572 whether it is supported. */
25573 if (ix86_builtins_isa[fcode].isa
25574 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
25576 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
25577 NULL, NULL, false);
25580 error ("%qE needs unknown isa option", fndecl);
25583 gcc_assert (opts != NULL);
25584 error ("%qE needs isa option %s", fndecl, opts);
25592 case IX86_BUILTIN_MASKMOVQ:
25593 case IX86_BUILTIN_MASKMOVDQU:
25594 icode = (fcode == IX86_BUILTIN_MASKMOVQ
25595 ? CODE_FOR_mmx_maskmovq
25596 : CODE_FOR_sse2_maskmovdqu);
25597 /* Note the arg order is different from the operand order. */
25598 arg1 = CALL_EXPR_ARG (exp, 0);
25599 arg2 = CALL_EXPR_ARG (exp, 1);
25600 arg0 = CALL_EXPR_ARG (exp, 2);
25601 op0 = expand_normal (arg0);
25602 op1 = expand_normal (arg1);
25603 op2 = expand_normal (arg2);
25604 mode0 = insn_data[icode].operand[0].mode;
25605 mode1 = insn_data[icode].operand[1].mode;
25606 mode2 = insn_data[icode].operand[2].mode;
25608 op0 = force_reg (Pmode, op0);
25609 op0 = gen_rtx_MEM (mode1, op0);
25611 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
25612 op0 = copy_to_mode_reg (mode0, op0);
25613 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
25614 op1 = copy_to_mode_reg (mode1, op1);
25615 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
25616 op2 = copy_to_mode_reg (mode2, op2);
25617 pat = GEN_FCN (icode) (op0, op1, op2);
25623 case IX86_BUILTIN_LDMXCSR:
25624 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
25625 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25626 emit_move_insn (target, op0);
25627 emit_insn (gen_sse_ldmxcsr (target));
25630 case IX86_BUILTIN_STMXCSR:
25631 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25632 emit_insn (gen_sse_stmxcsr (target));
25633 return copy_to_mode_reg (SImode, target);
25635 case IX86_BUILTIN_CLFLUSH:
25636 arg0 = CALL_EXPR_ARG (exp, 0);
25637 op0 = expand_normal (arg0);
25638 icode = CODE_FOR_sse2_clflush;
25639 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
25640 op0 = copy_to_mode_reg (Pmode, op0);
25642 emit_insn (gen_sse2_clflush (op0));
25645 case IX86_BUILTIN_MONITOR:
25646 arg0 = CALL_EXPR_ARG (exp, 0);
25647 arg1 = CALL_EXPR_ARG (exp, 1);
25648 arg2 = CALL_EXPR_ARG (exp, 2);
25649 op0 = expand_normal (arg0);
25650 op1 = expand_normal (arg1);
25651 op2 = expand_normal (arg2);
25653 op0 = copy_to_mode_reg (Pmode, op0);
25655 op1 = copy_to_mode_reg (SImode, op1);
25657 op2 = copy_to_mode_reg (SImode, op2);
25658 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
25661 case IX86_BUILTIN_MWAIT:
25662 arg0 = CALL_EXPR_ARG (exp, 0);
25663 arg1 = CALL_EXPR_ARG (exp, 1);
25664 op0 = expand_normal (arg0);
25665 op1 = expand_normal (arg1);
25667 op0 = copy_to_mode_reg (SImode, op0);
25669 op1 = copy_to_mode_reg (SImode, op1);
25670 emit_insn (gen_sse3_mwait (op0, op1));
25673 case IX86_BUILTIN_VEC_INIT_V2SI:
25674 case IX86_BUILTIN_VEC_INIT_V4HI:
25675 case IX86_BUILTIN_VEC_INIT_V8QI:
25676 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
25678 case IX86_BUILTIN_VEC_EXT_V2DF:
25679 case IX86_BUILTIN_VEC_EXT_V2DI:
25680 case IX86_BUILTIN_VEC_EXT_V4SF:
25681 case IX86_BUILTIN_VEC_EXT_V4SI:
25682 case IX86_BUILTIN_VEC_EXT_V8HI:
25683 case IX86_BUILTIN_VEC_EXT_V2SI:
25684 case IX86_BUILTIN_VEC_EXT_V4HI:
25685 case IX86_BUILTIN_VEC_EXT_V16QI:
25686 return ix86_expand_vec_ext_builtin (exp, target);
25688 case IX86_BUILTIN_VEC_SET_V2DI:
25689 case IX86_BUILTIN_VEC_SET_V4SF:
25690 case IX86_BUILTIN_VEC_SET_V4SI:
25691 case IX86_BUILTIN_VEC_SET_V8HI:
25692 case IX86_BUILTIN_VEC_SET_V4HI:
25693 case IX86_BUILTIN_VEC_SET_V16QI:
25694 return ix86_expand_vec_set_builtin (exp);
25696 case IX86_BUILTIN_INFQ:
25697 case IX86_BUILTIN_HUGE_VALQ:
25699 REAL_VALUE_TYPE inf;
25703 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
25705 tmp = validize_mem (force_const_mem (mode, tmp));
25708 target = gen_reg_rtx (mode);
25710 emit_move_insn (target, tmp);
25718 for (i = 0, d = bdesc_special_args;
25719 i < ARRAY_SIZE (bdesc_special_args);
25721 if (d->code == fcode)
25722 return ix86_expand_special_args_builtin (d, exp, target);
25724 for (i = 0, d = bdesc_args;
25725 i < ARRAY_SIZE (bdesc_args);
25727 if (d->code == fcode)
25730 case IX86_BUILTIN_FABSQ:
25731 case IX86_BUILTIN_COPYSIGNQ:
25733 /* Emit a normal call if SSE2 isn't available. */
25734 return expand_call (exp, target, ignore);
25736 return ix86_expand_args_builtin (d, exp, target);
25739 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25740 if (d->code == fcode)
25741 return ix86_expand_sse_comi (d, exp, target);
25743 for (i = 0, d = bdesc_pcmpestr;
25744 i < ARRAY_SIZE (bdesc_pcmpestr);
25746 if (d->code == fcode)
25747 return ix86_expand_sse_pcmpestr (d, exp, target);
25749 for (i = 0, d = bdesc_pcmpistr;
25750 i < ARRAY_SIZE (bdesc_pcmpistr);
25752 if (d->code == fcode)
25753 return ix86_expand_sse_pcmpistr (d, exp, target);
25755 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25756 if (d->code == fcode)
25757 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25758 (enum multi_arg_type)d->flag,
25761 gcc_unreachable ();
25764 /* Returns a function decl for a vectorized version of the builtin function
25765 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25766 if it is not available. */
25769 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25772 enum machine_mode in_mode, out_mode;
25775 if (TREE_CODE (type_out) != VECTOR_TYPE
25776 || TREE_CODE (type_in) != VECTOR_TYPE)
25779 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25780 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25781 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25782 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25786 case BUILT_IN_SQRT:
25787 if (out_mode == DFmode && out_n == 2
25788 && in_mode == DFmode && in_n == 2)
25789 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25792 case BUILT_IN_SQRTF:
25793 if (out_mode == SFmode && out_n == 4
25794 && in_mode == SFmode && in_n == 4)
25795 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25798 case BUILT_IN_LRINT:
25799 if (out_mode == SImode && out_n == 4
25800 && in_mode == DFmode && in_n == 2)
25801 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25804 case BUILT_IN_LRINTF:
25805 if (out_mode == SImode && out_n == 4
25806 && in_mode == SFmode && in_n == 4)
25807 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25810 case BUILT_IN_COPYSIGN:
25811 if (out_mode == DFmode && out_n == 2
25812 && in_mode == DFmode && in_n == 2)
25813 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
25816 case BUILT_IN_COPYSIGNF:
25817 if (out_mode == SFmode && out_n == 4
25818 && in_mode == SFmode && in_n == 4)
25819 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
25826 /* Dispatch to a handler for a vectorization library. */
25827 if (ix86_veclib_handler)
25828 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
25834 /* Handler for an SVML-style interface to
25835 a library with vectorized intrinsics. */
25838 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25841 tree fntype, new_fndecl, args;
25844 enum machine_mode el_mode, in_mode;
25847 /* The SVML is suitable for unsafe math only. */
25848 if (!flag_unsafe_math_optimizations)
25851 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25852 n = TYPE_VECTOR_SUBPARTS (type_out);
25853 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25854 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25855 if (el_mode != in_mode
25863 case BUILT_IN_LOG10:
25865 case BUILT_IN_TANH:
25867 case BUILT_IN_ATAN:
25868 case BUILT_IN_ATAN2:
25869 case BUILT_IN_ATANH:
25870 case BUILT_IN_CBRT:
25871 case BUILT_IN_SINH:
25873 case BUILT_IN_ASINH:
25874 case BUILT_IN_ASIN:
25875 case BUILT_IN_COSH:
25877 case BUILT_IN_ACOSH:
25878 case BUILT_IN_ACOS:
25879 if (el_mode != DFmode || n != 2)
25883 case BUILT_IN_EXPF:
25884 case BUILT_IN_LOGF:
25885 case BUILT_IN_LOG10F:
25886 case BUILT_IN_POWF:
25887 case BUILT_IN_TANHF:
25888 case BUILT_IN_TANF:
25889 case BUILT_IN_ATANF:
25890 case BUILT_IN_ATAN2F:
25891 case BUILT_IN_ATANHF:
25892 case BUILT_IN_CBRTF:
25893 case BUILT_IN_SINHF:
25894 case BUILT_IN_SINF:
25895 case BUILT_IN_ASINHF:
25896 case BUILT_IN_ASINF:
25897 case BUILT_IN_COSHF:
25898 case BUILT_IN_COSF:
25899 case BUILT_IN_ACOSHF:
25900 case BUILT_IN_ACOSF:
25901 if (el_mode != SFmode || n != 4)
25909 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25911 if (fn == BUILT_IN_LOGF)
25912 strcpy (name, "vmlsLn4");
25913 else if (fn == BUILT_IN_LOG)
25914 strcpy (name, "vmldLn2");
25917 sprintf (name, "vmls%s", bname+10);
25918 name[strlen (name)-1] = '4';
25921 sprintf (name, "vmld%s2", bname+10);
25923 /* Convert to uppercase. */
25927 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25928 args = TREE_CHAIN (args))
25932 fntype = build_function_type_list (type_out, type_in, NULL);
25934 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25936 /* Build a function declaration for the vectorized function. */
25937 new_fndecl = build_decl (BUILTINS_LOCATION,
25938 FUNCTION_DECL, get_identifier (name), fntype);
25939 TREE_PUBLIC (new_fndecl) = 1;
25940 DECL_EXTERNAL (new_fndecl) = 1;
25941 DECL_IS_NOVOPS (new_fndecl) = 1;
25942 TREE_READONLY (new_fndecl) = 1;
25947 /* Handler for an ACML-style interface to
25948 a library with vectorized intrinsics. */
25951 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25953 char name[20] = "__vr.._";
25954 tree fntype, new_fndecl, args;
25957 enum machine_mode el_mode, in_mode;
25960 /* The ACML is 64bits only and suitable for unsafe math only as
25961 it does not correctly support parts of IEEE with the required
25962 precision such as denormals. */
25964 || !flag_unsafe_math_optimizations)
25967 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25968 n = TYPE_VECTOR_SUBPARTS (type_out);
25969 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25970 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25971 if (el_mode != in_mode
25981 case BUILT_IN_LOG2:
25982 case BUILT_IN_LOG10:
25985 if (el_mode != DFmode
25990 case BUILT_IN_SINF:
25991 case BUILT_IN_COSF:
25992 case BUILT_IN_EXPF:
25993 case BUILT_IN_POWF:
25994 case BUILT_IN_LOGF:
25995 case BUILT_IN_LOG2F:
25996 case BUILT_IN_LOG10F:
25999 if (el_mode != SFmode
26008 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
26009 sprintf (name + 7, "%s", bname+10);
26012 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
26013 args = TREE_CHAIN (args))
26017 fntype = build_function_type_list (type_out, type_in, NULL);
26019 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
26021 /* Build a function declaration for the vectorized function. */
26022 new_fndecl = build_decl (BUILTINS_LOCATION,
26023 FUNCTION_DECL, get_identifier (name), fntype);
26024 TREE_PUBLIC (new_fndecl) = 1;
26025 DECL_EXTERNAL (new_fndecl) = 1;
26026 DECL_IS_NOVOPS (new_fndecl) = 1;
26027 TREE_READONLY (new_fndecl) = 1;
26033 /* Returns a decl of a function that implements conversion of an integer vector
26034 into a floating-point vector, or vice-versa. TYPE is the type of the integer
26035 side of the conversion.
26036 Return NULL_TREE if it is not available. */
26039 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
26041 if (! (TARGET_SSE2 && TREE_CODE (type) == VECTOR_TYPE))
26047 switch (TYPE_MODE (type))
26050 return TYPE_UNSIGNED (type)
26051 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
26052 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
26057 case FIX_TRUNC_EXPR:
26058 switch (TYPE_MODE (type))
26061 return TYPE_UNSIGNED (type)
26063 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
26073 /* Returns a code for a target-specific builtin that implements
26074 reciprocal of the function, or NULL_TREE if not available. */
26077 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
26078 bool sqrt ATTRIBUTE_UNUSED)
26080 if (! (TARGET_SSE_MATH && !optimize_insn_for_size_p ()
26081 && flag_finite_math_only && !flag_trapping_math
26082 && flag_unsafe_math_optimizations))
26086 /* Machine dependent builtins. */
26089 /* Vectorized version of sqrt to rsqrt conversion. */
26090 case IX86_BUILTIN_SQRTPS_NR:
26091 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
26097 /* Normal builtins. */
26100 /* Sqrt to rsqrt conversion. */
26101 case BUILT_IN_SQRTF:
26102 return ix86_builtins[IX86_BUILTIN_RSQRTF];
26109 /* Store OPERAND to the memory after reload is completed. This means
26110 that we can't easily use assign_stack_local. */
26112 ix86_force_to_memory (enum machine_mode mode, rtx operand)
26116 gcc_assert (reload_completed);
26117 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
26119 result = gen_rtx_MEM (mode,
26120 gen_rtx_PLUS (Pmode,
26122 GEN_INT (-RED_ZONE_SIZE)));
26123 emit_move_insn (result, operand);
26125 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
26131 operand = gen_lowpart (DImode, operand);
26135 gen_rtx_SET (VOIDmode,
26136 gen_rtx_MEM (DImode,
26137 gen_rtx_PRE_DEC (DImode,
26138 stack_pointer_rtx)),
26142 gcc_unreachable ();
26144 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26153 split_di (&operand, 1, operands, operands + 1);
26155 gen_rtx_SET (VOIDmode,
26156 gen_rtx_MEM (SImode,
26157 gen_rtx_PRE_DEC (Pmode,
26158 stack_pointer_rtx)),
26161 gen_rtx_SET (VOIDmode,
26162 gen_rtx_MEM (SImode,
26163 gen_rtx_PRE_DEC (Pmode,
26164 stack_pointer_rtx)),
26169 /* Store HImodes as SImodes. */
26170 operand = gen_lowpart (SImode, operand);
26174 gen_rtx_SET (VOIDmode,
26175 gen_rtx_MEM (GET_MODE (operand),
26176 gen_rtx_PRE_DEC (SImode,
26177 stack_pointer_rtx)),
26181 gcc_unreachable ();
26183 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26188 /* Free operand from the memory. */
26190 ix86_free_from_memory (enum machine_mode mode)
26192 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
26196 if (mode == DImode || TARGET_64BIT)
26200 /* Use LEA to deallocate stack space. In peephole2 it will be converted
26201 to pop or add instruction if registers are available. */
26202 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
26203 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
26208 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
26209 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
26211 static const enum reg_class *
26212 i386_ira_cover_classes (void)
26214 static const enum reg_class sse_fpmath_classes[] = {
26215 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
26217 static const enum reg_class no_sse_fpmath_classes[] = {
26218 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
26221 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
26224 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
26225 QImode must go into class Q_REGS.
26226 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
26227 movdf to do mem-to-mem moves through integer regs. */
26229 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
26231 enum machine_mode mode = GET_MODE (x);
26233 /* We're only allowed to return a subclass of CLASS. Many of the
26234 following checks fail for NO_REGS, so eliminate that early. */
26235 if (regclass == NO_REGS)
26238 /* All classes can load zeros. */
26239 if (x == CONST0_RTX (mode))
26242 /* Force constants into memory if we are loading a (nonzero) constant into
26243 an MMX or SSE register. This is because there are no MMX/SSE instructions
26244 to load from a constant. */
26246 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
26249 /* Prefer SSE regs only, if we can use them for math. */
26250 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
26251 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
26253 /* Floating-point constants need more complex checks. */
26254 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
26256 /* General regs can load everything. */
26257 if (reg_class_subset_p (regclass, GENERAL_REGS))
26260 /* Floats can load 0 and 1 plus some others. Note that we eliminated
26261 zero above. We only want to wind up preferring 80387 registers if
26262 we plan on doing computation with them. */
26264 && standard_80387_constant_p (x))
26266 /* Limit class to non-sse. */
26267 if (regclass == FLOAT_SSE_REGS)
26269 if (regclass == FP_TOP_SSE_REGS)
26271 if (regclass == FP_SECOND_SSE_REGS)
26272 return FP_SECOND_REG;
26273 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
26280 /* Generally when we see PLUS here, it's the function invariant
26281 (plus soft-fp const_int). Which can only be computed into general
26283 if (GET_CODE (x) == PLUS)
26284 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
26286 /* QImode constants are easy to load, but non-constant QImode data
26287 must go into Q_REGS. */
26288 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
26290 if (reg_class_subset_p (regclass, Q_REGS))
26292 if (reg_class_subset_p (Q_REGS, regclass))
26300 /* Discourage putting floating-point values in SSE registers unless
26301 SSE math is being used, and likewise for the 387 registers. */
26303 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
26305 enum machine_mode mode = GET_MODE (x);
26307 /* Restrict the output reload class to the register bank that we are doing
26308 math on. If we would like not to return a subset of CLASS, reject this
26309 alternative: if reload cannot do this, it will still use its choice. */
26310 mode = GET_MODE (x);
26311 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
26312 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
26314 if (X87_FLOAT_MODE_P (mode))
26316 if (regclass == FP_TOP_SSE_REGS)
26318 else if (regclass == FP_SECOND_SSE_REGS)
26319 return FP_SECOND_REG;
26321 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
26327 static enum reg_class
26328 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
26329 enum machine_mode mode,
26330 secondary_reload_info *sri ATTRIBUTE_UNUSED)
26332 /* QImode spills from non-QI registers require
26333 intermediate register on 32bit targets. */
26334 if (!in_p && mode == QImode && !TARGET_64BIT
26335 && (rclass == GENERAL_REGS
26336 || rclass == LEGACY_REGS
26337 || rclass == INDEX_REGS))
26346 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
26347 regno = true_regnum (x);
26349 /* Return Q_REGS if the operand is in memory. */
26357 /* If we are copying between general and FP registers, we need a memory
26358 location. The same is true for SSE and MMX registers.
26360 To optimize register_move_cost performance, allow inline variant.
26362 The macro can't work reliably when one of the CLASSES is class containing
26363 registers from multiple units (SSE, MMX, integer). We avoid this by never
26364 combining those units in single alternative in the machine description.
26365 Ensure that this constraint holds to avoid unexpected surprises.
26367 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
26368 enforce these sanity checks. */
26371 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26372 enum machine_mode mode, int strict)
26374 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
26375 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
26376 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
26377 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
26378 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
26379 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
26381 gcc_assert (!strict);
26385 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
26388 /* ??? This is a lie. We do have moves between mmx/general, and for
26389 mmx/sse2. But by saying we need secondary memory we discourage the
26390 register allocator from using the mmx registers unless needed. */
26391 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
26394 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26396 /* SSE1 doesn't have any direct moves from other classes. */
26400 /* If the target says that inter-unit moves are more expensive
26401 than moving through memory, then don't generate them. */
26402 if (!TARGET_INTER_UNIT_MOVES)
26405 /* Between SSE and general, we have moves no larger than word size. */
26406 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
26414 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26415 enum machine_mode mode, int strict)
26417 return inline_secondary_memory_needed (class1, class2, mode, strict);
26420 /* Return true if the registers in CLASS cannot represent the change from
26421 modes FROM to TO. */
26424 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
26425 enum reg_class regclass)
26430 /* x87 registers can't do subreg at all, as all values are reformatted
26431 to extended precision. */
26432 if (MAYBE_FLOAT_CLASS_P (regclass))
26435 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
26437 /* Vector registers do not support QI or HImode loads. If we don't
26438 disallow a change to these modes, reload will assume it's ok to
26439 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
26440 the vec_dupv4hi pattern. */
26441 if (GET_MODE_SIZE (from) < 4)
26444 /* Vector registers do not support subreg with nonzero offsets, which
26445 are otherwise valid for integer registers. Since we can't see
26446 whether we have a nonzero offset from here, prohibit all
26447 nonparadoxical subregs changing size. */
26448 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
26455 /* Return the cost of moving data of mode M between a
26456 register and memory. A value of 2 is the default; this cost is
26457 relative to those in `REGISTER_MOVE_COST'.
26459 This function is used extensively by register_move_cost that is used to
26460 build tables at startup. Make it inline in this case.
26461 When IN is 2, return maximum of in and out move cost.
26463 If moving between registers and memory is more expensive than
26464 between two registers, you should define this macro to express the
26467 Model also increased moving costs of QImode registers in non
26471 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
26475 if (FLOAT_CLASS_P (regclass))
26493 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
26494 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
26496 if (SSE_CLASS_P (regclass))
26499 switch (GET_MODE_SIZE (mode))
26514 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
26515 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
26517 if (MMX_CLASS_P (regclass))
26520 switch (GET_MODE_SIZE (mode))
26532 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
26533 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
26535 switch (GET_MODE_SIZE (mode))
26538 if (Q_CLASS_P (regclass) || TARGET_64BIT)
26541 return ix86_cost->int_store[0];
26542 if (TARGET_PARTIAL_REG_DEPENDENCY
26543 && optimize_function_for_speed_p (cfun))
26544 cost = ix86_cost->movzbl_load;
26546 cost = ix86_cost->int_load[0];
26548 return MAX (cost, ix86_cost->int_store[0]);
26554 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
26556 return ix86_cost->movzbl_load;
26558 return ix86_cost->int_store[0] + 4;
26563 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
26564 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
26566 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
26567 if (mode == TFmode)
26570 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
26572 cost = ix86_cost->int_load[2];
26574 cost = ix86_cost->int_store[2];
26575 return (cost * (((int) GET_MODE_SIZE (mode)
26576 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
26581 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
26583 return inline_memory_move_cost (mode, regclass, in);
26587 /* Return the cost of moving data from a register in class CLASS1 to
26588 one in class CLASS2.
26590 It is not required that the cost always equal 2 when FROM is the same as TO;
26591 on some machines it is expensive to move between registers if they are not
26592 general registers. */
26595 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
26596 enum reg_class class2)
26598 /* In case we require secondary memory, compute cost of the store followed
26599 by load. In order to avoid bad register allocation choices, we need
26600 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
26602 if (inline_secondary_memory_needed (class1, class2, mode, 0))
26606 cost += inline_memory_move_cost (mode, class1, 2);
26607 cost += inline_memory_move_cost (mode, class2, 2);
26609 /* In case of copying from general_purpose_register we may emit multiple
26610 stores followed by single load causing memory size mismatch stall.
26611 Count this as arbitrarily high cost of 20. */
26612 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
26615 /* In the case of FP/MMX moves, the registers actually overlap, and we
26616 have to switch modes in order to treat them differently. */
26617 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
26618 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
26624 /* Moves between SSE/MMX and integer unit are expensive. */
26625 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
26626 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26628 /* ??? By keeping returned value relatively high, we limit the number
26629 of moves between integer and MMX/SSE registers for all targets.
26630 Additionally, high value prevents problem with x86_modes_tieable_p(),
26631 where integer modes in MMX/SSE registers are not tieable
26632 because of missing QImode and HImode moves to, from or between
26633 MMX/SSE registers. */
26634 return MAX (8, ix86_cost->mmxsse_to_integer);
26636 if (MAYBE_FLOAT_CLASS_P (class1))
26637 return ix86_cost->fp_move;
26638 if (MAYBE_SSE_CLASS_P (class1))
26639 return ix86_cost->sse_move;
26640 if (MAYBE_MMX_CLASS_P (class1))
26641 return ix86_cost->mmx_move;
26645 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
26648 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
26650 /* Flags and only flags can only hold CCmode values. */
26651 if (CC_REGNO_P (regno))
26652 return GET_MODE_CLASS (mode) == MODE_CC;
26653 if (GET_MODE_CLASS (mode) == MODE_CC
26654 || GET_MODE_CLASS (mode) == MODE_RANDOM
26655 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
26657 if (FP_REGNO_P (regno))
26658 return VALID_FP_MODE_P (mode);
26659 if (SSE_REGNO_P (regno))
26661 /* We implement the move patterns for all vector modes into and
26662 out of SSE registers, even when no operation instructions
26663 are available. OImode move is available only when AVX is
26665 return ((TARGET_AVX && mode == OImode)
26666 || VALID_AVX256_REG_MODE (mode)
26667 || VALID_SSE_REG_MODE (mode)
26668 || VALID_SSE2_REG_MODE (mode)
26669 || VALID_MMX_REG_MODE (mode)
26670 || VALID_MMX_REG_MODE_3DNOW (mode));
26672 if (MMX_REGNO_P (regno))
26674 /* We implement the move patterns for 3DNOW modes even in MMX mode,
26675 so if the register is available at all, then we can move data of
26676 the given mode into or out of it. */
26677 return (VALID_MMX_REG_MODE (mode)
26678 || VALID_MMX_REG_MODE_3DNOW (mode));
26681 if (mode == QImode)
26683 /* Take care for QImode values - they can be in non-QI regs,
26684 but then they do cause partial register stalls. */
26685 if (regno <= BX_REG || TARGET_64BIT)
26687 if (!TARGET_PARTIAL_REG_STALL)
26689 return reload_in_progress || reload_completed;
26691 /* We handle both integer and floats in the general purpose registers. */
26692 else if (VALID_INT_MODE_P (mode))
26694 else if (VALID_FP_MODE_P (mode))
26696 else if (VALID_DFP_MODE_P (mode))
26698 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
26699 on to use that value in smaller contexts, this can easily force a
26700 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
26701 supporting DImode, allow it. */
26702 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
26708 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
26709 tieable integer mode. */
26712 ix86_tieable_integer_mode_p (enum machine_mode mode)
26721 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
26724 return TARGET_64BIT;
26731 /* Return true if MODE1 is accessible in a register that can hold MODE2
26732 without copying. That is, all register classes that can hold MODE2
26733 can also hold MODE1. */
26736 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
26738 if (mode1 == mode2)
26741 if (ix86_tieable_integer_mode_p (mode1)
26742 && ix86_tieable_integer_mode_p (mode2))
26745 /* MODE2 being XFmode implies fp stack or general regs, which means we
26746 can tie any smaller floating point modes to it. Note that we do not
26747 tie this with TFmode. */
26748 if (mode2 == XFmode)
26749 return mode1 == SFmode || mode1 == DFmode;
26751 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26752 that we can tie it with SFmode. */
26753 if (mode2 == DFmode)
26754 return mode1 == SFmode;
26756 /* If MODE2 is only appropriate for an SSE register, then tie with
26757 any other mode acceptable to SSE registers. */
26758 if (GET_MODE_SIZE (mode2) == 16
26759 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26760 return (GET_MODE_SIZE (mode1) == 16
26761 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26763 /* If MODE2 is appropriate for an MMX register, then tie
26764 with any other mode acceptable to MMX registers. */
26765 if (GET_MODE_SIZE (mode2) == 8
26766 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26767 return (GET_MODE_SIZE (mode1) == 8
26768 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26773 /* Compute a (partial) cost for rtx X. Return true if the complete
26774 cost has been computed, and false if subexpressions should be
26775 scanned. In either case, *TOTAL contains the cost result. */
26778 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26780 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26781 enum machine_mode mode = GET_MODE (x);
26782 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26790 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26792 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26794 else if (flag_pic && SYMBOLIC_CONST (x)
26796 || (!GET_CODE (x) != LABEL_REF
26797 && (GET_CODE (x) != SYMBOL_REF
26798 || !SYMBOL_REF_LOCAL_P (x)))))
26805 if (mode == VOIDmode)
26808 switch (standard_80387_constant_p (x))
26813 default: /* Other constants */
26818 /* Start with (MEM (SYMBOL_REF)), since that's where
26819 it'll probably end up. Add a penalty for size. */
26820 *total = (COSTS_N_INSNS (1)
26821 + (flag_pic != 0 && !TARGET_64BIT)
26822 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26828 /* The zero extensions is often completely free on x86_64, so make
26829 it as cheap as possible. */
26830 if (TARGET_64BIT && mode == DImode
26831 && GET_MODE (XEXP (x, 0)) == SImode)
26833 else if (TARGET_ZERO_EXTEND_WITH_AND)
26834 *total = cost->add;
26836 *total = cost->movzx;
26840 *total = cost->movsx;
26844 if (CONST_INT_P (XEXP (x, 1))
26845 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26847 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26850 *total = cost->add;
26853 if ((value == 2 || value == 3)
26854 && cost->lea <= cost->shift_const)
26856 *total = cost->lea;
26866 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26868 if (CONST_INT_P (XEXP (x, 1)))
26870 if (INTVAL (XEXP (x, 1)) > 32)
26871 *total = cost->shift_const + COSTS_N_INSNS (2);
26873 *total = cost->shift_const * 2;
26877 if (GET_CODE (XEXP (x, 1)) == AND)
26878 *total = cost->shift_var * 2;
26880 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26885 if (CONST_INT_P (XEXP (x, 1)))
26886 *total = cost->shift_const;
26888 *total = cost->shift_var;
26893 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26895 /* ??? SSE scalar cost should be used here. */
26896 *total = cost->fmul;
26899 else if (X87_FLOAT_MODE_P (mode))
26901 *total = cost->fmul;
26904 else if (FLOAT_MODE_P (mode))
26906 /* ??? SSE vector cost should be used here. */
26907 *total = cost->fmul;
26912 rtx op0 = XEXP (x, 0);
26913 rtx op1 = XEXP (x, 1);
26915 if (CONST_INT_P (XEXP (x, 1)))
26917 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26918 for (nbits = 0; value != 0; value &= value - 1)
26922 /* This is arbitrary. */
26925 /* Compute costs correctly for widening multiplication. */
26926 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26927 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26928 == GET_MODE_SIZE (mode))
26930 int is_mulwiden = 0;
26931 enum machine_mode inner_mode = GET_MODE (op0);
26933 if (GET_CODE (op0) == GET_CODE (op1))
26934 is_mulwiden = 1, op1 = XEXP (op1, 0);
26935 else if (CONST_INT_P (op1))
26937 if (GET_CODE (op0) == SIGN_EXTEND)
26938 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26941 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26945 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26948 *total = (cost->mult_init[MODE_INDEX (mode)]
26949 + nbits * cost->mult_bit
26950 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26959 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26960 /* ??? SSE cost should be used here. */
26961 *total = cost->fdiv;
26962 else if (X87_FLOAT_MODE_P (mode))
26963 *total = cost->fdiv;
26964 else if (FLOAT_MODE_P (mode))
26965 /* ??? SSE vector cost should be used here. */
26966 *total = cost->fdiv;
26968 *total = cost->divide[MODE_INDEX (mode)];
26972 if (GET_MODE_CLASS (mode) == MODE_INT
26973 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26975 if (GET_CODE (XEXP (x, 0)) == PLUS
26976 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26977 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26978 && CONSTANT_P (XEXP (x, 1)))
26980 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26981 if (val == 2 || val == 4 || val == 8)
26983 *total = cost->lea;
26984 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26985 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26986 outer_code, speed);
26987 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26991 else if (GET_CODE (XEXP (x, 0)) == MULT
26992 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26994 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26995 if (val == 2 || val == 4 || val == 8)
26997 *total = cost->lea;
26998 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26999 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27003 else if (GET_CODE (XEXP (x, 0)) == PLUS)
27005 *total = cost->lea;
27006 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
27007 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
27008 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27015 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27017 /* ??? SSE cost should be used here. */
27018 *total = cost->fadd;
27021 else if (X87_FLOAT_MODE_P (mode))
27023 *total = cost->fadd;
27026 else if (FLOAT_MODE_P (mode))
27028 /* ??? SSE vector cost should be used here. */
27029 *total = cost->fadd;
27037 if (!TARGET_64BIT && mode == DImode)
27039 *total = (cost->add * 2
27040 + (rtx_cost (XEXP (x, 0), outer_code, speed)
27041 << (GET_MODE (XEXP (x, 0)) != DImode))
27042 + (rtx_cost (XEXP (x, 1), outer_code, speed)
27043 << (GET_MODE (XEXP (x, 1)) != DImode)));
27049 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27051 /* ??? SSE cost should be used here. */
27052 *total = cost->fchs;
27055 else if (X87_FLOAT_MODE_P (mode))
27057 *total = cost->fchs;
27060 else if (FLOAT_MODE_P (mode))
27062 /* ??? SSE vector cost should be used here. */
27063 *total = cost->fchs;
27069 if (!TARGET_64BIT && mode == DImode)
27070 *total = cost->add * 2;
27072 *total = cost->add;
27076 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
27077 && XEXP (XEXP (x, 0), 1) == const1_rtx
27078 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
27079 && XEXP (x, 1) == const0_rtx)
27081 /* This kind of construct is implemented using test[bwl].
27082 Treat it as if we had an AND. */
27083 *total = (cost->add
27084 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
27085 + rtx_cost (const1_rtx, outer_code, speed));
27091 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
27096 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27097 /* ??? SSE cost should be used here. */
27098 *total = cost->fabs;
27099 else if (X87_FLOAT_MODE_P (mode))
27100 *total = cost->fabs;
27101 else if (FLOAT_MODE_P (mode))
27102 /* ??? SSE vector cost should be used here. */
27103 *total = cost->fabs;
27107 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27108 /* ??? SSE cost should be used here. */
27109 *total = cost->fsqrt;
27110 else if (X87_FLOAT_MODE_P (mode))
27111 *total = cost->fsqrt;
27112 else if (FLOAT_MODE_P (mode))
27113 /* ??? SSE vector cost should be used here. */
27114 *total = cost->fsqrt;
27118 if (XINT (x, 1) == UNSPEC_TP)
27129 static int current_machopic_label_num;
27131 /* Given a symbol name and its associated stub, write out the
27132 definition of the stub. */
27135 machopic_output_stub (FILE *file, const char *symb, const char *stub)
27137 unsigned int length;
27138 char *binder_name, *symbol_name, lazy_ptr_name[32];
27139 int label = ++current_machopic_label_num;
27141 /* For 64-bit we shouldn't get here. */
27142 gcc_assert (!TARGET_64BIT);
27144 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
27145 symb = (*targetm.strip_name_encoding) (symb);
27147 length = strlen (stub);
27148 binder_name = XALLOCAVEC (char, length + 32);
27149 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
27151 length = strlen (symb);
27152 symbol_name = XALLOCAVEC (char, length + 32);
27153 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
27155 sprintf (lazy_ptr_name, "L%d$lz", label);
27158 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
27160 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
27162 fprintf (file, "%s:\n", stub);
27163 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27167 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
27168 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
27169 fprintf (file, "\tjmp\t*%%edx\n");
27172 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
27174 fprintf (file, "%s:\n", binder_name);
27178 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
27179 fputs ("\tpushl\t%eax\n", file);
27182 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
27184 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
27186 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
27187 fprintf (file, "%s:\n", lazy_ptr_name);
27188 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27189 fprintf (file, ASM_LONG "%s\n", binder_name);
27193 darwin_x86_file_end (void)
27195 darwin_file_end ();
27198 #endif /* TARGET_MACHO */
27200 /* Order the registers for register allocator. */
27203 x86_order_regs_for_local_alloc (void)
27208 /* First allocate the local general purpose registers. */
27209 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27210 if (GENERAL_REGNO_P (i) && call_used_regs[i])
27211 reg_alloc_order [pos++] = i;
27213 /* Global general purpose registers. */
27214 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27215 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
27216 reg_alloc_order [pos++] = i;
27218 /* x87 registers come first in case we are doing FP math
27220 if (!TARGET_SSE_MATH)
27221 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27222 reg_alloc_order [pos++] = i;
27224 /* SSE registers. */
27225 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
27226 reg_alloc_order [pos++] = i;
27227 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
27228 reg_alloc_order [pos++] = i;
27230 /* x87 registers. */
27231 if (TARGET_SSE_MATH)
27232 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27233 reg_alloc_order [pos++] = i;
27235 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
27236 reg_alloc_order [pos++] = i;
27238 /* Initialize the rest of array as we do not allocate some registers
27240 while (pos < FIRST_PSEUDO_REGISTER)
27241 reg_alloc_order [pos++] = 0;
27244 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
27245 struct attribute_spec.handler. */
27247 ix86_handle_abi_attribute (tree *node, tree name,
27248 tree args ATTRIBUTE_UNUSED,
27249 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27251 if (TREE_CODE (*node) != FUNCTION_TYPE
27252 && TREE_CODE (*node) != METHOD_TYPE
27253 && TREE_CODE (*node) != FIELD_DECL
27254 && TREE_CODE (*node) != TYPE_DECL)
27256 warning (OPT_Wattributes, "%qE attribute only applies to functions",
27258 *no_add_attrs = true;
27263 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
27265 *no_add_attrs = true;
27269 /* Can combine regparm with all attributes but fastcall. */
27270 if (is_attribute_p ("ms_abi", name))
27272 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
27274 error ("ms_abi and sysv_abi attributes are not compatible");
27279 else if (is_attribute_p ("sysv_abi", name))
27281 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
27283 error ("ms_abi and sysv_abi attributes are not compatible");
27292 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27293 struct attribute_spec.handler. */
27295 ix86_handle_struct_attribute (tree *node, tree name,
27296 tree args ATTRIBUTE_UNUSED,
27297 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27300 if (DECL_P (*node))
27302 if (TREE_CODE (*node) == TYPE_DECL)
27303 type = &TREE_TYPE (*node);
27308 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
27309 || TREE_CODE (*type) == UNION_TYPE)))
27311 warning (OPT_Wattributes, "%qE attribute ignored",
27313 *no_add_attrs = true;
27316 else if ((is_attribute_p ("ms_struct", name)
27317 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
27318 || ((is_attribute_p ("gcc_struct", name)
27319 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
27321 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
27323 *no_add_attrs = true;
27330 ix86_handle_fndecl_attribute (tree *node, tree name,
27331 tree args ATTRIBUTE_UNUSED,
27332 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27334 if (TREE_CODE (*node) != FUNCTION_DECL)
27336 warning (OPT_Wattributes, "%qE attribute only applies to functions",
27338 *no_add_attrs = true;
27344 warning (OPT_Wattributes, "%qE attribute only available for 32-bit",
27349 #ifndef HAVE_AS_IX86_SWAP
27350 sorry ("ms_hook_prologue attribute needs assembler swap suffix support");
27357 ix86_ms_bitfield_layout_p (const_tree record_type)
27359 return (TARGET_MS_BITFIELD_LAYOUT &&
27360 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
27361 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
27364 /* Returns an expression indicating where the this parameter is
27365 located on entry to the FUNCTION. */
27368 x86_this_parameter (tree function)
27370 tree type = TREE_TYPE (function);
27371 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
27376 const int *parm_regs;
27378 if (ix86_function_type_abi (type) == MS_ABI)
27379 parm_regs = x86_64_ms_abi_int_parameter_registers;
27381 parm_regs = x86_64_int_parameter_registers;
27382 return gen_rtx_REG (DImode, parm_regs[aggr]);
27385 nregs = ix86_function_regparm (type, function);
27387 if (nregs > 0 && !stdarg_p (type))
27391 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
27392 regno = aggr ? DX_REG : CX_REG;
27400 return gen_rtx_MEM (SImode,
27401 plus_constant (stack_pointer_rtx, 4));
27404 return gen_rtx_REG (SImode, regno);
27407 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
27410 /* Determine whether x86_output_mi_thunk can succeed. */
27413 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
27414 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
27415 HOST_WIDE_INT vcall_offset, const_tree function)
27417 /* 64-bit can handle anything. */
27421 /* For 32-bit, everything's fine if we have one free register. */
27422 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
27425 /* Need a free register for vcall_offset. */
27429 /* Need a free register for GOT references. */
27430 if (flag_pic && !(*targetm.binds_local_p) (function))
27433 /* Otherwise ok. */
27437 /* Output the assembler code for a thunk function. THUNK_DECL is the
27438 declaration for the thunk function itself, FUNCTION is the decl for
27439 the target function. DELTA is an immediate constant offset to be
27440 added to THIS. If VCALL_OFFSET is nonzero, the word at
27441 *(*this + vcall_offset) should be added to THIS. */
27444 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
27445 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
27446 HOST_WIDE_INT vcall_offset, tree function)
27449 rtx this_param = x86_this_parameter (function);
27452 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
27453 pull it in now and let DELTA benefit. */
27454 if (REG_P (this_param))
27455 this_reg = this_param;
27456 else if (vcall_offset)
27458 /* Put the this parameter into %eax. */
27459 xops[0] = this_param;
27460 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
27461 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27464 this_reg = NULL_RTX;
27466 /* Adjust the this parameter by a fixed constant. */
27469 xops[0] = GEN_INT (delta);
27470 xops[1] = this_reg ? this_reg : this_param;
27473 if (!x86_64_general_operand (xops[0], DImode))
27475 tmp = gen_rtx_REG (DImode, R10_REG);
27477 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
27479 xops[1] = this_param;
27481 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
27484 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
27487 /* Adjust the this parameter by a value stored in the vtable. */
27491 tmp = gen_rtx_REG (DImode, R10_REG);
27494 int tmp_regno = CX_REG;
27495 if (lookup_attribute ("fastcall",
27496 TYPE_ATTRIBUTES (TREE_TYPE (function))))
27497 tmp_regno = AX_REG;
27498 tmp = gen_rtx_REG (SImode, tmp_regno);
27501 xops[0] = gen_rtx_MEM (Pmode, this_reg);
27503 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27505 /* Adjust the this parameter. */
27506 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
27507 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
27509 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
27510 xops[0] = GEN_INT (vcall_offset);
27512 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
27513 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
27515 xops[1] = this_reg;
27516 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
27519 /* If necessary, drop THIS back to its stack slot. */
27520 if (this_reg && this_reg != this_param)
27522 xops[0] = this_reg;
27523 xops[1] = this_param;
27524 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27527 xops[0] = XEXP (DECL_RTL (function), 0);
27530 if (!flag_pic || (*targetm.binds_local_p) (function))
27531 output_asm_insn ("jmp\t%P0", xops);
27532 /* All thunks should be in the same object as their target,
27533 and thus binds_local_p should be true. */
27534 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
27535 gcc_unreachable ();
27538 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
27539 tmp = gen_rtx_CONST (Pmode, tmp);
27540 tmp = gen_rtx_MEM (QImode, tmp);
27542 output_asm_insn ("jmp\t%A0", xops);
27547 if (!flag_pic || (*targetm.binds_local_p) (function))
27548 output_asm_insn ("jmp\t%P0", xops);
27553 rtx sym_ref = XEXP (DECL_RTL (function), 0);
27554 tmp = (gen_rtx_SYMBOL_REF
27556 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
27557 tmp = gen_rtx_MEM (QImode, tmp);
27559 output_asm_insn ("jmp\t%0", xops);
27562 #endif /* TARGET_MACHO */
27564 tmp = gen_rtx_REG (SImode, CX_REG);
27565 output_set_got (tmp, NULL_RTX);
27568 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
27569 output_asm_insn ("jmp\t{*}%1", xops);
27575 x86_file_start (void)
27577 default_file_start ();
27579 darwin_file_start ();
27581 if (X86_FILE_START_VERSION_DIRECTIVE)
27582 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
27583 if (X86_FILE_START_FLTUSED)
27584 fputs ("\t.global\t__fltused\n", asm_out_file);
27585 if (ix86_asm_dialect == ASM_INTEL)
27586 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
27590 x86_field_alignment (tree field, int computed)
27592 enum machine_mode mode;
27593 tree type = TREE_TYPE (field);
27595 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
27597 mode = TYPE_MODE (strip_array_types (type));
27598 if (mode == DFmode || mode == DCmode
27599 || GET_MODE_CLASS (mode) == MODE_INT
27600 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
27601 return MIN (32, computed);
27605 /* Output assembler code to FILE to increment profiler label # LABELNO
27606 for profiling a function entry. */
27608 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
27612 #ifndef NO_PROFILE_COUNTERS
27613 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
27616 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
27617 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
27619 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
27623 #ifndef NO_PROFILE_COUNTERS
27624 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
27627 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
27631 #ifndef NO_PROFILE_COUNTERS
27632 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
27635 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
27639 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27640 /* We don't have exact information about the insn sizes, but we may assume
27641 quite safely that we are informed about all 1 byte insns and memory
27642 address sizes. This is enough to eliminate unnecessary padding in
27646 min_insn_size (rtx insn)
27650 if (!INSN_P (insn) || !active_insn_p (insn))
27653 /* Discard alignments we've emit and jump instructions. */
27654 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
27655 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
27657 if (JUMP_TABLE_DATA_P (insn))
27660 /* Important case - calls are always 5 bytes.
27661 It is common to have many calls in the row. */
27663 && symbolic_reference_mentioned_p (PATTERN (insn))
27664 && !SIBLING_CALL_P (insn))
27666 len = get_attr_length (insn);
27670 /* For normal instructions we rely on get_attr_length being exact,
27671 with a few exceptions. */
27672 if (!JUMP_P (insn))
27674 enum attr_type type = get_attr_type (insn);
27679 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
27680 || asm_noperands (PATTERN (insn)) >= 0)
27687 /* Otherwise trust get_attr_length. */
27691 l = get_attr_length_address (insn);
27692 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
27701 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
27705 ix86_avoid_jump_mispredicts (void)
27707 rtx insn, start = get_insns ();
27708 int nbytes = 0, njumps = 0;
27711 /* Look for all minimal intervals of instructions containing 4 jumps.
27712 The intervals are bounded by START and INSN. NBYTES is the total
27713 size of instructions in the interval including INSN and not including
27714 START. When the NBYTES is smaller than 16 bytes, it is possible
27715 that the end of START and INSN ends up in the same 16byte page.
27717 The smallest offset in the page INSN can start is the case where START
27718 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
27719 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
27721 for (insn = start; insn; insn = NEXT_INSN (insn))
27725 if (LABEL_P (insn))
27727 int align = label_to_alignment (insn);
27728 int max_skip = label_to_max_skip (insn);
27732 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
27733 already in the current 16 byte page, because otherwise
27734 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
27735 bytes to reach 16 byte boundary. */
27737 || (align <= 3 && max_skip != (1 << align) - 1))
27740 fprintf (dump_file, "Label %i with max_skip %i\n",
27741 INSN_UID (insn), max_skip);
27744 while (nbytes + max_skip >= 16)
27746 start = NEXT_INSN (start);
27747 if ((JUMP_P (start)
27748 && GET_CODE (PATTERN (start)) != ADDR_VEC
27749 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27751 njumps--, isjump = 1;
27754 nbytes -= min_insn_size (start);
27760 min_size = min_insn_size (insn);
27761 nbytes += min_size;
27763 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
27764 INSN_UID (insn), min_size);
27766 && GET_CODE (PATTERN (insn)) != ADDR_VEC
27767 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
27775 start = NEXT_INSN (start);
27776 if ((JUMP_P (start)
27777 && GET_CODE (PATTERN (start)) != ADDR_VEC
27778 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27780 njumps--, isjump = 1;
27783 nbytes -= min_insn_size (start);
27785 gcc_assert (njumps >= 0);
27787 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
27788 INSN_UID (start), INSN_UID (insn), nbytes);
27790 if (njumps == 3 && isjump && nbytes < 16)
27792 int padsize = 15 - nbytes + min_insn_size (insn);
27795 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
27796 INSN_UID (insn), padsize);
27797 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
27803 /* AMD Athlon works faster
27804 when RET is not destination of conditional jump or directly preceded
27805 by other jump instruction. We avoid the penalty by inserting NOP just
27806 before the RET instructions in such cases. */
27808 ix86_pad_returns (void)
27813 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27815 basic_block bb = e->src;
27816 rtx ret = BB_END (bb);
27818 bool replace = false;
27820 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27821 || optimize_bb_for_size_p (bb))
27823 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27824 if (active_insn_p (prev) || LABEL_P (prev))
27826 if (prev && LABEL_P (prev))
27831 FOR_EACH_EDGE (e, ei, bb->preds)
27832 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27833 && !(e->flags & EDGE_FALLTHRU))
27838 prev = prev_active_insn (ret);
27840 && ((JUMP_P (prev) && any_condjump_p (prev))
27843 /* Empty functions get branch mispredict even when the jump destination
27844 is not visible to us. */
27845 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27850 emit_jump_insn_before (gen_return_internal_long (), ret);
27856 /* Implement machine specific optimizations. We implement padding of returns
27857 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27861 if (optimize && optimize_function_for_speed_p (cfun))
27863 if (TARGET_PAD_RETURNS)
27864 ix86_pad_returns ();
27865 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27866 if (TARGET_FOUR_JUMP_LIMIT)
27867 ix86_avoid_jump_mispredicts ();
27872 /* Return nonzero when QImode register that must be represented via REX prefix
27875 x86_extended_QIreg_mentioned_p (rtx insn)
27878 extract_insn_cached (insn);
27879 for (i = 0; i < recog_data.n_operands; i++)
27880 if (REG_P (recog_data.operand[i])
27881 && REGNO (recog_data.operand[i]) > BX_REG)
27886 /* Return nonzero when P points to register encoded via REX prefix.
27887 Called via for_each_rtx. */
27889 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27891 unsigned int regno;
27894 regno = REGNO (*p);
27895 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27898 /* Return true when INSN mentions register that must be encoded using REX
27901 x86_extended_reg_mentioned_p (rtx insn)
27903 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27904 extended_reg_mentioned_1, NULL);
27907 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27908 optabs would emit if we didn't have TFmode patterns. */
27911 x86_emit_floatuns (rtx operands[2])
27913 rtx neglab, donelab, i0, i1, f0, in, out;
27914 enum machine_mode mode, inmode;
27916 inmode = GET_MODE (operands[1]);
27917 gcc_assert (inmode == SImode || inmode == DImode);
27920 in = force_reg (inmode, operands[1]);
27921 mode = GET_MODE (out);
27922 neglab = gen_label_rtx ();
27923 donelab = gen_label_rtx ();
27924 f0 = gen_reg_rtx (mode);
27926 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27928 expand_float (out, in, 0);
27930 emit_jump_insn (gen_jump (donelab));
27933 emit_label (neglab);
27935 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27937 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27939 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27941 expand_float (f0, i0, 0);
27943 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27945 emit_label (donelab);
27948 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27949 with all elements equal to VAR. Return true if successful. */
27952 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27953 rtx target, rtx val)
27955 enum machine_mode hmode, smode, wsmode, wvmode;
27970 val = force_reg (GET_MODE_INNER (mode), val);
27971 x = gen_rtx_VEC_DUPLICATE (mode, val);
27972 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27978 if (TARGET_SSE || TARGET_3DNOW_A)
27980 val = gen_lowpart (SImode, val);
27981 x = gen_rtx_TRUNCATE (HImode, val);
27982 x = gen_rtx_VEC_DUPLICATE (mode, x);
27983 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28005 /* Extend HImode to SImode using a paradoxical SUBREG. */
28006 tmp1 = gen_reg_rtx (SImode);
28007 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28008 /* Insert the SImode value as low element of V4SImode vector. */
28009 tmp2 = gen_reg_rtx (V4SImode);
28010 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28011 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28012 CONST0_RTX (V4SImode),
28014 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28015 /* Cast the V4SImode vector back to a V8HImode vector. */
28016 tmp1 = gen_reg_rtx (V8HImode);
28017 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
28018 /* Duplicate the low short through the whole low SImode word. */
28019 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
28020 /* Cast the V8HImode vector back to a V4SImode vector. */
28021 tmp2 = gen_reg_rtx (V4SImode);
28022 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28023 /* Replicate the low element of the V4SImode vector. */
28024 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28025 /* Cast the V2SImode back to V8HImode, and store in target. */
28026 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
28037 /* Extend QImode to SImode using a paradoxical SUBREG. */
28038 tmp1 = gen_reg_rtx (SImode);
28039 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28040 /* Insert the SImode value as low element of V4SImode vector. */
28041 tmp2 = gen_reg_rtx (V4SImode);
28042 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28043 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28044 CONST0_RTX (V4SImode),
28046 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28047 /* Cast the V4SImode vector back to a V16QImode vector. */
28048 tmp1 = gen_reg_rtx (V16QImode);
28049 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
28050 /* Duplicate the low byte through the whole low SImode word. */
28051 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28052 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28053 /* Cast the V16QImode vector back to a V4SImode vector. */
28054 tmp2 = gen_reg_rtx (V4SImode);
28055 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28056 /* Replicate the low element of the V4SImode vector. */
28057 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28058 /* Cast the V2SImode back to V16QImode, and store in target. */
28059 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
28067 /* Replicate the value once into the next wider mode and recurse. */
28068 val = convert_modes (wsmode, smode, val, true);
28069 x = expand_simple_binop (wsmode, ASHIFT, val,
28070 GEN_INT (GET_MODE_BITSIZE (smode)),
28071 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28072 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
28074 x = gen_reg_rtx (wvmode);
28075 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
28076 gcc_unreachable ();
28077 emit_move_insn (target, gen_lowpart (mode, x));
28100 rtx tmp = gen_reg_rtx (hmode);
28101 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
28102 emit_insn (gen_rtx_SET (VOIDmode, target,
28103 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
28112 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28113 whose ONE_VAR element is VAR, and other elements are zero. Return true
28117 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
28118 rtx target, rtx var, int one_var)
28120 enum machine_mode vsimode;
28123 bool use_vector_set = false;
28128 /* For SSE4.1, we normally use vector set. But if the second
28129 element is zero and inter-unit moves are OK, we use movq
28131 use_vector_set = (TARGET_64BIT
28133 && !(TARGET_INTER_UNIT_MOVES
28139 use_vector_set = TARGET_SSE4_1;
28142 use_vector_set = TARGET_SSE2;
28145 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
28152 use_vector_set = TARGET_AVX;
28155 /* Use ix86_expand_vector_set in 64bit mode only. */
28156 use_vector_set = TARGET_AVX && TARGET_64BIT;
28162 if (use_vector_set)
28164 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
28165 var = force_reg (GET_MODE_INNER (mode), var);
28166 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28182 var = force_reg (GET_MODE_INNER (mode), var);
28183 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
28184 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28189 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
28190 new_target = gen_reg_rtx (mode);
28192 new_target = target;
28193 var = force_reg (GET_MODE_INNER (mode), var);
28194 x = gen_rtx_VEC_DUPLICATE (mode, var);
28195 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
28196 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
28199 /* We need to shuffle the value to the correct position, so
28200 create a new pseudo to store the intermediate result. */
28202 /* With SSE2, we can use the integer shuffle insns. */
28203 if (mode != V4SFmode && TARGET_SSE2)
28205 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
28207 GEN_INT (one_var == 1 ? 0 : 1),
28208 GEN_INT (one_var == 2 ? 0 : 1),
28209 GEN_INT (one_var == 3 ? 0 : 1)));
28210 if (target != new_target)
28211 emit_move_insn (target, new_target);
28215 /* Otherwise convert the intermediate result to V4SFmode and
28216 use the SSE1 shuffle instructions. */
28217 if (mode != V4SFmode)
28219 tmp = gen_reg_rtx (V4SFmode);
28220 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
28225 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
28227 GEN_INT (one_var == 1 ? 0 : 1),
28228 GEN_INT (one_var == 2 ? 0+4 : 1+4),
28229 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
28231 if (mode != V4SFmode)
28232 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
28233 else if (tmp != target)
28234 emit_move_insn (target, tmp);
28236 else if (target != new_target)
28237 emit_move_insn (target, new_target);
28242 vsimode = V4SImode;
28248 vsimode = V2SImode;
28254 /* Zero extend the variable element to SImode and recurse. */
28255 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
28257 x = gen_reg_rtx (vsimode);
28258 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
28260 gcc_unreachable ();
28262 emit_move_insn (target, gen_lowpart (mode, x));
28270 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28271 consisting of the values in VALS. It is known that all elements
28272 except ONE_VAR are constants. Return true if successful. */
28275 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
28276 rtx target, rtx vals, int one_var)
28278 rtx var = XVECEXP (vals, 0, one_var);
28279 enum machine_mode wmode;
28282 const_vec = copy_rtx (vals);
28283 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
28284 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
28292 /* For the two element vectors, it's just as easy to use
28293 the general case. */
28297 /* Use ix86_expand_vector_set in 64bit mode only. */
28320 /* There's no way to set one QImode entry easily. Combine
28321 the variable value with its adjacent constant value, and
28322 promote to an HImode set. */
28323 x = XVECEXP (vals, 0, one_var ^ 1);
28326 var = convert_modes (HImode, QImode, var, true);
28327 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
28328 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28329 x = GEN_INT (INTVAL (x) & 0xff);
28333 var = convert_modes (HImode, QImode, var, true);
28334 x = gen_int_mode (INTVAL (x) << 8, HImode);
28336 if (x != const0_rtx)
28337 var = expand_simple_binop (HImode, IOR, var, x, var,
28338 1, OPTAB_LIB_WIDEN);
28340 x = gen_reg_rtx (wmode);
28341 emit_move_insn (x, gen_lowpart (wmode, const_vec));
28342 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
28344 emit_move_insn (target, gen_lowpart (mode, x));
28351 emit_move_insn (target, const_vec);
28352 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28356 /* A subroutine of ix86_expand_vector_init_general. Use vector
28357 concatenate to handle the most general case: all values variable,
28358 and none identical. */
28361 ix86_expand_vector_init_concat (enum machine_mode mode,
28362 rtx target, rtx *ops, int n)
28364 enum machine_mode cmode, hmode = VOIDmode;
28365 rtx first[8], second[4];
28405 gcc_unreachable ();
28408 if (!register_operand (ops[1], cmode))
28409 ops[1] = force_reg (cmode, ops[1]);
28410 if (!register_operand (ops[0], cmode))
28411 ops[0] = force_reg (cmode, ops[0]);
28412 emit_insn (gen_rtx_SET (VOIDmode, target,
28413 gen_rtx_VEC_CONCAT (mode, ops[0],
28433 gcc_unreachable ();
28449 gcc_unreachable ();
28454 /* FIXME: We process inputs backward to help RA. PR 36222. */
28457 for (; i > 0; i -= 2, j--)
28459 first[j] = gen_reg_rtx (cmode);
28460 v = gen_rtvec (2, ops[i - 1], ops[i]);
28461 ix86_expand_vector_init (false, first[j],
28462 gen_rtx_PARALLEL (cmode, v));
28468 gcc_assert (hmode != VOIDmode);
28469 for (i = j = 0; i < n; i += 2, j++)
28471 second[j] = gen_reg_rtx (hmode);
28472 ix86_expand_vector_init_concat (hmode, second [j],
28476 ix86_expand_vector_init_concat (mode, target, second, n);
28479 ix86_expand_vector_init_concat (mode, target, first, n);
28483 gcc_unreachable ();
28487 /* A subroutine of ix86_expand_vector_init_general. Use vector
28488 interleave to handle the most general case: all values variable,
28489 and none identical. */
28492 ix86_expand_vector_init_interleave (enum machine_mode mode,
28493 rtx target, rtx *ops, int n)
28495 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
28498 rtx (*gen_load_even) (rtx, rtx, rtx);
28499 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
28500 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
28505 gen_load_even = gen_vec_setv8hi;
28506 gen_interleave_first_low = gen_vec_interleave_lowv4si;
28507 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28508 inner_mode = HImode;
28509 first_imode = V4SImode;
28510 second_imode = V2DImode;
28511 third_imode = VOIDmode;
28514 gen_load_even = gen_vec_setv16qi;
28515 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
28516 gen_interleave_second_low = gen_vec_interleave_lowv4si;
28517 inner_mode = QImode;
28518 first_imode = V8HImode;
28519 second_imode = V4SImode;
28520 third_imode = V2DImode;
28523 gcc_unreachable ();
28526 for (i = 0; i < n; i++)
28528 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
28529 op0 = gen_reg_rtx (SImode);
28530 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
28532 /* Insert the SImode value as low element of V4SImode vector. */
28533 op1 = gen_reg_rtx (V4SImode);
28534 op0 = gen_rtx_VEC_MERGE (V4SImode,
28535 gen_rtx_VEC_DUPLICATE (V4SImode,
28537 CONST0_RTX (V4SImode),
28539 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
28541 /* Cast the V4SImode vector back to a vector in orignal mode. */
28542 op0 = gen_reg_rtx (mode);
28543 emit_move_insn (op0, gen_lowpart (mode, op1));
28545 /* Load even elements into the second positon. */
28546 emit_insn ((*gen_load_even) (op0,
28547 force_reg (inner_mode,
28551 /* Cast vector to FIRST_IMODE vector. */
28552 ops[i] = gen_reg_rtx (first_imode);
28553 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
28556 /* Interleave low FIRST_IMODE vectors. */
28557 for (i = j = 0; i < n; i += 2, j++)
28559 op0 = gen_reg_rtx (first_imode);
28560 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
28562 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
28563 ops[j] = gen_reg_rtx (second_imode);
28564 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
28567 /* Interleave low SECOND_IMODE vectors. */
28568 switch (second_imode)
28571 for (i = j = 0; i < n / 2; i += 2, j++)
28573 op0 = gen_reg_rtx (second_imode);
28574 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
28577 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
28579 ops[j] = gen_reg_rtx (third_imode);
28580 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
28582 second_imode = V2DImode;
28583 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28587 op0 = gen_reg_rtx (second_imode);
28588 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
28591 /* Cast the SECOND_IMODE vector back to a vector on original
28593 emit_insn (gen_rtx_SET (VOIDmode, target,
28594 gen_lowpart (mode, op0)));
28598 gcc_unreachable ();
28602 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
28603 all values variable, and none identical. */
28606 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
28607 rtx target, rtx vals)
28609 rtx ops[32], op0, op1;
28610 enum machine_mode half_mode = VOIDmode;
28617 if (!mmx_ok && !TARGET_SSE)
28629 n = GET_MODE_NUNITS (mode);
28630 for (i = 0; i < n; i++)
28631 ops[i] = XVECEXP (vals, 0, i);
28632 ix86_expand_vector_init_concat (mode, target, ops, n);
28636 half_mode = V16QImode;
28640 half_mode = V8HImode;
28644 n = GET_MODE_NUNITS (mode);
28645 for (i = 0; i < n; i++)
28646 ops[i] = XVECEXP (vals, 0, i);
28647 op0 = gen_reg_rtx (half_mode);
28648 op1 = gen_reg_rtx (half_mode);
28649 ix86_expand_vector_init_interleave (half_mode, op0, ops,
28651 ix86_expand_vector_init_interleave (half_mode, op1,
28652 &ops [n >> 1], n >> 2);
28653 emit_insn (gen_rtx_SET (VOIDmode, target,
28654 gen_rtx_VEC_CONCAT (mode, op0, op1)));
28658 if (!TARGET_SSE4_1)
28666 /* Don't use ix86_expand_vector_init_interleave if we can't
28667 move from GPR to SSE register directly. */
28668 if (!TARGET_INTER_UNIT_MOVES)
28671 n = GET_MODE_NUNITS (mode);
28672 for (i = 0; i < n; i++)
28673 ops[i] = XVECEXP (vals, 0, i);
28674 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
28682 gcc_unreachable ();
28686 int i, j, n_elts, n_words, n_elt_per_word;
28687 enum machine_mode inner_mode;
28688 rtx words[4], shift;
28690 inner_mode = GET_MODE_INNER (mode);
28691 n_elts = GET_MODE_NUNITS (mode);
28692 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
28693 n_elt_per_word = n_elts / n_words;
28694 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
28696 for (i = 0; i < n_words; ++i)
28698 rtx word = NULL_RTX;
28700 for (j = 0; j < n_elt_per_word; ++j)
28702 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
28703 elt = convert_modes (word_mode, inner_mode, elt, true);
28709 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
28710 word, 1, OPTAB_LIB_WIDEN);
28711 word = expand_simple_binop (word_mode, IOR, word, elt,
28712 word, 1, OPTAB_LIB_WIDEN);
28720 emit_move_insn (target, gen_lowpart (mode, words[0]));
28721 else if (n_words == 2)
28723 rtx tmp = gen_reg_rtx (mode);
28724 emit_clobber (tmp);
28725 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
28726 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
28727 emit_move_insn (target, tmp);
28729 else if (n_words == 4)
28731 rtx tmp = gen_reg_rtx (V4SImode);
28732 gcc_assert (word_mode == SImode);
28733 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
28734 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
28735 emit_move_insn (target, gen_lowpart (mode, tmp));
28738 gcc_unreachable ();
28742 /* Initialize vector TARGET via VALS. Suppress the use of MMX
28743 instructions unless MMX_OK is true. */
28746 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
28748 enum machine_mode mode = GET_MODE (target);
28749 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28750 int n_elts = GET_MODE_NUNITS (mode);
28751 int n_var = 0, one_var = -1;
28752 bool all_same = true, all_const_zero = true;
28756 for (i = 0; i < n_elts; ++i)
28758 x = XVECEXP (vals, 0, i);
28759 if (!(CONST_INT_P (x)
28760 || GET_CODE (x) == CONST_DOUBLE
28761 || GET_CODE (x) == CONST_FIXED))
28762 n_var++, one_var = i;
28763 else if (x != CONST0_RTX (inner_mode))
28764 all_const_zero = false;
28765 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
28769 /* Constants are best loaded from the constant pool. */
28772 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
28776 /* If all values are identical, broadcast the value. */
28778 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
28779 XVECEXP (vals, 0, 0)))
28782 /* Values where only one field is non-constant are best loaded from
28783 the pool and overwritten via move later. */
28787 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
28788 XVECEXP (vals, 0, one_var),
28792 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
28796 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
28800 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
28802 enum machine_mode mode = GET_MODE (target);
28803 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28804 enum machine_mode half_mode;
28805 bool use_vec_merge = false;
28807 static rtx (*gen_extract[6][2]) (rtx, rtx)
28809 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
28810 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
28811 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
28812 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
28813 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
28814 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
28816 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28818 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28819 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28820 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28821 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28822 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28823 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28833 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28834 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28836 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28838 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28839 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28845 use_vec_merge = TARGET_SSE4_1;
28853 /* For the two element vectors, we implement a VEC_CONCAT with
28854 the extraction of the other element. */
28856 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28857 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28860 op0 = val, op1 = tmp;
28862 op0 = tmp, op1 = val;
28864 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28865 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28870 use_vec_merge = TARGET_SSE4_1;
28877 use_vec_merge = true;
28881 /* tmp = target = A B C D */
28882 tmp = copy_to_reg (target);
28883 /* target = A A B B */
28884 emit_insn (gen_sse_unpcklps (target, target, target));
28885 /* target = X A B B */
28886 ix86_expand_vector_set (false, target, val, 0);
28887 /* target = A X C D */
28888 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28889 const1_rtx, const0_rtx,
28890 GEN_INT (2+4), GEN_INT (3+4)));
28894 /* tmp = target = A B C D */
28895 tmp = copy_to_reg (target);
28896 /* tmp = X B C D */
28897 ix86_expand_vector_set (false, tmp, val, 0);
28898 /* target = A B X D */
28899 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28900 const0_rtx, const1_rtx,
28901 GEN_INT (0+4), GEN_INT (3+4)));
28905 /* tmp = target = A B C D */
28906 tmp = copy_to_reg (target);
28907 /* tmp = X B C D */
28908 ix86_expand_vector_set (false, tmp, val, 0);
28909 /* target = A B X D */
28910 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28911 const0_rtx, const1_rtx,
28912 GEN_INT (2+4), GEN_INT (0+4)));
28916 gcc_unreachable ();
28921 use_vec_merge = TARGET_SSE4_1;
28925 /* Element 0 handled by vec_merge below. */
28928 use_vec_merge = true;
28934 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28935 store into element 0, then shuffle them back. */
28939 order[0] = GEN_INT (elt);
28940 order[1] = const1_rtx;
28941 order[2] = const2_rtx;
28942 order[3] = GEN_INT (3);
28943 order[elt] = const0_rtx;
28945 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28946 order[1], order[2], order[3]));
28948 ix86_expand_vector_set (false, target, val, 0);
28950 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28951 order[1], order[2], order[3]));
28955 /* For SSE1, we have to reuse the V4SF code. */
28956 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28957 gen_lowpart (SFmode, val), elt);
28962 use_vec_merge = TARGET_SSE2;
28965 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28969 use_vec_merge = TARGET_SSE4_1;
28976 half_mode = V16QImode;
28982 half_mode = V8HImode;
28988 half_mode = V4SImode;
28994 half_mode = V2DImode;
29000 half_mode = V4SFmode;
29006 half_mode = V2DFmode;
29012 /* Compute offset. */
29016 gcc_assert (i <= 1);
29018 /* Extract the half. */
29019 tmp = gen_reg_rtx (half_mode);
29020 emit_insn ((*gen_extract[j][i]) (tmp, target));
29022 /* Put val in tmp at elt. */
29023 ix86_expand_vector_set (false, tmp, val, elt);
29026 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
29035 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
29036 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
29037 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29041 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29043 emit_move_insn (mem, target);
29045 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29046 emit_move_insn (tmp, val);
29048 emit_move_insn (target, mem);
29053 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
29055 enum machine_mode mode = GET_MODE (vec);
29056 enum machine_mode inner_mode = GET_MODE_INNER (mode);
29057 bool use_vec_extr = false;
29070 use_vec_extr = true;
29074 use_vec_extr = TARGET_SSE4_1;
29086 tmp = gen_reg_rtx (mode);
29087 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
29088 GEN_INT (elt), GEN_INT (elt),
29089 GEN_INT (elt+4), GEN_INT (elt+4)));
29093 tmp = gen_reg_rtx (mode);
29094 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
29098 gcc_unreachable ();
29101 use_vec_extr = true;
29106 use_vec_extr = TARGET_SSE4_1;
29120 tmp = gen_reg_rtx (mode);
29121 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
29122 GEN_INT (elt), GEN_INT (elt),
29123 GEN_INT (elt), GEN_INT (elt)));
29127 tmp = gen_reg_rtx (mode);
29128 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
29132 gcc_unreachable ();
29135 use_vec_extr = true;
29140 /* For SSE1, we have to reuse the V4SF code. */
29141 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
29142 gen_lowpart (V4SFmode, vec), elt);
29148 use_vec_extr = TARGET_SSE2;
29151 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
29155 use_vec_extr = TARGET_SSE4_1;
29159 /* ??? Could extract the appropriate HImode element and shift. */
29166 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
29167 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
29169 /* Let the rtl optimizers know about the zero extension performed. */
29170 if (inner_mode == QImode || inner_mode == HImode)
29172 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
29173 target = gen_lowpart (SImode, target);
29176 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29180 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29182 emit_move_insn (mem, vec);
29184 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29185 emit_move_insn (target, tmp);
29189 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
29190 pattern to reduce; DEST is the destination; IN is the input vector. */
29193 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
29195 rtx tmp1, tmp2, tmp3;
29197 tmp1 = gen_reg_rtx (V4SFmode);
29198 tmp2 = gen_reg_rtx (V4SFmode);
29199 tmp3 = gen_reg_rtx (V4SFmode);
29201 emit_insn (gen_sse_movhlps (tmp1, in, in));
29202 emit_insn (fn (tmp2, tmp1, in));
29204 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
29205 const1_rtx, const1_rtx,
29206 GEN_INT (1+4), GEN_INT (1+4)));
29207 emit_insn (fn (dest, tmp2, tmp3));
29210 /* Target hook for scalar_mode_supported_p. */
29212 ix86_scalar_mode_supported_p (enum machine_mode mode)
29214 if (DECIMAL_FLOAT_MODE_P (mode))
29215 return default_decimal_float_supported_p ();
29216 else if (mode == TFmode)
29219 return default_scalar_mode_supported_p (mode);
29222 /* Implements target hook vector_mode_supported_p. */
29224 ix86_vector_mode_supported_p (enum machine_mode mode)
29226 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
29228 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
29230 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
29232 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
29234 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
29239 /* Target hook for c_mode_for_suffix. */
29240 static enum machine_mode
29241 ix86_c_mode_for_suffix (char suffix)
29251 /* Worker function for TARGET_MD_ASM_CLOBBERS.
29253 We do this in the new i386 backend to maintain source compatibility
29254 with the old cc0-based compiler. */
29257 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
29258 tree inputs ATTRIBUTE_UNUSED,
29261 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
29263 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
29268 /* Implements target vector targetm.asm.encode_section_info. This
29269 is not used by netware. */
29271 static void ATTRIBUTE_UNUSED
29272 ix86_encode_section_info (tree decl, rtx rtl, int first)
29274 default_encode_section_info (decl, rtl, first);
29276 if (TREE_CODE (decl) == VAR_DECL
29277 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
29278 && ix86_in_large_data_p (decl))
29279 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
29282 /* Worker function for REVERSE_CONDITION. */
29285 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
29287 return (mode != CCFPmode && mode != CCFPUmode
29288 ? reverse_condition (code)
29289 : reverse_condition_maybe_unordered (code));
29292 /* Output code to perform an x87 FP register move, from OPERANDS[1]
29296 output_387_reg_move (rtx insn, rtx *operands)
29298 if (REG_P (operands[0]))
29300 if (REG_P (operands[1])
29301 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29303 if (REGNO (operands[0]) == FIRST_STACK_REG)
29304 return output_387_ffreep (operands, 0);
29305 return "fstp\t%y0";
29307 if (STACK_TOP_P (operands[0]))
29308 return "fld%Z1\t%y1";
29311 else if (MEM_P (operands[0]))
29313 gcc_assert (REG_P (operands[1]));
29314 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29315 return "fstp%Z0\t%y0";
29318 /* There is no non-popping store to memory for XFmode.
29319 So if we need one, follow the store with a load. */
29320 if (GET_MODE (operands[0]) == XFmode)
29321 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
29323 return "fst%Z0\t%y0";
29330 /* Output code to perform a conditional jump to LABEL, if C2 flag in
29331 FP status register is set. */
29334 ix86_emit_fp_unordered_jump (rtx label)
29336 rtx reg = gen_reg_rtx (HImode);
29339 emit_insn (gen_x86_fnstsw_1 (reg));
29341 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
29343 emit_insn (gen_x86_sahf_1 (reg));
29345 temp = gen_rtx_REG (CCmode, FLAGS_REG);
29346 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
29350 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
29352 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
29353 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
29356 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
29357 gen_rtx_LABEL_REF (VOIDmode, label),
29359 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
29361 emit_jump_insn (temp);
29362 predict_jump (REG_BR_PROB_BASE * 10 / 100);
29365 /* Output code to perform a log1p XFmode calculation. */
29367 void ix86_emit_i387_log1p (rtx op0, rtx op1)
29369 rtx label1 = gen_label_rtx ();
29370 rtx label2 = gen_label_rtx ();
29372 rtx tmp = gen_reg_rtx (XFmode);
29373 rtx tmp2 = gen_reg_rtx (XFmode);
29376 emit_insn (gen_absxf2 (tmp, op1));
29377 test = gen_rtx_GE (VOIDmode, tmp,
29378 CONST_DOUBLE_FROM_REAL_VALUE (
29379 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
29381 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
29383 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29384 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
29385 emit_jump (label2);
29387 emit_label (label1);
29388 emit_move_insn (tmp, CONST1_RTX (XFmode));
29389 emit_insn (gen_addxf3 (tmp, op1, tmp));
29390 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29391 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
29393 emit_label (label2);
29396 /* Output code to perform a Newton-Rhapson approximation of a single precision
29397 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
29399 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
29401 rtx x0, x1, e0, e1, two;
29403 x0 = gen_reg_rtx (mode);
29404 e0 = gen_reg_rtx (mode);
29405 e1 = gen_reg_rtx (mode);
29406 x1 = gen_reg_rtx (mode);
29408 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
29410 if (VECTOR_MODE_P (mode))
29411 two = ix86_build_const_vector (SFmode, true, two);
29413 two = force_reg (mode, two);
29415 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
29417 /* x0 = rcp(b) estimate */
29418 emit_insn (gen_rtx_SET (VOIDmode, x0,
29419 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
29422 emit_insn (gen_rtx_SET (VOIDmode, e0,
29423 gen_rtx_MULT (mode, x0, a)));
29425 emit_insn (gen_rtx_SET (VOIDmode, e1,
29426 gen_rtx_MULT (mode, x0, b)));
29428 emit_insn (gen_rtx_SET (VOIDmode, x1,
29429 gen_rtx_MINUS (mode, two, e1)));
29430 /* res = e0 * x1 */
29431 emit_insn (gen_rtx_SET (VOIDmode, res,
29432 gen_rtx_MULT (mode, e0, x1)));
29435 /* Output code to perform a Newton-Rhapson approximation of a
29436 single precision floating point [reciprocal] square root. */
29438 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
29441 rtx x0, e0, e1, e2, e3, mthree, mhalf;
29444 x0 = gen_reg_rtx (mode);
29445 e0 = gen_reg_rtx (mode);
29446 e1 = gen_reg_rtx (mode);
29447 e2 = gen_reg_rtx (mode);
29448 e3 = gen_reg_rtx (mode);
29450 real_from_integer (&r, VOIDmode, -3, -1, 0);
29451 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29453 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
29454 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29456 if (VECTOR_MODE_P (mode))
29458 mthree = ix86_build_const_vector (SFmode, true, mthree);
29459 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
29462 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
29463 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
29465 /* x0 = rsqrt(a) estimate */
29466 emit_insn (gen_rtx_SET (VOIDmode, x0,
29467 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
29470 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
29475 zero = gen_reg_rtx (mode);
29476 mask = gen_reg_rtx (mode);
29478 zero = force_reg (mode, CONST0_RTX(mode));
29479 emit_insn (gen_rtx_SET (VOIDmode, mask,
29480 gen_rtx_NE (mode, zero, a)));
29482 emit_insn (gen_rtx_SET (VOIDmode, x0,
29483 gen_rtx_AND (mode, x0, mask)));
29487 emit_insn (gen_rtx_SET (VOIDmode, e0,
29488 gen_rtx_MULT (mode, x0, a)));
29490 emit_insn (gen_rtx_SET (VOIDmode, e1,
29491 gen_rtx_MULT (mode, e0, x0)));
29494 mthree = force_reg (mode, mthree);
29495 emit_insn (gen_rtx_SET (VOIDmode, e2,
29496 gen_rtx_PLUS (mode, e1, mthree)));
29498 mhalf = force_reg (mode, mhalf);
29500 /* e3 = -.5 * x0 */
29501 emit_insn (gen_rtx_SET (VOIDmode, e3,
29502 gen_rtx_MULT (mode, x0, mhalf)));
29504 /* e3 = -.5 * e0 */
29505 emit_insn (gen_rtx_SET (VOIDmode, e3,
29506 gen_rtx_MULT (mode, e0, mhalf)));
29507 /* ret = e2 * e3 */
29508 emit_insn (gen_rtx_SET (VOIDmode, res,
29509 gen_rtx_MULT (mode, e2, e3)));
29512 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
29514 static void ATTRIBUTE_UNUSED
29515 i386_solaris_elf_named_section (const char *name, unsigned int flags,
29518 /* With Binutils 2.15, the "@unwind" marker must be specified on
29519 every occurrence of the ".eh_frame" section, not just the first
29522 && strcmp (name, ".eh_frame") == 0)
29524 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
29525 flags & SECTION_WRITE ? "aw" : "a");
29528 default_elf_asm_named_section (name, flags, decl);
29531 /* Return the mangling of TYPE if it is an extended fundamental type. */
29533 static const char *
29534 ix86_mangle_type (const_tree type)
29536 type = TYPE_MAIN_VARIANT (type);
29538 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
29539 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
29542 switch (TYPE_MODE (type))
29545 /* __float128 is "g". */
29548 /* "long double" or __float80 is "e". */
29555 /* For 32-bit code we can save PIC register setup by using
29556 __stack_chk_fail_local hidden function instead of calling
29557 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
29558 register, so it is better to call __stack_chk_fail directly. */
29561 ix86_stack_protect_fail (void)
29563 return TARGET_64BIT
29564 ? default_external_stack_protect_fail ()
29565 : default_hidden_stack_protect_fail ();
29568 /* Select a format to encode pointers in exception handling data. CODE
29569 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
29570 true if the symbol may be affected by dynamic relocations.
29572 ??? All x86 object file formats are capable of representing this.
29573 After all, the relocation needed is the same as for the call insn.
29574 Whether or not a particular assembler allows us to enter such, I
29575 guess we'll have to see. */
29577 asm_preferred_eh_data_format (int code, int global)
29581 int type = DW_EH_PE_sdata8;
29583 || ix86_cmodel == CM_SMALL_PIC
29584 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
29585 type = DW_EH_PE_sdata4;
29586 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
29588 if (ix86_cmodel == CM_SMALL
29589 || (ix86_cmodel == CM_MEDIUM && code))
29590 return DW_EH_PE_udata4;
29591 return DW_EH_PE_absptr;
29594 /* Expand copysign from SIGN to the positive value ABS_VALUE
29595 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
29598 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
29600 enum machine_mode mode = GET_MODE (sign);
29601 rtx sgn = gen_reg_rtx (mode);
29602 if (mask == NULL_RTX)
29604 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
29605 if (!VECTOR_MODE_P (mode))
29607 /* We need to generate a scalar mode mask in this case. */
29608 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29609 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29610 mask = gen_reg_rtx (mode);
29611 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29615 mask = gen_rtx_NOT (mode, mask);
29616 emit_insn (gen_rtx_SET (VOIDmode, sgn,
29617 gen_rtx_AND (mode, mask, sign)));
29618 emit_insn (gen_rtx_SET (VOIDmode, result,
29619 gen_rtx_IOR (mode, abs_value, sgn)));
29622 /* Expand fabs (OP0) and return a new rtx that holds the result. The
29623 mask for masking out the sign-bit is stored in *SMASK, if that is
29626 ix86_expand_sse_fabs (rtx op0, rtx *smask)
29628 enum machine_mode mode = GET_MODE (op0);
29631 xa = gen_reg_rtx (mode);
29632 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
29633 if (!VECTOR_MODE_P (mode))
29635 /* We need to generate a scalar mode mask in this case. */
29636 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29637 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29638 mask = gen_reg_rtx (mode);
29639 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29641 emit_insn (gen_rtx_SET (VOIDmode, xa,
29642 gen_rtx_AND (mode, op0, mask)));
29650 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
29651 swapping the operands if SWAP_OPERANDS is true. The expanded
29652 code is a forward jump to a newly created label in case the
29653 comparison is true. The generated label rtx is returned. */
29655 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
29656 bool swap_operands)
29667 label = gen_label_rtx ();
29668 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
29669 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29670 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
29671 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
29672 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
29673 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
29674 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
29675 JUMP_LABEL (tmp) = label;
29680 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
29681 using comparison code CODE. Operands are swapped for the comparison if
29682 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
29684 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
29685 bool swap_operands)
29687 enum machine_mode mode = GET_MODE (op0);
29688 rtx mask = gen_reg_rtx (mode);
29697 if (mode == DFmode)
29698 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
29699 gen_rtx_fmt_ee (code, mode, op0, op1)));
29701 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
29702 gen_rtx_fmt_ee (code, mode, op0, op1)));
29707 /* Generate and return a rtx of mode MODE for 2**n where n is the number
29708 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
29710 ix86_gen_TWO52 (enum machine_mode mode)
29712 REAL_VALUE_TYPE TWO52r;
29715 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
29716 TWO52 = const_double_from_real_value (TWO52r, mode);
29717 TWO52 = force_reg (mode, TWO52);
29722 /* Expand SSE sequence for computing lround from OP1 storing
29725 ix86_expand_lround (rtx op0, rtx op1)
29727 /* C code for the stuff we're doing below:
29728 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
29731 enum machine_mode mode = GET_MODE (op1);
29732 const struct real_format *fmt;
29733 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29736 /* load nextafter (0.5, 0.0) */
29737 fmt = REAL_MODE_FORMAT (mode);
29738 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29739 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29741 /* adj = copysign (0.5, op1) */
29742 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
29743 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
29745 /* adj = op1 + adj */
29746 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
29748 /* op0 = (imode)adj */
29749 expand_fix (op0, adj, 0);
29752 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
29755 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
29757 /* C code for the stuff we're doing below (for do_floor):
29759 xi -= (double)xi > op1 ? 1 : 0;
29762 enum machine_mode fmode = GET_MODE (op1);
29763 enum machine_mode imode = GET_MODE (op0);
29764 rtx ireg, freg, label, tmp;
29766 /* reg = (long)op1 */
29767 ireg = gen_reg_rtx (imode);
29768 expand_fix (ireg, op1, 0);
29770 /* freg = (double)reg */
29771 freg = gen_reg_rtx (fmode);
29772 expand_float (freg, ireg, 0);
29774 /* ireg = (freg > op1) ? ireg - 1 : ireg */
29775 label = ix86_expand_sse_compare_and_jump (UNLE,
29776 freg, op1, !do_floor);
29777 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
29778 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
29779 emit_move_insn (ireg, tmp);
29781 emit_label (label);
29782 LABEL_NUSES (label) = 1;
29784 emit_move_insn (op0, ireg);
29787 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
29788 result in OPERAND0. */
29790 ix86_expand_rint (rtx operand0, rtx operand1)
29792 /* C code for the stuff we're doing below:
29793 xa = fabs (operand1);
29794 if (!isless (xa, 2**52))
29796 xa = xa + 2**52 - 2**52;
29797 return copysign (xa, operand1);
29799 enum machine_mode mode = GET_MODE (operand0);
29800 rtx res, xa, label, TWO52, mask;
29802 res = gen_reg_rtx (mode);
29803 emit_move_insn (res, operand1);
29805 /* xa = abs (operand1) */
29806 xa = ix86_expand_sse_fabs (res, &mask);
29808 /* if (!isless (xa, TWO52)) goto label; */
29809 TWO52 = ix86_gen_TWO52 (mode);
29810 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29812 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29813 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29815 ix86_sse_copysign_to_positive (res, xa, res, mask);
29817 emit_label (label);
29818 LABEL_NUSES (label) = 1;
29820 emit_move_insn (operand0, res);
29823 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29826 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29828 /* C code for the stuff we expand below.
29829 double xa = fabs (x), x2;
29830 if (!isless (xa, TWO52))
29832 xa = xa + TWO52 - TWO52;
29833 x2 = copysign (xa, x);
29842 enum machine_mode mode = GET_MODE (operand0);
29843 rtx xa, TWO52, tmp, label, one, res, mask;
29845 TWO52 = ix86_gen_TWO52 (mode);
29847 /* Temporary for holding the result, initialized to the input
29848 operand to ease control flow. */
29849 res = gen_reg_rtx (mode);
29850 emit_move_insn (res, operand1);
29852 /* xa = abs (operand1) */
29853 xa = ix86_expand_sse_fabs (res, &mask);
29855 /* if (!isless (xa, TWO52)) goto label; */
29856 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29858 /* xa = xa + TWO52 - TWO52; */
29859 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29860 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29862 /* xa = copysign (xa, operand1) */
29863 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29865 /* generate 1.0 or -1.0 */
29866 one = force_reg (mode,
29867 const_double_from_real_value (do_floor
29868 ? dconst1 : dconstm1, mode));
29870 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29871 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29872 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29873 gen_rtx_AND (mode, one, tmp)));
29874 /* We always need to subtract here to preserve signed zero. */
29875 tmp = expand_simple_binop (mode, MINUS,
29876 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29877 emit_move_insn (res, tmp);
29879 emit_label (label);
29880 LABEL_NUSES (label) = 1;
29882 emit_move_insn (operand0, res);
29885 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29888 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29890 /* C code for the stuff we expand below.
29891 double xa = fabs (x), x2;
29892 if (!isless (xa, TWO52))
29894 x2 = (double)(long)x;
29901 if (HONOR_SIGNED_ZEROS (mode))
29902 return copysign (x2, x);
29905 enum machine_mode mode = GET_MODE (operand0);
29906 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29908 TWO52 = ix86_gen_TWO52 (mode);
29910 /* Temporary for holding the result, initialized to the input
29911 operand to ease control flow. */
29912 res = gen_reg_rtx (mode);
29913 emit_move_insn (res, operand1);
29915 /* xa = abs (operand1) */
29916 xa = ix86_expand_sse_fabs (res, &mask);
29918 /* if (!isless (xa, TWO52)) goto label; */
29919 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29921 /* xa = (double)(long)x */
29922 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29923 expand_fix (xi, res, 0);
29924 expand_float (xa, xi, 0);
29927 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29929 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29930 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29931 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29932 gen_rtx_AND (mode, one, tmp)));
29933 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29934 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29935 emit_move_insn (res, tmp);
29937 if (HONOR_SIGNED_ZEROS (mode))
29938 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29940 emit_label (label);
29941 LABEL_NUSES (label) = 1;
29943 emit_move_insn (operand0, res);
29946 /* Expand SSE sequence for computing round from OPERAND1 storing
29947 into OPERAND0. Sequence that works without relying on DImode truncation
29948 via cvttsd2siq that is only available on 64bit targets. */
29950 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29952 /* C code for the stuff we expand below.
29953 double xa = fabs (x), xa2, x2;
29954 if (!isless (xa, TWO52))
29956 Using the absolute value and copying back sign makes
29957 -0.0 -> -0.0 correct.
29958 xa2 = xa + TWO52 - TWO52;
29963 else if (dxa > 0.5)
29965 x2 = copysign (xa2, x);
29968 enum machine_mode mode = GET_MODE (operand0);
29969 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29971 TWO52 = ix86_gen_TWO52 (mode);
29973 /* Temporary for holding the result, initialized to the input
29974 operand to ease control flow. */
29975 res = gen_reg_rtx (mode);
29976 emit_move_insn (res, operand1);
29978 /* xa = abs (operand1) */
29979 xa = ix86_expand_sse_fabs (res, &mask);
29981 /* if (!isless (xa, TWO52)) goto label; */
29982 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29984 /* xa2 = xa + TWO52 - TWO52; */
29985 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29986 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29988 /* dxa = xa2 - xa; */
29989 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29991 /* generate 0.5, 1.0 and -0.5 */
29992 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29993 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29994 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29998 tmp = gen_reg_rtx (mode);
29999 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
30000 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
30001 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30002 gen_rtx_AND (mode, one, tmp)));
30003 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30004 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
30005 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
30006 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30007 gen_rtx_AND (mode, one, tmp)));
30008 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30010 /* res = copysign (xa2, operand1) */
30011 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
30013 emit_label (label);
30014 LABEL_NUSES (label) = 1;
30016 emit_move_insn (operand0, res);
30019 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30022 ix86_expand_trunc (rtx operand0, rtx operand1)
30024 /* C code for SSE variant we expand below.
30025 double xa = fabs (x), x2;
30026 if (!isless (xa, TWO52))
30028 x2 = (double)(long)x;
30029 if (HONOR_SIGNED_ZEROS (mode))
30030 return copysign (x2, x);
30033 enum machine_mode mode = GET_MODE (operand0);
30034 rtx xa, xi, TWO52, label, res, mask;
30036 TWO52 = ix86_gen_TWO52 (mode);
30038 /* Temporary for holding the result, initialized to the input
30039 operand to ease control flow. */
30040 res = gen_reg_rtx (mode);
30041 emit_move_insn (res, operand1);
30043 /* xa = abs (operand1) */
30044 xa = ix86_expand_sse_fabs (res, &mask);
30046 /* if (!isless (xa, TWO52)) goto label; */
30047 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30049 /* x = (double)(long)x */
30050 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30051 expand_fix (xi, res, 0);
30052 expand_float (res, xi, 0);
30054 if (HONOR_SIGNED_ZEROS (mode))
30055 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
30057 emit_label (label);
30058 LABEL_NUSES (label) = 1;
30060 emit_move_insn (operand0, res);
30063 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30066 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
30068 enum machine_mode mode = GET_MODE (operand0);
30069 rtx xa, mask, TWO52, label, one, res, smask, tmp;
30071 /* C code for SSE variant we expand below.
30072 double xa = fabs (x), x2;
30073 if (!isless (xa, TWO52))
30075 xa2 = xa + TWO52 - TWO52;
30079 x2 = copysign (xa2, x);
30083 TWO52 = ix86_gen_TWO52 (mode);
30085 /* Temporary for holding the result, initialized to the input
30086 operand to ease control flow. */
30087 res = gen_reg_rtx (mode);
30088 emit_move_insn (res, operand1);
30090 /* xa = abs (operand1) */
30091 xa = ix86_expand_sse_fabs (res, &smask);
30093 /* if (!isless (xa, TWO52)) goto label; */
30094 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30096 /* res = xa + TWO52 - TWO52; */
30097 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
30098 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
30099 emit_move_insn (res, tmp);
30102 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
30104 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
30105 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
30106 emit_insn (gen_rtx_SET (VOIDmode, mask,
30107 gen_rtx_AND (mode, mask, one)));
30108 tmp = expand_simple_binop (mode, MINUS,
30109 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
30110 emit_move_insn (res, tmp);
30112 /* res = copysign (res, operand1) */
30113 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
30115 emit_label (label);
30116 LABEL_NUSES (label) = 1;
30118 emit_move_insn (operand0, res);
30121 /* Expand SSE sequence for computing round from OPERAND1 storing
30124 ix86_expand_round (rtx operand0, rtx operand1)
30126 /* C code for the stuff we're doing below:
30127 double xa = fabs (x);
30128 if (!isless (xa, TWO52))
30130 xa = (double)(long)(xa + nextafter (0.5, 0.0));
30131 return copysign (xa, x);
30133 enum machine_mode mode = GET_MODE (operand0);
30134 rtx res, TWO52, xa, label, xi, half, mask;
30135 const struct real_format *fmt;
30136 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
30138 /* Temporary for holding the result, initialized to the input
30139 operand to ease control flow. */
30140 res = gen_reg_rtx (mode);
30141 emit_move_insn (res, operand1);
30143 TWO52 = ix86_gen_TWO52 (mode);
30144 xa = ix86_expand_sse_fabs (res, &mask);
30145 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30147 /* load nextafter (0.5, 0.0) */
30148 fmt = REAL_MODE_FORMAT (mode);
30149 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
30150 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
30152 /* xa = xa + 0.5 */
30153 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
30154 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
30156 /* xa = (double)(int64_t)xa */
30157 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30158 expand_fix (xi, xa, 0);
30159 expand_float (xa, xi, 0);
30161 /* res = copysign (xa, operand1) */
30162 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
30164 emit_label (label);
30165 LABEL_NUSES (label) = 1;
30167 emit_move_insn (operand0, res);
30170 /* Validate whether a FMA4 instruction is valid or not.
30171 OPERANDS is the array of operands.
30172 NUM is the number of operands.
30173 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
30174 NUM_MEMORY is the maximum number of memory operands to accept.
30175 NUM_MEMORY less than zero is a special case to allow an operand
30176 of an instruction to be memory operation.
30177 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
30180 ix86_fma4_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
30181 bool uses_oc0, int num_memory, bool commutative)
30187 /* Count the number of memory arguments */
30190 for (i = 0; i < num; i++)
30192 enum machine_mode mode = GET_MODE (operands[i]);
30193 if (register_operand (operands[i], mode))
30196 else if (memory_operand (operands[i], mode))
30198 mem_mask |= (1 << i);
30204 rtx pattern = PATTERN (insn);
30206 /* allow 0 for pcmov */
30207 if (GET_CODE (pattern) != SET
30208 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
30210 || operands[i] != CONST0_RTX (mode))
30215 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
30216 a memory operation. */
30217 if (num_memory < 0)
30219 num_memory = -num_memory;
30220 if ((mem_mask & (1 << (num-1))) != 0)
30222 mem_mask &= ~(1 << (num-1));
30227 /* If there were no memory operations, allow the insn */
30231 /* Do not allow the destination register to be a memory operand. */
30232 else if (mem_mask & (1 << 0))
30235 /* If there are too many memory operations, disallow the instruction. While
30236 the hardware only allows 1 memory reference, before register allocation
30237 for some insns, we allow two memory operations sometimes in order to allow
30238 code like the following to be optimized:
30240 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
30242 or similar cases that are vectorized into using the vfmaddss
30244 else if (mem_count > num_memory)
30247 /* Don't allow more than one memory operation if not optimizing. */
30248 else if (mem_count > 1 && !optimize)
30251 else if (num == 4 && mem_count == 1)
30253 /* formats (destination is the first argument), example vfmaddss:
30254 xmm1, xmm1, xmm2, xmm3/mem
30255 xmm1, xmm1, xmm2/mem, xmm3
30256 xmm1, xmm2, xmm3/mem, xmm1
30257 xmm1, xmm2/mem, xmm3, xmm1 */
30259 return ((mem_mask == (1 << 1))
30260 || (mem_mask == (1 << 2))
30261 || (mem_mask == (1 << 3)));
30263 /* format, example vpmacsdd:
30264 xmm1, xmm2, xmm3/mem, xmm1 */
30266 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
30268 return (mem_mask == (1 << 2));
30271 else if (num == 4 && num_memory == 2)
30273 /* If there are two memory operations, we can load one of the memory ops
30274 into the destination register. This is for optimizing the
30275 multiply/add ops, which the combiner has optimized both the multiply
30276 and the add insns to have a memory operation. We have to be careful
30277 that the destination doesn't overlap with the inputs. */
30278 rtx op0 = operands[0];
30280 if (reg_mentioned_p (op0, operands[1])
30281 || reg_mentioned_p (op0, operands[2])
30282 || reg_mentioned_p (op0, operands[3]))
30285 /* formats (destination is the first argument), example vfmaddss:
30286 xmm1, xmm1, xmm2, xmm3/mem
30287 xmm1, xmm1, xmm2/mem, xmm3
30288 xmm1, xmm2, xmm3/mem, xmm1
30289 xmm1, xmm2/mem, xmm3, xmm1
30291 For the oc0 case, we will load either operands[1] or operands[3] into
30292 operands[0], so any combination of 2 memory operands is ok. */
30296 /* format, example vpmacsdd:
30297 xmm1, xmm2, xmm3/mem, xmm1
30299 For the integer multiply/add instructions be more restrictive and
30300 require operands[2] and operands[3] to be the memory operands. */
30302 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
30304 return (mem_mask == ((1 << 2) | (1 << 3)));
30307 else if (num == 3 && num_memory == 1)
30309 /* formats, example vprotb:
30310 xmm1, xmm2, xmm3/mem
30311 xmm1, xmm2/mem, xmm3 */
30313 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
30315 /* format, example vpcomeq:
30316 xmm1, xmm2, xmm3/mem */
30318 return (mem_mask == (1 << 2));
30322 gcc_unreachable ();
30328 /* Fixup an FMA4 instruction that has 2 memory input references into a form the
30329 hardware will allow by using the destination register to load one of the
30330 memory operations. Presently this is used by the multiply/add routines to
30331 allow 2 memory references. */
30334 ix86_expand_fma4_multiple_memory (rtx operands[],
30336 enum machine_mode mode)
30338 rtx op0 = operands[0];
30340 || memory_operand (op0, mode)
30341 || reg_mentioned_p (op0, operands[1])
30342 || reg_mentioned_p (op0, operands[2])
30343 || reg_mentioned_p (op0, operands[3]))
30344 gcc_unreachable ();
30346 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
30347 the destination register. */
30348 if (memory_operand (operands[1], mode))
30350 emit_move_insn (op0, operands[1]);
30353 else if (memory_operand (operands[3], mode))
30355 emit_move_insn (op0, operands[3]);
30359 gcc_unreachable ();
30364 /* Table of valid machine attributes. */
30365 static const struct attribute_spec ix86_attribute_table[] =
30367 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
30368 /* Stdcall attribute says callee is responsible for popping arguments
30369 if they are not variable. */
30370 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30371 /* Fastcall attribute says callee is responsible for popping arguments
30372 if they are not variable. */
30373 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30374 /* Cdecl attribute says the callee is a normal C declaration */
30375 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30376 /* Regparm attribute specifies how many integer arguments are to be
30377 passed in registers. */
30378 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
30379 /* Sseregparm attribute says we are using x86_64 calling conventions
30380 for FP arguments. */
30381 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30382 /* force_align_arg_pointer says this function realigns the stack at entry. */
30383 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
30384 false, true, true, ix86_handle_cconv_attribute },
30385 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30386 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
30387 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
30388 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
30390 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30391 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30392 #ifdef SUBTARGET_ATTRIBUTE_TABLE
30393 SUBTARGET_ATTRIBUTE_TABLE,
30395 /* ms_abi and sysv_abi calling convention function attributes. */
30396 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30397 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30398 { "ms_hook_prologue", 0, 0, true, false, false, ix86_handle_fndecl_attribute },
30400 { NULL, 0, 0, false, false, false, NULL }
30403 /* Implement targetm.vectorize.builtin_vectorization_cost. */
30405 x86_builtin_vectorization_cost (bool runtime_test)
30407 /* If the branch of the runtime test is taken - i.e. - the vectorized
30408 version is skipped - this incurs a misprediction cost (because the
30409 vectorized version is expected to be the fall-through). So we subtract
30410 the latency of a mispredicted branch from the costs that are incured
30411 when the vectorized version is executed.
30413 TODO: The values in individual target tables have to be tuned or new
30414 fields may be needed. For eg. on K8, the default branch path is the
30415 not-taken path. If the taken path is predicted correctly, the minimum
30416 penalty of going down the taken-path is 1 cycle. If the taken-path is
30417 not predicted correctly, then the minimum penalty is 10 cycles. */
30421 return (-(ix86_cost->cond_taken_branch_cost));
30427 /* This function returns the calling abi specific va_list type node.
30428 It returns the FNDECL specific va_list type. */
30431 ix86_fn_abi_va_list (tree fndecl)
30434 return va_list_type_node;
30435 gcc_assert (fndecl != NULL_TREE);
30437 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
30438 return ms_va_list_type_node;
30440 return sysv_va_list_type_node;
30443 /* Returns the canonical va_list type specified by TYPE. If there
30444 is no valid TYPE provided, it return NULL_TREE. */
30447 ix86_canonical_va_list_type (tree type)
30451 /* Resolve references and pointers to va_list type. */
30452 if (INDIRECT_REF_P (type))
30453 type = TREE_TYPE (type);
30454 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
30455 type = TREE_TYPE (type);
30459 wtype = va_list_type_node;
30460 gcc_assert (wtype != NULL_TREE);
30462 if (TREE_CODE (wtype) == ARRAY_TYPE)
30464 /* If va_list is an array type, the argument may have decayed
30465 to a pointer type, e.g. by being passed to another function.
30466 In that case, unwrap both types so that we can compare the
30467 underlying records. */
30468 if (TREE_CODE (htype) == ARRAY_TYPE
30469 || POINTER_TYPE_P (htype))
30471 wtype = TREE_TYPE (wtype);
30472 htype = TREE_TYPE (htype);
30475 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30476 return va_list_type_node;
30477 wtype = sysv_va_list_type_node;
30478 gcc_assert (wtype != NULL_TREE);
30480 if (TREE_CODE (wtype) == ARRAY_TYPE)
30482 /* If va_list is an array type, the argument may have decayed
30483 to a pointer type, e.g. by being passed to another function.
30484 In that case, unwrap both types so that we can compare the
30485 underlying records. */
30486 if (TREE_CODE (htype) == ARRAY_TYPE
30487 || POINTER_TYPE_P (htype))
30489 wtype = TREE_TYPE (wtype);
30490 htype = TREE_TYPE (htype);
30493 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30494 return sysv_va_list_type_node;
30495 wtype = ms_va_list_type_node;
30496 gcc_assert (wtype != NULL_TREE);
30498 if (TREE_CODE (wtype) == ARRAY_TYPE)
30500 /* If va_list is an array type, the argument may have decayed
30501 to a pointer type, e.g. by being passed to another function.
30502 In that case, unwrap both types so that we can compare the
30503 underlying records. */
30504 if (TREE_CODE (htype) == ARRAY_TYPE
30505 || POINTER_TYPE_P (htype))
30507 wtype = TREE_TYPE (wtype);
30508 htype = TREE_TYPE (htype);
30511 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30512 return ms_va_list_type_node;
30515 return std_canonical_va_list_type (type);
30518 /* Iterate through the target-specific builtin types for va_list.
30519 IDX denotes the iterator, *PTREE is set to the result type of
30520 the va_list builtin, and *PNAME to its internal type.
30521 Returns zero if there is no element for this index, otherwise
30522 IDX should be increased upon the next call.
30523 Note, do not iterate a base builtin's name like __builtin_va_list.
30524 Used from c_common_nodes_and_builtins. */
30527 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
30533 *ptree = ms_va_list_type_node;
30534 *pname = "__builtin_ms_va_list";
30537 *ptree = sysv_va_list_type_node;
30538 *pname = "__builtin_sysv_va_list";
30546 /* Initialize the GCC target structure. */
30547 #undef TARGET_RETURN_IN_MEMORY
30548 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30550 #undef TARGET_LEGITIMIZE_ADDRESS
30551 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30553 #undef TARGET_ATTRIBUTE_TABLE
30554 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30555 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30556 # undef TARGET_MERGE_DECL_ATTRIBUTES
30557 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30560 #undef TARGET_COMP_TYPE_ATTRIBUTES
30561 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30563 #undef TARGET_INIT_BUILTINS
30564 #define TARGET_INIT_BUILTINS ix86_init_builtins
30565 #undef TARGET_BUILTIN_DECL
30566 #define TARGET_BUILTIN_DECL ix86_builtin_decl
30567 #undef TARGET_EXPAND_BUILTIN
30568 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30570 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30571 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30572 ix86_builtin_vectorized_function
30574 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30575 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30577 #undef TARGET_BUILTIN_RECIPROCAL
30578 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30580 #undef TARGET_ASM_FUNCTION_EPILOGUE
30581 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30583 #undef TARGET_ENCODE_SECTION_INFO
30584 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30585 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30587 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30590 #undef TARGET_ASM_OPEN_PAREN
30591 #define TARGET_ASM_OPEN_PAREN ""
30592 #undef TARGET_ASM_CLOSE_PAREN
30593 #define TARGET_ASM_CLOSE_PAREN ""
30595 #undef TARGET_ASM_BYTE_OP
30596 #define TARGET_ASM_BYTE_OP ASM_BYTE
30598 #undef TARGET_ASM_ALIGNED_HI_OP
30599 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30600 #undef TARGET_ASM_ALIGNED_SI_OP
30601 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30603 #undef TARGET_ASM_ALIGNED_DI_OP
30604 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30607 #undef TARGET_ASM_UNALIGNED_HI_OP
30608 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30609 #undef TARGET_ASM_UNALIGNED_SI_OP
30610 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30611 #undef TARGET_ASM_UNALIGNED_DI_OP
30612 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30614 #undef TARGET_SCHED_ADJUST_COST
30615 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30616 #undef TARGET_SCHED_ISSUE_RATE
30617 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30618 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30619 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30620 ia32_multipass_dfa_lookahead
30622 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30623 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30626 #undef TARGET_HAVE_TLS
30627 #define TARGET_HAVE_TLS true
30629 #undef TARGET_CANNOT_FORCE_CONST_MEM
30630 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30631 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30632 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30634 #undef TARGET_DELEGITIMIZE_ADDRESS
30635 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30637 #undef TARGET_MS_BITFIELD_LAYOUT_P
30638 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30641 #undef TARGET_BINDS_LOCAL_P
30642 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30644 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30645 #undef TARGET_BINDS_LOCAL_P
30646 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30649 #undef TARGET_ASM_OUTPUT_MI_THUNK
30650 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30651 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30652 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30654 #undef TARGET_ASM_FILE_START
30655 #define TARGET_ASM_FILE_START x86_file_start
30657 #undef TARGET_DEFAULT_TARGET_FLAGS
30658 #define TARGET_DEFAULT_TARGET_FLAGS \
30660 | TARGET_SUBTARGET_DEFAULT \
30661 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
30663 #undef TARGET_HANDLE_OPTION
30664 #define TARGET_HANDLE_OPTION ix86_handle_option
30666 #undef TARGET_RTX_COSTS
30667 #define TARGET_RTX_COSTS ix86_rtx_costs
30668 #undef TARGET_ADDRESS_COST
30669 #define TARGET_ADDRESS_COST ix86_address_cost
30671 #undef TARGET_FIXED_CONDITION_CODE_REGS
30672 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30673 #undef TARGET_CC_MODES_COMPATIBLE
30674 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30676 #undef TARGET_MACHINE_DEPENDENT_REORG
30677 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30679 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30680 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30682 #undef TARGET_BUILD_BUILTIN_VA_LIST
30683 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30685 #undef TARGET_FN_ABI_VA_LIST
30686 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30688 #undef TARGET_CANONICAL_VA_LIST_TYPE
30689 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30691 #undef TARGET_EXPAND_BUILTIN_VA_START
30692 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30694 #undef TARGET_MD_ASM_CLOBBERS
30695 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30697 #undef TARGET_PROMOTE_PROTOTYPES
30698 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30699 #undef TARGET_STRUCT_VALUE_RTX
30700 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30701 #undef TARGET_SETUP_INCOMING_VARARGS
30702 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30703 #undef TARGET_MUST_PASS_IN_STACK
30704 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30705 #undef TARGET_PASS_BY_REFERENCE
30706 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30707 #undef TARGET_INTERNAL_ARG_POINTER
30708 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30709 #undef TARGET_UPDATE_STACK_BOUNDARY
30710 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30711 #undef TARGET_GET_DRAP_RTX
30712 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30713 #undef TARGET_STRICT_ARGUMENT_NAMING
30714 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30715 #undef TARGET_STATIC_CHAIN
30716 #define TARGET_STATIC_CHAIN ix86_static_chain
30717 #undef TARGET_TRAMPOLINE_INIT
30718 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
30720 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30721 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30723 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30724 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30726 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30727 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30729 #undef TARGET_C_MODE_FOR_SUFFIX
30730 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30733 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30734 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30737 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30738 #undef TARGET_INSERT_ATTRIBUTES
30739 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30742 #undef TARGET_MANGLE_TYPE
30743 #define TARGET_MANGLE_TYPE ix86_mangle_type
30745 #undef TARGET_STACK_PROTECT_FAIL
30746 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30748 #undef TARGET_FUNCTION_VALUE
30749 #define TARGET_FUNCTION_VALUE ix86_function_value
30751 #undef TARGET_SECONDARY_RELOAD
30752 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30754 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30755 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
30757 #undef TARGET_SET_CURRENT_FUNCTION
30758 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30760 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30761 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30763 #undef TARGET_OPTION_SAVE
30764 #define TARGET_OPTION_SAVE ix86_function_specific_save
30766 #undef TARGET_OPTION_RESTORE
30767 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30769 #undef TARGET_OPTION_PRINT
30770 #define TARGET_OPTION_PRINT ix86_function_specific_print
30772 #undef TARGET_CAN_INLINE_P
30773 #define TARGET_CAN_INLINE_P ix86_can_inline_p
30775 #undef TARGET_EXPAND_TO_RTL_HOOK
30776 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30778 #undef TARGET_LEGITIMATE_ADDRESS_P
30779 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30781 #undef TARGET_IRA_COVER_CLASSES
30782 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
30784 #undef TARGET_FRAME_POINTER_REQUIRED
30785 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
30787 #undef TARGET_CAN_ELIMINATE
30788 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
30790 struct gcc_target targetm = TARGET_INITIALIZER;
30792 #include "gt-i386.h"
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