1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 static int const x86_64_int_parameter_registers[6] =
1538 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1539 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1542 static int const x86_64_ms_abi_int_parameter_registers[4] =
1544 2 /*RCX*/, 1 /*RDX*/,
1545 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1548 static int const x86_64_int_return_registers[4] =
1550 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1553 /* The "default" register map used in 64bit mode. */
1554 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1556 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1557 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1558 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1559 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1560 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1561 8,9,10,11,12,13,14,15, /* extended integer registers */
1562 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1565 /* Define the register numbers to be used in Dwarf debugging information.
1566 The SVR4 reference port C compiler uses the following register numbers
1567 in its Dwarf output code:
1568 0 for %eax (gcc regno = 0)
1569 1 for %ecx (gcc regno = 2)
1570 2 for %edx (gcc regno = 1)
1571 3 for %ebx (gcc regno = 3)
1572 4 for %esp (gcc regno = 7)
1573 5 for %ebp (gcc regno = 6)
1574 6 for %esi (gcc regno = 4)
1575 7 for %edi (gcc regno = 5)
1576 The following three DWARF register numbers are never generated by
1577 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1578 believes these numbers have these meanings.
1579 8 for %eip (no gcc equivalent)
1580 9 for %eflags (gcc regno = 17)
1581 10 for %trapno (no gcc equivalent)
1582 It is not at all clear how we should number the FP stack registers
1583 for the x86 architecture. If the version of SDB on x86/svr4 were
1584 a bit less brain dead with respect to floating-point then we would
1585 have a precedent to follow with respect to DWARF register numbers
1586 for x86 FP registers, but the SDB on x86/svr4 is so completely
1587 broken with respect to FP registers that it is hardly worth thinking
1588 of it as something to strive for compatibility with.
1589 The version of x86/svr4 SDB I have at the moment does (partially)
1590 seem to believe that DWARF register number 11 is associated with
1591 the x86 register %st(0), but that's about all. Higher DWARF
1592 register numbers don't seem to be associated with anything in
1593 particular, and even for DWARF regno 11, SDB only seems to under-
1594 stand that it should say that a variable lives in %st(0) (when
1595 asked via an `=' command) if we said it was in DWARF regno 11,
1596 but SDB still prints garbage when asked for the value of the
1597 variable in question (via a `/' command).
1598 (Also note that the labels SDB prints for various FP stack regs
1599 when doing an `x' command are all wrong.)
1600 Note that these problems generally don't affect the native SVR4
1601 C compiler because it doesn't allow the use of -O with -g and
1602 because when it is *not* optimizing, it allocates a memory
1603 location for each floating-point variable, and the memory
1604 location is what gets described in the DWARF AT_location
1605 attribute for the variable in question.
1606 Regardless of the severe mental illness of the x86/svr4 SDB, we
1607 do something sensible here and we use the following DWARF
1608 register numbers. Note that these are all stack-top-relative
1610 11 for %st(0) (gcc regno = 8)
1611 12 for %st(1) (gcc regno = 9)
1612 13 for %st(2) (gcc regno = 10)
1613 14 for %st(3) (gcc regno = 11)
1614 15 for %st(4) (gcc regno = 12)
1615 16 for %st(5) (gcc regno = 13)
1616 17 for %st(6) (gcc regno = 14)
1617 18 for %st(7) (gcc regno = 15)
1619 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1621 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1622 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1623 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1624 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1625 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1626 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1627 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1630 /* Test and compare insns in i386.md store the information needed to
1631 generate branch and scc insns here. */
1633 rtx ix86_compare_op0 = NULL_RTX;
1634 rtx ix86_compare_op1 = NULL_RTX;
1635 rtx ix86_compare_emitted = NULL_RTX;
1637 /* Define the structure for the machine field in struct function. */
1639 struct stack_local_entry GTY(())
1641 unsigned short mode;
1644 struct stack_local_entry *next;
1647 /* Structure describing stack frame layout.
1648 Stack grows downward:
1654 saved frame pointer if frame_pointer_needed
1655 <- HARD_FRAME_POINTER
1664 [va_arg registers] (
1665 > to_allocate <- FRAME_POINTER
1677 HOST_WIDE_INT frame;
1679 int outgoing_arguments_size;
1682 HOST_WIDE_INT to_allocate;
1683 /* The offsets relative to ARG_POINTER. */
1684 HOST_WIDE_INT frame_pointer_offset;
1685 HOST_WIDE_INT hard_frame_pointer_offset;
1686 HOST_WIDE_INT stack_pointer_offset;
1688 /* When save_regs_using_mov is set, emit prologue using
1689 move instead of push instructions. */
1690 bool save_regs_using_mov;
1693 /* Code model option. */
1694 enum cmodel ix86_cmodel;
1696 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1698 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1700 /* Which unit we are generating floating point math for. */
1701 enum fpmath_unit ix86_fpmath;
1703 /* Which cpu are we scheduling for. */
1704 enum attr_cpu ix86_schedule;
1706 /* Which cpu are we optimizing for. */
1707 enum processor_type ix86_tune;
1709 /* Which instruction set architecture to use. */
1710 enum processor_type ix86_arch;
1712 /* true if sse prefetch instruction is not NOOP. */
1713 int x86_prefetch_sse;
1715 /* ix86_regparm_string as a number */
1716 static int ix86_regparm;
1718 /* -mstackrealign option */
1719 extern int ix86_force_align_arg_pointer;
1720 static const char ix86_force_align_arg_pointer_string[]
1721 = "force_align_arg_pointer";
1723 static rtx (*ix86_gen_leave) (void);
1724 static rtx (*ix86_gen_pop1) (rtx);
1725 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1726 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1728 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1729 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1730 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1732 /* Preferred alignment for stack boundary in bits. */
1733 unsigned int ix86_preferred_stack_boundary;
1735 /* Alignment for incoming stack boundary in bits specified at
1737 static unsigned int ix86_user_incoming_stack_boundary;
1739 /* Default alignment for incoming stack boundary in bits. */
1740 static unsigned int ix86_default_incoming_stack_boundary;
1742 /* Alignment for incoming stack boundary in bits. */
1743 unsigned int ix86_incoming_stack_boundary;
1745 /* Values 1-5: see jump.c */
1746 int ix86_branch_cost;
1748 /* Calling abi specific va_list type nodes. */
1749 static GTY(()) tree sysv_va_list_type_node;
1750 static GTY(()) tree ms_va_list_type_node;
1752 /* Variables which are this size or smaller are put in the data/bss
1753 or ldata/lbss sections. */
1755 int ix86_section_threshold = 65536;
1757 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1758 char internal_label_prefix[16];
1759 int internal_label_prefix_len;
1761 /* Fence to use after loop using movnt. */
1764 /* Register class used for passing given 64bit part of the argument.
1765 These represent classes as documented by the PS ABI, with the exception
1766 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1767 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1769 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1770 whenever possible (upper half does contain padding). */
1771 enum x86_64_reg_class
1774 X86_64_INTEGER_CLASS,
1775 X86_64_INTEGERSI_CLASS,
1783 X86_64_COMPLEX_X87_CLASS,
1786 static const char * const x86_64_reg_class_name[] =
1788 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1789 "sseup", "x87", "x87up", "cplx87", "no"
1792 #define MAX_CLASSES 4
1794 /* Table of constants used by fldpi, fldln2, etc.... */
1795 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1796 static bool ext_80387_constants_init = 0;
1799 static struct machine_function * ix86_init_machine_status (void);
1800 static rtx ix86_function_value (const_tree, const_tree, bool);
1801 static int ix86_function_regparm (const_tree, const_tree);
1802 static void ix86_compute_frame_layout (struct ix86_frame *);
1803 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1805 static void ix86_add_new_builtins (int);
1807 enum ix86_function_specific_strings
1809 IX86_FUNCTION_SPECIFIC_ARCH,
1810 IX86_FUNCTION_SPECIFIC_TUNE,
1811 IX86_FUNCTION_SPECIFIC_FPMATH,
1812 IX86_FUNCTION_SPECIFIC_MAX
1815 static char *ix86_target_string (int, int, const char *, const char *,
1816 const char *, bool);
1817 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1818 static void ix86_function_specific_save (struct cl_target_option *);
1819 static void ix86_function_specific_restore (struct cl_target_option *);
1820 static void ix86_function_specific_print (FILE *, int,
1821 struct cl_target_option *);
1822 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1823 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1824 static bool ix86_can_inline_p (tree, tree);
1825 static void ix86_set_current_function (tree);
1828 /* The svr4 ABI for the i386 says that records and unions are returned
1830 #ifndef DEFAULT_PCC_STRUCT_RETURN
1831 #define DEFAULT_PCC_STRUCT_RETURN 1
1834 /* Whether -mtune= or -march= were specified */
1835 static int ix86_tune_defaulted;
1836 static int ix86_arch_specified;
1838 /* Bit flags that specify the ISA we are compiling for. */
1839 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1841 /* A mask of ix86_isa_flags that includes bit X if X
1842 was set or cleared on the command line. */
1843 static int ix86_isa_flags_explicit;
1845 /* Define a set of ISAs which are available when a given ISA is
1846 enabled. MMX and SSE ISAs are handled separately. */
1848 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1849 #define OPTION_MASK_ISA_3DNOW_SET \
1850 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1852 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1853 #define OPTION_MASK_ISA_SSE2_SET \
1854 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1855 #define OPTION_MASK_ISA_SSE3_SET \
1856 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1857 #define OPTION_MASK_ISA_SSSE3_SET \
1858 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1859 #define OPTION_MASK_ISA_SSE4_1_SET \
1860 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1861 #define OPTION_MASK_ISA_SSE4_2_SET \
1862 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1863 #define OPTION_MASK_ISA_AVX_SET \
1864 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1865 #define OPTION_MASK_ISA_FMA_SET \
1866 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1868 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1870 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1872 #define OPTION_MASK_ISA_SSE4A_SET \
1873 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1874 #define OPTION_MASK_ISA_SSE5_SET \
1875 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1877 /* AES and PCLMUL need SSE2 because they use xmm registers */
1878 #define OPTION_MASK_ISA_AES_SET \
1879 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1880 #define OPTION_MASK_ISA_PCLMUL_SET \
1881 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1883 #define OPTION_MASK_ISA_ABM_SET \
1884 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1885 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1886 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1887 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1889 /* Define a set of ISAs which aren't available when a given ISA is
1890 disabled. MMX and SSE ISAs are handled separately. */
1892 #define OPTION_MASK_ISA_MMX_UNSET \
1893 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1894 #define OPTION_MASK_ISA_3DNOW_UNSET \
1895 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1896 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1898 #define OPTION_MASK_ISA_SSE_UNSET \
1899 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1900 #define OPTION_MASK_ISA_SSE2_UNSET \
1901 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1902 #define OPTION_MASK_ISA_SSE3_UNSET \
1903 (OPTION_MASK_ISA_SSE3 \
1904 | OPTION_MASK_ISA_SSSE3_UNSET \
1905 | OPTION_MASK_ISA_SSE4A_UNSET )
1906 #define OPTION_MASK_ISA_SSSE3_UNSET \
1907 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1908 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1909 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1910 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1911 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1912 #define OPTION_MASK_ISA_AVX_UNSET \
1913 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1914 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1916 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1918 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1920 #define OPTION_MASK_ISA_SSE4A_UNSET \
1921 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1922 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1923 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1924 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1925 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1926 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1927 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1928 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1930 /* Vectorization library interface and handlers. */
1931 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1932 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1933 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1935 /* Processor target table, indexed by processor number */
1938 const struct processor_costs *cost; /* Processor costs */
1939 const int align_loop; /* Default alignments. */
1940 const int align_loop_max_skip;
1941 const int align_jump;
1942 const int align_jump_max_skip;
1943 const int align_func;
1946 static const struct ptt processor_target_table[PROCESSOR_max] =
1948 {&i386_cost, 4, 3, 4, 3, 4},
1949 {&i486_cost, 16, 15, 16, 15, 16},
1950 {&pentium_cost, 16, 7, 16, 7, 16},
1951 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1952 {&geode_cost, 0, 0, 0, 0, 0},
1953 {&k6_cost, 32, 7, 32, 7, 32},
1954 {&athlon_cost, 16, 7, 16, 7, 16},
1955 {&pentium4_cost, 0, 0, 0, 0, 0},
1956 {&k8_cost, 16, 7, 16, 7, 16},
1957 {&nocona_cost, 0, 0, 0, 0, 0},
1958 {&core2_cost, 16, 10, 16, 10, 16},
1959 {&generic32_cost, 16, 7, 16, 7, 16},
1960 {&generic64_cost, 16, 10, 16, 10, 16},
1961 {&amdfam10_cost, 32, 24, 32, 7, 32}
1964 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1989 /* Implement TARGET_HANDLE_OPTION. */
1992 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1999 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2004 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2005 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2012 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2017 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2018 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2028 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2033 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2034 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2041 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2046 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2047 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2054 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2059 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2060 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2067 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2072 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2073 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2080 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2085 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2086 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2093 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2098 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2099 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2106 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2111 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2112 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2119 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2124 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2130 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2135 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2136 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2142 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2147 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2148 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2155 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2160 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2161 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2168 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2173 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2174 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2181 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2186 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2187 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2194 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2199 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2200 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2207 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2212 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2213 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2220 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2225 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2226 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2233 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2238 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2239 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2248 /* Return a string the documents the current -m options. The caller is
2249 responsible for freeing the string. */
2252 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2253 const char *fpmath, bool add_nl_p)
2255 struct ix86_target_opts
2257 const char *option; /* option string */
2258 int mask; /* isa mask options */
2261 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2262 preceding options while match those first. */
2263 static struct ix86_target_opts isa_opts[] =
2265 { "-m64", OPTION_MASK_ISA_64BIT },
2266 { "-msse5", OPTION_MASK_ISA_SSE5 },
2267 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2268 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2269 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2270 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2271 { "-msse3", OPTION_MASK_ISA_SSE3 },
2272 { "-msse2", OPTION_MASK_ISA_SSE2 },
2273 { "-msse", OPTION_MASK_ISA_SSE },
2274 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2275 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2276 { "-mmmx", OPTION_MASK_ISA_MMX },
2277 { "-mabm", OPTION_MASK_ISA_ABM },
2278 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2279 { "-maes", OPTION_MASK_ISA_AES },
2280 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2284 static struct ix86_target_opts flag_opts[] =
2286 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2287 { "-m80387", MASK_80387 },
2288 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2289 { "-malign-double", MASK_ALIGN_DOUBLE },
2290 { "-mcld", MASK_CLD },
2291 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2292 { "-mieee-fp", MASK_IEEE_FP },
2293 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2294 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2295 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2296 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2297 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2298 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2299 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2300 { "-mno-red-zone", MASK_NO_RED_ZONE },
2301 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2302 { "-mrecip", MASK_RECIP },
2303 { "-mrtd", MASK_RTD },
2304 { "-msseregparm", MASK_SSEREGPARM },
2305 { "-mstack-arg-probe", MASK_STACK_PROBE },
2306 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2309 const char *opts[ (sizeof (isa_opts) / sizeof (isa_opts[0])
2310 + sizeof (flag_opts) / sizeof (flag_opts[0])
2314 char target_other[40];
2323 memset (opts, '\0', sizeof (opts));
2325 /* Add -march= option. */
2328 opts[num][0] = "-march=";
2329 opts[num++][1] = arch;
2332 /* Add -mtune= option. */
2335 opts[num][0] = "-mtune=";
2336 opts[num++][1] = tune;
2339 /* Pick out the options in isa options. */
2340 for (i = 0; i < sizeof (isa_opts) / sizeof (isa_opts[0]); i++)
2342 if ((isa & isa_opts[i].mask) != 0)
2344 opts[num++][0] = isa_opts[i].option;
2345 isa &= ~ isa_opts[i].mask;
2349 if (isa && add_nl_p)
2351 opts[num++][0] = isa_other;
2352 sprintf (isa_other, "(other isa: 0x%x)", isa);
2355 /* Add flag options. */
2356 for (i = 0; i < sizeof (flag_opts) / sizeof (flag_opts[0]); i++)
2358 if ((flags & flag_opts[i].mask) != 0)
2360 opts[num++][0] = flag_opts[i].option;
2361 flags &= ~ flag_opts[i].mask;
2365 if (flags && add_nl_p)
2367 opts[num++][0] = target_other;
2368 sprintf (target_other, "(other flags: 0x%x)", isa);
2371 /* Add -fpmath= option. */
2374 opts[num][0] = "-mfpmath=";
2375 opts[num++][1] = fpmath;
2382 gcc_assert (num < sizeof (opts) / sizeof (opts[0]));
2384 /* Size the string. */
2386 sep_len = (add_nl_p) ? 3 : 1;
2387 for (i = 0; i < num; i++)
2390 for (j = 0; j < 2; j++)
2392 len += strlen (opts[i][j]);
2395 /* Build the string. */
2396 ret = ptr = (char *) xmalloc (len);
2399 for (i = 0; i < num; i++)
2403 for (j = 0; j < 2; j++)
2404 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2411 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2419 for (j = 0; j < 2; j++)
2422 memcpy (ptr, opts[i][j], len2[j]);
2424 line_len += len2[j];
2429 gcc_assert (ret + len >= ptr);
2434 /* Function that is callable from the debugger to print the current
2437 ix86_debug_options (void)
2439 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2440 ix86_arch_string, ix86_tune_string,
2441 ix86_fpmath_string, true);
2445 fprintf (stderr, "%s\n\n", opts);
2449 fprintf (stderr, "<no options>\n\n");
2454 /* Sometimes certain combinations of command options do not make
2455 sense on a particular target machine. You can define a macro
2456 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2457 defined, is executed once just after all the command options have
2460 Don't use this macro to turn on various extra optimizations for
2461 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2464 override_options (bool main_args_p)
2467 unsigned int ix86_arch_mask, ix86_tune_mask;
2472 /* Comes from final.c -- no real reason to change it. */
2473 #define MAX_CODE_ALIGN 16
2481 PTA_PREFETCH_SSE = 1 << 4,
2483 PTA_3DNOW_A = 1 << 6,
2487 PTA_POPCNT = 1 << 10,
2489 PTA_SSE4A = 1 << 12,
2490 PTA_NO_SAHF = 1 << 13,
2491 PTA_SSE4_1 = 1 << 14,
2492 PTA_SSE4_2 = 1 << 15,
2495 PTA_PCLMUL = 1 << 18,
2502 const char *const name; /* processor name or nickname. */
2503 const enum processor_type processor;
2504 const enum attr_cpu schedule;
2505 const unsigned /*enum pta_flags*/ flags;
2507 const processor_alias_table[] =
2509 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2510 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2511 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2512 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2513 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2514 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2515 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2516 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2517 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2518 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2519 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2520 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2521 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2523 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2525 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2526 PTA_MMX | PTA_SSE | PTA_SSE2},
2527 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2528 PTA_MMX |PTA_SSE | PTA_SSE2},
2529 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2530 PTA_MMX | PTA_SSE | PTA_SSE2},
2531 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2532 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2533 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2534 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2535 | PTA_CX16 | PTA_NO_SAHF},
2536 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2537 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2538 | PTA_SSSE3 | PTA_CX16},
2539 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2540 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2541 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2542 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2543 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2544 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2545 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2546 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2547 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2548 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2549 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2550 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2551 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2552 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2553 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2554 {"x86-64", PROCESSOR_K8, CPU_K8,
2555 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2556 {"k8", PROCESSOR_K8, CPU_K8,
2557 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2558 | PTA_SSE2 | PTA_NO_SAHF},
2559 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2560 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2561 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2562 {"opteron", PROCESSOR_K8, CPU_K8,
2563 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2564 | PTA_SSE2 | PTA_NO_SAHF},
2565 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2566 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2567 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2568 {"athlon64", PROCESSOR_K8, CPU_K8,
2569 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2570 | PTA_SSE2 | PTA_NO_SAHF},
2571 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2572 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2573 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2574 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2575 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2576 | PTA_SSE2 | PTA_NO_SAHF},
2577 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2578 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2579 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2580 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2581 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2582 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2583 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2584 0 /* flags are only used for -march switch. */ },
2585 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2586 PTA_64BIT /* flags are only used for -march switch. */ },
2589 int const pta_size = ARRAY_SIZE (processor_alias_table);
2591 /* Set up prefix/suffix so the error messages refer to either the command
2592 line argument, or the attribute(target). */
2601 prefix = "option(\"";
2606 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2607 SUBTARGET_OVERRIDE_OPTIONS;
2610 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2611 SUBSUBTARGET_OVERRIDE_OPTIONS;
2614 /* -fPIC is the default for x86_64. */
2615 if (TARGET_MACHO && TARGET_64BIT)
2618 /* Set the default values for switches whose default depends on TARGET_64BIT
2619 in case they weren't overwritten by command line options. */
2622 /* Mach-O doesn't support omitting the frame pointer for now. */
2623 if (flag_omit_frame_pointer == 2)
2624 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2625 if (flag_asynchronous_unwind_tables == 2)
2626 flag_asynchronous_unwind_tables = 1;
2627 if (flag_pcc_struct_return == 2)
2628 flag_pcc_struct_return = 0;
2632 if (flag_omit_frame_pointer == 2)
2633 flag_omit_frame_pointer = 0;
2634 if (flag_asynchronous_unwind_tables == 2)
2635 flag_asynchronous_unwind_tables = 0;
2636 if (flag_pcc_struct_return == 2)
2637 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2640 /* Need to check -mtune=generic first. */
2641 if (ix86_tune_string)
2643 if (!strcmp (ix86_tune_string, "generic")
2644 || !strcmp (ix86_tune_string, "i686")
2645 /* As special support for cross compilers we read -mtune=native
2646 as -mtune=generic. With native compilers we won't see the
2647 -mtune=native, as it was changed by the driver. */
2648 || !strcmp (ix86_tune_string, "native"))
2651 ix86_tune_string = "generic64";
2653 ix86_tune_string = "generic32";
2655 /* If this call is for setting the option attribute, allow the
2656 generic32/generic64 that was previously set. */
2657 else if (!main_args_p
2658 && (!strcmp (ix86_tune_string, "generic32")
2659 || !strcmp (ix86_tune_string, "generic64")))
2661 else if (!strncmp (ix86_tune_string, "generic", 7))
2662 error ("bad value (%s) for %stune=%s %s",
2663 ix86_tune_string, prefix, suffix, sw);
2667 if (ix86_arch_string)
2668 ix86_tune_string = ix86_arch_string;
2669 if (!ix86_tune_string)
2671 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2672 ix86_tune_defaulted = 1;
2675 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2676 need to use a sensible tune option. */
2677 if (!strcmp (ix86_tune_string, "generic")
2678 || !strcmp (ix86_tune_string, "x86-64")
2679 || !strcmp (ix86_tune_string, "i686"))
2682 ix86_tune_string = "generic64";
2684 ix86_tune_string = "generic32";
2687 if (ix86_stringop_string)
2689 if (!strcmp (ix86_stringop_string, "rep_byte"))
2690 stringop_alg = rep_prefix_1_byte;
2691 else if (!strcmp (ix86_stringop_string, "libcall"))
2692 stringop_alg = libcall;
2693 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2694 stringop_alg = rep_prefix_4_byte;
2695 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2696 stringop_alg = rep_prefix_8_byte;
2697 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2698 stringop_alg = loop_1_byte;
2699 else if (!strcmp (ix86_stringop_string, "loop"))
2700 stringop_alg = loop;
2701 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2702 stringop_alg = unrolled_loop;
2704 error ("bad value (%s) for %sstringop-strategy=%s %s",
2705 ix86_stringop_string, prefix, suffix, sw);
2707 if (!strcmp (ix86_tune_string, "x86-64"))
2708 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2709 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2710 prefix, suffix, prefix, suffix, prefix, suffix);
2712 if (!ix86_arch_string)
2713 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2715 ix86_arch_specified = 1;
2717 if (!strcmp (ix86_arch_string, "generic"))
2718 error ("generic CPU can be used only for %stune=%s %s",
2719 prefix, suffix, sw);
2720 if (!strncmp (ix86_arch_string, "generic", 7))
2721 error ("bad value (%s) for %sarch=%s %s",
2722 ix86_arch_string, prefix, suffix, sw);
2724 if (ix86_cmodel_string != 0)
2726 if (!strcmp (ix86_cmodel_string, "small"))
2727 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2728 else if (!strcmp (ix86_cmodel_string, "medium"))
2729 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2730 else if (!strcmp (ix86_cmodel_string, "large"))
2731 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2733 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2734 else if (!strcmp (ix86_cmodel_string, "32"))
2735 ix86_cmodel = CM_32;
2736 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2737 ix86_cmodel = CM_KERNEL;
2739 error ("bad value (%s) for %scmodel=%s %s",
2740 ix86_cmodel_string, prefix, suffix, sw);
2744 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2745 use of rip-relative addressing. This eliminates fixups that
2746 would otherwise be needed if this object is to be placed in a
2747 DLL, and is essentially just as efficient as direct addressing. */
2748 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2749 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2750 else if (TARGET_64BIT)
2751 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2753 ix86_cmodel = CM_32;
2755 if (ix86_asm_string != 0)
2758 && !strcmp (ix86_asm_string, "intel"))
2759 ix86_asm_dialect = ASM_INTEL;
2760 else if (!strcmp (ix86_asm_string, "att"))
2761 ix86_asm_dialect = ASM_ATT;
2763 error ("bad value (%s) for %sasm=%s %s",
2764 ix86_asm_string, prefix, suffix, sw);
2766 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2767 error ("code model %qs not supported in the %s bit mode",
2768 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2769 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2770 sorry ("%i-bit mode not compiled in",
2771 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2773 for (i = 0; i < pta_size; i++)
2774 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2776 ix86_schedule = processor_alias_table[i].schedule;
2777 ix86_arch = processor_alias_table[i].processor;
2778 /* Default cpu tuning to the architecture. */
2779 ix86_tune = ix86_arch;
2781 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2782 error ("CPU you selected does not support x86-64 "
2785 if (processor_alias_table[i].flags & PTA_MMX
2786 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2787 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2788 if (processor_alias_table[i].flags & PTA_3DNOW
2789 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2790 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2791 if (processor_alias_table[i].flags & PTA_3DNOW_A
2792 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2793 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2794 if (processor_alias_table[i].flags & PTA_SSE
2795 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2796 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2797 if (processor_alias_table[i].flags & PTA_SSE2
2798 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2799 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2800 if (processor_alias_table[i].flags & PTA_SSE3
2801 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2802 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2803 if (processor_alias_table[i].flags & PTA_SSSE3
2804 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2805 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2806 if (processor_alias_table[i].flags & PTA_SSE4_1
2807 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2808 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2809 if (processor_alias_table[i].flags & PTA_SSE4_2
2810 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2811 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2812 if (processor_alias_table[i].flags & PTA_AVX
2813 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2814 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2815 if (processor_alias_table[i].flags & PTA_FMA
2816 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2817 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2818 if (processor_alias_table[i].flags & PTA_SSE4A
2819 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2820 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2821 if (processor_alias_table[i].flags & PTA_SSE5
2822 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2823 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2824 if (processor_alias_table[i].flags & PTA_ABM
2825 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2826 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2827 if (processor_alias_table[i].flags & PTA_CX16
2828 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2829 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2830 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2831 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2832 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2833 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2834 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2835 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2836 if (processor_alias_table[i].flags & PTA_AES
2837 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2838 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2839 if (processor_alias_table[i].flags & PTA_PCLMUL
2840 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2841 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2842 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2843 x86_prefetch_sse = true;
2849 error ("bad value (%s) for %sarch=%s %s",
2850 ix86_arch_string, prefix, suffix, sw);
2852 ix86_arch_mask = 1u << ix86_arch;
2853 for (i = 0; i < X86_ARCH_LAST; ++i)
2854 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2856 for (i = 0; i < pta_size; i++)
2857 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2859 ix86_schedule = processor_alias_table[i].schedule;
2860 ix86_tune = processor_alias_table[i].processor;
2861 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2863 if (ix86_tune_defaulted)
2865 ix86_tune_string = "x86-64";
2866 for (i = 0; i < pta_size; i++)
2867 if (! strcmp (ix86_tune_string,
2868 processor_alias_table[i].name))
2870 ix86_schedule = processor_alias_table[i].schedule;
2871 ix86_tune = processor_alias_table[i].processor;
2874 error ("CPU you selected does not support x86-64 "
2877 /* Intel CPUs have always interpreted SSE prefetch instructions as
2878 NOPs; so, we can enable SSE prefetch instructions even when
2879 -mtune (rather than -march) points us to a processor that has them.
2880 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2881 higher processors. */
2883 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2884 x86_prefetch_sse = true;
2888 error ("bad value (%s) for %stune=%s %s",
2889 ix86_tune_string, prefix, suffix, sw);
2891 ix86_tune_mask = 1u << ix86_tune;
2892 for (i = 0; i < X86_TUNE_LAST; ++i)
2893 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2896 ix86_cost = &ix86_size_cost;
2898 ix86_cost = processor_target_table[ix86_tune].cost;
2900 /* Arrange to set up i386_stack_locals for all functions. */
2901 init_machine_status = ix86_init_machine_status;
2903 /* Validate -mregparm= value. */
2904 if (ix86_regparm_string)
2907 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2908 i = atoi (ix86_regparm_string);
2909 if (i < 0 || i > REGPARM_MAX)
2910 error ("%sregparm=%d%s is not between 0 and %d",
2911 prefix, i, suffix, REGPARM_MAX);
2916 ix86_regparm = REGPARM_MAX;
2918 /* If the user has provided any of the -malign-* options,
2919 warn and use that value only if -falign-* is not set.
2920 Remove this code in GCC 3.2 or later. */
2921 if (ix86_align_loops_string)
2923 warning (0, "%salign-loops%s is obsolete, use %salign-loops%s",
2924 prefix, suffix, prefix, suffix);
2925 if (align_loops == 0)
2927 i = atoi (ix86_align_loops_string);
2928 if (i < 0 || i > MAX_CODE_ALIGN)
2929 error ("%salign-loops=%d%s is not between 0 and %d",
2930 prefix, i, suffix, MAX_CODE_ALIGN);
2932 align_loops = 1 << i;
2936 if (ix86_align_jumps_string)
2938 warning (0, "%salign-jumps%s is obsolete, use %salign-jumps%s",
2939 prefix, suffix, prefix, suffix);
2940 if (align_jumps == 0)
2942 i = atoi (ix86_align_jumps_string);
2943 if (i < 0 || i > MAX_CODE_ALIGN)
2944 error ("%salign-loops=%d%s is not between 0 and %d",
2945 prefix, i, suffix, MAX_CODE_ALIGN);
2947 align_jumps = 1 << i;
2951 if (ix86_align_funcs_string)
2953 warning (0, "%salign-functions%s is obsolete, use %salign-functions%s",
2954 prefix, suffix, prefix, suffix);
2955 if (align_functions == 0)
2957 i = atoi (ix86_align_funcs_string);
2958 if (i < 0 || i > MAX_CODE_ALIGN)
2959 error ("%salign-loops=%d%s is not between 0 and %d",
2960 prefix, i, suffix, MAX_CODE_ALIGN);
2962 align_functions = 1 << i;
2966 /* Default align_* from the processor table. */
2967 if (align_loops == 0)
2969 align_loops = processor_target_table[ix86_tune].align_loop;
2970 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2972 if (align_jumps == 0)
2974 align_jumps = processor_target_table[ix86_tune].align_jump;
2975 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2977 if (align_functions == 0)
2979 align_functions = processor_target_table[ix86_tune].align_func;
2982 /* Validate -mbranch-cost= value, or provide default. */
2983 ix86_branch_cost = ix86_cost->branch_cost;
2984 if (ix86_branch_cost_string)
2986 i = atoi (ix86_branch_cost_string);
2988 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2990 ix86_branch_cost = i;
2992 if (ix86_section_threshold_string)
2994 i = atoi (ix86_section_threshold_string);
2996 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2998 ix86_section_threshold = i;
3001 if (ix86_tls_dialect_string)
3003 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3004 ix86_tls_dialect = TLS_DIALECT_GNU;
3005 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3006 ix86_tls_dialect = TLS_DIALECT_GNU2;
3007 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3008 ix86_tls_dialect = TLS_DIALECT_SUN;
3010 error ("bad value (%s) for %stls-dialect=%s %s",
3011 ix86_tls_dialect_string, prefix, suffix, sw);
3014 if (ix87_precision_string)
3016 i = atoi (ix87_precision_string);
3017 if (i != 32 && i != 64 && i != 80)
3018 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3023 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3025 /* Enable by default the SSE and MMX builtins. Do allow the user to
3026 explicitly disable any of these. In particular, disabling SSE and
3027 MMX for kernel code is extremely useful. */
3028 if (!ix86_arch_specified)
3030 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3031 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3034 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3038 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3040 if (!ix86_arch_specified)
3042 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3044 /* i386 ABI does not specify red zone. It still makes sense to use it
3045 when programmer takes care to stack from being destroyed. */
3046 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3047 target_flags |= MASK_NO_RED_ZONE;
3050 /* Keep nonleaf frame pointers. */
3051 if (flag_omit_frame_pointer)
3052 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3053 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3054 flag_omit_frame_pointer = 1;
3056 /* If we're doing fast math, we don't care about comparison order
3057 wrt NaNs. This lets us use a shorter comparison sequence. */
3058 if (flag_finite_math_only)
3059 target_flags &= ~MASK_IEEE_FP;
3061 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3062 since the insns won't need emulation. */
3063 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3064 target_flags &= ~MASK_NO_FANCY_MATH_387;
3066 /* Likewise, if the target doesn't have a 387, or we've specified
3067 software floating point, don't use 387 inline intrinsics. */
3069 target_flags |= MASK_NO_FANCY_MATH_387;
3071 /* Turn on MMX builtins for -msse. */
3074 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3075 x86_prefetch_sse = true;
3078 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3079 if (TARGET_SSE4_2 || TARGET_ABM)
3080 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3082 /* Validate -mpreferred-stack-boundary= value or default it to
3083 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3084 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3085 if (ix86_preferred_stack_boundary_string)
3087 i = atoi (ix86_preferred_stack_boundary_string);
3088 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3089 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3090 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3092 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3095 /* Set the default value for -mstackrealign. */
3096 if (ix86_force_align_arg_pointer == -1)
3097 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3099 /* Validate -mincoming-stack-boundary= value or default it to
3100 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3101 if (ix86_force_align_arg_pointer)
3102 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3104 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3105 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3106 if (ix86_incoming_stack_boundary_string)
3108 i = atoi (ix86_incoming_stack_boundary_string);
3109 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3110 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3111 i, TARGET_64BIT ? 4 : 2);
3114 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3115 ix86_incoming_stack_boundary
3116 = ix86_user_incoming_stack_boundary;
3120 /* Accept -msseregparm only if at least SSE support is enabled. */
3121 if (TARGET_SSEREGPARM
3123 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3125 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3126 if (ix86_fpmath_string != 0)
3128 if (! strcmp (ix86_fpmath_string, "387"))
3129 ix86_fpmath = FPMATH_387;
3130 else if (! strcmp (ix86_fpmath_string, "sse"))
3134 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3135 ix86_fpmath = FPMATH_387;
3138 ix86_fpmath = FPMATH_SSE;
3140 else if (! strcmp (ix86_fpmath_string, "387,sse")
3141 || ! strcmp (ix86_fpmath_string, "387+sse")
3142 || ! strcmp (ix86_fpmath_string, "sse,387")
3143 || ! strcmp (ix86_fpmath_string, "sse+387")
3144 || ! strcmp (ix86_fpmath_string, "both"))
3148 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3149 ix86_fpmath = FPMATH_387;
3151 else if (!TARGET_80387)
3153 warning (0, "387 instruction set disabled, using SSE arithmetics");
3154 ix86_fpmath = FPMATH_SSE;
3157 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3160 error ("bad value (%s) for %sfpmath=%s %s",
3161 ix86_fpmath_string, prefix, suffix, sw);
3164 /* If the i387 is disabled, then do not return values in it. */
3166 target_flags &= ~MASK_FLOAT_RETURNS;
3168 /* Use external vectorized library in vectorizing intrinsics. */
3169 if (ix86_veclibabi_string)
3171 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3172 ix86_veclib_handler = ix86_veclibabi_svml;
3173 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3174 ix86_veclib_handler = ix86_veclibabi_acml;
3176 error ("unknown vectorization library ABI type (%s) for "
3177 "%sveclibabi=%s %s", ix86_veclibabi_string,
3178 prefix, suffix, sw);
3181 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3182 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3184 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3186 /* ??? Unwind info is not correct around the CFG unless either a frame
3187 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3188 unwind info generation to be aware of the CFG and propagating states
3190 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3191 || flag_exceptions || flag_non_call_exceptions)
3192 && flag_omit_frame_pointer
3193 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3195 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3196 warning (0, "unwind tables currently require either a frame pointer "
3197 "or %saccumulate-outgoing-args%s for correctness",
3199 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3202 /* If stack probes are required, the space used for large function
3203 arguments on the stack must also be probed, so enable
3204 -maccumulate-outgoing-args so this happens in the prologue. */
3205 if (TARGET_STACK_PROBE
3206 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3208 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3209 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3210 "for correctness", prefix, suffix);
3211 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3214 /* For sane SSE instruction set generation we need fcomi instruction.
3215 It is safe to enable all CMOVE instructions. */
3219 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3222 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3223 p = strchr (internal_label_prefix, 'X');
3224 internal_label_prefix_len = p - internal_label_prefix;
3228 /* When scheduling description is not available, disable scheduler pass
3229 so it won't slow down the compilation and make x87 code slower. */
3230 if (!TARGET_SCHEDULE)
3231 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3233 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3234 set_param_value ("simultaneous-prefetches",
3235 ix86_cost->simultaneous_prefetches);
3236 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3237 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3238 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3239 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3240 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3241 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3243 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3244 can be optimized to ap = __builtin_next_arg (0). */
3246 targetm.expand_builtin_va_start = NULL;
3250 ix86_gen_leave = gen_leave_rex64;
3251 ix86_gen_pop1 = gen_popdi1;
3252 ix86_gen_add3 = gen_adddi3;
3253 ix86_gen_sub3 = gen_subdi3;
3254 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3255 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3256 ix86_gen_monitor = gen_sse3_monitor64;
3257 ix86_gen_andsp = gen_anddi3;
3261 ix86_gen_leave = gen_leave;
3262 ix86_gen_pop1 = gen_popsi1;
3263 ix86_gen_add3 = gen_addsi3;
3264 ix86_gen_sub3 = gen_subsi3;
3265 ix86_gen_sub3_carry = gen_subsi3_carry;
3266 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3267 ix86_gen_monitor = gen_sse3_monitor;
3268 ix86_gen_andsp = gen_andsi3;
3272 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3274 target_flags |= MASK_CLD & ~target_flags_explicit;
3277 /* Save the initial options in case the user does function specific options */
3279 target_option_default_node = target_option_current_node
3280 = build_target_option_node ();
3283 /* Save the current options */
3286 ix86_function_specific_save (struct cl_target_option *ptr)
3288 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3289 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3290 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3291 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3292 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3294 ptr->arch = ix86_arch;
3295 ptr->schedule = ix86_schedule;
3296 ptr->tune = ix86_tune;
3297 ptr->fpmath = ix86_fpmath;
3298 ptr->branch_cost = ix86_branch_cost;
3299 ptr->tune_defaulted = ix86_tune_defaulted;
3300 ptr->arch_specified = ix86_arch_specified;
3301 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3302 ptr->target_flags_explicit = target_flags_explicit;
3305 /* Restore the current options */
3308 ix86_function_specific_restore (struct cl_target_option *ptr)
3310 enum processor_type old_tune = ix86_tune;
3311 enum processor_type old_arch = ix86_arch;
3312 unsigned int ix86_arch_mask, ix86_tune_mask;
3315 ix86_arch = ptr->arch;
3316 ix86_schedule = ptr->schedule;
3317 ix86_tune = ptr->tune;
3318 ix86_fpmath = ptr->fpmath;
3319 ix86_branch_cost = ptr->branch_cost;
3320 ix86_tune_defaulted = ptr->tune_defaulted;
3321 ix86_arch_specified = ptr->arch_specified;
3322 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3323 target_flags_explicit = ptr->target_flags_explicit;
3325 /* Recreate the arch feature tests if the arch changed */
3326 if (old_arch != ix86_arch)
3328 ix86_arch_mask = 1u << ix86_arch;
3329 for (i = 0; i < X86_ARCH_LAST; ++i)
3330 ix86_arch_features[i]
3331 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3334 /* Recreate the tune optimization tests */
3335 if (old_tune != ix86_tune)
3337 ix86_tune_mask = 1u << ix86_tune;
3338 for (i = 0; i < X86_TUNE_LAST; ++i)
3339 ix86_tune_features[i]
3340 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3344 /* Print the current options */
3347 ix86_function_specific_print (FILE *file, int indent,
3348 struct cl_target_option *ptr)
3351 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3352 NULL, NULL, NULL, false);
3354 fprintf (file, "%*sarch = %d (%s)\n",
3357 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3358 ? cpu_names[ptr->arch]
3361 fprintf (file, "%*stune = %d (%s)\n",
3364 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3365 ? cpu_names[ptr->tune]
3368 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3369 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3370 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3371 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3375 fprintf (file, "%*s%s\n", indent, "", target_string);
3376 free (target_string);
3381 /* Inner function to process the attribute((target(...))), take an argument and
3382 set the current options from the argument. If we have a list, recursively go
3386 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3391 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3392 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3393 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3394 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3409 enum ix86_opt_type type;
3414 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3415 IX86_ATTR_ISA ("abm", OPT_mabm),
3416 IX86_ATTR_ISA ("aes", OPT_maes),
3417 IX86_ATTR_ISA ("avx", OPT_mavx),
3418 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3419 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3420 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3421 IX86_ATTR_ISA ("sse", OPT_msse),
3422 IX86_ATTR_ISA ("sse2", OPT_msse2),
3423 IX86_ATTR_ISA ("sse3", OPT_msse3),
3424 IX86_ATTR_ISA ("sse4", OPT_msse4),
3425 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3426 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3427 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3428 IX86_ATTR_ISA ("sse5", OPT_msse5),
3429 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3431 /* string options */
3432 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3433 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3434 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3437 IX86_ATTR_YES ("cld",
3441 IX86_ATTR_NO ("fancy-math-387",
3442 OPT_mfancy_math_387,
3443 MASK_NO_FANCY_MATH_387),
3445 IX86_ATTR_NO ("fused-madd",
3447 MASK_NO_FUSED_MADD),
3449 IX86_ATTR_YES ("ieee-fp",
3453 IX86_ATTR_YES ("inline-all-stringops",
3454 OPT_minline_all_stringops,
3455 MASK_INLINE_ALL_STRINGOPS),
3457 IX86_ATTR_YES ("inline-stringops-dynamically",
3458 OPT_minline_stringops_dynamically,
3459 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3461 IX86_ATTR_NO ("align-stringops",
3462 OPT_mno_align_stringops,
3463 MASK_NO_ALIGN_STRINGOPS),
3465 IX86_ATTR_YES ("recip",
3471 /* If this is a list, recurse to get the options. */
3472 if (TREE_CODE (args) == TREE_LIST)
3476 for (; args; args = TREE_CHAIN (args))
3477 if (TREE_VALUE (args)
3478 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3484 else if (TREE_CODE (args) != STRING_CST)
3487 /* Handle multiple arguments separated by commas. */
3488 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3490 while (next_optstr && *next_optstr != '\0')
3492 char *p = next_optstr;
3494 char *comma = strchr (next_optstr, ',');
3495 const char *opt_string;
3496 size_t len, opt_len;
3501 enum ix86_opt_type type = ix86_opt_unknown;
3507 len = comma - next_optstr;
3508 next_optstr = comma + 1;
3516 /* Recognize no-xxx. */
3517 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3526 /* Find the option. */
3529 for (i = 0; i < sizeof (attrs) / sizeof (attrs[0]); i++)
3531 type = attrs[i].type;
3532 opt_len = attrs[i].len;
3533 if (ch == attrs[i].string[0]
3534 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3535 && memcmp (p, attrs[i].string, opt_len) == 0)
3538 mask = attrs[i].mask;
3539 opt_string = attrs[i].string;
3544 /* Process the option. */
3547 error ("attribute(target(\"%s\")) is unknown", orig_p);
3551 else if (type == ix86_opt_isa)
3552 ix86_handle_option (opt, p, opt_set_p);
3554 else if (type == ix86_opt_yes || type == ix86_opt_no)
3556 if (type == ix86_opt_no)
3557 opt_set_p = !opt_set_p;
3560 target_flags |= mask;
3562 target_flags &= ~mask;
3565 else if (type == ix86_opt_str)
3569 error ("option(\"%s\") was already specified", opt_string);
3573 p_strings[opt] = xstrdup (p + opt_len);
3583 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3586 ix86_valid_target_attribute_tree (tree args)
3588 const char *orig_arch_string = ix86_arch_string;
3589 const char *orig_tune_string = ix86_tune_string;
3590 const char *orig_fpmath_string = ix86_fpmath_string;
3591 int orig_tune_defaulted = ix86_tune_defaulted;
3592 int orig_arch_specified = ix86_arch_specified;
3593 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3596 struct cl_target_option *def
3597 = TREE_TARGET_OPTION (target_option_default_node);
3599 /* Process each of the options on the chain. */
3600 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3603 /* If the changed options are different from the default, rerun override_options,
3604 and then save the options away. The string options are are attribute options,
3605 and will be undone when we copy the save structure. */
3606 if (ix86_isa_flags != def->ix86_isa_flags
3607 || target_flags != def->target_flags
3608 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3609 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3610 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3612 /* If we are using the default tune= or arch=, undo the string assigned,
3613 and use the default. */
3614 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3615 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3616 else if (!orig_arch_specified)
3617 ix86_arch_string = NULL;
3619 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3620 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3621 else if (orig_tune_defaulted)
3622 ix86_tune_string = NULL;
3624 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3625 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3626 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3627 else if (!TARGET_64BIT && TARGET_SSE)
3628 ix86_fpmath_string = "sse,387";
3630 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3631 override_options (false);
3633 /* Add any builtin functions with the new isa if any. */
3634 ix86_add_new_builtins (ix86_isa_flags);
3636 /* Save the current options unless we are validating options for
3638 t = build_target_option_node ();
3640 ix86_arch_string = orig_arch_string;
3641 ix86_tune_string = orig_tune_string;
3642 ix86_fpmath_string = orig_fpmath_string;
3644 /* Free up memory allocated to hold the strings */
3645 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3646 if (option_strings[i])
3647 free (option_strings[i]);
3653 /* Hook to validate attribute((target("string"))). */
3656 ix86_valid_target_attribute_p (tree fndecl,
3657 tree ARG_UNUSED (name),
3659 int ARG_UNUSED (flags))
3661 struct cl_target_option cur_target;
3663 tree old_optimize = build_optimization_node ();
3664 tree new_target, new_optimize;
3665 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3667 /* If the function changed the optimization levels as well as setting target
3668 options, start with the optimizations specified. */
3669 if (func_optimize && func_optimize != old_optimize)
3670 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3672 /* The target attributes may also change some optimization flags, so update
3673 the optimization options if necessary. */
3674 cl_target_option_save (&cur_target);
3675 new_target = ix86_valid_target_attribute_tree (args);
3676 new_optimize = build_optimization_node ();
3683 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3685 if (old_optimize != new_optimize)
3686 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3689 cl_target_option_restore (&cur_target);
3691 if (old_optimize != new_optimize)
3692 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3698 /* Hook to determine if one function can safely inline another. */
3701 ix86_can_inline_p (tree caller, tree callee)
3704 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3705 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3707 /* If callee has no option attributes, then it is ok to inline. */
3711 /* If caller has no option attributes, but callee does then it is not ok to
3713 else if (!caller_tree)
3718 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3719 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3721 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3722 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3724 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3725 != callee_opts->ix86_isa_flags)
3728 /* See if we have the same non-isa options. */
3729 else if (caller_opts->target_flags != callee_opts->target_flags)
3732 /* See if arch, tune, etc. are the same. */
3733 else if (caller_opts->arch != callee_opts->arch)
3736 else if (caller_opts->tune != callee_opts->tune)
3739 else if (caller_opts->fpmath != callee_opts->fpmath)
3742 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3753 /* Remember the last target of ix86_set_current_function. */
3754 static GTY(()) tree ix86_previous_fndecl;
3756 /* Establish appropriate back-end context for processing the function
3757 FNDECL. The argument might be NULL to indicate processing at top
3758 level, outside of any function scope. */
3760 ix86_set_current_function (tree fndecl)
3762 /* Only change the context if the function changes. This hook is called
3763 several times in the course of compiling a function, and we don't want to
3764 slow things down too much or call target_reinit when it isn't safe. */
3765 if (fndecl && fndecl != ix86_previous_fndecl)
3767 tree old_tree = (ix86_previous_fndecl
3768 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3771 tree new_tree = (fndecl
3772 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3775 ix86_previous_fndecl = fndecl;
3776 if (old_tree == new_tree)
3781 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3787 struct cl_target_option *def
3788 = TREE_TARGET_OPTION (target_option_current_node);
3790 cl_target_option_restore (def);
3797 /* Return true if this goes in large data/bss. */
3800 ix86_in_large_data_p (tree exp)
3802 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3805 /* Functions are never large data. */
3806 if (TREE_CODE (exp) == FUNCTION_DECL)
3809 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3811 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3812 if (strcmp (section, ".ldata") == 0
3813 || strcmp (section, ".lbss") == 0)
3819 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3821 /* If this is an incomplete type with size 0, then we can't put it
3822 in data because it might be too big when completed. */
3823 if (!size || size > ix86_section_threshold)
3830 /* Switch to the appropriate section for output of DECL.
3831 DECL is either a `VAR_DECL' node or a constant of some sort.
3832 RELOC indicates whether forming the initial value of DECL requires
3833 link-time relocations. */
3835 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3839 x86_64_elf_select_section (tree decl, int reloc,
3840 unsigned HOST_WIDE_INT align)
3842 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3843 && ix86_in_large_data_p (decl))
3845 const char *sname = NULL;
3846 unsigned int flags = SECTION_WRITE;
3847 switch (categorize_decl_for_section (decl, reloc))
3852 case SECCAT_DATA_REL:
3853 sname = ".ldata.rel";
3855 case SECCAT_DATA_REL_LOCAL:
3856 sname = ".ldata.rel.local";
3858 case SECCAT_DATA_REL_RO:
3859 sname = ".ldata.rel.ro";
3861 case SECCAT_DATA_REL_RO_LOCAL:
3862 sname = ".ldata.rel.ro.local";
3866 flags |= SECTION_BSS;
3869 case SECCAT_RODATA_MERGE_STR:
3870 case SECCAT_RODATA_MERGE_STR_INIT:
3871 case SECCAT_RODATA_MERGE_CONST:
3875 case SECCAT_SRODATA:
3882 /* We don't split these for medium model. Place them into
3883 default sections and hope for best. */
3885 case SECCAT_EMUTLS_VAR:
3886 case SECCAT_EMUTLS_TMPL:
3891 /* We might get called with string constants, but get_named_section
3892 doesn't like them as they are not DECLs. Also, we need to set
3893 flags in that case. */
3895 return get_section (sname, flags, NULL);
3896 return get_named_section (decl, sname, reloc);
3899 return default_elf_select_section (decl, reloc, align);
3902 /* Build up a unique section name, expressed as a
3903 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3904 RELOC indicates whether the initial value of EXP requires
3905 link-time relocations. */
3907 static void ATTRIBUTE_UNUSED
3908 x86_64_elf_unique_section (tree decl, int reloc)
3910 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3911 && ix86_in_large_data_p (decl))
3913 const char *prefix = NULL;
3914 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3915 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3917 switch (categorize_decl_for_section (decl, reloc))
3920 case SECCAT_DATA_REL:
3921 case SECCAT_DATA_REL_LOCAL:
3922 case SECCAT_DATA_REL_RO:
3923 case SECCAT_DATA_REL_RO_LOCAL:
3924 prefix = one_only ? ".ld" : ".ldata";
3927 prefix = one_only ? ".lb" : ".lbss";
3930 case SECCAT_RODATA_MERGE_STR:
3931 case SECCAT_RODATA_MERGE_STR_INIT:
3932 case SECCAT_RODATA_MERGE_CONST:
3933 prefix = one_only ? ".lr" : ".lrodata";
3935 case SECCAT_SRODATA:
3942 /* We don't split these for medium model. Place them into
3943 default sections and hope for best. */
3945 case SECCAT_EMUTLS_VAR:
3946 prefix = targetm.emutls.var_section;
3948 case SECCAT_EMUTLS_TMPL:
3949 prefix = targetm.emutls.tmpl_section;
3954 const char *name, *linkonce;
3957 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3958 name = targetm.strip_name_encoding (name);
3960 /* If we're using one_only, then there needs to be a .gnu.linkonce
3961 prefix to the section name. */
3962 linkonce = one_only ? ".gnu.linkonce" : "";
3964 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3966 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3970 default_unique_section (decl, reloc);
3973 #ifdef COMMON_ASM_OP
3974 /* This says how to output assembler code to declare an
3975 uninitialized external linkage data object.
3977 For medium model x86-64 we need to use .largecomm opcode for
3980 x86_elf_aligned_common (FILE *file,
3981 const char *name, unsigned HOST_WIDE_INT size,
3984 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3985 && size > (unsigned int)ix86_section_threshold)
3986 fprintf (file, ".largecomm\t");
3988 fprintf (file, "%s", COMMON_ASM_OP);
3989 assemble_name (file, name);
3990 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
3991 size, align / BITS_PER_UNIT);
3995 /* Utility function for targets to use in implementing
3996 ASM_OUTPUT_ALIGNED_BSS. */
3999 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4000 const char *name, unsigned HOST_WIDE_INT size,
4003 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4004 && size > (unsigned int)ix86_section_threshold)
4005 switch_to_section (get_named_section (decl, ".lbss", 0));
4007 switch_to_section (bss_section);
4008 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4009 #ifdef ASM_DECLARE_OBJECT_NAME
4010 last_assemble_variable_decl = decl;
4011 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4013 /* Standard thing is just output label for the object. */
4014 ASM_OUTPUT_LABEL (file, name);
4015 #endif /* ASM_DECLARE_OBJECT_NAME */
4016 ASM_OUTPUT_SKIP (file, size ? size : 1);
4020 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4022 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4023 make the problem with not enough registers even worse. */
4024 #ifdef INSN_SCHEDULING
4026 flag_schedule_insns = 0;
4030 /* The Darwin libraries never set errno, so we might as well
4031 avoid calling them when that's the only reason we would. */
4032 flag_errno_math = 0;
4034 /* The default values of these switches depend on the TARGET_64BIT
4035 that is not known at this moment. Mark these values with 2 and
4036 let user the to override these. In case there is no command line option
4037 specifying them, we will set the defaults in override_options. */
4039 flag_omit_frame_pointer = 2;
4040 flag_pcc_struct_return = 2;
4041 flag_asynchronous_unwind_tables = 2;
4042 flag_vect_cost_model = 1;
4043 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4044 SUBTARGET_OPTIMIZATION_OPTIONS;
4048 /* Decide whether we can make a sibling call to a function. DECL is the
4049 declaration of the function being targeted by the call and EXP is the
4050 CALL_EXPR representing the call. */
4053 ix86_function_ok_for_sibcall (tree decl, tree exp)
4058 /* If we are generating position-independent code, we cannot sibcall
4059 optimize any indirect call, or a direct call to a global function,
4060 as the PLT requires %ebx be live. */
4061 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4068 func = TREE_TYPE (CALL_EXPR_FN (exp));
4069 if (POINTER_TYPE_P (func))
4070 func = TREE_TYPE (func);
4073 /* Check that the return value locations are the same. Like
4074 if we are returning floats on the 80387 register stack, we cannot
4075 make a sibcall from a function that doesn't return a float to a
4076 function that does or, conversely, from a function that does return
4077 a float to a function that doesn't; the necessary stack adjustment
4078 would not be executed. This is also the place we notice
4079 differences in the return value ABI. Note that it is ok for one
4080 of the functions to have void return type as long as the return
4081 value of the other is passed in a register. */
4082 a = ix86_function_value (TREE_TYPE (exp), func, false);
4083 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4085 if (STACK_REG_P (a) || STACK_REG_P (b))
4087 if (!rtx_equal_p (a, b))
4090 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4092 else if (!rtx_equal_p (a, b))
4095 /* If this call is indirect, we'll need to be able to use a call-clobbered
4096 register for the address of the target function. Make sure that all
4097 such registers are not used for passing parameters. */
4098 if (!decl && !TARGET_64BIT)
4102 /* We're looking at the CALL_EXPR, we need the type of the function. */
4103 type = CALL_EXPR_FN (exp); /* pointer expression */
4104 type = TREE_TYPE (type); /* pointer type */
4105 type = TREE_TYPE (type); /* function type */
4107 if (ix86_function_regparm (type, NULL) >= 3)
4109 /* ??? Need to count the actual number of registers to be used,
4110 not the possible number of registers. Fix later. */
4115 /* Dllimport'd functions are also called indirectly. */
4116 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4118 && decl && DECL_DLLIMPORT_P (decl)
4119 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4122 /* If we need to align the outgoing stack, then sibcalling would
4123 unalign the stack, which may break the called function. */
4124 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4127 /* Otherwise okay. That also includes certain types of indirect calls. */
4131 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4132 calling convention attributes;
4133 arguments as in struct attribute_spec.handler. */
4136 ix86_handle_cconv_attribute (tree *node, tree name,
4138 int flags ATTRIBUTE_UNUSED,
4141 if (TREE_CODE (*node) != FUNCTION_TYPE
4142 && TREE_CODE (*node) != METHOD_TYPE
4143 && TREE_CODE (*node) != FIELD_DECL
4144 && TREE_CODE (*node) != TYPE_DECL)
4146 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4147 IDENTIFIER_POINTER (name));
4148 *no_add_attrs = true;
4152 /* Can combine regparm with all attributes but fastcall. */
4153 if (is_attribute_p ("regparm", name))
4157 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4159 error ("fastcall and regparm attributes are not compatible");
4162 cst = TREE_VALUE (args);
4163 if (TREE_CODE (cst) != INTEGER_CST)
4165 warning (OPT_Wattributes,
4166 "%qs attribute requires an integer constant argument",
4167 IDENTIFIER_POINTER (name));
4168 *no_add_attrs = true;
4170 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4172 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4173 IDENTIFIER_POINTER (name), REGPARM_MAX);
4174 *no_add_attrs = true;
4182 /* Do not warn when emulating the MS ABI. */
4183 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4184 warning (OPT_Wattributes, "%qs attribute ignored",
4185 IDENTIFIER_POINTER (name));
4186 *no_add_attrs = true;
4190 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4191 if (is_attribute_p ("fastcall", name))
4193 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4195 error ("fastcall and cdecl attributes are not compatible");
4197 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4199 error ("fastcall and stdcall attributes are not compatible");
4201 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4203 error ("fastcall and regparm attributes are not compatible");
4207 /* Can combine stdcall with fastcall (redundant), regparm and
4209 else if (is_attribute_p ("stdcall", name))
4211 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4213 error ("stdcall and cdecl attributes are not compatible");
4215 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4217 error ("stdcall and fastcall attributes are not compatible");
4221 /* Can combine cdecl with regparm and sseregparm. */
4222 else if (is_attribute_p ("cdecl", name))
4224 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4226 error ("stdcall and cdecl attributes are not compatible");
4228 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4230 error ("fastcall and cdecl attributes are not compatible");
4234 /* Can combine sseregparm with all attributes. */
4239 /* Return 0 if the attributes for two types are incompatible, 1 if they
4240 are compatible, and 2 if they are nearly compatible (which causes a
4241 warning to be generated). */
4244 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4246 /* Check for mismatch of non-default calling convention. */
4247 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4249 if (TREE_CODE (type1) != FUNCTION_TYPE
4250 && TREE_CODE (type1) != METHOD_TYPE)
4253 /* Check for mismatched fastcall/regparm types. */
4254 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4255 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4256 || (ix86_function_regparm (type1, NULL)
4257 != ix86_function_regparm (type2, NULL)))
4260 /* Check for mismatched sseregparm types. */
4261 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4262 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4265 /* Check for mismatched return types (cdecl vs stdcall). */
4266 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4267 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4273 /* Return the regparm value for a function with the indicated TYPE and DECL.
4274 DECL may be NULL when calling function indirectly
4275 or considering a libcall. */
4278 ix86_function_regparm (const_tree type, const_tree decl)
4281 int regparm = ix86_regparm;
4283 static bool error_issued;
4287 if (ix86_function_type_abi (type) == DEFAULT_ABI)
4289 return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
4292 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4296 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4298 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4300 /* We can't use regparm(3) for nested functions because
4301 these pass static chain pointer in %ecx register. */
4302 if (!error_issued && regparm == 3
4303 && decl_function_context (decl)
4304 && !DECL_NO_STATIC_CHAIN (decl))
4306 error ("nested functions are limited to 2 register parameters");
4307 error_issued = true;
4315 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4318 /* Use register calling convention for local functions when possible. */
4319 if (decl && TREE_CODE (decl) == FUNCTION_DECL
4322 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4323 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4326 int local_regparm, globals = 0, regno;
4329 /* Make sure no regparm register is taken by a
4330 fixed register variable. */
4331 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4332 if (fixed_regs[local_regparm])
4335 /* We can't use regparm(3) for nested functions as these use
4336 static chain pointer in third argument. */
4337 if (local_regparm == 3
4338 && decl_function_context (decl)
4339 && !DECL_NO_STATIC_CHAIN (decl))
4342 /* If the function realigns its stackpointer, the prologue will
4343 clobber %ecx. If we've already generated code for the callee,
4344 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4345 scanning the attributes for the self-realigning property. */
4346 f = DECL_STRUCT_FUNCTION (decl);
4347 /* Since current internal arg pointer won't conflict with
4348 parameter passing regs, so no need to change stack
4349 realignment and adjust regparm number.
4351 Each fixed register usage increases register pressure,
4352 so less registers should be used for argument passing.
4353 This functionality can be overriden by an explicit
4355 for (regno = 0; regno <= DI_REG; regno++)
4356 if (fixed_regs[regno])
4360 = globals < local_regparm ? local_regparm - globals : 0;
4362 if (local_regparm > regparm)
4363 regparm = local_regparm;
4370 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4371 DFmode (2) arguments in SSE registers for a function with the
4372 indicated TYPE and DECL. DECL may be NULL when calling function
4373 indirectly or considering a libcall. Otherwise return 0. */
4376 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4378 gcc_assert (!TARGET_64BIT);
4380 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4381 by the sseregparm attribute. */
4382 if (TARGET_SSEREGPARM
4383 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4390 error ("Calling %qD with attribute sseregparm without "
4391 "SSE/SSE2 enabled", decl);
4393 error ("Calling %qT with attribute sseregparm without "
4394 "SSE/SSE2 enabled", type);
4402 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4403 (and DFmode for SSE2) arguments in SSE registers. */
4404 if (decl && TARGET_SSE_MATH && !profile_flag)
4406 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4407 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4409 return TARGET_SSE2 ? 2 : 1;
4415 /* Return true if EAX is live at the start of the function. Used by
4416 ix86_expand_prologue to determine if we need special help before
4417 calling allocate_stack_worker. */
4420 ix86_eax_live_at_start_p (void)
4422 /* Cheat. Don't bother working forward from ix86_function_regparm
4423 to the function type to whether an actual argument is located in
4424 eax. Instead just look at cfg info, which is still close enough
4425 to correct at this point. This gives false positives for broken
4426 functions that might use uninitialized data that happens to be
4427 allocated in eax, but who cares? */
4428 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4431 /* Value is the number of bytes of arguments automatically
4432 popped when returning from a subroutine call.
4433 FUNDECL is the declaration node of the function (as a tree),
4434 FUNTYPE is the data type of the function (as a tree),
4435 or for a library call it is an identifier node for the subroutine name.
4436 SIZE is the number of bytes of arguments passed on the stack.
4438 On the 80386, the RTD insn may be used to pop them if the number
4439 of args is fixed, but if the number is variable then the caller
4440 must pop them all. RTD can't be used for library calls now
4441 because the library is compiled with the Unix compiler.
4442 Use of RTD is a selectable option, since it is incompatible with
4443 standard Unix calling sequences. If the option is not selected,
4444 the caller must always pop the args.
4446 The attribute stdcall is equivalent to RTD on a per module basis. */
4449 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4453 /* None of the 64-bit ABIs pop arguments. */
4457 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4459 /* Cdecl functions override -mrtd, and never pop the stack. */
4460 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4462 /* Stdcall and fastcall functions will pop the stack if not
4464 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4465 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4468 if (rtd && ! stdarg_p (funtype))
4472 /* Lose any fake structure return argument if it is passed on the stack. */
4473 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4474 && !KEEP_AGGREGATE_RETURN_POINTER)
4476 int nregs = ix86_function_regparm (funtype, fundecl);
4478 return GET_MODE_SIZE (Pmode);
4484 /* Argument support functions. */
4486 /* Return true when register may be used to pass function parameters. */
4488 ix86_function_arg_regno_p (int regno)
4491 const int *parm_regs;
4496 return (regno < REGPARM_MAX
4497 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4499 return (regno < REGPARM_MAX
4500 || (TARGET_MMX && MMX_REGNO_P (regno)
4501 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4502 || (TARGET_SSE && SSE_REGNO_P (regno)
4503 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4508 if (SSE_REGNO_P (regno) && TARGET_SSE)
4513 if (TARGET_SSE && SSE_REGNO_P (regno)
4514 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4518 /* TODO: The function should depend on current function ABI but
4519 builtins.c would need updating then. Therefore we use the
4522 /* RAX is used as hidden argument to va_arg functions. */
4523 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4526 if (DEFAULT_ABI == MS_ABI)
4527 parm_regs = x86_64_ms_abi_int_parameter_registers;
4529 parm_regs = x86_64_int_parameter_registers;
4530 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4531 : X86_64_REGPARM_MAX); i++)
4532 if (regno == parm_regs[i])
4537 /* Return if we do not know how to pass TYPE solely in registers. */
4540 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4542 if (must_pass_in_stack_var_size_or_pad (mode, type))
4545 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4546 The layout_type routine is crafty and tries to trick us into passing
4547 currently unsupported vector types on the stack by using TImode. */
4548 return (!TARGET_64BIT && mode == TImode
4549 && type && TREE_CODE (type) != VECTOR_TYPE);
4552 /* It returns the size, in bytes, of the area reserved for arguments passed
4553 in registers for the function represented by fndecl dependent to the used
4556 ix86_reg_parm_stack_space (const_tree fndecl)
4558 int call_abi = SYSV_ABI;
4559 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4560 call_abi = ix86_function_abi (fndecl);
4562 call_abi = ix86_function_type_abi (fndecl);
4563 if (call_abi == MS_ABI)
4568 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4571 ix86_function_type_abi (const_tree fntype)
4573 if (TARGET_64BIT && fntype != NULL)
4576 if (DEFAULT_ABI == SYSV_ABI)
4577 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4579 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4587 ix86_function_abi (const_tree fndecl)
4591 return ix86_function_type_abi (TREE_TYPE (fndecl));
4594 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4597 ix86_cfun_abi (void)
4599 if (! cfun || ! TARGET_64BIT)
4601 return cfun->machine->call_abi;
4605 extern void init_regs (void);
4607 /* Implementation of call abi switching target hook. Specific to FNDECL
4608 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4609 for more details. */
4611 ix86_call_abi_override (const_tree fndecl)
4613 if (fndecl == NULL_TREE)
4614 cfun->machine->call_abi = DEFAULT_ABI;
4616 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4619 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4620 re-initialization of init_regs each time we switch function context since
4621 this is needed only during RTL expansion. */
4623 ix86_maybe_switch_abi (void)
4626 call_used_regs[4 /*RSI*/] == (cfun->machine->call_abi == MS_ABI))
4630 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4631 for a call to a function whose data type is FNTYPE.
4632 For a library call, FNTYPE is 0. */
4635 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4636 tree fntype, /* tree ptr for function decl */
4637 rtx libname, /* SYMBOL_REF of library name or 0 */
4640 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4641 memset (cum, 0, sizeof (*cum));
4644 cum->call_abi = ix86_function_abi (fndecl);
4646 cum->call_abi = ix86_function_type_abi (fntype);
4647 /* Set up the number of registers to use for passing arguments. */
4649 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4650 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4651 cum->nregs = ix86_regparm;
4654 if (cum->call_abi != DEFAULT_ABI)
4655 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4660 cum->sse_nregs = SSE_REGPARM_MAX;
4663 if (cum->call_abi != DEFAULT_ABI)
4664 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4665 : X64_SSE_REGPARM_MAX;
4669 cum->mmx_nregs = MMX_REGPARM_MAX;
4670 cum->warn_avx = true;
4671 cum->warn_sse = true;
4672 cum->warn_mmx = true;
4674 /* Because type might mismatch in between caller and callee, we need to
4675 use actual type of function for local calls.
4676 FIXME: cgraph_analyze can be told to actually record if function uses
4677 va_start so for local functions maybe_vaarg can be made aggressive
4679 FIXME: once typesytem is fixed, we won't need this code anymore. */
4681 fntype = TREE_TYPE (fndecl);
4682 cum->maybe_vaarg = (fntype
4683 ? (!prototype_p (fntype) || stdarg_p (fntype))
4688 /* If there are variable arguments, then we won't pass anything
4689 in registers in 32-bit mode. */
4690 if (stdarg_p (fntype))
4701 /* Use ecx and edx registers if function has fastcall attribute,
4702 else look for regparm information. */
4705 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4711 cum->nregs = ix86_function_regparm (fntype, fndecl);
4714 /* Set up the number of SSE registers used for passing SFmode
4715 and DFmode arguments. Warn for mismatching ABI. */
4716 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4720 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4721 But in the case of vector types, it is some vector mode.
4723 When we have only some of our vector isa extensions enabled, then there
4724 are some modes for which vector_mode_supported_p is false. For these
4725 modes, the generic vector support in gcc will choose some non-vector mode
4726 in order to implement the type. By computing the natural mode, we'll
4727 select the proper ABI location for the operand and not depend on whatever
4728 the middle-end decides to do with these vector types. */
4730 static enum machine_mode
4731 type_natural_mode (const_tree type)
4733 enum machine_mode mode = TYPE_MODE (type);
4735 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4737 HOST_WIDE_INT size = int_size_in_bytes (type);
4738 if ((size == 8 || size == 16)
4739 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4740 && TYPE_VECTOR_SUBPARTS (type) > 1)
4742 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4744 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4745 mode = MIN_MODE_VECTOR_FLOAT;
4747 mode = MIN_MODE_VECTOR_INT;
4749 /* Get the mode which has this inner mode and number of units. */
4750 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4751 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4752 && GET_MODE_INNER (mode) == innermode)
4762 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4763 this may not agree with the mode that the type system has chosen for the
4764 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4765 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4768 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4773 if (orig_mode != BLKmode)
4774 tmp = gen_rtx_REG (orig_mode, regno);
4777 tmp = gen_rtx_REG (mode, regno);
4778 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4779 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4785 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4786 of this code is to classify each 8bytes of incoming argument by the register
4787 class and assign registers accordingly. */
4789 /* Return the union class of CLASS1 and CLASS2.
4790 See the x86-64 PS ABI for details. */
4792 static enum x86_64_reg_class
4793 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4795 /* Rule #1: If both classes are equal, this is the resulting class. */
4796 if (class1 == class2)
4799 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4801 if (class1 == X86_64_NO_CLASS)
4803 if (class2 == X86_64_NO_CLASS)
4806 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4807 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4808 return X86_64_MEMORY_CLASS;
4810 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4811 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4812 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4813 return X86_64_INTEGERSI_CLASS;
4814 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4815 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4816 return X86_64_INTEGER_CLASS;
4818 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4820 if (class1 == X86_64_X87_CLASS
4821 || class1 == X86_64_X87UP_CLASS
4822 || class1 == X86_64_COMPLEX_X87_CLASS
4823 || class2 == X86_64_X87_CLASS
4824 || class2 == X86_64_X87UP_CLASS
4825 || class2 == X86_64_COMPLEX_X87_CLASS)
4826 return X86_64_MEMORY_CLASS;
4828 /* Rule #6: Otherwise class SSE is used. */
4829 return X86_64_SSE_CLASS;
4832 /* Classify the argument of type TYPE and mode MODE.
4833 CLASSES will be filled by the register class used to pass each word
4834 of the operand. The number of words is returned. In case the parameter
4835 should be passed in memory, 0 is returned. As a special case for zero
4836 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4838 BIT_OFFSET is used internally for handling records and specifies offset
4839 of the offset in bits modulo 256 to avoid overflow cases.
4841 See the x86-64 PS ABI for details.
4845 classify_argument (enum machine_mode mode, const_tree type,
4846 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4848 HOST_WIDE_INT bytes =
4849 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4850 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4852 /* Variable sized entities are always passed/returned in memory. */
4856 if (mode != VOIDmode
4857 && targetm.calls.must_pass_in_stack (mode, type))
4860 if (type && AGGREGATE_TYPE_P (type))
4864 enum x86_64_reg_class subclasses[MAX_CLASSES];
4866 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
4870 for (i = 0; i < words; i++)
4871 classes[i] = X86_64_NO_CLASS;
4873 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4874 signalize memory class, so handle it as special case. */
4877 classes[0] = X86_64_NO_CLASS;
4881 /* Classify each field of record and merge classes. */
4882 switch (TREE_CODE (type))
4885 /* And now merge the fields of structure. */
4886 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4888 if (TREE_CODE (field) == FIELD_DECL)
4892 if (TREE_TYPE (field) == error_mark_node)
4895 /* Bitfields are always classified as integer. Handle them
4896 early, since later code would consider them to be
4897 misaligned integers. */
4898 if (DECL_BIT_FIELD (field))
4900 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4901 i < ((int_bit_position (field) + (bit_offset % 64))
4902 + tree_low_cst (DECL_SIZE (field), 0)
4905 merge_classes (X86_64_INTEGER_CLASS,
4910 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4911 TREE_TYPE (field), subclasses,
4912 (int_bit_position (field)
4913 + bit_offset) % 256);
4916 for (i = 0; i < num; i++)
4919 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4921 merge_classes (subclasses[i], classes[i + pos]);
4929 /* Arrays are handled as small records. */
4932 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4933 TREE_TYPE (type), subclasses, bit_offset);
4937 /* The partial classes are now full classes. */
4938 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4939 subclasses[0] = X86_64_SSE_CLASS;
4940 if (subclasses[0] == X86_64_INTEGERSI_CLASS
4941 && !((bit_offset % 64) == 0 && bytes == 4))
4942 subclasses[0] = X86_64_INTEGER_CLASS;
4944 for (i = 0; i < words; i++)
4945 classes[i] = subclasses[i % num];
4950 case QUAL_UNION_TYPE:
4951 /* Unions are similar to RECORD_TYPE but offset is always 0.
4953 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4955 if (TREE_CODE (field) == FIELD_DECL)
4959 if (TREE_TYPE (field) == error_mark_node)
4962 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4963 TREE_TYPE (field), subclasses,
4967 for (i = 0; i < num; i++)
4968 classes[i] = merge_classes (subclasses[i], classes[i]);
4977 /* Final merger cleanup. */
4978 for (i = 0; i < words; i++)
4980 /* If one class is MEMORY, everything should be passed in
4982 if (classes[i] == X86_64_MEMORY_CLASS)
4985 /* The X86_64_SSEUP_CLASS should be always preceded by
4986 X86_64_SSE_CLASS. */
4987 if (classes[i] == X86_64_SSEUP_CLASS
4988 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
4989 classes[i] = X86_64_SSE_CLASS;
4991 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
4992 if (classes[i] == X86_64_X87UP_CLASS
4993 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
4994 classes[i] = X86_64_SSE_CLASS;
4999 /* Compute alignment needed. We align all types to natural boundaries with
5000 exception of XFmode that is aligned to 64bits. */
5001 if (mode != VOIDmode && mode != BLKmode)
5003 int mode_alignment = GET_MODE_BITSIZE (mode);
5006 mode_alignment = 128;
5007 else if (mode == XCmode)
5008 mode_alignment = 256;
5009 if (COMPLEX_MODE_P (mode))
5010 mode_alignment /= 2;
5011 /* Misaligned fields are always returned in memory. */
5012 if (bit_offset % mode_alignment)
5016 /* for V1xx modes, just use the base mode */
5017 if (VECTOR_MODE_P (mode) && mode != V1DImode
5018 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5019 mode = GET_MODE_INNER (mode);
5021 /* Classification of atomic types. */
5026 classes[0] = X86_64_SSE_CLASS;
5029 classes[0] = X86_64_SSE_CLASS;
5030 classes[1] = X86_64_SSEUP_CLASS;
5040 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5044 classes[0] = X86_64_INTEGERSI_CLASS;
5047 else if (size <= 64)
5049 classes[0] = X86_64_INTEGER_CLASS;
5052 else if (size <= 64+32)
5054 classes[0] = X86_64_INTEGER_CLASS;
5055 classes[1] = X86_64_INTEGERSI_CLASS;
5058 else if (size <= 64+64)
5060 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5068 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5075 if (!(bit_offset % 64))
5076 classes[0] = X86_64_SSESF_CLASS;
5078 classes[0] = X86_64_SSE_CLASS;
5081 classes[0] = X86_64_SSEDF_CLASS;
5084 classes[0] = X86_64_X87_CLASS;
5085 classes[1] = X86_64_X87UP_CLASS;
5088 classes[0] = X86_64_SSE_CLASS;
5089 classes[1] = X86_64_SSEUP_CLASS;
5092 classes[0] = X86_64_SSE_CLASS;
5095 classes[0] = X86_64_SSEDF_CLASS;
5096 classes[1] = X86_64_SSEDF_CLASS;
5099 classes[0] = X86_64_COMPLEX_X87_CLASS;
5102 /* This modes is larger than 16 bytes. */
5110 classes[0] = X86_64_AVX_CLASS;
5118 classes[0] = X86_64_SSE_CLASS;
5119 classes[1] = X86_64_SSEUP_CLASS;
5126 classes[0] = X86_64_SSE_CLASS;
5132 gcc_assert (VECTOR_MODE_P (mode));
5137 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5139 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5140 classes[0] = X86_64_INTEGERSI_CLASS;
5142 classes[0] = X86_64_INTEGER_CLASS;
5143 classes[1] = X86_64_INTEGER_CLASS;
5144 return 1 + (bytes > 8);
5148 /* Examine the argument and return set number of register required in each
5149 class. Return 0 iff parameter should be passed in memory. */
5151 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5152 int *int_nregs, int *sse_nregs)
5154 enum x86_64_reg_class regclass[MAX_CLASSES];
5155 int n = classify_argument (mode, type, regclass, 0);
5161 for (n--; n >= 0; n--)
5162 switch (regclass[n])
5164 case X86_64_INTEGER_CLASS:
5165 case X86_64_INTEGERSI_CLASS:
5168 case X86_64_AVX_CLASS:
5169 case X86_64_SSE_CLASS:
5170 case X86_64_SSESF_CLASS:
5171 case X86_64_SSEDF_CLASS:
5174 case X86_64_NO_CLASS:
5175 case X86_64_SSEUP_CLASS:
5177 case X86_64_X87_CLASS:
5178 case X86_64_X87UP_CLASS:
5182 case X86_64_COMPLEX_X87_CLASS:
5183 return in_return ? 2 : 0;
5184 case X86_64_MEMORY_CLASS:
5190 /* Construct container for the argument used by GCC interface. See
5191 FUNCTION_ARG for the detailed description. */
5194 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5195 const_tree type, int in_return, int nintregs, int nsseregs,
5196 const int *intreg, int sse_regno)
5198 /* The following variables hold the static issued_error state. */
5199 static bool issued_sse_arg_error;
5200 static bool issued_sse_ret_error;
5201 static bool issued_x87_ret_error;
5203 enum machine_mode tmpmode;
5205 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5206 enum x86_64_reg_class regclass[MAX_CLASSES];
5210 int needed_sseregs, needed_intregs;
5211 rtx exp[MAX_CLASSES];
5214 n = classify_argument (mode, type, regclass, 0);
5217 if (!examine_argument (mode, type, in_return, &needed_intregs,
5220 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5223 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5224 some less clueful developer tries to use floating-point anyway. */
5225 if (needed_sseregs && !TARGET_SSE)
5229 if (!issued_sse_ret_error)
5231 error ("SSE register return with SSE disabled");
5232 issued_sse_ret_error = true;
5235 else if (!issued_sse_arg_error)
5237 error ("SSE register argument with SSE disabled");
5238 issued_sse_arg_error = true;
5243 /* Likewise, error if the ABI requires us to return values in the
5244 x87 registers and the user specified -mno-80387. */
5245 if (!TARGET_80387 && in_return)
5246 for (i = 0; i < n; i++)
5247 if (regclass[i] == X86_64_X87_CLASS
5248 || regclass[i] == X86_64_X87UP_CLASS
5249 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5251 if (!issued_x87_ret_error)
5253 error ("x87 register return with x87 disabled");
5254 issued_x87_ret_error = true;
5259 /* First construct simple cases. Avoid SCmode, since we want to use
5260 single register to pass this type. */
5261 if (n == 1 && mode != SCmode)
5262 switch (regclass[0])
5264 case X86_64_INTEGER_CLASS:
5265 case X86_64_INTEGERSI_CLASS:
5266 return gen_rtx_REG (mode, intreg[0]);
5267 case X86_64_AVX_CLASS:
5268 case X86_64_SSE_CLASS:
5269 case X86_64_SSESF_CLASS:
5270 case X86_64_SSEDF_CLASS:
5271 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5272 case X86_64_X87_CLASS:
5273 case X86_64_COMPLEX_X87_CLASS:
5274 return gen_rtx_REG (mode, FIRST_STACK_REG);
5275 case X86_64_NO_CLASS:
5276 /* Zero sized array, struct or class. */
5281 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5282 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5283 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5286 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5287 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5288 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5289 && regclass[1] == X86_64_INTEGER_CLASS
5290 && (mode == CDImode || mode == TImode || mode == TFmode)
5291 && intreg[0] + 1 == intreg[1])
5292 return gen_rtx_REG (mode, intreg[0]);
5294 /* Otherwise figure out the entries of the PARALLEL. */
5295 for (i = 0; i < n; i++)
5297 switch (regclass[i])
5299 case X86_64_NO_CLASS:
5301 case X86_64_INTEGER_CLASS:
5302 case X86_64_INTEGERSI_CLASS:
5303 /* Merge TImodes on aligned occasions here too. */
5304 if (i * 8 + 8 > bytes)
5305 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5306 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5310 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5311 if (tmpmode == BLKmode)
5313 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5314 gen_rtx_REG (tmpmode, *intreg),
5318 case X86_64_SSESF_CLASS:
5319 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5320 gen_rtx_REG (SFmode,
5321 SSE_REGNO (sse_regno)),
5325 case X86_64_SSEDF_CLASS:
5326 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5327 gen_rtx_REG (DFmode,
5328 SSE_REGNO (sse_regno)),
5332 case X86_64_SSE_CLASS:
5333 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
5337 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5338 gen_rtx_REG (tmpmode,
5339 SSE_REGNO (sse_regno)),
5341 if (tmpmode == TImode)
5350 /* Empty aligned struct, union or class. */
5354 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5355 for (i = 0; i < nexps; i++)
5356 XVECEXP (ret, 0, i) = exp [i];
5360 /* Update the data in CUM to advance over an argument of mode MODE
5361 and data type TYPE. (TYPE is null for libcalls where that information
5362 may not be available.) */
5365 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5366 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5382 cum->words += words;
5383 cum->nregs -= words;
5384 cum->regno += words;
5386 if (cum->nregs <= 0)
5394 if (cum->float_in_sse < 2)
5397 if (cum->float_in_sse < 1)
5415 if (!type || !AGGREGATE_TYPE_P (type))
5417 cum->sse_words += words;
5418 cum->sse_nregs -= 1;
5419 cum->sse_regno += 1;
5420 if (cum->sse_nregs <= 0)
5433 if (!type || !AGGREGATE_TYPE_P (type))
5435 cum->mmx_words += words;
5436 cum->mmx_nregs -= 1;
5437 cum->mmx_regno += 1;
5438 if (cum->mmx_nregs <= 0)
5449 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5450 tree type, HOST_WIDE_INT words, int named)
5452 int int_nregs, sse_nregs;
5454 /* Unnamed 256bit vector mode parameters are passed on stack. */
5455 if (!named && VALID_AVX256_REG_MODE (mode))
5458 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5459 cum->words += words;
5460 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5462 cum->nregs -= int_nregs;
5463 cum->sse_nregs -= sse_nregs;
5464 cum->regno += int_nregs;
5465 cum->sse_regno += sse_nregs;
5468 cum->words += words;
5472 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5473 HOST_WIDE_INT words)
5475 /* Otherwise, this should be passed indirect. */
5476 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5478 cum->words += words;
5487 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5488 tree type, int named)
5490 HOST_WIDE_INT bytes, words;
5492 if (mode == BLKmode)
5493 bytes = int_size_in_bytes (type);
5495 bytes = GET_MODE_SIZE (mode);
5496 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5499 mode = type_natural_mode (type);
5501 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5502 function_arg_advance_ms_64 (cum, bytes, words);
5503 else if (TARGET_64BIT)
5504 function_arg_advance_64 (cum, mode, type, words, named);
5506 function_arg_advance_32 (cum, mode, type, bytes, words);
5509 /* Define where to put the arguments to a function.
5510 Value is zero to push the argument on the stack,
5511 or a hard register in which to store the argument.
5513 MODE is the argument's machine mode.
5514 TYPE is the data type of the argument (as a tree).
5515 This is null for libcalls where that information may
5517 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5518 the preceding args and about the function being called.
5519 NAMED is nonzero if this argument is a named parameter
5520 (otherwise it is an extra parameter matching an ellipsis). */
5523 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5524 enum machine_mode orig_mode, tree type,
5525 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5527 static bool warnedavx, warnedsse, warnedmmx;
5529 /* Avoid the AL settings for the Unix64 ABI. */
5530 if (mode == VOIDmode)
5546 if (words <= cum->nregs)
5548 int regno = cum->regno;
5550 /* Fastcall allocates the first two DWORD (SImode) or
5551 smaller arguments to ECX and EDX if it isn't an
5557 || (type && AGGREGATE_TYPE_P (type)))
5560 /* ECX not EAX is the first allocated register. */
5561 if (regno == AX_REG)
5564 return gen_rtx_REG (mode, regno);
5569 if (cum->float_in_sse < 2)
5572 if (cum->float_in_sse < 1)
5576 /* In 32bit, we pass TImode in xmm registers. */
5583 if (!type || !AGGREGATE_TYPE_P (type))
5585 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5588 warning (0, "SSE vector argument without SSE enabled "
5592 return gen_reg_or_parallel (mode, orig_mode,
5593 cum->sse_regno + FIRST_SSE_REG);
5598 /* In 32bit, we pass OImode in ymm registers. */
5605 if (!type || !AGGREGATE_TYPE_P (type))
5607 if (!TARGET_AVX && !warnedavx && cum->warn_avx)
5610 warning (0, "AVX vector argument without AVX enabled "
5614 return gen_reg_or_parallel (mode, orig_mode,
5615 cum->sse_regno + FIRST_SSE_REG);
5624 if (!type || !AGGREGATE_TYPE_P (type))
5626 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5629 warning (0, "MMX vector argument without MMX enabled "
5633 return gen_reg_or_parallel (mode, orig_mode,
5634 cum->mmx_regno + FIRST_MMX_REG);
5643 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5644 enum machine_mode orig_mode, tree type, int named)
5646 static bool warnedavx;
5648 /* Handle a hidden AL argument containing number of registers
5649 for varargs x86-64 functions. */
5650 if (mode == VOIDmode)
5651 return GEN_INT (cum->maybe_vaarg
5652 ? (cum->sse_nregs < 0
5653 ? (cum->call_abi == DEFAULT_ABI
5655 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5656 : X64_SSE_REGPARM_MAX))
5671 /* In 64bit, we pass TImode in interger registers and OImode on
5673 if (!type || !AGGREGATE_TYPE_P (type))
5675 if (!TARGET_AVX && !warnedavx && cum->warn_avx)
5678 warning (0, "AVX vector argument without AVX enabled "
5683 /* Unnamed 256bit vector mode parameters are passed on stack. */
5689 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5691 &x86_64_int_parameter_registers [cum->regno],
5696 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5697 enum machine_mode orig_mode, int named,
5698 HOST_WIDE_INT bytes)
5702 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5703 We use value of -2 to specify that current function call is MSABI. */
5704 if (mode == VOIDmode)
5705 return GEN_INT (-2);
5707 /* If we've run out of registers, it goes on the stack. */
5708 if (cum->nregs == 0)
5711 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5713 /* Only floating point modes are passed in anything but integer regs. */
5714 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5717 regno = cum->regno + FIRST_SSE_REG;
5722 /* Unnamed floating parameters are passed in both the
5723 SSE and integer registers. */
5724 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5725 t2 = gen_rtx_REG (mode, regno);
5726 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5727 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5728 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5731 /* Handle aggregated types passed in register. */
5732 if (orig_mode == BLKmode)
5734 if (bytes > 0 && bytes <= 8)
5735 mode = (bytes > 4 ? DImode : SImode);
5736 if (mode == BLKmode)
5740 return gen_reg_or_parallel (mode, orig_mode, regno);
5744 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5745 tree type, int named)
5747 enum machine_mode mode = omode;
5748 HOST_WIDE_INT bytes, words;
5750 if (mode == BLKmode)
5751 bytes = int_size_in_bytes (type);
5753 bytes = GET_MODE_SIZE (mode);
5754 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5756 /* To simplify the code below, represent vector types with a vector mode
5757 even if MMX/SSE are not active. */
5758 if (type && TREE_CODE (type) == VECTOR_TYPE)
5759 mode = type_natural_mode (type);
5761 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5762 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5763 else if (TARGET_64BIT)
5764 return function_arg_64 (cum, mode, omode, type, named);
5766 return function_arg_32 (cum, mode, omode, type, bytes, words);
5769 /* A C expression that indicates when an argument must be passed by
5770 reference. If nonzero for an argument, a copy of that argument is
5771 made in memory and a pointer to the argument is passed instead of
5772 the argument itself. The pointer is passed in whatever way is
5773 appropriate for passing a pointer to that type. */
5776 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5777 enum machine_mode mode ATTRIBUTE_UNUSED,
5778 const_tree type, bool named ATTRIBUTE_UNUSED)
5780 /* See Windows x64 Software Convention. */
5781 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5783 int msize = (int) GET_MODE_SIZE (mode);
5786 /* Arrays are passed by reference. */
5787 if (TREE_CODE (type) == ARRAY_TYPE)
5790 if (AGGREGATE_TYPE_P (type))
5792 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5793 are passed by reference. */
5794 msize = int_size_in_bytes (type);
5798 /* __m128 is passed by reference. */
5800 case 1: case 2: case 4: case 8:
5806 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5812 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5815 contains_aligned_value_p (tree type)
5817 enum machine_mode mode = TYPE_MODE (type);
5818 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5822 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5824 if (TYPE_ALIGN (type) < 128)
5827 if (AGGREGATE_TYPE_P (type))
5829 /* Walk the aggregates recursively. */
5830 switch (TREE_CODE (type))
5834 case QUAL_UNION_TYPE:
5838 /* Walk all the structure fields. */
5839 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5841 if (TREE_CODE (field) == FIELD_DECL
5842 && contains_aligned_value_p (TREE_TYPE (field)))
5849 /* Just for use if some languages passes arrays by value. */
5850 if (contains_aligned_value_p (TREE_TYPE (type)))
5861 /* Gives the alignment boundary, in bits, of an argument with the
5862 specified mode and type. */
5865 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5870 /* Since canonical type is used for call, we convert it to
5871 canonical type if needed. */
5872 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5873 type = TYPE_CANONICAL (type);
5874 align = TYPE_ALIGN (type);
5877 align = GET_MODE_ALIGNMENT (mode);
5878 if (align < PARM_BOUNDARY)
5879 align = PARM_BOUNDARY;
5880 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5881 natural boundaries. */
5882 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5884 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5885 make an exception for SSE modes since these require 128bit
5888 The handling here differs from field_alignment. ICC aligns MMX
5889 arguments to 4 byte boundaries, while structure fields are aligned
5890 to 8 byte boundaries. */
5893 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5894 align = PARM_BOUNDARY;
5898 if (!contains_aligned_value_p (type))
5899 align = PARM_BOUNDARY;
5902 if (align > BIGGEST_ALIGNMENT)
5903 align = BIGGEST_ALIGNMENT;
5907 /* Return true if N is a possible register number of function value. */
5910 ix86_function_value_regno_p (int regno)
5917 case FIRST_FLOAT_REG:
5918 /* TODO: The function should depend on current function ABI but
5919 builtins.c would need updating then. Therefore we use the
5921 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
5923 return TARGET_FLOAT_RETURNS_IN_80387;
5929 if (TARGET_MACHO || TARGET_64BIT)
5937 /* Define how to find the value returned by a function.
5938 VALTYPE is the data type of the value (as a tree).
5939 If the precise function being called is known, FUNC is its FUNCTION_DECL;
5940 otherwise, FUNC is 0. */
5943 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
5944 const_tree fntype, const_tree fn)
5948 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
5949 we normally prevent this case when mmx is not available. However
5950 some ABIs may require the result to be returned like DImode. */
5951 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
5952 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
5954 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
5955 we prevent this case when sse is not available. However some ABIs
5956 may require the result to be returned like integer TImode. */
5957 else if (mode == TImode
5958 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
5959 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
5961 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
5962 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
5963 regno = FIRST_FLOAT_REG;
5965 /* Most things go in %eax. */
5968 /* Override FP return register with %xmm0 for local functions when
5969 SSE math is enabled or for functions with sseregparm attribute. */
5970 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
5972 int sse_level = ix86_function_sseregparm (fntype, fn, false);
5973 if ((sse_level >= 1 && mode == SFmode)
5974 || (sse_level == 2 && mode == DFmode))
5975 regno = FIRST_SSE_REG;
5978 return gen_rtx_REG (orig_mode, regno);
5982 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
5987 /* Handle libcalls, which don't provide a type node. */
5988 if (valtype == NULL)
6000 return gen_rtx_REG (mode, FIRST_SSE_REG);
6003 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6007 return gen_rtx_REG (mode, AX_REG);
6011 ret = construct_container (mode, orig_mode, valtype, 1,
6012 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6013 x86_64_int_return_registers, 0);
6015 /* For zero sized structures, construct_container returns NULL, but we
6016 need to keep rest of compiler happy by returning meaningful value. */
6018 ret = gen_rtx_REG (orig_mode, AX_REG);
6024 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6026 unsigned int regno = AX_REG;
6030 switch (GET_MODE_SIZE (mode))
6033 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6034 && !COMPLEX_MODE_P (mode))
6035 regno = FIRST_SSE_REG;
6039 if (mode == SFmode || mode == DFmode)
6040 regno = FIRST_SSE_REG;
6046 return gen_rtx_REG (orig_mode, regno);
6050 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6051 enum machine_mode orig_mode, enum machine_mode mode)
6053 const_tree fn, fntype;
6056 if (fntype_or_decl && DECL_P (fntype_or_decl))
6057 fn = fntype_or_decl;
6058 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6060 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6061 return function_value_ms_64 (orig_mode, mode);
6062 else if (TARGET_64BIT)
6063 return function_value_64 (orig_mode, mode, valtype);
6065 return function_value_32 (orig_mode, mode, fntype, fn);
6069 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6070 bool outgoing ATTRIBUTE_UNUSED)
6072 enum machine_mode mode, orig_mode;
6074 orig_mode = TYPE_MODE (valtype);
6075 mode = type_natural_mode (valtype);
6076 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6080 ix86_libcall_value (enum machine_mode mode)
6082 return ix86_function_value_1 (NULL, NULL, mode, mode);
6085 /* Return true iff type is returned in memory. */
6087 static int ATTRIBUTE_UNUSED
6088 return_in_memory_32 (const_tree type, enum machine_mode mode)
6092 if (mode == BLKmode)
6095 size = int_size_in_bytes (type);
6097 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6100 if (VECTOR_MODE_P (mode) || mode == TImode)
6102 /* User-created vectors small enough to fit in EAX. */
6106 /* MMX/3dNow values are returned in MM0,
6107 except when it doesn't exits. */
6109 return (TARGET_MMX ? 0 : 1);
6111 /* SSE values are returned in XMM0, except when it doesn't exist. */
6113 return (TARGET_SSE ? 0 : 1);
6124 static int ATTRIBUTE_UNUSED
6125 return_in_memory_64 (const_tree type, enum machine_mode mode)
6127 int needed_intregs, needed_sseregs;
6128 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6131 static int ATTRIBUTE_UNUSED
6132 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6134 HOST_WIDE_INT size = int_size_in_bytes (type);
6136 /* __m128 is returned in xmm0. */
6137 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6138 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6141 /* Otherwise, the size must be exactly in [1248]. */
6142 return (size != 1 && size != 2 && size != 4 && size != 8);
6146 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6148 #ifdef SUBTARGET_RETURN_IN_MEMORY
6149 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6151 const enum machine_mode mode = type_natural_mode (type);
6153 if (TARGET_64BIT_MS_ABI)
6154 return return_in_memory_ms_64 (type, mode);
6155 else if (TARGET_64BIT)
6156 return return_in_memory_64 (type, mode);
6158 return return_in_memory_32 (type, mode);
6162 /* Return false iff TYPE is returned in memory. This version is used
6163 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6164 but differs notably in that when MMX is available, 8-byte vectors
6165 are returned in memory, rather than in MMX registers. */
6168 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6171 enum machine_mode mode = type_natural_mode (type);
6174 return return_in_memory_64 (type, mode);
6176 if (mode == BLKmode)
6179 size = int_size_in_bytes (type);
6181 if (VECTOR_MODE_P (mode))
6183 /* Return in memory only if MMX registers *are* available. This
6184 seems backwards, but it is consistent with the existing
6191 else if (mode == TImode)
6193 else if (mode == XFmode)
6199 /* When returning SSE vector types, we have a choice of either
6200 (1) being abi incompatible with a -march switch, or
6201 (2) generating an error.
6202 Given no good solution, I think the safest thing is one warning.
6203 The user won't be able to use -Werror, but....
6205 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6206 called in response to actually generating a caller or callee that
6207 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6208 via aggregate_value_p for general type probing from tree-ssa. */
6211 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6213 static bool warnedsse, warnedmmx;
6215 if (!TARGET_64BIT && type)
6217 /* Look at the return type of the function, not the function type. */
6218 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6220 if (!TARGET_SSE && !warnedsse)
6223 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6226 warning (0, "SSE vector return without SSE enabled "
6231 if (!TARGET_MMX && !warnedmmx)
6233 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6236 warning (0, "MMX vector return without MMX enabled "
6246 /* Create the va_list data type. */
6248 /* Returns the calling convention specific va_list date type.
6249 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6252 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6254 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6256 /* For i386 we use plain pointer to argument area. */
6257 if (!TARGET_64BIT || abi == MS_ABI)
6258 return build_pointer_type (char_type_node);
6260 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6261 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6263 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6264 unsigned_type_node);
6265 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6266 unsigned_type_node);
6267 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6269 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6272 va_list_gpr_counter_field = f_gpr;
6273 va_list_fpr_counter_field = f_fpr;
6275 DECL_FIELD_CONTEXT (f_gpr) = record;
6276 DECL_FIELD_CONTEXT (f_fpr) = record;
6277 DECL_FIELD_CONTEXT (f_ovf) = record;
6278 DECL_FIELD_CONTEXT (f_sav) = record;
6280 TREE_CHAIN (record) = type_decl;
6281 TYPE_NAME (record) = type_decl;
6282 TYPE_FIELDS (record) = f_gpr;
6283 TREE_CHAIN (f_gpr) = f_fpr;
6284 TREE_CHAIN (f_fpr) = f_ovf;
6285 TREE_CHAIN (f_ovf) = f_sav;
6287 layout_type (record);
6289 /* The correct type is an array type of one element. */
6290 return build_array_type (record, build_index_type (size_zero_node));
6293 /* Setup the builtin va_list data type and for 64-bit the additional
6294 calling convention specific va_list data types. */
6297 ix86_build_builtin_va_list (void)
6299 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6301 /* Initialize abi specific va_list builtin types. */
6305 if (DEFAULT_ABI == MS_ABI)
6307 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6308 if (TREE_CODE (t) != RECORD_TYPE)
6309 t = build_variant_type_copy (t);
6310 sysv_va_list_type_node = t;
6315 if (TREE_CODE (t) != RECORD_TYPE)
6316 t = build_variant_type_copy (t);
6317 sysv_va_list_type_node = t;
6319 if (DEFAULT_ABI != MS_ABI)
6321 t = ix86_build_builtin_va_list_abi (MS_ABI);
6322 if (TREE_CODE (t) != RECORD_TYPE)
6323 t = build_variant_type_copy (t);
6324 ms_va_list_type_node = t;
6329 if (TREE_CODE (t) != RECORD_TYPE)
6330 t = build_variant_type_copy (t);
6331 ms_va_list_type_node = t;
6338 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6341 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6350 int regparm = ix86_regparm;
6352 if (cum->call_abi != DEFAULT_ABI)
6353 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6355 /* GPR size of varargs save area. */
6356 if (cfun->va_list_gpr_size)
6357 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6359 ix86_varargs_gpr_size = 0;
6361 /* FPR size of varargs save area. We don't need it if we don't pass
6362 anything in SSE registers. */
6363 if (cum->sse_nregs && cfun->va_list_fpr_size)
6364 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6366 ix86_varargs_fpr_size = 0;
6368 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6371 save_area = frame_pointer_rtx;
6372 set = get_varargs_alias_set ();
6374 for (i = cum->regno;
6376 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6379 mem = gen_rtx_MEM (Pmode,
6380 plus_constant (save_area, i * UNITS_PER_WORD));
6381 MEM_NOTRAP_P (mem) = 1;
6382 set_mem_alias_set (mem, set);
6383 emit_move_insn (mem, gen_rtx_REG (Pmode,
6384 x86_64_int_parameter_registers[i]));
6387 if (ix86_varargs_fpr_size)
6389 /* Now emit code to save SSE registers. The AX parameter contains number
6390 of SSE parameter registers used to call this function. We use
6391 sse_prologue_save insn template that produces computed jump across
6392 SSE saves. We need some preparation work to get this working. */
6394 label = gen_label_rtx ();
6395 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6397 /* Compute address to jump to :
6398 label - eax*4 + nnamed_sse_arguments*4 Or
6399 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6400 tmp_reg = gen_reg_rtx (Pmode);
6401 nsse_reg = gen_reg_rtx (Pmode);
6402 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6403 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6404 gen_rtx_MULT (Pmode, nsse_reg,
6407 /* vmovaps is one byte longer than movaps. */
6409 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6410 gen_rtx_PLUS (Pmode, tmp_reg,
6416 gen_rtx_CONST (DImode,
6417 gen_rtx_PLUS (DImode,
6419 GEN_INT (cum->sse_regno
6420 * (TARGET_AVX ? 5 : 4)))));
6422 emit_move_insn (nsse_reg, label_ref);
6423 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6425 /* Compute address of memory block we save into. We always use pointer
6426 pointing 127 bytes after first byte to store - this is needed to keep
6427 instruction size limited by 4 bytes (5 bytes for AVX) with one
6428 byte displacement. */
6429 tmp_reg = gen_reg_rtx (Pmode);
6430 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6431 plus_constant (save_area,
6432 ix86_varargs_gpr_size + 127)));
6433 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6434 MEM_NOTRAP_P (mem) = 1;
6435 set_mem_alias_set (mem, set);
6436 set_mem_align (mem, BITS_PER_WORD);
6438 /* And finally do the dirty job! */
6439 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6440 GEN_INT (cum->sse_regno), label));
6445 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6447 alias_set_type set = get_varargs_alias_set ();
6450 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6454 mem = gen_rtx_MEM (Pmode,
6455 plus_constant (virtual_incoming_args_rtx,
6456 i * UNITS_PER_WORD));
6457 MEM_NOTRAP_P (mem) = 1;
6458 set_mem_alias_set (mem, set);
6460 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6461 emit_move_insn (mem, reg);
6466 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6467 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6470 CUMULATIVE_ARGS next_cum;
6473 /* This argument doesn't appear to be used anymore. Which is good,
6474 because the old code here didn't suppress rtl generation. */
6475 gcc_assert (!no_rtl);
6480 fntype = TREE_TYPE (current_function_decl);
6482 /* For varargs, we do not want to skip the dummy va_dcl argument.
6483 For stdargs, we do want to skip the last named argument. */
6485 if (stdarg_p (fntype))
6486 function_arg_advance (&next_cum, mode, type, 1);
6488 if (cum->call_abi == MS_ABI)
6489 setup_incoming_varargs_ms_64 (&next_cum);
6491 setup_incoming_varargs_64 (&next_cum);
6494 /* Checks if TYPE is of kind va_list char *. */
6497 is_va_list_char_pointer (tree type)
6501 /* For 32-bit it is always true. */
6504 canonic = ix86_canonical_va_list_type (type);
6505 return (canonic == ms_va_list_type_node
6506 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6509 /* Implement va_start. */
6512 ix86_va_start (tree valist, rtx nextarg)
6514 HOST_WIDE_INT words, n_gpr, n_fpr;
6515 tree f_gpr, f_fpr, f_ovf, f_sav;
6516 tree gpr, fpr, ovf, sav, t;
6519 /* Only 64bit target needs something special. */
6520 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6522 std_expand_builtin_va_start (valist, nextarg);
6526 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6527 f_fpr = TREE_CHAIN (f_gpr);
6528 f_ovf = TREE_CHAIN (f_fpr);
6529 f_sav = TREE_CHAIN (f_ovf);
6531 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6532 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6533 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6534 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6535 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6537 /* Count number of gp and fp argument registers used. */
6538 words = crtl->args.info.words;
6539 n_gpr = crtl->args.info.regno;
6540 n_fpr = crtl->args.info.sse_regno;
6542 if (cfun->va_list_gpr_size)
6544 type = TREE_TYPE (gpr);
6545 t = build2 (MODIFY_EXPR, type,
6546 gpr, build_int_cst (type, n_gpr * 8));
6547 TREE_SIDE_EFFECTS (t) = 1;
6548 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6551 if (TARGET_SSE && cfun->va_list_fpr_size)
6553 type = TREE_TYPE (fpr);
6554 t = build2 (MODIFY_EXPR, type, fpr,
6555 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6556 TREE_SIDE_EFFECTS (t) = 1;
6557 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6560 /* Find the overflow area. */
6561 type = TREE_TYPE (ovf);
6562 t = make_tree (type, crtl->args.internal_arg_pointer);
6564 t = build2 (POINTER_PLUS_EXPR, type, t,
6565 size_int (words * UNITS_PER_WORD));
6566 t = build2 (MODIFY_EXPR, type, ovf, t);
6567 TREE_SIDE_EFFECTS (t) = 1;
6568 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6570 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6572 /* Find the register save area.
6573 Prologue of the function save it right above stack frame. */
6574 type = TREE_TYPE (sav);
6575 t = make_tree (type, frame_pointer_rtx);
6576 if (!ix86_varargs_gpr_size)
6577 t = build2 (POINTER_PLUS_EXPR, type, t,
6578 size_int (-8 * X86_64_REGPARM_MAX));
6579 t = build2 (MODIFY_EXPR, type, sav, t);
6580 TREE_SIDE_EFFECTS (t) = 1;
6581 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6585 /* Implement va_arg. */
6588 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6591 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6592 tree f_gpr, f_fpr, f_ovf, f_sav;
6593 tree gpr, fpr, ovf, sav, t;
6595 tree lab_false, lab_over = NULL_TREE;
6600 enum machine_mode nat_mode;
6603 /* Only 64bit target needs something special. */
6604 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6605 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6607 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6608 f_fpr = TREE_CHAIN (f_gpr);
6609 f_ovf = TREE_CHAIN (f_fpr);
6610 f_sav = TREE_CHAIN (f_ovf);
6612 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6613 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6614 valist = build_va_arg_indirect_ref (valist);
6615 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6616 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6617 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6619 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6621 type = build_pointer_type (type);
6622 size = int_size_in_bytes (type);
6623 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6625 nat_mode = type_natural_mode (type);
6634 /* Unnamed 256bit vector mode parameters are passed on stack. */
6635 if (ix86_cfun_abi () == SYSV_ABI)
6642 container = construct_container (nat_mode, TYPE_MODE (type),
6643 type, 0, X86_64_REGPARM_MAX,
6644 X86_64_SSE_REGPARM_MAX, intreg,
6649 /* Pull the value out of the saved registers. */
6651 addr = create_tmp_var (ptr_type_node, "addr");
6652 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6656 int needed_intregs, needed_sseregs;
6658 tree int_addr, sse_addr;
6660 lab_false = create_artificial_label ();
6661 lab_over = create_artificial_label ();
6663 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6665 need_temp = (!REG_P (container)
6666 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6667 || TYPE_ALIGN (type) > 128));
6669 /* In case we are passing structure, verify that it is consecutive block
6670 on the register save area. If not we need to do moves. */
6671 if (!need_temp && !REG_P (container))
6673 /* Verify that all registers are strictly consecutive */
6674 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6678 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6680 rtx slot = XVECEXP (container, 0, i);
6681 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6682 || INTVAL (XEXP (slot, 1)) != i * 16)
6690 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6692 rtx slot = XVECEXP (container, 0, i);
6693 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6694 || INTVAL (XEXP (slot, 1)) != i * 8)
6706 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6707 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6708 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6709 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6712 /* First ensure that we fit completely in registers. */
6715 t = build_int_cst (TREE_TYPE (gpr),
6716 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6717 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6718 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6719 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6720 gimplify_and_add (t, pre_p);
6724 t = build_int_cst (TREE_TYPE (fpr),
6725 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6726 + X86_64_REGPARM_MAX * 8);
6727 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6728 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6729 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6730 gimplify_and_add (t, pre_p);
6733 /* Compute index to start of area used for integer regs. */
6736 /* int_addr = gpr + sav; */
6737 t = fold_convert (sizetype, gpr);
6738 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6739 gimplify_assign (int_addr, t, pre_p);
6743 /* sse_addr = fpr + sav; */
6744 t = fold_convert (sizetype, fpr);
6745 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6746 gimplify_assign (sse_addr, t, pre_p);
6751 tree temp = create_tmp_var (type, "va_arg_tmp");
6754 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6755 gimplify_assign (addr, t, pre_p);
6757 for (i = 0; i < XVECLEN (container, 0); i++)
6759 rtx slot = XVECEXP (container, 0, i);
6760 rtx reg = XEXP (slot, 0);
6761 enum machine_mode mode = GET_MODE (reg);
6762 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6763 tree addr_type = build_pointer_type (piece_type);
6764 tree daddr_type = build_pointer_type_for_mode (piece_type,
6768 tree dest_addr, dest;
6770 if (SSE_REGNO_P (REGNO (reg)))
6772 src_addr = sse_addr;
6773 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6777 src_addr = int_addr;
6778 src_offset = REGNO (reg) * 8;
6780 src_addr = fold_convert (addr_type, src_addr);
6781 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6782 size_int (src_offset));
6783 src = build_va_arg_indirect_ref (src_addr);
6785 dest_addr = fold_convert (daddr_type, addr);
6786 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6787 size_int (INTVAL (XEXP (slot, 1))));
6788 dest = build_va_arg_indirect_ref (dest_addr);
6790 gimplify_assign (dest, src, pre_p);
6796 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6797 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6798 gimplify_assign (gpr, t, pre_p);
6803 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6804 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6805 gimplify_assign (fpr, t, pre_p);
6808 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6810 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6813 /* ... otherwise out of the overflow area. */
6815 /* When we align parameter on stack for caller, if the parameter
6816 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6817 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6818 here with caller. */
6819 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6820 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6821 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6823 /* Care for on-stack alignment if needed. */
6824 if (arg_boundary <= 64
6825 || integer_zerop (TYPE_SIZE (type)))
6829 HOST_WIDE_INT align = arg_boundary / 8;
6830 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6831 size_int (align - 1));
6832 t = fold_convert (sizetype, t);
6833 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6835 t = fold_convert (TREE_TYPE (ovf), t);
6837 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6838 gimplify_assign (addr, t, pre_p);
6840 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6841 size_int (rsize * UNITS_PER_WORD));
6842 gimplify_assign (unshare_expr (ovf), t, pre_p);
6845 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6847 ptrtype = build_pointer_type (type);
6848 addr = fold_convert (ptrtype, addr);
6851 addr = build_va_arg_indirect_ref (addr);
6852 return build_va_arg_indirect_ref (addr);
6855 /* Return nonzero if OPNUM's MEM should be matched
6856 in movabs* patterns. */
6859 ix86_check_movabs (rtx insn, int opnum)
6863 set = PATTERN (insn);
6864 if (GET_CODE (set) == PARALLEL)
6865 set = XVECEXP (set, 0, 0);
6866 gcc_assert (GET_CODE (set) == SET);
6867 mem = XEXP (set, opnum);
6868 while (GET_CODE (mem) == SUBREG)
6869 mem = SUBREG_REG (mem);
6870 gcc_assert (MEM_P (mem));
6871 return (volatile_ok || !MEM_VOLATILE_P (mem));
6874 /* Initialize the table of extra 80387 mathematical constants. */
6877 init_ext_80387_constants (void)
6879 static const char * cst[5] =
6881 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6882 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6883 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6884 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6885 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6889 for (i = 0; i < 5; i++)
6891 real_from_string (&ext_80387_constants_table[i], cst[i]);
6892 /* Ensure each constant is rounded to XFmode precision. */
6893 real_convert (&ext_80387_constants_table[i],
6894 XFmode, &ext_80387_constants_table[i]);
6897 ext_80387_constants_init = 1;
6900 /* Return true if the constant is something that can be loaded with
6901 a special instruction. */
6904 standard_80387_constant_p (rtx x)
6906 enum machine_mode mode = GET_MODE (x);
6910 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
6913 if (x == CONST0_RTX (mode))
6915 if (x == CONST1_RTX (mode))
6918 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6920 /* For XFmode constants, try to find a special 80387 instruction when
6921 optimizing for size or on those CPUs that benefit from them. */
6923 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
6927 if (! ext_80387_constants_init)
6928 init_ext_80387_constants ();
6930 for (i = 0; i < 5; i++)
6931 if (real_identical (&r, &ext_80387_constants_table[i]))
6935 /* Load of the constant -0.0 or -1.0 will be split as
6936 fldz;fchs or fld1;fchs sequence. */
6937 if (real_isnegzero (&r))
6939 if (real_identical (&r, &dconstm1))
6945 /* Return the opcode of the special instruction to be used to load
6949 standard_80387_constant_opcode (rtx x)
6951 switch (standard_80387_constant_p (x))
6975 /* Return the CONST_DOUBLE representing the 80387 constant that is
6976 loaded by the specified special instruction. The argument IDX
6977 matches the return value from standard_80387_constant_p. */
6980 standard_80387_constant_rtx (int idx)
6984 if (! ext_80387_constants_init)
6985 init_ext_80387_constants ();
7001 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7005 /* Return 1 if mode is a valid mode for sse. */
7007 standard_sse_mode_p (enum machine_mode mode)
7024 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7025 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7026 modes and AVX is enabled. */
7029 standard_sse_constant_p (rtx x)
7031 enum machine_mode mode = GET_MODE (x);
7033 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7035 if (vector_all_ones_operand (x, mode))
7037 if (standard_sse_mode_p (mode))
7038 return TARGET_SSE2 ? 2 : -2;
7039 else if (VALID_AVX256_REG_MODE (mode))
7040 return TARGET_AVX ? 3 : -3;
7046 /* Return the opcode of the special instruction to be used to load
7050 standard_sse_constant_opcode (rtx insn, rtx x)
7052 switch (standard_sse_constant_p (x))
7055 switch (get_attr_mode (insn))
7058 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7060 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7062 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7064 return "vxorps\t%x0, %x0, %x0";
7066 return "vxorpd\t%x0, %x0, %x0";
7068 return "vpxor\t%x0, %x0, %x0";
7074 switch (get_attr_mode (insn))
7079 return "vpcmpeqd\t%0, %0, %0";
7085 return "pcmpeqd\t%0, %0";
7090 /* Returns 1 if OP contains a symbol reference */
7093 symbolic_reference_mentioned_p (rtx op)
7098 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7101 fmt = GET_RTX_FORMAT (GET_CODE (op));
7102 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7108 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7109 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7113 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7120 /* Return 1 if it is appropriate to emit `ret' instructions in the
7121 body of a function. Do this only if the epilogue is simple, needing a
7122 couple of insns. Prior to reloading, we can't tell how many registers
7123 must be saved, so return 0 then. Return 0 if there is no frame
7124 marker to de-allocate. */
7127 ix86_can_use_return_insn_p (void)
7129 struct ix86_frame frame;
7131 if (! reload_completed || frame_pointer_needed)
7134 /* Don't allow more than 32 pop, since that's all we can do
7135 with one instruction. */
7136 if (crtl->args.pops_args
7137 && crtl->args.size >= 32768)
7140 ix86_compute_frame_layout (&frame);
7141 return frame.to_allocate == 0 && frame.nregs == 0;
7144 /* Value should be nonzero if functions must have frame pointers.
7145 Zero means the frame pointer need not be set up (and parms may
7146 be accessed via the stack pointer) in functions that seem suitable. */
7149 ix86_frame_pointer_required (void)
7151 /* If we accessed previous frames, then the generated code expects
7152 to be able to access the saved ebp value in our frame. */
7153 if (cfun->machine->accesses_prev_frame)
7156 /* Several x86 os'es need a frame pointer for other reasons,
7157 usually pertaining to setjmp. */
7158 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7161 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7162 the frame pointer by default. Turn it back on now if we've not
7163 got a leaf function. */
7164 if (TARGET_OMIT_LEAF_FRAME_POINTER
7165 && (!current_function_is_leaf
7166 || ix86_current_function_calls_tls_descriptor))
7175 /* Record that the current function accesses previous call frames. */
7178 ix86_setup_frame_addresses (void)
7180 cfun->machine->accesses_prev_frame = 1;
7183 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7184 # define USE_HIDDEN_LINKONCE 1
7186 # define USE_HIDDEN_LINKONCE 0
7189 static int pic_labels_used;
7191 /* Fills in the label name that should be used for a pc thunk for
7192 the given register. */
7195 get_pc_thunk_name (char name[32], unsigned int regno)
7197 gcc_assert (!TARGET_64BIT);
7199 if (USE_HIDDEN_LINKONCE)
7200 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7202 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7206 /* This function generates code for -fpic that loads %ebx with
7207 the return address of the caller and then returns. */
7210 ix86_file_end (void)
7215 for (regno = 0; regno < 8; ++regno)
7219 if (! ((pic_labels_used >> regno) & 1))
7222 get_pc_thunk_name (name, regno);
7227 switch_to_section (darwin_sections[text_coal_section]);
7228 fputs ("\t.weak_definition\t", asm_out_file);
7229 assemble_name (asm_out_file, name);
7230 fputs ("\n\t.private_extern\t", asm_out_file);
7231 assemble_name (asm_out_file, name);
7232 fputs ("\n", asm_out_file);
7233 ASM_OUTPUT_LABEL (asm_out_file, name);
7237 if (USE_HIDDEN_LINKONCE)
7241 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7243 TREE_PUBLIC (decl) = 1;
7244 TREE_STATIC (decl) = 1;
7245 DECL_ONE_ONLY (decl) = 1;
7247 (*targetm.asm_out.unique_section) (decl, 0);
7248 switch_to_section (get_named_section (decl, NULL, 0));
7250 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7251 fputs ("\t.hidden\t", asm_out_file);
7252 assemble_name (asm_out_file, name);
7253 fputc ('\n', asm_out_file);
7254 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7258 switch_to_section (text_section);
7259 ASM_OUTPUT_LABEL (asm_out_file, name);
7262 xops[0] = gen_rtx_REG (Pmode, regno);
7263 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7264 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7265 output_asm_insn ("ret", xops);
7268 if (NEED_INDICATE_EXEC_STACK)
7269 file_end_indicate_exec_stack ();
7272 /* Emit code for the SET_GOT patterns. */
7275 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7281 if (TARGET_VXWORKS_RTP && flag_pic)
7283 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7284 xops[2] = gen_rtx_MEM (Pmode,
7285 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7286 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7288 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7289 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7290 an unadorned address. */
7291 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7292 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7293 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7297 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7299 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7301 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7304 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7306 output_asm_insn ("call\t%a2", xops);
7309 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7310 is what will be referenced by the Mach-O PIC subsystem. */
7312 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7315 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7316 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7319 output_asm_insn ("pop%z0\t%0", xops);
7324 get_pc_thunk_name (name, REGNO (dest));
7325 pic_labels_used |= 1 << REGNO (dest);
7327 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7328 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7329 output_asm_insn ("call\t%X2", xops);
7330 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7331 is what will be referenced by the Mach-O PIC subsystem. */
7334 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7336 targetm.asm_out.internal_label (asm_out_file, "L",
7337 CODE_LABEL_NUMBER (label));
7344 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7345 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7347 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7352 /* Generate an "push" pattern for input ARG. */
7357 return gen_rtx_SET (VOIDmode,
7359 gen_rtx_PRE_DEC (Pmode,
7360 stack_pointer_rtx)),
7364 /* Return >= 0 if there is an unused call-clobbered register available
7365 for the entire function. */
7368 ix86_select_alt_pic_regnum (void)
7370 if (current_function_is_leaf && !crtl->profile
7371 && !ix86_current_function_calls_tls_descriptor)
7374 /* Can't use the same register for both PIC and DRAP. */
7376 drap = REGNO (crtl->drap_reg);
7379 for (i = 2; i >= 0; --i)
7380 if (i != drap && !df_regs_ever_live_p (i))
7384 return INVALID_REGNUM;
7387 /* Return 1 if we need to save REGNO. */
7389 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7391 if (pic_offset_table_rtx
7392 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7393 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7395 || crtl->calls_eh_return
7396 || crtl->uses_const_pool))
7398 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7403 if (crtl->calls_eh_return && maybe_eh_return)
7408 unsigned test = EH_RETURN_DATA_REGNO (i);
7409 if (test == INVALID_REGNUM)
7417 && regno == REGNO (crtl->drap_reg))
7420 return (df_regs_ever_live_p (regno)
7421 && !call_used_regs[regno]
7422 && !fixed_regs[regno]
7423 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7426 /* Return number of saved general prupose registers. */
7429 ix86_nsaved_regs (void)
7434 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7435 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7440 /* Return number of saved SSE registrers. */
7443 ix86_nsaved_sseregs (void)
7448 if (ix86_cfun_abi () != MS_ABI)
7450 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7451 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7456 /* Given FROM and TO register numbers, say whether this elimination is
7457 allowed. If stack alignment is needed, we can only replace argument
7458 pointer with hard frame pointer, or replace frame pointer with stack
7459 pointer. Otherwise, frame pointer elimination is automatically
7460 handled and all other eliminations are valid. */
7463 ix86_can_eliminate (int from, int to)
7465 if (stack_realign_fp)
7466 return ((from == ARG_POINTER_REGNUM
7467 && to == HARD_FRAME_POINTER_REGNUM)
7468 || (from == FRAME_POINTER_REGNUM
7469 && to == STACK_POINTER_REGNUM));
7471 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7474 /* Return the offset between two registers, one to be eliminated, and the other
7475 its replacement, at the start of a routine. */
7478 ix86_initial_elimination_offset (int from, int to)
7480 struct ix86_frame frame;
7481 ix86_compute_frame_layout (&frame);
7483 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7484 return frame.hard_frame_pointer_offset;
7485 else if (from == FRAME_POINTER_REGNUM
7486 && to == HARD_FRAME_POINTER_REGNUM)
7487 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7490 gcc_assert (to == STACK_POINTER_REGNUM);
7492 if (from == ARG_POINTER_REGNUM)
7493 return frame.stack_pointer_offset;
7495 gcc_assert (from == FRAME_POINTER_REGNUM);
7496 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7500 /* Fill structure ix86_frame about frame of currently computed function. */
7503 ix86_compute_frame_layout (struct ix86_frame *frame)
7505 HOST_WIDE_INT total_size;
7506 unsigned int stack_alignment_needed;
7507 HOST_WIDE_INT offset;
7508 unsigned int preferred_alignment;
7509 HOST_WIDE_INT size = get_frame_size ();
7511 frame->nregs = ix86_nsaved_regs ();
7512 frame->nsseregs = ix86_nsaved_sseregs ();
7515 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7516 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7518 /* MS ABI seem to require stack alignment to be always 16 except for function
7520 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7522 preferred_alignment = 16;
7523 stack_alignment_needed = 16;
7524 crtl->preferred_stack_boundary = 128;
7525 crtl->stack_alignment_needed = 128;
7528 gcc_assert (!size || stack_alignment_needed);
7529 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7530 gcc_assert (preferred_alignment <= stack_alignment_needed);
7532 /* During reload iteration the amount of registers saved can change.
7533 Recompute the value as needed. Do not recompute when amount of registers
7534 didn't change as reload does multiple calls to the function and does not
7535 expect the decision to change within single iteration. */
7536 if (!optimize_function_for_size_p (cfun)
7537 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7539 int count = frame->nregs;
7541 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7542 /* The fast prologue uses move instead of push to save registers. This
7543 is significantly longer, but also executes faster as modern hardware
7544 can execute the moves in parallel, but can't do that for push/pop.
7546 Be careful about choosing what prologue to emit: When function takes
7547 many instructions to execute we may use slow version as well as in
7548 case function is known to be outside hot spot (this is known with
7549 feedback only). Weight the size of function by number of registers
7550 to save as it is cheap to use one or two push instructions but very
7551 slow to use many of them. */
7553 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7554 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7555 || (flag_branch_probabilities
7556 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7557 cfun->machine->use_fast_prologue_epilogue = false;
7559 cfun->machine->use_fast_prologue_epilogue
7560 = !expensive_function_p (count);
7562 if (TARGET_PROLOGUE_USING_MOVE
7563 && cfun->machine->use_fast_prologue_epilogue)
7564 frame->save_regs_using_mov = true;
7566 frame->save_regs_using_mov = false;
7569 /* Skip return address and saved base pointer. */
7570 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7572 frame->hard_frame_pointer_offset = offset;
7574 /* Set offset to aligned because the realigned frame starts from
7576 if (stack_realign_fp)
7577 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7579 /* Register save area */
7580 offset += frame->nregs * UNITS_PER_WORD;
7582 /* Align SSE reg save area. */
7583 if (frame->nsseregs)
7584 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7586 frame->padding0 = 0;
7588 /* SSE register save area. */
7589 offset += frame->padding0 + frame->nsseregs * 16;
7592 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7593 offset += frame->va_arg_size;
7595 /* Align start of frame for local function. */
7596 frame->padding1 = ((offset + stack_alignment_needed - 1)
7597 & -stack_alignment_needed) - offset;
7599 offset += frame->padding1;
7601 /* Frame pointer points here. */
7602 frame->frame_pointer_offset = offset;
7606 /* Add outgoing arguments area. Can be skipped if we eliminated
7607 all the function calls as dead code.
7608 Skipping is however impossible when function calls alloca. Alloca
7609 expander assumes that last crtl->outgoing_args_size
7610 of stack frame are unused. */
7611 if (ACCUMULATE_OUTGOING_ARGS
7612 && (!current_function_is_leaf || cfun->calls_alloca
7613 || ix86_current_function_calls_tls_descriptor))
7615 offset += crtl->outgoing_args_size;
7616 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7619 frame->outgoing_arguments_size = 0;
7621 /* Align stack boundary. Only needed if we're calling another function
7623 if (!current_function_is_leaf || cfun->calls_alloca
7624 || ix86_current_function_calls_tls_descriptor)
7625 frame->padding2 = ((offset + preferred_alignment - 1)
7626 & -preferred_alignment) - offset;
7628 frame->padding2 = 0;
7630 offset += frame->padding2;
7632 /* We've reached end of stack frame. */
7633 frame->stack_pointer_offset = offset;
7635 /* Size prologue needs to allocate. */
7636 frame->to_allocate =
7637 (size + frame->padding1 + frame->padding2
7638 + frame->outgoing_arguments_size + frame->va_arg_size);
7640 if ((!frame->to_allocate && frame->nregs <= 1)
7641 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7642 frame->save_regs_using_mov = false;
7644 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7645 && current_function_is_leaf
7646 && !ix86_current_function_calls_tls_descriptor)
7648 frame->red_zone_size = frame->to_allocate;
7649 if (frame->save_regs_using_mov)
7650 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7651 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7652 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7655 frame->red_zone_size = 0;
7656 frame->to_allocate -= frame->red_zone_size;
7657 frame->stack_pointer_offset -= frame->red_zone_size;
7659 fprintf (stderr, "\n");
7660 fprintf (stderr, "size: %ld\n", (long)size);
7661 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7662 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7663 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7664 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7665 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7666 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7667 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7668 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7669 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7670 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7671 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7672 (long)frame->hard_frame_pointer_offset);
7673 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7674 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7675 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7676 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7680 /* Emit code to save registers in the prologue. */
7683 ix86_emit_save_regs (void)
7688 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7689 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7691 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7692 RTX_FRAME_RELATED_P (insn) = 1;
7696 /* Emit code to save registers using MOV insns. First register
7697 is restored from POINTER + OFFSET. */
7699 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7704 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7705 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7707 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7709 gen_rtx_REG (Pmode, regno));
7710 RTX_FRAME_RELATED_P (insn) = 1;
7711 offset += UNITS_PER_WORD;
7715 /* Emit code to save registers using MOV insns. First register
7716 is restored from POINTER + OFFSET. */
7718 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7724 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7725 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7727 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7728 set_mem_align (mem, 128);
7729 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7730 RTX_FRAME_RELATED_P (insn) = 1;
7735 /* Expand prologue or epilogue stack adjustment.
7736 The pattern exist to put a dependency on all ebp-based memory accesses.
7737 STYLE should be negative if instructions should be marked as frame related,
7738 zero if %r11 register is live and cannot be freely used and positive
7742 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7747 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7748 else if (x86_64_immediate_operand (offset, DImode))
7749 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7753 /* r11 is used by indirect sibcall return as well, set before the
7754 epilogue and used after the epilogue. ATM indirect sibcall
7755 shouldn't be used together with huge frame sizes in one
7756 function because of the frame_size check in sibcall.c. */
7758 r11 = gen_rtx_REG (DImode, R11_REG);
7759 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7761 RTX_FRAME_RELATED_P (insn) = 1;
7762 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7766 RTX_FRAME_RELATED_P (insn) = 1;
7769 /* Find an available register to be used as dynamic realign argument
7770 pointer regsiter. Such a register will be written in prologue and
7771 used in begin of body, so it must not be
7772 1. parameter passing register.
7774 We reuse static-chain register if it is available. Otherwise, we
7775 use DI for i386 and R13 for x86-64. We chose R13 since it has
7778 Return: the regno of chosen register. */
7781 find_drap_reg (void)
7783 tree decl = cfun->decl;
7787 /* Use R13 for nested function or function need static chain.
7788 Since function with tail call may use any caller-saved
7789 registers in epilogue, DRAP must not use caller-saved
7790 register in such case. */
7791 if ((decl_function_context (decl)
7792 && !DECL_NO_STATIC_CHAIN (decl))
7793 || crtl->tail_call_emit)
7800 /* Use DI for nested function or function need static chain.
7801 Since function with tail call may use any caller-saved
7802 registers in epilogue, DRAP must not use caller-saved
7803 register in such case. */
7804 if ((decl_function_context (decl)
7805 && !DECL_NO_STATIC_CHAIN (decl))
7806 || crtl->tail_call_emit)
7809 /* Reuse static chain register if it isn't used for parameter
7811 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7812 && !lookup_attribute ("fastcall",
7813 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7820 /* Update incoming stack boundary and estimated stack alignment. */
7823 ix86_update_stack_boundary (void)
7825 /* Prefer the one specified at command line. */
7826 ix86_incoming_stack_boundary
7827 = (ix86_user_incoming_stack_boundary
7828 ? ix86_user_incoming_stack_boundary
7829 : ix86_default_incoming_stack_boundary);
7831 /* Incoming stack alignment can be changed on individual functions
7832 via force_align_arg_pointer attribute. We use the smallest
7833 incoming stack boundary. */
7834 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7835 && lookup_attribute (ix86_force_align_arg_pointer_string,
7836 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7837 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7839 /* The incoming stack frame has to be aligned at least at
7840 parm_stack_boundary. */
7841 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
7842 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
7844 /* Stack at entrance of main is aligned by runtime. We use the
7845 smallest incoming stack boundary. */
7846 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7847 && DECL_NAME (current_function_decl)
7848 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7849 && DECL_FILE_SCOPE_P (current_function_decl))
7850 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7852 /* x86_64 vararg needs 16byte stack alignment for register save
7856 && crtl->stack_alignment_estimated < 128)
7857 crtl->stack_alignment_estimated = 128;
7860 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7861 needed or an rtx for DRAP otherwise. */
7864 ix86_get_drap_rtx (void)
7866 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7867 crtl->need_drap = true;
7869 if (stack_realign_drap)
7871 /* Assign DRAP to vDRAP and returns vDRAP */
7872 unsigned int regno = find_drap_reg ();
7877 arg_ptr = gen_rtx_REG (Pmode, regno);
7878 crtl->drap_reg = arg_ptr;
7881 drap_vreg = copy_to_reg (arg_ptr);
7885 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
7886 RTX_FRAME_RELATED_P (insn) = 1;
7893 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7896 ix86_internal_arg_pointer (void)
7898 return virtual_incoming_args_rtx;
7901 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7902 This is called from dwarf2out.c to emit call frame instructions
7903 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7905 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
7907 rtx unspec = SET_SRC (pattern);
7908 gcc_assert (GET_CODE (unspec) == UNSPEC);
7912 case UNSPEC_REG_SAVE:
7913 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
7914 SET_DEST (pattern));
7916 case UNSPEC_DEF_CFA:
7917 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
7918 INTVAL (XVECEXP (unspec, 0, 0)));
7925 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
7926 to be generated in correct form. */
7928 ix86_finalize_stack_realign_flags (void)
7930 /* Check if stack realign is really needed after reload, and
7931 stores result in cfun */
7932 unsigned int incoming_stack_boundary
7933 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
7934 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
7935 unsigned int stack_realign = (incoming_stack_boundary
7936 < (current_function_is_leaf
7937 ? crtl->max_used_stack_slot_alignment
7938 : crtl->stack_alignment_needed));
7940 if (crtl->stack_realign_finalized)
7942 /* After stack_realign_needed is finalized, we can't no longer
7944 gcc_assert (crtl->stack_realign_needed == stack_realign);
7948 crtl->stack_realign_needed = stack_realign;
7949 crtl->stack_realign_finalized = true;
7953 /* Expand the prologue into a bunch of separate insns. */
7956 ix86_expand_prologue (void)
7960 struct ix86_frame frame;
7961 HOST_WIDE_INT allocate;
7963 ix86_finalize_stack_realign_flags ();
7965 /* DRAP should not coexist with stack_realign_fp */
7966 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
7968 ix86_compute_frame_layout (&frame);
7970 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
7971 of DRAP is needed and stack realignment is really needed after reload */
7972 if (crtl->drap_reg && crtl->stack_realign_needed)
7975 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
7976 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
7977 ? 0 : UNITS_PER_WORD);
7979 gcc_assert (stack_realign_drap);
7981 /* Grab the argument pointer. */
7982 x = plus_constant (stack_pointer_rtx,
7983 (UNITS_PER_WORD + param_ptr_offset));
7986 /* Only need to push parameter pointer reg if it is caller
7988 if (!call_used_regs[REGNO (crtl->drap_reg)])
7990 /* Push arg pointer reg */
7991 insn = emit_insn (gen_push (y));
7992 RTX_FRAME_RELATED_P (insn) = 1;
7995 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
7996 RTX_FRAME_RELATED_P (insn) = 1;
7998 /* Align the stack. */
7999 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8001 GEN_INT (-align_bytes)));
8002 RTX_FRAME_RELATED_P (insn) = 1;
8004 /* Replicate the return address on the stack so that return
8005 address can be reached via (argp - 1) slot. This is needed
8006 to implement macro RETURN_ADDR_RTX and intrinsic function
8007 expand_builtin_return_addr etc. */
8009 x = gen_frame_mem (Pmode,
8010 plus_constant (x, -UNITS_PER_WORD));
8011 insn = emit_insn (gen_push (x));
8012 RTX_FRAME_RELATED_P (insn) = 1;
8015 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8016 slower on all targets. Also sdb doesn't like it. */
8018 if (frame_pointer_needed)
8020 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8021 RTX_FRAME_RELATED_P (insn) = 1;
8023 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8024 RTX_FRAME_RELATED_P (insn) = 1;
8027 if (stack_realign_fp)
8029 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8030 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8032 /* Align the stack. */
8033 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8035 GEN_INT (-align_bytes)));
8036 RTX_FRAME_RELATED_P (insn) = 1;
8039 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8041 if (!frame.save_regs_using_mov)
8042 ix86_emit_save_regs ();
8044 allocate += frame.nregs * UNITS_PER_WORD;
8046 /* When using red zone we may start register saving before allocating
8047 the stack frame saving one cycle of the prologue. However I will
8048 avoid doing this if I am going to have to probe the stack since
8049 at least on x86_64 the stack probe can turn into a call that clobbers
8050 a red zone location */
8051 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8052 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8053 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8054 && !crtl->stack_realign_needed)
8055 ? hard_frame_pointer_rtx
8056 : stack_pointer_rtx,
8057 -frame.nregs * UNITS_PER_WORD);
8061 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8062 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8063 GEN_INT (-allocate), -1);
8066 /* Only valid for Win32. */
8067 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8071 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8073 if (cfun->machine->call_abi == MS_ABI)
8076 eax_live = ix86_eax_live_at_start_p ();
8080 emit_insn (gen_push (eax));
8081 allocate -= UNITS_PER_WORD;
8084 emit_move_insn (eax, GEN_INT (allocate));
8087 insn = gen_allocate_stack_worker_64 (eax, eax);
8089 insn = gen_allocate_stack_worker_32 (eax, eax);
8090 insn = emit_insn (insn);
8091 RTX_FRAME_RELATED_P (insn) = 1;
8092 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8093 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8094 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8095 t, REG_NOTES (insn));
8099 if (frame_pointer_needed)
8100 t = plus_constant (hard_frame_pointer_rtx,
8103 - frame.nregs * UNITS_PER_WORD);
8105 t = plus_constant (stack_pointer_rtx, allocate);
8106 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8110 if (frame.save_regs_using_mov
8111 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8112 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8114 if (!frame_pointer_needed
8115 || !frame.to_allocate
8116 || crtl->stack_realign_needed)
8117 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8119 + frame.nsseregs * 16 + frame.padding0);
8121 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8122 -frame.nregs * UNITS_PER_WORD);
8124 if (!frame_pointer_needed
8125 || !frame.to_allocate
8126 || crtl->stack_realign_needed)
8127 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8130 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8131 - frame.nregs * UNITS_PER_WORD
8132 - frame.nsseregs * 16
8135 pic_reg_used = false;
8136 if (pic_offset_table_rtx
8137 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8140 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8142 if (alt_pic_reg_used != INVALID_REGNUM)
8143 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8145 pic_reg_used = true;
8152 if (ix86_cmodel == CM_LARGE_PIC)
8154 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8155 rtx label = gen_label_rtx ();
8157 LABEL_PRESERVE_P (label) = 1;
8158 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8159 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8160 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8161 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8162 pic_offset_table_rtx, tmp_reg));
8165 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8168 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8171 /* Prevent function calls from being scheduled before the call to mcount.
8172 In the pic_reg_used case, make sure that the got load isn't deleted. */
8176 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8177 emit_insn (gen_blockage ());
8180 if (crtl->drap_reg && !crtl->stack_realign_needed)
8182 /* vDRAP is setup but after reload it turns out stack realign
8183 isn't necessary, here we will emit prologue to setup DRAP
8184 without stack realign adjustment */
8185 int drap_bp_offset = UNITS_PER_WORD * 2;
8186 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8187 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8190 /* Emit cld instruction if stringops are used in the function. */
8191 if (TARGET_CLD && ix86_current_function_needs_cld)
8192 emit_insn (gen_cld ());
8195 /* Emit code to restore saved registers using MOV insns. First register
8196 is restored from POINTER + OFFSET. */
8198 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8199 int maybe_eh_return)
8202 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8204 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8205 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8207 /* Ensure that adjust_address won't be forced to produce pointer
8208 out of range allowed by x86-64 instruction set. */
8209 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8213 r11 = gen_rtx_REG (DImode, R11_REG);
8214 emit_move_insn (r11, GEN_INT (offset));
8215 emit_insn (gen_adddi3 (r11, r11, pointer));
8216 base_address = gen_rtx_MEM (Pmode, r11);
8219 emit_move_insn (gen_rtx_REG (Pmode, regno),
8220 adjust_address (base_address, Pmode, offset));
8221 offset += UNITS_PER_WORD;
8225 /* Emit code to restore saved registers using MOV insns. First register
8226 is restored from POINTER + OFFSET. */
8228 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8229 int maybe_eh_return)
8232 rtx base_address = gen_rtx_MEM (TImode, pointer);
8235 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8236 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8238 /* Ensure that adjust_address won't be forced to produce pointer
8239 out of range allowed by x86-64 instruction set. */
8240 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8244 r11 = gen_rtx_REG (DImode, R11_REG);
8245 emit_move_insn (r11, GEN_INT (offset));
8246 emit_insn (gen_adddi3 (r11, r11, pointer));
8247 base_address = gen_rtx_MEM (TImode, r11);
8250 mem = adjust_address (base_address, TImode, offset);
8251 set_mem_align (mem, 128);
8252 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8257 /* Restore function stack, frame, and registers. */
8260 ix86_expand_epilogue (int style)
8264 struct ix86_frame frame;
8265 HOST_WIDE_INT offset;
8267 ix86_finalize_stack_realign_flags ();
8269 /* When stack is realigned, SP must be valid. */
8270 sp_valid = (!frame_pointer_needed
8271 || current_function_sp_is_unchanging
8272 || stack_realign_fp);
8274 ix86_compute_frame_layout (&frame);
8276 /* Calculate start of saved registers relative to ebp. Special care
8277 must be taken for the normal return case of a function using
8278 eh_return: the eax and edx registers are marked as saved, but not
8279 restored along this path. */
8280 offset = frame.nregs;
8281 if (crtl->calls_eh_return && style != 2)
8283 offset *= -UNITS_PER_WORD;
8284 offset -= frame.nsseregs * 16 + frame.padding0;
8286 /* If we're only restoring one register and sp is not valid then
8287 using a move instruction to restore the register since it's
8288 less work than reloading sp and popping the register.
8290 The default code result in stack adjustment using add/lea instruction,
8291 while this code results in LEAVE instruction (or discrete equivalent),
8292 so it is profitable in some other cases as well. Especially when there
8293 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8294 and there is exactly one register to pop. This heuristic may need some
8295 tuning in future. */
8296 if ((!sp_valid && frame.nregs <= 1)
8297 || (TARGET_EPILOGUE_USING_MOVE
8298 && cfun->machine->use_fast_prologue_epilogue
8299 && (frame.nregs > 1 || frame.to_allocate))
8300 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
8301 || (frame_pointer_needed && TARGET_USE_LEAVE
8302 && cfun->machine->use_fast_prologue_epilogue
8303 && frame.nregs == 1)
8304 || crtl->calls_eh_return)
8306 /* Restore registers. We can use ebp or esp to address the memory
8307 locations. If both are available, default to ebp, since offsets
8308 are known to be small. Only exception is esp pointing directly
8309 to the end of block of saved registers, where we may simplify
8312 If we are realigning stack with bp and sp, regs restore can't
8313 be addressed by bp. sp must be used instead. */
8315 if (!frame_pointer_needed
8316 || (sp_valid && !frame.to_allocate)
8317 || stack_realign_fp)
8319 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8320 frame.to_allocate, style == 2);
8321 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8323 + frame.nsseregs * 16
8324 + frame.padding0, style == 2);
8328 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8329 offset, style == 2);
8330 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8332 + frame.nsseregs * 16
8333 + frame.padding0, style == 2);
8336 /* eh_return epilogues need %ecx added to the stack pointer. */
8339 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8341 /* Stack align doesn't work with eh_return. */
8342 gcc_assert (!crtl->stack_realign_needed);
8344 if (frame_pointer_needed)
8346 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8347 tmp = plus_constant (tmp, UNITS_PER_WORD);
8348 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8350 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8351 emit_move_insn (hard_frame_pointer_rtx, tmp);
8353 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8358 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8359 tmp = plus_constant (tmp, (frame.to_allocate
8360 + frame.nregs * UNITS_PER_WORD
8361 + frame.nsseregs * 16
8363 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8366 else if (!frame_pointer_needed)
8367 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8368 GEN_INT (frame.to_allocate
8369 + frame.nregs * UNITS_PER_WORD
8370 + frame.nsseregs * 16
8373 /* If not an i386, mov & pop is faster than "leave". */
8374 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8375 || !cfun->machine->use_fast_prologue_epilogue)
8376 emit_insn ((*ix86_gen_leave) ());
8379 pro_epilogue_adjust_stack (stack_pointer_rtx,
8380 hard_frame_pointer_rtx,
8383 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8388 /* First step is to deallocate the stack frame so that we can
8391 If we realign stack with frame pointer, then stack pointer
8392 won't be able to recover via lea $offset(%bp), %sp, because
8393 there is a padding area between bp and sp for realign.
8394 "add $to_allocate, %sp" must be used instead. */
8397 gcc_assert (frame_pointer_needed);
8398 gcc_assert (!stack_realign_fp);
8399 pro_epilogue_adjust_stack (stack_pointer_rtx,
8400 hard_frame_pointer_rtx,
8401 GEN_INT (offset), style);
8402 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8403 frame.to_allocate, style == 2);
8404 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8405 GEN_INT (frame.nsseregs * 16), style);
8407 else if (frame.to_allocate || frame.nsseregs)
8409 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8412 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8413 GEN_INT (frame.to_allocate
8414 + frame.nsseregs * 16
8415 + frame.padding0), style);
8418 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8419 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8420 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8421 if (frame_pointer_needed)
8423 /* Leave results in shorter dependency chains on CPUs that are
8424 able to grok it fast. */
8425 if (TARGET_USE_LEAVE)
8426 emit_insn ((*ix86_gen_leave) ());
8429 /* For stack realigned really happens, recover stack
8430 pointer to hard frame pointer is a must, if not using
8432 if (stack_realign_fp)
8433 pro_epilogue_adjust_stack (stack_pointer_rtx,
8434 hard_frame_pointer_rtx,
8436 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8441 if (crtl->drap_reg && crtl->stack_realign_needed)
8443 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8444 ? 0 : UNITS_PER_WORD);
8445 gcc_assert (stack_realign_drap);
8446 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8448 GEN_INT (-(UNITS_PER_WORD
8449 + param_ptr_offset))));
8450 if (!call_used_regs[REGNO (crtl->drap_reg)])
8451 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8455 /* Sibcall epilogues don't want a return instruction. */
8459 if (crtl->args.pops_args && crtl->args.size)
8461 rtx popc = GEN_INT (crtl->args.pops_args);
8463 /* i386 can only pop 64K bytes. If asked to pop more, pop
8464 return address, do explicit add, and jump indirectly to the
8467 if (crtl->args.pops_args >= 65536)
8469 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8471 /* There is no "pascal" calling convention in any 64bit ABI. */
8472 gcc_assert (!TARGET_64BIT);
8474 emit_insn (gen_popsi1 (ecx));
8475 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8476 emit_jump_insn (gen_return_indirect_internal (ecx));
8479 emit_jump_insn (gen_return_pop_internal (popc));
8482 emit_jump_insn (gen_return_internal ());
8485 /* Reset from the function's potential modifications. */
8488 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8489 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8491 if (pic_offset_table_rtx)
8492 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8494 /* Mach-O doesn't support labels at the end of objects, so if
8495 it looks like we might want one, insert a NOP. */
8497 rtx insn = get_last_insn ();
8500 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8501 insn = PREV_INSN (insn);
8505 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8506 fputs ("\tnop\n", file);
8512 /* Extract the parts of an RTL expression that is a valid memory address
8513 for an instruction. Return 0 if the structure of the address is
8514 grossly off. Return -1 if the address contains ASHIFT, so it is not
8515 strictly valid, but still used for computing length of lea instruction. */
8518 ix86_decompose_address (rtx addr, struct ix86_address *out)
8520 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8521 rtx base_reg, index_reg;
8522 HOST_WIDE_INT scale = 1;
8523 rtx scale_rtx = NULL_RTX;
8525 enum ix86_address_seg seg = SEG_DEFAULT;
8527 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8529 else if (GET_CODE (addr) == PLUS)
8539 addends[n++] = XEXP (op, 1);
8542 while (GET_CODE (op) == PLUS);
8547 for (i = n; i >= 0; --i)
8550 switch (GET_CODE (op))
8555 index = XEXP (op, 0);
8556 scale_rtx = XEXP (op, 1);
8560 if (XINT (op, 1) == UNSPEC_TP
8561 && TARGET_TLS_DIRECT_SEG_REFS
8562 && seg == SEG_DEFAULT)
8563 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8592 else if (GET_CODE (addr) == MULT)
8594 index = XEXP (addr, 0); /* index*scale */
8595 scale_rtx = XEXP (addr, 1);
8597 else if (GET_CODE (addr) == ASHIFT)
8601 /* We're called for lea too, which implements ashift on occasion. */
8602 index = XEXP (addr, 0);
8603 tmp = XEXP (addr, 1);
8604 if (!CONST_INT_P (tmp))
8606 scale = INTVAL (tmp);
8607 if ((unsigned HOST_WIDE_INT) scale > 3)
8613 disp = addr; /* displacement */
8615 /* Extract the integral value of scale. */
8618 if (!CONST_INT_P (scale_rtx))
8620 scale = INTVAL (scale_rtx);
8623 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8624 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8626 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8627 if (base_reg && index_reg && scale == 1
8628 && (index_reg == arg_pointer_rtx
8629 || index_reg == frame_pointer_rtx
8630 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8633 tmp = base, base = index, index = tmp;
8634 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8637 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8638 if ((base_reg == hard_frame_pointer_rtx
8639 || base_reg == frame_pointer_rtx
8640 || base_reg == arg_pointer_rtx) && !disp)
8643 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8644 Avoid this by transforming to [%esi+0].
8645 Reload calls address legitimization without cfun defined, so we need
8646 to test cfun for being non-NULL. */
8647 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8648 && base_reg && !index_reg && !disp
8650 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8653 /* Special case: encode reg+reg instead of reg*2. */
8654 if (!base && index && scale && scale == 2)
8655 base = index, base_reg = index_reg, scale = 1;
8657 /* Special case: scaling cannot be encoded without base or displacement. */
8658 if (!base && !disp && index && scale != 1)
8670 /* Return cost of the memory address x.
8671 For i386, it is better to use a complex address than let gcc copy
8672 the address into a reg and make a new pseudo. But not if the address
8673 requires to two regs - that would mean more pseudos with longer
8676 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8678 struct ix86_address parts;
8680 int ok = ix86_decompose_address (x, &parts);
8684 if (parts.base && GET_CODE (parts.base) == SUBREG)
8685 parts.base = SUBREG_REG (parts.base);
8686 if (parts.index && GET_CODE (parts.index) == SUBREG)
8687 parts.index = SUBREG_REG (parts.index);
8689 /* Attempt to minimize number of registers in the address. */
8691 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8693 && (!REG_P (parts.index)
8694 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8698 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8700 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8701 && parts.base != parts.index)
8704 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8705 since it's predecode logic can't detect the length of instructions
8706 and it degenerates to vector decoded. Increase cost of such
8707 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8708 to split such addresses or even refuse such addresses at all.
8710 Following addressing modes are affected:
8715 The first and last case may be avoidable by explicitly coding the zero in
8716 memory address, but I don't have AMD-K6 machine handy to check this
8720 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8721 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8722 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8728 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8729 this is used for to form addresses to local data when -fPIC is in
8733 darwin_local_data_pic (rtx disp)
8735 return (GET_CODE (disp) == UNSPEC
8736 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8739 /* Determine if a given RTX is a valid constant. We already know this
8740 satisfies CONSTANT_P. */
8743 legitimate_constant_p (rtx x)
8745 switch (GET_CODE (x))
8750 if (GET_CODE (x) == PLUS)
8752 if (!CONST_INT_P (XEXP (x, 1)))
8757 if (TARGET_MACHO && darwin_local_data_pic (x))
8760 /* Only some unspecs are valid as "constants". */
8761 if (GET_CODE (x) == UNSPEC)
8762 switch (XINT (x, 1))
8767 return TARGET_64BIT;
8770 x = XVECEXP (x, 0, 0);
8771 return (GET_CODE (x) == SYMBOL_REF
8772 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8774 x = XVECEXP (x, 0, 0);
8775 return (GET_CODE (x) == SYMBOL_REF
8776 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8781 /* We must have drilled down to a symbol. */
8782 if (GET_CODE (x) == LABEL_REF)
8784 if (GET_CODE (x) != SYMBOL_REF)
8789 /* TLS symbols are never valid. */
8790 if (SYMBOL_REF_TLS_MODEL (x))
8793 /* DLLIMPORT symbols are never valid. */
8794 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8795 && SYMBOL_REF_DLLIMPORT_P (x))
8800 if (GET_MODE (x) == TImode
8801 && x != CONST0_RTX (TImode)
8807 if (x == CONST0_RTX (GET_MODE (x)))
8815 /* Otherwise we handle everything else in the move patterns. */
8819 /* Determine if it's legal to put X into the constant pool. This
8820 is not possible for the address of thread-local symbols, which
8821 is checked above. */
8824 ix86_cannot_force_const_mem (rtx x)
8826 /* We can always put integral constants and vectors in memory. */
8827 switch (GET_CODE (x))
8837 return !legitimate_constant_p (x);
8840 /* Determine if a given RTX is a valid constant address. */
8843 constant_address_p (rtx x)
8845 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8848 /* Nonzero if the constant value X is a legitimate general operand
8849 when generating PIC code. It is given that flag_pic is on and
8850 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8853 legitimate_pic_operand_p (rtx x)
8857 switch (GET_CODE (x))
8860 inner = XEXP (x, 0);
8861 if (GET_CODE (inner) == PLUS
8862 && CONST_INT_P (XEXP (inner, 1)))
8863 inner = XEXP (inner, 0);
8865 /* Only some unspecs are valid as "constants". */
8866 if (GET_CODE (inner) == UNSPEC)
8867 switch (XINT (inner, 1))
8872 return TARGET_64BIT;
8874 x = XVECEXP (inner, 0, 0);
8875 return (GET_CODE (x) == SYMBOL_REF
8876 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8877 case UNSPEC_MACHOPIC_OFFSET:
8878 return legitimate_pic_address_disp_p (x);
8886 return legitimate_pic_address_disp_p (x);
8893 /* Determine if a given CONST RTX is a valid memory displacement
8897 legitimate_pic_address_disp_p (rtx disp)
8901 /* In 64bit mode we can allow direct addresses of symbols and labels
8902 when they are not dynamic symbols. */
8905 rtx op0 = disp, op1;
8907 switch (GET_CODE (disp))
8913 if (GET_CODE (XEXP (disp, 0)) != PLUS)
8915 op0 = XEXP (XEXP (disp, 0), 0);
8916 op1 = XEXP (XEXP (disp, 0), 1);
8917 if (!CONST_INT_P (op1)
8918 || INTVAL (op1) >= 16*1024*1024
8919 || INTVAL (op1) < -16*1024*1024)
8921 if (GET_CODE (op0) == LABEL_REF)
8923 if (GET_CODE (op0) != SYMBOL_REF)
8928 /* TLS references should always be enclosed in UNSPEC. */
8929 if (SYMBOL_REF_TLS_MODEL (op0))
8931 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
8932 && ix86_cmodel != CM_LARGE_PIC)
8940 if (GET_CODE (disp) != CONST)
8942 disp = XEXP (disp, 0);
8946 /* We are unsafe to allow PLUS expressions. This limit allowed distance
8947 of GOT tables. We should not need these anyway. */
8948 if (GET_CODE (disp) != UNSPEC
8949 || (XINT (disp, 1) != UNSPEC_GOTPCREL
8950 && XINT (disp, 1) != UNSPEC_GOTOFF
8951 && XINT (disp, 1) != UNSPEC_PLTOFF))
8954 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
8955 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
8961 if (GET_CODE (disp) == PLUS)
8963 if (!CONST_INT_P (XEXP (disp, 1)))
8965 disp = XEXP (disp, 0);
8969 if (TARGET_MACHO && darwin_local_data_pic (disp))
8972 if (GET_CODE (disp) != UNSPEC)
8975 switch (XINT (disp, 1))
8980 /* We need to check for both symbols and labels because VxWorks loads
8981 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
8983 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
8984 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
8986 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
8987 While ABI specify also 32bit relocation but we don't produce it in
8988 small PIC model at all. */
8989 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
8990 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
8992 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
8994 case UNSPEC_GOTTPOFF:
8995 case UNSPEC_GOTNTPOFF:
8996 case UNSPEC_INDNTPOFF:
8999 disp = XVECEXP (disp, 0, 0);
9000 return (GET_CODE (disp) == SYMBOL_REF
9001 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9003 disp = XVECEXP (disp, 0, 0);
9004 return (GET_CODE (disp) == SYMBOL_REF
9005 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9007 disp = XVECEXP (disp, 0, 0);
9008 return (GET_CODE (disp) == SYMBOL_REF
9009 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9015 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9016 memory address for an instruction. The MODE argument is the machine mode
9017 for the MEM expression that wants to use this address.
9019 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9020 convert common non-canonical forms to canonical form so that they will
9024 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9025 rtx addr, int strict)
9027 struct ix86_address parts;
9028 rtx base, index, disp;
9029 HOST_WIDE_INT scale;
9030 const char *reason = NULL;
9031 rtx reason_rtx = NULL_RTX;
9033 if (ix86_decompose_address (addr, &parts) <= 0)
9035 reason = "decomposition failed";
9040 index = parts.index;
9042 scale = parts.scale;
9044 /* Validate base register.
9046 Don't allow SUBREG's that span more than a word here. It can lead to spill
9047 failures when the base is one word out of a two word structure, which is
9048 represented internally as a DImode int. */
9057 else if (GET_CODE (base) == SUBREG
9058 && REG_P (SUBREG_REG (base))
9059 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9061 reg = SUBREG_REG (base);
9064 reason = "base is not a register";
9068 if (GET_MODE (base) != Pmode)
9070 reason = "base is not in Pmode";
9074 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9075 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9077 reason = "base is not valid";
9082 /* Validate index register.
9084 Don't allow SUBREG's that span more than a word here -- same as above. */
9093 else if (GET_CODE (index) == SUBREG
9094 && REG_P (SUBREG_REG (index))
9095 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9097 reg = SUBREG_REG (index);
9100 reason = "index is not a register";
9104 if (GET_MODE (index) != Pmode)
9106 reason = "index is not in Pmode";
9110 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9111 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9113 reason = "index is not valid";
9118 /* Validate scale factor. */
9121 reason_rtx = GEN_INT (scale);
9124 reason = "scale without index";
9128 if (scale != 2 && scale != 4 && scale != 8)
9130 reason = "scale is not a valid multiplier";
9135 /* Validate displacement. */
9140 if (GET_CODE (disp) == CONST
9141 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9142 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9143 switch (XINT (XEXP (disp, 0), 1))
9145 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9146 used. While ABI specify also 32bit relocations, we don't produce
9147 them at all and use IP relative instead. */
9150 gcc_assert (flag_pic);
9152 goto is_legitimate_pic;
9153 reason = "64bit address unspec";
9156 case UNSPEC_GOTPCREL:
9157 gcc_assert (flag_pic);
9158 goto is_legitimate_pic;
9160 case UNSPEC_GOTTPOFF:
9161 case UNSPEC_GOTNTPOFF:
9162 case UNSPEC_INDNTPOFF:
9168 reason = "invalid address unspec";
9172 else if (SYMBOLIC_CONST (disp)
9176 && MACHOPIC_INDIRECT
9177 && !machopic_operand_p (disp)
9183 if (TARGET_64BIT && (index || base))
9185 /* foo@dtpoff(%rX) is ok. */
9186 if (GET_CODE (disp) != CONST
9187 || GET_CODE (XEXP (disp, 0)) != PLUS
9188 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9189 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9190 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9191 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9193 reason = "non-constant pic memory reference";
9197 else if (! legitimate_pic_address_disp_p (disp))
9199 reason = "displacement is an invalid pic construct";
9203 /* This code used to verify that a symbolic pic displacement
9204 includes the pic_offset_table_rtx register.
9206 While this is good idea, unfortunately these constructs may
9207 be created by "adds using lea" optimization for incorrect
9216 This code is nonsensical, but results in addressing
9217 GOT table with pic_offset_table_rtx base. We can't
9218 just refuse it easily, since it gets matched by
9219 "addsi3" pattern, that later gets split to lea in the
9220 case output register differs from input. While this
9221 can be handled by separate addsi pattern for this case
9222 that never results in lea, this seems to be easier and
9223 correct fix for crash to disable this test. */
9225 else if (GET_CODE (disp) != LABEL_REF
9226 && !CONST_INT_P (disp)
9227 && (GET_CODE (disp) != CONST
9228 || !legitimate_constant_p (disp))
9229 && (GET_CODE (disp) != SYMBOL_REF
9230 || !legitimate_constant_p (disp)))
9232 reason = "displacement is not constant";
9235 else if (TARGET_64BIT
9236 && !x86_64_immediate_operand (disp, VOIDmode))
9238 reason = "displacement is out of range";
9243 /* Everything looks valid. */
9250 /* Return a unique alias set for the GOT. */
9252 static alias_set_type
9253 ix86_GOT_alias_set (void)
9255 static alias_set_type set = -1;
9257 set = new_alias_set ();
9261 /* Return a legitimate reference for ORIG (an address) using the
9262 register REG. If REG is 0, a new pseudo is generated.
9264 There are two types of references that must be handled:
9266 1. Global data references must load the address from the GOT, via
9267 the PIC reg. An insn is emitted to do this load, and the reg is
9270 2. Static data references, constant pool addresses, and code labels
9271 compute the address as an offset from the GOT, whose base is in
9272 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9273 differentiate them from global data objects. The returned
9274 address is the PIC reg + an unspec constant.
9276 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9277 reg also appears in the address. */
9280 legitimize_pic_address (rtx orig, rtx reg)
9287 if (TARGET_MACHO && !TARGET_64BIT)
9290 reg = gen_reg_rtx (Pmode);
9291 /* Use the generic Mach-O PIC machinery. */
9292 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9296 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9298 else if (TARGET_64BIT
9299 && ix86_cmodel != CM_SMALL_PIC
9300 && gotoff_operand (addr, Pmode))
9303 /* This symbol may be referenced via a displacement from the PIC
9304 base address (@GOTOFF). */
9306 if (reload_in_progress)
9307 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9308 if (GET_CODE (addr) == CONST)
9309 addr = XEXP (addr, 0);
9310 if (GET_CODE (addr) == PLUS)
9312 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9314 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9317 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9318 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9320 tmpreg = gen_reg_rtx (Pmode);
9323 emit_move_insn (tmpreg, new_rtx);
9327 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9328 tmpreg, 1, OPTAB_DIRECT);
9331 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9333 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9335 /* This symbol may be referenced via a displacement from the PIC
9336 base address (@GOTOFF). */
9338 if (reload_in_progress)
9339 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9340 if (GET_CODE (addr) == CONST)
9341 addr = XEXP (addr, 0);
9342 if (GET_CODE (addr) == PLUS)
9344 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9346 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9349 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9350 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9351 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9355 emit_move_insn (reg, new_rtx);
9359 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9360 /* We can't use @GOTOFF for text labels on VxWorks;
9361 see gotoff_operand. */
9362 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9364 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9366 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9367 return legitimize_dllimport_symbol (addr, true);
9368 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9369 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9370 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9372 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9373 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9377 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9379 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9380 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9381 new_rtx = gen_const_mem (Pmode, new_rtx);
9382 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9385 reg = gen_reg_rtx (Pmode);
9386 /* Use directly gen_movsi, otherwise the address is loaded
9387 into register for CSE. We don't want to CSE this addresses,
9388 instead we CSE addresses from the GOT table, so skip this. */
9389 emit_insn (gen_movsi (reg, new_rtx));
9394 /* This symbol must be referenced via a load from the
9395 Global Offset Table (@GOT). */
9397 if (reload_in_progress)
9398 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9399 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9400 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9402 new_rtx = force_reg (Pmode, new_rtx);
9403 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9404 new_rtx = gen_const_mem (Pmode, new_rtx);
9405 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9408 reg = gen_reg_rtx (Pmode);
9409 emit_move_insn (reg, new_rtx);
9415 if (CONST_INT_P (addr)
9416 && !x86_64_immediate_operand (addr, VOIDmode))
9420 emit_move_insn (reg, addr);
9424 new_rtx = force_reg (Pmode, addr);
9426 else if (GET_CODE (addr) == CONST)
9428 addr = XEXP (addr, 0);
9430 /* We must match stuff we generate before. Assume the only
9431 unspecs that can get here are ours. Not that we could do
9432 anything with them anyway.... */
9433 if (GET_CODE (addr) == UNSPEC
9434 || (GET_CODE (addr) == PLUS
9435 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9437 gcc_assert (GET_CODE (addr) == PLUS);
9439 if (GET_CODE (addr) == PLUS)
9441 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9443 /* Check first to see if this is a constant offset from a @GOTOFF
9444 symbol reference. */
9445 if (gotoff_operand (op0, Pmode)
9446 && CONST_INT_P (op1))
9450 if (reload_in_progress)
9451 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9452 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9454 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9455 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9456 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9460 emit_move_insn (reg, new_rtx);
9466 if (INTVAL (op1) < -16*1024*1024
9467 || INTVAL (op1) >= 16*1024*1024)
9469 if (!x86_64_immediate_operand (op1, Pmode))
9470 op1 = force_reg (Pmode, op1);
9471 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9477 base = legitimize_pic_address (XEXP (addr, 0), reg);
9478 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9479 base == reg ? NULL_RTX : reg);
9481 if (CONST_INT_P (new_rtx))
9482 new_rtx = plus_constant (base, INTVAL (new_rtx));
9485 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9487 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9488 new_rtx = XEXP (new_rtx, 1);
9490 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9498 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9501 get_thread_pointer (int to_reg)
9505 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9509 reg = gen_reg_rtx (Pmode);
9510 insn = gen_rtx_SET (VOIDmode, reg, tp);
9511 insn = emit_insn (insn);
9516 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9517 false if we expect this to be used for a memory address and true if
9518 we expect to load the address into a register. */
9521 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9523 rtx dest, base, off, pic, tp;
9528 case TLS_MODEL_GLOBAL_DYNAMIC:
9529 dest = gen_reg_rtx (Pmode);
9530 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9532 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9534 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9537 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9538 insns = get_insns ();
9541 RTL_CONST_CALL_P (insns) = 1;
9542 emit_libcall_block (insns, dest, rax, x);
9544 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9545 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9547 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9549 if (TARGET_GNU2_TLS)
9551 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9553 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9557 case TLS_MODEL_LOCAL_DYNAMIC:
9558 base = gen_reg_rtx (Pmode);
9559 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9561 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9563 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9566 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9567 insns = get_insns ();
9570 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9571 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9572 RTL_CONST_CALL_P (insns) = 1;
9573 emit_libcall_block (insns, base, rax, note);
9575 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9576 emit_insn (gen_tls_local_dynamic_base_64 (base));
9578 emit_insn (gen_tls_local_dynamic_base_32 (base));
9580 if (TARGET_GNU2_TLS)
9582 rtx x = ix86_tls_module_base ();
9584 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9585 gen_rtx_MINUS (Pmode, x, tp));
9588 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9589 off = gen_rtx_CONST (Pmode, off);
9591 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9593 if (TARGET_GNU2_TLS)
9595 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9597 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9602 case TLS_MODEL_INITIAL_EXEC:
9606 type = UNSPEC_GOTNTPOFF;
9610 if (reload_in_progress)
9611 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9612 pic = pic_offset_table_rtx;
9613 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9615 else if (!TARGET_ANY_GNU_TLS)
9617 pic = gen_reg_rtx (Pmode);
9618 emit_insn (gen_set_got (pic));
9619 type = UNSPEC_GOTTPOFF;
9624 type = UNSPEC_INDNTPOFF;
9627 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9628 off = gen_rtx_CONST (Pmode, off);
9630 off = gen_rtx_PLUS (Pmode, pic, off);
9631 off = gen_const_mem (Pmode, off);
9632 set_mem_alias_set (off, ix86_GOT_alias_set ());
9634 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9636 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9637 off = force_reg (Pmode, off);
9638 return gen_rtx_PLUS (Pmode, base, off);
9642 base = get_thread_pointer (true);
9643 dest = gen_reg_rtx (Pmode);
9644 emit_insn (gen_subsi3 (dest, base, off));
9648 case TLS_MODEL_LOCAL_EXEC:
9649 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9650 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9651 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9652 off = gen_rtx_CONST (Pmode, off);
9654 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9656 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9657 return gen_rtx_PLUS (Pmode, base, off);
9661 base = get_thread_pointer (true);
9662 dest = gen_reg_rtx (Pmode);
9663 emit_insn (gen_subsi3 (dest, base, off));
9674 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9677 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9678 htab_t dllimport_map;
9681 get_dllimport_decl (tree decl)
9683 struct tree_map *h, in;
9687 size_t namelen, prefixlen;
9693 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9695 in.hash = htab_hash_pointer (decl);
9696 in.base.from = decl;
9697 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9698 h = (struct tree_map *) *loc;
9702 *loc = h = GGC_NEW (struct tree_map);
9704 h->base.from = decl;
9705 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9706 DECL_ARTIFICIAL (to) = 1;
9707 DECL_IGNORED_P (to) = 1;
9708 DECL_EXTERNAL (to) = 1;
9709 TREE_READONLY (to) = 1;
9711 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9712 name = targetm.strip_name_encoding (name);
9713 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9714 ? "*__imp_" : "*__imp__";
9715 namelen = strlen (name);
9716 prefixlen = strlen (prefix);
9717 imp_name = (char *) alloca (namelen + prefixlen + 1);
9718 memcpy (imp_name, prefix, prefixlen);
9719 memcpy (imp_name + prefixlen, name, namelen + 1);
9721 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9722 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9723 SET_SYMBOL_REF_DECL (rtl, to);
9724 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9726 rtl = gen_const_mem (Pmode, rtl);
9727 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9729 SET_DECL_RTL (to, rtl);
9730 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9735 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9736 true if we require the result be a register. */
9739 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9744 gcc_assert (SYMBOL_REF_DECL (symbol));
9745 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9747 x = DECL_RTL (imp_decl);
9749 x = force_reg (Pmode, x);
9753 /* Try machine-dependent ways of modifying an illegitimate address
9754 to be legitimate. If we find one, return the new, valid address.
9755 This macro is used in only one place: `memory_address' in explow.c.
9757 OLDX is the address as it was before break_out_memory_refs was called.
9758 In some cases it is useful to look at this to decide what needs to be done.
9760 MODE and WIN are passed so that this macro can use
9761 GO_IF_LEGITIMATE_ADDRESS.
9763 It is always safe for this macro to do nothing. It exists to recognize
9764 opportunities to optimize the output.
9766 For the 80386, we handle X+REG by loading X into a register R and
9767 using R+REG. R will go in a general reg and indexing will be used.
9768 However, if REG is a broken-out memory address or multiplication,
9769 nothing needs to be done because REG can certainly go in a general reg.
9771 When -fpic is used, special handling is needed for symbolic references.
9772 See comments by legitimize_pic_address in i386.c for details. */
9775 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9780 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9782 return legitimize_tls_address (x, (enum tls_model) log, false);
9783 if (GET_CODE (x) == CONST
9784 && GET_CODE (XEXP (x, 0)) == PLUS
9785 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9786 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9788 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9789 (enum tls_model) log, false);
9790 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9793 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9795 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9796 return legitimize_dllimport_symbol (x, true);
9797 if (GET_CODE (x) == CONST
9798 && GET_CODE (XEXP (x, 0)) == PLUS
9799 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9800 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9802 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9803 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9807 if (flag_pic && SYMBOLIC_CONST (x))
9808 return legitimize_pic_address (x, 0);
9810 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9811 if (GET_CODE (x) == ASHIFT
9812 && CONST_INT_P (XEXP (x, 1))
9813 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9816 log = INTVAL (XEXP (x, 1));
9817 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9818 GEN_INT (1 << log));
9821 if (GET_CODE (x) == PLUS)
9823 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9825 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9826 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9827 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9830 log = INTVAL (XEXP (XEXP (x, 0), 1));
9831 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9832 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9833 GEN_INT (1 << log));
9836 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9837 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9838 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9841 log = INTVAL (XEXP (XEXP (x, 1), 1));
9842 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9843 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9844 GEN_INT (1 << log));
9847 /* Put multiply first if it isn't already. */
9848 if (GET_CODE (XEXP (x, 1)) == MULT)
9850 rtx tmp = XEXP (x, 0);
9851 XEXP (x, 0) = XEXP (x, 1);
9856 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9857 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9858 created by virtual register instantiation, register elimination, and
9859 similar optimizations. */
9860 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9863 x = gen_rtx_PLUS (Pmode,
9864 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9865 XEXP (XEXP (x, 1), 0)),
9866 XEXP (XEXP (x, 1), 1));
9870 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9871 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9872 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9873 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
9874 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
9875 && CONSTANT_P (XEXP (x, 1)))
9878 rtx other = NULL_RTX;
9880 if (CONST_INT_P (XEXP (x, 1)))
9882 constant = XEXP (x, 1);
9883 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
9885 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
9887 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
9888 other = XEXP (x, 1);
9896 x = gen_rtx_PLUS (Pmode,
9897 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
9898 XEXP (XEXP (XEXP (x, 0), 1), 0)),
9899 plus_constant (other, INTVAL (constant)));
9903 if (changed && legitimate_address_p (mode, x, FALSE))
9906 if (GET_CODE (XEXP (x, 0)) == MULT)
9909 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
9912 if (GET_CODE (XEXP (x, 1)) == MULT)
9915 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
9919 && REG_P (XEXP (x, 1))
9920 && REG_P (XEXP (x, 0)))
9923 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
9926 x = legitimize_pic_address (x, 0);
9929 if (changed && legitimate_address_p (mode, x, FALSE))
9932 if (REG_P (XEXP (x, 0)))
9934 rtx temp = gen_reg_rtx (Pmode);
9935 rtx val = force_operand (XEXP (x, 1), temp);
9937 emit_move_insn (temp, val);
9943 else if (REG_P (XEXP (x, 1)))
9945 rtx temp = gen_reg_rtx (Pmode);
9946 rtx val = force_operand (XEXP (x, 0), temp);
9948 emit_move_insn (temp, val);
9958 /* Print an integer constant expression in assembler syntax. Addition
9959 and subtraction are the only arithmetic that may appear in these
9960 expressions. FILE is the stdio stream to write to, X is the rtx, and
9961 CODE is the operand print code from the output string. */
9964 output_pic_addr_const (FILE *file, rtx x, int code)
9968 switch (GET_CODE (x))
9971 gcc_assert (flag_pic);
9976 if (! TARGET_MACHO || TARGET_64BIT)
9977 output_addr_const (file, x);
9980 const char *name = XSTR (x, 0);
9982 /* Mark the decl as referenced so that cgraph will
9983 output the function. */
9984 if (SYMBOL_REF_DECL (x))
9985 mark_decl_referenced (SYMBOL_REF_DECL (x));
9988 if (MACHOPIC_INDIRECT
9989 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9990 name = machopic_indirection_name (x, /*stub_p=*/true);
9992 assemble_name (file, name);
9994 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
9995 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
9996 fputs ("@PLT", file);
10003 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10004 assemble_name (asm_out_file, buf);
10008 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10012 /* This used to output parentheses around the expression,
10013 but that does not work on the 386 (either ATT or BSD assembler). */
10014 output_pic_addr_const (file, XEXP (x, 0), code);
10018 if (GET_MODE (x) == VOIDmode)
10020 /* We can use %d if the number is <32 bits and positive. */
10021 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10022 fprintf (file, "0x%lx%08lx",
10023 (unsigned long) CONST_DOUBLE_HIGH (x),
10024 (unsigned long) CONST_DOUBLE_LOW (x));
10026 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10029 /* We can't handle floating point constants;
10030 PRINT_OPERAND must handle them. */
10031 output_operand_lossage ("floating constant misused");
10035 /* Some assemblers need integer constants to appear first. */
10036 if (CONST_INT_P (XEXP (x, 0)))
10038 output_pic_addr_const (file, XEXP (x, 0), code);
10040 output_pic_addr_const (file, XEXP (x, 1), code);
10044 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10045 output_pic_addr_const (file, XEXP (x, 1), code);
10047 output_pic_addr_const (file, XEXP (x, 0), code);
10053 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10054 output_pic_addr_const (file, XEXP (x, 0), code);
10056 output_pic_addr_const (file, XEXP (x, 1), code);
10058 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10062 gcc_assert (XVECLEN (x, 0) == 1);
10063 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10064 switch (XINT (x, 1))
10067 fputs ("@GOT", file);
10069 case UNSPEC_GOTOFF:
10070 fputs ("@GOTOFF", file);
10072 case UNSPEC_PLTOFF:
10073 fputs ("@PLTOFF", file);
10075 case UNSPEC_GOTPCREL:
10076 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10077 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10079 case UNSPEC_GOTTPOFF:
10080 /* FIXME: This might be @TPOFF in Sun ld too. */
10081 fputs ("@GOTTPOFF", file);
10084 fputs ("@TPOFF", file);
10086 case UNSPEC_NTPOFF:
10088 fputs ("@TPOFF", file);
10090 fputs ("@NTPOFF", file);
10092 case UNSPEC_DTPOFF:
10093 fputs ("@DTPOFF", file);
10095 case UNSPEC_GOTNTPOFF:
10097 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10098 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10100 fputs ("@GOTNTPOFF", file);
10102 case UNSPEC_INDNTPOFF:
10103 fputs ("@INDNTPOFF", file);
10106 case UNSPEC_MACHOPIC_OFFSET:
10108 machopic_output_function_base_name (file);
10112 output_operand_lossage ("invalid UNSPEC as operand");
10118 output_operand_lossage ("invalid expression as operand");
10122 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10123 We need to emit DTP-relative relocations. */
10125 static void ATTRIBUTE_UNUSED
10126 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10128 fputs (ASM_LONG, file);
10129 output_addr_const (file, x);
10130 fputs ("@DTPOFF", file);
10136 fputs (", 0", file);
10139 gcc_unreachable ();
10143 /* Return true if X is a representation of the PIC register. This copes
10144 with calls from ix86_find_base_term, where the register might have
10145 been replaced by a cselib value. */
10148 ix86_pic_register_p (rtx x)
10150 if (GET_CODE (x) == VALUE)
10151 return (pic_offset_table_rtx
10152 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10154 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10157 /* In the name of slightly smaller debug output, and to cater to
10158 general assembler lossage, recognize PIC+GOTOFF and turn it back
10159 into a direct symbol reference.
10161 On Darwin, this is necessary to avoid a crash, because Darwin
10162 has a different PIC label for each routine but the DWARF debugging
10163 information is not associated with any particular routine, so it's
10164 necessary to remove references to the PIC label from RTL stored by
10165 the DWARF output code. */
10168 ix86_delegitimize_address (rtx orig_x)
10171 /* reg_addend is NULL or a multiple of some register. */
10172 rtx reg_addend = NULL_RTX;
10173 /* const_addend is NULL or a const_int. */
10174 rtx const_addend = NULL_RTX;
10175 /* This is the result, or NULL. */
10176 rtx result = NULL_RTX;
10183 if (GET_CODE (x) != CONST
10184 || GET_CODE (XEXP (x, 0)) != UNSPEC
10185 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10186 || !MEM_P (orig_x))
10188 return XVECEXP (XEXP (x, 0), 0, 0);
10191 if (GET_CODE (x) != PLUS
10192 || GET_CODE (XEXP (x, 1)) != CONST)
10195 if (ix86_pic_register_p (XEXP (x, 0)))
10196 /* %ebx + GOT/GOTOFF */
10198 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10200 /* %ebx + %reg * scale + GOT/GOTOFF */
10201 reg_addend = XEXP (x, 0);
10202 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10203 reg_addend = XEXP (reg_addend, 1);
10204 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10205 reg_addend = XEXP (reg_addend, 0);
10208 if (!REG_P (reg_addend)
10209 && GET_CODE (reg_addend) != MULT
10210 && GET_CODE (reg_addend) != ASHIFT)
10216 x = XEXP (XEXP (x, 1), 0);
10217 if (GET_CODE (x) == PLUS
10218 && CONST_INT_P (XEXP (x, 1)))
10220 const_addend = XEXP (x, 1);
10224 if (GET_CODE (x) == UNSPEC
10225 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10226 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10227 result = XVECEXP (x, 0, 0);
10229 if (TARGET_MACHO && darwin_local_data_pic (x)
10230 && !MEM_P (orig_x))
10231 result = XVECEXP (x, 0, 0);
10237 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10239 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10243 /* If X is a machine specific address (i.e. a symbol or label being
10244 referenced as a displacement from the GOT implemented using an
10245 UNSPEC), then return the base term. Otherwise return X. */
10248 ix86_find_base_term (rtx x)
10254 if (GET_CODE (x) != CONST)
10256 term = XEXP (x, 0);
10257 if (GET_CODE (term) == PLUS
10258 && (CONST_INT_P (XEXP (term, 1))
10259 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10260 term = XEXP (term, 0);
10261 if (GET_CODE (term) != UNSPEC
10262 || XINT (term, 1) != UNSPEC_GOTPCREL)
10265 return XVECEXP (term, 0, 0);
10268 return ix86_delegitimize_address (x);
10272 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10273 int fp, FILE *file)
10275 const char *suffix;
10277 if (mode == CCFPmode || mode == CCFPUmode)
10279 enum rtx_code second_code, bypass_code;
10280 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10281 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10282 code = ix86_fp_compare_code_to_integer (code);
10286 code = reverse_condition (code);
10337 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10341 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10342 Those same assemblers have the same but opposite lossage on cmov. */
10343 if (mode == CCmode)
10344 suffix = fp ? "nbe" : "a";
10345 else if (mode == CCCmode)
10348 gcc_unreachable ();
10364 gcc_unreachable ();
10368 gcc_assert (mode == CCmode || mode == CCCmode);
10385 gcc_unreachable ();
10389 /* ??? As above. */
10390 gcc_assert (mode == CCmode || mode == CCCmode);
10391 suffix = fp ? "nb" : "ae";
10394 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10398 /* ??? As above. */
10399 if (mode == CCmode)
10401 else if (mode == CCCmode)
10402 suffix = fp ? "nb" : "ae";
10404 gcc_unreachable ();
10407 suffix = fp ? "u" : "p";
10410 suffix = fp ? "nu" : "np";
10413 gcc_unreachable ();
10415 fputs (suffix, file);
10418 /* Print the name of register X to FILE based on its machine mode and number.
10419 If CODE is 'w', pretend the mode is HImode.
10420 If CODE is 'b', pretend the mode is QImode.
10421 If CODE is 'k', pretend the mode is SImode.
10422 If CODE is 'q', pretend the mode is DImode.
10423 If CODE is 'x', pretend the mode is V4SFmode.
10424 If CODE is 't', pretend the mode is V8SFmode.
10425 If CODE is 'h', pretend the reg is the 'high' byte register.
10426 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10427 If CODE is 'd', duplicate the operand for AVX instruction.
10431 print_reg (rtx x, int code, FILE *file)
10434 bool duplicated = code == 'd' && TARGET_AVX;
10436 gcc_assert (x == pc_rtx
10437 || (REGNO (x) != ARG_POINTER_REGNUM
10438 && REGNO (x) != FRAME_POINTER_REGNUM
10439 && REGNO (x) != FLAGS_REG
10440 && REGNO (x) != FPSR_REG
10441 && REGNO (x) != FPCR_REG));
10443 if (ASSEMBLER_DIALECT == ASM_ATT)
10448 gcc_assert (TARGET_64BIT);
10449 fputs ("rip", file);
10453 if (code == 'w' || MMX_REG_P (x))
10455 else if (code == 'b')
10457 else if (code == 'k')
10459 else if (code == 'q')
10461 else if (code == 'y')
10463 else if (code == 'h')
10465 else if (code == 'x')
10467 else if (code == 't')
10470 code = GET_MODE_SIZE (GET_MODE (x));
10472 /* Irritatingly, AMD extended registers use different naming convention
10473 from the normal registers. */
10474 if (REX_INT_REG_P (x))
10476 gcc_assert (TARGET_64BIT);
10480 error ("extended registers have no high halves");
10483 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10486 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10489 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10492 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10495 error ("unsupported operand size for extended register");
10505 if (STACK_TOP_P (x))
10514 if (! ANY_FP_REG_P (x))
10515 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10520 reg = hi_reg_name[REGNO (x)];
10523 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10525 reg = qi_reg_name[REGNO (x)];
10528 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10530 reg = qi_high_reg_name[REGNO (x)];
10535 gcc_assert (!duplicated);
10537 fputs (hi_reg_name[REGNO (x)] + 1, file);
10542 gcc_unreachable ();
10548 if (ASSEMBLER_DIALECT == ASM_ATT)
10549 fprintf (file, ", %%%s", reg);
10551 fprintf (file, ", %s", reg);
10555 /* Locate some local-dynamic symbol still in use by this function
10556 so that we can print its name in some tls_local_dynamic_base
10560 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10564 if (GET_CODE (x) == SYMBOL_REF
10565 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10567 cfun->machine->some_ld_name = XSTR (x, 0);
10574 static const char *
10575 get_some_local_dynamic_name (void)
10579 if (cfun->machine->some_ld_name)
10580 return cfun->machine->some_ld_name;
10582 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10584 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10585 return cfun->machine->some_ld_name;
10587 gcc_unreachable ();
10590 /* Meaning of CODE:
10591 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10592 C -- print opcode suffix for set/cmov insn.
10593 c -- like C, but print reversed condition
10594 E,e -- likewise, but for compare-and-branch fused insn.
10595 F,f -- likewise, but for floating-point.
10596 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10598 R -- print the prefix for register names.
10599 z -- print the opcode suffix for the size of the current operand.
10600 * -- print a star (in certain assembler syntax)
10601 A -- print an absolute memory reference.
10602 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10603 s -- print a shift double count, followed by the assemblers argument
10605 b -- print the QImode name of the register for the indicated operand.
10606 %b0 would print %al if operands[0] is reg 0.
10607 w -- likewise, print the HImode name of the register.
10608 k -- likewise, print the SImode name of the register.
10609 q -- likewise, print the DImode name of the register.
10610 x -- likewise, print the V4SFmode name of the register.
10611 t -- likewise, print the V8SFmode name of the register.
10612 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10613 y -- print "st(0)" instead of "st" as a register.
10614 d -- print duplicated register operand for AVX instruction.
10615 D -- print condition for SSE cmp instruction.
10616 P -- if PIC, print an @PLT suffix.
10617 X -- don't print any sort of PIC '@' suffix for a symbol.
10618 & -- print some in-use local-dynamic symbol name.
10619 H -- print a memory address offset by 8; used for sse high-parts
10620 Y -- print condition for SSE5 com* instruction.
10621 + -- print a branch hint as 'cs' or 'ds' prefix
10622 ; -- print a semicolon (after prefixes due to bug in older gas).
10626 print_operand (FILE *file, rtx x, int code)
10633 if (ASSEMBLER_DIALECT == ASM_ATT)
10638 assemble_name (file, get_some_local_dynamic_name ());
10642 switch (ASSEMBLER_DIALECT)
10649 /* Intel syntax. For absolute addresses, registers should not
10650 be surrounded by braces. */
10654 PRINT_OPERAND (file, x, 0);
10661 gcc_unreachable ();
10664 PRINT_OPERAND (file, x, 0);
10669 if (ASSEMBLER_DIALECT == ASM_ATT)
10674 if (ASSEMBLER_DIALECT == ASM_ATT)
10679 if (ASSEMBLER_DIALECT == ASM_ATT)
10684 if (ASSEMBLER_DIALECT == ASM_ATT)
10689 if (ASSEMBLER_DIALECT == ASM_ATT)
10694 if (ASSEMBLER_DIALECT == ASM_ATT)
10699 /* 387 opcodes don't get size suffixes if the operands are
10701 if (STACK_REG_P (x))
10704 /* Likewise if using Intel opcodes. */
10705 if (ASSEMBLER_DIALECT == ASM_INTEL)
10708 /* This is the size of op from size of operand. */
10709 switch (GET_MODE_SIZE (GET_MODE (x)))
10718 #ifdef HAVE_GAS_FILDS_FISTS
10728 if (GET_MODE (x) == SFmode)
10743 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10747 #ifdef GAS_MNEMONICS
10762 gcc_unreachable ();
10779 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10781 PRINT_OPERAND (file, x, 0);
10782 fputs (", ", file);
10787 /* Little bit of braindamage here. The SSE compare instructions
10788 does use completely different names for the comparisons that the
10789 fp conditional moves. */
10792 switch (GET_CODE (x))
10795 fputs ("eq", file);
10798 fputs ("eq_us", file);
10801 fputs ("lt", file);
10804 fputs ("nge", file);
10807 fputs ("le", file);
10810 fputs ("ngt", file);
10813 fputs ("unord", file);
10816 fputs ("neq", file);
10819 fputs ("neq_oq", file);
10822 fputs ("ge", file);
10825 fputs ("nlt", file);
10828 fputs ("gt", file);
10831 fputs ("nle", file);
10834 fputs ("ord", file);
10837 gcc_unreachable ();
10842 switch (GET_CODE (x))
10846 fputs ("eq", file);
10850 fputs ("lt", file);
10854 fputs ("le", file);
10857 fputs ("unord", file);
10861 fputs ("neq", file);
10865 fputs ("nlt", file);
10869 fputs ("nle", file);
10872 fputs ("ord", file);
10875 gcc_unreachable ();
10880 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10881 if (ASSEMBLER_DIALECT == ASM_ATT)
10883 switch (GET_MODE (x))
10885 case HImode: putc ('w', file); break;
10887 case SFmode: putc ('l', file); break;
10889 case DFmode: putc ('q', file); break;
10890 default: gcc_unreachable ();
10897 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
10900 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10901 if (ASSEMBLER_DIALECT == ASM_ATT)
10904 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
10907 /* Like above, but reverse condition */
10909 /* Check to see if argument to %c is really a constant
10910 and not a condition code which needs to be reversed. */
10911 if (!COMPARISON_P (x))
10913 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
10916 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
10919 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10920 if (ASSEMBLER_DIALECT == ASM_ATT)
10923 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
10927 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
10931 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
10935 /* It doesn't actually matter what mode we use here, as we're
10936 only going to use this for printing. */
10937 x = adjust_address_nv (x, DImode, 8);
10945 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
10948 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
10951 int pred_val = INTVAL (XEXP (x, 0));
10953 if (pred_val < REG_BR_PROB_BASE * 45 / 100
10954 || pred_val > REG_BR_PROB_BASE * 55 / 100)
10956 int taken = pred_val > REG_BR_PROB_BASE / 2;
10957 int cputaken = final_forward_branch_p (current_output_insn) == 0;
10959 /* Emit hints only in the case default branch prediction
10960 heuristics would fail. */
10961 if (taken != cputaken)
10963 /* We use 3e (DS) prefix for taken branches and
10964 2e (CS) prefix for not taken branches. */
10966 fputs ("ds ; ", file);
10968 fputs ("cs ; ", file);
10976 switch (GET_CODE (x))
10979 fputs ("neq", file);
10982 fputs ("eq", file);
10986 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
10990 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
10994 fputs ("le", file);
10998 fputs ("lt", file);
11001 fputs ("unord", file);
11004 fputs ("ord", file);
11007 fputs ("ueq", file);
11010 fputs ("nlt", file);
11013 fputs ("nle", file);
11016 fputs ("ule", file);
11019 fputs ("ult", file);
11022 fputs ("une", file);
11025 gcc_unreachable ();
11031 fputs (" ; ", file);
11038 output_operand_lossage ("invalid operand code '%c'", code);
11043 print_reg (x, code, file);
11045 else if (MEM_P (x))
11047 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11048 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11049 && GET_MODE (x) != BLKmode)
11052 switch (GET_MODE_SIZE (GET_MODE (x)))
11054 case 1: size = "BYTE"; break;
11055 case 2: size = "WORD"; break;
11056 case 4: size = "DWORD"; break;
11057 case 8: size = "QWORD"; break;
11058 case 12: size = "XWORD"; break;
11060 if (GET_MODE (x) == XFmode)
11066 gcc_unreachable ();
11069 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11072 else if (code == 'w')
11074 else if (code == 'k')
11077 fputs (size, file);
11078 fputs (" PTR ", file);
11082 /* Avoid (%rip) for call operands. */
11083 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11084 && !CONST_INT_P (x))
11085 output_addr_const (file, x);
11086 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11087 output_operand_lossage ("invalid constraints for operand");
11089 output_address (x);
11092 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11097 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11098 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11100 if (ASSEMBLER_DIALECT == ASM_ATT)
11102 fprintf (file, "0x%08lx", (long unsigned int) l);
11105 /* These float cases don't actually occur as immediate operands. */
11106 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11110 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11111 fprintf (file, "%s", dstr);
11114 else if (GET_CODE (x) == CONST_DOUBLE
11115 && GET_MODE (x) == XFmode)
11119 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11120 fprintf (file, "%s", dstr);
11125 /* We have patterns that allow zero sets of memory, for instance.
11126 In 64-bit mode, we should probably support all 8-byte vectors,
11127 since we can in fact encode that into an immediate. */
11128 if (GET_CODE (x) == CONST_VECTOR)
11130 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11136 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11138 if (ASSEMBLER_DIALECT == ASM_ATT)
11141 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11142 || GET_CODE (x) == LABEL_REF)
11144 if (ASSEMBLER_DIALECT == ASM_ATT)
11147 fputs ("OFFSET FLAT:", file);
11150 if (CONST_INT_P (x))
11151 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11153 output_pic_addr_const (file, x, code);
11155 output_addr_const (file, x);
11159 /* Print a memory operand whose address is ADDR. */
11162 print_operand_address (FILE *file, rtx addr)
11164 struct ix86_address parts;
11165 rtx base, index, disp;
11167 int ok = ix86_decompose_address (addr, &parts);
11172 index = parts.index;
11174 scale = parts.scale;
11182 if (ASSEMBLER_DIALECT == ASM_ATT)
11184 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11187 gcc_unreachable ();
11190 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11191 if (TARGET_64BIT && !base && !index)
11195 if (GET_CODE (disp) == CONST
11196 && GET_CODE (XEXP (disp, 0)) == PLUS
11197 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11198 symbol = XEXP (XEXP (disp, 0), 0);
11200 if (GET_CODE (symbol) == LABEL_REF
11201 || (GET_CODE (symbol) == SYMBOL_REF
11202 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11205 if (!base && !index)
11207 /* Displacement only requires special attention. */
11209 if (CONST_INT_P (disp))
11211 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11212 fputs ("ds:", file);
11213 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11216 output_pic_addr_const (file, disp, 0);
11218 output_addr_const (file, disp);
11222 if (ASSEMBLER_DIALECT == ASM_ATT)
11227 output_pic_addr_const (file, disp, 0);
11228 else if (GET_CODE (disp) == LABEL_REF)
11229 output_asm_label (disp);
11231 output_addr_const (file, disp);
11236 print_reg (base, 0, file);
11240 print_reg (index, 0, file);
11242 fprintf (file, ",%d", scale);
11248 rtx offset = NULL_RTX;
11252 /* Pull out the offset of a symbol; print any symbol itself. */
11253 if (GET_CODE (disp) == CONST
11254 && GET_CODE (XEXP (disp, 0)) == PLUS
11255 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11257 offset = XEXP (XEXP (disp, 0), 1);
11258 disp = gen_rtx_CONST (VOIDmode,
11259 XEXP (XEXP (disp, 0), 0));
11263 output_pic_addr_const (file, disp, 0);
11264 else if (GET_CODE (disp) == LABEL_REF)
11265 output_asm_label (disp);
11266 else if (CONST_INT_P (disp))
11269 output_addr_const (file, disp);
11275 print_reg (base, 0, file);
11278 if (INTVAL (offset) >= 0)
11280 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11284 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11291 print_reg (index, 0, file);
11293 fprintf (file, "*%d", scale);
11301 output_addr_const_extra (FILE *file, rtx x)
11305 if (GET_CODE (x) != UNSPEC)
11308 op = XVECEXP (x, 0, 0);
11309 switch (XINT (x, 1))
11311 case UNSPEC_GOTTPOFF:
11312 output_addr_const (file, op);
11313 /* FIXME: This might be @TPOFF in Sun ld. */
11314 fputs ("@GOTTPOFF", file);
11317 output_addr_const (file, op);
11318 fputs ("@TPOFF", file);
11320 case UNSPEC_NTPOFF:
11321 output_addr_const (file, op);
11323 fputs ("@TPOFF", file);
11325 fputs ("@NTPOFF", file);
11327 case UNSPEC_DTPOFF:
11328 output_addr_const (file, op);
11329 fputs ("@DTPOFF", file);
11331 case UNSPEC_GOTNTPOFF:
11332 output_addr_const (file, op);
11334 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11335 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11337 fputs ("@GOTNTPOFF", file);
11339 case UNSPEC_INDNTPOFF:
11340 output_addr_const (file, op);
11341 fputs ("@INDNTPOFF", file);
11344 case UNSPEC_MACHOPIC_OFFSET:
11345 output_addr_const (file, op);
11347 machopic_output_function_base_name (file);
11358 /* Split one or more DImode RTL references into pairs of SImode
11359 references. The RTL can be REG, offsettable MEM, integer constant, or
11360 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11361 split and "num" is its length. lo_half and hi_half are output arrays
11362 that parallel "operands". */
11365 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11369 rtx op = operands[num];
11371 /* simplify_subreg refuse to split volatile memory addresses,
11372 but we still have to handle it. */
11375 lo_half[num] = adjust_address (op, SImode, 0);
11376 hi_half[num] = adjust_address (op, SImode, 4);
11380 lo_half[num] = simplify_gen_subreg (SImode, op,
11381 GET_MODE (op) == VOIDmode
11382 ? DImode : GET_MODE (op), 0);
11383 hi_half[num] = simplify_gen_subreg (SImode, op,
11384 GET_MODE (op) == VOIDmode
11385 ? DImode : GET_MODE (op), 4);
11389 /* Split one or more TImode RTL references into pairs of DImode
11390 references. The RTL can be REG, offsettable MEM, integer constant, or
11391 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11392 split and "num" is its length. lo_half and hi_half are output arrays
11393 that parallel "operands". */
11396 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11400 rtx op = operands[num];
11402 /* simplify_subreg refuse to split volatile memory addresses, but we
11403 still have to handle it. */
11406 lo_half[num] = adjust_address (op, DImode, 0);
11407 hi_half[num] = adjust_address (op, DImode, 8);
11411 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11412 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11417 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11418 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11419 is the expression of the binary operation. The output may either be
11420 emitted here, or returned to the caller, like all output_* functions.
11422 There is no guarantee that the operands are the same mode, as they
11423 might be within FLOAT or FLOAT_EXTEND expressions. */
11425 #ifndef SYSV386_COMPAT
11426 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11427 wants to fix the assemblers because that causes incompatibility
11428 with gcc. No-one wants to fix gcc because that causes
11429 incompatibility with assemblers... You can use the option of
11430 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11431 #define SYSV386_COMPAT 1
11435 output_387_binary_op (rtx insn, rtx *operands)
11437 static char buf[40];
11440 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11442 #ifdef ENABLE_CHECKING
11443 /* Even if we do not want to check the inputs, this documents input
11444 constraints. Which helps in understanding the following code. */
11445 if (STACK_REG_P (operands[0])
11446 && ((REG_P (operands[1])
11447 && REGNO (operands[0]) == REGNO (operands[1])
11448 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11449 || (REG_P (operands[2])
11450 && REGNO (operands[0]) == REGNO (operands[2])
11451 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11452 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11455 gcc_assert (is_sse);
11458 switch (GET_CODE (operands[3]))
11461 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11462 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11470 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11471 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11479 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11480 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11488 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11489 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11497 gcc_unreachable ();
11504 strcpy (buf, ssep);
11505 if (GET_MODE (operands[0]) == SFmode)
11506 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11508 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11512 strcpy (buf, ssep + 1);
11513 if (GET_MODE (operands[0]) == SFmode)
11514 strcat (buf, "ss\t{%2, %0|%0, %2}");
11516 strcat (buf, "sd\t{%2, %0|%0, %2}");
11522 switch (GET_CODE (operands[3]))
11526 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11528 rtx temp = operands[2];
11529 operands[2] = operands[1];
11530 operands[1] = temp;
11533 /* know operands[0] == operands[1]. */
11535 if (MEM_P (operands[2]))
11541 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11543 if (STACK_TOP_P (operands[0]))
11544 /* How is it that we are storing to a dead operand[2]?
11545 Well, presumably operands[1] is dead too. We can't
11546 store the result to st(0) as st(0) gets popped on this
11547 instruction. Instead store to operands[2] (which I
11548 think has to be st(1)). st(1) will be popped later.
11549 gcc <= 2.8.1 didn't have this check and generated
11550 assembly code that the Unixware assembler rejected. */
11551 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11553 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11557 if (STACK_TOP_P (operands[0]))
11558 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11560 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11565 if (MEM_P (operands[1]))
11571 if (MEM_P (operands[2]))
11577 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11580 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11581 derived assemblers, confusingly reverse the direction of
11582 the operation for fsub{r} and fdiv{r} when the
11583 destination register is not st(0). The Intel assembler
11584 doesn't have this brain damage. Read !SYSV386_COMPAT to
11585 figure out what the hardware really does. */
11586 if (STACK_TOP_P (operands[0]))
11587 p = "{p\t%0, %2|rp\t%2, %0}";
11589 p = "{rp\t%2, %0|p\t%0, %2}";
11591 if (STACK_TOP_P (operands[0]))
11592 /* As above for fmul/fadd, we can't store to st(0). */
11593 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11595 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11600 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11603 if (STACK_TOP_P (operands[0]))
11604 p = "{rp\t%0, %1|p\t%1, %0}";
11606 p = "{p\t%1, %0|rp\t%0, %1}";
11608 if (STACK_TOP_P (operands[0]))
11609 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11611 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11616 if (STACK_TOP_P (operands[0]))
11618 if (STACK_TOP_P (operands[1]))
11619 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11621 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11624 else if (STACK_TOP_P (operands[1]))
11627 p = "{\t%1, %0|r\t%0, %1}";
11629 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11635 p = "{r\t%2, %0|\t%0, %2}";
11637 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11643 gcc_unreachable ();
11650 /* Return needed mode for entity in optimize_mode_switching pass. */
11653 ix86_mode_needed (int entity, rtx insn)
11655 enum attr_i387_cw mode;
11657 /* The mode UNINITIALIZED is used to store control word after a
11658 function call or ASM pattern. The mode ANY specify that function
11659 has no requirements on the control word and make no changes in the
11660 bits we are interested in. */
11663 || (NONJUMP_INSN_P (insn)
11664 && (asm_noperands (PATTERN (insn)) >= 0
11665 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11666 return I387_CW_UNINITIALIZED;
11668 if (recog_memoized (insn) < 0)
11669 return I387_CW_ANY;
11671 mode = get_attr_i387_cw (insn);
11676 if (mode == I387_CW_TRUNC)
11681 if (mode == I387_CW_FLOOR)
11686 if (mode == I387_CW_CEIL)
11691 if (mode == I387_CW_MASK_PM)
11696 gcc_unreachable ();
11699 return I387_CW_ANY;
11702 /* Output code to initialize control word copies used by trunc?f?i and
11703 rounding patterns. CURRENT_MODE is set to current control word,
11704 while NEW_MODE is set to new control word. */
11707 emit_i387_cw_initialization (int mode)
11709 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11712 enum ix86_stack_slot slot;
11714 rtx reg = gen_reg_rtx (HImode);
11716 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11717 emit_move_insn (reg, copy_rtx (stored_mode));
11719 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11720 || optimize_function_for_size_p (cfun))
11724 case I387_CW_TRUNC:
11725 /* round toward zero (truncate) */
11726 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11727 slot = SLOT_CW_TRUNC;
11730 case I387_CW_FLOOR:
11731 /* round down toward -oo */
11732 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11733 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11734 slot = SLOT_CW_FLOOR;
11738 /* round up toward +oo */
11739 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11740 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11741 slot = SLOT_CW_CEIL;
11744 case I387_CW_MASK_PM:
11745 /* mask precision exception for nearbyint() */
11746 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11747 slot = SLOT_CW_MASK_PM;
11751 gcc_unreachable ();
11758 case I387_CW_TRUNC:
11759 /* round toward zero (truncate) */
11760 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11761 slot = SLOT_CW_TRUNC;
11764 case I387_CW_FLOOR:
11765 /* round down toward -oo */
11766 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11767 slot = SLOT_CW_FLOOR;
11771 /* round up toward +oo */
11772 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11773 slot = SLOT_CW_CEIL;
11776 case I387_CW_MASK_PM:
11777 /* mask precision exception for nearbyint() */
11778 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11779 slot = SLOT_CW_MASK_PM;
11783 gcc_unreachable ();
11787 gcc_assert (slot < MAX_386_STACK_LOCALS);
11789 new_mode = assign_386_stack_local (HImode, slot);
11790 emit_move_insn (new_mode, reg);
11793 /* Output code for INSN to convert a float to a signed int. OPERANDS
11794 are the insn operands. The output may be [HSD]Imode and the input
11795 operand may be [SDX]Fmode. */
11798 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11800 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11801 int dimode_p = GET_MODE (operands[0]) == DImode;
11802 int round_mode = get_attr_i387_cw (insn);
11804 /* Jump through a hoop or two for DImode, since the hardware has no
11805 non-popping instruction. We used to do this a different way, but
11806 that was somewhat fragile and broke with post-reload splitters. */
11807 if ((dimode_p || fisttp) && !stack_top_dies)
11808 output_asm_insn ("fld\t%y1", operands);
11810 gcc_assert (STACK_TOP_P (operands[1]));
11811 gcc_assert (MEM_P (operands[0]));
11812 gcc_assert (GET_MODE (operands[1]) != TFmode);
11815 output_asm_insn ("fisttp%z0\t%0", operands);
11818 if (round_mode != I387_CW_ANY)
11819 output_asm_insn ("fldcw\t%3", operands);
11820 if (stack_top_dies || dimode_p)
11821 output_asm_insn ("fistp%z0\t%0", operands);
11823 output_asm_insn ("fist%z0\t%0", operands);
11824 if (round_mode != I387_CW_ANY)
11825 output_asm_insn ("fldcw\t%2", operands);
11831 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11832 have the values zero or one, indicates the ffreep insn's operand
11833 from the OPERANDS array. */
11835 static const char *
11836 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11838 if (TARGET_USE_FFREEP)
11839 #if HAVE_AS_IX86_FFREEP
11840 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11843 static char retval[] = ".word\t0xc_df";
11844 int regno = REGNO (operands[opno]);
11846 gcc_assert (FP_REGNO_P (regno));
11848 retval[9] = '0' + (regno - FIRST_STACK_REG);
11853 return opno ? "fstp\t%y1" : "fstp\t%y0";
11857 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11858 should be used. UNORDERED_P is true when fucom should be used. */
11861 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
11863 int stack_top_dies;
11864 rtx cmp_op0, cmp_op1;
11865 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
11869 cmp_op0 = operands[0];
11870 cmp_op1 = operands[1];
11874 cmp_op0 = operands[1];
11875 cmp_op1 = operands[2];
11880 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
11881 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
11882 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
11883 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
11885 if (GET_MODE (operands[0]) == SFmode)
11887 return &ucomiss[TARGET_AVX ? 0 : 1];
11889 return &comiss[TARGET_AVX ? 0 : 1];
11892 return &ucomisd[TARGET_AVX ? 0 : 1];
11894 return &comisd[TARGET_AVX ? 0 : 1];
11897 gcc_assert (STACK_TOP_P (cmp_op0));
11899 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11901 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
11903 if (stack_top_dies)
11905 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
11906 return output_387_ffreep (operands, 1);
11909 return "ftst\n\tfnstsw\t%0";
11912 if (STACK_REG_P (cmp_op1)
11914 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
11915 && REGNO (cmp_op1) != FIRST_STACK_REG)
11917 /* If both the top of the 387 stack dies, and the other operand
11918 is also a stack register that dies, then this must be a
11919 `fcompp' float compare */
11923 /* There is no double popping fcomi variant. Fortunately,
11924 eflags is immune from the fstp's cc clobbering. */
11926 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
11928 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
11929 return output_387_ffreep (operands, 0);
11934 return "fucompp\n\tfnstsw\t%0";
11936 return "fcompp\n\tfnstsw\t%0";
11941 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
11943 static const char * const alt[16] =
11945 "fcom%z2\t%y2\n\tfnstsw\t%0",
11946 "fcomp%z2\t%y2\n\tfnstsw\t%0",
11947 "fucom%z2\t%y2\n\tfnstsw\t%0",
11948 "fucomp%z2\t%y2\n\tfnstsw\t%0",
11950 "ficom%z2\t%y2\n\tfnstsw\t%0",
11951 "ficomp%z2\t%y2\n\tfnstsw\t%0",
11955 "fcomi\t{%y1, %0|%0, %y1}",
11956 "fcomip\t{%y1, %0|%0, %y1}",
11957 "fucomi\t{%y1, %0|%0, %y1}",
11958 "fucomip\t{%y1, %0|%0, %y1}",
11969 mask = eflags_p << 3;
11970 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
11971 mask |= unordered_p << 1;
11972 mask |= stack_top_dies;
11974 gcc_assert (mask < 16);
11983 ix86_output_addr_vec_elt (FILE *file, int value)
11985 const char *directive = ASM_LONG;
11989 directive = ASM_QUAD;
11991 gcc_assert (!TARGET_64BIT);
11994 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
11998 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12000 const char *directive = ASM_LONG;
12003 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12004 directive = ASM_QUAD;
12006 gcc_assert (!TARGET_64BIT);
12008 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12009 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12010 fprintf (file, "%s%s%d-%s%d\n",
12011 directive, LPREFIX, value, LPREFIX, rel);
12012 else if (HAVE_AS_GOTOFF_IN_DATA)
12013 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12015 else if (TARGET_MACHO)
12017 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12018 machopic_output_function_base_name (file);
12019 fprintf(file, "\n");
12023 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12024 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12027 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12031 ix86_expand_clear (rtx dest)
12035 /* We play register width games, which are only valid after reload. */
12036 gcc_assert (reload_completed);
12038 /* Avoid HImode and its attendant prefix byte. */
12039 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12040 dest = gen_rtx_REG (SImode, REGNO (dest));
12041 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12043 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12044 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12046 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12047 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12053 /* X is an unchanging MEM. If it is a constant pool reference, return
12054 the constant pool rtx, else NULL. */
12057 maybe_get_pool_constant (rtx x)
12059 x = ix86_delegitimize_address (XEXP (x, 0));
12061 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12062 return get_pool_constant (x);
12068 ix86_expand_move (enum machine_mode mode, rtx operands[])
12071 enum tls_model model;
12076 if (GET_CODE (op1) == SYMBOL_REF)
12078 model = SYMBOL_REF_TLS_MODEL (op1);
12081 op1 = legitimize_tls_address (op1, model, true);
12082 op1 = force_operand (op1, op0);
12086 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12087 && SYMBOL_REF_DLLIMPORT_P (op1))
12088 op1 = legitimize_dllimport_symbol (op1, false);
12090 else if (GET_CODE (op1) == CONST
12091 && GET_CODE (XEXP (op1, 0)) == PLUS
12092 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12094 rtx addend = XEXP (XEXP (op1, 0), 1);
12095 rtx symbol = XEXP (XEXP (op1, 0), 0);
12098 model = SYMBOL_REF_TLS_MODEL (symbol);
12100 tmp = legitimize_tls_address (symbol, model, true);
12101 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12102 && SYMBOL_REF_DLLIMPORT_P (symbol))
12103 tmp = legitimize_dllimport_symbol (symbol, true);
12107 tmp = force_operand (tmp, NULL);
12108 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12109 op0, 1, OPTAB_DIRECT);
12115 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12117 if (TARGET_MACHO && !TARGET_64BIT)
12122 rtx temp = ((reload_in_progress
12123 || ((op0 && REG_P (op0))
12125 ? op0 : gen_reg_rtx (Pmode));
12126 op1 = machopic_indirect_data_reference (op1, temp);
12127 op1 = machopic_legitimize_pic_address (op1, mode,
12128 temp == op1 ? 0 : temp);
12130 else if (MACHOPIC_INDIRECT)
12131 op1 = machopic_indirect_data_reference (op1, 0);
12139 op1 = force_reg (Pmode, op1);
12140 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12142 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12143 op1 = legitimize_pic_address (op1, reg);
12152 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12153 || !push_operand (op0, mode))
12155 op1 = force_reg (mode, op1);
12157 if (push_operand (op0, mode)
12158 && ! general_no_elim_operand (op1, mode))
12159 op1 = copy_to_mode_reg (mode, op1);
12161 /* Force large constants in 64bit compilation into register
12162 to get them CSEed. */
12163 if (can_create_pseudo_p ()
12164 && (mode == DImode) && TARGET_64BIT
12165 && immediate_operand (op1, mode)
12166 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12167 && !register_operand (op0, mode)
12169 op1 = copy_to_mode_reg (mode, op1);
12171 if (can_create_pseudo_p ()
12172 && FLOAT_MODE_P (mode)
12173 && GET_CODE (op1) == CONST_DOUBLE)
12175 /* If we are loading a floating point constant to a register,
12176 force the value to memory now, since we'll get better code
12177 out the back end. */
12179 op1 = validize_mem (force_const_mem (mode, op1));
12180 if (!register_operand (op0, mode))
12182 rtx temp = gen_reg_rtx (mode);
12183 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12184 emit_move_insn (op0, temp);
12190 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12194 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12196 rtx op0 = operands[0], op1 = operands[1];
12197 unsigned int align = GET_MODE_ALIGNMENT (mode);
12199 /* Force constants other than zero into memory. We do not know how
12200 the instructions used to build constants modify the upper 64 bits
12201 of the register, once we have that information we may be able
12202 to handle some of them more efficiently. */
12203 if (can_create_pseudo_p ()
12204 && register_operand (op0, mode)
12205 && (CONSTANT_P (op1)
12206 || (GET_CODE (op1) == SUBREG
12207 && CONSTANT_P (SUBREG_REG (op1))))
12208 && standard_sse_constant_p (op1) <= 0)
12209 op1 = validize_mem (force_const_mem (mode, op1));
12211 /* We need to check memory alignment for SSE mode since attribute
12212 can make operands unaligned. */
12213 if (can_create_pseudo_p ()
12214 && SSE_REG_MODE_P (mode)
12215 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12216 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12220 /* ix86_expand_vector_move_misalign() does not like constants ... */
12221 if (CONSTANT_P (op1)
12222 || (GET_CODE (op1) == SUBREG
12223 && CONSTANT_P (SUBREG_REG (op1))))
12224 op1 = validize_mem (force_const_mem (mode, op1));
12226 /* ... nor both arguments in memory. */
12227 if (!register_operand (op0, mode)
12228 && !register_operand (op1, mode))
12229 op1 = force_reg (mode, op1);
12231 tmp[0] = op0; tmp[1] = op1;
12232 ix86_expand_vector_move_misalign (mode, tmp);
12236 /* Make operand1 a register if it isn't already. */
12237 if (can_create_pseudo_p ()
12238 && !register_operand (op0, mode)
12239 && !register_operand (op1, mode))
12241 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12245 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12248 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12249 straight to ix86_expand_vector_move. */
12250 /* Code generation for scalar reg-reg moves of single and double precision data:
12251 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12255 if (x86_sse_partial_reg_dependency == true)
12260 Code generation for scalar loads of double precision data:
12261 if (x86_sse_split_regs == true)
12262 movlpd mem, reg (gas syntax)
12266 Code generation for unaligned packed loads of single precision data
12267 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12268 if (x86_sse_unaligned_move_optimal)
12271 if (x86_sse_partial_reg_dependency == true)
12283 Code generation for unaligned packed loads of double precision data
12284 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12285 if (x86_sse_unaligned_move_optimal)
12288 if (x86_sse_split_regs == true)
12301 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12310 switch (GET_MODE_CLASS (mode))
12312 case MODE_VECTOR_INT:
12314 switch (GET_MODE_SIZE (mode))
12317 op0 = gen_lowpart (V16QImode, op0);
12318 op1 = gen_lowpart (V16QImode, op1);
12319 emit_insn (gen_avx_movdqu (op0, op1));
12322 op0 = gen_lowpart (V32QImode, op0);
12323 op1 = gen_lowpart (V32QImode, op1);
12324 emit_insn (gen_avx_movdqu256 (op0, op1));
12327 gcc_unreachable ();
12330 case MODE_VECTOR_FLOAT:
12331 op0 = gen_lowpart (mode, op0);
12332 op1 = gen_lowpart (mode, op1);
12337 emit_insn (gen_avx_movups (op0, op1));
12340 emit_insn (gen_avx_movups256 (op0, op1));
12343 emit_insn (gen_avx_movupd (op0, op1));
12346 emit_insn (gen_avx_movupd256 (op0, op1));
12349 gcc_unreachable ();
12354 gcc_unreachable ();
12362 /* If we're optimizing for size, movups is the smallest. */
12363 if (optimize_insn_for_size_p ())
12365 op0 = gen_lowpart (V4SFmode, op0);
12366 op1 = gen_lowpart (V4SFmode, op1);
12367 emit_insn (gen_sse_movups (op0, op1));
12371 /* ??? If we have typed data, then it would appear that using
12372 movdqu is the only way to get unaligned data loaded with
12374 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12376 op0 = gen_lowpart (V16QImode, op0);
12377 op1 = gen_lowpart (V16QImode, op1);
12378 emit_insn (gen_sse2_movdqu (op0, op1));
12382 if (TARGET_SSE2 && mode == V2DFmode)
12386 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12388 op0 = gen_lowpart (V2DFmode, op0);
12389 op1 = gen_lowpart (V2DFmode, op1);
12390 emit_insn (gen_sse2_movupd (op0, op1));
12394 /* When SSE registers are split into halves, we can avoid
12395 writing to the top half twice. */
12396 if (TARGET_SSE_SPLIT_REGS)
12398 emit_clobber (op0);
12403 /* ??? Not sure about the best option for the Intel chips.
12404 The following would seem to satisfy; the register is
12405 entirely cleared, breaking the dependency chain. We
12406 then store to the upper half, with a dependency depth
12407 of one. A rumor has it that Intel recommends two movsd
12408 followed by an unpacklpd, but this is unconfirmed. And
12409 given that the dependency depth of the unpacklpd would
12410 still be one, I'm not sure why this would be better. */
12411 zero = CONST0_RTX (V2DFmode);
12414 m = adjust_address (op1, DFmode, 0);
12415 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12416 m = adjust_address (op1, DFmode, 8);
12417 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12421 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12423 op0 = gen_lowpart (V4SFmode, op0);
12424 op1 = gen_lowpart (V4SFmode, op1);
12425 emit_insn (gen_sse_movups (op0, op1));
12429 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12430 emit_move_insn (op0, CONST0_RTX (mode));
12432 emit_clobber (op0);
12434 if (mode != V4SFmode)
12435 op0 = gen_lowpart (V4SFmode, op0);
12436 m = adjust_address (op1, V2SFmode, 0);
12437 emit_insn (gen_sse_loadlps (op0, op0, m));
12438 m = adjust_address (op1, V2SFmode, 8);
12439 emit_insn (gen_sse_loadhps (op0, op0, m));
12442 else if (MEM_P (op0))
12444 /* If we're optimizing for size, movups is the smallest. */
12445 if (optimize_insn_for_size_p ())
12447 op0 = gen_lowpart (V4SFmode, op0);
12448 op1 = gen_lowpart (V4SFmode, op1);
12449 emit_insn (gen_sse_movups (op0, op1));
12453 /* ??? Similar to above, only less clear because of quote
12454 typeless stores unquote. */
12455 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12456 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12458 op0 = gen_lowpart (V16QImode, op0);
12459 op1 = gen_lowpart (V16QImode, op1);
12460 emit_insn (gen_sse2_movdqu (op0, op1));
12464 if (TARGET_SSE2 && mode == V2DFmode)
12466 m = adjust_address (op0, DFmode, 0);
12467 emit_insn (gen_sse2_storelpd (m, op1));
12468 m = adjust_address (op0, DFmode, 8);
12469 emit_insn (gen_sse2_storehpd (m, op1));
12473 if (mode != V4SFmode)
12474 op1 = gen_lowpart (V4SFmode, op1);
12475 m = adjust_address (op0, V2SFmode, 0);
12476 emit_insn (gen_sse_storelps (m, op1));
12477 m = adjust_address (op0, V2SFmode, 8);
12478 emit_insn (gen_sse_storehps (m, op1));
12482 gcc_unreachable ();
12485 /* Expand a push in MODE. This is some mode for which we do not support
12486 proper push instructions, at least from the registers that we expect
12487 the value to live in. */
12490 ix86_expand_push (enum machine_mode mode, rtx x)
12494 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12495 GEN_INT (-GET_MODE_SIZE (mode)),
12496 stack_pointer_rtx, 1, OPTAB_DIRECT);
12497 if (tmp != stack_pointer_rtx)
12498 emit_move_insn (stack_pointer_rtx, tmp);
12500 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12501 emit_move_insn (tmp, x);
12504 /* Helper function of ix86_fixup_binary_operands to canonicalize
12505 operand order. Returns true if the operands should be swapped. */
12508 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12511 rtx dst = operands[0];
12512 rtx src1 = operands[1];
12513 rtx src2 = operands[2];
12515 /* If the operation is not commutative, we can't do anything. */
12516 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12519 /* Highest priority is that src1 should match dst. */
12520 if (rtx_equal_p (dst, src1))
12522 if (rtx_equal_p (dst, src2))
12525 /* Next highest priority is that immediate constants come second. */
12526 if (immediate_operand (src2, mode))
12528 if (immediate_operand (src1, mode))
12531 /* Lowest priority is that memory references should come second. */
12541 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12542 destination to use for the operation. If different from the true
12543 destination in operands[0], a copy operation will be required. */
12546 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12549 rtx dst = operands[0];
12550 rtx src1 = operands[1];
12551 rtx src2 = operands[2];
12553 /* Canonicalize operand order. */
12554 if (ix86_swap_binary_operands_p (code, mode, operands))
12558 /* It is invalid to swap operands of different modes. */
12559 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12566 /* Both source operands cannot be in memory. */
12567 if (MEM_P (src1) && MEM_P (src2))
12569 /* Optimization: Only read from memory once. */
12570 if (rtx_equal_p (src1, src2))
12572 src2 = force_reg (mode, src2);
12576 src2 = force_reg (mode, src2);
12579 /* If the destination is memory, and we do not have matching source
12580 operands, do things in registers. */
12581 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12582 dst = gen_reg_rtx (mode);
12584 /* Source 1 cannot be a constant. */
12585 if (CONSTANT_P (src1))
12586 src1 = force_reg (mode, src1);
12588 /* Source 1 cannot be a non-matching memory. */
12589 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12590 src1 = force_reg (mode, src1);
12592 operands[1] = src1;
12593 operands[2] = src2;
12597 /* Similarly, but assume that the destination has already been
12598 set up properly. */
12601 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12602 enum machine_mode mode, rtx operands[])
12604 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12605 gcc_assert (dst == operands[0]);
12608 /* Attempt to expand a binary operator. Make the expansion closer to the
12609 actual machine, then just general_operand, which will allow 3 separate
12610 memory references (one output, two input) in a single insn. */
12613 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12616 rtx src1, src2, dst, op, clob;
12618 dst = ix86_fixup_binary_operands (code, mode, operands);
12619 src1 = operands[1];
12620 src2 = operands[2];
12622 /* Emit the instruction. */
12624 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12625 if (reload_in_progress)
12627 /* Reload doesn't know about the flags register, and doesn't know that
12628 it doesn't want to clobber it. We can only do this with PLUS. */
12629 gcc_assert (code == PLUS);
12634 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12635 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12638 /* Fix up the destination if needed. */
12639 if (dst != operands[0])
12640 emit_move_insn (operands[0], dst);
12643 /* Return TRUE or FALSE depending on whether the binary operator meets the
12644 appropriate constraints. */
12647 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12650 rtx dst = operands[0];
12651 rtx src1 = operands[1];
12652 rtx src2 = operands[2];
12654 /* Both source operands cannot be in memory. */
12655 if (MEM_P (src1) && MEM_P (src2))
12658 /* Canonicalize operand order for commutative operators. */
12659 if (ix86_swap_binary_operands_p (code, mode, operands))
12666 /* If the destination is memory, we must have a matching source operand. */
12667 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12670 /* Source 1 cannot be a constant. */
12671 if (CONSTANT_P (src1))
12674 /* Source 1 cannot be a non-matching memory. */
12675 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12681 /* Attempt to expand a unary operator. Make the expansion closer to the
12682 actual machine, then just general_operand, which will allow 2 separate
12683 memory references (one output, one input) in a single insn. */
12686 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12689 int matching_memory;
12690 rtx src, dst, op, clob;
12695 /* If the destination is memory, and we do not have matching source
12696 operands, do things in registers. */
12697 matching_memory = 0;
12700 if (rtx_equal_p (dst, src))
12701 matching_memory = 1;
12703 dst = gen_reg_rtx (mode);
12706 /* When source operand is memory, destination must match. */
12707 if (MEM_P (src) && !matching_memory)
12708 src = force_reg (mode, src);
12710 /* Emit the instruction. */
12712 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12713 if (reload_in_progress || code == NOT)
12715 /* Reload doesn't know about the flags register, and doesn't know that
12716 it doesn't want to clobber it. */
12717 gcc_assert (code == NOT);
12722 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12723 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12726 /* Fix up the destination if needed. */
12727 if (dst != operands[0])
12728 emit_move_insn (operands[0], dst);
12731 /* Return TRUE or FALSE depending on whether the unary operator meets the
12732 appropriate constraints. */
12735 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12736 enum machine_mode mode ATTRIBUTE_UNUSED,
12737 rtx operands[2] ATTRIBUTE_UNUSED)
12739 /* If one of operands is memory, source and destination must match. */
12740 if ((MEM_P (operands[0])
12741 || MEM_P (operands[1]))
12742 && ! rtx_equal_p (operands[0], operands[1]))
12747 /* Post-reload splitter for converting an SF or DFmode value in an
12748 SSE register into an unsigned SImode. */
12751 ix86_split_convert_uns_si_sse (rtx operands[])
12753 enum machine_mode vecmode;
12754 rtx value, large, zero_or_two31, input, two31, x;
12756 large = operands[1];
12757 zero_or_two31 = operands[2];
12758 input = operands[3];
12759 two31 = operands[4];
12760 vecmode = GET_MODE (large);
12761 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12763 /* Load up the value into the low element. We must ensure that the other
12764 elements are valid floats -- zero is the easiest such value. */
12767 if (vecmode == V4SFmode)
12768 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12770 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12774 input = gen_rtx_REG (vecmode, REGNO (input));
12775 emit_move_insn (value, CONST0_RTX (vecmode));
12776 if (vecmode == V4SFmode)
12777 emit_insn (gen_sse_movss (value, value, input));
12779 emit_insn (gen_sse2_movsd (value, value, input));
12782 emit_move_insn (large, two31);
12783 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12785 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12786 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12788 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12789 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12791 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12792 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12794 large = gen_rtx_REG (V4SImode, REGNO (large));
12795 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12797 x = gen_rtx_REG (V4SImode, REGNO (value));
12798 if (vecmode == V4SFmode)
12799 emit_insn (gen_sse2_cvttps2dq (x, value));
12801 emit_insn (gen_sse2_cvttpd2dq (x, value));
12804 emit_insn (gen_xorv4si3 (value, value, large));
12807 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12808 Expects the 64-bit DImode to be supplied in a pair of integral
12809 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12810 -mfpmath=sse, !optimize_size only. */
12813 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12815 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12816 rtx int_xmm, fp_xmm;
12817 rtx biases, exponents;
12820 int_xmm = gen_reg_rtx (V4SImode);
12821 if (TARGET_INTER_UNIT_MOVES)
12822 emit_insn (gen_movdi_to_sse (int_xmm, input));
12823 else if (TARGET_SSE_SPLIT_REGS)
12825 emit_clobber (int_xmm);
12826 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12830 x = gen_reg_rtx (V2DImode);
12831 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12832 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12835 x = gen_rtx_CONST_VECTOR (V4SImode,
12836 gen_rtvec (4, GEN_INT (0x43300000UL),
12837 GEN_INT (0x45300000UL),
12838 const0_rtx, const0_rtx));
12839 exponents = validize_mem (force_const_mem (V4SImode, x));
12841 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12842 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
12844 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12845 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12846 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12847 (0x1.0p84 + double(fp_value_hi_xmm)).
12848 Note these exponents differ by 32. */
12850 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
12852 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12853 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12854 real_ldexp (&bias_lo_rvt, &dconst1, 52);
12855 real_ldexp (&bias_hi_rvt, &dconst1, 84);
12856 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
12857 x = const_double_from_real_value (bias_hi_rvt, DFmode);
12858 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
12859 biases = validize_mem (force_const_mem (V2DFmode, biases));
12860 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
12862 /* Add the upper and lower DFmode values together. */
12864 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
12867 x = copy_to_mode_reg (V2DFmode, fp_xmm);
12868 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
12869 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
12872 ix86_expand_vector_extract (false, target, fp_xmm, 0);
12875 /* Not used, but eases macroization of patterns. */
12877 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
12878 rtx input ATTRIBUTE_UNUSED)
12880 gcc_unreachable ();
12883 /* Convert an unsigned SImode value into a DFmode. Only currently used
12884 for SSE, but applicable anywhere. */
12887 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
12889 REAL_VALUE_TYPE TWO31r;
12892 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
12893 NULL, 1, OPTAB_DIRECT);
12895 fp = gen_reg_rtx (DFmode);
12896 emit_insn (gen_floatsidf2 (fp, x));
12898 real_ldexp (&TWO31r, &dconst1, 31);
12899 x = const_double_from_real_value (TWO31r, DFmode);
12901 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
12903 emit_move_insn (target, x);
12906 /* Convert a signed DImode value into a DFmode. Only used for SSE in
12907 32-bit mode; otherwise we have a direct convert instruction. */
12910 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
12912 REAL_VALUE_TYPE TWO32r;
12913 rtx fp_lo, fp_hi, x;
12915 fp_lo = gen_reg_rtx (DFmode);
12916 fp_hi = gen_reg_rtx (DFmode);
12918 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
12920 real_ldexp (&TWO32r, &dconst1, 32);
12921 x = const_double_from_real_value (TWO32r, DFmode);
12922 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
12924 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
12926 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
12929 emit_move_insn (target, x);
12932 /* Convert an unsigned SImode value into a SFmode, using only SSE.
12933 For x86_32, -mfpmath=sse, !optimize_size only. */
12935 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
12937 REAL_VALUE_TYPE ONE16r;
12938 rtx fp_hi, fp_lo, int_hi, int_lo, x;
12940 real_ldexp (&ONE16r, &dconst1, 16);
12941 x = const_double_from_real_value (ONE16r, SFmode);
12942 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
12943 NULL, 0, OPTAB_DIRECT);
12944 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
12945 NULL, 0, OPTAB_DIRECT);
12946 fp_hi = gen_reg_rtx (SFmode);
12947 fp_lo = gen_reg_rtx (SFmode);
12948 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
12949 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
12950 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
12952 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
12954 if (!rtx_equal_p (target, fp_hi))
12955 emit_move_insn (target, fp_hi);
12958 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
12959 then replicate the value for all elements of the vector
12963 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
12970 v = gen_rtvec (4, value, value, value, value);
12971 return gen_rtx_CONST_VECTOR (V4SImode, v);
12975 v = gen_rtvec (2, value, value);
12976 return gen_rtx_CONST_VECTOR (V2DImode, v);
12980 v = gen_rtvec (4, value, value, value, value);
12982 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
12983 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
12984 return gen_rtx_CONST_VECTOR (V4SFmode, v);
12988 v = gen_rtvec (2, value, value);
12990 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
12991 return gen_rtx_CONST_VECTOR (V2DFmode, v);
12994 gcc_unreachable ();
12998 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
12999 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13000 for an SSE register. If VECT is true, then replicate the mask for
13001 all elements of the vector register. If INVERT is true, then create
13002 a mask excluding the sign bit. */
13005 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13007 enum machine_mode vec_mode, imode;
13008 HOST_WIDE_INT hi, lo;
13013 /* Find the sign bit, sign extended to 2*HWI. */
13019 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13020 lo = 0x80000000, hi = lo < 0;
13026 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13027 if (HOST_BITS_PER_WIDE_INT >= 64)
13028 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13030 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13035 vec_mode = VOIDmode;
13036 if (HOST_BITS_PER_WIDE_INT >= 64)
13039 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13046 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13050 lo = ~lo, hi = ~hi;
13056 mask = immed_double_const (lo, hi, imode);
13058 vec = gen_rtvec (2, v, mask);
13059 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13060 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13067 gcc_unreachable ();
13071 lo = ~lo, hi = ~hi;
13073 /* Force this value into the low part of a fp vector constant. */
13074 mask = immed_double_const (lo, hi, imode);
13075 mask = gen_lowpart (mode, mask);
13077 if (vec_mode == VOIDmode)
13078 return force_reg (mode, mask);
13080 v = ix86_build_const_vector (mode, vect, mask);
13081 return force_reg (vec_mode, v);
13084 /* Generate code for floating point ABS or NEG. */
13087 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13090 rtx mask, set, use, clob, dst, src;
13091 bool use_sse = false;
13092 bool vector_mode = VECTOR_MODE_P (mode);
13093 enum machine_mode elt_mode = mode;
13097 elt_mode = GET_MODE_INNER (mode);
13100 else if (mode == TFmode)
13102 else if (TARGET_SSE_MATH)
13103 use_sse = SSE_FLOAT_MODE_P (mode);
13105 /* NEG and ABS performed with SSE use bitwise mask operations.
13106 Create the appropriate mask now. */
13108 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13117 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13118 set = gen_rtx_SET (VOIDmode, dst, set);
13123 set = gen_rtx_fmt_e (code, mode, src);
13124 set = gen_rtx_SET (VOIDmode, dst, set);
13127 use = gen_rtx_USE (VOIDmode, mask);
13128 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13129 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13130 gen_rtvec (3, set, use, clob)));
13137 /* Expand a copysign operation. Special case operand 0 being a constant. */
13140 ix86_expand_copysign (rtx operands[])
13142 enum machine_mode mode;
13143 rtx dest, op0, op1, mask, nmask;
13145 dest = operands[0];
13149 mode = GET_MODE (dest);
13151 if (GET_CODE (op0) == CONST_DOUBLE)
13153 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13155 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13156 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13158 if (mode == SFmode || mode == DFmode)
13160 enum machine_mode vmode;
13162 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13164 if (op0 == CONST0_RTX (mode))
13165 op0 = CONST0_RTX (vmode);
13170 if (mode == SFmode)
13171 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13172 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13174 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13176 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13179 else if (op0 != CONST0_RTX (mode))
13180 op0 = force_reg (mode, op0);
13182 mask = ix86_build_signbit_mask (mode, 0, 0);
13184 if (mode == SFmode)
13185 copysign_insn = gen_copysignsf3_const;
13186 else if (mode == DFmode)
13187 copysign_insn = gen_copysigndf3_const;
13189 copysign_insn = gen_copysigntf3_const;
13191 emit_insn (copysign_insn (dest, op0, op1, mask));
13195 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13197 nmask = ix86_build_signbit_mask (mode, 0, 1);
13198 mask = ix86_build_signbit_mask (mode, 0, 0);
13200 if (mode == SFmode)
13201 copysign_insn = gen_copysignsf3_var;
13202 else if (mode == DFmode)
13203 copysign_insn = gen_copysigndf3_var;
13205 copysign_insn = gen_copysigntf3_var;
13207 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13211 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13212 be a constant, and so has already been expanded into a vector constant. */
13215 ix86_split_copysign_const (rtx operands[])
13217 enum machine_mode mode, vmode;
13218 rtx dest, op0, op1, mask, x;
13220 dest = operands[0];
13223 mask = operands[3];
13225 mode = GET_MODE (dest);
13226 vmode = GET_MODE (mask);
13228 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13229 x = gen_rtx_AND (vmode, dest, mask);
13230 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13232 if (op0 != CONST0_RTX (vmode))
13234 x = gen_rtx_IOR (vmode, dest, op0);
13235 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13239 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13240 so we have to do two masks. */
13243 ix86_split_copysign_var (rtx operands[])
13245 enum machine_mode mode, vmode;
13246 rtx dest, scratch, op0, op1, mask, nmask, x;
13248 dest = operands[0];
13249 scratch = operands[1];
13252 nmask = operands[4];
13253 mask = operands[5];
13255 mode = GET_MODE (dest);
13256 vmode = GET_MODE (mask);
13258 if (rtx_equal_p (op0, op1))
13260 /* Shouldn't happen often (it's useless, obviously), but when it does
13261 we'd generate incorrect code if we continue below. */
13262 emit_move_insn (dest, op0);
13266 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13268 gcc_assert (REGNO (op1) == REGNO (scratch));
13270 x = gen_rtx_AND (vmode, scratch, mask);
13271 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13274 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13275 x = gen_rtx_NOT (vmode, dest);
13276 x = gen_rtx_AND (vmode, x, op0);
13277 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13281 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13283 x = gen_rtx_AND (vmode, scratch, mask);
13285 else /* alternative 2,4 */
13287 gcc_assert (REGNO (mask) == REGNO (scratch));
13288 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13289 x = gen_rtx_AND (vmode, scratch, op1);
13291 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13293 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13295 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13296 x = gen_rtx_AND (vmode, dest, nmask);
13298 else /* alternative 3,4 */
13300 gcc_assert (REGNO (nmask) == REGNO (dest));
13302 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13303 x = gen_rtx_AND (vmode, dest, op0);
13305 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13308 x = gen_rtx_IOR (vmode, dest, scratch);
13309 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13312 /* Return TRUE or FALSE depending on whether the first SET in INSN
13313 has source and destination with matching CC modes, and that the
13314 CC mode is at least as constrained as REQ_MODE. */
13317 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13320 enum machine_mode set_mode;
13322 set = PATTERN (insn);
13323 if (GET_CODE (set) == PARALLEL)
13324 set = XVECEXP (set, 0, 0);
13325 gcc_assert (GET_CODE (set) == SET);
13326 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13328 set_mode = GET_MODE (SET_DEST (set));
13332 if (req_mode != CCNOmode
13333 && (req_mode != CCmode
13334 || XEXP (SET_SRC (set), 1) != const0_rtx))
13338 if (req_mode == CCGCmode)
13342 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13346 if (req_mode == CCZmode)
13357 gcc_unreachable ();
13360 return (GET_MODE (SET_SRC (set)) == set_mode);
13363 /* Generate insn patterns to do an integer compare of OPERANDS. */
13366 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13368 enum machine_mode cmpmode;
13371 cmpmode = SELECT_CC_MODE (code, op0, op1);
13372 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13374 /* This is very simple, but making the interface the same as in the
13375 FP case makes the rest of the code easier. */
13376 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13377 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13379 /* Return the test that should be put into the flags user, i.e.
13380 the bcc, scc, or cmov instruction. */
13381 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13384 /* Figure out whether to use ordered or unordered fp comparisons.
13385 Return the appropriate mode to use. */
13388 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13390 /* ??? In order to make all comparisons reversible, we do all comparisons
13391 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13392 all forms trapping and nontrapping comparisons, we can make inequality
13393 comparisons trapping again, since it results in better code when using
13394 FCOM based compares. */
13395 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13399 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13401 enum machine_mode mode = GET_MODE (op0);
13403 if (SCALAR_FLOAT_MODE_P (mode))
13405 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13406 return ix86_fp_compare_mode (code);
13411 /* Only zero flag is needed. */
13412 case EQ: /* ZF=0 */
13413 case NE: /* ZF!=0 */
13415 /* Codes needing carry flag. */
13416 case GEU: /* CF=0 */
13417 case LTU: /* CF=1 */
13418 /* Detect overflow checks. They need just the carry flag. */
13419 if (GET_CODE (op0) == PLUS
13420 && rtx_equal_p (op1, XEXP (op0, 0)))
13424 case GTU: /* CF=0 & ZF=0 */
13425 case LEU: /* CF=1 | ZF=1 */
13426 /* Detect overflow checks. They need just the carry flag. */
13427 if (GET_CODE (op0) == MINUS
13428 && rtx_equal_p (op1, XEXP (op0, 0)))
13432 /* Codes possibly doable only with sign flag when
13433 comparing against zero. */
13434 case GE: /* SF=OF or SF=0 */
13435 case LT: /* SF<>OF or SF=1 */
13436 if (op1 == const0_rtx)
13439 /* For other cases Carry flag is not required. */
13441 /* Codes doable only with sign flag when comparing
13442 against zero, but we miss jump instruction for it
13443 so we need to use relational tests against overflow
13444 that thus needs to be zero. */
13445 case GT: /* ZF=0 & SF=OF */
13446 case LE: /* ZF=1 | SF<>OF */
13447 if (op1 == const0_rtx)
13451 /* strcmp pattern do (use flags) and combine may ask us for proper
13456 gcc_unreachable ();
13460 /* Return the fixed registers used for condition codes. */
13463 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13470 /* If two condition code modes are compatible, return a condition code
13471 mode which is compatible with both. Otherwise, return
13474 static enum machine_mode
13475 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13480 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13483 if ((m1 == CCGCmode && m2 == CCGOCmode)
13484 || (m1 == CCGOCmode && m2 == CCGCmode))
13490 gcc_unreachable ();
13520 /* These are only compatible with themselves, which we already
13526 /* Split comparison code CODE into comparisons we can do using branch
13527 instructions. BYPASS_CODE is comparison code for branch that will
13528 branch around FIRST_CODE and SECOND_CODE. If some of branches
13529 is not required, set value to UNKNOWN.
13530 We never require more than two branches. */
13533 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13534 enum rtx_code *first_code,
13535 enum rtx_code *second_code)
13537 *first_code = code;
13538 *bypass_code = UNKNOWN;
13539 *second_code = UNKNOWN;
13541 /* The fcomi comparison sets flags as follows:
13551 case GT: /* GTU - CF=0 & ZF=0 */
13552 case GE: /* GEU - CF=0 */
13553 case ORDERED: /* PF=0 */
13554 case UNORDERED: /* PF=1 */
13555 case UNEQ: /* EQ - ZF=1 */
13556 case UNLT: /* LTU - CF=1 */
13557 case UNLE: /* LEU - CF=1 | ZF=1 */
13558 case LTGT: /* EQ - ZF=0 */
13560 case LT: /* LTU - CF=1 - fails on unordered */
13561 *first_code = UNLT;
13562 *bypass_code = UNORDERED;
13564 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13565 *first_code = UNLE;
13566 *bypass_code = UNORDERED;
13568 case EQ: /* EQ - ZF=1 - fails on unordered */
13569 *first_code = UNEQ;
13570 *bypass_code = UNORDERED;
13572 case NE: /* NE - ZF=0 - fails on unordered */
13573 *first_code = LTGT;
13574 *second_code = UNORDERED;
13576 case UNGE: /* GEU - CF=0 - fails on unordered */
13578 *second_code = UNORDERED;
13580 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13582 *second_code = UNORDERED;
13585 gcc_unreachable ();
13587 if (!TARGET_IEEE_FP)
13589 *second_code = UNKNOWN;
13590 *bypass_code = UNKNOWN;
13594 /* Return cost of comparison done fcom + arithmetics operations on AX.
13595 All following functions do use number of instructions as a cost metrics.
13596 In future this should be tweaked to compute bytes for optimize_size and
13597 take into account performance of various instructions on various CPUs. */
13599 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13601 if (!TARGET_IEEE_FP)
13603 /* The cost of code output by ix86_expand_fp_compare. */
13627 gcc_unreachable ();
13631 /* Return cost of comparison done using fcomi operation.
13632 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13634 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13636 enum rtx_code bypass_code, first_code, second_code;
13637 /* Return arbitrarily high cost when instruction is not supported - this
13638 prevents gcc from using it. */
13641 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13642 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13645 /* Return cost of comparison done using sahf operation.
13646 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13648 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13650 enum rtx_code bypass_code, first_code, second_code;
13651 /* Return arbitrarily high cost when instruction is not preferred - this
13652 avoids gcc from using it. */
13653 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13655 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13656 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13659 /* Compute cost of the comparison done using any method.
13660 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13662 ix86_fp_comparison_cost (enum rtx_code code)
13664 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13667 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13668 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13670 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13671 if (min > sahf_cost)
13673 if (min > fcomi_cost)
13678 /* Return true if we should use an FCOMI instruction for this
13682 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13684 enum rtx_code swapped_code = swap_condition (code);
13686 return ((ix86_fp_comparison_cost (code)
13687 == ix86_fp_comparison_fcomi_cost (code))
13688 || (ix86_fp_comparison_cost (swapped_code)
13689 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13692 /* Swap, force into registers, or otherwise massage the two operands
13693 to a fp comparison. The operands are updated in place; the new
13694 comparison code is returned. */
13696 static enum rtx_code
13697 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13699 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13700 rtx op0 = *pop0, op1 = *pop1;
13701 enum machine_mode op_mode = GET_MODE (op0);
13702 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13704 /* All of the unordered compare instructions only work on registers.
13705 The same is true of the fcomi compare instructions. The XFmode
13706 compare instructions require registers except when comparing
13707 against zero or when converting operand 1 from fixed point to
13711 && (fpcmp_mode == CCFPUmode
13712 || (op_mode == XFmode
13713 && ! (standard_80387_constant_p (op0) == 1
13714 || standard_80387_constant_p (op1) == 1)
13715 && GET_CODE (op1) != FLOAT)
13716 || ix86_use_fcomi_compare (code)))
13718 op0 = force_reg (op_mode, op0);
13719 op1 = force_reg (op_mode, op1);
13723 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13724 things around if they appear profitable, otherwise force op0
13725 into a register. */
13727 if (standard_80387_constant_p (op0) == 0
13729 && ! (standard_80387_constant_p (op1) == 0
13733 tmp = op0, op0 = op1, op1 = tmp;
13734 code = swap_condition (code);
13738 op0 = force_reg (op_mode, op0);
13740 if (CONSTANT_P (op1))
13742 int tmp = standard_80387_constant_p (op1);
13744 op1 = validize_mem (force_const_mem (op_mode, op1));
13748 op1 = force_reg (op_mode, op1);
13751 op1 = force_reg (op_mode, op1);
13755 /* Try to rearrange the comparison to make it cheaper. */
13756 if (ix86_fp_comparison_cost (code)
13757 > ix86_fp_comparison_cost (swap_condition (code))
13758 && (REG_P (op1) || can_create_pseudo_p ()))
13761 tmp = op0, op0 = op1, op1 = tmp;
13762 code = swap_condition (code);
13764 op0 = force_reg (op_mode, op0);
13772 /* Convert comparison codes we use to represent FP comparison to integer
13773 code that will result in proper branch. Return UNKNOWN if no such code
13777 ix86_fp_compare_code_to_integer (enum rtx_code code)
13806 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13809 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13810 rtx *second_test, rtx *bypass_test)
13812 enum machine_mode fpcmp_mode, intcmp_mode;
13814 int cost = ix86_fp_comparison_cost (code);
13815 enum rtx_code bypass_code, first_code, second_code;
13817 fpcmp_mode = ix86_fp_compare_mode (code);
13818 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13821 *second_test = NULL_RTX;
13823 *bypass_test = NULL_RTX;
13825 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13827 /* Do fcomi/sahf based test when profitable. */
13828 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13829 && (bypass_code == UNKNOWN || bypass_test)
13830 && (second_code == UNKNOWN || second_test))
13832 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13833 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13839 gcc_assert (TARGET_SAHF);
13842 scratch = gen_reg_rtx (HImode);
13843 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
13845 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
13848 /* The FP codes work out to act like unsigned. */
13849 intcmp_mode = fpcmp_mode;
13851 if (bypass_code != UNKNOWN)
13852 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
13853 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13855 if (second_code != UNKNOWN)
13856 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
13857 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13862 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13863 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13864 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
13866 scratch = gen_reg_rtx (HImode);
13867 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
13869 /* In the unordered case, we have to check C2 for NaN's, which
13870 doesn't happen to work out to anything nice combination-wise.
13871 So do some bit twiddling on the value we've got in AH to come
13872 up with an appropriate set of condition codes. */
13874 intcmp_mode = CCNOmode;
13879 if (code == GT || !TARGET_IEEE_FP)
13881 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
13886 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13887 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
13888 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
13889 intcmp_mode = CCmode;
13895 if (code == LT && TARGET_IEEE_FP)
13897 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13898 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
13899 intcmp_mode = CCmode;
13904 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
13910 if (code == GE || !TARGET_IEEE_FP)
13912 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
13917 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13918 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
13925 if (code == LE && TARGET_IEEE_FP)
13927 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13928 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
13929 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
13930 intcmp_mode = CCmode;
13935 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
13941 if (code == EQ && TARGET_IEEE_FP)
13943 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13944 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
13945 intcmp_mode = CCmode;
13950 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
13957 if (code == NE && TARGET_IEEE_FP)
13959 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13960 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
13966 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
13972 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
13976 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
13981 gcc_unreachable ();
13985 /* Return the test that should be put into the flags user, i.e.
13986 the bcc, scc, or cmov instruction. */
13987 return gen_rtx_fmt_ee (code, VOIDmode,
13988 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13993 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
13996 op0 = ix86_compare_op0;
13997 op1 = ix86_compare_op1;
14000 *second_test = NULL_RTX;
14002 *bypass_test = NULL_RTX;
14004 if (ix86_compare_emitted)
14006 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14007 ix86_compare_emitted = NULL_RTX;
14009 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14011 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14012 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14013 second_test, bypass_test);
14016 ret = ix86_expand_int_compare (code, op0, op1);
14021 /* Return true if the CODE will result in nontrivial jump sequence. */
14023 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14025 enum rtx_code bypass_code, first_code, second_code;
14028 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14029 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14033 ix86_expand_branch (enum rtx_code code, rtx label)
14037 /* If we have emitted a compare insn, go straight to simple.
14038 ix86_expand_compare won't emit anything if ix86_compare_emitted
14040 if (ix86_compare_emitted)
14043 switch (GET_MODE (ix86_compare_op0))
14049 tmp = ix86_expand_compare (code, NULL, NULL);
14050 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14051 gen_rtx_LABEL_REF (VOIDmode, label),
14053 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14062 enum rtx_code bypass_code, first_code, second_code;
14064 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14065 &ix86_compare_op1);
14067 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14069 /* Check whether we will use the natural sequence with one jump. If
14070 so, we can expand jump early. Otherwise delay expansion by
14071 creating compound insn to not confuse optimizers. */
14072 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14074 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14075 gen_rtx_LABEL_REF (VOIDmode, label),
14076 pc_rtx, NULL_RTX, NULL_RTX);
14080 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14081 ix86_compare_op0, ix86_compare_op1);
14082 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14083 gen_rtx_LABEL_REF (VOIDmode, label),
14085 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14087 use_fcomi = ix86_use_fcomi_compare (code);
14088 vec = rtvec_alloc (3 + !use_fcomi);
14089 RTVEC_ELT (vec, 0) = tmp;
14091 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14093 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14096 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14098 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14107 /* Expand DImode branch into multiple compare+branch. */
14109 rtx lo[2], hi[2], label2;
14110 enum rtx_code code1, code2, code3;
14111 enum machine_mode submode;
14113 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14115 tmp = ix86_compare_op0;
14116 ix86_compare_op0 = ix86_compare_op1;
14117 ix86_compare_op1 = tmp;
14118 code = swap_condition (code);
14120 if (GET_MODE (ix86_compare_op0) == DImode)
14122 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14123 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14128 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14129 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14133 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14134 avoid two branches. This costs one extra insn, so disable when
14135 optimizing for size. */
14137 if ((code == EQ || code == NE)
14138 && (!optimize_insn_for_size_p ()
14139 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14144 if (hi[1] != const0_rtx)
14145 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14146 NULL_RTX, 0, OPTAB_WIDEN);
14149 if (lo[1] != const0_rtx)
14150 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14151 NULL_RTX, 0, OPTAB_WIDEN);
14153 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14154 NULL_RTX, 0, OPTAB_WIDEN);
14156 ix86_compare_op0 = tmp;
14157 ix86_compare_op1 = const0_rtx;
14158 ix86_expand_branch (code, label);
14162 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14163 op1 is a constant and the low word is zero, then we can just
14164 examine the high word. Similarly for low word -1 and
14165 less-or-equal-than or greater-than. */
14167 if (CONST_INT_P (hi[1]))
14170 case LT: case LTU: case GE: case GEU:
14171 if (lo[1] == const0_rtx)
14173 ix86_compare_op0 = hi[0];
14174 ix86_compare_op1 = hi[1];
14175 ix86_expand_branch (code, label);
14179 case LE: case LEU: case GT: case GTU:
14180 if (lo[1] == constm1_rtx)
14182 ix86_compare_op0 = hi[0];
14183 ix86_compare_op1 = hi[1];
14184 ix86_expand_branch (code, label);
14192 /* Otherwise, we need two or three jumps. */
14194 label2 = gen_label_rtx ();
14197 code2 = swap_condition (code);
14198 code3 = unsigned_condition (code);
14202 case LT: case GT: case LTU: case GTU:
14205 case LE: code1 = LT; code2 = GT; break;
14206 case GE: code1 = GT; code2 = LT; break;
14207 case LEU: code1 = LTU; code2 = GTU; break;
14208 case GEU: code1 = GTU; code2 = LTU; break;
14210 case EQ: code1 = UNKNOWN; code2 = NE; break;
14211 case NE: code2 = UNKNOWN; break;
14214 gcc_unreachable ();
14219 * if (hi(a) < hi(b)) goto true;
14220 * if (hi(a) > hi(b)) goto false;
14221 * if (lo(a) < lo(b)) goto true;
14225 ix86_compare_op0 = hi[0];
14226 ix86_compare_op1 = hi[1];
14228 if (code1 != UNKNOWN)
14229 ix86_expand_branch (code1, label);
14230 if (code2 != UNKNOWN)
14231 ix86_expand_branch (code2, label2);
14233 ix86_compare_op0 = lo[0];
14234 ix86_compare_op1 = lo[1];
14235 ix86_expand_branch (code3, label);
14237 if (code2 != UNKNOWN)
14238 emit_label (label2);
14243 gcc_unreachable ();
14247 /* Split branch based on floating point condition. */
14249 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14250 rtx target1, rtx target2, rtx tmp, rtx pushed)
14252 rtx second, bypass;
14253 rtx label = NULL_RTX;
14255 int bypass_probability = -1, second_probability = -1, probability = -1;
14258 if (target2 != pc_rtx)
14261 code = reverse_condition_maybe_unordered (code);
14266 condition = ix86_expand_fp_compare (code, op1, op2,
14267 tmp, &second, &bypass);
14269 /* Remove pushed operand from stack. */
14271 ix86_free_from_memory (GET_MODE (pushed));
14273 if (split_branch_probability >= 0)
14275 /* Distribute the probabilities across the jumps.
14276 Assume the BYPASS and SECOND to be always test
14278 probability = split_branch_probability;
14280 /* Value of 1 is low enough to make no need for probability
14281 to be updated. Later we may run some experiments and see
14282 if unordered values are more frequent in practice. */
14284 bypass_probability = 1;
14286 second_probability = 1;
14288 if (bypass != NULL_RTX)
14290 label = gen_label_rtx ();
14291 i = emit_jump_insn (gen_rtx_SET
14293 gen_rtx_IF_THEN_ELSE (VOIDmode,
14295 gen_rtx_LABEL_REF (VOIDmode,
14298 if (bypass_probability >= 0)
14300 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14301 GEN_INT (bypass_probability),
14304 i = emit_jump_insn (gen_rtx_SET
14306 gen_rtx_IF_THEN_ELSE (VOIDmode,
14307 condition, target1, target2)));
14308 if (probability >= 0)
14310 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14311 GEN_INT (probability),
14313 if (second != NULL_RTX)
14315 i = emit_jump_insn (gen_rtx_SET
14317 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14319 if (second_probability >= 0)
14321 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14322 GEN_INT (second_probability),
14325 if (label != NULL_RTX)
14326 emit_label (label);
14330 ix86_expand_setcc (enum rtx_code code, rtx dest)
14332 rtx ret, tmp, tmpreg, equiv;
14333 rtx second_test, bypass_test;
14335 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14336 return 0; /* FAIL */
14338 gcc_assert (GET_MODE (dest) == QImode);
14340 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14341 PUT_MODE (ret, QImode);
14346 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14347 if (bypass_test || second_test)
14349 rtx test = second_test;
14351 rtx tmp2 = gen_reg_rtx (QImode);
14354 gcc_assert (!second_test);
14355 test = bypass_test;
14357 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14359 PUT_MODE (test, QImode);
14360 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14363 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14365 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14368 /* Attach a REG_EQUAL note describing the comparison result. */
14369 if (ix86_compare_op0 && ix86_compare_op1)
14371 equiv = simplify_gen_relational (code, QImode,
14372 GET_MODE (ix86_compare_op0),
14373 ix86_compare_op0, ix86_compare_op1);
14374 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14377 return 1; /* DONE */
14380 /* Expand comparison setting or clearing carry flag. Return true when
14381 successful and set pop for the operation. */
14383 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14385 enum machine_mode mode =
14386 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14388 /* Do not handle DImode compares that go through special path. */
14389 if (mode == (TARGET_64BIT ? TImode : DImode))
14392 if (SCALAR_FLOAT_MODE_P (mode))
14394 rtx second_test = NULL, bypass_test = NULL;
14395 rtx compare_op, compare_seq;
14397 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14399 /* Shortcut: following common codes never translate
14400 into carry flag compares. */
14401 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14402 || code == ORDERED || code == UNORDERED)
14405 /* These comparisons require zero flag; swap operands so they won't. */
14406 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14407 && !TARGET_IEEE_FP)
14412 code = swap_condition (code);
14415 /* Try to expand the comparison and verify that we end up with
14416 carry flag based comparison. This fails to be true only when
14417 we decide to expand comparison using arithmetic that is not
14418 too common scenario. */
14420 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14421 &second_test, &bypass_test);
14422 compare_seq = get_insns ();
14425 if (second_test || bypass_test)
14428 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14429 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14430 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14432 code = GET_CODE (compare_op);
14434 if (code != LTU && code != GEU)
14437 emit_insn (compare_seq);
14442 if (!INTEGRAL_MODE_P (mode))
14451 /* Convert a==0 into (unsigned)a<1. */
14454 if (op1 != const0_rtx)
14457 code = (code == EQ ? LTU : GEU);
14460 /* Convert a>b into b<a or a>=b-1. */
14463 if (CONST_INT_P (op1))
14465 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14466 /* Bail out on overflow. We still can swap operands but that
14467 would force loading of the constant into register. */
14468 if (op1 == const0_rtx
14469 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14471 code = (code == GTU ? GEU : LTU);
14478 code = (code == GTU ? LTU : GEU);
14482 /* Convert a>=0 into (unsigned)a<0x80000000. */
14485 if (mode == DImode || op1 != const0_rtx)
14487 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14488 code = (code == LT ? GEU : LTU);
14492 if (mode == DImode || op1 != constm1_rtx)
14494 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14495 code = (code == LE ? GEU : LTU);
14501 /* Swapping operands may cause constant to appear as first operand. */
14502 if (!nonimmediate_operand (op0, VOIDmode))
14504 if (!can_create_pseudo_p ())
14506 op0 = force_reg (mode, op0);
14508 ix86_compare_op0 = op0;
14509 ix86_compare_op1 = op1;
14510 *pop = ix86_expand_compare (code, NULL, NULL);
14511 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14516 ix86_expand_int_movcc (rtx operands[])
14518 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14519 rtx compare_seq, compare_op;
14520 rtx second_test, bypass_test;
14521 enum machine_mode mode = GET_MODE (operands[0]);
14522 bool sign_bit_compare_p = false;;
14525 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14526 compare_seq = get_insns ();
14529 compare_code = GET_CODE (compare_op);
14531 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14532 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14533 sign_bit_compare_p = true;
14535 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14536 HImode insns, we'd be swallowed in word prefix ops. */
14538 if ((mode != HImode || TARGET_FAST_PREFIX)
14539 && (mode != (TARGET_64BIT ? TImode : DImode))
14540 && CONST_INT_P (operands[2])
14541 && CONST_INT_P (operands[3]))
14543 rtx out = operands[0];
14544 HOST_WIDE_INT ct = INTVAL (operands[2]);
14545 HOST_WIDE_INT cf = INTVAL (operands[3]);
14546 HOST_WIDE_INT diff;
14549 /* Sign bit compares are better done using shifts than we do by using
14551 if (sign_bit_compare_p
14552 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14553 ix86_compare_op1, &compare_op))
14555 /* Detect overlap between destination and compare sources. */
14558 if (!sign_bit_compare_p)
14560 bool fpcmp = false;
14562 compare_code = GET_CODE (compare_op);
14564 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14565 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14568 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14571 /* To simplify rest of code, restrict to the GEU case. */
14572 if (compare_code == LTU)
14574 HOST_WIDE_INT tmp = ct;
14577 compare_code = reverse_condition (compare_code);
14578 code = reverse_condition (code);
14583 PUT_CODE (compare_op,
14584 reverse_condition_maybe_unordered
14585 (GET_CODE (compare_op)));
14587 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14591 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14592 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14593 tmp = gen_reg_rtx (mode);
14595 if (mode == DImode)
14596 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14598 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14602 if (code == GT || code == GE)
14603 code = reverse_condition (code);
14606 HOST_WIDE_INT tmp = ct;
14611 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14612 ix86_compare_op1, VOIDmode, 0, -1);
14625 tmp = expand_simple_binop (mode, PLUS,
14627 copy_rtx (tmp), 1, OPTAB_DIRECT);
14638 tmp = expand_simple_binop (mode, IOR,
14640 copy_rtx (tmp), 1, OPTAB_DIRECT);
14642 else if (diff == -1 && ct)
14652 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14654 tmp = expand_simple_binop (mode, PLUS,
14655 copy_rtx (tmp), GEN_INT (cf),
14656 copy_rtx (tmp), 1, OPTAB_DIRECT);
14664 * andl cf - ct, dest
14674 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14677 tmp = expand_simple_binop (mode, AND,
14679 gen_int_mode (cf - ct, mode),
14680 copy_rtx (tmp), 1, OPTAB_DIRECT);
14682 tmp = expand_simple_binop (mode, PLUS,
14683 copy_rtx (tmp), GEN_INT (ct),
14684 copy_rtx (tmp), 1, OPTAB_DIRECT);
14687 if (!rtx_equal_p (tmp, out))
14688 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14690 return 1; /* DONE */
14695 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14698 tmp = ct, ct = cf, cf = tmp;
14701 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14703 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14705 /* We may be reversing unordered compare to normal compare, that
14706 is not valid in general (we may convert non-trapping condition
14707 to trapping one), however on i386 we currently emit all
14708 comparisons unordered. */
14709 compare_code = reverse_condition_maybe_unordered (compare_code);
14710 code = reverse_condition_maybe_unordered (code);
14714 compare_code = reverse_condition (compare_code);
14715 code = reverse_condition (code);
14719 compare_code = UNKNOWN;
14720 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14721 && CONST_INT_P (ix86_compare_op1))
14723 if (ix86_compare_op1 == const0_rtx
14724 && (code == LT || code == GE))
14725 compare_code = code;
14726 else if (ix86_compare_op1 == constm1_rtx)
14730 else if (code == GT)
14735 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14736 if (compare_code != UNKNOWN
14737 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14738 && (cf == -1 || ct == -1))
14740 /* If lea code below could be used, only optimize
14741 if it results in a 2 insn sequence. */
14743 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14744 || diff == 3 || diff == 5 || diff == 9)
14745 || (compare_code == LT && ct == -1)
14746 || (compare_code == GE && cf == -1))
14749 * notl op1 (if necessary)
14757 code = reverse_condition (code);
14760 out = emit_store_flag (out, code, ix86_compare_op0,
14761 ix86_compare_op1, VOIDmode, 0, -1);
14763 out = expand_simple_binop (mode, IOR,
14765 out, 1, OPTAB_DIRECT);
14766 if (out != operands[0])
14767 emit_move_insn (operands[0], out);
14769 return 1; /* DONE */
14774 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14775 || diff == 3 || diff == 5 || diff == 9)
14776 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14778 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14784 * lea cf(dest*(ct-cf)),dest
14788 * This also catches the degenerate setcc-only case.
14794 out = emit_store_flag (out, code, ix86_compare_op0,
14795 ix86_compare_op1, VOIDmode, 0, 1);
14798 /* On x86_64 the lea instruction operates on Pmode, so we need
14799 to get arithmetics done in proper mode to match. */
14801 tmp = copy_rtx (out);
14805 out1 = copy_rtx (out);
14806 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14810 tmp = gen_rtx_PLUS (mode, tmp, out1);
14816 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14819 if (!rtx_equal_p (tmp, out))
14822 out = force_operand (tmp, copy_rtx (out));
14824 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14826 if (!rtx_equal_p (out, operands[0]))
14827 emit_move_insn (operands[0], copy_rtx (out));
14829 return 1; /* DONE */
14833 * General case: Jumpful:
14834 * xorl dest,dest cmpl op1, op2
14835 * cmpl op1, op2 movl ct, dest
14836 * setcc dest jcc 1f
14837 * decl dest movl cf, dest
14838 * andl (cf-ct),dest 1:
14841 * Size 20. Size 14.
14843 * This is reasonably steep, but branch mispredict costs are
14844 * high on modern cpus, so consider failing only if optimizing
14848 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14849 && BRANCH_COST (optimize_insn_for_speed_p (),
14854 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14859 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14861 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14863 /* We may be reversing unordered compare to normal compare,
14864 that is not valid in general (we may convert non-trapping
14865 condition to trapping one), however on i386 we currently
14866 emit all comparisons unordered. */
14867 code = reverse_condition_maybe_unordered (code);
14871 code = reverse_condition (code);
14872 if (compare_code != UNKNOWN)
14873 compare_code = reverse_condition (compare_code);
14877 if (compare_code != UNKNOWN)
14879 /* notl op1 (if needed)
14884 For x < 0 (resp. x <= -1) there will be no notl,
14885 so if possible swap the constants to get rid of the
14887 True/false will be -1/0 while code below (store flag
14888 followed by decrement) is 0/-1, so the constants need
14889 to be exchanged once more. */
14891 if (compare_code == GE || !cf)
14893 code = reverse_condition (code);
14898 HOST_WIDE_INT tmp = cf;
14903 out = emit_store_flag (out, code, ix86_compare_op0,
14904 ix86_compare_op1, VOIDmode, 0, -1);
14908 out = emit_store_flag (out, code, ix86_compare_op0,
14909 ix86_compare_op1, VOIDmode, 0, 1);
14911 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
14912 copy_rtx (out), 1, OPTAB_DIRECT);
14915 out = expand_simple_binop (mode, AND, copy_rtx (out),
14916 gen_int_mode (cf - ct, mode),
14917 copy_rtx (out), 1, OPTAB_DIRECT);
14919 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
14920 copy_rtx (out), 1, OPTAB_DIRECT);
14921 if (!rtx_equal_p (out, operands[0]))
14922 emit_move_insn (operands[0], copy_rtx (out));
14924 return 1; /* DONE */
14928 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14930 /* Try a few things more with specific constants and a variable. */
14933 rtx var, orig_out, out, tmp;
14935 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
14936 return 0; /* FAIL */
14938 /* If one of the two operands is an interesting constant, load a
14939 constant with the above and mask it in with a logical operation. */
14941 if (CONST_INT_P (operands[2]))
14944 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
14945 operands[3] = constm1_rtx, op = and_optab;
14946 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
14947 operands[3] = const0_rtx, op = ior_optab;
14949 return 0; /* FAIL */
14951 else if (CONST_INT_P (operands[3]))
14954 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
14955 operands[2] = constm1_rtx, op = and_optab;
14956 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
14957 operands[2] = const0_rtx, op = ior_optab;
14959 return 0; /* FAIL */
14962 return 0; /* FAIL */
14964 orig_out = operands[0];
14965 tmp = gen_reg_rtx (mode);
14968 /* Recurse to get the constant loaded. */
14969 if (ix86_expand_int_movcc (operands) == 0)
14970 return 0; /* FAIL */
14972 /* Mask in the interesting variable. */
14973 out = expand_binop (mode, op, var, tmp, orig_out, 0,
14975 if (!rtx_equal_p (out, orig_out))
14976 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
14978 return 1; /* DONE */
14982 * For comparison with above,
14992 if (! nonimmediate_operand (operands[2], mode))
14993 operands[2] = force_reg (mode, operands[2]);
14994 if (! nonimmediate_operand (operands[3], mode))
14995 operands[3] = force_reg (mode, operands[3]);
14997 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
14999 rtx tmp = gen_reg_rtx (mode);
15000 emit_move_insn (tmp, operands[3]);
15003 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15005 rtx tmp = gen_reg_rtx (mode);
15006 emit_move_insn (tmp, operands[2]);
15010 if (! register_operand (operands[2], VOIDmode)
15012 || ! register_operand (operands[3], VOIDmode)))
15013 operands[2] = force_reg (mode, operands[2]);
15016 && ! register_operand (operands[3], VOIDmode))
15017 operands[3] = force_reg (mode, operands[3]);
15019 emit_insn (compare_seq);
15020 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15021 gen_rtx_IF_THEN_ELSE (mode,
15022 compare_op, operands[2],
15025 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15026 gen_rtx_IF_THEN_ELSE (mode,
15028 copy_rtx (operands[3]),
15029 copy_rtx (operands[0]))));
15031 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15032 gen_rtx_IF_THEN_ELSE (mode,
15034 copy_rtx (operands[2]),
15035 copy_rtx (operands[0]))));
15037 return 1; /* DONE */
15040 /* Swap, force into registers, or otherwise massage the two operands
15041 to an sse comparison with a mask result. Thus we differ a bit from
15042 ix86_prepare_fp_compare_args which expects to produce a flags result.
15044 The DEST operand exists to help determine whether to commute commutative
15045 operators. The POP0/POP1 operands are updated in place. The new
15046 comparison code is returned, or UNKNOWN if not implementable. */
15048 static enum rtx_code
15049 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15050 rtx *pop0, rtx *pop1)
15058 /* We have no LTGT as an operator. We could implement it with
15059 NE & ORDERED, but this requires an extra temporary. It's
15060 not clear that it's worth it. */
15067 /* These are supported directly. */
15074 /* For commutative operators, try to canonicalize the destination
15075 operand to be first in the comparison - this helps reload to
15076 avoid extra moves. */
15077 if (!dest || !rtx_equal_p (dest, *pop1))
15085 /* These are not supported directly. Swap the comparison operands
15086 to transform into something that is supported. */
15090 code = swap_condition (code);
15094 gcc_unreachable ();
15100 /* Detect conditional moves that exactly match min/max operational
15101 semantics. Note that this is IEEE safe, as long as we don't
15102 interchange the operands.
15104 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15105 and TRUE if the operation is successful and instructions are emitted. */
15108 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15109 rtx cmp_op1, rtx if_true, rtx if_false)
15111 enum machine_mode mode;
15117 else if (code == UNGE)
15120 if_true = if_false;
15126 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15128 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15133 mode = GET_MODE (dest);
15135 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15136 but MODE may be a vector mode and thus not appropriate. */
15137 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15139 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15142 if_true = force_reg (mode, if_true);
15143 v = gen_rtvec (2, if_true, if_false);
15144 tmp = gen_rtx_UNSPEC (mode, v, u);
15148 code = is_min ? SMIN : SMAX;
15149 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15152 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15156 /* Expand an sse vector comparison. Return the register with the result. */
15159 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15160 rtx op_true, rtx op_false)
15162 enum machine_mode mode = GET_MODE (dest);
15165 cmp_op0 = force_reg (mode, cmp_op0);
15166 if (!nonimmediate_operand (cmp_op1, mode))
15167 cmp_op1 = force_reg (mode, cmp_op1);
15170 || reg_overlap_mentioned_p (dest, op_true)
15171 || reg_overlap_mentioned_p (dest, op_false))
15172 dest = gen_reg_rtx (mode);
15174 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15175 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15180 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15181 operations. This is used for both scalar and vector conditional moves. */
15184 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15186 enum machine_mode mode = GET_MODE (dest);
15189 if (op_false == CONST0_RTX (mode))
15191 op_true = force_reg (mode, op_true);
15192 x = gen_rtx_AND (mode, cmp, op_true);
15193 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15195 else if (op_true == CONST0_RTX (mode))
15197 op_false = force_reg (mode, op_false);
15198 x = gen_rtx_NOT (mode, cmp);
15199 x = gen_rtx_AND (mode, x, op_false);
15200 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15202 else if (TARGET_SSE5)
15204 rtx pcmov = gen_rtx_SET (mode, dest,
15205 gen_rtx_IF_THEN_ELSE (mode, cmp,
15212 op_true = force_reg (mode, op_true);
15213 op_false = force_reg (mode, op_false);
15215 t2 = gen_reg_rtx (mode);
15217 t3 = gen_reg_rtx (mode);
15221 x = gen_rtx_AND (mode, op_true, cmp);
15222 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15224 x = gen_rtx_NOT (mode, cmp);
15225 x = gen_rtx_AND (mode, x, op_false);
15226 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15228 x = gen_rtx_IOR (mode, t3, t2);
15229 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15233 /* Expand a floating-point conditional move. Return true if successful. */
15236 ix86_expand_fp_movcc (rtx operands[])
15238 enum machine_mode mode = GET_MODE (operands[0]);
15239 enum rtx_code code = GET_CODE (operands[1]);
15240 rtx tmp, compare_op, second_test, bypass_test;
15242 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15244 enum machine_mode cmode;
15246 /* Since we've no cmove for sse registers, don't force bad register
15247 allocation just to gain access to it. Deny movcc when the
15248 comparison mode doesn't match the move mode. */
15249 cmode = GET_MODE (ix86_compare_op0);
15250 if (cmode == VOIDmode)
15251 cmode = GET_MODE (ix86_compare_op1);
15255 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15257 &ix86_compare_op1);
15258 if (code == UNKNOWN)
15261 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15262 ix86_compare_op1, operands[2],
15266 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15267 ix86_compare_op1, operands[2], operands[3]);
15268 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15272 /* The floating point conditional move instructions don't directly
15273 support conditions resulting from a signed integer comparison. */
15275 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15277 /* The floating point conditional move instructions don't directly
15278 support signed integer comparisons. */
15280 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15282 gcc_assert (!second_test && !bypass_test);
15283 tmp = gen_reg_rtx (QImode);
15284 ix86_expand_setcc (code, tmp);
15286 ix86_compare_op0 = tmp;
15287 ix86_compare_op1 = const0_rtx;
15288 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15290 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15292 tmp = gen_reg_rtx (mode);
15293 emit_move_insn (tmp, operands[3]);
15296 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15298 tmp = gen_reg_rtx (mode);
15299 emit_move_insn (tmp, operands[2]);
15303 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15304 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15305 operands[2], operands[3])));
15307 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15308 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15309 operands[3], operands[0])));
15311 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15312 gen_rtx_IF_THEN_ELSE (mode, second_test,
15313 operands[2], operands[0])));
15318 /* Expand a floating-point vector conditional move; a vcond operation
15319 rather than a movcc operation. */
15322 ix86_expand_fp_vcond (rtx operands[])
15324 enum rtx_code code = GET_CODE (operands[3]);
15327 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15328 &operands[4], &operands[5]);
15329 if (code == UNKNOWN)
15332 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15333 operands[5], operands[1], operands[2]))
15336 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15337 operands[1], operands[2]);
15338 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15342 /* Expand a signed/unsigned integral vector conditional move. */
15345 ix86_expand_int_vcond (rtx operands[])
15347 enum machine_mode mode = GET_MODE (operands[0]);
15348 enum rtx_code code = GET_CODE (operands[3]);
15349 bool negate = false;
15352 cop0 = operands[4];
15353 cop1 = operands[5];
15355 /* SSE5 supports all of the comparisons on all vector int types. */
15358 /* Canonicalize the comparison to EQ, GT, GTU. */
15369 code = reverse_condition (code);
15375 code = reverse_condition (code);
15381 code = swap_condition (code);
15382 x = cop0, cop0 = cop1, cop1 = x;
15386 gcc_unreachable ();
15389 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15390 if (mode == V2DImode)
15395 /* SSE4.1 supports EQ. */
15396 if (!TARGET_SSE4_1)
15402 /* SSE4.2 supports GT/GTU. */
15403 if (!TARGET_SSE4_2)
15408 gcc_unreachable ();
15412 /* Unsigned parallel compare is not supported by the hardware. Play some
15413 tricks to turn this into a signed comparison against 0. */
15416 cop0 = force_reg (mode, cop0);
15425 /* Perform a parallel modulo subtraction. */
15426 t1 = gen_reg_rtx (mode);
15427 emit_insn ((mode == V4SImode
15429 : gen_subv2di3) (t1, cop0, cop1));
15431 /* Extract the original sign bit of op0. */
15432 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15434 t2 = gen_reg_rtx (mode);
15435 emit_insn ((mode == V4SImode
15437 : gen_andv2di3) (t2, cop0, mask));
15439 /* XOR it back into the result of the subtraction. This results
15440 in the sign bit set iff we saw unsigned underflow. */
15441 x = gen_reg_rtx (mode);
15442 emit_insn ((mode == V4SImode
15444 : gen_xorv2di3) (x, t1, t2));
15452 /* Perform a parallel unsigned saturating subtraction. */
15453 x = gen_reg_rtx (mode);
15454 emit_insn (gen_rtx_SET (VOIDmode, x,
15455 gen_rtx_US_MINUS (mode, cop0, cop1)));
15462 gcc_unreachable ();
15466 cop1 = CONST0_RTX (mode);
15470 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15471 operands[1+negate], operands[2-negate]);
15473 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15474 operands[2-negate]);
15478 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15479 true if we should do zero extension, else sign extension. HIGH_P is
15480 true if we want the N/2 high elements, else the low elements. */
15483 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15485 enum machine_mode imode = GET_MODE (operands[1]);
15486 rtx (*unpack)(rtx, rtx, rtx);
15493 unpack = gen_vec_interleave_highv16qi;
15495 unpack = gen_vec_interleave_lowv16qi;
15499 unpack = gen_vec_interleave_highv8hi;
15501 unpack = gen_vec_interleave_lowv8hi;
15505 unpack = gen_vec_interleave_highv4si;
15507 unpack = gen_vec_interleave_lowv4si;
15510 gcc_unreachable ();
15513 dest = gen_lowpart (imode, operands[0]);
15516 se = force_reg (imode, CONST0_RTX (imode));
15518 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15519 operands[1], pc_rtx, pc_rtx);
15521 emit_insn (unpack (dest, operands[1], se));
15524 /* This function performs the same task as ix86_expand_sse_unpack,
15525 but with SSE4.1 instructions. */
15528 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15530 enum machine_mode imode = GET_MODE (operands[1]);
15531 rtx (*unpack)(rtx, rtx);
15538 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15540 unpack = gen_sse4_1_extendv8qiv8hi2;
15544 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15546 unpack = gen_sse4_1_extendv4hiv4si2;
15550 unpack = gen_sse4_1_zero_extendv2siv2di2;
15552 unpack = gen_sse4_1_extendv2siv2di2;
15555 gcc_unreachable ();
15558 dest = operands[0];
15561 /* Shift higher 8 bytes to lower 8 bytes. */
15562 src = gen_reg_rtx (imode);
15563 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15564 gen_lowpart (TImode, operands[1]),
15570 emit_insn (unpack (dest, src));
15573 /* This function performs the same task as ix86_expand_sse_unpack,
15574 but with sse5 instructions. */
15577 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15579 enum machine_mode imode = GET_MODE (operands[1]);
15580 int pperm_bytes[16];
15582 int h = (high_p) ? 8 : 0;
15585 rtvec v = rtvec_alloc (16);
15588 rtx op0 = operands[0], op1 = operands[1];
15593 vs = rtvec_alloc (8);
15594 h2 = (high_p) ? 8 : 0;
15595 for (i = 0; i < 8; i++)
15597 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15598 pperm_bytes[2*i+1] = ((unsigned_p)
15600 : PPERM_SIGN | PPERM_SRC2 | i | h);
15603 for (i = 0; i < 16; i++)
15604 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15606 for (i = 0; i < 8; i++)
15607 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15609 p = gen_rtx_PARALLEL (VOIDmode, vs);
15610 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15612 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15614 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15618 vs = rtvec_alloc (4);
15619 h2 = (high_p) ? 4 : 0;
15620 for (i = 0; i < 4; i++)
15622 sign_extend = ((unsigned_p)
15624 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15625 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15626 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15627 pperm_bytes[4*i+2] = sign_extend;
15628 pperm_bytes[4*i+3] = sign_extend;
15631 for (i = 0; i < 16; i++)
15632 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15634 for (i = 0; i < 4; i++)
15635 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15637 p = gen_rtx_PARALLEL (VOIDmode, vs);
15638 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15640 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15642 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15646 vs = rtvec_alloc (2);
15647 h2 = (high_p) ? 2 : 0;
15648 for (i = 0; i < 2; i++)
15650 sign_extend = ((unsigned_p)
15652 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15653 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15654 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15655 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15656 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15657 pperm_bytes[8*i+4] = sign_extend;
15658 pperm_bytes[8*i+5] = sign_extend;
15659 pperm_bytes[8*i+6] = sign_extend;
15660 pperm_bytes[8*i+7] = sign_extend;
15663 for (i = 0; i < 16; i++)
15664 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15666 for (i = 0; i < 2; i++)
15667 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15669 p = gen_rtx_PARALLEL (VOIDmode, vs);
15670 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15672 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15674 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15678 gcc_unreachable ();
15684 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15685 next narrower integer vector type */
15687 ix86_expand_sse5_pack (rtx operands[3])
15689 enum machine_mode imode = GET_MODE (operands[0]);
15690 int pperm_bytes[16];
15692 rtvec v = rtvec_alloc (16);
15694 rtx op0 = operands[0];
15695 rtx op1 = operands[1];
15696 rtx op2 = operands[2];
15701 for (i = 0; i < 8; i++)
15703 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15704 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15707 for (i = 0; i < 16; i++)
15708 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15710 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15711 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15715 for (i = 0; i < 4; i++)
15717 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15718 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15719 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15720 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15723 for (i = 0; i < 16; i++)
15724 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15726 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15727 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15731 for (i = 0; i < 2; i++)
15733 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15734 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15735 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15736 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15737 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15738 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15739 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15740 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15743 for (i = 0; i < 16; i++)
15744 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15746 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15747 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15751 gcc_unreachable ();
15757 /* Expand conditional increment or decrement using adb/sbb instructions.
15758 The default case using setcc followed by the conditional move can be
15759 done by generic code. */
15761 ix86_expand_int_addcc (rtx operands[])
15763 enum rtx_code code = GET_CODE (operands[1]);
15765 rtx val = const0_rtx;
15766 bool fpcmp = false;
15767 enum machine_mode mode = GET_MODE (operands[0]);
15769 if (operands[3] != const1_rtx
15770 && operands[3] != constm1_rtx)
15772 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15773 ix86_compare_op1, &compare_op))
15775 code = GET_CODE (compare_op);
15777 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15778 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15781 code = ix86_fp_compare_code_to_integer (code);
15788 PUT_CODE (compare_op,
15789 reverse_condition_maybe_unordered
15790 (GET_CODE (compare_op)));
15792 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15794 PUT_MODE (compare_op, mode);
15796 /* Construct either adc or sbb insn. */
15797 if ((code == LTU) == (operands[3] == constm1_rtx))
15799 switch (GET_MODE (operands[0]))
15802 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15805 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15808 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15811 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15814 gcc_unreachable ();
15819 switch (GET_MODE (operands[0]))
15822 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15825 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15828 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15831 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15834 gcc_unreachable ();
15837 return 1; /* DONE */
15841 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15842 works for floating pointer parameters and nonoffsetable memories.
15843 For pushes, it returns just stack offsets; the values will be saved
15844 in the right order. Maximally three parts are generated. */
15847 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
15852 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
15854 size = (GET_MODE_SIZE (mode) + 4) / 8;
15856 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
15857 gcc_assert (size >= 2 && size <= 4);
15859 /* Optimize constant pool reference to immediates. This is used by fp
15860 moves, that force all constants to memory to allow combining. */
15861 if (MEM_P (operand) && MEM_READONLY_P (operand))
15863 rtx tmp = maybe_get_pool_constant (operand);
15868 if (MEM_P (operand) && !offsettable_memref_p (operand))
15870 /* The only non-offsetable memories we handle are pushes. */
15871 int ok = push_operand (operand, VOIDmode);
15875 operand = copy_rtx (operand);
15876 PUT_MODE (operand, Pmode);
15877 parts[0] = parts[1] = parts[2] = parts[3] = operand;
15881 if (GET_CODE (operand) == CONST_VECTOR)
15883 enum machine_mode imode = int_mode_for_mode (mode);
15884 /* Caution: if we looked through a constant pool memory above,
15885 the operand may actually have a different mode now. That's
15886 ok, since we want to pun this all the way back to an integer. */
15887 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
15888 gcc_assert (operand != NULL);
15894 if (mode == DImode)
15895 split_di (&operand, 1, &parts[0], &parts[1]);
15900 if (REG_P (operand))
15902 gcc_assert (reload_completed);
15903 for (i = 0; i < size; i++)
15904 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
15906 else if (offsettable_memref_p (operand))
15908 operand = adjust_address (operand, SImode, 0);
15909 parts[0] = operand;
15910 for (i = 1; i < size; i++)
15911 parts[i] = adjust_address (operand, SImode, 4 * i);
15913 else if (GET_CODE (operand) == CONST_DOUBLE)
15918 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
15922 real_to_target (l, &r, mode);
15923 parts[3] = gen_int_mode (l[3], SImode);
15924 parts[2] = gen_int_mode (l[2], SImode);
15927 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
15928 parts[2] = gen_int_mode (l[2], SImode);
15931 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
15934 gcc_unreachable ();
15936 parts[1] = gen_int_mode (l[1], SImode);
15937 parts[0] = gen_int_mode (l[0], SImode);
15940 gcc_unreachable ();
15945 if (mode == TImode)
15946 split_ti (&operand, 1, &parts[0], &parts[1]);
15947 if (mode == XFmode || mode == TFmode)
15949 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
15950 if (REG_P (operand))
15952 gcc_assert (reload_completed);
15953 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
15954 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
15956 else if (offsettable_memref_p (operand))
15958 operand = adjust_address (operand, DImode, 0);
15959 parts[0] = operand;
15960 parts[1] = adjust_address (operand, upper_mode, 8);
15962 else if (GET_CODE (operand) == CONST_DOUBLE)
15967 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
15968 real_to_target (l, &r, mode);
15970 /* Do not use shift by 32 to avoid warning on 32bit systems. */
15971 if (HOST_BITS_PER_WIDE_INT >= 64)
15974 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
15975 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
15978 parts[0] = immed_double_const (l[0], l[1], DImode);
15980 if (upper_mode == SImode)
15981 parts[1] = gen_int_mode (l[2], SImode);
15982 else if (HOST_BITS_PER_WIDE_INT >= 64)
15985 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
15986 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
15989 parts[1] = immed_double_const (l[2], l[3], DImode);
15992 gcc_unreachable ();
15999 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16000 Return false when normal moves are needed; true when all required
16001 insns have been emitted. Operands 2-4 contain the input values
16002 int the correct order; operands 5-7 contain the output values. */
16005 ix86_split_long_move (rtx operands[])
16010 int collisions = 0;
16011 enum machine_mode mode = GET_MODE (operands[0]);
16012 bool collisionparts[4];
16014 /* The DFmode expanders may ask us to move double.
16015 For 64bit target this is single move. By hiding the fact
16016 here we simplify i386.md splitters. */
16017 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16019 /* Optimize constant pool reference to immediates. This is used by
16020 fp moves, that force all constants to memory to allow combining. */
16022 if (MEM_P (operands[1])
16023 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16024 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16025 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16026 if (push_operand (operands[0], VOIDmode))
16028 operands[0] = copy_rtx (operands[0]);
16029 PUT_MODE (operands[0], Pmode);
16032 operands[0] = gen_lowpart (DImode, operands[0]);
16033 operands[1] = gen_lowpart (DImode, operands[1]);
16034 emit_move_insn (operands[0], operands[1]);
16038 /* The only non-offsettable memory we handle is push. */
16039 if (push_operand (operands[0], VOIDmode))
16042 gcc_assert (!MEM_P (operands[0])
16043 || offsettable_memref_p (operands[0]));
16045 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16046 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16048 /* When emitting push, take care for source operands on the stack. */
16049 if (push && MEM_P (operands[1])
16050 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16051 for (i = 0; i < nparts - 1; i++)
16052 part[1][i] = change_address (part[1][i],
16053 GET_MODE (part[1][i]),
16054 XEXP (part[1][i + 1], 0));
16056 /* We need to do copy in the right order in case an address register
16057 of the source overlaps the destination. */
16058 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16062 for (i = 0; i < nparts; i++)
16065 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16066 if (collisionparts[i])
16070 /* Collision in the middle part can be handled by reordering. */
16071 if (collisions == 1 && nparts == 3 && collisionparts [1])
16073 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16074 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16076 else if (collisions == 1
16078 && (collisionparts [1] || collisionparts [2]))
16080 if (collisionparts [1])
16082 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16083 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16087 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16088 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16092 /* If there are more collisions, we can't handle it by reordering.
16093 Do an lea to the last part and use only one colliding move. */
16094 else if (collisions > 1)
16100 base = part[0][nparts - 1];
16102 /* Handle the case when the last part isn't valid for lea.
16103 Happens in 64-bit mode storing the 12-byte XFmode. */
16104 if (GET_MODE (base) != Pmode)
16105 base = gen_rtx_REG (Pmode, REGNO (base));
16107 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16108 part[1][0] = replace_equiv_address (part[1][0], base);
16109 for (i = 1; i < nparts; i++)
16111 tmp = plus_constant (base, UNITS_PER_WORD * i);
16112 part[1][i] = replace_equiv_address (part[1][i], tmp);
16123 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16124 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
16125 emit_move_insn (part[0][2], part[1][2]);
16127 else if (nparts == 4)
16129 emit_move_insn (part[0][3], part[1][3]);
16130 emit_move_insn (part[0][2], part[1][2]);
16135 /* In 64bit mode we don't have 32bit push available. In case this is
16136 register, it is OK - we will just use larger counterpart. We also
16137 retype memory - these comes from attempt to avoid REX prefix on
16138 moving of second half of TFmode value. */
16139 if (GET_MODE (part[1][1]) == SImode)
16141 switch (GET_CODE (part[1][1]))
16144 part[1][1] = adjust_address (part[1][1], DImode, 0);
16148 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16152 gcc_unreachable ();
16155 if (GET_MODE (part[1][0]) == SImode)
16156 part[1][0] = part[1][1];
16159 emit_move_insn (part[0][1], part[1][1]);
16160 emit_move_insn (part[0][0], part[1][0]);
16164 /* Choose correct order to not overwrite the source before it is copied. */
16165 if ((REG_P (part[0][0])
16166 && REG_P (part[1][1])
16167 && (REGNO (part[0][0]) == REGNO (part[1][1])
16169 && REGNO (part[0][0]) == REGNO (part[1][2]))
16171 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16173 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16175 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16177 operands[2 + i] = part[0][j];
16178 operands[6 + i] = part[1][j];
16183 for (i = 0; i < nparts; i++)
16185 operands[2 + i] = part[0][i];
16186 operands[6 + i] = part[1][i];
16190 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16191 if (optimize_insn_for_size_p ())
16193 for (j = 0; j < nparts - 1; j++)
16194 if (CONST_INT_P (operands[6 + j])
16195 && operands[6 + j] != const0_rtx
16196 && REG_P (operands[2 + j]))
16197 for (i = j; i < nparts - 1; i++)
16198 if (CONST_INT_P (operands[7 + i])
16199 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16200 operands[7 + i] = operands[2 + j];
16203 for (i = 0; i < nparts; i++)
16204 emit_move_insn (operands[2 + i], operands[6 + i]);
16209 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16210 left shift by a constant, either using a single shift or
16211 a sequence of add instructions. */
16214 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16218 emit_insn ((mode == DImode
16220 : gen_adddi3) (operand, operand, operand));
16222 else if (!optimize_insn_for_size_p ()
16223 && count * ix86_cost->add <= ix86_cost->shift_const)
16226 for (i=0; i<count; i++)
16228 emit_insn ((mode == DImode
16230 : gen_adddi3) (operand, operand, operand));
16234 emit_insn ((mode == DImode
16236 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16240 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16242 rtx low[2], high[2];
16244 const int single_width = mode == DImode ? 32 : 64;
16246 if (CONST_INT_P (operands[2]))
16248 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16249 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16251 if (count >= single_width)
16253 emit_move_insn (high[0], low[1]);
16254 emit_move_insn (low[0], const0_rtx);
16256 if (count > single_width)
16257 ix86_expand_ashl_const (high[0], count - single_width, mode);
16261 if (!rtx_equal_p (operands[0], operands[1]))
16262 emit_move_insn (operands[0], operands[1]);
16263 emit_insn ((mode == DImode
16265 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16266 ix86_expand_ashl_const (low[0], count, mode);
16271 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16273 if (operands[1] == const1_rtx)
16275 /* Assuming we've chosen a QImode capable registers, then 1 << N
16276 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16277 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16279 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16281 ix86_expand_clear (low[0]);
16282 ix86_expand_clear (high[0]);
16283 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16285 d = gen_lowpart (QImode, low[0]);
16286 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16287 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16288 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16290 d = gen_lowpart (QImode, high[0]);
16291 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16292 s = gen_rtx_NE (QImode, flags, const0_rtx);
16293 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16296 /* Otherwise, we can get the same results by manually performing
16297 a bit extract operation on bit 5/6, and then performing the two
16298 shifts. The two methods of getting 0/1 into low/high are exactly
16299 the same size. Avoiding the shift in the bit extract case helps
16300 pentium4 a bit; no one else seems to care much either way. */
16305 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16306 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16308 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16309 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16311 emit_insn ((mode == DImode
16313 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16314 emit_insn ((mode == DImode
16316 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16317 emit_move_insn (low[0], high[0]);
16318 emit_insn ((mode == DImode
16320 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16323 emit_insn ((mode == DImode
16325 : gen_ashldi3) (low[0], low[0], operands[2]));
16326 emit_insn ((mode == DImode
16328 : gen_ashldi3) (high[0], high[0], operands[2]));
16332 if (operands[1] == constm1_rtx)
16334 /* For -1 << N, we can avoid the shld instruction, because we
16335 know that we're shifting 0...31/63 ones into a -1. */
16336 emit_move_insn (low[0], constm1_rtx);
16337 if (optimize_insn_for_size_p ())
16338 emit_move_insn (high[0], low[0]);
16340 emit_move_insn (high[0], constm1_rtx);
16344 if (!rtx_equal_p (operands[0], operands[1]))
16345 emit_move_insn (operands[0], operands[1]);
16347 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16348 emit_insn ((mode == DImode
16350 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16353 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16355 if (TARGET_CMOVE && scratch)
16357 ix86_expand_clear (scratch);
16358 emit_insn ((mode == DImode
16359 ? gen_x86_shift_adj_1
16360 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16364 emit_insn ((mode == DImode
16365 ? gen_x86_shift_adj_2
16366 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16370 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16372 rtx low[2], high[2];
16374 const int single_width = mode == DImode ? 32 : 64;
16376 if (CONST_INT_P (operands[2]))
16378 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16379 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16381 if (count == single_width * 2 - 1)
16383 emit_move_insn (high[0], high[1]);
16384 emit_insn ((mode == DImode
16386 : gen_ashrdi3) (high[0], high[0],
16387 GEN_INT (single_width - 1)));
16388 emit_move_insn (low[0], high[0]);
16391 else if (count >= single_width)
16393 emit_move_insn (low[0], high[1]);
16394 emit_move_insn (high[0], low[0]);
16395 emit_insn ((mode == DImode
16397 : gen_ashrdi3) (high[0], high[0],
16398 GEN_INT (single_width - 1)));
16399 if (count > single_width)
16400 emit_insn ((mode == DImode
16402 : gen_ashrdi3) (low[0], low[0],
16403 GEN_INT (count - single_width)));
16407 if (!rtx_equal_p (operands[0], operands[1]))
16408 emit_move_insn (operands[0], operands[1]);
16409 emit_insn ((mode == DImode
16411 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16412 emit_insn ((mode == DImode
16414 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16419 if (!rtx_equal_p (operands[0], operands[1]))
16420 emit_move_insn (operands[0], operands[1]);
16422 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16424 emit_insn ((mode == DImode
16426 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16427 emit_insn ((mode == DImode
16429 : gen_ashrdi3) (high[0], high[0], operands[2]));
16431 if (TARGET_CMOVE && scratch)
16433 emit_move_insn (scratch, high[0]);
16434 emit_insn ((mode == DImode
16436 : gen_ashrdi3) (scratch, scratch,
16437 GEN_INT (single_width - 1)));
16438 emit_insn ((mode == DImode
16439 ? gen_x86_shift_adj_1
16440 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16444 emit_insn ((mode == DImode
16445 ? gen_x86_shift_adj_3
16446 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16451 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16453 rtx low[2], high[2];
16455 const int single_width = mode == DImode ? 32 : 64;
16457 if (CONST_INT_P (operands[2]))
16459 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16460 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16462 if (count >= single_width)
16464 emit_move_insn (low[0], high[1]);
16465 ix86_expand_clear (high[0]);
16467 if (count > single_width)
16468 emit_insn ((mode == DImode
16470 : gen_lshrdi3) (low[0], low[0],
16471 GEN_INT (count - single_width)));
16475 if (!rtx_equal_p (operands[0], operands[1]))
16476 emit_move_insn (operands[0], operands[1]);
16477 emit_insn ((mode == DImode
16479 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16480 emit_insn ((mode == DImode
16482 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16487 if (!rtx_equal_p (operands[0], operands[1]))
16488 emit_move_insn (operands[0], operands[1]);
16490 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16492 emit_insn ((mode == DImode
16494 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16495 emit_insn ((mode == DImode
16497 : gen_lshrdi3) (high[0], high[0], operands[2]));
16499 /* Heh. By reversing the arguments, we can reuse this pattern. */
16500 if (TARGET_CMOVE && scratch)
16502 ix86_expand_clear (scratch);
16503 emit_insn ((mode == DImode
16504 ? gen_x86_shift_adj_1
16505 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16509 emit_insn ((mode == DImode
16510 ? gen_x86_shift_adj_2
16511 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16515 /* Predict just emitted jump instruction to be taken with probability PROB. */
16517 predict_jump (int prob)
16519 rtx insn = get_last_insn ();
16520 gcc_assert (JUMP_P (insn));
16522 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16527 /* Helper function for the string operations below. Dest VARIABLE whether
16528 it is aligned to VALUE bytes. If true, jump to the label. */
16530 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16532 rtx label = gen_label_rtx ();
16533 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16534 if (GET_MODE (variable) == DImode)
16535 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16537 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16538 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16541 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16543 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16547 /* Adjust COUNTER by the VALUE. */
16549 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16551 if (GET_MODE (countreg) == DImode)
16552 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16554 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16557 /* Zero extend possibly SImode EXP to Pmode register. */
16559 ix86_zero_extend_to_Pmode (rtx exp)
16562 if (GET_MODE (exp) == VOIDmode)
16563 return force_reg (Pmode, exp);
16564 if (GET_MODE (exp) == Pmode)
16565 return copy_to_mode_reg (Pmode, exp);
16566 r = gen_reg_rtx (Pmode);
16567 emit_insn (gen_zero_extendsidi2 (r, exp));
16571 /* Divide COUNTREG by SCALE. */
16573 scale_counter (rtx countreg, int scale)
16576 rtx piece_size_mask;
16580 if (CONST_INT_P (countreg))
16581 return GEN_INT (INTVAL (countreg) / scale);
16582 gcc_assert (REG_P (countreg));
16584 piece_size_mask = GEN_INT (scale - 1);
16585 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16586 GEN_INT (exact_log2 (scale)),
16587 NULL, 1, OPTAB_DIRECT);
16591 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16592 DImode for constant loop counts. */
16594 static enum machine_mode
16595 counter_mode (rtx count_exp)
16597 if (GET_MODE (count_exp) != VOIDmode)
16598 return GET_MODE (count_exp);
16599 if (GET_CODE (count_exp) != CONST_INT)
16601 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16606 /* When SRCPTR is non-NULL, output simple loop to move memory
16607 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16608 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16609 equivalent loop to set memory by VALUE (supposed to be in MODE).
16611 The size is rounded down to whole number of chunk size moved at once.
16612 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16616 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16617 rtx destptr, rtx srcptr, rtx value,
16618 rtx count, enum machine_mode mode, int unroll,
16621 rtx out_label, top_label, iter, tmp;
16622 enum machine_mode iter_mode = counter_mode (count);
16623 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16624 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16630 top_label = gen_label_rtx ();
16631 out_label = gen_label_rtx ();
16632 iter = gen_reg_rtx (iter_mode);
16634 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16635 NULL, 1, OPTAB_DIRECT);
16636 /* Those two should combine. */
16637 if (piece_size == const1_rtx)
16639 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16641 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16643 emit_move_insn (iter, const0_rtx);
16645 emit_label (top_label);
16647 tmp = convert_modes (Pmode, iter_mode, iter, true);
16648 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16649 destmem = change_address (destmem, mode, x_addr);
16653 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16654 srcmem = change_address (srcmem, mode, y_addr);
16656 /* When unrolling for chips that reorder memory reads and writes,
16657 we can save registers by using single temporary.
16658 Also using 4 temporaries is overkill in 32bit mode. */
16659 if (!TARGET_64BIT && 0)
16661 for (i = 0; i < unroll; i++)
16666 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16668 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16670 emit_move_insn (destmem, srcmem);
16676 gcc_assert (unroll <= 4);
16677 for (i = 0; i < unroll; i++)
16679 tmpreg[i] = gen_reg_rtx (mode);
16683 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16685 emit_move_insn (tmpreg[i], srcmem);
16687 for (i = 0; i < unroll; i++)
16692 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16694 emit_move_insn (destmem, tmpreg[i]);
16699 for (i = 0; i < unroll; i++)
16703 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16704 emit_move_insn (destmem, value);
16707 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16708 true, OPTAB_LIB_WIDEN);
16710 emit_move_insn (iter, tmp);
16712 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16714 if (expected_size != -1)
16716 expected_size /= GET_MODE_SIZE (mode) * unroll;
16717 if (expected_size == 0)
16719 else if (expected_size > REG_BR_PROB_BASE)
16720 predict_jump (REG_BR_PROB_BASE - 1);
16722 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16725 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16726 iter = ix86_zero_extend_to_Pmode (iter);
16727 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16728 true, OPTAB_LIB_WIDEN);
16729 if (tmp != destptr)
16730 emit_move_insn (destptr, tmp);
16733 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16734 true, OPTAB_LIB_WIDEN);
16736 emit_move_insn (srcptr, tmp);
16738 emit_label (out_label);
16741 /* Output "rep; mov" instruction.
16742 Arguments have same meaning as for previous function */
16744 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16745 rtx destptr, rtx srcptr,
16747 enum machine_mode mode)
16753 /* If the size is known, it is shorter to use rep movs. */
16754 if (mode == QImode && CONST_INT_P (count)
16755 && !(INTVAL (count) & 3))
16758 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16759 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16760 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16761 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16762 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16763 if (mode != QImode)
16765 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16766 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16767 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16768 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16769 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16770 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16774 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16775 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16777 if (CONST_INT_P (count))
16779 count = GEN_INT (INTVAL (count)
16780 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16781 destmem = shallow_copy_rtx (destmem);
16782 srcmem = shallow_copy_rtx (srcmem);
16783 set_mem_size (destmem, count);
16784 set_mem_size (srcmem, count);
16788 if (MEM_SIZE (destmem))
16789 set_mem_size (destmem, NULL_RTX);
16790 if (MEM_SIZE (srcmem))
16791 set_mem_size (srcmem, NULL_RTX);
16793 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16797 /* Output "rep; stos" instruction.
16798 Arguments have same meaning as for previous function */
16800 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16801 rtx count, enum machine_mode mode,
16807 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16808 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16809 value = force_reg (mode, gen_lowpart (mode, value));
16810 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16811 if (mode != QImode)
16813 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16814 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16815 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16818 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16819 if (orig_value == const0_rtx && CONST_INT_P (count))
16821 count = GEN_INT (INTVAL (count)
16822 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16823 destmem = shallow_copy_rtx (destmem);
16824 set_mem_size (destmem, count);
16826 else if (MEM_SIZE (destmem))
16827 set_mem_size (destmem, NULL_RTX);
16828 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16832 emit_strmov (rtx destmem, rtx srcmem,
16833 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16835 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16836 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16837 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16840 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16842 expand_movmem_epilogue (rtx destmem, rtx srcmem,
16843 rtx destptr, rtx srcptr, rtx count, int max_size)
16846 if (CONST_INT_P (count))
16848 HOST_WIDE_INT countval = INTVAL (count);
16851 if ((countval & 0x10) && max_size > 16)
16855 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16856 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
16859 gcc_unreachable ();
16862 if ((countval & 0x08) && max_size > 8)
16865 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16868 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16869 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
16873 if ((countval & 0x04) && max_size > 4)
16875 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16878 if ((countval & 0x02) && max_size > 2)
16880 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
16883 if ((countval & 0x01) && max_size > 1)
16885 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
16892 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
16893 count, 1, OPTAB_DIRECT);
16894 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
16895 count, QImode, 1, 4);
16899 /* When there are stringops, we can cheaply increase dest and src pointers.
16900 Otherwise we save code size by maintaining offset (zero is readily
16901 available from preceding rep operation) and using x86 addressing modes.
16903 if (TARGET_SINGLE_STRINGOP)
16907 rtx label = ix86_expand_aligntest (count, 4, true);
16908 src = change_address (srcmem, SImode, srcptr);
16909 dest = change_address (destmem, SImode, destptr);
16910 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16911 emit_label (label);
16912 LABEL_NUSES (label) = 1;
16916 rtx label = ix86_expand_aligntest (count, 2, true);
16917 src = change_address (srcmem, HImode, srcptr);
16918 dest = change_address (destmem, HImode, destptr);
16919 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16920 emit_label (label);
16921 LABEL_NUSES (label) = 1;
16925 rtx label = ix86_expand_aligntest (count, 1, true);
16926 src = change_address (srcmem, QImode, srcptr);
16927 dest = change_address (destmem, QImode, destptr);
16928 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16929 emit_label (label);
16930 LABEL_NUSES (label) = 1;
16935 rtx offset = force_reg (Pmode, const0_rtx);
16940 rtx label = ix86_expand_aligntest (count, 4, true);
16941 src = change_address (srcmem, SImode, srcptr);
16942 dest = change_address (destmem, SImode, destptr);
16943 emit_move_insn (dest, src);
16944 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
16945 true, OPTAB_LIB_WIDEN);
16947 emit_move_insn (offset, tmp);
16948 emit_label (label);
16949 LABEL_NUSES (label) = 1;
16953 rtx label = ix86_expand_aligntest (count, 2, true);
16954 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
16955 src = change_address (srcmem, HImode, tmp);
16956 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
16957 dest = change_address (destmem, HImode, tmp);
16958 emit_move_insn (dest, src);
16959 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
16960 true, OPTAB_LIB_WIDEN);
16962 emit_move_insn (offset, tmp);
16963 emit_label (label);
16964 LABEL_NUSES (label) = 1;
16968 rtx label = ix86_expand_aligntest (count, 1, true);
16969 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
16970 src = change_address (srcmem, QImode, tmp);
16971 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
16972 dest = change_address (destmem, QImode, tmp);
16973 emit_move_insn (dest, src);
16974 emit_label (label);
16975 LABEL_NUSES (label) = 1;
16980 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16982 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
16983 rtx count, int max_size)
16986 expand_simple_binop (counter_mode (count), AND, count,
16987 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
16988 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
16989 gen_lowpart (QImode, value), count, QImode,
16993 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16995 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
16999 if (CONST_INT_P (count))
17001 HOST_WIDE_INT countval = INTVAL (count);
17004 if ((countval & 0x10) && max_size > 16)
17008 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17009 emit_insn (gen_strset (destptr, dest, value));
17010 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17011 emit_insn (gen_strset (destptr, dest, value));
17014 gcc_unreachable ();
17017 if ((countval & 0x08) && max_size > 8)
17021 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17022 emit_insn (gen_strset (destptr, dest, value));
17026 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17027 emit_insn (gen_strset (destptr, dest, value));
17028 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17029 emit_insn (gen_strset (destptr, dest, value));
17033 if ((countval & 0x04) && max_size > 4)
17035 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17036 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17039 if ((countval & 0x02) && max_size > 2)
17041 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17042 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17045 if ((countval & 0x01) && max_size > 1)
17047 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17048 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17055 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17060 rtx label = ix86_expand_aligntest (count, 16, true);
17063 dest = change_address (destmem, DImode, destptr);
17064 emit_insn (gen_strset (destptr, dest, value));
17065 emit_insn (gen_strset (destptr, dest, value));
17069 dest = change_address (destmem, SImode, destptr);
17070 emit_insn (gen_strset (destptr, dest, value));
17071 emit_insn (gen_strset (destptr, dest, value));
17072 emit_insn (gen_strset (destptr, dest, value));
17073 emit_insn (gen_strset (destptr, dest, value));
17075 emit_label (label);
17076 LABEL_NUSES (label) = 1;
17080 rtx label = ix86_expand_aligntest (count, 8, true);
17083 dest = change_address (destmem, DImode, destptr);
17084 emit_insn (gen_strset (destptr, dest, value));
17088 dest = change_address (destmem, SImode, destptr);
17089 emit_insn (gen_strset (destptr, dest, value));
17090 emit_insn (gen_strset (destptr, dest, value));
17092 emit_label (label);
17093 LABEL_NUSES (label) = 1;
17097 rtx label = ix86_expand_aligntest (count, 4, true);
17098 dest = change_address (destmem, SImode, destptr);
17099 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17100 emit_label (label);
17101 LABEL_NUSES (label) = 1;
17105 rtx label = ix86_expand_aligntest (count, 2, true);
17106 dest = change_address (destmem, HImode, destptr);
17107 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17108 emit_label (label);
17109 LABEL_NUSES (label) = 1;
17113 rtx label = ix86_expand_aligntest (count, 1, true);
17114 dest = change_address (destmem, QImode, destptr);
17115 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17116 emit_label (label);
17117 LABEL_NUSES (label) = 1;
17121 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17122 DESIRED_ALIGNMENT. */
17124 expand_movmem_prologue (rtx destmem, rtx srcmem,
17125 rtx destptr, rtx srcptr, rtx count,
17126 int align, int desired_alignment)
17128 if (align <= 1 && desired_alignment > 1)
17130 rtx label = ix86_expand_aligntest (destptr, 1, false);
17131 srcmem = change_address (srcmem, QImode, srcptr);
17132 destmem = change_address (destmem, QImode, destptr);
17133 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17134 ix86_adjust_counter (count, 1);
17135 emit_label (label);
17136 LABEL_NUSES (label) = 1;
17138 if (align <= 2 && desired_alignment > 2)
17140 rtx label = ix86_expand_aligntest (destptr, 2, false);
17141 srcmem = change_address (srcmem, HImode, srcptr);
17142 destmem = change_address (destmem, HImode, destptr);
17143 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17144 ix86_adjust_counter (count, 2);
17145 emit_label (label);
17146 LABEL_NUSES (label) = 1;
17148 if (align <= 4 && desired_alignment > 4)
17150 rtx label = ix86_expand_aligntest (destptr, 4, false);
17151 srcmem = change_address (srcmem, SImode, srcptr);
17152 destmem = change_address (destmem, SImode, destptr);
17153 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17154 ix86_adjust_counter (count, 4);
17155 emit_label (label);
17156 LABEL_NUSES (label) = 1;
17158 gcc_assert (desired_alignment <= 8);
17161 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17162 ALIGN_BYTES is how many bytes need to be copied. */
17164 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17165 int desired_align, int align_bytes)
17168 rtx src_size, dst_size;
17170 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17171 if (src_align_bytes >= 0)
17172 src_align_bytes = desired_align - src_align_bytes;
17173 src_size = MEM_SIZE (src);
17174 dst_size = MEM_SIZE (dst);
17175 if (align_bytes & 1)
17177 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17178 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17180 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17182 if (align_bytes & 2)
17184 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17185 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17186 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17187 set_mem_align (dst, 2 * BITS_PER_UNIT);
17188 if (src_align_bytes >= 0
17189 && (src_align_bytes & 1) == (align_bytes & 1)
17190 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17191 set_mem_align (src, 2 * BITS_PER_UNIT);
17193 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17195 if (align_bytes & 4)
17197 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17198 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17199 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17200 set_mem_align (dst, 4 * BITS_PER_UNIT);
17201 if (src_align_bytes >= 0)
17203 unsigned int src_align = 0;
17204 if ((src_align_bytes & 3) == (align_bytes & 3))
17206 else if ((src_align_bytes & 1) == (align_bytes & 1))
17208 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17209 set_mem_align (src, src_align * BITS_PER_UNIT);
17212 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17214 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17215 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17216 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17217 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17218 if (src_align_bytes >= 0)
17220 unsigned int src_align = 0;
17221 if ((src_align_bytes & 7) == (align_bytes & 7))
17223 else if ((src_align_bytes & 3) == (align_bytes & 3))
17225 else if ((src_align_bytes & 1) == (align_bytes & 1))
17227 if (src_align > (unsigned int) desired_align)
17228 src_align = desired_align;
17229 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17230 set_mem_align (src, src_align * BITS_PER_UNIT);
17233 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17235 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17240 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17241 DESIRED_ALIGNMENT. */
17243 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17244 int align, int desired_alignment)
17246 if (align <= 1 && desired_alignment > 1)
17248 rtx label = ix86_expand_aligntest (destptr, 1, false);
17249 destmem = change_address (destmem, QImode, destptr);
17250 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17251 ix86_adjust_counter (count, 1);
17252 emit_label (label);
17253 LABEL_NUSES (label) = 1;
17255 if (align <= 2 && desired_alignment > 2)
17257 rtx label = ix86_expand_aligntest (destptr, 2, false);
17258 destmem = change_address (destmem, HImode, destptr);
17259 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17260 ix86_adjust_counter (count, 2);
17261 emit_label (label);
17262 LABEL_NUSES (label) = 1;
17264 if (align <= 4 && desired_alignment > 4)
17266 rtx label = ix86_expand_aligntest (destptr, 4, false);
17267 destmem = change_address (destmem, SImode, destptr);
17268 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17269 ix86_adjust_counter (count, 4);
17270 emit_label (label);
17271 LABEL_NUSES (label) = 1;
17273 gcc_assert (desired_alignment <= 8);
17276 /* Set enough from DST to align DST known to by aligned by ALIGN to
17277 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17279 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17280 int desired_align, int align_bytes)
17283 rtx dst_size = MEM_SIZE (dst);
17284 if (align_bytes & 1)
17286 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17288 emit_insn (gen_strset (destreg, dst,
17289 gen_lowpart (QImode, value)));
17291 if (align_bytes & 2)
17293 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17294 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17295 set_mem_align (dst, 2 * BITS_PER_UNIT);
17297 emit_insn (gen_strset (destreg, dst,
17298 gen_lowpart (HImode, value)));
17300 if (align_bytes & 4)
17302 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17303 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17304 set_mem_align (dst, 4 * BITS_PER_UNIT);
17306 emit_insn (gen_strset (destreg, dst,
17307 gen_lowpart (SImode, value)));
17309 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17310 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17311 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17313 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17317 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17318 static enum stringop_alg
17319 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17320 int *dynamic_check)
17322 const struct stringop_algs * algs;
17323 bool optimize_for_speed;
17324 /* Algorithms using the rep prefix want at least edi and ecx;
17325 additionally, memset wants eax and memcpy wants esi. Don't
17326 consider such algorithms if the user has appropriated those
17327 registers for their own purposes. */
17328 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17330 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17332 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17333 || (alg != rep_prefix_1_byte \
17334 && alg != rep_prefix_4_byte \
17335 && alg != rep_prefix_8_byte))
17336 const struct processor_costs *cost;
17338 /* Even if the string operation call is cold, we still might spend a lot
17339 of time processing large blocks. */
17340 if (optimize_function_for_size_p (cfun)
17341 || (optimize_insn_for_size_p ()
17342 && expected_size != -1 && expected_size < 256))
17343 optimize_for_speed = false;
17345 optimize_for_speed = true;
17347 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17349 *dynamic_check = -1;
17351 algs = &cost->memset[TARGET_64BIT != 0];
17353 algs = &cost->memcpy[TARGET_64BIT != 0];
17354 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17355 return stringop_alg;
17356 /* rep; movq or rep; movl is the smallest variant. */
17357 else if (!optimize_for_speed)
17359 if (!count || (count & 3))
17360 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17362 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17364 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17366 else if (expected_size != -1 && expected_size < 4)
17367 return loop_1_byte;
17368 else if (expected_size != -1)
17371 enum stringop_alg alg = libcall;
17372 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17374 /* We get here if the algorithms that were not libcall-based
17375 were rep-prefix based and we are unable to use rep prefixes
17376 based on global register usage. Break out of the loop and
17377 use the heuristic below. */
17378 if (algs->size[i].max == 0)
17380 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17382 enum stringop_alg candidate = algs->size[i].alg;
17384 if (candidate != libcall && ALG_USABLE_P (candidate))
17386 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17387 last non-libcall inline algorithm. */
17388 if (TARGET_INLINE_ALL_STRINGOPS)
17390 /* When the current size is best to be copied by a libcall,
17391 but we are still forced to inline, run the heuristic below
17392 that will pick code for medium sized blocks. */
17393 if (alg != libcall)
17397 else if (ALG_USABLE_P (candidate))
17401 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17403 /* When asked to inline the call anyway, try to pick meaningful choice.
17404 We look for maximal size of block that is faster to copy by hand and
17405 take blocks of at most of that size guessing that average size will
17406 be roughly half of the block.
17408 If this turns out to be bad, we might simply specify the preferred
17409 choice in ix86_costs. */
17410 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17411 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17414 enum stringop_alg alg;
17416 bool any_alg_usable_p = true;
17418 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17420 enum stringop_alg candidate = algs->size[i].alg;
17421 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17423 if (candidate != libcall && candidate
17424 && ALG_USABLE_P (candidate))
17425 max = algs->size[i].max;
17427 /* If there aren't any usable algorithms, then recursing on
17428 smaller sizes isn't going to find anything. Just return the
17429 simple byte-at-a-time copy loop. */
17430 if (!any_alg_usable_p)
17432 /* Pick something reasonable. */
17433 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17434 *dynamic_check = 128;
17435 return loop_1_byte;
17439 alg = decide_alg (count, max / 2, memset, dynamic_check);
17440 gcc_assert (*dynamic_check == -1);
17441 gcc_assert (alg != libcall);
17442 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17443 *dynamic_check = max;
17446 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17447 #undef ALG_USABLE_P
17450 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17451 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17453 decide_alignment (int align,
17454 enum stringop_alg alg,
17457 int desired_align = 0;
17461 gcc_unreachable ();
17463 case unrolled_loop:
17464 desired_align = GET_MODE_SIZE (Pmode);
17466 case rep_prefix_8_byte:
17469 case rep_prefix_4_byte:
17470 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17471 copying whole cacheline at once. */
17472 if (TARGET_PENTIUMPRO)
17477 case rep_prefix_1_byte:
17478 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17479 copying whole cacheline at once. */
17480 if (TARGET_PENTIUMPRO)
17494 if (desired_align < align)
17495 desired_align = align;
17496 if (expected_size != -1 && expected_size < 4)
17497 desired_align = align;
17498 return desired_align;
17501 /* Return the smallest power of 2 greater than VAL. */
17503 smallest_pow2_greater_than (int val)
17511 /* Expand string move (memcpy) operation. Use i386 string operations when
17512 profitable. expand_setmem contains similar code. The code depends upon
17513 architecture, block size and alignment, but always has the same
17516 1) Prologue guard: Conditional that jumps up to epilogues for small
17517 blocks that can be handled by epilogue alone. This is faster but
17518 also needed for correctness, since prologue assume the block is larger
17519 than the desired alignment.
17521 Optional dynamic check for size and libcall for large
17522 blocks is emitted here too, with -minline-stringops-dynamically.
17524 2) Prologue: copy first few bytes in order to get destination aligned
17525 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17526 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17527 We emit either a jump tree on power of two sized blocks, or a byte loop.
17529 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17530 with specified algorithm.
17532 4) Epilogue: code copying tail of the block that is too small to be
17533 handled by main body (or up to size guarded by prologue guard). */
17536 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17537 rtx expected_align_exp, rtx expected_size_exp)
17543 rtx jump_around_label = NULL;
17544 HOST_WIDE_INT align = 1;
17545 unsigned HOST_WIDE_INT count = 0;
17546 HOST_WIDE_INT expected_size = -1;
17547 int size_needed = 0, epilogue_size_needed;
17548 int desired_align = 0, align_bytes = 0;
17549 enum stringop_alg alg;
17551 bool need_zero_guard = false;
17553 if (CONST_INT_P (align_exp))
17554 align = INTVAL (align_exp);
17555 /* i386 can do misaligned access on reasonably increased cost. */
17556 if (CONST_INT_P (expected_align_exp)
17557 && INTVAL (expected_align_exp) > align)
17558 align = INTVAL (expected_align_exp);
17559 /* ALIGN is the minimum of destination and source alignment, but we care here
17560 just about destination alignment. */
17561 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17562 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17564 if (CONST_INT_P (count_exp))
17565 count = expected_size = INTVAL (count_exp);
17566 if (CONST_INT_P (expected_size_exp) && count == 0)
17567 expected_size = INTVAL (expected_size_exp);
17569 /* Make sure we don't need to care about overflow later on. */
17570 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17573 /* Step 0: Decide on preferred algorithm, desired alignment and
17574 size of chunks to be copied by main loop. */
17576 alg = decide_alg (count, expected_size, false, &dynamic_check);
17577 desired_align = decide_alignment (align, alg, expected_size);
17579 if (!TARGET_ALIGN_STRINGOPS)
17580 align = desired_align;
17582 if (alg == libcall)
17584 gcc_assert (alg != no_stringop);
17586 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17587 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17588 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17593 gcc_unreachable ();
17595 need_zero_guard = true;
17596 size_needed = GET_MODE_SIZE (Pmode);
17598 case unrolled_loop:
17599 need_zero_guard = true;
17600 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17602 case rep_prefix_8_byte:
17605 case rep_prefix_4_byte:
17608 case rep_prefix_1_byte:
17612 need_zero_guard = true;
17617 epilogue_size_needed = size_needed;
17619 /* Step 1: Prologue guard. */
17621 /* Alignment code needs count to be in register. */
17622 if (CONST_INT_P (count_exp) && desired_align > align)
17624 if (INTVAL (count_exp) > desired_align
17625 && INTVAL (count_exp) > size_needed)
17628 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17629 if (align_bytes <= 0)
17632 align_bytes = desired_align - align_bytes;
17634 if (align_bytes == 0)
17635 count_exp = force_reg (counter_mode (count_exp), count_exp);
17637 gcc_assert (desired_align >= 1 && align >= 1);
17639 /* Ensure that alignment prologue won't copy past end of block. */
17640 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17642 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17643 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17644 Make sure it is power of 2. */
17645 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17647 if (CONST_INT_P (count_exp))
17649 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17654 label = gen_label_rtx ();
17655 emit_cmp_and_jump_insns (count_exp,
17656 GEN_INT (epilogue_size_needed),
17657 LTU, 0, counter_mode (count_exp), 1, label);
17658 if (expected_size == -1 || expected_size < epilogue_size_needed)
17659 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17661 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17665 /* Emit code to decide on runtime whether library call or inline should be
17667 if (dynamic_check != -1)
17669 if (CONST_INT_P (count_exp))
17671 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17673 emit_block_move_via_libcall (dst, src, count_exp, false);
17674 count_exp = const0_rtx;
17680 rtx hot_label = gen_label_rtx ();
17681 jump_around_label = gen_label_rtx ();
17682 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17683 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17684 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17685 emit_block_move_via_libcall (dst, src, count_exp, false);
17686 emit_jump (jump_around_label);
17687 emit_label (hot_label);
17691 /* Step 2: Alignment prologue. */
17693 if (desired_align > align)
17695 if (align_bytes == 0)
17697 /* Except for the first move in epilogue, we no longer know
17698 constant offset in aliasing info. It don't seems to worth
17699 the pain to maintain it for the first move, so throw away
17701 src = change_address (src, BLKmode, srcreg);
17702 dst = change_address (dst, BLKmode, destreg);
17703 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17708 /* If we know how many bytes need to be stored before dst is
17709 sufficiently aligned, maintain aliasing info accurately. */
17710 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17711 desired_align, align_bytes);
17712 count_exp = plus_constant (count_exp, -align_bytes);
17713 count -= align_bytes;
17715 if (need_zero_guard && !count)
17717 /* It is possible that we copied enough so the main loop will not
17719 emit_cmp_and_jump_insns (count_exp,
17720 GEN_INT (size_needed),
17721 LTU, 0, counter_mode (count_exp), 1, label);
17722 if (expected_size == -1
17723 || expected_size < (desired_align - align) / 2 + size_needed)
17724 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17726 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17729 if (label && size_needed == 1)
17731 emit_label (label);
17732 LABEL_NUSES (label) = 1;
17736 /* Step 3: Main loop. */
17742 gcc_unreachable ();
17744 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17745 count_exp, QImode, 1, expected_size);
17748 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17749 count_exp, Pmode, 1, expected_size);
17751 case unrolled_loop:
17752 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17753 registers for 4 temporaries anyway. */
17754 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17755 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
17758 case rep_prefix_8_byte:
17759 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17762 case rep_prefix_4_byte:
17763 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17766 case rep_prefix_1_byte:
17767 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17771 /* Adjust properly the offset of src and dest memory for aliasing. */
17772 if (CONST_INT_P (count_exp))
17774 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17775 (count / size_needed) * size_needed);
17776 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17777 (count / size_needed) * size_needed);
17781 src = change_address (src, BLKmode, srcreg);
17782 dst = change_address (dst, BLKmode, destreg);
17785 /* Step 4: Epilogue to copy the remaining bytes. */
17789 /* When the main loop is done, COUNT_EXP might hold original count,
17790 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17791 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17792 bytes. Compensate if needed. */
17794 if (size_needed < epilogue_size_needed)
17797 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17798 GEN_INT (size_needed - 1), count_exp, 1,
17800 if (tmp != count_exp)
17801 emit_move_insn (count_exp, tmp);
17803 emit_label (label);
17804 LABEL_NUSES (label) = 1;
17807 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17808 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17809 epilogue_size_needed);
17810 if (jump_around_label)
17811 emit_label (jump_around_label);
17815 /* Helper function for memcpy. For QImode value 0xXY produce
17816 0xXYXYXYXY of wide specified by MODE. This is essentially
17817 a * 0x10101010, but we can do slightly better than
17818 synth_mult by unwinding the sequence by hand on CPUs with
17821 promote_duplicated_reg (enum machine_mode mode, rtx val)
17823 enum machine_mode valmode = GET_MODE (val);
17825 int nops = mode == DImode ? 3 : 2;
17827 gcc_assert (mode == SImode || mode == DImode);
17828 if (val == const0_rtx)
17829 return copy_to_mode_reg (mode, const0_rtx);
17830 if (CONST_INT_P (val))
17832 HOST_WIDE_INT v = INTVAL (val) & 255;
17836 if (mode == DImode)
17837 v |= (v << 16) << 16;
17838 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
17841 if (valmode == VOIDmode)
17843 if (valmode != QImode)
17844 val = gen_lowpart (QImode, val);
17845 if (mode == QImode)
17847 if (!TARGET_PARTIAL_REG_STALL)
17849 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
17850 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
17851 <= (ix86_cost->shift_const + ix86_cost->add) * nops
17852 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
17854 rtx reg = convert_modes (mode, QImode, val, true);
17855 tmp = promote_duplicated_reg (mode, const1_rtx);
17856 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
17861 rtx reg = convert_modes (mode, QImode, val, true);
17863 if (!TARGET_PARTIAL_REG_STALL)
17864 if (mode == SImode)
17865 emit_insn (gen_movsi_insv_1 (reg, reg));
17867 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
17870 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
17871 NULL, 1, OPTAB_DIRECT);
17873 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17875 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
17876 NULL, 1, OPTAB_DIRECT);
17877 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17878 if (mode == SImode)
17880 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
17881 NULL, 1, OPTAB_DIRECT);
17882 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17887 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
17888 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
17889 alignment from ALIGN to DESIRED_ALIGN. */
17891 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
17896 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
17897 promoted_val = promote_duplicated_reg (DImode, val);
17898 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
17899 promoted_val = promote_duplicated_reg (SImode, val);
17900 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
17901 promoted_val = promote_duplicated_reg (HImode, val);
17903 promoted_val = val;
17905 return promoted_val;
17908 /* Expand string clear operation (bzero). Use i386 string operations when
17909 profitable. See expand_movmem comment for explanation of individual
17910 steps performed. */
17912 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
17913 rtx expected_align_exp, rtx expected_size_exp)
17918 rtx jump_around_label = NULL;
17919 HOST_WIDE_INT align = 1;
17920 unsigned HOST_WIDE_INT count = 0;
17921 HOST_WIDE_INT expected_size = -1;
17922 int size_needed = 0, epilogue_size_needed;
17923 int desired_align = 0, align_bytes = 0;
17924 enum stringop_alg alg;
17925 rtx promoted_val = NULL;
17926 bool force_loopy_epilogue = false;
17928 bool need_zero_guard = false;
17930 if (CONST_INT_P (align_exp))
17931 align = INTVAL (align_exp);
17932 /* i386 can do misaligned access on reasonably increased cost. */
17933 if (CONST_INT_P (expected_align_exp)
17934 && INTVAL (expected_align_exp) > align)
17935 align = INTVAL (expected_align_exp);
17936 if (CONST_INT_P (count_exp))
17937 count = expected_size = INTVAL (count_exp);
17938 if (CONST_INT_P (expected_size_exp) && count == 0)
17939 expected_size = INTVAL (expected_size_exp);
17941 /* Make sure we don't need to care about overflow later on. */
17942 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17945 /* Step 0: Decide on preferred algorithm, desired alignment and
17946 size of chunks to be copied by main loop. */
17948 alg = decide_alg (count, expected_size, true, &dynamic_check);
17949 desired_align = decide_alignment (align, alg, expected_size);
17951 if (!TARGET_ALIGN_STRINGOPS)
17952 align = desired_align;
17954 if (alg == libcall)
17956 gcc_assert (alg != no_stringop);
17958 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
17959 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17964 gcc_unreachable ();
17966 need_zero_guard = true;
17967 size_needed = GET_MODE_SIZE (Pmode);
17969 case unrolled_loop:
17970 need_zero_guard = true;
17971 size_needed = GET_MODE_SIZE (Pmode) * 4;
17973 case rep_prefix_8_byte:
17976 case rep_prefix_4_byte:
17979 case rep_prefix_1_byte:
17983 need_zero_guard = true;
17987 epilogue_size_needed = size_needed;
17989 /* Step 1: Prologue guard. */
17991 /* Alignment code needs count to be in register. */
17992 if (CONST_INT_P (count_exp) && desired_align > align)
17994 if (INTVAL (count_exp) > desired_align
17995 && INTVAL (count_exp) > size_needed)
17998 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17999 if (align_bytes <= 0)
18002 align_bytes = desired_align - align_bytes;
18004 if (align_bytes == 0)
18006 enum machine_mode mode = SImode;
18007 if (TARGET_64BIT && (count & ~0xffffffff))
18009 count_exp = force_reg (mode, count_exp);
18012 /* Do the cheap promotion to allow better CSE across the
18013 main loop and epilogue (ie one load of the big constant in the
18014 front of all code. */
18015 if (CONST_INT_P (val_exp))
18016 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18017 desired_align, align);
18018 /* Ensure that alignment prologue won't copy past end of block. */
18019 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18021 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18022 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18023 Make sure it is power of 2. */
18024 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18026 /* To improve performance of small blocks, we jump around the VAL
18027 promoting mode. This mean that if the promoted VAL is not constant,
18028 we might not use it in the epilogue and have to use byte
18030 if (epilogue_size_needed > 2 && !promoted_val)
18031 force_loopy_epilogue = true;
18032 label = gen_label_rtx ();
18033 emit_cmp_and_jump_insns (count_exp,
18034 GEN_INT (epilogue_size_needed),
18035 LTU, 0, counter_mode (count_exp), 1, label);
18036 if (GET_CODE (count_exp) == CONST_INT)
18038 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
18039 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18041 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18043 if (dynamic_check != -1)
18045 rtx hot_label = gen_label_rtx ();
18046 jump_around_label = gen_label_rtx ();
18047 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18048 LEU, 0, counter_mode (count_exp), 1, hot_label);
18049 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18050 set_storage_via_libcall (dst, count_exp, val_exp, false);
18051 emit_jump (jump_around_label);
18052 emit_label (hot_label);
18055 /* Step 2: Alignment prologue. */
18057 /* Do the expensive promotion once we branched off the small blocks. */
18059 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18060 desired_align, align);
18061 gcc_assert (desired_align >= 1 && align >= 1);
18063 if (desired_align > align)
18065 if (align_bytes == 0)
18067 /* Except for the first move in epilogue, we no longer know
18068 constant offset in aliasing info. It don't seems to worth
18069 the pain to maintain it for the first move, so throw away
18071 dst = change_address (dst, BLKmode, destreg);
18072 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18077 /* If we know how many bytes need to be stored before dst is
18078 sufficiently aligned, maintain aliasing info accurately. */
18079 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18080 desired_align, align_bytes);
18081 count_exp = plus_constant (count_exp, -align_bytes);
18082 count -= align_bytes;
18084 if (need_zero_guard && !count)
18086 /* It is possible that we copied enough so the main loop will not
18088 emit_cmp_and_jump_insns (count_exp,
18089 GEN_INT (size_needed),
18090 LTU, 0, counter_mode (count_exp), 1, label);
18091 if (expected_size == -1
18092 || expected_size < (desired_align - align) / 2 + size_needed)
18093 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18095 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18098 if (label && size_needed == 1)
18100 emit_label (label);
18101 LABEL_NUSES (label) = 1;
18105 /* Step 3: Main loop. */
18111 gcc_unreachable ();
18113 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18114 count_exp, QImode, 1, expected_size);
18117 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18118 count_exp, Pmode, 1, expected_size);
18120 case unrolled_loop:
18121 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18122 count_exp, Pmode, 4, expected_size);
18124 case rep_prefix_8_byte:
18125 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18128 case rep_prefix_4_byte:
18129 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18132 case rep_prefix_1_byte:
18133 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18137 /* Adjust properly the offset of src and dest memory for aliasing. */
18138 if (CONST_INT_P (count_exp))
18139 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18140 (count / size_needed) * size_needed);
18142 dst = change_address (dst, BLKmode, destreg);
18144 /* Step 4: Epilogue to copy the remaining bytes. */
18148 /* When the main loop is done, COUNT_EXP might hold original count,
18149 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18150 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18151 bytes. Compensate if needed. */
18153 if (size_needed < desired_align - align)
18156 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18157 GEN_INT (size_needed - 1), count_exp, 1,
18159 size_needed = desired_align - align + 1;
18160 if (tmp != count_exp)
18161 emit_move_insn (count_exp, tmp);
18163 emit_label (label);
18164 LABEL_NUSES (label) = 1;
18166 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18168 if (force_loopy_epilogue)
18169 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18172 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18175 if (jump_around_label)
18176 emit_label (jump_around_label);
18180 /* Expand the appropriate insns for doing strlen if not just doing
18183 out = result, initialized with the start address
18184 align_rtx = alignment of the address.
18185 scratch = scratch register, initialized with the startaddress when
18186 not aligned, otherwise undefined
18188 This is just the body. It needs the initializations mentioned above and
18189 some address computing at the end. These things are done in i386.md. */
18192 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18196 rtx align_2_label = NULL_RTX;
18197 rtx align_3_label = NULL_RTX;
18198 rtx align_4_label = gen_label_rtx ();
18199 rtx end_0_label = gen_label_rtx ();
18201 rtx tmpreg = gen_reg_rtx (SImode);
18202 rtx scratch = gen_reg_rtx (SImode);
18206 if (CONST_INT_P (align_rtx))
18207 align = INTVAL (align_rtx);
18209 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18211 /* Is there a known alignment and is it less than 4? */
18214 rtx scratch1 = gen_reg_rtx (Pmode);
18215 emit_move_insn (scratch1, out);
18216 /* Is there a known alignment and is it not 2? */
18219 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18220 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18222 /* Leave just the 3 lower bits. */
18223 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18224 NULL_RTX, 0, OPTAB_WIDEN);
18226 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18227 Pmode, 1, align_4_label);
18228 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18229 Pmode, 1, align_2_label);
18230 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18231 Pmode, 1, align_3_label);
18235 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18236 check if is aligned to 4 - byte. */
18238 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18239 NULL_RTX, 0, OPTAB_WIDEN);
18241 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18242 Pmode, 1, align_4_label);
18245 mem = change_address (src, QImode, out);
18247 /* Now compare the bytes. */
18249 /* Compare the first n unaligned byte on a byte per byte basis. */
18250 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18251 QImode, 1, end_0_label);
18253 /* Increment the address. */
18254 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18256 /* Not needed with an alignment of 2 */
18259 emit_label (align_2_label);
18261 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18264 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18266 emit_label (align_3_label);
18269 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18272 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18275 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18276 align this loop. It gives only huge programs, but does not help to
18278 emit_label (align_4_label);
18280 mem = change_address (src, SImode, out);
18281 emit_move_insn (scratch, mem);
18282 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18284 /* This formula yields a nonzero result iff one of the bytes is zero.
18285 This saves three branches inside loop and many cycles. */
18287 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18288 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18289 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18290 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18291 gen_int_mode (0x80808080, SImode)));
18292 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18297 rtx reg = gen_reg_rtx (SImode);
18298 rtx reg2 = gen_reg_rtx (Pmode);
18299 emit_move_insn (reg, tmpreg);
18300 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18302 /* If zero is not in the first two bytes, move two bytes forward. */
18303 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18304 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18305 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18306 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18307 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18310 /* Emit lea manually to avoid clobbering of flags. */
18311 emit_insn (gen_rtx_SET (SImode, reg2,
18312 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18314 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18315 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18316 emit_insn (gen_rtx_SET (VOIDmode, out,
18317 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18324 rtx end_2_label = gen_label_rtx ();
18325 /* Is zero in the first two bytes? */
18327 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18328 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18329 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18330 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18331 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18333 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18334 JUMP_LABEL (tmp) = end_2_label;
18336 /* Not in the first two. Move two bytes forward. */
18337 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18338 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18340 emit_label (end_2_label);
18344 /* Avoid branch in fixing the byte. */
18345 tmpreg = gen_lowpart (QImode, tmpreg);
18346 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18347 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18348 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18350 emit_label (end_0_label);
18353 /* Expand strlen. */
18356 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18358 rtx addr, scratch1, scratch2, scratch3, scratch4;
18360 /* The generic case of strlen expander is long. Avoid it's
18361 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18363 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18364 && !TARGET_INLINE_ALL_STRINGOPS
18365 && !optimize_insn_for_size_p ()
18366 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18369 addr = force_reg (Pmode, XEXP (src, 0));
18370 scratch1 = gen_reg_rtx (Pmode);
18372 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18373 && !optimize_insn_for_size_p ())
18375 /* Well it seems that some optimizer does not combine a call like
18376 foo(strlen(bar), strlen(bar));
18377 when the move and the subtraction is done here. It does calculate
18378 the length just once when these instructions are done inside of
18379 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18380 often used and I use one fewer register for the lifetime of
18381 output_strlen_unroll() this is better. */
18383 emit_move_insn (out, addr);
18385 ix86_expand_strlensi_unroll_1 (out, src, align);
18387 /* strlensi_unroll_1 returns the address of the zero at the end of
18388 the string, like memchr(), so compute the length by subtracting
18389 the start address. */
18390 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18396 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18397 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18400 scratch2 = gen_reg_rtx (Pmode);
18401 scratch3 = gen_reg_rtx (Pmode);
18402 scratch4 = force_reg (Pmode, constm1_rtx);
18404 emit_move_insn (scratch3, addr);
18405 eoschar = force_reg (QImode, eoschar);
18407 src = replace_equiv_address_nv (src, scratch3);
18409 /* If .md starts supporting :P, this can be done in .md. */
18410 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18411 scratch4), UNSPEC_SCAS);
18412 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18413 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18414 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18419 /* For given symbol (function) construct code to compute address of it's PLT
18420 entry in large x86-64 PIC model. */
18422 construct_plt_address (rtx symbol)
18424 rtx tmp = gen_reg_rtx (Pmode);
18425 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18427 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18428 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18430 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18431 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18436 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18438 rtx pop, int sibcall)
18440 rtx use = NULL, call;
18441 enum calling_abi function_call_abi;
18443 if (callarg2 && INTVAL (callarg2) == -2)
18444 function_call_abi = MS_ABI;
18446 function_call_abi = SYSV_ABI;
18447 if (pop == const0_rtx)
18449 gcc_assert (!TARGET_64BIT || !pop);
18451 if (TARGET_MACHO && !TARGET_64BIT)
18454 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18455 fnaddr = machopic_indirect_call_target (fnaddr);
18460 /* Static functions and indirect calls don't need the pic register. */
18461 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18462 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18463 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18464 use_reg (&use, pic_offset_table_rtx);
18467 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18469 rtx al = gen_rtx_REG (QImode, AX_REG);
18470 emit_move_insn (al, callarg2);
18471 use_reg (&use, al);
18474 if (ix86_cmodel == CM_LARGE_PIC
18475 && GET_CODE (fnaddr) == MEM
18476 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18477 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18478 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18479 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
18481 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18482 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18484 if (sibcall && TARGET_64BIT
18485 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
18488 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18489 fnaddr = gen_rtx_REG (Pmode, R11_REG);
18490 emit_move_insn (fnaddr, addr);
18491 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18494 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18496 call = gen_rtx_SET (VOIDmode, retval, call);
18499 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18500 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18501 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18502 gcc_assert (ix86_cfun_abi () != MS_ABI || function_call_abi != SYSV_ABI);
18504 /* We need to represent that SI and DI registers are clobbered
18506 if (ix86_cfun_abi () == MS_ABI && function_call_abi == SYSV_ABI)
18508 static int clobbered_registers[] = {27, 28, 45, 46, 47, 48, 49, 50, 51,
18509 52, SI_REG, DI_REG};
18511 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18512 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18513 UNSPEC_MS_TO_SYSV_CALL);
18517 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18518 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18521 (SSE_REGNO_P (clobbered_registers[i])
18523 clobbered_registers[i]));
18525 call = gen_rtx_PARALLEL (VOIDmode,
18526 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18530 call = emit_call_insn (call);
18532 CALL_INSN_FUNCTION_USAGE (call) = use;
18536 /* Clear stack slot assignments remembered from previous functions.
18537 This is called from INIT_EXPANDERS once before RTL is emitted for each
18540 static struct machine_function *
18541 ix86_init_machine_status (void)
18543 struct machine_function *f;
18545 f = GGC_CNEW (struct machine_function);
18546 f->use_fast_prologue_epilogue_nregs = -1;
18547 f->tls_descriptor_call_expanded_p = 0;
18548 f->call_abi = DEFAULT_ABI;
18553 /* Return a MEM corresponding to a stack slot with mode MODE.
18554 Allocate a new slot if necessary.
18556 The RTL for a function can have several slots available: N is
18557 which slot to use. */
18560 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18562 struct stack_local_entry *s;
18564 gcc_assert (n < MAX_386_STACK_LOCALS);
18566 /* Virtual slot is valid only before vregs are instantiated. */
18567 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18569 for (s = ix86_stack_locals; s; s = s->next)
18570 if (s->mode == mode && s->n == n)
18571 return copy_rtx (s->rtl);
18573 s = (struct stack_local_entry *)
18574 ggc_alloc (sizeof (struct stack_local_entry));
18577 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18579 s->next = ix86_stack_locals;
18580 ix86_stack_locals = s;
18584 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18586 static GTY(()) rtx ix86_tls_symbol;
18588 ix86_tls_get_addr (void)
18591 if (!ix86_tls_symbol)
18593 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18594 (TARGET_ANY_GNU_TLS
18596 ? "___tls_get_addr"
18597 : "__tls_get_addr");
18600 return ix86_tls_symbol;
18603 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18605 static GTY(()) rtx ix86_tls_module_base_symbol;
18607 ix86_tls_module_base (void)
18610 if (!ix86_tls_module_base_symbol)
18612 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18613 "_TLS_MODULE_BASE_");
18614 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18615 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18618 return ix86_tls_module_base_symbol;
18621 /* Calculate the length of the memory address in the instruction
18622 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18625 memory_address_length (rtx addr)
18627 struct ix86_address parts;
18628 rtx base, index, disp;
18632 if (GET_CODE (addr) == PRE_DEC
18633 || GET_CODE (addr) == POST_INC
18634 || GET_CODE (addr) == PRE_MODIFY
18635 || GET_CODE (addr) == POST_MODIFY)
18638 ok = ix86_decompose_address (addr, &parts);
18641 if (parts.base && GET_CODE (parts.base) == SUBREG)
18642 parts.base = SUBREG_REG (parts.base);
18643 if (parts.index && GET_CODE (parts.index) == SUBREG)
18644 parts.index = SUBREG_REG (parts.index);
18647 index = parts.index;
18652 - esp as the base always wants an index,
18653 - ebp as the base always wants a displacement. */
18655 /* Register Indirect. */
18656 if (base && !index && !disp)
18658 /* esp (for its index) and ebp (for its displacement) need
18659 the two-byte modrm form. */
18660 if (addr == stack_pointer_rtx
18661 || addr == arg_pointer_rtx
18662 || addr == frame_pointer_rtx
18663 || addr == hard_frame_pointer_rtx)
18667 /* Direct Addressing. */
18668 else if (disp && !base && !index)
18673 /* Find the length of the displacement constant. */
18676 if (base && satisfies_constraint_K (disp))
18681 /* ebp always wants a displacement. */
18682 else if (base == hard_frame_pointer_rtx)
18685 /* An index requires the two-byte modrm form.... */
18687 /* ...like esp, which always wants an index. */
18688 || base == stack_pointer_rtx
18689 || base == arg_pointer_rtx
18690 || base == frame_pointer_rtx)
18697 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18698 is set, expect that insn have 8bit immediate alternative. */
18700 ix86_attr_length_immediate_default (rtx insn, int shortform)
18704 extract_insn_cached (insn);
18705 for (i = recog_data.n_operands - 1; i >= 0; --i)
18706 if (CONSTANT_P (recog_data.operand[i]))
18709 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
18713 switch (get_attr_mode (insn))
18724 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18729 fatal_insn ("unknown insn mode", insn);
18735 /* Compute default value for "length_address" attribute. */
18737 ix86_attr_length_address_default (rtx insn)
18741 if (get_attr_type (insn) == TYPE_LEA)
18743 rtx set = PATTERN (insn);
18745 if (GET_CODE (set) == PARALLEL)
18746 set = XVECEXP (set, 0, 0);
18748 gcc_assert (GET_CODE (set) == SET);
18750 return memory_address_length (SET_SRC (set));
18753 extract_insn_cached (insn);
18754 for (i = recog_data.n_operands - 1; i >= 0; --i)
18755 if (MEM_P (recog_data.operand[i]))
18757 return memory_address_length (XEXP (recog_data.operand[i], 0));
18763 /* Compute default value for "length_vex" attribute. It includes
18764 2 or 3 byte VEX prefix and 1 opcode byte. */
18767 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
18772 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18773 byte VEX prefix. */
18774 if (!has_0f_opcode || has_vex_w)
18777 /* We can always use 2 byte VEX prefix in 32bit. */
18781 extract_insn_cached (insn);
18783 for (i = recog_data.n_operands - 1; i >= 0; --i)
18784 if (REG_P (recog_data.operand[i]))
18786 /* REX.W bit uses 3 byte VEX prefix. */
18787 if (GET_MODE (recog_data.operand[i]) == DImode)
18792 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18793 if (MEM_P (recog_data.operand[i])
18794 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
18801 /* Return the maximum number of instructions a cpu can issue. */
18804 ix86_issue_rate (void)
18808 case PROCESSOR_PENTIUM:
18812 case PROCESSOR_PENTIUMPRO:
18813 case PROCESSOR_PENTIUM4:
18814 case PROCESSOR_ATHLON:
18816 case PROCESSOR_AMDFAM10:
18817 case PROCESSOR_NOCONA:
18818 case PROCESSOR_GENERIC32:
18819 case PROCESSOR_GENERIC64:
18822 case PROCESSOR_CORE2:
18830 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
18831 by DEP_INSN and nothing set by DEP_INSN. */
18834 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
18838 /* Simplify the test for uninteresting insns. */
18839 if (insn_type != TYPE_SETCC
18840 && insn_type != TYPE_ICMOV
18841 && insn_type != TYPE_FCMOV
18842 && insn_type != TYPE_IBR)
18845 if ((set = single_set (dep_insn)) != 0)
18847 set = SET_DEST (set);
18850 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
18851 && XVECLEN (PATTERN (dep_insn), 0) == 2
18852 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
18853 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
18855 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
18856 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
18861 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
18864 /* This test is true if the dependent insn reads the flags but
18865 not any other potentially set register. */
18866 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
18869 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
18875 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
18876 address with operands set by DEP_INSN. */
18879 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
18883 if (insn_type == TYPE_LEA
18886 addr = PATTERN (insn);
18888 if (GET_CODE (addr) == PARALLEL)
18889 addr = XVECEXP (addr, 0, 0);
18891 gcc_assert (GET_CODE (addr) == SET);
18893 addr = SET_SRC (addr);
18898 extract_insn_cached (insn);
18899 for (i = recog_data.n_operands - 1; i >= 0; --i)
18900 if (MEM_P (recog_data.operand[i]))
18902 addr = XEXP (recog_data.operand[i], 0);
18909 return modified_in_p (addr, dep_insn);
18913 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
18915 enum attr_type insn_type, dep_insn_type;
18916 enum attr_memory memory;
18918 int dep_insn_code_number;
18920 /* Anti and output dependencies have zero cost on all CPUs. */
18921 if (REG_NOTE_KIND (link) != 0)
18924 dep_insn_code_number = recog_memoized (dep_insn);
18926 /* If we can't recognize the insns, we can't really do anything. */
18927 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
18930 insn_type = get_attr_type (insn);
18931 dep_insn_type = get_attr_type (dep_insn);
18935 case PROCESSOR_PENTIUM:
18936 /* Address Generation Interlock adds a cycle of latency. */
18937 if (ix86_agi_dependent (insn, dep_insn, insn_type))
18940 /* ??? Compares pair with jump/setcc. */
18941 if (ix86_flags_dependent (insn, dep_insn, insn_type))
18944 /* Floating point stores require value to be ready one cycle earlier. */
18945 if (insn_type == TYPE_FMOV
18946 && get_attr_memory (insn) == MEMORY_STORE
18947 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18951 case PROCESSOR_PENTIUMPRO:
18952 memory = get_attr_memory (insn);
18954 /* INT->FP conversion is expensive. */
18955 if (get_attr_fp_int_src (dep_insn))
18958 /* There is one cycle extra latency between an FP op and a store. */
18959 if (insn_type == TYPE_FMOV
18960 && (set = single_set (dep_insn)) != NULL_RTX
18961 && (set2 = single_set (insn)) != NULL_RTX
18962 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
18963 && MEM_P (SET_DEST (set2)))
18966 /* Show ability of reorder buffer to hide latency of load by executing
18967 in parallel with previous instruction in case
18968 previous instruction is not needed to compute the address. */
18969 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18970 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18972 /* Claim moves to take one cycle, as core can issue one load
18973 at time and the next load can start cycle later. */
18974 if (dep_insn_type == TYPE_IMOV
18975 || dep_insn_type == TYPE_FMOV)
18983 memory = get_attr_memory (insn);
18985 /* The esp dependency is resolved before the instruction is really
18987 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
18988 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
18991 /* INT->FP conversion is expensive. */
18992 if (get_attr_fp_int_src (dep_insn))
18995 /* Show ability of reorder buffer to hide latency of load by executing
18996 in parallel with previous instruction in case
18997 previous instruction is not needed to compute the address. */
18998 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18999 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19001 /* Claim moves to take one cycle, as core can issue one load
19002 at time and the next load can start cycle later. */
19003 if (dep_insn_type == TYPE_IMOV
19004 || dep_insn_type == TYPE_FMOV)
19013 case PROCESSOR_ATHLON:
19015 case PROCESSOR_AMDFAM10:
19016 case PROCESSOR_GENERIC32:
19017 case PROCESSOR_GENERIC64:
19018 memory = get_attr_memory (insn);
19020 /* Show ability of reorder buffer to hide latency of load by executing
19021 in parallel with previous instruction in case
19022 previous instruction is not needed to compute the address. */
19023 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19024 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19026 enum attr_unit unit = get_attr_unit (insn);
19029 /* Because of the difference between the length of integer and
19030 floating unit pipeline preparation stages, the memory operands
19031 for floating point are cheaper.
19033 ??? For Athlon it the difference is most probably 2. */
19034 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19037 loadcost = TARGET_ATHLON ? 2 : 0;
19039 if (cost >= loadcost)
19052 /* How many alternative schedules to try. This should be as wide as the
19053 scheduling freedom in the DFA, but no wider. Making this value too
19054 large results extra work for the scheduler. */
19057 ia32_multipass_dfa_lookahead (void)
19061 case PROCESSOR_PENTIUM:
19064 case PROCESSOR_PENTIUMPRO:
19074 /* Compute the alignment given to a constant that is being placed in memory.
19075 EXP is the constant and ALIGN is the alignment that the object would
19077 The value of this function is used instead of that alignment to align
19081 ix86_constant_alignment (tree exp, int align)
19083 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19084 || TREE_CODE (exp) == INTEGER_CST)
19086 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19088 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19091 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19092 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19093 return BITS_PER_WORD;
19098 /* Compute the alignment for a static variable.
19099 TYPE is the data type, and ALIGN is the alignment that
19100 the object would ordinarily have. The value of this function is used
19101 instead of that alignment to align the object. */
19104 ix86_data_alignment (tree type, int align)
19106 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19108 if (AGGREGATE_TYPE_P (type)
19109 && TYPE_SIZE (type)
19110 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19111 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19112 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19113 && align < max_align)
19116 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19117 to 16byte boundary. */
19120 if (AGGREGATE_TYPE_P (type)
19121 && TYPE_SIZE (type)
19122 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19123 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19124 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19128 if (TREE_CODE (type) == ARRAY_TYPE)
19130 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19132 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19135 else if (TREE_CODE (type) == COMPLEX_TYPE)
19138 if (TYPE_MODE (type) == DCmode && align < 64)
19140 if ((TYPE_MODE (type) == XCmode
19141 || TYPE_MODE (type) == TCmode) && align < 128)
19144 else if ((TREE_CODE (type) == RECORD_TYPE
19145 || TREE_CODE (type) == UNION_TYPE
19146 || TREE_CODE (type) == QUAL_UNION_TYPE)
19147 && TYPE_FIELDS (type))
19149 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19151 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19154 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19155 || TREE_CODE (type) == INTEGER_TYPE)
19157 if (TYPE_MODE (type) == DFmode && align < 64)
19159 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19166 /* Compute the alignment for a local variable or a stack slot. TYPE is
19167 the data type, MODE is the widest mode available and ALIGN is the
19168 alignment that the object would ordinarily have. The value of this
19169 macro is used instead of that alignment to align the object. */
19172 ix86_local_alignment (tree type, enum machine_mode mode,
19173 unsigned int align)
19175 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19176 register in MODE. We will return the largest alignment of XF
19180 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19181 align = GET_MODE_ALIGNMENT (DFmode);
19185 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19186 to 16byte boundary. */
19189 if (AGGREGATE_TYPE_P (type)
19190 && TYPE_SIZE (type)
19191 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19192 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19193 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19196 if (TREE_CODE (type) == ARRAY_TYPE)
19198 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19200 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19203 else if (TREE_CODE (type) == COMPLEX_TYPE)
19205 if (TYPE_MODE (type) == DCmode && align < 64)
19207 if ((TYPE_MODE (type) == XCmode
19208 || TYPE_MODE (type) == TCmode) && align < 128)
19211 else if ((TREE_CODE (type) == RECORD_TYPE
19212 || TREE_CODE (type) == UNION_TYPE
19213 || TREE_CODE (type) == QUAL_UNION_TYPE)
19214 && TYPE_FIELDS (type))
19216 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19218 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19221 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19222 || TREE_CODE (type) == INTEGER_TYPE)
19225 if (TYPE_MODE (type) == DFmode && align < 64)
19227 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19233 /* Emit RTL insns to initialize the variable parts of a trampoline.
19234 FNADDR is an RTX for the address of the function's pure code.
19235 CXT is an RTX for the static chain value for the function. */
19237 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19241 /* Compute offset from the end of the jmp to the target function. */
19242 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19243 plus_constant (tramp, 10),
19244 NULL_RTX, 1, OPTAB_DIRECT);
19245 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19246 gen_int_mode (0xb9, QImode));
19247 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19248 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19249 gen_int_mode (0xe9, QImode));
19250 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19255 /* Try to load address using shorter movl instead of movabs.
19256 We may want to support movq for kernel mode, but kernel does not use
19257 trampolines at the moment. */
19258 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19260 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19261 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19262 gen_int_mode (0xbb41, HImode));
19263 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19264 gen_lowpart (SImode, fnaddr));
19269 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19270 gen_int_mode (0xbb49, HImode));
19271 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19275 /* Load static chain using movabs to r10. */
19276 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19277 gen_int_mode (0xba49, HImode));
19278 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19281 /* Jump to the r11 */
19282 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19283 gen_int_mode (0xff49, HImode));
19284 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19285 gen_int_mode (0xe3, QImode));
19287 gcc_assert (offset <= TRAMPOLINE_SIZE);
19290 #ifdef ENABLE_EXECUTE_STACK
19291 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19292 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19296 /* Codes for all the SSE/MMX builtins. */
19299 IX86_BUILTIN_ADDPS,
19300 IX86_BUILTIN_ADDSS,
19301 IX86_BUILTIN_DIVPS,
19302 IX86_BUILTIN_DIVSS,
19303 IX86_BUILTIN_MULPS,
19304 IX86_BUILTIN_MULSS,
19305 IX86_BUILTIN_SUBPS,
19306 IX86_BUILTIN_SUBSS,
19308 IX86_BUILTIN_CMPEQPS,
19309 IX86_BUILTIN_CMPLTPS,
19310 IX86_BUILTIN_CMPLEPS,
19311 IX86_BUILTIN_CMPGTPS,
19312 IX86_BUILTIN_CMPGEPS,
19313 IX86_BUILTIN_CMPNEQPS,
19314 IX86_BUILTIN_CMPNLTPS,
19315 IX86_BUILTIN_CMPNLEPS,
19316 IX86_BUILTIN_CMPNGTPS,
19317 IX86_BUILTIN_CMPNGEPS,
19318 IX86_BUILTIN_CMPORDPS,
19319 IX86_BUILTIN_CMPUNORDPS,
19320 IX86_BUILTIN_CMPEQSS,
19321 IX86_BUILTIN_CMPLTSS,
19322 IX86_BUILTIN_CMPLESS,
19323 IX86_BUILTIN_CMPNEQSS,
19324 IX86_BUILTIN_CMPNLTSS,
19325 IX86_BUILTIN_CMPNLESS,
19326 IX86_BUILTIN_CMPNGTSS,
19327 IX86_BUILTIN_CMPNGESS,
19328 IX86_BUILTIN_CMPORDSS,
19329 IX86_BUILTIN_CMPUNORDSS,
19331 IX86_BUILTIN_COMIEQSS,
19332 IX86_BUILTIN_COMILTSS,
19333 IX86_BUILTIN_COMILESS,
19334 IX86_BUILTIN_COMIGTSS,
19335 IX86_BUILTIN_COMIGESS,
19336 IX86_BUILTIN_COMINEQSS,
19337 IX86_BUILTIN_UCOMIEQSS,
19338 IX86_BUILTIN_UCOMILTSS,
19339 IX86_BUILTIN_UCOMILESS,
19340 IX86_BUILTIN_UCOMIGTSS,
19341 IX86_BUILTIN_UCOMIGESS,
19342 IX86_BUILTIN_UCOMINEQSS,
19344 IX86_BUILTIN_CVTPI2PS,
19345 IX86_BUILTIN_CVTPS2PI,
19346 IX86_BUILTIN_CVTSI2SS,
19347 IX86_BUILTIN_CVTSI642SS,
19348 IX86_BUILTIN_CVTSS2SI,
19349 IX86_BUILTIN_CVTSS2SI64,
19350 IX86_BUILTIN_CVTTPS2PI,
19351 IX86_BUILTIN_CVTTSS2SI,
19352 IX86_BUILTIN_CVTTSS2SI64,
19354 IX86_BUILTIN_MAXPS,
19355 IX86_BUILTIN_MAXSS,
19356 IX86_BUILTIN_MINPS,
19357 IX86_BUILTIN_MINSS,
19359 IX86_BUILTIN_LOADUPS,
19360 IX86_BUILTIN_STOREUPS,
19361 IX86_BUILTIN_MOVSS,
19363 IX86_BUILTIN_MOVHLPS,
19364 IX86_BUILTIN_MOVLHPS,
19365 IX86_BUILTIN_LOADHPS,
19366 IX86_BUILTIN_LOADLPS,
19367 IX86_BUILTIN_STOREHPS,
19368 IX86_BUILTIN_STORELPS,
19370 IX86_BUILTIN_MASKMOVQ,
19371 IX86_BUILTIN_MOVMSKPS,
19372 IX86_BUILTIN_PMOVMSKB,
19374 IX86_BUILTIN_MOVNTPS,
19375 IX86_BUILTIN_MOVNTQ,
19377 IX86_BUILTIN_LOADDQU,
19378 IX86_BUILTIN_STOREDQU,
19380 IX86_BUILTIN_PACKSSWB,
19381 IX86_BUILTIN_PACKSSDW,
19382 IX86_BUILTIN_PACKUSWB,
19384 IX86_BUILTIN_PADDB,
19385 IX86_BUILTIN_PADDW,
19386 IX86_BUILTIN_PADDD,
19387 IX86_BUILTIN_PADDQ,
19388 IX86_BUILTIN_PADDSB,
19389 IX86_BUILTIN_PADDSW,
19390 IX86_BUILTIN_PADDUSB,
19391 IX86_BUILTIN_PADDUSW,
19392 IX86_BUILTIN_PSUBB,
19393 IX86_BUILTIN_PSUBW,
19394 IX86_BUILTIN_PSUBD,
19395 IX86_BUILTIN_PSUBQ,
19396 IX86_BUILTIN_PSUBSB,
19397 IX86_BUILTIN_PSUBSW,
19398 IX86_BUILTIN_PSUBUSB,
19399 IX86_BUILTIN_PSUBUSW,
19402 IX86_BUILTIN_PANDN,
19406 IX86_BUILTIN_PAVGB,
19407 IX86_BUILTIN_PAVGW,
19409 IX86_BUILTIN_PCMPEQB,
19410 IX86_BUILTIN_PCMPEQW,
19411 IX86_BUILTIN_PCMPEQD,
19412 IX86_BUILTIN_PCMPGTB,
19413 IX86_BUILTIN_PCMPGTW,
19414 IX86_BUILTIN_PCMPGTD,
19416 IX86_BUILTIN_PMADDWD,
19418 IX86_BUILTIN_PMAXSW,
19419 IX86_BUILTIN_PMAXUB,
19420 IX86_BUILTIN_PMINSW,
19421 IX86_BUILTIN_PMINUB,
19423 IX86_BUILTIN_PMULHUW,
19424 IX86_BUILTIN_PMULHW,
19425 IX86_BUILTIN_PMULLW,
19427 IX86_BUILTIN_PSADBW,
19428 IX86_BUILTIN_PSHUFW,
19430 IX86_BUILTIN_PSLLW,
19431 IX86_BUILTIN_PSLLD,
19432 IX86_BUILTIN_PSLLQ,
19433 IX86_BUILTIN_PSRAW,
19434 IX86_BUILTIN_PSRAD,
19435 IX86_BUILTIN_PSRLW,
19436 IX86_BUILTIN_PSRLD,
19437 IX86_BUILTIN_PSRLQ,
19438 IX86_BUILTIN_PSLLWI,
19439 IX86_BUILTIN_PSLLDI,
19440 IX86_BUILTIN_PSLLQI,
19441 IX86_BUILTIN_PSRAWI,
19442 IX86_BUILTIN_PSRADI,
19443 IX86_BUILTIN_PSRLWI,
19444 IX86_BUILTIN_PSRLDI,
19445 IX86_BUILTIN_PSRLQI,
19447 IX86_BUILTIN_PUNPCKHBW,
19448 IX86_BUILTIN_PUNPCKHWD,
19449 IX86_BUILTIN_PUNPCKHDQ,
19450 IX86_BUILTIN_PUNPCKLBW,
19451 IX86_BUILTIN_PUNPCKLWD,
19452 IX86_BUILTIN_PUNPCKLDQ,
19454 IX86_BUILTIN_SHUFPS,
19456 IX86_BUILTIN_RCPPS,
19457 IX86_BUILTIN_RCPSS,
19458 IX86_BUILTIN_RSQRTPS,
19459 IX86_BUILTIN_RSQRTPS_NR,
19460 IX86_BUILTIN_RSQRTSS,
19461 IX86_BUILTIN_RSQRTF,
19462 IX86_BUILTIN_SQRTPS,
19463 IX86_BUILTIN_SQRTPS_NR,
19464 IX86_BUILTIN_SQRTSS,
19466 IX86_BUILTIN_UNPCKHPS,
19467 IX86_BUILTIN_UNPCKLPS,
19469 IX86_BUILTIN_ANDPS,
19470 IX86_BUILTIN_ANDNPS,
19472 IX86_BUILTIN_XORPS,
19475 IX86_BUILTIN_LDMXCSR,
19476 IX86_BUILTIN_STMXCSR,
19477 IX86_BUILTIN_SFENCE,
19479 /* 3DNow! Original */
19480 IX86_BUILTIN_FEMMS,
19481 IX86_BUILTIN_PAVGUSB,
19482 IX86_BUILTIN_PF2ID,
19483 IX86_BUILTIN_PFACC,
19484 IX86_BUILTIN_PFADD,
19485 IX86_BUILTIN_PFCMPEQ,
19486 IX86_BUILTIN_PFCMPGE,
19487 IX86_BUILTIN_PFCMPGT,
19488 IX86_BUILTIN_PFMAX,
19489 IX86_BUILTIN_PFMIN,
19490 IX86_BUILTIN_PFMUL,
19491 IX86_BUILTIN_PFRCP,
19492 IX86_BUILTIN_PFRCPIT1,
19493 IX86_BUILTIN_PFRCPIT2,
19494 IX86_BUILTIN_PFRSQIT1,
19495 IX86_BUILTIN_PFRSQRT,
19496 IX86_BUILTIN_PFSUB,
19497 IX86_BUILTIN_PFSUBR,
19498 IX86_BUILTIN_PI2FD,
19499 IX86_BUILTIN_PMULHRW,
19501 /* 3DNow! Athlon Extensions */
19502 IX86_BUILTIN_PF2IW,
19503 IX86_BUILTIN_PFNACC,
19504 IX86_BUILTIN_PFPNACC,
19505 IX86_BUILTIN_PI2FW,
19506 IX86_BUILTIN_PSWAPDSI,
19507 IX86_BUILTIN_PSWAPDSF,
19510 IX86_BUILTIN_ADDPD,
19511 IX86_BUILTIN_ADDSD,
19512 IX86_BUILTIN_DIVPD,
19513 IX86_BUILTIN_DIVSD,
19514 IX86_BUILTIN_MULPD,
19515 IX86_BUILTIN_MULSD,
19516 IX86_BUILTIN_SUBPD,
19517 IX86_BUILTIN_SUBSD,
19519 IX86_BUILTIN_CMPEQPD,
19520 IX86_BUILTIN_CMPLTPD,
19521 IX86_BUILTIN_CMPLEPD,
19522 IX86_BUILTIN_CMPGTPD,
19523 IX86_BUILTIN_CMPGEPD,
19524 IX86_BUILTIN_CMPNEQPD,
19525 IX86_BUILTIN_CMPNLTPD,
19526 IX86_BUILTIN_CMPNLEPD,
19527 IX86_BUILTIN_CMPNGTPD,
19528 IX86_BUILTIN_CMPNGEPD,
19529 IX86_BUILTIN_CMPORDPD,
19530 IX86_BUILTIN_CMPUNORDPD,
19531 IX86_BUILTIN_CMPEQSD,
19532 IX86_BUILTIN_CMPLTSD,
19533 IX86_BUILTIN_CMPLESD,
19534 IX86_BUILTIN_CMPNEQSD,
19535 IX86_BUILTIN_CMPNLTSD,
19536 IX86_BUILTIN_CMPNLESD,
19537 IX86_BUILTIN_CMPORDSD,
19538 IX86_BUILTIN_CMPUNORDSD,
19540 IX86_BUILTIN_COMIEQSD,
19541 IX86_BUILTIN_COMILTSD,
19542 IX86_BUILTIN_COMILESD,
19543 IX86_BUILTIN_COMIGTSD,
19544 IX86_BUILTIN_COMIGESD,
19545 IX86_BUILTIN_COMINEQSD,
19546 IX86_BUILTIN_UCOMIEQSD,
19547 IX86_BUILTIN_UCOMILTSD,
19548 IX86_BUILTIN_UCOMILESD,
19549 IX86_BUILTIN_UCOMIGTSD,
19550 IX86_BUILTIN_UCOMIGESD,
19551 IX86_BUILTIN_UCOMINEQSD,
19553 IX86_BUILTIN_MAXPD,
19554 IX86_BUILTIN_MAXSD,
19555 IX86_BUILTIN_MINPD,
19556 IX86_BUILTIN_MINSD,
19558 IX86_BUILTIN_ANDPD,
19559 IX86_BUILTIN_ANDNPD,
19561 IX86_BUILTIN_XORPD,
19563 IX86_BUILTIN_SQRTPD,
19564 IX86_BUILTIN_SQRTSD,
19566 IX86_BUILTIN_UNPCKHPD,
19567 IX86_BUILTIN_UNPCKLPD,
19569 IX86_BUILTIN_SHUFPD,
19571 IX86_BUILTIN_LOADUPD,
19572 IX86_BUILTIN_STOREUPD,
19573 IX86_BUILTIN_MOVSD,
19575 IX86_BUILTIN_LOADHPD,
19576 IX86_BUILTIN_LOADLPD,
19578 IX86_BUILTIN_CVTDQ2PD,
19579 IX86_BUILTIN_CVTDQ2PS,
19581 IX86_BUILTIN_CVTPD2DQ,
19582 IX86_BUILTIN_CVTPD2PI,
19583 IX86_BUILTIN_CVTPD2PS,
19584 IX86_BUILTIN_CVTTPD2DQ,
19585 IX86_BUILTIN_CVTTPD2PI,
19587 IX86_BUILTIN_CVTPI2PD,
19588 IX86_BUILTIN_CVTSI2SD,
19589 IX86_BUILTIN_CVTSI642SD,
19591 IX86_BUILTIN_CVTSD2SI,
19592 IX86_BUILTIN_CVTSD2SI64,
19593 IX86_BUILTIN_CVTSD2SS,
19594 IX86_BUILTIN_CVTSS2SD,
19595 IX86_BUILTIN_CVTTSD2SI,
19596 IX86_BUILTIN_CVTTSD2SI64,
19598 IX86_BUILTIN_CVTPS2DQ,
19599 IX86_BUILTIN_CVTPS2PD,
19600 IX86_BUILTIN_CVTTPS2DQ,
19602 IX86_BUILTIN_MOVNTI,
19603 IX86_BUILTIN_MOVNTPD,
19604 IX86_BUILTIN_MOVNTDQ,
19606 IX86_BUILTIN_MOVQ128,
19609 IX86_BUILTIN_MASKMOVDQU,
19610 IX86_BUILTIN_MOVMSKPD,
19611 IX86_BUILTIN_PMOVMSKB128,
19613 IX86_BUILTIN_PACKSSWB128,
19614 IX86_BUILTIN_PACKSSDW128,
19615 IX86_BUILTIN_PACKUSWB128,
19617 IX86_BUILTIN_PADDB128,
19618 IX86_BUILTIN_PADDW128,
19619 IX86_BUILTIN_PADDD128,
19620 IX86_BUILTIN_PADDQ128,
19621 IX86_BUILTIN_PADDSB128,
19622 IX86_BUILTIN_PADDSW128,
19623 IX86_BUILTIN_PADDUSB128,
19624 IX86_BUILTIN_PADDUSW128,
19625 IX86_BUILTIN_PSUBB128,
19626 IX86_BUILTIN_PSUBW128,
19627 IX86_BUILTIN_PSUBD128,
19628 IX86_BUILTIN_PSUBQ128,
19629 IX86_BUILTIN_PSUBSB128,
19630 IX86_BUILTIN_PSUBSW128,
19631 IX86_BUILTIN_PSUBUSB128,
19632 IX86_BUILTIN_PSUBUSW128,
19634 IX86_BUILTIN_PAND128,
19635 IX86_BUILTIN_PANDN128,
19636 IX86_BUILTIN_POR128,
19637 IX86_BUILTIN_PXOR128,
19639 IX86_BUILTIN_PAVGB128,
19640 IX86_BUILTIN_PAVGW128,
19642 IX86_BUILTIN_PCMPEQB128,
19643 IX86_BUILTIN_PCMPEQW128,
19644 IX86_BUILTIN_PCMPEQD128,
19645 IX86_BUILTIN_PCMPGTB128,
19646 IX86_BUILTIN_PCMPGTW128,
19647 IX86_BUILTIN_PCMPGTD128,
19649 IX86_BUILTIN_PMADDWD128,
19651 IX86_BUILTIN_PMAXSW128,
19652 IX86_BUILTIN_PMAXUB128,
19653 IX86_BUILTIN_PMINSW128,
19654 IX86_BUILTIN_PMINUB128,
19656 IX86_BUILTIN_PMULUDQ,
19657 IX86_BUILTIN_PMULUDQ128,
19658 IX86_BUILTIN_PMULHUW128,
19659 IX86_BUILTIN_PMULHW128,
19660 IX86_BUILTIN_PMULLW128,
19662 IX86_BUILTIN_PSADBW128,
19663 IX86_BUILTIN_PSHUFHW,
19664 IX86_BUILTIN_PSHUFLW,
19665 IX86_BUILTIN_PSHUFD,
19667 IX86_BUILTIN_PSLLDQI128,
19668 IX86_BUILTIN_PSLLWI128,
19669 IX86_BUILTIN_PSLLDI128,
19670 IX86_BUILTIN_PSLLQI128,
19671 IX86_BUILTIN_PSRAWI128,
19672 IX86_BUILTIN_PSRADI128,
19673 IX86_BUILTIN_PSRLDQI128,
19674 IX86_BUILTIN_PSRLWI128,
19675 IX86_BUILTIN_PSRLDI128,
19676 IX86_BUILTIN_PSRLQI128,
19678 IX86_BUILTIN_PSLLDQ128,
19679 IX86_BUILTIN_PSLLW128,
19680 IX86_BUILTIN_PSLLD128,
19681 IX86_BUILTIN_PSLLQ128,
19682 IX86_BUILTIN_PSRAW128,
19683 IX86_BUILTIN_PSRAD128,
19684 IX86_BUILTIN_PSRLW128,
19685 IX86_BUILTIN_PSRLD128,
19686 IX86_BUILTIN_PSRLQ128,
19688 IX86_BUILTIN_PUNPCKHBW128,
19689 IX86_BUILTIN_PUNPCKHWD128,
19690 IX86_BUILTIN_PUNPCKHDQ128,
19691 IX86_BUILTIN_PUNPCKHQDQ128,
19692 IX86_BUILTIN_PUNPCKLBW128,
19693 IX86_BUILTIN_PUNPCKLWD128,
19694 IX86_BUILTIN_PUNPCKLDQ128,
19695 IX86_BUILTIN_PUNPCKLQDQ128,
19697 IX86_BUILTIN_CLFLUSH,
19698 IX86_BUILTIN_MFENCE,
19699 IX86_BUILTIN_LFENCE,
19702 IX86_BUILTIN_ADDSUBPS,
19703 IX86_BUILTIN_HADDPS,
19704 IX86_BUILTIN_HSUBPS,
19705 IX86_BUILTIN_MOVSHDUP,
19706 IX86_BUILTIN_MOVSLDUP,
19707 IX86_BUILTIN_ADDSUBPD,
19708 IX86_BUILTIN_HADDPD,
19709 IX86_BUILTIN_HSUBPD,
19710 IX86_BUILTIN_LDDQU,
19712 IX86_BUILTIN_MONITOR,
19713 IX86_BUILTIN_MWAIT,
19716 IX86_BUILTIN_PHADDW,
19717 IX86_BUILTIN_PHADDD,
19718 IX86_BUILTIN_PHADDSW,
19719 IX86_BUILTIN_PHSUBW,
19720 IX86_BUILTIN_PHSUBD,
19721 IX86_BUILTIN_PHSUBSW,
19722 IX86_BUILTIN_PMADDUBSW,
19723 IX86_BUILTIN_PMULHRSW,
19724 IX86_BUILTIN_PSHUFB,
19725 IX86_BUILTIN_PSIGNB,
19726 IX86_BUILTIN_PSIGNW,
19727 IX86_BUILTIN_PSIGND,
19728 IX86_BUILTIN_PALIGNR,
19729 IX86_BUILTIN_PABSB,
19730 IX86_BUILTIN_PABSW,
19731 IX86_BUILTIN_PABSD,
19733 IX86_BUILTIN_PHADDW128,
19734 IX86_BUILTIN_PHADDD128,
19735 IX86_BUILTIN_PHADDSW128,
19736 IX86_BUILTIN_PHSUBW128,
19737 IX86_BUILTIN_PHSUBD128,
19738 IX86_BUILTIN_PHSUBSW128,
19739 IX86_BUILTIN_PMADDUBSW128,
19740 IX86_BUILTIN_PMULHRSW128,
19741 IX86_BUILTIN_PSHUFB128,
19742 IX86_BUILTIN_PSIGNB128,
19743 IX86_BUILTIN_PSIGNW128,
19744 IX86_BUILTIN_PSIGND128,
19745 IX86_BUILTIN_PALIGNR128,
19746 IX86_BUILTIN_PABSB128,
19747 IX86_BUILTIN_PABSW128,
19748 IX86_BUILTIN_PABSD128,
19750 /* AMDFAM10 - SSE4A New Instructions. */
19751 IX86_BUILTIN_MOVNTSD,
19752 IX86_BUILTIN_MOVNTSS,
19753 IX86_BUILTIN_EXTRQI,
19754 IX86_BUILTIN_EXTRQ,
19755 IX86_BUILTIN_INSERTQI,
19756 IX86_BUILTIN_INSERTQ,
19759 IX86_BUILTIN_BLENDPD,
19760 IX86_BUILTIN_BLENDPS,
19761 IX86_BUILTIN_BLENDVPD,
19762 IX86_BUILTIN_BLENDVPS,
19763 IX86_BUILTIN_PBLENDVB128,
19764 IX86_BUILTIN_PBLENDW128,
19769 IX86_BUILTIN_INSERTPS128,
19771 IX86_BUILTIN_MOVNTDQA,
19772 IX86_BUILTIN_MPSADBW128,
19773 IX86_BUILTIN_PACKUSDW128,
19774 IX86_BUILTIN_PCMPEQQ,
19775 IX86_BUILTIN_PHMINPOSUW128,
19777 IX86_BUILTIN_PMAXSB128,
19778 IX86_BUILTIN_PMAXSD128,
19779 IX86_BUILTIN_PMAXUD128,
19780 IX86_BUILTIN_PMAXUW128,
19782 IX86_BUILTIN_PMINSB128,
19783 IX86_BUILTIN_PMINSD128,
19784 IX86_BUILTIN_PMINUD128,
19785 IX86_BUILTIN_PMINUW128,
19787 IX86_BUILTIN_PMOVSXBW128,
19788 IX86_BUILTIN_PMOVSXBD128,
19789 IX86_BUILTIN_PMOVSXBQ128,
19790 IX86_BUILTIN_PMOVSXWD128,
19791 IX86_BUILTIN_PMOVSXWQ128,
19792 IX86_BUILTIN_PMOVSXDQ128,
19794 IX86_BUILTIN_PMOVZXBW128,
19795 IX86_BUILTIN_PMOVZXBD128,
19796 IX86_BUILTIN_PMOVZXBQ128,
19797 IX86_BUILTIN_PMOVZXWD128,
19798 IX86_BUILTIN_PMOVZXWQ128,
19799 IX86_BUILTIN_PMOVZXDQ128,
19801 IX86_BUILTIN_PMULDQ128,
19802 IX86_BUILTIN_PMULLD128,
19804 IX86_BUILTIN_ROUNDPD,
19805 IX86_BUILTIN_ROUNDPS,
19806 IX86_BUILTIN_ROUNDSD,
19807 IX86_BUILTIN_ROUNDSS,
19809 IX86_BUILTIN_PTESTZ,
19810 IX86_BUILTIN_PTESTC,
19811 IX86_BUILTIN_PTESTNZC,
19813 IX86_BUILTIN_VEC_INIT_V2SI,
19814 IX86_BUILTIN_VEC_INIT_V4HI,
19815 IX86_BUILTIN_VEC_INIT_V8QI,
19816 IX86_BUILTIN_VEC_EXT_V2DF,
19817 IX86_BUILTIN_VEC_EXT_V2DI,
19818 IX86_BUILTIN_VEC_EXT_V4SF,
19819 IX86_BUILTIN_VEC_EXT_V4SI,
19820 IX86_BUILTIN_VEC_EXT_V8HI,
19821 IX86_BUILTIN_VEC_EXT_V2SI,
19822 IX86_BUILTIN_VEC_EXT_V4HI,
19823 IX86_BUILTIN_VEC_EXT_V16QI,
19824 IX86_BUILTIN_VEC_SET_V2DI,
19825 IX86_BUILTIN_VEC_SET_V4SF,
19826 IX86_BUILTIN_VEC_SET_V4SI,
19827 IX86_BUILTIN_VEC_SET_V8HI,
19828 IX86_BUILTIN_VEC_SET_V4HI,
19829 IX86_BUILTIN_VEC_SET_V16QI,
19831 IX86_BUILTIN_VEC_PACK_SFIX,
19834 IX86_BUILTIN_CRC32QI,
19835 IX86_BUILTIN_CRC32HI,
19836 IX86_BUILTIN_CRC32SI,
19837 IX86_BUILTIN_CRC32DI,
19839 IX86_BUILTIN_PCMPESTRI128,
19840 IX86_BUILTIN_PCMPESTRM128,
19841 IX86_BUILTIN_PCMPESTRA128,
19842 IX86_BUILTIN_PCMPESTRC128,
19843 IX86_BUILTIN_PCMPESTRO128,
19844 IX86_BUILTIN_PCMPESTRS128,
19845 IX86_BUILTIN_PCMPESTRZ128,
19846 IX86_BUILTIN_PCMPISTRI128,
19847 IX86_BUILTIN_PCMPISTRM128,
19848 IX86_BUILTIN_PCMPISTRA128,
19849 IX86_BUILTIN_PCMPISTRC128,
19850 IX86_BUILTIN_PCMPISTRO128,
19851 IX86_BUILTIN_PCMPISTRS128,
19852 IX86_BUILTIN_PCMPISTRZ128,
19854 IX86_BUILTIN_PCMPGTQ,
19856 /* AES instructions */
19857 IX86_BUILTIN_AESENC128,
19858 IX86_BUILTIN_AESENCLAST128,
19859 IX86_BUILTIN_AESDEC128,
19860 IX86_BUILTIN_AESDECLAST128,
19861 IX86_BUILTIN_AESIMC128,
19862 IX86_BUILTIN_AESKEYGENASSIST128,
19864 /* PCLMUL instruction */
19865 IX86_BUILTIN_PCLMULQDQ128,
19868 IX86_BUILTIN_ADDPD256,
19869 IX86_BUILTIN_ADDPS256,
19870 IX86_BUILTIN_ADDSUBPD256,
19871 IX86_BUILTIN_ADDSUBPS256,
19872 IX86_BUILTIN_ANDPD256,
19873 IX86_BUILTIN_ANDPS256,
19874 IX86_BUILTIN_ANDNPD256,
19875 IX86_BUILTIN_ANDNPS256,
19876 IX86_BUILTIN_BLENDPD256,
19877 IX86_BUILTIN_BLENDPS256,
19878 IX86_BUILTIN_BLENDVPD256,
19879 IX86_BUILTIN_BLENDVPS256,
19880 IX86_BUILTIN_DIVPD256,
19881 IX86_BUILTIN_DIVPS256,
19882 IX86_BUILTIN_DPPS256,
19883 IX86_BUILTIN_HADDPD256,
19884 IX86_BUILTIN_HADDPS256,
19885 IX86_BUILTIN_HSUBPD256,
19886 IX86_BUILTIN_HSUBPS256,
19887 IX86_BUILTIN_MAXPD256,
19888 IX86_BUILTIN_MAXPS256,
19889 IX86_BUILTIN_MINPD256,
19890 IX86_BUILTIN_MINPS256,
19891 IX86_BUILTIN_MULPD256,
19892 IX86_BUILTIN_MULPS256,
19893 IX86_BUILTIN_ORPD256,
19894 IX86_BUILTIN_ORPS256,
19895 IX86_BUILTIN_SHUFPD256,
19896 IX86_BUILTIN_SHUFPS256,
19897 IX86_BUILTIN_SUBPD256,
19898 IX86_BUILTIN_SUBPS256,
19899 IX86_BUILTIN_XORPD256,
19900 IX86_BUILTIN_XORPS256,
19901 IX86_BUILTIN_CMPSD,
19902 IX86_BUILTIN_CMPSS,
19903 IX86_BUILTIN_CMPPD,
19904 IX86_BUILTIN_CMPPS,
19905 IX86_BUILTIN_CMPPD256,
19906 IX86_BUILTIN_CMPPS256,
19907 IX86_BUILTIN_CVTDQ2PD256,
19908 IX86_BUILTIN_CVTDQ2PS256,
19909 IX86_BUILTIN_CVTPD2PS256,
19910 IX86_BUILTIN_CVTPS2DQ256,
19911 IX86_BUILTIN_CVTPS2PD256,
19912 IX86_BUILTIN_CVTTPD2DQ256,
19913 IX86_BUILTIN_CVTPD2DQ256,
19914 IX86_BUILTIN_CVTTPS2DQ256,
19915 IX86_BUILTIN_EXTRACTF128PD256,
19916 IX86_BUILTIN_EXTRACTF128PS256,
19917 IX86_BUILTIN_EXTRACTF128SI256,
19918 IX86_BUILTIN_VZEROALL,
19919 IX86_BUILTIN_VZEROUPPER,
19920 IX86_BUILTIN_VZEROUPPER_REX64,
19921 IX86_BUILTIN_VPERMILVARPD,
19922 IX86_BUILTIN_VPERMILVARPS,
19923 IX86_BUILTIN_VPERMILVARPD256,
19924 IX86_BUILTIN_VPERMILVARPS256,
19925 IX86_BUILTIN_VPERMILPD,
19926 IX86_BUILTIN_VPERMILPS,
19927 IX86_BUILTIN_VPERMILPD256,
19928 IX86_BUILTIN_VPERMILPS256,
19929 IX86_BUILTIN_VPERM2F128PD256,
19930 IX86_BUILTIN_VPERM2F128PS256,
19931 IX86_BUILTIN_VPERM2F128SI256,
19932 IX86_BUILTIN_VBROADCASTSS,
19933 IX86_BUILTIN_VBROADCASTSD256,
19934 IX86_BUILTIN_VBROADCASTSS256,
19935 IX86_BUILTIN_VBROADCASTPD256,
19936 IX86_BUILTIN_VBROADCASTPS256,
19937 IX86_BUILTIN_VINSERTF128PD256,
19938 IX86_BUILTIN_VINSERTF128PS256,
19939 IX86_BUILTIN_VINSERTF128SI256,
19940 IX86_BUILTIN_LOADUPD256,
19941 IX86_BUILTIN_LOADUPS256,
19942 IX86_BUILTIN_STOREUPD256,
19943 IX86_BUILTIN_STOREUPS256,
19944 IX86_BUILTIN_LDDQU256,
19945 IX86_BUILTIN_LOADDQU256,
19946 IX86_BUILTIN_STOREDQU256,
19947 IX86_BUILTIN_MASKLOADPD,
19948 IX86_BUILTIN_MASKLOADPS,
19949 IX86_BUILTIN_MASKSTOREPD,
19950 IX86_BUILTIN_MASKSTOREPS,
19951 IX86_BUILTIN_MASKLOADPD256,
19952 IX86_BUILTIN_MASKLOADPS256,
19953 IX86_BUILTIN_MASKSTOREPD256,
19954 IX86_BUILTIN_MASKSTOREPS256,
19955 IX86_BUILTIN_MOVSHDUP256,
19956 IX86_BUILTIN_MOVSLDUP256,
19957 IX86_BUILTIN_MOVDDUP256,
19959 IX86_BUILTIN_SQRTPD256,
19960 IX86_BUILTIN_SQRTPS256,
19961 IX86_BUILTIN_SQRTPS_NR256,
19962 IX86_BUILTIN_RSQRTPS256,
19963 IX86_BUILTIN_RSQRTPS_NR256,
19965 IX86_BUILTIN_RCPPS256,
19967 IX86_BUILTIN_ROUNDPD256,
19968 IX86_BUILTIN_ROUNDPS256,
19970 IX86_BUILTIN_UNPCKHPD256,
19971 IX86_BUILTIN_UNPCKLPD256,
19972 IX86_BUILTIN_UNPCKHPS256,
19973 IX86_BUILTIN_UNPCKLPS256,
19975 IX86_BUILTIN_SI256_SI,
19976 IX86_BUILTIN_PS256_PS,
19977 IX86_BUILTIN_PD256_PD,
19978 IX86_BUILTIN_SI_SI256,
19979 IX86_BUILTIN_PS_PS256,
19980 IX86_BUILTIN_PD_PD256,
19982 IX86_BUILTIN_VTESTZPD,
19983 IX86_BUILTIN_VTESTCPD,
19984 IX86_BUILTIN_VTESTNZCPD,
19985 IX86_BUILTIN_VTESTZPS,
19986 IX86_BUILTIN_VTESTCPS,
19987 IX86_BUILTIN_VTESTNZCPS,
19988 IX86_BUILTIN_VTESTZPD256,
19989 IX86_BUILTIN_VTESTCPD256,
19990 IX86_BUILTIN_VTESTNZCPD256,
19991 IX86_BUILTIN_VTESTZPS256,
19992 IX86_BUILTIN_VTESTCPS256,
19993 IX86_BUILTIN_VTESTNZCPS256,
19994 IX86_BUILTIN_PTESTZ256,
19995 IX86_BUILTIN_PTESTC256,
19996 IX86_BUILTIN_PTESTNZC256,
19998 IX86_BUILTIN_MOVMSKPD256,
19999 IX86_BUILTIN_MOVMSKPS256,
20001 /* TFmode support builtins. */
20003 IX86_BUILTIN_FABSQ,
20004 IX86_BUILTIN_COPYSIGNQ,
20006 /* SSE5 instructions */
20007 IX86_BUILTIN_FMADDSS,
20008 IX86_BUILTIN_FMADDSD,
20009 IX86_BUILTIN_FMADDPS,
20010 IX86_BUILTIN_FMADDPD,
20011 IX86_BUILTIN_FMSUBSS,
20012 IX86_BUILTIN_FMSUBSD,
20013 IX86_BUILTIN_FMSUBPS,
20014 IX86_BUILTIN_FMSUBPD,
20015 IX86_BUILTIN_FNMADDSS,
20016 IX86_BUILTIN_FNMADDSD,
20017 IX86_BUILTIN_FNMADDPS,
20018 IX86_BUILTIN_FNMADDPD,
20019 IX86_BUILTIN_FNMSUBSS,
20020 IX86_BUILTIN_FNMSUBSD,
20021 IX86_BUILTIN_FNMSUBPS,
20022 IX86_BUILTIN_FNMSUBPD,
20023 IX86_BUILTIN_PCMOV,
20024 IX86_BUILTIN_PCMOV_V2DI,
20025 IX86_BUILTIN_PCMOV_V4SI,
20026 IX86_BUILTIN_PCMOV_V8HI,
20027 IX86_BUILTIN_PCMOV_V16QI,
20028 IX86_BUILTIN_PCMOV_V4SF,
20029 IX86_BUILTIN_PCMOV_V2DF,
20030 IX86_BUILTIN_PPERM,
20031 IX86_BUILTIN_PERMPS,
20032 IX86_BUILTIN_PERMPD,
20033 IX86_BUILTIN_PMACSSWW,
20034 IX86_BUILTIN_PMACSWW,
20035 IX86_BUILTIN_PMACSSWD,
20036 IX86_BUILTIN_PMACSWD,
20037 IX86_BUILTIN_PMACSSDD,
20038 IX86_BUILTIN_PMACSDD,
20039 IX86_BUILTIN_PMACSSDQL,
20040 IX86_BUILTIN_PMACSSDQH,
20041 IX86_BUILTIN_PMACSDQL,
20042 IX86_BUILTIN_PMACSDQH,
20043 IX86_BUILTIN_PMADCSSWD,
20044 IX86_BUILTIN_PMADCSWD,
20045 IX86_BUILTIN_PHADDBW,
20046 IX86_BUILTIN_PHADDBD,
20047 IX86_BUILTIN_PHADDBQ,
20048 IX86_BUILTIN_PHADDWD,
20049 IX86_BUILTIN_PHADDWQ,
20050 IX86_BUILTIN_PHADDDQ,
20051 IX86_BUILTIN_PHADDUBW,
20052 IX86_BUILTIN_PHADDUBD,
20053 IX86_BUILTIN_PHADDUBQ,
20054 IX86_BUILTIN_PHADDUWD,
20055 IX86_BUILTIN_PHADDUWQ,
20056 IX86_BUILTIN_PHADDUDQ,
20057 IX86_BUILTIN_PHSUBBW,
20058 IX86_BUILTIN_PHSUBWD,
20059 IX86_BUILTIN_PHSUBDQ,
20060 IX86_BUILTIN_PROTB,
20061 IX86_BUILTIN_PROTW,
20062 IX86_BUILTIN_PROTD,
20063 IX86_BUILTIN_PROTQ,
20064 IX86_BUILTIN_PROTB_IMM,
20065 IX86_BUILTIN_PROTW_IMM,
20066 IX86_BUILTIN_PROTD_IMM,
20067 IX86_BUILTIN_PROTQ_IMM,
20068 IX86_BUILTIN_PSHLB,
20069 IX86_BUILTIN_PSHLW,
20070 IX86_BUILTIN_PSHLD,
20071 IX86_BUILTIN_PSHLQ,
20072 IX86_BUILTIN_PSHAB,
20073 IX86_BUILTIN_PSHAW,
20074 IX86_BUILTIN_PSHAD,
20075 IX86_BUILTIN_PSHAQ,
20076 IX86_BUILTIN_FRCZSS,
20077 IX86_BUILTIN_FRCZSD,
20078 IX86_BUILTIN_FRCZPS,
20079 IX86_BUILTIN_FRCZPD,
20080 IX86_BUILTIN_CVTPH2PS,
20081 IX86_BUILTIN_CVTPS2PH,
20083 IX86_BUILTIN_COMEQSS,
20084 IX86_BUILTIN_COMNESS,
20085 IX86_BUILTIN_COMLTSS,
20086 IX86_BUILTIN_COMLESS,
20087 IX86_BUILTIN_COMGTSS,
20088 IX86_BUILTIN_COMGESS,
20089 IX86_BUILTIN_COMUEQSS,
20090 IX86_BUILTIN_COMUNESS,
20091 IX86_BUILTIN_COMULTSS,
20092 IX86_BUILTIN_COMULESS,
20093 IX86_BUILTIN_COMUGTSS,
20094 IX86_BUILTIN_COMUGESS,
20095 IX86_BUILTIN_COMORDSS,
20096 IX86_BUILTIN_COMUNORDSS,
20097 IX86_BUILTIN_COMFALSESS,
20098 IX86_BUILTIN_COMTRUESS,
20100 IX86_BUILTIN_COMEQSD,
20101 IX86_BUILTIN_COMNESD,
20102 IX86_BUILTIN_COMLTSD,
20103 IX86_BUILTIN_COMLESD,
20104 IX86_BUILTIN_COMGTSD,
20105 IX86_BUILTIN_COMGESD,
20106 IX86_BUILTIN_COMUEQSD,
20107 IX86_BUILTIN_COMUNESD,
20108 IX86_BUILTIN_COMULTSD,
20109 IX86_BUILTIN_COMULESD,
20110 IX86_BUILTIN_COMUGTSD,
20111 IX86_BUILTIN_COMUGESD,
20112 IX86_BUILTIN_COMORDSD,
20113 IX86_BUILTIN_COMUNORDSD,
20114 IX86_BUILTIN_COMFALSESD,
20115 IX86_BUILTIN_COMTRUESD,
20117 IX86_BUILTIN_COMEQPS,
20118 IX86_BUILTIN_COMNEPS,
20119 IX86_BUILTIN_COMLTPS,
20120 IX86_BUILTIN_COMLEPS,
20121 IX86_BUILTIN_COMGTPS,
20122 IX86_BUILTIN_COMGEPS,
20123 IX86_BUILTIN_COMUEQPS,
20124 IX86_BUILTIN_COMUNEPS,
20125 IX86_BUILTIN_COMULTPS,
20126 IX86_BUILTIN_COMULEPS,
20127 IX86_BUILTIN_COMUGTPS,
20128 IX86_BUILTIN_COMUGEPS,
20129 IX86_BUILTIN_COMORDPS,
20130 IX86_BUILTIN_COMUNORDPS,
20131 IX86_BUILTIN_COMFALSEPS,
20132 IX86_BUILTIN_COMTRUEPS,
20134 IX86_BUILTIN_COMEQPD,
20135 IX86_BUILTIN_COMNEPD,
20136 IX86_BUILTIN_COMLTPD,
20137 IX86_BUILTIN_COMLEPD,
20138 IX86_BUILTIN_COMGTPD,
20139 IX86_BUILTIN_COMGEPD,
20140 IX86_BUILTIN_COMUEQPD,
20141 IX86_BUILTIN_COMUNEPD,
20142 IX86_BUILTIN_COMULTPD,
20143 IX86_BUILTIN_COMULEPD,
20144 IX86_BUILTIN_COMUGTPD,
20145 IX86_BUILTIN_COMUGEPD,
20146 IX86_BUILTIN_COMORDPD,
20147 IX86_BUILTIN_COMUNORDPD,
20148 IX86_BUILTIN_COMFALSEPD,
20149 IX86_BUILTIN_COMTRUEPD,
20151 IX86_BUILTIN_PCOMEQUB,
20152 IX86_BUILTIN_PCOMNEUB,
20153 IX86_BUILTIN_PCOMLTUB,
20154 IX86_BUILTIN_PCOMLEUB,
20155 IX86_BUILTIN_PCOMGTUB,
20156 IX86_BUILTIN_PCOMGEUB,
20157 IX86_BUILTIN_PCOMFALSEUB,
20158 IX86_BUILTIN_PCOMTRUEUB,
20159 IX86_BUILTIN_PCOMEQUW,
20160 IX86_BUILTIN_PCOMNEUW,
20161 IX86_BUILTIN_PCOMLTUW,
20162 IX86_BUILTIN_PCOMLEUW,
20163 IX86_BUILTIN_PCOMGTUW,
20164 IX86_BUILTIN_PCOMGEUW,
20165 IX86_BUILTIN_PCOMFALSEUW,
20166 IX86_BUILTIN_PCOMTRUEUW,
20167 IX86_BUILTIN_PCOMEQUD,
20168 IX86_BUILTIN_PCOMNEUD,
20169 IX86_BUILTIN_PCOMLTUD,
20170 IX86_BUILTIN_PCOMLEUD,
20171 IX86_BUILTIN_PCOMGTUD,
20172 IX86_BUILTIN_PCOMGEUD,
20173 IX86_BUILTIN_PCOMFALSEUD,
20174 IX86_BUILTIN_PCOMTRUEUD,
20175 IX86_BUILTIN_PCOMEQUQ,
20176 IX86_BUILTIN_PCOMNEUQ,
20177 IX86_BUILTIN_PCOMLTUQ,
20178 IX86_BUILTIN_PCOMLEUQ,
20179 IX86_BUILTIN_PCOMGTUQ,
20180 IX86_BUILTIN_PCOMGEUQ,
20181 IX86_BUILTIN_PCOMFALSEUQ,
20182 IX86_BUILTIN_PCOMTRUEUQ,
20184 IX86_BUILTIN_PCOMEQB,
20185 IX86_BUILTIN_PCOMNEB,
20186 IX86_BUILTIN_PCOMLTB,
20187 IX86_BUILTIN_PCOMLEB,
20188 IX86_BUILTIN_PCOMGTB,
20189 IX86_BUILTIN_PCOMGEB,
20190 IX86_BUILTIN_PCOMFALSEB,
20191 IX86_BUILTIN_PCOMTRUEB,
20192 IX86_BUILTIN_PCOMEQW,
20193 IX86_BUILTIN_PCOMNEW,
20194 IX86_BUILTIN_PCOMLTW,
20195 IX86_BUILTIN_PCOMLEW,
20196 IX86_BUILTIN_PCOMGTW,
20197 IX86_BUILTIN_PCOMGEW,
20198 IX86_BUILTIN_PCOMFALSEW,
20199 IX86_BUILTIN_PCOMTRUEW,
20200 IX86_BUILTIN_PCOMEQD,
20201 IX86_BUILTIN_PCOMNED,
20202 IX86_BUILTIN_PCOMLTD,
20203 IX86_BUILTIN_PCOMLED,
20204 IX86_BUILTIN_PCOMGTD,
20205 IX86_BUILTIN_PCOMGED,
20206 IX86_BUILTIN_PCOMFALSED,
20207 IX86_BUILTIN_PCOMTRUED,
20208 IX86_BUILTIN_PCOMEQQ,
20209 IX86_BUILTIN_PCOMNEQ,
20210 IX86_BUILTIN_PCOMLTQ,
20211 IX86_BUILTIN_PCOMLEQ,
20212 IX86_BUILTIN_PCOMGTQ,
20213 IX86_BUILTIN_PCOMGEQ,
20214 IX86_BUILTIN_PCOMFALSEQ,
20215 IX86_BUILTIN_PCOMTRUEQ,
20220 /* Table for the ix86 builtin decls. */
20221 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20223 /* Table of all of the builtin functions that are possible with different ISA's
20224 but are waiting to be built until a function is declared to use that
20226 struct builtin_isa GTY(())
20228 tree type; /* builtin type to use in the declaration */
20229 const char *name; /* function name */
20230 int isa; /* isa_flags this builtin is defined for */
20231 bool const_p; /* true if the declaration is constant */
20234 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20237 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20238 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20239 * function decl in the ix86_builtins array. Returns the function decl or
20240 * NULL_TREE, if the builtin was not added.
20242 * If the front end has a special hook for builtin functions, delay adding
20243 * builtin functions that aren't in the current ISA until the ISA is changed
20244 * with function specific optimization. Doing so, can save about 300K for the
20245 * default compiler. When the builtin is expanded, check at that time whether
20248 * If the front end doesn't have a special hook, record all builtins, even if
20249 * it isn't an instruction set in the current ISA in case the user uses
20250 * function specific options for a different ISA, so that we don't get scope
20251 * errors if a builtin is added in the middle of a function scope. */
20254 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20256 tree decl = NULL_TREE;
20258 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20260 ix86_builtins_isa[(int) code].isa = mask;
20262 if ((mask & ix86_isa_flags) != 0
20263 || (lang_hooks.builtin_function
20264 == lang_hooks.builtin_function_ext_scope))
20267 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20269 ix86_builtins[(int) code] = decl;
20270 ix86_builtins_isa[(int) code].type = NULL_TREE;
20274 ix86_builtins[(int) code] = NULL_TREE;
20275 ix86_builtins_isa[(int) code].const_p = false;
20276 ix86_builtins_isa[(int) code].type = type;
20277 ix86_builtins_isa[(int) code].name = name;
20284 /* Like def_builtin, but also marks the function decl "const". */
20287 def_builtin_const (int mask, const char *name, tree type,
20288 enum ix86_builtins code)
20290 tree decl = def_builtin (mask, name, type, code);
20292 TREE_READONLY (decl) = 1;
20294 ix86_builtins_isa[(int) code].const_p = true;
20299 /* Add any new builtin functions for a given ISA that may not have been
20300 declared. This saves a bit of space compared to adding all of the
20301 declarations to the tree, even if we didn't use them. */
20304 ix86_add_new_builtins (int isa)
20309 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20311 if ((ix86_builtins_isa[i].isa & isa) != 0
20312 && ix86_builtins_isa[i].type != NULL_TREE)
20314 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20315 ix86_builtins_isa[i].type,
20316 i, BUILT_IN_MD, NULL,
20319 ix86_builtins[i] = decl;
20320 ix86_builtins_isa[i].type = NULL_TREE;
20321 if (ix86_builtins_isa[i].const_p)
20322 TREE_READONLY (decl) = 1;
20327 /* Bits for builtin_description.flag. */
20329 /* Set when we don't support the comparison natively, and should
20330 swap_comparison in order to support it. */
20331 #define BUILTIN_DESC_SWAP_OPERANDS 1
20333 struct builtin_description
20335 const unsigned int mask;
20336 const enum insn_code icode;
20337 const char *const name;
20338 const enum ix86_builtins code;
20339 const enum rtx_code comparison;
20343 static const struct builtin_description bdesc_comi[] =
20345 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20346 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20347 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20348 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20349 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20350 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20352 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20353 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20354 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20355 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20356 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20361 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20362 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20366 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20371 static const struct builtin_description bdesc_pcmpestr[] =
20374 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20375 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20376 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20377 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20378 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20379 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20380 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20383 static const struct builtin_description bdesc_pcmpistr[] =
20386 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20387 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20388 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20389 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20390 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20391 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20392 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20395 /* Special builtin types */
20396 enum ix86_special_builtin_type
20398 SPECIAL_FTYPE_UNKNOWN,
20400 V32QI_FTYPE_PCCHAR,
20401 V16QI_FTYPE_PCCHAR,
20403 V8SF_FTYPE_PCFLOAT,
20405 V4DF_FTYPE_PCDOUBLE,
20406 V4SF_FTYPE_PCFLOAT,
20407 V2DF_FTYPE_PCDOUBLE,
20408 V8SF_FTYPE_PCV8SF_V8SF,
20409 V4DF_FTYPE_PCV4DF_V4DF,
20410 V4SF_FTYPE_V4SF_PCV2SF,
20411 V4SF_FTYPE_PCV4SF_V4SF,
20412 V2DF_FTYPE_V2DF_PCDOUBLE,
20413 V2DF_FTYPE_PCV2DF_V2DF,
20415 VOID_FTYPE_PV2SF_V4SF,
20416 VOID_FTYPE_PV2DI_V2DI,
20417 VOID_FTYPE_PCHAR_V32QI,
20418 VOID_FTYPE_PCHAR_V16QI,
20419 VOID_FTYPE_PFLOAT_V8SF,
20420 VOID_FTYPE_PFLOAT_V4SF,
20421 VOID_FTYPE_PDOUBLE_V4DF,
20422 VOID_FTYPE_PDOUBLE_V2DF,
20424 VOID_FTYPE_PINT_INT,
20425 VOID_FTYPE_PV8SF_V8SF_V8SF,
20426 VOID_FTYPE_PV4DF_V4DF_V4DF,
20427 VOID_FTYPE_PV4SF_V4SF_V4SF,
20428 VOID_FTYPE_PV2DF_V2DF_V2DF
20431 /* Builtin types */
20432 enum ix86_builtin_type
20435 FLOAT128_FTYPE_FLOAT128,
20437 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20438 INT_FTYPE_V8SF_V8SF_PTEST,
20439 INT_FTYPE_V4DI_V4DI_PTEST,
20440 INT_FTYPE_V4DF_V4DF_PTEST,
20441 INT_FTYPE_V4SF_V4SF_PTEST,
20442 INT_FTYPE_V2DI_V2DI_PTEST,
20443 INT_FTYPE_V2DF_V2DF_PTEST,
20475 V4SF_FTYPE_V4SF_VEC_MERGE,
20484 V2DF_FTYPE_V2DF_VEC_MERGE,
20495 V16QI_FTYPE_V16QI_V16QI,
20496 V16QI_FTYPE_V8HI_V8HI,
20497 V8QI_FTYPE_V8QI_V8QI,
20498 V8QI_FTYPE_V4HI_V4HI,
20499 V8HI_FTYPE_V8HI_V8HI,
20500 V8HI_FTYPE_V8HI_V8HI_COUNT,
20501 V8HI_FTYPE_V16QI_V16QI,
20502 V8HI_FTYPE_V4SI_V4SI,
20503 V8HI_FTYPE_V8HI_SI_COUNT,
20504 V8SF_FTYPE_V8SF_V8SF,
20505 V8SF_FTYPE_V8SF_V8SI,
20506 V4SI_FTYPE_V4SI_V4SI,
20507 V4SI_FTYPE_V4SI_V4SI_COUNT,
20508 V4SI_FTYPE_V8HI_V8HI,
20509 V4SI_FTYPE_V4SF_V4SF,
20510 V4SI_FTYPE_V2DF_V2DF,
20511 V4SI_FTYPE_V4SI_SI_COUNT,
20512 V4HI_FTYPE_V4HI_V4HI,
20513 V4HI_FTYPE_V4HI_V4HI_COUNT,
20514 V4HI_FTYPE_V8QI_V8QI,
20515 V4HI_FTYPE_V2SI_V2SI,
20516 V4HI_FTYPE_V4HI_SI_COUNT,
20517 V4DF_FTYPE_V4DF_V4DF,
20518 V4DF_FTYPE_V4DF_V4DI,
20519 V4SF_FTYPE_V4SF_V4SF,
20520 V4SF_FTYPE_V4SF_V4SF_SWAP,
20521 V4SF_FTYPE_V4SF_V4SI,
20522 V4SF_FTYPE_V4SF_V2SI,
20523 V4SF_FTYPE_V4SF_V2DF,
20524 V4SF_FTYPE_V4SF_DI,
20525 V4SF_FTYPE_V4SF_SI,
20526 V2DI_FTYPE_V2DI_V2DI,
20527 V2DI_FTYPE_V2DI_V2DI_COUNT,
20528 V2DI_FTYPE_V16QI_V16QI,
20529 V2DI_FTYPE_V4SI_V4SI,
20530 V2DI_FTYPE_V2DI_V16QI,
20531 V2DI_FTYPE_V2DF_V2DF,
20532 V2DI_FTYPE_V2DI_SI_COUNT,
20533 V2SI_FTYPE_V2SI_V2SI,
20534 V2SI_FTYPE_V2SI_V2SI_COUNT,
20535 V2SI_FTYPE_V4HI_V4HI,
20536 V2SI_FTYPE_V2SF_V2SF,
20537 V2SI_FTYPE_V2SI_SI_COUNT,
20538 V2DF_FTYPE_V2DF_V2DF,
20539 V2DF_FTYPE_V2DF_V2DF_SWAP,
20540 V2DF_FTYPE_V2DF_V4SF,
20541 V2DF_FTYPE_V2DF_V2DI,
20542 V2DF_FTYPE_V2DF_DI,
20543 V2DF_FTYPE_V2DF_SI,
20544 V2SF_FTYPE_V2SF_V2SF,
20545 V1DI_FTYPE_V1DI_V1DI,
20546 V1DI_FTYPE_V1DI_V1DI_COUNT,
20547 V1DI_FTYPE_V8QI_V8QI,
20548 V1DI_FTYPE_V2SI_V2SI,
20549 V1DI_FTYPE_V1DI_SI_COUNT,
20550 UINT64_FTYPE_UINT64_UINT64,
20551 UINT_FTYPE_UINT_UINT,
20552 UINT_FTYPE_UINT_USHORT,
20553 UINT_FTYPE_UINT_UCHAR,
20554 V8HI_FTYPE_V8HI_INT,
20555 V4SI_FTYPE_V4SI_INT,
20556 V4HI_FTYPE_V4HI_INT,
20557 V8SF_FTYPE_V8SF_INT,
20558 V4SI_FTYPE_V8SI_INT,
20559 V4SF_FTYPE_V8SF_INT,
20560 V2DF_FTYPE_V4DF_INT,
20561 V4DF_FTYPE_V4DF_INT,
20562 V4SF_FTYPE_V4SF_INT,
20563 V2DI_FTYPE_V2DI_INT,
20564 V2DI2TI_FTYPE_V2DI_INT,
20565 V2DF_FTYPE_V2DF_INT,
20566 V16QI_FTYPE_V16QI_V16QI_V16QI,
20567 V8SF_FTYPE_V8SF_V8SF_V8SF,
20568 V4DF_FTYPE_V4DF_V4DF_V4DF,
20569 V4SF_FTYPE_V4SF_V4SF_V4SF,
20570 V2DF_FTYPE_V2DF_V2DF_V2DF,
20571 V16QI_FTYPE_V16QI_V16QI_INT,
20572 V8SI_FTYPE_V8SI_V8SI_INT,
20573 V8SI_FTYPE_V8SI_V4SI_INT,
20574 V8HI_FTYPE_V8HI_V8HI_INT,
20575 V8SF_FTYPE_V8SF_V8SF_INT,
20576 V8SF_FTYPE_V8SF_V4SF_INT,
20577 V4SI_FTYPE_V4SI_V4SI_INT,
20578 V4DF_FTYPE_V4DF_V4DF_INT,
20579 V4DF_FTYPE_V4DF_V2DF_INT,
20580 V4SF_FTYPE_V4SF_V4SF_INT,
20581 V2DI_FTYPE_V2DI_V2DI_INT,
20582 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20583 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20584 V2DF_FTYPE_V2DF_V2DF_INT,
20585 V2DI_FTYPE_V2DI_UINT_UINT,
20586 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20589 /* Special builtins with variable number of arguments. */
20590 static const struct builtin_description bdesc_special_args[] =
20593 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20596 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20599 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20600 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20601 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20603 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20604 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20605 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20606 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20608 /* SSE or 3DNow!A */
20609 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20610 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20618 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20619 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20620 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20621 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20623 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20627 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20630 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20633 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20634 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20639 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20665 /* Builtins with variable number of arguments. */
20666 static const struct builtin_description bdesc_args[] =
20669 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20670 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20671 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20672 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20673 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20674 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20676 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20677 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20678 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20679 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20680 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20681 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20682 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20683 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20685 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20686 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20688 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20689 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20690 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20691 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20693 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20694 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20695 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20696 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20697 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20698 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20700 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20701 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20702 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20703 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20704 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20705 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20707 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20708 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20709 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20711 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20713 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20714 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20715 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20716 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20717 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20718 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20720 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20721 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20722 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20723 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20724 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20725 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20727 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20728 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20729 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20730 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20733 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20734 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20735 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20736 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20738 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20739 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20740 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20741 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20742 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20743 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20744 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20745 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20746 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20747 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20748 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20749 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20750 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20751 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20752 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20755 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20756 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20757 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20758 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20759 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20760 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20765 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20767 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20771 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20774 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20776 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20778 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20779 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20780 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20782 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20783 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20784 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20785 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20787 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20788 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20789 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20790 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20791 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20792 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20793 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20794 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20795 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20796 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20797 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
20798 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20799 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20800 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20801 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20802 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20803 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20805 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20806 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20807 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20808 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20810 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20811 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20812 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20813 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20815 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20816 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20817 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20818 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20820 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20821 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20822 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20823 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20824 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20826 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
20827 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
20828 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
20830 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
20832 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20833 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20834 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20836 /* SSE MMX or 3Dnow!A */
20837 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20838 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20839 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20841 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20842 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20843 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20844 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20846 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
20847 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
20849 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
20852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
20855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
20856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
20857 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
20858 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
20860 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20862 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
20863 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20864 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
20868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20870 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20871 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
20875 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20877 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20878 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20879 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20880 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20881 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
20891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20896 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20898 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20899 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20902 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20903 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20908 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20912 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20913 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20914 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20915 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20921 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
20923 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20924 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20925 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20926 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20927 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20928 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20929 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20930 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20932 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20934 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20935 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20936 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20937 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20938 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20941 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20942 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
20944 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20945 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20946 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20947 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20949 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20950 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20952 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20953 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20954 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20956 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20957 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20959 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20960 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20961 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20962 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20973 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20974 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
20975 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20977 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
20980 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
20981 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
20983 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
20985 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
20986 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
20987 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
20988 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
20990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20991 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20992 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20993 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
20994 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20995 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20996 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
20998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20999 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21000 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21001 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21002 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21003 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21004 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21006 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21007 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21008 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21009 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21012 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21013 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21015 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21017 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21018 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21023 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21024 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21027 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21028 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21030 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21031 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21032 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21033 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21034 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21035 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21038 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21039 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21040 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21041 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21042 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21043 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21045 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21046 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21047 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21048 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21049 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21050 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21051 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21052 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21053 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21054 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21055 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21056 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21057 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21058 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21059 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21060 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21061 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21062 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21063 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21064 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21065 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21066 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21067 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21068 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21071 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21072 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21075 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21076 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21077 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21078 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21079 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21080 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21081 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21082 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21083 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21084 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21086 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21087 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21088 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21089 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21090 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21091 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21092 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21093 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21094 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21095 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21096 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21097 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21098 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21100 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21101 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21102 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21103 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21104 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21105 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21106 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21107 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21108 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21109 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21110 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21111 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21113 /* SSE4.1 and SSE5 */
21114 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21115 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21116 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21117 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21119 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21120 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21121 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21124 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21125 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21126 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21127 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21128 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21131 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21132 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21133 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21134 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21137 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21138 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21140 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21141 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21142 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21143 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21146 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21149 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21150 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21151 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21152 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21153 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21154 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21155 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21157 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21160 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21163 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21164 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21165 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21166 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21167 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21168 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21169 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21170 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21171 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21172 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21173 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21174 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21176 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21177 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21179 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21182 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21183 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21185 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21187 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21189 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21190 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21192 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21194 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21195 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21197 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21198 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21199 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21200 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21202 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21204 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21205 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21207 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21210 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21211 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21212 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21213 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21214 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21216 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21217 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21218 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21220 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21221 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21222 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21223 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21224 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21226 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21228 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21229 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21231 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21232 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21233 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21234 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21236 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21237 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21238 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21239 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21240 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21241 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21243 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21244 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21245 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21246 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21247 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21248 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21249 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21250 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21251 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21252 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21253 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21254 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21255 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21256 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21257 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21259 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21260 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21264 enum multi_arg_type {
21274 MULTI_ARG_3_PERMPS,
21275 MULTI_ARG_3_PERMPD,
21282 MULTI_ARG_2_DI_IMM,
21283 MULTI_ARG_2_SI_IMM,
21284 MULTI_ARG_2_HI_IMM,
21285 MULTI_ARG_2_QI_IMM,
21286 MULTI_ARG_2_SF_CMP,
21287 MULTI_ARG_2_DF_CMP,
21288 MULTI_ARG_2_DI_CMP,
21289 MULTI_ARG_2_SI_CMP,
21290 MULTI_ARG_2_HI_CMP,
21291 MULTI_ARG_2_QI_CMP,
21314 static const struct builtin_description bdesc_multi_arg[] =
21316 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21317 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21318 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21319 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21320 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21321 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21322 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21323 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21324 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21325 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21326 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21327 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21328 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21329 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21330 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21331 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21332 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21333 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21334 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21335 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21336 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21337 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21338 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21339 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21340 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21341 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21342 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21343 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21344 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21345 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21346 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21347 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21348 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21349 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21350 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21351 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21352 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21353 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21354 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21355 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21356 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21357 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21358 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21359 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21360 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21361 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21362 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21363 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21364 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21365 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21366 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21367 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21368 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21369 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21370 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21371 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21372 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21373 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21374 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21375 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21376 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21377 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21378 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21379 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21380 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21381 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21382 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21383 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21384 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21385 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21386 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21387 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21388 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21389 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21390 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21392 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21393 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21394 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21395 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21396 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21397 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21398 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21399 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21400 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21401 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21402 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21403 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21404 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21405 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21406 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21407 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21409 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21410 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21411 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21412 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21413 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21414 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21415 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21416 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21417 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21418 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21419 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21420 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21421 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21422 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21423 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21424 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21426 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21427 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21428 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21429 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21430 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21431 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21432 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21433 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21434 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21435 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21436 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21437 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21438 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21439 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21440 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21441 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21443 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21444 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21445 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21446 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21447 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21448 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21449 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21450 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21451 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21452 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21453 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21454 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21455 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21456 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21457 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21458 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21460 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21461 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21462 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21463 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21464 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21465 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21466 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21468 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21469 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21470 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21471 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21472 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21473 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21474 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21476 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21477 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21478 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21479 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21480 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21481 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21482 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21484 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21485 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21486 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21487 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21488 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21489 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21490 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21492 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21493 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21494 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21495 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21496 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21497 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21498 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21500 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21501 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21502 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21503 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21504 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21505 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21506 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21508 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21512 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21516 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21517 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21520 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21524 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21552 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21553 in the current target ISA to allow the user to compile particular modules
21554 with different target specific options that differ from the command line
21557 ix86_init_mmx_sse_builtins (void)
21559 const struct builtin_description * d;
21562 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21563 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21564 tree V1DI_type_node
21565 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21566 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21567 tree V2DI_type_node
21568 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21569 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21570 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21571 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21572 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21573 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21574 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21576 tree pchar_type_node = build_pointer_type (char_type_node);
21577 tree pcchar_type_node
21578 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21579 tree pfloat_type_node = build_pointer_type (float_type_node);
21580 tree pcfloat_type_node
21581 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21582 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21583 tree pcv2sf_type_node
21584 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21585 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21586 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21589 tree int_ftype_v4sf_v4sf
21590 = build_function_type_list (integer_type_node,
21591 V4SF_type_node, V4SF_type_node, NULL_TREE);
21592 tree v4si_ftype_v4sf_v4sf
21593 = build_function_type_list (V4SI_type_node,
21594 V4SF_type_node, V4SF_type_node, NULL_TREE);
21595 /* MMX/SSE/integer conversions. */
21596 tree int_ftype_v4sf
21597 = build_function_type_list (integer_type_node,
21598 V4SF_type_node, NULL_TREE);
21599 tree int64_ftype_v4sf
21600 = build_function_type_list (long_long_integer_type_node,
21601 V4SF_type_node, NULL_TREE);
21602 tree int_ftype_v8qi
21603 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21604 tree v4sf_ftype_v4sf_int
21605 = build_function_type_list (V4SF_type_node,
21606 V4SF_type_node, integer_type_node, NULL_TREE);
21607 tree v4sf_ftype_v4sf_int64
21608 = build_function_type_list (V4SF_type_node,
21609 V4SF_type_node, long_long_integer_type_node,
21611 tree v4sf_ftype_v4sf_v2si
21612 = build_function_type_list (V4SF_type_node,
21613 V4SF_type_node, V2SI_type_node, NULL_TREE);
21615 /* Miscellaneous. */
21616 tree v8qi_ftype_v4hi_v4hi
21617 = build_function_type_list (V8QI_type_node,
21618 V4HI_type_node, V4HI_type_node, NULL_TREE);
21619 tree v4hi_ftype_v2si_v2si
21620 = build_function_type_list (V4HI_type_node,
21621 V2SI_type_node, V2SI_type_node, NULL_TREE);
21622 tree v4sf_ftype_v4sf_v4sf_int
21623 = build_function_type_list (V4SF_type_node,
21624 V4SF_type_node, V4SF_type_node,
21625 integer_type_node, NULL_TREE);
21626 tree v2si_ftype_v4hi_v4hi
21627 = build_function_type_list (V2SI_type_node,
21628 V4HI_type_node, V4HI_type_node, NULL_TREE);
21629 tree v4hi_ftype_v4hi_int
21630 = build_function_type_list (V4HI_type_node,
21631 V4HI_type_node, integer_type_node, NULL_TREE);
21632 tree v2si_ftype_v2si_int
21633 = build_function_type_list (V2SI_type_node,
21634 V2SI_type_node, integer_type_node, NULL_TREE);
21635 tree v1di_ftype_v1di_int
21636 = build_function_type_list (V1DI_type_node,
21637 V1DI_type_node, integer_type_node, NULL_TREE);
21639 tree void_ftype_void
21640 = build_function_type (void_type_node, void_list_node);
21641 tree void_ftype_unsigned
21642 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21643 tree void_ftype_unsigned_unsigned
21644 = build_function_type_list (void_type_node, unsigned_type_node,
21645 unsigned_type_node, NULL_TREE);
21646 tree void_ftype_pcvoid_unsigned_unsigned
21647 = build_function_type_list (void_type_node, const_ptr_type_node,
21648 unsigned_type_node, unsigned_type_node,
21650 tree unsigned_ftype_void
21651 = build_function_type (unsigned_type_node, void_list_node);
21652 tree v2si_ftype_v4sf
21653 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21654 /* Loads/stores. */
21655 tree void_ftype_v8qi_v8qi_pchar
21656 = build_function_type_list (void_type_node,
21657 V8QI_type_node, V8QI_type_node,
21658 pchar_type_node, NULL_TREE);
21659 tree v4sf_ftype_pcfloat
21660 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21661 tree v4sf_ftype_v4sf_pcv2sf
21662 = build_function_type_list (V4SF_type_node,
21663 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21664 tree void_ftype_pv2sf_v4sf
21665 = build_function_type_list (void_type_node,
21666 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21667 tree void_ftype_pfloat_v4sf
21668 = build_function_type_list (void_type_node,
21669 pfloat_type_node, V4SF_type_node, NULL_TREE);
21670 tree void_ftype_pdi_di
21671 = build_function_type_list (void_type_node,
21672 pdi_type_node, long_long_unsigned_type_node,
21674 tree void_ftype_pv2di_v2di
21675 = build_function_type_list (void_type_node,
21676 pv2di_type_node, V2DI_type_node, NULL_TREE);
21677 /* Normal vector unops. */
21678 tree v4sf_ftype_v4sf
21679 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21680 tree v16qi_ftype_v16qi
21681 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21682 tree v8hi_ftype_v8hi
21683 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21684 tree v4si_ftype_v4si
21685 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21686 tree v8qi_ftype_v8qi
21687 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21688 tree v4hi_ftype_v4hi
21689 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21691 /* Normal vector binops. */
21692 tree v4sf_ftype_v4sf_v4sf
21693 = build_function_type_list (V4SF_type_node,
21694 V4SF_type_node, V4SF_type_node, NULL_TREE);
21695 tree v8qi_ftype_v8qi_v8qi
21696 = build_function_type_list (V8QI_type_node,
21697 V8QI_type_node, V8QI_type_node, NULL_TREE);
21698 tree v4hi_ftype_v4hi_v4hi
21699 = build_function_type_list (V4HI_type_node,
21700 V4HI_type_node, V4HI_type_node, NULL_TREE);
21701 tree v2si_ftype_v2si_v2si
21702 = build_function_type_list (V2SI_type_node,
21703 V2SI_type_node, V2SI_type_node, NULL_TREE);
21704 tree v1di_ftype_v1di_v1di
21705 = build_function_type_list (V1DI_type_node,
21706 V1DI_type_node, V1DI_type_node, NULL_TREE);
21707 tree v1di_ftype_v1di_v1di_int
21708 = build_function_type_list (V1DI_type_node,
21709 V1DI_type_node, V1DI_type_node,
21710 integer_type_node, NULL_TREE);
21711 tree v2si_ftype_v2sf
21712 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21713 tree v2sf_ftype_v2si
21714 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21715 tree v2si_ftype_v2si
21716 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21717 tree v2sf_ftype_v2sf
21718 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21719 tree v2sf_ftype_v2sf_v2sf
21720 = build_function_type_list (V2SF_type_node,
21721 V2SF_type_node, V2SF_type_node, NULL_TREE);
21722 tree v2si_ftype_v2sf_v2sf
21723 = build_function_type_list (V2SI_type_node,
21724 V2SF_type_node, V2SF_type_node, NULL_TREE);
21725 tree pint_type_node = build_pointer_type (integer_type_node);
21726 tree pdouble_type_node = build_pointer_type (double_type_node);
21727 tree pcdouble_type_node = build_pointer_type (
21728 build_type_variant (double_type_node, 1, 0));
21729 tree int_ftype_v2df_v2df
21730 = build_function_type_list (integer_type_node,
21731 V2DF_type_node, V2DF_type_node, NULL_TREE);
21733 tree void_ftype_pcvoid
21734 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21735 tree v4sf_ftype_v4si
21736 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21737 tree v4si_ftype_v4sf
21738 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21739 tree v2df_ftype_v4si
21740 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21741 tree v4si_ftype_v2df
21742 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21743 tree v4si_ftype_v2df_v2df
21744 = build_function_type_list (V4SI_type_node,
21745 V2DF_type_node, V2DF_type_node, NULL_TREE);
21746 tree v2si_ftype_v2df
21747 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21748 tree v4sf_ftype_v2df
21749 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21750 tree v2df_ftype_v2si
21751 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21752 tree v2df_ftype_v4sf
21753 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21754 tree int_ftype_v2df
21755 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21756 tree int64_ftype_v2df
21757 = build_function_type_list (long_long_integer_type_node,
21758 V2DF_type_node, NULL_TREE);
21759 tree v2df_ftype_v2df_int
21760 = build_function_type_list (V2DF_type_node,
21761 V2DF_type_node, integer_type_node, NULL_TREE);
21762 tree v2df_ftype_v2df_int64
21763 = build_function_type_list (V2DF_type_node,
21764 V2DF_type_node, long_long_integer_type_node,
21766 tree v4sf_ftype_v4sf_v2df
21767 = build_function_type_list (V4SF_type_node,
21768 V4SF_type_node, V2DF_type_node, NULL_TREE);
21769 tree v2df_ftype_v2df_v4sf
21770 = build_function_type_list (V2DF_type_node,
21771 V2DF_type_node, V4SF_type_node, NULL_TREE);
21772 tree v2df_ftype_v2df_v2df_int
21773 = build_function_type_list (V2DF_type_node,
21774 V2DF_type_node, V2DF_type_node,
21777 tree v2df_ftype_v2df_pcdouble
21778 = build_function_type_list (V2DF_type_node,
21779 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21780 tree void_ftype_pdouble_v2df
21781 = build_function_type_list (void_type_node,
21782 pdouble_type_node, V2DF_type_node, NULL_TREE);
21783 tree void_ftype_pint_int
21784 = build_function_type_list (void_type_node,
21785 pint_type_node, integer_type_node, NULL_TREE);
21786 tree void_ftype_v16qi_v16qi_pchar
21787 = build_function_type_list (void_type_node,
21788 V16QI_type_node, V16QI_type_node,
21789 pchar_type_node, NULL_TREE);
21790 tree v2df_ftype_pcdouble
21791 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
21792 tree v2df_ftype_v2df_v2df
21793 = build_function_type_list (V2DF_type_node,
21794 V2DF_type_node, V2DF_type_node, NULL_TREE);
21795 tree v16qi_ftype_v16qi_v16qi
21796 = build_function_type_list (V16QI_type_node,
21797 V16QI_type_node, V16QI_type_node, NULL_TREE);
21798 tree v8hi_ftype_v8hi_v8hi
21799 = build_function_type_list (V8HI_type_node,
21800 V8HI_type_node, V8HI_type_node, NULL_TREE);
21801 tree v4si_ftype_v4si_v4si
21802 = build_function_type_list (V4SI_type_node,
21803 V4SI_type_node, V4SI_type_node, NULL_TREE);
21804 tree v2di_ftype_v2di_v2di
21805 = build_function_type_list (V2DI_type_node,
21806 V2DI_type_node, V2DI_type_node, NULL_TREE);
21807 tree v2di_ftype_v2df_v2df
21808 = build_function_type_list (V2DI_type_node,
21809 V2DF_type_node, V2DF_type_node, NULL_TREE);
21810 tree v2df_ftype_v2df
21811 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
21812 tree v2di_ftype_v2di_int
21813 = build_function_type_list (V2DI_type_node,
21814 V2DI_type_node, integer_type_node, NULL_TREE);
21815 tree v2di_ftype_v2di_v2di_int
21816 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21817 V2DI_type_node, integer_type_node, NULL_TREE);
21818 tree v4si_ftype_v4si_int
21819 = build_function_type_list (V4SI_type_node,
21820 V4SI_type_node, integer_type_node, NULL_TREE);
21821 tree v8hi_ftype_v8hi_int
21822 = build_function_type_list (V8HI_type_node,
21823 V8HI_type_node, integer_type_node, NULL_TREE);
21824 tree v4si_ftype_v8hi_v8hi
21825 = build_function_type_list (V4SI_type_node,
21826 V8HI_type_node, V8HI_type_node, NULL_TREE);
21827 tree v1di_ftype_v8qi_v8qi
21828 = build_function_type_list (V1DI_type_node,
21829 V8QI_type_node, V8QI_type_node, NULL_TREE);
21830 tree v1di_ftype_v2si_v2si
21831 = build_function_type_list (V1DI_type_node,
21832 V2SI_type_node, V2SI_type_node, NULL_TREE);
21833 tree v2di_ftype_v16qi_v16qi
21834 = build_function_type_list (V2DI_type_node,
21835 V16QI_type_node, V16QI_type_node, NULL_TREE);
21836 tree v2di_ftype_v4si_v4si
21837 = build_function_type_list (V2DI_type_node,
21838 V4SI_type_node, V4SI_type_node, NULL_TREE);
21839 tree int_ftype_v16qi
21840 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
21841 tree v16qi_ftype_pcchar
21842 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
21843 tree void_ftype_pchar_v16qi
21844 = build_function_type_list (void_type_node,
21845 pchar_type_node, V16QI_type_node, NULL_TREE);
21847 tree v2di_ftype_v2di_unsigned_unsigned
21848 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21849 unsigned_type_node, unsigned_type_node,
21851 tree v2di_ftype_v2di_v2di_unsigned_unsigned
21852 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
21853 unsigned_type_node, unsigned_type_node,
21855 tree v2di_ftype_v2di_v16qi
21856 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
21858 tree v2df_ftype_v2df_v2df_v2df
21859 = build_function_type_list (V2DF_type_node,
21860 V2DF_type_node, V2DF_type_node,
21861 V2DF_type_node, NULL_TREE);
21862 tree v4sf_ftype_v4sf_v4sf_v4sf
21863 = build_function_type_list (V4SF_type_node,
21864 V4SF_type_node, V4SF_type_node,
21865 V4SF_type_node, NULL_TREE);
21866 tree v8hi_ftype_v16qi
21867 = build_function_type_list (V8HI_type_node, V16QI_type_node,
21869 tree v4si_ftype_v16qi
21870 = build_function_type_list (V4SI_type_node, V16QI_type_node,
21872 tree v2di_ftype_v16qi
21873 = build_function_type_list (V2DI_type_node, V16QI_type_node,
21875 tree v4si_ftype_v8hi
21876 = build_function_type_list (V4SI_type_node, V8HI_type_node,
21878 tree v2di_ftype_v8hi
21879 = build_function_type_list (V2DI_type_node, V8HI_type_node,
21881 tree v2di_ftype_v4si
21882 = build_function_type_list (V2DI_type_node, V4SI_type_node,
21884 tree v2di_ftype_pv2di
21885 = build_function_type_list (V2DI_type_node, pv2di_type_node,
21887 tree v16qi_ftype_v16qi_v16qi_int
21888 = build_function_type_list (V16QI_type_node, V16QI_type_node,
21889 V16QI_type_node, integer_type_node,
21891 tree v16qi_ftype_v16qi_v16qi_v16qi
21892 = build_function_type_list (V16QI_type_node, V16QI_type_node,
21893 V16QI_type_node, V16QI_type_node,
21895 tree v8hi_ftype_v8hi_v8hi_int
21896 = build_function_type_list (V8HI_type_node, V8HI_type_node,
21897 V8HI_type_node, integer_type_node,
21899 tree v4si_ftype_v4si_v4si_int
21900 = build_function_type_list (V4SI_type_node, V4SI_type_node,
21901 V4SI_type_node, integer_type_node,
21903 tree int_ftype_v2di_v2di
21904 = build_function_type_list (integer_type_node,
21905 V2DI_type_node, V2DI_type_node,
21907 tree int_ftype_v16qi_int_v16qi_int_int
21908 = build_function_type_list (integer_type_node,
21915 tree v16qi_ftype_v16qi_int_v16qi_int_int
21916 = build_function_type_list (V16QI_type_node,
21923 tree int_ftype_v16qi_v16qi_int
21924 = build_function_type_list (integer_type_node,
21930 /* SSE5 instructions */
21931 tree v2di_ftype_v2di_v2di_v2di
21932 = build_function_type_list (V2DI_type_node,
21938 tree v4si_ftype_v4si_v4si_v4si
21939 = build_function_type_list (V4SI_type_node,
21945 tree v4si_ftype_v4si_v4si_v2di
21946 = build_function_type_list (V4SI_type_node,
21952 tree v8hi_ftype_v8hi_v8hi_v8hi
21953 = build_function_type_list (V8HI_type_node,
21959 tree v8hi_ftype_v8hi_v8hi_v4si
21960 = build_function_type_list (V8HI_type_node,
21966 tree v2df_ftype_v2df_v2df_v16qi
21967 = build_function_type_list (V2DF_type_node,
21973 tree v4sf_ftype_v4sf_v4sf_v16qi
21974 = build_function_type_list (V4SF_type_node,
21980 tree v2di_ftype_v2di_si
21981 = build_function_type_list (V2DI_type_node,
21986 tree v4si_ftype_v4si_si
21987 = build_function_type_list (V4SI_type_node,
21992 tree v8hi_ftype_v8hi_si
21993 = build_function_type_list (V8HI_type_node,
21998 tree v16qi_ftype_v16qi_si
21999 = build_function_type_list (V16QI_type_node,
22003 tree v4sf_ftype_v4hi
22004 = build_function_type_list (V4SF_type_node,
22008 tree v4hi_ftype_v4sf
22009 = build_function_type_list (V4HI_type_node,
22013 tree v2di_ftype_v2di
22014 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22016 tree v16qi_ftype_v8hi_v8hi
22017 = build_function_type_list (V16QI_type_node,
22018 V8HI_type_node, V8HI_type_node,
22020 tree v8hi_ftype_v4si_v4si
22021 = build_function_type_list (V8HI_type_node,
22022 V4SI_type_node, V4SI_type_node,
22024 tree v8hi_ftype_v16qi_v16qi
22025 = build_function_type_list (V8HI_type_node,
22026 V16QI_type_node, V16QI_type_node,
22028 tree v4hi_ftype_v8qi_v8qi
22029 = build_function_type_list (V4HI_type_node,
22030 V8QI_type_node, V8QI_type_node,
22032 tree unsigned_ftype_unsigned_uchar
22033 = build_function_type_list (unsigned_type_node,
22034 unsigned_type_node,
22035 unsigned_char_type_node,
22037 tree unsigned_ftype_unsigned_ushort
22038 = build_function_type_list (unsigned_type_node,
22039 unsigned_type_node,
22040 short_unsigned_type_node,
22042 tree unsigned_ftype_unsigned_unsigned
22043 = build_function_type_list (unsigned_type_node,
22044 unsigned_type_node,
22045 unsigned_type_node,
22047 tree uint64_ftype_uint64_uint64
22048 = build_function_type_list (long_long_unsigned_type_node,
22049 long_long_unsigned_type_node,
22050 long_long_unsigned_type_node,
22052 tree float_ftype_float
22053 = build_function_type_list (float_type_node,
22058 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22060 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22062 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22064 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22066 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22068 tree v8sf_ftype_v8sf
22069 = build_function_type_list (V8SF_type_node,
22072 tree v8si_ftype_v8sf
22073 = build_function_type_list (V8SI_type_node,
22076 tree v8sf_ftype_v8si
22077 = build_function_type_list (V8SF_type_node,
22080 tree v4si_ftype_v4df
22081 = build_function_type_list (V4SI_type_node,
22084 tree v4df_ftype_v4df
22085 = build_function_type_list (V4DF_type_node,
22088 tree v4df_ftype_v4si
22089 = build_function_type_list (V4DF_type_node,
22092 tree v4df_ftype_v4sf
22093 = build_function_type_list (V4DF_type_node,
22096 tree v4sf_ftype_v4df
22097 = build_function_type_list (V4SF_type_node,
22100 tree v8sf_ftype_v8sf_v8sf
22101 = build_function_type_list (V8SF_type_node,
22102 V8SF_type_node, V8SF_type_node,
22104 tree v4df_ftype_v4df_v4df
22105 = build_function_type_list (V4DF_type_node,
22106 V4DF_type_node, V4DF_type_node,
22108 tree v8sf_ftype_v8sf_int
22109 = build_function_type_list (V8SF_type_node,
22110 V8SF_type_node, integer_type_node,
22112 tree v4si_ftype_v8si_int
22113 = build_function_type_list (V4SI_type_node,
22114 V8SI_type_node, integer_type_node,
22116 tree v4df_ftype_v4df_int
22117 = build_function_type_list (V4DF_type_node,
22118 V4DF_type_node, integer_type_node,
22120 tree v4sf_ftype_v8sf_int
22121 = build_function_type_list (V4SF_type_node,
22122 V8SF_type_node, integer_type_node,
22124 tree v2df_ftype_v4df_int
22125 = build_function_type_list (V2DF_type_node,
22126 V4DF_type_node, integer_type_node,
22128 tree v8sf_ftype_v8sf_v8sf_int
22129 = build_function_type_list (V8SF_type_node,
22130 V8SF_type_node, V8SF_type_node,
22133 tree v8sf_ftype_v8sf_v8sf_v8sf
22134 = build_function_type_list (V8SF_type_node,
22135 V8SF_type_node, V8SF_type_node,
22138 tree v4df_ftype_v4df_v4df_v4df
22139 = build_function_type_list (V4DF_type_node,
22140 V4DF_type_node, V4DF_type_node,
22143 tree v8si_ftype_v8si_v8si_int
22144 = build_function_type_list (V8SI_type_node,
22145 V8SI_type_node, V8SI_type_node,
22148 tree v4df_ftype_v4df_v4df_int
22149 = build_function_type_list (V4DF_type_node,
22150 V4DF_type_node, V4DF_type_node,
22153 tree v8sf_ftype_pcfloat
22154 = build_function_type_list (V8SF_type_node,
22157 tree v4df_ftype_pcdouble
22158 = build_function_type_list (V4DF_type_node,
22159 pcdouble_type_node,
22161 tree pcv4sf_type_node
22162 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22163 tree pcv2df_type_node
22164 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22165 tree v8sf_ftype_pcv4sf
22166 = build_function_type_list (V8SF_type_node,
22169 tree v4df_ftype_pcv2df
22170 = build_function_type_list (V4DF_type_node,
22173 tree v32qi_ftype_pcchar
22174 = build_function_type_list (V32QI_type_node,
22177 tree void_ftype_pchar_v32qi
22178 = build_function_type_list (void_type_node,
22179 pchar_type_node, V32QI_type_node,
22181 tree v8si_ftype_v8si_v4si_int
22182 = build_function_type_list (V8SI_type_node,
22183 V8SI_type_node, V4SI_type_node,
22186 tree v8sf_ftype_v8sf_v4sf_int
22187 = build_function_type_list (V8SF_type_node,
22188 V8SF_type_node, V4SF_type_node,
22191 tree v4df_ftype_v4df_v2df_int
22192 = build_function_type_list (V4DF_type_node,
22193 V4DF_type_node, V2DF_type_node,
22196 tree void_ftype_pfloat_v8sf
22197 = build_function_type_list (void_type_node,
22198 pfloat_type_node, V8SF_type_node,
22200 tree void_ftype_pdouble_v4df
22201 = build_function_type_list (void_type_node,
22202 pdouble_type_node, V4DF_type_node,
22204 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22205 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22206 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22207 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22208 tree pcv8sf_type_node
22209 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22210 tree pcv4df_type_node
22211 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22212 tree v8sf_ftype_pcv8sf_v8sf
22213 = build_function_type_list (V8SF_type_node,
22214 pcv8sf_type_node, V8SF_type_node,
22216 tree v4df_ftype_pcv4df_v4df
22217 = build_function_type_list (V4DF_type_node,
22218 pcv4df_type_node, V4DF_type_node,
22220 tree v4sf_ftype_pcv4sf_v4sf
22221 = build_function_type_list (V4SF_type_node,
22222 pcv4sf_type_node, V4SF_type_node,
22224 tree v2df_ftype_pcv2df_v2df
22225 = build_function_type_list (V2DF_type_node,
22226 pcv2df_type_node, V2DF_type_node,
22228 tree void_ftype_pv8sf_v8sf_v8sf
22229 = build_function_type_list (void_type_node,
22230 pv8sf_type_node, V8SF_type_node,
22233 tree void_ftype_pv4df_v4df_v4df
22234 = build_function_type_list (void_type_node,
22235 pv4df_type_node, V4DF_type_node,
22238 tree void_ftype_pv4sf_v4sf_v4sf
22239 = build_function_type_list (void_type_node,
22240 pv4sf_type_node, V4SF_type_node,
22243 tree void_ftype_pv2df_v2df_v2df
22244 = build_function_type_list (void_type_node,
22245 pv2df_type_node, V2DF_type_node,
22248 tree v4df_ftype_v2df
22249 = build_function_type_list (V4DF_type_node,
22252 tree v8sf_ftype_v4sf
22253 = build_function_type_list (V8SF_type_node,
22256 tree v8si_ftype_v4si
22257 = build_function_type_list (V8SI_type_node,
22260 tree v2df_ftype_v4df
22261 = build_function_type_list (V2DF_type_node,
22264 tree v4sf_ftype_v8sf
22265 = build_function_type_list (V4SF_type_node,
22268 tree v4si_ftype_v8si
22269 = build_function_type_list (V4SI_type_node,
22272 tree int_ftype_v4df
22273 = build_function_type_list (integer_type_node,
22276 tree int_ftype_v8sf
22277 = build_function_type_list (integer_type_node,
22280 tree int_ftype_v8sf_v8sf
22281 = build_function_type_list (integer_type_node,
22282 V8SF_type_node, V8SF_type_node,
22284 tree int_ftype_v4di_v4di
22285 = build_function_type_list (integer_type_node,
22286 V4DI_type_node, V4DI_type_node,
22288 tree int_ftype_v4df_v4df
22289 = build_function_type_list (integer_type_node,
22290 V4DF_type_node, V4DF_type_node,
22292 tree v8sf_ftype_v8sf_v8si
22293 = build_function_type_list (V8SF_type_node,
22294 V8SF_type_node, V8SI_type_node,
22296 tree v4df_ftype_v4df_v4di
22297 = build_function_type_list (V4DF_type_node,
22298 V4DF_type_node, V4DI_type_node,
22300 tree v4sf_ftype_v4sf_v4si
22301 = build_function_type_list (V4SF_type_node,
22302 V4SF_type_node, V4SI_type_node, NULL_TREE);
22303 tree v2df_ftype_v2df_v2di
22304 = build_function_type_list (V2DF_type_node,
22305 V2DF_type_node, V2DI_type_node, NULL_TREE);
22309 /* Add all special builtins with variable number of operands. */
22310 for (i = 0, d = bdesc_special_args;
22311 i < ARRAY_SIZE (bdesc_special_args);
22319 switch ((enum ix86_special_builtin_type) d->flag)
22321 case VOID_FTYPE_VOID:
22322 type = void_ftype_void;
22324 case V32QI_FTYPE_PCCHAR:
22325 type = v32qi_ftype_pcchar;
22327 case V16QI_FTYPE_PCCHAR:
22328 type = v16qi_ftype_pcchar;
22330 case V8SF_FTYPE_PCV4SF:
22331 type = v8sf_ftype_pcv4sf;
22333 case V8SF_FTYPE_PCFLOAT:
22334 type = v8sf_ftype_pcfloat;
22336 case V4DF_FTYPE_PCV2DF:
22337 type = v4df_ftype_pcv2df;
22339 case V4DF_FTYPE_PCDOUBLE:
22340 type = v4df_ftype_pcdouble;
22342 case V4SF_FTYPE_PCFLOAT:
22343 type = v4sf_ftype_pcfloat;
22345 case V2DI_FTYPE_PV2DI:
22346 type = v2di_ftype_pv2di;
22348 case V2DF_FTYPE_PCDOUBLE:
22349 type = v2df_ftype_pcdouble;
22351 case V8SF_FTYPE_PCV8SF_V8SF:
22352 type = v8sf_ftype_pcv8sf_v8sf;
22354 case V4DF_FTYPE_PCV4DF_V4DF:
22355 type = v4df_ftype_pcv4df_v4df;
22357 case V4SF_FTYPE_V4SF_PCV2SF:
22358 type = v4sf_ftype_v4sf_pcv2sf;
22360 case V4SF_FTYPE_PCV4SF_V4SF:
22361 type = v4sf_ftype_pcv4sf_v4sf;
22363 case V2DF_FTYPE_V2DF_PCDOUBLE:
22364 type = v2df_ftype_v2df_pcdouble;
22366 case V2DF_FTYPE_PCV2DF_V2DF:
22367 type = v2df_ftype_pcv2df_v2df;
22369 case VOID_FTYPE_PV2SF_V4SF:
22370 type = void_ftype_pv2sf_v4sf;
22372 case VOID_FTYPE_PV2DI_V2DI:
22373 type = void_ftype_pv2di_v2di;
22375 case VOID_FTYPE_PCHAR_V32QI:
22376 type = void_ftype_pchar_v32qi;
22378 case VOID_FTYPE_PCHAR_V16QI:
22379 type = void_ftype_pchar_v16qi;
22381 case VOID_FTYPE_PFLOAT_V8SF:
22382 type = void_ftype_pfloat_v8sf;
22384 case VOID_FTYPE_PFLOAT_V4SF:
22385 type = void_ftype_pfloat_v4sf;
22387 case VOID_FTYPE_PDOUBLE_V4DF:
22388 type = void_ftype_pdouble_v4df;
22390 case VOID_FTYPE_PDOUBLE_V2DF:
22391 type = void_ftype_pdouble_v2df;
22393 case VOID_FTYPE_PDI_DI:
22394 type = void_ftype_pdi_di;
22396 case VOID_FTYPE_PINT_INT:
22397 type = void_ftype_pint_int;
22399 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22400 type = void_ftype_pv8sf_v8sf_v8sf;
22402 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22403 type = void_ftype_pv4df_v4df_v4df;
22405 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22406 type = void_ftype_pv4sf_v4sf_v4sf;
22408 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22409 type = void_ftype_pv2df_v2df_v2df;
22412 gcc_unreachable ();
22415 def_builtin (d->mask, d->name, type, d->code);
22418 /* Add all builtins with variable number of operands. */
22419 for (i = 0, d = bdesc_args;
22420 i < ARRAY_SIZE (bdesc_args);
22428 switch ((enum ix86_builtin_type) d->flag)
22430 case FLOAT_FTYPE_FLOAT:
22431 type = float_ftype_float;
22433 case INT_FTYPE_V8SF_V8SF_PTEST:
22434 type = int_ftype_v8sf_v8sf;
22436 case INT_FTYPE_V4DI_V4DI_PTEST:
22437 type = int_ftype_v4di_v4di;
22439 case INT_FTYPE_V4DF_V4DF_PTEST:
22440 type = int_ftype_v4df_v4df;
22442 case INT_FTYPE_V4SF_V4SF_PTEST:
22443 type = int_ftype_v4sf_v4sf;
22445 case INT_FTYPE_V2DI_V2DI_PTEST:
22446 type = int_ftype_v2di_v2di;
22448 case INT_FTYPE_V2DF_V2DF_PTEST:
22449 type = int_ftype_v2df_v2df;
22451 case INT64_FTYPE_V4SF:
22452 type = int64_ftype_v4sf;
22454 case INT64_FTYPE_V2DF:
22455 type = int64_ftype_v2df;
22457 case INT_FTYPE_V16QI:
22458 type = int_ftype_v16qi;
22460 case INT_FTYPE_V8QI:
22461 type = int_ftype_v8qi;
22463 case INT_FTYPE_V8SF:
22464 type = int_ftype_v8sf;
22466 case INT_FTYPE_V4DF:
22467 type = int_ftype_v4df;
22469 case INT_FTYPE_V4SF:
22470 type = int_ftype_v4sf;
22472 case INT_FTYPE_V2DF:
22473 type = int_ftype_v2df;
22475 case V16QI_FTYPE_V16QI:
22476 type = v16qi_ftype_v16qi;
22478 case V8SI_FTYPE_V8SF:
22479 type = v8si_ftype_v8sf;
22481 case V8SI_FTYPE_V4SI:
22482 type = v8si_ftype_v4si;
22484 case V8HI_FTYPE_V8HI:
22485 type = v8hi_ftype_v8hi;
22487 case V8HI_FTYPE_V16QI:
22488 type = v8hi_ftype_v16qi;
22490 case V8QI_FTYPE_V8QI:
22491 type = v8qi_ftype_v8qi;
22493 case V8SF_FTYPE_V8SF:
22494 type = v8sf_ftype_v8sf;
22496 case V8SF_FTYPE_V8SI:
22497 type = v8sf_ftype_v8si;
22499 case V8SF_FTYPE_V4SF:
22500 type = v8sf_ftype_v4sf;
22502 case V4SI_FTYPE_V4DF:
22503 type = v4si_ftype_v4df;
22505 case V4SI_FTYPE_V4SI:
22506 type = v4si_ftype_v4si;
22508 case V4SI_FTYPE_V16QI:
22509 type = v4si_ftype_v16qi;
22511 case V4SI_FTYPE_V8SI:
22512 type = v4si_ftype_v8si;
22514 case V4SI_FTYPE_V8HI:
22515 type = v4si_ftype_v8hi;
22517 case V4SI_FTYPE_V4SF:
22518 type = v4si_ftype_v4sf;
22520 case V4SI_FTYPE_V2DF:
22521 type = v4si_ftype_v2df;
22523 case V4HI_FTYPE_V4HI:
22524 type = v4hi_ftype_v4hi;
22526 case V4DF_FTYPE_V4DF:
22527 type = v4df_ftype_v4df;
22529 case V4DF_FTYPE_V4SI:
22530 type = v4df_ftype_v4si;
22532 case V4DF_FTYPE_V4SF:
22533 type = v4df_ftype_v4sf;
22535 case V4DF_FTYPE_V2DF:
22536 type = v4df_ftype_v2df;
22538 case V4SF_FTYPE_V4SF:
22539 case V4SF_FTYPE_V4SF_VEC_MERGE:
22540 type = v4sf_ftype_v4sf;
22542 case V4SF_FTYPE_V8SF:
22543 type = v4sf_ftype_v8sf;
22545 case V4SF_FTYPE_V4SI:
22546 type = v4sf_ftype_v4si;
22548 case V4SF_FTYPE_V4DF:
22549 type = v4sf_ftype_v4df;
22551 case V4SF_FTYPE_V2DF:
22552 type = v4sf_ftype_v2df;
22554 case V2DI_FTYPE_V2DI:
22555 type = v2di_ftype_v2di;
22557 case V2DI_FTYPE_V16QI:
22558 type = v2di_ftype_v16qi;
22560 case V2DI_FTYPE_V8HI:
22561 type = v2di_ftype_v8hi;
22563 case V2DI_FTYPE_V4SI:
22564 type = v2di_ftype_v4si;
22566 case V2SI_FTYPE_V2SI:
22567 type = v2si_ftype_v2si;
22569 case V2SI_FTYPE_V4SF:
22570 type = v2si_ftype_v4sf;
22572 case V2SI_FTYPE_V2DF:
22573 type = v2si_ftype_v2df;
22575 case V2SI_FTYPE_V2SF:
22576 type = v2si_ftype_v2sf;
22578 case V2DF_FTYPE_V4DF:
22579 type = v2df_ftype_v4df;
22581 case V2DF_FTYPE_V4SF:
22582 type = v2df_ftype_v4sf;
22584 case V2DF_FTYPE_V2DF:
22585 case V2DF_FTYPE_V2DF_VEC_MERGE:
22586 type = v2df_ftype_v2df;
22588 case V2DF_FTYPE_V2SI:
22589 type = v2df_ftype_v2si;
22591 case V2DF_FTYPE_V4SI:
22592 type = v2df_ftype_v4si;
22594 case V2SF_FTYPE_V2SF:
22595 type = v2sf_ftype_v2sf;
22597 case V2SF_FTYPE_V2SI:
22598 type = v2sf_ftype_v2si;
22600 case V16QI_FTYPE_V16QI_V16QI:
22601 type = v16qi_ftype_v16qi_v16qi;
22603 case V16QI_FTYPE_V8HI_V8HI:
22604 type = v16qi_ftype_v8hi_v8hi;
22606 case V8QI_FTYPE_V8QI_V8QI:
22607 type = v8qi_ftype_v8qi_v8qi;
22609 case V8QI_FTYPE_V4HI_V4HI:
22610 type = v8qi_ftype_v4hi_v4hi;
22612 case V8HI_FTYPE_V8HI_V8HI:
22613 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22614 type = v8hi_ftype_v8hi_v8hi;
22616 case V8HI_FTYPE_V16QI_V16QI:
22617 type = v8hi_ftype_v16qi_v16qi;
22619 case V8HI_FTYPE_V4SI_V4SI:
22620 type = v8hi_ftype_v4si_v4si;
22622 case V8HI_FTYPE_V8HI_SI_COUNT:
22623 type = v8hi_ftype_v8hi_int;
22625 case V8SF_FTYPE_V8SF_V8SF:
22626 type = v8sf_ftype_v8sf_v8sf;
22628 case V8SF_FTYPE_V8SF_V8SI:
22629 type = v8sf_ftype_v8sf_v8si;
22631 case V4SI_FTYPE_V4SI_V4SI:
22632 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22633 type = v4si_ftype_v4si_v4si;
22635 case V4SI_FTYPE_V8HI_V8HI:
22636 type = v4si_ftype_v8hi_v8hi;
22638 case V4SI_FTYPE_V4SF_V4SF:
22639 type = v4si_ftype_v4sf_v4sf;
22641 case V4SI_FTYPE_V2DF_V2DF:
22642 type = v4si_ftype_v2df_v2df;
22644 case V4SI_FTYPE_V4SI_SI_COUNT:
22645 type = v4si_ftype_v4si_int;
22647 case V4HI_FTYPE_V4HI_V4HI:
22648 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22649 type = v4hi_ftype_v4hi_v4hi;
22651 case V4HI_FTYPE_V8QI_V8QI:
22652 type = v4hi_ftype_v8qi_v8qi;
22654 case V4HI_FTYPE_V2SI_V2SI:
22655 type = v4hi_ftype_v2si_v2si;
22657 case V4HI_FTYPE_V4HI_SI_COUNT:
22658 type = v4hi_ftype_v4hi_int;
22660 case V4DF_FTYPE_V4DF_V4DF:
22661 type = v4df_ftype_v4df_v4df;
22663 case V4DF_FTYPE_V4DF_V4DI:
22664 type = v4df_ftype_v4df_v4di;
22666 case V4SF_FTYPE_V4SF_V4SF:
22667 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22668 type = v4sf_ftype_v4sf_v4sf;
22670 case V4SF_FTYPE_V4SF_V4SI:
22671 type = v4sf_ftype_v4sf_v4si;
22673 case V4SF_FTYPE_V4SF_V2SI:
22674 type = v4sf_ftype_v4sf_v2si;
22676 case V4SF_FTYPE_V4SF_V2DF:
22677 type = v4sf_ftype_v4sf_v2df;
22679 case V4SF_FTYPE_V4SF_DI:
22680 type = v4sf_ftype_v4sf_int64;
22682 case V4SF_FTYPE_V4SF_SI:
22683 type = v4sf_ftype_v4sf_int;
22685 case V2DI_FTYPE_V2DI_V2DI:
22686 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22687 type = v2di_ftype_v2di_v2di;
22689 case V2DI_FTYPE_V16QI_V16QI:
22690 type = v2di_ftype_v16qi_v16qi;
22692 case V2DI_FTYPE_V4SI_V4SI:
22693 type = v2di_ftype_v4si_v4si;
22695 case V2DI_FTYPE_V2DI_V16QI:
22696 type = v2di_ftype_v2di_v16qi;
22698 case V2DI_FTYPE_V2DF_V2DF:
22699 type = v2di_ftype_v2df_v2df;
22701 case V2DI_FTYPE_V2DI_SI_COUNT:
22702 type = v2di_ftype_v2di_int;
22704 case V2SI_FTYPE_V2SI_V2SI:
22705 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22706 type = v2si_ftype_v2si_v2si;
22708 case V2SI_FTYPE_V4HI_V4HI:
22709 type = v2si_ftype_v4hi_v4hi;
22711 case V2SI_FTYPE_V2SF_V2SF:
22712 type = v2si_ftype_v2sf_v2sf;
22714 case V2SI_FTYPE_V2SI_SI_COUNT:
22715 type = v2si_ftype_v2si_int;
22717 case V2DF_FTYPE_V2DF_V2DF:
22718 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22719 type = v2df_ftype_v2df_v2df;
22721 case V2DF_FTYPE_V2DF_V4SF:
22722 type = v2df_ftype_v2df_v4sf;
22724 case V2DF_FTYPE_V2DF_V2DI:
22725 type = v2df_ftype_v2df_v2di;
22727 case V2DF_FTYPE_V2DF_DI:
22728 type = v2df_ftype_v2df_int64;
22730 case V2DF_FTYPE_V2DF_SI:
22731 type = v2df_ftype_v2df_int;
22733 case V2SF_FTYPE_V2SF_V2SF:
22734 type = v2sf_ftype_v2sf_v2sf;
22736 case V1DI_FTYPE_V1DI_V1DI:
22737 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22738 type = v1di_ftype_v1di_v1di;
22740 case V1DI_FTYPE_V8QI_V8QI:
22741 type = v1di_ftype_v8qi_v8qi;
22743 case V1DI_FTYPE_V2SI_V2SI:
22744 type = v1di_ftype_v2si_v2si;
22746 case V1DI_FTYPE_V1DI_SI_COUNT:
22747 type = v1di_ftype_v1di_int;
22749 case UINT64_FTYPE_UINT64_UINT64:
22750 type = uint64_ftype_uint64_uint64;
22752 case UINT_FTYPE_UINT_UINT:
22753 type = unsigned_ftype_unsigned_unsigned;
22755 case UINT_FTYPE_UINT_USHORT:
22756 type = unsigned_ftype_unsigned_ushort;
22758 case UINT_FTYPE_UINT_UCHAR:
22759 type = unsigned_ftype_unsigned_uchar;
22761 case V8HI_FTYPE_V8HI_INT:
22762 type = v8hi_ftype_v8hi_int;
22764 case V8SF_FTYPE_V8SF_INT:
22765 type = v8sf_ftype_v8sf_int;
22767 case V4SI_FTYPE_V4SI_INT:
22768 type = v4si_ftype_v4si_int;
22770 case V4SI_FTYPE_V8SI_INT:
22771 type = v4si_ftype_v8si_int;
22773 case V4HI_FTYPE_V4HI_INT:
22774 type = v4hi_ftype_v4hi_int;
22776 case V4DF_FTYPE_V4DF_INT:
22777 type = v4df_ftype_v4df_int;
22779 case V4SF_FTYPE_V4SF_INT:
22780 type = v4sf_ftype_v4sf_int;
22782 case V4SF_FTYPE_V8SF_INT:
22783 type = v4sf_ftype_v8sf_int;
22785 case V2DI_FTYPE_V2DI_INT:
22786 case V2DI2TI_FTYPE_V2DI_INT:
22787 type = v2di_ftype_v2di_int;
22789 case V2DF_FTYPE_V2DF_INT:
22790 type = v2df_ftype_v2df_int;
22792 case V2DF_FTYPE_V4DF_INT:
22793 type = v2df_ftype_v4df_int;
22795 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22796 type = v16qi_ftype_v16qi_v16qi_v16qi;
22798 case V8SF_FTYPE_V8SF_V8SF_V8SF:
22799 type = v8sf_ftype_v8sf_v8sf_v8sf;
22801 case V4DF_FTYPE_V4DF_V4DF_V4DF:
22802 type = v4df_ftype_v4df_v4df_v4df;
22804 case V4SF_FTYPE_V4SF_V4SF_V4SF:
22805 type = v4sf_ftype_v4sf_v4sf_v4sf;
22807 case V2DF_FTYPE_V2DF_V2DF_V2DF:
22808 type = v2df_ftype_v2df_v2df_v2df;
22810 case V16QI_FTYPE_V16QI_V16QI_INT:
22811 type = v16qi_ftype_v16qi_v16qi_int;
22813 case V8SI_FTYPE_V8SI_V8SI_INT:
22814 type = v8si_ftype_v8si_v8si_int;
22816 case V8SI_FTYPE_V8SI_V4SI_INT:
22817 type = v8si_ftype_v8si_v4si_int;
22819 case V8HI_FTYPE_V8HI_V8HI_INT:
22820 type = v8hi_ftype_v8hi_v8hi_int;
22822 case V8SF_FTYPE_V8SF_V8SF_INT:
22823 type = v8sf_ftype_v8sf_v8sf_int;
22825 case V8SF_FTYPE_V8SF_V4SF_INT:
22826 type = v8sf_ftype_v8sf_v4sf_int;
22828 case V4SI_FTYPE_V4SI_V4SI_INT:
22829 type = v4si_ftype_v4si_v4si_int;
22831 case V4DF_FTYPE_V4DF_V4DF_INT:
22832 type = v4df_ftype_v4df_v4df_int;
22834 case V4DF_FTYPE_V4DF_V2DF_INT:
22835 type = v4df_ftype_v4df_v2df_int;
22837 case V4SF_FTYPE_V4SF_V4SF_INT:
22838 type = v4sf_ftype_v4sf_v4sf_int;
22840 case V2DI_FTYPE_V2DI_V2DI_INT:
22841 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
22842 type = v2di_ftype_v2di_v2di_int;
22844 case V2DF_FTYPE_V2DF_V2DF_INT:
22845 type = v2df_ftype_v2df_v2df_int;
22847 case V2DI_FTYPE_V2DI_UINT_UINT:
22848 type = v2di_ftype_v2di_unsigned_unsigned;
22850 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
22851 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
22853 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
22854 type = v1di_ftype_v1di_v1di_int;
22857 gcc_unreachable ();
22860 def_builtin_const (d->mask, d->name, type, d->code);
22863 /* pcmpestr[im] insns. */
22864 for (i = 0, d = bdesc_pcmpestr;
22865 i < ARRAY_SIZE (bdesc_pcmpestr);
22868 if (d->code == IX86_BUILTIN_PCMPESTRM128)
22869 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
22871 ftype = int_ftype_v16qi_int_v16qi_int_int;
22872 def_builtin_const (d->mask, d->name, ftype, d->code);
22875 /* pcmpistr[im] insns. */
22876 for (i = 0, d = bdesc_pcmpistr;
22877 i < ARRAY_SIZE (bdesc_pcmpistr);
22880 if (d->code == IX86_BUILTIN_PCMPISTRM128)
22881 ftype = v16qi_ftype_v16qi_v16qi_int;
22883 ftype = int_ftype_v16qi_v16qi_int;
22884 def_builtin_const (d->mask, d->name, ftype, d->code);
22887 /* comi/ucomi insns. */
22888 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
22889 if (d->mask == OPTION_MASK_ISA_SSE2)
22890 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
22892 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
22895 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
22896 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
22898 /* SSE or 3DNow!A */
22899 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
22902 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
22904 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
22905 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
22908 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
22909 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
22912 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
22913 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
22914 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
22915 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
22916 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
22917 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
22920 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
22923 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
22924 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
22926 /* Access to the vec_init patterns. */
22927 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
22928 integer_type_node, NULL_TREE);
22929 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
22931 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
22932 short_integer_type_node,
22933 short_integer_type_node,
22934 short_integer_type_node, NULL_TREE);
22935 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
22937 ftype = build_function_type_list (V8QI_type_node, char_type_node,
22938 char_type_node, char_type_node,
22939 char_type_node, char_type_node,
22940 char_type_node, char_type_node,
22941 char_type_node, NULL_TREE);
22942 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
22944 /* Access to the vec_extract patterns. */
22945 ftype = build_function_type_list (double_type_node, V2DF_type_node,
22946 integer_type_node, NULL_TREE);
22947 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
22949 ftype = build_function_type_list (long_long_integer_type_node,
22950 V2DI_type_node, integer_type_node,
22952 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
22954 ftype = build_function_type_list (float_type_node, V4SF_type_node,
22955 integer_type_node, NULL_TREE);
22956 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
22958 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
22959 integer_type_node, NULL_TREE);
22960 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
22962 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
22963 integer_type_node, NULL_TREE);
22964 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
22966 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
22967 integer_type_node, NULL_TREE);
22968 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
22970 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
22971 integer_type_node, NULL_TREE);
22972 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
22974 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
22975 integer_type_node, NULL_TREE);
22976 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
22978 /* Access to the vec_set patterns. */
22979 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
22981 integer_type_node, NULL_TREE);
22982 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
22984 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
22986 integer_type_node, NULL_TREE);
22987 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
22989 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
22991 integer_type_node, NULL_TREE);
22992 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
22994 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
22996 integer_type_node, NULL_TREE);
22997 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
22999 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23001 integer_type_node, NULL_TREE);
23002 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23004 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23006 integer_type_node, NULL_TREE);
23007 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23009 /* Add SSE5 multi-arg argument instructions */
23010 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23012 tree mtype = NULL_TREE;
23017 switch ((enum multi_arg_type)d->flag)
23019 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23020 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23021 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23022 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23023 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23024 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23025 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23026 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23027 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23028 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23029 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23030 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23031 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23032 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23033 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23034 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23035 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23036 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23037 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23038 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23039 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23040 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23041 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23042 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23043 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23044 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23045 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23046 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23047 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23048 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23049 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23050 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23051 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23052 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23053 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23054 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23055 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23056 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23057 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23058 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23059 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23060 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23061 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23062 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23063 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23064 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23065 case MULTI_ARG_UNKNOWN:
23067 gcc_unreachable ();
23071 def_builtin_const (d->mask, d->name, mtype, d->code);
23075 /* Internal method for ix86_init_builtins. */
23078 ix86_init_builtins_va_builtins_abi (void)
23080 tree ms_va_ref, sysv_va_ref;
23081 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23082 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23083 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23084 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23088 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23089 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23090 ms_va_ref = build_reference_type (ms_va_list_type_node);
23092 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23095 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23096 fnvoid_va_start_ms =
23097 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23098 fnvoid_va_end_sysv =
23099 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23100 fnvoid_va_start_sysv =
23101 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23103 fnvoid_va_copy_ms =
23104 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23106 fnvoid_va_copy_sysv =
23107 build_function_type_list (void_type_node, sysv_va_ref,
23108 sysv_va_ref, NULL_TREE);
23110 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23111 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23112 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23113 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23114 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23115 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23116 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23117 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23118 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23119 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23120 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23121 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23125 ix86_init_builtins (void)
23127 tree float128_type_node = make_node (REAL_TYPE);
23130 /* The __float80 type. */
23131 if (TYPE_MODE (long_double_type_node) == XFmode)
23132 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23136 /* The __float80 type. */
23137 tree float80_type_node = make_node (REAL_TYPE);
23139 TYPE_PRECISION (float80_type_node) = 80;
23140 layout_type (float80_type_node);
23141 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23145 /* The __float128 type. */
23146 TYPE_PRECISION (float128_type_node) = 128;
23147 layout_type (float128_type_node);
23148 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23151 /* TFmode support builtins. */
23152 ftype = build_function_type (float128_type_node, void_list_node);
23153 decl = add_builtin_function ("__builtin_infq", ftype,
23154 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23156 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23158 /* We will expand them to normal call if SSE2 isn't available since
23159 they are used by libgcc. */
23160 ftype = build_function_type_list (float128_type_node,
23161 float128_type_node,
23163 decl = add_builtin_function ("__builtin_fabsq", ftype,
23164 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23165 "__fabstf2", NULL_TREE);
23166 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23167 TREE_READONLY (decl) = 1;
23169 ftype = build_function_type_list (float128_type_node,
23170 float128_type_node,
23171 float128_type_node,
23173 decl = add_builtin_function ("__builtin_copysignq", ftype,
23174 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23175 "__copysigntf3", NULL_TREE);
23176 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23177 TREE_READONLY (decl) = 1;
23179 ix86_init_mmx_sse_builtins ();
23181 ix86_init_builtins_va_builtins_abi ();
23184 /* Errors in the source file can cause expand_expr to return const0_rtx
23185 where we expect a vector. To avoid crashing, use one of the vector
23186 clear instructions. */
23188 safe_vector_operand (rtx x, enum machine_mode mode)
23190 if (x == const0_rtx)
23191 x = CONST0_RTX (mode);
23195 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23198 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23201 tree arg0 = CALL_EXPR_ARG (exp, 0);
23202 tree arg1 = CALL_EXPR_ARG (exp, 1);
23203 rtx op0 = expand_normal (arg0);
23204 rtx op1 = expand_normal (arg1);
23205 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23206 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23207 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23209 if (VECTOR_MODE_P (mode0))
23210 op0 = safe_vector_operand (op0, mode0);
23211 if (VECTOR_MODE_P (mode1))
23212 op1 = safe_vector_operand (op1, mode1);
23214 if (optimize || !target
23215 || GET_MODE (target) != tmode
23216 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23217 target = gen_reg_rtx (tmode);
23219 if (GET_MODE (op1) == SImode && mode1 == TImode)
23221 rtx x = gen_reg_rtx (V4SImode);
23222 emit_insn (gen_sse2_loadd (x, op1));
23223 op1 = gen_lowpart (TImode, x);
23226 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23227 op0 = copy_to_mode_reg (mode0, op0);
23228 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23229 op1 = copy_to_mode_reg (mode1, op1);
23231 pat = GEN_FCN (icode) (target, op0, op1);
23240 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23243 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23244 enum multi_arg_type m_type,
23245 enum insn_code sub_code)
23250 bool comparison_p = false;
23252 bool last_arg_constant = false;
23253 int num_memory = 0;
23256 enum machine_mode mode;
23259 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23263 case MULTI_ARG_3_SF:
23264 case MULTI_ARG_3_DF:
23265 case MULTI_ARG_3_DI:
23266 case MULTI_ARG_3_SI:
23267 case MULTI_ARG_3_SI_DI:
23268 case MULTI_ARG_3_HI:
23269 case MULTI_ARG_3_HI_SI:
23270 case MULTI_ARG_3_QI:
23271 case MULTI_ARG_3_PERMPS:
23272 case MULTI_ARG_3_PERMPD:
23276 case MULTI_ARG_2_SF:
23277 case MULTI_ARG_2_DF:
23278 case MULTI_ARG_2_DI:
23279 case MULTI_ARG_2_SI:
23280 case MULTI_ARG_2_HI:
23281 case MULTI_ARG_2_QI:
23285 case MULTI_ARG_2_DI_IMM:
23286 case MULTI_ARG_2_SI_IMM:
23287 case MULTI_ARG_2_HI_IMM:
23288 case MULTI_ARG_2_QI_IMM:
23290 last_arg_constant = true;
23293 case MULTI_ARG_1_SF:
23294 case MULTI_ARG_1_DF:
23295 case MULTI_ARG_1_DI:
23296 case MULTI_ARG_1_SI:
23297 case MULTI_ARG_1_HI:
23298 case MULTI_ARG_1_QI:
23299 case MULTI_ARG_1_SI_DI:
23300 case MULTI_ARG_1_HI_DI:
23301 case MULTI_ARG_1_HI_SI:
23302 case MULTI_ARG_1_QI_DI:
23303 case MULTI_ARG_1_QI_SI:
23304 case MULTI_ARG_1_QI_HI:
23305 case MULTI_ARG_1_PH2PS:
23306 case MULTI_ARG_1_PS2PH:
23310 case MULTI_ARG_2_SF_CMP:
23311 case MULTI_ARG_2_DF_CMP:
23312 case MULTI_ARG_2_DI_CMP:
23313 case MULTI_ARG_2_SI_CMP:
23314 case MULTI_ARG_2_HI_CMP:
23315 case MULTI_ARG_2_QI_CMP:
23317 comparison_p = true;
23320 case MULTI_ARG_2_SF_TF:
23321 case MULTI_ARG_2_DF_TF:
23322 case MULTI_ARG_2_DI_TF:
23323 case MULTI_ARG_2_SI_TF:
23324 case MULTI_ARG_2_HI_TF:
23325 case MULTI_ARG_2_QI_TF:
23330 case MULTI_ARG_UNKNOWN:
23332 gcc_unreachable ();
23335 if (optimize || !target
23336 || GET_MODE (target) != tmode
23337 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23338 target = gen_reg_rtx (tmode);
23340 gcc_assert (nargs <= 4);
23342 for (i = 0; i < nargs; i++)
23344 tree arg = CALL_EXPR_ARG (exp, i);
23345 rtx op = expand_normal (arg);
23346 int adjust = (comparison_p) ? 1 : 0;
23347 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23349 if (last_arg_constant && i == nargs-1)
23351 if (GET_CODE (op) != CONST_INT)
23353 error ("last argument must be an immediate");
23354 return gen_reg_rtx (tmode);
23359 if (VECTOR_MODE_P (mode))
23360 op = safe_vector_operand (op, mode);
23362 /* If we aren't optimizing, only allow one memory operand to be
23364 if (memory_operand (op, mode))
23367 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23370 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23372 op = force_reg (mode, op);
23376 args[i].mode = mode;
23382 pat = GEN_FCN (icode) (target, args[0].op);
23387 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23388 GEN_INT ((int)sub_code));
23389 else if (! comparison_p)
23390 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23393 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23397 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23402 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23406 gcc_unreachable ();
23416 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23417 insns with vec_merge. */
23420 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23424 tree arg0 = CALL_EXPR_ARG (exp, 0);
23425 rtx op1, op0 = expand_normal (arg0);
23426 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23427 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23429 if (optimize || !target
23430 || GET_MODE (target) != tmode
23431 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23432 target = gen_reg_rtx (tmode);
23434 if (VECTOR_MODE_P (mode0))
23435 op0 = safe_vector_operand (op0, mode0);
23437 if ((optimize && !register_operand (op0, mode0))
23438 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23439 op0 = copy_to_mode_reg (mode0, op0);
23442 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23443 op1 = copy_to_mode_reg (mode0, op1);
23445 pat = GEN_FCN (icode) (target, op0, op1);
23452 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23455 ix86_expand_sse_compare (const struct builtin_description *d,
23456 tree exp, rtx target, bool swap)
23459 tree arg0 = CALL_EXPR_ARG (exp, 0);
23460 tree arg1 = CALL_EXPR_ARG (exp, 1);
23461 rtx op0 = expand_normal (arg0);
23462 rtx op1 = expand_normal (arg1);
23464 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23465 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23466 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23467 enum rtx_code comparison = d->comparison;
23469 if (VECTOR_MODE_P (mode0))
23470 op0 = safe_vector_operand (op0, mode0);
23471 if (VECTOR_MODE_P (mode1))
23472 op1 = safe_vector_operand (op1, mode1);
23474 /* Swap operands if we have a comparison that isn't available in
23478 rtx tmp = gen_reg_rtx (mode1);
23479 emit_move_insn (tmp, op1);
23484 if (optimize || !target
23485 || GET_MODE (target) != tmode
23486 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23487 target = gen_reg_rtx (tmode);
23489 if ((optimize && !register_operand (op0, mode0))
23490 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23491 op0 = copy_to_mode_reg (mode0, op0);
23492 if ((optimize && !register_operand (op1, mode1))
23493 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23494 op1 = copy_to_mode_reg (mode1, op1);
23496 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23497 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23504 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23507 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23511 tree arg0 = CALL_EXPR_ARG (exp, 0);
23512 tree arg1 = CALL_EXPR_ARG (exp, 1);
23513 rtx op0 = expand_normal (arg0);
23514 rtx op1 = expand_normal (arg1);
23515 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23516 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23517 enum rtx_code comparison = d->comparison;
23519 if (VECTOR_MODE_P (mode0))
23520 op0 = safe_vector_operand (op0, mode0);
23521 if (VECTOR_MODE_P (mode1))
23522 op1 = safe_vector_operand (op1, mode1);
23524 /* Swap operands if we have a comparison that isn't available in
23526 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23533 target = gen_reg_rtx (SImode);
23534 emit_move_insn (target, const0_rtx);
23535 target = gen_rtx_SUBREG (QImode, target, 0);
23537 if ((optimize && !register_operand (op0, mode0))
23538 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23539 op0 = copy_to_mode_reg (mode0, op0);
23540 if ((optimize && !register_operand (op1, mode1))
23541 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23542 op1 = copy_to_mode_reg (mode1, op1);
23544 pat = GEN_FCN (d->icode) (op0, op1);
23548 emit_insn (gen_rtx_SET (VOIDmode,
23549 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23550 gen_rtx_fmt_ee (comparison, QImode,
23554 return SUBREG_REG (target);
23557 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23560 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23564 tree arg0 = CALL_EXPR_ARG (exp, 0);
23565 tree arg1 = CALL_EXPR_ARG (exp, 1);
23566 rtx op0 = expand_normal (arg0);
23567 rtx op1 = expand_normal (arg1);
23568 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23569 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23570 enum rtx_code comparison = d->comparison;
23572 if (VECTOR_MODE_P (mode0))
23573 op0 = safe_vector_operand (op0, mode0);
23574 if (VECTOR_MODE_P (mode1))
23575 op1 = safe_vector_operand (op1, mode1);
23577 target = gen_reg_rtx (SImode);
23578 emit_move_insn (target, const0_rtx);
23579 target = gen_rtx_SUBREG (QImode, target, 0);
23581 if ((optimize && !register_operand (op0, mode0))
23582 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23583 op0 = copy_to_mode_reg (mode0, op0);
23584 if ((optimize && !register_operand (op1, mode1))
23585 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23586 op1 = copy_to_mode_reg (mode1, op1);
23588 pat = GEN_FCN (d->icode) (op0, op1);
23592 emit_insn (gen_rtx_SET (VOIDmode,
23593 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23594 gen_rtx_fmt_ee (comparison, QImode,
23598 return SUBREG_REG (target);
23601 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23604 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23605 tree exp, rtx target)
23608 tree arg0 = CALL_EXPR_ARG (exp, 0);
23609 tree arg1 = CALL_EXPR_ARG (exp, 1);
23610 tree arg2 = CALL_EXPR_ARG (exp, 2);
23611 tree arg3 = CALL_EXPR_ARG (exp, 3);
23612 tree arg4 = CALL_EXPR_ARG (exp, 4);
23613 rtx scratch0, scratch1;
23614 rtx op0 = expand_normal (arg0);
23615 rtx op1 = expand_normal (arg1);
23616 rtx op2 = expand_normal (arg2);
23617 rtx op3 = expand_normal (arg3);
23618 rtx op4 = expand_normal (arg4);
23619 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23621 tmode0 = insn_data[d->icode].operand[0].mode;
23622 tmode1 = insn_data[d->icode].operand[1].mode;
23623 modev2 = insn_data[d->icode].operand[2].mode;
23624 modei3 = insn_data[d->icode].operand[3].mode;
23625 modev4 = insn_data[d->icode].operand[4].mode;
23626 modei5 = insn_data[d->icode].operand[5].mode;
23627 modeimm = insn_data[d->icode].operand[6].mode;
23629 if (VECTOR_MODE_P (modev2))
23630 op0 = safe_vector_operand (op0, modev2);
23631 if (VECTOR_MODE_P (modev4))
23632 op2 = safe_vector_operand (op2, modev4);
23634 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23635 op0 = copy_to_mode_reg (modev2, op0);
23636 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23637 op1 = copy_to_mode_reg (modei3, op1);
23638 if ((optimize && !register_operand (op2, modev4))
23639 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23640 op2 = copy_to_mode_reg (modev4, op2);
23641 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23642 op3 = copy_to_mode_reg (modei5, op3);
23644 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23646 error ("the fifth argument must be a 8-bit immediate");
23650 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23652 if (optimize || !target
23653 || GET_MODE (target) != tmode0
23654 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23655 target = gen_reg_rtx (tmode0);
23657 scratch1 = gen_reg_rtx (tmode1);
23659 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23661 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23663 if (optimize || !target
23664 || GET_MODE (target) != tmode1
23665 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23666 target = gen_reg_rtx (tmode1);
23668 scratch0 = gen_reg_rtx (tmode0);
23670 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23674 gcc_assert (d->flag);
23676 scratch0 = gen_reg_rtx (tmode0);
23677 scratch1 = gen_reg_rtx (tmode1);
23679 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23689 target = gen_reg_rtx (SImode);
23690 emit_move_insn (target, const0_rtx);
23691 target = gen_rtx_SUBREG (QImode, target, 0);
23694 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23695 gen_rtx_fmt_ee (EQ, QImode,
23696 gen_rtx_REG ((enum machine_mode) d->flag,
23699 return SUBREG_REG (target);
23706 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23709 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23710 tree exp, rtx target)
23713 tree arg0 = CALL_EXPR_ARG (exp, 0);
23714 tree arg1 = CALL_EXPR_ARG (exp, 1);
23715 tree arg2 = CALL_EXPR_ARG (exp, 2);
23716 rtx scratch0, scratch1;
23717 rtx op0 = expand_normal (arg0);
23718 rtx op1 = expand_normal (arg1);
23719 rtx op2 = expand_normal (arg2);
23720 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23722 tmode0 = insn_data[d->icode].operand[0].mode;
23723 tmode1 = insn_data[d->icode].operand[1].mode;
23724 modev2 = insn_data[d->icode].operand[2].mode;
23725 modev3 = insn_data[d->icode].operand[3].mode;
23726 modeimm = insn_data[d->icode].operand[4].mode;
23728 if (VECTOR_MODE_P (modev2))
23729 op0 = safe_vector_operand (op0, modev2);
23730 if (VECTOR_MODE_P (modev3))
23731 op1 = safe_vector_operand (op1, modev3);
23733 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23734 op0 = copy_to_mode_reg (modev2, op0);
23735 if ((optimize && !register_operand (op1, modev3))
23736 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23737 op1 = copy_to_mode_reg (modev3, op1);
23739 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23741 error ("the third argument must be a 8-bit immediate");
23745 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23747 if (optimize || !target
23748 || GET_MODE (target) != tmode0
23749 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23750 target = gen_reg_rtx (tmode0);
23752 scratch1 = gen_reg_rtx (tmode1);
23754 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23756 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23758 if (optimize || !target
23759 || GET_MODE (target) != tmode1
23760 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23761 target = gen_reg_rtx (tmode1);
23763 scratch0 = gen_reg_rtx (tmode0);
23765 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23769 gcc_assert (d->flag);
23771 scratch0 = gen_reg_rtx (tmode0);
23772 scratch1 = gen_reg_rtx (tmode1);
23774 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23784 target = gen_reg_rtx (SImode);
23785 emit_move_insn (target, const0_rtx);
23786 target = gen_rtx_SUBREG (QImode, target, 0);
23789 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23790 gen_rtx_fmt_ee (EQ, QImode,
23791 gen_rtx_REG ((enum machine_mode) d->flag,
23794 return SUBREG_REG (target);
23800 /* Subroutine of ix86_expand_builtin to take care of insns with
23801 variable number of operands. */
23804 ix86_expand_args_builtin (const struct builtin_description *d,
23805 tree exp, rtx target)
23807 rtx pat, real_target;
23808 unsigned int i, nargs;
23809 unsigned int nargs_constant = 0;
23810 int num_memory = 0;
23814 enum machine_mode mode;
23816 bool last_arg_count = false;
23817 enum insn_code icode = d->icode;
23818 const struct insn_data *insn_p = &insn_data[icode];
23819 enum machine_mode tmode = insn_p->operand[0].mode;
23820 enum machine_mode rmode = VOIDmode;
23822 enum rtx_code comparison = d->comparison;
23824 switch ((enum ix86_builtin_type) d->flag)
23826 case INT_FTYPE_V8SF_V8SF_PTEST:
23827 case INT_FTYPE_V4DI_V4DI_PTEST:
23828 case INT_FTYPE_V4DF_V4DF_PTEST:
23829 case INT_FTYPE_V4SF_V4SF_PTEST:
23830 case INT_FTYPE_V2DI_V2DI_PTEST:
23831 case INT_FTYPE_V2DF_V2DF_PTEST:
23832 return ix86_expand_sse_ptest (d, exp, target);
23833 case FLOAT128_FTYPE_FLOAT128:
23834 case FLOAT_FTYPE_FLOAT:
23835 case INT64_FTYPE_V4SF:
23836 case INT64_FTYPE_V2DF:
23837 case INT_FTYPE_V16QI:
23838 case INT_FTYPE_V8QI:
23839 case INT_FTYPE_V8SF:
23840 case INT_FTYPE_V4DF:
23841 case INT_FTYPE_V4SF:
23842 case INT_FTYPE_V2DF:
23843 case V16QI_FTYPE_V16QI:
23844 case V8SI_FTYPE_V8SF:
23845 case V8SI_FTYPE_V4SI:
23846 case V8HI_FTYPE_V8HI:
23847 case V8HI_FTYPE_V16QI:
23848 case V8QI_FTYPE_V8QI:
23849 case V8SF_FTYPE_V8SF:
23850 case V8SF_FTYPE_V8SI:
23851 case V8SF_FTYPE_V4SF:
23852 case V4SI_FTYPE_V4SI:
23853 case V4SI_FTYPE_V16QI:
23854 case V4SI_FTYPE_V4SF:
23855 case V4SI_FTYPE_V8SI:
23856 case V4SI_FTYPE_V8HI:
23857 case V4SI_FTYPE_V4DF:
23858 case V4SI_FTYPE_V2DF:
23859 case V4HI_FTYPE_V4HI:
23860 case V4DF_FTYPE_V4DF:
23861 case V4DF_FTYPE_V4SI:
23862 case V4DF_FTYPE_V4SF:
23863 case V4DF_FTYPE_V2DF:
23864 case V4SF_FTYPE_V4SF:
23865 case V4SF_FTYPE_V4SI:
23866 case V4SF_FTYPE_V8SF:
23867 case V4SF_FTYPE_V4DF:
23868 case V4SF_FTYPE_V2DF:
23869 case V2DI_FTYPE_V2DI:
23870 case V2DI_FTYPE_V16QI:
23871 case V2DI_FTYPE_V8HI:
23872 case V2DI_FTYPE_V4SI:
23873 case V2DF_FTYPE_V2DF:
23874 case V2DF_FTYPE_V4SI:
23875 case V2DF_FTYPE_V4DF:
23876 case V2DF_FTYPE_V4SF:
23877 case V2DF_FTYPE_V2SI:
23878 case V2SI_FTYPE_V2SI:
23879 case V2SI_FTYPE_V4SF:
23880 case V2SI_FTYPE_V2SF:
23881 case V2SI_FTYPE_V2DF:
23882 case V2SF_FTYPE_V2SF:
23883 case V2SF_FTYPE_V2SI:
23886 case V4SF_FTYPE_V4SF_VEC_MERGE:
23887 case V2DF_FTYPE_V2DF_VEC_MERGE:
23888 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
23889 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
23890 case V16QI_FTYPE_V16QI_V16QI:
23891 case V16QI_FTYPE_V8HI_V8HI:
23892 case V8QI_FTYPE_V8QI_V8QI:
23893 case V8QI_FTYPE_V4HI_V4HI:
23894 case V8HI_FTYPE_V8HI_V8HI:
23895 case V8HI_FTYPE_V16QI_V16QI:
23896 case V8HI_FTYPE_V4SI_V4SI:
23897 case V8SF_FTYPE_V8SF_V8SF:
23898 case V8SF_FTYPE_V8SF_V8SI:
23899 case V4SI_FTYPE_V4SI_V4SI:
23900 case V4SI_FTYPE_V8HI_V8HI:
23901 case V4SI_FTYPE_V4SF_V4SF:
23902 case V4SI_FTYPE_V2DF_V2DF:
23903 case V4HI_FTYPE_V4HI_V4HI:
23904 case V4HI_FTYPE_V8QI_V8QI:
23905 case V4HI_FTYPE_V2SI_V2SI:
23906 case V4DF_FTYPE_V4DF_V4DF:
23907 case V4DF_FTYPE_V4DF_V4DI:
23908 case V4SF_FTYPE_V4SF_V4SF:
23909 case V4SF_FTYPE_V4SF_V4SI:
23910 case V4SF_FTYPE_V4SF_V2SI:
23911 case V4SF_FTYPE_V4SF_V2DF:
23912 case V4SF_FTYPE_V4SF_DI:
23913 case V4SF_FTYPE_V4SF_SI:
23914 case V2DI_FTYPE_V2DI_V2DI:
23915 case V2DI_FTYPE_V16QI_V16QI:
23916 case V2DI_FTYPE_V4SI_V4SI:
23917 case V2DI_FTYPE_V2DI_V16QI:
23918 case V2DI_FTYPE_V2DF_V2DF:
23919 case V2SI_FTYPE_V2SI_V2SI:
23920 case V2SI_FTYPE_V4HI_V4HI:
23921 case V2SI_FTYPE_V2SF_V2SF:
23922 case V2DF_FTYPE_V2DF_V2DF:
23923 case V2DF_FTYPE_V2DF_V4SF:
23924 case V2DF_FTYPE_V2DF_V2DI:
23925 case V2DF_FTYPE_V2DF_DI:
23926 case V2DF_FTYPE_V2DF_SI:
23927 case V2SF_FTYPE_V2SF_V2SF:
23928 case V1DI_FTYPE_V1DI_V1DI:
23929 case V1DI_FTYPE_V8QI_V8QI:
23930 case V1DI_FTYPE_V2SI_V2SI:
23931 if (comparison == UNKNOWN)
23932 return ix86_expand_binop_builtin (icode, exp, target);
23935 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23936 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23937 gcc_assert (comparison != UNKNOWN);
23941 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23942 case V8HI_FTYPE_V8HI_SI_COUNT:
23943 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23944 case V4SI_FTYPE_V4SI_SI_COUNT:
23945 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23946 case V4HI_FTYPE_V4HI_SI_COUNT:
23947 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23948 case V2DI_FTYPE_V2DI_SI_COUNT:
23949 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23950 case V2SI_FTYPE_V2SI_SI_COUNT:
23951 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23952 case V1DI_FTYPE_V1DI_SI_COUNT:
23954 last_arg_count = true;
23956 case UINT64_FTYPE_UINT64_UINT64:
23957 case UINT_FTYPE_UINT_UINT:
23958 case UINT_FTYPE_UINT_USHORT:
23959 case UINT_FTYPE_UINT_UCHAR:
23962 case V2DI2TI_FTYPE_V2DI_INT:
23965 nargs_constant = 1;
23967 case V8HI_FTYPE_V8HI_INT:
23968 case V8SF_FTYPE_V8SF_INT:
23969 case V4SI_FTYPE_V4SI_INT:
23970 case V4SI_FTYPE_V8SI_INT:
23971 case V4HI_FTYPE_V4HI_INT:
23972 case V4DF_FTYPE_V4DF_INT:
23973 case V4SF_FTYPE_V4SF_INT:
23974 case V4SF_FTYPE_V8SF_INT:
23975 case V2DI_FTYPE_V2DI_INT:
23976 case V2DF_FTYPE_V2DF_INT:
23977 case V2DF_FTYPE_V4DF_INT:
23979 nargs_constant = 1;
23981 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23982 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23983 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23984 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23985 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23988 case V16QI_FTYPE_V16QI_V16QI_INT:
23989 case V8HI_FTYPE_V8HI_V8HI_INT:
23990 case V8SI_FTYPE_V8SI_V8SI_INT:
23991 case V8SI_FTYPE_V8SI_V4SI_INT:
23992 case V8SF_FTYPE_V8SF_V8SF_INT:
23993 case V8SF_FTYPE_V8SF_V4SF_INT:
23994 case V4SI_FTYPE_V4SI_V4SI_INT:
23995 case V4DF_FTYPE_V4DF_V4DF_INT:
23996 case V4DF_FTYPE_V4DF_V2DF_INT:
23997 case V4SF_FTYPE_V4SF_V4SF_INT:
23998 case V2DI_FTYPE_V2DI_V2DI_INT:
23999 case V2DF_FTYPE_V2DF_V2DF_INT:
24001 nargs_constant = 1;
24003 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24006 nargs_constant = 1;
24008 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24011 nargs_constant = 1;
24013 case V2DI_FTYPE_V2DI_UINT_UINT:
24015 nargs_constant = 2;
24017 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24019 nargs_constant = 2;
24022 gcc_unreachable ();
24025 gcc_assert (nargs <= ARRAY_SIZE (args));
24027 if (comparison != UNKNOWN)
24029 gcc_assert (nargs == 2);
24030 return ix86_expand_sse_compare (d, exp, target, swap);
24033 if (rmode == VOIDmode || rmode == tmode)
24037 || GET_MODE (target) != tmode
24038 || ! (*insn_p->operand[0].predicate) (target, tmode))
24039 target = gen_reg_rtx (tmode);
24040 real_target = target;
24044 target = gen_reg_rtx (rmode);
24045 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24048 for (i = 0; i < nargs; i++)
24050 tree arg = CALL_EXPR_ARG (exp, i);
24051 rtx op = expand_normal (arg);
24052 enum machine_mode mode = insn_p->operand[i + 1].mode;
24053 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24055 if (last_arg_count && (i + 1) == nargs)
24057 /* SIMD shift insns take either an 8-bit immediate or
24058 register as count. But builtin functions take int as
24059 count. If count doesn't match, we put it in register. */
24062 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24063 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24064 op = copy_to_reg (op);
24067 else if ((nargs - i) <= nargs_constant)
24072 case CODE_FOR_sse4_1_roundpd:
24073 case CODE_FOR_sse4_1_roundps:
24074 case CODE_FOR_sse4_1_roundsd:
24075 case CODE_FOR_sse4_1_roundss:
24076 case CODE_FOR_sse4_1_blendps:
24077 case CODE_FOR_avx_blendpd256:
24078 case CODE_FOR_avx_vpermilv4df:
24079 case CODE_FOR_avx_roundpd256:
24080 case CODE_FOR_avx_roundps256:
24081 error ("the last argument must be a 4-bit immediate");
24084 case CODE_FOR_sse4_1_blendpd:
24085 case CODE_FOR_avx_vpermilv2df:
24086 error ("the last argument must be a 2-bit immediate");
24089 case CODE_FOR_avx_vextractf128v4df:
24090 case CODE_FOR_avx_vextractf128v8sf:
24091 case CODE_FOR_avx_vextractf128v8si:
24092 case CODE_FOR_avx_vinsertf128v4df:
24093 case CODE_FOR_avx_vinsertf128v8sf:
24094 case CODE_FOR_avx_vinsertf128v8si:
24095 error ("the last argument must be a 1-bit immediate");
24098 case CODE_FOR_avx_cmpsdv2df3:
24099 case CODE_FOR_avx_cmpssv4sf3:
24100 case CODE_FOR_avx_cmppdv2df3:
24101 case CODE_FOR_avx_cmppsv4sf3:
24102 case CODE_FOR_avx_cmppdv4df3:
24103 case CODE_FOR_avx_cmppsv8sf3:
24104 error ("the last argument must be a 5-bit immediate");
24108 switch (nargs_constant)
24111 if ((nargs - i) == nargs_constant)
24113 error ("the next to last argument must be an 8-bit immediate");
24117 error ("the last argument must be an 8-bit immediate");
24120 gcc_unreachable ();
24127 if (VECTOR_MODE_P (mode))
24128 op = safe_vector_operand (op, mode);
24130 /* If we aren't optimizing, only allow one memory operand to
24132 if (memory_operand (op, mode))
24135 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24137 if (optimize || !match || num_memory > 1)
24138 op = copy_to_mode_reg (mode, op);
24142 op = copy_to_reg (op);
24143 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24148 args[i].mode = mode;
24154 pat = GEN_FCN (icode) (real_target, args[0].op);
24157 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24160 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24164 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24165 args[2].op, args[3].op);
24168 gcc_unreachable ();
24178 /* Subroutine of ix86_expand_builtin to take care of special insns
24179 with variable number of operands. */
24182 ix86_expand_special_args_builtin (const struct builtin_description *d,
24183 tree exp, rtx target)
24187 unsigned int i, nargs, arg_adjust, memory;
24191 enum machine_mode mode;
24193 enum insn_code icode = d->icode;
24194 bool last_arg_constant = false;
24195 const struct insn_data *insn_p = &insn_data[icode];
24196 enum machine_mode tmode = insn_p->operand[0].mode;
24197 enum { load, store } klass;
24199 switch ((enum ix86_special_builtin_type) d->flag)
24201 case VOID_FTYPE_VOID:
24202 emit_insn (GEN_FCN (icode) (target));
24204 case V2DI_FTYPE_PV2DI:
24205 case V32QI_FTYPE_PCCHAR:
24206 case V16QI_FTYPE_PCCHAR:
24207 case V8SF_FTYPE_PCV4SF:
24208 case V8SF_FTYPE_PCFLOAT:
24209 case V4SF_FTYPE_PCFLOAT:
24210 case V4DF_FTYPE_PCV2DF:
24211 case V4DF_FTYPE_PCDOUBLE:
24212 case V2DF_FTYPE_PCDOUBLE:
24217 case VOID_FTYPE_PV2SF_V4SF:
24218 case VOID_FTYPE_PV2DI_V2DI:
24219 case VOID_FTYPE_PCHAR_V32QI:
24220 case VOID_FTYPE_PCHAR_V16QI:
24221 case VOID_FTYPE_PFLOAT_V8SF:
24222 case VOID_FTYPE_PFLOAT_V4SF:
24223 case VOID_FTYPE_PDOUBLE_V4DF:
24224 case VOID_FTYPE_PDOUBLE_V2DF:
24225 case VOID_FTYPE_PDI_DI:
24226 case VOID_FTYPE_PINT_INT:
24229 /* Reserve memory operand for target. */
24230 memory = ARRAY_SIZE (args);
24232 case V4SF_FTYPE_V4SF_PCV2SF:
24233 case V2DF_FTYPE_V2DF_PCDOUBLE:
24238 case V8SF_FTYPE_PCV8SF_V8SF:
24239 case V4DF_FTYPE_PCV4DF_V4DF:
24240 case V4SF_FTYPE_PCV4SF_V4SF:
24241 case V2DF_FTYPE_PCV2DF_V2DF:
24246 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24247 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24248 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24249 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24252 /* Reserve memory operand for target. */
24253 memory = ARRAY_SIZE (args);
24256 gcc_unreachable ();
24259 gcc_assert (nargs <= ARRAY_SIZE (args));
24261 if (klass == store)
24263 arg = CALL_EXPR_ARG (exp, 0);
24264 op = expand_normal (arg);
24265 gcc_assert (target == 0);
24266 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24274 || GET_MODE (target) != tmode
24275 || ! (*insn_p->operand[0].predicate) (target, tmode))
24276 target = gen_reg_rtx (tmode);
24279 for (i = 0; i < nargs; i++)
24281 enum machine_mode mode = insn_p->operand[i + 1].mode;
24284 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24285 op = expand_normal (arg);
24286 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24288 if (last_arg_constant && (i + 1) == nargs)
24294 error ("the last argument must be an 8-bit immediate");
24302 /* This must be the memory operand. */
24303 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24304 gcc_assert (GET_MODE (op) == mode
24305 || GET_MODE (op) == VOIDmode);
24309 /* This must be register. */
24310 if (VECTOR_MODE_P (mode))
24311 op = safe_vector_operand (op, mode);
24313 gcc_assert (GET_MODE (op) == mode
24314 || GET_MODE (op) == VOIDmode);
24315 op = copy_to_mode_reg (mode, op);
24320 args[i].mode = mode;
24326 pat = GEN_FCN (icode) (target, args[0].op);
24329 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24332 gcc_unreachable ();
24338 return klass == store ? 0 : target;
24341 /* Return the integer constant in ARG. Constrain it to be in the range
24342 of the subparts of VEC_TYPE; issue an error if not. */
24345 get_element_number (tree vec_type, tree arg)
24347 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24349 if (!host_integerp (arg, 1)
24350 || (elt = tree_low_cst (arg, 1), elt > max))
24352 error ("selector must be an integer constant in the range 0..%wi", max);
24359 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24360 ix86_expand_vector_init. We DO have language-level syntax for this, in
24361 the form of (type){ init-list }. Except that since we can't place emms
24362 instructions from inside the compiler, we can't allow the use of MMX
24363 registers unless the user explicitly asks for it. So we do *not* define
24364 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24365 we have builtins invoked by mmintrin.h that gives us license to emit
24366 these sorts of instructions. */
24369 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24371 enum machine_mode tmode = TYPE_MODE (type);
24372 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24373 int i, n_elt = GET_MODE_NUNITS (tmode);
24374 rtvec v = rtvec_alloc (n_elt);
24376 gcc_assert (VECTOR_MODE_P (tmode));
24377 gcc_assert (call_expr_nargs (exp) == n_elt);
24379 for (i = 0; i < n_elt; ++i)
24381 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24382 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24385 if (!target || !register_operand (target, tmode))
24386 target = gen_reg_rtx (tmode);
24388 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24392 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24393 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24394 had a language-level syntax for referencing vector elements. */
24397 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24399 enum machine_mode tmode, mode0;
24404 arg0 = CALL_EXPR_ARG (exp, 0);
24405 arg1 = CALL_EXPR_ARG (exp, 1);
24407 op0 = expand_normal (arg0);
24408 elt = get_element_number (TREE_TYPE (arg0), arg1);
24410 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24411 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24412 gcc_assert (VECTOR_MODE_P (mode0));
24414 op0 = force_reg (mode0, op0);
24416 if (optimize || !target || !register_operand (target, tmode))
24417 target = gen_reg_rtx (tmode);
24419 ix86_expand_vector_extract (true, target, op0, elt);
24424 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24425 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24426 a language-level syntax for referencing vector elements. */
24429 ix86_expand_vec_set_builtin (tree exp)
24431 enum machine_mode tmode, mode1;
24432 tree arg0, arg1, arg2;
24434 rtx op0, op1, target;
24436 arg0 = CALL_EXPR_ARG (exp, 0);
24437 arg1 = CALL_EXPR_ARG (exp, 1);
24438 arg2 = CALL_EXPR_ARG (exp, 2);
24440 tmode = TYPE_MODE (TREE_TYPE (arg0));
24441 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24442 gcc_assert (VECTOR_MODE_P (tmode));
24444 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24445 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24446 elt = get_element_number (TREE_TYPE (arg0), arg2);
24448 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24449 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24451 op0 = force_reg (tmode, op0);
24452 op1 = force_reg (mode1, op1);
24454 /* OP0 is the source of these builtin functions and shouldn't be
24455 modified. Create a copy, use it and return it as target. */
24456 target = gen_reg_rtx (tmode);
24457 emit_move_insn (target, op0);
24458 ix86_expand_vector_set (true, target, op1, elt);
24463 /* Expand an expression EXP that calls a built-in function,
24464 with result going to TARGET if that's convenient
24465 (and in mode MODE if that's convenient).
24466 SUBTARGET may be used as the target for computing one of EXP's operands.
24467 IGNORE is nonzero if the value is to be ignored. */
24470 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24471 enum machine_mode mode ATTRIBUTE_UNUSED,
24472 int ignore ATTRIBUTE_UNUSED)
24474 const struct builtin_description *d;
24476 enum insn_code icode;
24477 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24478 tree arg0, arg1, arg2;
24479 rtx op0, op1, op2, pat;
24480 enum machine_mode mode0, mode1, mode2;
24481 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24483 /* Determine whether the builtin function is available under the current ISA.
24484 Originally the builtin was not created if it wasn't applicable to the
24485 current ISA based on the command line switches. With function specific
24486 options, we need to check in the context of the function making the call
24487 whether it is supported. */
24488 if (ix86_builtins_isa[fcode].isa
24489 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24491 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24492 NULL, NULL, false);
24495 error ("%qE needs unknown isa option", fndecl);
24498 gcc_assert (opts != NULL);
24499 error ("%qE needs isa option %s", fndecl, opts);
24507 case IX86_BUILTIN_MASKMOVQ:
24508 case IX86_BUILTIN_MASKMOVDQU:
24509 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24510 ? CODE_FOR_mmx_maskmovq
24511 : CODE_FOR_sse2_maskmovdqu);
24512 /* Note the arg order is different from the operand order. */
24513 arg1 = CALL_EXPR_ARG (exp, 0);
24514 arg2 = CALL_EXPR_ARG (exp, 1);
24515 arg0 = CALL_EXPR_ARG (exp, 2);
24516 op0 = expand_normal (arg0);
24517 op1 = expand_normal (arg1);
24518 op2 = expand_normal (arg2);
24519 mode0 = insn_data[icode].operand[0].mode;
24520 mode1 = insn_data[icode].operand[1].mode;
24521 mode2 = insn_data[icode].operand[2].mode;
24523 op0 = force_reg (Pmode, op0);
24524 op0 = gen_rtx_MEM (mode1, op0);
24526 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24527 op0 = copy_to_mode_reg (mode0, op0);
24528 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24529 op1 = copy_to_mode_reg (mode1, op1);
24530 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24531 op2 = copy_to_mode_reg (mode2, op2);
24532 pat = GEN_FCN (icode) (op0, op1, op2);
24538 case IX86_BUILTIN_LDMXCSR:
24539 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24540 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24541 emit_move_insn (target, op0);
24542 emit_insn (gen_sse_ldmxcsr (target));
24545 case IX86_BUILTIN_STMXCSR:
24546 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24547 emit_insn (gen_sse_stmxcsr (target));
24548 return copy_to_mode_reg (SImode, target);
24550 case IX86_BUILTIN_CLFLUSH:
24551 arg0 = CALL_EXPR_ARG (exp, 0);
24552 op0 = expand_normal (arg0);
24553 icode = CODE_FOR_sse2_clflush;
24554 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24555 op0 = copy_to_mode_reg (Pmode, op0);
24557 emit_insn (gen_sse2_clflush (op0));
24560 case IX86_BUILTIN_MONITOR:
24561 arg0 = CALL_EXPR_ARG (exp, 0);
24562 arg1 = CALL_EXPR_ARG (exp, 1);
24563 arg2 = CALL_EXPR_ARG (exp, 2);
24564 op0 = expand_normal (arg0);
24565 op1 = expand_normal (arg1);
24566 op2 = expand_normal (arg2);
24568 op0 = copy_to_mode_reg (Pmode, op0);
24570 op1 = copy_to_mode_reg (SImode, op1);
24572 op2 = copy_to_mode_reg (SImode, op2);
24573 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24576 case IX86_BUILTIN_MWAIT:
24577 arg0 = CALL_EXPR_ARG (exp, 0);
24578 arg1 = CALL_EXPR_ARG (exp, 1);
24579 op0 = expand_normal (arg0);
24580 op1 = expand_normal (arg1);
24582 op0 = copy_to_mode_reg (SImode, op0);
24584 op1 = copy_to_mode_reg (SImode, op1);
24585 emit_insn (gen_sse3_mwait (op0, op1));
24588 case IX86_BUILTIN_VEC_INIT_V2SI:
24589 case IX86_BUILTIN_VEC_INIT_V4HI:
24590 case IX86_BUILTIN_VEC_INIT_V8QI:
24591 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24593 case IX86_BUILTIN_VEC_EXT_V2DF:
24594 case IX86_BUILTIN_VEC_EXT_V2DI:
24595 case IX86_BUILTIN_VEC_EXT_V4SF:
24596 case IX86_BUILTIN_VEC_EXT_V4SI:
24597 case IX86_BUILTIN_VEC_EXT_V8HI:
24598 case IX86_BUILTIN_VEC_EXT_V2SI:
24599 case IX86_BUILTIN_VEC_EXT_V4HI:
24600 case IX86_BUILTIN_VEC_EXT_V16QI:
24601 return ix86_expand_vec_ext_builtin (exp, target);
24603 case IX86_BUILTIN_VEC_SET_V2DI:
24604 case IX86_BUILTIN_VEC_SET_V4SF:
24605 case IX86_BUILTIN_VEC_SET_V4SI:
24606 case IX86_BUILTIN_VEC_SET_V8HI:
24607 case IX86_BUILTIN_VEC_SET_V4HI:
24608 case IX86_BUILTIN_VEC_SET_V16QI:
24609 return ix86_expand_vec_set_builtin (exp);
24611 case IX86_BUILTIN_INFQ:
24613 REAL_VALUE_TYPE inf;
24617 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24619 tmp = validize_mem (force_const_mem (mode, tmp));
24622 target = gen_reg_rtx (mode);
24624 emit_move_insn (target, tmp);
24632 for (i = 0, d = bdesc_special_args;
24633 i < ARRAY_SIZE (bdesc_special_args);
24635 if (d->code == fcode)
24636 return ix86_expand_special_args_builtin (d, exp, target);
24638 for (i = 0, d = bdesc_args;
24639 i < ARRAY_SIZE (bdesc_args);
24641 if (d->code == fcode)
24644 case IX86_BUILTIN_FABSQ:
24645 case IX86_BUILTIN_COPYSIGNQ:
24647 /* Emit a normal call if SSE2 isn't available. */
24648 return expand_call (exp, target, ignore);
24650 return ix86_expand_args_builtin (d, exp, target);
24653 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24654 if (d->code == fcode)
24655 return ix86_expand_sse_comi (d, exp, target);
24657 for (i = 0, d = bdesc_pcmpestr;
24658 i < ARRAY_SIZE (bdesc_pcmpestr);
24660 if (d->code == fcode)
24661 return ix86_expand_sse_pcmpestr (d, exp, target);
24663 for (i = 0, d = bdesc_pcmpistr;
24664 i < ARRAY_SIZE (bdesc_pcmpistr);
24666 if (d->code == fcode)
24667 return ix86_expand_sse_pcmpistr (d, exp, target);
24669 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24670 if (d->code == fcode)
24671 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24672 (enum multi_arg_type)d->flag,
24675 gcc_unreachable ();
24678 /* Returns a function decl for a vectorized version of the builtin function
24679 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24680 if it is not available. */
24683 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24686 enum machine_mode in_mode, out_mode;
24689 if (TREE_CODE (type_out) != VECTOR_TYPE
24690 || TREE_CODE (type_in) != VECTOR_TYPE)
24693 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24694 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24695 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24696 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24700 case BUILT_IN_SQRT:
24701 if (out_mode == DFmode && out_n == 2
24702 && in_mode == DFmode && in_n == 2)
24703 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24706 case BUILT_IN_SQRTF:
24707 if (out_mode == SFmode && out_n == 4
24708 && in_mode == SFmode && in_n == 4)
24709 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24712 case BUILT_IN_LRINT:
24713 if (out_mode == SImode && out_n == 4
24714 && in_mode == DFmode && in_n == 2)
24715 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24718 case BUILT_IN_LRINTF:
24719 if (out_mode == SImode && out_n == 4
24720 && in_mode == SFmode && in_n == 4)
24721 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24728 /* Dispatch to a handler for a vectorization library. */
24729 if (ix86_veclib_handler)
24730 return (*ix86_veclib_handler)(fn, type_out, type_in);
24735 /* Handler for an SVML-style interface to
24736 a library with vectorized intrinsics. */
24739 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24742 tree fntype, new_fndecl, args;
24745 enum machine_mode el_mode, in_mode;
24748 /* The SVML is suitable for unsafe math only. */
24749 if (!flag_unsafe_math_optimizations)
24752 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24753 n = TYPE_VECTOR_SUBPARTS (type_out);
24754 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24755 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24756 if (el_mode != in_mode
24764 case BUILT_IN_LOG10:
24766 case BUILT_IN_TANH:
24768 case BUILT_IN_ATAN:
24769 case BUILT_IN_ATAN2:
24770 case BUILT_IN_ATANH:
24771 case BUILT_IN_CBRT:
24772 case BUILT_IN_SINH:
24774 case BUILT_IN_ASINH:
24775 case BUILT_IN_ASIN:
24776 case BUILT_IN_COSH:
24778 case BUILT_IN_ACOSH:
24779 case BUILT_IN_ACOS:
24780 if (el_mode != DFmode || n != 2)
24784 case BUILT_IN_EXPF:
24785 case BUILT_IN_LOGF:
24786 case BUILT_IN_LOG10F:
24787 case BUILT_IN_POWF:
24788 case BUILT_IN_TANHF:
24789 case BUILT_IN_TANF:
24790 case BUILT_IN_ATANF:
24791 case BUILT_IN_ATAN2F:
24792 case BUILT_IN_ATANHF:
24793 case BUILT_IN_CBRTF:
24794 case BUILT_IN_SINHF:
24795 case BUILT_IN_SINF:
24796 case BUILT_IN_ASINHF:
24797 case BUILT_IN_ASINF:
24798 case BUILT_IN_COSHF:
24799 case BUILT_IN_COSF:
24800 case BUILT_IN_ACOSHF:
24801 case BUILT_IN_ACOSF:
24802 if (el_mode != SFmode || n != 4)
24810 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24812 if (fn == BUILT_IN_LOGF)
24813 strcpy (name, "vmlsLn4");
24814 else if (fn == BUILT_IN_LOG)
24815 strcpy (name, "vmldLn2");
24818 sprintf (name, "vmls%s", bname+10);
24819 name[strlen (name)-1] = '4';
24822 sprintf (name, "vmld%s2", bname+10);
24824 /* Convert to uppercase. */
24828 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24829 args = TREE_CHAIN (args))
24833 fntype = build_function_type_list (type_out, type_in, NULL);
24835 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24837 /* Build a function declaration for the vectorized function. */
24838 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
24839 TREE_PUBLIC (new_fndecl) = 1;
24840 DECL_EXTERNAL (new_fndecl) = 1;
24841 DECL_IS_NOVOPS (new_fndecl) = 1;
24842 TREE_READONLY (new_fndecl) = 1;
24847 /* Handler for an ACML-style interface to
24848 a library with vectorized intrinsics. */
24851 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
24853 char name[20] = "__vr.._";
24854 tree fntype, new_fndecl, args;
24857 enum machine_mode el_mode, in_mode;
24860 /* The ACML is 64bits only and suitable for unsafe math only as
24861 it does not correctly support parts of IEEE with the required
24862 precision such as denormals. */
24864 || !flag_unsafe_math_optimizations)
24867 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24868 n = TYPE_VECTOR_SUBPARTS (type_out);
24869 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24870 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24871 if (el_mode != in_mode
24881 case BUILT_IN_LOG2:
24882 case BUILT_IN_LOG10:
24885 if (el_mode != DFmode
24890 case BUILT_IN_SINF:
24891 case BUILT_IN_COSF:
24892 case BUILT_IN_EXPF:
24893 case BUILT_IN_POWF:
24894 case BUILT_IN_LOGF:
24895 case BUILT_IN_LOG2F:
24896 case BUILT_IN_LOG10F:
24899 if (el_mode != SFmode
24908 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24909 sprintf (name + 7, "%s", bname+10);
24912 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24913 args = TREE_CHAIN (args))
24917 fntype = build_function_type_list (type_out, type_in, NULL);
24919 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24921 /* Build a function declaration for the vectorized function. */
24922 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
24923 TREE_PUBLIC (new_fndecl) = 1;
24924 DECL_EXTERNAL (new_fndecl) = 1;
24925 DECL_IS_NOVOPS (new_fndecl) = 1;
24926 TREE_READONLY (new_fndecl) = 1;
24932 /* Returns a decl of a function that implements conversion of an integer vector
24933 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24934 side of the conversion.
24935 Return NULL_TREE if it is not available. */
24938 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
24940 if (TREE_CODE (type) != VECTOR_TYPE)
24946 switch (TYPE_MODE (type))
24949 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
24954 case FIX_TRUNC_EXPR:
24955 switch (TYPE_MODE (type))
24958 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
24968 /* Returns a code for a target-specific builtin that implements
24969 reciprocal of the function, or NULL_TREE if not available. */
24972 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
24973 bool sqrt ATTRIBUTE_UNUSED)
24975 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
24976 && flag_finite_math_only && !flag_trapping_math
24977 && flag_unsafe_math_optimizations))
24981 /* Machine dependent builtins. */
24984 /* Vectorized version of sqrt to rsqrt conversion. */
24985 case IX86_BUILTIN_SQRTPS_NR:
24986 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
24992 /* Normal builtins. */
24995 /* Sqrt to rsqrt conversion. */
24996 case BUILT_IN_SQRTF:
24997 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25004 /* Store OPERAND to the memory after reload is completed. This means
25005 that we can't easily use assign_stack_local. */
25007 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25011 gcc_assert (reload_completed);
25012 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25014 result = gen_rtx_MEM (mode,
25015 gen_rtx_PLUS (Pmode,
25017 GEN_INT (-RED_ZONE_SIZE)));
25018 emit_move_insn (result, operand);
25020 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25026 operand = gen_lowpart (DImode, operand);
25030 gen_rtx_SET (VOIDmode,
25031 gen_rtx_MEM (DImode,
25032 gen_rtx_PRE_DEC (DImode,
25033 stack_pointer_rtx)),
25037 gcc_unreachable ();
25039 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25048 split_di (&operand, 1, operands, operands + 1);
25050 gen_rtx_SET (VOIDmode,
25051 gen_rtx_MEM (SImode,
25052 gen_rtx_PRE_DEC (Pmode,
25053 stack_pointer_rtx)),
25056 gen_rtx_SET (VOIDmode,
25057 gen_rtx_MEM (SImode,
25058 gen_rtx_PRE_DEC (Pmode,
25059 stack_pointer_rtx)),
25064 /* Store HImodes as SImodes. */
25065 operand = gen_lowpart (SImode, operand);
25069 gen_rtx_SET (VOIDmode,
25070 gen_rtx_MEM (GET_MODE (operand),
25071 gen_rtx_PRE_DEC (SImode,
25072 stack_pointer_rtx)),
25076 gcc_unreachable ();
25078 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25083 /* Free operand from the memory. */
25085 ix86_free_from_memory (enum machine_mode mode)
25087 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25091 if (mode == DImode || TARGET_64BIT)
25095 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25096 to pop or add instruction if registers are available. */
25097 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25098 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25103 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25104 QImode must go into class Q_REGS.
25105 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25106 movdf to do mem-to-mem moves through integer regs. */
25108 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25110 enum machine_mode mode = GET_MODE (x);
25112 /* We're only allowed to return a subclass of CLASS. Many of the
25113 following checks fail for NO_REGS, so eliminate that early. */
25114 if (regclass == NO_REGS)
25117 /* All classes can load zeros. */
25118 if (x == CONST0_RTX (mode))
25121 /* Force constants into memory if we are loading a (nonzero) constant into
25122 an MMX or SSE register. This is because there are no MMX/SSE instructions
25123 to load from a constant. */
25125 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25128 /* Prefer SSE regs only, if we can use them for math. */
25129 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25130 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25132 /* Floating-point constants need more complex checks. */
25133 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25135 /* General regs can load everything. */
25136 if (reg_class_subset_p (regclass, GENERAL_REGS))
25139 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25140 zero above. We only want to wind up preferring 80387 registers if
25141 we plan on doing computation with them. */
25143 && standard_80387_constant_p (x))
25145 /* Limit class to non-sse. */
25146 if (regclass == FLOAT_SSE_REGS)
25148 if (regclass == FP_TOP_SSE_REGS)
25150 if (regclass == FP_SECOND_SSE_REGS)
25151 return FP_SECOND_REG;
25152 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25159 /* Generally when we see PLUS here, it's the function invariant
25160 (plus soft-fp const_int). Which can only be computed into general
25162 if (GET_CODE (x) == PLUS)
25163 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25165 /* QImode constants are easy to load, but non-constant QImode data
25166 must go into Q_REGS. */
25167 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25169 if (reg_class_subset_p (regclass, Q_REGS))
25171 if (reg_class_subset_p (Q_REGS, regclass))
25179 /* Discourage putting floating-point values in SSE registers unless
25180 SSE math is being used, and likewise for the 387 registers. */
25182 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25184 enum machine_mode mode = GET_MODE (x);
25186 /* Restrict the output reload class to the register bank that we are doing
25187 math on. If we would like not to return a subset of CLASS, reject this
25188 alternative: if reload cannot do this, it will still use its choice. */
25189 mode = GET_MODE (x);
25190 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25191 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25193 if (X87_FLOAT_MODE_P (mode))
25195 if (regclass == FP_TOP_SSE_REGS)
25197 else if (regclass == FP_SECOND_SSE_REGS)
25198 return FP_SECOND_REG;
25200 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25206 static enum reg_class
25207 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25208 enum machine_mode mode,
25209 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25211 /* QImode spills from non-QI registers require
25212 intermediate register on 32bit targets. */
25213 if (!in_p && mode == QImode && !TARGET_64BIT
25214 && (rclass == GENERAL_REGS
25215 || rclass == LEGACY_REGS
25216 || rclass == INDEX_REGS))
25225 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25226 regno = true_regnum (x);
25228 /* Return Q_REGS if the operand is in memory. */
25236 /* If we are copying between general and FP registers, we need a memory
25237 location. The same is true for SSE and MMX registers.
25239 To optimize register_move_cost performance, allow inline variant.
25241 The macro can't work reliably when one of the CLASSES is class containing
25242 registers from multiple units (SSE, MMX, integer). We avoid this by never
25243 combining those units in single alternative in the machine description.
25244 Ensure that this constraint holds to avoid unexpected surprises.
25246 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25247 enforce these sanity checks. */
25250 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25251 enum machine_mode mode, int strict)
25253 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25254 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25255 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25256 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25257 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25258 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25260 gcc_assert (!strict);
25264 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25267 /* ??? This is a lie. We do have moves between mmx/general, and for
25268 mmx/sse2. But by saying we need secondary memory we discourage the
25269 register allocator from using the mmx registers unless needed. */
25270 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25273 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25275 /* SSE1 doesn't have any direct moves from other classes. */
25279 /* If the target says that inter-unit moves are more expensive
25280 than moving through memory, then don't generate them. */
25281 if (!TARGET_INTER_UNIT_MOVES)
25284 /* Between SSE and general, we have moves no larger than word size. */
25285 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25293 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25294 enum machine_mode mode, int strict)
25296 return inline_secondary_memory_needed (class1, class2, mode, strict);
25299 /* Return true if the registers in CLASS cannot represent the change from
25300 modes FROM to TO. */
25303 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25304 enum reg_class regclass)
25309 /* x87 registers can't do subreg at all, as all values are reformatted
25310 to extended precision. */
25311 if (MAYBE_FLOAT_CLASS_P (regclass))
25314 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25316 /* Vector registers do not support QI or HImode loads. If we don't
25317 disallow a change to these modes, reload will assume it's ok to
25318 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25319 the vec_dupv4hi pattern. */
25320 if (GET_MODE_SIZE (from) < 4)
25323 /* Vector registers do not support subreg with nonzero offsets, which
25324 are otherwise valid for integer registers. Since we can't see
25325 whether we have a nonzero offset from here, prohibit all
25326 nonparadoxical subregs changing size. */
25327 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25334 /* Return the cost of moving data of mode M between a
25335 register and memory. A value of 2 is the default; this cost is
25336 relative to those in `REGISTER_MOVE_COST'.
25338 This function is used extensively by register_move_cost that is used to
25339 build tables at startup. Make it inline in this case.
25340 When IN is 2, return maximum of in and out move cost.
25342 If moving between registers and memory is more expensive than
25343 between two registers, you should define this macro to express the
25346 Model also increased moving costs of QImode registers in non
25350 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25354 if (FLOAT_CLASS_P (regclass))
25372 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25373 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25375 if (SSE_CLASS_P (regclass))
25378 switch (GET_MODE_SIZE (mode))
25393 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25394 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25396 if (MMX_CLASS_P (regclass))
25399 switch (GET_MODE_SIZE (mode))
25411 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25412 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25414 switch (GET_MODE_SIZE (mode))
25417 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25420 return ix86_cost->int_store[0];
25421 if (TARGET_PARTIAL_REG_DEPENDENCY
25422 && optimize_function_for_speed_p (cfun))
25423 cost = ix86_cost->movzbl_load;
25425 cost = ix86_cost->int_load[0];
25427 return MAX (cost, ix86_cost->int_store[0]);
25433 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25435 return ix86_cost->movzbl_load;
25437 return ix86_cost->int_store[0] + 4;
25442 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25443 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25445 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25446 if (mode == TFmode)
25449 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25451 cost = ix86_cost->int_load[2];
25453 cost = ix86_cost->int_store[2];
25454 return (cost * (((int) GET_MODE_SIZE (mode)
25455 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25460 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25462 return inline_memory_move_cost (mode, regclass, in);
25466 /* Return the cost of moving data from a register in class CLASS1 to
25467 one in class CLASS2.
25469 It is not required that the cost always equal 2 when FROM is the same as TO;
25470 on some machines it is expensive to move between registers if they are not
25471 general registers. */
25474 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25475 enum reg_class class2)
25477 /* In case we require secondary memory, compute cost of the store followed
25478 by load. In order to avoid bad register allocation choices, we need
25479 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25481 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25485 cost += inline_memory_move_cost (mode, class1, 2);
25486 cost += inline_memory_move_cost (mode, class2, 2);
25488 /* In case of copying from general_purpose_register we may emit multiple
25489 stores followed by single load causing memory size mismatch stall.
25490 Count this as arbitrarily high cost of 20. */
25491 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25494 /* In the case of FP/MMX moves, the registers actually overlap, and we
25495 have to switch modes in order to treat them differently. */
25496 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25497 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25503 /* Moves between SSE/MMX and integer unit are expensive. */
25504 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25505 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25507 /* ??? By keeping returned value relatively high, we limit the number
25508 of moves between integer and MMX/SSE registers for all targets.
25509 Additionally, high value prevents problem with x86_modes_tieable_p(),
25510 where integer modes in MMX/SSE registers are not tieable
25511 because of missing QImode and HImode moves to, from or between
25512 MMX/SSE registers. */
25513 return MAX (8, ix86_cost->mmxsse_to_integer);
25515 if (MAYBE_FLOAT_CLASS_P (class1))
25516 return ix86_cost->fp_move;
25517 if (MAYBE_SSE_CLASS_P (class1))
25518 return ix86_cost->sse_move;
25519 if (MAYBE_MMX_CLASS_P (class1))
25520 return ix86_cost->mmx_move;
25524 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25527 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25529 /* Flags and only flags can only hold CCmode values. */
25530 if (CC_REGNO_P (regno))
25531 return GET_MODE_CLASS (mode) == MODE_CC;
25532 if (GET_MODE_CLASS (mode) == MODE_CC
25533 || GET_MODE_CLASS (mode) == MODE_RANDOM
25534 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25536 if (FP_REGNO_P (regno))
25537 return VALID_FP_MODE_P (mode);
25538 if (SSE_REGNO_P (regno))
25540 /* We implement the move patterns for all vector modes into and
25541 out of SSE registers, even when no operation instructions
25542 are available. OImode move is available only when AVX is
25544 return ((TARGET_AVX && mode == OImode)
25545 || VALID_AVX256_REG_MODE (mode)
25546 || VALID_SSE_REG_MODE (mode)
25547 || VALID_SSE2_REG_MODE (mode)
25548 || VALID_MMX_REG_MODE (mode)
25549 || VALID_MMX_REG_MODE_3DNOW (mode));
25551 if (MMX_REGNO_P (regno))
25553 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25554 so if the register is available at all, then we can move data of
25555 the given mode into or out of it. */
25556 return (VALID_MMX_REG_MODE (mode)
25557 || VALID_MMX_REG_MODE_3DNOW (mode));
25560 if (mode == QImode)
25562 /* Take care for QImode values - they can be in non-QI regs,
25563 but then they do cause partial register stalls. */
25564 if (regno < 4 || TARGET_64BIT)
25566 if (!TARGET_PARTIAL_REG_STALL)
25568 return reload_in_progress || reload_completed;
25570 /* We handle both integer and floats in the general purpose registers. */
25571 else if (VALID_INT_MODE_P (mode))
25573 else if (VALID_FP_MODE_P (mode))
25575 else if (VALID_DFP_MODE_P (mode))
25577 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25578 on to use that value in smaller contexts, this can easily force a
25579 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25580 supporting DImode, allow it. */
25581 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25587 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25588 tieable integer mode. */
25591 ix86_tieable_integer_mode_p (enum machine_mode mode)
25600 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25603 return TARGET_64BIT;
25610 /* Return true if MODE1 is accessible in a register that can hold MODE2
25611 without copying. That is, all register classes that can hold MODE2
25612 can also hold MODE1. */
25615 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25617 if (mode1 == mode2)
25620 if (ix86_tieable_integer_mode_p (mode1)
25621 && ix86_tieable_integer_mode_p (mode2))
25624 /* MODE2 being XFmode implies fp stack or general regs, which means we
25625 can tie any smaller floating point modes to it. Note that we do not
25626 tie this with TFmode. */
25627 if (mode2 == XFmode)
25628 return mode1 == SFmode || mode1 == DFmode;
25630 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25631 that we can tie it with SFmode. */
25632 if (mode2 == DFmode)
25633 return mode1 == SFmode;
25635 /* If MODE2 is only appropriate for an SSE register, then tie with
25636 any other mode acceptable to SSE registers. */
25637 if (GET_MODE_SIZE (mode2) == 16
25638 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25639 return (GET_MODE_SIZE (mode1) == 16
25640 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25642 /* If MODE2 is appropriate for an MMX register, then tie
25643 with any other mode acceptable to MMX registers. */
25644 if (GET_MODE_SIZE (mode2) == 8
25645 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25646 return (GET_MODE_SIZE (mode1) == 8
25647 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25652 /* Compute a (partial) cost for rtx X. Return true if the complete
25653 cost has been computed, and false if subexpressions should be
25654 scanned. In either case, *TOTAL contains the cost result. */
25657 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25659 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25660 enum machine_mode mode = GET_MODE (x);
25661 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25669 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25671 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25673 else if (flag_pic && SYMBOLIC_CONST (x)
25675 || (!GET_CODE (x) != LABEL_REF
25676 && (GET_CODE (x) != SYMBOL_REF
25677 || !SYMBOL_REF_LOCAL_P (x)))))
25684 if (mode == VOIDmode)
25687 switch (standard_80387_constant_p (x))
25692 default: /* Other constants */
25697 /* Start with (MEM (SYMBOL_REF)), since that's where
25698 it'll probably end up. Add a penalty for size. */
25699 *total = (COSTS_N_INSNS (1)
25700 + (flag_pic != 0 && !TARGET_64BIT)
25701 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25707 /* The zero extensions is often completely free on x86_64, so make
25708 it as cheap as possible. */
25709 if (TARGET_64BIT && mode == DImode
25710 && GET_MODE (XEXP (x, 0)) == SImode)
25712 else if (TARGET_ZERO_EXTEND_WITH_AND)
25713 *total = cost->add;
25715 *total = cost->movzx;
25719 *total = cost->movsx;
25723 if (CONST_INT_P (XEXP (x, 1))
25724 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25726 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25729 *total = cost->add;
25732 if ((value == 2 || value == 3)
25733 && cost->lea <= cost->shift_const)
25735 *total = cost->lea;
25745 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25747 if (CONST_INT_P (XEXP (x, 1)))
25749 if (INTVAL (XEXP (x, 1)) > 32)
25750 *total = cost->shift_const + COSTS_N_INSNS (2);
25752 *total = cost->shift_const * 2;
25756 if (GET_CODE (XEXP (x, 1)) == AND)
25757 *total = cost->shift_var * 2;
25759 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25764 if (CONST_INT_P (XEXP (x, 1)))
25765 *total = cost->shift_const;
25767 *total = cost->shift_var;
25772 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25774 /* ??? SSE scalar cost should be used here. */
25775 *total = cost->fmul;
25778 else if (X87_FLOAT_MODE_P (mode))
25780 *total = cost->fmul;
25783 else if (FLOAT_MODE_P (mode))
25785 /* ??? SSE vector cost should be used here. */
25786 *total = cost->fmul;
25791 rtx op0 = XEXP (x, 0);
25792 rtx op1 = XEXP (x, 1);
25794 if (CONST_INT_P (XEXP (x, 1)))
25796 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25797 for (nbits = 0; value != 0; value &= value - 1)
25801 /* This is arbitrary. */
25804 /* Compute costs correctly for widening multiplication. */
25805 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
25806 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
25807 == GET_MODE_SIZE (mode))
25809 int is_mulwiden = 0;
25810 enum machine_mode inner_mode = GET_MODE (op0);
25812 if (GET_CODE (op0) == GET_CODE (op1))
25813 is_mulwiden = 1, op1 = XEXP (op1, 0);
25814 else if (CONST_INT_P (op1))
25816 if (GET_CODE (op0) == SIGN_EXTEND)
25817 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
25820 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
25824 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
25827 *total = (cost->mult_init[MODE_INDEX (mode)]
25828 + nbits * cost->mult_bit
25829 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
25838 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25839 /* ??? SSE cost should be used here. */
25840 *total = cost->fdiv;
25841 else if (X87_FLOAT_MODE_P (mode))
25842 *total = cost->fdiv;
25843 else if (FLOAT_MODE_P (mode))
25844 /* ??? SSE vector cost should be used here. */
25845 *total = cost->fdiv;
25847 *total = cost->divide[MODE_INDEX (mode)];
25851 if (GET_MODE_CLASS (mode) == MODE_INT
25852 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
25854 if (GET_CODE (XEXP (x, 0)) == PLUS
25855 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
25856 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
25857 && CONSTANT_P (XEXP (x, 1)))
25859 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
25860 if (val == 2 || val == 4 || val == 8)
25862 *total = cost->lea;
25863 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25864 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
25865 outer_code, speed);
25866 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25870 else if (GET_CODE (XEXP (x, 0)) == MULT
25871 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
25873 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
25874 if (val == 2 || val == 4 || val == 8)
25876 *total = cost->lea;
25877 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25878 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25882 else if (GET_CODE (XEXP (x, 0)) == PLUS)
25884 *total = cost->lea;
25885 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25886 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25887 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25894 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25896 /* ??? SSE cost should be used here. */
25897 *total = cost->fadd;
25900 else if (X87_FLOAT_MODE_P (mode))
25902 *total = cost->fadd;
25905 else if (FLOAT_MODE_P (mode))
25907 /* ??? SSE vector cost should be used here. */
25908 *total = cost->fadd;
25916 if (!TARGET_64BIT && mode == DImode)
25918 *total = (cost->add * 2
25919 + (rtx_cost (XEXP (x, 0), outer_code, speed)
25920 << (GET_MODE (XEXP (x, 0)) != DImode))
25921 + (rtx_cost (XEXP (x, 1), outer_code, speed)
25922 << (GET_MODE (XEXP (x, 1)) != DImode)));
25928 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25930 /* ??? SSE cost should be used here. */
25931 *total = cost->fchs;
25934 else if (X87_FLOAT_MODE_P (mode))
25936 *total = cost->fchs;
25939 else if (FLOAT_MODE_P (mode))
25941 /* ??? SSE vector cost should be used here. */
25942 *total = cost->fchs;
25948 if (!TARGET_64BIT && mode == DImode)
25949 *total = cost->add * 2;
25951 *total = cost->add;
25955 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
25956 && XEXP (XEXP (x, 0), 1) == const1_rtx
25957 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
25958 && XEXP (x, 1) == const0_rtx)
25960 /* This kind of construct is implemented using test[bwl].
25961 Treat it as if we had an AND. */
25962 *total = (cost->add
25963 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
25964 + rtx_cost (const1_rtx, outer_code, speed));
25970 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
25975 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25976 /* ??? SSE cost should be used here. */
25977 *total = cost->fabs;
25978 else if (X87_FLOAT_MODE_P (mode))
25979 *total = cost->fabs;
25980 else if (FLOAT_MODE_P (mode))
25981 /* ??? SSE vector cost should be used here. */
25982 *total = cost->fabs;
25986 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25987 /* ??? SSE cost should be used here. */
25988 *total = cost->fsqrt;
25989 else if (X87_FLOAT_MODE_P (mode))
25990 *total = cost->fsqrt;
25991 else if (FLOAT_MODE_P (mode))
25992 /* ??? SSE vector cost should be used here. */
25993 *total = cost->fsqrt;
25997 if (XINT (x, 1) == UNSPEC_TP)
26008 static int current_machopic_label_num;
26010 /* Given a symbol name and its associated stub, write out the
26011 definition of the stub. */
26014 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26016 unsigned int length;
26017 char *binder_name, *symbol_name, lazy_ptr_name[32];
26018 int label = ++current_machopic_label_num;
26020 /* For 64-bit we shouldn't get here. */
26021 gcc_assert (!TARGET_64BIT);
26023 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26024 symb = (*targetm.strip_name_encoding) (symb);
26026 length = strlen (stub);
26027 binder_name = XALLOCAVEC (char, length + 32);
26028 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26030 length = strlen (symb);
26031 symbol_name = XALLOCAVEC (char, length + 32);
26032 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26034 sprintf (lazy_ptr_name, "L%d$lz", label);
26037 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26039 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26041 fprintf (file, "%s:\n", stub);
26042 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26046 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26047 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26048 fprintf (file, "\tjmp\t*%%edx\n");
26051 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26053 fprintf (file, "%s:\n", binder_name);
26057 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26058 fprintf (file, "\tpushl\t%%eax\n");
26061 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26063 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26065 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26066 fprintf (file, "%s:\n", lazy_ptr_name);
26067 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26068 fprintf (file, "\t.long %s\n", binder_name);
26072 darwin_x86_file_end (void)
26074 darwin_file_end ();
26077 #endif /* TARGET_MACHO */
26079 /* Order the registers for register allocator. */
26082 x86_order_regs_for_local_alloc (void)
26087 /* First allocate the local general purpose registers. */
26088 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26089 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26090 reg_alloc_order [pos++] = i;
26092 /* Global general purpose registers. */
26093 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26094 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26095 reg_alloc_order [pos++] = i;
26097 /* x87 registers come first in case we are doing FP math
26099 if (!TARGET_SSE_MATH)
26100 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26101 reg_alloc_order [pos++] = i;
26103 /* SSE registers. */
26104 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26105 reg_alloc_order [pos++] = i;
26106 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26107 reg_alloc_order [pos++] = i;
26109 /* x87 registers. */
26110 if (TARGET_SSE_MATH)
26111 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26112 reg_alloc_order [pos++] = i;
26114 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26115 reg_alloc_order [pos++] = i;
26117 /* Initialize the rest of array as we do not allocate some registers
26119 while (pos < FIRST_PSEUDO_REGISTER)
26120 reg_alloc_order [pos++] = 0;
26123 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26124 struct attribute_spec.handler. */
26126 ix86_handle_abi_attribute (tree *node, tree name,
26127 tree args ATTRIBUTE_UNUSED,
26128 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26130 if (TREE_CODE (*node) != FUNCTION_TYPE
26131 && TREE_CODE (*node) != METHOD_TYPE
26132 && TREE_CODE (*node) != FIELD_DECL
26133 && TREE_CODE (*node) != TYPE_DECL)
26135 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26136 IDENTIFIER_POINTER (name));
26137 *no_add_attrs = true;
26142 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26143 IDENTIFIER_POINTER (name));
26144 *no_add_attrs = true;
26148 /* Can combine regparm with all attributes but fastcall. */
26149 if (is_attribute_p ("ms_abi", name))
26151 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26153 error ("ms_abi and sysv_abi attributes are not compatible");
26158 else if (is_attribute_p ("sysv_abi", name))
26160 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26162 error ("ms_abi and sysv_abi attributes are not compatible");
26171 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26172 struct attribute_spec.handler. */
26174 ix86_handle_struct_attribute (tree *node, tree name,
26175 tree args ATTRIBUTE_UNUSED,
26176 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26179 if (DECL_P (*node))
26181 if (TREE_CODE (*node) == TYPE_DECL)
26182 type = &TREE_TYPE (*node);
26187 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26188 || TREE_CODE (*type) == UNION_TYPE)))
26190 warning (OPT_Wattributes, "%qs attribute ignored",
26191 IDENTIFIER_POINTER (name));
26192 *no_add_attrs = true;
26195 else if ((is_attribute_p ("ms_struct", name)
26196 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26197 || ((is_attribute_p ("gcc_struct", name)
26198 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26200 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26201 IDENTIFIER_POINTER (name));
26202 *no_add_attrs = true;
26209 ix86_ms_bitfield_layout_p (const_tree record_type)
26211 return (TARGET_MS_BITFIELD_LAYOUT &&
26212 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26213 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26216 /* Returns an expression indicating where the this parameter is
26217 located on entry to the FUNCTION. */
26220 x86_this_parameter (tree function)
26222 tree type = TREE_TYPE (function);
26223 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26228 const int *parm_regs;
26230 if (ix86_function_type_abi (type) == MS_ABI)
26231 parm_regs = x86_64_ms_abi_int_parameter_registers;
26233 parm_regs = x86_64_int_parameter_registers;
26234 return gen_rtx_REG (DImode, parm_regs[aggr]);
26237 nregs = ix86_function_regparm (type, function);
26239 if (nregs > 0 && !stdarg_p (type))
26243 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26244 regno = aggr ? DX_REG : CX_REG;
26252 return gen_rtx_MEM (SImode,
26253 plus_constant (stack_pointer_rtx, 4));
26256 return gen_rtx_REG (SImode, regno);
26259 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26262 /* Determine whether x86_output_mi_thunk can succeed. */
26265 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26266 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26267 HOST_WIDE_INT vcall_offset, const_tree function)
26269 /* 64-bit can handle anything. */
26273 /* For 32-bit, everything's fine if we have one free register. */
26274 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26277 /* Need a free register for vcall_offset. */
26281 /* Need a free register for GOT references. */
26282 if (flag_pic && !(*targetm.binds_local_p) (function))
26285 /* Otherwise ok. */
26289 /* Output the assembler code for a thunk function. THUNK_DECL is the
26290 declaration for the thunk function itself, FUNCTION is the decl for
26291 the target function. DELTA is an immediate constant offset to be
26292 added to THIS. If VCALL_OFFSET is nonzero, the word at
26293 *(*this + vcall_offset) should be added to THIS. */
26296 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26297 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26298 HOST_WIDE_INT vcall_offset, tree function)
26301 rtx this_param = x86_this_parameter (function);
26304 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26305 pull it in now and let DELTA benefit. */
26306 if (REG_P (this_param))
26307 this_reg = this_param;
26308 else if (vcall_offset)
26310 /* Put the this parameter into %eax. */
26311 xops[0] = this_param;
26312 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26313 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26316 this_reg = NULL_RTX;
26318 /* Adjust the this parameter by a fixed constant. */
26321 xops[0] = GEN_INT (delta);
26322 xops[1] = this_reg ? this_reg : this_param;
26325 if (!x86_64_general_operand (xops[0], DImode))
26327 tmp = gen_rtx_REG (DImode, R10_REG);
26329 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26331 xops[1] = this_param;
26333 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26336 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26339 /* Adjust the this parameter by a value stored in the vtable. */
26343 tmp = gen_rtx_REG (DImode, R10_REG);
26346 int tmp_regno = CX_REG;
26347 if (lookup_attribute ("fastcall",
26348 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26349 tmp_regno = AX_REG;
26350 tmp = gen_rtx_REG (SImode, tmp_regno);
26353 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26355 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26357 /* Adjust the this parameter. */
26358 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26359 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26361 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26362 xops[0] = GEN_INT (vcall_offset);
26364 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26365 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26367 xops[1] = this_reg;
26368 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26371 /* If necessary, drop THIS back to its stack slot. */
26372 if (this_reg && this_reg != this_param)
26374 xops[0] = this_reg;
26375 xops[1] = this_param;
26376 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26379 xops[0] = XEXP (DECL_RTL (function), 0);
26382 if (!flag_pic || (*targetm.binds_local_p) (function))
26383 output_asm_insn ("jmp\t%P0", xops);
26384 /* All thunks should be in the same object as their target,
26385 and thus binds_local_p should be true. */
26386 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26387 gcc_unreachable ();
26390 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26391 tmp = gen_rtx_CONST (Pmode, tmp);
26392 tmp = gen_rtx_MEM (QImode, tmp);
26394 output_asm_insn ("jmp\t%A0", xops);
26399 if (!flag_pic || (*targetm.binds_local_p) (function))
26400 output_asm_insn ("jmp\t%P0", xops);
26405 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26406 tmp = (gen_rtx_SYMBOL_REF
26408 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26409 tmp = gen_rtx_MEM (QImode, tmp);
26411 output_asm_insn ("jmp\t%0", xops);
26414 #endif /* TARGET_MACHO */
26416 tmp = gen_rtx_REG (SImode, CX_REG);
26417 output_set_got (tmp, NULL_RTX);
26420 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26421 output_asm_insn ("jmp\t{*}%1", xops);
26427 x86_file_start (void)
26429 default_file_start ();
26431 darwin_file_start ();
26433 if (X86_FILE_START_VERSION_DIRECTIVE)
26434 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26435 if (X86_FILE_START_FLTUSED)
26436 fputs ("\t.global\t__fltused\n", asm_out_file);
26437 if (ix86_asm_dialect == ASM_INTEL)
26438 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26442 x86_field_alignment (tree field, int computed)
26444 enum machine_mode mode;
26445 tree type = TREE_TYPE (field);
26447 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26449 mode = TYPE_MODE (strip_array_types (type));
26450 if (mode == DFmode || mode == DCmode
26451 || GET_MODE_CLASS (mode) == MODE_INT
26452 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26453 return MIN (32, computed);
26457 /* Output assembler code to FILE to increment profiler label # LABELNO
26458 for profiling a function entry. */
26460 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26464 #ifndef NO_PROFILE_COUNTERS
26465 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26468 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26469 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26471 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26475 #ifndef NO_PROFILE_COUNTERS
26476 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26477 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26479 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26483 #ifndef NO_PROFILE_COUNTERS
26484 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26485 PROFILE_COUNT_REGISTER);
26487 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26491 /* We don't have exact information about the insn sizes, but we may assume
26492 quite safely that we are informed about all 1 byte insns and memory
26493 address sizes. This is enough to eliminate unnecessary padding in
26497 min_insn_size (rtx insn)
26501 if (!INSN_P (insn) || !active_insn_p (insn))
26504 /* Discard alignments we've emit and jump instructions. */
26505 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26506 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26509 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26510 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26513 /* Important case - calls are always 5 bytes.
26514 It is common to have many calls in the row. */
26516 && symbolic_reference_mentioned_p (PATTERN (insn))
26517 && !SIBLING_CALL_P (insn))
26519 if (get_attr_length (insn) <= 1)
26522 /* For normal instructions we may rely on the sizes of addresses
26523 and the presence of symbol to require 4 bytes of encoding.
26524 This is not the case for jumps where references are PC relative. */
26525 if (!JUMP_P (insn))
26527 l = get_attr_length_address (insn);
26528 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26537 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26541 ix86_avoid_jump_misspredicts (void)
26543 rtx insn, start = get_insns ();
26544 int nbytes = 0, njumps = 0;
26547 /* Look for all minimal intervals of instructions containing 4 jumps.
26548 The intervals are bounded by START and INSN. NBYTES is the total
26549 size of instructions in the interval including INSN and not including
26550 START. When the NBYTES is smaller than 16 bytes, it is possible
26551 that the end of START and INSN ends up in the same 16byte page.
26553 The smallest offset in the page INSN can start is the case where START
26554 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26555 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26557 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26560 nbytes += min_insn_size (insn);
26562 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26563 INSN_UID (insn), min_insn_size (insn));
26565 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26566 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26574 start = NEXT_INSN (start);
26575 if ((JUMP_P (start)
26576 && GET_CODE (PATTERN (start)) != ADDR_VEC
26577 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26579 njumps--, isjump = 1;
26582 nbytes -= min_insn_size (start);
26584 gcc_assert (njumps >= 0);
26586 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26587 INSN_UID (start), INSN_UID (insn), nbytes);
26589 if (njumps == 3 && isjump && nbytes < 16)
26591 int padsize = 15 - nbytes + min_insn_size (insn);
26594 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26595 INSN_UID (insn), padsize);
26596 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26601 /* AMD Athlon works faster
26602 when RET is not destination of conditional jump or directly preceded
26603 by other jump instruction. We avoid the penalty by inserting NOP just
26604 before the RET instructions in such cases. */
26606 ix86_pad_returns (void)
26611 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26613 basic_block bb = e->src;
26614 rtx ret = BB_END (bb);
26616 bool replace = false;
26618 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26619 || optimize_bb_for_size_p (bb))
26621 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26622 if (active_insn_p (prev) || LABEL_P (prev))
26624 if (prev && LABEL_P (prev))
26629 FOR_EACH_EDGE (e, ei, bb->preds)
26630 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26631 && !(e->flags & EDGE_FALLTHRU))
26636 prev = prev_active_insn (ret);
26638 && ((JUMP_P (prev) && any_condjump_p (prev))
26641 /* Empty functions get branch mispredict even when the jump destination
26642 is not visible to us. */
26643 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26648 emit_insn_before (gen_return_internal_long (), ret);
26654 /* Implement machine specific optimizations. We implement padding of returns
26655 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26659 if (TARGET_PAD_RETURNS && optimize
26660 && optimize_function_for_speed_p (cfun))
26661 ix86_pad_returns ();
26662 if (TARGET_FOUR_JUMP_LIMIT && optimize
26663 && optimize_function_for_speed_p (cfun))
26664 ix86_avoid_jump_misspredicts ();
26667 /* Return nonzero when QImode register that must be represented via REX prefix
26670 x86_extended_QIreg_mentioned_p (rtx insn)
26673 extract_insn_cached (insn);
26674 for (i = 0; i < recog_data.n_operands; i++)
26675 if (REG_P (recog_data.operand[i])
26676 && REGNO (recog_data.operand[i]) >= 4)
26681 /* Return nonzero when P points to register encoded via REX prefix.
26682 Called via for_each_rtx. */
26684 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26686 unsigned int regno;
26689 regno = REGNO (*p);
26690 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26693 /* Return true when INSN mentions register that must be encoded using REX
26696 x86_extended_reg_mentioned_p (rtx insn)
26698 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26699 extended_reg_mentioned_1, NULL);
26702 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26703 optabs would emit if we didn't have TFmode patterns. */
26706 x86_emit_floatuns (rtx operands[2])
26708 rtx neglab, donelab, i0, i1, f0, in, out;
26709 enum machine_mode mode, inmode;
26711 inmode = GET_MODE (operands[1]);
26712 gcc_assert (inmode == SImode || inmode == DImode);
26715 in = force_reg (inmode, operands[1]);
26716 mode = GET_MODE (out);
26717 neglab = gen_label_rtx ();
26718 donelab = gen_label_rtx ();
26719 f0 = gen_reg_rtx (mode);
26721 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26723 expand_float (out, in, 0);
26725 emit_jump_insn (gen_jump (donelab));
26728 emit_label (neglab);
26730 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26732 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26734 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26736 expand_float (f0, i0, 0);
26738 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26740 emit_label (donelab);
26743 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26744 with all elements equal to VAR. Return true if successful. */
26747 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26748 rtx target, rtx val)
26750 enum machine_mode hmode, smode, wsmode, wvmode;
26765 val = force_reg (GET_MODE_INNER (mode), val);
26766 x = gen_rtx_VEC_DUPLICATE (mode, val);
26767 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26773 if (TARGET_SSE || TARGET_3DNOW_A)
26775 val = gen_lowpart (SImode, val);
26776 x = gen_rtx_TRUNCATE (HImode, val);
26777 x = gen_rtx_VEC_DUPLICATE (mode, x);
26778 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26800 /* Extend HImode to SImode using a paradoxical SUBREG. */
26801 tmp1 = gen_reg_rtx (SImode);
26802 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26803 /* Insert the SImode value as low element of V4SImode vector. */
26804 tmp2 = gen_reg_rtx (V4SImode);
26805 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26806 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26807 CONST0_RTX (V4SImode),
26809 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26810 /* Cast the V4SImode vector back to a V8HImode vector. */
26811 tmp1 = gen_reg_rtx (V8HImode);
26812 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
26813 /* Duplicate the low short through the whole low SImode word. */
26814 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
26815 /* Cast the V8HImode vector back to a V4SImode vector. */
26816 tmp2 = gen_reg_rtx (V4SImode);
26817 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26818 /* Replicate the low element of the V4SImode vector. */
26819 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26820 /* Cast the V2SImode back to V8HImode, and store in target. */
26821 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
26832 /* Extend QImode to SImode using a paradoxical SUBREG. */
26833 tmp1 = gen_reg_rtx (SImode);
26834 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26835 /* Insert the SImode value as low element of V4SImode vector. */
26836 tmp2 = gen_reg_rtx (V4SImode);
26837 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26838 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26839 CONST0_RTX (V4SImode),
26841 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26842 /* Cast the V4SImode vector back to a V16QImode vector. */
26843 tmp1 = gen_reg_rtx (V16QImode);
26844 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
26845 /* Duplicate the low byte through the whole low SImode word. */
26846 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26847 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26848 /* Cast the V16QImode vector back to a V4SImode vector. */
26849 tmp2 = gen_reg_rtx (V4SImode);
26850 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26851 /* Replicate the low element of the V4SImode vector. */
26852 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26853 /* Cast the V2SImode back to V16QImode, and store in target. */
26854 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
26862 /* Replicate the value once into the next wider mode and recurse. */
26863 val = convert_modes (wsmode, smode, val, true);
26864 x = expand_simple_binop (wsmode, ASHIFT, val,
26865 GEN_INT (GET_MODE_BITSIZE (smode)),
26866 NULL_RTX, 1, OPTAB_LIB_WIDEN);
26867 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
26869 x = gen_reg_rtx (wvmode);
26870 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
26871 gcc_unreachable ();
26872 emit_move_insn (target, gen_lowpart (mode, x));
26895 rtx tmp = gen_reg_rtx (hmode);
26896 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
26897 emit_insn (gen_rtx_SET (VOIDmode, target,
26898 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
26907 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26908 whose ONE_VAR element is VAR, and other elements are zero. Return true
26912 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
26913 rtx target, rtx var, int one_var)
26915 enum machine_mode vsimode;
26918 bool use_vector_set = false;
26923 /* For SSE4.1, we normally use vector set. But if the second
26924 element is zero and inter-unit moves are OK, we use movq
26926 use_vector_set = (TARGET_64BIT
26928 && !(TARGET_INTER_UNIT_MOVES
26934 use_vector_set = TARGET_SSE4_1;
26937 use_vector_set = TARGET_SSE2;
26940 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
26948 use_vector_set = TARGET_AVX;
26954 if (use_vector_set)
26956 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
26957 var = force_reg (GET_MODE_INNER (mode), var);
26958 ix86_expand_vector_set (mmx_ok, target, var, one_var);
26974 var = force_reg (GET_MODE_INNER (mode), var);
26975 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
26976 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26981 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
26982 new_target = gen_reg_rtx (mode);
26984 new_target = target;
26985 var = force_reg (GET_MODE_INNER (mode), var);
26986 x = gen_rtx_VEC_DUPLICATE (mode, var);
26987 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
26988 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
26991 /* We need to shuffle the value to the correct position, so
26992 create a new pseudo to store the intermediate result. */
26994 /* With SSE2, we can use the integer shuffle insns. */
26995 if (mode != V4SFmode && TARGET_SSE2)
26997 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
26999 GEN_INT (one_var == 1 ? 0 : 1),
27000 GEN_INT (one_var == 2 ? 0 : 1),
27001 GEN_INT (one_var == 3 ? 0 : 1)));
27002 if (target != new_target)
27003 emit_move_insn (target, new_target);
27007 /* Otherwise convert the intermediate result to V4SFmode and
27008 use the SSE1 shuffle instructions. */
27009 if (mode != V4SFmode)
27011 tmp = gen_reg_rtx (V4SFmode);
27012 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27017 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27019 GEN_INT (one_var == 1 ? 0 : 1),
27020 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27021 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27023 if (mode != V4SFmode)
27024 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27025 else if (tmp != target)
27026 emit_move_insn (target, tmp);
27028 else if (target != new_target)
27029 emit_move_insn (target, new_target);
27034 vsimode = V4SImode;
27040 vsimode = V2SImode;
27046 /* Zero extend the variable element to SImode and recurse. */
27047 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27049 x = gen_reg_rtx (vsimode);
27050 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27052 gcc_unreachable ();
27054 emit_move_insn (target, gen_lowpart (mode, x));
27062 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27063 consisting of the values in VALS. It is known that all elements
27064 except ONE_VAR are constants. Return true if successful. */
27067 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27068 rtx target, rtx vals, int one_var)
27070 rtx var = XVECEXP (vals, 0, one_var);
27071 enum machine_mode wmode;
27074 const_vec = copy_rtx (vals);
27075 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27076 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27084 /* For the two element vectors, it's just as easy to use
27085 the general case. */
27109 /* There's no way to set one QImode entry easily. Combine
27110 the variable value with its adjacent constant value, and
27111 promote to an HImode set. */
27112 x = XVECEXP (vals, 0, one_var ^ 1);
27115 var = convert_modes (HImode, QImode, var, true);
27116 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27117 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27118 x = GEN_INT (INTVAL (x) & 0xff);
27122 var = convert_modes (HImode, QImode, var, true);
27123 x = gen_int_mode (INTVAL (x) << 8, HImode);
27125 if (x != const0_rtx)
27126 var = expand_simple_binop (HImode, IOR, var, x, var,
27127 1, OPTAB_LIB_WIDEN);
27129 x = gen_reg_rtx (wmode);
27130 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27131 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27133 emit_move_insn (target, gen_lowpart (mode, x));
27140 emit_move_insn (target, const_vec);
27141 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27145 /* A subroutine of ix86_expand_vector_init_general. Use vector
27146 concatenate to handle the most general case: all values variable,
27147 and none identical. */
27150 ix86_expand_vector_init_concat (enum machine_mode mode,
27151 rtx target, rtx *ops, int n)
27153 enum machine_mode cmode, hmode = VOIDmode;
27154 rtx first[8], second[4];
27194 gcc_unreachable ();
27197 if (!register_operand (ops[1], cmode))
27198 ops[1] = force_reg (cmode, ops[1]);
27199 if (!register_operand (ops[0], cmode))
27200 ops[0] = force_reg (cmode, ops[0]);
27201 emit_insn (gen_rtx_SET (VOIDmode, target,
27202 gen_rtx_VEC_CONCAT (mode, ops[0],
27222 gcc_unreachable ();
27238 gcc_unreachable ();
27243 /* FIXME: We process inputs backward to help RA. PR 36222. */
27246 for (; i > 0; i -= 2, j--)
27248 first[j] = gen_reg_rtx (cmode);
27249 v = gen_rtvec (2, ops[i - 1], ops[i]);
27250 ix86_expand_vector_init (false, first[j],
27251 gen_rtx_PARALLEL (cmode, v));
27257 gcc_assert (hmode != VOIDmode);
27258 for (i = j = 0; i < n; i += 2, j++)
27260 second[j] = gen_reg_rtx (hmode);
27261 ix86_expand_vector_init_concat (hmode, second [j],
27265 ix86_expand_vector_init_concat (mode, target, second, n);
27268 ix86_expand_vector_init_concat (mode, target, first, n);
27272 gcc_unreachable ();
27276 /* A subroutine of ix86_expand_vector_init_general. Use vector
27277 interleave to handle the most general case: all values variable,
27278 and none identical. */
27281 ix86_expand_vector_init_interleave (enum machine_mode mode,
27282 rtx target, rtx *ops, int n)
27284 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27287 rtx (*gen_load_even) (rtx, rtx, rtx);
27288 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27289 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27294 gen_load_even = gen_vec_setv8hi;
27295 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27296 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27297 inner_mode = HImode;
27298 first_imode = V4SImode;
27299 second_imode = V2DImode;
27300 third_imode = VOIDmode;
27303 gen_load_even = gen_vec_setv16qi;
27304 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27305 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27306 inner_mode = QImode;
27307 first_imode = V8HImode;
27308 second_imode = V4SImode;
27309 third_imode = V2DImode;
27312 gcc_unreachable ();
27315 for (i = 0; i < n; i++)
27317 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27318 op0 = gen_reg_rtx (SImode);
27319 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27321 /* Insert the SImode value as low element of V4SImode vector. */
27322 op1 = gen_reg_rtx (V4SImode);
27323 op0 = gen_rtx_VEC_MERGE (V4SImode,
27324 gen_rtx_VEC_DUPLICATE (V4SImode,
27326 CONST0_RTX (V4SImode),
27328 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27330 /* Cast the V4SImode vector back to a vector in orignal mode. */
27331 op0 = gen_reg_rtx (mode);
27332 emit_move_insn (op0, gen_lowpart (mode, op1));
27334 /* Load even elements into the second positon. */
27335 emit_insn ((*gen_load_even) (op0,
27336 force_reg (inner_mode,
27340 /* Cast vector to FIRST_IMODE vector. */
27341 ops[i] = gen_reg_rtx (first_imode);
27342 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27345 /* Interleave low FIRST_IMODE vectors. */
27346 for (i = j = 0; i < n; i += 2, j++)
27348 op0 = gen_reg_rtx (first_imode);
27349 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27351 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27352 ops[j] = gen_reg_rtx (second_imode);
27353 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27356 /* Interleave low SECOND_IMODE vectors. */
27357 switch (second_imode)
27360 for (i = j = 0; i < n / 2; i += 2, j++)
27362 op0 = gen_reg_rtx (second_imode);
27363 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27366 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27368 ops[j] = gen_reg_rtx (third_imode);
27369 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27371 second_imode = V2DImode;
27372 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27376 op0 = gen_reg_rtx (second_imode);
27377 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27380 /* Cast the SECOND_IMODE vector back to a vector on original
27382 emit_insn (gen_rtx_SET (VOIDmode, target,
27383 gen_lowpart (mode, op0)));
27387 gcc_unreachable ();
27391 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27392 all values variable, and none identical. */
27395 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27396 rtx target, rtx vals)
27398 rtx ops[32], op0, op1;
27399 enum machine_mode half_mode = VOIDmode;
27406 if (!mmx_ok && !TARGET_SSE)
27418 n = GET_MODE_NUNITS (mode);
27419 for (i = 0; i < n; i++)
27420 ops[i] = XVECEXP (vals, 0, i);
27421 ix86_expand_vector_init_concat (mode, target, ops, n);
27425 half_mode = V16QImode;
27429 half_mode = V8HImode;
27433 n = GET_MODE_NUNITS (mode);
27434 for (i = 0; i < n; i++)
27435 ops[i] = XVECEXP (vals, 0, i);
27436 op0 = gen_reg_rtx (half_mode);
27437 op1 = gen_reg_rtx (half_mode);
27438 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27440 ix86_expand_vector_init_interleave (half_mode, op1,
27441 &ops [n >> 1], n >> 2);
27442 emit_insn (gen_rtx_SET (VOIDmode, target,
27443 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27447 if (!TARGET_SSE4_1)
27455 /* Don't use ix86_expand_vector_init_interleave if we can't
27456 move from GPR to SSE register directly. */
27457 if (!TARGET_INTER_UNIT_MOVES)
27460 n = GET_MODE_NUNITS (mode);
27461 for (i = 0; i < n; i++)
27462 ops[i] = XVECEXP (vals, 0, i);
27463 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27471 gcc_unreachable ();
27475 int i, j, n_elts, n_words, n_elt_per_word;
27476 enum machine_mode inner_mode;
27477 rtx words[4], shift;
27479 inner_mode = GET_MODE_INNER (mode);
27480 n_elts = GET_MODE_NUNITS (mode);
27481 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27482 n_elt_per_word = n_elts / n_words;
27483 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27485 for (i = 0; i < n_words; ++i)
27487 rtx word = NULL_RTX;
27489 for (j = 0; j < n_elt_per_word; ++j)
27491 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27492 elt = convert_modes (word_mode, inner_mode, elt, true);
27498 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27499 word, 1, OPTAB_LIB_WIDEN);
27500 word = expand_simple_binop (word_mode, IOR, word, elt,
27501 word, 1, OPTAB_LIB_WIDEN);
27509 emit_move_insn (target, gen_lowpart (mode, words[0]));
27510 else if (n_words == 2)
27512 rtx tmp = gen_reg_rtx (mode);
27513 emit_clobber (tmp);
27514 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27515 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27516 emit_move_insn (target, tmp);
27518 else if (n_words == 4)
27520 rtx tmp = gen_reg_rtx (V4SImode);
27521 gcc_assert (word_mode == SImode);
27522 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27523 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27524 emit_move_insn (target, gen_lowpart (mode, tmp));
27527 gcc_unreachable ();
27531 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27532 instructions unless MMX_OK is true. */
27535 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27537 enum machine_mode mode = GET_MODE (target);
27538 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27539 int n_elts = GET_MODE_NUNITS (mode);
27540 int n_var = 0, one_var = -1;
27541 bool all_same = true, all_const_zero = true;
27545 for (i = 0; i < n_elts; ++i)
27547 x = XVECEXP (vals, 0, i);
27548 if (!(CONST_INT_P (x)
27549 || GET_CODE (x) == CONST_DOUBLE
27550 || GET_CODE (x) == CONST_FIXED))
27551 n_var++, one_var = i;
27552 else if (x != CONST0_RTX (inner_mode))
27553 all_const_zero = false;
27554 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27558 /* Constants are best loaded from the constant pool. */
27561 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27565 /* If all values are identical, broadcast the value. */
27567 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27568 XVECEXP (vals, 0, 0)))
27571 /* Values where only one field is non-constant are best loaded from
27572 the pool and overwritten via move later. */
27576 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27577 XVECEXP (vals, 0, one_var),
27581 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27585 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27589 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27591 enum machine_mode mode = GET_MODE (target);
27592 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27593 enum machine_mode half_mode;
27594 bool use_vec_merge = false;
27596 static rtx (*gen_extract[6][2]) (rtx, rtx)
27598 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27599 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27600 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27601 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27602 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27603 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27605 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27607 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27608 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27609 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27610 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27611 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27612 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27622 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27623 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27625 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27627 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27628 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27634 use_vec_merge = TARGET_SSE4_1;
27642 /* For the two element vectors, we implement a VEC_CONCAT with
27643 the extraction of the other element. */
27645 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27646 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27649 op0 = val, op1 = tmp;
27651 op0 = tmp, op1 = val;
27653 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27654 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27659 use_vec_merge = TARGET_SSE4_1;
27666 use_vec_merge = true;
27670 /* tmp = target = A B C D */
27671 tmp = copy_to_reg (target);
27672 /* target = A A B B */
27673 emit_insn (gen_sse_unpcklps (target, target, target));
27674 /* target = X A B B */
27675 ix86_expand_vector_set (false, target, val, 0);
27676 /* target = A X C D */
27677 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27678 GEN_INT (1), GEN_INT (0),
27679 GEN_INT (2+4), GEN_INT (3+4)));
27683 /* tmp = target = A B C D */
27684 tmp = copy_to_reg (target);
27685 /* tmp = X B C D */
27686 ix86_expand_vector_set (false, tmp, val, 0);
27687 /* target = A B X D */
27688 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27689 GEN_INT (0), GEN_INT (1),
27690 GEN_INT (0+4), GEN_INT (3+4)));
27694 /* tmp = target = A B C D */
27695 tmp = copy_to_reg (target);
27696 /* tmp = X B C D */
27697 ix86_expand_vector_set (false, tmp, val, 0);
27698 /* target = A B X D */
27699 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27700 GEN_INT (0), GEN_INT (1),
27701 GEN_INT (2+4), GEN_INT (0+4)));
27705 gcc_unreachable ();
27710 use_vec_merge = TARGET_SSE4_1;
27714 /* Element 0 handled by vec_merge below. */
27717 use_vec_merge = true;
27723 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27724 store into element 0, then shuffle them back. */
27728 order[0] = GEN_INT (elt);
27729 order[1] = const1_rtx;
27730 order[2] = const2_rtx;
27731 order[3] = GEN_INT (3);
27732 order[elt] = const0_rtx;
27734 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27735 order[1], order[2], order[3]));
27737 ix86_expand_vector_set (false, target, val, 0);
27739 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27740 order[1], order[2], order[3]));
27744 /* For SSE1, we have to reuse the V4SF code. */
27745 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27746 gen_lowpart (SFmode, val), elt);
27751 use_vec_merge = TARGET_SSE2;
27754 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27758 use_vec_merge = TARGET_SSE4_1;
27765 half_mode = V16QImode;
27771 half_mode = V8HImode;
27777 half_mode = V4SImode;
27783 half_mode = V2DImode;
27789 half_mode = V4SFmode;
27795 half_mode = V2DFmode;
27801 /* Compute offset. */
27805 gcc_assert (i <= 1);
27807 /* Extract the half. */
27808 tmp = gen_reg_rtx (half_mode);
27809 emit_insn ((*gen_extract[j][i]) (tmp, target));
27811 /* Put val in tmp at elt. */
27812 ix86_expand_vector_set (false, tmp, val, elt);
27815 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
27824 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
27825 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
27826 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27830 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27832 emit_move_insn (mem, target);
27834 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27835 emit_move_insn (tmp, val);
27837 emit_move_insn (target, mem);
27842 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
27844 enum machine_mode mode = GET_MODE (vec);
27845 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27846 bool use_vec_extr = false;
27859 use_vec_extr = true;
27863 use_vec_extr = TARGET_SSE4_1;
27875 tmp = gen_reg_rtx (mode);
27876 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
27877 GEN_INT (elt), GEN_INT (elt),
27878 GEN_INT (elt+4), GEN_INT (elt+4)));
27882 tmp = gen_reg_rtx (mode);
27883 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
27887 gcc_unreachable ();
27890 use_vec_extr = true;
27895 use_vec_extr = TARGET_SSE4_1;
27909 tmp = gen_reg_rtx (mode);
27910 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
27911 GEN_INT (elt), GEN_INT (elt),
27912 GEN_INT (elt), GEN_INT (elt)));
27916 tmp = gen_reg_rtx (mode);
27917 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
27921 gcc_unreachable ();
27924 use_vec_extr = true;
27929 /* For SSE1, we have to reuse the V4SF code. */
27930 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
27931 gen_lowpart (V4SFmode, vec), elt);
27937 use_vec_extr = TARGET_SSE2;
27940 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27944 use_vec_extr = TARGET_SSE4_1;
27948 /* ??? Could extract the appropriate HImode element and shift. */
27955 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
27956 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
27958 /* Let the rtl optimizers know about the zero extension performed. */
27959 if (inner_mode == QImode || inner_mode == HImode)
27961 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
27962 target = gen_lowpart (SImode, target);
27965 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27969 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27971 emit_move_insn (mem, vec);
27973 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27974 emit_move_insn (target, tmp);
27978 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
27979 pattern to reduce; DEST is the destination; IN is the input vector. */
27982 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
27984 rtx tmp1, tmp2, tmp3;
27986 tmp1 = gen_reg_rtx (V4SFmode);
27987 tmp2 = gen_reg_rtx (V4SFmode);
27988 tmp3 = gen_reg_rtx (V4SFmode);
27990 emit_insn (gen_sse_movhlps (tmp1, in, in));
27991 emit_insn (fn (tmp2, tmp1, in));
27993 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
27994 GEN_INT (1), GEN_INT (1),
27995 GEN_INT (1+4), GEN_INT (1+4)));
27996 emit_insn (fn (dest, tmp2, tmp3));
27999 /* Target hook for scalar_mode_supported_p. */
28001 ix86_scalar_mode_supported_p (enum machine_mode mode)
28003 if (DECIMAL_FLOAT_MODE_P (mode))
28005 else if (mode == TFmode)
28008 return default_scalar_mode_supported_p (mode);
28011 /* Implements target hook vector_mode_supported_p. */
28013 ix86_vector_mode_supported_p (enum machine_mode mode)
28015 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28017 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28019 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28021 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28023 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28028 /* Target hook for c_mode_for_suffix. */
28029 static enum machine_mode
28030 ix86_c_mode_for_suffix (char suffix)
28040 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28042 We do this in the new i386 backend to maintain source compatibility
28043 with the old cc0-based compiler. */
28046 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28047 tree inputs ATTRIBUTE_UNUSED,
28050 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28052 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28057 /* Implements target vector targetm.asm.encode_section_info. This
28058 is not used by netware. */
28060 static void ATTRIBUTE_UNUSED
28061 ix86_encode_section_info (tree decl, rtx rtl, int first)
28063 default_encode_section_info (decl, rtl, first);
28065 if (TREE_CODE (decl) == VAR_DECL
28066 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28067 && ix86_in_large_data_p (decl))
28068 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28071 /* Worker function for REVERSE_CONDITION. */
28074 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28076 return (mode != CCFPmode && mode != CCFPUmode
28077 ? reverse_condition (code)
28078 : reverse_condition_maybe_unordered (code));
28081 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28085 output_387_reg_move (rtx insn, rtx *operands)
28087 if (REG_P (operands[0]))
28089 if (REG_P (operands[1])
28090 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28092 if (REGNO (operands[0]) == FIRST_STACK_REG)
28093 return output_387_ffreep (operands, 0);
28094 return "fstp\t%y0";
28096 if (STACK_TOP_P (operands[0]))
28097 return "fld%z1\t%y1";
28100 else if (MEM_P (operands[0]))
28102 gcc_assert (REG_P (operands[1]));
28103 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28104 return "fstp%z0\t%y0";
28107 /* There is no non-popping store to memory for XFmode.
28108 So if we need one, follow the store with a load. */
28109 if (GET_MODE (operands[0]) == XFmode)
28110 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28112 return "fst%z0\t%y0";
28119 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28120 FP status register is set. */
28123 ix86_emit_fp_unordered_jump (rtx label)
28125 rtx reg = gen_reg_rtx (HImode);
28128 emit_insn (gen_x86_fnstsw_1 (reg));
28130 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28132 emit_insn (gen_x86_sahf_1 (reg));
28134 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28135 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28139 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28141 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28142 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28145 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28146 gen_rtx_LABEL_REF (VOIDmode, label),
28148 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28150 emit_jump_insn (temp);
28151 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28154 /* Output code to perform a log1p XFmode calculation. */
28156 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28158 rtx label1 = gen_label_rtx ();
28159 rtx label2 = gen_label_rtx ();
28161 rtx tmp = gen_reg_rtx (XFmode);
28162 rtx tmp2 = gen_reg_rtx (XFmode);
28164 emit_insn (gen_absxf2 (tmp, op1));
28165 emit_insn (gen_cmpxf (tmp,
28166 CONST_DOUBLE_FROM_REAL_VALUE (
28167 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28169 emit_jump_insn (gen_bge (label1));
28171 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28172 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28173 emit_jump (label2);
28175 emit_label (label1);
28176 emit_move_insn (tmp, CONST1_RTX (XFmode));
28177 emit_insn (gen_addxf3 (tmp, op1, tmp));
28178 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28179 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28181 emit_label (label2);
28184 /* Output code to perform a Newton-Rhapson approximation of a single precision
28185 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28187 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28189 rtx x0, x1, e0, e1, two;
28191 x0 = gen_reg_rtx (mode);
28192 e0 = gen_reg_rtx (mode);
28193 e1 = gen_reg_rtx (mode);
28194 x1 = gen_reg_rtx (mode);
28196 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28198 if (VECTOR_MODE_P (mode))
28199 two = ix86_build_const_vector (SFmode, true, two);
28201 two = force_reg (mode, two);
28203 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28205 /* x0 = rcp(b) estimate */
28206 emit_insn (gen_rtx_SET (VOIDmode, x0,
28207 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28210 emit_insn (gen_rtx_SET (VOIDmode, e0,
28211 gen_rtx_MULT (mode, x0, b)));
28213 emit_insn (gen_rtx_SET (VOIDmode, e1,
28214 gen_rtx_MINUS (mode, two, e0)));
28216 emit_insn (gen_rtx_SET (VOIDmode, x1,
28217 gen_rtx_MULT (mode, x0, e1)));
28219 emit_insn (gen_rtx_SET (VOIDmode, res,
28220 gen_rtx_MULT (mode, a, x1)));
28223 /* Output code to perform a Newton-Rhapson approximation of a
28224 single precision floating point [reciprocal] square root. */
28226 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28229 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28232 x0 = gen_reg_rtx (mode);
28233 e0 = gen_reg_rtx (mode);
28234 e1 = gen_reg_rtx (mode);
28235 e2 = gen_reg_rtx (mode);
28236 e3 = gen_reg_rtx (mode);
28238 real_from_integer (&r, VOIDmode, -3, -1, 0);
28239 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28241 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28242 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28244 if (VECTOR_MODE_P (mode))
28246 mthree = ix86_build_const_vector (SFmode, true, mthree);
28247 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28250 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28251 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28253 /* x0 = rsqrt(a) estimate */
28254 emit_insn (gen_rtx_SET (VOIDmode, x0,
28255 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28258 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28263 zero = gen_reg_rtx (mode);
28264 mask = gen_reg_rtx (mode);
28266 zero = force_reg (mode, CONST0_RTX(mode));
28267 emit_insn (gen_rtx_SET (VOIDmode, mask,
28268 gen_rtx_NE (mode, zero, a)));
28270 emit_insn (gen_rtx_SET (VOIDmode, x0,
28271 gen_rtx_AND (mode, x0, mask)));
28275 emit_insn (gen_rtx_SET (VOIDmode, e0,
28276 gen_rtx_MULT (mode, x0, a)));
28278 emit_insn (gen_rtx_SET (VOIDmode, e1,
28279 gen_rtx_MULT (mode, e0, x0)));
28282 mthree = force_reg (mode, mthree);
28283 emit_insn (gen_rtx_SET (VOIDmode, e2,
28284 gen_rtx_PLUS (mode, e1, mthree)));
28286 mhalf = force_reg (mode, mhalf);
28288 /* e3 = -.5 * x0 */
28289 emit_insn (gen_rtx_SET (VOIDmode, e3,
28290 gen_rtx_MULT (mode, x0, mhalf)));
28292 /* e3 = -.5 * e0 */
28293 emit_insn (gen_rtx_SET (VOIDmode, e3,
28294 gen_rtx_MULT (mode, e0, mhalf)));
28295 /* ret = e2 * e3 */
28296 emit_insn (gen_rtx_SET (VOIDmode, res,
28297 gen_rtx_MULT (mode, e2, e3)));
28300 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28302 static void ATTRIBUTE_UNUSED
28303 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28306 /* With Binutils 2.15, the "@unwind" marker must be specified on
28307 every occurrence of the ".eh_frame" section, not just the first
28310 && strcmp (name, ".eh_frame") == 0)
28312 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28313 flags & SECTION_WRITE ? "aw" : "a");
28316 default_elf_asm_named_section (name, flags, decl);
28319 /* Return the mangling of TYPE if it is an extended fundamental type. */
28321 static const char *
28322 ix86_mangle_type (const_tree type)
28324 type = TYPE_MAIN_VARIANT (type);
28326 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28327 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28330 switch (TYPE_MODE (type))
28333 /* __float128 is "g". */
28336 /* "long double" or __float80 is "e". */
28343 /* For 32-bit code we can save PIC register setup by using
28344 __stack_chk_fail_local hidden function instead of calling
28345 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28346 register, so it is better to call __stack_chk_fail directly. */
28349 ix86_stack_protect_fail (void)
28351 return TARGET_64BIT
28352 ? default_external_stack_protect_fail ()
28353 : default_hidden_stack_protect_fail ();
28356 /* Select a format to encode pointers in exception handling data. CODE
28357 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28358 true if the symbol may be affected by dynamic relocations.
28360 ??? All x86 object file formats are capable of representing this.
28361 After all, the relocation needed is the same as for the call insn.
28362 Whether or not a particular assembler allows us to enter such, I
28363 guess we'll have to see. */
28365 asm_preferred_eh_data_format (int code, int global)
28369 int type = DW_EH_PE_sdata8;
28371 || ix86_cmodel == CM_SMALL_PIC
28372 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28373 type = DW_EH_PE_sdata4;
28374 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28376 if (ix86_cmodel == CM_SMALL
28377 || (ix86_cmodel == CM_MEDIUM && code))
28378 return DW_EH_PE_udata4;
28379 return DW_EH_PE_absptr;
28382 /* Expand copysign from SIGN to the positive value ABS_VALUE
28383 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28386 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28388 enum machine_mode mode = GET_MODE (sign);
28389 rtx sgn = gen_reg_rtx (mode);
28390 if (mask == NULL_RTX)
28392 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28393 if (!VECTOR_MODE_P (mode))
28395 /* We need to generate a scalar mode mask in this case. */
28396 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28397 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28398 mask = gen_reg_rtx (mode);
28399 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28403 mask = gen_rtx_NOT (mode, mask);
28404 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28405 gen_rtx_AND (mode, mask, sign)));
28406 emit_insn (gen_rtx_SET (VOIDmode, result,
28407 gen_rtx_IOR (mode, abs_value, sgn)));
28410 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28411 mask for masking out the sign-bit is stored in *SMASK, if that is
28414 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28416 enum machine_mode mode = GET_MODE (op0);
28419 xa = gen_reg_rtx (mode);
28420 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28421 if (!VECTOR_MODE_P (mode))
28423 /* We need to generate a scalar mode mask in this case. */
28424 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28425 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28426 mask = gen_reg_rtx (mode);
28427 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28429 emit_insn (gen_rtx_SET (VOIDmode, xa,
28430 gen_rtx_AND (mode, op0, mask)));
28438 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28439 swapping the operands if SWAP_OPERANDS is true. The expanded
28440 code is a forward jump to a newly created label in case the
28441 comparison is true. The generated label rtx is returned. */
28443 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28444 bool swap_operands)
28455 label = gen_label_rtx ();
28456 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28457 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28458 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28459 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28460 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28461 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28462 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28463 JUMP_LABEL (tmp) = label;
28468 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28469 using comparison code CODE. Operands are swapped for the comparison if
28470 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28472 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28473 bool swap_operands)
28475 enum machine_mode mode = GET_MODE (op0);
28476 rtx mask = gen_reg_rtx (mode);
28485 if (mode == DFmode)
28486 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28487 gen_rtx_fmt_ee (code, mode, op0, op1)));
28489 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28490 gen_rtx_fmt_ee (code, mode, op0, op1)));
28495 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28496 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28498 ix86_gen_TWO52 (enum machine_mode mode)
28500 REAL_VALUE_TYPE TWO52r;
28503 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28504 TWO52 = const_double_from_real_value (TWO52r, mode);
28505 TWO52 = force_reg (mode, TWO52);
28510 /* Expand SSE sequence for computing lround from OP1 storing
28513 ix86_expand_lround (rtx op0, rtx op1)
28515 /* C code for the stuff we're doing below:
28516 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28519 enum machine_mode mode = GET_MODE (op1);
28520 const struct real_format *fmt;
28521 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28524 /* load nextafter (0.5, 0.0) */
28525 fmt = REAL_MODE_FORMAT (mode);
28526 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28527 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28529 /* adj = copysign (0.5, op1) */
28530 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28531 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28533 /* adj = op1 + adj */
28534 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28536 /* op0 = (imode)adj */
28537 expand_fix (op0, adj, 0);
28540 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28543 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28545 /* C code for the stuff we're doing below (for do_floor):
28547 xi -= (double)xi > op1 ? 1 : 0;
28550 enum machine_mode fmode = GET_MODE (op1);
28551 enum machine_mode imode = GET_MODE (op0);
28552 rtx ireg, freg, label, tmp;
28554 /* reg = (long)op1 */
28555 ireg = gen_reg_rtx (imode);
28556 expand_fix (ireg, op1, 0);
28558 /* freg = (double)reg */
28559 freg = gen_reg_rtx (fmode);
28560 expand_float (freg, ireg, 0);
28562 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28563 label = ix86_expand_sse_compare_and_jump (UNLE,
28564 freg, op1, !do_floor);
28565 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28566 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28567 emit_move_insn (ireg, tmp);
28569 emit_label (label);
28570 LABEL_NUSES (label) = 1;
28572 emit_move_insn (op0, ireg);
28575 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28576 result in OPERAND0. */
28578 ix86_expand_rint (rtx operand0, rtx operand1)
28580 /* C code for the stuff we're doing below:
28581 xa = fabs (operand1);
28582 if (!isless (xa, 2**52))
28584 xa = xa + 2**52 - 2**52;
28585 return copysign (xa, operand1);
28587 enum machine_mode mode = GET_MODE (operand0);
28588 rtx res, xa, label, TWO52, mask;
28590 res = gen_reg_rtx (mode);
28591 emit_move_insn (res, operand1);
28593 /* xa = abs (operand1) */
28594 xa = ix86_expand_sse_fabs (res, &mask);
28596 /* if (!isless (xa, TWO52)) goto label; */
28597 TWO52 = ix86_gen_TWO52 (mode);
28598 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28600 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28601 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28603 ix86_sse_copysign_to_positive (res, xa, res, mask);
28605 emit_label (label);
28606 LABEL_NUSES (label) = 1;
28608 emit_move_insn (operand0, res);
28611 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28614 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28616 /* C code for the stuff we expand below.
28617 double xa = fabs (x), x2;
28618 if (!isless (xa, TWO52))
28620 xa = xa + TWO52 - TWO52;
28621 x2 = copysign (xa, x);
28630 enum machine_mode mode = GET_MODE (operand0);
28631 rtx xa, TWO52, tmp, label, one, res, mask;
28633 TWO52 = ix86_gen_TWO52 (mode);
28635 /* Temporary for holding the result, initialized to the input
28636 operand to ease control flow. */
28637 res = gen_reg_rtx (mode);
28638 emit_move_insn (res, operand1);
28640 /* xa = abs (operand1) */
28641 xa = ix86_expand_sse_fabs (res, &mask);
28643 /* if (!isless (xa, TWO52)) goto label; */
28644 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28646 /* xa = xa + TWO52 - TWO52; */
28647 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28648 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28650 /* xa = copysign (xa, operand1) */
28651 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28653 /* generate 1.0 or -1.0 */
28654 one = force_reg (mode,
28655 const_double_from_real_value (do_floor
28656 ? dconst1 : dconstm1, mode));
28658 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28659 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28660 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28661 gen_rtx_AND (mode, one, tmp)));
28662 /* We always need to subtract here to preserve signed zero. */
28663 tmp = expand_simple_binop (mode, MINUS,
28664 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28665 emit_move_insn (res, tmp);
28667 emit_label (label);
28668 LABEL_NUSES (label) = 1;
28670 emit_move_insn (operand0, res);
28673 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28676 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28678 /* C code for the stuff we expand below.
28679 double xa = fabs (x), x2;
28680 if (!isless (xa, TWO52))
28682 x2 = (double)(long)x;
28689 if (HONOR_SIGNED_ZEROS (mode))
28690 return copysign (x2, x);
28693 enum machine_mode mode = GET_MODE (operand0);
28694 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28696 TWO52 = ix86_gen_TWO52 (mode);
28698 /* Temporary for holding the result, initialized to the input
28699 operand to ease control flow. */
28700 res = gen_reg_rtx (mode);
28701 emit_move_insn (res, operand1);
28703 /* xa = abs (operand1) */
28704 xa = ix86_expand_sse_fabs (res, &mask);
28706 /* if (!isless (xa, TWO52)) goto label; */
28707 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28709 /* xa = (double)(long)x */
28710 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28711 expand_fix (xi, res, 0);
28712 expand_float (xa, xi, 0);
28715 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28717 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28718 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28719 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28720 gen_rtx_AND (mode, one, tmp)));
28721 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28722 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28723 emit_move_insn (res, tmp);
28725 if (HONOR_SIGNED_ZEROS (mode))
28726 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28728 emit_label (label);
28729 LABEL_NUSES (label) = 1;
28731 emit_move_insn (operand0, res);
28734 /* Expand SSE sequence for computing round from OPERAND1 storing
28735 into OPERAND0. Sequence that works without relying on DImode truncation
28736 via cvttsd2siq that is only available on 64bit targets. */
28738 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28740 /* C code for the stuff we expand below.
28741 double xa = fabs (x), xa2, x2;
28742 if (!isless (xa, TWO52))
28744 Using the absolute value and copying back sign makes
28745 -0.0 -> -0.0 correct.
28746 xa2 = xa + TWO52 - TWO52;
28751 else if (dxa > 0.5)
28753 x2 = copysign (xa2, x);
28756 enum machine_mode mode = GET_MODE (operand0);
28757 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28759 TWO52 = ix86_gen_TWO52 (mode);
28761 /* Temporary for holding the result, initialized to the input
28762 operand to ease control flow. */
28763 res = gen_reg_rtx (mode);
28764 emit_move_insn (res, operand1);
28766 /* xa = abs (operand1) */
28767 xa = ix86_expand_sse_fabs (res, &mask);
28769 /* if (!isless (xa, TWO52)) goto label; */
28770 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28772 /* xa2 = xa + TWO52 - TWO52; */
28773 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28774 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
28776 /* dxa = xa2 - xa; */
28777 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
28779 /* generate 0.5, 1.0 and -0.5 */
28780 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
28781 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
28782 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
28786 tmp = gen_reg_rtx (mode);
28787 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28788 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
28789 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28790 gen_rtx_AND (mode, one, tmp)));
28791 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28792 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28793 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
28794 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28795 gen_rtx_AND (mode, one, tmp)));
28796 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28798 /* res = copysign (xa2, operand1) */
28799 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
28801 emit_label (label);
28802 LABEL_NUSES (label) = 1;
28804 emit_move_insn (operand0, res);
28807 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28810 ix86_expand_trunc (rtx operand0, rtx operand1)
28812 /* C code for SSE variant we expand below.
28813 double xa = fabs (x), x2;
28814 if (!isless (xa, TWO52))
28816 x2 = (double)(long)x;
28817 if (HONOR_SIGNED_ZEROS (mode))
28818 return copysign (x2, x);
28821 enum machine_mode mode = GET_MODE (operand0);
28822 rtx xa, xi, TWO52, label, res, mask;
28824 TWO52 = ix86_gen_TWO52 (mode);
28826 /* Temporary for holding the result, initialized to the input
28827 operand to ease control flow. */
28828 res = gen_reg_rtx (mode);
28829 emit_move_insn (res, operand1);
28831 /* xa = abs (operand1) */
28832 xa = ix86_expand_sse_fabs (res, &mask);
28834 /* if (!isless (xa, TWO52)) goto label; */
28835 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28837 /* x = (double)(long)x */
28838 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28839 expand_fix (xi, res, 0);
28840 expand_float (res, xi, 0);
28842 if (HONOR_SIGNED_ZEROS (mode))
28843 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28845 emit_label (label);
28846 LABEL_NUSES (label) = 1;
28848 emit_move_insn (operand0, res);
28851 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28854 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
28856 enum machine_mode mode = GET_MODE (operand0);
28857 rtx xa, mask, TWO52, label, one, res, smask, tmp;
28859 /* C code for SSE variant we expand below.
28860 double xa = fabs (x), x2;
28861 if (!isless (xa, TWO52))
28863 xa2 = xa + TWO52 - TWO52;
28867 x2 = copysign (xa2, x);
28871 TWO52 = ix86_gen_TWO52 (mode);
28873 /* Temporary for holding the result, initialized to the input
28874 operand to ease control flow. */
28875 res = gen_reg_rtx (mode);
28876 emit_move_insn (res, operand1);
28878 /* xa = abs (operand1) */
28879 xa = ix86_expand_sse_fabs (res, &smask);
28881 /* if (!isless (xa, TWO52)) goto label; */
28882 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28884 /* res = xa + TWO52 - TWO52; */
28885 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28886 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
28887 emit_move_insn (res, tmp);
28890 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28892 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28893 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
28894 emit_insn (gen_rtx_SET (VOIDmode, mask,
28895 gen_rtx_AND (mode, mask, one)));
28896 tmp = expand_simple_binop (mode, MINUS,
28897 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
28898 emit_move_insn (res, tmp);
28900 /* res = copysign (res, operand1) */
28901 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
28903 emit_label (label);
28904 LABEL_NUSES (label) = 1;
28906 emit_move_insn (operand0, res);
28909 /* Expand SSE sequence for computing round from OPERAND1 storing
28912 ix86_expand_round (rtx operand0, rtx operand1)
28914 /* C code for the stuff we're doing below:
28915 double xa = fabs (x);
28916 if (!isless (xa, TWO52))
28918 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28919 return copysign (xa, x);
28921 enum machine_mode mode = GET_MODE (operand0);
28922 rtx res, TWO52, xa, label, xi, half, mask;
28923 const struct real_format *fmt;
28924 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28926 /* Temporary for holding the result, initialized to the input
28927 operand to ease control flow. */
28928 res = gen_reg_rtx (mode);
28929 emit_move_insn (res, operand1);
28931 TWO52 = ix86_gen_TWO52 (mode);
28932 xa = ix86_expand_sse_fabs (res, &mask);
28933 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28935 /* load nextafter (0.5, 0.0) */
28936 fmt = REAL_MODE_FORMAT (mode);
28937 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28938 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28940 /* xa = xa + 0.5 */
28941 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
28942 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
28944 /* xa = (double)(int64_t)xa */
28945 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28946 expand_fix (xi, xa, 0);
28947 expand_float (xa, xi, 0);
28949 /* res = copysign (xa, operand1) */
28950 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
28952 emit_label (label);
28953 LABEL_NUSES (label) = 1;
28955 emit_move_insn (operand0, res);
28959 /* Validate whether a SSE5 instruction is valid or not.
28960 OPERANDS is the array of operands.
28961 NUM is the number of operands.
28962 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
28963 NUM_MEMORY is the maximum number of memory operands to accept.
28964 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
28967 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
28968 bool uses_oc0, int num_memory, bool commutative)
28974 /* Count the number of memory arguments */
28977 for (i = 0; i < num; i++)
28979 enum machine_mode mode = GET_MODE (operands[i]);
28980 if (register_operand (operands[i], mode))
28983 else if (memory_operand (operands[i], mode))
28985 mem_mask |= (1 << i);
28991 rtx pattern = PATTERN (insn);
28993 /* allow 0 for pcmov */
28994 if (GET_CODE (pattern) != SET
28995 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
28997 || operands[i] != CONST0_RTX (mode))
29002 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29003 a memory operation. */
29004 if (num_memory < 0)
29006 num_memory = -num_memory;
29007 if ((mem_mask & (1 << (num-1))) != 0)
29009 mem_mask &= ~(1 << (num-1));
29014 /* If there were no memory operations, allow the insn */
29018 /* Do not allow the destination register to be a memory operand. */
29019 else if (mem_mask & (1 << 0))
29022 /* If there are too many memory operations, disallow the instruction. While
29023 the hardware only allows 1 memory reference, before register allocation
29024 for some insns, we allow two memory operations sometimes in order to allow
29025 code like the following to be optimized:
29027 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29029 or similar cases that are vectorized into using the fmaddss
29031 else if (mem_count > num_memory)
29034 /* Don't allow more than one memory operation if not optimizing. */
29035 else if (mem_count > 1 && !optimize)
29038 else if (num == 4 && mem_count == 1)
29040 /* formats (destination is the first argument), example fmaddss:
29041 xmm1, xmm1, xmm2, xmm3/mem
29042 xmm1, xmm1, xmm2/mem, xmm3
29043 xmm1, xmm2, xmm3/mem, xmm1
29044 xmm1, xmm2/mem, xmm3, xmm1 */
29046 return ((mem_mask == (1 << 1))
29047 || (mem_mask == (1 << 2))
29048 || (mem_mask == (1 << 3)));
29050 /* format, example pmacsdd:
29051 xmm1, xmm2, xmm3/mem, xmm1 */
29053 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29055 return (mem_mask == (1 << 2));
29058 else if (num == 4 && num_memory == 2)
29060 /* If there are two memory operations, we can load one of the memory ops
29061 into the destination register. This is for optimizing the
29062 multiply/add ops, which the combiner has optimized both the multiply
29063 and the add insns to have a memory operation. We have to be careful
29064 that the destination doesn't overlap with the inputs. */
29065 rtx op0 = operands[0];
29067 if (reg_mentioned_p (op0, operands[1])
29068 || reg_mentioned_p (op0, operands[2])
29069 || reg_mentioned_p (op0, operands[3]))
29072 /* formats (destination is the first argument), example fmaddss:
29073 xmm1, xmm1, xmm2, xmm3/mem
29074 xmm1, xmm1, xmm2/mem, xmm3
29075 xmm1, xmm2, xmm3/mem, xmm1
29076 xmm1, xmm2/mem, xmm3, xmm1
29078 For the oc0 case, we will load either operands[1] or operands[3] into
29079 operands[0], so any combination of 2 memory operands is ok. */
29083 /* format, example pmacsdd:
29084 xmm1, xmm2, xmm3/mem, xmm1
29086 For the integer multiply/add instructions be more restrictive and
29087 require operands[2] and operands[3] to be the memory operands. */
29089 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29091 return (mem_mask == ((1 << 2) | (1 << 3)));
29094 else if (num == 3 && num_memory == 1)
29096 /* formats, example protb:
29097 xmm1, xmm2, xmm3/mem
29098 xmm1, xmm2/mem, xmm3 */
29100 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29102 /* format, example comeq:
29103 xmm1, xmm2, xmm3/mem */
29105 return (mem_mask == (1 << 2));
29109 gcc_unreachable ();
29115 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29116 hardware will allow by using the destination register to load one of the
29117 memory operations. Presently this is used by the multiply/add routines to
29118 allow 2 memory references. */
29121 ix86_expand_sse5_multiple_memory (rtx operands[],
29123 enum machine_mode mode)
29125 rtx op0 = operands[0];
29127 || memory_operand (op0, mode)
29128 || reg_mentioned_p (op0, operands[1])
29129 || reg_mentioned_p (op0, operands[2])
29130 || reg_mentioned_p (op0, operands[3]))
29131 gcc_unreachable ();
29133 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29134 the destination register. */
29135 if (memory_operand (operands[1], mode))
29137 emit_move_insn (op0, operands[1]);
29140 else if (memory_operand (operands[3], mode))
29142 emit_move_insn (op0, operands[3]);
29146 gcc_unreachable ();
29152 /* Table of valid machine attributes. */
29153 static const struct attribute_spec ix86_attribute_table[] =
29155 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29156 /* Stdcall attribute says callee is responsible for popping arguments
29157 if they are not variable. */
29158 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29159 /* Fastcall attribute says callee is responsible for popping arguments
29160 if they are not variable. */
29161 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29162 /* Cdecl attribute says the callee is a normal C declaration */
29163 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29164 /* Regparm attribute specifies how many integer arguments are to be
29165 passed in registers. */
29166 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29167 /* Sseregparm attribute says we are using x86_64 calling conventions
29168 for FP arguments. */
29169 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29170 /* force_align_arg_pointer says this function realigns the stack at entry. */
29171 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29172 false, true, true, ix86_handle_cconv_attribute },
29173 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29174 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29175 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29176 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29178 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29179 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29180 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29181 SUBTARGET_ATTRIBUTE_TABLE,
29183 /* ms_abi and sysv_abi calling convention function attributes. */
29184 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29185 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29187 { NULL, 0, 0, false, false, false, NULL }
29190 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29192 x86_builtin_vectorization_cost (bool runtime_test)
29194 /* If the branch of the runtime test is taken - i.e. - the vectorized
29195 version is skipped - this incurs a misprediction cost (because the
29196 vectorized version is expected to be the fall-through). So we subtract
29197 the latency of a mispredicted branch from the costs that are incured
29198 when the vectorized version is executed.
29200 TODO: The values in individual target tables have to be tuned or new
29201 fields may be needed. For eg. on K8, the default branch path is the
29202 not-taken path. If the taken path is predicted correctly, the minimum
29203 penalty of going down the taken-path is 1 cycle. If the taken-path is
29204 not predicted correctly, then the minimum penalty is 10 cycles. */
29208 return (-(ix86_cost->cond_taken_branch_cost));
29214 /* This function returns the calling abi specific va_list type node.
29215 It returns the FNDECL specific va_list type. */
29218 ix86_fn_abi_va_list (tree fndecl)
29223 return va_list_type_node;
29224 gcc_assert (fndecl != NULL_TREE);
29225 abi = ix86_function_abi ((const_tree) fndecl);
29228 return ms_va_list_type_node;
29230 return sysv_va_list_type_node;
29233 /* Returns the canonical va_list type specified by TYPE. If there
29234 is no valid TYPE provided, it return NULL_TREE. */
29237 ix86_canonical_va_list_type (tree type)
29241 /* Resolve references and pointers to va_list type. */
29242 if (INDIRECT_REF_P (type))
29243 type = TREE_TYPE (type);
29244 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29245 type = TREE_TYPE (type);
29249 wtype = va_list_type_node;
29250 gcc_assert (wtype != NULL_TREE);
29252 if (TREE_CODE (wtype) == ARRAY_TYPE)
29254 /* If va_list is an array type, the argument may have decayed
29255 to a pointer type, e.g. by being passed to another function.
29256 In that case, unwrap both types so that we can compare the
29257 underlying records. */
29258 if (TREE_CODE (htype) == ARRAY_TYPE
29259 || POINTER_TYPE_P (htype))
29261 wtype = TREE_TYPE (wtype);
29262 htype = TREE_TYPE (htype);
29265 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29266 return va_list_type_node;
29267 wtype = sysv_va_list_type_node;
29268 gcc_assert (wtype != NULL_TREE);
29270 if (TREE_CODE (wtype) == ARRAY_TYPE)
29272 /* If va_list is an array type, the argument may have decayed
29273 to a pointer type, e.g. by being passed to another function.
29274 In that case, unwrap both types so that we can compare the
29275 underlying records. */
29276 if (TREE_CODE (htype) == ARRAY_TYPE
29277 || POINTER_TYPE_P (htype))
29279 wtype = TREE_TYPE (wtype);
29280 htype = TREE_TYPE (htype);
29283 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29284 return sysv_va_list_type_node;
29285 wtype = ms_va_list_type_node;
29286 gcc_assert (wtype != NULL_TREE);
29288 if (TREE_CODE (wtype) == ARRAY_TYPE)
29290 /* If va_list is an array type, the argument may have decayed
29291 to a pointer type, e.g. by being passed to another function.
29292 In that case, unwrap both types so that we can compare the
29293 underlying records. */
29294 if (TREE_CODE (htype) == ARRAY_TYPE
29295 || POINTER_TYPE_P (htype))
29297 wtype = TREE_TYPE (wtype);
29298 htype = TREE_TYPE (htype);
29301 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29302 return ms_va_list_type_node;
29305 return std_canonical_va_list_type (type);
29308 /* Iterate through the target-specific builtin types for va_list.
29309 IDX denotes the iterator, *PTREE is set to the result type of
29310 the va_list builtin, and *PNAME to its internal type.
29311 Returns zero if there is no element for this index, otherwise
29312 IDX should be increased upon the next call.
29313 Note, do not iterate a base builtin's name like __builtin_va_list.
29314 Used from c_common_nodes_and_builtins. */
29317 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29323 *ptree = ms_va_list_type_node;
29324 *pname = "__builtin_ms_va_list";
29327 *ptree = sysv_va_list_type_node;
29328 *pname = "__builtin_sysv_va_list";
29336 /* Initialize the GCC target structure. */
29337 #undef TARGET_RETURN_IN_MEMORY
29338 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29340 #undef TARGET_ATTRIBUTE_TABLE
29341 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29342 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29343 # undef TARGET_MERGE_DECL_ATTRIBUTES
29344 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29347 #undef TARGET_COMP_TYPE_ATTRIBUTES
29348 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29350 #undef TARGET_INIT_BUILTINS
29351 #define TARGET_INIT_BUILTINS ix86_init_builtins
29352 #undef TARGET_EXPAND_BUILTIN
29353 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29355 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29356 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29357 ix86_builtin_vectorized_function
29359 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29360 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29362 #undef TARGET_BUILTIN_RECIPROCAL
29363 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29365 #undef TARGET_ASM_FUNCTION_EPILOGUE
29366 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29368 #undef TARGET_ENCODE_SECTION_INFO
29369 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29370 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29372 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29375 #undef TARGET_ASM_OPEN_PAREN
29376 #define TARGET_ASM_OPEN_PAREN ""
29377 #undef TARGET_ASM_CLOSE_PAREN
29378 #define TARGET_ASM_CLOSE_PAREN ""
29380 #undef TARGET_ASM_ALIGNED_HI_OP
29381 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29382 #undef TARGET_ASM_ALIGNED_SI_OP
29383 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29385 #undef TARGET_ASM_ALIGNED_DI_OP
29386 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29389 #undef TARGET_ASM_UNALIGNED_HI_OP
29390 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29391 #undef TARGET_ASM_UNALIGNED_SI_OP
29392 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29393 #undef TARGET_ASM_UNALIGNED_DI_OP
29394 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29396 #undef TARGET_SCHED_ADJUST_COST
29397 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29398 #undef TARGET_SCHED_ISSUE_RATE
29399 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29400 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29401 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29402 ia32_multipass_dfa_lookahead
29404 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29405 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29408 #undef TARGET_HAVE_TLS
29409 #define TARGET_HAVE_TLS true
29411 #undef TARGET_CANNOT_FORCE_CONST_MEM
29412 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29413 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29414 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29416 #undef TARGET_DELEGITIMIZE_ADDRESS
29417 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29419 #undef TARGET_MS_BITFIELD_LAYOUT_P
29420 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29423 #undef TARGET_BINDS_LOCAL_P
29424 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29426 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29427 #undef TARGET_BINDS_LOCAL_P
29428 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29431 #undef TARGET_ASM_OUTPUT_MI_THUNK
29432 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29433 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29434 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29436 #undef TARGET_ASM_FILE_START
29437 #define TARGET_ASM_FILE_START x86_file_start
29439 #undef TARGET_DEFAULT_TARGET_FLAGS
29440 #define TARGET_DEFAULT_TARGET_FLAGS \
29442 | TARGET_SUBTARGET_DEFAULT \
29443 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29445 #undef TARGET_HANDLE_OPTION
29446 #define TARGET_HANDLE_OPTION ix86_handle_option
29448 #undef TARGET_RTX_COSTS
29449 #define TARGET_RTX_COSTS ix86_rtx_costs
29450 #undef TARGET_ADDRESS_COST
29451 #define TARGET_ADDRESS_COST ix86_address_cost
29453 #undef TARGET_FIXED_CONDITION_CODE_REGS
29454 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29455 #undef TARGET_CC_MODES_COMPATIBLE
29456 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29458 #undef TARGET_MACHINE_DEPENDENT_REORG
29459 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29461 #undef TARGET_BUILD_BUILTIN_VA_LIST
29462 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29464 #undef TARGET_FN_ABI_VA_LIST
29465 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29467 #undef TARGET_CANONICAL_VA_LIST_TYPE
29468 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29470 #undef TARGET_EXPAND_BUILTIN_VA_START
29471 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29473 #undef TARGET_MD_ASM_CLOBBERS
29474 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29476 #undef TARGET_PROMOTE_PROTOTYPES
29477 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29478 #undef TARGET_STRUCT_VALUE_RTX
29479 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29480 #undef TARGET_SETUP_INCOMING_VARARGS
29481 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29482 #undef TARGET_MUST_PASS_IN_STACK
29483 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29484 #undef TARGET_PASS_BY_REFERENCE
29485 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29486 #undef TARGET_INTERNAL_ARG_POINTER
29487 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29488 #undef TARGET_UPDATE_STACK_BOUNDARY
29489 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29490 #undef TARGET_GET_DRAP_RTX
29491 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29492 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29493 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29494 #undef TARGET_STRICT_ARGUMENT_NAMING
29495 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29497 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29498 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29500 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29501 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29503 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29504 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29506 #undef TARGET_C_MODE_FOR_SUFFIX
29507 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29510 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29511 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29514 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29515 #undef TARGET_INSERT_ATTRIBUTES
29516 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29519 #undef TARGET_MANGLE_TYPE
29520 #define TARGET_MANGLE_TYPE ix86_mangle_type
29522 #undef TARGET_STACK_PROTECT_FAIL
29523 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29525 #undef TARGET_FUNCTION_VALUE
29526 #define TARGET_FUNCTION_VALUE ix86_function_value
29528 #undef TARGET_SECONDARY_RELOAD
29529 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29531 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29532 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29534 #undef TARGET_SET_CURRENT_FUNCTION
29535 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29537 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29538 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29540 #undef TARGET_OPTION_SAVE
29541 #define TARGET_OPTION_SAVE ix86_function_specific_save
29543 #undef TARGET_OPTION_RESTORE
29544 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29546 #undef TARGET_OPTION_PRINT
29547 #define TARGET_OPTION_PRINT ix86_function_specific_print
29549 #undef TARGET_OPTION_CAN_INLINE_P
29550 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29552 #undef TARGET_EXPAND_TO_RTL_HOOK
29553 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29555 struct gcc_target targetm = TARGET_INITIALIZER;
29557 #include "gt-i386.h"
OSDN Git Service
