1 /* Subroutines for insn-output.c for Intel 80386.
2 Copyright (C) 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
35 #ifdef EXTRA_CONSTRAINT
36 /* If EXTRA_CONSTRAINT is defined, then the 'S'
37 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
38 asm statements that need 'S' for class SIREG will break. */
39 error EXTRA_CONSTRAINT conflicts with S constraint letter
40 /* The previous line used to be #error, but some compilers barf
41 even if the conditional was untrue. */
44 #define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx))
46 extern FILE *asm_out_file;
47 extern char *strcat ();
49 char *singlemove_string ();
50 char *output_move_const_single ();
51 char *output_fp_cc0_set ();
53 char *hi_reg_name[] = HI_REGISTER_NAMES;
54 char *qi_reg_name[] = QI_REGISTER_NAMES;
55 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
57 /* Array of the smallest class containing reg number REGNO, indexed by
58 REGNO. Used by REGNO_REG_CLASS in i386.h. */
60 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
63 AREG, DREG, CREG, BREG,
65 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
67 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
68 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
73 /* Test and compare insns in i386.md store the information needed to
74 generate branch and scc insns here. */
76 struct rtx_def *i386_compare_op0, *i386_compare_op1;
77 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
79 /* Output an insn whose source is a 386 integer register. SRC is the
80 rtx for the register, and TEMPLATE is the op-code template. SRC may
81 be either SImode or DImode.
83 The template will be output with operands[0] as SRC, and operands[1]
84 as a pointer to the top of the 386 stack. So a call from floatsidf2
87 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
89 where %z0 corresponds to the caller's operands[1], and is used to
90 emit the proper size suffix.
92 ??? Extend this to handle HImode - a 387 can load and store HImode
96 output_op_from_reg (src, template)
101 int size = GET_MODE_SIZE (GET_MODE (src));
104 xops[1] = AT_SP (Pmode);
105 xops[2] = GEN_INT (size);
106 xops[3] = stack_pointer_rtx;
108 if (size > UNITS_PER_WORD)
111 if (size > 2 * UNITS_PER_WORD)
113 high = gen_rtx (REG, SImode, REGNO (src) + 2);
114 output_asm_insn (AS1 (push%L0,%0), &high);
116 high = gen_rtx (REG, SImode, REGNO (src) + 1);
117 output_asm_insn (AS1 (push%L0,%0), &high);
119 output_asm_insn (AS1 (push%L0,%0), &src);
121 output_asm_insn (template, xops);
123 output_asm_insn (AS2 (add%L3,%2,%3), xops);
126 /* Output an insn to pop an value from the 387 top-of-stack to 386
127 register DEST. The 387 register stack is popped if DIES is true. If
128 the mode of DEST is an integer mode, a `fist' integer store is done,
129 otherwise a `fst' float store is done. */
132 output_to_reg (dest, dies)
137 int size = GET_MODE_SIZE (GET_MODE (dest));
139 xops[0] = AT_SP (Pmode);
140 xops[1] = stack_pointer_rtx;
141 xops[2] = GEN_INT (size);
144 output_asm_insn (AS2 (sub%L1,%2,%1), xops);
146 if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
149 output_asm_insn (AS1 (fistp%z3,%y0), xops);
151 output_asm_insn (AS1 (fist%z3,%y0), xops);
153 else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
156 output_asm_insn (AS1 (fstp%z3,%y0), xops);
159 if (GET_MODE (dest) == XFmode)
162 output_asm_insn (AS1 (fst%z3,%y0), xops);
168 output_asm_insn (AS1 (pop%L0,%0), &dest);
170 if (size > UNITS_PER_WORD)
172 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
173 output_asm_insn (AS1 (pop%L0,%0), &dest);
174 if (size > 2 * UNITS_PER_WORD)
176 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
177 output_asm_insn (AS1 (pop%L0,%0), &dest);
183 singlemove_string (operands)
187 if (GET_CODE (operands[0]) == MEM
188 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
190 if (XEXP (x, 0) != stack_pointer_rtx)
194 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
196 return output_move_const_single (operands);
198 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
199 return AS2 (mov%L0,%1,%0);
200 else if (CONSTANT_P (operands[1]))
201 return AS2 (mov%L0,%1,%0);
204 output_asm_insn ("push%L1 %1", operands);
209 /* Return a REG that occurs in ADDR with coefficient 1.
210 ADDR can be effectively incremented by incrementing REG. */
216 while (GET_CODE (addr) == PLUS)
218 if (GET_CODE (XEXP (addr, 0)) == REG)
219 addr = XEXP (addr, 0);
220 else if (GET_CODE (XEXP (addr, 1)) == REG)
221 addr = XEXP (addr, 1);
222 else if (CONSTANT_P (XEXP (addr, 0)))
223 addr = XEXP (addr, 1);
224 else if (CONSTANT_P (XEXP (addr, 1)))
225 addr = XEXP (addr, 0);
229 if (GET_CODE (addr) == REG)
234 /* Output an insn to add the constant N to the register X. */
245 xops[0] = GEN_INT (-n);
246 output_asm_insn (AS2 (sub%L0,%0,%1), xops);
250 xops[0] = GEN_INT (n);
251 output_asm_insn (AS2 (add%L0,%0,%1), xops);
255 /* Output assembler code to perform a doubleword move insn
256 with operands OPERANDS. */
259 output_move_double (operands)
262 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
266 rtx addreg0 = 0, addreg1 = 0;
267 int dest_overlapped_low = 0;
268 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
273 /* First classify both operands. */
275 if (REG_P (operands[0]))
277 else if (offsettable_memref_p (operands[0]))
279 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
281 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
283 else if (GET_CODE (operands[0]) == MEM)
288 if (REG_P (operands[1]))
290 else if (CONSTANT_P (operands[1]))
292 else if (offsettable_memref_p (operands[1]))
294 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
296 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
298 else if (GET_CODE (operands[1]) == MEM)
303 /* Check for the cases that the operand constraints are not
304 supposed to allow to happen. Abort if we get one,
305 because generating code for these cases is painful. */
307 if (optype0 == RNDOP || optype1 == RNDOP)
310 /* If one operand is decrementing and one is incrementing
311 decrement the former register explicitly
312 and change that operand into ordinary indexing. */
314 if (optype0 == PUSHOP && optype1 == POPOP)
316 /* ??? Can this ever happen on i386? */
317 operands[0] = XEXP (XEXP (operands[0], 0), 0);
318 asm_add (-size, operands[0]);
319 if (GET_MODE (operands[1]) == XFmode)
320 operands[0] = gen_rtx (MEM, XFmode, operands[0]);
321 else if (GET_MODE (operands[0]) == DFmode)
322 operands[0] = gen_rtx (MEM, DFmode, operands[0]);
324 operands[0] = gen_rtx (MEM, DImode, operands[0]);
328 if (optype0 == POPOP && optype1 == PUSHOP)
330 /* ??? Can this ever happen on i386? */
331 operands[1] = XEXP (XEXP (operands[1], 0), 0);
332 asm_add (-size, operands[1]);
333 if (GET_MODE (operands[1]) == XFmode)
334 operands[1] = gen_rtx (MEM, XFmode, operands[1]);
335 else if (GET_MODE (operands[1]) == DFmode)
336 operands[1] = gen_rtx (MEM, DFmode, operands[1]);
338 operands[1] = gen_rtx (MEM, DImode, operands[1]);
342 /* If an operand is an unoffsettable memory ref, find a register
343 we can increment temporarily to make it refer to the second word. */
345 if (optype0 == MEMOP)
346 addreg0 = find_addr_reg (XEXP (operands[0], 0));
348 if (optype1 == MEMOP)
349 addreg1 = find_addr_reg (XEXP (operands[1], 0));
351 /* Ok, we can do one word at a time.
352 Normally we do the low-numbered word first,
353 but if either operand is autodecrementing then we
354 do the high-numbered word first.
356 In either case, set up in LATEHALF the operands to use
357 for the high-numbered word and in some cases alter the
358 operands in OPERANDS to be suitable for the low-numbered word. */
362 if (optype0 == REGOP)
364 middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
365 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
367 else if (optype0 == OFFSOP)
369 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
370 latehalf[0] = adj_offsettable_operand (operands[0], 8);
374 middlehalf[0] = operands[0];
375 latehalf[0] = operands[0];
378 if (optype1 == REGOP)
380 middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
381 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
383 else if (optype1 == OFFSOP)
385 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
386 latehalf[1] = adj_offsettable_operand (operands[1], 8);
388 else if (optype1 == CNSTOP)
390 if (GET_CODE (operands[1]) == CONST_DOUBLE)
392 REAL_VALUE_TYPE r; long l[3];
394 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
395 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
396 operands[1] = GEN_INT (l[0]);
397 middlehalf[1] = GEN_INT (l[1]);
398 latehalf[1] = GEN_INT (l[2]);
400 else if (CONSTANT_P (operands[1]))
401 /* No non-CONST_DOUBLE constant should ever appear here. */
406 middlehalf[1] = operands[1];
407 latehalf[1] = operands[1];
410 else /* size is not 12: */
412 if (optype0 == REGOP)
413 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
414 else if (optype0 == OFFSOP)
415 latehalf[0] = adj_offsettable_operand (operands[0], 4);
417 latehalf[0] = operands[0];
419 if (optype1 == REGOP)
420 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
421 else if (optype1 == OFFSOP)
422 latehalf[1] = adj_offsettable_operand (operands[1], 4);
423 else if (optype1 == CNSTOP)
425 if (GET_CODE (operands[1]) == CONST_DOUBLE)
426 split_double (operands[1], &operands[1], &latehalf[1]);
427 else if (CONSTANT_P (operands[1]))
429 /* ??? jrv: Can this really happen? A DImode constant
430 that isn't a CONST_DOUBLE? */
431 if (GET_CODE (operands[1]) == CONST_INT
432 && INTVAL (operands[1]) < 0)
433 latehalf[1] = constm1_rtx;
435 latehalf[1] = const0_rtx;
439 latehalf[1] = operands[1];
442 /* If insn is effectively movd N (sp),-(sp) then we will do the
443 high word first. We should use the adjusted operand 1 (which is N+4 (sp))
444 for the low word as well, to compensate for the first decrement of sp. */
445 if (optype0 == PUSHOP
446 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
447 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
448 operands[1] = latehalf[1];
450 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
451 if the upper part of reg N does not appear in the MEM, arrange to
452 emit the move late-half first. Otherwise, compute the MEM address
453 into the upper part of N and use that as a pointer to the memory
456 && (optype1 == OFFSOP || optype1 == MEMOP))
458 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
459 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
461 /* If both halves of dest are used in the src memory address,
462 compute the address into latehalf of dest. */
464 xops[0] = latehalf[0];
465 xops[1] = XEXP (operands[1], 0);
466 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
467 if( GET_MODE (operands[1]) == XFmode )
470 operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
471 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
472 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
476 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
477 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
481 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
483 /* Check for two regs used by both source and dest. */
484 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
485 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
488 /* JRV says this can't happen: */
489 if (addreg0 || addreg1)
492 /* Only the middle reg conflicts; simply put it last. */
493 output_asm_insn (singlemove_string (operands), operands);
494 output_asm_insn (singlemove_string (latehalf), latehalf);
495 output_asm_insn (singlemove_string (middlehalf), middlehalf);
498 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
499 /* If the low half of dest is mentioned in the source memory
500 address, the arrange to emit the move late half first. */
501 dest_overlapped_low = 1;
504 /* If one or both operands autodecrementing,
505 do the two words, high-numbered first. */
507 /* Likewise, the first move would clobber the source of the second one,
508 do them in the other order. This happens only for registers;
509 such overlap can't happen in memory unless the user explicitly
510 sets it up, and that is an undefined circumstance. */
513 if (optype0 == PUSHOP || optype1 == PUSHOP
514 || (optype0 == REGOP && optype1 == REGOP
515 && REGNO (operands[0]) == REGNO (latehalf[1]))
516 || dest_overlapped_low)
518 if (optype0 == PUSHOP || optype1 == PUSHOP
519 || (optype0 == REGOP && optype1 == REGOP
520 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
521 || REGNO (operands[0]) == REGNO (latehalf[1])))
522 || dest_overlapped_low)
524 /* Make any unoffsettable addresses point at high-numbered word. */
526 asm_add (size-4, addreg0);
528 asm_add (size-4, addreg1);
531 output_asm_insn (singlemove_string (latehalf), latehalf);
533 /* Undo the adds we just did. */
535 asm_add (-4, addreg0);
537 asm_add (-4, addreg1);
541 output_asm_insn (singlemove_string (middlehalf), middlehalf);
543 asm_add (-4, addreg0);
545 asm_add (-4, addreg1);
548 /* Do low-numbered word. */
549 return singlemove_string (operands);
552 /* Normal case: do the two words, low-numbered first. */
554 output_asm_insn (singlemove_string (operands), operands);
556 /* Do the middle one of the three words for long double */
560 asm_add (4, addreg0);
562 asm_add (4, addreg1);
564 output_asm_insn (singlemove_string (middlehalf), middlehalf);
567 /* Make any unoffsettable addresses point at high-numbered word. */
569 asm_add (4, addreg0);
571 asm_add (4, addreg1);
574 output_asm_insn (singlemove_string (latehalf), latehalf);
576 /* Undo the adds we just did. */
578 asm_add (4-size, addreg0);
580 asm_add (4-size, addreg1);
586 standard_80387_constant_p (x)
589 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
594 if (setjmp (handler))
597 set_float_handler (handler);
598 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
599 is0 = REAL_VALUES_EQUAL (d, dconst0);
600 is1 = REAL_VALUES_EQUAL (d, dconst1);
601 set_float_handler (NULL_PTR);
609 /* Note that on the 80387, other constants, such as pi,
610 are much slower to load as standard constants
611 than to load from doubles in memory! */
618 output_move_const_single (operands)
621 if (FP_REG_P (operands[0]))
623 int conval = standard_80387_constant_p (operands[1]);
631 if (GET_CODE (operands[1]) == CONST_DOUBLE)
633 REAL_VALUE_TYPE r; long l;
635 if (GET_MODE (operands[1]) == XFmode)
638 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
639 REAL_VALUE_TO_TARGET_SINGLE (r, l);
640 operands[1] = GEN_INT (l);
642 return singlemove_string (operands);
645 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
646 reference and a constant. */
649 symbolic_operand (op, mode)
651 enum machine_mode mode;
653 switch (GET_CODE (op))
660 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
661 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
662 && GET_CODE (XEXP (op, 1)) == CONST_INT);
668 /* Test for a valid operand for a call instruction.
669 Don't allow the arg pointer register or virtual regs
670 since they may change into reg + const, which the patterns
674 call_insn_operand (op, mode)
676 enum machine_mode mode;
678 if (GET_CODE (op) == MEM
679 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
680 /* This makes a difference for PIC. */
681 && general_operand (XEXP (op, 0), Pmode))
682 || (GET_CODE (XEXP (op, 0)) == REG
683 && XEXP (op, 0) != arg_pointer_rtx
684 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
685 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
690 /* Like call_insn_operand but allow (mem (symbol_ref ...))
694 expander_call_insn_operand (op, mode)
696 enum machine_mode mode;
698 if (GET_CODE (op) == MEM
699 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
700 || (GET_CODE (XEXP (op, 0)) == REG
701 && XEXP (op, 0) != arg_pointer_rtx
702 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
703 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
708 /* Returns 1 if OP contains a symbol reference */
711 symbolic_reference_mentioned_p (op)
717 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
720 fmt = GET_RTX_FORMAT (GET_CODE (op));
721 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
727 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
728 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
731 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
738 /* Return a legitimate reference for ORIG (an address) using the
739 register REG. If REG is 0, a new pseudo is generated.
741 There are three types of references that must be handled:
743 1. Global data references must load the address from the GOT, via
744 the PIC reg. An insn is emitted to do this load, and the reg is
747 2. Static data references must compute the address as an offset
748 from the GOT, whose base is in the PIC reg. An insn is emitted to
749 compute the address into a reg, and the reg is returned. Static
750 data objects have SYMBOL_REF_FLAG set to differentiate them from
753 3. Constant pool addresses must be handled special. They are
754 considered legitimate addresses, but only if not used with regs.
755 When printed, the output routines know to print the reference with the
756 PIC reg, even though the PIC reg doesn't appear in the RTL.
758 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
759 reg also appears in the address (except for constant pool references,
762 "switch" statements also require special handling when generating
763 PIC code. See comments by the `casesi' insn in i386.md for details. */
766 legitimize_pic_address (orig, reg)
773 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
775 if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
780 reg = gen_reg_rtx (Pmode);
782 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
783 new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
785 new = gen_rtx (MEM, Pmode,
786 gen_rtx (PLUS, Pmode,
787 pic_offset_table_rtx, orig));
789 emit_move_insn (reg, new);
791 current_function_uses_pic_offset_table = 1;
794 else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
798 if (GET_CODE (addr) == CONST)
800 addr = XEXP (addr, 0);
801 if (GET_CODE (addr) != PLUS)
805 if (XEXP (addr, 0) == pic_offset_table_rtx)
809 reg = gen_reg_rtx (Pmode);
811 base = legitimize_pic_address (XEXP (addr, 0), reg);
812 addr = legitimize_pic_address (XEXP (addr, 1),
813 base == reg ? NULL_RTX : reg);
815 if (GET_CODE (addr) == CONST_INT)
816 return plus_constant (base, INTVAL (addr));
818 if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
820 base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
821 addr = XEXP (addr, 1);
823 return gen_rtx (PLUS, Pmode, base, addr);
828 /* Emit insns to move operands[1] into operands[0]. */
831 emit_pic_move (operands, mode)
833 enum machine_mode mode;
835 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
837 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
838 operands[1] = (rtx) force_reg (SImode, operands[1]);
840 operands[1] = legitimize_pic_address (operands[1], temp);
843 /* This function generates the assembly code for function entry.
844 FILE is an stdio stream to output the code to.
845 SIZE is an int: how many units of temporary storage to allocate. */
848 function_prologue (file, size)
855 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
856 || current_function_uses_const_pool);
858 xops[0] = stack_pointer_rtx;
859 xops[1] = frame_pointer_rtx;
860 xops[2] = GEN_INT (size);
861 if (frame_pointer_needed)
863 output_asm_insn ("push%L1 %1", xops);
864 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
868 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
870 /* Note If use enter it is NOT reversed args.
871 This one is not reversed from intel!!
872 I think enter is slower. Also sdb doesn't like it.
873 But if you want it the code is:
875 xops[3] = const0_rtx;
876 output_asm_insn ("enter %2,%3", xops);
879 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
880 for (regno = limit - 1; regno >= 0; regno--)
881 if ((regs_ever_live[regno] && ! call_used_regs[regno])
882 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
884 xops[0] = gen_rtx (REG, SImode, regno);
885 output_asm_insn ("push%L0 %0", xops);
890 xops[0] = pic_offset_table_rtx;
891 xops[1] = (rtx) gen_label_rtx ();
893 output_asm_insn (AS1 (call,%P1), xops);
894 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1]));
895 output_asm_insn (AS1 (pop%L0,%0), xops);
896 output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
900 /* Return 1 if it is appropriate to emit `ret' instructions in the
901 body of a function. Do this only if the epilogue is simple, needing a
902 couple of insns. Prior to reloading, we can't tell how many registers
903 must be saved, so return 0 then.
905 If NON_SAVING_SETJMP is defined and true, then it is not possible
906 for the epilogue to be simple, so return 0. This is a special case
907 since NON_SAVING_SETJMP will not cause regs_ever_live to change until
908 final, but jump_optimize may need to know sooner if a `return' is OK. */
911 simple_386_epilogue ()
915 int reglimit = (frame_pointer_needed
916 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
917 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
918 || current_function_uses_const_pool);
920 #ifdef NON_SAVING_SETJMP
921 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
925 if (! reload_completed)
928 for (regno = reglimit - 1; regno >= 0; regno--)
929 if ((regs_ever_live[regno] && ! call_used_regs[regno])
930 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
933 return nregs == 0 || ! frame_pointer_needed;
936 /* This function generates the assembly code for function exit.
937 FILE is an stdio stream to output the code to.
938 SIZE is an int: how many units of temporary storage to deallocate. */
941 function_epilogue (file, size)
946 register int nregs, limit;
949 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
950 || current_function_uses_const_pool);
952 /* Compute the number of registers to pop */
954 limit = (frame_pointer_needed
955 ? FRAME_POINTER_REGNUM
956 : STACK_POINTER_REGNUM);
960 for (regno = limit - 1; regno >= 0; regno--)
961 if ((regs_ever_live[regno] && ! call_used_regs[regno])
962 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
965 /* sp is often unreliable so we must go off the frame pointer,
968 /* In reality, we may not care if sp is unreliable, because we can
969 restore the register relative to the frame pointer. In theory,
970 since each move is the same speed as a pop, and we don't need the
971 leal, this is faster. For now restore multiple registers the old
974 offset = -size - (nregs * UNITS_PER_WORD);
976 xops[2] = stack_pointer_rtx;
978 if (nregs > 1 || ! frame_pointer_needed)
980 if (frame_pointer_needed)
982 xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset);
983 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
986 for (regno = 0; regno < limit; regno++)
987 if ((regs_ever_live[regno] && ! call_used_regs[regno])
988 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
990 xops[0] = gen_rtx (REG, SImode, regno);
991 output_asm_insn ("pop%L0 %0", xops);
995 for (regno = 0; regno < limit; regno++)
996 if ((regs_ever_live[regno] && ! call_used_regs[regno])
997 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
999 xops[0] = gen_rtx (REG, SImode, regno);
1000 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
1001 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
1005 if (frame_pointer_needed)
1007 /* On i486, mov & pop is faster than "leave". */
1011 xops[0] = frame_pointer_rtx;
1012 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
1013 output_asm_insn ("pop%L0 %0", xops);
1016 output_asm_insn ("leave", xops);
1020 /* If there is no frame pointer, we must still release the frame. */
1022 xops[0] = GEN_INT (size);
1023 output_asm_insn (AS2 (add%L2,%0,%2), xops);
1026 if (current_function_pops_args && current_function_args_size)
1028 xops[1] = GEN_INT (current_function_pops_args);
1030 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
1031 asked to pop more, pop return address, do explicit add, and jump
1032 indirectly to the caller. */
1034 if (current_function_pops_args >= 32768)
1036 /* ??? Which register to use here? */
1037 xops[0] = gen_rtx (REG, SImode, 2);
1038 output_asm_insn ("pop%L0 %0", xops);
1039 output_asm_insn (AS2 (add%L2,%1,%2), xops);
1040 output_asm_insn ("jmp %*%0", xops);
1043 output_asm_insn ("ret %1", xops);
1046 output_asm_insn ("ret", xops);
1049 /* Print an integer constant expression in assembler syntax. Addition
1050 and subtraction are the only arithmetic that may appear in these
1051 expressions. FILE is the stdio stream to write to, X is the rtx, and
1052 CODE is the operand print code from the output string. */
1055 output_pic_addr_const (file, x, code)
1062 switch (GET_CODE (x))
1073 if (GET_CODE (x) == SYMBOL_REF)
1074 assemble_name (file, XSTR (x, 0));
1077 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
1078 CODE_LABEL_NUMBER (XEXP (x, 0)));
1079 assemble_name (asm_out_file, buf);
1082 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
1083 fprintf (file, "@GOTOFF(%%ebx)");
1084 else if (code == 'P')
1085 fprintf (file, "@PLT");
1086 else if (GET_CODE (x) == LABEL_REF || ! SYMBOL_REF_FLAG (x))
1087 fprintf (file, "@GOT");
1089 fprintf (file, "@GOTOFF");
1094 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
1095 assemble_name (asm_out_file, buf);
1099 fprintf (file, "%d", INTVAL (x));
1103 /* This used to output parentheses around the expression,
1104 but that does not work on the 386 (either ATT or BSD assembler). */
1105 output_pic_addr_const (file, XEXP (x, 0), code);
1109 if (GET_MODE (x) == VOIDmode)
1111 /* We can use %d if the number is <32 bits and positive. */
1112 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
1113 fprintf (file, "0x%x%08x",
1114 CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x));
1116 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
1119 /* We can't handle floating point constants;
1120 PRINT_OPERAND must handle them. */
1121 output_operand_lossage ("floating constant misused");
1125 /* Some assemblers need integer constants to appear last (eg masm). */
1126 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
1128 output_pic_addr_const (file, XEXP (x, 1), code);
1129 if (INTVAL (XEXP (x, 0)) >= 0)
1130 fprintf (file, "+");
1131 output_pic_addr_const (file, XEXP (x, 0), code);
1135 output_pic_addr_const (file, XEXP (x, 0), code);
1136 if (INTVAL (XEXP (x, 1)) >= 0)
1137 fprintf (file, "+");
1138 output_pic_addr_const (file, XEXP (x, 1), code);
1143 output_pic_addr_const (file, XEXP (x, 0), code);
1144 fprintf (file, "-");
1145 output_pic_addr_const (file, XEXP (x, 1), code);
1149 output_operand_lossage ("invalid expression as operand");
1154 f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
1155 D,L,W,B,Q,S -- print the opcode suffix for specified size of operand.
1156 R -- print the prefix for register names.
1157 z -- print the opcode suffix for the size of the current operand.
1158 * -- print a star (in certain assembler syntax)
1159 w -- print the operand as if it's a "word" (HImode) even if it isn't.
1160 c -- don't print special prefixes before constant operands.
1164 print_operand (file, x, code)
1179 PUT_OP_SIZE (code, 'l', file);
1183 PUT_OP_SIZE (code, 'w', file);
1187 PUT_OP_SIZE (code, 'b', file);
1191 PUT_OP_SIZE (code, 'l', file);
1195 PUT_OP_SIZE (code, 's', file);
1199 PUT_OP_SIZE (code, 't', file);
1203 /* 387 opcodes don't get size suffixes if the operands are
1206 if (STACK_REG_P (x))
1209 /* this is the size of op from size of operand */
1210 switch (GET_MODE_SIZE (GET_MODE (x)))
1213 PUT_OP_SIZE ('B', 'b', file);
1217 PUT_OP_SIZE ('W', 'w', file);
1221 if (GET_MODE (x) == SFmode)
1223 PUT_OP_SIZE ('S', 's', file);
1227 PUT_OP_SIZE ('L', 'l', file);
1231 PUT_OP_SIZE ('T', 't', file);
1235 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
1237 #ifdef GAS_MNEMONICS
1238 PUT_OP_SIZE ('Q', 'q', file);
1241 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
1245 PUT_OP_SIZE ('Q', 'l', file);
1261 sprintf (str, "invalid operand code `%c'", code);
1262 output_operand_lossage (str);
1266 if (GET_CODE (x) == REG)
1268 PRINT_REG (x, code, file);
1270 else if (GET_CODE (x) == MEM)
1272 PRINT_PTR (x, file);
1273 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
1276 output_pic_addr_const (file, XEXP (x, 0), code);
1278 output_addr_const (file, XEXP (x, 0));
1281 output_address (XEXP (x, 0));
1283 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
1285 REAL_VALUE_TYPE r; long l;
1286 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1287 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1288 PRINT_IMMED_PREFIX (file);
1289 fprintf (file, "0x%x", l);
1291 /* These float cases don't actually occur as immediate operands. */
1292 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
1294 REAL_VALUE_TYPE r; char dstr[30];
1295 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1296 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
1297 fprintf (file, "%s", dstr);
1299 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
1301 REAL_VALUE_TYPE r; char dstr[30];
1302 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1303 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
1304 fprintf (file, "%s", dstr);
1310 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
1311 PRINT_IMMED_PREFIX (file);
1312 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
1313 || GET_CODE (x) == LABEL_REF)
1314 PRINT_OFFSET_PREFIX (file);
1317 output_pic_addr_const (file, x, code);
1319 output_addr_const (file, x);
1323 /* Print a memory operand whose address is ADDR. */
1326 print_operand_address (file, addr)
1330 register rtx reg1, reg2, breg, ireg;
1333 switch (GET_CODE (addr))
1337 fprintf (file, "%se", RP);
1338 fputs (hi_reg_name[REGNO (addr)], file);
1348 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
1350 offset = XEXP (addr, 0);
1351 addr = XEXP (addr, 1);
1353 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
1355 offset = XEXP (addr, 1);
1356 addr = XEXP (addr, 0);
1358 if (GET_CODE (addr) != PLUS) ;
1359 else if (GET_CODE (XEXP (addr, 0)) == MULT)
1361 reg1 = XEXP (addr, 0);
1362 addr = XEXP (addr, 1);
1364 else if (GET_CODE (XEXP (addr, 1)) == MULT)
1366 reg1 = XEXP (addr, 1);
1367 addr = XEXP (addr, 0);
1369 else if (GET_CODE (XEXP (addr, 0)) == REG)
1371 reg1 = XEXP (addr, 0);
1372 addr = XEXP (addr, 1);
1374 else if (GET_CODE (XEXP (addr, 1)) == REG)
1376 reg1 = XEXP (addr, 1);
1377 addr = XEXP (addr, 0);
1379 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
1381 if (reg1 == 0) reg1 = addr;
1387 if (addr != 0) abort ();
1390 if ((reg1 && GET_CODE (reg1) == MULT)
1391 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
1396 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
1402 if (ireg != 0 || breg != 0)
1408 if (GET_CODE (addr) == LABEL_REF)
1409 output_asm_label (addr);
1413 output_pic_addr_const (file, addr, 0);
1415 output_addr_const (file, addr);
1419 if (ireg != 0 && GET_CODE (ireg) == MULT)
1421 scale = INTVAL (XEXP (ireg, 1));
1422 ireg = XEXP (ireg, 0);
1425 /* The stack pointer can only appear as a base register,
1426 never an index register, so exchange the regs if it is wrong. */
1428 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
1437 /* output breg+ireg*scale */
1438 PRINT_B_I_S (breg, ireg, scale, file);
1445 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
1447 scale = INTVAL (XEXP (addr, 0));
1448 ireg = XEXP (addr, 1);
1452 scale = INTVAL (XEXP (addr, 1));
1453 ireg = XEXP (addr, 0);
1455 output_addr_const (file, const0_rtx);
1456 PRINT_B_I_S ((rtx) 0, ireg, scale, file);
1461 if (GET_CODE (addr) == CONST_INT
1462 && INTVAL (addr) < 0x8000
1463 && INTVAL (addr) >= -0x8000)
1464 fprintf (file, "%d", INTVAL (addr));
1468 output_pic_addr_const (file, addr, 0);
1470 output_addr_const (file, addr);
1475 /* Set the cc_status for the results of an insn whose pattern is EXP.
1476 On the 80386, we assume that only test and compare insns, as well
1477 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, LSHIFT,
1478 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
1479 Also, we assume that jumps, moves and sCOND don't affect the condition
1480 codes. All else clobbers the condition codes, by assumption.
1482 We assume that ALL integer add, minus, etc. instructions effect the
1483 condition codes. This MUST be consistent with i386.md.
1485 We don't record any float test or compare - the redundant test &
1486 compare check in final.c does not handle stack-like regs correctly. */
1489 notice_update_cc (exp)
1492 if (GET_CODE (exp) == SET)
1494 /* Jumps do not alter the cc's. */
1495 if (SET_DEST (exp) == pc_rtx)
1497 /* Moving register or memory into a register:
1498 it doesn't alter the cc's, but it might invalidate
1499 the RTX's which we remember the cc's came from.
1500 (Note that moving a constant 0 or 1 MAY set the cc's). */
1501 if (REG_P (SET_DEST (exp))
1502 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
1503 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
1505 if (cc_status.value1
1506 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
1507 cc_status.value1 = 0;
1508 if (cc_status.value2
1509 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
1510 cc_status.value2 = 0;
1513 /* Moving register into memory doesn't alter the cc's.
1514 It may invalidate the RTX's which we remember the cc's came from. */
1515 if (GET_CODE (SET_DEST (exp)) == MEM
1516 && (REG_P (SET_SRC (exp))
1517 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
1519 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM)
1520 cc_status.value1 = 0;
1521 if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM)
1522 cc_status.value2 = 0;
1525 /* Function calls clobber the cc's. */
1526 else if (GET_CODE (SET_SRC (exp)) == CALL)
1531 /* Tests and compares set the cc's in predictable ways. */
1532 else if (SET_DEST (exp) == cc0_rtx)
1535 cc_status.value1 = SET_SRC (exp);
1538 /* Certain instructions effect the condition codes. */
1539 else if (GET_MODE (SET_SRC (exp)) == SImode
1540 || GET_MODE (SET_SRC (exp)) == HImode
1541 || GET_MODE (SET_SRC (exp)) == QImode)
1542 switch (GET_CODE (SET_SRC (exp)))
1544 case ASHIFTRT: case LSHIFTRT:
1545 case ASHIFT: case LSHIFT:
1546 /* Shifts on the 386 don't set the condition codes if the
1547 shift count is zero. */
1548 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
1553 /* We assume that the CONST_INT is non-zero (this rtx would
1554 have been deleted if it were zero. */
1556 case PLUS: case MINUS: case NEG:
1557 case AND: case IOR: case XOR:
1558 cc_status.flags = CC_NO_OVERFLOW;
1559 cc_status.value1 = SET_SRC (exp);
1560 cc_status.value2 = SET_DEST (exp);
1571 else if (GET_CODE (exp) == PARALLEL
1572 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
1574 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
1576 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
1579 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
1580 cc_status.flags |= CC_IN_80387;
1582 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
1593 /* Split one or more DImode RTL references into pairs of SImode
1594 references. The RTL can be REG, offsettable MEM, integer constant, or
1595 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
1596 split and "num" is its length. lo_half and hi_half are output arrays
1597 that parallel "operands". */
1600 split_di (operands, num, lo_half, hi_half)
1603 rtx lo_half[], hi_half[];
1607 if (GET_CODE (operands[num]) == REG)
1609 lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
1610 hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
1612 else if (CONSTANT_P (operands[num]))
1614 split_double (operands[num], &lo_half[num], &hi_half[num]);
1616 else if (offsettable_memref_p (operands[num]))
1618 lo_half[num] = operands[num];
1619 hi_half[num] = adj_offsettable_operand (operands[num], 4);
1626 /* Return 1 if this is a valid binary operation on a 387.
1627 OP is the expression matched, and MODE is its mode. */
1630 binary_387_op (op, mode)
1632 enum machine_mode mode;
1634 if (mode != VOIDmode && mode != GET_MODE (op))
1637 switch (GET_CODE (op))
1643 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
1650 /* Return 1 if this is a valid conversion operation on a 387.
1651 OP is the expression matched, and MODE is its mode. */
1654 convert_387_op (op, mode)
1656 enum machine_mode mode;
1658 if (mode != VOIDmode && mode != GET_MODE (op))
1661 switch (GET_CODE (op))
1664 return GET_MODE (XEXP (op, 0)) == SImode;
1667 return ((mode == DFmode && GET_MODE (XEXP (op, 0)) == SFmode)
1668 || (mode == XFmode && GET_MODE (XEXP (op, 0)) == DFmode)
1669 || (mode == XFmode && GET_MODE (XEXP (op, 0)) == SFmode));
1676 /* Return 1 if this is a valid shift or rotate operation on a 386.
1677 OP is the expression matched, and MODE is its mode. */
1682 enum machine_mode mode;
1684 rtx operand = XEXP (op, 0);
1686 if (mode != VOIDmode && mode != GET_MODE (op))
1689 if (GET_MODE (operand) != GET_MODE (op)
1690 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
1693 return (GET_CODE (op) == ASHIFT
1694 || GET_CODE (op) == ASHIFTRT
1695 || GET_CODE (op) == LSHIFTRT
1696 || GET_CODE (op) == ROTATE
1697 || GET_CODE (op) == ROTATERT);
1700 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
1701 MODE is not used. */
1704 VOIDmode_compare_op (op, mode)
1706 enum machine_mode mode;
1708 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
1711 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
1712 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
1713 is the expression of the binary operation. The output may either be
1714 emitted here, or returned to the caller, like all output_* functions.
1716 There is no guarantee that the operands are the same mode, as they
1717 might be within FLOAT or FLOAT_EXTEND expressions. */
1720 output_387_binary_op (insn, operands)
1726 static char buf[100];
1728 switch (GET_CODE (operands[3]))
1731 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1732 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
1739 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1740 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
1747 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1748 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
1755 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1756 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
1766 strcpy (buf, base_op);
1768 switch (GET_CODE (operands[3]))
1772 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
1775 operands[2] = operands[1];
1779 if (GET_CODE (operands[2]) == MEM)
1780 return strcat (buf, AS1 (%z2,%2));
1782 if (NON_STACK_REG_P (operands[1]))
1784 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
1787 else if (NON_STACK_REG_P (operands[2]))
1789 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
1793 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
1794 return strcat (buf, AS2 (p,%2,%0));
1796 if (STACK_TOP_P (operands[0]))
1797 return strcat (buf, AS2 (,%y2,%0));
1799 return strcat (buf, AS2 (,%2,%0));
1803 if (GET_CODE (operands[1]) == MEM)
1804 return strcat (buf, AS1 (r%z1,%1));
1806 if (GET_CODE (operands[2]) == MEM)
1807 return strcat (buf, AS1 (%z2,%2));
1809 if (NON_STACK_REG_P (operands[1]))
1811 output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
1814 else if (NON_STACK_REG_P (operands[2]))
1816 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
1820 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
1823 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
1824 return strcat (buf, AS2 (rp,%2,%0));
1826 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1827 return strcat (buf, AS2 (p,%1,%0));
1829 if (STACK_TOP_P (operands[0]))
1831 if (STACK_TOP_P (operands[1]))
1832 return strcat (buf, AS2 (,%y2,%0));
1834 return strcat (buf, AS2 (r,%y1,%0));
1836 else if (STACK_TOP_P (operands[1]))
1837 return strcat (buf, AS2 (,%1,%0));
1839 return strcat (buf, AS2 (r,%2,%0));
1846 /* Output code for INSN to convert a float to a signed int. OPERANDS
1847 are the insn operands. The output may be SFmode or DFmode and the
1848 input operand may be SImode or DImode. As a special case, make sure
1849 that the 387 stack top dies if the output mode is DImode, because the
1850 hardware requires this. */
1853 output_fix_trunc (insn, operands)
1857 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1860 if (! STACK_TOP_P (operands[1]) ||
1861 (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
1864 xops[0] = GEN_INT (12);
1865 xops[1] = operands[4];
1867 output_asm_insn (AS1 (fnstc%W2,%2), operands);
1868 output_asm_insn (AS2 (mov%L2,%2,%4), operands);
1869 output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
1870 output_asm_insn (AS2 (mov%L4,%4,%3), operands);
1871 output_asm_insn (AS1 (fldc%W3,%3), operands);
1873 if (NON_STACK_REG_P (operands[0]))
1874 output_to_reg (operands[0], stack_top_dies);
1875 else if (GET_CODE (operands[0]) == MEM)
1878 output_asm_insn (AS1 (fistp%z0,%0), operands);
1880 output_asm_insn (AS1 (fist%z0,%0), operands);
1885 return AS1 (fldc%W2,%2);
1888 /* Output code for INSN to compare OPERANDS. The two operands might
1889 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
1890 expression. If the compare is in mode CCFPEQmode, use an opcode that
1891 will not fault if a qNaN is present. */
1894 output_float_compare (insn, operands)
1899 rtx body = XVECEXP (PATTERN (insn), 0, 0);
1900 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
1902 if (! STACK_TOP_P (operands[0]))
1905 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1907 if (STACK_REG_P (operands[1])
1909 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
1910 && REGNO (operands[1]) != FIRST_STACK_REG)
1912 /* If both the top of the 387 stack dies, and the other operand
1913 is also a stack register that dies, then this must be a
1914 `fcompp' float compare */
1916 if (unordered_compare)
1917 output_asm_insn ("fucompp", operands);
1919 output_asm_insn ("fcompp", operands);
1923 static char buf[100];
1925 /* Decide if this is the integer or float compare opcode, or the
1926 unordered float compare. */
1928 if (unordered_compare)
1929 strcpy (buf, "fucom");
1930 else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
1931 strcpy (buf, "fcom");
1933 strcpy (buf, "ficom");
1935 /* Modify the opcode if the 387 stack is to be popped. */
1940 if (NON_STACK_REG_P (operands[1]))
1941 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
1943 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
1946 /* Now retrieve the condition code. */
1948 return output_fp_cc0_set (insn);
1951 /* Output opcodes to transfer the results of FP compare or test INSN
1952 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
1953 result of the compare or test is unordered, no comparison operator
1954 succeeds except NE. Return an output template, if any. */
1957 output_fp_cc0_set (insn)
1961 rtx unordered_label;
1965 xops[0] = gen_rtx (REG, HImode, 0);
1966 output_asm_insn (AS1 (fnsts%W0,%0), xops);
1968 if (! TARGET_IEEE_FP)
1971 next = next_cc0_user (insn);
1972 if (next == NULL_RTX)
1975 if (GET_CODE (next) == JUMP_INSN
1976 && GET_CODE (PATTERN (next)) == SET
1977 && SET_DEST (PATTERN (next)) == pc_rtx
1978 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
1980 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
1982 else if (GET_CODE (PATTERN (next)) == SET)
1984 code = GET_CODE (SET_SRC (PATTERN (next)));
1989 xops[0] = gen_rtx (REG, QImode, 0);
1994 xops[1] = GEN_INT (0x45);
1995 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2000 xops[1] = GEN_INT (0x45);
2001 xops[2] = GEN_INT (0x01);
2002 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2003 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
2008 xops[1] = GEN_INT (0x05);
2009 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2014 xops[1] = GEN_INT (0x45);
2015 xops[2] = GEN_INT (0x40);
2016 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2017 output_asm_insn (AS1 (dec%B0,%h0), xops);
2018 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
2023 xops[1] = GEN_INT (0x45);
2024 xops[2] = GEN_INT (0x40);
2025 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2026 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
2031 xops[1] = GEN_INT (0x44);
2032 xops[2] = GEN_INT (0x40);
2033 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2034 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
2048 #define MAX_386_STACK_LOCALS 2
2050 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
2052 /* Clear stack slot assignments remembered from previous functions.
2053 This is called from INIT_EXPANDERS once before RTL is emitted for each
2057 clear_386_stack_locals ()
2059 enum machine_mode mode;
2062 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
2063 mode = (enum machine_mode) ((int) mode + 1))
2064 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
2065 i386_stack_locals[(int) mode][n] = NULL_RTX;
2068 /* Return a MEM corresponding to a stack slot with mode MODE.
2069 Allocate a new slot if necessary.
2071 The RTL for a function can have several slots available: N is
2072 which slot to use. */
2075 assign_386_stack_local (mode, n)
2076 enum machine_mode mode;
2079 if (n < 0 || n >= MAX_386_STACK_LOCALS)
2082 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
2083 i386_stack_locals[(int) mode][n]
2084 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
2086 return i386_stack_locals[(int) mode][n];