1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1557 /* X86_ARCH_CALL_ESP: P6 processors will jump to the address after
1558 the decrement (so they will execute return address as code). See
1559 Pentium Pro errata 70, Pentium 2 errata A33, Pentium 3 errata E17. */
1560 ~(m_386 | m_486 | m_PENT | m_PPRO),
1563 static const unsigned int x86_accumulate_outgoing_args
1564 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1567 static const unsigned int x86_arch_always_fancy_math_387
1568 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1569 | m_NOCONA | m_CORE2 | m_GENERIC;
1571 static enum stringop_alg stringop_alg = no_stringop;
1573 /* In case the average insn count for single function invocation is
1574 lower than this constant, emit fast (but longer) prologue and
1576 #define FAST_PROLOGUE_INSN_COUNT 20
1578 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1579 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1580 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1581 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1583 /* Array of the smallest class containing reg number REGNO, indexed by
1584 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1586 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1588 /* ax, dx, cx, bx */
1589 AREG, DREG, CREG, BREG,
1590 /* si, di, bp, sp */
1591 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1593 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1594 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1597 /* flags, fpsr, fpcr, frame */
1598 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1600 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1603 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1606 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1607 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1608 /* SSE REX registers */
1609 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1613 /* The "default" register map used in 32bit mode. */
1615 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1617 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1618 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1619 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1620 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1621 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1622 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1623 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1626 /* The "default" register map used in 64bit mode. */
1628 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1630 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1631 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1632 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1633 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1634 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1635 8,9,10,11,12,13,14,15, /* extended integer registers */
1636 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1639 /* Define the register numbers to be used in Dwarf debugging information.
1640 The SVR4 reference port C compiler uses the following register numbers
1641 in its Dwarf output code:
1642 0 for %eax (gcc regno = 0)
1643 1 for %ecx (gcc regno = 2)
1644 2 for %edx (gcc regno = 1)
1645 3 for %ebx (gcc regno = 3)
1646 4 for %esp (gcc regno = 7)
1647 5 for %ebp (gcc regno = 6)
1648 6 for %esi (gcc regno = 4)
1649 7 for %edi (gcc regno = 5)
1650 The following three DWARF register numbers are never generated by
1651 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1652 believes these numbers have these meanings.
1653 8 for %eip (no gcc equivalent)
1654 9 for %eflags (gcc regno = 17)
1655 10 for %trapno (no gcc equivalent)
1656 It is not at all clear how we should number the FP stack registers
1657 for the x86 architecture. If the version of SDB on x86/svr4 were
1658 a bit less brain dead with respect to floating-point then we would
1659 have a precedent to follow with respect to DWARF register numbers
1660 for x86 FP registers, but the SDB on x86/svr4 is so completely
1661 broken with respect to FP registers that it is hardly worth thinking
1662 of it as something to strive for compatibility with.
1663 The version of x86/svr4 SDB I have at the moment does (partially)
1664 seem to believe that DWARF register number 11 is associated with
1665 the x86 register %st(0), but that's about all. Higher DWARF
1666 register numbers don't seem to be associated with anything in
1667 particular, and even for DWARF regno 11, SDB only seems to under-
1668 stand that it should say that a variable lives in %st(0) (when
1669 asked via an `=' command) if we said it was in DWARF regno 11,
1670 but SDB still prints garbage when asked for the value of the
1671 variable in question (via a `/' command).
1672 (Also note that the labels SDB prints for various FP stack regs
1673 when doing an `x' command are all wrong.)
1674 Note that these problems generally don't affect the native SVR4
1675 C compiler because it doesn't allow the use of -O with -g and
1676 because when it is *not* optimizing, it allocates a memory
1677 location for each floating-point variable, and the memory
1678 location is what gets described in the DWARF AT_location
1679 attribute for the variable in question.
1680 Regardless of the severe mental illness of the x86/svr4 SDB, we
1681 do something sensible here and we use the following DWARF
1682 register numbers. Note that these are all stack-top-relative
1684 11 for %st(0) (gcc regno = 8)
1685 12 for %st(1) (gcc regno = 9)
1686 13 for %st(2) (gcc regno = 10)
1687 14 for %st(3) (gcc regno = 11)
1688 15 for %st(4) (gcc regno = 12)
1689 16 for %st(5) (gcc regno = 13)
1690 17 for %st(6) (gcc regno = 14)
1691 18 for %st(7) (gcc regno = 15)
1693 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1695 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1696 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1697 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1698 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1699 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1700 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1701 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1704 /* Test and compare insns in i386.md store the information needed to
1705 generate branch and scc insns here. */
1707 rtx ix86_compare_op0 = NULL_RTX;
1708 rtx ix86_compare_op1 = NULL_RTX;
1710 /* Define parameter passing and return registers. */
1712 static int const x86_64_int_parameter_registers[6] =
1714 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1717 static int const x86_64_ms_abi_int_parameter_registers[4] =
1719 CX_REG, DX_REG, R8_REG, R9_REG
1722 static int const x86_64_int_return_registers[4] =
1724 AX_REG, DX_REG, DI_REG, SI_REG
1727 /* Define the structure for the machine field in struct function. */
1729 struct GTY(()) stack_local_entry {
1730 unsigned short mode;
1733 struct stack_local_entry *next;
1736 /* Structure describing stack frame layout.
1737 Stack grows downward:
1743 saved frame pointer if frame_pointer_needed
1744 <- HARD_FRAME_POINTER
1753 [va_arg registers] (
1754 > to_allocate <- FRAME_POINTER
1766 HOST_WIDE_INT frame;
1768 int outgoing_arguments_size;
1771 HOST_WIDE_INT to_allocate;
1772 /* The offsets relative to ARG_POINTER. */
1773 HOST_WIDE_INT frame_pointer_offset;
1774 HOST_WIDE_INT hard_frame_pointer_offset;
1775 HOST_WIDE_INT stack_pointer_offset;
1777 /* When save_regs_using_mov is set, emit prologue using
1778 move instead of push instructions. */
1779 bool save_regs_using_mov;
1782 /* Code model option. */
1783 enum cmodel ix86_cmodel;
1785 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1787 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1789 /* Which unit we are generating floating point math for. */
1790 enum fpmath_unit ix86_fpmath;
1792 /* Which cpu are we scheduling for. */
1793 enum attr_cpu ix86_schedule;
1795 /* Which cpu are we optimizing for. */
1796 enum processor_type ix86_tune;
1798 /* Which instruction set architecture to use. */
1799 enum processor_type ix86_arch;
1801 /* true if sse prefetch instruction is not NOOP. */
1802 int x86_prefetch_sse;
1804 /* ix86_regparm_string as a number */
1805 static int ix86_regparm;
1807 /* -mstackrealign option */
1808 extern int ix86_force_align_arg_pointer;
1809 static const char ix86_force_align_arg_pointer_string[]
1810 = "force_align_arg_pointer";
1812 static rtx (*ix86_gen_leave) (void);
1813 static rtx (*ix86_gen_pop1) (rtx);
1814 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1815 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1816 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1817 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1818 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1819 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1821 /* Preferred alignment for stack boundary in bits. */
1822 unsigned int ix86_preferred_stack_boundary;
1824 /* Alignment for incoming stack boundary in bits specified at
1826 static unsigned int ix86_user_incoming_stack_boundary;
1828 /* Default alignment for incoming stack boundary in bits. */
1829 static unsigned int ix86_default_incoming_stack_boundary;
1831 /* Alignment for incoming stack boundary in bits. */
1832 unsigned int ix86_incoming_stack_boundary;
1834 /* The abi used by target. */
1835 enum calling_abi ix86_abi;
1837 /* Values 1-5: see jump.c */
1838 int ix86_branch_cost;
1840 /* Calling abi specific va_list type nodes. */
1841 static GTY(()) tree sysv_va_list_type_node;
1842 static GTY(()) tree ms_va_list_type_node;
1844 /* Variables which are this size or smaller are put in the data/bss
1845 or ldata/lbss sections. */
1847 int ix86_section_threshold = 65536;
1849 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1850 char internal_label_prefix[16];
1851 int internal_label_prefix_len;
1853 /* Fence to use after loop using movnt. */
1856 /* Register class used for passing given 64bit part of the argument.
1857 These represent classes as documented by the PS ABI, with the exception
1858 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1859 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1861 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1862 whenever possible (upper half does contain padding). */
1863 enum x86_64_reg_class
1866 X86_64_INTEGER_CLASS,
1867 X86_64_INTEGERSI_CLASS,
1874 X86_64_COMPLEX_X87_CLASS,
1878 #define MAX_CLASSES 4
1880 /* Table of constants used by fldpi, fldln2, etc.... */
1881 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1882 static bool ext_80387_constants_init = 0;
1885 static struct machine_function * ix86_init_machine_status (void);
1886 static rtx ix86_function_value (const_tree, const_tree, bool);
1887 static rtx ix86_static_chain (const_tree, bool);
1888 static int ix86_function_regparm (const_tree, const_tree);
1889 static void ix86_compute_frame_layout (struct ix86_frame *);
1890 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1892 static void ix86_add_new_builtins (int);
1894 enum ix86_function_specific_strings
1896 IX86_FUNCTION_SPECIFIC_ARCH,
1897 IX86_FUNCTION_SPECIFIC_TUNE,
1898 IX86_FUNCTION_SPECIFIC_FPMATH,
1899 IX86_FUNCTION_SPECIFIC_MAX
1902 static char *ix86_target_string (int, int, const char *, const char *,
1903 const char *, bool);
1904 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1905 static void ix86_function_specific_save (struct cl_target_option *);
1906 static void ix86_function_specific_restore (struct cl_target_option *);
1907 static void ix86_function_specific_print (FILE *, int,
1908 struct cl_target_option *);
1909 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1910 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1911 static bool ix86_can_inline_p (tree, tree);
1912 static void ix86_set_current_function (tree);
1913 static unsigned int ix86_minimum_incoming_stack_boundary (bool);
1915 static enum calling_abi ix86_function_abi (const_tree);
1918 /* The svr4 ABI for the i386 says that records and unions are returned
1920 #ifndef DEFAULT_PCC_STRUCT_RETURN
1921 #define DEFAULT_PCC_STRUCT_RETURN 1
1924 /* Whether -mtune= or -march= were specified */
1925 static int ix86_tune_defaulted;
1926 static int ix86_arch_specified;
1928 /* Bit flags that specify the ISA we are compiling for. */
1929 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1931 /* A mask of ix86_isa_flags that includes bit X if X
1932 was set or cleared on the command line. */
1933 static int ix86_isa_flags_explicit;
1935 /* Define a set of ISAs which are available when a given ISA is
1936 enabled. MMX and SSE ISAs are handled separately. */
1938 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1939 #define OPTION_MASK_ISA_3DNOW_SET \
1940 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1942 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1943 #define OPTION_MASK_ISA_SSE2_SET \
1944 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1945 #define OPTION_MASK_ISA_SSE3_SET \
1946 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1947 #define OPTION_MASK_ISA_SSSE3_SET \
1948 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1949 #define OPTION_MASK_ISA_SSE4_1_SET \
1950 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1951 #define OPTION_MASK_ISA_SSE4_2_SET \
1952 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1953 #define OPTION_MASK_ISA_AVX_SET \
1954 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1955 #define OPTION_MASK_ISA_FMA_SET \
1956 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1958 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1960 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1962 #define OPTION_MASK_ISA_SSE4A_SET \
1963 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1964 #define OPTION_MASK_ISA_FMA4_SET \
1965 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
1966 | OPTION_MASK_ISA_AVX_SET)
1967 #define OPTION_MASK_ISA_XOP_SET \
1968 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
1969 #define OPTION_MASK_ISA_LWP_SET \
1972 /* AES and PCLMUL need SSE2 because they use xmm registers */
1973 #define OPTION_MASK_ISA_AES_SET \
1974 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1975 #define OPTION_MASK_ISA_PCLMUL_SET \
1976 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1978 #define OPTION_MASK_ISA_ABM_SET \
1979 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1981 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1982 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1983 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1984 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1985 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1987 /* Define a set of ISAs which aren't available when a given ISA is
1988 disabled. MMX and SSE ISAs are handled separately. */
1990 #define OPTION_MASK_ISA_MMX_UNSET \
1991 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1992 #define OPTION_MASK_ISA_3DNOW_UNSET \
1993 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1994 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1996 #define OPTION_MASK_ISA_SSE_UNSET \
1997 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1998 #define OPTION_MASK_ISA_SSE2_UNSET \
1999 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2000 #define OPTION_MASK_ISA_SSE3_UNSET \
2001 (OPTION_MASK_ISA_SSE3 \
2002 | OPTION_MASK_ISA_SSSE3_UNSET \
2003 | OPTION_MASK_ISA_SSE4A_UNSET )
2004 #define OPTION_MASK_ISA_SSSE3_UNSET \
2005 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2006 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2007 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2008 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2009 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2010 #define OPTION_MASK_ISA_AVX_UNSET \
2011 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2012 | OPTION_MASK_ISA_FMA4_UNSET)
2013 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2015 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2017 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2019 #define OPTION_MASK_ISA_SSE4A_UNSET \
2020 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2022 #define OPTION_MASK_ISA_FMA4_UNSET \
2023 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2024 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2025 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2027 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2028 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2029 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2030 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2031 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2032 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2033 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2034 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2036 /* Vectorization library interface and handlers. */
2037 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2038 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2039 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2041 /* Processor target table, indexed by processor number */
2044 const struct processor_costs *cost; /* Processor costs */
2045 const int align_loop; /* Default alignments. */
2046 const int align_loop_max_skip;
2047 const int align_jump;
2048 const int align_jump_max_skip;
2049 const int align_func;
2052 static const struct ptt processor_target_table[PROCESSOR_max] =
2054 {&i386_cost, 4, 3, 4, 3, 4},
2055 {&i486_cost, 16, 15, 16, 15, 16},
2056 {&pentium_cost, 16, 7, 16, 7, 16},
2057 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2058 {&geode_cost, 0, 0, 0, 0, 0},
2059 {&k6_cost, 32, 7, 32, 7, 32},
2060 {&athlon_cost, 16, 7, 16, 7, 16},
2061 {&pentium4_cost, 0, 0, 0, 0, 0},
2062 {&k8_cost, 16, 7, 16, 7, 16},
2063 {&nocona_cost, 0, 0, 0, 0, 0},
2064 {&core2_cost, 16, 10, 16, 10, 16},
2065 {&generic32_cost, 16, 7, 16, 7, 16},
2066 {&generic64_cost, 16, 10, 16, 10, 16},
2067 {&amdfam10_cost, 32, 24, 32, 7, 32},
2068 {&atom_cost, 16, 7, 16, 7, 16}
2071 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2097 /* Implement TARGET_HANDLE_OPTION. */
2100 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2107 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2108 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2112 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2113 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2120 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2121 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2125 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2136 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2141 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2149 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2154 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2162 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2167 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2175 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2180 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2188 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2193 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2201 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2206 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2207 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2214 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2219 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2220 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2227 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2228 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2232 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2233 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2238 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2239 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2243 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2244 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2250 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2251 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2255 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2256 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2263 ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
2264 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
2268 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
2269 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
2276 ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
2277 ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
2281 ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
2282 ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
2289 ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
2290 ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
2294 ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
2295 ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
2302 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2303 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2307 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2308 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2315 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2316 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2320 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2321 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2328 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2329 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2333 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2334 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2341 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2342 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2346 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2347 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2354 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2355 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2359 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2360 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2367 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2368 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2372 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2373 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2380 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2381 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2385 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2386 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2393 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2394 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2398 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2399 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2408 /* Return a string the documents the current -m options. The caller is
2409 responsible for freeing the string. */
2412 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2413 const char *fpmath, bool add_nl_p)
2415 struct ix86_target_opts
2417 const char *option; /* option string */
2418 int mask; /* isa mask options */
2421 /* This table is ordered so that options like -msse4.2 that imply
2422 preceding options while match those first. */
2423 static struct ix86_target_opts isa_opts[] =
2425 { "-m64", OPTION_MASK_ISA_64BIT },
2426 { "-mfma4", OPTION_MASK_ISA_FMA4 },
2427 { "-mxop", OPTION_MASK_ISA_XOP },
2428 { "-mlwp", OPTION_MASK_ISA_LWP },
2429 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2430 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2431 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2432 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2433 { "-msse3", OPTION_MASK_ISA_SSE3 },
2434 { "-msse2", OPTION_MASK_ISA_SSE2 },
2435 { "-msse", OPTION_MASK_ISA_SSE },
2436 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2437 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2438 { "-mmmx", OPTION_MASK_ISA_MMX },
2439 { "-mabm", OPTION_MASK_ISA_ABM },
2440 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2441 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2442 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2443 { "-maes", OPTION_MASK_ISA_AES },
2444 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2448 static struct ix86_target_opts flag_opts[] =
2450 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2451 { "-m80387", MASK_80387 },
2452 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2453 { "-malign-double", MASK_ALIGN_DOUBLE },
2454 { "-mcld", MASK_CLD },
2455 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2456 { "-mieee-fp", MASK_IEEE_FP },
2457 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2458 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2459 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2460 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2461 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2462 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2463 { "-mno-red-zone", MASK_NO_RED_ZONE },
2464 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2465 { "-mrecip", MASK_RECIP },
2466 { "-mrtd", MASK_RTD },
2467 { "-msseregparm", MASK_SSEREGPARM },
2468 { "-mstack-arg-probe", MASK_STACK_PROBE },
2469 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2472 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2475 char target_other[40];
2484 memset (opts, '\0', sizeof (opts));
2486 /* Add -march= option. */
2489 opts[num][0] = "-march=";
2490 opts[num++][1] = arch;
2493 /* Add -mtune= option. */
2496 opts[num][0] = "-mtune=";
2497 opts[num++][1] = tune;
2500 /* Pick out the options in isa options. */
2501 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2503 if ((isa & isa_opts[i].mask) != 0)
2505 opts[num++][0] = isa_opts[i].option;
2506 isa &= ~ isa_opts[i].mask;
2510 if (isa && add_nl_p)
2512 opts[num++][0] = isa_other;
2513 sprintf (isa_other, "(other isa: 0x%x)", isa);
2516 /* Add flag options. */
2517 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2519 if ((flags & flag_opts[i].mask) != 0)
2521 opts[num++][0] = flag_opts[i].option;
2522 flags &= ~ flag_opts[i].mask;
2526 if (flags && add_nl_p)
2528 opts[num++][0] = target_other;
2529 sprintf (target_other, "(other flags: 0x%x)", isa);
2532 /* Add -fpmath= option. */
2535 opts[num][0] = "-mfpmath=";
2536 opts[num++][1] = fpmath;
2543 gcc_assert (num < ARRAY_SIZE (opts));
2545 /* Size the string. */
2547 sep_len = (add_nl_p) ? 3 : 1;
2548 for (i = 0; i < num; i++)
2551 for (j = 0; j < 2; j++)
2553 len += strlen (opts[i][j]);
2556 /* Build the string. */
2557 ret = ptr = (char *) xmalloc (len);
2560 for (i = 0; i < num; i++)
2564 for (j = 0; j < 2; j++)
2565 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2572 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2580 for (j = 0; j < 2; j++)
2583 memcpy (ptr, opts[i][j], len2[j]);
2585 line_len += len2[j];
2590 gcc_assert (ret + len >= ptr);
2595 /* Function that is callable from the debugger to print the current
2598 ix86_debug_options (void)
2600 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2601 ix86_arch_string, ix86_tune_string,
2602 ix86_fpmath_string, true);
2606 fprintf (stderr, "%s\n\n", opts);
2610 fputs ("<no options>\n\n", stderr);
2615 /* Sometimes certain combinations of command options do not make
2616 sense on a particular target machine. You can define a macro
2617 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2618 defined, is executed once just after all the command options have
2621 Don't use this macro to turn on various extra optimizations for
2622 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2625 override_options (bool main_args_p)
2628 unsigned int ix86_arch_mask, ix86_tune_mask;
2633 /* Comes from final.c -- no real reason to change it. */
2634 #define MAX_CODE_ALIGN 16
2642 PTA_PREFETCH_SSE = 1 << 4,
2644 PTA_3DNOW_A = 1 << 6,
2648 PTA_POPCNT = 1 << 10,
2650 PTA_SSE4A = 1 << 12,
2651 PTA_NO_SAHF = 1 << 13,
2652 PTA_SSE4_1 = 1 << 14,
2653 PTA_SSE4_2 = 1 << 15,
2655 PTA_PCLMUL = 1 << 17,
2658 PTA_MOVBE = 1 << 20,
2666 const char *const name; /* processor name or nickname. */
2667 const enum processor_type processor;
2668 const enum attr_cpu schedule;
2669 const unsigned /*enum pta_flags*/ flags;
2671 const processor_alias_table[] =
2673 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2674 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2675 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2676 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2677 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2678 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2679 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2680 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2681 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2682 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2683 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2684 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2685 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2687 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2689 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2690 PTA_MMX | PTA_SSE | PTA_SSE2},
2691 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2692 PTA_MMX |PTA_SSE | PTA_SSE2},
2693 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2694 PTA_MMX | PTA_SSE | PTA_SSE2},
2695 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2696 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2697 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2698 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2699 | PTA_CX16 | PTA_NO_SAHF},
2700 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2701 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2702 | PTA_SSSE3 | PTA_CX16},
2703 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2704 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2705 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2706 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2707 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2708 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2709 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2710 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2711 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2712 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2713 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2714 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2715 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2716 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2717 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2718 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2719 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2720 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2721 {"x86-64", PROCESSOR_K8, CPU_K8,
2722 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2723 {"k8", PROCESSOR_K8, CPU_K8,
2724 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2725 | PTA_SSE2 | PTA_NO_SAHF},
2726 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2727 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2728 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2729 {"opteron", PROCESSOR_K8, CPU_K8,
2730 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2731 | PTA_SSE2 | PTA_NO_SAHF},
2732 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2733 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2734 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2735 {"athlon64", PROCESSOR_K8, CPU_K8,
2736 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2737 | PTA_SSE2 | PTA_NO_SAHF},
2738 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2739 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2740 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2741 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2742 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2743 | PTA_SSE2 | PTA_NO_SAHF},
2744 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2745 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2746 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2747 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2748 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2749 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2750 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2751 0 /* flags are only used for -march switch. */ },
2752 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2753 PTA_64BIT /* flags are only used for -march switch. */ },
2756 int const pta_size = ARRAY_SIZE (processor_alias_table);
2758 /* Set up prefix/suffix so the error messages refer to either the command
2759 line argument, or the attribute(target). */
2768 prefix = "option(\"";
2773 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2774 SUBTARGET_OVERRIDE_OPTIONS;
2777 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2778 SUBSUBTARGET_OVERRIDE_OPTIONS;
2781 /* -fPIC is the default for x86_64. */
2782 if (TARGET_MACHO && TARGET_64BIT)
2785 /* Set the default values for switches whose default depends on TARGET_64BIT
2786 in case they weren't overwritten by command line options. */
2789 /* Mach-O doesn't support omitting the frame pointer for now. */
2790 if (flag_omit_frame_pointer == 2)
2791 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2792 if (flag_asynchronous_unwind_tables == 2)
2793 flag_asynchronous_unwind_tables = 1;
2794 if (flag_pcc_struct_return == 2)
2795 flag_pcc_struct_return = 0;
2799 if (flag_omit_frame_pointer == 2)
2800 flag_omit_frame_pointer = 0;
2801 if (flag_asynchronous_unwind_tables == 2)
2802 flag_asynchronous_unwind_tables = 0;
2803 if (flag_pcc_struct_return == 2)
2804 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2807 /* Need to check -mtune=generic first. */
2808 if (ix86_tune_string)
2810 if (!strcmp (ix86_tune_string, "generic")
2811 || !strcmp (ix86_tune_string, "i686")
2812 /* As special support for cross compilers we read -mtune=native
2813 as -mtune=generic. With native compilers we won't see the
2814 -mtune=native, as it was changed by the driver. */
2815 || !strcmp (ix86_tune_string, "native"))
2818 ix86_tune_string = "generic64";
2820 ix86_tune_string = "generic32";
2822 /* If this call is for setting the option attribute, allow the
2823 generic32/generic64 that was previously set. */
2824 else if (!main_args_p
2825 && (!strcmp (ix86_tune_string, "generic32")
2826 || !strcmp (ix86_tune_string, "generic64")))
2828 else if (!strncmp (ix86_tune_string, "generic", 7))
2829 error ("bad value (%s) for %stune=%s %s",
2830 ix86_tune_string, prefix, suffix, sw);
2834 if (ix86_arch_string)
2835 ix86_tune_string = ix86_arch_string;
2836 if (!ix86_tune_string)
2838 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2839 ix86_tune_defaulted = 1;
2842 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2843 need to use a sensible tune option. */
2844 if (!strcmp (ix86_tune_string, "generic")
2845 || !strcmp (ix86_tune_string, "x86-64")
2846 || !strcmp (ix86_tune_string, "i686"))
2849 ix86_tune_string = "generic64";
2851 ix86_tune_string = "generic32";
2854 if (ix86_stringop_string)
2856 if (!strcmp (ix86_stringop_string, "rep_byte"))
2857 stringop_alg = rep_prefix_1_byte;
2858 else if (!strcmp (ix86_stringop_string, "libcall"))
2859 stringop_alg = libcall;
2860 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2861 stringop_alg = rep_prefix_4_byte;
2862 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2864 /* rep; movq isn't available in 32-bit code. */
2865 stringop_alg = rep_prefix_8_byte;
2866 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2867 stringop_alg = loop_1_byte;
2868 else if (!strcmp (ix86_stringop_string, "loop"))
2869 stringop_alg = loop;
2870 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2871 stringop_alg = unrolled_loop;
2873 error ("bad value (%s) for %sstringop-strategy=%s %s",
2874 ix86_stringop_string, prefix, suffix, sw);
2876 if (!strcmp (ix86_tune_string, "x86-64"))
2877 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2878 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2879 prefix, suffix, prefix, suffix, prefix, suffix);
2881 if (!ix86_arch_string)
2882 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2884 ix86_arch_specified = 1;
2886 if (!strcmp (ix86_arch_string, "generic"))
2887 error ("generic CPU can be used only for %stune=%s %s",
2888 prefix, suffix, sw);
2889 if (!strncmp (ix86_arch_string, "generic", 7))
2890 error ("bad value (%s) for %sarch=%s %s",
2891 ix86_arch_string, prefix, suffix, sw);
2893 /* Validate -mabi= value. */
2894 if (ix86_abi_string)
2896 if (strcmp (ix86_abi_string, "sysv") == 0)
2897 ix86_abi = SYSV_ABI;
2898 else if (strcmp (ix86_abi_string, "ms") == 0)
2901 error ("unknown ABI (%s) for %sabi=%s %s",
2902 ix86_abi_string, prefix, suffix, sw);
2905 ix86_abi = DEFAULT_ABI;
2907 if (ix86_cmodel_string != 0)
2909 if (!strcmp (ix86_cmodel_string, "small"))
2910 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2911 else if (!strcmp (ix86_cmodel_string, "medium"))
2912 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2913 else if (!strcmp (ix86_cmodel_string, "large"))
2914 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2916 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2917 else if (!strcmp (ix86_cmodel_string, "32"))
2918 ix86_cmodel = CM_32;
2919 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2920 ix86_cmodel = CM_KERNEL;
2922 error ("bad value (%s) for %scmodel=%s %s",
2923 ix86_cmodel_string, prefix, suffix, sw);
2927 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2928 use of rip-relative addressing. This eliminates fixups that
2929 would otherwise be needed if this object is to be placed in a
2930 DLL, and is essentially just as efficient as direct addressing. */
2931 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2932 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2933 else if (TARGET_64BIT)
2934 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2936 ix86_cmodel = CM_32;
2938 if (ix86_asm_string != 0)
2941 && !strcmp (ix86_asm_string, "intel"))
2942 ix86_asm_dialect = ASM_INTEL;
2943 else if (!strcmp (ix86_asm_string, "att"))
2944 ix86_asm_dialect = ASM_ATT;
2946 error ("bad value (%s) for %sasm=%s %s",
2947 ix86_asm_string, prefix, suffix, sw);
2949 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2950 error ("code model %qs not supported in the %s bit mode",
2951 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2952 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2953 sorry ("%i-bit mode not compiled in",
2954 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2956 for (i = 0; i < pta_size; i++)
2957 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2959 ix86_schedule = processor_alias_table[i].schedule;
2960 ix86_arch = processor_alias_table[i].processor;
2961 /* Default cpu tuning to the architecture. */
2962 ix86_tune = ix86_arch;
2964 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2965 error ("CPU you selected does not support x86-64 "
2968 if (processor_alias_table[i].flags & PTA_MMX
2969 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2970 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2971 if (processor_alias_table[i].flags & PTA_3DNOW
2972 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2973 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2974 if (processor_alias_table[i].flags & PTA_3DNOW_A
2975 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2976 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2977 if (processor_alias_table[i].flags & PTA_SSE
2978 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2979 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2980 if (processor_alias_table[i].flags & PTA_SSE2
2981 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2982 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2983 if (processor_alias_table[i].flags & PTA_SSE3
2984 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2985 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2986 if (processor_alias_table[i].flags & PTA_SSSE3
2987 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2988 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2989 if (processor_alias_table[i].flags & PTA_SSE4_1
2990 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2991 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2992 if (processor_alias_table[i].flags & PTA_SSE4_2
2993 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2994 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2995 if (processor_alias_table[i].flags & PTA_AVX
2996 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2997 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2998 if (processor_alias_table[i].flags & PTA_FMA
2999 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
3000 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
3001 if (processor_alias_table[i].flags & PTA_SSE4A
3002 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
3003 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
3004 if (processor_alias_table[i].flags & PTA_FMA4
3005 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
3006 ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
3007 if (processor_alias_table[i].flags & PTA_XOP
3008 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
3009 ix86_isa_flags |= OPTION_MASK_ISA_XOP;
3010 if (processor_alias_table[i].flags & PTA_LWP
3011 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
3012 ix86_isa_flags |= OPTION_MASK_ISA_LWP;
3013 if (processor_alias_table[i].flags & PTA_ABM
3014 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
3015 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
3016 if (processor_alias_table[i].flags & PTA_CX16
3017 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
3018 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
3019 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
3020 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
3021 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
3022 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
3023 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
3024 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
3025 if (processor_alias_table[i].flags & PTA_MOVBE
3026 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
3027 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
3028 if (processor_alias_table[i].flags & PTA_AES
3029 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
3030 ix86_isa_flags |= OPTION_MASK_ISA_AES;
3031 if (processor_alias_table[i].flags & PTA_PCLMUL
3032 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
3033 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
3034 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
3035 x86_prefetch_sse = true;
3041 error ("bad value (%s) for %sarch=%s %s",
3042 ix86_arch_string, prefix, suffix, sw);
3044 ix86_arch_mask = 1u << ix86_arch;
3045 for (i = 0; i < X86_ARCH_LAST; ++i)
3046 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3048 for (i = 0; i < pta_size; i++)
3049 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
3051 ix86_schedule = processor_alias_table[i].schedule;
3052 ix86_tune = processor_alias_table[i].processor;
3053 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
3055 if (ix86_tune_defaulted)
3057 ix86_tune_string = "x86-64";
3058 for (i = 0; i < pta_size; i++)
3059 if (! strcmp (ix86_tune_string,
3060 processor_alias_table[i].name))
3062 ix86_schedule = processor_alias_table[i].schedule;
3063 ix86_tune = processor_alias_table[i].processor;
3066 error ("CPU you selected does not support x86-64 "
3069 /* Intel CPUs have always interpreted SSE prefetch instructions as
3070 NOPs; so, we can enable SSE prefetch instructions even when
3071 -mtune (rather than -march) points us to a processor that has them.
3072 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3073 higher processors. */
3075 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3076 x86_prefetch_sse = true;
3080 error ("bad value (%s) for %stune=%s %s",
3081 ix86_tune_string, prefix, suffix, sw);
3083 ix86_tune_mask = 1u << ix86_tune;
3084 for (i = 0; i < X86_TUNE_LAST; ++i)
3085 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3088 ix86_cost = &ix86_size_cost;
3090 ix86_cost = processor_target_table[ix86_tune].cost;
3092 /* Arrange to set up i386_stack_locals for all functions. */
3093 init_machine_status = ix86_init_machine_status;
3095 /* Validate -mregparm= value. */
3096 if (ix86_regparm_string)
3099 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3100 i = atoi (ix86_regparm_string);
3101 if (i < 0 || i > REGPARM_MAX)
3102 error ("%sregparm=%d%s is not between 0 and %d",
3103 prefix, i, suffix, REGPARM_MAX);
3108 ix86_regparm = REGPARM_MAX;
3110 /* If the user has provided any of the -malign-* options,
3111 warn and use that value only if -falign-* is not set.
3112 Remove this code in GCC 3.2 or later. */
3113 if (ix86_align_loops_string)
3115 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3116 prefix, suffix, suffix);
3117 if (align_loops == 0)
3119 i = atoi (ix86_align_loops_string);
3120 if (i < 0 || i > MAX_CODE_ALIGN)
3121 error ("%salign-loops=%d%s is not between 0 and %d",
3122 prefix, i, suffix, MAX_CODE_ALIGN);
3124 align_loops = 1 << i;
3128 if (ix86_align_jumps_string)
3130 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3131 prefix, suffix, suffix);
3132 if (align_jumps == 0)
3134 i = atoi (ix86_align_jumps_string);
3135 if (i < 0 || i > MAX_CODE_ALIGN)
3136 error ("%salign-loops=%d%s is not between 0 and %d",
3137 prefix, i, suffix, MAX_CODE_ALIGN);
3139 align_jumps = 1 << i;
3143 if (ix86_align_funcs_string)
3145 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3146 prefix, suffix, suffix);
3147 if (align_functions == 0)
3149 i = atoi (ix86_align_funcs_string);
3150 if (i < 0 || i > MAX_CODE_ALIGN)
3151 error ("%salign-loops=%d%s is not between 0 and %d",
3152 prefix, i, suffix, MAX_CODE_ALIGN);
3154 align_functions = 1 << i;
3158 /* Default align_* from the processor table. */
3159 if (align_loops == 0)
3161 align_loops = processor_target_table[ix86_tune].align_loop;
3162 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3164 if (align_jumps == 0)
3166 align_jumps = processor_target_table[ix86_tune].align_jump;
3167 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3169 if (align_functions == 0)
3171 align_functions = processor_target_table[ix86_tune].align_func;
3174 /* Validate -mbranch-cost= value, or provide default. */
3175 ix86_branch_cost = ix86_cost->branch_cost;
3176 if (ix86_branch_cost_string)
3178 i = atoi (ix86_branch_cost_string);
3180 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3182 ix86_branch_cost = i;
3184 if (ix86_section_threshold_string)
3186 i = atoi (ix86_section_threshold_string);
3188 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3190 ix86_section_threshold = i;
3193 if (ix86_tls_dialect_string)
3195 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3196 ix86_tls_dialect = TLS_DIALECT_GNU;
3197 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3198 ix86_tls_dialect = TLS_DIALECT_GNU2;
3199 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3200 ix86_tls_dialect = TLS_DIALECT_SUN;
3202 error ("bad value (%s) for %stls-dialect=%s %s",
3203 ix86_tls_dialect_string, prefix, suffix, sw);
3206 if (ix87_precision_string)
3208 i = atoi (ix87_precision_string);
3209 if (i != 32 && i != 64 && i != 80)
3210 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3215 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3217 /* Enable by default the SSE and MMX builtins. Do allow the user to
3218 explicitly disable any of these. In particular, disabling SSE and
3219 MMX for kernel code is extremely useful. */
3220 if (!ix86_arch_specified)
3222 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3223 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3226 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3230 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3232 if (!ix86_arch_specified)
3234 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3236 /* i386 ABI does not specify red zone. It still makes sense to use it
3237 when programmer takes care to stack from being destroyed. */
3238 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3239 target_flags |= MASK_NO_RED_ZONE;
3242 /* Keep nonleaf frame pointers. */
3243 if (flag_omit_frame_pointer)
3244 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3245 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3246 flag_omit_frame_pointer = 1;
3248 /* If we're doing fast math, we don't care about comparison order
3249 wrt NaNs. This lets us use a shorter comparison sequence. */
3250 if (flag_finite_math_only)
3251 target_flags &= ~MASK_IEEE_FP;
3253 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3254 since the insns won't need emulation. */
3255 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3256 target_flags &= ~MASK_NO_FANCY_MATH_387;
3258 /* Likewise, if the target doesn't have a 387, or we've specified
3259 software floating point, don't use 387 inline intrinsics. */
3261 target_flags |= MASK_NO_FANCY_MATH_387;
3263 /* Turn on MMX builtins for -msse. */
3266 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3267 x86_prefetch_sse = true;
3270 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3271 if (TARGET_SSE4_2 || TARGET_ABM)
3272 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3274 /* Validate -mpreferred-stack-boundary= value or default it to
3275 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3276 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3277 if (ix86_preferred_stack_boundary_string)
3279 i = atoi (ix86_preferred_stack_boundary_string);
3280 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3281 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3282 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3284 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3287 /* Set the default value for -mstackrealign. */
3288 if (ix86_force_align_arg_pointer == -1)
3289 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3291 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3293 /* Validate -mincoming-stack-boundary= value or default it to
3294 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3295 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3296 if (ix86_incoming_stack_boundary_string)
3298 i = atoi (ix86_incoming_stack_boundary_string);
3299 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3300 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3301 i, TARGET_64BIT ? 4 : 2);
3304 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3305 ix86_incoming_stack_boundary
3306 = ix86_user_incoming_stack_boundary;
3310 /* Accept -msseregparm only if at least SSE support is enabled. */
3311 if (TARGET_SSEREGPARM
3313 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3315 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3316 if (ix86_fpmath_string != 0)
3318 if (! strcmp (ix86_fpmath_string, "387"))
3319 ix86_fpmath = FPMATH_387;
3320 else if (! strcmp (ix86_fpmath_string, "sse"))
3324 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3325 ix86_fpmath = FPMATH_387;
3328 ix86_fpmath = FPMATH_SSE;
3330 else if (! strcmp (ix86_fpmath_string, "387,sse")
3331 || ! strcmp (ix86_fpmath_string, "387+sse")
3332 || ! strcmp (ix86_fpmath_string, "sse,387")
3333 || ! strcmp (ix86_fpmath_string, "sse+387")
3334 || ! strcmp (ix86_fpmath_string, "both"))
3338 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3339 ix86_fpmath = FPMATH_387;
3341 else if (!TARGET_80387)
3343 warning (0, "387 instruction set disabled, using SSE arithmetics");
3344 ix86_fpmath = FPMATH_SSE;
3347 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3350 error ("bad value (%s) for %sfpmath=%s %s",
3351 ix86_fpmath_string, prefix, suffix, sw);
3354 /* If the i387 is disabled, then do not return values in it. */
3356 target_flags &= ~MASK_FLOAT_RETURNS;
3358 /* Use external vectorized library in vectorizing intrinsics. */
3359 if (ix86_veclibabi_string)
3361 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3362 ix86_veclib_handler = ix86_veclibabi_svml;
3363 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3364 ix86_veclib_handler = ix86_veclibabi_acml;
3366 error ("unknown vectorization library ABI type (%s) for "
3367 "%sveclibabi=%s %s", ix86_veclibabi_string,
3368 prefix, suffix, sw);
3371 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3372 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3374 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3376 /* ??? Unwind info is not correct around the CFG unless either a frame
3377 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3378 unwind info generation to be aware of the CFG and propagating states
3380 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3381 || flag_exceptions || flag_non_call_exceptions)
3382 && flag_omit_frame_pointer
3383 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3385 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3386 warning (0, "unwind tables currently require either a frame pointer "
3387 "or %saccumulate-outgoing-args%s for correctness",
3389 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3392 /* If stack probes are required, the space used for large function
3393 arguments on the stack must also be probed, so enable
3394 -maccumulate-outgoing-args so this happens in the prologue. */
3395 if (TARGET_STACK_PROBE
3396 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3398 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3399 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3400 "for correctness", prefix, suffix);
3401 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3404 /* For sane SSE instruction set generation we need fcomi instruction.
3405 It is safe to enable all CMOVE instructions. */
3409 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3412 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3413 p = strchr (internal_label_prefix, 'X');
3414 internal_label_prefix_len = p - internal_label_prefix;
3418 /* When scheduling description is not available, disable scheduler pass
3419 so it won't slow down the compilation and make x87 code slower. */
3420 if (!TARGET_SCHEDULE)
3421 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3423 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3424 set_param_value ("simultaneous-prefetches",
3425 ix86_cost->simultaneous_prefetches);
3426 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3427 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3428 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3429 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3430 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3431 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3433 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3434 can be optimized to ap = __builtin_next_arg (0). */
3436 targetm.expand_builtin_va_start = NULL;
3440 ix86_gen_leave = gen_leave_rex64;
3441 ix86_gen_pop1 = gen_popdi1;
3442 ix86_gen_add3 = gen_adddi3;
3443 ix86_gen_sub3 = gen_subdi3;
3444 ix86_gen_sub3_carry = gen_subdi3_carry;
3445 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3446 ix86_gen_monitor = gen_sse3_monitor64;
3447 ix86_gen_andsp = gen_anddi3;
3451 ix86_gen_leave = gen_leave;
3452 ix86_gen_pop1 = gen_popsi1;
3453 ix86_gen_add3 = gen_addsi3;
3454 ix86_gen_sub3 = gen_subsi3;
3455 ix86_gen_sub3_carry = gen_subsi3_carry;
3456 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3457 ix86_gen_monitor = gen_sse3_monitor;
3458 ix86_gen_andsp = gen_andsi3;
3462 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3464 target_flags |= MASK_CLD & ~target_flags_explicit;
3467 /* Save the initial options in case the user does function specific options */
3469 target_option_default_node = target_option_current_node
3470 = build_target_option_node ();
3473 /* Update register usage after having seen the compiler flags. */
3476 ix86_conditional_register_usage (void)
3481 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3483 if (fixed_regs[i] > 1)
3484 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3485 if (call_used_regs[i] > 1)
3486 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3489 /* The PIC register, if it exists, is fixed. */
3490 j = PIC_OFFSET_TABLE_REGNUM;
3491 if (j != INVALID_REGNUM)
3492 fixed_regs[j] = call_used_regs[j] = 1;
3494 /* The MS_ABI changes the set of call-used registers. */
3495 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3497 call_used_regs[SI_REG] = 0;
3498 call_used_regs[DI_REG] = 0;
3499 call_used_regs[XMM6_REG] = 0;
3500 call_used_regs[XMM7_REG] = 0;
3501 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3502 call_used_regs[i] = 0;
3505 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3506 other call-clobbered regs for 64-bit. */
3509 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3511 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3512 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3513 && call_used_regs[i])
3514 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3517 /* If MMX is disabled, squash the registers. */
3519 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3520 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3521 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3523 /* If SSE is disabled, squash the registers. */
3525 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3526 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3527 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3529 /* If the FPU is disabled, squash the registers. */
3530 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3531 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3532 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3533 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3535 /* If 32-bit, squash the 64-bit registers. */
3538 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3540 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3546 /* Save the current options */
3549 ix86_function_specific_save (struct cl_target_option *ptr)
3551 ptr->arch = ix86_arch;
3552 ptr->schedule = ix86_schedule;
3553 ptr->tune = ix86_tune;
3554 ptr->fpmath = ix86_fpmath;
3555 ptr->branch_cost = ix86_branch_cost;
3556 ptr->tune_defaulted = ix86_tune_defaulted;
3557 ptr->arch_specified = ix86_arch_specified;
3558 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3559 ptr->target_flags_explicit = target_flags_explicit;
3561 /* The fields are char but the variables are not; make sure the
3562 values fit in the fields. */
3563 gcc_assert (ptr->arch == ix86_arch);
3564 gcc_assert (ptr->schedule == ix86_schedule);
3565 gcc_assert (ptr->tune == ix86_tune);
3566 gcc_assert (ptr->fpmath == ix86_fpmath);
3567 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3570 /* Restore the current options */
3573 ix86_function_specific_restore (struct cl_target_option *ptr)
3575 enum processor_type old_tune = ix86_tune;
3576 enum processor_type old_arch = ix86_arch;
3577 unsigned int ix86_arch_mask, ix86_tune_mask;
3580 ix86_arch = (enum processor_type) ptr->arch;
3581 ix86_schedule = (enum attr_cpu) ptr->schedule;
3582 ix86_tune = (enum processor_type) ptr->tune;
3583 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3584 ix86_branch_cost = ptr->branch_cost;
3585 ix86_tune_defaulted = ptr->tune_defaulted;
3586 ix86_arch_specified = ptr->arch_specified;
3587 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3588 target_flags_explicit = ptr->target_flags_explicit;
3590 /* Recreate the arch feature tests if the arch changed */
3591 if (old_arch != ix86_arch)
3593 ix86_arch_mask = 1u << ix86_arch;
3594 for (i = 0; i < X86_ARCH_LAST; ++i)
3595 ix86_arch_features[i]
3596 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3599 /* Recreate the tune optimization tests */
3600 if (old_tune != ix86_tune)
3602 ix86_tune_mask = 1u << ix86_tune;
3603 for (i = 0; i < X86_TUNE_LAST; ++i)
3604 ix86_tune_features[i]
3605 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3609 /* Print the current options */
3612 ix86_function_specific_print (FILE *file, int indent,
3613 struct cl_target_option *ptr)
3616 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3617 NULL, NULL, NULL, false);
3619 fprintf (file, "%*sarch = %d (%s)\n",
3622 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3623 ? cpu_names[ptr->arch]
3626 fprintf (file, "%*stune = %d (%s)\n",
3629 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3630 ? cpu_names[ptr->tune]
3633 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3634 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3635 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3636 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3640 fprintf (file, "%*s%s\n", indent, "", target_string);
3641 free (target_string);
3646 /* Inner function to process the attribute((target(...))), take an argument and
3647 set the current options from the argument. If we have a list, recursively go
3651 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3656 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3657 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3658 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3659 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3674 enum ix86_opt_type type;
3679 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3680 IX86_ATTR_ISA ("abm", OPT_mabm),
3681 IX86_ATTR_ISA ("aes", OPT_maes),
3682 IX86_ATTR_ISA ("avx", OPT_mavx),
3683 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3684 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3685 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3686 IX86_ATTR_ISA ("sse", OPT_msse),
3687 IX86_ATTR_ISA ("sse2", OPT_msse2),
3688 IX86_ATTR_ISA ("sse3", OPT_msse3),
3689 IX86_ATTR_ISA ("sse4", OPT_msse4),
3690 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3691 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3692 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3693 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3694 IX86_ATTR_ISA ("fma4", OPT_mfma4),
3695 IX86_ATTR_ISA ("xop", OPT_mxop),
3696 IX86_ATTR_ISA ("lwp", OPT_mlwp),
3698 /* string options */
3699 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3700 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3701 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3704 IX86_ATTR_YES ("cld",
3708 IX86_ATTR_NO ("fancy-math-387",
3709 OPT_mfancy_math_387,
3710 MASK_NO_FANCY_MATH_387),
3712 IX86_ATTR_YES ("ieee-fp",
3716 IX86_ATTR_YES ("inline-all-stringops",
3717 OPT_minline_all_stringops,
3718 MASK_INLINE_ALL_STRINGOPS),
3720 IX86_ATTR_YES ("inline-stringops-dynamically",
3721 OPT_minline_stringops_dynamically,
3722 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3724 IX86_ATTR_NO ("align-stringops",
3725 OPT_mno_align_stringops,
3726 MASK_NO_ALIGN_STRINGOPS),
3728 IX86_ATTR_YES ("recip",
3734 /* If this is a list, recurse to get the options. */
3735 if (TREE_CODE (args) == TREE_LIST)
3739 for (; args; args = TREE_CHAIN (args))
3740 if (TREE_VALUE (args)
3741 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3747 else if (TREE_CODE (args) != STRING_CST)
3750 /* Handle multiple arguments separated by commas. */
3751 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3753 while (next_optstr && *next_optstr != '\0')
3755 char *p = next_optstr;
3757 char *comma = strchr (next_optstr, ',');
3758 const char *opt_string;
3759 size_t len, opt_len;
3764 enum ix86_opt_type type = ix86_opt_unknown;
3770 len = comma - next_optstr;
3771 next_optstr = comma + 1;
3779 /* Recognize no-xxx. */
3780 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3789 /* Find the option. */
3792 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3794 type = attrs[i].type;
3795 opt_len = attrs[i].len;
3796 if (ch == attrs[i].string[0]
3797 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3798 && memcmp (p, attrs[i].string, opt_len) == 0)
3801 mask = attrs[i].mask;
3802 opt_string = attrs[i].string;
3807 /* Process the option. */
3810 error ("attribute(target(\"%s\")) is unknown", orig_p);
3814 else if (type == ix86_opt_isa)
3815 ix86_handle_option (opt, p, opt_set_p);
3817 else if (type == ix86_opt_yes || type == ix86_opt_no)
3819 if (type == ix86_opt_no)
3820 opt_set_p = !opt_set_p;
3823 target_flags |= mask;
3825 target_flags &= ~mask;
3828 else if (type == ix86_opt_str)
3832 error ("option(\"%s\") was already specified", opt_string);
3836 p_strings[opt] = xstrdup (p + opt_len);
3846 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3849 ix86_valid_target_attribute_tree (tree args)
3851 const char *orig_arch_string = ix86_arch_string;
3852 const char *orig_tune_string = ix86_tune_string;
3853 const char *orig_fpmath_string = ix86_fpmath_string;
3854 int orig_tune_defaulted = ix86_tune_defaulted;
3855 int orig_arch_specified = ix86_arch_specified;
3856 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3859 struct cl_target_option *def
3860 = TREE_TARGET_OPTION (target_option_default_node);
3862 /* Process each of the options on the chain. */
3863 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3866 /* If the changed options are different from the default, rerun override_options,
3867 and then save the options away. The string options are are attribute options,
3868 and will be undone when we copy the save structure. */
3869 if (ix86_isa_flags != def->ix86_isa_flags
3870 || target_flags != def->target_flags
3871 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3872 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3873 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3875 /* If we are using the default tune= or arch=, undo the string assigned,
3876 and use the default. */
3877 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3878 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3879 else if (!orig_arch_specified)
3880 ix86_arch_string = NULL;
3882 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3883 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3884 else if (orig_tune_defaulted)
3885 ix86_tune_string = NULL;
3887 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3888 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3889 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3890 else if (!TARGET_64BIT && TARGET_SSE)
3891 ix86_fpmath_string = "sse,387";
3893 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3894 override_options (false);
3896 /* Add any builtin functions with the new isa if any. */
3897 ix86_add_new_builtins (ix86_isa_flags);
3899 /* Save the current options unless we are validating options for
3901 t = build_target_option_node ();
3903 ix86_arch_string = orig_arch_string;
3904 ix86_tune_string = orig_tune_string;
3905 ix86_fpmath_string = orig_fpmath_string;
3907 /* Free up memory allocated to hold the strings */
3908 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3909 if (option_strings[i])
3910 free (option_strings[i]);
3916 /* Hook to validate attribute((target("string"))). */
3919 ix86_valid_target_attribute_p (tree fndecl,
3920 tree ARG_UNUSED (name),
3922 int ARG_UNUSED (flags))
3924 struct cl_target_option cur_target;
3926 tree old_optimize = build_optimization_node ();
3927 tree new_target, new_optimize;
3928 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3930 /* If the function changed the optimization levels as well as setting target
3931 options, start with the optimizations specified. */
3932 if (func_optimize && func_optimize != old_optimize)
3933 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3935 /* The target attributes may also change some optimization flags, so update
3936 the optimization options if necessary. */
3937 cl_target_option_save (&cur_target);
3938 new_target = ix86_valid_target_attribute_tree (args);
3939 new_optimize = build_optimization_node ();
3946 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3948 if (old_optimize != new_optimize)
3949 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3952 cl_target_option_restore (&cur_target);
3954 if (old_optimize != new_optimize)
3955 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3961 /* Hook to determine if one function can safely inline another. */
3964 ix86_can_inline_p (tree caller, tree callee)
3967 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3968 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3970 /* If callee has no option attributes, then it is ok to inline. */
3974 /* If caller has no option attributes, but callee does then it is not ok to
3976 else if (!caller_tree)
3981 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3982 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3984 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3985 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3987 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3988 != callee_opts->ix86_isa_flags)
3991 /* See if we have the same non-isa options. */
3992 else if (caller_opts->target_flags != callee_opts->target_flags)
3995 /* See if arch, tune, etc. are the same. */
3996 else if (caller_opts->arch != callee_opts->arch)
3999 else if (caller_opts->tune != callee_opts->tune)
4002 else if (caller_opts->fpmath != callee_opts->fpmath)
4005 else if (caller_opts->branch_cost != callee_opts->branch_cost)
4016 /* Remember the last target of ix86_set_current_function. */
4017 static GTY(()) tree ix86_previous_fndecl;
4019 /* Establish appropriate back-end context for processing the function
4020 FNDECL. The argument might be NULL to indicate processing at top
4021 level, outside of any function scope. */
4023 ix86_set_current_function (tree fndecl)
4025 /* Only change the context if the function changes. This hook is called
4026 several times in the course of compiling a function, and we don't want to
4027 slow things down too much or call target_reinit when it isn't safe. */
4028 if (fndecl && fndecl != ix86_previous_fndecl)
4030 tree old_tree = (ix86_previous_fndecl
4031 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
4034 tree new_tree = (fndecl
4035 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
4038 ix86_previous_fndecl = fndecl;
4039 if (old_tree == new_tree)
4044 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
4050 struct cl_target_option *def
4051 = TREE_TARGET_OPTION (target_option_current_node);
4053 cl_target_option_restore (def);
4060 /* Return true if this goes in large data/bss. */
4063 ix86_in_large_data_p (tree exp)
4065 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
4068 /* Functions are never large data. */
4069 if (TREE_CODE (exp) == FUNCTION_DECL)
4072 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
4074 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
4075 if (strcmp (section, ".ldata") == 0
4076 || strcmp (section, ".lbss") == 0)
4082 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4084 /* If this is an incomplete type with size 0, then we can't put it
4085 in data because it might be too big when completed. */
4086 if (!size || size > ix86_section_threshold)
4093 /* Switch to the appropriate section for output of DECL.
4094 DECL is either a `VAR_DECL' node or a constant of some sort.
4095 RELOC indicates whether forming the initial value of DECL requires
4096 link-time relocations. */
4098 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4102 x86_64_elf_select_section (tree decl, int reloc,
4103 unsigned HOST_WIDE_INT align)
4105 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4106 && ix86_in_large_data_p (decl))
4108 const char *sname = NULL;
4109 unsigned int flags = SECTION_WRITE;
4110 switch (categorize_decl_for_section (decl, reloc))
4115 case SECCAT_DATA_REL:
4116 sname = ".ldata.rel";
4118 case SECCAT_DATA_REL_LOCAL:
4119 sname = ".ldata.rel.local";
4121 case SECCAT_DATA_REL_RO:
4122 sname = ".ldata.rel.ro";
4124 case SECCAT_DATA_REL_RO_LOCAL:
4125 sname = ".ldata.rel.ro.local";
4129 flags |= SECTION_BSS;
4132 case SECCAT_RODATA_MERGE_STR:
4133 case SECCAT_RODATA_MERGE_STR_INIT:
4134 case SECCAT_RODATA_MERGE_CONST:
4138 case SECCAT_SRODATA:
4145 /* We don't split these for medium model. Place them into
4146 default sections and hope for best. */
4148 case SECCAT_EMUTLS_VAR:
4149 case SECCAT_EMUTLS_TMPL:
4154 /* We might get called with string constants, but get_named_section
4155 doesn't like them as they are not DECLs. Also, we need to set
4156 flags in that case. */
4158 return get_section (sname, flags, NULL);
4159 return get_named_section (decl, sname, reloc);
4162 return default_elf_select_section (decl, reloc, align);
4165 /* Build up a unique section name, expressed as a
4166 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4167 RELOC indicates whether the initial value of EXP requires
4168 link-time relocations. */
4170 static void ATTRIBUTE_UNUSED
4171 x86_64_elf_unique_section (tree decl, int reloc)
4173 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4174 && ix86_in_large_data_p (decl))
4176 const char *prefix = NULL;
4177 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4178 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4180 switch (categorize_decl_for_section (decl, reloc))
4183 case SECCAT_DATA_REL:
4184 case SECCAT_DATA_REL_LOCAL:
4185 case SECCAT_DATA_REL_RO:
4186 case SECCAT_DATA_REL_RO_LOCAL:
4187 prefix = one_only ? ".ld" : ".ldata";
4190 prefix = one_only ? ".lb" : ".lbss";
4193 case SECCAT_RODATA_MERGE_STR:
4194 case SECCAT_RODATA_MERGE_STR_INIT:
4195 case SECCAT_RODATA_MERGE_CONST:
4196 prefix = one_only ? ".lr" : ".lrodata";
4198 case SECCAT_SRODATA:
4205 /* We don't split these for medium model. Place them into
4206 default sections and hope for best. */
4208 case SECCAT_EMUTLS_VAR:
4209 prefix = targetm.emutls.var_section;
4211 case SECCAT_EMUTLS_TMPL:
4212 prefix = targetm.emutls.tmpl_section;
4217 const char *name, *linkonce;
4220 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4221 name = targetm.strip_name_encoding (name);
4223 /* If we're using one_only, then there needs to be a .gnu.linkonce
4224 prefix to the section name. */
4225 linkonce = one_only ? ".gnu.linkonce" : "";
4227 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4229 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4233 default_unique_section (decl, reloc);
4236 #ifdef COMMON_ASM_OP
4237 /* This says how to output assembler code to declare an
4238 uninitialized external linkage data object.
4240 For medium model x86-64 we need to use .largecomm opcode for
4243 x86_elf_aligned_common (FILE *file,
4244 const char *name, unsigned HOST_WIDE_INT size,
4247 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4248 && size > (unsigned int)ix86_section_threshold)
4249 fputs (".largecomm\t", file);
4251 fputs (COMMON_ASM_OP, file);
4252 assemble_name (file, name);
4253 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4254 size, align / BITS_PER_UNIT);
4258 /* Utility function for targets to use in implementing
4259 ASM_OUTPUT_ALIGNED_BSS. */
4262 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4263 const char *name, unsigned HOST_WIDE_INT size,
4266 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4267 && size > (unsigned int)ix86_section_threshold)
4268 switch_to_section (get_named_section (decl, ".lbss", 0));
4270 switch_to_section (bss_section);
4271 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4272 #ifdef ASM_DECLARE_OBJECT_NAME
4273 last_assemble_variable_decl = decl;
4274 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4276 /* Standard thing is just output label for the object. */
4277 ASM_OUTPUT_LABEL (file, name);
4278 #endif /* ASM_DECLARE_OBJECT_NAME */
4279 ASM_OUTPUT_SKIP (file, size ? size : 1);
4283 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4285 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4286 make the problem with not enough registers even worse. */
4287 #ifdef INSN_SCHEDULING
4289 flag_schedule_insns = 0;
4293 /* The Darwin libraries never set errno, so we might as well
4294 avoid calling them when that's the only reason we would. */
4295 flag_errno_math = 0;
4297 /* The default values of these switches depend on the TARGET_64BIT
4298 that is not known at this moment. Mark these values with 2 and
4299 let user the to override these. In case there is no command line option
4300 specifying them, we will set the defaults in override_options. */
4302 flag_omit_frame_pointer = 2;
4303 flag_pcc_struct_return = 2;
4304 flag_asynchronous_unwind_tables = 2;
4305 flag_vect_cost_model = 1;
4306 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4307 SUBTARGET_OPTIMIZATION_OPTIONS;
4311 /* Decide whether we can make a sibling call to a function. DECL is the
4312 declaration of the function being targeted by the call and EXP is the
4313 CALL_EXPR representing the call. */
4316 ix86_function_ok_for_sibcall (tree decl, tree exp)
4318 tree type, decl_or_type;
4321 /* If we are generating position-independent code, we cannot sibcall
4322 optimize any indirect call, or a direct call to a global function,
4323 as the PLT requires %ebx be live. */
4324 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4327 /* If we need to align the outgoing stack, then sibcalling would
4328 unalign the stack, which may break the called function. */
4329 if (ix86_minimum_incoming_stack_boundary (true)
4330 < PREFERRED_STACK_BOUNDARY)
4335 decl_or_type = decl;
4336 type = TREE_TYPE (decl);
4340 /* We're looking at the CALL_EXPR, we need the type of the function. */
4341 type = CALL_EXPR_FN (exp); /* pointer expression */
4342 type = TREE_TYPE (type); /* pointer type */
4343 type = TREE_TYPE (type); /* function type */
4344 decl_or_type = type;
4347 /* Check that the return value locations are the same. Like
4348 if we are returning floats on the 80387 register stack, we cannot
4349 make a sibcall from a function that doesn't return a float to a
4350 function that does or, conversely, from a function that does return
4351 a float to a function that doesn't; the necessary stack adjustment
4352 would not be executed. This is also the place we notice
4353 differences in the return value ABI. Note that it is ok for one
4354 of the functions to have void return type as long as the return
4355 value of the other is passed in a register. */
4356 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4357 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4359 if (STACK_REG_P (a) || STACK_REG_P (b))
4361 if (!rtx_equal_p (a, b))
4364 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4366 else if (!rtx_equal_p (a, b))
4371 /* The SYSV ABI has more call-clobbered registers;
4372 disallow sibcalls from MS to SYSV. */
4373 if (cfun->machine->call_abi == MS_ABI
4374 && ix86_function_type_abi (type) == SYSV_ABI)
4379 /* If this call is indirect, we'll need to be able to use a
4380 call-clobbered register for the address of the target function.
4381 Make sure that all such registers are not used for passing
4382 parameters. Note that DLLIMPORT functions are indirect. */
4384 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4386 if (ix86_function_regparm (type, NULL) >= 3)
4388 /* ??? Need to count the actual number of registers to be used,
4389 not the possible number of registers. Fix later. */
4395 /* Otherwise okay. That also includes certain types of indirect calls. */
4399 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4400 calling convention attributes;
4401 arguments as in struct attribute_spec.handler. */
4404 ix86_handle_cconv_attribute (tree *node, tree name,
4406 int flags ATTRIBUTE_UNUSED,
4409 if (TREE_CODE (*node) != FUNCTION_TYPE
4410 && TREE_CODE (*node) != METHOD_TYPE
4411 && TREE_CODE (*node) != FIELD_DECL
4412 && TREE_CODE (*node) != TYPE_DECL)
4414 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4416 *no_add_attrs = true;
4420 /* Can combine regparm with all attributes but fastcall. */
4421 if (is_attribute_p ("regparm", name))
4425 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4427 error ("fastcall and regparm attributes are not compatible");
4430 cst = TREE_VALUE (args);
4431 if (TREE_CODE (cst) != INTEGER_CST)
4433 warning (OPT_Wattributes,
4434 "%qE attribute requires an integer constant argument",
4436 *no_add_attrs = true;
4438 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4440 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4442 *no_add_attrs = true;
4450 /* Do not warn when emulating the MS ABI. */
4451 if (TREE_CODE (*node) != FUNCTION_TYPE
4452 || ix86_function_type_abi (*node) != MS_ABI)
4453 warning (OPT_Wattributes, "%qE attribute ignored",
4455 *no_add_attrs = true;
4459 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4460 if (is_attribute_p ("fastcall", name))
4462 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4464 error ("fastcall and cdecl attributes are not compatible");
4466 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4468 error ("fastcall and stdcall attributes are not compatible");
4470 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4472 error ("fastcall and regparm attributes are not compatible");
4476 /* Can combine stdcall with fastcall (redundant), regparm and
4478 else if (is_attribute_p ("stdcall", name))
4480 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4482 error ("stdcall and cdecl attributes are not compatible");
4484 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4486 error ("stdcall and fastcall attributes are not compatible");
4490 /* Can combine cdecl with regparm and sseregparm. */
4491 else if (is_attribute_p ("cdecl", name))
4493 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4495 error ("stdcall and cdecl attributes are not compatible");
4497 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4499 error ("fastcall and cdecl attributes are not compatible");
4503 /* Can combine sseregparm with all attributes. */
4508 /* Return 0 if the attributes for two types are incompatible, 1 if they
4509 are compatible, and 2 if they are nearly compatible (which causes a
4510 warning to be generated). */
4513 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4515 /* Check for mismatch of non-default calling convention. */
4516 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4518 if (TREE_CODE (type1) != FUNCTION_TYPE
4519 && TREE_CODE (type1) != METHOD_TYPE)
4522 /* Check for mismatched fastcall/regparm types. */
4523 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4524 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4525 || (ix86_function_regparm (type1, NULL)
4526 != ix86_function_regparm (type2, NULL)))
4529 /* Check for mismatched sseregparm types. */
4530 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4531 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4534 /* Check for mismatched return types (cdecl vs stdcall). */
4535 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4536 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4542 /* Return the regparm value for a function with the indicated TYPE and DECL.
4543 DECL may be NULL when calling function indirectly
4544 or considering a libcall. */
4547 ix86_function_regparm (const_tree type, const_tree decl)
4553 return (ix86_function_type_abi (type) == SYSV_ABI
4554 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4556 regparm = ix86_regparm;
4557 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4560 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4564 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4567 /* Use register calling convention for local functions when possible. */
4569 && TREE_CODE (decl) == FUNCTION_DECL
4573 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4574 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE (decl));
4577 int local_regparm, globals = 0, regno;
4579 /* Make sure no regparm register is taken by a
4580 fixed register variable. */
4581 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4582 if (fixed_regs[local_regparm])
4585 /* We don't want to use regparm(3) for nested functions as
4586 these use a static chain pointer in the third argument. */
4587 if (local_regparm == 3 && DECL_STATIC_CHAIN (decl))
4590 /* Each fixed register usage increases register pressure,
4591 so less registers should be used for argument passing.
4592 This functionality can be overriden by an explicit
4594 for (regno = 0; regno <= DI_REG; regno++)
4595 if (fixed_regs[regno])
4599 = globals < local_regparm ? local_regparm - globals : 0;
4601 if (local_regparm > regparm)
4602 regparm = local_regparm;
4609 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4610 DFmode (2) arguments in SSE registers for a function with the
4611 indicated TYPE and DECL. DECL may be NULL when calling function
4612 indirectly or considering a libcall. Otherwise return 0. */
4615 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4617 gcc_assert (!TARGET_64BIT);
4619 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4620 by the sseregparm attribute. */
4621 if (TARGET_SSEREGPARM
4622 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4629 error ("Calling %qD with attribute sseregparm without "
4630 "SSE/SSE2 enabled", decl);
4632 error ("Calling %qT with attribute sseregparm without "
4633 "SSE/SSE2 enabled", type);
4641 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4642 (and DFmode for SSE2) arguments in SSE registers. */
4643 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4645 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4646 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4648 return TARGET_SSE2 ? 2 : 1;
4654 /* Return true if EAX is live at the start of the function. Used by
4655 ix86_expand_prologue to determine if we need special help before
4656 calling allocate_stack_worker. */
4659 ix86_eax_live_at_start_p (void)
4661 /* Cheat. Don't bother working forward from ix86_function_regparm
4662 to the function type to whether an actual argument is located in
4663 eax. Instead just look at cfg info, which is still close enough
4664 to correct at this point. This gives false positives for broken
4665 functions that might use uninitialized data that happens to be
4666 allocated in eax, but who cares? */
4667 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4670 /* Value is the number of bytes of arguments automatically
4671 popped when returning from a subroutine call.
4672 FUNDECL is the declaration node of the function (as a tree),
4673 FUNTYPE is the data type of the function (as a tree),
4674 or for a library call it is an identifier node for the subroutine name.
4675 SIZE is the number of bytes of arguments passed on the stack.
4677 On the 80386, the RTD insn may be used to pop them if the number
4678 of args is fixed, but if the number is variable then the caller
4679 must pop them all. RTD can't be used for library calls now
4680 because the library is compiled with the Unix compiler.
4681 Use of RTD is a selectable option, since it is incompatible with
4682 standard Unix calling sequences. If the option is not selected,
4683 the caller must always pop the args.
4685 The attribute stdcall is equivalent to RTD on a per module basis. */
4688 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4692 /* None of the 64-bit ABIs pop arguments. */
4696 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4698 /* Cdecl functions override -mrtd, and never pop the stack. */
4699 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4701 /* Stdcall and fastcall functions will pop the stack if not
4703 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4704 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4707 if (rtd && ! stdarg_p (funtype))
4711 /* Lose any fake structure return argument if it is passed on the stack. */
4712 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4713 && !KEEP_AGGREGATE_RETURN_POINTER)
4715 int nregs = ix86_function_regparm (funtype, fundecl);
4717 return GET_MODE_SIZE (Pmode);
4723 /* Argument support functions. */
4725 /* Return true when register may be used to pass function parameters. */
4727 ix86_function_arg_regno_p (int regno)
4730 const int *parm_regs;
4735 return (regno < REGPARM_MAX
4736 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4738 return (regno < REGPARM_MAX
4739 || (TARGET_MMX && MMX_REGNO_P (regno)
4740 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4741 || (TARGET_SSE && SSE_REGNO_P (regno)
4742 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4747 if (SSE_REGNO_P (regno) && TARGET_SSE)
4752 if (TARGET_SSE && SSE_REGNO_P (regno)
4753 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4757 /* TODO: The function should depend on current function ABI but
4758 builtins.c would need updating then. Therefore we use the
4761 /* RAX is used as hidden argument to va_arg functions. */
4762 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4765 if (ix86_abi == MS_ABI)
4766 parm_regs = x86_64_ms_abi_int_parameter_registers;
4768 parm_regs = x86_64_int_parameter_registers;
4769 for (i = 0; i < (ix86_abi == MS_ABI
4770 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4771 if (regno == parm_regs[i])
4776 /* Return if we do not know how to pass TYPE solely in registers. */
4779 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4781 if (must_pass_in_stack_var_size_or_pad (mode, type))
4784 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4785 The layout_type routine is crafty and tries to trick us into passing
4786 currently unsupported vector types on the stack by using TImode. */
4787 return (!TARGET_64BIT && mode == TImode
4788 && type && TREE_CODE (type) != VECTOR_TYPE);
4791 /* It returns the size, in bytes, of the area reserved for arguments passed
4792 in registers for the function represented by fndecl dependent to the used
4795 ix86_reg_parm_stack_space (const_tree fndecl)
4797 enum calling_abi call_abi = SYSV_ABI;
4798 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4799 call_abi = ix86_function_abi (fndecl);
4801 call_abi = ix86_function_type_abi (fndecl);
4802 if (call_abi == MS_ABI)
4807 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4810 ix86_function_type_abi (const_tree fntype)
4812 if (TARGET_64BIT && fntype != NULL)
4814 enum calling_abi abi = ix86_abi;
4815 if (abi == SYSV_ABI)
4817 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4820 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4828 ix86_function_ms_hook_prologue (const_tree fntype)
4832 if (lookup_attribute ("ms_hook_prologue", DECL_ATTRIBUTES (fntype)))
4834 if (decl_function_context (fntype) != NULL_TREE)
4836 error_at (DECL_SOURCE_LOCATION (fntype),
4837 "ms_hook_prologue is not compatible with nested function");
4846 static enum calling_abi
4847 ix86_function_abi (const_tree fndecl)
4851 return ix86_function_type_abi (TREE_TYPE (fndecl));
4854 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4857 ix86_cfun_abi (void)
4859 if (! cfun || ! TARGET_64BIT)
4861 return cfun->machine->call_abi;
4865 extern void init_regs (void);
4867 /* Implementation of call abi switching target hook. Specific to FNDECL
4868 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4869 for more details. */
4871 ix86_call_abi_override (const_tree fndecl)
4873 if (fndecl == NULL_TREE)
4874 cfun->machine->call_abi = ix86_abi;
4876 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4879 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4880 re-initialization of init_regs each time we switch function context since
4881 this is needed only during RTL expansion. */
4883 ix86_maybe_switch_abi (void)
4886 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4890 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4891 for a call to a function whose data type is FNTYPE.
4892 For a library call, FNTYPE is 0. */
4895 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4896 tree fntype, /* tree ptr for function decl */
4897 rtx libname, /* SYMBOL_REF of library name or 0 */
4900 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4901 memset (cum, 0, sizeof (*cum));
4904 cum->call_abi = ix86_function_abi (fndecl);
4906 cum->call_abi = ix86_function_type_abi (fntype);
4907 /* Set up the number of registers to use for passing arguments. */
4909 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4910 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4911 "or subtarget optimization implying it");
4912 cum->nregs = ix86_regparm;
4915 if (cum->call_abi != ix86_abi)
4916 cum->nregs = (ix86_abi != SYSV_ABI
4917 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4921 cum->sse_nregs = SSE_REGPARM_MAX;
4924 if (cum->call_abi != ix86_abi)
4925 cum->sse_nregs = (ix86_abi != SYSV_ABI
4926 ? X86_64_SSE_REGPARM_MAX
4927 : X86_64_MS_SSE_REGPARM_MAX);
4931 cum->mmx_nregs = MMX_REGPARM_MAX;
4932 cum->warn_avx = true;
4933 cum->warn_sse = true;
4934 cum->warn_mmx = true;
4936 /* Because type might mismatch in between caller and callee, we need to
4937 use actual type of function for local calls.
4938 FIXME: cgraph_analyze can be told to actually record if function uses
4939 va_start so for local functions maybe_vaarg can be made aggressive
4941 FIXME: once typesytem is fixed, we won't need this code anymore. */
4943 fntype = TREE_TYPE (fndecl);
4944 cum->maybe_vaarg = (fntype
4945 ? (!prototype_p (fntype) || stdarg_p (fntype))
4950 /* If there are variable arguments, then we won't pass anything
4951 in registers in 32-bit mode. */
4952 if (stdarg_p (fntype))
4963 /* Use ecx and edx registers if function has fastcall attribute,
4964 else look for regparm information. */
4967 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4973 cum->nregs = ix86_function_regparm (fntype, fndecl);
4976 /* Set up the number of SSE registers used for passing SFmode
4977 and DFmode arguments. Warn for mismatching ABI. */
4978 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4982 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4983 But in the case of vector types, it is some vector mode.
4985 When we have only some of our vector isa extensions enabled, then there
4986 are some modes for which vector_mode_supported_p is false. For these
4987 modes, the generic vector support in gcc will choose some non-vector mode
4988 in order to implement the type. By computing the natural mode, we'll
4989 select the proper ABI location for the operand and not depend on whatever
4990 the middle-end decides to do with these vector types.
4992 The midde-end can't deal with the vector types > 16 bytes. In this
4993 case, we return the original mode and warn ABI change if CUM isn't
4996 static enum machine_mode
4997 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4999 enum machine_mode mode = TYPE_MODE (type);
5001 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
5003 HOST_WIDE_INT size = int_size_in_bytes (type);
5004 if ((size == 8 || size == 16 || size == 32)
5005 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5006 && TYPE_VECTOR_SUBPARTS (type) > 1)
5008 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
5010 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5011 mode = MIN_MODE_VECTOR_FLOAT;
5013 mode = MIN_MODE_VECTOR_INT;
5015 /* Get the mode which has this inner mode and number of units. */
5016 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
5017 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
5018 && GET_MODE_INNER (mode) == innermode)
5020 if (size == 32 && !TARGET_AVX)
5022 static bool warnedavx;
5029 warning (0, "AVX vector argument without AVX "
5030 "enabled changes the ABI");
5032 return TYPE_MODE (type);
5045 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5046 this may not agree with the mode that the type system has chosen for the
5047 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5048 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5051 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
5056 if (orig_mode != BLKmode)
5057 tmp = gen_rtx_REG (orig_mode, regno);
5060 tmp = gen_rtx_REG (mode, regno);
5061 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
5062 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
5068 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5069 of this code is to classify each 8bytes of incoming argument by the register
5070 class and assign registers accordingly. */
5072 /* Return the union class of CLASS1 and CLASS2.
5073 See the x86-64 PS ABI for details. */
5075 static enum x86_64_reg_class
5076 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5078 /* Rule #1: If both classes are equal, this is the resulting class. */
5079 if (class1 == class2)
5082 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5084 if (class1 == X86_64_NO_CLASS)
5086 if (class2 == X86_64_NO_CLASS)
5089 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5090 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5091 return X86_64_MEMORY_CLASS;
5093 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5094 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5095 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5096 return X86_64_INTEGERSI_CLASS;
5097 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5098 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5099 return X86_64_INTEGER_CLASS;
5101 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5103 if (class1 == X86_64_X87_CLASS
5104 || class1 == X86_64_X87UP_CLASS
5105 || class1 == X86_64_COMPLEX_X87_CLASS
5106 || class2 == X86_64_X87_CLASS
5107 || class2 == X86_64_X87UP_CLASS
5108 || class2 == X86_64_COMPLEX_X87_CLASS)
5109 return X86_64_MEMORY_CLASS;
5111 /* Rule #6: Otherwise class SSE is used. */
5112 return X86_64_SSE_CLASS;
5115 /* Classify the argument of type TYPE and mode MODE.
5116 CLASSES will be filled by the register class used to pass each word
5117 of the operand. The number of words is returned. In case the parameter
5118 should be passed in memory, 0 is returned. As a special case for zero
5119 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5121 BIT_OFFSET is used internally for handling records and specifies offset
5122 of the offset in bits modulo 256 to avoid overflow cases.
5124 See the x86-64 PS ABI for details.
5128 classify_argument (enum machine_mode mode, const_tree type,
5129 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5131 HOST_WIDE_INT bytes =
5132 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5133 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5135 /* Variable sized entities are always passed/returned in memory. */
5139 if (mode != VOIDmode
5140 && targetm.calls.must_pass_in_stack (mode, type))
5143 if (type && AGGREGATE_TYPE_P (type))
5147 enum x86_64_reg_class subclasses[MAX_CLASSES];
5149 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5153 for (i = 0; i < words; i++)
5154 classes[i] = X86_64_NO_CLASS;
5156 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5157 signalize memory class, so handle it as special case. */
5160 classes[0] = X86_64_NO_CLASS;
5164 /* Classify each field of record and merge classes. */
5165 switch (TREE_CODE (type))
5168 /* And now merge the fields of structure. */
5169 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5171 if (TREE_CODE (field) == FIELD_DECL)
5175 if (TREE_TYPE (field) == error_mark_node)
5178 /* Bitfields are always classified as integer. Handle them
5179 early, since later code would consider them to be
5180 misaligned integers. */
5181 if (DECL_BIT_FIELD (field))
5183 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5184 i < ((int_bit_position (field) + (bit_offset % 64))
5185 + tree_low_cst (DECL_SIZE (field), 0)
5188 merge_classes (X86_64_INTEGER_CLASS,
5195 type = TREE_TYPE (field);
5197 /* Flexible array member is ignored. */
5198 if (TYPE_MODE (type) == BLKmode
5199 && TREE_CODE (type) == ARRAY_TYPE
5200 && TYPE_SIZE (type) == NULL_TREE
5201 && TYPE_DOMAIN (type) != NULL_TREE
5202 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5207 if (!warned && warn_psabi)
5210 inform (input_location,
5211 "The ABI of passing struct with"
5212 " a flexible array member has"
5213 " changed in GCC 4.4");
5217 num = classify_argument (TYPE_MODE (type), type,
5219 (int_bit_position (field)
5220 + bit_offset) % 256);
5223 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5224 for (i = 0; i < num && (i + pos) < words; i++)
5226 merge_classes (subclasses[i], classes[i + pos]);
5233 /* Arrays are handled as small records. */
5236 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5237 TREE_TYPE (type), subclasses, bit_offset);
5241 /* The partial classes are now full classes. */
5242 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5243 subclasses[0] = X86_64_SSE_CLASS;
5244 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5245 && !((bit_offset % 64) == 0 && bytes == 4))
5246 subclasses[0] = X86_64_INTEGER_CLASS;
5248 for (i = 0; i < words; i++)
5249 classes[i] = subclasses[i % num];
5254 case QUAL_UNION_TYPE:
5255 /* Unions are similar to RECORD_TYPE but offset is always 0.
5257 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5259 if (TREE_CODE (field) == FIELD_DECL)
5263 if (TREE_TYPE (field) == error_mark_node)
5266 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5267 TREE_TYPE (field), subclasses,
5271 for (i = 0; i < num; i++)
5272 classes[i] = merge_classes (subclasses[i], classes[i]);
5283 /* When size > 16 bytes, if the first one isn't
5284 X86_64_SSE_CLASS or any other ones aren't
5285 X86_64_SSEUP_CLASS, everything should be passed in
5287 if (classes[0] != X86_64_SSE_CLASS)
5290 for (i = 1; i < words; i++)
5291 if (classes[i] != X86_64_SSEUP_CLASS)
5295 /* Final merger cleanup. */
5296 for (i = 0; i < words; i++)
5298 /* If one class is MEMORY, everything should be passed in
5300 if (classes[i] == X86_64_MEMORY_CLASS)
5303 /* The X86_64_SSEUP_CLASS should be always preceded by
5304 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5305 if (classes[i] == X86_64_SSEUP_CLASS
5306 && classes[i - 1] != X86_64_SSE_CLASS
5307 && classes[i - 1] != X86_64_SSEUP_CLASS)
5309 /* The first one should never be X86_64_SSEUP_CLASS. */
5310 gcc_assert (i != 0);
5311 classes[i] = X86_64_SSE_CLASS;
5314 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5315 everything should be passed in memory. */
5316 if (classes[i] == X86_64_X87UP_CLASS
5317 && (classes[i - 1] != X86_64_X87_CLASS))
5321 /* The first one should never be X86_64_X87UP_CLASS. */
5322 gcc_assert (i != 0);
5323 if (!warned && warn_psabi)
5326 inform (input_location,
5327 "The ABI of passing union with long double"
5328 " has changed in GCC 4.4");
5336 /* Compute alignment needed. We align all types to natural boundaries with
5337 exception of XFmode that is aligned to 64bits. */
5338 if (mode != VOIDmode && mode != BLKmode)
5340 int mode_alignment = GET_MODE_BITSIZE (mode);
5343 mode_alignment = 128;
5344 else if (mode == XCmode)
5345 mode_alignment = 256;
5346 if (COMPLEX_MODE_P (mode))
5347 mode_alignment /= 2;
5348 /* Misaligned fields are always returned in memory. */
5349 if (bit_offset % mode_alignment)
5353 /* for V1xx modes, just use the base mode */
5354 if (VECTOR_MODE_P (mode) && mode != V1DImode
5355 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5356 mode = GET_MODE_INNER (mode);
5358 /* Classification of atomic types. */
5363 classes[0] = X86_64_SSE_CLASS;
5366 classes[0] = X86_64_SSE_CLASS;
5367 classes[1] = X86_64_SSEUP_CLASS;
5377 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5381 classes[0] = X86_64_INTEGERSI_CLASS;
5384 else if (size <= 64)
5386 classes[0] = X86_64_INTEGER_CLASS;
5389 else if (size <= 64+32)
5391 classes[0] = X86_64_INTEGER_CLASS;
5392 classes[1] = X86_64_INTEGERSI_CLASS;
5395 else if (size <= 64+64)
5397 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5405 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5409 /* OImode shouldn't be used directly. */
5414 if (!(bit_offset % 64))
5415 classes[0] = X86_64_SSESF_CLASS;
5417 classes[0] = X86_64_SSE_CLASS;
5420 classes[0] = X86_64_SSEDF_CLASS;
5423 classes[0] = X86_64_X87_CLASS;
5424 classes[1] = X86_64_X87UP_CLASS;
5427 classes[0] = X86_64_SSE_CLASS;
5428 classes[1] = X86_64_SSEUP_CLASS;
5431 classes[0] = X86_64_SSE_CLASS;
5432 if (!(bit_offset % 64))
5438 if (!warned && warn_psabi)
5441 inform (input_location,
5442 "The ABI of passing structure with complex float"
5443 " member has changed in GCC 4.4");
5445 classes[1] = X86_64_SSESF_CLASS;
5449 classes[0] = X86_64_SSEDF_CLASS;
5450 classes[1] = X86_64_SSEDF_CLASS;
5453 classes[0] = X86_64_COMPLEX_X87_CLASS;
5456 /* This modes is larger than 16 bytes. */
5464 classes[0] = X86_64_SSE_CLASS;
5465 classes[1] = X86_64_SSEUP_CLASS;
5466 classes[2] = X86_64_SSEUP_CLASS;
5467 classes[3] = X86_64_SSEUP_CLASS;
5475 classes[0] = X86_64_SSE_CLASS;
5476 classes[1] = X86_64_SSEUP_CLASS;
5483 classes[0] = X86_64_SSE_CLASS;
5489 gcc_assert (VECTOR_MODE_P (mode));
5494 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5496 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5497 classes[0] = X86_64_INTEGERSI_CLASS;
5499 classes[0] = X86_64_INTEGER_CLASS;
5500 classes[1] = X86_64_INTEGER_CLASS;
5501 return 1 + (bytes > 8);
5505 /* Examine the argument and return set number of register required in each
5506 class. Return 0 iff parameter should be passed in memory. */
5508 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5509 int *int_nregs, int *sse_nregs)
5511 enum x86_64_reg_class regclass[MAX_CLASSES];
5512 int n = classify_argument (mode, type, regclass, 0);
5518 for (n--; n >= 0; n--)
5519 switch (regclass[n])
5521 case X86_64_INTEGER_CLASS:
5522 case X86_64_INTEGERSI_CLASS:
5525 case X86_64_SSE_CLASS:
5526 case X86_64_SSESF_CLASS:
5527 case X86_64_SSEDF_CLASS:
5530 case X86_64_NO_CLASS:
5531 case X86_64_SSEUP_CLASS:
5533 case X86_64_X87_CLASS:
5534 case X86_64_X87UP_CLASS:
5538 case X86_64_COMPLEX_X87_CLASS:
5539 return in_return ? 2 : 0;
5540 case X86_64_MEMORY_CLASS:
5546 /* Construct container for the argument used by GCC interface. See
5547 FUNCTION_ARG for the detailed description. */
5550 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5551 const_tree type, int in_return, int nintregs, int nsseregs,
5552 const int *intreg, int sse_regno)
5554 /* The following variables hold the static issued_error state. */
5555 static bool issued_sse_arg_error;
5556 static bool issued_sse_ret_error;
5557 static bool issued_x87_ret_error;
5559 enum machine_mode tmpmode;
5561 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5562 enum x86_64_reg_class regclass[MAX_CLASSES];
5566 int needed_sseregs, needed_intregs;
5567 rtx exp[MAX_CLASSES];
5570 n = classify_argument (mode, type, regclass, 0);
5573 if (!examine_argument (mode, type, in_return, &needed_intregs,
5576 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5579 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5580 some less clueful developer tries to use floating-point anyway. */
5581 if (needed_sseregs && !TARGET_SSE)
5585 if (!issued_sse_ret_error)
5587 error ("SSE register return with SSE disabled");
5588 issued_sse_ret_error = true;
5591 else if (!issued_sse_arg_error)
5593 error ("SSE register argument with SSE disabled");
5594 issued_sse_arg_error = true;
5599 /* Likewise, error if the ABI requires us to return values in the
5600 x87 registers and the user specified -mno-80387. */
5601 if (!TARGET_80387 && in_return)
5602 for (i = 0; i < n; i++)
5603 if (regclass[i] == X86_64_X87_CLASS
5604 || regclass[i] == X86_64_X87UP_CLASS
5605 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5607 if (!issued_x87_ret_error)
5609 error ("x87 register return with x87 disabled");
5610 issued_x87_ret_error = true;
5615 /* First construct simple cases. Avoid SCmode, since we want to use
5616 single register to pass this type. */
5617 if (n == 1 && mode != SCmode)
5618 switch (regclass[0])
5620 case X86_64_INTEGER_CLASS:
5621 case X86_64_INTEGERSI_CLASS:
5622 return gen_rtx_REG (mode, intreg[0]);
5623 case X86_64_SSE_CLASS:
5624 case X86_64_SSESF_CLASS:
5625 case X86_64_SSEDF_CLASS:
5626 if (mode != BLKmode)
5627 return gen_reg_or_parallel (mode, orig_mode,
5628 SSE_REGNO (sse_regno));
5630 case X86_64_X87_CLASS:
5631 case X86_64_COMPLEX_X87_CLASS:
5632 return gen_rtx_REG (mode, FIRST_STACK_REG);
5633 case X86_64_NO_CLASS:
5634 /* Zero sized array, struct or class. */
5639 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5640 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5641 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5643 && regclass[0] == X86_64_SSE_CLASS
5644 && regclass[1] == X86_64_SSEUP_CLASS
5645 && regclass[2] == X86_64_SSEUP_CLASS
5646 && regclass[3] == X86_64_SSEUP_CLASS
5648 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5651 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5652 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5653 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5654 && regclass[1] == X86_64_INTEGER_CLASS
5655 && (mode == CDImode || mode == TImode || mode == TFmode)
5656 && intreg[0] + 1 == intreg[1])
5657 return gen_rtx_REG (mode, intreg[0]);
5659 /* Otherwise figure out the entries of the PARALLEL. */
5660 for (i = 0; i < n; i++)
5664 switch (regclass[i])
5666 case X86_64_NO_CLASS:
5668 case X86_64_INTEGER_CLASS:
5669 case X86_64_INTEGERSI_CLASS:
5670 /* Merge TImodes on aligned occasions here too. */
5671 if (i * 8 + 8 > bytes)
5672 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5673 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5677 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5678 if (tmpmode == BLKmode)
5680 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5681 gen_rtx_REG (tmpmode, *intreg),
5685 case X86_64_SSESF_CLASS:
5686 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5687 gen_rtx_REG (SFmode,
5688 SSE_REGNO (sse_regno)),
5692 case X86_64_SSEDF_CLASS:
5693 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5694 gen_rtx_REG (DFmode,
5695 SSE_REGNO (sse_regno)),
5699 case X86_64_SSE_CLASS:
5707 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5717 && regclass[1] == X86_64_SSEUP_CLASS
5718 && regclass[2] == X86_64_SSEUP_CLASS
5719 && regclass[3] == X86_64_SSEUP_CLASS);
5726 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5727 gen_rtx_REG (tmpmode,
5728 SSE_REGNO (sse_regno)),
5737 /* Empty aligned struct, union or class. */
5741 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5742 for (i = 0; i < nexps; i++)
5743 XVECEXP (ret, 0, i) = exp [i];
5747 /* Update the data in CUM to advance over an argument of mode MODE
5748 and data type TYPE. (TYPE is null for libcalls where that information
5749 may not be available.) */
5752 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5753 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5769 cum->words += words;
5770 cum->nregs -= words;
5771 cum->regno += words;
5773 if (cum->nregs <= 0)
5781 /* OImode shouldn't be used directly. */
5785 if (cum->float_in_sse < 2)
5788 if (cum->float_in_sse < 1)
5805 if (!type || !AGGREGATE_TYPE_P (type))
5807 cum->sse_words += words;
5808 cum->sse_nregs -= 1;
5809 cum->sse_regno += 1;
5810 if (cum->sse_nregs <= 0)
5823 if (!type || !AGGREGATE_TYPE_P (type))
5825 cum->mmx_words += words;
5826 cum->mmx_nregs -= 1;
5827 cum->mmx_regno += 1;
5828 if (cum->mmx_nregs <= 0)
5839 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5840 tree type, HOST_WIDE_INT words, int named)
5842 int int_nregs, sse_nregs;
5844 /* Unnamed 256bit vector mode parameters are passed on stack. */
5845 if (!named && VALID_AVX256_REG_MODE (mode))
5848 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5849 cum->words += words;
5850 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5852 cum->nregs -= int_nregs;
5853 cum->sse_nregs -= sse_nregs;
5854 cum->regno += int_nregs;
5855 cum->sse_regno += sse_nregs;
5858 cum->words += words;
5862 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5863 HOST_WIDE_INT words)
5865 /* Otherwise, this should be passed indirect. */
5866 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5868 cum->words += words;
5877 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5878 tree type, int named)
5880 HOST_WIDE_INT bytes, words;
5882 if (mode == BLKmode)
5883 bytes = int_size_in_bytes (type);
5885 bytes = GET_MODE_SIZE (mode);
5886 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5889 mode = type_natural_mode (type, NULL);
5891 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5892 function_arg_advance_ms_64 (cum, bytes, words);
5893 else if (TARGET_64BIT)
5894 function_arg_advance_64 (cum, mode, type, words, named);
5896 function_arg_advance_32 (cum, mode, type, bytes, words);
5899 /* Define where to put the arguments to a function.
5900 Value is zero to push the argument on the stack,
5901 or a hard register in which to store the argument.
5903 MODE is the argument's machine mode.
5904 TYPE is the data type of the argument (as a tree).
5905 This is null for libcalls where that information may
5907 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5908 the preceding args and about the function being called.
5909 NAMED is nonzero if this argument is a named parameter
5910 (otherwise it is an extra parameter matching an ellipsis). */
5913 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5914 enum machine_mode orig_mode, tree type,
5915 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5917 static bool warnedsse, warnedmmx;
5919 /* Avoid the AL settings for the Unix64 ABI. */
5920 if (mode == VOIDmode)
5936 if (words <= cum->nregs)
5938 int regno = cum->regno;
5940 /* Fastcall allocates the first two DWORD (SImode) or
5941 smaller arguments to ECX and EDX if it isn't an
5947 || (type && AGGREGATE_TYPE_P (type)))
5950 /* ECX not EAX is the first allocated register. */
5951 if (regno == AX_REG)
5954 return gen_rtx_REG (mode, regno);
5959 if (cum->float_in_sse < 2)
5962 if (cum->float_in_sse < 1)
5966 /* In 32bit, we pass TImode in xmm registers. */
5973 if (!type || !AGGREGATE_TYPE_P (type))
5975 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5978 warning (0, "SSE vector argument without SSE enabled "
5982 return gen_reg_or_parallel (mode, orig_mode,
5983 cum->sse_regno + FIRST_SSE_REG);
5988 /* OImode shouldn't be used directly. */
5997 if (!type || !AGGREGATE_TYPE_P (type))
6000 return gen_reg_or_parallel (mode, orig_mode,
6001 cum->sse_regno + FIRST_SSE_REG);
6010 if (!type || !AGGREGATE_TYPE_P (type))
6012 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
6015 warning (0, "MMX vector argument without MMX enabled "
6019 return gen_reg_or_parallel (mode, orig_mode,
6020 cum->mmx_regno + FIRST_MMX_REG);
6029 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6030 enum machine_mode orig_mode, tree type, int named)
6032 /* Handle a hidden AL argument containing number of registers
6033 for varargs x86-64 functions. */
6034 if (mode == VOIDmode)
6035 return GEN_INT (cum->maybe_vaarg
6036 ? (cum->sse_nregs < 0
6037 ? (cum->call_abi == ix86_abi
6039 : (ix86_abi != SYSV_ABI
6040 ? X86_64_SSE_REGPARM_MAX
6041 : X86_64_MS_SSE_REGPARM_MAX))
6056 /* Unnamed 256bit vector mode parameters are passed on stack. */
6062 return construct_container (mode, orig_mode, type, 0, cum->nregs,
6064 &x86_64_int_parameter_registers [cum->regno],
6069 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6070 enum machine_mode orig_mode, int named,
6071 HOST_WIDE_INT bytes)
6075 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6076 We use value of -2 to specify that current function call is MSABI. */
6077 if (mode == VOIDmode)
6078 return GEN_INT (-2);
6080 /* If we've run out of registers, it goes on the stack. */
6081 if (cum->nregs == 0)
6084 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6086 /* Only floating point modes are passed in anything but integer regs. */
6087 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6090 regno = cum->regno + FIRST_SSE_REG;
6095 /* Unnamed floating parameters are passed in both the
6096 SSE and integer registers. */
6097 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6098 t2 = gen_rtx_REG (mode, regno);
6099 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6100 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6101 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6104 /* Handle aggregated types passed in register. */
6105 if (orig_mode == BLKmode)
6107 if (bytes > 0 && bytes <= 8)
6108 mode = (bytes > 4 ? DImode : SImode);
6109 if (mode == BLKmode)
6113 return gen_reg_or_parallel (mode, orig_mode, regno);
6117 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6118 tree type, int named)
6120 enum machine_mode mode = omode;
6121 HOST_WIDE_INT bytes, words;
6123 if (mode == BLKmode)
6124 bytes = int_size_in_bytes (type);
6126 bytes = GET_MODE_SIZE (mode);
6127 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6129 /* To simplify the code below, represent vector types with a vector mode
6130 even if MMX/SSE are not active. */
6131 if (type && TREE_CODE (type) == VECTOR_TYPE)
6132 mode = type_natural_mode (type, cum);
6134 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6135 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6136 else if (TARGET_64BIT)
6137 return function_arg_64 (cum, mode, omode, type, named);
6139 return function_arg_32 (cum, mode, omode, type, bytes, words);
6142 /* A C expression that indicates when an argument must be passed by
6143 reference. If nonzero for an argument, a copy of that argument is
6144 made in memory and a pointer to the argument is passed instead of
6145 the argument itself. The pointer is passed in whatever way is
6146 appropriate for passing a pointer to that type. */
6149 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6150 enum machine_mode mode ATTRIBUTE_UNUSED,
6151 const_tree type, bool named ATTRIBUTE_UNUSED)
6153 /* See Windows x64 Software Convention. */
6154 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6156 int msize = (int) GET_MODE_SIZE (mode);
6159 /* Arrays are passed by reference. */
6160 if (TREE_CODE (type) == ARRAY_TYPE)
6163 if (AGGREGATE_TYPE_P (type))
6165 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6166 are passed by reference. */
6167 msize = int_size_in_bytes (type);
6171 /* __m128 is passed by reference. */
6173 case 1: case 2: case 4: case 8:
6179 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6185 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6188 contains_aligned_value_p (tree type)
6190 enum machine_mode mode = TYPE_MODE (type);
6191 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6195 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6197 if (TYPE_ALIGN (type) < 128)
6200 if (AGGREGATE_TYPE_P (type))
6202 /* Walk the aggregates recursively. */
6203 switch (TREE_CODE (type))
6207 case QUAL_UNION_TYPE:
6211 /* Walk all the structure fields. */
6212 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6214 if (TREE_CODE (field) == FIELD_DECL
6215 && contains_aligned_value_p (TREE_TYPE (field)))
6222 /* Just for use if some languages passes arrays by value. */
6223 if (contains_aligned_value_p (TREE_TYPE (type)))
6234 /* Gives the alignment boundary, in bits, of an argument with the
6235 specified mode and type. */
6238 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6243 /* Since canonical type is used for call, we convert it to
6244 canonical type if needed. */
6245 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6246 type = TYPE_CANONICAL (type);
6247 align = TYPE_ALIGN (type);
6250 align = GET_MODE_ALIGNMENT (mode);
6251 if (align < PARM_BOUNDARY)
6252 align = PARM_BOUNDARY;
6253 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6254 natural boundaries. */
6255 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6257 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6258 make an exception for SSE modes since these require 128bit
6261 The handling here differs from field_alignment. ICC aligns MMX
6262 arguments to 4 byte boundaries, while structure fields are aligned
6263 to 8 byte boundaries. */
6266 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6267 align = PARM_BOUNDARY;
6271 if (!contains_aligned_value_p (type))
6272 align = PARM_BOUNDARY;
6275 if (align > BIGGEST_ALIGNMENT)
6276 align = BIGGEST_ALIGNMENT;
6280 /* Return true if N is a possible register number of function value. */
6283 ix86_function_value_regno_p (int regno)
6290 case FIRST_FLOAT_REG:
6291 /* TODO: The function should depend on current function ABI but
6292 builtins.c would need updating then. Therefore we use the
6294 if (TARGET_64BIT && ix86_abi == MS_ABI)
6296 return TARGET_FLOAT_RETURNS_IN_80387;
6302 if (TARGET_MACHO || TARGET_64BIT)
6310 /* Define how to find the value returned by a function.
6311 VALTYPE is the data type of the value (as a tree).
6312 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6313 otherwise, FUNC is 0. */
6316 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6317 const_tree fntype, const_tree fn)
6321 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6322 we normally prevent this case when mmx is not available. However
6323 some ABIs may require the result to be returned like DImode. */
6324 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6325 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6327 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6328 we prevent this case when sse is not available. However some ABIs
6329 may require the result to be returned like integer TImode. */
6330 else if (mode == TImode
6331 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6332 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6334 /* 32-byte vector modes in %ymm0. */
6335 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6336 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6338 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6339 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6340 regno = FIRST_FLOAT_REG;
6342 /* Most things go in %eax. */
6345 /* Override FP return register with %xmm0 for local functions when
6346 SSE math is enabled or for functions with sseregparm attribute. */
6347 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6349 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6350 if ((sse_level >= 1 && mode == SFmode)
6351 || (sse_level == 2 && mode == DFmode))
6352 regno = FIRST_SSE_REG;
6355 /* OImode shouldn't be used directly. */
6356 gcc_assert (mode != OImode);
6358 return gen_rtx_REG (orig_mode, regno);
6362 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6367 /* Handle libcalls, which don't provide a type node. */
6368 if (valtype == NULL)
6380 return gen_rtx_REG (mode, FIRST_SSE_REG);
6383 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6387 return gen_rtx_REG (mode, AX_REG);
6391 ret = construct_container (mode, orig_mode, valtype, 1,
6392 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6393 x86_64_int_return_registers, 0);
6395 /* For zero sized structures, construct_container returns NULL, but we
6396 need to keep rest of compiler happy by returning meaningful value. */
6398 ret = gen_rtx_REG (orig_mode, AX_REG);
6404 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6406 unsigned int regno = AX_REG;
6410 switch (GET_MODE_SIZE (mode))
6413 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6414 && !COMPLEX_MODE_P (mode))
6415 regno = FIRST_SSE_REG;
6419 if (mode == SFmode || mode == DFmode)
6420 regno = FIRST_SSE_REG;
6426 return gen_rtx_REG (orig_mode, regno);
6430 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6431 enum machine_mode orig_mode, enum machine_mode mode)
6433 const_tree fn, fntype;
6436 if (fntype_or_decl && DECL_P (fntype_or_decl))
6437 fn = fntype_or_decl;
6438 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6440 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6441 return function_value_ms_64 (orig_mode, mode);
6442 else if (TARGET_64BIT)
6443 return function_value_64 (orig_mode, mode, valtype);
6445 return function_value_32 (orig_mode, mode, fntype, fn);
6449 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6450 bool outgoing ATTRIBUTE_UNUSED)
6452 enum machine_mode mode, orig_mode;
6454 orig_mode = TYPE_MODE (valtype);
6455 mode = type_natural_mode (valtype, NULL);
6456 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6460 ix86_libcall_value (enum machine_mode mode)
6462 return ix86_function_value_1 (NULL, NULL, mode, mode);
6465 /* Return true iff type is returned in memory. */
6467 static int ATTRIBUTE_UNUSED
6468 return_in_memory_32 (const_tree type, enum machine_mode mode)
6472 if (mode == BLKmode)
6475 size = int_size_in_bytes (type);
6477 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6480 if (VECTOR_MODE_P (mode) || mode == TImode)
6482 /* User-created vectors small enough to fit in EAX. */
6486 /* MMX/3dNow values are returned in MM0,
6487 except when it doesn't exits. */
6489 return (TARGET_MMX ? 0 : 1);
6491 /* SSE values are returned in XMM0, except when it doesn't exist. */
6493 return (TARGET_SSE ? 0 : 1);
6495 /* AVX values are returned in YMM0, except when it doesn't exist. */
6497 return TARGET_AVX ? 0 : 1;
6506 /* OImode shouldn't be used directly. */
6507 gcc_assert (mode != OImode);
6512 static int ATTRIBUTE_UNUSED
6513 return_in_memory_64 (const_tree type, enum machine_mode mode)
6515 int needed_intregs, needed_sseregs;
6516 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6519 static int ATTRIBUTE_UNUSED
6520 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6522 HOST_WIDE_INT size = int_size_in_bytes (type);
6524 /* __m128 is returned in xmm0. */
6525 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6526 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6529 /* Otherwise, the size must be exactly in [1248]. */
6530 return (size != 1 && size != 2 && size != 4 && size != 8);
6534 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6536 #ifdef SUBTARGET_RETURN_IN_MEMORY
6537 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6539 const enum machine_mode mode = type_natural_mode (type, NULL);
6543 if (ix86_function_type_abi (fntype) == MS_ABI)
6544 return return_in_memory_ms_64 (type, mode);
6546 return return_in_memory_64 (type, mode);
6549 return return_in_memory_32 (type, mode);
6553 /* Return false iff TYPE is returned in memory. This version is used
6554 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6555 but differs notably in that when MMX is available, 8-byte vectors
6556 are returned in memory, rather than in MMX registers. */
6559 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6562 enum machine_mode mode = type_natural_mode (type, NULL);
6565 return return_in_memory_64 (type, mode);
6567 if (mode == BLKmode)
6570 size = int_size_in_bytes (type);
6572 if (VECTOR_MODE_P (mode))
6574 /* Return in memory only if MMX registers *are* available. This
6575 seems backwards, but it is consistent with the existing
6582 else if (mode == TImode)
6584 else if (mode == XFmode)
6590 /* When returning SSE vector types, we have a choice of either
6591 (1) being abi incompatible with a -march switch, or
6592 (2) generating an error.
6593 Given no good solution, I think the safest thing is one warning.
6594 The user won't be able to use -Werror, but....
6596 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6597 called in response to actually generating a caller or callee that
6598 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6599 via aggregate_value_p for general type probing from tree-ssa. */
6602 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6604 static bool warnedsse, warnedmmx;
6606 if (!TARGET_64BIT && type)
6608 /* Look at the return type of the function, not the function type. */
6609 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6611 if (!TARGET_SSE && !warnedsse)
6614 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6617 warning (0, "SSE vector return without SSE enabled "
6622 if (!TARGET_MMX && !warnedmmx)
6624 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6627 warning (0, "MMX vector return without MMX enabled "
6637 /* Create the va_list data type. */
6639 /* Returns the calling convention specific va_list date type.
6640 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6643 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6645 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6647 /* For i386 we use plain pointer to argument area. */
6648 if (!TARGET_64BIT || abi == MS_ABI)
6649 return build_pointer_type (char_type_node);
6651 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6652 type_decl = build_decl (BUILTINS_LOCATION,
6653 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6655 f_gpr = build_decl (BUILTINS_LOCATION,
6656 FIELD_DECL, get_identifier ("gp_offset"),
6657 unsigned_type_node);
6658 f_fpr = build_decl (BUILTINS_LOCATION,
6659 FIELD_DECL, get_identifier ("fp_offset"),
6660 unsigned_type_node);
6661 f_ovf = build_decl (BUILTINS_LOCATION,
6662 FIELD_DECL, get_identifier ("overflow_arg_area"),
6664 f_sav = build_decl (BUILTINS_LOCATION,
6665 FIELD_DECL, get_identifier ("reg_save_area"),
6668 va_list_gpr_counter_field = f_gpr;
6669 va_list_fpr_counter_field = f_fpr;
6671 DECL_FIELD_CONTEXT (f_gpr) = record;
6672 DECL_FIELD_CONTEXT (f_fpr) = record;
6673 DECL_FIELD_CONTEXT (f_ovf) = record;
6674 DECL_FIELD_CONTEXT (f_sav) = record;
6676 TREE_CHAIN (record) = type_decl;
6677 TYPE_NAME (record) = type_decl;
6678 TYPE_FIELDS (record) = f_gpr;
6679 TREE_CHAIN (f_gpr) = f_fpr;
6680 TREE_CHAIN (f_fpr) = f_ovf;
6681 TREE_CHAIN (f_ovf) = f_sav;
6683 layout_type (record);
6685 /* The correct type is an array type of one element. */
6686 return build_array_type (record, build_index_type (size_zero_node));
6689 /* Setup the builtin va_list data type and for 64-bit the additional
6690 calling convention specific va_list data types. */
6693 ix86_build_builtin_va_list (void)
6695 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6697 /* Initialize abi specific va_list builtin types. */
6701 if (ix86_abi == MS_ABI)
6703 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6704 if (TREE_CODE (t) != RECORD_TYPE)
6705 t = build_variant_type_copy (t);
6706 sysv_va_list_type_node = t;
6711 if (TREE_CODE (t) != RECORD_TYPE)
6712 t = build_variant_type_copy (t);
6713 sysv_va_list_type_node = t;
6715 if (ix86_abi != MS_ABI)
6717 t = ix86_build_builtin_va_list_abi (MS_ABI);
6718 if (TREE_CODE (t) != RECORD_TYPE)
6719 t = build_variant_type_copy (t);
6720 ms_va_list_type_node = t;
6725 if (TREE_CODE (t) != RECORD_TYPE)
6726 t = build_variant_type_copy (t);
6727 ms_va_list_type_node = t;
6734 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6737 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6746 int regparm = ix86_regparm;
6748 if (cum->call_abi != ix86_abi)
6749 regparm = (ix86_abi != SYSV_ABI
6750 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6752 /* GPR size of varargs save area. */
6753 if (cfun->va_list_gpr_size)
6754 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6756 ix86_varargs_gpr_size = 0;
6758 /* FPR size of varargs save area. We don't need it if we don't pass
6759 anything in SSE registers. */
6760 if (cum->sse_nregs && cfun->va_list_fpr_size)
6761 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6763 ix86_varargs_fpr_size = 0;
6765 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6768 save_area = frame_pointer_rtx;
6769 set = get_varargs_alias_set ();
6771 for (i = cum->regno;
6773 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6776 mem = gen_rtx_MEM (Pmode,
6777 plus_constant (save_area, i * UNITS_PER_WORD));
6778 MEM_NOTRAP_P (mem) = 1;
6779 set_mem_alias_set (mem, set);
6780 emit_move_insn (mem, gen_rtx_REG (Pmode,
6781 x86_64_int_parameter_registers[i]));
6784 if (ix86_varargs_fpr_size)
6786 /* Now emit code to save SSE registers. The AX parameter contains number
6787 of SSE parameter registers used to call this function. We use
6788 sse_prologue_save insn template that produces computed jump across
6789 SSE saves. We need some preparation work to get this working. */
6791 label = gen_label_rtx ();
6792 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6794 /* Compute address to jump to :
6795 label - eax*4 + nnamed_sse_arguments*4 Or
6796 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6797 tmp_reg = gen_reg_rtx (Pmode);
6798 nsse_reg = gen_reg_rtx (Pmode);
6799 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6800 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6801 gen_rtx_MULT (Pmode, nsse_reg,
6804 /* vmovaps is one byte longer than movaps. */
6806 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6807 gen_rtx_PLUS (Pmode, tmp_reg,
6813 gen_rtx_CONST (DImode,
6814 gen_rtx_PLUS (DImode,
6816 GEN_INT (cum->sse_regno
6817 * (TARGET_AVX ? 5 : 4)))));
6819 emit_move_insn (nsse_reg, label_ref);
6820 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6822 /* Compute address of memory block we save into. We always use pointer
6823 pointing 127 bytes after first byte to store - this is needed to keep
6824 instruction size limited by 4 bytes (5 bytes for AVX) with one
6825 byte displacement. */
6826 tmp_reg = gen_reg_rtx (Pmode);
6827 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6828 plus_constant (save_area,
6829 ix86_varargs_gpr_size + 127)));
6830 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6831 MEM_NOTRAP_P (mem) = 1;
6832 set_mem_alias_set (mem, set);
6833 set_mem_align (mem, BITS_PER_WORD);
6835 /* And finally do the dirty job! */
6836 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6837 GEN_INT (cum->sse_regno), label));
6842 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6844 alias_set_type set = get_varargs_alias_set ();
6847 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6851 mem = gen_rtx_MEM (Pmode,
6852 plus_constant (virtual_incoming_args_rtx,
6853 i * UNITS_PER_WORD));
6854 MEM_NOTRAP_P (mem) = 1;
6855 set_mem_alias_set (mem, set);
6857 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6858 emit_move_insn (mem, reg);
6863 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6864 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6867 CUMULATIVE_ARGS next_cum;
6870 /* This argument doesn't appear to be used anymore. Which is good,
6871 because the old code here didn't suppress rtl generation. */
6872 gcc_assert (!no_rtl);
6877 fntype = TREE_TYPE (current_function_decl);
6879 /* For varargs, we do not want to skip the dummy va_dcl argument.
6880 For stdargs, we do want to skip the last named argument. */
6882 if (stdarg_p (fntype))
6883 function_arg_advance (&next_cum, mode, type, 1);
6885 if (cum->call_abi == MS_ABI)
6886 setup_incoming_varargs_ms_64 (&next_cum);
6888 setup_incoming_varargs_64 (&next_cum);
6891 /* Checks if TYPE is of kind va_list char *. */
6894 is_va_list_char_pointer (tree type)
6898 /* For 32-bit it is always true. */
6901 canonic = ix86_canonical_va_list_type (type);
6902 return (canonic == ms_va_list_type_node
6903 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6906 /* Implement va_start. */
6909 ix86_va_start (tree valist, rtx nextarg)
6911 HOST_WIDE_INT words, n_gpr, n_fpr;
6912 tree f_gpr, f_fpr, f_ovf, f_sav;
6913 tree gpr, fpr, ovf, sav, t;
6916 /* Only 64bit target needs something special. */
6917 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6919 std_expand_builtin_va_start (valist, nextarg);
6923 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6924 f_fpr = TREE_CHAIN (f_gpr);
6925 f_ovf = TREE_CHAIN (f_fpr);
6926 f_sav = TREE_CHAIN (f_ovf);
6928 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6929 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6930 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6931 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6932 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6934 /* Count number of gp and fp argument registers used. */
6935 words = crtl->args.info.words;
6936 n_gpr = crtl->args.info.regno;
6937 n_fpr = crtl->args.info.sse_regno;
6939 if (cfun->va_list_gpr_size)
6941 type = TREE_TYPE (gpr);
6942 t = build2 (MODIFY_EXPR, type,
6943 gpr, build_int_cst (type, n_gpr * 8));
6944 TREE_SIDE_EFFECTS (t) = 1;
6945 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6948 if (TARGET_SSE && cfun->va_list_fpr_size)
6950 type = TREE_TYPE (fpr);
6951 t = build2 (MODIFY_EXPR, type, fpr,
6952 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6953 TREE_SIDE_EFFECTS (t) = 1;
6954 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6957 /* Find the overflow area. */
6958 type = TREE_TYPE (ovf);
6959 t = make_tree (type, crtl->args.internal_arg_pointer);
6961 t = build2 (POINTER_PLUS_EXPR, type, t,
6962 size_int (words * UNITS_PER_WORD));
6963 t = build2 (MODIFY_EXPR, type, ovf, t);
6964 TREE_SIDE_EFFECTS (t) = 1;
6965 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6967 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6969 /* Find the register save area.
6970 Prologue of the function save it right above stack frame. */
6971 type = TREE_TYPE (sav);
6972 t = make_tree (type, frame_pointer_rtx);
6973 if (!ix86_varargs_gpr_size)
6974 t = build2 (POINTER_PLUS_EXPR, type, t,
6975 size_int (-8 * X86_64_REGPARM_MAX));
6976 t = build2 (MODIFY_EXPR, type, sav, t);
6977 TREE_SIDE_EFFECTS (t) = 1;
6978 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6982 /* Implement va_arg. */
6985 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6988 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6989 tree f_gpr, f_fpr, f_ovf, f_sav;
6990 tree gpr, fpr, ovf, sav, t;
6992 tree lab_false, lab_over = NULL_TREE;
6997 enum machine_mode nat_mode;
7000 /* Only 64bit target needs something special. */
7001 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
7002 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
7004 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
7005 f_fpr = TREE_CHAIN (f_gpr);
7006 f_ovf = TREE_CHAIN (f_fpr);
7007 f_sav = TREE_CHAIN (f_ovf);
7009 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
7010 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
7011 valist = build_va_arg_indirect_ref (valist);
7012 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7013 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7014 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7016 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
7018 type = build_pointer_type (type);
7019 size = int_size_in_bytes (type);
7020 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7022 nat_mode = type_natural_mode (type, NULL);
7031 /* Unnamed 256bit vector mode parameters are passed on stack. */
7032 if (ix86_cfun_abi () == SYSV_ABI)
7039 container = construct_container (nat_mode, TYPE_MODE (type),
7040 type, 0, X86_64_REGPARM_MAX,
7041 X86_64_SSE_REGPARM_MAX, intreg,
7046 /* Pull the value out of the saved registers. */
7048 addr = create_tmp_var (ptr_type_node, "addr");
7052 int needed_intregs, needed_sseregs;
7054 tree int_addr, sse_addr;
7056 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7057 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7059 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
7061 need_temp = (!REG_P (container)
7062 && ((needed_intregs && TYPE_ALIGN (type) > 64)
7063 || TYPE_ALIGN (type) > 128));
7065 /* In case we are passing structure, verify that it is consecutive block
7066 on the register save area. If not we need to do moves. */
7067 if (!need_temp && !REG_P (container))
7069 /* Verify that all registers are strictly consecutive */
7070 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7074 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7076 rtx slot = XVECEXP (container, 0, i);
7077 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7078 || INTVAL (XEXP (slot, 1)) != i * 16)
7086 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7088 rtx slot = XVECEXP (container, 0, i);
7089 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7090 || INTVAL (XEXP (slot, 1)) != i * 8)
7102 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7103 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7106 /* First ensure that we fit completely in registers. */
7109 t = build_int_cst (TREE_TYPE (gpr),
7110 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7111 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7112 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7113 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7114 gimplify_and_add (t, pre_p);
7118 t = build_int_cst (TREE_TYPE (fpr),
7119 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7120 + X86_64_REGPARM_MAX * 8);
7121 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7122 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7123 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7124 gimplify_and_add (t, pre_p);
7127 /* Compute index to start of area used for integer regs. */
7130 /* int_addr = gpr + sav; */
7131 t = fold_convert (sizetype, gpr);
7132 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7133 gimplify_assign (int_addr, t, pre_p);
7137 /* sse_addr = fpr + sav; */
7138 t = fold_convert (sizetype, fpr);
7139 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7140 gimplify_assign (sse_addr, t, pre_p);
7145 tree temp = create_tmp_var (type, "va_arg_tmp");
7148 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7149 gimplify_assign (addr, t, pre_p);
7151 for (i = 0; i < XVECLEN (container, 0); i++)
7153 rtx slot = XVECEXP (container, 0, i);
7154 rtx reg = XEXP (slot, 0);
7155 enum machine_mode mode = GET_MODE (reg);
7156 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7157 tree addr_type = build_pointer_type (piece_type);
7158 tree daddr_type = build_pointer_type_for_mode (piece_type,
7162 tree dest_addr, dest;
7164 if (SSE_REGNO_P (REGNO (reg)))
7166 src_addr = sse_addr;
7167 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7171 src_addr = int_addr;
7172 src_offset = REGNO (reg) * 8;
7174 src_addr = fold_convert (addr_type, src_addr);
7175 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7176 size_int (src_offset));
7177 src = build_va_arg_indirect_ref (src_addr);
7179 dest_addr = fold_convert (daddr_type, addr);
7180 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7181 size_int (INTVAL (XEXP (slot, 1))));
7182 dest = build_va_arg_indirect_ref (dest_addr);
7184 gimplify_assign (dest, src, pre_p);
7190 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7191 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7192 gimplify_assign (gpr, t, pre_p);
7197 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7198 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7199 gimplify_assign (fpr, t, pre_p);
7202 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7204 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7207 /* ... otherwise out of the overflow area. */
7209 /* When we align parameter on stack for caller, if the parameter
7210 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7211 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7212 here with caller. */
7213 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7214 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7215 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7217 /* Care for on-stack alignment if needed. */
7218 if (arg_boundary <= 64
7219 || integer_zerop (TYPE_SIZE (type)))
7223 HOST_WIDE_INT align = arg_boundary / 8;
7224 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7225 size_int (align - 1));
7226 t = fold_convert (sizetype, t);
7227 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7229 t = fold_convert (TREE_TYPE (ovf), t);
7231 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7232 gimplify_assign (addr, t, pre_p);
7234 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7235 size_int (rsize * UNITS_PER_WORD));
7236 gimplify_assign (unshare_expr (ovf), t, pre_p);
7239 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7241 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7242 addr = fold_convert (ptrtype, addr);
7245 addr = build_va_arg_indirect_ref (addr);
7246 return build_va_arg_indirect_ref (addr);
7249 /* Return nonzero if OPNUM's MEM should be matched
7250 in movabs* patterns. */
7253 ix86_check_movabs (rtx insn, int opnum)
7257 set = PATTERN (insn);
7258 if (GET_CODE (set) == PARALLEL)
7259 set = XVECEXP (set, 0, 0);
7260 gcc_assert (GET_CODE (set) == SET);
7261 mem = XEXP (set, opnum);
7262 while (GET_CODE (mem) == SUBREG)
7263 mem = SUBREG_REG (mem);
7264 gcc_assert (MEM_P (mem));
7265 return (volatile_ok || !MEM_VOLATILE_P (mem));
7268 /* Initialize the table of extra 80387 mathematical constants. */
7271 init_ext_80387_constants (void)
7273 static const char * cst[5] =
7275 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7276 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7277 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7278 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7279 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7283 for (i = 0; i < 5; i++)
7285 real_from_string (&ext_80387_constants_table[i], cst[i]);
7286 /* Ensure each constant is rounded to XFmode precision. */
7287 real_convert (&ext_80387_constants_table[i],
7288 XFmode, &ext_80387_constants_table[i]);
7291 ext_80387_constants_init = 1;
7294 /* Return true if the constant is something that can be loaded with
7295 a special instruction. */
7298 standard_80387_constant_p (rtx x)
7300 enum machine_mode mode = GET_MODE (x);
7304 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7307 if (x == CONST0_RTX (mode))
7309 if (x == CONST1_RTX (mode))
7312 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7314 /* For XFmode constants, try to find a special 80387 instruction when
7315 optimizing for size or on those CPUs that benefit from them. */
7317 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7321 if (! ext_80387_constants_init)
7322 init_ext_80387_constants ();
7324 for (i = 0; i < 5; i++)
7325 if (real_identical (&r, &ext_80387_constants_table[i]))
7329 /* Load of the constant -0.0 or -1.0 will be split as
7330 fldz;fchs or fld1;fchs sequence. */
7331 if (real_isnegzero (&r))
7333 if (real_identical (&r, &dconstm1))
7339 /* Return the opcode of the special instruction to be used to load
7343 standard_80387_constant_opcode (rtx x)
7345 switch (standard_80387_constant_p (x))
7369 /* Return the CONST_DOUBLE representing the 80387 constant that is
7370 loaded by the specified special instruction. The argument IDX
7371 matches the return value from standard_80387_constant_p. */
7374 standard_80387_constant_rtx (int idx)
7378 if (! ext_80387_constants_init)
7379 init_ext_80387_constants ();
7395 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7399 /* Return 1 if X is all 0s and 2 if x is all 1s
7400 in supported SSE vector mode. */
7403 standard_sse_constant_p (rtx x)
7405 enum machine_mode mode = GET_MODE (x);
7407 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7409 if (vector_all_ones_operand (x, mode))
7425 /* Return the opcode of the special instruction to be used to load
7429 standard_sse_constant_opcode (rtx insn, rtx x)
7431 switch (standard_sse_constant_p (x))
7434 switch (get_attr_mode (insn))
7437 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7439 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7441 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7443 return "vxorps\t%x0, %x0, %x0";
7445 return "vxorpd\t%x0, %x0, %x0";
7447 return "vpxor\t%x0, %x0, %x0";
7452 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7459 /* Returns 1 if OP contains a symbol reference */
7462 symbolic_reference_mentioned_p (rtx op)
7467 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7470 fmt = GET_RTX_FORMAT (GET_CODE (op));
7471 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7477 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7478 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7482 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7489 /* Return 1 if it is appropriate to emit `ret' instructions in the
7490 body of a function. Do this only if the epilogue is simple, needing a
7491 couple of insns. Prior to reloading, we can't tell how many registers
7492 must be saved, so return 0 then. Return 0 if there is no frame
7493 marker to de-allocate. */
7496 ix86_can_use_return_insn_p (void)
7498 struct ix86_frame frame;
7500 if (! reload_completed || frame_pointer_needed)
7503 /* Don't allow more than 32 pop, since that's all we can do
7504 with one instruction. */
7505 if (crtl->args.pops_args
7506 && crtl->args.size >= 32768)
7509 ix86_compute_frame_layout (&frame);
7510 return frame.to_allocate == 0 && frame.padding0 == 0
7511 && (frame.nregs + frame.nsseregs) == 0;
7514 /* Value should be nonzero if functions must have frame pointers.
7515 Zero means the frame pointer need not be set up (and parms may
7516 be accessed via the stack pointer) in functions that seem suitable. */
7519 ix86_frame_pointer_required (void)
7521 /* If we accessed previous frames, then the generated code expects
7522 to be able to access the saved ebp value in our frame. */
7523 if (cfun->machine->accesses_prev_frame)
7526 /* Several x86 os'es need a frame pointer for other reasons,
7527 usually pertaining to setjmp. */
7528 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7531 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7532 the frame pointer by default. Turn it back on now if we've not
7533 got a leaf function. */
7534 if (TARGET_OMIT_LEAF_FRAME_POINTER
7535 && (!current_function_is_leaf
7536 || ix86_current_function_calls_tls_descriptor))
7545 /* Record that the current function accesses previous call frames. */
7548 ix86_setup_frame_addresses (void)
7550 cfun->machine->accesses_prev_frame = 1;
7553 #ifndef USE_HIDDEN_LINKONCE
7554 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7555 # define USE_HIDDEN_LINKONCE 1
7557 # define USE_HIDDEN_LINKONCE 0
7561 static int pic_labels_used;
7563 /* Fills in the label name that should be used for a pc thunk for
7564 the given register. */
7567 get_pc_thunk_name (char name[32], unsigned int regno)
7569 gcc_assert (!TARGET_64BIT);
7571 if (USE_HIDDEN_LINKONCE)
7572 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7574 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7578 /* This function generates code for -fpic that loads %ebx with
7579 the return address of the caller and then returns. */
7582 ix86_file_end (void)
7587 for (regno = 0; regno < 8; ++regno)
7591 if (! ((pic_labels_used >> regno) & 1))
7594 get_pc_thunk_name (name, regno);
7599 switch_to_section (darwin_sections[text_coal_section]);
7600 fputs ("\t.weak_definition\t", asm_out_file);
7601 assemble_name (asm_out_file, name);
7602 fputs ("\n\t.private_extern\t", asm_out_file);
7603 assemble_name (asm_out_file, name);
7604 fputs ("\n", asm_out_file);
7605 ASM_OUTPUT_LABEL (asm_out_file, name);
7609 if (USE_HIDDEN_LINKONCE)
7613 decl = build_decl (BUILTINS_LOCATION,
7614 FUNCTION_DECL, get_identifier (name),
7616 TREE_PUBLIC (decl) = 1;
7617 TREE_STATIC (decl) = 1;
7618 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7620 (*targetm.asm_out.unique_section) (decl, 0);
7621 switch_to_section (get_named_section (decl, NULL, 0));
7623 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7624 fputs ("\t.hidden\t", asm_out_file);
7625 assemble_name (asm_out_file, name);
7626 putc ('\n', asm_out_file);
7627 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7631 switch_to_section (text_section);
7632 ASM_OUTPUT_LABEL (asm_out_file, name);
7635 xops[0] = gen_rtx_REG (Pmode, regno);
7636 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7637 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7638 output_asm_insn ("ret", xops);
7641 if (NEED_INDICATE_EXEC_STACK)
7642 file_end_indicate_exec_stack ();
7645 /* Emit code for the SET_GOT patterns. */
7648 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7654 if (TARGET_VXWORKS_RTP && flag_pic)
7656 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7657 xops[2] = gen_rtx_MEM (Pmode,
7658 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7659 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7661 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7662 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7663 an unadorned address. */
7664 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7665 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7666 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7670 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7672 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7674 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7677 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7679 output_asm_insn ("call\t%a2", xops);
7682 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7683 is what will be referenced by the Mach-O PIC subsystem. */
7685 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7688 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7689 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7692 output_asm_insn ("pop%z0\t%0", xops);
7697 get_pc_thunk_name (name, REGNO (dest));
7698 pic_labels_used |= 1 << REGNO (dest);
7700 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7701 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7702 output_asm_insn ("call\t%X2", xops);
7703 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7704 is what will be referenced by the Mach-O PIC subsystem. */
7707 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7709 targetm.asm_out.internal_label (asm_out_file, "L",
7710 CODE_LABEL_NUMBER (label));
7717 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7718 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7720 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7725 /* Generate an "push" pattern for input ARG. */
7730 if (ix86_cfa_state->reg == stack_pointer_rtx)
7731 ix86_cfa_state->offset += UNITS_PER_WORD;
7733 return gen_rtx_SET (VOIDmode,
7735 gen_rtx_PRE_DEC (Pmode,
7736 stack_pointer_rtx)),
7740 /* Return >= 0 if there is an unused call-clobbered register available
7741 for the entire function. */
7744 ix86_select_alt_pic_regnum (void)
7746 if (current_function_is_leaf && !crtl->profile
7747 && !ix86_current_function_calls_tls_descriptor)
7750 /* Can't use the same register for both PIC and DRAP. */
7752 drap = REGNO (crtl->drap_reg);
7755 for (i = 2; i >= 0; --i)
7756 if (i != drap && !df_regs_ever_live_p (i))
7760 return INVALID_REGNUM;
7763 /* Return 1 if we need to save REGNO. */
7765 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7767 if (pic_offset_table_rtx
7768 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7769 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7771 || crtl->calls_eh_return
7772 || crtl->uses_const_pool))
7774 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7779 if (crtl->calls_eh_return && maybe_eh_return)
7784 unsigned test = EH_RETURN_DATA_REGNO (i);
7785 if (test == INVALID_REGNUM)
7792 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7795 return (df_regs_ever_live_p (regno)
7796 && !call_used_regs[regno]
7797 && !fixed_regs[regno]
7798 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7801 /* Return number of saved general prupose registers. */
7804 ix86_nsaved_regs (void)
7809 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7810 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7815 /* Return number of saved SSE registrers. */
7818 ix86_nsaved_sseregs (void)
7823 if (ix86_cfun_abi () != MS_ABI)
7825 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7826 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7831 /* Given FROM and TO register numbers, say whether this elimination is
7832 allowed. If stack alignment is needed, we can only replace argument
7833 pointer with hard frame pointer, or replace frame pointer with stack
7834 pointer. Otherwise, frame pointer elimination is automatically
7835 handled and all other eliminations are valid. */
7838 ix86_can_eliminate (const int from, const int to)
7840 if (stack_realign_fp)
7841 return ((from == ARG_POINTER_REGNUM
7842 && to == HARD_FRAME_POINTER_REGNUM)
7843 || (from == FRAME_POINTER_REGNUM
7844 && to == STACK_POINTER_REGNUM));
7846 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7849 /* Return the offset between two registers, one to be eliminated, and the other
7850 its replacement, at the start of a routine. */
7853 ix86_initial_elimination_offset (int from, int to)
7855 struct ix86_frame frame;
7856 ix86_compute_frame_layout (&frame);
7858 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7859 return frame.hard_frame_pointer_offset;
7860 else if (from == FRAME_POINTER_REGNUM
7861 && to == HARD_FRAME_POINTER_REGNUM)
7862 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7865 gcc_assert (to == STACK_POINTER_REGNUM);
7867 if (from == ARG_POINTER_REGNUM)
7868 return frame.stack_pointer_offset;
7870 gcc_assert (from == FRAME_POINTER_REGNUM);
7871 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7875 /* In a dynamically-aligned function, we can't know the offset from
7876 stack pointer to frame pointer, so we must ensure that setjmp
7877 eliminates fp against the hard fp (%ebp) rather than trying to
7878 index from %esp up to the top of the frame across a gap that is
7879 of unknown (at compile-time) size. */
7881 ix86_builtin_setjmp_frame_value (void)
7883 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7886 /* Fill structure ix86_frame about frame of currently computed function. */
7889 ix86_compute_frame_layout (struct ix86_frame *frame)
7891 unsigned int stack_alignment_needed;
7892 HOST_WIDE_INT offset;
7893 unsigned int preferred_alignment;
7894 HOST_WIDE_INT size = get_frame_size ();
7896 frame->nregs = ix86_nsaved_regs ();
7897 frame->nsseregs = ix86_nsaved_sseregs ();
7899 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7900 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7902 /* MS ABI seem to require stack alignment to be always 16 except for function
7904 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7906 preferred_alignment = 16;
7907 stack_alignment_needed = 16;
7908 crtl->preferred_stack_boundary = 128;
7909 crtl->stack_alignment_needed = 128;
7912 gcc_assert (!size || stack_alignment_needed);
7913 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7914 gcc_assert (preferred_alignment <= stack_alignment_needed);
7916 /* During reload iteration the amount of registers saved can change.
7917 Recompute the value as needed. Do not recompute when amount of registers
7918 didn't change as reload does multiple calls to the function and does not
7919 expect the decision to change within single iteration. */
7920 if (!optimize_function_for_size_p (cfun)
7921 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7923 int count = frame->nregs;
7925 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7926 /* The fast prologue uses move instead of push to save registers. This
7927 is significantly longer, but also executes faster as modern hardware
7928 can execute the moves in parallel, but can't do that for push/pop.
7930 Be careful about choosing what prologue to emit: When function takes
7931 many instructions to execute we may use slow version as well as in
7932 case function is known to be outside hot spot (this is known with
7933 feedback only). Weight the size of function by number of registers
7934 to save as it is cheap to use one or two push instructions but very
7935 slow to use many of them. */
7937 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7938 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7939 || (flag_branch_probabilities
7940 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7941 cfun->machine->use_fast_prologue_epilogue = false;
7943 cfun->machine->use_fast_prologue_epilogue
7944 = !expensive_function_p (count);
7946 if (TARGET_PROLOGUE_USING_MOVE
7947 && cfun->machine->use_fast_prologue_epilogue)
7948 frame->save_regs_using_mov = true;
7950 frame->save_regs_using_mov = false;
7952 /* Skip return address. */
7953 offset = UNITS_PER_WORD;
7955 /* Skip pushed static chain. */
7956 if (ix86_static_chain_on_stack)
7957 offset += UNITS_PER_WORD;
7959 /* Skip saved base pointer. */
7960 if (frame_pointer_needed)
7961 offset += UNITS_PER_WORD;
7963 frame->hard_frame_pointer_offset = offset;
7965 /* Set offset to aligned because the realigned frame starts from
7967 if (stack_realign_fp)
7968 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7970 /* Register save area */
7971 offset += frame->nregs * UNITS_PER_WORD;
7973 /* Align SSE reg save area. */
7974 if (frame->nsseregs)
7975 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7977 frame->padding0 = 0;
7979 /* SSE register save area. */
7980 offset += frame->padding0 + frame->nsseregs * 16;
7983 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7984 offset += frame->va_arg_size;
7986 /* Align start of frame for local function. */
7987 frame->padding1 = ((offset + stack_alignment_needed - 1)
7988 & -stack_alignment_needed) - offset;
7990 offset += frame->padding1;
7992 /* Frame pointer points here. */
7993 frame->frame_pointer_offset = offset;
7997 /* Add outgoing arguments area. Can be skipped if we eliminated
7998 all the function calls as dead code.
7999 Skipping is however impossible when function calls alloca. Alloca
8000 expander assumes that last crtl->outgoing_args_size
8001 of stack frame are unused. */
8002 if (ACCUMULATE_OUTGOING_ARGS
8003 && (!current_function_is_leaf || cfun->calls_alloca
8004 || ix86_current_function_calls_tls_descriptor))
8006 offset += crtl->outgoing_args_size;
8007 frame->outgoing_arguments_size = crtl->outgoing_args_size;
8010 frame->outgoing_arguments_size = 0;
8012 /* Align stack boundary. Only needed if we're calling another function
8014 if (!current_function_is_leaf || cfun->calls_alloca
8015 || ix86_current_function_calls_tls_descriptor)
8016 frame->padding2 = ((offset + preferred_alignment - 1)
8017 & -preferred_alignment) - offset;
8019 frame->padding2 = 0;
8021 offset += frame->padding2;
8023 /* We've reached end of stack frame. */
8024 frame->stack_pointer_offset = offset;
8026 /* Size prologue needs to allocate. */
8027 frame->to_allocate =
8028 (size + frame->padding1 + frame->padding2
8029 + frame->outgoing_arguments_size + frame->va_arg_size);
8031 if ((!frame->to_allocate && frame->nregs <= 1)
8032 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
8033 frame->save_regs_using_mov = false;
8035 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8036 && current_function_sp_is_unchanging
8037 && current_function_is_leaf
8038 && !ix86_current_function_calls_tls_descriptor)
8040 frame->red_zone_size = frame->to_allocate;
8041 if (frame->save_regs_using_mov)
8042 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
8043 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
8044 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
8047 frame->red_zone_size = 0;
8048 frame->to_allocate -= frame->red_zone_size;
8049 frame->stack_pointer_offset -= frame->red_zone_size;
8052 /* Emit code to save registers in the prologue. */
8055 ix86_emit_save_regs (void)
8060 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
8061 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8063 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
8064 RTX_FRAME_RELATED_P (insn) = 1;
8068 /* Emit code to save registers using MOV insns. First register
8069 is restored from POINTER + OFFSET. */
8071 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8076 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8077 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8079 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8081 gen_rtx_REG (Pmode, regno));
8082 RTX_FRAME_RELATED_P (insn) = 1;
8083 offset += UNITS_PER_WORD;
8087 /* Emit code to save registers using MOV insns. First register
8088 is restored from POINTER + OFFSET. */
8090 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8096 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8097 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8099 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8100 set_mem_align (mem, 128);
8101 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8102 RTX_FRAME_RELATED_P (insn) = 1;
8107 static GTY(()) rtx queued_cfa_restores;
8109 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8110 manipulation insn. Don't add it if the previously
8111 saved value will be left untouched within stack red-zone till return,
8112 as unwinders can find the same value in the register and
8116 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8119 && !TARGET_64BIT_MS_ABI
8120 && red_offset + RED_ZONE_SIZE >= 0
8121 && crtl->args.pops_args < 65536)
8126 add_reg_note (insn, REG_CFA_RESTORE, reg);
8127 RTX_FRAME_RELATED_P (insn) = 1;
8131 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8134 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8137 ix86_add_queued_cfa_restore_notes (rtx insn)
8140 if (!queued_cfa_restores)
8142 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8144 XEXP (last, 1) = REG_NOTES (insn);
8145 REG_NOTES (insn) = queued_cfa_restores;
8146 queued_cfa_restores = NULL_RTX;
8147 RTX_FRAME_RELATED_P (insn) = 1;
8150 /* Expand prologue or epilogue stack adjustment.
8151 The pattern exist to put a dependency on all ebp-based memory accesses.
8152 STYLE should be negative if instructions should be marked as frame related,
8153 zero if %r11 register is live and cannot be freely used and positive
8157 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8158 int style, bool set_cfa)
8163 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8164 else if (x86_64_immediate_operand (offset, DImode))
8165 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8169 /* r11 is used by indirect sibcall return as well, set before the
8170 epilogue and used after the epilogue. ATM indirect sibcall
8171 shouldn't be used together with huge frame sizes in one
8172 function because of the frame_size check in sibcall.c. */
8174 r11 = gen_rtx_REG (DImode, R11_REG);
8175 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8177 RTX_FRAME_RELATED_P (insn) = 1;
8178 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8183 ix86_add_queued_cfa_restore_notes (insn);
8189 gcc_assert (ix86_cfa_state->reg == src);
8190 ix86_cfa_state->offset += INTVAL (offset);
8191 ix86_cfa_state->reg = dest;
8193 r = gen_rtx_PLUS (Pmode, src, offset);
8194 r = gen_rtx_SET (VOIDmode, dest, r);
8195 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8196 RTX_FRAME_RELATED_P (insn) = 1;
8199 RTX_FRAME_RELATED_P (insn) = 1;
8202 /* Find an available register to be used as dynamic realign argument
8203 pointer regsiter. Such a register will be written in prologue and
8204 used in begin of body, so it must not be
8205 1. parameter passing register.
8207 We reuse static-chain register if it is available. Otherwise, we
8208 use DI for i386 and R13 for x86-64. We chose R13 since it has
8211 Return: the regno of chosen register. */
8214 find_drap_reg (void)
8216 tree decl = cfun->decl;
8220 /* Use R13 for nested function or function need static chain.
8221 Since function with tail call may use any caller-saved
8222 registers in epilogue, DRAP must not use caller-saved
8223 register in such case. */
8224 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8231 /* Use DI for nested function or function need static chain.
8232 Since function with tail call may use any caller-saved
8233 registers in epilogue, DRAP must not use caller-saved
8234 register in such case. */
8235 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8238 /* Reuse static chain register if it isn't used for parameter
8240 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8241 && !lookup_attribute ("fastcall",
8242 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8249 /* Return minimum incoming stack alignment. */
8252 ix86_minimum_incoming_stack_boundary (bool sibcall)
8254 unsigned int incoming_stack_boundary;
8256 /* Prefer the one specified at command line. */
8257 if (ix86_user_incoming_stack_boundary)
8258 incoming_stack_boundary = ix86_user_incoming_stack_boundary;
8259 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8260 if -mstackrealign is used, it isn't used for sibcall check and
8261 estimated stack alignment is 128bit. */
8264 && ix86_force_align_arg_pointer
8265 && crtl->stack_alignment_estimated == 128)
8266 incoming_stack_boundary = MIN_STACK_BOUNDARY;
8268 incoming_stack_boundary = ix86_default_incoming_stack_boundary;
8270 /* Incoming stack alignment can be changed on individual functions
8271 via force_align_arg_pointer attribute. We use the smallest
8272 incoming stack boundary. */
8273 if (incoming_stack_boundary > MIN_STACK_BOUNDARY
8274 && lookup_attribute (ix86_force_align_arg_pointer_string,
8275 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8276 incoming_stack_boundary = MIN_STACK_BOUNDARY;
8278 /* The incoming stack frame has to be aligned at least at
8279 parm_stack_boundary. */
8280 if (incoming_stack_boundary < crtl->parm_stack_boundary)
8281 incoming_stack_boundary = crtl->parm_stack_boundary;
8283 /* Stack at entrance of main is aligned by runtime. We use the
8284 smallest incoming stack boundary. */
8285 if (incoming_stack_boundary > MAIN_STACK_BOUNDARY
8286 && DECL_NAME (current_function_decl)
8287 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8288 && DECL_FILE_SCOPE_P (current_function_decl))
8289 incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8291 return incoming_stack_boundary;
8294 /* Update incoming stack boundary and estimated stack alignment. */
8297 ix86_update_stack_boundary (void)
8299 ix86_incoming_stack_boundary
8300 = ix86_minimum_incoming_stack_boundary (false);
8302 /* x86_64 vararg needs 16byte stack alignment for register save
8306 && crtl->stack_alignment_estimated < 128)
8307 crtl->stack_alignment_estimated = 128;
8310 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8311 needed or an rtx for DRAP otherwise. */
8314 ix86_get_drap_rtx (void)
8316 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8317 crtl->need_drap = true;
8319 if (stack_realign_drap)
8321 /* Assign DRAP to vDRAP and returns vDRAP */
8322 unsigned int regno = find_drap_reg ();
8327 arg_ptr = gen_rtx_REG (Pmode, regno);
8328 crtl->drap_reg = arg_ptr;
8331 drap_vreg = copy_to_reg (arg_ptr);
8335 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8336 RTX_FRAME_RELATED_P (insn) = 1;
8343 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8346 ix86_internal_arg_pointer (void)
8348 return virtual_incoming_args_rtx;
8351 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8352 to be generated in correct form. */
8354 ix86_finalize_stack_realign_flags (void)
8356 /* Check if stack realign is really needed after reload, and
8357 stores result in cfun */
8358 unsigned int incoming_stack_boundary
8359 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8360 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8361 unsigned int stack_realign = (incoming_stack_boundary
8362 < (current_function_is_leaf
8363 ? crtl->max_used_stack_slot_alignment
8364 : crtl->stack_alignment_needed));
8366 if (crtl->stack_realign_finalized)
8368 /* After stack_realign_needed is finalized, we can't no longer
8370 gcc_assert (crtl->stack_realign_needed == stack_realign);
8374 crtl->stack_realign_needed = stack_realign;
8375 crtl->stack_realign_finalized = true;
8379 /* Expand the prologue into a bunch of separate insns. */
8382 ix86_expand_prologue (void)
8386 struct ix86_frame frame;
8387 HOST_WIDE_INT allocate;
8388 int gen_frame_pointer = frame_pointer_needed;
8390 ix86_finalize_stack_realign_flags ();
8392 /* DRAP should not coexist with stack_realign_fp */
8393 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8395 /* Initialize CFA state for before the prologue. */
8396 ix86_cfa_state->reg = stack_pointer_rtx;
8397 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8399 ix86_compute_frame_layout (&frame);
8401 if (ix86_function_ms_hook_prologue (current_function_decl))
8405 /* Make sure the function starts with
8406 8b ff movl.s %edi,%edi
8408 8b ec movl.s %esp,%ebp
8410 This matches the hookable function prologue in Win32 API
8411 functions in Microsoft Windows XP Service Pack 2 and newer.
8412 Wine uses this to enable Windows apps to hook the Win32 API
8413 functions provided by Wine. */
8414 insn = emit_insn (gen_vswapmov (gen_rtx_REG (SImode, DI_REG),
8415 gen_rtx_REG (SImode, DI_REG)));
8416 push = emit_insn (gen_push (hard_frame_pointer_rtx));
8417 mov = emit_insn (gen_vswapmov (hard_frame_pointer_rtx,
8418 stack_pointer_rtx));
8420 if (frame_pointer_needed && !(crtl->drap_reg
8421 && crtl->stack_realign_needed))
8423 /* The push %ebp and movl.s %esp, %ebp already set up
8424 the frame pointer. No need to do this again. */
8425 gen_frame_pointer = 0;
8426 RTX_FRAME_RELATED_P (push) = 1;
8427 RTX_FRAME_RELATED_P (mov) = 1;
8428 if (ix86_cfa_state->reg == stack_pointer_rtx)
8429 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8432 /* If the frame pointer is not needed, pop %ebp again. This
8433 could be optimized for cases where ebp needs to be backed up
8434 for some other reason. If stack realignment is needed, pop
8435 the base pointer again, align the stack, and later regenerate
8436 the frame pointer setup. The frame pointer generated by the
8437 hook prologue is not aligned, so it can't be used. */
8438 insn = emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8441 /* The first insn of a function that accepts its static chain on the
8442 stack is to push the register that would be filled in by a direct
8443 call. This insn will be skipped by the trampoline. */
8444 if (ix86_static_chain_on_stack)
8448 insn = emit_insn (gen_push (ix86_static_chain (cfun->decl, false)));
8449 emit_insn (gen_blockage ());
8451 /* We don't want to interpret this push insn as a register save,
8452 only as a stack adjustment. The real copy of the register as
8453 a save will be done later, if needed. */
8454 t = plus_constant (stack_pointer_rtx, -UNITS_PER_WORD);
8455 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8456 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8457 RTX_FRAME_RELATED_P (insn) = 1;
8460 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8461 of DRAP is needed and stack realignment is really needed after reload */
8462 if (crtl->drap_reg && crtl->stack_realign_needed)
8465 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8466 int param_ptr_offset = UNITS_PER_WORD;
8468 if (ix86_static_chain_on_stack)
8469 param_ptr_offset += UNITS_PER_WORD;
8470 if (!call_used_regs[REGNO (crtl->drap_reg)])
8471 param_ptr_offset += UNITS_PER_WORD;
8473 gcc_assert (stack_realign_drap);
8475 /* Grab the argument pointer. */
8476 x = plus_constant (stack_pointer_rtx, param_ptr_offset);
8479 /* Only need to push parameter pointer reg if it is caller
8481 if (!call_used_regs[REGNO (crtl->drap_reg)])
8483 /* Push arg pointer reg */
8484 insn = emit_insn (gen_push (y));
8485 RTX_FRAME_RELATED_P (insn) = 1;
8488 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8489 RTX_FRAME_RELATED_P (insn) = 1;
8490 ix86_cfa_state->reg = crtl->drap_reg;
8492 /* Align the stack. */
8493 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8495 GEN_INT (-align_bytes)));
8496 RTX_FRAME_RELATED_P (insn) = 1;
8498 /* Replicate the return address on the stack so that return
8499 address can be reached via (argp - 1) slot. This is needed
8500 to implement macro RETURN_ADDR_RTX and intrinsic function
8501 expand_builtin_return_addr etc. */
8503 x = gen_frame_mem (Pmode,
8504 plus_constant (x, -UNITS_PER_WORD));
8505 insn = emit_insn (gen_push (x));
8506 RTX_FRAME_RELATED_P (insn) = 1;
8509 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8510 slower on all targets. Also sdb doesn't like it. */
8512 if (gen_frame_pointer)
8514 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8515 RTX_FRAME_RELATED_P (insn) = 1;
8517 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8518 RTX_FRAME_RELATED_P (insn) = 1;
8520 if (ix86_cfa_state->reg == stack_pointer_rtx)
8521 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8524 if (stack_realign_fp)
8526 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8527 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8529 /* Align the stack. */
8530 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8532 GEN_INT (-align_bytes)));
8533 RTX_FRAME_RELATED_P (insn) = 1;
8536 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8538 if (!frame.save_regs_using_mov)
8539 ix86_emit_save_regs ();
8541 allocate += frame.nregs * UNITS_PER_WORD;
8543 /* When using red zone we may start register saving before allocating
8544 the stack frame saving one cycle of the prologue. However I will
8545 avoid doing this if I am going to have to probe the stack since
8546 at least on x86_64 the stack probe can turn into a call that clobbers
8547 a red zone location */
8548 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8549 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8550 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8551 && !crtl->stack_realign_needed)
8552 ? hard_frame_pointer_rtx
8553 : stack_pointer_rtx,
8554 -frame.nregs * UNITS_PER_WORD);
8558 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8559 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8560 GEN_INT (-allocate), -1,
8561 ix86_cfa_state->reg == stack_pointer_rtx);
8564 /* Only valid for Win32. */
8565 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8569 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8571 if (cfun->machine->call_abi == MS_ABI)
8574 eax_live = ix86_eax_live_at_start_p ();
8578 emit_insn (gen_push (eax));
8579 allocate -= UNITS_PER_WORD;
8582 emit_move_insn (eax, GEN_INT (allocate));
8585 insn = gen_allocate_stack_worker_64 (eax, eax);
8587 insn = gen_allocate_stack_worker_32 (eax, eax);
8588 insn = emit_insn (insn);
8590 if (ix86_cfa_state->reg == stack_pointer_rtx)
8592 ix86_cfa_state->offset += allocate;
8593 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8594 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8595 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8596 RTX_FRAME_RELATED_P (insn) = 1;
8601 if (frame_pointer_needed)
8602 t = plus_constant (hard_frame_pointer_rtx,
8605 - frame.nregs * UNITS_PER_WORD);
8607 t = plus_constant (stack_pointer_rtx, allocate);
8608 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8612 if (frame.save_regs_using_mov
8613 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8614 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8616 if (!frame_pointer_needed
8617 || !(frame.to_allocate + frame.padding0)
8618 || crtl->stack_realign_needed)
8619 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8621 + frame.nsseregs * 16 + frame.padding0);
8623 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8624 -frame.nregs * UNITS_PER_WORD);
8626 if (!frame_pointer_needed
8627 || !(frame.to_allocate + frame.padding0)
8628 || crtl->stack_realign_needed)
8629 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8632 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8633 - frame.nregs * UNITS_PER_WORD
8634 - frame.nsseregs * 16
8637 pic_reg_used = false;
8638 if (pic_offset_table_rtx
8639 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8642 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8644 if (alt_pic_reg_used != INVALID_REGNUM)
8645 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8647 pic_reg_used = true;
8654 if (ix86_cmodel == CM_LARGE_PIC)
8656 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8657 rtx label = gen_label_rtx ();
8659 LABEL_PRESERVE_P (label) = 1;
8660 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8661 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8662 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8663 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8664 pic_offset_table_rtx, tmp_reg));
8667 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8670 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8673 /* In the pic_reg_used case, make sure that the got load isn't deleted
8674 when mcount needs it. Blockage to avoid call movement across mcount
8675 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8677 if (crtl->profile && pic_reg_used)
8678 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8680 if (crtl->drap_reg && !crtl->stack_realign_needed)
8682 /* vDRAP is setup but after reload it turns out stack realign
8683 isn't necessary, here we will emit prologue to setup DRAP
8684 without stack realign adjustment */
8686 int drap_bp_offset = UNITS_PER_WORD * 2;
8688 if (ix86_static_chain_on_stack)
8689 drap_bp_offset += UNITS_PER_WORD;
8690 x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8691 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8694 /* Prevent instructions from being scheduled into register save push
8695 sequence when access to the redzone area is done through frame pointer.
8696 The offset between the frame pointer and the stack pointer is calculated
8697 relative to the value of the stack pointer at the end of the function
8698 prologue, and moving instructions that access redzone area via frame
8699 pointer inside push sequence violates this assumption. */
8700 if (frame_pointer_needed && frame.red_zone_size)
8701 emit_insn (gen_memory_blockage ());
8703 /* Emit cld instruction if stringops are used in the function. */
8704 if (TARGET_CLD && ix86_current_function_needs_cld)
8705 emit_insn (gen_cld ());
8708 /* Emit code to restore REG using a POP insn. */
8711 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8713 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8715 if (ix86_cfa_state->reg == crtl->drap_reg
8716 && REGNO (reg) == REGNO (crtl->drap_reg))
8718 /* Previously we'd represented the CFA as an expression
8719 like *(%ebp - 8). We've just popped that value from
8720 the stack, which means we need to reset the CFA to
8721 the drap register. This will remain until we restore
8722 the stack pointer. */
8723 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8724 RTX_FRAME_RELATED_P (insn) = 1;
8728 if (ix86_cfa_state->reg == stack_pointer_rtx)
8730 ix86_cfa_state->offset -= UNITS_PER_WORD;
8731 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8732 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8733 RTX_FRAME_RELATED_P (insn) = 1;
8736 /* When the frame pointer is the CFA, and we pop it, we are
8737 swapping back to the stack pointer as the CFA. This happens
8738 for stack frames that don't allocate other data, so we assume
8739 the stack pointer is now pointing at the return address, i.e.
8740 the function entry state, which makes the offset be 1 word. */
8741 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8742 && reg == hard_frame_pointer_rtx)
8744 ix86_cfa_state->reg = stack_pointer_rtx;
8745 ix86_cfa_state->offset -= UNITS_PER_WORD;
8747 add_reg_note (insn, REG_CFA_DEF_CFA,
8748 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8749 GEN_INT (ix86_cfa_state->offset)));
8750 RTX_FRAME_RELATED_P (insn) = 1;
8753 ix86_add_cfa_restore_note (insn, reg, red_offset);
8756 /* Emit code to restore saved registers using POP insns. */
8759 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8763 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8764 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8766 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8768 red_offset += UNITS_PER_WORD;
8772 /* Emit code and notes for the LEAVE instruction. */
8775 ix86_emit_leave (HOST_WIDE_INT red_offset)
8777 rtx insn = emit_insn (ix86_gen_leave ());
8779 ix86_add_queued_cfa_restore_notes (insn);
8781 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8783 ix86_cfa_state->reg = stack_pointer_rtx;
8784 ix86_cfa_state->offset -= UNITS_PER_WORD;
8786 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8787 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8788 RTX_FRAME_RELATED_P (insn) = 1;
8789 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8793 /* Emit code to restore saved registers using MOV insns. First register
8794 is restored from POINTER + OFFSET. */
8796 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8797 HOST_WIDE_INT red_offset,
8798 int maybe_eh_return)
8801 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8804 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8805 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8807 rtx reg = gen_rtx_REG (Pmode, regno);
8809 /* Ensure that adjust_address won't be forced to produce pointer
8810 out of range allowed by x86-64 instruction set. */
8811 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8815 r11 = gen_rtx_REG (DImode, R11_REG);
8816 emit_move_insn (r11, GEN_INT (offset));
8817 emit_insn (gen_adddi3 (r11, r11, pointer));
8818 base_address = gen_rtx_MEM (Pmode, r11);
8821 insn = emit_move_insn (reg,
8822 adjust_address (base_address, Pmode, offset));
8823 offset += UNITS_PER_WORD;
8825 if (ix86_cfa_state->reg == crtl->drap_reg
8826 && regno == REGNO (crtl->drap_reg))
8828 /* Previously we'd represented the CFA as an expression
8829 like *(%ebp - 8). We've just popped that value from
8830 the stack, which means we need to reset the CFA to
8831 the drap register. This will remain until we restore
8832 the stack pointer. */
8833 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8834 RTX_FRAME_RELATED_P (insn) = 1;
8837 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8839 red_offset += UNITS_PER_WORD;
8843 /* Emit code to restore saved registers using MOV insns. First register
8844 is restored from POINTER + OFFSET. */
8846 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8847 HOST_WIDE_INT red_offset,
8848 int maybe_eh_return)
8851 rtx base_address = gen_rtx_MEM (TImode, pointer);
8854 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8855 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8857 rtx reg = gen_rtx_REG (TImode, regno);
8859 /* Ensure that adjust_address won't be forced to produce pointer
8860 out of range allowed by x86-64 instruction set. */
8861 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8865 r11 = gen_rtx_REG (DImode, R11_REG);
8866 emit_move_insn (r11, GEN_INT (offset));
8867 emit_insn (gen_adddi3 (r11, r11, pointer));
8868 base_address = gen_rtx_MEM (TImode, r11);
8871 mem = adjust_address (base_address, TImode, offset);
8872 set_mem_align (mem, 128);
8873 insn = emit_move_insn (reg, mem);
8876 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8882 /* Restore function stack, frame, and registers. */
8885 ix86_expand_epilogue (int style)
8888 struct ix86_frame frame;
8889 HOST_WIDE_INT offset, red_offset;
8890 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8893 ix86_finalize_stack_realign_flags ();
8895 /* When stack is realigned, SP must be valid. */
8896 sp_valid = (!frame_pointer_needed
8897 || current_function_sp_is_unchanging
8898 || stack_realign_fp);
8900 ix86_compute_frame_layout (&frame);
8902 /* See the comment about red zone and frame
8903 pointer usage in ix86_expand_prologue. */
8904 if (frame_pointer_needed && frame.red_zone_size)
8905 emit_insn (gen_memory_blockage ());
8907 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8908 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8910 /* Calculate start of saved registers relative to ebp. Special care
8911 must be taken for the normal return case of a function using
8912 eh_return: the eax and edx registers are marked as saved, but not
8913 restored along this path. */
8914 offset = frame.nregs;
8915 if (crtl->calls_eh_return && style != 2)
8917 offset *= -UNITS_PER_WORD;
8918 offset -= frame.nsseregs * 16 + frame.padding0;
8920 /* Calculate start of saved registers relative to esp on entry of the
8921 function. When realigning stack, this needs to be the most negative
8922 value possible at runtime. */
8923 red_offset = offset;
8925 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8927 else if (stack_realign_fp)
8928 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8930 if (ix86_static_chain_on_stack)
8931 red_offset -= UNITS_PER_WORD;
8932 if (frame_pointer_needed)
8933 red_offset -= UNITS_PER_WORD;
8935 /* If we're only restoring one register and sp is not valid then
8936 using a move instruction to restore the register since it's
8937 less work than reloading sp and popping the register.
8939 The default code result in stack adjustment using add/lea instruction,
8940 while this code results in LEAVE instruction (or discrete equivalent),
8941 so it is profitable in some other cases as well. Especially when there
8942 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8943 and there is exactly one register to pop. This heuristic may need some
8944 tuning in future. */
8945 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8946 || (TARGET_EPILOGUE_USING_MOVE
8947 && cfun->machine->use_fast_prologue_epilogue
8948 && ((frame.nregs + frame.nsseregs) > 1
8949 || (frame.to_allocate + frame.padding0) != 0))
8950 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8951 && (frame.to_allocate + frame.padding0) != 0)
8952 || (frame_pointer_needed && TARGET_USE_LEAVE
8953 && cfun->machine->use_fast_prologue_epilogue
8954 && (frame.nregs + frame.nsseregs) == 1)
8955 || crtl->calls_eh_return)
8957 /* Restore registers. We can use ebp or esp to address the memory
8958 locations. If both are available, default to ebp, since offsets
8959 are known to be small. Only exception is esp pointing directly
8960 to the end of block of saved registers, where we may simplify
8963 If we are realigning stack with bp and sp, regs restore can't
8964 be addressed by bp. sp must be used instead. */
8966 if (!frame_pointer_needed
8967 || (sp_valid && !(frame.to_allocate + frame.padding0))
8968 || stack_realign_fp)
8970 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8971 frame.to_allocate, red_offset,
8973 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8975 + frame.nsseregs * 16
8978 + frame.nsseregs * 16
8979 + frame.padding0, style == 2);
8983 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8986 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8988 + frame.nsseregs * 16
8991 + frame.nsseregs * 16
8992 + frame.padding0, style == 2);
8995 red_offset -= offset;
8997 /* eh_return epilogues need %ecx added to the stack pointer. */
9000 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
9002 /* Stack align doesn't work with eh_return. */
9003 gcc_assert (!crtl->stack_realign_needed);
9004 /* Neither does regparm nested functions. */
9005 gcc_assert (!ix86_static_chain_on_stack);
9007 if (frame_pointer_needed)
9009 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
9010 tmp = plus_constant (tmp, UNITS_PER_WORD);
9011 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
9013 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
9014 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
9016 /* Note that we use SA as a temporary CFA, as the return
9017 address is at the proper place relative to it. We
9018 pretend this happens at the FP restore insn because
9019 prior to this insn the FP would be stored at the wrong
9020 offset relative to SA, and after this insn we have no
9021 other reasonable register to use for the CFA. We don't
9022 bother resetting the CFA to the SP for the duration of
9024 add_reg_note (tmp, REG_CFA_DEF_CFA,
9025 plus_constant (sa, UNITS_PER_WORD));
9026 ix86_add_queued_cfa_restore_notes (tmp);
9027 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
9028 RTX_FRAME_RELATED_P (tmp) = 1;
9029 ix86_cfa_state->reg = sa;
9030 ix86_cfa_state->offset = UNITS_PER_WORD;
9032 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
9033 const0_rtx, style, false);
9037 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
9038 tmp = plus_constant (tmp, (frame.to_allocate
9039 + frame.nregs * UNITS_PER_WORD
9040 + frame.nsseregs * 16
9042 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
9043 ix86_add_queued_cfa_restore_notes (tmp);
9045 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9046 if (ix86_cfa_state->offset != UNITS_PER_WORD)
9048 ix86_cfa_state->offset = UNITS_PER_WORD;
9049 add_reg_note (tmp, REG_CFA_DEF_CFA,
9050 plus_constant (stack_pointer_rtx,
9052 RTX_FRAME_RELATED_P (tmp) = 1;
9056 else if (!frame_pointer_needed)
9057 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9058 GEN_INT (frame.to_allocate
9059 + frame.nregs * UNITS_PER_WORD
9060 + frame.nsseregs * 16
9062 style, !using_drap);
9063 /* If not an i386, mov & pop is faster than "leave". */
9064 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
9065 || !cfun->machine->use_fast_prologue_epilogue)
9066 ix86_emit_leave (red_offset);
9069 pro_epilogue_adjust_stack (stack_pointer_rtx,
9070 hard_frame_pointer_rtx,
9071 const0_rtx, style, !using_drap);
9073 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
9078 /* First step is to deallocate the stack frame so that we can
9081 If we realign stack with frame pointer, then stack pointer
9082 won't be able to recover via lea $offset(%bp), %sp, because
9083 there is a padding area between bp and sp for realign.
9084 "add $to_allocate, %sp" must be used instead. */
9087 gcc_assert (frame_pointer_needed);
9088 gcc_assert (!stack_realign_fp);
9089 pro_epilogue_adjust_stack (stack_pointer_rtx,
9090 hard_frame_pointer_rtx,
9091 GEN_INT (offset), style, false);
9092 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9095 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9096 GEN_INT (frame.nsseregs * 16
9100 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
9102 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9103 frame.to_allocate, red_offset,
9105 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9106 GEN_INT (frame.to_allocate
9107 + frame.nsseregs * 16
9108 + frame.padding0), style,
9109 !using_drap && !frame_pointer_needed);
9112 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
9114 red_offset -= offset;
9116 if (frame_pointer_needed)
9118 /* Leave results in shorter dependency chains on CPUs that are
9119 able to grok it fast. */
9120 if (TARGET_USE_LEAVE)
9121 ix86_emit_leave (red_offset);
9124 /* For stack realigned really happens, recover stack
9125 pointer to hard frame pointer is a must, if not using
9127 if (stack_realign_fp)
9128 pro_epilogue_adjust_stack (stack_pointer_rtx,
9129 hard_frame_pointer_rtx,
9130 const0_rtx, style, !using_drap);
9131 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
9139 int param_ptr_offset = UNITS_PER_WORD;
9142 gcc_assert (stack_realign_drap);
9144 if (ix86_static_chain_on_stack)
9145 param_ptr_offset += UNITS_PER_WORD;
9146 if (!call_used_regs[REGNO (crtl->drap_reg)])
9147 param_ptr_offset += UNITS_PER_WORD;
9149 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
9151 GEN_INT (-param_ptr_offset)));
9153 ix86_cfa_state->reg = stack_pointer_rtx;
9154 ix86_cfa_state->offset = param_ptr_offset;
9156 add_reg_note (insn, REG_CFA_DEF_CFA,
9157 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9158 GEN_INT (ix86_cfa_state->offset)));
9159 RTX_FRAME_RELATED_P (insn) = 1;
9161 if (!call_used_regs[REGNO (crtl->drap_reg)])
9162 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9165 /* Remove the saved static chain from the stack. The use of ECX is
9166 merely as a scratch register, not as the actual static chain. */
9167 if (ix86_static_chain_on_stack)
9171 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9172 ix86_cfa_state->offset += UNITS_PER_WORD;
9174 r = gen_rtx_REG (Pmode, CX_REG);
9175 insn = emit_insn (ix86_gen_pop1 (r));
9177 r = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
9178 r = gen_rtx_SET (VOIDmode, stack_pointer_rtx, r);
9179 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
9180 RTX_FRAME_RELATED_P (insn) = 1;
9183 /* Sibcall epilogues don't want a return instruction. */
9186 *ix86_cfa_state = cfa_state_save;
9190 if (crtl->args.pops_args && crtl->args.size)
9192 rtx popc = GEN_INT (crtl->args.pops_args);
9194 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9195 address, do explicit add, and jump indirectly to the caller. */
9197 if (crtl->args.pops_args >= 65536)
9199 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9202 /* There is no "pascal" calling convention in any 64bit ABI. */
9203 gcc_assert (!TARGET_64BIT);
9205 insn = emit_insn (gen_popsi1 (ecx));
9206 ix86_cfa_state->offset -= UNITS_PER_WORD;
9208 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9209 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9210 add_reg_note (insn, REG_CFA_REGISTER,
9211 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9212 RTX_FRAME_RELATED_P (insn) = 1;
9214 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9216 emit_jump_insn (gen_return_indirect_internal (ecx));
9219 emit_jump_insn (gen_return_pop_internal (popc));
9222 emit_jump_insn (gen_return_internal ());
9224 /* Restore the state back to the state from the prologue,
9225 so that it's correct for the next epilogue. */
9226 *ix86_cfa_state = cfa_state_save;
9229 /* Reset from the function's potential modifications. */
9232 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9233 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9235 if (pic_offset_table_rtx)
9236 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9238 /* Mach-O doesn't support labels at the end of objects, so if
9239 it looks like we might want one, insert a NOP. */
9241 rtx insn = get_last_insn ();
9244 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9245 insn = PREV_INSN (insn);
9249 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9250 fputs ("\tnop\n", file);
9256 /* Extract the parts of an RTL expression that is a valid memory address
9257 for an instruction. Return 0 if the structure of the address is
9258 grossly off. Return -1 if the address contains ASHIFT, so it is not
9259 strictly valid, but still used for computing length of lea instruction. */
9262 ix86_decompose_address (rtx addr, struct ix86_address *out)
9264 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9265 rtx base_reg, index_reg;
9266 HOST_WIDE_INT scale = 1;
9267 rtx scale_rtx = NULL_RTX;
9269 enum ix86_address_seg seg = SEG_DEFAULT;
9271 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9273 else if (GET_CODE (addr) == PLUS)
9283 addends[n++] = XEXP (op, 1);
9286 while (GET_CODE (op) == PLUS);
9291 for (i = n; i >= 0; --i)
9294 switch (GET_CODE (op))
9299 index = XEXP (op, 0);
9300 scale_rtx = XEXP (op, 1);
9304 if (XINT (op, 1) == UNSPEC_TP
9305 && TARGET_TLS_DIRECT_SEG_REFS
9306 && seg == SEG_DEFAULT)
9307 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9336 else if (GET_CODE (addr) == MULT)
9338 index = XEXP (addr, 0); /* index*scale */
9339 scale_rtx = XEXP (addr, 1);
9341 else if (GET_CODE (addr) == ASHIFT)
9345 /* We're called for lea too, which implements ashift on occasion. */
9346 index = XEXP (addr, 0);
9347 tmp = XEXP (addr, 1);
9348 if (!CONST_INT_P (tmp))
9350 scale = INTVAL (tmp);
9351 if ((unsigned HOST_WIDE_INT) scale > 3)
9357 disp = addr; /* displacement */
9359 /* Extract the integral value of scale. */
9362 if (!CONST_INT_P (scale_rtx))
9364 scale = INTVAL (scale_rtx);
9367 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9368 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9370 /* Avoid useless 0 displacement. */
9371 if (disp == const0_rtx && (base || index))
9374 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9375 if (base_reg && index_reg && scale == 1
9376 && (index_reg == arg_pointer_rtx
9377 || index_reg == frame_pointer_rtx
9378 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9381 tmp = base, base = index, index = tmp;
9382 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9385 /* Special case: %ebp cannot be encoded as a base without a displacement.
9389 && (base_reg == hard_frame_pointer_rtx
9390 || base_reg == frame_pointer_rtx
9391 || base_reg == arg_pointer_rtx
9392 || (REG_P (base_reg)
9393 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9394 || REGNO (base_reg) == R13_REG))))
9397 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9398 Avoid this by transforming to [%esi+0].
9399 Reload calls address legitimization without cfun defined, so we need
9400 to test cfun for being non-NULL. */
9401 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9402 && base_reg && !index_reg && !disp
9404 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9407 /* Special case: encode reg+reg instead of reg*2. */
9408 if (!base && index && scale == 2)
9409 base = index, base_reg = index_reg, scale = 1;
9411 /* Special case: scaling cannot be encoded without base or displacement. */
9412 if (!base && !disp && index && scale != 1)
9424 /* Return cost of the memory address x.
9425 For i386, it is better to use a complex address than let gcc copy
9426 the address into a reg and make a new pseudo. But not if the address
9427 requires to two regs - that would mean more pseudos with longer
9430 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9432 struct ix86_address parts;
9434 int ok = ix86_decompose_address (x, &parts);
9438 if (parts.base && GET_CODE (parts.base) == SUBREG)
9439 parts.base = SUBREG_REG (parts.base);
9440 if (parts.index && GET_CODE (parts.index) == SUBREG)
9441 parts.index = SUBREG_REG (parts.index);
9443 /* Attempt to minimize number of registers in the address. */
9445 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9447 && (!REG_P (parts.index)
9448 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9452 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9454 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9455 && parts.base != parts.index)
9458 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9459 since it's predecode logic can't detect the length of instructions
9460 and it degenerates to vector decoded. Increase cost of such
9461 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9462 to split such addresses or even refuse such addresses at all.
9464 Following addressing modes are affected:
9469 The first and last case may be avoidable by explicitly coding the zero in
9470 memory address, but I don't have AMD-K6 machine handy to check this
9474 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9475 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9476 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9482 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9483 this is used for to form addresses to local data when -fPIC is in
9487 darwin_local_data_pic (rtx disp)
9489 return (GET_CODE (disp) == UNSPEC
9490 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9493 /* Determine if a given RTX is a valid constant. We already know this
9494 satisfies CONSTANT_P. */
9497 legitimate_constant_p (rtx x)
9499 switch (GET_CODE (x))
9504 if (GET_CODE (x) == PLUS)
9506 if (!CONST_INT_P (XEXP (x, 1)))
9511 if (TARGET_MACHO && darwin_local_data_pic (x))
9514 /* Only some unspecs are valid as "constants". */
9515 if (GET_CODE (x) == UNSPEC)
9516 switch (XINT (x, 1))
9521 return TARGET_64BIT;
9524 x = XVECEXP (x, 0, 0);
9525 return (GET_CODE (x) == SYMBOL_REF
9526 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9528 x = XVECEXP (x, 0, 0);
9529 return (GET_CODE (x) == SYMBOL_REF
9530 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9535 /* We must have drilled down to a symbol. */
9536 if (GET_CODE (x) == LABEL_REF)
9538 if (GET_CODE (x) != SYMBOL_REF)
9543 /* TLS symbols are never valid. */
9544 if (SYMBOL_REF_TLS_MODEL (x))
9547 /* DLLIMPORT symbols are never valid. */
9548 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9549 && SYMBOL_REF_DLLIMPORT_P (x))
9554 if (GET_MODE (x) == TImode
9555 && x != CONST0_RTX (TImode)
9561 if (!standard_sse_constant_p (x))
9568 /* Otherwise we handle everything else in the move patterns. */
9572 /* Determine if it's legal to put X into the constant pool. This
9573 is not possible for the address of thread-local symbols, which
9574 is checked above. */
9577 ix86_cannot_force_const_mem (rtx x)
9579 /* We can always put integral constants and vectors in memory. */
9580 switch (GET_CODE (x))
9590 return !legitimate_constant_p (x);
9594 /* Nonzero if the constant value X is a legitimate general operand
9595 when generating PIC code. It is given that flag_pic is on and
9596 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9599 legitimate_pic_operand_p (rtx x)
9603 switch (GET_CODE (x))
9606 inner = XEXP (x, 0);
9607 if (GET_CODE (inner) == PLUS
9608 && CONST_INT_P (XEXP (inner, 1)))
9609 inner = XEXP (inner, 0);
9611 /* Only some unspecs are valid as "constants". */
9612 if (GET_CODE (inner) == UNSPEC)
9613 switch (XINT (inner, 1))
9618 return TARGET_64BIT;
9620 x = XVECEXP (inner, 0, 0);
9621 return (GET_CODE (x) == SYMBOL_REF
9622 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9623 case UNSPEC_MACHOPIC_OFFSET:
9624 return legitimate_pic_address_disp_p (x);
9632 return legitimate_pic_address_disp_p (x);
9639 /* Determine if a given CONST RTX is a valid memory displacement
9643 legitimate_pic_address_disp_p (rtx disp)
9647 /* In 64bit mode we can allow direct addresses of symbols and labels
9648 when they are not dynamic symbols. */
9651 rtx op0 = disp, op1;
9653 switch (GET_CODE (disp))
9659 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9661 op0 = XEXP (XEXP (disp, 0), 0);
9662 op1 = XEXP (XEXP (disp, 0), 1);
9663 if (!CONST_INT_P (op1)
9664 || INTVAL (op1) >= 16*1024*1024
9665 || INTVAL (op1) < -16*1024*1024)
9667 if (GET_CODE (op0) == LABEL_REF)
9669 if (GET_CODE (op0) != SYMBOL_REF)
9674 /* TLS references should always be enclosed in UNSPEC. */
9675 if (SYMBOL_REF_TLS_MODEL (op0))
9677 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9678 && ix86_cmodel != CM_LARGE_PIC)
9686 if (GET_CODE (disp) != CONST)
9688 disp = XEXP (disp, 0);
9692 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9693 of GOT tables. We should not need these anyway. */
9694 if (GET_CODE (disp) != UNSPEC
9695 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9696 && XINT (disp, 1) != UNSPEC_GOTOFF
9697 && XINT (disp, 1) != UNSPEC_PLTOFF))
9700 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9701 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9707 if (GET_CODE (disp) == PLUS)
9709 if (!CONST_INT_P (XEXP (disp, 1)))
9711 disp = XEXP (disp, 0);
9715 if (TARGET_MACHO && darwin_local_data_pic (disp))
9718 if (GET_CODE (disp) != UNSPEC)
9721 switch (XINT (disp, 1))
9726 /* We need to check for both symbols and labels because VxWorks loads
9727 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9729 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9730 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9732 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9733 While ABI specify also 32bit relocation but we don't produce it in
9734 small PIC model at all. */
9735 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9736 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9738 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9740 case UNSPEC_GOTTPOFF:
9741 case UNSPEC_GOTNTPOFF:
9742 case UNSPEC_INDNTPOFF:
9745 disp = XVECEXP (disp, 0, 0);
9746 return (GET_CODE (disp) == SYMBOL_REF
9747 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9749 disp = XVECEXP (disp, 0, 0);
9750 return (GET_CODE (disp) == SYMBOL_REF
9751 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9753 disp = XVECEXP (disp, 0, 0);
9754 return (GET_CODE (disp) == SYMBOL_REF
9755 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9761 /* Recognizes RTL expressions that are valid memory addresses for an
9762 instruction. The MODE argument is the machine mode for the MEM
9763 expression that wants to use this address.
9765 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9766 convert common non-canonical forms to canonical form so that they will
9770 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9771 rtx addr, bool strict)
9773 struct ix86_address parts;
9774 rtx base, index, disp;
9775 HOST_WIDE_INT scale;
9777 if (ix86_decompose_address (addr, &parts) <= 0)
9778 /* Decomposition failed. */
9782 index = parts.index;
9784 scale = parts.scale;
9786 /* Validate base register.
9788 Don't allow SUBREG's that span more than a word here. It can lead to spill
9789 failures when the base is one word out of a two word structure, which is
9790 represented internally as a DImode int. */
9798 else if (GET_CODE (base) == SUBREG
9799 && REG_P (SUBREG_REG (base))
9800 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9802 reg = SUBREG_REG (base);
9804 /* Base is not a register. */
9807 if (GET_MODE (base) != Pmode)
9808 /* Base is not in Pmode. */
9811 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9812 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9813 /* Base is not valid. */
9817 /* Validate index register.
9819 Don't allow SUBREG's that span more than a word here -- same as above. */
9827 else if (GET_CODE (index) == SUBREG
9828 && REG_P (SUBREG_REG (index))
9829 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9831 reg = SUBREG_REG (index);
9833 /* Index is not a register. */
9836 if (GET_MODE (index) != Pmode)
9837 /* Index is not in Pmode. */
9840 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9841 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9842 /* Index is not valid. */
9846 /* Validate scale factor. */
9850 /* Scale without index. */
9853 if (scale != 2 && scale != 4 && scale != 8)
9854 /* Scale is not a valid multiplier. */
9858 /* Validate displacement. */
9861 if (GET_CODE (disp) == CONST
9862 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9863 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9864 switch (XINT (XEXP (disp, 0), 1))
9866 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9867 used. While ABI specify also 32bit relocations, we don't produce
9868 them at all and use IP relative instead. */
9871 gcc_assert (flag_pic);
9873 goto is_legitimate_pic;
9875 /* 64bit address unspec. */
9878 case UNSPEC_GOTPCREL:
9879 gcc_assert (flag_pic);
9880 goto is_legitimate_pic;
9882 case UNSPEC_GOTTPOFF:
9883 case UNSPEC_GOTNTPOFF:
9884 case UNSPEC_INDNTPOFF:
9890 /* Invalid address unspec. */
9894 else if (SYMBOLIC_CONST (disp)
9898 && MACHOPIC_INDIRECT
9899 && !machopic_operand_p (disp)
9905 if (TARGET_64BIT && (index || base))
9907 /* foo@dtpoff(%rX) is ok. */
9908 if (GET_CODE (disp) != CONST
9909 || GET_CODE (XEXP (disp, 0)) != PLUS
9910 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9911 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9912 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9913 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9914 /* Non-constant pic memory reference. */
9917 else if (! legitimate_pic_address_disp_p (disp))
9918 /* Displacement is an invalid pic construct. */
9921 /* This code used to verify that a symbolic pic displacement
9922 includes the pic_offset_table_rtx register.
9924 While this is good idea, unfortunately these constructs may
9925 be created by "adds using lea" optimization for incorrect
9934 This code is nonsensical, but results in addressing
9935 GOT table with pic_offset_table_rtx base. We can't
9936 just refuse it easily, since it gets matched by
9937 "addsi3" pattern, that later gets split to lea in the
9938 case output register differs from input. While this
9939 can be handled by separate addsi pattern for this case
9940 that never results in lea, this seems to be easier and
9941 correct fix for crash to disable this test. */
9943 else if (GET_CODE (disp) != LABEL_REF
9944 && !CONST_INT_P (disp)
9945 && (GET_CODE (disp) != CONST
9946 || !legitimate_constant_p (disp))
9947 && (GET_CODE (disp) != SYMBOL_REF
9948 || !legitimate_constant_p (disp)))
9949 /* Displacement is not constant. */
9951 else if (TARGET_64BIT
9952 && !x86_64_immediate_operand (disp, VOIDmode))
9953 /* Displacement is out of range. */
9957 /* Everything looks valid. */
9961 /* Determine if a given RTX is a valid constant address. */
9964 constant_address_p (rtx x)
9966 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9969 /* Return a unique alias set for the GOT. */
9971 static alias_set_type
9972 ix86_GOT_alias_set (void)
9974 static alias_set_type set = -1;
9976 set = new_alias_set ();
9980 /* Return a legitimate reference for ORIG (an address) using the
9981 register REG. If REG is 0, a new pseudo is generated.
9983 There are two types of references that must be handled:
9985 1. Global data references must load the address from the GOT, via
9986 the PIC reg. An insn is emitted to do this load, and the reg is
9989 2. Static data references, constant pool addresses, and code labels
9990 compute the address as an offset from the GOT, whose base is in
9991 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9992 differentiate them from global data objects. The returned
9993 address is the PIC reg + an unspec constant.
9995 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9996 reg also appears in the address. */
9999 legitimize_pic_address (rtx orig, rtx reg)
10002 rtx new_rtx = orig;
10006 if (TARGET_MACHO && !TARGET_64BIT)
10009 reg = gen_reg_rtx (Pmode);
10010 /* Use the generic Mach-O PIC machinery. */
10011 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
10015 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
10017 else if (TARGET_64BIT
10018 && ix86_cmodel != CM_SMALL_PIC
10019 && gotoff_operand (addr, Pmode))
10022 /* This symbol may be referenced via a displacement from the PIC
10023 base address (@GOTOFF). */
10025 if (reload_in_progress)
10026 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10027 if (GET_CODE (addr) == CONST)
10028 addr = XEXP (addr, 0);
10029 if (GET_CODE (addr) == PLUS)
10031 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
10033 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
10036 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
10037 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10039 tmpreg = gen_reg_rtx (Pmode);
10042 emit_move_insn (tmpreg, new_rtx);
10046 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
10047 tmpreg, 1, OPTAB_DIRECT);
10050 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
10052 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
10054 /* This symbol may be referenced via a displacement from the PIC
10055 base address (@GOTOFF). */
10057 if (reload_in_progress)
10058 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10059 if (GET_CODE (addr) == CONST)
10060 addr = XEXP (addr, 0);
10061 if (GET_CODE (addr) == PLUS)
10063 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
10065 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
10068 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
10069 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10070 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10074 emit_move_insn (reg, new_rtx);
10078 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
10079 /* We can't use @GOTOFF for text labels on VxWorks;
10080 see gotoff_operand. */
10081 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
10083 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10085 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
10086 return legitimize_dllimport_symbol (addr, true);
10087 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
10088 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
10089 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
10091 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
10092 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
10096 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
10098 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
10099 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10100 new_rtx = gen_const_mem (Pmode, new_rtx);
10101 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10104 reg = gen_reg_rtx (Pmode);
10105 /* Use directly gen_movsi, otherwise the address is loaded
10106 into register for CSE. We don't want to CSE this addresses,
10107 instead we CSE addresses from the GOT table, so skip this. */
10108 emit_insn (gen_movsi (reg, new_rtx));
10113 /* This symbol must be referenced via a load from the
10114 Global Offset Table (@GOT). */
10116 if (reload_in_progress)
10117 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10118 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
10119 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10121 new_rtx = force_reg (Pmode, new_rtx);
10122 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10123 new_rtx = gen_const_mem (Pmode, new_rtx);
10124 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10127 reg = gen_reg_rtx (Pmode);
10128 emit_move_insn (reg, new_rtx);
10134 if (CONST_INT_P (addr)
10135 && !x86_64_immediate_operand (addr, VOIDmode))
10139 emit_move_insn (reg, addr);
10143 new_rtx = force_reg (Pmode, addr);
10145 else if (GET_CODE (addr) == CONST)
10147 addr = XEXP (addr, 0);
10149 /* We must match stuff we generate before. Assume the only
10150 unspecs that can get here are ours. Not that we could do
10151 anything with them anyway.... */
10152 if (GET_CODE (addr) == UNSPEC
10153 || (GET_CODE (addr) == PLUS
10154 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10156 gcc_assert (GET_CODE (addr) == PLUS);
10158 if (GET_CODE (addr) == PLUS)
10160 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10162 /* Check first to see if this is a constant offset from a @GOTOFF
10163 symbol reference. */
10164 if (gotoff_operand (op0, Pmode)
10165 && CONST_INT_P (op1))
10169 if (reload_in_progress)
10170 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10171 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10173 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10174 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10175 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10179 emit_move_insn (reg, new_rtx);
10185 if (INTVAL (op1) < -16*1024*1024
10186 || INTVAL (op1) >= 16*1024*1024)
10188 if (!x86_64_immediate_operand (op1, Pmode))
10189 op1 = force_reg (Pmode, op1);
10190 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10196 base = legitimize_pic_address (XEXP (addr, 0), reg);
10197 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10198 base == reg ? NULL_RTX : reg);
10200 if (CONST_INT_P (new_rtx))
10201 new_rtx = plus_constant (base, INTVAL (new_rtx));
10204 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10206 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10207 new_rtx = XEXP (new_rtx, 1);
10209 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10217 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10220 get_thread_pointer (int to_reg)
10224 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10228 reg = gen_reg_rtx (Pmode);
10229 insn = gen_rtx_SET (VOIDmode, reg, tp);
10230 insn = emit_insn (insn);
10235 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10236 false if we expect this to be used for a memory address and true if
10237 we expect to load the address into a register. */
10240 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10242 rtx dest, base, off, pic, tp;
10247 case TLS_MODEL_GLOBAL_DYNAMIC:
10248 dest = gen_reg_rtx (Pmode);
10249 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10251 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10253 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10256 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10257 insns = get_insns ();
10260 RTL_CONST_CALL_P (insns) = 1;
10261 emit_libcall_block (insns, dest, rax, x);
10263 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10264 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10266 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10268 if (TARGET_GNU2_TLS)
10270 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10272 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10276 case TLS_MODEL_LOCAL_DYNAMIC:
10277 base = gen_reg_rtx (Pmode);
10278 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10280 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10282 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10285 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10286 insns = get_insns ();
10289 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10290 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10291 RTL_CONST_CALL_P (insns) = 1;
10292 emit_libcall_block (insns, base, rax, note);
10294 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10295 emit_insn (gen_tls_local_dynamic_base_64 (base));
10297 emit_insn (gen_tls_local_dynamic_base_32 (base));
10299 if (TARGET_GNU2_TLS)
10301 rtx x = ix86_tls_module_base ();
10303 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10304 gen_rtx_MINUS (Pmode, x, tp));
10307 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10308 off = gen_rtx_CONST (Pmode, off);
10310 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10312 if (TARGET_GNU2_TLS)
10314 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10316 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10321 case TLS_MODEL_INITIAL_EXEC:
10325 type = UNSPEC_GOTNTPOFF;
10329 if (reload_in_progress)
10330 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10331 pic = pic_offset_table_rtx;
10332 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10334 else if (!TARGET_ANY_GNU_TLS)
10336 pic = gen_reg_rtx (Pmode);
10337 emit_insn (gen_set_got (pic));
10338 type = UNSPEC_GOTTPOFF;
10343 type = UNSPEC_INDNTPOFF;
10346 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10347 off = gen_rtx_CONST (Pmode, off);
10349 off = gen_rtx_PLUS (Pmode, pic, off);
10350 off = gen_const_mem (Pmode, off);
10351 set_mem_alias_set (off, ix86_GOT_alias_set ());
10353 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10355 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10356 off = force_reg (Pmode, off);
10357 return gen_rtx_PLUS (Pmode, base, off);
10361 base = get_thread_pointer (true);
10362 dest = gen_reg_rtx (Pmode);
10363 emit_insn (gen_subsi3 (dest, base, off));
10367 case TLS_MODEL_LOCAL_EXEC:
10368 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10369 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10370 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10371 off = gen_rtx_CONST (Pmode, off);
10373 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10375 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10376 return gen_rtx_PLUS (Pmode, base, off);
10380 base = get_thread_pointer (true);
10381 dest = gen_reg_rtx (Pmode);
10382 emit_insn (gen_subsi3 (dest, base, off));
10387 gcc_unreachable ();
10393 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10396 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10397 htab_t dllimport_map;
10400 get_dllimport_decl (tree decl)
10402 struct tree_map *h, in;
10405 const char *prefix;
10406 size_t namelen, prefixlen;
10411 if (!dllimport_map)
10412 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10414 in.hash = htab_hash_pointer (decl);
10415 in.base.from = decl;
10416 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10417 h = (struct tree_map *) *loc;
10421 *loc = h = GGC_NEW (struct tree_map);
10423 h->base.from = decl;
10424 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10425 VAR_DECL, NULL, ptr_type_node);
10426 DECL_ARTIFICIAL (to) = 1;
10427 DECL_IGNORED_P (to) = 1;
10428 DECL_EXTERNAL (to) = 1;
10429 TREE_READONLY (to) = 1;
10431 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10432 name = targetm.strip_name_encoding (name);
10433 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10434 ? "*__imp_" : "*__imp__";
10435 namelen = strlen (name);
10436 prefixlen = strlen (prefix);
10437 imp_name = (char *) alloca (namelen + prefixlen + 1);
10438 memcpy (imp_name, prefix, prefixlen);
10439 memcpy (imp_name + prefixlen, name, namelen + 1);
10441 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10442 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10443 SET_SYMBOL_REF_DECL (rtl, to);
10444 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10446 rtl = gen_const_mem (Pmode, rtl);
10447 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10449 SET_DECL_RTL (to, rtl);
10450 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10455 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10456 true if we require the result be a register. */
10459 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10464 gcc_assert (SYMBOL_REF_DECL (symbol));
10465 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10467 x = DECL_RTL (imp_decl);
10469 x = force_reg (Pmode, x);
10473 /* Try machine-dependent ways of modifying an illegitimate address
10474 to be legitimate. If we find one, return the new, valid address.
10475 This macro is used in only one place: `memory_address' in explow.c.
10477 OLDX is the address as it was before break_out_memory_refs was called.
10478 In some cases it is useful to look at this to decide what needs to be done.
10480 It is always safe for this macro to do nothing. It exists to recognize
10481 opportunities to optimize the output.
10483 For the 80386, we handle X+REG by loading X into a register R and
10484 using R+REG. R will go in a general reg and indexing will be used.
10485 However, if REG is a broken-out memory address or multiplication,
10486 nothing needs to be done because REG can certainly go in a general reg.
10488 When -fpic is used, special handling is needed for symbolic references.
10489 See comments by legitimize_pic_address in i386.c for details. */
10492 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10493 enum machine_mode mode)
10498 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10500 return legitimize_tls_address (x, (enum tls_model) log, false);
10501 if (GET_CODE (x) == CONST
10502 && GET_CODE (XEXP (x, 0)) == PLUS
10503 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10504 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10506 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10507 (enum tls_model) log, false);
10508 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10511 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10513 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10514 return legitimize_dllimport_symbol (x, true);
10515 if (GET_CODE (x) == CONST
10516 && GET_CODE (XEXP (x, 0)) == PLUS
10517 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10518 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10520 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10521 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10525 if (flag_pic && SYMBOLIC_CONST (x))
10526 return legitimize_pic_address (x, 0);
10528 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10529 if (GET_CODE (x) == ASHIFT
10530 && CONST_INT_P (XEXP (x, 1))
10531 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10534 log = INTVAL (XEXP (x, 1));
10535 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10536 GEN_INT (1 << log));
10539 if (GET_CODE (x) == PLUS)
10541 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10543 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10544 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10545 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10548 log = INTVAL (XEXP (XEXP (x, 0), 1));
10549 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10550 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10551 GEN_INT (1 << log));
10554 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10555 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10556 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10559 log = INTVAL (XEXP (XEXP (x, 1), 1));
10560 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10561 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10562 GEN_INT (1 << log));
10565 /* Put multiply first if it isn't already. */
10566 if (GET_CODE (XEXP (x, 1)) == MULT)
10568 rtx tmp = XEXP (x, 0);
10569 XEXP (x, 0) = XEXP (x, 1);
10574 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10575 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10576 created by virtual register instantiation, register elimination, and
10577 similar optimizations. */
10578 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10581 x = gen_rtx_PLUS (Pmode,
10582 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10583 XEXP (XEXP (x, 1), 0)),
10584 XEXP (XEXP (x, 1), 1));
10588 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10589 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10590 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10591 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10592 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10593 && CONSTANT_P (XEXP (x, 1)))
10596 rtx other = NULL_RTX;
10598 if (CONST_INT_P (XEXP (x, 1)))
10600 constant = XEXP (x, 1);
10601 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10603 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10605 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10606 other = XEXP (x, 1);
10614 x = gen_rtx_PLUS (Pmode,
10615 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10616 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10617 plus_constant (other, INTVAL (constant)));
10621 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10624 if (GET_CODE (XEXP (x, 0)) == MULT)
10627 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10630 if (GET_CODE (XEXP (x, 1)) == MULT)
10633 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10637 && REG_P (XEXP (x, 1))
10638 && REG_P (XEXP (x, 0)))
10641 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10644 x = legitimize_pic_address (x, 0);
10647 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10650 if (REG_P (XEXP (x, 0)))
10652 rtx temp = gen_reg_rtx (Pmode);
10653 rtx val = force_operand (XEXP (x, 1), temp);
10655 emit_move_insn (temp, val);
10657 XEXP (x, 1) = temp;
10661 else if (REG_P (XEXP (x, 1)))
10663 rtx temp = gen_reg_rtx (Pmode);
10664 rtx val = force_operand (XEXP (x, 0), temp);
10666 emit_move_insn (temp, val);
10668 XEXP (x, 0) = temp;
10676 /* Print an integer constant expression in assembler syntax. Addition
10677 and subtraction are the only arithmetic that may appear in these
10678 expressions. FILE is the stdio stream to write to, X is the rtx, and
10679 CODE is the operand print code from the output string. */
10682 output_pic_addr_const (FILE *file, rtx x, int code)
10686 switch (GET_CODE (x))
10689 gcc_assert (flag_pic);
10694 if (! TARGET_MACHO || TARGET_64BIT)
10695 output_addr_const (file, x);
10698 const char *name = XSTR (x, 0);
10700 /* Mark the decl as referenced so that cgraph will
10701 output the function. */
10702 if (SYMBOL_REF_DECL (x))
10703 mark_decl_referenced (SYMBOL_REF_DECL (x));
10706 if (MACHOPIC_INDIRECT
10707 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10708 name = machopic_indirection_name (x, /*stub_p=*/true);
10710 assemble_name (file, name);
10712 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10713 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10714 fputs ("@PLT", file);
10721 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10722 assemble_name (asm_out_file, buf);
10726 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10730 /* This used to output parentheses around the expression,
10731 but that does not work on the 386 (either ATT or BSD assembler). */
10732 output_pic_addr_const (file, XEXP (x, 0), code);
10736 if (GET_MODE (x) == VOIDmode)
10738 /* We can use %d if the number is <32 bits and positive. */
10739 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10740 fprintf (file, "0x%lx%08lx",
10741 (unsigned long) CONST_DOUBLE_HIGH (x),
10742 (unsigned long) CONST_DOUBLE_LOW (x));
10744 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10747 /* We can't handle floating point constants;
10748 PRINT_OPERAND must handle them. */
10749 output_operand_lossage ("floating constant misused");
10753 /* Some assemblers need integer constants to appear first. */
10754 if (CONST_INT_P (XEXP (x, 0)))
10756 output_pic_addr_const (file, XEXP (x, 0), code);
10758 output_pic_addr_const (file, XEXP (x, 1), code);
10762 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10763 output_pic_addr_const (file, XEXP (x, 1), code);
10765 output_pic_addr_const (file, XEXP (x, 0), code);
10771 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10772 output_pic_addr_const (file, XEXP (x, 0), code);
10774 output_pic_addr_const (file, XEXP (x, 1), code);
10776 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10780 gcc_assert (XVECLEN (x, 0) == 1);
10781 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10782 switch (XINT (x, 1))
10785 fputs ("@GOT", file);
10787 case UNSPEC_GOTOFF:
10788 fputs ("@GOTOFF", file);
10790 case UNSPEC_PLTOFF:
10791 fputs ("@PLTOFF", file);
10793 case UNSPEC_GOTPCREL:
10794 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10795 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10797 case UNSPEC_GOTTPOFF:
10798 /* FIXME: This might be @TPOFF in Sun ld too. */
10799 fputs ("@GOTTPOFF", file);
10802 fputs ("@TPOFF", file);
10804 case UNSPEC_NTPOFF:
10806 fputs ("@TPOFF", file);
10808 fputs ("@NTPOFF", file);
10810 case UNSPEC_DTPOFF:
10811 fputs ("@DTPOFF", file);
10813 case UNSPEC_GOTNTPOFF:
10815 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10816 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10818 fputs ("@GOTNTPOFF", file);
10820 case UNSPEC_INDNTPOFF:
10821 fputs ("@INDNTPOFF", file);
10824 case UNSPEC_MACHOPIC_OFFSET:
10826 machopic_output_function_base_name (file);
10830 output_operand_lossage ("invalid UNSPEC as operand");
10836 output_operand_lossage ("invalid expression as operand");
10840 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10841 We need to emit DTP-relative relocations. */
10843 static void ATTRIBUTE_UNUSED
10844 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10846 fputs (ASM_LONG, file);
10847 output_addr_const (file, x);
10848 fputs ("@DTPOFF", file);
10854 fputs (", 0", file);
10857 gcc_unreachable ();
10861 /* Return true if X is a representation of the PIC register. This copes
10862 with calls from ix86_find_base_term, where the register might have
10863 been replaced by a cselib value. */
10866 ix86_pic_register_p (rtx x)
10868 if (GET_CODE (x) == VALUE && CSELIB_VAL_PTR (x))
10869 return (pic_offset_table_rtx
10870 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10872 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10875 /* In the name of slightly smaller debug output, and to cater to
10876 general assembler lossage, recognize PIC+GOTOFF and turn it back
10877 into a direct symbol reference.
10879 On Darwin, this is necessary to avoid a crash, because Darwin
10880 has a different PIC label for each routine but the DWARF debugging
10881 information is not associated with any particular routine, so it's
10882 necessary to remove references to the PIC label from RTL stored by
10883 the DWARF output code. */
10886 ix86_delegitimize_address (rtx x)
10888 rtx orig_x = delegitimize_mem_from_attrs (x);
10889 /* reg_addend is NULL or a multiple of some register. */
10890 rtx reg_addend = NULL_RTX;
10891 /* const_addend is NULL or a const_int. */
10892 rtx const_addend = NULL_RTX;
10893 /* This is the result, or NULL. */
10894 rtx result = NULL_RTX;
10903 if (GET_CODE (x) != CONST
10904 || GET_CODE (XEXP (x, 0)) != UNSPEC
10905 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10906 || !MEM_P (orig_x))
10908 return XVECEXP (XEXP (x, 0), 0, 0);
10911 if (GET_CODE (x) != PLUS
10912 || GET_CODE (XEXP (x, 1)) != CONST)
10915 if (ix86_pic_register_p (XEXP (x, 0)))
10916 /* %ebx + GOT/GOTOFF */
10918 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10920 /* %ebx + %reg * scale + GOT/GOTOFF */
10921 reg_addend = XEXP (x, 0);
10922 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10923 reg_addend = XEXP (reg_addend, 1);
10924 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10925 reg_addend = XEXP (reg_addend, 0);
10928 if (!REG_P (reg_addend)
10929 && GET_CODE (reg_addend) != MULT
10930 && GET_CODE (reg_addend) != ASHIFT)
10936 x = XEXP (XEXP (x, 1), 0);
10937 if (GET_CODE (x) == PLUS
10938 && CONST_INT_P (XEXP (x, 1)))
10940 const_addend = XEXP (x, 1);
10944 if (GET_CODE (x) == UNSPEC
10945 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10946 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10947 result = XVECEXP (x, 0, 0);
10949 if (TARGET_MACHO && darwin_local_data_pic (x)
10950 && !MEM_P (orig_x))
10951 result = XVECEXP (x, 0, 0);
10957 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10959 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10963 /* If X is a machine specific address (i.e. a symbol or label being
10964 referenced as a displacement from the GOT implemented using an
10965 UNSPEC), then return the base term. Otherwise return X. */
10968 ix86_find_base_term (rtx x)
10974 if (GET_CODE (x) != CONST)
10976 term = XEXP (x, 0);
10977 if (GET_CODE (term) == PLUS
10978 && (CONST_INT_P (XEXP (term, 1))
10979 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10980 term = XEXP (term, 0);
10981 if (GET_CODE (term) != UNSPEC
10982 || XINT (term, 1) != UNSPEC_GOTPCREL)
10985 return XVECEXP (term, 0, 0);
10988 return ix86_delegitimize_address (x);
10992 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10993 int fp, FILE *file)
10995 const char *suffix;
10997 if (mode == CCFPmode || mode == CCFPUmode)
10999 code = ix86_fp_compare_code_to_integer (code);
11003 code = reverse_condition (code);
11054 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
11058 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
11059 Those same assemblers have the same but opposite lossage on cmov. */
11060 if (mode == CCmode)
11061 suffix = fp ? "nbe" : "a";
11062 else if (mode == CCCmode)
11065 gcc_unreachable ();
11081 gcc_unreachable ();
11085 gcc_assert (mode == CCmode || mode == CCCmode);
11102 gcc_unreachable ();
11106 /* ??? As above. */
11107 gcc_assert (mode == CCmode || mode == CCCmode);
11108 suffix = fp ? "nb" : "ae";
11111 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
11115 /* ??? As above. */
11116 if (mode == CCmode)
11118 else if (mode == CCCmode)
11119 suffix = fp ? "nb" : "ae";
11121 gcc_unreachable ();
11124 suffix = fp ? "u" : "p";
11127 suffix = fp ? "nu" : "np";
11130 gcc_unreachable ();
11132 fputs (suffix, file);
11135 /* Print the name of register X to FILE based on its machine mode and number.
11136 If CODE is 'w', pretend the mode is HImode.
11137 If CODE is 'b', pretend the mode is QImode.
11138 If CODE is 'k', pretend the mode is SImode.
11139 If CODE is 'q', pretend the mode is DImode.
11140 If CODE is 'x', pretend the mode is V4SFmode.
11141 If CODE is 't', pretend the mode is V8SFmode.
11142 If CODE is 'h', pretend the reg is the 'high' byte register.
11143 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11144 If CODE is 'd', duplicate the operand for AVX instruction.
11148 print_reg (rtx x, int code, FILE *file)
11151 bool duplicated = code == 'd' && TARGET_AVX;
11153 gcc_assert (x == pc_rtx
11154 || (REGNO (x) != ARG_POINTER_REGNUM
11155 && REGNO (x) != FRAME_POINTER_REGNUM
11156 && REGNO (x) != FLAGS_REG
11157 && REGNO (x) != FPSR_REG
11158 && REGNO (x) != FPCR_REG));
11160 if (ASSEMBLER_DIALECT == ASM_ATT)
11165 gcc_assert (TARGET_64BIT);
11166 fputs ("rip", file);
11170 if (code == 'w' || MMX_REG_P (x))
11172 else if (code == 'b')
11174 else if (code == 'k')
11176 else if (code == 'q')
11178 else if (code == 'y')
11180 else if (code == 'h')
11182 else if (code == 'x')
11184 else if (code == 't')
11187 code = GET_MODE_SIZE (GET_MODE (x));
11189 /* Irritatingly, AMD extended registers use different naming convention
11190 from the normal registers. */
11191 if (REX_INT_REG_P (x))
11193 gcc_assert (TARGET_64BIT);
11197 error ("extended registers have no high halves");
11200 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11203 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11206 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11209 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11212 error ("unsupported operand size for extended register");
11222 if (STACK_TOP_P (x))
11231 if (! ANY_FP_REG_P (x))
11232 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11237 reg = hi_reg_name[REGNO (x)];
11240 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11242 reg = qi_reg_name[REGNO (x)];
11245 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11247 reg = qi_high_reg_name[REGNO (x)];
11252 gcc_assert (!duplicated);
11254 fputs (hi_reg_name[REGNO (x)] + 1, file);
11259 gcc_unreachable ();
11265 if (ASSEMBLER_DIALECT == ASM_ATT)
11266 fprintf (file, ", %%%s", reg);
11268 fprintf (file, ", %s", reg);
11272 /* Locate some local-dynamic symbol still in use by this function
11273 so that we can print its name in some tls_local_dynamic_base
11277 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11281 if (GET_CODE (x) == SYMBOL_REF
11282 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11284 cfun->machine->some_ld_name = XSTR (x, 0);
11291 static const char *
11292 get_some_local_dynamic_name (void)
11296 if (cfun->machine->some_ld_name)
11297 return cfun->machine->some_ld_name;
11299 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11301 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11302 return cfun->machine->some_ld_name;
11307 /* Meaning of CODE:
11308 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11309 C -- print opcode suffix for set/cmov insn.
11310 c -- like C, but print reversed condition
11311 E,e -- likewise, but for compare-and-branch fused insn.
11312 F,f -- likewise, but for floating-point.
11313 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11315 R -- print the prefix for register names.
11316 z -- print the opcode suffix for the size of the current operand.
11317 Z -- likewise, with special suffixes for x87 instructions.
11318 * -- print a star (in certain assembler syntax)
11319 A -- print an absolute memory reference.
11320 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11321 s -- print a shift double count, followed by the assemblers argument
11323 b -- print the QImode name of the register for the indicated operand.
11324 %b0 would print %al if operands[0] is reg 0.
11325 w -- likewise, print the HImode name of the register.
11326 k -- likewise, print the SImode name of the register.
11327 q -- likewise, print the DImode name of the register.
11328 x -- likewise, print the V4SFmode name of the register.
11329 t -- likewise, print the V8SFmode name of the register.
11330 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11331 y -- print "st(0)" instead of "st" as a register.
11332 d -- print duplicated register operand for AVX instruction.
11333 D -- print condition for SSE cmp instruction.
11334 P -- if PIC, print an @PLT suffix.
11335 X -- don't print any sort of PIC '@' suffix for a symbol.
11336 & -- print some in-use local-dynamic symbol name.
11337 H -- print a memory address offset by 8; used for sse high-parts
11338 Y -- print condition for XOP pcom* instruction.
11339 + -- print a branch hint as 'cs' or 'ds' prefix
11340 ; -- print a semicolon (after prefixes due to bug in older gas).
11344 print_operand (FILE *file, rtx x, int code)
11351 if (ASSEMBLER_DIALECT == ASM_ATT)
11357 const char *name = get_some_local_dynamic_name ();
11359 output_operand_lossage ("'%%&' used without any "
11360 "local dynamic TLS references");
11362 assemble_name (file, name);
11367 switch (ASSEMBLER_DIALECT)
11374 /* Intel syntax. For absolute addresses, registers should not
11375 be surrounded by braces. */
11379 PRINT_OPERAND (file, x, 0);
11386 gcc_unreachable ();
11389 PRINT_OPERAND (file, x, 0);
11394 if (ASSEMBLER_DIALECT == ASM_ATT)
11399 if (ASSEMBLER_DIALECT == ASM_ATT)
11404 if (ASSEMBLER_DIALECT == ASM_ATT)
11409 if (ASSEMBLER_DIALECT == ASM_ATT)
11414 if (ASSEMBLER_DIALECT == ASM_ATT)
11419 if (ASSEMBLER_DIALECT == ASM_ATT)
11424 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11426 /* Opcodes don't get size suffixes if using Intel opcodes. */
11427 if (ASSEMBLER_DIALECT == ASM_INTEL)
11430 switch (GET_MODE_SIZE (GET_MODE (x)))
11449 output_operand_lossage
11450 ("invalid operand size for operand code '%c'", code);
11455 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11457 (0, "non-integer operand used with operand code '%c'", code);
11461 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11462 if (ASSEMBLER_DIALECT == ASM_INTEL)
11465 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11467 switch (GET_MODE_SIZE (GET_MODE (x)))
11470 #ifdef HAVE_AS_IX86_FILDS
11480 #ifdef HAVE_AS_IX86_FILDQ
11483 fputs ("ll", file);
11491 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11493 /* 387 opcodes don't get size suffixes
11494 if the operands are registers. */
11495 if (STACK_REG_P (x))
11498 switch (GET_MODE_SIZE (GET_MODE (x)))
11519 output_operand_lossage
11520 ("invalid operand type used with operand code '%c'", code);
11524 output_operand_lossage
11525 ("invalid operand size for operand code '%c'", code);
11542 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11544 PRINT_OPERAND (file, x, 0);
11545 fputs (", ", file);
11550 /* Little bit of braindamage here. The SSE compare instructions
11551 does use completely different names for the comparisons that the
11552 fp conditional moves. */
11555 switch (GET_CODE (x))
11558 fputs ("eq", file);
11561 fputs ("eq_us", file);
11564 fputs ("lt", file);
11567 fputs ("nge", file);
11570 fputs ("le", file);
11573 fputs ("ngt", file);
11576 fputs ("unord", file);
11579 fputs ("neq", file);
11582 fputs ("neq_oq", file);
11585 fputs ("ge", file);
11588 fputs ("nlt", file);
11591 fputs ("gt", file);
11594 fputs ("nle", file);
11597 fputs ("ord", file);
11600 output_operand_lossage ("operand is not a condition code, "
11601 "invalid operand code 'D'");
11607 switch (GET_CODE (x))
11611 fputs ("eq", file);
11615 fputs ("lt", file);
11619 fputs ("le", file);
11622 fputs ("unord", file);
11626 fputs ("neq", file);
11630 fputs ("nlt", file);
11634 fputs ("nle", file);
11637 fputs ("ord", file);
11640 output_operand_lossage ("operand is not a condition code, "
11641 "invalid operand code 'D'");
11647 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11648 if (ASSEMBLER_DIALECT == ASM_ATT)
11650 switch (GET_MODE (x))
11652 case HImode: putc ('w', file); break;
11654 case SFmode: putc ('l', file); break;
11656 case DFmode: putc ('q', file); break;
11657 default: gcc_unreachable ();
11664 if (!COMPARISON_P (x))
11666 output_operand_lossage ("operand is neither a constant nor a "
11667 "condition code, invalid operand code "
11671 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11674 if (!COMPARISON_P (x))
11676 output_operand_lossage ("operand is neither a constant nor a "
11677 "condition code, invalid operand code "
11681 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11682 if (ASSEMBLER_DIALECT == ASM_ATT)
11685 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11688 /* Like above, but reverse condition */
11690 /* Check to see if argument to %c is really a constant
11691 and not a condition code which needs to be reversed. */
11692 if (!COMPARISON_P (x))
11694 output_operand_lossage ("operand is neither a constant nor a "
11695 "condition code, invalid operand "
11699 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11702 if (!COMPARISON_P (x))
11704 output_operand_lossage ("operand is neither a constant nor a "
11705 "condition code, invalid operand "
11709 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11710 if (ASSEMBLER_DIALECT == ASM_ATT)
11713 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11717 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11721 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11725 /* It doesn't actually matter what mode we use here, as we're
11726 only going to use this for printing. */
11727 x = adjust_address_nv (x, DImode, 8);
11735 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11738 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11741 int pred_val = INTVAL (XEXP (x, 0));
11743 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11744 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11746 int taken = pred_val > REG_BR_PROB_BASE / 2;
11747 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11749 /* Emit hints only in the case default branch prediction
11750 heuristics would fail. */
11751 if (taken != cputaken)
11753 /* We use 3e (DS) prefix for taken branches and
11754 2e (CS) prefix for not taken branches. */
11756 fputs ("ds ; ", file);
11758 fputs ("cs ; ", file);
11766 switch (GET_CODE (x))
11769 fputs ("neq", file);
11772 fputs ("eq", file);
11776 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11780 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11784 fputs ("le", file);
11788 fputs ("lt", file);
11791 fputs ("unord", file);
11794 fputs ("ord", file);
11797 fputs ("ueq", file);
11800 fputs ("nlt", file);
11803 fputs ("nle", file);
11806 fputs ("ule", file);
11809 fputs ("ult", file);
11812 fputs ("une", file);
11815 output_operand_lossage ("operand is not a condition code, "
11816 "invalid operand code 'Y'");
11823 fputs (" ; ", file);
11830 output_operand_lossage ("invalid operand code '%c'", code);
11835 print_reg (x, code, file);
11837 else if (MEM_P (x))
11839 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11840 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11841 && GET_MODE (x) != BLKmode)
11844 switch (GET_MODE_SIZE (GET_MODE (x)))
11846 case 1: size = "BYTE"; break;
11847 case 2: size = "WORD"; break;
11848 case 4: size = "DWORD"; break;
11849 case 8: size = "QWORD"; break;
11850 case 12: size = "XWORD"; break;
11852 if (GET_MODE (x) == XFmode)
11858 gcc_unreachable ();
11861 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11864 else if (code == 'w')
11866 else if (code == 'k')
11869 fputs (size, file);
11870 fputs (" PTR ", file);
11874 /* Avoid (%rip) for call operands. */
11875 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11876 && !CONST_INT_P (x))
11877 output_addr_const (file, x);
11878 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11879 output_operand_lossage ("invalid constraints for operand");
11881 output_address (x);
11884 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11889 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11890 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11892 if (ASSEMBLER_DIALECT == ASM_ATT)
11894 fprintf (file, "0x%08lx", (long unsigned int) l);
11897 /* These float cases don't actually occur as immediate operands. */
11898 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11902 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11903 fputs (dstr, file);
11906 else if (GET_CODE (x) == CONST_DOUBLE
11907 && GET_MODE (x) == XFmode)
11911 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11912 fputs (dstr, file);
11917 /* We have patterns that allow zero sets of memory, for instance.
11918 In 64-bit mode, we should probably support all 8-byte vectors,
11919 since we can in fact encode that into an immediate. */
11920 if (GET_CODE (x) == CONST_VECTOR)
11922 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11928 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11930 if (ASSEMBLER_DIALECT == ASM_ATT)
11933 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11934 || GET_CODE (x) == LABEL_REF)
11936 if (ASSEMBLER_DIALECT == ASM_ATT)
11939 fputs ("OFFSET FLAT:", file);
11942 if (CONST_INT_P (x))
11943 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11945 output_pic_addr_const (file, x, code);
11947 output_addr_const (file, x);
11951 /* Print a memory operand whose address is ADDR. */
11954 print_operand_address (FILE *file, rtx addr)
11956 struct ix86_address parts;
11957 rtx base, index, disp;
11959 int ok = ix86_decompose_address (addr, &parts);
11964 index = parts.index;
11966 scale = parts.scale;
11974 if (ASSEMBLER_DIALECT == ASM_ATT)
11976 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11979 gcc_unreachable ();
11982 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11983 if (TARGET_64BIT && !base && !index)
11987 if (GET_CODE (disp) == CONST
11988 && GET_CODE (XEXP (disp, 0)) == PLUS
11989 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11990 symbol = XEXP (XEXP (disp, 0), 0);
11992 if (GET_CODE (symbol) == LABEL_REF
11993 || (GET_CODE (symbol) == SYMBOL_REF
11994 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11997 if (!base && !index)
11999 /* Displacement only requires special attention. */
12001 if (CONST_INT_P (disp))
12003 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
12004 fputs ("ds:", file);
12005 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
12008 output_pic_addr_const (file, disp, 0);
12010 output_addr_const (file, disp);
12014 if (ASSEMBLER_DIALECT == ASM_ATT)
12019 output_pic_addr_const (file, disp, 0);
12020 else if (GET_CODE (disp) == LABEL_REF)
12021 output_asm_label (disp);
12023 output_addr_const (file, disp);
12028 print_reg (base, 0, file);
12032 print_reg (index, 0, file);
12034 fprintf (file, ",%d", scale);
12040 rtx offset = NULL_RTX;
12044 /* Pull out the offset of a symbol; print any symbol itself. */
12045 if (GET_CODE (disp) == CONST
12046 && GET_CODE (XEXP (disp, 0)) == PLUS
12047 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
12049 offset = XEXP (XEXP (disp, 0), 1);
12050 disp = gen_rtx_CONST (VOIDmode,
12051 XEXP (XEXP (disp, 0), 0));
12055 output_pic_addr_const (file, disp, 0);
12056 else if (GET_CODE (disp) == LABEL_REF)
12057 output_asm_label (disp);
12058 else if (CONST_INT_P (disp))
12061 output_addr_const (file, disp);
12067 print_reg (base, 0, file);
12070 if (INTVAL (offset) >= 0)
12072 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
12076 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
12083 print_reg (index, 0, file);
12085 fprintf (file, "*%d", scale);
12093 output_addr_const_extra (FILE *file, rtx x)
12097 if (GET_CODE (x) != UNSPEC)
12100 op = XVECEXP (x, 0, 0);
12101 switch (XINT (x, 1))
12103 case UNSPEC_GOTTPOFF:
12104 output_addr_const (file, op);
12105 /* FIXME: This might be @TPOFF in Sun ld. */
12106 fputs ("@GOTTPOFF", file);
12109 output_addr_const (file, op);
12110 fputs ("@TPOFF", file);
12112 case UNSPEC_NTPOFF:
12113 output_addr_const (file, op);
12115 fputs ("@TPOFF", file);
12117 fputs ("@NTPOFF", file);
12119 case UNSPEC_DTPOFF:
12120 output_addr_const (file, op);
12121 fputs ("@DTPOFF", file);
12123 case UNSPEC_GOTNTPOFF:
12124 output_addr_const (file, op);
12126 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
12127 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
12129 fputs ("@GOTNTPOFF", file);
12131 case UNSPEC_INDNTPOFF:
12132 output_addr_const (file, op);
12133 fputs ("@INDNTPOFF", file);
12136 case UNSPEC_MACHOPIC_OFFSET:
12137 output_addr_const (file, op);
12139 machopic_output_function_base_name (file);
12150 /* Split one or more DImode RTL references into pairs of SImode
12151 references. The RTL can be REG, offsettable MEM, integer constant, or
12152 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12153 split and "num" is its length. lo_half and hi_half are output arrays
12154 that parallel "operands". */
12157 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12161 rtx op = operands[num];
12163 /* simplify_subreg refuse to split volatile memory addresses,
12164 but we still have to handle it. */
12167 lo_half[num] = adjust_address (op, SImode, 0);
12168 hi_half[num] = adjust_address (op, SImode, 4);
12172 lo_half[num] = simplify_gen_subreg (SImode, op,
12173 GET_MODE (op) == VOIDmode
12174 ? DImode : GET_MODE (op), 0);
12175 hi_half[num] = simplify_gen_subreg (SImode, op,
12176 GET_MODE (op) == VOIDmode
12177 ? DImode : GET_MODE (op), 4);
12181 /* Split one or more TImode RTL references into pairs of DImode
12182 references. The RTL can be REG, offsettable MEM, integer constant, or
12183 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12184 split and "num" is its length. lo_half and hi_half are output arrays
12185 that parallel "operands". */
12188 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12192 rtx op = operands[num];
12194 /* simplify_subreg refuse to split volatile memory addresses, but we
12195 still have to handle it. */
12198 lo_half[num] = adjust_address (op, DImode, 0);
12199 hi_half[num] = adjust_address (op, DImode, 8);
12203 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12204 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12209 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12210 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12211 is the expression of the binary operation. The output may either be
12212 emitted here, or returned to the caller, like all output_* functions.
12214 There is no guarantee that the operands are the same mode, as they
12215 might be within FLOAT or FLOAT_EXTEND expressions. */
12217 #ifndef SYSV386_COMPAT
12218 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12219 wants to fix the assemblers because that causes incompatibility
12220 with gcc. No-one wants to fix gcc because that causes
12221 incompatibility with assemblers... You can use the option of
12222 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12223 #define SYSV386_COMPAT 1
12227 output_387_binary_op (rtx insn, rtx *operands)
12229 static char buf[40];
12232 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12234 #ifdef ENABLE_CHECKING
12235 /* Even if we do not want to check the inputs, this documents input
12236 constraints. Which helps in understanding the following code. */
12237 if (STACK_REG_P (operands[0])
12238 && ((REG_P (operands[1])
12239 && REGNO (operands[0]) == REGNO (operands[1])
12240 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12241 || (REG_P (operands[2])
12242 && REGNO (operands[0]) == REGNO (operands[2])
12243 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12244 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12247 gcc_assert (is_sse);
12250 switch (GET_CODE (operands[3]))
12253 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12254 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12262 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12263 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12271 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12272 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12280 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12281 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12289 gcc_unreachable ();
12296 strcpy (buf, ssep);
12297 if (GET_MODE (operands[0]) == SFmode)
12298 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12300 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12304 strcpy (buf, ssep + 1);
12305 if (GET_MODE (operands[0]) == SFmode)
12306 strcat (buf, "ss\t{%2, %0|%0, %2}");
12308 strcat (buf, "sd\t{%2, %0|%0, %2}");
12314 switch (GET_CODE (operands[3]))
12318 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12320 rtx temp = operands[2];
12321 operands[2] = operands[1];
12322 operands[1] = temp;
12325 /* know operands[0] == operands[1]. */
12327 if (MEM_P (operands[2]))
12333 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12335 if (STACK_TOP_P (operands[0]))
12336 /* How is it that we are storing to a dead operand[2]?
12337 Well, presumably operands[1] is dead too. We can't
12338 store the result to st(0) as st(0) gets popped on this
12339 instruction. Instead store to operands[2] (which I
12340 think has to be st(1)). st(1) will be popped later.
12341 gcc <= 2.8.1 didn't have this check and generated
12342 assembly code that the Unixware assembler rejected. */
12343 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12345 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12349 if (STACK_TOP_P (operands[0]))
12350 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12352 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12357 if (MEM_P (operands[1]))
12363 if (MEM_P (operands[2]))
12369 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12372 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12373 derived assemblers, confusingly reverse the direction of
12374 the operation for fsub{r} and fdiv{r} when the
12375 destination register is not st(0). The Intel assembler
12376 doesn't have this brain damage. Read !SYSV386_COMPAT to
12377 figure out what the hardware really does. */
12378 if (STACK_TOP_P (operands[0]))
12379 p = "{p\t%0, %2|rp\t%2, %0}";
12381 p = "{rp\t%2, %0|p\t%0, %2}";
12383 if (STACK_TOP_P (operands[0]))
12384 /* As above for fmul/fadd, we can't store to st(0). */
12385 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12387 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12392 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12395 if (STACK_TOP_P (operands[0]))
12396 p = "{rp\t%0, %1|p\t%1, %0}";
12398 p = "{p\t%1, %0|rp\t%0, %1}";
12400 if (STACK_TOP_P (operands[0]))
12401 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12403 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12408 if (STACK_TOP_P (operands[0]))
12410 if (STACK_TOP_P (operands[1]))
12411 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12413 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12416 else if (STACK_TOP_P (operands[1]))
12419 p = "{\t%1, %0|r\t%0, %1}";
12421 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12427 p = "{r\t%2, %0|\t%0, %2}";
12429 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12435 gcc_unreachable ();
12442 /* Return needed mode for entity in optimize_mode_switching pass. */
12445 ix86_mode_needed (int entity, rtx insn)
12447 enum attr_i387_cw mode;
12449 /* The mode UNINITIALIZED is used to store control word after a
12450 function call or ASM pattern. The mode ANY specify that function
12451 has no requirements on the control word and make no changes in the
12452 bits we are interested in. */
12455 || (NONJUMP_INSN_P (insn)
12456 && (asm_noperands (PATTERN (insn)) >= 0
12457 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12458 return I387_CW_UNINITIALIZED;
12460 if (recog_memoized (insn) < 0)
12461 return I387_CW_ANY;
12463 mode = get_attr_i387_cw (insn);
12468 if (mode == I387_CW_TRUNC)
12473 if (mode == I387_CW_FLOOR)
12478 if (mode == I387_CW_CEIL)
12483 if (mode == I387_CW_MASK_PM)
12488 gcc_unreachable ();
12491 return I387_CW_ANY;
12494 /* Output code to initialize control word copies used by trunc?f?i and
12495 rounding patterns. CURRENT_MODE is set to current control word,
12496 while NEW_MODE is set to new control word. */
12499 emit_i387_cw_initialization (int mode)
12501 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12504 enum ix86_stack_slot slot;
12506 rtx reg = gen_reg_rtx (HImode);
12508 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12509 emit_move_insn (reg, copy_rtx (stored_mode));
12511 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12512 || optimize_function_for_size_p (cfun))
12516 case I387_CW_TRUNC:
12517 /* round toward zero (truncate) */
12518 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12519 slot = SLOT_CW_TRUNC;
12522 case I387_CW_FLOOR:
12523 /* round down toward -oo */
12524 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12525 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12526 slot = SLOT_CW_FLOOR;
12530 /* round up toward +oo */
12531 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12532 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12533 slot = SLOT_CW_CEIL;
12536 case I387_CW_MASK_PM:
12537 /* mask precision exception for nearbyint() */
12538 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12539 slot = SLOT_CW_MASK_PM;
12543 gcc_unreachable ();
12550 case I387_CW_TRUNC:
12551 /* round toward zero (truncate) */
12552 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12553 slot = SLOT_CW_TRUNC;
12556 case I387_CW_FLOOR:
12557 /* round down toward -oo */
12558 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12559 slot = SLOT_CW_FLOOR;
12563 /* round up toward +oo */
12564 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12565 slot = SLOT_CW_CEIL;
12568 case I387_CW_MASK_PM:
12569 /* mask precision exception for nearbyint() */
12570 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12571 slot = SLOT_CW_MASK_PM;
12575 gcc_unreachable ();
12579 gcc_assert (slot < MAX_386_STACK_LOCALS);
12581 new_mode = assign_386_stack_local (HImode, slot);
12582 emit_move_insn (new_mode, reg);
12585 /* Output code for INSN to convert a float to a signed int. OPERANDS
12586 are the insn operands. The output may be [HSD]Imode and the input
12587 operand may be [SDX]Fmode. */
12590 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12592 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12593 int dimode_p = GET_MODE (operands[0]) == DImode;
12594 int round_mode = get_attr_i387_cw (insn);
12596 /* Jump through a hoop or two for DImode, since the hardware has no
12597 non-popping instruction. We used to do this a different way, but
12598 that was somewhat fragile and broke with post-reload splitters. */
12599 if ((dimode_p || fisttp) && !stack_top_dies)
12600 output_asm_insn ("fld\t%y1", operands);
12602 gcc_assert (STACK_TOP_P (operands[1]));
12603 gcc_assert (MEM_P (operands[0]));
12604 gcc_assert (GET_MODE (operands[1]) != TFmode);
12607 output_asm_insn ("fisttp%Z0\t%0", operands);
12610 if (round_mode != I387_CW_ANY)
12611 output_asm_insn ("fldcw\t%3", operands);
12612 if (stack_top_dies || dimode_p)
12613 output_asm_insn ("fistp%Z0\t%0", operands);
12615 output_asm_insn ("fist%Z0\t%0", operands);
12616 if (round_mode != I387_CW_ANY)
12617 output_asm_insn ("fldcw\t%2", operands);
12623 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12624 have the values zero or one, indicates the ffreep insn's operand
12625 from the OPERANDS array. */
12627 static const char *
12628 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12630 if (TARGET_USE_FFREEP)
12631 #ifdef HAVE_AS_IX86_FFREEP
12632 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12635 static char retval[32];
12636 int regno = REGNO (operands[opno]);
12638 gcc_assert (FP_REGNO_P (regno));
12640 regno -= FIRST_STACK_REG;
12642 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12647 return opno ? "fstp\t%y1" : "fstp\t%y0";
12651 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12652 should be used. UNORDERED_P is true when fucom should be used. */
12655 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12657 int stack_top_dies;
12658 rtx cmp_op0, cmp_op1;
12659 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12663 cmp_op0 = operands[0];
12664 cmp_op1 = operands[1];
12668 cmp_op0 = operands[1];
12669 cmp_op1 = operands[2];
12674 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12675 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12676 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12677 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12679 if (GET_MODE (operands[0]) == SFmode)
12681 return &ucomiss[TARGET_AVX ? 0 : 1];
12683 return &comiss[TARGET_AVX ? 0 : 1];
12686 return &ucomisd[TARGET_AVX ? 0 : 1];
12688 return &comisd[TARGET_AVX ? 0 : 1];
12691 gcc_assert (STACK_TOP_P (cmp_op0));
12693 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12695 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12697 if (stack_top_dies)
12699 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12700 return output_387_ffreep (operands, 1);
12703 return "ftst\n\tfnstsw\t%0";
12706 if (STACK_REG_P (cmp_op1)
12708 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12709 && REGNO (cmp_op1) != FIRST_STACK_REG)
12711 /* If both the top of the 387 stack dies, and the other operand
12712 is also a stack register that dies, then this must be a
12713 `fcompp' float compare */
12717 /* There is no double popping fcomi variant. Fortunately,
12718 eflags is immune from the fstp's cc clobbering. */
12720 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12722 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12723 return output_387_ffreep (operands, 0);
12728 return "fucompp\n\tfnstsw\t%0";
12730 return "fcompp\n\tfnstsw\t%0";
12735 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12737 static const char * const alt[16] =
12739 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12740 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12741 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12742 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12744 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12745 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12749 "fcomi\t{%y1, %0|%0, %y1}",
12750 "fcomip\t{%y1, %0|%0, %y1}",
12751 "fucomi\t{%y1, %0|%0, %y1}",
12752 "fucomip\t{%y1, %0|%0, %y1}",
12763 mask = eflags_p << 3;
12764 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12765 mask |= unordered_p << 1;
12766 mask |= stack_top_dies;
12768 gcc_assert (mask < 16);
12777 ix86_output_addr_vec_elt (FILE *file, int value)
12779 const char *directive = ASM_LONG;
12783 directive = ASM_QUAD;
12785 gcc_assert (!TARGET_64BIT);
12788 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12792 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12794 const char *directive = ASM_LONG;
12797 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12798 directive = ASM_QUAD;
12800 gcc_assert (!TARGET_64BIT);
12802 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12803 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12804 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12805 directive, value, rel);
12806 else if (HAVE_AS_GOTOFF_IN_DATA)
12807 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12809 else if (TARGET_MACHO)
12811 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12812 machopic_output_function_base_name (file);
12817 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12818 GOT_SYMBOL_NAME, value);
12821 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12825 ix86_expand_clear (rtx dest)
12829 /* We play register width games, which are only valid after reload. */
12830 gcc_assert (reload_completed);
12832 /* Avoid HImode and its attendant prefix byte. */
12833 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12834 dest = gen_rtx_REG (SImode, REGNO (dest));
12835 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12837 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12838 if (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ())
12840 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12841 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12847 /* X is an unchanging MEM. If it is a constant pool reference, return
12848 the constant pool rtx, else NULL. */
12851 maybe_get_pool_constant (rtx x)
12853 x = ix86_delegitimize_address (XEXP (x, 0));
12855 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12856 return get_pool_constant (x);
12862 ix86_expand_move (enum machine_mode mode, rtx operands[])
12865 enum tls_model model;
12870 if (GET_CODE (op1) == SYMBOL_REF)
12872 model = SYMBOL_REF_TLS_MODEL (op1);
12875 op1 = legitimize_tls_address (op1, model, true);
12876 op1 = force_operand (op1, op0);
12880 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12881 && SYMBOL_REF_DLLIMPORT_P (op1))
12882 op1 = legitimize_dllimport_symbol (op1, false);
12884 else if (GET_CODE (op1) == CONST
12885 && GET_CODE (XEXP (op1, 0)) == PLUS
12886 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12888 rtx addend = XEXP (XEXP (op1, 0), 1);
12889 rtx symbol = XEXP (XEXP (op1, 0), 0);
12892 model = SYMBOL_REF_TLS_MODEL (symbol);
12894 tmp = legitimize_tls_address (symbol, model, true);
12895 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12896 && SYMBOL_REF_DLLIMPORT_P (symbol))
12897 tmp = legitimize_dllimport_symbol (symbol, true);
12901 tmp = force_operand (tmp, NULL);
12902 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12903 op0, 1, OPTAB_DIRECT);
12909 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12911 if (TARGET_MACHO && !TARGET_64BIT)
12916 rtx temp = ((reload_in_progress
12917 || ((op0 && REG_P (op0))
12919 ? op0 : gen_reg_rtx (Pmode));
12920 op1 = machopic_indirect_data_reference (op1, temp);
12921 op1 = machopic_legitimize_pic_address (op1, mode,
12922 temp == op1 ? 0 : temp);
12924 else if (MACHOPIC_INDIRECT)
12925 op1 = machopic_indirect_data_reference (op1, 0);
12933 op1 = force_reg (Pmode, op1);
12934 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12936 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12937 op1 = legitimize_pic_address (op1, reg);
12946 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12947 || !push_operand (op0, mode))
12949 op1 = force_reg (mode, op1);
12951 if (push_operand (op0, mode)
12952 && ! general_no_elim_operand (op1, mode))
12953 op1 = copy_to_mode_reg (mode, op1);
12955 /* Force large constants in 64bit compilation into register
12956 to get them CSEed. */
12957 if (can_create_pseudo_p ()
12958 && (mode == DImode) && TARGET_64BIT
12959 && immediate_operand (op1, mode)
12960 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12961 && !register_operand (op0, mode)
12963 op1 = copy_to_mode_reg (mode, op1);
12965 if (can_create_pseudo_p ()
12966 && FLOAT_MODE_P (mode)
12967 && GET_CODE (op1) == CONST_DOUBLE)
12969 /* If we are loading a floating point constant to a register,
12970 force the value to memory now, since we'll get better code
12971 out the back end. */
12973 op1 = validize_mem (force_const_mem (mode, op1));
12974 if (!register_operand (op0, mode))
12976 rtx temp = gen_reg_rtx (mode);
12977 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12978 emit_move_insn (op0, temp);
12984 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12988 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12990 rtx op0 = operands[0], op1 = operands[1];
12991 unsigned int align = GET_MODE_ALIGNMENT (mode);
12993 /* Force constants other than zero into memory. We do not know how
12994 the instructions used to build constants modify the upper 64 bits
12995 of the register, once we have that information we may be able
12996 to handle some of them more efficiently. */
12997 if (can_create_pseudo_p ()
12998 && register_operand (op0, mode)
12999 && (CONSTANT_P (op1)
13000 || (GET_CODE (op1) == SUBREG
13001 && CONSTANT_P (SUBREG_REG (op1))))
13002 && !standard_sse_constant_p (op1))
13003 op1 = validize_mem (force_const_mem (mode, op1));
13005 /* We need to check memory alignment for SSE mode since attribute
13006 can make operands unaligned. */
13007 if (can_create_pseudo_p ()
13008 && SSE_REG_MODE_P (mode)
13009 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
13010 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
13014 /* ix86_expand_vector_move_misalign() does not like constants ... */
13015 if (CONSTANT_P (op1)
13016 || (GET_CODE (op1) == SUBREG
13017 && CONSTANT_P (SUBREG_REG (op1))))
13018 op1 = validize_mem (force_const_mem (mode, op1));
13020 /* ... nor both arguments in memory. */
13021 if (!register_operand (op0, mode)
13022 && !register_operand (op1, mode))
13023 op1 = force_reg (mode, op1);
13025 tmp[0] = op0; tmp[1] = op1;
13026 ix86_expand_vector_move_misalign (mode, tmp);
13030 /* Make operand1 a register if it isn't already. */
13031 if (can_create_pseudo_p ()
13032 && !register_operand (op0, mode)
13033 && !register_operand (op1, mode))
13035 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
13039 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
13042 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
13043 straight to ix86_expand_vector_move. */
13044 /* Code generation for scalar reg-reg moves of single and double precision data:
13045 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
13049 if (x86_sse_partial_reg_dependency == true)
13054 Code generation for scalar loads of double precision data:
13055 if (x86_sse_split_regs == true)
13056 movlpd mem, reg (gas syntax)
13060 Code generation for unaligned packed loads of single precision data
13061 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
13062 if (x86_sse_unaligned_move_optimal)
13065 if (x86_sse_partial_reg_dependency == true)
13077 Code generation for unaligned packed loads of double precision data
13078 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
13079 if (x86_sse_unaligned_move_optimal)
13082 if (x86_sse_split_regs == true)
13095 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
13104 switch (GET_MODE_CLASS (mode))
13106 case MODE_VECTOR_INT:
13108 switch (GET_MODE_SIZE (mode))
13111 op0 = gen_lowpart (V16QImode, op0);
13112 op1 = gen_lowpart (V16QImode, op1);
13113 emit_insn (gen_avx_movdqu (op0, op1));
13116 op0 = gen_lowpart (V32QImode, op0);
13117 op1 = gen_lowpart (V32QImode, op1);
13118 emit_insn (gen_avx_movdqu256 (op0, op1));
13121 gcc_unreachable ();
13124 case MODE_VECTOR_FLOAT:
13125 op0 = gen_lowpart (mode, op0);
13126 op1 = gen_lowpart (mode, op1);
13131 emit_insn (gen_avx_movups (op0, op1));
13134 emit_insn (gen_avx_movups256 (op0, op1));
13137 emit_insn (gen_avx_movupd (op0, op1));
13140 emit_insn (gen_avx_movupd256 (op0, op1));
13143 gcc_unreachable ();
13148 gcc_unreachable ();
13156 /* If we're optimizing for size, movups is the smallest. */
13157 if (optimize_insn_for_size_p ())
13159 op0 = gen_lowpart (V4SFmode, op0);
13160 op1 = gen_lowpart (V4SFmode, op1);
13161 emit_insn (gen_sse_movups (op0, op1));
13165 /* ??? If we have typed data, then it would appear that using
13166 movdqu is the only way to get unaligned data loaded with
13168 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13170 op0 = gen_lowpart (V16QImode, op0);
13171 op1 = gen_lowpart (V16QImode, op1);
13172 emit_insn (gen_sse2_movdqu (op0, op1));
13176 if (TARGET_SSE2 && mode == V2DFmode)
13180 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13182 op0 = gen_lowpart (V2DFmode, op0);
13183 op1 = gen_lowpart (V2DFmode, op1);
13184 emit_insn (gen_sse2_movupd (op0, op1));
13188 /* When SSE registers are split into halves, we can avoid
13189 writing to the top half twice. */
13190 if (TARGET_SSE_SPLIT_REGS)
13192 emit_clobber (op0);
13197 /* ??? Not sure about the best option for the Intel chips.
13198 The following would seem to satisfy; the register is
13199 entirely cleared, breaking the dependency chain. We
13200 then store to the upper half, with a dependency depth
13201 of one. A rumor has it that Intel recommends two movsd
13202 followed by an unpacklpd, but this is unconfirmed. And
13203 given that the dependency depth of the unpacklpd would
13204 still be one, I'm not sure why this would be better. */
13205 zero = CONST0_RTX (V2DFmode);
13208 m = adjust_address (op1, DFmode, 0);
13209 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13210 m = adjust_address (op1, DFmode, 8);
13211 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13215 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13217 op0 = gen_lowpart (V4SFmode, op0);
13218 op1 = gen_lowpart (V4SFmode, op1);
13219 emit_insn (gen_sse_movups (op0, op1));
13223 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13224 emit_move_insn (op0, CONST0_RTX (mode));
13226 emit_clobber (op0);
13228 if (mode != V4SFmode)
13229 op0 = gen_lowpart (V4SFmode, op0);
13230 m = adjust_address (op1, V2SFmode, 0);
13231 emit_insn (gen_sse_loadlps (op0, op0, m));
13232 m = adjust_address (op1, V2SFmode, 8);
13233 emit_insn (gen_sse_loadhps (op0, op0, m));
13236 else if (MEM_P (op0))
13238 /* If we're optimizing for size, movups is the smallest. */
13239 if (optimize_insn_for_size_p ())
13241 op0 = gen_lowpart (V4SFmode, op0);
13242 op1 = gen_lowpart (V4SFmode, op1);
13243 emit_insn (gen_sse_movups (op0, op1));
13247 /* ??? Similar to above, only less clear because of quote
13248 typeless stores unquote. */
13249 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13250 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13252 op0 = gen_lowpart (V16QImode, op0);
13253 op1 = gen_lowpart (V16QImode, op1);
13254 emit_insn (gen_sse2_movdqu (op0, op1));
13258 if (TARGET_SSE2 && mode == V2DFmode)
13260 m = adjust_address (op0, DFmode, 0);
13261 emit_insn (gen_sse2_storelpd (m, op1));
13262 m = adjust_address (op0, DFmode, 8);
13263 emit_insn (gen_sse2_storehpd (m, op1));
13267 if (mode != V4SFmode)
13268 op1 = gen_lowpart (V4SFmode, op1);
13269 m = adjust_address (op0, V2SFmode, 0);
13270 emit_insn (gen_sse_storelps (m, op1));
13271 m = adjust_address (op0, V2SFmode, 8);
13272 emit_insn (gen_sse_storehps (m, op1));
13276 gcc_unreachable ();
13279 /* Expand a push in MODE. This is some mode for which we do not support
13280 proper push instructions, at least from the registers that we expect
13281 the value to live in. */
13284 ix86_expand_push (enum machine_mode mode, rtx x)
13288 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13289 GEN_INT (-GET_MODE_SIZE (mode)),
13290 stack_pointer_rtx, 1, OPTAB_DIRECT);
13291 if (tmp != stack_pointer_rtx)
13292 emit_move_insn (stack_pointer_rtx, tmp);
13294 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13296 /* When we push an operand onto stack, it has to be aligned at least
13297 at the function argument boundary. However since we don't have
13298 the argument type, we can't determine the actual argument
13300 emit_move_insn (tmp, x);
13303 /* Helper function of ix86_fixup_binary_operands to canonicalize
13304 operand order. Returns true if the operands should be swapped. */
13307 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13310 rtx dst = operands[0];
13311 rtx src1 = operands[1];
13312 rtx src2 = operands[2];
13314 /* If the operation is not commutative, we can't do anything. */
13315 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13318 /* Highest priority is that src1 should match dst. */
13319 if (rtx_equal_p (dst, src1))
13321 if (rtx_equal_p (dst, src2))
13324 /* Next highest priority is that immediate constants come second. */
13325 if (immediate_operand (src2, mode))
13327 if (immediate_operand (src1, mode))
13330 /* Lowest priority is that memory references should come second. */
13340 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13341 destination to use for the operation. If different from the true
13342 destination in operands[0], a copy operation will be required. */
13345 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13348 rtx dst = operands[0];
13349 rtx src1 = operands[1];
13350 rtx src2 = operands[2];
13352 /* Canonicalize operand order. */
13353 if (ix86_swap_binary_operands_p (code, mode, operands))
13357 /* It is invalid to swap operands of different modes. */
13358 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13365 /* Both source operands cannot be in memory. */
13366 if (MEM_P (src1) && MEM_P (src2))
13368 /* Optimization: Only read from memory once. */
13369 if (rtx_equal_p (src1, src2))
13371 src2 = force_reg (mode, src2);
13375 src2 = force_reg (mode, src2);
13378 /* If the destination is memory, and we do not have matching source
13379 operands, do things in registers. */
13380 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13381 dst = gen_reg_rtx (mode);
13383 /* Source 1 cannot be a constant. */
13384 if (CONSTANT_P (src1))
13385 src1 = force_reg (mode, src1);
13387 /* Source 1 cannot be a non-matching memory. */
13388 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13389 src1 = force_reg (mode, src1);
13391 operands[1] = src1;
13392 operands[2] = src2;
13396 /* Similarly, but assume that the destination has already been
13397 set up properly. */
13400 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13401 enum machine_mode mode, rtx operands[])
13403 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13404 gcc_assert (dst == operands[0]);
13407 /* Attempt to expand a binary operator. Make the expansion closer to the
13408 actual machine, then just general_operand, which will allow 3 separate
13409 memory references (one output, two input) in a single insn. */
13412 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13415 rtx src1, src2, dst, op, clob;
13417 dst = ix86_fixup_binary_operands (code, mode, operands);
13418 src1 = operands[1];
13419 src2 = operands[2];
13421 /* Emit the instruction. */
13423 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13424 if (reload_in_progress)
13426 /* Reload doesn't know about the flags register, and doesn't know that
13427 it doesn't want to clobber it. We can only do this with PLUS. */
13428 gcc_assert (code == PLUS);
13433 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13434 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13437 /* Fix up the destination if needed. */
13438 if (dst != operands[0])
13439 emit_move_insn (operands[0], dst);
13442 /* Return TRUE or FALSE depending on whether the binary operator meets the
13443 appropriate constraints. */
13446 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13449 rtx dst = operands[0];
13450 rtx src1 = operands[1];
13451 rtx src2 = operands[2];
13453 /* Both source operands cannot be in memory. */
13454 if (MEM_P (src1) && MEM_P (src2))
13457 /* Canonicalize operand order for commutative operators. */
13458 if (ix86_swap_binary_operands_p (code, mode, operands))
13465 /* If the destination is memory, we must have a matching source operand. */
13466 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13469 /* Source 1 cannot be a constant. */
13470 if (CONSTANT_P (src1))
13473 /* Source 1 cannot be a non-matching memory. */
13474 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13480 /* Attempt to expand a unary operator. Make the expansion closer to the
13481 actual machine, then just general_operand, which will allow 2 separate
13482 memory references (one output, one input) in a single insn. */
13485 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13488 int matching_memory;
13489 rtx src, dst, op, clob;
13494 /* If the destination is memory, and we do not have matching source
13495 operands, do things in registers. */
13496 matching_memory = 0;
13499 if (rtx_equal_p (dst, src))
13500 matching_memory = 1;
13502 dst = gen_reg_rtx (mode);
13505 /* When source operand is memory, destination must match. */
13506 if (MEM_P (src) && !matching_memory)
13507 src = force_reg (mode, src);
13509 /* Emit the instruction. */
13511 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13512 if (reload_in_progress || code == NOT)
13514 /* Reload doesn't know about the flags register, and doesn't know that
13515 it doesn't want to clobber it. */
13516 gcc_assert (code == NOT);
13521 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13522 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13525 /* Fix up the destination if needed. */
13526 if (dst != operands[0])
13527 emit_move_insn (operands[0], dst);
13530 #define LEA_SEARCH_THRESHOLD 12
13532 /* Search backward for non-agu definition of register number REGNO1
13533 or register number REGNO2 in INSN's basic block until
13534 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13535 2. Reach BB boundary, or
13536 3. Reach agu definition.
13537 Returns the distance between the non-agu definition point and INSN.
13538 If no definition point, returns -1. */
13541 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13544 basic_block bb = BLOCK_FOR_INSN (insn);
13547 enum attr_type insn_type;
13549 if (insn != BB_HEAD (bb))
13551 rtx prev = PREV_INSN (insn);
13552 while (prev && distance < LEA_SEARCH_THRESHOLD)
13557 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13558 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13559 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13560 && (regno1 == DF_REF_REGNO (*def_rec)
13561 || regno2 == DF_REF_REGNO (*def_rec)))
13563 insn_type = get_attr_type (prev);
13564 if (insn_type != TYPE_LEA)
13568 if (prev == BB_HEAD (bb))
13570 prev = PREV_INSN (prev);
13574 if (distance < LEA_SEARCH_THRESHOLD)
13578 bool simple_loop = false;
13580 FOR_EACH_EDGE (e, ei, bb->preds)
13583 simple_loop = true;
13589 rtx prev = BB_END (bb);
13592 && distance < LEA_SEARCH_THRESHOLD)
13597 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13598 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13599 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13600 && (regno1 == DF_REF_REGNO (*def_rec)
13601 || regno2 == DF_REF_REGNO (*def_rec)))
13603 insn_type = get_attr_type (prev);
13604 if (insn_type != TYPE_LEA)
13608 prev = PREV_INSN (prev);
13616 /* get_attr_type may modify recog data. We want to make sure
13617 that recog data is valid for instruction INSN, on which
13618 distance_non_agu_define is called. INSN is unchanged here. */
13619 extract_insn_cached (insn);
13623 /* Return the distance between INSN and the next insn that uses
13624 register number REGNO0 in memory address. Return -1 if no such
13625 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13628 distance_agu_use (unsigned int regno0, rtx insn)
13630 basic_block bb = BLOCK_FOR_INSN (insn);
13635 if (insn != BB_END (bb))
13637 rtx next = NEXT_INSN (insn);
13638 while (next && distance < LEA_SEARCH_THRESHOLD)
13644 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13645 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13646 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13647 && regno0 == DF_REF_REGNO (*use_rec))
13649 /* Return DISTANCE if OP0 is used in memory
13650 address in NEXT. */
13654 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13655 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13656 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13657 && regno0 == DF_REF_REGNO (*def_rec))
13659 /* Return -1 if OP0 is set in NEXT. */
13663 if (next == BB_END (bb))
13665 next = NEXT_INSN (next);
13669 if (distance < LEA_SEARCH_THRESHOLD)
13673 bool simple_loop = false;
13675 FOR_EACH_EDGE (e, ei, bb->succs)
13678 simple_loop = true;
13684 rtx next = BB_HEAD (bb);
13687 && distance < LEA_SEARCH_THRESHOLD)
13693 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13694 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13695 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13696 && regno0 == DF_REF_REGNO (*use_rec))
13698 /* Return DISTANCE if OP0 is used in memory
13699 address in NEXT. */
13703 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13704 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13705 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13706 && regno0 == DF_REF_REGNO (*def_rec))
13708 /* Return -1 if OP0 is set in NEXT. */
13713 next = NEXT_INSN (next);
13721 /* Define this macro to tune LEA priority vs ADD, it take effect when
13722 there is a dilemma of choicing LEA or ADD
13723 Negative value: ADD is more preferred than LEA
13725 Positive value: LEA is more preferred than ADD*/
13726 #define IX86_LEA_PRIORITY 2
13728 /* Return true if it is ok to optimize an ADD operation to LEA
13729 operation to avoid flag register consumation. For the processors
13730 like ATOM, if the destination register of LEA holds an actual
13731 address which will be used soon, LEA is better and otherwise ADD
13735 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13736 rtx insn, rtx operands[])
13738 unsigned int regno0 = true_regnum (operands[0]);
13739 unsigned int regno1 = true_regnum (operands[1]);
13740 unsigned int regno2;
13742 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13743 return regno0 != regno1;
13745 regno2 = true_regnum (operands[2]);
13747 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13748 if (regno0 != regno1 && regno0 != regno2)
13752 int dist_define, dist_use;
13753 dist_define = distance_non_agu_define (regno1, regno2, insn);
13754 if (dist_define <= 0)
13757 /* If this insn has both backward non-agu dependence and forward
13758 agu dependence, the one with short distance take effect. */
13759 dist_use = distance_agu_use (regno0, insn);
13761 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13768 /* Return true if destination reg of SET_BODY is shift count of
13772 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13778 /* Retrieve destination of SET_BODY. */
13779 switch (GET_CODE (set_body))
13782 set_dest = SET_DEST (set_body);
13783 if (!set_dest || !REG_P (set_dest))
13787 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13788 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13796 /* Retrieve shift count of USE_BODY. */
13797 switch (GET_CODE (use_body))
13800 shift_rtx = XEXP (use_body, 1);
13803 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13804 if (ix86_dep_by_shift_count_body (set_body,
13805 XVECEXP (use_body, 0, i)))
13813 && (GET_CODE (shift_rtx) == ASHIFT
13814 || GET_CODE (shift_rtx) == LSHIFTRT
13815 || GET_CODE (shift_rtx) == ASHIFTRT
13816 || GET_CODE (shift_rtx) == ROTATE
13817 || GET_CODE (shift_rtx) == ROTATERT))
13819 rtx shift_count = XEXP (shift_rtx, 1);
13821 /* Return true if shift count is dest of SET_BODY. */
13822 if (REG_P (shift_count)
13823 && true_regnum (set_dest) == true_regnum (shift_count))
13830 /* Return true if destination reg of SET_INSN is shift count of
13834 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13836 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13837 PATTERN (use_insn));
13840 /* Return TRUE or FALSE depending on whether the unary operator meets the
13841 appropriate constraints. */
13844 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13845 enum machine_mode mode ATTRIBUTE_UNUSED,
13846 rtx operands[2] ATTRIBUTE_UNUSED)
13848 /* If one of operands is memory, source and destination must match. */
13849 if ((MEM_P (operands[0])
13850 || MEM_P (operands[1]))
13851 && ! rtx_equal_p (operands[0], operands[1]))
13856 /* Post-reload splitter for converting an SF or DFmode value in an
13857 SSE register into an unsigned SImode. */
13860 ix86_split_convert_uns_si_sse (rtx operands[])
13862 enum machine_mode vecmode;
13863 rtx value, large, zero_or_two31, input, two31, x;
13865 large = operands[1];
13866 zero_or_two31 = operands[2];
13867 input = operands[3];
13868 two31 = operands[4];
13869 vecmode = GET_MODE (large);
13870 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13872 /* Load up the value into the low element. We must ensure that the other
13873 elements are valid floats -- zero is the easiest such value. */
13876 if (vecmode == V4SFmode)
13877 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13879 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13883 input = gen_rtx_REG (vecmode, REGNO (input));
13884 emit_move_insn (value, CONST0_RTX (vecmode));
13885 if (vecmode == V4SFmode)
13886 emit_insn (gen_sse_movss (value, value, input));
13888 emit_insn (gen_sse2_movsd (value, value, input));
13891 emit_move_insn (large, two31);
13892 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13894 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13895 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13897 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13898 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13900 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13901 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13903 large = gen_rtx_REG (V4SImode, REGNO (large));
13904 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13906 x = gen_rtx_REG (V4SImode, REGNO (value));
13907 if (vecmode == V4SFmode)
13908 emit_insn (gen_sse2_cvttps2dq (x, value));
13910 emit_insn (gen_sse2_cvttpd2dq (x, value));
13913 emit_insn (gen_xorv4si3 (value, value, large));
13916 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13917 Expects the 64-bit DImode to be supplied in a pair of integral
13918 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13919 -mfpmath=sse, !optimize_size only. */
13922 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13924 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13925 rtx int_xmm, fp_xmm;
13926 rtx biases, exponents;
13929 int_xmm = gen_reg_rtx (V4SImode);
13930 if (TARGET_INTER_UNIT_MOVES)
13931 emit_insn (gen_movdi_to_sse (int_xmm, input));
13932 else if (TARGET_SSE_SPLIT_REGS)
13934 emit_clobber (int_xmm);
13935 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13939 x = gen_reg_rtx (V2DImode);
13940 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13941 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13944 x = gen_rtx_CONST_VECTOR (V4SImode,
13945 gen_rtvec (4, GEN_INT (0x43300000UL),
13946 GEN_INT (0x45300000UL),
13947 const0_rtx, const0_rtx));
13948 exponents = validize_mem (force_const_mem (V4SImode, x));
13950 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13951 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13953 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13954 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13955 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13956 (0x1.0p84 + double(fp_value_hi_xmm)).
13957 Note these exponents differ by 32. */
13959 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13961 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13962 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13963 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13964 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13965 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13966 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13967 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13968 biases = validize_mem (force_const_mem (V2DFmode, biases));
13969 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13971 /* Add the upper and lower DFmode values together. */
13973 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13976 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13977 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13978 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13981 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13984 /* Not used, but eases macroization of patterns. */
13986 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13987 rtx input ATTRIBUTE_UNUSED)
13989 gcc_unreachable ();
13992 /* Convert an unsigned SImode value into a DFmode. Only currently used
13993 for SSE, but applicable anywhere. */
13996 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13998 REAL_VALUE_TYPE TWO31r;
14001 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
14002 NULL, 1, OPTAB_DIRECT);
14004 fp = gen_reg_rtx (DFmode);
14005 emit_insn (gen_floatsidf2 (fp, x));
14007 real_ldexp (&TWO31r, &dconst1, 31);
14008 x = const_double_from_real_value (TWO31r, DFmode);
14010 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
14012 emit_move_insn (target, x);
14015 /* Convert a signed DImode value into a DFmode. Only used for SSE in
14016 32-bit mode; otherwise we have a direct convert instruction. */
14019 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
14021 REAL_VALUE_TYPE TWO32r;
14022 rtx fp_lo, fp_hi, x;
14024 fp_lo = gen_reg_rtx (DFmode);
14025 fp_hi = gen_reg_rtx (DFmode);
14027 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
14029 real_ldexp (&TWO32r, &dconst1, 32);
14030 x = const_double_from_real_value (TWO32r, DFmode);
14031 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
14033 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
14035 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
14038 emit_move_insn (target, x);
14041 /* Convert an unsigned SImode value into a SFmode, using only SSE.
14042 For x86_32, -mfpmath=sse, !optimize_size only. */
14044 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
14046 REAL_VALUE_TYPE ONE16r;
14047 rtx fp_hi, fp_lo, int_hi, int_lo, x;
14049 real_ldexp (&ONE16r, &dconst1, 16);
14050 x = const_double_from_real_value (ONE16r, SFmode);
14051 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
14052 NULL, 0, OPTAB_DIRECT);
14053 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
14054 NULL, 0, OPTAB_DIRECT);
14055 fp_hi = gen_reg_rtx (SFmode);
14056 fp_lo = gen_reg_rtx (SFmode);
14057 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
14058 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
14059 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
14061 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
14063 if (!rtx_equal_p (target, fp_hi))
14064 emit_move_insn (target, fp_hi);
14067 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
14068 then replicate the value for all elements of the vector
14072 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
14079 v = gen_rtvec (4, value, value, value, value);
14080 return gen_rtx_CONST_VECTOR (V4SImode, v);
14084 v = gen_rtvec (2, value, value);
14085 return gen_rtx_CONST_VECTOR (V2DImode, v);
14089 v = gen_rtvec (4, value, value, value, value);
14091 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
14092 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
14093 return gen_rtx_CONST_VECTOR (V4SFmode, v);
14097 v = gen_rtvec (2, value, value);
14099 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
14100 return gen_rtx_CONST_VECTOR (V2DFmode, v);
14103 gcc_unreachable ();
14107 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
14108 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
14109 for an SSE register. If VECT is true, then replicate the mask for
14110 all elements of the vector register. If INVERT is true, then create
14111 a mask excluding the sign bit. */
14114 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
14116 enum machine_mode vec_mode, imode;
14117 HOST_WIDE_INT hi, lo;
14122 /* Find the sign bit, sign extended to 2*HWI. */
14128 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
14129 lo = 0x80000000, hi = lo < 0;
14135 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
14136 if (HOST_BITS_PER_WIDE_INT >= 64)
14137 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
14139 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14144 vec_mode = VOIDmode;
14145 if (HOST_BITS_PER_WIDE_INT >= 64)
14148 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
14155 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14159 lo = ~lo, hi = ~hi;
14165 mask = immed_double_const (lo, hi, imode);
14167 vec = gen_rtvec (2, v, mask);
14168 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
14169 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
14176 gcc_unreachable ();
14180 lo = ~lo, hi = ~hi;
14182 /* Force this value into the low part of a fp vector constant. */
14183 mask = immed_double_const (lo, hi, imode);
14184 mask = gen_lowpart (mode, mask);
14186 if (vec_mode == VOIDmode)
14187 return force_reg (mode, mask);
14189 v = ix86_build_const_vector (mode, vect, mask);
14190 return force_reg (vec_mode, v);
14193 /* Generate code for floating point ABS or NEG. */
14196 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14199 rtx mask, set, use, clob, dst, src;
14200 bool use_sse = false;
14201 bool vector_mode = VECTOR_MODE_P (mode);
14202 enum machine_mode elt_mode = mode;
14206 elt_mode = GET_MODE_INNER (mode);
14209 else if (mode == TFmode)
14211 else if (TARGET_SSE_MATH)
14212 use_sse = SSE_FLOAT_MODE_P (mode);
14214 /* NEG and ABS performed with SSE use bitwise mask operations.
14215 Create the appropriate mask now. */
14217 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14226 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14227 set = gen_rtx_SET (VOIDmode, dst, set);
14232 set = gen_rtx_fmt_e (code, mode, src);
14233 set = gen_rtx_SET (VOIDmode, dst, set);
14236 use = gen_rtx_USE (VOIDmode, mask);
14237 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14238 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14239 gen_rtvec (3, set, use, clob)));
14246 /* Expand a copysign operation. Special case operand 0 being a constant. */
14249 ix86_expand_copysign (rtx operands[])
14251 enum machine_mode mode;
14252 rtx dest, op0, op1, mask, nmask;
14254 dest = operands[0];
14258 mode = GET_MODE (dest);
14260 if (GET_CODE (op0) == CONST_DOUBLE)
14262 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14264 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14265 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14267 if (mode == SFmode || mode == DFmode)
14269 enum machine_mode vmode;
14271 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14273 if (op0 == CONST0_RTX (mode))
14274 op0 = CONST0_RTX (vmode);
14277 rtx v = ix86_build_const_vector (mode, false, op0);
14279 op0 = force_reg (vmode, v);
14282 else if (op0 != CONST0_RTX (mode))
14283 op0 = force_reg (mode, op0);
14285 mask = ix86_build_signbit_mask (mode, 0, 0);
14287 if (mode == SFmode)
14288 copysign_insn = gen_copysignsf3_const;
14289 else if (mode == DFmode)
14290 copysign_insn = gen_copysigndf3_const;
14292 copysign_insn = gen_copysigntf3_const;
14294 emit_insn (copysign_insn (dest, op0, op1, mask));
14298 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14300 nmask = ix86_build_signbit_mask (mode, 0, 1);
14301 mask = ix86_build_signbit_mask (mode, 0, 0);
14303 if (mode == SFmode)
14304 copysign_insn = gen_copysignsf3_var;
14305 else if (mode == DFmode)
14306 copysign_insn = gen_copysigndf3_var;
14308 copysign_insn = gen_copysigntf3_var;
14310 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14314 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14315 be a constant, and so has already been expanded into a vector constant. */
14318 ix86_split_copysign_const (rtx operands[])
14320 enum machine_mode mode, vmode;
14321 rtx dest, op0, mask, x;
14323 dest = operands[0];
14325 mask = operands[3];
14327 mode = GET_MODE (dest);
14328 vmode = GET_MODE (mask);
14330 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14331 x = gen_rtx_AND (vmode, dest, mask);
14332 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14334 if (op0 != CONST0_RTX (vmode))
14336 x = gen_rtx_IOR (vmode, dest, op0);
14337 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14341 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14342 so we have to do two masks. */
14345 ix86_split_copysign_var (rtx operands[])
14347 enum machine_mode mode, vmode;
14348 rtx dest, scratch, op0, op1, mask, nmask, x;
14350 dest = operands[0];
14351 scratch = operands[1];
14354 nmask = operands[4];
14355 mask = operands[5];
14357 mode = GET_MODE (dest);
14358 vmode = GET_MODE (mask);
14360 if (rtx_equal_p (op0, op1))
14362 /* Shouldn't happen often (it's useless, obviously), but when it does
14363 we'd generate incorrect code if we continue below. */
14364 emit_move_insn (dest, op0);
14368 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14370 gcc_assert (REGNO (op1) == REGNO (scratch));
14372 x = gen_rtx_AND (vmode, scratch, mask);
14373 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14376 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14377 x = gen_rtx_NOT (vmode, dest);
14378 x = gen_rtx_AND (vmode, x, op0);
14379 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14383 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14385 x = gen_rtx_AND (vmode, scratch, mask);
14387 else /* alternative 2,4 */
14389 gcc_assert (REGNO (mask) == REGNO (scratch));
14390 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14391 x = gen_rtx_AND (vmode, scratch, op1);
14393 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14395 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14397 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14398 x = gen_rtx_AND (vmode, dest, nmask);
14400 else /* alternative 3,4 */
14402 gcc_assert (REGNO (nmask) == REGNO (dest));
14404 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14405 x = gen_rtx_AND (vmode, dest, op0);
14407 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14410 x = gen_rtx_IOR (vmode, dest, scratch);
14411 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14414 /* Return TRUE or FALSE depending on whether the first SET in INSN
14415 has source and destination with matching CC modes, and that the
14416 CC mode is at least as constrained as REQ_MODE. */
14419 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14422 enum machine_mode set_mode;
14424 set = PATTERN (insn);
14425 if (GET_CODE (set) == PARALLEL)
14426 set = XVECEXP (set, 0, 0);
14427 gcc_assert (GET_CODE (set) == SET);
14428 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14430 set_mode = GET_MODE (SET_DEST (set));
14434 if (req_mode != CCNOmode
14435 && (req_mode != CCmode
14436 || XEXP (SET_SRC (set), 1) != const0_rtx))
14440 if (req_mode == CCGCmode)
14444 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14448 if (req_mode == CCZmode)
14459 gcc_unreachable ();
14462 return (GET_MODE (SET_SRC (set)) == set_mode);
14465 /* Generate insn patterns to do an integer compare of OPERANDS. */
14468 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14470 enum machine_mode cmpmode;
14473 cmpmode = SELECT_CC_MODE (code, op0, op1);
14474 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14476 /* This is very simple, but making the interface the same as in the
14477 FP case makes the rest of the code easier. */
14478 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14479 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14481 /* Return the test that should be put into the flags user, i.e.
14482 the bcc, scc, or cmov instruction. */
14483 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14486 /* Figure out whether to use ordered or unordered fp comparisons.
14487 Return the appropriate mode to use. */
14490 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14492 /* ??? In order to make all comparisons reversible, we do all comparisons
14493 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14494 all forms trapping and nontrapping comparisons, we can make inequality
14495 comparisons trapping again, since it results in better code when using
14496 FCOM based compares. */
14497 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14501 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14503 enum machine_mode mode = GET_MODE (op0);
14505 if (SCALAR_FLOAT_MODE_P (mode))
14507 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14508 return ix86_fp_compare_mode (code);
14513 /* Only zero flag is needed. */
14514 case EQ: /* ZF=0 */
14515 case NE: /* ZF!=0 */
14517 /* Codes needing carry flag. */
14518 case GEU: /* CF=0 */
14519 case LTU: /* CF=1 */
14520 /* Detect overflow checks. They need just the carry flag. */
14521 if (GET_CODE (op0) == PLUS
14522 && rtx_equal_p (op1, XEXP (op0, 0)))
14526 case GTU: /* CF=0 & ZF=0 */
14527 case LEU: /* CF=1 | ZF=1 */
14528 /* Detect overflow checks. They need just the carry flag. */
14529 if (GET_CODE (op0) == MINUS
14530 && rtx_equal_p (op1, XEXP (op0, 0)))
14534 /* Codes possibly doable only with sign flag when
14535 comparing against zero. */
14536 case GE: /* SF=OF or SF=0 */
14537 case LT: /* SF<>OF or SF=1 */
14538 if (op1 == const0_rtx)
14541 /* For other cases Carry flag is not required. */
14543 /* Codes doable only with sign flag when comparing
14544 against zero, but we miss jump instruction for it
14545 so we need to use relational tests against overflow
14546 that thus needs to be zero. */
14547 case GT: /* ZF=0 & SF=OF */
14548 case LE: /* ZF=1 | SF<>OF */
14549 if (op1 == const0_rtx)
14553 /* strcmp pattern do (use flags) and combine may ask us for proper
14558 gcc_unreachable ();
14562 /* Return the fixed registers used for condition codes. */
14565 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14572 /* If two condition code modes are compatible, return a condition code
14573 mode which is compatible with both. Otherwise, return
14576 static enum machine_mode
14577 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14582 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14585 if ((m1 == CCGCmode && m2 == CCGOCmode)
14586 || (m1 == CCGOCmode && m2 == CCGCmode))
14592 gcc_unreachable ();
14622 /* These are only compatible with themselves, which we already
14629 /* Return a comparison we can do and that it is equivalent to
14630 swap_condition (code) apart possibly from orderedness.
14631 But, never change orderedness if TARGET_IEEE_FP, returning
14632 UNKNOWN in that case if necessary. */
14634 static enum rtx_code
14635 ix86_fp_swap_condition (enum rtx_code code)
14639 case GT: /* GTU - CF=0 & ZF=0 */
14640 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14641 case GE: /* GEU - CF=0 */
14642 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14643 case UNLT: /* LTU - CF=1 */
14644 return TARGET_IEEE_FP ? UNKNOWN : GT;
14645 case UNLE: /* LEU - CF=1 | ZF=1 */
14646 return TARGET_IEEE_FP ? UNKNOWN : GE;
14648 return swap_condition (code);
14652 /* Return cost of comparison CODE using the best strategy for performance.
14653 All following functions do use number of instructions as a cost metrics.
14654 In future this should be tweaked to compute bytes for optimize_size and
14655 take into account performance of various instructions on various CPUs. */
14658 ix86_fp_comparison_cost (enum rtx_code code)
14662 /* The cost of code using bit-twiddling on %ah. */
14679 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14683 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14686 gcc_unreachable ();
14689 switch (ix86_fp_comparison_strategy (code))
14691 case IX86_FPCMP_COMI:
14692 return arith_cost > 4 ? 3 : 2;
14693 case IX86_FPCMP_SAHF:
14694 return arith_cost > 4 ? 4 : 3;
14700 /* Return strategy to use for floating-point. We assume that fcomi is always
14701 preferrable where available, since that is also true when looking at size
14702 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14704 enum ix86_fpcmp_strategy
14705 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14707 /* Do fcomi/sahf based test when profitable. */
14710 return IX86_FPCMP_COMI;
14712 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14713 return IX86_FPCMP_SAHF;
14715 return IX86_FPCMP_ARITH;
14718 /* Swap, force into registers, or otherwise massage the two operands
14719 to a fp comparison. The operands are updated in place; the new
14720 comparison code is returned. */
14722 static enum rtx_code
14723 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14725 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14726 rtx op0 = *pop0, op1 = *pop1;
14727 enum machine_mode op_mode = GET_MODE (op0);
14728 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14730 /* All of the unordered compare instructions only work on registers.
14731 The same is true of the fcomi compare instructions. The XFmode
14732 compare instructions require registers except when comparing
14733 against zero or when converting operand 1 from fixed point to
14737 && (fpcmp_mode == CCFPUmode
14738 || (op_mode == XFmode
14739 && ! (standard_80387_constant_p (op0) == 1
14740 || standard_80387_constant_p (op1) == 1)
14741 && GET_CODE (op1) != FLOAT)
14742 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14744 op0 = force_reg (op_mode, op0);
14745 op1 = force_reg (op_mode, op1);
14749 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14750 things around if they appear profitable, otherwise force op0
14751 into a register. */
14753 if (standard_80387_constant_p (op0) == 0
14755 && ! (standard_80387_constant_p (op1) == 0
14758 enum rtx_code new_code = ix86_fp_swap_condition (code);
14759 if (new_code != UNKNOWN)
14762 tmp = op0, op0 = op1, op1 = tmp;
14768 op0 = force_reg (op_mode, op0);
14770 if (CONSTANT_P (op1))
14772 int tmp = standard_80387_constant_p (op1);
14774 op1 = validize_mem (force_const_mem (op_mode, op1));
14778 op1 = force_reg (op_mode, op1);
14781 op1 = force_reg (op_mode, op1);
14785 /* Try to rearrange the comparison to make it cheaper. */
14786 if (ix86_fp_comparison_cost (code)
14787 > ix86_fp_comparison_cost (swap_condition (code))
14788 && (REG_P (op1) || can_create_pseudo_p ()))
14791 tmp = op0, op0 = op1, op1 = tmp;
14792 code = swap_condition (code);
14794 op0 = force_reg (op_mode, op0);
14802 /* Convert comparison codes we use to represent FP comparison to integer
14803 code that will result in proper branch. Return UNKNOWN if no such code
14807 ix86_fp_compare_code_to_integer (enum rtx_code code)
14836 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14839 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14841 enum machine_mode fpcmp_mode, intcmp_mode;
14844 fpcmp_mode = ix86_fp_compare_mode (code);
14845 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14847 /* Do fcomi/sahf based test when profitable. */
14848 switch (ix86_fp_comparison_strategy (code))
14850 case IX86_FPCMP_COMI:
14851 intcmp_mode = fpcmp_mode;
14852 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14853 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14858 case IX86_FPCMP_SAHF:
14859 intcmp_mode = fpcmp_mode;
14860 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14861 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14865 scratch = gen_reg_rtx (HImode);
14866 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14867 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14870 case IX86_FPCMP_ARITH:
14871 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14872 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14873 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14875 scratch = gen_reg_rtx (HImode);
14876 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14878 /* In the unordered case, we have to check C2 for NaN's, which
14879 doesn't happen to work out to anything nice combination-wise.
14880 So do some bit twiddling on the value we've got in AH to come
14881 up with an appropriate set of condition codes. */
14883 intcmp_mode = CCNOmode;
14888 if (code == GT || !TARGET_IEEE_FP)
14890 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14895 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14896 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14897 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14898 intcmp_mode = CCmode;
14904 if (code == LT && TARGET_IEEE_FP)
14906 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14907 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14908 intcmp_mode = CCmode;
14913 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14919 if (code == GE || !TARGET_IEEE_FP)
14921 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14926 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14927 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14933 if (code == LE && TARGET_IEEE_FP)
14935 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14936 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14937 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14938 intcmp_mode = CCmode;
14943 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14949 if (code == EQ && TARGET_IEEE_FP)
14951 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14952 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14953 intcmp_mode = CCmode;
14958 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14964 if (code == NE && TARGET_IEEE_FP)
14966 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14967 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14973 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14979 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14983 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14988 gcc_unreachable ();
14996 /* Return the test that should be put into the flags user, i.e.
14997 the bcc, scc, or cmov instruction. */
14998 return gen_rtx_fmt_ee (code, VOIDmode,
14999 gen_rtx_REG (intcmp_mode, FLAGS_REG),
15004 ix86_expand_compare (enum rtx_code code)
15007 op0 = ix86_compare_op0;
15008 op1 = ix86_compare_op1;
15010 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
15011 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
15013 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
15015 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
15016 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15019 ret = ix86_expand_int_compare (code, op0, op1);
15025 ix86_expand_branch (enum rtx_code code, rtx label)
15029 switch (GET_MODE (ix86_compare_op0))
15038 tmp = ix86_expand_compare (code);
15039 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15040 gen_rtx_LABEL_REF (VOIDmode, label),
15042 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15049 /* Expand DImode branch into multiple compare+branch. */
15051 rtx lo[2], hi[2], label2;
15052 enum rtx_code code1, code2, code3;
15053 enum machine_mode submode;
15055 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
15057 tmp = ix86_compare_op0;
15058 ix86_compare_op0 = ix86_compare_op1;
15059 ix86_compare_op1 = tmp;
15060 code = swap_condition (code);
15062 if (GET_MODE (ix86_compare_op0) == DImode)
15064 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
15065 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
15070 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
15071 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
15075 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15076 avoid two branches. This costs one extra insn, so disable when
15077 optimizing for size. */
15079 if ((code == EQ || code == NE)
15080 && (!optimize_insn_for_size_p ()
15081 || hi[1] == const0_rtx || lo[1] == const0_rtx))
15086 if (hi[1] != const0_rtx)
15087 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
15088 NULL_RTX, 0, OPTAB_WIDEN);
15091 if (lo[1] != const0_rtx)
15092 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
15093 NULL_RTX, 0, OPTAB_WIDEN);
15095 tmp = expand_binop (submode, ior_optab, xor1, xor0,
15096 NULL_RTX, 0, OPTAB_WIDEN);
15098 ix86_compare_op0 = tmp;
15099 ix86_compare_op1 = const0_rtx;
15100 ix86_expand_branch (code, label);
15104 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15105 op1 is a constant and the low word is zero, then we can just
15106 examine the high word. Similarly for low word -1 and
15107 less-or-equal-than or greater-than. */
15109 if (CONST_INT_P (hi[1]))
15112 case LT: case LTU: case GE: case GEU:
15113 if (lo[1] == const0_rtx)
15115 ix86_compare_op0 = hi[0];
15116 ix86_compare_op1 = hi[1];
15117 ix86_expand_branch (code, label);
15121 case LE: case LEU: case GT: case GTU:
15122 if (lo[1] == constm1_rtx)
15124 ix86_compare_op0 = hi[0];
15125 ix86_compare_op1 = hi[1];
15126 ix86_expand_branch (code, label);
15134 /* Otherwise, we need two or three jumps. */
15136 label2 = gen_label_rtx ();
15139 code2 = swap_condition (code);
15140 code3 = unsigned_condition (code);
15144 case LT: case GT: case LTU: case GTU:
15147 case LE: code1 = LT; code2 = GT; break;
15148 case GE: code1 = GT; code2 = LT; break;
15149 case LEU: code1 = LTU; code2 = GTU; break;
15150 case GEU: code1 = GTU; code2 = LTU; break;
15152 case EQ: code1 = UNKNOWN; code2 = NE; break;
15153 case NE: code2 = UNKNOWN; break;
15156 gcc_unreachable ();
15161 * if (hi(a) < hi(b)) goto true;
15162 * if (hi(a) > hi(b)) goto false;
15163 * if (lo(a) < lo(b)) goto true;
15167 ix86_compare_op0 = hi[0];
15168 ix86_compare_op1 = hi[1];
15170 if (code1 != UNKNOWN)
15171 ix86_expand_branch (code1, label);
15172 if (code2 != UNKNOWN)
15173 ix86_expand_branch (code2, label2);
15175 ix86_compare_op0 = lo[0];
15176 ix86_compare_op1 = lo[1];
15177 ix86_expand_branch (code3, label);
15179 if (code2 != UNKNOWN)
15180 emit_label (label2);
15185 /* If we have already emitted a compare insn, go straight to simple.
15186 ix86_expand_compare won't emit anything if ix86_compare_emitted
15188 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
15193 /* Split branch based on floating point condition. */
15195 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
15196 rtx target1, rtx target2, rtx tmp, rtx pushed)
15201 if (target2 != pc_rtx)
15204 code = reverse_condition_maybe_unordered (code);
15209 condition = ix86_expand_fp_compare (code, op1, op2,
15212 /* Remove pushed operand from stack. */
15214 ix86_free_from_memory (GET_MODE (pushed));
15216 i = emit_jump_insn (gen_rtx_SET
15218 gen_rtx_IF_THEN_ELSE (VOIDmode,
15219 condition, target1, target2)));
15220 if (split_branch_probability >= 0)
15221 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15225 ix86_expand_setcc (enum rtx_code code, rtx dest)
15229 gcc_assert (GET_MODE (dest) == QImode);
15231 ret = ix86_expand_compare (code);
15232 PUT_MODE (ret, QImode);
15233 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15236 /* Expand comparison setting or clearing carry flag. Return true when
15237 successful and set pop for the operation. */
15239 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15241 enum machine_mode mode =
15242 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15244 /* Do not handle DImode compares that go through special path. */
15245 if (mode == (TARGET_64BIT ? TImode : DImode))
15248 if (SCALAR_FLOAT_MODE_P (mode))
15250 rtx compare_op, compare_seq;
15252 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15254 /* Shortcut: following common codes never translate
15255 into carry flag compares. */
15256 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15257 || code == ORDERED || code == UNORDERED)
15260 /* These comparisons require zero flag; swap operands so they won't. */
15261 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15262 && !TARGET_IEEE_FP)
15267 code = swap_condition (code);
15270 /* Try to expand the comparison and verify that we end up with
15271 carry flag based comparison. This fails to be true only when
15272 we decide to expand comparison using arithmetic that is not
15273 too common scenario. */
15275 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15276 compare_seq = get_insns ();
15279 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15280 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15281 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15283 code = GET_CODE (compare_op);
15285 if (code != LTU && code != GEU)
15288 emit_insn (compare_seq);
15293 if (!INTEGRAL_MODE_P (mode))
15302 /* Convert a==0 into (unsigned)a<1. */
15305 if (op1 != const0_rtx)
15308 code = (code == EQ ? LTU : GEU);
15311 /* Convert a>b into b<a or a>=b-1. */
15314 if (CONST_INT_P (op1))
15316 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15317 /* Bail out on overflow. We still can swap operands but that
15318 would force loading of the constant into register. */
15319 if (op1 == const0_rtx
15320 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15322 code = (code == GTU ? GEU : LTU);
15329 code = (code == GTU ? LTU : GEU);
15333 /* Convert a>=0 into (unsigned)a<0x80000000. */
15336 if (mode == DImode || op1 != const0_rtx)
15338 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15339 code = (code == LT ? GEU : LTU);
15343 if (mode == DImode || op1 != constm1_rtx)
15345 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15346 code = (code == LE ? GEU : LTU);
15352 /* Swapping operands may cause constant to appear as first operand. */
15353 if (!nonimmediate_operand (op0, VOIDmode))
15355 if (!can_create_pseudo_p ())
15357 op0 = force_reg (mode, op0);
15359 ix86_compare_op0 = op0;
15360 ix86_compare_op1 = op1;
15361 *pop = ix86_expand_compare (code);
15362 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15367 ix86_expand_int_movcc (rtx operands[])
15369 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15370 rtx compare_seq, compare_op;
15371 enum machine_mode mode = GET_MODE (operands[0]);
15372 bool sign_bit_compare_p = false;;
15375 ix86_compare_op0 = XEXP (operands[1], 0);
15376 ix86_compare_op1 = XEXP (operands[1], 1);
15377 compare_op = ix86_expand_compare (code);
15378 compare_seq = get_insns ();
15381 compare_code = GET_CODE (compare_op);
15383 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15384 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15385 sign_bit_compare_p = true;
15387 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15388 HImode insns, we'd be swallowed in word prefix ops. */
15390 if ((mode != HImode || TARGET_FAST_PREFIX)
15391 && (mode != (TARGET_64BIT ? TImode : DImode))
15392 && CONST_INT_P (operands[2])
15393 && CONST_INT_P (operands[3]))
15395 rtx out = operands[0];
15396 HOST_WIDE_INT ct = INTVAL (operands[2]);
15397 HOST_WIDE_INT cf = INTVAL (operands[3]);
15398 HOST_WIDE_INT diff;
15401 /* Sign bit compares are better done using shifts than we do by using
15403 if (sign_bit_compare_p
15404 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15405 ix86_compare_op1, &compare_op))
15407 /* Detect overlap between destination and compare sources. */
15410 if (!sign_bit_compare_p)
15412 bool fpcmp = false;
15414 compare_code = GET_CODE (compare_op);
15416 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15417 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15420 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15423 /* To simplify rest of code, restrict to the GEU case. */
15424 if (compare_code == LTU)
15426 HOST_WIDE_INT tmp = ct;
15429 compare_code = reverse_condition (compare_code);
15430 code = reverse_condition (code);
15435 PUT_CODE (compare_op,
15436 reverse_condition_maybe_unordered
15437 (GET_CODE (compare_op)));
15439 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15443 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15444 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15445 tmp = gen_reg_rtx (mode);
15447 if (mode == DImode)
15448 emit_insn (gen_x86_movdicc_0_m1 (tmp, compare_op));
15450 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
15455 if (code == GT || code == GE)
15456 code = reverse_condition (code);
15459 HOST_WIDE_INT tmp = ct;
15464 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15465 ix86_compare_op1, VOIDmode, 0, -1);
15478 tmp = expand_simple_binop (mode, PLUS,
15480 copy_rtx (tmp), 1, OPTAB_DIRECT);
15491 tmp = expand_simple_binop (mode, IOR,
15493 copy_rtx (tmp), 1, OPTAB_DIRECT);
15495 else if (diff == -1 && ct)
15505 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15507 tmp = expand_simple_binop (mode, PLUS,
15508 copy_rtx (tmp), GEN_INT (cf),
15509 copy_rtx (tmp), 1, OPTAB_DIRECT);
15517 * andl cf - ct, dest
15527 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15530 tmp = expand_simple_binop (mode, AND,
15532 gen_int_mode (cf - ct, mode),
15533 copy_rtx (tmp), 1, OPTAB_DIRECT);
15535 tmp = expand_simple_binop (mode, PLUS,
15536 copy_rtx (tmp), GEN_INT (ct),
15537 copy_rtx (tmp), 1, OPTAB_DIRECT);
15540 if (!rtx_equal_p (tmp, out))
15541 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15543 return 1; /* DONE */
15548 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15551 tmp = ct, ct = cf, cf = tmp;
15554 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15556 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15558 /* We may be reversing unordered compare to normal compare, that
15559 is not valid in general (we may convert non-trapping condition
15560 to trapping one), however on i386 we currently emit all
15561 comparisons unordered. */
15562 compare_code = reverse_condition_maybe_unordered (compare_code);
15563 code = reverse_condition_maybe_unordered (code);
15567 compare_code = reverse_condition (compare_code);
15568 code = reverse_condition (code);
15572 compare_code = UNKNOWN;
15573 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15574 && CONST_INT_P (ix86_compare_op1))
15576 if (ix86_compare_op1 == const0_rtx
15577 && (code == LT || code == GE))
15578 compare_code = code;
15579 else if (ix86_compare_op1 == constm1_rtx)
15583 else if (code == GT)
15588 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15589 if (compare_code != UNKNOWN
15590 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15591 && (cf == -1 || ct == -1))
15593 /* If lea code below could be used, only optimize
15594 if it results in a 2 insn sequence. */
15596 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15597 || diff == 3 || diff == 5 || diff == 9)
15598 || (compare_code == LT && ct == -1)
15599 || (compare_code == GE && cf == -1))
15602 * notl op1 (if necessary)
15610 code = reverse_condition (code);
15613 out = emit_store_flag (out, code, ix86_compare_op0,
15614 ix86_compare_op1, VOIDmode, 0, -1);
15616 out = expand_simple_binop (mode, IOR,
15618 out, 1, OPTAB_DIRECT);
15619 if (out != operands[0])
15620 emit_move_insn (operands[0], out);
15622 return 1; /* DONE */
15627 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15628 || diff == 3 || diff == 5 || diff == 9)
15629 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15631 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15637 * lea cf(dest*(ct-cf)),dest
15641 * This also catches the degenerate setcc-only case.
15647 out = emit_store_flag (out, code, ix86_compare_op0,
15648 ix86_compare_op1, VOIDmode, 0, 1);
15651 /* On x86_64 the lea instruction operates on Pmode, so we need
15652 to get arithmetics done in proper mode to match. */
15654 tmp = copy_rtx (out);
15658 out1 = copy_rtx (out);
15659 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15663 tmp = gen_rtx_PLUS (mode, tmp, out1);
15669 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15672 if (!rtx_equal_p (tmp, out))
15675 out = force_operand (tmp, copy_rtx (out));
15677 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15679 if (!rtx_equal_p (out, operands[0]))
15680 emit_move_insn (operands[0], copy_rtx (out));
15682 return 1; /* DONE */
15686 * General case: Jumpful:
15687 * xorl dest,dest cmpl op1, op2
15688 * cmpl op1, op2 movl ct, dest
15689 * setcc dest jcc 1f
15690 * decl dest movl cf, dest
15691 * andl (cf-ct),dest 1:
15694 * Size 20. Size 14.
15696 * This is reasonably steep, but branch mispredict costs are
15697 * high on modern cpus, so consider failing only if optimizing
15701 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15702 && BRANCH_COST (optimize_insn_for_speed_p (),
15707 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15712 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15714 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15716 /* We may be reversing unordered compare to normal compare,
15717 that is not valid in general (we may convert non-trapping
15718 condition to trapping one), however on i386 we currently
15719 emit all comparisons unordered. */
15720 code = reverse_condition_maybe_unordered (code);
15724 code = reverse_condition (code);
15725 if (compare_code != UNKNOWN)
15726 compare_code = reverse_condition (compare_code);
15730 if (compare_code != UNKNOWN)
15732 /* notl op1 (if needed)
15737 For x < 0 (resp. x <= -1) there will be no notl,
15738 so if possible swap the constants to get rid of the
15740 True/false will be -1/0 while code below (store flag
15741 followed by decrement) is 0/-1, so the constants need
15742 to be exchanged once more. */
15744 if (compare_code == GE || !cf)
15746 code = reverse_condition (code);
15751 HOST_WIDE_INT tmp = cf;
15756 out = emit_store_flag (out, code, ix86_compare_op0,
15757 ix86_compare_op1, VOIDmode, 0, -1);
15761 out = emit_store_flag (out, code, ix86_compare_op0,
15762 ix86_compare_op1, VOIDmode, 0, 1);
15764 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15765 copy_rtx (out), 1, OPTAB_DIRECT);
15768 out = expand_simple_binop (mode, AND, copy_rtx (out),
15769 gen_int_mode (cf - ct, mode),
15770 copy_rtx (out), 1, OPTAB_DIRECT);
15772 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15773 copy_rtx (out), 1, OPTAB_DIRECT);
15774 if (!rtx_equal_p (out, operands[0]))
15775 emit_move_insn (operands[0], copy_rtx (out));
15777 return 1; /* DONE */
15781 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15783 /* Try a few things more with specific constants and a variable. */
15786 rtx var, orig_out, out, tmp;
15788 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15789 return 0; /* FAIL */
15791 /* If one of the two operands is an interesting constant, load a
15792 constant with the above and mask it in with a logical operation. */
15794 if (CONST_INT_P (operands[2]))
15797 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15798 operands[3] = constm1_rtx, op = and_optab;
15799 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15800 operands[3] = const0_rtx, op = ior_optab;
15802 return 0; /* FAIL */
15804 else if (CONST_INT_P (operands[3]))
15807 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15808 operands[2] = constm1_rtx, op = and_optab;
15809 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15810 operands[2] = const0_rtx, op = ior_optab;
15812 return 0; /* FAIL */
15815 return 0; /* FAIL */
15817 orig_out = operands[0];
15818 tmp = gen_reg_rtx (mode);
15821 /* Recurse to get the constant loaded. */
15822 if (ix86_expand_int_movcc (operands) == 0)
15823 return 0; /* FAIL */
15825 /* Mask in the interesting variable. */
15826 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15828 if (!rtx_equal_p (out, orig_out))
15829 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15831 return 1; /* DONE */
15835 * For comparison with above,
15845 if (! nonimmediate_operand (operands[2], mode))
15846 operands[2] = force_reg (mode, operands[2]);
15847 if (! nonimmediate_operand (operands[3], mode))
15848 operands[3] = force_reg (mode, operands[3]);
15850 if (! register_operand (operands[2], VOIDmode)
15852 || ! register_operand (operands[3], VOIDmode)))
15853 operands[2] = force_reg (mode, operands[2]);
15856 && ! register_operand (operands[3], VOIDmode))
15857 operands[3] = force_reg (mode, operands[3]);
15859 emit_insn (compare_seq);
15860 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15861 gen_rtx_IF_THEN_ELSE (mode,
15862 compare_op, operands[2],
15865 return 1; /* DONE */
15868 /* Swap, force into registers, or otherwise massage the two operands
15869 to an sse comparison with a mask result. Thus we differ a bit from
15870 ix86_prepare_fp_compare_args which expects to produce a flags result.
15872 The DEST operand exists to help determine whether to commute commutative
15873 operators. The POP0/POP1 operands are updated in place. The new
15874 comparison code is returned, or UNKNOWN if not implementable. */
15876 static enum rtx_code
15877 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15878 rtx *pop0, rtx *pop1)
15886 /* We have no LTGT as an operator. We could implement it with
15887 NE & ORDERED, but this requires an extra temporary. It's
15888 not clear that it's worth it. */
15895 /* These are supported directly. */
15902 /* For commutative operators, try to canonicalize the destination
15903 operand to be first in the comparison - this helps reload to
15904 avoid extra moves. */
15905 if (!dest || !rtx_equal_p (dest, *pop1))
15913 /* These are not supported directly. Swap the comparison operands
15914 to transform into something that is supported. */
15918 code = swap_condition (code);
15922 gcc_unreachable ();
15928 /* Detect conditional moves that exactly match min/max operational
15929 semantics. Note that this is IEEE safe, as long as we don't
15930 interchange the operands.
15932 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15933 and TRUE if the operation is successful and instructions are emitted. */
15936 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15937 rtx cmp_op1, rtx if_true, rtx if_false)
15939 enum machine_mode mode;
15945 else if (code == UNGE)
15948 if_true = if_false;
15954 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15956 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15961 mode = GET_MODE (dest);
15963 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15964 but MODE may be a vector mode and thus not appropriate. */
15965 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15967 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15970 if_true = force_reg (mode, if_true);
15971 v = gen_rtvec (2, if_true, if_false);
15972 tmp = gen_rtx_UNSPEC (mode, v, u);
15976 code = is_min ? SMIN : SMAX;
15977 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15980 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15984 /* Expand an sse vector comparison. Return the register with the result. */
15987 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15988 rtx op_true, rtx op_false)
15990 enum machine_mode mode = GET_MODE (dest);
15993 cmp_op0 = force_reg (mode, cmp_op0);
15994 if (!nonimmediate_operand (cmp_op1, mode))
15995 cmp_op1 = force_reg (mode, cmp_op1);
15998 || reg_overlap_mentioned_p (dest, op_true)
15999 || reg_overlap_mentioned_p (dest, op_false))
16000 dest = gen_reg_rtx (mode);
16002 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
16003 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16008 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16009 operations. This is used for both scalar and vector conditional moves. */
16012 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
16014 enum machine_mode mode = GET_MODE (dest);
16017 if (op_false == CONST0_RTX (mode))
16019 op_true = force_reg (mode, op_true);
16020 x = gen_rtx_AND (mode, cmp, op_true);
16021 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16023 else if (op_true == CONST0_RTX (mode))
16025 op_false = force_reg (mode, op_false);
16026 x = gen_rtx_NOT (mode, cmp);
16027 x = gen_rtx_AND (mode, x, op_false);
16028 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16030 else if (TARGET_XOP)
16032 rtx pcmov = gen_rtx_SET (mode, dest,
16033 gen_rtx_IF_THEN_ELSE (mode, cmp,
16040 op_true = force_reg (mode, op_true);
16041 op_false = force_reg (mode, op_false);
16043 t2 = gen_reg_rtx (mode);
16045 t3 = gen_reg_rtx (mode);
16049 x = gen_rtx_AND (mode, op_true, cmp);
16050 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
16052 x = gen_rtx_NOT (mode, cmp);
16053 x = gen_rtx_AND (mode, x, op_false);
16054 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
16056 x = gen_rtx_IOR (mode, t3, t2);
16057 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16061 /* Expand a floating-point conditional move. Return true if successful. */
16064 ix86_expand_fp_movcc (rtx operands[])
16066 enum machine_mode mode = GET_MODE (operands[0]);
16067 enum rtx_code code = GET_CODE (operands[1]);
16068 rtx tmp, compare_op;
16070 ix86_compare_op0 = XEXP (operands[1], 0);
16071 ix86_compare_op1 = XEXP (operands[1], 1);
16072 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
16074 enum machine_mode cmode;
16076 /* Since we've no cmove for sse registers, don't force bad register
16077 allocation just to gain access to it. Deny movcc when the
16078 comparison mode doesn't match the move mode. */
16079 cmode = GET_MODE (ix86_compare_op0);
16080 if (cmode == VOIDmode)
16081 cmode = GET_MODE (ix86_compare_op1);
16085 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16087 &ix86_compare_op1);
16088 if (code == UNKNOWN)
16091 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
16092 ix86_compare_op1, operands[2],
16096 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
16097 ix86_compare_op1, operands[2], operands[3]);
16098 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
16102 /* The floating point conditional move instructions don't directly
16103 support conditions resulting from a signed integer comparison. */
16105 compare_op = ix86_expand_compare (code);
16106 if (!fcmov_comparison_operator (compare_op, VOIDmode))
16108 tmp = gen_reg_rtx (QImode);
16109 ix86_expand_setcc (code, tmp);
16111 ix86_compare_op0 = tmp;
16112 ix86_compare_op1 = const0_rtx;
16113 compare_op = ix86_expand_compare (code);
16116 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16117 gen_rtx_IF_THEN_ELSE (mode, compare_op,
16118 operands[2], operands[3])));
16123 /* Expand a floating-point vector conditional move; a vcond operation
16124 rather than a movcc operation. */
16127 ix86_expand_fp_vcond (rtx operands[])
16129 enum rtx_code code = GET_CODE (operands[3]);
16132 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16133 &operands[4], &operands[5]);
16134 if (code == UNKNOWN)
16137 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
16138 operands[5], operands[1], operands[2]))
16141 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
16142 operands[1], operands[2]);
16143 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
16147 /* Expand a signed/unsigned integral vector conditional move. */
16150 ix86_expand_int_vcond (rtx operands[])
16152 enum machine_mode mode = GET_MODE (operands[0]);
16153 enum rtx_code code = GET_CODE (operands[3]);
16154 bool negate = false;
16157 cop0 = operands[4];
16158 cop1 = operands[5];
16160 /* XOP supports all of the comparisons on all vector int types. */
16163 /* Canonicalize the comparison to EQ, GT, GTU. */
16174 code = reverse_condition (code);
16180 code = reverse_condition (code);
16186 code = swap_condition (code);
16187 x = cop0, cop0 = cop1, cop1 = x;
16191 gcc_unreachable ();
16194 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16195 if (mode == V2DImode)
16200 /* SSE4.1 supports EQ. */
16201 if (!TARGET_SSE4_1)
16207 /* SSE4.2 supports GT/GTU. */
16208 if (!TARGET_SSE4_2)
16213 gcc_unreachable ();
16217 /* Unsigned parallel compare is not supported by the hardware. Play some
16218 tricks to turn this into a signed comparison against 0. */
16221 cop0 = force_reg (mode, cop0);
16230 /* Perform a parallel modulo subtraction. */
16231 t1 = gen_reg_rtx (mode);
16232 emit_insn ((mode == V4SImode
16234 : gen_subv2di3) (t1, cop0, cop1));
16236 /* Extract the original sign bit of op0. */
16237 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16239 t2 = gen_reg_rtx (mode);
16240 emit_insn ((mode == V4SImode
16242 : gen_andv2di3) (t2, cop0, mask));
16244 /* XOR it back into the result of the subtraction. This results
16245 in the sign bit set iff we saw unsigned underflow. */
16246 x = gen_reg_rtx (mode);
16247 emit_insn ((mode == V4SImode
16249 : gen_xorv2di3) (x, t1, t2));
16257 /* Perform a parallel unsigned saturating subtraction. */
16258 x = gen_reg_rtx (mode);
16259 emit_insn (gen_rtx_SET (VOIDmode, x,
16260 gen_rtx_US_MINUS (mode, cop0, cop1)));
16267 gcc_unreachable ();
16271 cop1 = CONST0_RTX (mode);
16275 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16276 operands[1+negate], operands[2-negate]);
16278 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16279 operands[2-negate]);
16283 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16284 true if we should do zero extension, else sign extension. HIGH_P is
16285 true if we want the N/2 high elements, else the low elements. */
16288 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16290 enum machine_mode imode = GET_MODE (operands[1]);
16291 rtx (*unpack)(rtx, rtx, rtx);
16298 unpack = gen_vec_interleave_highv16qi;
16300 unpack = gen_vec_interleave_lowv16qi;
16304 unpack = gen_vec_interleave_highv8hi;
16306 unpack = gen_vec_interleave_lowv8hi;
16310 unpack = gen_vec_interleave_highv4si;
16312 unpack = gen_vec_interleave_lowv4si;
16315 gcc_unreachable ();
16318 dest = gen_lowpart (imode, operands[0]);
16321 se = force_reg (imode, CONST0_RTX (imode));
16323 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16324 operands[1], pc_rtx, pc_rtx);
16326 emit_insn (unpack (dest, operands[1], se));
16329 /* This function performs the same task as ix86_expand_sse_unpack,
16330 but with SSE4.1 instructions. */
16333 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16335 enum machine_mode imode = GET_MODE (operands[1]);
16336 rtx (*unpack)(rtx, rtx);
16343 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16345 unpack = gen_sse4_1_extendv8qiv8hi2;
16349 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16351 unpack = gen_sse4_1_extendv4hiv4si2;
16355 unpack = gen_sse4_1_zero_extendv2siv2di2;
16357 unpack = gen_sse4_1_extendv2siv2di2;
16360 gcc_unreachable ();
16363 dest = operands[0];
16366 /* Shift higher 8 bytes to lower 8 bytes. */
16367 src = gen_reg_rtx (imode);
16368 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16369 gen_lowpart (TImode, operands[1]),
16375 emit_insn (unpack (dest, src));
16378 /* Expand conditional increment or decrement using adb/sbb instructions.
16379 The default case using setcc followed by the conditional move can be
16380 done by generic code. */
16382 ix86_expand_int_addcc (rtx operands[])
16384 enum rtx_code code = GET_CODE (operands[1]);
16385 rtx (*insn)(rtx, rtx, rtx, rtx);
16387 rtx val = const0_rtx;
16388 bool fpcmp = false;
16389 enum machine_mode mode = GET_MODE (operands[0]);
16391 ix86_compare_op0 = XEXP (operands[1], 0);
16392 ix86_compare_op1 = XEXP (operands[1], 1);
16393 if (operands[3] != const1_rtx
16394 && operands[3] != constm1_rtx)
16396 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16397 ix86_compare_op1, &compare_op))
16399 code = GET_CODE (compare_op);
16401 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16402 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16405 code = ix86_fp_compare_code_to_integer (code);
16412 PUT_CODE (compare_op,
16413 reverse_condition_maybe_unordered
16414 (GET_CODE (compare_op)));
16416 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16418 PUT_MODE (compare_op, mode);
16420 /* Construct either adc or sbb insn. */
16421 if ((code == LTU) == (operands[3] == constm1_rtx))
16423 switch (GET_MODE (operands[0]))
16426 insn = gen_subqi3_carry;
16429 insn = gen_subhi3_carry;
16432 insn = gen_subsi3_carry;
16435 insn = gen_subdi3_carry;
16438 gcc_unreachable ();
16443 switch (GET_MODE (operands[0]))
16446 insn = gen_addqi3_carry;
16449 insn = gen_addhi3_carry;
16452 insn = gen_addsi3_carry;
16455 insn = gen_adddi3_carry;
16458 gcc_unreachable ();
16461 emit_insn (insn (operands[0], operands[2], val, compare_op));
16463 return 1; /* DONE */
16467 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16468 works for floating pointer parameters and nonoffsetable memories.
16469 For pushes, it returns just stack offsets; the values will be saved
16470 in the right order. Maximally three parts are generated. */
16473 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16478 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16480 size = (GET_MODE_SIZE (mode) + 4) / 8;
16482 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16483 gcc_assert (size >= 2 && size <= 4);
16485 /* Optimize constant pool reference to immediates. This is used by fp
16486 moves, that force all constants to memory to allow combining. */
16487 if (MEM_P (operand) && MEM_READONLY_P (operand))
16489 rtx tmp = maybe_get_pool_constant (operand);
16494 if (MEM_P (operand) && !offsettable_memref_p (operand))
16496 /* The only non-offsetable memories we handle are pushes. */
16497 int ok = push_operand (operand, VOIDmode);
16501 operand = copy_rtx (operand);
16502 PUT_MODE (operand, Pmode);
16503 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16507 if (GET_CODE (operand) == CONST_VECTOR)
16509 enum machine_mode imode = int_mode_for_mode (mode);
16510 /* Caution: if we looked through a constant pool memory above,
16511 the operand may actually have a different mode now. That's
16512 ok, since we want to pun this all the way back to an integer. */
16513 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16514 gcc_assert (operand != NULL);
16520 if (mode == DImode)
16521 split_di (&operand, 1, &parts[0], &parts[1]);
16526 if (REG_P (operand))
16528 gcc_assert (reload_completed);
16529 for (i = 0; i < size; i++)
16530 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16532 else if (offsettable_memref_p (operand))
16534 operand = adjust_address (operand, SImode, 0);
16535 parts[0] = operand;
16536 for (i = 1; i < size; i++)
16537 parts[i] = adjust_address (operand, SImode, 4 * i);
16539 else if (GET_CODE (operand) == CONST_DOUBLE)
16544 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16548 real_to_target (l, &r, mode);
16549 parts[3] = gen_int_mode (l[3], SImode);
16550 parts[2] = gen_int_mode (l[2], SImode);
16553 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16554 parts[2] = gen_int_mode (l[2], SImode);
16557 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16560 gcc_unreachable ();
16562 parts[1] = gen_int_mode (l[1], SImode);
16563 parts[0] = gen_int_mode (l[0], SImode);
16566 gcc_unreachable ();
16571 if (mode == TImode)
16572 split_ti (&operand, 1, &parts[0], &parts[1]);
16573 if (mode == XFmode || mode == TFmode)
16575 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16576 if (REG_P (operand))
16578 gcc_assert (reload_completed);
16579 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16580 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16582 else if (offsettable_memref_p (operand))
16584 operand = adjust_address (operand, DImode, 0);
16585 parts[0] = operand;
16586 parts[1] = adjust_address (operand, upper_mode, 8);
16588 else if (GET_CODE (operand) == CONST_DOUBLE)
16593 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16594 real_to_target (l, &r, mode);
16596 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16597 if (HOST_BITS_PER_WIDE_INT >= 64)
16600 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16601 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16604 parts[0] = immed_double_const (l[0], l[1], DImode);
16606 if (upper_mode == SImode)
16607 parts[1] = gen_int_mode (l[2], SImode);
16608 else if (HOST_BITS_PER_WIDE_INT >= 64)
16611 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16612 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16615 parts[1] = immed_double_const (l[2], l[3], DImode);
16618 gcc_unreachable ();
16625 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16626 Return false when normal moves are needed; true when all required
16627 insns have been emitted. Operands 2-4 contain the input values
16628 int the correct order; operands 5-7 contain the output values. */
16631 ix86_split_long_move (rtx operands[])
16636 int collisions = 0;
16637 enum machine_mode mode = GET_MODE (operands[0]);
16638 bool collisionparts[4];
16640 /* The DFmode expanders may ask us to move double.
16641 For 64bit target this is single move. By hiding the fact
16642 here we simplify i386.md splitters. */
16643 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16645 /* Optimize constant pool reference to immediates. This is used by
16646 fp moves, that force all constants to memory to allow combining. */
16648 if (MEM_P (operands[1])
16649 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16650 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16651 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16652 if (push_operand (operands[0], VOIDmode))
16654 operands[0] = copy_rtx (operands[0]);
16655 PUT_MODE (operands[0], Pmode);
16658 operands[0] = gen_lowpart (DImode, operands[0]);
16659 operands[1] = gen_lowpart (DImode, operands[1]);
16660 emit_move_insn (operands[0], operands[1]);
16664 /* The only non-offsettable memory we handle is push. */
16665 if (push_operand (operands[0], VOIDmode))
16668 gcc_assert (!MEM_P (operands[0])
16669 || offsettable_memref_p (operands[0]));
16671 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16672 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16674 /* When emitting push, take care for source operands on the stack. */
16675 if (push && MEM_P (operands[1])
16676 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16678 rtx src_base = XEXP (part[1][nparts - 1], 0);
16680 /* Compensate for the stack decrement by 4. */
16681 if (!TARGET_64BIT && nparts == 3
16682 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16683 src_base = plus_constant (src_base, 4);
16685 /* src_base refers to the stack pointer and is
16686 automatically decreased by emitted push. */
16687 for (i = 0; i < nparts; i++)
16688 part[1][i] = change_address (part[1][i],
16689 GET_MODE (part[1][i]), src_base);
16692 /* We need to do copy in the right order in case an address register
16693 of the source overlaps the destination. */
16694 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16698 for (i = 0; i < nparts; i++)
16701 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16702 if (collisionparts[i])
16706 /* Collision in the middle part can be handled by reordering. */
16707 if (collisions == 1 && nparts == 3 && collisionparts [1])
16709 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16710 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16712 else if (collisions == 1
16714 && (collisionparts [1] || collisionparts [2]))
16716 if (collisionparts [1])
16718 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16719 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16723 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16724 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16728 /* If there are more collisions, we can't handle it by reordering.
16729 Do an lea to the last part and use only one colliding move. */
16730 else if (collisions > 1)
16736 base = part[0][nparts - 1];
16738 /* Handle the case when the last part isn't valid for lea.
16739 Happens in 64-bit mode storing the 12-byte XFmode. */
16740 if (GET_MODE (base) != Pmode)
16741 base = gen_rtx_REG (Pmode, REGNO (base));
16743 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16744 part[1][0] = replace_equiv_address (part[1][0], base);
16745 for (i = 1; i < nparts; i++)
16747 tmp = plus_constant (base, UNITS_PER_WORD * i);
16748 part[1][i] = replace_equiv_address (part[1][i], tmp);
16759 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16760 emit_insn (gen_addsi3 (stack_pointer_rtx,
16761 stack_pointer_rtx, GEN_INT (-4)));
16762 emit_move_insn (part[0][2], part[1][2]);
16764 else if (nparts == 4)
16766 emit_move_insn (part[0][3], part[1][3]);
16767 emit_move_insn (part[0][2], part[1][2]);
16772 /* In 64bit mode we don't have 32bit push available. In case this is
16773 register, it is OK - we will just use larger counterpart. We also
16774 retype memory - these comes from attempt to avoid REX prefix on
16775 moving of second half of TFmode value. */
16776 if (GET_MODE (part[1][1]) == SImode)
16778 switch (GET_CODE (part[1][1]))
16781 part[1][1] = adjust_address (part[1][1], DImode, 0);
16785 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16789 gcc_unreachable ();
16792 if (GET_MODE (part[1][0]) == SImode)
16793 part[1][0] = part[1][1];
16796 emit_move_insn (part[0][1], part[1][1]);
16797 emit_move_insn (part[0][0], part[1][0]);
16801 /* Choose correct order to not overwrite the source before it is copied. */
16802 if ((REG_P (part[0][0])
16803 && REG_P (part[1][1])
16804 && (REGNO (part[0][0]) == REGNO (part[1][1])
16806 && REGNO (part[0][0]) == REGNO (part[1][2]))
16808 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16810 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16812 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16814 operands[2 + i] = part[0][j];
16815 operands[6 + i] = part[1][j];
16820 for (i = 0; i < nparts; i++)
16822 operands[2 + i] = part[0][i];
16823 operands[6 + i] = part[1][i];
16827 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16828 if (optimize_insn_for_size_p ())
16830 for (j = 0; j < nparts - 1; j++)
16831 if (CONST_INT_P (operands[6 + j])
16832 && operands[6 + j] != const0_rtx
16833 && REG_P (operands[2 + j]))
16834 for (i = j; i < nparts - 1; i++)
16835 if (CONST_INT_P (operands[7 + i])
16836 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16837 operands[7 + i] = operands[2 + j];
16840 for (i = 0; i < nparts; i++)
16841 emit_move_insn (operands[2 + i], operands[6 + i]);
16846 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16847 left shift by a constant, either using a single shift or
16848 a sequence of add instructions. */
16851 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16855 emit_insn ((mode == DImode
16857 : gen_adddi3) (operand, operand, operand));
16859 else if (!optimize_insn_for_size_p ()
16860 && count * ix86_cost->add <= ix86_cost->shift_const)
16863 for (i=0; i<count; i++)
16865 emit_insn ((mode == DImode
16867 : gen_adddi3) (operand, operand, operand));
16871 emit_insn ((mode == DImode
16873 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16877 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16879 rtx low[2], high[2];
16881 const int single_width = mode == DImode ? 32 : 64;
16883 if (CONST_INT_P (operands[2]))
16885 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16886 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16888 if (count >= single_width)
16890 emit_move_insn (high[0], low[1]);
16891 emit_move_insn (low[0], const0_rtx);
16893 if (count > single_width)
16894 ix86_expand_ashl_const (high[0], count - single_width, mode);
16898 if (!rtx_equal_p (operands[0], operands[1]))
16899 emit_move_insn (operands[0], operands[1]);
16900 emit_insn ((mode == DImode
16902 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16903 ix86_expand_ashl_const (low[0], count, mode);
16908 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16910 if (operands[1] == const1_rtx)
16912 /* Assuming we've chosen a QImode capable registers, then 1 << N
16913 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16914 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16916 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16918 ix86_expand_clear (low[0]);
16919 ix86_expand_clear (high[0]);
16920 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16922 d = gen_lowpart (QImode, low[0]);
16923 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16924 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16925 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16927 d = gen_lowpart (QImode, high[0]);
16928 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16929 s = gen_rtx_NE (QImode, flags, const0_rtx);
16930 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16933 /* Otherwise, we can get the same results by manually performing
16934 a bit extract operation on bit 5/6, and then performing the two
16935 shifts. The two methods of getting 0/1 into low/high are exactly
16936 the same size. Avoiding the shift in the bit extract case helps
16937 pentium4 a bit; no one else seems to care much either way. */
16942 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16943 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16945 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16946 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16948 emit_insn ((mode == DImode
16950 : gen_lshrdi3) (high[0], high[0],
16951 GEN_INT (mode == DImode ? 5 : 6)));
16952 emit_insn ((mode == DImode
16954 : gen_anddi3) (high[0], high[0], const1_rtx));
16955 emit_move_insn (low[0], high[0]);
16956 emit_insn ((mode == DImode
16958 : gen_xordi3) (low[0], low[0], const1_rtx));
16961 emit_insn ((mode == DImode
16963 : gen_ashldi3) (low[0], low[0], operands[2]));
16964 emit_insn ((mode == DImode
16966 : gen_ashldi3) (high[0], high[0], operands[2]));
16970 if (operands[1] == constm1_rtx)
16972 /* For -1 << N, we can avoid the shld instruction, because we
16973 know that we're shifting 0...31/63 ones into a -1. */
16974 emit_move_insn (low[0], constm1_rtx);
16975 if (optimize_insn_for_size_p ())
16976 emit_move_insn (high[0], low[0]);
16978 emit_move_insn (high[0], constm1_rtx);
16982 if (!rtx_equal_p (operands[0], operands[1]))
16983 emit_move_insn (operands[0], operands[1]);
16985 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16986 emit_insn ((mode == DImode
16988 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16991 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16993 if (TARGET_CMOVE && scratch)
16995 ix86_expand_clear (scratch);
16996 emit_insn ((mode == DImode
16997 ? gen_x86_shift_adj_1
16998 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
17002 emit_insn ((mode == DImode
17003 ? gen_x86_shift_adj_2
17004 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
17008 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
17010 rtx low[2], high[2];
17012 const int single_width = mode == DImode ? 32 : 64;
17014 if (CONST_INT_P (operands[2]))
17016 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17017 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17019 if (count == single_width * 2 - 1)
17021 emit_move_insn (high[0], high[1]);
17022 emit_insn ((mode == DImode
17024 : gen_ashrdi3) (high[0], high[0],
17025 GEN_INT (single_width - 1)));
17026 emit_move_insn (low[0], high[0]);
17029 else if (count >= single_width)
17031 emit_move_insn (low[0], high[1]);
17032 emit_move_insn (high[0], low[0]);
17033 emit_insn ((mode == DImode
17035 : gen_ashrdi3) (high[0], high[0],
17036 GEN_INT (single_width - 1)));
17037 if (count > single_width)
17038 emit_insn ((mode == DImode
17040 : gen_ashrdi3) (low[0], low[0],
17041 GEN_INT (count - single_width)));
17045 if (!rtx_equal_p (operands[0], operands[1]))
17046 emit_move_insn (operands[0], operands[1]);
17047 emit_insn ((mode == DImode
17049 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17050 emit_insn ((mode == DImode
17052 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
17057 if (!rtx_equal_p (operands[0], operands[1]))
17058 emit_move_insn (operands[0], operands[1]);
17060 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17062 emit_insn ((mode == DImode
17064 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17065 emit_insn ((mode == DImode
17067 : gen_ashrdi3) (high[0], high[0], operands[2]));
17069 if (TARGET_CMOVE && scratch)
17071 emit_move_insn (scratch, high[0]);
17072 emit_insn ((mode == DImode
17074 : gen_ashrdi3) (scratch, scratch,
17075 GEN_INT (single_width - 1)));
17076 emit_insn ((mode == DImode
17077 ? gen_x86_shift_adj_1
17078 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17082 emit_insn ((mode == DImode
17083 ? gen_x86_shift_adj_3
17084 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
17089 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
17091 rtx low[2], high[2];
17093 const int single_width = mode == DImode ? 32 : 64;
17095 if (CONST_INT_P (operands[2]))
17097 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17098 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17100 if (count >= single_width)
17102 emit_move_insn (low[0], high[1]);
17103 ix86_expand_clear (high[0]);
17105 if (count > single_width)
17106 emit_insn ((mode == DImode
17108 : gen_lshrdi3) (low[0], low[0],
17109 GEN_INT (count - single_width)));
17113 if (!rtx_equal_p (operands[0], operands[1]))
17114 emit_move_insn (operands[0], operands[1]);
17115 emit_insn ((mode == DImode
17117 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17118 emit_insn ((mode == DImode
17120 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
17125 if (!rtx_equal_p (operands[0], operands[1]))
17126 emit_move_insn (operands[0], operands[1]);
17128 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17130 emit_insn ((mode == DImode
17132 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17133 emit_insn ((mode == DImode
17135 : gen_lshrdi3) (high[0], high[0], operands[2]));
17137 /* Heh. By reversing the arguments, we can reuse this pattern. */
17138 if (TARGET_CMOVE && scratch)
17140 ix86_expand_clear (scratch);
17141 emit_insn ((mode == DImode
17142 ? gen_x86_shift_adj_1
17143 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17147 emit_insn ((mode == DImode
17148 ? gen_x86_shift_adj_2
17149 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
17153 /* Predict just emitted jump instruction to be taken with probability PROB. */
17155 predict_jump (int prob)
17157 rtx insn = get_last_insn ();
17158 gcc_assert (JUMP_P (insn));
17159 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
17162 /* Helper function for the string operations below. Dest VARIABLE whether
17163 it is aligned to VALUE bytes. If true, jump to the label. */
17165 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
17167 rtx label = gen_label_rtx ();
17168 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
17169 if (GET_MODE (variable) == DImode)
17170 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
17172 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
17173 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
17176 predict_jump (REG_BR_PROB_BASE * 50 / 100);
17178 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17182 /* Adjust COUNTER by the VALUE. */
17184 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
17186 if (GET_MODE (countreg) == DImode)
17187 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
17189 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
17192 /* Zero extend possibly SImode EXP to Pmode register. */
17194 ix86_zero_extend_to_Pmode (rtx exp)
17197 if (GET_MODE (exp) == VOIDmode)
17198 return force_reg (Pmode, exp);
17199 if (GET_MODE (exp) == Pmode)
17200 return copy_to_mode_reg (Pmode, exp);
17201 r = gen_reg_rtx (Pmode);
17202 emit_insn (gen_zero_extendsidi2 (r, exp));
17206 /* Divide COUNTREG by SCALE. */
17208 scale_counter (rtx countreg, int scale)
17214 if (CONST_INT_P (countreg))
17215 return GEN_INT (INTVAL (countreg) / scale);
17216 gcc_assert (REG_P (countreg));
17218 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17219 GEN_INT (exact_log2 (scale)),
17220 NULL, 1, OPTAB_DIRECT);
17224 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17225 DImode for constant loop counts. */
17227 static enum machine_mode
17228 counter_mode (rtx count_exp)
17230 if (GET_MODE (count_exp) != VOIDmode)
17231 return GET_MODE (count_exp);
17232 if (!CONST_INT_P (count_exp))
17234 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17239 /* When SRCPTR is non-NULL, output simple loop to move memory
17240 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17241 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17242 equivalent loop to set memory by VALUE (supposed to be in MODE).
17244 The size is rounded down to whole number of chunk size moved at once.
17245 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17249 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17250 rtx destptr, rtx srcptr, rtx value,
17251 rtx count, enum machine_mode mode, int unroll,
17254 rtx out_label, top_label, iter, tmp;
17255 enum machine_mode iter_mode = counter_mode (count);
17256 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17257 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17263 top_label = gen_label_rtx ();
17264 out_label = gen_label_rtx ();
17265 iter = gen_reg_rtx (iter_mode);
17267 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17268 NULL, 1, OPTAB_DIRECT);
17269 /* Those two should combine. */
17270 if (piece_size == const1_rtx)
17272 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17274 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17276 emit_move_insn (iter, const0_rtx);
17278 emit_label (top_label);
17280 tmp = convert_modes (Pmode, iter_mode, iter, true);
17281 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17282 destmem = change_address (destmem, mode, x_addr);
17286 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17287 srcmem = change_address (srcmem, mode, y_addr);
17289 /* When unrolling for chips that reorder memory reads and writes,
17290 we can save registers by using single temporary.
17291 Also using 4 temporaries is overkill in 32bit mode. */
17292 if (!TARGET_64BIT && 0)
17294 for (i = 0; i < unroll; i++)
17299 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17301 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17303 emit_move_insn (destmem, srcmem);
17309 gcc_assert (unroll <= 4);
17310 for (i = 0; i < unroll; i++)
17312 tmpreg[i] = gen_reg_rtx (mode);
17316 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17318 emit_move_insn (tmpreg[i], srcmem);
17320 for (i = 0; i < unroll; i++)
17325 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17327 emit_move_insn (destmem, tmpreg[i]);
17332 for (i = 0; i < unroll; i++)
17336 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17337 emit_move_insn (destmem, value);
17340 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17341 true, OPTAB_LIB_WIDEN);
17343 emit_move_insn (iter, tmp);
17345 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17347 if (expected_size != -1)
17349 expected_size /= GET_MODE_SIZE (mode) * unroll;
17350 if (expected_size == 0)
17352 else if (expected_size > REG_BR_PROB_BASE)
17353 predict_jump (REG_BR_PROB_BASE - 1);
17355 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17358 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17359 iter = ix86_zero_extend_to_Pmode (iter);
17360 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17361 true, OPTAB_LIB_WIDEN);
17362 if (tmp != destptr)
17363 emit_move_insn (destptr, tmp);
17366 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17367 true, OPTAB_LIB_WIDEN);
17369 emit_move_insn (srcptr, tmp);
17371 emit_label (out_label);
17374 /* Output "rep; mov" instruction.
17375 Arguments have same meaning as for previous function */
17377 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17378 rtx destptr, rtx srcptr,
17380 enum machine_mode mode)
17386 /* If the size is known, it is shorter to use rep movs. */
17387 if (mode == QImode && CONST_INT_P (count)
17388 && !(INTVAL (count) & 3))
17391 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17392 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17393 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17394 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17395 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17396 if (mode != QImode)
17398 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17399 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17400 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17401 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17402 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17403 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17407 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17408 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17410 if (CONST_INT_P (count))
17412 count = GEN_INT (INTVAL (count)
17413 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17414 destmem = shallow_copy_rtx (destmem);
17415 srcmem = shallow_copy_rtx (srcmem);
17416 set_mem_size (destmem, count);
17417 set_mem_size (srcmem, count);
17421 if (MEM_SIZE (destmem))
17422 set_mem_size (destmem, NULL_RTX);
17423 if (MEM_SIZE (srcmem))
17424 set_mem_size (srcmem, NULL_RTX);
17426 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17430 /* Output "rep; stos" instruction.
17431 Arguments have same meaning as for previous function */
17433 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17434 rtx count, enum machine_mode mode,
17440 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17441 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17442 value = force_reg (mode, gen_lowpart (mode, value));
17443 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17444 if (mode != QImode)
17446 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17447 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17448 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17451 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17452 if (orig_value == const0_rtx && CONST_INT_P (count))
17454 count = GEN_INT (INTVAL (count)
17455 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17456 destmem = shallow_copy_rtx (destmem);
17457 set_mem_size (destmem, count);
17459 else if (MEM_SIZE (destmem))
17460 set_mem_size (destmem, NULL_RTX);
17461 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17465 emit_strmov (rtx destmem, rtx srcmem,
17466 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17468 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17469 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17470 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17473 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17475 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17476 rtx destptr, rtx srcptr, rtx count, int max_size)
17479 if (CONST_INT_P (count))
17481 HOST_WIDE_INT countval = INTVAL (count);
17484 if ((countval & 0x10) && max_size > 16)
17488 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17489 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17492 gcc_unreachable ();
17495 if ((countval & 0x08) && max_size > 8)
17498 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17501 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17502 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17506 if ((countval & 0x04) && max_size > 4)
17508 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17511 if ((countval & 0x02) && max_size > 2)
17513 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17516 if ((countval & 0x01) && max_size > 1)
17518 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17525 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17526 count, 1, OPTAB_DIRECT);
17527 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17528 count, QImode, 1, 4);
17532 /* When there are stringops, we can cheaply increase dest and src pointers.
17533 Otherwise we save code size by maintaining offset (zero is readily
17534 available from preceding rep operation) and using x86 addressing modes.
17536 if (TARGET_SINGLE_STRINGOP)
17540 rtx label = ix86_expand_aligntest (count, 4, true);
17541 src = change_address (srcmem, SImode, srcptr);
17542 dest = change_address (destmem, SImode, destptr);
17543 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17544 emit_label (label);
17545 LABEL_NUSES (label) = 1;
17549 rtx label = ix86_expand_aligntest (count, 2, true);
17550 src = change_address (srcmem, HImode, srcptr);
17551 dest = change_address (destmem, HImode, destptr);
17552 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17553 emit_label (label);
17554 LABEL_NUSES (label) = 1;
17558 rtx label = ix86_expand_aligntest (count, 1, true);
17559 src = change_address (srcmem, QImode, srcptr);
17560 dest = change_address (destmem, QImode, destptr);
17561 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17562 emit_label (label);
17563 LABEL_NUSES (label) = 1;
17568 rtx offset = force_reg (Pmode, const0_rtx);
17573 rtx label = ix86_expand_aligntest (count, 4, true);
17574 src = change_address (srcmem, SImode, srcptr);
17575 dest = change_address (destmem, SImode, destptr);
17576 emit_move_insn (dest, src);
17577 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17578 true, OPTAB_LIB_WIDEN);
17580 emit_move_insn (offset, tmp);
17581 emit_label (label);
17582 LABEL_NUSES (label) = 1;
17586 rtx label = ix86_expand_aligntest (count, 2, true);
17587 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17588 src = change_address (srcmem, HImode, tmp);
17589 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17590 dest = change_address (destmem, HImode, tmp);
17591 emit_move_insn (dest, src);
17592 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17593 true, OPTAB_LIB_WIDEN);
17595 emit_move_insn (offset, tmp);
17596 emit_label (label);
17597 LABEL_NUSES (label) = 1;
17601 rtx label = ix86_expand_aligntest (count, 1, true);
17602 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17603 src = change_address (srcmem, QImode, tmp);
17604 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17605 dest = change_address (destmem, QImode, tmp);
17606 emit_move_insn (dest, src);
17607 emit_label (label);
17608 LABEL_NUSES (label) = 1;
17613 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17615 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17616 rtx count, int max_size)
17619 expand_simple_binop (counter_mode (count), AND, count,
17620 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17621 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17622 gen_lowpart (QImode, value), count, QImode,
17626 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17628 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17632 if (CONST_INT_P (count))
17634 HOST_WIDE_INT countval = INTVAL (count);
17637 if ((countval & 0x10) && max_size > 16)
17641 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17642 emit_insn (gen_strset (destptr, dest, value));
17643 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17644 emit_insn (gen_strset (destptr, dest, value));
17647 gcc_unreachable ();
17650 if ((countval & 0x08) && max_size > 8)
17654 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17655 emit_insn (gen_strset (destptr, dest, value));
17659 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17660 emit_insn (gen_strset (destptr, dest, value));
17661 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17662 emit_insn (gen_strset (destptr, dest, value));
17666 if ((countval & 0x04) && max_size > 4)
17668 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17669 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17672 if ((countval & 0x02) && max_size > 2)
17674 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17675 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17678 if ((countval & 0x01) && max_size > 1)
17680 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17681 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17688 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17693 rtx label = ix86_expand_aligntest (count, 16, true);
17696 dest = change_address (destmem, DImode, destptr);
17697 emit_insn (gen_strset (destptr, dest, value));
17698 emit_insn (gen_strset (destptr, dest, value));
17702 dest = change_address (destmem, SImode, destptr);
17703 emit_insn (gen_strset (destptr, dest, value));
17704 emit_insn (gen_strset (destptr, dest, value));
17705 emit_insn (gen_strset (destptr, dest, value));
17706 emit_insn (gen_strset (destptr, dest, value));
17708 emit_label (label);
17709 LABEL_NUSES (label) = 1;
17713 rtx label = ix86_expand_aligntest (count, 8, true);
17716 dest = change_address (destmem, DImode, destptr);
17717 emit_insn (gen_strset (destptr, dest, value));
17721 dest = change_address (destmem, SImode, destptr);
17722 emit_insn (gen_strset (destptr, dest, value));
17723 emit_insn (gen_strset (destptr, dest, value));
17725 emit_label (label);
17726 LABEL_NUSES (label) = 1;
17730 rtx label = ix86_expand_aligntest (count, 4, true);
17731 dest = change_address (destmem, SImode, destptr);
17732 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17733 emit_label (label);
17734 LABEL_NUSES (label) = 1;
17738 rtx label = ix86_expand_aligntest (count, 2, true);
17739 dest = change_address (destmem, HImode, destptr);
17740 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17741 emit_label (label);
17742 LABEL_NUSES (label) = 1;
17746 rtx label = ix86_expand_aligntest (count, 1, true);
17747 dest = change_address (destmem, QImode, destptr);
17748 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17749 emit_label (label);
17750 LABEL_NUSES (label) = 1;
17754 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17755 DESIRED_ALIGNMENT. */
17757 expand_movmem_prologue (rtx destmem, rtx srcmem,
17758 rtx destptr, rtx srcptr, rtx count,
17759 int align, int desired_alignment)
17761 if (align <= 1 && desired_alignment > 1)
17763 rtx label = ix86_expand_aligntest (destptr, 1, false);
17764 srcmem = change_address (srcmem, QImode, srcptr);
17765 destmem = change_address (destmem, QImode, destptr);
17766 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17767 ix86_adjust_counter (count, 1);
17768 emit_label (label);
17769 LABEL_NUSES (label) = 1;
17771 if (align <= 2 && desired_alignment > 2)
17773 rtx label = ix86_expand_aligntest (destptr, 2, false);
17774 srcmem = change_address (srcmem, HImode, srcptr);
17775 destmem = change_address (destmem, HImode, destptr);
17776 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17777 ix86_adjust_counter (count, 2);
17778 emit_label (label);
17779 LABEL_NUSES (label) = 1;
17781 if (align <= 4 && desired_alignment > 4)
17783 rtx label = ix86_expand_aligntest (destptr, 4, false);
17784 srcmem = change_address (srcmem, SImode, srcptr);
17785 destmem = change_address (destmem, SImode, destptr);
17786 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17787 ix86_adjust_counter (count, 4);
17788 emit_label (label);
17789 LABEL_NUSES (label) = 1;
17791 gcc_assert (desired_alignment <= 8);
17794 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17795 ALIGN_BYTES is how many bytes need to be copied. */
17797 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17798 int desired_align, int align_bytes)
17801 rtx src_size, dst_size;
17803 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17804 if (src_align_bytes >= 0)
17805 src_align_bytes = desired_align - src_align_bytes;
17806 src_size = MEM_SIZE (src);
17807 dst_size = MEM_SIZE (dst);
17808 if (align_bytes & 1)
17810 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17811 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17813 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17815 if (align_bytes & 2)
17817 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17818 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17819 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17820 set_mem_align (dst, 2 * BITS_PER_UNIT);
17821 if (src_align_bytes >= 0
17822 && (src_align_bytes & 1) == (align_bytes & 1)
17823 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17824 set_mem_align (src, 2 * BITS_PER_UNIT);
17826 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17828 if (align_bytes & 4)
17830 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17831 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17832 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17833 set_mem_align (dst, 4 * BITS_PER_UNIT);
17834 if (src_align_bytes >= 0)
17836 unsigned int src_align = 0;
17837 if ((src_align_bytes & 3) == (align_bytes & 3))
17839 else if ((src_align_bytes & 1) == (align_bytes & 1))
17841 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17842 set_mem_align (src, src_align * BITS_PER_UNIT);
17845 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17847 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17848 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17849 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17850 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17851 if (src_align_bytes >= 0)
17853 unsigned int src_align = 0;
17854 if ((src_align_bytes & 7) == (align_bytes & 7))
17856 else if ((src_align_bytes & 3) == (align_bytes & 3))
17858 else if ((src_align_bytes & 1) == (align_bytes & 1))
17860 if (src_align > (unsigned int) desired_align)
17861 src_align = desired_align;
17862 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17863 set_mem_align (src, src_align * BITS_PER_UNIT);
17866 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17868 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17873 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17874 DESIRED_ALIGNMENT. */
17876 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17877 int align, int desired_alignment)
17879 if (align <= 1 && desired_alignment > 1)
17881 rtx label = ix86_expand_aligntest (destptr, 1, false);
17882 destmem = change_address (destmem, QImode, destptr);
17883 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17884 ix86_adjust_counter (count, 1);
17885 emit_label (label);
17886 LABEL_NUSES (label) = 1;
17888 if (align <= 2 && desired_alignment > 2)
17890 rtx label = ix86_expand_aligntest (destptr, 2, false);
17891 destmem = change_address (destmem, HImode, destptr);
17892 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17893 ix86_adjust_counter (count, 2);
17894 emit_label (label);
17895 LABEL_NUSES (label) = 1;
17897 if (align <= 4 && desired_alignment > 4)
17899 rtx label = ix86_expand_aligntest (destptr, 4, false);
17900 destmem = change_address (destmem, SImode, destptr);
17901 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17902 ix86_adjust_counter (count, 4);
17903 emit_label (label);
17904 LABEL_NUSES (label) = 1;
17906 gcc_assert (desired_alignment <= 8);
17909 /* Set enough from DST to align DST known to by aligned by ALIGN to
17910 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17912 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17913 int desired_align, int align_bytes)
17916 rtx dst_size = MEM_SIZE (dst);
17917 if (align_bytes & 1)
17919 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17921 emit_insn (gen_strset (destreg, dst,
17922 gen_lowpart (QImode, value)));
17924 if (align_bytes & 2)
17926 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17927 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17928 set_mem_align (dst, 2 * BITS_PER_UNIT);
17930 emit_insn (gen_strset (destreg, dst,
17931 gen_lowpart (HImode, value)));
17933 if (align_bytes & 4)
17935 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17936 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17937 set_mem_align (dst, 4 * BITS_PER_UNIT);
17939 emit_insn (gen_strset (destreg, dst,
17940 gen_lowpart (SImode, value)));
17942 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17943 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17944 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17946 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17950 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17951 static enum stringop_alg
17952 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17953 int *dynamic_check)
17955 const struct stringop_algs * algs;
17956 bool optimize_for_speed;
17957 /* Algorithms using the rep prefix want at least edi and ecx;
17958 additionally, memset wants eax and memcpy wants esi. Don't
17959 consider such algorithms if the user has appropriated those
17960 registers for their own purposes. */
17961 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17963 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17965 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17966 || (alg != rep_prefix_1_byte \
17967 && alg != rep_prefix_4_byte \
17968 && alg != rep_prefix_8_byte))
17969 const struct processor_costs *cost;
17971 /* Even if the string operation call is cold, we still might spend a lot
17972 of time processing large blocks. */
17973 if (optimize_function_for_size_p (cfun)
17974 || (optimize_insn_for_size_p ()
17975 && expected_size != -1 && expected_size < 256))
17976 optimize_for_speed = false;
17978 optimize_for_speed = true;
17980 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17982 *dynamic_check = -1;
17984 algs = &cost->memset[TARGET_64BIT != 0];
17986 algs = &cost->memcpy[TARGET_64BIT != 0];
17987 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17988 return stringop_alg;
17989 /* rep; movq or rep; movl is the smallest variant. */
17990 else if (!optimize_for_speed)
17992 if (!count || (count & 3))
17993 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17995 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17997 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17999 else if (expected_size != -1 && expected_size < 4)
18000 return loop_1_byte;
18001 else if (expected_size != -1)
18004 enum stringop_alg alg = libcall;
18005 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18007 /* We get here if the algorithms that were not libcall-based
18008 were rep-prefix based and we are unable to use rep prefixes
18009 based on global register usage. Break out of the loop and
18010 use the heuristic below. */
18011 if (algs->size[i].max == 0)
18013 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
18015 enum stringop_alg candidate = algs->size[i].alg;
18017 if (candidate != libcall && ALG_USABLE_P (candidate))
18019 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18020 last non-libcall inline algorithm. */
18021 if (TARGET_INLINE_ALL_STRINGOPS)
18023 /* When the current size is best to be copied by a libcall,
18024 but we are still forced to inline, run the heuristic below
18025 that will pick code for medium sized blocks. */
18026 if (alg != libcall)
18030 else if (ALG_USABLE_P (candidate))
18034 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
18036 /* When asked to inline the call anyway, try to pick meaningful choice.
18037 We look for maximal size of block that is faster to copy by hand and
18038 take blocks of at most of that size guessing that average size will
18039 be roughly half of the block.
18041 If this turns out to be bad, we might simply specify the preferred
18042 choice in ix86_costs. */
18043 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18044 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
18047 enum stringop_alg alg;
18049 bool any_alg_usable_p = true;
18051 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18053 enum stringop_alg candidate = algs->size[i].alg;
18054 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
18056 if (candidate != libcall && candidate
18057 && ALG_USABLE_P (candidate))
18058 max = algs->size[i].max;
18060 /* If there aren't any usable algorithms, then recursing on
18061 smaller sizes isn't going to find anything. Just return the
18062 simple byte-at-a-time copy loop. */
18063 if (!any_alg_usable_p)
18065 /* Pick something reasonable. */
18066 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18067 *dynamic_check = 128;
18068 return loop_1_byte;
18072 alg = decide_alg (count, max / 2, memset, dynamic_check);
18073 gcc_assert (*dynamic_check == -1);
18074 gcc_assert (alg != libcall);
18075 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18076 *dynamic_check = max;
18079 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
18080 #undef ALG_USABLE_P
18083 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18084 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18086 decide_alignment (int align,
18087 enum stringop_alg alg,
18090 int desired_align = 0;
18094 gcc_unreachable ();
18096 case unrolled_loop:
18097 desired_align = GET_MODE_SIZE (Pmode);
18099 case rep_prefix_8_byte:
18102 case rep_prefix_4_byte:
18103 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18104 copying whole cacheline at once. */
18105 if (TARGET_PENTIUMPRO)
18110 case rep_prefix_1_byte:
18111 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18112 copying whole cacheline at once. */
18113 if (TARGET_PENTIUMPRO)
18127 if (desired_align < align)
18128 desired_align = align;
18129 if (expected_size != -1 && expected_size < 4)
18130 desired_align = align;
18131 return desired_align;
18134 /* Return the smallest power of 2 greater than VAL. */
18136 smallest_pow2_greater_than (int val)
18144 /* Expand string move (memcpy) operation. Use i386 string operations when
18145 profitable. expand_setmem contains similar code. The code depends upon
18146 architecture, block size and alignment, but always has the same
18149 1) Prologue guard: Conditional that jumps up to epilogues for small
18150 blocks that can be handled by epilogue alone. This is faster but
18151 also needed for correctness, since prologue assume the block is larger
18152 than the desired alignment.
18154 Optional dynamic check for size and libcall for large
18155 blocks is emitted here too, with -minline-stringops-dynamically.
18157 2) Prologue: copy first few bytes in order to get destination aligned
18158 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18159 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18160 We emit either a jump tree on power of two sized blocks, or a byte loop.
18162 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18163 with specified algorithm.
18165 4) Epilogue: code copying tail of the block that is too small to be
18166 handled by main body (or up to size guarded by prologue guard). */
18169 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
18170 rtx expected_align_exp, rtx expected_size_exp)
18176 rtx jump_around_label = NULL;
18177 HOST_WIDE_INT align = 1;
18178 unsigned HOST_WIDE_INT count = 0;
18179 HOST_WIDE_INT expected_size = -1;
18180 int size_needed = 0, epilogue_size_needed;
18181 int desired_align = 0, align_bytes = 0;
18182 enum stringop_alg alg;
18184 bool need_zero_guard = false;
18186 if (CONST_INT_P (align_exp))
18187 align = INTVAL (align_exp);
18188 /* i386 can do misaligned access on reasonably increased cost. */
18189 if (CONST_INT_P (expected_align_exp)
18190 && INTVAL (expected_align_exp) > align)
18191 align = INTVAL (expected_align_exp);
18192 /* ALIGN is the minimum of destination and source alignment, but we care here
18193 just about destination alignment. */
18194 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
18195 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
18197 if (CONST_INT_P (count_exp))
18198 count = expected_size = INTVAL (count_exp);
18199 if (CONST_INT_P (expected_size_exp) && count == 0)
18200 expected_size = INTVAL (expected_size_exp);
18202 /* Make sure we don't need to care about overflow later on. */
18203 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18206 /* Step 0: Decide on preferred algorithm, desired alignment and
18207 size of chunks to be copied by main loop. */
18209 alg = decide_alg (count, expected_size, false, &dynamic_check);
18210 desired_align = decide_alignment (align, alg, expected_size);
18212 if (!TARGET_ALIGN_STRINGOPS)
18213 align = desired_align;
18215 if (alg == libcall)
18217 gcc_assert (alg != no_stringop);
18219 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18220 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18221 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18226 gcc_unreachable ();
18228 need_zero_guard = true;
18229 size_needed = GET_MODE_SIZE (Pmode);
18231 case unrolled_loop:
18232 need_zero_guard = true;
18233 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18235 case rep_prefix_8_byte:
18238 case rep_prefix_4_byte:
18241 case rep_prefix_1_byte:
18245 need_zero_guard = true;
18250 epilogue_size_needed = size_needed;
18252 /* Step 1: Prologue guard. */
18254 /* Alignment code needs count to be in register. */
18255 if (CONST_INT_P (count_exp) && desired_align > align)
18257 if (INTVAL (count_exp) > desired_align
18258 && INTVAL (count_exp) > size_needed)
18261 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18262 if (align_bytes <= 0)
18265 align_bytes = desired_align - align_bytes;
18267 if (align_bytes == 0)
18268 count_exp = force_reg (counter_mode (count_exp), count_exp);
18270 gcc_assert (desired_align >= 1 && align >= 1);
18272 /* Ensure that alignment prologue won't copy past end of block. */
18273 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18275 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18276 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18277 Make sure it is power of 2. */
18278 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18282 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18284 /* If main algorithm works on QImode, no epilogue is needed.
18285 For small sizes just don't align anything. */
18286 if (size_needed == 1)
18287 desired_align = align;
18294 label = gen_label_rtx ();
18295 emit_cmp_and_jump_insns (count_exp,
18296 GEN_INT (epilogue_size_needed),
18297 LTU, 0, counter_mode (count_exp), 1, label);
18298 if (expected_size == -1 || expected_size < epilogue_size_needed)
18299 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18301 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18305 /* Emit code to decide on runtime whether library call or inline should be
18307 if (dynamic_check != -1)
18309 if (CONST_INT_P (count_exp))
18311 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18313 emit_block_move_via_libcall (dst, src, count_exp, false);
18314 count_exp = const0_rtx;
18320 rtx hot_label = gen_label_rtx ();
18321 jump_around_label = gen_label_rtx ();
18322 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18323 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18324 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18325 emit_block_move_via_libcall (dst, src, count_exp, false);
18326 emit_jump (jump_around_label);
18327 emit_label (hot_label);
18331 /* Step 2: Alignment prologue. */
18333 if (desired_align > align)
18335 if (align_bytes == 0)
18337 /* Except for the first move in epilogue, we no longer know
18338 constant offset in aliasing info. It don't seems to worth
18339 the pain to maintain it for the first move, so throw away
18341 src = change_address (src, BLKmode, srcreg);
18342 dst = change_address (dst, BLKmode, destreg);
18343 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18348 /* If we know how many bytes need to be stored before dst is
18349 sufficiently aligned, maintain aliasing info accurately. */
18350 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18351 desired_align, align_bytes);
18352 count_exp = plus_constant (count_exp, -align_bytes);
18353 count -= align_bytes;
18355 if (need_zero_guard
18356 && (count < (unsigned HOST_WIDE_INT) size_needed
18357 || (align_bytes == 0
18358 && count < ((unsigned HOST_WIDE_INT) size_needed
18359 + desired_align - align))))
18361 /* It is possible that we copied enough so the main loop will not
18363 gcc_assert (size_needed > 1);
18364 if (label == NULL_RTX)
18365 label = gen_label_rtx ();
18366 emit_cmp_and_jump_insns (count_exp,
18367 GEN_INT (size_needed),
18368 LTU, 0, counter_mode (count_exp), 1, label);
18369 if (expected_size == -1
18370 || expected_size < (desired_align - align) / 2 + size_needed)
18371 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18373 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18376 if (label && size_needed == 1)
18378 emit_label (label);
18379 LABEL_NUSES (label) = 1;
18381 epilogue_size_needed = 1;
18383 else if (label == NULL_RTX)
18384 epilogue_size_needed = size_needed;
18386 /* Step 3: Main loop. */
18392 gcc_unreachable ();
18394 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18395 count_exp, QImode, 1, expected_size);
18398 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18399 count_exp, Pmode, 1, expected_size);
18401 case unrolled_loop:
18402 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18403 registers for 4 temporaries anyway. */
18404 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18405 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18408 case rep_prefix_8_byte:
18409 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18412 case rep_prefix_4_byte:
18413 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18416 case rep_prefix_1_byte:
18417 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18421 /* Adjust properly the offset of src and dest memory for aliasing. */
18422 if (CONST_INT_P (count_exp))
18424 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18425 (count / size_needed) * size_needed);
18426 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18427 (count / size_needed) * size_needed);
18431 src = change_address (src, BLKmode, srcreg);
18432 dst = change_address (dst, BLKmode, destreg);
18435 /* Step 4: Epilogue to copy the remaining bytes. */
18439 /* When the main loop is done, COUNT_EXP might hold original count,
18440 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18441 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18442 bytes. Compensate if needed. */
18444 if (size_needed < epilogue_size_needed)
18447 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18448 GEN_INT (size_needed - 1), count_exp, 1,
18450 if (tmp != count_exp)
18451 emit_move_insn (count_exp, tmp);
18453 emit_label (label);
18454 LABEL_NUSES (label) = 1;
18457 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18458 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18459 epilogue_size_needed);
18460 if (jump_around_label)
18461 emit_label (jump_around_label);
18465 /* Helper function for memcpy. For QImode value 0xXY produce
18466 0xXYXYXYXY of wide specified by MODE. This is essentially
18467 a * 0x10101010, but we can do slightly better than
18468 synth_mult by unwinding the sequence by hand on CPUs with
18471 promote_duplicated_reg (enum machine_mode mode, rtx val)
18473 enum machine_mode valmode = GET_MODE (val);
18475 int nops = mode == DImode ? 3 : 2;
18477 gcc_assert (mode == SImode || mode == DImode);
18478 if (val == const0_rtx)
18479 return copy_to_mode_reg (mode, const0_rtx);
18480 if (CONST_INT_P (val))
18482 HOST_WIDE_INT v = INTVAL (val) & 255;
18486 if (mode == DImode)
18487 v |= (v << 16) << 16;
18488 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18491 if (valmode == VOIDmode)
18493 if (valmode != QImode)
18494 val = gen_lowpart (QImode, val);
18495 if (mode == QImode)
18497 if (!TARGET_PARTIAL_REG_STALL)
18499 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18500 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18501 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18502 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18504 rtx reg = convert_modes (mode, QImode, val, true);
18505 tmp = promote_duplicated_reg (mode, const1_rtx);
18506 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18511 rtx reg = convert_modes (mode, QImode, val, true);
18513 if (!TARGET_PARTIAL_REG_STALL)
18514 if (mode == SImode)
18515 emit_insn (gen_movsi_insv_1 (reg, reg));
18517 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18520 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18521 NULL, 1, OPTAB_DIRECT);
18523 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18525 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18526 NULL, 1, OPTAB_DIRECT);
18527 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18528 if (mode == SImode)
18530 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18531 NULL, 1, OPTAB_DIRECT);
18532 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18537 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18538 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18539 alignment from ALIGN to DESIRED_ALIGN. */
18541 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18546 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18547 promoted_val = promote_duplicated_reg (DImode, val);
18548 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18549 promoted_val = promote_duplicated_reg (SImode, val);
18550 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18551 promoted_val = promote_duplicated_reg (HImode, val);
18553 promoted_val = val;
18555 return promoted_val;
18558 /* Expand string clear operation (bzero). Use i386 string operations when
18559 profitable. See expand_movmem comment for explanation of individual
18560 steps performed. */
18562 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18563 rtx expected_align_exp, rtx expected_size_exp)
18568 rtx jump_around_label = NULL;
18569 HOST_WIDE_INT align = 1;
18570 unsigned HOST_WIDE_INT count = 0;
18571 HOST_WIDE_INT expected_size = -1;
18572 int size_needed = 0, epilogue_size_needed;
18573 int desired_align = 0, align_bytes = 0;
18574 enum stringop_alg alg;
18575 rtx promoted_val = NULL;
18576 bool force_loopy_epilogue = false;
18578 bool need_zero_guard = false;
18580 if (CONST_INT_P (align_exp))
18581 align = INTVAL (align_exp);
18582 /* i386 can do misaligned access on reasonably increased cost. */
18583 if (CONST_INT_P (expected_align_exp)
18584 && INTVAL (expected_align_exp) > align)
18585 align = INTVAL (expected_align_exp);
18586 if (CONST_INT_P (count_exp))
18587 count = expected_size = INTVAL (count_exp);
18588 if (CONST_INT_P (expected_size_exp) && count == 0)
18589 expected_size = INTVAL (expected_size_exp);
18591 /* Make sure we don't need to care about overflow later on. */
18592 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18595 /* Step 0: Decide on preferred algorithm, desired alignment and
18596 size of chunks to be copied by main loop. */
18598 alg = decide_alg (count, expected_size, true, &dynamic_check);
18599 desired_align = decide_alignment (align, alg, expected_size);
18601 if (!TARGET_ALIGN_STRINGOPS)
18602 align = desired_align;
18604 if (alg == libcall)
18606 gcc_assert (alg != no_stringop);
18608 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18609 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18614 gcc_unreachable ();
18616 need_zero_guard = true;
18617 size_needed = GET_MODE_SIZE (Pmode);
18619 case unrolled_loop:
18620 need_zero_guard = true;
18621 size_needed = GET_MODE_SIZE (Pmode) * 4;
18623 case rep_prefix_8_byte:
18626 case rep_prefix_4_byte:
18629 case rep_prefix_1_byte:
18633 need_zero_guard = true;
18637 epilogue_size_needed = size_needed;
18639 /* Step 1: Prologue guard. */
18641 /* Alignment code needs count to be in register. */
18642 if (CONST_INT_P (count_exp) && desired_align > align)
18644 if (INTVAL (count_exp) > desired_align
18645 && INTVAL (count_exp) > size_needed)
18648 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18649 if (align_bytes <= 0)
18652 align_bytes = desired_align - align_bytes;
18654 if (align_bytes == 0)
18656 enum machine_mode mode = SImode;
18657 if (TARGET_64BIT && (count & ~0xffffffff))
18659 count_exp = force_reg (mode, count_exp);
18662 /* Do the cheap promotion to allow better CSE across the
18663 main loop and epilogue (ie one load of the big constant in the
18664 front of all code. */
18665 if (CONST_INT_P (val_exp))
18666 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18667 desired_align, align);
18668 /* Ensure that alignment prologue won't copy past end of block. */
18669 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18671 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18672 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18673 Make sure it is power of 2. */
18674 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18676 /* To improve performance of small blocks, we jump around the VAL
18677 promoting mode. This mean that if the promoted VAL is not constant,
18678 we might not use it in the epilogue and have to use byte
18680 if (epilogue_size_needed > 2 && !promoted_val)
18681 force_loopy_epilogue = true;
18684 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18686 /* If main algorithm works on QImode, no epilogue is needed.
18687 For small sizes just don't align anything. */
18688 if (size_needed == 1)
18689 desired_align = align;
18696 label = gen_label_rtx ();
18697 emit_cmp_and_jump_insns (count_exp,
18698 GEN_INT (epilogue_size_needed),
18699 LTU, 0, counter_mode (count_exp), 1, label);
18700 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18701 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18703 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18706 if (dynamic_check != -1)
18708 rtx hot_label = gen_label_rtx ();
18709 jump_around_label = gen_label_rtx ();
18710 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18711 LEU, 0, counter_mode (count_exp), 1, hot_label);
18712 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18713 set_storage_via_libcall (dst, count_exp, val_exp, false);
18714 emit_jump (jump_around_label);
18715 emit_label (hot_label);
18718 /* Step 2: Alignment prologue. */
18720 /* Do the expensive promotion once we branched off the small blocks. */
18722 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18723 desired_align, align);
18724 gcc_assert (desired_align >= 1 && align >= 1);
18726 if (desired_align > align)
18728 if (align_bytes == 0)
18730 /* Except for the first move in epilogue, we no longer know
18731 constant offset in aliasing info. It don't seems to worth
18732 the pain to maintain it for the first move, so throw away
18734 dst = change_address (dst, BLKmode, destreg);
18735 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18740 /* If we know how many bytes need to be stored before dst is
18741 sufficiently aligned, maintain aliasing info accurately. */
18742 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18743 desired_align, align_bytes);
18744 count_exp = plus_constant (count_exp, -align_bytes);
18745 count -= align_bytes;
18747 if (need_zero_guard
18748 && (count < (unsigned HOST_WIDE_INT) size_needed
18749 || (align_bytes == 0
18750 && count < ((unsigned HOST_WIDE_INT) size_needed
18751 + desired_align - align))))
18753 /* It is possible that we copied enough so the main loop will not
18755 gcc_assert (size_needed > 1);
18756 if (label == NULL_RTX)
18757 label = gen_label_rtx ();
18758 emit_cmp_and_jump_insns (count_exp,
18759 GEN_INT (size_needed),
18760 LTU, 0, counter_mode (count_exp), 1, label);
18761 if (expected_size == -1
18762 || expected_size < (desired_align - align) / 2 + size_needed)
18763 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18765 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18768 if (label && size_needed == 1)
18770 emit_label (label);
18771 LABEL_NUSES (label) = 1;
18773 promoted_val = val_exp;
18774 epilogue_size_needed = 1;
18776 else if (label == NULL_RTX)
18777 epilogue_size_needed = size_needed;
18779 /* Step 3: Main loop. */
18785 gcc_unreachable ();
18787 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18788 count_exp, QImode, 1, expected_size);
18791 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18792 count_exp, Pmode, 1, expected_size);
18794 case unrolled_loop:
18795 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18796 count_exp, Pmode, 4, expected_size);
18798 case rep_prefix_8_byte:
18799 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18802 case rep_prefix_4_byte:
18803 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18806 case rep_prefix_1_byte:
18807 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18811 /* Adjust properly the offset of src and dest memory for aliasing. */
18812 if (CONST_INT_P (count_exp))
18813 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18814 (count / size_needed) * size_needed);
18816 dst = change_address (dst, BLKmode, destreg);
18818 /* Step 4: Epilogue to copy the remaining bytes. */
18822 /* When the main loop is done, COUNT_EXP might hold original count,
18823 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18824 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18825 bytes. Compensate if needed. */
18827 if (size_needed < epilogue_size_needed)
18830 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18831 GEN_INT (size_needed - 1), count_exp, 1,
18833 if (tmp != count_exp)
18834 emit_move_insn (count_exp, tmp);
18836 emit_label (label);
18837 LABEL_NUSES (label) = 1;
18840 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18842 if (force_loopy_epilogue)
18843 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18844 epilogue_size_needed);
18846 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18847 epilogue_size_needed);
18849 if (jump_around_label)
18850 emit_label (jump_around_label);
18854 /* Expand the appropriate insns for doing strlen if not just doing
18857 out = result, initialized with the start address
18858 align_rtx = alignment of the address.
18859 scratch = scratch register, initialized with the startaddress when
18860 not aligned, otherwise undefined
18862 This is just the body. It needs the initializations mentioned above and
18863 some address computing at the end. These things are done in i386.md. */
18866 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18870 rtx align_2_label = NULL_RTX;
18871 rtx align_3_label = NULL_RTX;
18872 rtx align_4_label = gen_label_rtx ();
18873 rtx end_0_label = gen_label_rtx ();
18875 rtx tmpreg = gen_reg_rtx (SImode);
18876 rtx scratch = gen_reg_rtx (SImode);
18880 if (CONST_INT_P (align_rtx))
18881 align = INTVAL (align_rtx);
18883 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18885 /* Is there a known alignment and is it less than 4? */
18888 rtx scratch1 = gen_reg_rtx (Pmode);
18889 emit_move_insn (scratch1, out);
18890 /* Is there a known alignment and is it not 2? */
18893 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18894 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18896 /* Leave just the 3 lower bits. */
18897 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18898 NULL_RTX, 0, OPTAB_WIDEN);
18900 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18901 Pmode, 1, align_4_label);
18902 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18903 Pmode, 1, align_2_label);
18904 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18905 Pmode, 1, align_3_label);
18909 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18910 check if is aligned to 4 - byte. */
18912 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18913 NULL_RTX, 0, OPTAB_WIDEN);
18915 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18916 Pmode, 1, align_4_label);
18919 mem = change_address (src, QImode, out);
18921 /* Now compare the bytes. */
18923 /* Compare the first n unaligned byte on a byte per byte basis. */
18924 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18925 QImode, 1, end_0_label);
18927 /* Increment the address. */
18928 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18930 /* Not needed with an alignment of 2 */
18933 emit_label (align_2_label);
18935 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18938 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18940 emit_label (align_3_label);
18943 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18946 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18949 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18950 align this loop. It gives only huge programs, but does not help to
18952 emit_label (align_4_label);
18954 mem = change_address (src, SImode, out);
18955 emit_move_insn (scratch, mem);
18956 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18958 /* This formula yields a nonzero result iff one of the bytes is zero.
18959 This saves three branches inside loop and many cycles. */
18961 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18962 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18963 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18964 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18965 gen_int_mode (0x80808080, SImode)));
18966 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18971 rtx reg = gen_reg_rtx (SImode);
18972 rtx reg2 = gen_reg_rtx (Pmode);
18973 emit_move_insn (reg, tmpreg);
18974 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18976 /* If zero is not in the first two bytes, move two bytes forward. */
18977 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18978 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18979 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18980 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18981 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18984 /* Emit lea manually to avoid clobbering of flags. */
18985 emit_insn (gen_rtx_SET (SImode, reg2,
18986 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18988 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18989 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18990 emit_insn (gen_rtx_SET (VOIDmode, out,
18991 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18998 rtx end_2_label = gen_label_rtx ();
18999 /* Is zero in the first two bytes? */
19001 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
19002 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
19003 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
19004 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
19005 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
19007 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
19008 JUMP_LABEL (tmp) = end_2_label;
19010 /* Not in the first two. Move two bytes forward. */
19011 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
19012 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
19014 emit_label (end_2_label);
19018 /* Avoid branch in fixing the byte. */
19019 tmpreg = gen_lowpart (QImode, tmpreg);
19020 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
19021 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
19022 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
19024 emit_label (end_0_label);
19027 /* Expand strlen. */
19030 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
19032 rtx addr, scratch1, scratch2, scratch3, scratch4;
19034 /* The generic case of strlen expander is long. Avoid it's
19035 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19037 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19038 && !TARGET_INLINE_ALL_STRINGOPS
19039 && !optimize_insn_for_size_p ()
19040 && (!CONST_INT_P (align) || INTVAL (align) < 4))
19043 addr = force_reg (Pmode, XEXP (src, 0));
19044 scratch1 = gen_reg_rtx (Pmode);
19046 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19047 && !optimize_insn_for_size_p ())
19049 /* Well it seems that some optimizer does not combine a call like
19050 foo(strlen(bar), strlen(bar));
19051 when the move and the subtraction is done here. It does calculate
19052 the length just once when these instructions are done inside of
19053 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19054 often used and I use one fewer register for the lifetime of
19055 output_strlen_unroll() this is better. */
19057 emit_move_insn (out, addr);
19059 ix86_expand_strlensi_unroll_1 (out, src, align);
19061 /* strlensi_unroll_1 returns the address of the zero at the end of
19062 the string, like memchr(), so compute the length by subtracting
19063 the start address. */
19064 emit_insn ((*ix86_gen_sub3) (out, out, addr));
19070 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19071 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
19074 scratch2 = gen_reg_rtx (Pmode);
19075 scratch3 = gen_reg_rtx (Pmode);
19076 scratch4 = force_reg (Pmode, constm1_rtx);
19078 emit_move_insn (scratch3, addr);
19079 eoschar = force_reg (QImode, eoschar);
19081 src = replace_equiv_address_nv (src, scratch3);
19083 /* If .md starts supporting :P, this can be done in .md. */
19084 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
19085 scratch4), UNSPEC_SCAS);
19086 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
19087 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
19088 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
19093 /* For given symbol (function) construct code to compute address of it's PLT
19094 entry in large x86-64 PIC model. */
19096 construct_plt_address (rtx symbol)
19098 rtx tmp = gen_reg_rtx (Pmode);
19099 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
19101 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
19102 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
19104 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
19105 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
19110 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
19112 rtx pop, int sibcall)
19114 rtx use = NULL, call;
19116 if (pop == const0_rtx)
19118 gcc_assert (!TARGET_64BIT || !pop);
19120 if (TARGET_MACHO && !TARGET_64BIT)
19123 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
19124 fnaddr = machopic_indirect_call_target (fnaddr);
19129 /* Static functions and indirect calls don't need the pic register. */
19130 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
19131 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19132 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
19133 use_reg (&use, pic_offset_table_rtx);
19136 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
19138 rtx al = gen_rtx_REG (QImode, AX_REG);
19139 emit_move_insn (al, callarg2);
19140 use_reg (&use, al);
19143 if (ix86_cmodel == CM_LARGE_PIC
19145 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19146 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
19147 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
19149 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
19150 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
19152 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19153 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19156 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
19158 call = gen_rtx_SET (VOIDmode, retval, call);
19161 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
19162 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
19163 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
19166 && ix86_cfun_abi () == MS_ABI
19167 && (!callarg2 || INTVAL (callarg2) != -2))
19169 /* We need to represent that SI and DI registers are clobbered
19171 static int clobbered_registers[] = {
19172 XMM6_REG, XMM7_REG, XMM8_REG,
19173 XMM9_REG, XMM10_REG, XMM11_REG,
19174 XMM12_REG, XMM13_REG, XMM14_REG,
19175 XMM15_REG, SI_REG, DI_REG
19178 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
19179 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
19180 UNSPEC_MS_TO_SYSV_CALL);
19184 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
19185 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
19188 (SSE_REGNO_P (clobbered_registers[i])
19190 clobbered_registers[i]));
19192 call = gen_rtx_PARALLEL (VOIDmode,
19193 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
19197 call = emit_call_insn (call);
19199 CALL_INSN_FUNCTION_USAGE (call) = use;
19203 /* Clear stack slot assignments remembered from previous functions.
19204 This is called from INIT_EXPANDERS once before RTL is emitted for each
19207 static struct machine_function *
19208 ix86_init_machine_status (void)
19210 struct machine_function *f;
19212 f = GGC_CNEW (struct machine_function);
19213 f->use_fast_prologue_epilogue_nregs = -1;
19214 f->tls_descriptor_call_expanded_p = 0;
19215 f->call_abi = ix86_abi;
19220 /* Return a MEM corresponding to a stack slot with mode MODE.
19221 Allocate a new slot if necessary.
19223 The RTL for a function can have several slots available: N is
19224 which slot to use. */
19227 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19229 struct stack_local_entry *s;
19231 gcc_assert (n < MAX_386_STACK_LOCALS);
19233 /* Virtual slot is valid only before vregs are instantiated. */
19234 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19236 for (s = ix86_stack_locals; s; s = s->next)
19237 if (s->mode == mode && s->n == n)
19238 return copy_rtx (s->rtl);
19240 s = (struct stack_local_entry *)
19241 ggc_alloc (sizeof (struct stack_local_entry));
19244 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19246 s->next = ix86_stack_locals;
19247 ix86_stack_locals = s;
19251 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19253 static GTY(()) rtx ix86_tls_symbol;
19255 ix86_tls_get_addr (void)
19258 if (!ix86_tls_symbol)
19260 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19261 (TARGET_ANY_GNU_TLS
19263 ? "___tls_get_addr"
19264 : "__tls_get_addr");
19267 return ix86_tls_symbol;
19270 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19272 static GTY(()) rtx ix86_tls_module_base_symbol;
19274 ix86_tls_module_base (void)
19277 if (!ix86_tls_module_base_symbol)
19279 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19280 "_TLS_MODULE_BASE_");
19281 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19282 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19285 return ix86_tls_module_base_symbol;
19288 /* Calculate the length of the memory address in the instruction
19289 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19292 memory_address_length (rtx addr)
19294 struct ix86_address parts;
19295 rtx base, index, disp;
19299 if (GET_CODE (addr) == PRE_DEC
19300 || GET_CODE (addr) == POST_INC
19301 || GET_CODE (addr) == PRE_MODIFY
19302 || GET_CODE (addr) == POST_MODIFY)
19305 ok = ix86_decompose_address (addr, &parts);
19308 if (parts.base && GET_CODE (parts.base) == SUBREG)
19309 parts.base = SUBREG_REG (parts.base);
19310 if (parts.index && GET_CODE (parts.index) == SUBREG)
19311 parts.index = SUBREG_REG (parts.index);
19314 index = parts.index;
19319 - esp as the base always wants an index,
19320 - ebp as the base always wants a displacement,
19321 - r12 as the base always wants an index,
19322 - r13 as the base always wants a displacement. */
19324 /* Register Indirect. */
19325 if (base && !index && !disp)
19327 /* esp (for its index) and ebp (for its displacement) need
19328 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19331 && (addr == arg_pointer_rtx
19332 || addr == frame_pointer_rtx
19333 || REGNO (addr) == SP_REG
19334 || REGNO (addr) == BP_REG
19335 || REGNO (addr) == R12_REG
19336 || REGNO (addr) == R13_REG))
19340 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19341 is not disp32, but disp32(%rip), so for disp32
19342 SIB byte is needed, unless print_operand_address
19343 optimizes it into disp32(%rip) or (%rip) is implied
19345 else if (disp && !base && !index)
19352 if (GET_CODE (disp) == CONST)
19353 symbol = XEXP (disp, 0);
19354 if (GET_CODE (symbol) == PLUS
19355 && CONST_INT_P (XEXP (symbol, 1)))
19356 symbol = XEXP (symbol, 0);
19358 if (GET_CODE (symbol) != LABEL_REF
19359 && (GET_CODE (symbol) != SYMBOL_REF
19360 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19361 && (GET_CODE (symbol) != UNSPEC
19362 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19363 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19370 /* Find the length of the displacement constant. */
19373 if (base && satisfies_constraint_K (disp))
19378 /* ebp always wants a displacement. Similarly r13. */
19379 else if (base && REG_P (base)
19380 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19383 /* An index requires the two-byte modrm form.... */
19385 /* ...like esp (or r12), which always wants an index. */
19386 || base == arg_pointer_rtx
19387 || base == frame_pointer_rtx
19388 || (base && REG_P (base)
19389 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19406 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19407 is set, expect that insn have 8bit immediate alternative. */
19409 ix86_attr_length_immediate_default (rtx insn, int shortform)
19413 extract_insn_cached (insn);
19414 for (i = recog_data.n_operands - 1; i >= 0; --i)
19415 if (CONSTANT_P (recog_data.operand[i]))
19417 enum attr_mode mode = get_attr_mode (insn);
19420 if (shortform && CONST_INT_P (recog_data.operand[i]))
19422 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19429 ival = trunc_int_for_mode (ival, HImode);
19432 ival = trunc_int_for_mode (ival, SImode);
19437 if (IN_RANGE (ival, -128, 127))
19454 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19459 fatal_insn ("unknown insn mode", insn);
19464 /* Compute default value for "length_address" attribute. */
19466 ix86_attr_length_address_default (rtx insn)
19470 if (get_attr_type (insn) == TYPE_LEA)
19472 rtx set = PATTERN (insn), addr;
19474 if (GET_CODE (set) == PARALLEL)
19475 set = XVECEXP (set, 0, 0);
19477 gcc_assert (GET_CODE (set) == SET);
19479 addr = SET_SRC (set);
19480 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19482 if (GET_CODE (addr) == ZERO_EXTEND)
19483 addr = XEXP (addr, 0);
19484 if (GET_CODE (addr) == SUBREG)
19485 addr = SUBREG_REG (addr);
19488 return memory_address_length (addr);
19491 extract_insn_cached (insn);
19492 for (i = recog_data.n_operands - 1; i >= 0; --i)
19493 if (MEM_P (recog_data.operand[i]))
19495 constrain_operands_cached (reload_completed);
19496 if (which_alternative != -1)
19498 const char *constraints = recog_data.constraints[i];
19499 int alt = which_alternative;
19501 while (*constraints == '=' || *constraints == '+')
19504 while (*constraints++ != ',')
19506 /* Skip ignored operands. */
19507 if (*constraints == 'X')
19510 return memory_address_length (XEXP (recog_data.operand[i], 0));
19515 /* Compute default value for "length_vex" attribute. It includes
19516 2 or 3 byte VEX prefix and 1 opcode byte. */
19519 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19524 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19525 byte VEX prefix. */
19526 if (!has_0f_opcode || has_vex_w)
19529 /* We can always use 2 byte VEX prefix in 32bit. */
19533 extract_insn_cached (insn);
19535 for (i = recog_data.n_operands - 1; i >= 0; --i)
19536 if (REG_P (recog_data.operand[i]))
19538 /* REX.W bit uses 3 byte VEX prefix. */
19539 if (GET_MODE (recog_data.operand[i]) == DImode
19540 && GENERAL_REG_P (recog_data.operand[i]))
19545 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19546 if (MEM_P (recog_data.operand[i])
19547 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19554 /* Return the maximum number of instructions a cpu can issue. */
19557 ix86_issue_rate (void)
19561 case PROCESSOR_PENTIUM:
19562 case PROCESSOR_ATOM:
19566 case PROCESSOR_PENTIUMPRO:
19567 case PROCESSOR_PENTIUM4:
19568 case PROCESSOR_ATHLON:
19570 case PROCESSOR_AMDFAM10:
19571 case PROCESSOR_NOCONA:
19572 case PROCESSOR_GENERIC32:
19573 case PROCESSOR_GENERIC64:
19576 case PROCESSOR_CORE2:
19584 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19585 by DEP_INSN and nothing set by DEP_INSN. */
19588 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19592 /* Simplify the test for uninteresting insns. */
19593 if (insn_type != TYPE_SETCC
19594 && insn_type != TYPE_ICMOV
19595 && insn_type != TYPE_FCMOV
19596 && insn_type != TYPE_IBR)
19599 if ((set = single_set (dep_insn)) != 0)
19601 set = SET_DEST (set);
19604 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19605 && XVECLEN (PATTERN (dep_insn), 0) == 2
19606 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19607 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19609 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19610 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19615 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19618 /* This test is true if the dependent insn reads the flags but
19619 not any other potentially set register. */
19620 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19623 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19629 /* Return true iff USE_INSN has a memory address with operands set by
19633 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19636 extract_insn_cached (use_insn);
19637 for (i = recog_data.n_operands - 1; i >= 0; --i)
19638 if (MEM_P (recog_data.operand[i]))
19640 rtx addr = XEXP (recog_data.operand[i], 0);
19641 return modified_in_p (addr, set_insn) != 0;
19647 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19649 enum attr_type insn_type, dep_insn_type;
19650 enum attr_memory memory;
19652 int dep_insn_code_number;
19654 /* Anti and output dependencies have zero cost on all CPUs. */
19655 if (REG_NOTE_KIND (link) != 0)
19658 dep_insn_code_number = recog_memoized (dep_insn);
19660 /* If we can't recognize the insns, we can't really do anything. */
19661 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19664 insn_type = get_attr_type (insn);
19665 dep_insn_type = get_attr_type (dep_insn);
19669 case PROCESSOR_PENTIUM:
19670 /* Address Generation Interlock adds a cycle of latency. */
19671 if (insn_type == TYPE_LEA)
19673 rtx addr = PATTERN (insn);
19675 if (GET_CODE (addr) == PARALLEL)
19676 addr = XVECEXP (addr, 0, 0);
19678 gcc_assert (GET_CODE (addr) == SET);
19680 addr = SET_SRC (addr);
19681 if (modified_in_p (addr, dep_insn))
19684 else if (ix86_agi_dependent (dep_insn, insn))
19687 /* ??? Compares pair with jump/setcc. */
19688 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19691 /* Floating point stores require value to be ready one cycle earlier. */
19692 if (insn_type == TYPE_FMOV
19693 && get_attr_memory (insn) == MEMORY_STORE
19694 && !ix86_agi_dependent (dep_insn, insn))
19698 case PROCESSOR_PENTIUMPRO:
19699 memory = get_attr_memory (insn);
19701 /* INT->FP conversion is expensive. */
19702 if (get_attr_fp_int_src (dep_insn))
19705 /* There is one cycle extra latency between an FP op and a store. */
19706 if (insn_type == TYPE_FMOV
19707 && (set = single_set (dep_insn)) != NULL_RTX
19708 && (set2 = single_set (insn)) != NULL_RTX
19709 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19710 && MEM_P (SET_DEST (set2)))
19713 /* Show ability of reorder buffer to hide latency of load by executing
19714 in parallel with previous instruction in case
19715 previous instruction is not needed to compute the address. */
19716 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19717 && !ix86_agi_dependent (dep_insn, insn))
19719 /* Claim moves to take one cycle, as core can issue one load
19720 at time and the next load can start cycle later. */
19721 if (dep_insn_type == TYPE_IMOV
19722 || dep_insn_type == TYPE_FMOV)
19730 memory = get_attr_memory (insn);
19732 /* The esp dependency is resolved before the instruction is really
19734 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19735 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19738 /* INT->FP conversion is expensive. */
19739 if (get_attr_fp_int_src (dep_insn))
19742 /* Show ability of reorder buffer to hide latency of load by executing
19743 in parallel with previous instruction in case
19744 previous instruction is not needed to compute the address. */
19745 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19746 && !ix86_agi_dependent (dep_insn, insn))
19748 /* Claim moves to take one cycle, as core can issue one load
19749 at time and the next load can start cycle later. */
19750 if (dep_insn_type == TYPE_IMOV
19751 || dep_insn_type == TYPE_FMOV)
19760 case PROCESSOR_ATHLON:
19762 case PROCESSOR_AMDFAM10:
19763 case PROCESSOR_ATOM:
19764 case PROCESSOR_GENERIC32:
19765 case PROCESSOR_GENERIC64:
19766 memory = get_attr_memory (insn);
19768 /* Show ability of reorder buffer to hide latency of load by executing
19769 in parallel with previous instruction in case
19770 previous instruction is not needed to compute the address. */
19771 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19772 && !ix86_agi_dependent (dep_insn, insn))
19774 enum attr_unit unit = get_attr_unit (insn);
19777 /* Because of the difference between the length of integer and
19778 floating unit pipeline preparation stages, the memory operands
19779 for floating point are cheaper.
19781 ??? For Athlon it the difference is most probably 2. */
19782 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19785 loadcost = TARGET_ATHLON ? 2 : 0;
19787 if (cost >= loadcost)
19800 /* How many alternative schedules to try. This should be as wide as the
19801 scheduling freedom in the DFA, but no wider. Making this value too
19802 large results extra work for the scheduler. */
19805 ia32_multipass_dfa_lookahead (void)
19809 case PROCESSOR_PENTIUM:
19812 case PROCESSOR_PENTIUMPRO:
19822 /* Compute the alignment given to a constant that is being placed in memory.
19823 EXP is the constant and ALIGN is the alignment that the object would
19825 The value of this function is used instead of that alignment to align
19829 ix86_constant_alignment (tree exp, int align)
19831 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19832 || TREE_CODE (exp) == INTEGER_CST)
19834 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19836 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19839 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19840 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19841 return BITS_PER_WORD;
19846 /* Compute the alignment for a static variable.
19847 TYPE is the data type, and ALIGN is the alignment that
19848 the object would ordinarily have. The value of this function is used
19849 instead of that alignment to align the object. */
19852 ix86_data_alignment (tree type, int align)
19854 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19856 if (AGGREGATE_TYPE_P (type)
19857 && TYPE_SIZE (type)
19858 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19859 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19860 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19861 && align < max_align)
19864 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19865 to 16byte boundary. */
19868 if (AGGREGATE_TYPE_P (type)
19869 && TYPE_SIZE (type)
19870 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19871 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19872 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19876 if (TREE_CODE (type) == ARRAY_TYPE)
19878 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19880 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19883 else if (TREE_CODE (type) == COMPLEX_TYPE)
19886 if (TYPE_MODE (type) == DCmode && align < 64)
19888 if ((TYPE_MODE (type) == XCmode
19889 || TYPE_MODE (type) == TCmode) && align < 128)
19892 else if ((TREE_CODE (type) == RECORD_TYPE
19893 || TREE_CODE (type) == UNION_TYPE
19894 || TREE_CODE (type) == QUAL_UNION_TYPE)
19895 && TYPE_FIELDS (type))
19897 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19899 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19902 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19903 || TREE_CODE (type) == INTEGER_TYPE)
19905 if (TYPE_MODE (type) == DFmode && align < 64)
19907 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19914 /* Compute the alignment for a local variable or a stack slot. EXP is
19915 the data type or decl itself, MODE is the widest mode available and
19916 ALIGN is the alignment that the object would ordinarily have. The
19917 value of this macro is used instead of that alignment to align the
19921 ix86_local_alignment (tree exp, enum machine_mode mode,
19922 unsigned int align)
19926 if (exp && DECL_P (exp))
19928 type = TREE_TYPE (exp);
19937 /* Don't do dynamic stack realignment for long long objects with
19938 -mpreferred-stack-boundary=2. */
19941 && ix86_preferred_stack_boundary < 64
19942 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19943 && (!type || !TYPE_USER_ALIGN (type))
19944 && (!decl || !DECL_USER_ALIGN (decl)))
19947 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19948 register in MODE. We will return the largest alignment of XF
19952 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19953 align = GET_MODE_ALIGNMENT (DFmode);
19957 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19958 to 16byte boundary. */
19961 if (AGGREGATE_TYPE_P (type)
19962 && TYPE_SIZE (type)
19963 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19964 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19965 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19968 if (TREE_CODE (type) == ARRAY_TYPE)
19970 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19972 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19975 else if (TREE_CODE (type) == COMPLEX_TYPE)
19977 if (TYPE_MODE (type) == DCmode && align < 64)
19979 if ((TYPE_MODE (type) == XCmode
19980 || TYPE_MODE (type) == TCmode) && align < 128)
19983 else if ((TREE_CODE (type) == RECORD_TYPE
19984 || TREE_CODE (type) == UNION_TYPE
19985 || TREE_CODE (type) == QUAL_UNION_TYPE)
19986 && TYPE_FIELDS (type))
19988 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19990 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19993 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19994 || TREE_CODE (type) == INTEGER_TYPE)
19997 if (TYPE_MODE (type) == DFmode && align < 64)
19999 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
20005 /* Compute the minimum required alignment for dynamic stack realignment
20006 purposes for a local variable, parameter or a stack slot. EXP is
20007 the data type or decl itself, MODE is its mode and ALIGN is the
20008 alignment that the object would ordinarily have. */
20011 ix86_minimum_alignment (tree exp, enum machine_mode mode,
20012 unsigned int align)
20016 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
20019 if (exp && DECL_P (exp))
20021 type = TREE_TYPE (exp);
20030 /* Don't do dynamic stack realignment for long long objects with
20031 -mpreferred-stack-boundary=2. */
20032 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
20033 && (!type || !TYPE_USER_ALIGN (type))
20034 && (!decl || !DECL_USER_ALIGN (decl)))
20040 /* Find a location for the static chain incoming to a nested function.
20041 This is a register, unless all free registers are used by arguments. */
20044 ix86_static_chain (const_tree fndecl, bool incoming_p)
20048 if (!DECL_STATIC_CHAIN (fndecl))
20053 /* We always use R10 in 64-bit mode. */
20059 /* By default in 32-bit mode we use ECX to pass the static chain. */
20062 fntype = TREE_TYPE (fndecl);
20063 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
20065 /* Fastcall functions use ecx/edx for arguments, which leaves
20066 us with EAX for the static chain. */
20069 else if (ix86_function_regparm (fntype, fndecl) == 3)
20071 /* For regparm 3, we have no free call-clobbered registers in
20072 which to store the static chain. In order to implement this,
20073 we have the trampoline push the static chain to the stack.
20074 However, we can't push a value below the return address when
20075 we call the nested function directly, so we have to use an
20076 alternate entry point. For this we use ESI, and have the
20077 alternate entry point push ESI, so that things appear the
20078 same once we're executing the nested function. */
20081 if (fndecl == current_function_decl)
20082 ix86_static_chain_on_stack = true;
20083 return gen_frame_mem (SImode,
20084 plus_constant (arg_pointer_rtx, -8));
20090 return gen_rtx_REG (Pmode, regno);
20093 /* Emit RTL insns to initialize the variable parts of a trampoline.
20094 FNDECL is the decl of the target address; M_TRAMP is a MEM for
20095 the trampoline, and CHAIN_VALUE is an RTX for the static chain
20096 to be passed to the target function. */
20099 ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
20103 fnaddr = XEXP (DECL_RTL (fndecl), 0);
20110 /* Depending on the static chain location, either load a register
20111 with a constant, or push the constant to the stack. All of the
20112 instructions are the same size. */
20113 chain = ix86_static_chain (fndecl, true);
20116 if (REGNO (chain) == CX_REG)
20118 else if (REGNO (chain) == AX_REG)
20121 gcc_unreachable ();
20126 mem = adjust_address (m_tramp, QImode, 0);
20127 emit_move_insn (mem, gen_int_mode (opcode, QImode));
20129 mem = adjust_address (m_tramp, SImode, 1);
20130 emit_move_insn (mem, chain_value);
20132 /* Compute offset from the end of the jmp to the target function.
20133 In the case in which the trampoline stores the static chain on
20134 the stack, we need to skip the first insn which pushes the
20135 (call-saved) register static chain; this push is 1 byte. */
20136 disp = expand_binop (SImode, sub_optab, fnaddr,
20137 plus_constant (XEXP (m_tramp, 0),
20138 MEM_P (chain) ? 9 : 10),
20139 NULL_RTX, 1, OPTAB_DIRECT);
20141 mem = adjust_address (m_tramp, QImode, 5);
20142 emit_move_insn (mem, gen_int_mode (0xe9, QImode));
20144 mem = adjust_address (m_tramp, SImode, 6);
20145 emit_move_insn (mem, disp);
20151 /* Load the function address to r11. Try to load address using
20152 the shorter movl instead of movabs. We may want to support
20153 movq for kernel mode, but kernel does not use trampolines at
20155 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
20157 fnaddr = copy_to_mode_reg (DImode, fnaddr);
20159 mem = adjust_address (m_tramp, HImode, offset);
20160 emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
20162 mem = adjust_address (m_tramp, SImode, offset + 2);
20163 emit_move_insn (mem, gen_lowpart (SImode, fnaddr));
20168 mem = adjust_address (m_tramp, HImode, offset);
20169 emit_move_insn (mem, gen_int_mode (0xbb49, HImode));
20171 mem = adjust_address (m_tramp, DImode, offset + 2);
20172 emit_move_insn (mem, fnaddr);
20176 /* Load static chain using movabs to r10. */
20177 mem = adjust_address (m_tramp, HImode, offset);
20178 emit_move_insn (mem, gen_int_mode (0xba49, HImode));
20180 mem = adjust_address (m_tramp, DImode, offset + 2);
20181 emit_move_insn (mem, chain_value);
20184 /* Jump to r11; the last (unused) byte is a nop, only there to
20185 pad the write out to a single 32-bit store. */
20186 mem = adjust_address (m_tramp, SImode, offset);
20187 emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
20190 gcc_assert (offset <= TRAMPOLINE_SIZE);
20193 #ifdef ENABLE_EXECUTE_STACK
20194 #ifdef CHECK_EXECUTE_STACK_ENABLED
20195 if (CHECK_EXECUTE_STACK_ENABLED)
20197 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
20198 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
20202 /* Codes for all the SSE/MMX builtins. */
20205 IX86_BUILTIN_ADDPS,
20206 IX86_BUILTIN_ADDSS,
20207 IX86_BUILTIN_DIVPS,
20208 IX86_BUILTIN_DIVSS,
20209 IX86_BUILTIN_MULPS,
20210 IX86_BUILTIN_MULSS,
20211 IX86_BUILTIN_SUBPS,
20212 IX86_BUILTIN_SUBSS,
20214 IX86_BUILTIN_CMPEQPS,
20215 IX86_BUILTIN_CMPLTPS,
20216 IX86_BUILTIN_CMPLEPS,
20217 IX86_BUILTIN_CMPGTPS,
20218 IX86_BUILTIN_CMPGEPS,
20219 IX86_BUILTIN_CMPNEQPS,
20220 IX86_BUILTIN_CMPNLTPS,
20221 IX86_BUILTIN_CMPNLEPS,
20222 IX86_BUILTIN_CMPNGTPS,
20223 IX86_BUILTIN_CMPNGEPS,
20224 IX86_BUILTIN_CMPORDPS,
20225 IX86_BUILTIN_CMPUNORDPS,
20226 IX86_BUILTIN_CMPEQSS,
20227 IX86_BUILTIN_CMPLTSS,
20228 IX86_BUILTIN_CMPLESS,
20229 IX86_BUILTIN_CMPNEQSS,
20230 IX86_BUILTIN_CMPNLTSS,
20231 IX86_BUILTIN_CMPNLESS,
20232 IX86_BUILTIN_CMPNGTSS,
20233 IX86_BUILTIN_CMPNGESS,
20234 IX86_BUILTIN_CMPORDSS,
20235 IX86_BUILTIN_CMPUNORDSS,
20237 IX86_BUILTIN_COMIEQSS,
20238 IX86_BUILTIN_COMILTSS,
20239 IX86_BUILTIN_COMILESS,
20240 IX86_BUILTIN_COMIGTSS,
20241 IX86_BUILTIN_COMIGESS,
20242 IX86_BUILTIN_COMINEQSS,
20243 IX86_BUILTIN_UCOMIEQSS,
20244 IX86_BUILTIN_UCOMILTSS,
20245 IX86_BUILTIN_UCOMILESS,
20246 IX86_BUILTIN_UCOMIGTSS,
20247 IX86_BUILTIN_UCOMIGESS,
20248 IX86_BUILTIN_UCOMINEQSS,
20250 IX86_BUILTIN_CVTPI2PS,
20251 IX86_BUILTIN_CVTPS2PI,
20252 IX86_BUILTIN_CVTSI2SS,
20253 IX86_BUILTIN_CVTSI642SS,
20254 IX86_BUILTIN_CVTSS2SI,
20255 IX86_BUILTIN_CVTSS2SI64,
20256 IX86_BUILTIN_CVTTPS2PI,
20257 IX86_BUILTIN_CVTTSS2SI,
20258 IX86_BUILTIN_CVTTSS2SI64,
20260 IX86_BUILTIN_MAXPS,
20261 IX86_BUILTIN_MAXSS,
20262 IX86_BUILTIN_MINPS,
20263 IX86_BUILTIN_MINSS,
20265 IX86_BUILTIN_LOADUPS,
20266 IX86_BUILTIN_STOREUPS,
20267 IX86_BUILTIN_MOVSS,
20269 IX86_BUILTIN_MOVHLPS,
20270 IX86_BUILTIN_MOVLHPS,
20271 IX86_BUILTIN_LOADHPS,
20272 IX86_BUILTIN_LOADLPS,
20273 IX86_BUILTIN_STOREHPS,
20274 IX86_BUILTIN_STORELPS,
20276 IX86_BUILTIN_MASKMOVQ,
20277 IX86_BUILTIN_MOVMSKPS,
20278 IX86_BUILTIN_PMOVMSKB,
20280 IX86_BUILTIN_MOVNTPS,
20281 IX86_BUILTIN_MOVNTQ,
20283 IX86_BUILTIN_LOADDQU,
20284 IX86_BUILTIN_STOREDQU,
20286 IX86_BUILTIN_PACKSSWB,
20287 IX86_BUILTIN_PACKSSDW,
20288 IX86_BUILTIN_PACKUSWB,
20290 IX86_BUILTIN_PADDB,
20291 IX86_BUILTIN_PADDW,
20292 IX86_BUILTIN_PADDD,
20293 IX86_BUILTIN_PADDQ,
20294 IX86_BUILTIN_PADDSB,
20295 IX86_BUILTIN_PADDSW,
20296 IX86_BUILTIN_PADDUSB,
20297 IX86_BUILTIN_PADDUSW,
20298 IX86_BUILTIN_PSUBB,
20299 IX86_BUILTIN_PSUBW,
20300 IX86_BUILTIN_PSUBD,
20301 IX86_BUILTIN_PSUBQ,
20302 IX86_BUILTIN_PSUBSB,
20303 IX86_BUILTIN_PSUBSW,
20304 IX86_BUILTIN_PSUBUSB,
20305 IX86_BUILTIN_PSUBUSW,
20308 IX86_BUILTIN_PANDN,
20312 IX86_BUILTIN_PAVGB,
20313 IX86_BUILTIN_PAVGW,
20315 IX86_BUILTIN_PCMPEQB,
20316 IX86_BUILTIN_PCMPEQW,
20317 IX86_BUILTIN_PCMPEQD,
20318 IX86_BUILTIN_PCMPGTB,
20319 IX86_BUILTIN_PCMPGTW,
20320 IX86_BUILTIN_PCMPGTD,
20322 IX86_BUILTIN_PMADDWD,
20324 IX86_BUILTIN_PMAXSW,
20325 IX86_BUILTIN_PMAXUB,
20326 IX86_BUILTIN_PMINSW,
20327 IX86_BUILTIN_PMINUB,
20329 IX86_BUILTIN_PMULHUW,
20330 IX86_BUILTIN_PMULHW,
20331 IX86_BUILTIN_PMULLW,
20333 IX86_BUILTIN_PSADBW,
20334 IX86_BUILTIN_PSHUFW,
20336 IX86_BUILTIN_PSLLW,
20337 IX86_BUILTIN_PSLLD,
20338 IX86_BUILTIN_PSLLQ,
20339 IX86_BUILTIN_PSRAW,
20340 IX86_BUILTIN_PSRAD,
20341 IX86_BUILTIN_PSRLW,
20342 IX86_BUILTIN_PSRLD,
20343 IX86_BUILTIN_PSRLQ,
20344 IX86_BUILTIN_PSLLWI,
20345 IX86_BUILTIN_PSLLDI,
20346 IX86_BUILTIN_PSLLQI,
20347 IX86_BUILTIN_PSRAWI,
20348 IX86_BUILTIN_PSRADI,
20349 IX86_BUILTIN_PSRLWI,
20350 IX86_BUILTIN_PSRLDI,
20351 IX86_BUILTIN_PSRLQI,
20353 IX86_BUILTIN_PUNPCKHBW,
20354 IX86_BUILTIN_PUNPCKHWD,
20355 IX86_BUILTIN_PUNPCKHDQ,
20356 IX86_BUILTIN_PUNPCKLBW,
20357 IX86_BUILTIN_PUNPCKLWD,
20358 IX86_BUILTIN_PUNPCKLDQ,
20360 IX86_BUILTIN_SHUFPS,
20362 IX86_BUILTIN_RCPPS,
20363 IX86_BUILTIN_RCPSS,
20364 IX86_BUILTIN_RSQRTPS,
20365 IX86_BUILTIN_RSQRTPS_NR,
20366 IX86_BUILTIN_RSQRTSS,
20367 IX86_BUILTIN_RSQRTF,
20368 IX86_BUILTIN_SQRTPS,
20369 IX86_BUILTIN_SQRTPS_NR,
20370 IX86_BUILTIN_SQRTSS,
20372 IX86_BUILTIN_UNPCKHPS,
20373 IX86_BUILTIN_UNPCKLPS,
20375 IX86_BUILTIN_ANDPS,
20376 IX86_BUILTIN_ANDNPS,
20378 IX86_BUILTIN_XORPS,
20381 IX86_BUILTIN_LDMXCSR,
20382 IX86_BUILTIN_STMXCSR,
20383 IX86_BUILTIN_SFENCE,
20385 /* 3DNow! Original */
20386 IX86_BUILTIN_FEMMS,
20387 IX86_BUILTIN_PAVGUSB,
20388 IX86_BUILTIN_PF2ID,
20389 IX86_BUILTIN_PFACC,
20390 IX86_BUILTIN_PFADD,
20391 IX86_BUILTIN_PFCMPEQ,
20392 IX86_BUILTIN_PFCMPGE,
20393 IX86_BUILTIN_PFCMPGT,
20394 IX86_BUILTIN_PFMAX,
20395 IX86_BUILTIN_PFMIN,
20396 IX86_BUILTIN_PFMUL,
20397 IX86_BUILTIN_PFRCP,
20398 IX86_BUILTIN_PFRCPIT1,
20399 IX86_BUILTIN_PFRCPIT2,
20400 IX86_BUILTIN_PFRSQIT1,
20401 IX86_BUILTIN_PFRSQRT,
20402 IX86_BUILTIN_PFSUB,
20403 IX86_BUILTIN_PFSUBR,
20404 IX86_BUILTIN_PI2FD,
20405 IX86_BUILTIN_PMULHRW,
20407 /* 3DNow! Athlon Extensions */
20408 IX86_BUILTIN_PF2IW,
20409 IX86_BUILTIN_PFNACC,
20410 IX86_BUILTIN_PFPNACC,
20411 IX86_BUILTIN_PI2FW,
20412 IX86_BUILTIN_PSWAPDSI,
20413 IX86_BUILTIN_PSWAPDSF,
20416 IX86_BUILTIN_ADDPD,
20417 IX86_BUILTIN_ADDSD,
20418 IX86_BUILTIN_DIVPD,
20419 IX86_BUILTIN_DIVSD,
20420 IX86_BUILTIN_MULPD,
20421 IX86_BUILTIN_MULSD,
20422 IX86_BUILTIN_SUBPD,
20423 IX86_BUILTIN_SUBSD,
20425 IX86_BUILTIN_CMPEQPD,
20426 IX86_BUILTIN_CMPLTPD,
20427 IX86_BUILTIN_CMPLEPD,
20428 IX86_BUILTIN_CMPGTPD,
20429 IX86_BUILTIN_CMPGEPD,
20430 IX86_BUILTIN_CMPNEQPD,
20431 IX86_BUILTIN_CMPNLTPD,
20432 IX86_BUILTIN_CMPNLEPD,
20433 IX86_BUILTIN_CMPNGTPD,
20434 IX86_BUILTIN_CMPNGEPD,
20435 IX86_BUILTIN_CMPORDPD,
20436 IX86_BUILTIN_CMPUNORDPD,
20437 IX86_BUILTIN_CMPEQSD,
20438 IX86_BUILTIN_CMPLTSD,
20439 IX86_BUILTIN_CMPLESD,
20440 IX86_BUILTIN_CMPNEQSD,
20441 IX86_BUILTIN_CMPNLTSD,
20442 IX86_BUILTIN_CMPNLESD,
20443 IX86_BUILTIN_CMPORDSD,
20444 IX86_BUILTIN_CMPUNORDSD,
20446 IX86_BUILTIN_COMIEQSD,
20447 IX86_BUILTIN_COMILTSD,
20448 IX86_BUILTIN_COMILESD,
20449 IX86_BUILTIN_COMIGTSD,
20450 IX86_BUILTIN_COMIGESD,
20451 IX86_BUILTIN_COMINEQSD,
20452 IX86_BUILTIN_UCOMIEQSD,
20453 IX86_BUILTIN_UCOMILTSD,
20454 IX86_BUILTIN_UCOMILESD,
20455 IX86_BUILTIN_UCOMIGTSD,
20456 IX86_BUILTIN_UCOMIGESD,
20457 IX86_BUILTIN_UCOMINEQSD,
20459 IX86_BUILTIN_MAXPD,
20460 IX86_BUILTIN_MAXSD,
20461 IX86_BUILTIN_MINPD,
20462 IX86_BUILTIN_MINSD,
20464 IX86_BUILTIN_ANDPD,
20465 IX86_BUILTIN_ANDNPD,
20467 IX86_BUILTIN_XORPD,
20469 IX86_BUILTIN_SQRTPD,
20470 IX86_BUILTIN_SQRTSD,
20472 IX86_BUILTIN_UNPCKHPD,
20473 IX86_BUILTIN_UNPCKLPD,
20475 IX86_BUILTIN_SHUFPD,
20477 IX86_BUILTIN_LOADUPD,
20478 IX86_BUILTIN_STOREUPD,
20479 IX86_BUILTIN_MOVSD,
20481 IX86_BUILTIN_LOADHPD,
20482 IX86_BUILTIN_LOADLPD,
20484 IX86_BUILTIN_CVTDQ2PD,
20485 IX86_BUILTIN_CVTDQ2PS,
20487 IX86_BUILTIN_CVTPD2DQ,
20488 IX86_BUILTIN_CVTPD2PI,
20489 IX86_BUILTIN_CVTPD2PS,
20490 IX86_BUILTIN_CVTTPD2DQ,
20491 IX86_BUILTIN_CVTTPD2PI,
20493 IX86_BUILTIN_CVTPI2PD,
20494 IX86_BUILTIN_CVTSI2SD,
20495 IX86_BUILTIN_CVTSI642SD,
20497 IX86_BUILTIN_CVTSD2SI,
20498 IX86_BUILTIN_CVTSD2SI64,
20499 IX86_BUILTIN_CVTSD2SS,
20500 IX86_BUILTIN_CVTSS2SD,
20501 IX86_BUILTIN_CVTTSD2SI,
20502 IX86_BUILTIN_CVTTSD2SI64,
20504 IX86_BUILTIN_CVTPS2DQ,
20505 IX86_BUILTIN_CVTPS2PD,
20506 IX86_BUILTIN_CVTTPS2DQ,
20508 IX86_BUILTIN_MOVNTI,
20509 IX86_BUILTIN_MOVNTPD,
20510 IX86_BUILTIN_MOVNTDQ,
20512 IX86_BUILTIN_MOVQ128,
20515 IX86_BUILTIN_MASKMOVDQU,
20516 IX86_BUILTIN_MOVMSKPD,
20517 IX86_BUILTIN_PMOVMSKB128,
20519 IX86_BUILTIN_PACKSSWB128,
20520 IX86_BUILTIN_PACKSSDW128,
20521 IX86_BUILTIN_PACKUSWB128,
20523 IX86_BUILTIN_PADDB128,
20524 IX86_BUILTIN_PADDW128,
20525 IX86_BUILTIN_PADDD128,
20526 IX86_BUILTIN_PADDQ128,
20527 IX86_BUILTIN_PADDSB128,
20528 IX86_BUILTIN_PADDSW128,
20529 IX86_BUILTIN_PADDUSB128,
20530 IX86_BUILTIN_PADDUSW128,
20531 IX86_BUILTIN_PSUBB128,
20532 IX86_BUILTIN_PSUBW128,
20533 IX86_BUILTIN_PSUBD128,
20534 IX86_BUILTIN_PSUBQ128,
20535 IX86_BUILTIN_PSUBSB128,
20536 IX86_BUILTIN_PSUBSW128,
20537 IX86_BUILTIN_PSUBUSB128,
20538 IX86_BUILTIN_PSUBUSW128,
20540 IX86_BUILTIN_PAND128,
20541 IX86_BUILTIN_PANDN128,
20542 IX86_BUILTIN_POR128,
20543 IX86_BUILTIN_PXOR128,
20545 IX86_BUILTIN_PAVGB128,
20546 IX86_BUILTIN_PAVGW128,
20548 IX86_BUILTIN_PCMPEQB128,
20549 IX86_BUILTIN_PCMPEQW128,
20550 IX86_BUILTIN_PCMPEQD128,
20551 IX86_BUILTIN_PCMPGTB128,
20552 IX86_BUILTIN_PCMPGTW128,
20553 IX86_BUILTIN_PCMPGTD128,
20555 IX86_BUILTIN_PMADDWD128,
20557 IX86_BUILTIN_PMAXSW128,
20558 IX86_BUILTIN_PMAXUB128,
20559 IX86_BUILTIN_PMINSW128,
20560 IX86_BUILTIN_PMINUB128,
20562 IX86_BUILTIN_PMULUDQ,
20563 IX86_BUILTIN_PMULUDQ128,
20564 IX86_BUILTIN_PMULHUW128,
20565 IX86_BUILTIN_PMULHW128,
20566 IX86_BUILTIN_PMULLW128,
20568 IX86_BUILTIN_PSADBW128,
20569 IX86_BUILTIN_PSHUFHW,
20570 IX86_BUILTIN_PSHUFLW,
20571 IX86_BUILTIN_PSHUFD,
20573 IX86_BUILTIN_PSLLDQI128,
20574 IX86_BUILTIN_PSLLWI128,
20575 IX86_BUILTIN_PSLLDI128,
20576 IX86_BUILTIN_PSLLQI128,
20577 IX86_BUILTIN_PSRAWI128,
20578 IX86_BUILTIN_PSRADI128,
20579 IX86_BUILTIN_PSRLDQI128,
20580 IX86_BUILTIN_PSRLWI128,
20581 IX86_BUILTIN_PSRLDI128,
20582 IX86_BUILTIN_PSRLQI128,
20584 IX86_BUILTIN_PSLLDQ128,
20585 IX86_BUILTIN_PSLLW128,
20586 IX86_BUILTIN_PSLLD128,
20587 IX86_BUILTIN_PSLLQ128,
20588 IX86_BUILTIN_PSRAW128,
20589 IX86_BUILTIN_PSRAD128,
20590 IX86_BUILTIN_PSRLW128,
20591 IX86_BUILTIN_PSRLD128,
20592 IX86_BUILTIN_PSRLQ128,
20594 IX86_BUILTIN_PUNPCKHBW128,
20595 IX86_BUILTIN_PUNPCKHWD128,
20596 IX86_BUILTIN_PUNPCKHDQ128,
20597 IX86_BUILTIN_PUNPCKHQDQ128,
20598 IX86_BUILTIN_PUNPCKLBW128,
20599 IX86_BUILTIN_PUNPCKLWD128,
20600 IX86_BUILTIN_PUNPCKLDQ128,
20601 IX86_BUILTIN_PUNPCKLQDQ128,
20603 IX86_BUILTIN_CLFLUSH,
20604 IX86_BUILTIN_MFENCE,
20605 IX86_BUILTIN_LFENCE,
20607 IX86_BUILTIN_BSRSI,
20608 IX86_BUILTIN_BSRDI,
20609 IX86_BUILTIN_RDPMC,
20610 IX86_BUILTIN_RDTSC,
20611 IX86_BUILTIN_RDTSCP,
20612 IX86_BUILTIN_ROLQI,
20613 IX86_BUILTIN_ROLHI,
20614 IX86_BUILTIN_RORQI,
20615 IX86_BUILTIN_RORHI,
20618 IX86_BUILTIN_ADDSUBPS,
20619 IX86_BUILTIN_HADDPS,
20620 IX86_BUILTIN_HSUBPS,
20621 IX86_BUILTIN_MOVSHDUP,
20622 IX86_BUILTIN_MOVSLDUP,
20623 IX86_BUILTIN_ADDSUBPD,
20624 IX86_BUILTIN_HADDPD,
20625 IX86_BUILTIN_HSUBPD,
20626 IX86_BUILTIN_LDDQU,
20628 IX86_BUILTIN_MONITOR,
20629 IX86_BUILTIN_MWAIT,
20632 IX86_BUILTIN_PHADDW,
20633 IX86_BUILTIN_PHADDD,
20634 IX86_BUILTIN_PHADDSW,
20635 IX86_BUILTIN_PHSUBW,
20636 IX86_BUILTIN_PHSUBD,
20637 IX86_BUILTIN_PHSUBSW,
20638 IX86_BUILTIN_PMADDUBSW,
20639 IX86_BUILTIN_PMULHRSW,
20640 IX86_BUILTIN_PSHUFB,
20641 IX86_BUILTIN_PSIGNB,
20642 IX86_BUILTIN_PSIGNW,
20643 IX86_BUILTIN_PSIGND,
20644 IX86_BUILTIN_PALIGNR,
20645 IX86_BUILTIN_PABSB,
20646 IX86_BUILTIN_PABSW,
20647 IX86_BUILTIN_PABSD,
20649 IX86_BUILTIN_PHADDW128,
20650 IX86_BUILTIN_PHADDD128,
20651 IX86_BUILTIN_PHADDSW128,
20652 IX86_BUILTIN_PHSUBW128,
20653 IX86_BUILTIN_PHSUBD128,
20654 IX86_BUILTIN_PHSUBSW128,
20655 IX86_BUILTIN_PMADDUBSW128,
20656 IX86_BUILTIN_PMULHRSW128,
20657 IX86_BUILTIN_PSHUFB128,
20658 IX86_BUILTIN_PSIGNB128,
20659 IX86_BUILTIN_PSIGNW128,
20660 IX86_BUILTIN_PSIGND128,
20661 IX86_BUILTIN_PALIGNR128,
20662 IX86_BUILTIN_PABSB128,
20663 IX86_BUILTIN_PABSW128,
20664 IX86_BUILTIN_PABSD128,
20666 /* AMDFAM10 - SSE4A New Instructions. */
20667 IX86_BUILTIN_MOVNTSD,
20668 IX86_BUILTIN_MOVNTSS,
20669 IX86_BUILTIN_EXTRQI,
20670 IX86_BUILTIN_EXTRQ,
20671 IX86_BUILTIN_INSERTQI,
20672 IX86_BUILTIN_INSERTQ,
20675 IX86_BUILTIN_BLENDPD,
20676 IX86_BUILTIN_BLENDPS,
20677 IX86_BUILTIN_BLENDVPD,
20678 IX86_BUILTIN_BLENDVPS,
20679 IX86_BUILTIN_PBLENDVB128,
20680 IX86_BUILTIN_PBLENDW128,
20685 IX86_BUILTIN_INSERTPS128,
20687 IX86_BUILTIN_MOVNTDQA,
20688 IX86_BUILTIN_MPSADBW128,
20689 IX86_BUILTIN_PACKUSDW128,
20690 IX86_BUILTIN_PCMPEQQ,
20691 IX86_BUILTIN_PHMINPOSUW128,
20693 IX86_BUILTIN_PMAXSB128,
20694 IX86_BUILTIN_PMAXSD128,
20695 IX86_BUILTIN_PMAXUD128,
20696 IX86_BUILTIN_PMAXUW128,
20698 IX86_BUILTIN_PMINSB128,
20699 IX86_BUILTIN_PMINSD128,
20700 IX86_BUILTIN_PMINUD128,
20701 IX86_BUILTIN_PMINUW128,
20703 IX86_BUILTIN_PMOVSXBW128,
20704 IX86_BUILTIN_PMOVSXBD128,
20705 IX86_BUILTIN_PMOVSXBQ128,
20706 IX86_BUILTIN_PMOVSXWD128,
20707 IX86_BUILTIN_PMOVSXWQ128,
20708 IX86_BUILTIN_PMOVSXDQ128,
20710 IX86_BUILTIN_PMOVZXBW128,
20711 IX86_BUILTIN_PMOVZXBD128,
20712 IX86_BUILTIN_PMOVZXBQ128,
20713 IX86_BUILTIN_PMOVZXWD128,
20714 IX86_BUILTIN_PMOVZXWQ128,
20715 IX86_BUILTIN_PMOVZXDQ128,
20717 IX86_BUILTIN_PMULDQ128,
20718 IX86_BUILTIN_PMULLD128,
20720 IX86_BUILTIN_ROUNDPD,
20721 IX86_BUILTIN_ROUNDPS,
20722 IX86_BUILTIN_ROUNDSD,
20723 IX86_BUILTIN_ROUNDSS,
20725 IX86_BUILTIN_PTESTZ,
20726 IX86_BUILTIN_PTESTC,
20727 IX86_BUILTIN_PTESTNZC,
20729 IX86_BUILTIN_VEC_INIT_V2SI,
20730 IX86_BUILTIN_VEC_INIT_V4HI,
20731 IX86_BUILTIN_VEC_INIT_V8QI,
20732 IX86_BUILTIN_VEC_EXT_V2DF,
20733 IX86_BUILTIN_VEC_EXT_V2DI,
20734 IX86_BUILTIN_VEC_EXT_V4SF,
20735 IX86_BUILTIN_VEC_EXT_V4SI,
20736 IX86_BUILTIN_VEC_EXT_V8HI,
20737 IX86_BUILTIN_VEC_EXT_V2SI,
20738 IX86_BUILTIN_VEC_EXT_V4HI,
20739 IX86_BUILTIN_VEC_EXT_V16QI,
20740 IX86_BUILTIN_VEC_SET_V2DI,
20741 IX86_BUILTIN_VEC_SET_V4SF,
20742 IX86_BUILTIN_VEC_SET_V4SI,
20743 IX86_BUILTIN_VEC_SET_V8HI,
20744 IX86_BUILTIN_VEC_SET_V4HI,
20745 IX86_BUILTIN_VEC_SET_V16QI,
20747 IX86_BUILTIN_VEC_PACK_SFIX,
20750 IX86_BUILTIN_CRC32QI,
20751 IX86_BUILTIN_CRC32HI,
20752 IX86_BUILTIN_CRC32SI,
20753 IX86_BUILTIN_CRC32DI,
20755 IX86_BUILTIN_PCMPESTRI128,
20756 IX86_BUILTIN_PCMPESTRM128,
20757 IX86_BUILTIN_PCMPESTRA128,
20758 IX86_BUILTIN_PCMPESTRC128,
20759 IX86_BUILTIN_PCMPESTRO128,
20760 IX86_BUILTIN_PCMPESTRS128,
20761 IX86_BUILTIN_PCMPESTRZ128,
20762 IX86_BUILTIN_PCMPISTRI128,
20763 IX86_BUILTIN_PCMPISTRM128,
20764 IX86_BUILTIN_PCMPISTRA128,
20765 IX86_BUILTIN_PCMPISTRC128,
20766 IX86_BUILTIN_PCMPISTRO128,
20767 IX86_BUILTIN_PCMPISTRS128,
20768 IX86_BUILTIN_PCMPISTRZ128,
20770 IX86_BUILTIN_PCMPGTQ,
20772 /* AES instructions */
20773 IX86_BUILTIN_AESENC128,
20774 IX86_BUILTIN_AESENCLAST128,
20775 IX86_BUILTIN_AESDEC128,
20776 IX86_BUILTIN_AESDECLAST128,
20777 IX86_BUILTIN_AESIMC128,
20778 IX86_BUILTIN_AESKEYGENASSIST128,
20780 /* PCLMUL instruction */
20781 IX86_BUILTIN_PCLMULQDQ128,
20784 IX86_BUILTIN_ADDPD256,
20785 IX86_BUILTIN_ADDPS256,
20786 IX86_BUILTIN_ADDSUBPD256,
20787 IX86_BUILTIN_ADDSUBPS256,
20788 IX86_BUILTIN_ANDPD256,
20789 IX86_BUILTIN_ANDPS256,
20790 IX86_BUILTIN_ANDNPD256,
20791 IX86_BUILTIN_ANDNPS256,
20792 IX86_BUILTIN_BLENDPD256,
20793 IX86_BUILTIN_BLENDPS256,
20794 IX86_BUILTIN_BLENDVPD256,
20795 IX86_BUILTIN_BLENDVPS256,
20796 IX86_BUILTIN_DIVPD256,
20797 IX86_BUILTIN_DIVPS256,
20798 IX86_BUILTIN_DPPS256,
20799 IX86_BUILTIN_HADDPD256,
20800 IX86_BUILTIN_HADDPS256,
20801 IX86_BUILTIN_HSUBPD256,
20802 IX86_BUILTIN_HSUBPS256,
20803 IX86_BUILTIN_MAXPD256,
20804 IX86_BUILTIN_MAXPS256,
20805 IX86_BUILTIN_MINPD256,
20806 IX86_BUILTIN_MINPS256,
20807 IX86_BUILTIN_MULPD256,
20808 IX86_BUILTIN_MULPS256,
20809 IX86_BUILTIN_ORPD256,
20810 IX86_BUILTIN_ORPS256,
20811 IX86_BUILTIN_SHUFPD256,
20812 IX86_BUILTIN_SHUFPS256,
20813 IX86_BUILTIN_SUBPD256,
20814 IX86_BUILTIN_SUBPS256,
20815 IX86_BUILTIN_XORPD256,
20816 IX86_BUILTIN_XORPS256,
20817 IX86_BUILTIN_CMPSD,
20818 IX86_BUILTIN_CMPSS,
20819 IX86_BUILTIN_CMPPD,
20820 IX86_BUILTIN_CMPPS,
20821 IX86_BUILTIN_CMPPD256,
20822 IX86_BUILTIN_CMPPS256,
20823 IX86_BUILTIN_CVTDQ2PD256,
20824 IX86_BUILTIN_CVTDQ2PS256,
20825 IX86_BUILTIN_CVTPD2PS256,
20826 IX86_BUILTIN_CVTPS2DQ256,
20827 IX86_BUILTIN_CVTPS2PD256,
20828 IX86_BUILTIN_CVTTPD2DQ256,
20829 IX86_BUILTIN_CVTPD2DQ256,
20830 IX86_BUILTIN_CVTTPS2DQ256,
20831 IX86_BUILTIN_EXTRACTF128PD256,
20832 IX86_BUILTIN_EXTRACTF128PS256,
20833 IX86_BUILTIN_EXTRACTF128SI256,
20834 IX86_BUILTIN_VZEROALL,
20835 IX86_BUILTIN_VZEROUPPER,
20836 IX86_BUILTIN_VZEROUPPER_REX64,
20837 IX86_BUILTIN_VPERMILVARPD,
20838 IX86_BUILTIN_VPERMILVARPS,
20839 IX86_BUILTIN_VPERMILVARPD256,
20840 IX86_BUILTIN_VPERMILVARPS256,
20841 IX86_BUILTIN_VPERMILPD,
20842 IX86_BUILTIN_VPERMILPS,
20843 IX86_BUILTIN_VPERMILPD256,
20844 IX86_BUILTIN_VPERMILPS256,
20845 IX86_BUILTIN_VPERM2F128PD256,
20846 IX86_BUILTIN_VPERM2F128PS256,
20847 IX86_BUILTIN_VPERM2F128SI256,
20848 IX86_BUILTIN_VBROADCASTSS,
20849 IX86_BUILTIN_VBROADCASTSD256,
20850 IX86_BUILTIN_VBROADCASTSS256,
20851 IX86_BUILTIN_VBROADCASTPD256,
20852 IX86_BUILTIN_VBROADCASTPS256,
20853 IX86_BUILTIN_VINSERTF128PD256,
20854 IX86_BUILTIN_VINSERTF128PS256,
20855 IX86_BUILTIN_VINSERTF128SI256,
20856 IX86_BUILTIN_LOADUPD256,
20857 IX86_BUILTIN_LOADUPS256,
20858 IX86_BUILTIN_STOREUPD256,
20859 IX86_BUILTIN_STOREUPS256,
20860 IX86_BUILTIN_LDDQU256,
20861 IX86_BUILTIN_MOVNTDQ256,
20862 IX86_BUILTIN_MOVNTPD256,
20863 IX86_BUILTIN_MOVNTPS256,
20864 IX86_BUILTIN_LOADDQU256,
20865 IX86_BUILTIN_STOREDQU256,
20866 IX86_BUILTIN_MASKLOADPD,
20867 IX86_BUILTIN_MASKLOADPS,
20868 IX86_BUILTIN_MASKSTOREPD,
20869 IX86_BUILTIN_MASKSTOREPS,
20870 IX86_BUILTIN_MASKLOADPD256,
20871 IX86_BUILTIN_MASKLOADPS256,
20872 IX86_BUILTIN_MASKSTOREPD256,
20873 IX86_BUILTIN_MASKSTOREPS256,
20874 IX86_BUILTIN_MOVSHDUP256,
20875 IX86_BUILTIN_MOVSLDUP256,
20876 IX86_BUILTIN_MOVDDUP256,
20878 IX86_BUILTIN_SQRTPD256,
20879 IX86_BUILTIN_SQRTPS256,
20880 IX86_BUILTIN_SQRTPS_NR256,
20881 IX86_BUILTIN_RSQRTPS256,
20882 IX86_BUILTIN_RSQRTPS_NR256,
20884 IX86_BUILTIN_RCPPS256,
20886 IX86_BUILTIN_ROUNDPD256,
20887 IX86_BUILTIN_ROUNDPS256,
20889 IX86_BUILTIN_UNPCKHPD256,
20890 IX86_BUILTIN_UNPCKLPD256,
20891 IX86_BUILTIN_UNPCKHPS256,
20892 IX86_BUILTIN_UNPCKLPS256,
20894 IX86_BUILTIN_SI256_SI,
20895 IX86_BUILTIN_PS256_PS,
20896 IX86_BUILTIN_PD256_PD,
20897 IX86_BUILTIN_SI_SI256,
20898 IX86_BUILTIN_PS_PS256,
20899 IX86_BUILTIN_PD_PD256,
20901 IX86_BUILTIN_VTESTZPD,
20902 IX86_BUILTIN_VTESTCPD,
20903 IX86_BUILTIN_VTESTNZCPD,
20904 IX86_BUILTIN_VTESTZPS,
20905 IX86_BUILTIN_VTESTCPS,
20906 IX86_BUILTIN_VTESTNZCPS,
20907 IX86_BUILTIN_VTESTZPD256,
20908 IX86_BUILTIN_VTESTCPD256,
20909 IX86_BUILTIN_VTESTNZCPD256,
20910 IX86_BUILTIN_VTESTZPS256,
20911 IX86_BUILTIN_VTESTCPS256,
20912 IX86_BUILTIN_VTESTNZCPS256,
20913 IX86_BUILTIN_PTESTZ256,
20914 IX86_BUILTIN_PTESTC256,
20915 IX86_BUILTIN_PTESTNZC256,
20917 IX86_BUILTIN_MOVMSKPD256,
20918 IX86_BUILTIN_MOVMSKPS256,
20920 /* TFmode support builtins. */
20922 IX86_BUILTIN_HUGE_VALQ,
20923 IX86_BUILTIN_FABSQ,
20924 IX86_BUILTIN_COPYSIGNQ,
20926 /* Vectorizer support builtins. */
20927 IX86_BUILTIN_CPYSGNPS,
20928 IX86_BUILTIN_CPYSGNPD,
20930 IX86_BUILTIN_CVTUDQ2PS,
20932 /* FMA4 and XOP instructions. */
20933 IX86_BUILTIN_VFMADDSS,
20934 IX86_BUILTIN_VFMADDSD,
20935 IX86_BUILTIN_VFMADDPS,
20936 IX86_BUILTIN_VFMADDPD,
20937 IX86_BUILTIN_VFMSUBSS,
20938 IX86_BUILTIN_VFMSUBSD,
20939 IX86_BUILTIN_VFMSUBPS,
20940 IX86_BUILTIN_VFMSUBPD,
20941 IX86_BUILTIN_VFMADDSUBPS,
20942 IX86_BUILTIN_VFMADDSUBPD,
20943 IX86_BUILTIN_VFMSUBADDPS,
20944 IX86_BUILTIN_VFMSUBADDPD,
20945 IX86_BUILTIN_VFNMADDSS,
20946 IX86_BUILTIN_VFNMADDSD,
20947 IX86_BUILTIN_VFNMADDPS,
20948 IX86_BUILTIN_VFNMADDPD,
20949 IX86_BUILTIN_VFNMSUBSS,
20950 IX86_BUILTIN_VFNMSUBSD,
20951 IX86_BUILTIN_VFNMSUBPS,
20952 IX86_BUILTIN_VFNMSUBPD,
20953 IX86_BUILTIN_VFMADDPS256,
20954 IX86_BUILTIN_VFMADDPD256,
20955 IX86_BUILTIN_VFMSUBPS256,
20956 IX86_BUILTIN_VFMSUBPD256,
20957 IX86_BUILTIN_VFMADDSUBPS256,
20958 IX86_BUILTIN_VFMADDSUBPD256,
20959 IX86_BUILTIN_VFMSUBADDPS256,
20960 IX86_BUILTIN_VFMSUBADDPD256,
20961 IX86_BUILTIN_VFNMADDPS256,
20962 IX86_BUILTIN_VFNMADDPD256,
20963 IX86_BUILTIN_VFNMSUBPS256,
20964 IX86_BUILTIN_VFNMSUBPD256,
20966 IX86_BUILTIN_VPCMOV,
20967 IX86_BUILTIN_VPCMOV_V2DI,
20968 IX86_BUILTIN_VPCMOV_V4SI,
20969 IX86_BUILTIN_VPCMOV_V8HI,
20970 IX86_BUILTIN_VPCMOV_V16QI,
20971 IX86_BUILTIN_VPCMOV_V4SF,
20972 IX86_BUILTIN_VPCMOV_V2DF,
20973 IX86_BUILTIN_VPCMOV256,
20974 IX86_BUILTIN_VPCMOV_V4DI256,
20975 IX86_BUILTIN_VPCMOV_V8SI256,
20976 IX86_BUILTIN_VPCMOV_V16HI256,
20977 IX86_BUILTIN_VPCMOV_V32QI256,
20978 IX86_BUILTIN_VPCMOV_V8SF256,
20979 IX86_BUILTIN_VPCMOV_V4DF256,
20981 IX86_BUILTIN_VPPERM,
20983 IX86_BUILTIN_VPMACSSWW,
20984 IX86_BUILTIN_VPMACSWW,
20985 IX86_BUILTIN_VPMACSSWD,
20986 IX86_BUILTIN_VPMACSWD,
20987 IX86_BUILTIN_VPMACSSDD,
20988 IX86_BUILTIN_VPMACSDD,
20989 IX86_BUILTIN_VPMACSSDQL,
20990 IX86_BUILTIN_VPMACSSDQH,
20991 IX86_BUILTIN_VPMACSDQL,
20992 IX86_BUILTIN_VPMACSDQH,
20993 IX86_BUILTIN_VPMADCSSWD,
20994 IX86_BUILTIN_VPMADCSWD,
20996 IX86_BUILTIN_VPHADDBW,
20997 IX86_BUILTIN_VPHADDBD,
20998 IX86_BUILTIN_VPHADDBQ,
20999 IX86_BUILTIN_VPHADDWD,
21000 IX86_BUILTIN_VPHADDWQ,
21001 IX86_BUILTIN_VPHADDDQ,
21002 IX86_BUILTIN_VPHADDUBW,
21003 IX86_BUILTIN_VPHADDUBD,
21004 IX86_BUILTIN_VPHADDUBQ,
21005 IX86_BUILTIN_VPHADDUWD,
21006 IX86_BUILTIN_VPHADDUWQ,
21007 IX86_BUILTIN_VPHADDUDQ,
21008 IX86_BUILTIN_VPHSUBBW,
21009 IX86_BUILTIN_VPHSUBWD,
21010 IX86_BUILTIN_VPHSUBDQ,
21012 IX86_BUILTIN_VPROTB,
21013 IX86_BUILTIN_VPROTW,
21014 IX86_BUILTIN_VPROTD,
21015 IX86_BUILTIN_VPROTQ,
21016 IX86_BUILTIN_VPROTB_IMM,
21017 IX86_BUILTIN_VPROTW_IMM,
21018 IX86_BUILTIN_VPROTD_IMM,
21019 IX86_BUILTIN_VPROTQ_IMM,
21021 IX86_BUILTIN_VPSHLB,
21022 IX86_BUILTIN_VPSHLW,
21023 IX86_BUILTIN_VPSHLD,
21024 IX86_BUILTIN_VPSHLQ,
21025 IX86_BUILTIN_VPSHAB,
21026 IX86_BUILTIN_VPSHAW,
21027 IX86_BUILTIN_VPSHAD,
21028 IX86_BUILTIN_VPSHAQ,
21030 IX86_BUILTIN_VFRCZSS,
21031 IX86_BUILTIN_VFRCZSD,
21032 IX86_BUILTIN_VFRCZPS,
21033 IX86_BUILTIN_VFRCZPD,
21034 IX86_BUILTIN_VFRCZPS256,
21035 IX86_BUILTIN_VFRCZPD256,
21037 IX86_BUILTIN_VPCOMEQUB,
21038 IX86_BUILTIN_VPCOMNEUB,
21039 IX86_BUILTIN_VPCOMLTUB,
21040 IX86_BUILTIN_VPCOMLEUB,
21041 IX86_BUILTIN_VPCOMGTUB,
21042 IX86_BUILTIN_VPCOMGEUB,
21043 IX86_BUILTIN_VPCOMFALSEUB,
21044 IX86_BUILTIN_VPCOMTRUEUB,
21046 IX86_BUILTIN_VPCOMEQUW,
21047 IX86_BUILTIN_VPCOMNEUW,
21048 IX86_BUILTIN_VPCOMLTUW,
21049 IX86_BUILTIN_VPCOMLEUW,
21050 IX86_BUILTIN_VPCOMGTUW,
21051 IX86_BUILTIN_VPCOMGEUW,
21052 IX86_BUILTIN_VPCOMFALSEUW,
21053 IX86_BUILTIN_VPCOMTRUEUW,
21055 IX86_BUILTIN_VPCOMEQUD,
21056 IX86_BUILTIN_VPCOMNEUD,
21057 IX86_BUILTIN_VPCOMLTUD,
21058 IX86_BUILTIN_VPCOMLEUD,
21059 IX86_BUILTIN_VPCOMGTUD,
21060 IX86_BUILTIN_VPCOMGEUD,
21061 IX86_BUILTIN_VPCOMFALSEUD,
21062 IX86_BUILTIN_VPCOMTRUEUD,
21064 IX86_BUILTIN_VPCOMEQUQ,
21065 IX86_BUILTIN_VPCOMNEUQ,
21066 IX86_BUILTIN_VPCOMLTUQ,
21067 IX86_BUILTIN_VPCOMLEUQ,
21068 IX86_BUILTIN_VPCOMGTUQ,
21069 IX86_BUILTIN_VPCOMGEUQ,
21070 IX86_BUILTIN_VPCOMFALSEUQ,
21071 IX86_BUILTIN_VPCOMTRUEUQ,
21073 IX86_BUILTIN_VPCOMEQB,
21074 IX86_BUILTIN_VPCOMNEB,
21075 IX86_BUILTIN_VPCOMLTB,
21076 IX86_BUILTIN_VPCOMLEB,
21077 IX86_BUILTIN_VPCOMGTB,
21078 IX86_BUILTIN_VPCOMGEB,
21079 IX86_BUILTIN_VPCOMFALSEB,
21080 IX86_BUILTIN_VPCOMTRUEB,
21082 IX86_BUILTIN_VPCOMEQW,
21083 IX86_BUILTIN_VPCOMNEW,
21084 IX86_BUILTIN_VPCOMLTW,
21085 IX86_BUILTIN_VPCOMLEW,
21086 IX86_BUILTIN_VPCOMGTW,
21087 IX86_BUILTIN_VPCOMGEW,
21088 IX86_BUILTIN_VPCOMFALSEW,
21089 IX86_BUILTIN_VPCOMTRUEW,
21091 IX86_BUILTIN_VPCOMEQD,
21092 IX86_BUILTIN_VPCOMNED,
21093 IX86_BUILTIN_VPCOMLTD,
21094 IX86_BUILTIN_VPCOMLED,
21095 IX86_BUILTIN_VPCOMGTD,
21096 IX86_BUILTIN_VPCOMGED,
21097 IX86_BUILTIN_VPCOMFALSED,
21098 IX86_BUILTIN_VPCOMTRUED,
21100 IX86_BUILTIN_VPCOMEQQ,
21101 IX86_BUILTIN_VPCOMNEQ,
21102 IX86_BUILTIN_VPCOMLTQ,
21103 IX86_BUILTIN_VPCOMLEQ,
21104 IX86_BUILTIN_VPCOMGTQ,
21105 IX86_BUILTIN_VPCOMGEQ,
21106 IX86_BUILTIN_VPCOMFALSEQ,
21107 IX86_BUILTIN_VPCOMTRUEQ,
21109 /* LWP instructions. */
21110 IX86_BUILTIN_LLWPCB16,
21111 IX86_BUILTIN_LLWPCB32,
21112 IX86_BUILTIN_LLWPCB64,
21113 IX86_BUILTIN_SLWPCB16,
21114 IX86_BUILTIN_SLWPCB32,
21115 IX86_BUILTIN_SLWPCB64,
21116 IX86_BUILTIN_LWPVAL16,
21117 IX86_BUILTIN_LWPVAL32,
21118 IX86_BUILTIN_LWPVAL64,
21119 IX86_BUILTIN_LWPINS16,
21120 IX86_BUILTIN_LWPINS32,
21121 IX86_BUILTIN_LWPINS64,
21126 /* Table for the ix86 builtin decls. */
21127 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
21129 /* Table of all of the builtin functions that are possible with different ISA's
21130 but are waiting to be built until a function is declared to use that
21132 struct GTY(()) builtin_isa {
21133 tree type; /* builtin type to use in the declaration */
21134 const char *name; /* function name */
21135 int isa; /* isa_flags this builtin is defined for */
21136 bool const_p; /* true if the declaration is constant */
21139 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
21142 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21143 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
21144 * function decl in the ix86_builtins array. Returns the function decl or
21145 * NULL_TREE, if the builtin was not added.
21147 * If the front end has a special hook for builtin functions, delay adding
21148 * builtin functions that aren't in the current ISA until the ISA is changed
21149 * with function specific optimization. Doing so, can save about 300K for the
21150 * default compiler. When the builtin is expanded, check at that time whether
21153 * If the front end doesn't have a special hook, record all builtins, even if
21154 * it isn't an instruction set in the current ISA in case the user uses
21155 * function specific options for a different ISA, so that we don't get scope
21156 * errors if a builtin is added in the middle of a function scope. */
21159 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
21161 tree decl = NULL_TREE;
21163 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
21165 ix86_builtins_isa[(int) code].isa = mask;
21167 if ((mask & ix86_isa_flags) != 0
21168 || (lang_hooks.builtin_function
21169 == lang_hooks.builtin_function_ext_scope))
21172 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
21174 ix86_builtins[(int) code] = decl;
21175 ix86_builtins_isa[(int) code].type = NULL_TREE;
21179 ix86_builtins[(int) code] = NULL_TREE;
21180 ix86_builtins_isa[(int) code].const_p = false;
21181 ix86_builtins_isa[(int) code].type = type;
21182 ix86_builtins_isa[(int) code].name = name;
21189 /* Like def_builtin, but also marks the function decl "const". */
21192 def_builtin_const (int mask, const char *name, tree type,
21193 enum ix86_builtins code)
21195 tree decl = def_builtin (mask, name, type, code);
21197 TREE_READONLY (decl) = 1;
21199 ix86_builtins_isa[(int) code].const_p = true;
21204 /* Add any new builtin functions for a given ISA that may not have been
21205 declared. This saves a bit of space compared to adding all of the
21206 declarations to the tree, even if we didn't use them. */
21209 ix86_add_new_builtins (int isa)
21214 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
21216 if ((ix86_builtins_isa[i].isa & isa) != 0
21217 && ix86_builtins_isa[i].type != NULL_TREE)
21219 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
21220 ix86_builtins_isa[i].type,
21221 i, BUILT_IN_MD, NULL,
21224 ix86_builtins[i] = decl;
21225 ix86_builtins_isa[i].type = NULL_TREE;
21226 if (ix86_builtins_isa[i].const_p)
21227 TREE_READONLY (decl) = 1;
21232 /* Bits for builtin_description.flag. */
21234 /* Set when we don't support the comparison natively, and should
21235 swap_comparison in order to support it. */
21236 #define BUILTIN_DESC_SWAP_OPERANDS 1
21238 struct builtin_description
21240 const unsigned int mask;
21241 const enum insn_code icode;
21242 const char *const name;
21243 const enum ix86_builtins code;
21244 const enum rtx_code comparison;
21248 static const struct builtin_description bdesc_comi[] =
21250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21259 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21260 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21261 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21276 static const struct builtin_description bdesc_pcmpestr[] =
21279 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21280 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21281 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21282 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21283 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21284 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21285 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21288 static const struct builtin_description bdesc_pcmpistr[] =
21291 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21292 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21293 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21294 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21295 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21296 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21297 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21300 /* Special builtin types */
21301 enum ix86_special_builtin_type
21303 SPECIAL_FTYPE_UNKNOWN,
21306 UINT64_FTYPE_PUNSIGNED,
21307 V32QI_FTYPE_PCCHAR,
21308 V16QI_FTYPE_PCCHAR,
21310 V8SF_FTYPE_PCFLOAT,
21312 V4DF_FTYPE_PCDOUBLE,
21313 V4SF_FTYPE_PCFLOAT,
21314 V2DF_FTYPE_PCDOUBLE,
21315 V8SF_FTYPE_PCV8SF_V8SF,
21316 V4DF_FTYPE_PCV4DF_V4DF,
21317 V4SF_FTYPE_V4SF_PCV2SF,
21318 V4SF_FTYPE_PCV4SF_V4SF,
21319 V2DF_FTYPE_V2DF_PCDOUBLE,
21320 V2DF_FTYPE_PCV2DF_V2DF,
21322 VOID_FTYPE_PV2SF_V4SF,
21323 VOID_FTYPE_PV4DI_V4DI,
21324 VOID_FTYPE_PV2DI_V2DI,
21325 VOID_FTYPE_PCHAR_V32QI,
21326 VOID_FTYPE_PCHAR_V16QI,
21327 VOID_FTYPE_PFLOAT_V8SF,
21328 VOID_FTYPE_PFLOAT_V4SF,
21329 VOID_FTYPE_PDOUBLE_V4DF,
21330 VOID_FTYPE_PDOUBLE_V2DF,
21332 VOID_FTYPE_PINT_INT,
21333 VOID_FTYPE_PV8SF_V8SF_V8SF,
21334 VOID_FTYPE_PV4DF_V4DF_V4DF,
21335 VOID_FTYPE_PV4SF_V4SF_V4SF,
21336 VOID_FTYPE_PV2DF_V2DF_V2DF,
21337 VOID_FTYPE_USHORT_UINT_USHORT,
21338 VOID_FTYPE_UINT_UINT_UINT,
21339 VOID_FTYPE_UINT64_UINT_UINT,
21340 UCHAR_FTYPE_USHORT_UINT_USHORT,
21341 UCHAR_FTYPE_UINT_UINT_UINT,
21342 UCHAR_FTYPE_UINT64_UINT_UINT
21345 /* Builtin types */
21346 enum ix86_builtin_type
21349 FLOAT128_FTYPE_FLOAT128,
21351 FLOAT128_FTYPE_FLOAT128_FLOAT128,
21352 INT_FTYPE_V8SF_V8SF_PTEST,
21353 INT_FTYPE_V4DI_V4DI_PTEST,
21354 INT_FTYPE_V4DF_V4DF_PTEST,
21355 INT_FTYPE_V4SF_V4SF_PTEST,
21356 INT_FTYPE_V2DI_V2DI_PTEST,
21357 INT_FTYPE_V2DF_V2DF_PTEST,
21392 V4SF_FTYPE_V4SF_VEC_MERGE,
21401 V2DF_FTYPE_V2DF_VEC_MERGE,
21412 V16QI_FTYPE_V16QI_V16QI,
21413 V16QI_FTYPE_V8HI_V8HI,
21414 V8QI_FTYPE_V8QI_V8QI,
21415 V8QI_FTYPE_V4HI_V4HI,
21416 V8HI_FTYPE_V8HI_V8HI,
21417 V8HI_FTYPE_V8HI_V8HI_COUNT,
21418 V8HI_FTYPE_V16QI_V16QI,
21419 V8HI_FTYPE_V4SI_V4SI,
21420 V8HI_FTYPE_V8HI_SI_COUNT,
21421 V8SF_FTYPE_V8SF_V8SF,
21422 V8SF_FTYPE_V8SF_V8SI,
21423 V4SI_FTYPE_V4SI_V4SI,
21424 V4SI_FTYPE_V4SI_V4SI_COUNT,
21425 V4SI_FTYPE_V8HI_V8HI,
21426 V4SI_FTYPE_V4SF_V4SF,
21427 V4SI_FTYPE_V2DF_V2DF,
21428 V4SI_FTYPE_V4SI_SI_COUNT,
21429 V4HI_FTYPE_V4HI_V4HI,
21430 V4HI_FTYPE_V4HI_V4HI_COUNT,
21431 V4HI_FTYPE_V8QI_V8QI,
21432 V4HI_FTYPE_V2SI_V2SI,
21433 V4HI_FTYPE_V4HI_SI_COUNT,
21434 V4DF_FTYPE_V4DF_V4DF,
21435 V4DF_FTYPE_V4DF_V4DI,
21436 V4SF_FTYPE_V4SF_V4SF,
21437 V4SF_FTYPE_V4SF_V4SF_SWAP,
21438 V4SF_FTYPE_V4SF_V4SI,
21439 V4SF_FTYPE_V4SF_V2SI,
21440 V4SF_FTYPE_V4SF_V2DF,
21441 V4SF_FTYPE_V4SF_DI,
21442 V4SF_FTYPE_V4SF_SI,
21443 V2DI_FTYPE_V2DI_V2DI,
21444 V2DI_FTYPE_V2DI_V2DI_COUNT,
21445 V2DI_FTYPE_V16QI_V16QI,
21446 V2DI_FTYPE_V4SI_V4SI,
21447 V2DI_FTYPE_V2DI_V16QI,
21448 V2DI_FTYPE_V2DF_V2DF,
21449 V2DI_FTYPE_V2DI_SI_COUNT,
21450 V2SI_FTYPE_V2SI_V2SI,
21451 V2SI_FTYPE_V2SI_V2SI_COUNT,
21452 V2SI_FTYPE_V4HI_V4HI,
21453 V2SI_FTYPE_V2SF_V2SF,
21454 V2SI_FTYPE_V2SI_SI_COUNT,
21455 V2DF_FTYPE_V2DF_V2DF,
21456 V2DF_FTYPE_V2DF_V2DF_SWAP,
21457 V2DF_FTYPE_V2DF_V4SF,
21458 V2DF_FTYPE_V2DF_V2DI,
21459 V2DF_FTYPE_V2DF_DI,
21460 V2DF_FTYPE_V2DF_SI,
21461 V2SF_FTYPE_V2SF_V2SF,
21462 V1DI_FTYPE_V1DI_V1DI,
21463 V1DI_FTYPE_V1DI_V1DI_COUNT,
21464 V1DI_FTYPE_V8QI_V8QI,
21465 V1DI_FTYPE_V2SI_V2SI,
21466 V1DI_FTYPE_V1DI_SI_COUNT,
21467 UINT64_FTYPE_UINT64_UINT64,
21468 UINT_FTYPE_UINT_UINT,
21469 UINT_FTYPE_UINT_USHORT,
21470 UINT_FTYPE_UINT_UCHAR,
21471 UINT16_FTYPE_UINT16_INT,
21472 UINT8_FTYPE_UINT8_INT,
21473 V8HI_FTYPE_V8HI_INT,
21474 V4SI_FTYPE_V4SI_INT,
21475 V4HI_FTYPE_V4HI_INT,
21476 V8SF_FTYPE_V8SF_INT,
21477 V4SI_FTYPE_V8SI_INT,
21478 V4SF_FTYPE_V8SF_INT,
21479 V2DF_FTYPE_V4DF_INT,
21480 V4DF_FTYPE_V4DF_INT,
21481 V4SF_FTYPE_V4SF_INT,
21482 V2DI_FTYPE_V2DI_INT,
21483 V2DI2TI_FTYPE_V2DI_INT,
21484 V2DF_FTYPE_V2DF_INT,
21485 V16QI_FTYPE_V16QI_V16QI_V16QI,
21486 V8SF_FTYPE_V8SF_V8SF_V8SF,
21487 V4DF_FTYPE_V4DF_V4DF_V4DF,
21488 V4SF_FTYPE_V4SF_V4SF_V4SF,
21489 V2DF_FTYPE_V2DF_V2DF_V2DF,
21490 V16QI_FTYPE_V16QI_V16QI_INT,
21491 V8SI_FTYPE_V8SI_V8SI_INT,
21492 V8SI_FTYPE_V8SI_V4SI_INT,
21493 V8HI_FTYPE_V8HI_V8HI_INT,
21494 V8SF_FTYPE_V8SF_V8SF_INT,
21495 V8SF_FTYPE_V8SF_V4SF_INT,
21496 V4SI_FTYPE_V4SI_V4SI_INT,
21497 V4DF_FTYPE_V4DF_V4DF_INT,
21498 V4DF_FTYPE_V4DF_V2DF_INT,
21499 V4SF_FTYPE_V4SF_V4SF_INT,
21500 V2DI_FTYPE_V2DI_V2DI_INT,
21501 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21502 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21503 V2DF_FTYPE_V2DF_V2DF_INT,
21504 V2DI_FTYPE_V2DI_UINT_UINT,
21505 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21508 /* Special builtins with variable number of arguments. */
21509 static const struct builtin_description bdesc_special_args[] =
21511 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21512 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21515 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21518 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21521 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21522 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21523 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21525 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21526 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21527 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21528 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21530 /* SSE or 3DNow!A */
21531 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21532 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21549 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21555 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21556 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21561 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21590 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbhi1, "__builtin_ia32_llwpcb16", IX86_BUILTIN_LLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID },
21591 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbsi1, "__builtin_ia32_llwpcb32", IX86_BUILTIN_LLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID },
21592 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbdi1, "__builtin_ia32_llwpcb64", IX86_BUILTIN_LLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID },
21594 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbhi1, "__builtin_ia32_slwpcb16", IX86_BUILTIN_SLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID },
21595 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbsi1, "__builtin_ia32_slwpcb32", IX86_BUILTIN_SLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID },
21596 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbdi1, "__builtin_ia32_slwpcb64", IX86_BUILTIN_SLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID },
21598 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalhi3, "__builtin_ia32_lwpval16", IX86_BUILTIN_LWPVAL16, UNKNOWN, (int) VOID_FTYPE_USHORT_UINT_USHORT },
21599 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
21600 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
21601 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinshi3, "__builtin_ia32_lwpins16", IX86_BUILTIN_LWPINS16, UNKNOWN, (int) UCHAR_FTYPE_USHORT_UINT_USHORT },
21602 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
21603 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
21607 /* Builtins with variable number of arguments. */
21608 static const struct builtin_description bdesc_args[] =
21610 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21611 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21612 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21613 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21614 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21615 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21616 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21619 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21620 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21621 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21622 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21623 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21624 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21626 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21627 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21628 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21629 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21630 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21631 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21632 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21633 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21635 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21636 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21638 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21639 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21640 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21641 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21643 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21644 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21645 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21646 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21647 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21648 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21650 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21651 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21652 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21653 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21654 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21655 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21657 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21658 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21659 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21661 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21663 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21664 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21665 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21666 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21667 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21668 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21670 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21671 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21672 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21673 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21674 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21675 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21677 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21678 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21679 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21680 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21683 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21684 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21685 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21686 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21688 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21689 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21690 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21691 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21692 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21693 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21694 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21695 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21696 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21697 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21698 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21699 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21700 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21701 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21702 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21705 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21706 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21707 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21708 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21709 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21710 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21713 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21714 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21715 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21716 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21717 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21718 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21719 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21720 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21721 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21722 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21723 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21724 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21726 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21728 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21729 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21730 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21731 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21732 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21733 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21734 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21737 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21738 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21739 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21740 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21741 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21742 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21745 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21756 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21758 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21760 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21761 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21765 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21767 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21768 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21770 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21774 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21775 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21776 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21778 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21779 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21780 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21782 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21784 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21785 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21786 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21788 /* SSE MMX or 3Dnow!A */
21789 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21790 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21791 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21793 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21794 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21795 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21796 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21798 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21799 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21801 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21804 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21813 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21817 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21819 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21823 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21824 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21827 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21830 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21831 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21832 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21833 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21857 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21858 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21860 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21861 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21862 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21863 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21865 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21867 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21868 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21870 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21876 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21878 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21879 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21880 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21881 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21882 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21883 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21884 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21885 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21896 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21897 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21899 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21901 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21902 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21914 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21915 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21916 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21920 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21922 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21924 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21926 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21928 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21929 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21930 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21932 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21935 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21936 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21938 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21941 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21943 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21945 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21946 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21947 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21948 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21949 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21950 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21951 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21953 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21954 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21955 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21956 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21957 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21958 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21959 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21961 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21962 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21963 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21964 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21972 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21973 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21975 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21978 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21979 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21982 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21983 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21985 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21986 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21987 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21988 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21989 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21990 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21993 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21994 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21995 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21996 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21997 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21998 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
22000 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22001 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22002 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22003 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22004 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22005 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22006 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22007 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22008 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22009 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22010 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22011 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22012 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
22013 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
22014 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22015 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22016 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22017 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22018 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22019 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22020 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22021 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22022 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22023 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22026 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
22027 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
22030 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22031 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22032 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
22033 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
22034 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22035 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22036 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22037 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
22038 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22039 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
22041 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22042 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22043 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22044 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22045 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22046 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22047 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22048 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22049 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22050 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22051 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22052 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22053 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22056 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22057 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22058 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22059 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22060 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22061 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22062 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22063 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22064 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22065 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22066 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22069 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22070 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22071 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22072 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22074 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22075 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22076 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22079 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22080 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22081 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22082 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22083 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22086 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22087 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22088 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22089 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22092 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22093 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22095 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22096 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22097 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22098 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22101 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22104 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22105 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22106 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22107 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22108 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22109 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22111 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22112 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22113 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22114 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22115 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22116 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22117 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22118 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22119 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22120 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22121 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22122 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22123 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22124 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22125 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22126 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22127 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22128 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22129 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22134 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22139 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22141 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22142 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22146 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22147 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22148 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22149 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22150 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22151 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22152 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22153 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22154 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22155 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22157 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22160 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22163 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22164 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22165 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22166 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22167 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22168 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22169 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22171 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22172 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22173 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22175 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22176 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22177 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22179 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22183 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22187 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22189 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22192 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22194 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22195 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22198 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22199 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22200 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22202 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22204 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22205 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22207 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22210 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22211 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22212 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22214 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22215 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22218 /* FMA4 and XOP. */
22219 enum multi_arg_type {
22241 MULTI_ARG_2_DI_IMM,
22242 MULTI_ARG_2_SI_IMM,
22243 MULTI_ARG_2_HI_IMM,
22244 MULTI_ARG_2_QI_IMM,
22245 MULTI_ARG_2_DI_CMP,
22246 MULTI_ARG_2_SI_CMP,
22247 MULTI_ARG_2_HI_CMP,
22248 MULTI_ARG_2_QI_CMP,
22272 static const struct builtin_description bdesc_multi_arg[] =
22274 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22275 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22276 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22277 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22278 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22279 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22280 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22281 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22283 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22284 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22285 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22286 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22287 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22288 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22289 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22290 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22292 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22293 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22294 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22295 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22297 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22298 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22299 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22300 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22302 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22303 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22304 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22305 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22307 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22308 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22309 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22310 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
22323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
22324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
22325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22339 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22348 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22356 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22363 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22364 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
22365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
22367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22379 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22380 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22467 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22468 in the current target ISA to allow the user to compile particular modules
22469 with different target specific options that differ from the command line
22472 ix86_init_mmx_sse_builtins (void)
22474 const struct builtin_description * d;
22477 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
22478 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
22479 tree V1DI_type_node
22480 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
22481 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
22482 tree V2DI_type_node
22483 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
22484 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
22485 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
22486 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
22487 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
22488 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
22489 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
22491 tree pchar_type_node = build_pointer_type (char_type_node);
22492 tree pcchar_type_node
22493 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
22494 tree pfloat_type_node = build_pointer_type (float_type_node);
22495 tree pcfloat_type_node
22496 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
22497 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
22498 tree pcv2sf_type_node
22499 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
22500 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
22501 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
22504 tree int_ftype_v4sf_v4sf
22505 = build_function_type_list (integer_type_node,
22506 V4SF_type_node, V4SF_type_node, NULL_TREE);
22507 tree v4si_ftype_v4sf_v4sf
22508 = build_function_type_list (V4SI_type_node,
22509 V4SF_type_node, V4SF_type_node, NULL_TREE);
22510 /* MMX/SSE/integer conversions. */
22511 tree int_ftype_v4sf
22512 = build_function_type_list (integer_type_node,
22513 V4SF_type_node, NULL_TREE);
22514 tree int64_ftype_v4sf
22515 = build_function_type_list (long_long_integer_type_node,
22516 V4SF_type_node, NULL_TREE);
22517 tree int_ftype_v8qi
22518 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
22519 tree v4sf_ftype_v4sf_int
22520 = build_function_type_list (V4SF_type_node,
22521 V4SF_type_node, integer_type_node, NULL_TREE);
22522 tree v4sf_ftype_v4sf_int64
22523 = build_function_type_list (V4SF_type_node,
22524 V4SF_type_node, long_long_integer_type_node,
22526 tree v4sf_ftype_v4sf_v2si
22527 = build_function_type_list (V4SF_type_node,
22528 V4SF_type_node, V2SI_type_node, NULL_TREE);
22530 /* Miscellaneous. */
22531 tree v8qi_ftype_v4hi_v4hi
22532 = build_function_type_list (V8QI_type_node,
22533 V4HI_type_node, V4HI_type_node, NULL_TREE);
22534 tree v4hi_ftype_v2si_v2si
22535 = build_function_type_list (V4HI_type_node,
22536 V2SI_type_node, V2SI_type_node, NULL_TREE);
22537 tree v4sf_ftype_v4sf_v4sf_int
22538 = build_function_type_list (V4SF_type_node,
22539 V4SF_type_node, V4SF_type_node,
22540 integer_type_node, NULL_TREE);
22541 tree v2si_ftype_v4hi_v4hi
22542 = build_function_type_list (V2SI_type_node,
22543 V4HI_type_node, V4HI_type_node, NULL_TREE);
22544 tree v4hi_ftype_v4hi_int
22545 = build_function_type_list (V4HI_type_node,
22546 V4HI_type_node, integer_type_node, NULL_TREE);
22547 tree v2si_ftype_v2si_int
22548 = build_function_type_list (V2SI_type_node,
22549 V2SI_type_node, integer_type_node, NULL_TREE);
22550 tree v1di_ftype_v1di_int
22551 = build_function_type_list (V1DI_type_node,
22552 V1DI_type_node, integer_type_node, NULL_TREE);
22554 tree void_ftype_void
22555 = build_function_type (void_type_node, void_list_node);
22556 tree void_ftype_unsigned
22557 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22558 tree void_ftype_unsigned_unsigned
22559 = build_function_type_list (void_type_node, unsigned_type_node,
22560 unsigned_type_node, NULL_TREE);
22561 tree void_ftype_pcvoid_unsigned_unsigned
22562 = build_function_type_list (void_type_node, const_ptr_type_node,
22563 unsigned_type_node, unsigned_type_node,
22565 tree unsigned_ftype_void
22566 = build_function_type (unsigned_type_node, void_list_node);
22567 tree v2si_ftype_v4sf
22568 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22569 /* Loads/stores. */
22570 tree void_ftype_v8qi_v8qi_pchar
22571 = build_function_type_list (void_type_node,
22572 V8QI_type_node, V8QI_type_node,
22573 pchar_type_node, NULL_TREE);
22574 tree v4sf_ftype_pcfloat
22575 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22576 tree v4sf_ftype_v4sf_pcv2sf
22577 = build_function_type_list (V4SF_type_node,
22578 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22579 tree void_ftype_pv2sf_v4sf
22580 = build_function_type_list (void_type_node,
22581 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22582 tree void_ftype_pfloat_v4sf
22583 = build_function_type_list (void_type_node,
22584 pfloat_type_node, V4SF_type_node, NULL_TREE);
22585 tree void_ftype_pdi_di
22586 = build_function_type_list (void_type_node,
22587 pdi_type_node, long_long_unsigned_type_node,
22589 tree void_ftype_pv2di_v2di
22590 = build_function_type_list (void_type_node,
22591 pv2di_type_node, V2DI_type_node, NULL_TREE);
22592 /* Normal vector unops. */
22593 tree v4sf_ftype_v4sf
22594 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22595 tree v16qi_ftype_v16qi
22596 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22597 tree v8hi_ftype_v8hi
22598 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22599 tree v4si_ftype_v4si
22600 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22601 tree v8qi_ftype_v8qi
22602 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22603 tree v4hi_ftype_v4hi
22604 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22606 /* Normal vector binops. */
22607 tree v4sf_ftype_v4sf_v4sf
22608 = build_function_type_list (V4SF_type_node,
22609 V4SF_type_node, V4SF_type_node, NULL_TREE);
22610 tree v8qi_ftype_v8qi_v8qi
22611 = build_function_type_list (V8QI_type_node,
22612 V8QI_type_node, V8QI_type_node, NULL_TREE);
22613 tree v4hi_ftype_v4hi_v4hi
22614 = build_function_type_list (V4HI_type_node,
22615 V4HI_type_node, V4HI_type_node, NULL_TREE);
22616 tree v2si_ftype_v2si_v2si
22617 = build_function_type_list (V2SI_type_node,
22618 V2SI_type_node, V2SI_type_node, NULL_TREE);
22619 tree v1di_ftype_v1di_v1di
22620 = build_function_type_list (V1DI_type_node,
22621 V1DI_type_node, V1DI_type_node, NULL_TREE);
22622 tree v1di_ftype_v1di_v1di_int
22623 = build_function_type_list (V1DI_type_node,
22624 V1DI_type_node, V1DI_type_node,
22625 integer_type_node, NULL_TREE);
22626 tree v2si_ftype_v2sf
22627 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22628 tree v2sf_ftype_v2si
22629 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22630 tree v2si_ftype_v2si
22631 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22632 tree v2sf_ftype_v2sf
22633 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22634 tree v2sf_ftype_v2sf_v2sf
22635 = build_function_type_list (V2SF_type_node,
22636 V2SF_type_node, V2SF_type_node, NULL_TREE);
22637 tree v2si_ftype_v2sf_v2sf
22638 = build_function_type_list (V2SI_type_node,
22639 V2SF_type_node, V2SF_type_node, NULL_TREE);
22640 tree pint_type_node = build_pointer_type (integer_type_node);
22641 tree pdouble_type_node = build_pointer_type (double_type_node);
22642 tree pcdouble_type_node = build_pointer_type (
22643 build_type_variant (double_type_node, 1, 0));
22644 tree int_ftype_v2df_v2df
22645 = build_function_type_list (integer_type_node,
22646 V2DF_type_node, V2DF_type_node, NULL_TREE);
22648 tree void_ftype_pcvoid
22649 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22650 tree v4sf_ftype_v4si
22651 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22652 tree v4si_ftype_v4sf
22653 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22654 tree v2df_ftype_v4si
22655 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22656 tree v4si_ftype_v2df
22657 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22658 tree v4si_ftype_v2df_v2df
22659 = build_function_type_list (V4SI_type_node,
22660 V2DF_type_node, V2DF_type_node, NULL_TREE);
22661 tree v2si_ftype_v2df
22662 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22663 tree v4sf_ftype_v2df
22664 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22665 tree v2df_ftype_v2si
22666 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22667 tree v2df_ftype_v4sf
22668 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22669 tree int_ftype_v2df
22670 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22671 tree int64_ftype_v2df
22672 = build_function_type_list (long_long_integer_type_node,
22673 V2DF_type_node, NULL_TREE);
22674 tree v2df_ftype_v2df_int
22675 = build_function_type_list (V2DF_type_node,
22676 V2DF_type_node, integer_type_node, NULL_TREE);
22677 tree v2df_ftype_v2df_int64
22678 = build_function_type_list (V2DF_type_node,
22679 V2DF_type_node, long_long_integer_type_node,
22681 tree v4sf_ftype_v4sf_v2df
22682 = build_function_type_list (V4SF_type_node,
22683 V4SF_type_node, V2DF_type_node, NULL_TREE);
22684 tree v2df_ftype_v2df_v4sf
22685 = build_function_type_list (V2DF_type_node,
22686 V2DF_type_node, V4SF_type_node, NULL_TREE);
22687 tree v2df_ftype_v2df_v2df_int
22688 = build_function_type_list (V2DF_type_node,
22689 V2DF_type_node, V2DF_type_node,
22692 tree v2df_ftype_v2df_pcdouble
22693 = build_function_type_list (V2DF_type_node,
22694 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22695 tree void_ftype_pdouble_v2df
22696 = build_function_type_list (void_type_node,
22697 pdouble_type_node, V2DF_type_node, NULL_TREE);
22698 tree void_ftype_pint_int
22699 = build_function_type_list (void_type_node,
22700 pint_type_node, integer_type_node, NULL_TREE);
22701 tree void_ftype_v16qi_v16qi_pchar
22702 = build_function_type_list (void_type_node,
22703 V16QI_type_node, V16QI_type_node,
22704 pchar_type_node, NULL_TREE);
22705 tree v2df_ftype_pcdouble
22706 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22707 tree v2df_ftype_v2df_v2df
22708 = build_function_type_list (V2DF_type_node,
22709 V2DF_type_node, V2DF_type_node, NULL_TREE);
22710 tree v16qi_ftype_v16qi_v16qi
22711 = build_function_type_list (V16QI_type_node,
22712 V16QI_type_node, V16QI_type_node, NULL_TREE);
22713 tree v8hi_ftype_v8hi_v8hi
22714 = build_function_type_list (V8HI_type_node,
22715 V8HI_type_node, V8HI_type_node, NULL_TREE);
22716 tree v4si_ftype_v4si_v4si
22717 = build_function_type_list (V4SI_type_node,
22718 V4SI_type_node, V4SI_type_node, NULL_TREE);
22719 tree v2di_ftype_v2di_v2di
22720 = build_function_type_list (V2DI_type_node,
22721 V2DI_type_node, V2DI_type_node, NULL_TREE);
22722 tree v2di_ftype_v2df_v2df
22723 = build_function_type_list (V2DI_type_node,
22724 V2DF_type_node, V2DF_type_node, NULL_TREE);
22725 tree v2df_ftype_v2df
22726 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22727 tree v2di_ftype_v2di_int
22728 = build_function_type_list (V2DI_type_node,
22729 V2DI_type_node, integer_type_node, NULL_TREE);
22730 tree v2di_ftype_v2di_v2di_int
22731 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22732 V2DI_type_node, integer_type_node, NULL_TREE);
22733 tree v4si_ftype_v4si_int
22734 = build_function_type_list (V4SI_type_node,
22735 V4SI_type_node, integer_type_node, NULL_TREE);
22736 tree v8hi_ftype_v8hi_int
22737 = build_function_type_list (V8HI_type_node,
22738 V8HI_type_node, integer_type_node, NULL_TREE);
22739 tree v4si_ftype_v8hi_v8hi
22740 = build_function_type_list (V4SI_type_node,
22741 V8HI_type_node, V8HI_type_node, NULL_TREE);
22742 tree v1di_ftype_v8qi_v8qi
22743 = build_function_type_list (V1DI_type_node,
22744 V8QI_type_node, V8QI_type_node, NULL_TREE);
22745 tree v1di_ftype_v2si_v2si
22746 = build_function_type_list (V1DI_type_node,
22747 V2SI_type_node, V2SI_type_node, NULL_TREE);
22748 tree v2di_ftype_v16qi_v16qi
22749 = build_function_type_list (V2DI_type_node,
22750 V16QI_type_node, V16QI_type_node, NULL_TREE);
22751 tree v2di_ftype_v4si_v4si
22752 = build_function_type_list (V2DI_type_node,
22753 V4SI_type_node, V4SI_type_node, NULL_TREE);
22754 tree int_ftype_v16qi
22755 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22756 tree v16qi_ftype_pcchar
22757 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22758 tree void_ftype_pchar_v16qi
22759 = build_function_type_list (void_type_node,
22760 pchar_type_node, V16QI_type_node, NULL_TREE);
22762 tree v2di_ftype_v2di_unsigned_unsigned
22763 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22764 unsigned_type_node, unsigned_type_node,
22766 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22767 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22768 unsigned_type_node, unsigned_type_node,
22770 tree v2di_ftype_v2di_v16qi
22771 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22773 tree v2df_ftype_v2df_v2df_v2df
22774 = build_function_type_list (V2DF_type_node,
22775 V2DF_type_node, V2DF_type_node,
22776 V2DF_type_node, NULL_TREE);
22777 tree v4sf_ftype_v4sf_v4sf_v4sf
22778 = build_function_type_list (V4SF_type_node,
22779 V4SF_type_node, V4SF_type_node,
22780 V4SF_type_node, NULL_TREE);
22781 tree v8hi_ftype_v16qi
22782 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22784 tree v4si_ftype_v16qi
22785 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22787 tree v2di_ftype_v16qi
22788 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22790 tree v4si_ftype_v8hi
22791 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22793 tree v2di_ftype_v8hi
22794 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22796 tree v2di_ftype_v4si
22797 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22799 tree v2di_ftype_pv2di
22800 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22802 tree v16qi_ftype_v16qi_v16qi_int
22803 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22804 V16QI_type_node, integer_type_node,
22806 tree v16qi_ftype_v16qi_v16qi_v16qi
22807 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22808 V16QI_type_node, V16QI_type_node,
22810 tree v8hi_ftype_v8hi_v8hi_int
22811 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22812 V8HI_type_node, integer_type_node,
22814 tree v4si_ftype_v4si_v4si_int
22815 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22816 V4SI_type_node, integer_type_node,
22818 tree int_ftype_v2di_v2di
22819 = build_function_type_list (integer_type_node,
22820 V2DI_type_node, V2DI_type_node,
22822 tree int_ftype_v16qi_int_v16qi_int_int
22823 = build_function_type_list (integer_type_node,
22830 tree v16qi_ftype_v16qi_int_v16qi_int_int
22831 = build_function_type_list (V16QI_type_node,
22838 tree int_ftype_v16qi_v16qi_int
22839 = build_function_type_list (integer_type_node,
22846 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22848 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22850 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22852 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22854 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22856 tree V16HI_type_node = build_vector_type_for_mode (intHI_type_node,
22858 tree v8sf_ftype_v8sf
22859 = build_function_type_list (V8SF_type_node,
22862 tree v8si_ftype_v8sf
22863 = build_function_type_list (V8SI_type_node,
22866 tree v8sf_ftype_v8si
22867 = build_function_type_list (V8SF_type_node,
22870 tree v4si_ftype_v4df
22871 = build_function_type_list (V4SI_type_node,
22874 tree v4df_ftype_v4df
22875 = build_function_type_list (V4DF_type_node,
22878 tree v4df_ftype_v4si
22879 = build_function_type_list (V4DF_type_node,
22882 tree v4df_ftype_v4sf
22883 = build_function_type_list (V4DF_type_node,
22886 tree v4sf_ftype_v4df
22887 = build_function_type_list (V4SF_type_node,
22890 tree v8sf_ftype_v8sf_v8sf
22891 = build_function_type_list (V8SF_type_node,
22892 V8SF_type_node, V8SF_type_node,
22894 tree v4df_ftype_v4df_v4df
22895 = build_function_type_list (V4DF_type_node,
22896 V4DF_type_node, V4DF_type_node,
22898 tree v8sf_ftype_v8sf_int
22899 = build_function_type_list (V8SF_type_node,
22900 V8SF_type_node, integer_type_node,
22902 tree v4si_ftype_v8si_int
22903 = build_function_type_list (V4SI_type_node,
22904 V8SI_type_node, integer_type_node,
22906 tree v4df_ftype_v4df_int
22907 = build_function_type_list (V4DF_type_node,
22908 V4DF_type_node, integer_type_node,
22910 tree v4sf_ftype_v8sf_int
22911 = build_function_type_list (V4SF_type_node,
22912 V8SF_type_node, integer_type_node,
22914 tree v2df_ftype_v4df_int
22915 = build_function_type_list (V2DF_type_node,
22916 V4DF_type_node, integer_type_node,
22918 tree v8sf_ftype_v8sf_v8sf_int
22919 = build_function_type_list (V8SF_type_node,
22920 V8SF_type_node, V8SF_type_node,
22923 tree v8sf_ftype_v8sf_v8sf_v8sf
22924 = build_function_type_list (V8SF_type_node,
22925 V8SF_type_node, V8SF_type_node,
22928 tree v4df_ftype_v4df_v4df_v4df
22929 = build_function_type_list (V4DF_type_node,
22930 V4DF_type_node, V4DF_type_node,
22933 tree v8si_ftype_v8si_v8si_int
22934 = build_function_type_list (V8SI_type_node,
22935 V8SI_type_node, V8SI_type_node,
22938 tree v4df_ftype_v4df_v4df_int
22939 = build_function_type_list (V4DF_type_node,
22940 V4DF_type_node, V4DF_type_node,
22943 tree v8sf_ftype_pcfloat
22944 = build_function_type_list (V8SF_type_node,
22947 tree v4df_ftype_pcdouble
22948 = build_function_type_list (V4DF_type_node,
22949 pcdouble_type_node,
22951 tree pcv4sf_type_node
22952 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22953 tree pcv2df_type_node
22954 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22955 tree v8sf_ftype_pcv4sf
22956 = build_function_type_list (V8SF_type_node,
22959 tree v4df_ftype_pcv2df
22960 = build_function_type_list (V4DF_type_node,
22963 tree v32qi_ftype_pcchar
22964 = build_function_type_list (V32QI_type_node,
22967 tree void_ftype_pchar_v32qi
22968 = build_function_type_list (void_type_node,
22969 pchar_type_node, V32QI_type_node,
22971 tree v8si_ftype_v8si_v4si_int
22972 = build_function_type_list (V8SI_type_node,
22973 V8SI_type_node, V4SI_type_node,
22976 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22977 tree void_ftype_pv4di_v4di
22978 = build_function_type_list (void_type_node,
22979 pv4di_type_node, V4DI_type_node,
22981 tree v8sf_ftype_v8sf_v4sf_int
22982 = build_function_type_list (V8SF_type_node,
22983 V8SF_type_node, V4SF_type_node,
22986 tree v4df_ftype_v4df_v2df_int
22987 = build_function_type_list (V4DF_type_node,
22988 V4DF_type_node, V2DF_type_node,
22991 tree void_ftype_pfloat_v8sf
22992 = build_function_type_list (void_type_node,
22993 pfloat_type_node, V8SF_type_node,
22995 tree void_ftype_pdouble_v4df
22996 = build_function_type_list (void_type_node,
22997 pdouble_type_node, V4DF_type_node,
22999 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
23000 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
23001 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
23002 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
23003 tree pcv8sf_type_node
23004 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
23005 tree pcv4df_type_node
23006 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
23007 tree v8sf_ftype_pcv8sf_v8sf
23008 = build_function_type_list (V8SF_type_node,
23009 pcv8sf_type_node, V8SF_type_node,
23011 tree v4df_ftype_pcv4df_v4df
23012 = build_function_type_list (V4DF_type_node,
23013 pcv4df_type_node, V4DF_type_node,
23015 tree v4sf_ftype_pcv4sf_v4sf
23016 = build_function_type_list (V4SF_type_node,
23017 pcv4sf_type_node, V4SF_type_node,
23019 tree v2df_ftype_pcv2df_v2df
23020 = build_function_type_list (V2DF_type_node,
23021 pcv2df_type_node, V2DF_type_node,
23023 tree void_ftype_pv8sf_v8sf_v8sf
23024 = build_function_type_list (void_type_node,
23025 pv8sf_type_node, V8SF_type_node,
23028 tree void_ftype_pv4df_v4df_v4df
23029 = build_function_type_list (void_type_node,
23030 pv4df_type_node, V4DF_type_node,
23033 tree void_ftype_pv4sf_v4sf_v4sf
23034 = build_function_type_list (void_type_node,
23035 pv4sf_type_node, V4SF_type_node,
23038 tree void_ftype_pv2df_v2df_v2df
23039 = build_function_type_list (void_type_node,
23040 pv2df_type_node, V2DF_type_node,
23043 tree v4df_ftype_v2df
23044 = build_function_type_list (V4DF_type_node,
23047 tree v8sf_ftype_v4sf
23048 = build_function_type_list (V8SF_type_node,
23051 tree v8si_ftype_v4si
23052 = build_function_type_list (V8SI_type_node,
23055 tree v2df_ftype_v4df
23056 = build_function_type_list (V2DF_type_node,
23059 tree v4sf_ftype_v8sf
23060 = build_function_type_list (V4SF_type_node,
23063 tree v4si_ftype_v8si
23064 = build_function_type_list (V4SI_type_node,
23067 tree int_ftype_v4df
23068 = build_function_type_list (integer_type_node,
23071 tree int_ftype_v8sf
23072 = build_function_type_list (integer_type_node,
23075 tree int_ftype_v8sf_v8sf
23076 = build_function_type_list (integer_type_node,
23077 V8SF_type_node, V8SF_type_node,
23079 tree int_ftype_v4di_v4di
23080 = build_function_type_list (integer_type_node,
23081 V4DI_type_node, V4DI_type_node,
23083 tree int_ftype_v4df_v4df
23084 = build_function_type_list (integer_type_node,
23085 V4DF_type_node, V4DF_type_node,
23087 tree v8sf_ftype_v8sf_v8si
23088 = build_function_type_list (V8SF_type_node,
23089 V8SF_type_node, V8SI_type_node,
23091 tree v4df_ftype_v4df_v4di
23092 = build_function_type_list (V4DF_type_node,
23093 V4DF_type_node, V4DI_type_node,
23095 tree v4sf_ftype_v4sf_v4si
23096 = build_function_type_list (V4SF_type_node,
23097 V4SF_type_node, V4SI_type_node, NULL_TREE);
23098 tree v2df_ftype_v2df_v2di
23099 = build_function_type_list (V2DF_type_node,
23100 V2DF_type_node, V2DI_type_node, NULL_TREE);
23102 /* XOP instructions */
23103 tree v2di_ftype_v2di_v2di_v2di
23104 = build_function_type_list (V2DI_type_node,
23110 tree v4di_ftype_v4di_v4di_v4di
23111 = build_function_type_list (V4DI_type_node,
23117 tree v4si_ftype_v4si_v4si_v4si
23118 = build_function_type_list (V4SI_type_node,
23124 tree v8si_ftype_v8si_v8si_v8si
23125 = build_function_type_list (V8SI_type_node,
23131 tree v32qi_ftype_v32qi_v32qi_v32qi
23132 = build_function_type_list (V32QI_type_node,
23138 tree v4si_ftype_v4si_v4si_v2di
23139 = build_function_type_list (V4SI_type_node,
23145 tree v8hi_ftype_v8hi_v8hi_v8hi
23146 = build_function_type_list (V8HI_type_node,
23152 tree v16hi_ftype_v16hi_v16hi_v16hi
23153 = build_function_type_list (V16HI_type_node,
23159 tree v8hi_ftype_v8hi_v8hi_v4si
23160 = build_function_type_list (V8HI_type_node,
23166 tree v2di_ftype_v2di_si
23167 = build_function_type_list (V2DI_type_node,
23172 tree v4si_ftype_v4si_si
23173 = build_function_type_list (V4SI_type_node,
23178 tree v8hi_ftype_v8hi_si
23179 = build_function_type_list (V8HI_type_node,
23184 tree v16qi_ftype_v16qi_si
23185 = build_function_type_list (V16QI_type_node,
23190 tree v2di_ftype_v2di
23191 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
23193 tree v16qi_ftype_v8hi_v8hi
23194 = build_function_type_list (V16QI_type_node,
23195 V8HI_type_node, V8HI_type_node,
23197 tree v8hi_ftype_v4si_v4si
23198 = build_function_type_list (V8HI_type_node,
23199 V4SI_type_node, V4SI_type_node,
23201 tree v8hi_ftype_v16qi_v16qi
23202 = build_function_type_list (V8HI_type_node,
23203 V16QI_type_node, V16QI_type_node,
23205 tree v4hi_ftype_v8qi_v8qi
23206 = build_function_type_list (V4HI_type_node,
23207 V8QI_type_node, V8QI_type_node,
23209 tree unsigned_ftype_unsigned_uchar
23210 = build_function_type_list (unsigned_type_node,
23211 unsigned_type_node,
23212 unsigned_char_type_node,
23214 tree unsigned_ftype_unsigned_ushort
23215 = build_function_type_list (unsigned_type_node,
23216 unsigned_type_node,
23217 short_unsigned_type_node,
23219 tree unsigned_ftype_unsigned_unsigned
23220 = build_function_type_list (unsigned_type_node,
23221 unsigned_type_node,
23222 unsigned_type_node,
23224 tree uint64_ftype_uint64_uint64
23225 = build_function_type_list (long_long_unsigned_type_node,
23226 long_long_unsigned_type_node,
23227 long_long_unsigned_type_node,
23229 tree float_ftype_float
23230 = build_function_type_list (float_type_node,
23234 /* Integer intrinsics. */
23235 tree uint64_ftype_void
23236 = build_function_type (long_long_unsigned_type_node,
23239 = build_function_type_list (integer_type_node,
23240 integer_type_node, NULL_TREE);
23241 tree int64_ftype_int64
23242 = build_function_type_list (long_long_integer_type_node,
23243 long_long_integer_type_node,
23245 tree uint64_ftype_int
23246 = build_function_type_list (long_long_unsigned_type_node,
23247 integer_type_node, NULL_TREE);
23248 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
23249 tree uint64_ftype_punsigned
23250 = build_function_type_list (long_long_unsigned_type_node,
23251 punsigned_type_node, NULL_TREE);
23252 tree ushort_ftype_ushort_int
23253 = build_function_type_list (short_unsigned_type_node,
23254 short_unsigned_type_node,
23257 tree uchar_ftype_uchar_int
23258 = build_function_type_list (unsigned_char_type_node,
23259 unsigned_char_type_node,
23263 /* LWP instructions. */
23265 tree void_ftype_ushort_unsigned_ushort
23266 = build_function_type_list (void_type_node,
23267 short_unsigned_type_node,
23268 unsigned_type_node,
23269 short_unsigned_type_node,
23272 tree void_ftype_unsigned_unsigned_unsigned
23273 = build_function_type_list (void_type_node,
23274 unsigned_type_node,
23275 unsigned_type_node,
23276 unsigned_type_node,
23279 tree void_ftype_uint64_unsigned_unsigned
23280 = build_function_type_list (void_type_node,
23281 long_long_unsigned_type_node,
23282 unsigned_type_node,
23283 unsigned_type_node,
23286 tree uchar_ftype_ushort_unsigned_ushort
23287 = build_function_type_list (unsigned_char_type_node,
23288 short_unsigned_type_node,
23289 unsigned_type_node,
23290 short_unsigned_type_node,
23293 tree uchar_ftype_unsigned_unsigned_unsigned
23294 = build_function_type_list (unsigned_char_type_node,
23295 unsigned_type_node,
23296 unsigned_type_node,
23297 unsigned_type_node,
23300 tree uchar_ftype_uint64_unsigned_unsigned
23301 = build_function_type_list (unsigned_char_type_node,
23302 long_long_unsigned_type_node,
23303 unsigned_type_node,
23304 unsigned_type_node,
23309 /* Add all special builtins with variable number of operands. */
23310 for (i = 0, d = bdesc_special_args;
23311 i < ARRAY_SIZE (bdesc_special_args);
23319 switch ((enum ix86_special_builtin_type) d->flag)
23321 case VOID_FTYPE_VOID:
23322 type = void_ftype_void;
23324 case UINT64_FTYPE_VOID:
23325 type = uint64_ftype_void;
23327 case UINT64_FTYPE_PUNSIGNED:
23328 type = uint64_ftype_punsigned;
23330 case V32QI_FTYPE_PCCHAR:
23331 type = v32qi_ftype_pcchar;
23333 case V16QI_FTYPE_PCCHAR:
23334 type = v16qi_ftype_pcchar;
23336 case V8SF_FTYPE_PCV4SF:
23337 type = v8sf_ftype_pcv4sf;
23339 case V8SF_FTYPE_PCFLOAT:
23340 type = v8sf_ftype_pcfloat;
23342 case V4DF_FTYPE_PCV2DF:
23343 type = v4df_ftype_pcv2df;
23345 case V4DF_FTYPE_PCDOUBLE:
23346 type = v4df_ftype_pcdouble;
23348 case V4SF_FTYPE_PCFLOAT:
23349 type = v4sf_ftype_pcfloat;
23351 case V2DI_FTYPE_PV2DI:
23352 type = v2di_ftype_pv2di;
23354 case V2DF_FTYPE_PCDOUBLE:
23355 type = v2df_ftype_pcdouble;
23357 case V8SF_FTYPE_PCV8SF_V8SF:
23358 type = v8sf_ftype_pcv8sf_v8sf;
23360 case V4DF_FTYPE_PCV4DF_V4DF:
23361 type = v4df_ftype_pcv4df_v4df;
23363 case V4SF_FTYPE_V4SF_PCV2SF:
23364 type = v4sf_ftype_v4sf_pcv2sf;
23366 case V4SF_FTYPE_PCV4SF_V4SF:
23367 type = v4sf_ftype_pcv4sf_v4sf;
23369 case V2DF_FTYPE_V2DF_PCDOUBLE:
23370 type = v2df_ftype_v2df_pcdouble;
23372 case V2DF_FTYPE_PCV2DF_V2DF:
23373 type = v2df_ftype_pcv2df_v2df;
23375 case VOID_FTYPE_PV2SF_V4SF:
23376 type = void_ftype_pv2sf_v4sf;
23378 case VOID_FTYPE_PV4DI_V4DI:
23379 type = void_ftype_pv4di_v4di;
23381 case VOID_FTYPE_PV2DI_V2DI:
23382 type = void_ftype_pv2di_v2di;
23384 case VOID_FTYPE_PCHAR_V32QI:
23385 type = void_ftype_pchar_v32qi;
23387 case VOID_FTYPE_PCHAR_V16QI:
23388 type = void_ftype_pchar_v16qi;
23390 case VOID_FTYPE_PFLOAT_V8SF:
23391 type = void_ftype_pfloat_v8sf;
23393 case VOID_FTYPE_PFLOAT_V4SF:
23394 type = void_ftype_pfloat_v4sf;
23396 case VOID_FTYPE_PDOUBLE_V4DF:
23397 type = void_ftype_pdouble_v4df;
23399 case VOID_FTYPE_PDOUBLE_V2DF:
23400 type = void_ftype_pdouble_v2df;
23402 case VOID_FTYPE_PDI_DI:
23403 type = void_ftype_pdi_di;
23405 case VOID_FTYPE_PINT_INT:
23406 type = void_ftype_pint_int;
23408 case VOID_FTYPE_PV8SF_V8SF_V8SF:
23409 type = void_ftype_pv8sf_v8sf_v8sf;
23411 case VOID_FTYPE_PV4DF_V4DF_V4DF:
23412 type = void_ftype_pv4df_v4df_v4df;
23414 case VOID_FTYPE_PV4SF_V4SF_V4SF:
23415 type = void_ftype_pv4sf_v4sf_v4sf;
23417 case VOID_FTYPE_PV2DF_V2DF_V2DF:
23418 type = void_ftype_pv2df_v2df_v2df;
23420 case VOID_FTYPE_USHORT_UINT_USHORT:
23421 type = void_ftype_ushort_unsigned_ushort;
23423 case VOID_FTYPE_UINT_UINT_UINT:
23424 type = void_ftype_unsigned_unsigned_unsigned;
23426 case VOID_FTYPE_UINT64_UINT_UINT:
23427 type = void_ftype_uint64_unsigned_unsigned;
23429 case UCHAR_FTYPE_USHORT_UINT_USHORT:
23430 type = uchar_ftype_ushort_unsigned_ushort;
23432 case UCHAR_FTYPE_UINT_UINT_UINT:
23433 type = uchar_ftype_unsigned_unsigned_unsigned;
23435 case UCHAR_FTYPE_UINT64_UINT_UINT:
23436 type = uchar_ftype_uint64_unsigned_unsigned;
23440 gcc_unreachable ();
23443 def_builtin (d->mask, d->name, type, d->code);
23446 /* Add all builtins with variable number of operands. */
23447 for (i = 0, d = bdesc_args;
23448 i < ARRAY_SIZE (bdesc_args);
23456 switch ((enum ix86_builtin_type) d->flag)
23458 case FLOAT_FTYPE_FLOAT:
23459 type = float_ftype_float;
23461 case INT_FTYPE_V8SF_V8SF_PTEST:
23462 type = int_ftype_v8sf_v8sf;
23464 case INT_FTYPE_V4DI_V4DI_PTEST:
23465 type = int_ftype_v4di_v4di;
23467 case INT_FTYPE_V4DF_V4DF_PTEST:
23468 type = int_ftype_v4df_v4df;
23470 case INT_FTYPE_V4SF_V4SF_PTEST:
23471 type = int_ftype_v4sf_v4sf;
23473 case INT_FTYPE_V2DI_V2DI_PTEST:
23474 type = int_ftype_v2di_v2di;
23476 case INT_FTYPE_V2DF_V2DF_PTEST:
23477 type = int_ftype_v2df_v2df;
23479 case INT_FTYPE_INT:
23480 type = int_ftype_int;
23482 case UINT64_FTYPE_INT:
23483 type = uint64_ftype_int;
23485 case INT64_FTYPE_INT64:
23486 type = int64_ftype_int64;
23488 case INT64_FTYPE_V4SF:
23489 type = int64_ftype_v4sf;
23491 case INT64_FTYPE_V2DF:
23492 type = int64_ftype_v2df;
23494 case INT_FTYPE_V16QI:
23495 type = int_ftype_v16qi;
23497 case INT_FTYPE_V8QI:
23498 type = int_ftype_v8qi;
23500 case INT_FTYPE_V8SF:
23501 type = int_ftype_v8sf;
23503 case INT_FTYPE_V4DF:
23504 type = int_ftype_v4df;
23506 case INT_FTYPE_V4SF:
23507 type = int_ftype_v4sf;
23509 case INT_FTYPE_V2DF:
23510 type = int_ftype_v2df;
23512 case V16QI_FTYPE_V16QI:
23513 type = v16qi_ftype_v16qi;
23515 case V8SI_FTYPE_V8SF:
23516 type = v8si_ftype_v8sf;
23518 case V8SI_FTYPE_V4SI:
23519 type = v8si_ftype_v4si;
23521 case V8HI_FTYPE_V8HI:
23522 type = v8hi_ftype_v8hi;
23524 case V8HI_FTYPE_V16QI:
23525 type = v8hi_ftype_v16qi;
23527 case V8QI_FTYPE_V8QI:
23528 type = v8qi_ftype_v8qi;
23530 case V8SF_FTYPE_V8SF:
23531 type = v8sf_ftype_v8sf;
23533 case V8SF_FTYPE_V8SI:
23534 type = v8sf_ftype_v8si;
23536 case V8SF_FTYPE_V4SF:
23537 type = v8sf_ftype_v4sf;
23539 case V4SI_FTYPE_V4DF:
23540 type = v4si_ftype_v4df;
23542 case V4SI_FTYPE_V4SI:
23543 type = v4si_ftype_v4si;
23545 case V4SI_FTYPE_V16QI:
23546 type = v4si_ftype_v16qi;
23548 case V4SI_FTYPE_V8SI:
23549 type = v4si_ftype_v8si;
23551 case V4SI_FTYPE_V8HI:
23552 type = v4si_ftype_v8hi;
23554 case V4SI_FTYPE_V4SF:
23555 type = v4si_ftype_v4sf;
23557 case V4SI_FTYPE_V2DF:
23558 type = v4si_ftype_v2df;
23560 case V4HI_FTYPE_V4HI:
23561 type = v4hi_ftype_v4hi;
23563 case V4DF_FTYPE_V4DF:
23564 type = v4df_ftype_v4df;
23566 case V4DF_FTYPE_V4SI:
23567 type = v4df_ftype_v4si;
23569 case V4DF_FTYPE_V4SF:
23570 type = v4df_ftype_v4sf;
23572 case V4DF_FTYPE_V2DF:
23573 type = v4df_ftype_v2df;
23575 case V4SF_FTYPE_V4SF:
23576 case V4SF_FTYPE_V4SF_VEC_MERGE:
23577 type = v4sf_ftype_v4sf;
23579 case V4SF_FTYPE_V8SF:
23580 type = v4sf_ftype_v8sf;
23582 case V4SF_FTYPE_V4SI:
23583 type = v4sf_ftype_v4si;
23585 case V4SF_FTYPE_V4DF:
23586 type = v4sf_ftype_v4df;
23588 case V4SF_FTYPE_V2DF:
23589 type = v4sf_ftype_v2df;
23591 case V2DI_FTYPE_V2DI:
23592 type = v2di_ftype_v2di;
23594 case V2DI_FTYPE_V16QI:
23595 type = v2di_ftype_v16qi;
23597 case V2DI_FTYPE_V8HI:
23598 type = v2di_ftype_v8hi;
23600 case V2DI_FTYPE_V4SI:
23601 type = v2di_ftype_v4si;
23603 case V2SI_FTYPE_V2SI:
23604 type = v2si_ftype_v2si;
23606 case V2SI_FTYPE_V4SF:
23607 type = v2si_ftype_v4sf;
23609 case V2SI_FTYPE_V2DF:
23610 type = v2si_ftype_v2df;
23612 case V2SI_FTYPE_V2SF:
23613 type = v2si_ftype_v2sf;
23615 case V2DF_FTYPE_V4DF:
23616 type = v2df_ftype_v4df;
23618 case V2DF_FTYPE_V4SF:
23619 type = v2df_ftype_v4sf;
23621 case V2DF_FTYPE_V2DF:
23622 case V2DF_FTYPE_V2DF_VEC_MERGE:
23623 type = v2df_ftype_v2df;
23625 case V2DF_FTYPE_V2SI:
23626 type = v2df_ftype_v2si;
23628 case V2DF_FTYPE_V4SI:
23629 type = v2df_ftype_v4si;
23631 case V2SF_FTYPE_V2SF:
23632 type = v2sf_ftype_v2sf;
23634 case V2SF_FTYPE_V2SI:
23635 type = v2sf_ftype_v2si;
23637 case V16QI_FTYPE_V16QI_V16QI:
23638 type = v16qi_ftype_v16qi_v16qi;
23640 case V16QI_FTYPE_V8HI_V8HI:
23641 type = v16qi_ftype_v8hi_v8hi;
23643 case V8QI_FTYPE_V8QI_V8QI:
23644 type = v8qi_ftype_v8qi_v8qi;
23646 case V8QI_FTYPE_V4HI_V4HI:
23647 type = v8qi_ftype_v4hi_v4hi;
23649 case V8HI_FTYPE_V8HI_V8HI:
23650 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23651 type = v8hi_ftype_v8hi_v8hi;
23653 case V8HI_FTYPE_V16QI_V16QI:
23654 type = v8hi_ftype_v16qi_v16qi;
23656 case V8HI_FTYPE_V4SI_V4SI:
23657 type = v8hi_ftype_v4si_v4si;
23659 case V8HI_FTYPE_V8HI_SI_COUNT:
23660 type = v8hi_ftype_v8hi_int;
23662 case V8SF_FTYPE_V8SF_V8SF:
23663 type = v8sf_ftype_v8sf_v8sf;
23665 case V8SF_FTYPE_V8SF_V8SI:
23666 type = v8sf_ftype_v8sf_v8si;
23668 case V4SI_FTYPE_V4SI_V4SI:
23669 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23670 type = v4si_ftype_v4si_v4si;
23672 case V4SI_FTYPE_V8HI_V8HI:
23673 type = v4si_ftype_v8hi_v8hi;
23675 case V4SI_FTYPE_V4SF_V4SF:
23676 type = v4si_ftype_v4sf_v4sf;
23678 case V4SI_FTYPE_V2DF_V2DF:
23679 type = v4si_ftype_v2df_v2df;
23681 case V4SI_FTYPE_V4SI_SI_COUNT:
23682 type = v4si_ftype_v4si_int;
23684 case V4HI_FTYPE_V4HI_V4HI:
23685 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23686 type = v4hi_ftype_v4hi_v4hi;
23688 case V4HI_FTYPE_V8QI_V8QI:
23689 type = v4hi_ftype_v8qi_v8qi;
23691 case V4HI_FTYPE_V2SI_V2SI:
23692 type = v4hi_ftype_v2si_v2si;
23694 case V4HI_FTYPE_V4HI_SI_COUNT:
23695 type = v4hi_ftype_v4hi_int;
23697 case V4DF_FTYPE_V4DF_V4DF:
23698 type = v4df_ftype_v4df_v4df;
23700 case V4DF_FTYPE_V4DF_V4DI:
23701 type = v4df_ftype_v4df_v4di;
23703 case V4SF_FTYPE_V4SF_V4SF:
23704 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23705 type = v4sf_ftype_v4sf_v4sf;
23707 case V4SF_FTYPE_V4SF_V4SI:
23708 type = v4sf_ftype_v4sf_v4si;
23710 case V4SF_FTYPE_V4SF_V2SI:
23711 type = v4sf_ftype_v4sf_v2si;
23713 case V4SF_FTYPE_V4SF_V2DF:
23714 type = v4sf_ftype_v4sf_v2df;
23716 case V4SF_FTYPE_V4SF_DI:
23717 type = v4sf_ftype_v4sf_int64;
23719 case V4SF_FTYPE_V4SF_SI:
23720 type = v4sf_ftype_v4sf_int;
23722 case V2DI_FTYPE_V2DI_V2DI:
23723 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23724 type = v2di_ftype_v2di_v2di;
23726 case V2DI_FTYPE_V16QI_V16QI:
23727 type = v2di_ftype_v16qi_v16qi;
23729 case V2DI_FTYPE_V4SI_V4SI:
23730 type = v2di_ftype_v4si_v4si;
23732 case V2DI_FTYPE_V2DI_V16QI:
23733 type = v2di_ftype_v2di_v16qi;
23735 case V2DI_FTYPE_V2DF_V2DF:
23736 type = v2di_ftype_v2df_v2df;
23738 case V2DI_FTYPE_V2DI_SI_COUNT:
23739 type = v2di_ftype_v2di_int;
23741 case V2SI_FTYPE_V2SI_V2SI:
23742 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23743 type = v2si_ftype_v2si_v2si;
23745 case V2SI_FTYPE_V4HI_V4HI:
23746 type = v2si_ftype_v4hi_v4hi;
23748 case V2SI_FTYPE_V2SF_V2SF:
23749 type = v2si_ftype_v2sf_v2sf;
23751 case V2SI_FTYPE_V2SI_SI_COUNT:
23752 type = v2si_ftype_v2si_int;
23754 case V2DF_FTYPE_V2DF_V2DF:
23755 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23756 type = v2df_ftype_v2df_v2df;
23758 case V2DF_FTYPE_V2DF_V4SF:
23759 type = v2df_ftype_v2df_v4sf;
23761 case V2DF_FTYPE_V2DF_V2DI:
23762 type = v2df_ftype_v2df_v2di;
23764 case V2DF_FTYPE_V2DF_DI:
23765 type = v2df_ftype_v2df_int64;
23767 case V2DF_FTYPE_V2DF_SI:
23768 type = v2df_ftype_v2df_int;
23770 case V2SF_FTYPE_V2SF_V2SF:
23771 type = v2sf_ftype_v2sf_v2sf;
23773 case V1DI_FTYPE_V1DI_V1DI:
23774 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23775 type = v1di_ftype_v1di_v1di;
23777 case V1DI_FTYPE_V8QI_V8QI:
23778 type = v1di_ftype_v8qi_v8qi;
23780 case V1DI_FTYPE_V2SI_V2SI:
23781 type = v1di_ftype_v2si_v2si;
23783 case V1DI_FTYPE_V1DI_SI_COUNT:
23784 type = v1di_ftype_v1di_int;
23786 case UINT64_FTYPE_UINT64_UINT64:
23787 type = uint64_ftype_uint64_uint64;
23789 case UINT_FTYPE_UINT_UINT:
23790 type = unsigned_ftype_unsigned_unsigned;
23792 case UINT_FTYPE_UINT_USHORT:
23793 type = unsigned_ftype_unsigned_ushort;
23795 case UINT_FTYPE_UINT_UCHAR:
23796 type = unsigned_ftype_unsigned_uchar;
23798 case UINT16_FTYPE_UINT16_INT:
23799 type = ushort_ftype_ushort_int;
23801 case UINT8_FTYPE_UINT8_INT:
23802 type = uchar_ftype_uchar_int;
23804 case V8HI_FTYPE_V8HI_INT:
23805 type = v8hi_ftype_v8hi_int;
23807 case V8SF_FTYPE_V8SF_INT:
23808 type = v8sf_ftype_v8sf_int;
23810 case V4SI_FTYPE_V4SI_INT:
23811 type = v4si_ftype_v4si_int;
23813 case V4SI_FTYPE_V8SI_INT:
23814 type = v4si_ftype_v8si_int;
23816 case V4HI_FTYPE_V4HI_INT:
23817 type = v4hi_ftype_v4hi_int;
23819 case V4DF_FTYPE_V4DF_INT:
23820 type = v4df_ftype_v4df_int;
23822 case V4SF_FTYPE_V4SF_INT:
23823 type = v4sf_ftype_v4sf_int;
23825 case V4SF_FTYPE_V8SF_INT:
23826 type = v4sf_ftype_v8sf_int;
23828 case V2DI_FTYPE_V2DI_INT:
23829 case V2DI2TI_FTYPE_V2DI_INT:
23830 type = v2di_ftype_v2di_int;
23832 case V2DF_FTYPE_V2DF_INT:
23833 type = v2df_ftype_v2df_int;
23835 case V2DF_FTYPE_V4DF_INT:
23836 type = v2df_ftype_v4df_int;
23838 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23839 type = v16qi_ftype_v16qi_v16qi_v16qi;
23841 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23842 type = v8sf_ftype_v8sf_v8sf_v8sf;
23844 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23845 type = v4df_ftype_v4df_v4df_v4df;
23847 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23848 type = v4sf_ftype_v4sf_v4sf_v4sf;
23850 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23851 type = v2df_ftype_v2df_v2df_v2df;
23853 case V16QI_FTYPE_V16QI_V16QI_INT:
23854 type = v16qi_ftype_v16qi_v16qi_int;
23856 case V8SI_FTYPE_V8SI_V8SI_INT:
23857 type = v8si_ftype_v8si_v8si_int;
23859 case V8SI_FTYPE_V8SI_V4SI_INT:
23860 type = v8si_ftype_v8si_v4si_int;
23862 case V8HI_FTYPE_V8HI_V8HI_INT:
23863 type = v8hi_ftype_v8hi_v8hi_int;
23865 case V8SF_FTYPE_V8SF_V8SF_INT:
23866 type = v8sf_ftype_v8sf_v8sf_int;
23868 case V8SF_FTYPE_V8SF_V4SF_INT:
23869 type = v8sf_ftype_v8sf_v4sf_int;
23871 case V4SI_FTYPE_V4SI_V4SI_INT:
23872 type = v4si_ftype_v4si_v4si_int;
23874 case V4DF_FTYPE_V4DF_V4DF_INT:
23875 type = v4df_ftype_v4df_v4df_int;
23877 case V4DF_FTYPE_V4DF_V2DF_INT:
23878 type = v4df_ftype_v4df_v2df_int;
23880 case V4SF_FTYPE_V4SF_V4SF_INT:
23881 type = v4sf_ftype_v4sf_v4sf_int;
23883 case V2DI_FTYPE_V2DI_V2DI_INT:
23884 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23885 type = v2di_ftype_v2di_v2di_int;
23887 case V2DF_FTYPE_V2DF_V2DF_INT:
23888 type = v2df_ftype_v2df_v2df_int;
23890 case V2DI_FTYPE_V2DI_UINT_UINT:
23891 type = v2di_ftype_v2di_unsigned_unsigned;
23893 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23894 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23896 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23897 type = v1di_ftype_v1di_v1di_int;
23900 gcc_unreachable ();
23903 def_builtin_const (d->mask, d->name, type, d->code);
23906 /* pcmpestr[im] insns. */
23907 for (i = 0, d = bdesc_pcmpestr;
23908 i < ARRAY_SIZE (bdesc_pcmpestr);
23911 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23912 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23914 ftype = int_ftype_v16qi_int_v16qi_int_int;
23915 def_builtin_const (d->mask, d->name, ftype, d->code);
23918 /* pcmpistr[im] insns. */
23919 for (i = 0, d = bdesc_pcmpistr;
23920 i < ARRAY_SIZE (bdesc_pcmpistr);
23923 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23924 ftype = v16qi_ftype_v16qi_v16qi_int;
23926 ftype = int_ftype_v16qi_v16qi_int;
23927 def_builtin_const (d->mask, d->name, ftype, d->code);
23930 /* comi/ucomi insns. */
23931 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23932 if (d->mask == OPTION_MASK_ISA_SSE2)
23933 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23935 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23938 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23939 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23941 /* SSE or 3DNow!A */
23942 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23945 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23947 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23948 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23951 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23952 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23955 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23956 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23957 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23958 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23959 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23960 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23963 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23966 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23967 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23969 /* Access to the vec_init patterns. */
23970 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23971 integer_type_node, NULL_TREE);
23972 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23974 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23975 short_integer_type_node,
23976 short_integer_type_node,
23977 short_integer_type_node, NULL_TREE);
23978 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23980 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23981 char_type_node, char_type_node,
23982 char_type_node, char_type_node,
23983 char_type_node, char_type_node,
23984 char_type_node, NULL_TREE);
23985 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23987 /* Access to the vec_extract patterns. */
23988 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23989 integer_type_node, NULL_TREE);
23990 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23992 ftype = build_function_type_list (long_long_integer_type_node,
23993 V2DI_type_node, integer_type_node,
23995 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23997 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23998 integer_type_node, NULL_TREE);
23999 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
24001 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
24002 integer_type_node, NULL_TREE);
24003 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
24005 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
24006 integer_type_node, NULL_TREE);
24007 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
24009 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
24010 integer_type_node, NULL_TREE);
24011 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
24013 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
24014 integer_type_node, NULL_TREE);
24015 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
24017 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
24018 integer_type_node, NULL_TREE);
24019 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
24021 /* Access to the vec_set patterns. */
24022 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
24024 integer_type_node, NULL_TREE);
24025 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
24027 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
24029 integer_type_node, NULL_TREE);
24030 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
24032 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
24034 integer_type_node, NULL_TREE);
24035 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
24037 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
24039 integer_type_node, NULL_TREE);
24040 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
24042 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
24044 integer_type_node, NULL_TREE);
24045 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
24047 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
24049 integer_type_node, NULL_TREE);
24050 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
24051 /* Add FMA4 multi-arg argument instructions */
24052 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24054 tree mtype = NULL_TREE;
24059 switch ((enum multi_arg_type)d->flag)
24061 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
24062 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
24063 case MULTI_ARG_3_SF2: mtype = v8sf_ftype_v8sf_v8sf_v8sf; break;
24064 case MULTI_ARG_3_DF2: mtype = v4df_ftype_v4df_v4df_v4df; break;
24065 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
24066 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
24067 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
24068 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
24069 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
24070 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
24071 case MULTI_ARG_3_DI2: mtype = v4di_ftype_v4di_v4di_v4di; break;
24072 case MULTI_ARG_3_SI2: mtype = v8si_ftype_v8si_v8si_v8si; break;
24073 case MULTI_ARG_3_HI2: mtype = v16hi_ftype_v16hi_v16hi_v16hi; break;
24074 case MULTI_ARG_3_QI2: mtype = v32qi_ftype_v32qi_v32qi_v32qi; break;
24075 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
24076 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
24077 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
24078 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
24079 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
24080 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
24081 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
24082 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
24083 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
24084 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
24085 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
24086 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
24087 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
24088 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
24089 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
24090 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
24091 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
24092 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
24093 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
24094 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
24095 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
24096 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
24097 case MULTI_ARG_1_SF2: mtype = v8sf_ftype_v8sf; break;
24098 case MULTI_ARG_1_DF2: mtype = v4df_ftype_v4df; break;
24099 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
24100 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
24101 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
24102 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
24103 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
24104 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
24105 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
24106 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
24107 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
24108 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
24110 case MULTI_ARG_UNKNOWN:
24112 gcc_unreachable ();
24116 def_builtin_const (d->mask, d->name, mtype, d->code);
24120 /* Internal method for ix86_init_builtins. */
24123 ix86_init_builtins_va_builtins_abi (void)
24125 tree ms_va_ref, sysv_va_ref;
24126 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
24127 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
24128 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
24129 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
24133 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
24134 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
24135 ms_va_ref = build_reference_type (ms_va_list_type_node);
24137 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
24140 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24141 fnvoid_va_start_ms =
24142 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24143 fnvoid_va_end_sysv =
24144 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
24145 fnvoid_va_start_sysv =
24146 build_varargs_function_type_list (void_type_node, sysv_va_ref,
24148 fnvoid_va_copy_ms =
24149 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
24151 fnvoid_va_copy_sysv =
24152 build_function_type_list (void_type_node, sysv_va_ref,
24153 sysv_va_ref, NULL_TREE);
24155 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
24156 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
24157 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
24158 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
24159 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
24160 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
24161 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
24162 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24163 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
24164 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24165 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
24166 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24170 ix86_init_builtins (void)
24172 tree float128_type_node = make_node (REAL_TYPE);
24175 /* The __float80 type. */
24176 if (TYPE_MODE (long_double_type_node) == XFmode)
24177 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
24181 /* The __float80 type. */
24182 tree float80_type_node = make_node (REAL_TYPE);
24184 TYPE_PRECISION (float80_type_node) = 80;
24185 layout_type (float80_type_node);
24186 (*lang_hooks.types.register_builtin_type) (float80_type_node,
24190 /* The __float128 type. */
24191 TYPE_PRECISION (float128_type_node) = 128;
24192 layout_type (float128_type_node);
24193 (*lang_hooks.types.register_builtin_type) (float128_type_node,
24196 /* TFmode support builtins. */
24197 ftype = build_function_type (float128_type_node, void_list_node);
24198 decl = add_builtin_function ("__builtin_infq", ftype,
24199 IX86_BUILTIN_INFQ, BUILT_IN_MD,
24201 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
24203 decl = add_builtin_function ("__builtin_huge_valq", ftype,
24204 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
24206 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
24208 /* We will expand them to normal call if SSE2 isn't available since
24209 they are used by libgcc. */
24210 ftype = build_function_type_list (float128_type_node,
24211 float128_type_node,
24213 decl = add_builtin_function ("__builtin_fabsq", ftype,
24214 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
24215 "__fabstf2", NULL_TREE);
24216 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
24217 TREE_READONLY (decl) = 1;
24219 ftype = build_function_type_list (float128_type_node,
24220 float128_type_node,
24221 float128_type_node,
24223 decl = add_builtin_function ("__builtin_copysignq", ftype,
24224 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
24225 "__copysigntf3", NULL_TREE);
24226 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
24227 TREE_READONLY (decl) = 1;
24229 ix86_init_mmx_sse_builtins ();
24231 ix86_init_builtins_va_builtins_abi ();
24234 /* Return the ix86 builtin for CODE. */
24237 ix86_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
24239 if (code >= IX86_BUILTIN_MAX)
24240 return error_mark_node;
24242 return ix86_builtins[code];
24245 /* Errors in the source file can cause expand_expr to return const0_rtx
24246 where we expect a vector. To avoid crashing, use one of the vector
24247 clear instructions. */
24249 safe_vector_operand (rtx x, enum machine_mode mode)
24251 if (x == const0_rtx)
24252 x = CONST0_RTX (mode);
24256 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
24259 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
24262 tree arg0 = CALL_EXPR_ARG (exp, 0);
24263 tree arg1 = CALL_EXPR_ARG (exp, 1);
24264 rtx op0 = expand_normal (arg0);
24265 rtx op1 = expand_normal (arg1);
24266 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24267 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24268 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
24270 if (VECTOR_MODE_P (mode0))
24271 op0 = safe_vector_operand (op0, mode0);
24272 if (VECTOR_MODE_P (mode1))
24273 op1 = safe_vector_operand (op1, mode1);
24275 if (optimize || !target
24276 || GET_MODE (target) != tmode
24277 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24278 target = gen_reg_rtx (tmode);
24280 if (GET_MODE (op1) == SImode && mode1 == TImode)
24282 rtx x = gen_reg_rtx (V4SImode);
24283 emit_insn (gen_sse2_loadd (x, op1));
24284 op1 = gen_lowpart (TImode, x);
24287 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
24288 op0 = copy_to_mode_reg (mode0, op0);
24289 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
24290 op1 = copy_to_mode_reg (mode1, op1);
24292 pat = GEN_FCN (icode) (target, op0, op1);
24301 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
24304 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
24305 enum multi_arg_type m_type,
24306 enum rtx_code sub_code)
24311 bool comparison_p = false;
24313 bool last_arg_constant = false;
24314 int num_memory = 0;
24317 enum machine_mode mode;
24320 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24324 case MULTI_ARG_3_SF:
24325 case MULTI_ARG_3_DF:
24326 case MULTI_ARG_3_SF2:
24327 case MULTI_ARG_3_DF2:
24328 case MULTI_ARG_3_DI:
24329 case MULTI_ARG_3_SI:
24330 case MULTI_ARG_3_SI_DI:
24331 case MULTI_ARG_3_HI:
24332 case MULTI_ARG_3_HI_SI:
24333 case MULTI_ARG_3_QI:
24334 case MULTI_ARG_3_DI2:
24335 case MULTI_ARG_3_SI2:
24336 case MULTI_ARG_3_HI2:
24337 case MULTI_ARG_3_QI2:
24341 case MULTI_ARG_2_SF:
24342 case MULTI_ARG_2_DF:
24343 case MULTI_ARG_2_DI:
24344 case MULTI_ARG_2_SI:
24345 case MULTI_ARG_2_HI:
24346 case MULTI_ARG_2_QI:
24350 case MULTI_ARG_2_DI_IMM:
24351 case MULTI_ARG_2_SI_IMM:
24352 case MULTI_ARG_2_HI_IMM:
24353 case MULTI_ARG_2_QI_IMM:
24355 last_arg_constant = true;
24358 case MULTI_ARG_1_SF:
24359 case MULTI_ARG_1_DF:
24360 case MULTI_ARG_1_SF2:
24361 case MULTI_ARG_1_DF2:
24362 case MULTI_ARG_1_DI:
24363 case MULTI_ARG_1_SI:
24364 case MULTI_ARG_1_HI:
24365 case MULTI_ARG_1_QI:
24366 case MULTI_ARG_1_SI_DI:
24367 case MULTI_ARG_1_HI_DI:
24368 case MULTI_ARG_1_HI_SI:
24369 case MULTI_ARG_1_QI_DI:
24370 case MULTI_ARG_1_QI_SI:
24371 case MULTI_ARG_1_QI_HI:
24375 case MULTI_ARG_2_DI_CMP:
24376 case MULTI_ARG_2_SI_CMP:
24377 case MULTI_ARG_2_HI_CMP:
24378 case MULTI_ARG_2_QI_CMP:
24380 comparison_p = true;
24383 case MULTI_ARG_2_SF_TF:
24384 case MULTI_ARG_2_DF_TF:
24385 case MULTI_ARG_2_DI_TF:
24386 case MULTI_ARG_2_SI_TF:
24387 case MULTI_ARG_2_HI_TF:
24388 case MULTI_ARG_2_QI_TF:
24393 case MULTI_ARG_UNKNOWN:
24395 gcc_unreachable ();
24398 if (optimize || !target
24399 || GET_MODE (target) != tmode
24400 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24401 target = gen_reg_rtx (tmode);
24403 gcc_assert (nargs <= 4);
24405 for (i = 0; i < nargs; i++)
24407 tree arg = CALL_EXPR_ARG (exp, i);
24408 rtx op = expand_normal (arg);
24409 int adjust = (comparison_p) ? 1 : 0;
24410 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
24412 if (last_arg_constant && i == nargs-1)
24414 if (!CONST_INT_P (op))
24416 error ("last argument must be an immediate");
24417 return gen_reg_rtx (tmode);
24422 if (VECTOR_MODE_P (mode))
24423 op = safe_vector_operand (op, mode);
24425 /* If we aren't optimizing, only allow one memory operand to be
24427 if (memory_operand (op, mode))
24430 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
24433 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
24435 op = force_reg (mode, op);
24439 args[i].mode = mode;
24445 pat = GEN_FCN (icode) (target, args[0].op);
24450 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
24451 GEN_INT ((int)sub_code));
24452 else if (! comparison_p)
24453 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24456 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
24460 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
24465 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
24469 gcc_unreachable ();
24479 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
24480 insns with vec_merge. */
24483 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
24487 tree arg0 = CALL_EXPR_ARG (exp, 0);
24488 rtx op1, op0 = expand_normal (arg0);
24489 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24490 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24492 if (optimize || !target
24493 || GET_MODE (target) != tmode
24494 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24495 target = gen_reg_rtx (tmode);
24497 if (VECTOR_MODE_P (mode0))
24498 op0 = safe_vector_operand (op0, mode0);
24500 if ((optimize && !register_operand (op0, mode0))
24501 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
24502 op0 = copy_to_mode_reg (mode0, op0);
24505 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
24506 op1 = copy_to_mode_reg (mode0, op1);
24508 pat = GEN_FCN (icode) (target, op0, op1);
24515 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
24518 ix86_expand_sse_compare (const struct builtin_description *d,
24519 tree exp, rtx target, bool swap)
24522 tree arg0 = CALL_EXPR_ARG (exp, 0);
24523 tree arg1 = CALL_EXPR_ARG (exp, 1);
24524 rtx op0 = expand_normal (arg0);
24525 rtx op1 = expand_normal (arg1);
24527 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
24528 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
24529 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
24530 enum rtx_code comparison = d->comparison;
24532 if (VECTOR_MODE_P (mode0))
24533 op0 = safe_vector_operand (op0, mode0);
24534 if (VECTOR_MODE_P (mode1))
24535 op1 = safe_vector_operand (op1, mode1);
24537 /* Swap operands if we have a comparison that isn't available in
24541 rtx tmp = gen_reg_rtx (mode1);
24542 emit_move_insn (tmp, op1);
24547 if (optimize || !target
24548 || GET_MODE (target) != tmode
24549 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
24550 target = gen_reg_rtx (tmode);
24552 if ((optimize && !register_operand (op0, mode0))
24553 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
24554 op0 = copy_to_mode_reg (mode0, op0);
24555 if ((optimize && !register_operand (op1, mode1))
24556 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
24557 op1 = copy_to_mode_reg (mode1, op1);
24559 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
24560 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
24567 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
24570 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
24574 tree arg0 = CALL_EXPR_ARG (exp, 0);
24575 tree arg1 = CALL_EXPR_ARG (exp, 1);
24576 rtx op0 = expand_normal (arg0);
24577 rtx op1 = expand_normal (arg1);
24578 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24579 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24580 enum rtx_code comparison = d->comparison;
24582 if (VECTOR_MODE_P (mode0))
24583 op0 = safe_vector_operand (op0, mode0);
24584 if (VECTOR_MODE_P (mode1))
24585 op1 = safe_vector_operand (op1, mode1);
24587 /* Swap operands if we have a comparison that isn't available in
24589 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
24596 target = gen_reg_rtx (SImode);
24597 emit_move_insn (target, const0_rtx);
24598 target = gen_rtx_SUBREG (QImode, target, 0);
24600 if ((optimize && !register_operand (op0, mode0))
24601 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24602 op0 = copy_to_mode_reg (mode0, op0);
24603 if ((optimize && !register_operand (op1, mode1))
24604 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24605 op1 = copy_to_mode_reg (mode1, op1);
24607 pat = GEN_FCN (d->icode) (op0, op1);
24611 emit_insn (gen_rtx_SET (VOIDmode,
24612 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24613 gen_rtx_fmt_ee (comparison, QImode,
24617 return SUBREG_REG (target);
24620 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
24623 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
24627 tree arg0 = CALL_EXPR_ARG (exp, 0);
24628 tree arg1 = CALL_EXPR_ARG (exp, 1);
24629 rtx op0 = expand_normal (arg0);
24630 rtx op1 = expand_normal (arg1);
24631 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24632 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24633 enum rtx_code comparison = d->comparison;
24635 if (VECTOR_MODE_P (mode0))
24636 op0 = safe_vector_operand (op0, mode0);
24637 if (VECTOR_MODE_P (mode1))
24638 op1 = safe_vector_operand (op1, mode1);
24640 target = gen_reg_rtx (SImode);
24641 emit_move_insn (target, const0_rtx);
24642 target = gen_rtx_SUBREG (QImode, target, 0);
24644 if ((optimize && !register_operand (op0, mode0))
24645 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24646 op0 = copy_to_mode_reg (mode0, op0);
24647 if ((optimize && !register_operand (op1, mode1))
24648 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24649 op1 = copy_to_mode_reg (mode1, op1);
24651 pat = GEN_FCN (d->icode) (op0, op1);
24655 emit_insn (gen_rtx_SET (VOIDmode,
24656 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24657 gen_rtx_fmt_ee (comparison, QImode,
24661 return SUBREG_REG (target);
24664 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
24667 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
24668 tree exp, rtx target)
24671 tree arg0 = CALL_EXPR_ARG (exp, 0);
24672 tree arg1 = CALL_EXPR_ARG (exp, 1);
24673 tree arg2 = CALL_EXPR_ARG (exp, 2);
24674 tree arg3 = CALL_EXPR_ARG (exp, 3);
24675 tree arg4 = CALL_EXPR_ARG (exp, 4);
24676 rtx scratch0, scratch1;
24677 rtx op0 = expand_normal (arg0);
24678 rtx op1 = expand_normal (arg1);
24679 rtx op2 = expand_normal (arg2);
24680 rtx op3 = expand_normal (arg3);
24681 rtx op4 = expand_normal (arg4);
24682 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
24684 tmode0 = insn_data[d->icode].operand[0].mode;
24685 tmode1 = insn_data[d->icode].operand[1].mode;
24686 modev2 = insn_data[d->icode].operand[2].mode;
24687 modei3 = insn_data[d->icode].operand[3].mode;
24688 modev4 = insn_data[d->icode].operand[4].mode;
24689 modei5 = insn_data[d->icode].operand[5].mode;
24690 modeimm = insn_data[d->icode].operand[6].mode;
24692 if (VECTOR_MODE_P (modev2))
24693 op0 = safe_vector_operand (op0, modev2);
24694 if (VECTOR_MODE_P (modev4))
24695 op2 = safe_vector_operand (op2, modev4);
24697 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24698 op0 = copy_to_mode_reg (modev2, op0);
24699 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24700 op1 = copy_to_mode_reg (modei3, op1);
24701 if ((optimize && !register_operand (op2, modev4))
24702 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24703 op2 = copy_to_mode_reg (modev4, op2);
24704 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24705 op3 = copy_to_mode_reg (modei5, op3);
24707 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24709 error ("the fifth argument must be a 8-bit immediate");
24713 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24715 if (optimize || !target
24716 || GET_MODE (target) != tmode0
24717 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24718 target = gen_reg_rtx (tmode0);
24720 scratch1 = gen_reg_rtx (tmode1);
24722 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24724 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24726 if (optimize || !target
24727 || GET_MODE (target) != tmode1
24728 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24729 target = gen_reg_rtx (tmode1);
24731 scratch0 = gen_reg_rtx (tmode0);
24733 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24737 gcc_assert (d->flag);
24739 scratch0 = gen_reg_rtx (tmode0);
24740 scratch1 = gen_reg_rtx (tmode1);
24742 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24752 target = gen_reg_rtx (SImode);
24753 emit_move_insn (target, const0_rtx);
24754 target = gen_rtx_SUBREG (QImode, target, 0);
24757 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24758 gen_rtx_fmt_ee (EQ, QImode,
24759 gen_rtx_REG ((enum machine_mode) d->flag,
24762 return SUBREG_REG (target);
24769 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24772 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24773 tree exp, rtx target)
24776 tree arg0 = CALL_EXPR_ARG (exp, 0);
24777 tree arg1 = CALL_EXPR_ARG (exp, 1);
24778 tree arg2 = CALL_EXPR_ARG (exp, 2);
24779 rtx scratch0, scratch1;
24780 rtx op0 = expand_normal (arg0);
24781 rtx op1 = expand_normal (arg1);
24782 rtx op2 = expand_normal (arg2);
24783 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24785 tmode0 = insn_data[d->icode].operand[0].mode;
24786 tmode1 = insn_data[d->icode].operand[1].mode;
24787 modev2 = insn_data[d->icode].operand[2].mode;
24788 modev3 = insn_data[d->icode].operand[3].mode;
24789 modeimm = insn_data[d->icode].operand[4].mode;
24791 if (VECTOR_MODE_P (modev2))
24792 op0 = safe_vector_operand (op0, modev2);
24793 if (VECTOR_MODE_P (modev3))
24794 op1 = safe_vector_operand (op1, modev3);
24796 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24797 op0 = copy_to_mode_reg (modev2, op0);
24798 if ((optimize && !register_operand (op1, modev3))
24799 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24800 op1 = copy_to_mode_reg (modev3, op1);
24802 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24804 error ("the third argument must be a 8-bit immediate");
24808 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24810 if (optimize || !target
24811 || GET_MODE (target) != tmode0
24812 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24813 target = gen_reg_rtx (tmode0);
24815 scratch1 = gen_reg_rtx (tmode1);
24817 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24819 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24821 if (optimize || !target
24822 || GET_MODE (target) != tmode1
24823 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24824 target = gen_reg_rtx (tmode1);
24826 scratch0 = gen_reg_rtx (tmode0);
24828 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24832 gcc_assert (d->flag);
24834 scratch0 = gen_reg_rtx (tmode0);
24835 scratch1 = gen_reg_rtx (tmode1);
24837 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24847 target = gen_reg_rtx (SImode);
24848 emit_move_insn (target, const0_rtx);
24849 target = gen_rtx_SUBREG (QImode, target, 0);
24852 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24853 gen_rtx_fmt_ee (EQ, QImode,
24854 gen_rtx_REG ((enum machine_mode) d->flag,
24857 return SUBREG_REG (target);
24863 /* Subroutine of ix86_expand_builtin to take care of insns with
24864 variable number of operands. */
24867 ix86_expand_args_builtin (const struct builtin_description *d,
24868 tree exp, rtx target)
24870 rtx pat, real_target;
24871 unsigned int i, nargs;
24872 unsigned int nargs_constant = 0;
24873 int num_memory = 0;
24877 enum machine_mode mode;
24879 bool last_arg_count = false;
24880 enum insn_code icode = d->icode;
24881 const struct insn_data *insn_p = &insn_data[icode];
24882 enum machine_mode tmode = insn_p->operand[0].mode;
24883 enum machine_mode rmode = VOIDmode;
24885 enum rtx_code comparison = d->comparison;
24887 switch ((enum ix86_builtin_type) d->flag)
24889 case INT_FTYPE_V8SF_V8SF_PTEST:
24890 case INT_FTYPE_V4DI_V4DI_PTEST:
24891 case INT_FTYPE_V4DF_V4DF_PTEST:
24892 case INT_FTYPE_V4SF_V4SF_PTEST:
24893 case INT_FTYPE_V2DI_V2DI_PTEST:
24894 case INT_FTYPE_V2DF_V2DF_PTEST:
24895 return ix86_expand_sse_ptest (d, exp, target);
24896 case FLOAT128_FTYPE_FLOAT128:
24897 case FLOAT_FTYPE_FLOAT:
24898 case INT_FTYPE_INT:
24899 case UINT64_FTYPE_INT:
24900 case INT64_FTYPE_INT64:
24901 case INT64_FTYPE_V4SF:
24902 case INT64_FTYPE_V2DF:
24903 case INT_FTYPE_V16QI:
24904 case INT_FTYPE_V8QI:
24905 case INT_FTYPE_V8SF:
24906 case INT_FTYPE_V4DF:
24907 case INT_FTYPE_V4SF:
24908 case INT_FTYPE_V2DF:
24909 case V16QI_FTYPE_V16QI:
24910 case V8SI_FTYPE_V8SF:
24911 case V8SI_FTYPE_V4SI:
24912 case V8HI_FTYPE_V8HI:
24913 case V8HI_FTYPE_V16QI:
24914 case V8QI_FTYPE_V8QI:
24915 case V8SF_FTYPE_V8SF:
24916 case V8SF_FTYPE_V8SI:
24917 case V8SF_FTYPE_V4SF:
24918 case V4SI_FTYPE_V4SI:
24919 case V4SI_FTYPE_V16QI:
24920 case V4SI_FTYPE_V4SF:
24921 case V4SI_FTYPE_V8SI:
24922 case V4SI_FTYPE_V8HI:
24923 case V4SI_FTYPE_V4DF:
24924 case V4SI_FTYPE_V2DF:
24925 case V4HI_FTYPE_V4HI:
24926 case V4DF_FTYPE_V4DF:
24927 case V4DF_FTYPE_V4SI:
24928 case V4DF_FTYPE_V4SF:
24929 case V4DF_FTYPE_V2DF:
24930 case V4SF_FTYPE_V4SF:
24931 case V4SF_FTYPE_V4SI:
24932 case V4SF_FTYPE_V8SF:
24933 case V4SF_FTYPE_V4DF:
24934 case V4SF_FTYPE_V2DF:
24935 case V2DI_FTYPE_V2DI:
24936 case V2DI_FTYPE_V16QI:
24937 case V2DI_FTYPE_V8HI:
24938 case V2DI_FTYPE_V4SI:
24939 case V2DF_FTYPE_V2DF:
24940 case V2DF_FTYPE_V4SI:
24941 case V2DF_FTYPE_V4DF:
24942 case V2DF_FTYPE_V4SF:
24943 case V2DF_FTYPE_V2SI:
24944 case V2SI_FTYPE_V2SI:
24945 case V2SI_FTYPE_V4SF:
24946 case V2SI_FTYPE_V2SF:
24947 case V2SI_FTYPE_V2DF:
24948 case V2SF_FTYPE_V2SF:
24949 case V2SF_FTYPE_V2SI:
24952 case V4SF_FTYPE_V4SF_VEC_MERGE:
24953 case V2DF_FTYPE_V2DF_VEC_MERGE:
24954 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24955 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24956 case V16QI_FTYPE_V16QI_V16QI:
24957 case V16QI_FTYPE_V8HI_V8HI:
24958 case V8QI_FTYPE_V8QI_V8QI:
24959 case V8QI_FTYPE_V4HI_V4HI:
24960 case V8HI_FTYPE_V8HI_V8HI:
24961 case V8HI_FTYPE_V16QI_V16QI:
24962 case V8HI_FTYPE_V4SI_V4SI:
24963 case V8SF_FTYPE_V8SF_V8SF:
24964 case V8SF_FTYPE_V8SF_V8SI:
24965 case V4SI_FTYPE_V4SI_V4SI:
24966 case V4SI_FTYPE_V8HI_V8HI:
24967 case V4SI_FTYPE_V4SF_V4SF:
24968 case V4SI_FTYPE_V2DF_V2DF:
24969 case V4HI_FTYPE_V4HI_V4HI:
24970 case V4HI_FTYPE_V8QI_V8QI:
24971 case V4HI_FTYPE_V2SI_V2SI:
24972 case V4DF_FTYPE_V4DF_V4DF:
24973 case V4DF_FTYPE_V4DF_V4DI:
24974 case V4SF_FTYPE_V4SF_V4SF:
24975 case V4SF_FTYPE_V4SF_V4SI:
24976 case V4SF_FTYPE_V4SF_V2SI:
24977 case V4SF_FTYPE_V4SF_V2DF:
24978 case V4SF_FTYPE_V4SF_DI:
24979 case V4SF_FTYPE_V4SF_SI:
24980 case V2DI_FTYPE_V2DI_V2DI:
24981 case V2DI_FTYPE_V16QI_V16QI:
24982 case V2DI_FTYPE_V4SI_V4SI:
24983 case V2DI_FTYPE_V2DI_V16QI:
24984 case V2DI_FTYPE_V2DF_V2DF:
24985 case V2SI_FTYPE_V2SI_V2SI:
24986 case V2SI_FTYPE_V4HI_V4HI:
24987 case V2SI_FTYPE_V2SF_V2SF:
24988 case V2DF_FTYPE_V2DF_V2DF:
24989 case V2DF_FTYPE_V2DF_V4SF:
24990 case V2DF_FTYPE_V2DF_V2DI:
24991 case V2DF_FTYPE_V2DF_DI:
24992 case V2DF_FTYPE_V2DF_SI:
24993 case V2SF_FTYPE_V2SF_V2SF:
24994 case V1DI_FTYPE_V1DI_V1DI:
24995 case V1DI_FTYPE_V8QI_V8QI:
24996 case V1DI_FTYPE_V2SI_V2SI:
24997 if (comparison == UNKNOWN)
24998 return ix86_expand_binop_builtin (icode, exp, target);
25001 case V4SF_FTYPE_V4SF_V4SF_SWAP:
25002 case V2DF_FTYPE_V2DF_V2DF_SWAP:
25003 gcc_assert (comparison != UNKNOWN);
25007 case V8HI_FTYPE_V8HI_V8HI_COUNT:
25008 case V8HI_FTYPE_V8HI_SI_COUNT:
25009 case V4SI_FTYPE_V4SI_V4SI_COUNT:
25010 case V4SI_FTYPE_V4SI_SI_COUNT:
25011 case V4HI_FTYPE_V4HI_V4HI_COUNT:
25012 case V4HI_FTYPE_V4HI_SI_COUNT:
25013 case V2DI_FTYPE_V2DI_V2DI_COUNT:
25014 case V2DI_FTYPE_V2DI_SI_COUNT:
25015 case V2SI_FTYPE_V2SI_V2SI_COUNT:
25016 case V2SI_FTYPE_V2SI_SI_COUNT:
25017 case V1DI_FTYPE_V1DI_V1DI_COUNT:
25018 case V1DI_FTYPE_V1DI_SI_COUNT:
25020 last_arg_count = true;
25022 case UINT64_FTYPE_UINT64_UINT64:
25023 case UINT_FTYPE_UINT_UINT:
25024 case UINT_FTYPE_UINT_USHORT:
25025 case UINT_FTYPE_UINT_UCHAR:
25026 case UINT16_FTYPE_UINT16_INT:
25027 case UINT8_FTYPE_UINT8_INT:
25030 case V2DI2TI_FTYPE_V2DI_INT:
25033 nargs_constant = 1;
25035 case V8HI_FTYPE_V8HI_INT:
25036 case V8SF_FTYPE_V8SF_INT:
25037 case V4SI_FTYPE_V4SI_INT:
25038 case V4SI_FTYPE_V8SI_INT:
25039 case V4HI_FTYPE_V4HI_INT:
25040 case V4DF_FTYPE_V4DF_INT:
25041 case V4SF_FTYPE_V4SF_INT:
25042 case V4SF_FTYPE_V8SF_INT:
25043 case V2DI_FTYPE_V2DI_INT:
25044 case V2DF_FTYPE_V2DF_INT:
25045 case V2DF_FTYPE_V4DF_INT:
25047 nargs_constant = 1;
25049 case V16QI_FTYPE_V16QI_V16QI_V16QI:
25050 case V8SF_FTYPE_V8SF_V8SF_V8SF:
25051 case V4DF_FTYPE_V4DF_V4DF_V4DF:
25052 case V4SF_FTYPE_V4SF_V4SF_V4SF:
25053 case V2DF_FTYPE_V2DF_V2DF_V2DF:
25056 case V16QI_FTYPE_V16QI_V16QI_INT:
25057 case V8HI_FTYPE_V8HI_V8HI_INT:
25058 case V8SI_FTYPE_V8SI_V8SI_INT:
25059 case V8SI_FTYPE_V8SI_V4SI_INT:
25060 case V8SF_FTYPE_V8SF_V8SF_INT:
25061 case V8SF_FTYPE_V8SF_V4SF_INT:
25062 case V4SI_FTYPE_V4SI_V4SI_INT:
25063 case V4DF_FTYPE_V4DF_V4DF_INT:
25064 case V4DF_FTYPE_V4DF_V2DF_INT:
25065 case V4SF_FTYPE_V4SF_V4SF_INT:
25066 case V2DI_FTYPE_V2DI_V2DI_INT:
25067 case V2DF_FTYPE_V2DF_V2DF_INT:
25069 nargs_constant = 1;
25071 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
25074 nargs_constant = 1;
25076 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
25079 nargs_constant = 1;
25081 case V2DI_FTYPE_V2DI_UINT_UINT:
25083 nargs_constant = 2;
25085 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
25087 nargs_constant = 2;
25090 gcc_unreachable ();
25093 gcc_assert (nargs <= ARRAY_SIZE (args));
25095 if (comparison != UNKNOWN)
25097 gcc_assert (nargs == 2);
25098 return ix86_expand_sse_compare (d, exp, target, swap);
25101 if (rmode == VOIDmode || rmode == tmode)
25105 || GET_MODE (target) != tmode
25106 || ! (*insn_p->operand[0].predicate) (target, tmode))
25107 target = gen_reg_rtx (tmode);
25108 real_target = target;
25112 target = gen_reg_rtx (rmode);
25113 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
25116 for (i = 0; i < nargs; i++)
25118 tree arg = CALL_EXPR_ARG (exp, i);
25119 rtx op = expand_normal (arg);
25120 enum machine_mode mode = insn_p->operand[i + 1].mode;
25121 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
25123 if (last_arg_count && (i + 1) == nargs)
25125 /* SIMD shift insns take either an 8-bit immediate or
25126 register as count. But builtin functions take int as
25127 count. If count doesn't match, we put it in register. */
25130 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
25131 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
25132 op = copy_to_reg (op);
25135 else if ((nargs - i) <= nargs_constant)
25140 case CODE_FOR_sse4_1_roundpd:
25141 case CODE_FOR_sse4_1_roundps:
25142 case CODE_FOR_sse4_1_roundsd:
25143 case CODE_FOR_sse4_1_roundss:
25144 case CODE_FOR_sse4_1_blendps:
25145 case CODE_FOR_avx_blendpd256:
25146 case CODE_FOR_avx_vpermilv4df:
25147 case CODE_FOR_avx_roundpd256:
25148 case CODE_FOR_avx_roundps256:
25149 error ("the last argument must be a 4-bit immediate");
25152 case CODE_FOR_sse4_1_blendpd:
25153 case CODE_FOR_avx_vpermilv2df:
25154 error ("the last argument must be a 2-bit immediate");
25157 case CODE_FOR_avx_vextractf128v4df:
25158 case CODE_FOR_avx_vextractf128v8sf:
25159 case CODE_FOR_avx_vextractf128v8si:
25160 case CODE_FOR_avx_vinsertf128v4df:
25161 case CODE_FOR_avx_vinsertf128v8sf:
25162 case CODE_FOR_avx_vinsertf128v8si:
25163 error ("the last argument must be a 1-bit immediate");
25166 case CODE_FOR_avx_cmpsdv2df3:
25167 case CODE_FOR_avx_cmpssv4sf3:
25168 case CODE_FOR_avx_cmppdv2df3:
25169 case CODE_FOR_avx_cmppsv4sf3:
25170 case CODE_FOR_avx_cmppdv4df3:
25171 case CODE_FOR_avx_cmppsv8sf3:
25172 error ("the last argument must be a 5-bit immediate");
25176 switch (nargs_constant)
25179 if ((nargs - i) == nargs_constant)
25181 error ("the next to last argument must be an 8-bit immediate");
25185 error ("the last argument must be an 8-bit immediate");
25188 gcc_unreachable ();
25195 if (VECTOR_MODE_P (mode))
25196 op = safe_vector_operand (op, mode);
25198 /* If we aren't optimizing, only allow one memory operand to
25200 if (memory_operand (op, mode))
25203 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
25205 if (optimize || !match || num_memory > 1)
25206 op = copy_to_mode_reg (mode, op);
25210 op = copy_to_reg (op);
25211 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
25216 args[i].mode = mode;
25222 pat = GEN_FCN (icode) (real_target, args[0].op);
25225 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
25228 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25232 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25233 args[2].op, args[3].op);
25236 gcc_unreachable ();
25246 /* Subroutine of ix86_expand_builtin to take care of special insns
25247 with variable number of operands. */
25250 ix86_expand_special_args_builtin (const struct builtin_description *d,
25251 tree exp, rtx target)
25255 unsigned int i, nargs, arg_adjust, memory;
25259 enum machine_mode mode;
25261 enum insn_code icode = d->icode;
25262 bool last_arg_constant = false;
25263 const struct insn_data *insn_p = &insn_data[icode];
25264 enum machine_mode tmode = insn_p->operand[0].mode;
25265 enum { load, store } klass;
25267 switch ((enum ix86_special_builtin_type) d->flag)
25269 case VOID_FTYPE_VOID:
25270 emit_insn (GEN_FCN (icode) (target));
25272 case UINT64_FTYPE_VOID:
25277 case UINT64_FTYPE_PUNSIGNED:
25278 case V2DI_FTYPE_PV2DI:
25279 case V32QI_FTYPE_PCCHAR:
25280 case V16QI_FTYPE_PCCHAR:
25281 case V8SF_FTYPE_PCV4SF:
25282 case V8SF_FTYPE_PCFLOAT:
25283 case V4SF_FTYPE_PCFLOAT:
25284 case V4DF_FTYPE_PCV2DF:
25285 case V4DF_FTYPE_PCDOUBLE:
25286 case V2DF_FTYPE_PCDOUBLE:
25291 case VOID_FTYPE_PV2SF_V4SF:
25292 case VOID_FTYPE_PV4DI_V4DI:
25293 case VOID_FTYPE_PV2DI_V2DI:
25294 case VOID_FTYPE_PCHAR_V32QI:
25295 case VOID_FTYPE_PCHAR_V16QI:
25296 case VOID_FTYPE_PFLOAT_V8SF:
25297 case VOID_FTYPE_PFLOAT_V4SF:
25298 case VOID_FTYPE_PDOUBLE_V4DF:
25299 case VOID_FTYPE_PDOUBLE_V2DF:
25300 case VOID_FTYPE_PDI_DI:
25301 case VOID_FTYPE_PINT_INT:
25304 /* Reserve memory operand for target. */
25305 memory = ARRAY_SIZE (args);
25307 case V4SF_FTYPE_V4SF_PCV2SF:
25308 case V2DF_FTYPE_V2DF_PCDOUBLE:
25313 case V8SF_FTYPE_PCV8SF_V8SF:
25314 case V4DF_FTYPE_PCV4DF_V4DF:
25315 case V4SF_FTYPE_PCV4SF_V4SF:
25316 case V2DF_FTYPE_PCV2DF_V2DF:
25321 case VOID_FTYPE_PV8SF_V8SF_V8SF:
25322 case VOID_FTYPE_PV4DF_V4DF_V4DF:
25323 case VOID_FTYPE_PV4SF_V4SF_V4SF:
25324 case VOID_FTYPE_PV2DF_V2DF_V2DF:
25327 /* Reserve memory operand for target. */
25328 memory = ARRAY_SIZE (args);
25330 case VOID_FTYPE_USHORT_UINT_USHORT:
25331 case VOID_FTYPE_UINT_UINT_UINT:
25332 case VOID_FTYPE_UINT64_UINT_UINT:
25333 case UCHAR_FTYPE_USHORT_UINT_USHORT:
25334 case UCHAR_FTYPE_UINT_UINT_UINT:
25335 case UCHAR_FTYPE_UINT64_UINT_UINT:
25341 gcc_unreachable ();
25344 gcc_assert (nargs <= ARRAY_SIZE (args));
25346 if (klass == store)
25348 arg = CALL_EXPR_ARG (exp, 0);
25349 op = expand_normal (arg);
25350 gcc_assert (target == 0);
25351 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
25359 || GET_MODE (target) != tmode
25360 || ! (*insn_p->operand[0].predicate) (target, tmode))
25361 target = gen_reg_rtx (tmode);
25364 for (i = 0; i < nargs; i++)
25366 enum machine_mode mode = insn_p->operand[i + 1].mode;
25369 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
25370 op = expand_normal (arg);
25371 match = (*insn_p->operand[i + 1].predicate) (op, mode);
25373 if (last_arg_constant && (i + 1) == nargs)
25379 error ("the last argument must be an 8-bit immediate");
25387 /* This must be the memory operand. */
25388 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
25389 gcc_assert (GET_MODE (op) == mode
25390 || GET_MODE (op) == VOIDmode);
25394 /* This must be register. */
25395 if (VECTOR_MODE_P (mode))
25396 op = safe_vector_operand (op, mode);
25398 gcc_assert (GET_MODE (op) == mode
25399 || GET_MODE (op) == VOIDmode);
25400 op = copy_to_mode_reg (mode, op);
25405 args[i].mode = mode;
25411 pat = GEN_FCN (icode) (target);
25414 pat = GEN_FCN (icode) (target, args[0].op);
25417 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
25420 gcc_unreachable ();
25426 return klass == store ? 0 : target;
25429 /* Return the integer constant in ARG. Constrain it to be in the range
25430 of the subparts of VEC_TYPE; issue an error if not. */
25433 get_element_number (tree vec_type, tree arg)
25435 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
25437 if (!host_integerp (arg, 1)
25438 || (elt = tree_low_cst (arg, 1), elt > max))
25440 error ("selector must be an integer constant in the range 0..%wi", max);
25447 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25448 ix86_expand_vector_init. We DO have language-level syntax for this, in
25449 the form of (type){ init-list }. Except that since we can't place emms
25450 instructions from inside the compiler, we can't allow the use of MMX
25451 registers unless the user explicitly asks for it. So we do *not* define
25452 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
25453 we have builtins invoked by mmintrin.h that gives us license to emit
25454 these sorts of instructions. */
25457 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
25459 enum machine_mode tmode = TYPE_MODE (type);
25460 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
25461 int i, n_elt = GET_MODE_NUNITS (tmode);
25462 rtvec v = rtvec_alloc (n_elt);
25464 gcc_assert (VECTOR_MODE_P (tmode));
25465 gcc_assert (call_expr_nargs (exp) == n_elt);
25467 for (i = 0; i < n_elt; ++i)
25469 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
25470 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
25473 if (!target || !register_operand (target, tmode))
25474 target = gen_reg_rtx (tmode);
25476 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
25480 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25481 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
25482 had a language-level syntax for referencing vector elements. */
25485 ix86_expand_vec_ext_builtin (tree exp, rtx target)
25487 enum machine_mode tmode, mode0;
25492 arg0 = CALL_EXPR_ARG (exp, 0);
25493 arg1 = CALL_EXPR_ARG (exp, 1);
25495 op0 = expand_normal (arg0);
25496 elt = get_element_number (TREE_TYPE (arg0), arg1);
25498 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25499 mode0 = TYPE_MODE (TREE_TYPE (arg0));
25500 gcc_assert (VECTOR_MODE_P (mode0));
25502 op0 = force_reg (mode0, op0);
25504 if (optimize || !target || !register_operand (target, tmode))
25505 target = gen_reg_rtx (tmode);
25507 ix86_expand_vector_extract (true, target, op0, elt);
25512 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25513 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
25514 a language-level syntax for referencing vector elements. */
25517 ix86_expand_vec_set_builtin (tree exp)
25519 enum machine_mode tmode, mode1;
25520 tree arg0, arg1, arg2;
25522 rtx op0, op1, target;
25524 arg0 = CALL_EXPR_ARG (exp, 0);
25525 arg1 = CALL_EXPR_ARG (exp, 1);
25526 arg2 = CALL_EXPR_ARG (exp, 2);
25528 tmode = TYPE_MODE (TREE_TYPE (arg0));
25529 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25530 gcc_assert (VECTOR_MODE_P (tmode));
25532 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
25533 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
25534 elt = get_element_number (TREE_TYPE (arg0), arg2);
25536 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
25537 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
25539 op0 = force_reg (tmode, op0);
25540 op1 = force_reg (mode1, op1);
25542 /* OP0 is the source of these builtin functions and shouldn't be
25543 modified. Create a copy, use it and return it as target. */
25544 target = gen_reg_rtx (tmode);
25545 emit_move_insn (target, op0);
25546 ix86_expand_vector_set (true, target, op1, elt);
25551 /* Expand an expression EXP that calls a built-in function,
25552 with result going to TARGET if that's convenient
25553 (and in mode MODE if that's convenient).
25554 SUBTARGET may be used as the target for computing one of EXP's operands.
25555 IGNORE is nonzero if the value is to be ignored. */
25558 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
25559 enum machine_mode mode ATTRIBUTE_UNUSED,
25560 int ignore ATTRIBUTE_UNUSED)
25562 const struct builtin_description *d;
25564 enum insn_code icode;
25565 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
25566 tree arg0, arg1, arg2;
25567 rtx op0, op1, op2, pat;
25568 enum machine_mode mode0, mode1, mode2;
25569 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
25571 /* Determine whether the builtin function is available under the current ISA.
25572 Originally the builtin was not created if it wasn't applicable to the
25573 current ISA based on the command line switches. With function specific
25574 options, we need to check in the context of the function making the call
25575 whether it is supported. */
25576 if (ix86_builtins_isa[fcode].isa
25577 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
25579 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
25580 NULL, NULL, false);
25583 error ("%qE needs unknown isa option", fndecl);
25586 gcc_assert (opts != NULL);
25587 error ("%qE needs isa option %s", fndecl, opts);
25595 case IX86_BUILTIN_MASKMOVQ:
25596 case IX86_BUILTIN_MASKMOVDQU:
25597 icode = (fcode == IX86_BUILTIN_MASKMOVQ
25598 ? CODE_FOR_mmx_maskmovq
25599 : CODE_FOR_sse2_maskmovdqu);
25600 /* Note the arg order is different from the operand order. */
25601 arg1 = CALL_EXPR_ARG (exp, 0);
25602 arg2 = CALL_EXPR_ARG (exp, 1);
25603 arg0 = CALL_EXPR_ARG (exp, 2);
25604 op0 = expand_normal (arg0);
25605 op1 = expand_normal (arg1);
25606 op2 = expand_normal (arg2);
25607 mode0 = insn_data[icode].operand[0].mode;
25608 mode1 = insn_data[icode].operand[1].mode;
25609 mode2 = insn_data[icode].operand[2].mode;
25611 op0 = force_reg (Pmode, op0);
25612 op0 = gen_rtx_MEM (mode1, op0);
25614 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
25615 op0 = copy_to_mode_reg (mode0, op0);
25616 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
25617 op1 = copy_to_mode_reg (mode1, op1);
25618 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
25619 op2 = copy_to_mode_reg (mode2, op2);
25620 pat = GEN_FCN (icode) (op0, op1, op2);
25626 case IX86_BUILTIN_LDMXCSR:
25627 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
25628 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25629 emit_move_insn (target, op0);
25630 emit_insn (gen_sse_ldmxcsr (target));
25633 case IX86_BUILTIN_STMXCSR:
25634 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25635 emit_insn (gen_sse_stmxcsr (target));
25636 return copy_to_mode_reg (SImode, target);
25638 case IX86_BUILTIN_CLFLUSH:
25639 arg0 = CALL_EXPR_ARG (exp, 0);
25640 op0 = expand_normal (arg0);
25641 icode = CODE_FOR_sse2_clflush;
25642 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
25643 op0 = copy_to_mode_reg (Pmode, op0);
25645 emit_insn (gen_sse2_clflush (op0));
25648 case IX86_BUILTIN_MONITOR:
25649 arg0 = CALL_EXPR_ARG (exp, 0);
25650 arg1 = CALL_EXPR_ARG (exp, 1);
25651 arg2 = CALL_EXPR_ARG (exp, 2);
25652 op0 = expand_normal (arg0);
25653 op1 = expand_normal (arg1);
25654 op2 = expand_normal (arg2);
25656 op0 = copy_to_mode_reg (Pmode, op0);
25658 op1 = copy_to_mode_reg (SImode, op1);
25660 op2 = copy_to_mode_reg (SImode, op2);
25661 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
25664 case IX86_BUILTIN_MWAIT:
25665 arg0 = CALL_EXPR_ARG (exp, 0);
25666 arg1 = CALL_EXPR_ARG (exp, 1);
25667 op0 = expand_normal (arg0);
25668 op1 = expand_normal (arg1);
25670 op0 = copy_to_mode_reg (SImode, op0);
25672 op1 = copy_to_mode_reg (SImode, op1);
25673 emit_insn (gen_sse3_mwait (op0, op1));
25676 case IX86_BUILTIN_VEC_INIT_V2SI:
25677 case IX86_BUILTIN_VEC_INIT_V4HI:
25678 case IX86_BUILTIN_VEC_INIT_V8QI:
25679 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
25681 case IX86_BUILTIN_VEC_EXT_V2DF:
25682 case IX86_BUILTIN_VEC_EXT_V2DI:
25683 case IX86_BUILTIN_VEC_EXT_V4SF:
25684 case IX86_BUILTIN_VEC_EXT_V4SI:
25685 case IX86_BUILTIN_VEC_EXT_V8HI:
25686 case IX86_BUILTIN_VEC_EXT_V2SI:
25687 case IX86_BUILTIN_VEC_EXT_V4HI:
25688 case IX86_BUILTIN_VEC_EXT_V16QI:
25689 return ix86_expand_vec_ext_builtin (exp, target);
25691 case IX86_BUILTIN_VEC_SET_V2DI:
25692 case IX86_BUILTIN_VEC_SET_V4SF:
25693 case IX86_BUILTIN_VEC_SET_V4SI:
25694 case IX86_BUILTIN_VEC_SET_V8HI:
25695 case IX86_BUILTIN_VEC_SET_V4HI:
25696 case IX86_BUILTIN_VEC_SET_V16QI:
25697 return ix86_expand_vec_set_builtin (exp);
25699 case IX86_BUILTIN_INFQ:
25700 case IX86_BUILTIN_HUGE_VALQ:
25702 REAL_VALUE_TYPE inf;
25706 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
25708 tmp = validize_mem (force_const_mem (mode, tmp));
25711 target = gen_reg_rtx (mode);
25713 emit_move_insn (target, tmp);
25721 for (i = 0, d = bdesc_special_args;
25722 i < ARRAY_SIZE (bdesc_special_args);
25724 if (d->code == fcode)
25725 return ix86_expand_special_args_builtin (d, exp, target);
25727 for (i = 0, d = bdesc_args;
25728 i < ARRAY_SIZE (bdesc_args);
25730 if (d->code == fcode)
25733 case IX86_BUILTIN_FABSQ:
25734 case IX86_BUILTIN_COPYSIGNQ:
25736 /* Emit a normal call if SSE2 isn't available. */
25737 return expand_call (exp, target, ignore);
25739 return ix86_expand_args_builtin (d, exp, target);
25742 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25743 if (d->code == fcode)
25744 return ix86_expand_sse_comi (d, exp, target);
25746 for (i = 0, d = bdesc_pcmpestr;
25747 i < ARRAY_SIZE (bdesc_pcmpestr);
25749 if (d->code == fcode)
25750 return ix86_expand_sse_pcmpestr (d, exp, target);
25752 for (i = 0, d = bdesc_pcmpistr;
25753 i < ARRAY_SIZE (bdesc_pcmpistr);
25755 if (d->code == fcode)
25756 return ix86_expand_sse_pcmpistr (d, exp, target);
25758 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25759 if (d->code == fcode)
25760 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25761 (enum multi_arg_type)d->flag,
25764 gcc_unreachable ();
25767 /* Returns a function decl for a vectorized version of the builtin function
25768 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25769 if it is not available. */
25772 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25775 enum machine_mode in_mode, out_mode;
25778 if (TREE_CODE (type_out) != VECTOR_TYPE
25779 || TREE_CODE (type_in) != VECTOR_TYPE)
25782 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25783 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25784 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25785 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25789 case BUILT_IN_SQRT:
25790 if (out_mode == DFmode && out_n == 2
25791 && in_mode == DFmode && in_n == 2)
25792 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25795 case BUILT_IN_SQRTF:
25796 if (out_mode == SFmode && out_n == 4
25797 && in_mode == SFmode && in_n == 4)
25798 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25801 case BUILT_IN_LRINT:
25802 if (out_mode == SImode && out_n == 4
25803 && in_mode == DFmode && in_n == 2)
25804 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25807 case BUILT_IN_LRINTF:
25808 if (out_mode == SImode && out_n == 4
25809 && in_mode == SFmode && in_n == 4)
25810 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25813 case BUILT_IN_COPYSIGN:
25814 if (out_mode == DFmode && out_n == 2
25815 && in_mode == DFmode && in_n == 2)
25816 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
25819 case BUILT_IN_COPYSIGNF:
25820 if (out_mode == SFmode && out_n == 4
25821 && in_mode == SFmode && in_n == 4)
25822 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
25829 /* Dispatch to a handler for a vectorization library. */
25830 if (ix86_veclib_handler)
25831 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
25837 /* Handler for an SVML-style interface to
25838 a library with vectorized intrinsics. */
25841 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25844 tree fntype, new_fndecl, args;
25847 enum machine_mode el_mode, in_mode;
25850 /* The SVML is suitable for unsafe math only. */
25851 if (!flag_unsafe_math_optimizations)
25854 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25855 n = TYPE_VECTOR_SUBPARTS (type_out);
25856 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25857 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25858 if (el_mode != in_mode
25866 case BUILT_IN_LOG10:
25868 case BUILT_IN_TANH:
25870 case BUILT_IN_ATAN:
25871 case BUILT_IN_ATAN2:
25872 case BUILT_IN_ATANH:
25873 case BUILT_IN_CBRT:
25874 case BUILT_IN_SINH:
25876 case BUILT_IN_ASINH:
25877 case BUILT_IN_ASIN:
25878 case BUILT_IN_COSH:
25880 case BUILT_IN_ACOSH:
25881 case BUILT_IN_ACOS:
25882 if (el_mode != DFmode || n != 2)
25886 case BUILT_IN_EXPF:
25887 case BUILT_IN_LOGF:
25888 case BUILT_IN_LOG10F:
25889 case BUILT_IN_POWF:
25890 case BUILT_IN_TANHF:
25891 case BUILT_IN_TANF:
25892 case BUILT_IN_ATANF:
25893 case BUILT_IN_ATAN2F:
25894 case BUILT_IN_ATANHF:
25895 case BUILT_IN_CBRTF:
25896 case BUILT_IN_SINHF:
25897 case BUILT_IN_SINF:
25898 case BUILT_IN_ASINHF:
25899 case BUILT_IN_ASINF:
25900 case BUILT_IN_COSHF:
25901 case BUILT_IN_COSF:
25902 case BUILT_IN_ACOSHF:
25903 case BUILT_IN_ACOSF:
25904 if (el_mode != SFmode || n != 4)
25912 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25914 if (fn == BUILT_IN_LOGF)
25915 strcpy (name, "vmlsLn4");
25916 else if (fn == BUILT_IN_LOG)
25917 strcpy (name, "vmldLn2");
25920 sprintf (name, "vmls%s", bname+10);
25921 name[strlen (name)-1] = '4';
25924 sprintf (name, "vmld%s2", bname+10);
25926 /* Convert to uppercase. */
25930 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25931 args = TREE_CHAIN (args))
25935 fntype = build_function_type_list (type_out, type_in, NULL);
25937 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25939 /* Build a function declaration for the vectorized function. */
25940 new_fndecl = build_decl (BUILTINS_LOCATION,
25941 FUNCTION_DECL, get_identifier (name), fntype);
25942 TREE_PUBLIC (new_fndecl) = 1;
25943 DECL_EXTERNAL (new_fndecl) = 1;
25944 DECL_IS_NOVOPS (new_fndecl) = 1;
25945 TREE_READONLY (new_fndecl) = 1;
25950 /* Handler for an ACML-style interface to
25951 a library with vectorized intrinsics. */
25954 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25956 char name[20] = "__vr.._";
25957 tree fntype, new_fndecl, args;
25960 enum machine_mode el_mode, in_mode;
25963 /* The ACML is 64bits only and suitable for unsafe math only as
25964 it does not correctly support parts of IEEE with the required
25965 precision such as denormals. */
25967 || !flag_unsafe_math_optimizations)
25970 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25971 n = TYPE_VECTOR_SUBPARTS (type_out);
25972 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25973 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25974 if (el_mode != in_mode
25984 case BUILT_IN_LOG2:
25985 case BUILT_IN_LOG10:
25988 if (el_mode != DFmode
25993 case BUILT_IN_SINF:
25994 case BUILT_IN_COSF:
25995 case BUILT_IN_EXPF:
25996 case BUILT_IN_POWF:
25997 case BUILT_IN_LOGF:
25998 case BUILT_IN_LOG2F:
25999 case BUILT_IN_LOG10F:
26002 if (el_mode != SFmode
26011 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
26012 sprintf (name + 7, "%s", bname+10);
26015 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
26016 args = TREE_CHAIN (args))
26020 fntype = build_function_type_list (type_out, type_in, NULL);
26022 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
26024 /* Build a function declaration for the vectorized function. */
26025 new_fndecl = build_decl (BUILTINS_LOCATION,
26026 FUNCTION_DECL, get_identifier (name), fntype);
26027 TREE_PUBLIC (new_fndecl) = 1;
26028 DECL_EXTERNAL (new_fndecl) = 1;
26029 DECL_IS_NOVOPS (new_fndecl) = 1;
26030 TREE_READONLY (new_fndecl) = 1;
26036 /* Returns a decl of a function that implements conversion of an integer vector
26037 into a floating-point vector, or vice-versa. TYPE is the type of the integer
26038 side of the conversion.
26039 Return NULL_TREE if it is not available. */
26042 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
26044 if (! (TARGET_SSE2 && TREE_CODE (type) == VECTOR_TYPE))
26050 switch (TYPE_MODE (type))
26053 return TYPE_UNSIGNED (type)
26054 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
26055 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
26060 case FIX_TRUNC_EXPR:
26061 switch (TYPE_MODE (type))
26064 return TYPE_UNSIGNED (type)
26066 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
26076 /* Returns a code for a target-specific builtin that implements
26077 reciprocal of the function, or NULL_TREE if not available. */
26080 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
26081 bool sqrt ATTRIBUTE_UNUSED)
26083 if (! (TARGET_SSE_MATH && !optimize_insn_for_size_p ()
26084 && flag_finite_math_only && !flag_trapping_math
26085 && flag_unsafe_math_optimizations))
26089 /* Machine dependent builtins. */
26092 /* Vectorized version of sqrt to rsqrt conversion. */
26093 case IX86_BUILTIN_SQRTPS_NR:
26094 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
26100 /* Normal builtins. */
26103 /* Sqrt to rsqrt conversion. */
26104 case BUILT_IN_SQRTF:
26105 return ix86_builtins[IX86_BUILTIN_RSQRTF];
26112 /* Store OPERAND to the memory after reload is completed. This means
26113 that we can't easily use assign_stack_local. */
26115 ix86_force_to_memory (enum machine_mode mode, rtx operand)
26119 gcc_assert (reload_completed);
26120 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
26122 result = gen_rtx_MEM (mode,
26123 gen_rtx_PLUS (Pmode,
26125 GEN_INT (-RED_ZONE_SIZE)));
26126 emit_move_insn (result, operand);
26128 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
26134 operand = gen_lowpart (DImode, operand);
26138 gen_rtx_SET (VOIDmode,
26139 gen_rtx_MEM (DImode,
26140 gen_rtx_PRE_DEC (DImode,
26141 stack_pointer_rtx)),
26145 gcc_unreachable ();
26147 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26156 split_di (&operand, 1, operands, operands + 1);
26158 gen_rtx_SET (VOIDmode,
26159 gen_rtx_MEM (SImode,
26160 gen_rtx_PRE_DEC (Pmode,
26161 stack_pointer_rtx)),
26164 gen_rtx_SET (VOIDmode,
26165 gen_rtx_MEM (SImode,
26166 gen_rtx_PRE_DEC (Pmode,
26167 stack_pointer_rtx)),
26172 /* Store HImodes as SImodes. */
26173 operand = gen_lowpart (SImode, operand);
26177 gen_rtx_SET (VOIDmode,
26178 gen_rtx_MEM (GET_MODE (operand),
26179 gen_rtx_PRE_DEC (SImode,
26180 stack_pointer_rtx)),
26184 gcc_unreachable ();
26186 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26191 /* Free operand from the memory. */
26193 ix86_free_from_memory (enum machine_mode mode)
26195 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
26199 if (mode == DImode || TARGET_64BIT)
26203 /* Use LEA to deallocate stack space. In peephole2 it will be converted
26204 to pop or add instruction if registers are available. */
26205 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
26206 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
26211 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
26212 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
26214 static const enum reg_class *
26215 i386_ira_cover_classes (void)
26217 static const enum reg_class sse_fpmath_classes[] = {
26218 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
26220 static const enum reg_class no_sse_fpmath_classes[] = {
26221 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
26224 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
26227 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
26228 QImode must go into class Q_REGS.
26229 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
26230 movdf to do mem-to-mem moves through integer regs. */
26232 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
26234 enum machine_mode mode = GET_MODE (x);
26236 /* We're only allowed to return a subclass of CLASS. Many of the
26237 following checks fail for NO_REGS, so eliminate that early. */
26238 if (regclass == NO_REGS)
26241 /* All classes can load zeros. */
26242 if (x == CONST0_RTX (mode))
26245 /* Force constants into memory if we are loading a (nonzero) constant into
26246 an MMX or SSE register. This is because there are no MMX/SSE instructions
26247 to load from a constant. */
26249 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
26252 /* Prefer SSE regs only, if we can use them for math. */
26253 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
26254 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
26256 /* Floating-point constants need more complex checks. */
26257 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
26259 /* General regs can load everything. */
26260 if (reg_class_subset_p (regclass, GENERAL_REGS))
26263 /* Floats can load 0 and 1 plus some others. Note that we eliminated
26264 zero above. We only want to wind up preferring 80387 registers if
26265 we plan on doing computation with them. */
26267 && standard_80387_constant_p (x))
26269 /* Limit class to non-sse. */
26270 if (regclass == FLOAT_SSE_REGS)
26272 if (regclass == FP_TOP_SSE_REGS)
26274 if (regclass == FP_SECOND_SSE_REGS)
26275 return FP_SECOND_REG;
26276 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
26283 /* Generally when we see PLUS here, it's the function invariant
26284 (plus soft-fp const_int). Which can only be computed into general
26286 if (GET_CODE (x) == PLUS)
26287 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
26289 /* QImode constants are easy to load, but non-constant QImode data
26290 must go into Q_REGS. */
26291 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
26293 if (reg_class_subset_p (regclass, Q_REGS))
26295 if (reg_class_subset_p (Q_REGS, regclass))
26303 /* Discourage putting floating-point values in SSE registers unless
26304 SSE math is being used, and likewise for the 387 registers. */
26306 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
26308 enum machine_mode mode = GET_MODE (x);
26310 /* Restrict the output reload class to the register bank that we are doing
26311 math on. If we would like not to return a subset of CLASS, reject this
26312 alternative: if reload cannot do this, it will still use its choice. */
26313 mode = GET_MODE (x);
26314 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
26315 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
26317 if (X87_FLOAT_MODE_P (mode))
26319 if (regclass == FP_TOP_SSE_REGS)
26321 else if (regclass == FP_SECOND_SSE_REGS)
26322 return FP_SECOND_REG;
26324 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
26330 static enum reg_class
26331 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
26332 enum machine_mode mode,
26333 secondary_reload_info *sri ATTRIBUTE_UNUSED)
26335 /* QImode spills from non-QI registers require
26336 intermediate register on 32bit targets. */
26337 if (!in_p && mode == QImode && !TARGET_64BIT
26338 && (rclass == GENERAL_REGS
26339 || rclass == LEGACY_REGS
26340 || rclass == INDEX_REGS))
26349 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
26350 regno = true_regnum (x);
26352 /* Return Q_REGS if the operand is in memory. */
26360 /* If we are copying between general and FP registers, we need a memory
26361 location. The same is true for SSE and MMX registers.
26363 To optimize register_move_cost performance, allow inline variant.
26365 The macro can't work reliably when one of the CLASSES is class containing
26366 registers from multiple units (SSE, MMX, integer). We avoid this by never
26367 combining those units in single alternative in the machine description.
26368 Ensure that this constraint holds to avoid unexpected surprises.
26370 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
26371 enforce these sanity checks. */
26374 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26375 enum machine_mode mode, int strict)
26377 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
26378 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
26379 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
26380 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
26381 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
26382 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
26384 gcc_assert (!strict);
26388 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
26391 /* ??? This is a lie. We do have moves between mmx/general, and for
26392 mmx/sse2. But by saying we need secondary memory we discourage the
26393 register allocator from using the mmx registers unless needed. */
26394 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
26397 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26399 /* SSE1 doesn't have any direct moves from other classes. */
26403 /* If the target says that inter-unit moves are more expensive
26404 than moving through memory, then don't generate them. */
26405 if (!TARGET_INTER_UNIT_MOVES)
26408 /* Between SSE and general, we have moves no larger than word size. */
26409 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
26417 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26418 enum machine_mode mode, int strict)
26420 return inline_secondary_memory_needed (class1, class2, mode, strict);
26423 /* Return true if the registers in CLASS cannot represent the change from
26424 modes FROM to TO. */
26427 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
26428 enum reg_class regclass)
26433 /* x87 registers can't do subreg at all, as all values are reformatted
26434 to extended precision. */
26435 if (MAYBE_FLOAT_CLASS_P (regclass))
26438 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
26440 /* Vector registers do not support QI or HImode loads. If we don't
26441 disallow a change to these modes, reload will assume it's ok to
26442 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
26443 the vec_dupv4hi pattern. */
26444 if (GET_MODE_SIZE (from) < 4)
26447 /* Vector registers do not support subreg with nonzero offsets, which
26448 are otherwise valid for integer registers. Since we can't see
26449 whether we have a nonzero offset from here, prohibit all
26450 nonparadoxical subregs changing size. */
26451 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
26458 /* Return the cost of moving data of mode M between a
26459 register and memory. A value of 2 is the default; this cost is
26460 relative to those in `REGISTER_MOVE_COST'.
26462 This function is used extensively by register_move_cost that is used to
26463 build tables at startup. Make it inline in this case.
26464 When IN is 2, return maximum of in and out move cost.
26466 If moving between registers and memory is more expensive than
26467 between two registers, you should define this macro to express the
26470 Model also increased moving costs of QImode registers in non
26474 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
26478 if (FLOAT_CLASS_P (regclass))
26496 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
26497 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
26499 if (SSE_CLASS_P (regclass))
26502 switch (GET_MODE_SIZE (mode))
26517 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
26518 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
26520 if (MMX_CLASS_P (regclass))
26523 switch (GET_MODE_SIZE (mode))
26535 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
26536 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
26538 switch (GET_MODE_SIZE (mode))
26541 if (Q_CLASS_P (regclass) || TARGET_64BIT)
26544 return ix86_cost->int_store[0];
26545 if (TARGET_PARTIAL_REG_DEPENDENCY
26546 && optimize_function_for_speed_p (cfun))
26547 cost = ix86_cost->movzbl_load;
26549 cost = ix86_cost->int_load[0];
26551 return MAX (cost, ix86_cost->int_store[0]);
26557 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
26559 return ix86_cost->movzbl_load;
26561 return ix86_cost->int_store[0] + 4;
26566 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
26567 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
26569 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
26570 if (mode == TFmode)
26573 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
26575 cost = ix86_cost->int_load[2];
26577 cost = ix86_cost->int_store[2];
26578 return (cost * (((int) GET_MODE_SIZE (mode)
26579 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
26584 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
26586 return inline_memory_move_cost (mode, regclass, in);
26590 /* Return the cost of moving data from a register in class CLASS1 to
26591 one in class CLASS2.
26593 It is not required that the cost always equal 2 when FROM is the same as TO;
26594 on some machines it is expensive to move between registers if they are not
26595 general registers. */
26598 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
26599 enum reg_class class2)
26601 /* In case we require secondary memory, compute cost of the store followed
26602 by load. In order to avoid bad register allocation choices, we need
26603 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
26605 if (inline_secondary_memory_needed (class1, class2, mode, 0))
26609 cost += inline_memory_move_cost (mode, class1, 2);
26610 cost += inline_memory_move_cost (mode, class2, 2);
26612 /* In case of copying from general_purpose_register we may emit multiple
26613 stores followed by single load causing memory size mismatch stall.
26614 Count this as arbitrarily high cost of 20. */
26615 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
26618 /* In the case of FP/MMX moves, the registers actually overlap, and we
26619 have to switch modes in order to treat them differently. */
26620 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
26621 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
26627 /* Moves between SSE/MMX and integer unit are expensive. */
26628 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
26629 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26631 /* ??? By keeping returned value relatively high, we limit the number
26632 of moves between integer and MMX/SSE registers for all targets.
26633 Additionally, high value prevents problem with x86_modes_tieable_p(),
26634 where integer modes in MMX/SSE registers are not tieable
26635 because of missing QImode and HImode moves to, from or between
26636 MMX/SSE registers. */
26637 return MAX (8, ix86_cost->mmxsse_to_integer);
26639 if (MAYBE_FLOAT_CLASS_P (class1))
26640 return ix86_cost->fp_move;
26641 if (MAYBE_SSE_CLASS_P (class1))
26642 return ix86_cost->sse_move;
26643 if (MAYBE_MMX_CLASS_P (class1))
26644 return ix86_cost->mmx_move;
26648 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
26651 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
26653 /* Flags and only flags can only hold CCmode values. */
26654 if (CC_REGNO_P (regno))
26655 return GET_MODE_CLASS (mode) == MODE_CC;
26656 if (GET_MODE_CLASS (mode) == MODE_CC
26657 || GET_MODE_CLASS (mode) == MODE_RANDOM
26658 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
26660 if (FP_REGNO_P (regno))
26661 return VALID_FP_MODE_P (mode);
26662 if (SSE_REGNO_P (regno))
26664 /* We implement the move patterns for all vector modes into and
26665 out of SSE registers, even when no operation instructions
26666 are available. OImode move is available only when AVX is
26668 return ((TARGET_AVX && mode == OImode)
26669 || VALID_AVX256_REG_MODE (mode)
26670 || VALID_SSE_REG_MODE (mode)
26671 || VALID_SSE2_REG_MODE (mode)
26672 || VALID_MMX_REG_MODE (mode)
26673 || VALID_MMX_REG_MODE_3DNOW (mode));
26675 if (MMX_REGNO_P (regno))
26677 /* We implement the move patterns for 3DNOW modes even in MMX mode,
26678 so if the register is available at all, then we can move data of
26679 the given mode into or out of it. */
26680 return (VALID_MMX_REG_MODE (mode)
26681 || VALID_MMX_REG_MODE_3DNOW (mode));
26684 if (mode == QImode)
26686 /* Take care for QImode values - they can be in non-QI regs,
26687 but then they do cause partial register stalls. */
26688 if (regno <= BX_REG || TARGET_64BIT)
26690 if (!TARGET_PARTIAL_REG_STALL)
26692 return reload_in_progress || reload_completed;
26694 /* We handle both integer and floats in the general purpose registers. */
26695 else if (VALID_INT_MODE_P (mode))
26697 else if (VALID_FP_MODE_P (mode))
26699 else if (VALID_DFP_MODE_P (mode))
26701 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
26702 on to use that value in smaller contexts, this can easily force a
26703 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
26704 supporting DImode, allow it. */
26705 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
26711 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
26712 tieable integer mode. */
26715 ix86_tieable_integer_mode_p (enum machine_mode mode)
26724 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
26727 return TARGET_64BIT;
26734 /* Return true if MODE1 is accessible in a register that can hold MODE2
26735 without copying. That is, all register classes that can hold MODE2
26736 can also hold MODE1. */
26739 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
26741 if (mode1 == mode2)
26744 if (ix86_tieable_integer_mode_p (mode1)
26745 && ix86_tieable_integer_mode_p (mode2))
26748 /* MODE2 being XFmode implies fp stack or general regs, which means we
26749 can tie any smaller floating point modes to it. Note that we do not
26750 tie this with TFmode. */
26751 if (mode2 == XFmode)
26752 return mode1 == SFmode || mode1 == DFmode;
26754 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26755 that we can tie it with SFmode. */
26756 if (mode2 == DFmode)
26757 return mode1 == SFmode;
26759 /* If MODE2 is only appropriate for an SSE register, then tie with
26760 any other mode acceptable to SSE registers. */
26761 if (GET_MODE_SIZE (mode2) == 16
26762 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26763 return (GET_MODE_SIZE (mode1) == 16
26764 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26766 /* If MODE2 is appropriate for an MMX register, then tie
26767 with any other mode acceptable to MMX registers. */
26768 if (GET_MODE_SIZE (mode2) == 8
26769 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26770 return (GET_MODE_SIZE (mode1) == 8
26771 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26776 /* Compute a (partial) cost for rtx X. Return true if the complete
26777 cost has been computed, and false if subexpressions should be
26778 scanned. In either case, *TOTAL contains the cost result. */
26781 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26783 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26784 enum machine_mode mode = GET_MODE (x);
26785 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26793 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26795 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26797 else if (flag_pic && SYMBOLIC_CONST (x)
26799 || (!GET_CODE (x) != LABEL_REF
26800 && (GET_CODE (x) != SYMBOL_REF
26801 || !SYMBOL_REF_LOCAL_P (x)))))
26808 if (mode == VOIDmode)
26811 switch (standard_80387_constant_p (x))
26816 default: /* Other constants */
26821 /* Start with (MEM (SYMBOL_REF)), since that's where
26822 it'll probably end up. Add a penalty for size. */
26823 *total = (COSTS_N_INSNS (1)
26824 + (flag_pic != 0 && !TARGET_64BIT)
26825 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26831 /* The zero extensions is often completely free on x86_64, so make
26832 it as cheap as possible. */
26833 if (TARGET_64BIT && mode == DImode
26834 && GET_MODE (XEXP (x, 0)) == SImode)
26836 else if (TARGET_ZERO_EXTEND_WITH_AND)
26837 *total = cost->add;
26839 *total = cost->movzx;
26843 *total = cost->movsx;
26847 if (CONST_INT_P (XEXP (x, 1))
26848 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26850 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26853 *total = cost->add;
26856 if ((value == 2 || value == 3)
26857 && cost->lea <= cost->shift_const)
26859 *total = cost->lea;
26869 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26871 if (CONST_INT_P (XEXP (x, 1)))
26873 if (INTVAL (XEXP (x, 1)) > 32)
26874 *total = cost->shift_const + COSTS_N_INSNS (2);
26876 *total = cost->shift_const * 2;
26880 if (GET_CODE (XEXP (x, 1)) == AND)
26881 *total = cost->shift_var * 2;
26883 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26888 if (CONST_INT_P (XEXP (x, 1)))
26889 *total = cost->shift_const;
26891 *total = cost->shift_var;
26896 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26898 /* ??? SSE scalar cost should be used here. */
26899 *total = cost->fmul;
26902 else if (X87_FLOAT_MODE_P (mode))
26904 *total = cost->fmul;
26907 else if (FLOAT_MODE_P (mode))
26909 /* ??? SSE vector cost should be used here. */
26910 *total = cost->fmul;
26915 rtx op0 = XEXP (x, 0);
26916 rtx op1 = XEXP (x, 1);
26918 if (CONST_INT_P (XEXP (x, 1)))
26920 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26921 for (nbits = 0; value != 0; value &= value - 1)
26925 /* This is arbitrary. */
26928 /* Compute costs correctly for widening multiplication. */
26929 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26930 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26931 == GET_MODE_SIZE (mode))
26933 int is_mulwiden = 0;
26934 enum machine_mode inner_mode = GET_MODE (op0);
26936 if (GET_CODE (op0) == GET_CODE (op1))
26937 is_mulwiden = 1, op1 = XEXP (op1, 0);
26938 else if (CONST_INT_P (op1))
26940 if (GET_CODE (op0) == SIGN_EXTEND)
26941 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26944 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26948 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26951 *total = (cost->mult_init[MODE_INDEX (mode)]
26952 + nbits * cost->mult_bit
26953 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26962 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26963 /* ??? SSE cost should be used here. */
26964 *total = cost->fdiv;
26965 else if (X87_FLOAT_MODE_P (mode))
26966 *total = cost->fdiv;
26967 else if (FLOAT_MODE_P (mode))
26968 /* ??? SSE vector cost should be used here. */
26969 *total = cost->fdiv;
26971 *total = cost->divide[MODE_INDEX (mode)];
26975 if (GET_MODE_CLASS (mode) == MODE_INT
26976 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26978 if (GET_CODE (XEXP (x, 0)) == PLUS
26979 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26980 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26981 && CONSTANT_P (XEXP (x, 1)))
26983 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26984 if (val == 2 || val == 4 || val == 8)
26986 *total = cost->lea;
26987 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26988 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26989 outer_code, speed);
26990 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26994 else if (GET_CODE (XEXP (x, 0)) == MULT
26995 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26997 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26998 if (val == 2 || val == 4 || val == 8)
27000 *total = cost->lea;
27001 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
27002 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27006 else if (GET_CODE (XEXP (x, 0)) == PLUS)
27008 *total = cost->lea;
27009 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
27010 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
27011 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27018 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27020 /* ??? SSE cost should be used here. */
27021 *total = cost->fadd;
27024 else if (X87_FLOAT_MODE_P (mode))
27026 *total = cost->fadd;
27029 else if (FLOAT_MODE_P (mode))
27031 /* ??? SSE vector cost should be used here. */
27032 *total = cost->fadd;
27040 if (!TARGET_64BIT && mode == DImode)
27042 *total = (cost->add * 2
27043 + (rtx_cost (XEXP (x, 0), outer_code, speed)
27044 << (GET_MODE (XEXP (x, 0)) != DImode))
27045 + (rtx_cost (XEXP (x, 1), outer_code, speed)
27046 << (GET_MODE (XEXP (x, 1)) != DImode)));
27052 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27054 /* ??? SSE cost should be used here. */
27055 *total = cost->fchs;
27058 else if (X87_FLOAT_MODE_P (mode))
27060 *total = cost->fchs;
27063 else if (FLOAT_MODE_P (mode))
27065 /* ??? SSE vector cost should be used here. */
27066 *total = cost->fchs;
27072 if (!TARGET_64BIT && mode == DImode)
27073 *total = cost->add * 2;
27075 *total = cost->add;
27079 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
27080 && XEXP (XEXP (x, 0), 1) == const1_rtx
27081 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
27082 && XEXP (x, 1) == const0_rtx)
27084 /* This kind of construct is implemented using test[bwl].
27085 Treat it as if we had an AND. */
27086 *total = (cost->add
27087 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
27088 + rtx_cost (const1_rtx, outer_code, speed));
27094 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
27099 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27100 /* ??? SSE cost should be used here. */
27101 *total = cost->fabs;
27102 else if (X87_FLOAT_MODE_P (mode))
27103 *total = cost->fabs;
27104 else if (FLOAT_MODE_P (mode))
27105 /* ??? SSE vector cost should be used here. */
27106 *total = cost->fabs;
27110 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27111 /* ??? SSE cost should be used here. */
27112 *total = cost->fsqrt;
27113 else if (X87_FLOAT_MODE_P (mode))
27114 *total = cost->fsqrt;
27115 else if (FLOAT_MODE_P (mode))
27116 /* ??? SSE vector cost should be used here. */
27117 *total = cost->fsqrt;
27121 if (XINT (x, 1) == UNSPEC_TP)
27132 static int current_machopic_label_num;
27134 /* Given a symbol name and its associated stub, write out the
27135 definition of the stub. */
27138 machopic_output_stub (FILE *file, const char *symb, const char *stub)
27140 unsigned int length;
27141 char *binder_name, *symbol_name, lazy_ptr_name[32];
27142 int label = ++current_machopic_label_num;
27144 /* For 64-bit we shouldn't get here. */
27145 gcc_assert (!TARGET_64BIT);
27147 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
27148 symb = (*targetm.strip_name_encoding) (symb);
27150 length = strlen (stub);
27151 binder_name = XALLOCAVEC (char, length + 32);
27152 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
27154 length = strlen (symb);
27155 symbol_name = XALLOCAVEC (char, length + 32);
27156 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
27158 sprintf (lazy_ptr_name, "L%d$lz", label);
27161 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
27163 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
27165 fprintf (file, "%s:\n", stub);
27166 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27170 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
27171 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
27172 fprintf (file, "\tjmp\t*%%edx\n");
27175 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
27177 fprintf (file, "%s:\n", binder_name);
27181 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
27182 fputs ("\tpushl\t%eax\n", file);
27185 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
27187 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
27189 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
27190 fprintf (file, "%s:\n", lazy_ptr_name);
27191 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27192 fprintf (file, ASM_LONG "%s\n", binder_name);
27196 darwin_x86_file_end (void)
27198 darwin_file_end ();
27201 #endif /* TARGET_MACHO */
27203 /* Order the registers for register allocator. */
27206 x86_order_regs_for_local_alloc (void)
27211 /* First allocate the local general purpose registers. */
27212 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27213 if (GENERAL_REGNO_P (i) && call_used_regs[i])
27214 reg_alloc_order [pos++] = i;
27216 /* Global general purpose registers. */
27217 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27218 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
27219 reg_alloc_order [pos++] = i;
27221 /* x87 registers come first in case we are doing FP math
27223 if (!TARGET_SSE_MATH)
27224 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27225 reg_alloc_order [pos++] = i;
27227 /* SSE registers. */
27228 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
27229 reg_alloc_order [pos++] = i;
27230 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
27231 reg_alloc_order [pos++] = i;
27233 /* x87 registers. */
27234 if (TARGET_SSE_MATH)
27235 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27236 reg_alloc_order [pos++] = i;
27238 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
27239 reg_alloc_order [pos++] = i;
27241 /* Initialize the rest of array as we do not allocate some registers
27243 while (pos < FIRST_PSEUDO_REGISTER)
27244 reg_alloc_order [pos++] = 0;
27247 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
27248 struct attribute_spec.handler. */
27250 ix86_handle_abi_attribute (tree *node, tree name,
27251 tree args ATTRIBUTE_UNUSED,
27252 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27254 if (TREE_CODE (*node) != FUNCTION_TYPE
27255 && TREE_CODE (*node) != METHOD_TYPE
27256 && TREE_CODE (*node) != FIELD_DECL
27257 && TREE_CODE (*node) != TYPE_DECL)
27259 warning (OPT_Wattributes, "%qE attribute only applies to functions",
27261 *no_add_attrs = true;
27266 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
27268 *no_add_attrs = true;
27272 /* Can combine regparm with all attributes but fastcall. */
27273 if (is_attribute_p ("ms_abi", name))
27275 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
27277 error ("ms_abi and sysv_abi attributes are not compatible");
27282 else if (is_attribute_p ("sysv_abi", name))
27284 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
27286 error ("ms_abi and sysv_abi attributes are not compatible");
27295 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27296 struct attribute_spec.handler. */
27298 ix86_handle_struct_attribute (tree *node, tree name,
27299 tree args ATTRIBUTE_UNUSED,
27300 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27303 if (DECL_P (*node))
27305 if (TREE_CODE (*node) == TYPE_DECL)
27306 type = &TREE_TYPE (*node);
27311 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
27312 || TREE_CODE (*type) == UNION_TYPE)))
27314 warning (OPT_Wattributes, "%qE attribute ignored",
27316 *no_add_attrs = true;
27319 else if ((is_attribute_p ("ms_struct", name)
27320 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
27321 || ((is_attribute_p ("gcc_struct", name)
27322 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
27324 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
27326 *no_add_attrs = true;
27333 ix86_handle_fndecl_attribute (tree *node, tree name,
27334 tree args ATTRIBUTE_UNUSED,
27335 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27337 if (TREE_CODE (*node) != FUNCTION_DECL)
27339 warning (OPT_Wattributes, "%qE attribute only applies to functions",
27341 *no_add_attrs = true;
27347 warning (OPT_Wattributes, "%qE attribute only available for 32-bit",
27352 #ifndef HAVE_AS_IX86_SWAP
27353 sorry ("ms_hook_prologue attribute needs assembler swap suffix support");
27360 ix86_ms_bitfield_layout_p (const_tree record_type)
27362 return (TARGET_MS_BITFIELD_LAYOUT &&
27363 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
27364 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
27367 /* Returns an expression indicating where the this parameter is
27368 located on entry to the FUNCTION. */
27371 x86_this_parameter (tree function)
27373 tree type = TREE_TYPE (function);
27374 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
27379 const int *parm_regs;
27381 if (ix86_function_type_abi (type) == MS_ABI)
27382 parm_regs = x86_64_ms_abi_int_parameter_registers;
27384 parm_regs = x86_64_int_parameter_registers;
27385 return gen_rtx_REG (DImode, parm_regs[aggr]);
27388 nregs = ix86_function_regparm (type, function);
27390 if (nregs > 0 && !stdarg_p (type))
27394 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
27395 regno = aggr ? DX_REG : CX_REG;
27403 return gen_rtx_MEM (SImode,
27404 plus_constant (stack_pointer_rtx, 4));
27407 return gen_rtx_REG (SImode, regno);
27410 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
27413 /* Determine whether x86_output_mi_thunk can succeed. */
27416 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
27417 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
27418 HOST_WIDE_INT vcall_offset, const_tree function)
27420 /* 64-bit can handle anything. */
27424 /* For 32-bit, everything's fine if we have one free register. */
27425 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
27428 /* Need a free register for vcall_offset. */
27432 /* Need a free register for GOT references. */
27433 if (flag_pic && !(*targetm.binds_local_p) (function))
27436 /* Otherwise ok. */
27440 /* Output the assembler code for a thunk function. THUNK_DECL is the
27441 declaration for the thunk function itself, FUNCTION is the decl for
27442 the target function. DELTA is an immediate constant offset to be
27443 added to THIS. If VCALL_OFFSET is nonzero, the word at
27444 *(*this + vcall_offset) should be added to THIS. */
27447 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
27448 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
27449 HOST_WIDE_INT vcall_offset, tree function)
27452 rtx this_param = x86_this_parameter (function);
27455 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
27456 pull it in now and let DELTA benefit. */
27457 if (REG_P (this_param))
27458 this_reg = this_param;
27459 else if (vcall_offset)
27461 /* Put the this parameter into %eax. */
27462 xops[0] = this_param;
27463 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
27464 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27467 this_reg = NULL_RTX;
27469 /* Adjust the this parameter by a fixed constant. */
27472 xops[0] = GEN_INT (delta);
27473 xops[1] = this_reg ? this_reg : this_param;
27476 if (!x86_64_general_operand (xops[0], DImode))
27478 tmp = gen_rtx_REG (DImode, R10_REG);
27480 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
27482 xops[1] = this_param;
27484 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
27487 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
27490 /* Adjust the this parameter by a value stored in the vtable. */
27494 tmp = gen_rtx_REG (DImode, R10_REG);
27497 int tmp_regno = CX_REG;
27498 if (lookup_attribute ("fastcall",
27499 TYPE_ATTRIBUTES (TREE_TYPE (function))))
27500 tmp_regno = AX_REG;
27501 tmp = gen_rtx_REG (SImode, tmp_regno);
27504 xops[0] = gen_rtx_MEM (Pmode, this_reg);
27506 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27508 /* Adjust the this parameter. */
27509 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
27510 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
27512 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
27513 xops[0] = GEN_INT (vcall_offset);
27515 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
27516 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
27518 xops[1] = this_reg;
27519 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
27522 /* If necessary, drop THIS back to its stack slot. */
27523 if (this_reg && this_reg != this_param)
27525 xops[0] = this_reg;
27526 xops[1] = this_param;
27527 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27530 xops[0] = XEXP (DECL_RTL (function), 0);
27533 if (!flag_pic || (*targetm.binds_local_p) (function))
27534 output_asm_insn ("jmp\t%P0", xops);
27535 /* All thunks should be in the same object as their target,
27536 and thus binds_local_p should be true. */
27537 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
27538 gcc_unreachable ();
27541 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
27542 tmp = gen_rtx_CONST (Pmode, tmp);
27543 tmp = gen_rtx_MEM (QImode, tmp);
27545 output_asm_insn ("jmp\t%A0", xops);
27550 if (!flag_pic || (*targetm.binds_local_p) (function))
27551 output_asm_insn ("jmp\t%P0", xops);
27556 rtx sym_ref = XEXP (DECL_RTL (function), 0);
27557 tmp = (gen_rtx_SYMBOL_REF
27559 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
27560 tmp = gen_rtx_MEM (QImode, tmp);
27562 output_asm_insn ("jmp\t%0", xops);
27565 #endif /* TARGET_MACHO */
27567 tmp = gen_rtx_REG (SImode, CX_REG);
27568 output_set_got (tmp, NULL_RTX);
27571 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
27572 output_asm_insn ("jmp\t{*}%1", xops);
27578 x86_file_start (void)
27580 default_file_start ();
27582 darwin_file_start ();
27584 if (X86_FILE_START_VERSION_DIRECTIVE)
27585 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
27586 if (X86_FILE_START_FLTUSED)
27587 fputs ("\t.global\t__fltused\n", asm_out_file);
27588 if (ix86_asm_dialect == ASM_INTEL)
27589 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
27593 x86_field_alignment (tree field, int computed)
27595 enum machine_mode mode;
27596 tree type = TREE_TYPE (field);
27598 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
27600 mode = TYPE_MODE (strip_array_types (type));
27601 if (mode == DFmode || mode == DCmode
27602 || GET_MODE_CLASS (mode) == MODE_INT
27603 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
27604 return MIN (32, computed);
27608 /* Output assembler code to FILE to increment profiler label # LABELNO
27609 for profiling a function entry. */
27611 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
27615 #ifndef NO_PROFILE_COUNTERS
27616 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
27619 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
27620 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
27622 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
27626 #ifndef NO_PROFILE_COUNTERS
27627 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
27630 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
27634 #ifndef NO_PROFILE_COUNTERS
27635 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
27638 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
27642 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27643 /* We don't have exact information about the insn sizes, but we may assume
27644 quite safely that we are informed about all 1 byte insns and memory
27645 address sizes. This is enough to eliminate unnecessary padding in
27649 min_insn_size (rtx insn)
27653 if (!INSN_P (insn) || !active_insn_p (insn))
27656 /* Discard alignments we've emit and jump instructions. */
27657 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
27658 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
27660 if (JUMP_TABLE_DATA_P (insn))
27663 /* Important case - calls are always 5 bytes.
27664 It is common to have many calls in the row. */
27666 && symbolic_reference_mentioned_p (PATTERN (insn))
27667 && !SIBLING_CALL_P (insn))
27669 len = get_attr_length (insn);
27673 /* For normal instructions we rely on get_attr_length being exact,
27674 with a few exceptions. */
27675 if (!JUMP_P (insn))
27677 enum attr_type type = get_attr_type (insn);
27682 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
27683 || asm_noperands (PATTERN (insn)) >= 0)
27690 /* Otherwise trust get_attr_length. */
27694 l = get_attr_length_address (insn);
27695 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
27704 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
27708 ix86_avoid_jump_mispredicts (void)
27710 rtx insn, start = get_insns ();
27711 int nbytes = 0, njumps = 0;
27714 /* Look for all minimal intervals of instructions containing 4 jumps.
27715 The intervals are bounded by START and INSN. NBYTES is the total
27716 size of instructions in the interval including INSN and not including
27717 START. When the NBYTES is smaller than 16 bytes, it is possible
27718 that the end of START and INSN ends up in the same 16byte page.
27720 The smallest offset in the page INSN can start is the case where START
27721 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
27722 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
27724 for (insn = start; insn; insn = NEXT_INSN (insn))
27728 if (LABEL_P (insn))
27730 int align = label_to_alignment (insn);
27731 int max_skip = label_to_max_skip (insn);
27735 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
27736 already in the current 16 byte page, because otherwise
27737 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
27738 bytes to reach 16 byte boundary. */
27740 || (align <= 3 && max_skip != (1 << align) - 1))
27743 fprintf (dump_file, "Label %i with max_skip %i\n",
27744 INSN_UID (insn), max_skip);
27747 while (nbytes + max_skip >= 16)
27749 start = NEXT_INSN (start);
27750 if ((JUMP_P (start)
27751 && GET_CODE (PATTERN (start)) != ADDR_VEC
27752 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27754 njumps--, isjump = 1;
27757 nbytes -= min_insn_size (start);
27763 min_size = min_insn_size (insn);
27764 nbytes += min_size;
27766 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
27767 INSN_UID (insn), min_size);
27769 && GET_CODE (PATTERN (insn)) != ADDR_VEC
27770 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
27778 start = NEXT_INSN (start);
27779 if ((JUMP_P (start)
27780 && GET_CODE (PATTERN (start)) != ADDR_VEC
27781 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27783 njumps--, isjump = 1;
27786 nbytes -= min_insn_size (start);
27788 gcc_assert (njumps >= 0);
27790 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
27791 INSN_UID (start), INSN_UID (insn), nbytes);
27793 if (njumps == 3 && isjump && nbytes < 16)
27795 int padsize = 15 - nbytes + min_insn_size (insn);
27798 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
27799 INSN_UID (insn), padsize);
27800 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
27806 /* AMD Athlon works faster
27807 when RET is not destination of conditional jump or directly preceded
27808 by other jump instruction. We avoid the penalty by inserting NOP just
27809 before the RET instructions in such cases. */
27811 ix86_pad_returns (void)
27816 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27818 basic_block bb = e->src;
27819 rtx ret = BB_END (bb);
27821 bool replace = false;
27823 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27824 || optimize_bb_for_size_p (bb))
27826 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27827 if (active_insn_p (prev) || LABEL_P (prev))
27829 if (prev && LABEL_P (prev))
27834 FOR_EACH_EDGE (e, ei, bb->preds)
27835 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27836 && !(e->flags & EDGE_FALLTHRU))
27841 prev = prev_active_insn (ret);
27843 && ((JUMP_P (prev) && any_condjump_p (prev))
27846 /* Empty functions get branch mispredict even when the jump destination
27847 is not visible to us. */
27848 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27853 emit_jump_insn_before (gen_return_internal_long (), ret);
27859 /* Implement machine specific optimizations. We implement padding of returns
27860 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27864 if (optimize && optimize_function_for_speed_p (cfun))
27866 if (TARGET_PAD_RETURNS)
27867 ix86_pad_returns ();
27868 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27869 if (TARGET_FOUR_JUMP_LIMIT)
27870 ix86_avoid_jump_mispredicts ();
27875 /* Return nonzero when QImode register that must be represented via REX prefix
27878 x86_extended_QIreg_mentioned_p (rtx insn)
27881 extract_insn_cached (insn);
27882 for (i = 0; i < recog_data.n_operands; i++)
27883 if (REG_P (recog_data.operand[i])
27884 && REGNO (recog_data.operand[i]) > BX_REG)
27889 /* Return nonzero when P points to register encoded via REX prefix.
27890 Called via for_each_rtx. */
27892 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27894 unsigned int regno;
27897 regno = REGNO (*p);
27898 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27901 /* Return true when INSN mentions register that must be encoded using REX
27904 x86_extended_reg_mentioned_p (rtx insn)
27906 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27907 extended_reg_mentioned_1, NULL);
27910 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27911 optabs would emit if we didn't have TFmode patterns. */
27914 x86_emit_floatuns (rtx operands[2])
27916 rtx neglab, donelab, i0, i1, f0, in, out;
27917 enum machine_mode mode, inmode;
27919 inmode = GET_MODE (operands[1]);
27920 gcc_assert (inmode == SImode || inmode == DImode);
27923 in = force_reg (inmode, operands[1]);
27924 mode = GET_MODE (out);
27925 neglab = gen_label_rtx ();
27926 donelab = gen_label_rtx ();
27927 f0 = gen_reg_rtx (mode);
27929 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27931 expand_float (out, in, 0);
27933 emit_jump_insn (gen_jump (donelab));
27936 emit_label (neglab);
27938 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27940 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27942 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27944 expand_float (f0, i0, 0);
27946 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27948 emit_label (donelab);
27951 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27952 with all elements equal to VAR. Return true if successful. */
27955 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27956 rtx target, rtx val)
27958 enum machine_mode hmode, smode, wsmode, wvmode;
27973 val = force_reg (GET_MODE_INNER (mode), val);
27974 x = gen_rtx_VEC_DUPLICATE (mode, val);
27975 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27981 if (TARGET_SSE || TARGET_3DNOW_A)
27983 val = gen_lowpart (SImode, val);
27984 x = gen_rtx_TRUNCATE (HImode, val);
27985 x = gen_rtx_VEC_DUPLICATE (mode, x);
27986 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28008 /* Extend HImode to SImode using a paradoxical SUBREG. */
28009 tmp1 = gen_reg_rtx (SImode);
28010 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28011 /* Insert the SImode value as low element of V4SImode vector. */
28012 tmp2 = gen_reg_rtx (V4SImode);
28013 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28014 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28015 CONST0_RTX (V4SImode),
28017 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28018 /* Cast the V4SImode vector back to a V8HImode vector. */
28019 tmp1 = gen_reg_rtx (V8HImode);
28020 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
28021 /* Duplicate the low short through the whole low SImode word. */
28022 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
28023 /* Cast the V8HImode vector back to a V4SImode vector. */
28024 tmp2 = gen_reg_rtx (V4SImode);
28025 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28026 /* Replicate the low element of the V4SImode vector. */
28027 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28028 /* Cast the V2SImode back to V8HImode, and store in target. */
28029 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
28040 /* Extend QImode to SImode using a paradoxical SUBREG. */
28041 tmp1 = gen_reg_rtx (SImode);
28042 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28043 /* Insert the SImode value as low element of V4SImode vector. */
28044 tmp2 = gen_reg_rtx (V4SImode);
28045 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28046 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28047 CONST0_RTX (V4SImode),
28049 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28050 /* Cast the V4SImode vector back to a V16QImode vector. */
28051 tmp1 = gen_reg_rtx (V16QImode);
28052 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
28053 /* Duplicate the low byte through the whole low SImode word. */
28054 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28055 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28056 /* Cast the V16QImode vector back to a V4SImode vector. */
28057 tmp2 = gen_reg_rtx (V4SImode);
28058 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28059 /* Replicate the low element of the V4SImode vector. */
28060 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28061 /* Cast the V2SImode back to V16QImode, and store in target. */
28062 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
28070 /* Replicate the value once into the next wider mode and recurse. */
28071 val = convert_modes (wsmode, smode, val, true);
28072 x = expand_simple_binop (wsmode, ASHIFT, val,
28073 GEN_INT (GET_MODE_BITSIZE (smode)),
28074 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28075 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
28077 x = gen_reg_rtx (wvmode);
28078 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
28079 gcc_unreachable ();
28080 emit_move_insn (target, gen_lowpart (mode, x));
28103 rtx tmp = gen_reg_rtx (hmode);
28104 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
28105 emit_insn (gen_rtx_SET (VOIDmode, target,
28106 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
28115 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28116 whose ONE_VAR element is VAR, and other elements are zero. Return true
28120 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
28121 rtx target, rtx var, int one_var)
28123 enum machine_mode vsimode;
28126 bool use_vector_set = false;
28131 /* For SSE4.1, we normally use vector set. But if the second
28132 element is zero and inter-unit moves are OK, we use movq
28134 use_vector_set = (TARGET_64BIT
28136 && !(TARGET_INTER_UNIT_MOVES
28142 use_vector_set = TARGET_SSE4_1;
28145 use_vector_set = TARGET_SSE2;
28148 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
28155 use_vector_set = TARGET_AVX;
28158 /* Use ix86_expand_vector_set in 64bit mode only. */
28159 use_vector_set = TARGET_AVX && TARGET_64BIT;
28165 if (use_vector_set)
28167 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
28168 var = force_reg (GET_MODE_INNER (mode), var);
28169 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28185 var = force_reg (GET_MODE_INNER (mode), var);
28186 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
28187 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28192 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
28193 new_target = gen_reg_rtx (mode);
28195 new_target = target;
28196 var = force_reg (GET_MODE_INNER (mode), var);
28197 x = gen_rtx_VEC_DUPLICATE (mode, var);
28198 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
28199 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
28202 /* We need to shuffle the value to the correct position, so
28203 create a new pseudo to store the intermediate result. */
28205 /* With SSE2, we can use the integer shuffle insns. */
28206 if (mode != V4SFmode && TARGET_SSE2)
28208 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
28210 GEN_INT (one_var == 1 ? 0 : 1),
28211 GEN_INT (one_var == 2 ? 0 : 1),
28212 GEN_INT (one_var == 3 ? 0 : 1)));
28213 if (target != new_target)
28214 emit_move_insn (target, new_target);
28218 /* Otherwise convert the intermediate result to V4SFmode and
28219 use the SSE1 shuffle instructions. */
28220 if (mode != V4SFmode)
28222 tmp = gen_reg_rtx (V4SFmode);
28223 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
28228 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
28230 GEN_INT (one_var == 1 ? 0 : 1),
28231 GEN_INT (one_var == 2 ? 0+4 : 1+4),
28232 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
28234 if (mode != V4SFmode)
28235 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
28236 else if (tmp != target)
28237 emit_move_insn (target, tmp);
28239 else if (target != new_target)
28240 emit_move_insn (target, new_target);
28245 vsimode = V4SImode;
28251 vsimode = V2SImode;
28257 /* Zero extend the variable element to SImode and recurse. */
28258 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
28260 x = gen_reg_rtx (vsimode);
28261 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
28263 gcc_unreachable ();
28265 emit_move_insn (target, gen_lowpart (mode, x));
28273 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28274 consisting of the values in VALS. It is known that all elements
28275 except ONE_VAR are constants. Return true if successful. */
28278 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
28279 rtx target, rtx vals, int one_var)
28281 rtx var = XVECEXP (vals, 0, one_var);
28282 enum machine_mode wmode;
28285 const_vec = copy_rtx (vals);
28286 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
28287 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
28295 /* For the two element vectors, it's just as easy to use
28296 the general case. */
28300 /* Use ix86_expand_vector_set in 64bit mode only. */
28323 /* There's no way to set one QImode entry easily. Combine
28324 the variable value with its adjacent constant value, and
28325 promote to an HImode set. */
28326 x = XVECEXP (vals, 0, one_var ^ 1);
28329 var = convert_modes (HImode, QImode, var, true);
28330 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
28331 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28332 x = GEN_INT (INTVAL (x) & 0xff);
28336 var = convert_modes (HImode, QImode, var, true);
28337 x = gen_int_mode (INTVAL (x) << 8, HImode);
28339 if (x != const0_rtx)
28340 var = expand_simple_binop (HImode, IOR, var, x, var,
28341 1, OPTAB_LIB_WIDEN);
28343 x = gen_reg_rtx (wmode);
28344 emit_move_insn (x, gen_lowpart (wmode, const_vec));
28345 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
28347 emit_move_insn (target, gen_lowpart (mode, x));
28354 emit_move_insn (target, const_vec);
28355 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28359 /* A subroutine of ix86_expand_vector_init_general. Use vector
28360 concatenate to handle the most general case: all values variable,
28361 and none identical. */
28364 ix86_expand_vector_init_concat (enum machine_mode mode,
28365 rtx target, rtx *ops, int n)
28367 enum machine_mode cmode, hmode = VOIDmode;
28368 rtx first[8], second[4];
28408 gcc_unreachable ();
28411 if (!register_operand (ops[1], cmode))
28412 ops[1] = force_reg (cmode, ops[1]);
28413 if (!register_operand (ops[0], cmode))
28414 ops[0] = force_reg (cmode, ops[0]);
28415 emit_insn (gen_rtx_SET (VOIDmode, target,
28416 gen_rtx_VEC_CONCAT (mode, ops[0],
28436 gcc_unreachable ();
28452 gcc_unreachable ();
28457 /* FIXME: We process inputs backward to help RA. PR 36222. */
28460 for (; i > 0; i -= 2, j--)
28462 first[j] = gen_reg_rtx (cmode);
28463 v = gen_rtvec (2, ops[i - 1], ops[i]);
28464 ix86_expand_vector_init (false, first[j],
28465 gen_rtx_PARALLEL (cmode, v));
28471 gcc_assert (hmode != VOIDmode);
28472 for (i = j = 0; i < n; i += 2, j++)
28474 second[j] = gen_reg_rtx (hmode);
28475 ix86_expand_vector_init_concat (hmode, second [j],
28479 ix86_expand_vector_init_concat (mode, target, second, n);
28482 ix86_expand_vector_init_concat (mode, target, first, n);
28486 gcc_unreachable ();
28490 /* A subroutine of ix86_expand_vector_init_general. Use vector
28491 interleave to handle the most general case: all values variable,
28492 and none identical. */
28495 ix86_expand_vector_init_interleave (enum machine_mode mode,
28496 rtx target, rtx *ops, int n)
28498 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
28501 rtx (*gen_load_even) (rtx, rtx, rtx);
28502 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
28503 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
28508 gen_load_even = gen_vec_setv8hi;
28509 gen_interleave_first_low = gen_vec_interleave_lowv4si;
28510 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28511 inner_mode = HImode;
28512 first_imode = V4SImode;
28513 second_imode = V2DImode;
28514 third_imode = VOIDmode;
28517 gen_load_even = gen_vec_setv16qi;
28518 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
28519 gen_interleave_second_low = gen_vec_interleave_lowv4si;
28520 inner_mode = QImode;
28521 first_imode = V8HImode;
28522 second_imode = V4SImode;
28523 third_imode = V2DImode;
28526 gcc_unreachable ();
28529 for (i = 0; i < n; i++)
28531 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
28532 op0 = gen_reg_rtx (SImode);
28533 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
28535 /* Insert the SImode value as low element of V4SImode vector. */
28536 op1 = gen_reg_rtx (V4SImode);
28537 op0 = gen_rtx_VEC_MERGE (V4SImode,
28538 gen_rtx_VEC_DUPLICATE (V4SImode,
28540 CONST0_RTX (V4SImode),
28542 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
28544 /* Cast the V4SImode vector back to a vector in orignal mode. */
28545 op0 = gen_reg_rtx (mode);
28546 emit_move_insn (op0, gen_lowpart (mode, op1));
28548 /* Load even elements into the second positon. */
28549 emit_insn ((*gen_load_even) (op0,
28550 force_reg (inner_mode,
28554 /* Cast vector to FIRST_IMODE vector. */
28555 ops[i] = gen_reg_rtx (first_imode);
28556 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
28559 /* Interleave low FIRST_IMODE vectors. */
28560 for (i = j = 0; i < n; i += 2, j++)
28562 op0 = gen_reg_rtx (first_imode);
28563 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
28565 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
28566 ops[j] = gen_reg_rtx (second_imode);
28567 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
28570 /* Interleave low SECOND_IMODE vectors. */
28571 switch (second_imode)
28574 for (i = j = 0; i < n / 2; i += 2, j++)
28576 op0 = gen_reg_rtx (second_imode);
28577 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
28580 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
28582 ops[j] = gen_reg_rtx (third_imode);
28583 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
28585 second_imode = V2DImode;
28586 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28590 op0 = gen_reg_rtx (second_imode);
28591 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
28594 /* Cast the SECOND_IMODE vector back to a vector on original
28596 emit_insn (gen_rtx_SET (VOIDmode, target,
28597 gen_lowpart (mode, op0)));
28601 gcc_unreachable ();
28605 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
28606 all values variable, and none identical. */
28609 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
28610 rtx target, rtx vals)
28612 rtx ops[32], op0, op1;
28613 enum machine_mode half_mode = VOIDmode;
28620 if (!mmx_ok && !TARGET_SSE)
28632 n = GET_MODE_NUNITS (mode);
28633 for (i = 0; i < n; i++)
28634 ops[i] = XVECEXP (vals, 0, i);
28635 ix86_expand_vector_init_concat (mode, target, ops, n);
28639 half_mode = V16QImode;
28643 half_mode = V8HImode;
28647 n = GET_MODE_NUNITS (mode);
28648 for (i = 0; i < n; i++)
28649 ops[i] = XVECEXP (vals, 0, i);
28650 op0 = gen_reg_rtx (half_mode);
28651 op1 = gen_reg_rtx (half_mode);
28652 ix86_expand_vector_init_interleave (half_mode, op0, ops,
28654 ix86_expand_vector_init_interleave (half_mode, op1,
28655 &ops [n >> 1], n >> 2);
28656 emit_insn (gen_rtx_SET (VOIDmode, target,
28657 gen_rtx_VEC_CONCAT (mode, op0, op1)));
28661 if (!TARGET_SSE4_1)
28669 /* Don't use ix86_expand_vector_init_interleave if we can't
28670 move from GPR to SSE register directly. */
28671 if (!TARGET_INTER_UNIT_MOVES)
28674 n = GET_MODE_NUNITS (mode);
28675 for (i = 0; i < n; i++)
28676 ops[i] = XVECEXP (vals, 0, i);
28677 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
28685 gcc_unreachable ();
28689 int i, j, n_elts, n_words, n_elt_per_word;
28690 enum machine_mode inner_mode;
28691 rtx words[4], shift;
28693 inner_mode = GET_MODE_INNER (mode);
28694 n_elts = GET_MODE_NUNITS (mode);
28695 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
28696 n_elt_per_word = n_elts / n_words;
28697 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
28699 for (i = 0; i < n_words; ++i)
28701 rtx word = NULL_RTX;
28703 for (j = 0; j < n_elt_per_word; ++j)
28705 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
28706 elt = convert_modes (word_mode, inner_mode, elt, true);
28712 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
28713 word, 1, OPTAB_LIB_WIDEN);
28714 word = expand_simple_binop (word_mode, IOR, word, elt,
28715 word, 1, OPTAB_LIB_WIDEN);
28723 emit_move_insn (target, gen_lowpart (mode, words[0]));
28724 else if (n_words == 2)
28726 rtx tmp = gen_reg_rtx (mode);
28727 emit_clobber (tmp);
28728 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
28729 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
28730 emit_move_insn (target, tmp);
28732 else if (n_words == 4)
28734 rtx tmp = gen_reg_rtx (V4SImode);
28735 gcc_assert (word_mode == SImode);
28736 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
28737 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
28738 emit_move_insn (target, gen_lowpart (mode, tmp));
28741 gcc_unreachable ();
28745 /* Initialize vector TARGET via VALS. Suppress the use of MMX
28746 instructions unless MMX_OK is true. */
28749 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
28751 enum machine_mode mode = GET_MODE (target);
28752 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28753 int n_elts = GET_MODE_NUNITS (mode);
28754 int n_var = 0, one_var = -1;
28755 bool all_same = true, all_const_zero = true;
28759 for (i = 0; i < n_elts; ++i)
28761 x = XVECEXP (vals, 0, i);
28762 if (!(CONST_INT_P (x)
28763 || GET_CODE (x) == CONST_DOUBLE
28764 || GET_CODE (x) == CONST_FIXED))
28765 n_var++, one_var = i;
28766 else if (x != CONST0_RTX (inner_mode))
28767 all_const_zero = false;
28768 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
28772 /* Constants are best loaded from the constant pool. */
28775 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
28779 /* If all values are identical, broadcast the value. */
28781 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
28782 XVECEXP (vals, 0, 0)))
28785 /* Values where only one field is non-constant are best loaded from
28786 the pool and overwritten via move later. */
28790 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
28791 XVECEXP (vals, 0, one_var),
28795 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
28799 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
28803 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
28805 enum machine_mode mode = GET_MODE (target);
28806 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28807 enum machine_mode half_mode;
28808 bool use_vec_merge = false;
28810 static rtx (*gen_extract[6][2]) (rtx, rtx)
28812 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
28813 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
28814 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
28815 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
28816 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
28817 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
28819 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28821 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28822 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28823 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28824 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28825 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28826 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28836 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28837 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28839 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28841 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28842 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28848 use_vec_merge = TARGET_SSE4_1;
28856 /* For the two element vectors, we implement a VEC_CONCAT with
28857 the extraction of the other element. */
28859 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28860 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28863 op0 = val, op1 = tmp;
28865 op0 = tmp, op1 = val;
28867 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28868 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28873 use_vec_merge = TARGET_SSE4_1;
28880 use_vec_merge = true;
28884 /* tmp = target = A B C D */
28885 tmp = copy_to_reg (target);
28886 /* target = A A B B */
28887 emit_insn (gen_sse_unpcklps (target, target, target));
28888 /* target = X A B B */
28889 ix86_expand_vector_set (false, target, val, 0);
28890 /* target = A X C D */
28891 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28892 const1_rtx, const0_rtx,
28893 GEN_INT (2+4), GEN_INT (3+4)));
28897 /* tmp = target = A B C D */
28898 tmp = copy_to_reg (target);
28899 /* tmp = X B C D */
28900 ix86_expand_vector_set (false, tmp, val, 0);
28901 /* target = A B X D */
28902 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28903 const0_rtx, const1_rtx,
28904 GEN_INT (0+4), GEN_INT (3+4)));
28908 /* tmp = target = A B C D */
28909 tmp = copy_to_reg (target);
28910 /* tmp = X B C D */
28911 ix86_expand_vector_set (false, tmp, val, 0);
28912 /* target = A B X D */
28913 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28914 const0_rtx, const1_rtx,
28915 GEN_INT (2+4), GEN_INT (0+4)));
28919 gcc_unreachable ();
28924 use_vec_merge = TARGET_SSE4_1;
28928 /* Element 0 handled by vec_merge below. */
28931 use_vec_merge = true;
28937 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28938 store into element 0, then shuffle them back. */
28942 order[0] = GEN_INT (elt);
28943 order[1] = const1_rtx;
28944 order[2] = const2_rtx;
28945 order[3] = GEN_INT (3);
28946 order[elt] = const0_rtx;
28948 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28949 order[1], order[2], order[3]));
28951 ix86_expand_vector_set (false, target, val, 0);
28953 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28954 order[1], order[2], order[3]));
28958 /* For SSE1, we have to reuse the V4SF code. */
28959 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28960 gen_lowpart (SFmode, val), elt);
28965 use_vec_merge = TARGET_SSE2;
28968 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28972 use_vec_merge = TARGET_SSE4_1;
28979 half_mode = V16QImode;
28985 half_mode = V8HImode;
28991 half_mode = V4SImode;
28997 half_mode = V2DImode;
29003 half_mode = V4SFmode;
29009 half_mode = V2DFmode;
29015 /* Compute offset. */
29019 gcc_assert (i <= 1);
29021 /* Extract the half. */
29022 tmp = gen_reg_rtx (half_mode);
29023 emit_insn ((*gen_extract[j][i]) (tmp, target));
29025 /* Put val in tmp at elt. */
29026 ix86_expand_vector_set (false, tmp, val, elt);
29029 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
29038 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
29039 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
29040 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29044 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29046 emit_move_insn (mem, target);
29048 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29049 emit_move_insn (tmp, val);
29051 emit_move_insn (target, mem);
29056 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
29058 enum machine_mode mode = GET_MODE (vec);
29059 enum machine_mode inner_mode = GET_MODE_INNER (mode);
29060 bool use_vec_extr = false;
29073 use_vec_extr = true;
29077 use_vec_extr = TARGET_SSE4_1;
29089 tmp = gen_reg_rtx (mode);
29090 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
29091 GEN_INT (elt), GEN_INT (elt),
29092 GEN_INT (elt+4), GEN_INT (elt+4)));
29096 tmp = gen_reg_rtx (mode);
29097 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
29101 gcc_unreachable ();
29104 use_vec_extr = true;
29109 use_vec_extr = TARGET_SSE4_1;
29123 tmp = gen_reg_rtx (mode);
29124 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
29125 GEN_INT (elt), GEN_INT (elt),
29126 GEN_INT (elt), GEN_INT (elt)));
29130 tmp = gen_reg_rtx (mode);
29131 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
29135 gcc_unreachable ();
29138 use_vec_extr = true;
29143 /* For SSE1, we have to reuse the V4SF code. */
29144 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
29145 gen_lowpart (V4SFmode, vec), elt);
29151 use_vec_extr = TARGET_SSE2;
29154 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
29158 use_vec_extr = TARGET_SSE4_1;
29162 /* ??? Could extract the appropriate HImode element and shift. */
29169 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
29170 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
29172 /* Let the rtl optimizers know about the zero extension performed. */
29173 if (inner_mode == QImode || inner_mode == HImode)
29175 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
29176 target = gen_lowpart (SImode, target);
29179 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29183 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29185 emit_move_insn (mem, vec);
29187 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29188 emit_move_insn (target, tmp);
29192 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
29193 pattern to reduce; DEST is the destination; IN is the input vector. */
29196 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
29198 rtx tmp1, tmp2, tmp3;
29200 tmp1 = gen_reg_rtx (V4SFmode);
29201 tmp2 = gen_reg_rtx (V4SFmode);
29202 tmp3 = gen_reg_rtx (V4SFmode);
29204 emit_insn (gen_sse_movhlps (tmp1, in, in));
29205 emit_insn (fn (tmp2, tmp1, in));
29207 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
29208 const1_rtx, const1_rtx,
29209 GEN_INT (1+4), GEN_INT (1+4)));
29210 emit_insn (fn (dest, tmp2, tmp3));
29213 /* Target hook for scalar_mode_supported_p. */
29215 ix86_scalar_mode_supported_p (enum machine_mode mode)
29217 if (DECIMAL_FLOAT_MODE_P (mode))
29218 return default_decimal_float_supported_p ();
29219 else if (mode == TFmode)
29222 return default_scalar_mode_supported_p (mode);
29225 /* Implements target hook vector_mode_supported_p. */
29227 ix86_vector_mode_supported_p (enum machine_mode mode)
29229 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
29231 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
29233 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
29235 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
29237 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
29242 /* Target hook for c_mode_for_suffix. */
29243 static enum machine_mode
29244 ix86_c_mode_for_suffix (char suffix)
29254 /* Worker function for TARGET_MD_ASM_CLOBBERS.
29256 We do this in the new i386 backend to maintain source compatibility
29257 with the old cc0-based compiler. */
29260 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
29261 tree inputs ATTRIBUTE_UNUSED,
29264 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
29266 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
29271 /* Implements target vector targetm.asm.encode_section_info. This
29272 is not used by netware. */
29274 static void ATTRIBUTE_UNUSED
29275 ix86_encode_section_info (tree decl, rtx rtl, int first)
29277 default_encode_section_info (decl, rtl, first);
29279 if (TREE_CODE (decl) == VAR_DECL
29280 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
29281 && ix86_in_large_data_p (decl))
29282 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
29285 /* Worker function for REVERSE_CONDITION. */
29288 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
29290 return (mode != CCFPmode && mode != CCFPUmode
29291 ? reverse_condition (code)
29292 : reverse_condition_maybe_unordered (code));
29295 /* Output code to perform an x87 FP register move, from OPERANDS[1]
29299 output_387_reg_move (rtx insn, rtx *operands)
29301 if (REG_P (operands[0]))
29303 if (REG_P (operands[1])
29304 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29306 if (REGNO (operands[0]) == FIRST_STACK_REG)
29307 return output_387_ffreep (operands, 0);
29308 return "fstp\t%y0";
29310 if (STACK_TOP_P (operands[0]))
29311 return "fld%Z1\t%y1";
29314 else if (MEM_P (operands[0]))
29316 gcc_assert (REG_P (operands[1]));
29317 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29318 return "fstp%Z0\t%y0";
29321 /* There is no non-popping store to memory for XFmode.
29322 So if we need one, follow the store with a load. */
29323 if (GET_MODE (operands[0]) == XFmode)
29324 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
29326 return "fst%Z0\t%y0";
29333 /* Output code to perform a conditional jump to LABEL, if C2 flag in
29334 FP status register is set. */
29337 ix86_emit_fp_unordered_jump (rtx label)
29339 rtx reg = gen_reg_rtx (HImode);
29342 emit_insn (gen_x86_fnstsw_1 (reg));
29344 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
29346 emit_insn (gen_x86_sahf_1 (reg));
29348 temp = gen_rtx_REG (CCmode, FLAGS_REG);
29349 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
29353 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
29355 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
29356 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
29359 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
29360 gen_rtx_LABEL_REF (VOIDmode, label),
29362 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
29364 emit_jump_insn (temp);
29365 predict_jump (REG_BR_PROB_BASE * 10 / 100);
29368 /* Output code to perform a log1p XFmode calculation. */
29370 void ix86_emit_i387_log1p (rtx op0, rtx op1)
29372 rtx label1 = gen_label_rtx ();
29373 rtx label2 = gen_label_rtx ();
29375 rtx tmp = gen_reg_rtx (XFmode);
29376 rtx tmp2 = gen_reg_rtx (XFmode);
29379 emit_insn (gen_absxf2 (tmp, op1));
29380 test = gen_rtx_GE (VOIDmode, tmp,
29381 CONST_DOUBLE_FROM_REAL_VALUE (
29382 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
29384 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
29386 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29387 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
29388 emit_jump (label2);
29390 emit_label (label1);
29391 emit_move_insn (tmp, CONST1_RTX (XFmode));
29392 emit_insn (gen_addxf3 (tmp, op1, tmp));
29393 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29394 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
29396 emit_label (label2);
29399 /* Output code to perform a Newton-Rhapson approximation of a single precision
29400 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
29402 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
29404 rtx x0, x1, e0, e1, two;
29406 x0 = gen_reg_rtx (mode);
29407 e0 = gen_reg_rtx (mode);
29408 e1 = gen_reg_rtx (mode);
29409 x1 = gen_reg_rtx (mode);
29411 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
29413 if (VECTOR_MODE_P (mode))
29414 two = ix86_build_const_vector (SFmode, true, two);
29416 two = force_reg (mode, two);
29418 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
29420 /* x0 = rcp(b) estimate */
29421 emit_insn (gen_rtx_SET (VOIDmode, x0,
29422 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
29425 emit_insn (gen_rtx_SET (VOIDmode, e0,
29426 gen_rtx_MULT (mode, x0, a)));
29428 emit_insn (gen_rtx_SET (VOIDmode, e1,
29429 gen_rtx_MULT (mode, x0, b)));
29431 emit_insn (gen_rtx_SET (VOIDmode, x1,
29432 gen_rtx_MINUS (mode, two, e1)));
29433 /* res = e0 * x1 */
29434 emit_insn (gen_rtx_SET (VOIDmode, res,
29435 gen_rtx_MULT (mode, e0, x1)));
29438 /* Output code to perform a Newton-Rhapson approximation of a
29439 single precision floating point [reciprocal] square root. */
29441 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
29444 rtx x0, e0, e1, e2, e3, mthree, mhalf;
29447 x0 = gen_reg_rtx (mode);
29448 e0 = gen_reg_rtx (mode);
29449 e1 = gen_reg_rtx (mode);
29450 e2 = gen_reg_rtx (mode);
29451 e3 = gen_reg_rtx (mode);
29453 real_from_integer (&r, VOIDmode, -3, -1, 0);
29454 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29456 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
29457 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29459 if (VECTOR_MODE_P (mode))
29461 mthree = ix86_build_const_vector (SFmode, true, mthree);
29462 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
29465 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
29466 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
29468 /* x0 = rsqrt(a) estimate */
29469 emit_insn (gen_rtx_SET (VOIDmode, x0,
29470 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
29473 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
29478 zero = gen_reg_rtx (mode);
29479 mask = gen_reg_rtx (mode);
29481 zero = force_reg (mode, CONST0_RTX(mode));
29482 emit_insn (gen_rtx_SET (VOIDmode, mask,
29483 gen_rtx_NE (mode, zero, a)));
29485 emit_insn (gen_rtx_SET (VOIDmode, x0,
29486 gen_rtx_AND (mode, x0, mask)));
29490 emit_insn (gen_rtx_SET (VOIDmode, e0,
29491 gen_rtx_MULT (mode, x0, a)));
29493 emit_insn (gen_rtx_SET (VOIDmode, e1,
29494 gen_rtx_MULT (mode, e0, x0)));
29497 mthree = force_reg (mode, mthree);
29498 emit_insn (gen_rtx_SET (VOIDmode, e2,
29499 gen_rtx_PLUS (mode, e1, mthree)));
29501 mhalf = force_reg (mode, mhalf);
29503 /* e3 = -.5 * x0 */
29504 emit_insn (gen_rtx_SET (VOIDmode, e3,
29505 gen_rtx_MULT (mode, x0, mhalf)));
29507 /* e3 = -.5 * e0 */
29508 emit_insn (gen_rtx_SET (VOIDmode, e3,
29509 gen_rtx_MULT (mode, e0, mhalf)));
29510 /* ret = e2 * e3 */
29511 emit_insn (gen_rtx_SET (VOIDmode, res,
29512 gen_rtx_MULT (mode, e2, e3)));
29515 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
29517 static void ATTRIBUTE_UNUSED
29518 i386_solaris_elf_named_section (const char *name, unsigned int flags,
29521 /* With Binutils 2.15, the "@unwind" marker must be specified on
29522 every occurrence of the ".eh_frame" section, not just the first
29525 && strcmp (name, ".eh_frame") == 0)
29527 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
29528 flags & SECTION_WRITE ? "aw" : "a");
29531 default_elf_asm_named_section (name, flags, decl);
29534 /* Return the mangling of TYPE if it is an extended fundamental type. */
29536 static const char *
29537 ix86_mangle_type (const_tree type)
29539 type = TYPE_MAIN_VARIANT (type);
29541 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
29542 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
29545 switch (TYPE_MODE (type))
29548 /* __float128 is "g". */
29551 /* "long double" or __float80 is "e". */
29558 /* For 32-bit code we can save PIC register setup by using
29559 __stack_chk_fail_local hidden function instead of calling
29560 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
29561 register, so it is better to call __stack_chk_fail directly. */
29564 ix86_stack_protect_fail (void)
29566 return TARGET_64BIT
29567 ? default_external_stack_protect_fail ()
29568 : default_hidden_stack_protect_fail ();
29571 /* Select a format to encode pointers in exception handling data. CODE
29572 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
29573 true if the symbol may be affected by dynamic relocations.
29575 ??? All x86 object file formats are capable of representing this.
29576 After all, the relocation needed is the same as for the call insn.
29577 Whether or not a particular assembler allows us to enter such, I
29578 guess we'll have to see. */
29580 asm_preferred_eh_data_format (int code, int global)
29584 int type = DW_EH_PE_sdata8;
29586 || ix86_cmodel == CM_SMALL_PIC
29587 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
29588 type = DW_EH_PE_sdata4;
29589 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
29591 if (ix86_cmodel == CM_SMALL
29592 || (ix86_cmodel == CM_MEDIUM && code))
29593 return DW_EH_PE_udata4;
29594 return DW_EH_PE_absptr;
29597 /* Expand copysign from SIGN to the positive value ABS_VALUE
29598 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
29601 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
29603 enum machine_mode mode = GET_MODE (sign);
29604 rtx sgn = gen_reg_rtx (mode);
29605 if (mask == NULL_RTX)
29607 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
29608 if (!VECTOR_MODE_P (mode))
29610 /* We need to generate a scalar mode mask in this case. */
29611 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29612 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29613 mask = gen_reg_rtx (mode);
29614 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29618 mask = gen_rtx_NOT (mode, mask);
29619 emit_insn (gen_rtx_SET (VOIDmode, sgn,
29620 gen_rtx_AND (mode, mask, sign)));
29621 emit_insn (gen_rtx_SET (VOIDmode, result,
29622 gen_rtx_IOR (mode, abs_value, sgn)));
29625 /* Expand fabs (OP0) and return a new rtx that holds the result. The
29626 mask for masking out the sign-bit is stored in *SMASK, if that is
29629 ix86_expand_sse_fabs (rtx op0, rtx *smask)
29631 enum machine_mode mode = GET_MODE (op0);
29634 xa = gen_reg_rtx (mode);
29635 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
29636 if (!VECTOR_MODE_P (mode))
29638 /* We need to generate a scalar mode mask in this case. */
29639 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29640 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29641 mask = gen_reg_rtx (mode);
29642 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29644 emit_insn (gen_rtx_SET (VOIDmode, xa,
29645 gen_rtx_AND (mode, op0, mask)));
29653 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
29654 swapping the operands if SWAP_OPERANDS is true. The expanded
29655 code is a forward jump to a newly created label in case the
29656 comparison is true. The generated label rtx is returned. */
29658 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
29659 bool swap_operands)
29670 label = gen_label_rtx ();
29671 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
29672 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29673 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
29674 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
29675 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
29676 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
29677 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
29678 JUMP_LABEL (tmp) = label;
29683 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
29684 using comparison code CODE. Operands are swapped for the comparison if
29685 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
29687 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
29688 bool swap_operands)
29690 enum machine_mode mode = GET_MODE (op0);
29691 rtx mask = gen_reg_rtx (mode);
29700 if (mode == DFmode)
29701 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
29702 gen_rtx_fmt_ee (code, mode, op0, op1)));
29704 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
29705 gen_rtx_fmt_ee (code, mode, op0, op1)));
29710 /* Generate and return a rtx of mode MODE for 2**n where n is the number
29711 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
29713 ix86_gen_TWO52 (enum machine_mode mode)
29715 REAL_VALUE_TYPE TWO52r;
29718 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
29719 TWO52 = const_double_from_real_value (TWO52r, mode);
29720 TWO52 = force_reg (mode, TWO52);
29725 /* Expand SSE sequence for computing lround from OP1 storing
29728 ix86_expand_lround (rtx op0, rtx op1)
29730 /* C code for the stuff we're doing below:
29731 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
29734 enum machine_mode mode = GET_MODE (op1);
29735 const struct real_format *fmt;
29736 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29739 /* load nextafter (0.5, 0.0) */
29740 fmt = REAL_MODE_FORMAT (mode);
29741 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29742 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29744 /* adj = copysign (0.5, op1) */
29745 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
29746 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
29748 /* adj = op1 + adj */
29749 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
29751 /* op0 = (imode)adj */
29752 expand_fix (op0, adj, 0);
29755 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
29758 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
29760 /* C code for the stuff we're doing below (for do_floor):
29762 xi -= (double)xi > op1 ? 1 : 0;
29765 enum machine_mode fmode = GET_MODE (op1);
29766 enum machine_mode imode = GET_MODE (op0);
29767 rtx ireg, freg, label, tmp;
29769 /* reg = (long)op1 */
29770 ireg = gen_reg_rtx (imode);
29771 expand_fix (ireg, op1, 0);
29773 /* freg = (double)reg */
29774 freg = gen_reg_rtx (fmode);
29775 expand_float (freg, ireg, 0);
29777 /* ireg = (freg > op1) ? ireg - 1 : ireg */
29778 label = ix86_expand_sse_compare_and_jump (UNLE,
29779 freg, op1, !do_floor);
29780 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
29781 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
29782 emit_move_insn (ireg, tmp);
29784 emit_label (label);
29785 LABEL_NUSES (label) = 1;
29787 emit_move_insn (op0, ireg);
29790 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
29791 result in OPERAND0. */
29793 ix86_expand_rint (rtx operand0, rtx operand1)
29795 /* C code for the stuff we're doing below:
29796 xa = fabs (operand1);
29797 if (!isless (xa, 2**52))
29799 xa = xa + 2**52 - 2**52;
29800 return copysign (xa, operand1);
29802 enum machine_mode mode = GET_MODE (operand0);
29803 rtx res, xa, label, TWO52, mask;
29805 res = gen_reg_rtx (mode);
29806 emit_move_insn (res, operand1);
29808 /* xa = abs (operand1) */
29809 xa = ix86_expand_sse_fabs (res, &mask);
29811 /* if (!isless (xa, TWO52)) goto label; */
29812 TWO52 = ix86_gen_TWO52 (mode);
29813 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29815 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29816 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29818 ix86_sse_copysign_to_positive (res, xa, res, mask);
29820 emit_label (label);
29821 LABEL_NUSES (label) = 1;
29823 emit_move_insn (operand0, res);
29826 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29829 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29831 /* C code for the stuff we expand below.
29832 double xa = fabs (x), x2;
29833 if (!isless (xa, TWO52))
29835 xa = xa + TWO52 - TWO52;
29836 x2 = copysign (xa, x);
29845 enum machine_mode mode = GET_MODE (operand0);
29846 rtx xa, TWO52, tmp, label, one, res, mask;
29848 TWO52 = ix86_gen_TWO52 (mode);
29850 /* Temporary for holding the result, initialized to the input
29851 operand to ease control flow. */
29852 res = gen_reg_rtx (mode);
29853 emit_move_insn (res, operand1);
29855 /* xa = abs (operand1) */
29856 xa = ix86_expand_sse_fabs (res, &mask);
29858 /* if (!isless (xa, TWO52)) goto label; */
29859 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29861 /* xa = xa + TWO52 - TWO52; */
29862 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29863 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29865 /* xa = copysign (xa, operand1) */
29866 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29868 /* generate 1.0 or -1.0 */
29869 one = force_reg (mode,
29870 const_double_from_real_value (do_floor
29871 ? dconst1 : dconstm1, mode));
29873 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29874 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29875 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29876 gen_rtx_AND (mode, one, tmp)));
29877 /* We always need to subtract here to preserve signed zero. */
29878 tmp = expand_simple_binop (mode, MINUS,
29879 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29880 emit_move_insn (res, tmp);
29882 emit_label (label);
29883 LABEL_NUSES (label) = 1;
29885 emit_move_insn (operand0, res);
29888 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29891 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29893 /* C code for the stuff we expand below.
29894 double xa = fabs (x), x2;
29895 if (!isless (xa, TWO52))
29897 x2 = (double)(long)x;
29904 if (HONOR_SIGNED_ZEROS (mode))
29905 return copysign (x2, x);
29908 enum machine_mode mode = GET_MODE (operand0);
29909 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29911 TWO52 = ix86_gen_TWO52 (mode);
29913 /* Temporary for holding the result, initialized to the input
29914 operand to ease control flow. */
29915 res = gen_reg_rtx (mode);
29916 emit_move_insn (res, operand1);
29918 /* xa = abs (operand1) */
29919 xa = ix86_expand_sse_fabs (res, &mask);
29921 /* if (!isless (xa, TWO52)) goto label; */
29922 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29924 /* xa = (double)(long)x */
29925 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29926 expand_fix (xi, res, 0);
29927 expand_float (xa, xi, 0);
29930 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29932 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29933 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29934 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29935 gen_rtx_AND (mode, one, tmp)));
29936 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29937 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29938 emit_move_insn (res, tmp);
29940 if (HONOR_SIGNED_ZEROS (mode))
29941 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29943 emit_label (label);
29944 LABEL_NUSES (label) = 1;
29946 emit_move_insn (operand0, res);
29949 /* Expand SSE sequence for computing round from OPERAND1 storing
29950 into OPERAND0. Sequence that works without relying on DImode truncation
29951 via cvttsd2siq that is only available on 64bit targets. */
29953 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29955 /* C code for the stuff we expand below.
29956 double xa = fabs (x), xa2, x2;
29957 if (!isless (xa, TWO52))
29959 Using the absolute value and copying back sign makes
29960 -0.0 -> -0.0 correct.
29961 xa2 = xa + TWO52 - TWO52;
29966 else if (dxa > 0.5)
29968 x2 = copysign (xa2, x);
29971 enum machine_mode mode = GET_MODE (operand0);
29972 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29974 TWO52 = ix86_gen_TWO52 (mode);
29976 /* Temporary for holding the result, initialized to the input
29977 operand to ease control flow. */
29978 res = gen_reg_rtx (mode);
29979 emit_move_insn (res, operand1);
29981 /* xa = abs (operand1) */
29982 xa = ix86_expand_sse_fabs (res, &mask);
29984 /* if (!isless (xa, TWO52)) goto label; */
29985 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29987 /* xa2 = xa + TWO52 - TWO52; */
29988 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29989 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29991 /* dxa = xa2 - xa; */
29992 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29994 /* generate 0.5, 1.0 and -0.5 */
29995 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29996 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29997 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
30001 tmp = gen_reg_rtx (mode);
30002 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
30003 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
30004 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30005 gen_rtx_AND (mode, one, tmp)));
30006 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30007 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
30008 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
30009 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30010 gen_rtx_AND (mode, one, tmp)));
30011 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30013 /* res = copysign (xa2, operand1) */
30014 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
30016 emit_label (label);
30017 LABEL_NUSES (label) = 1;
30019 emit_move_insn (operand0, res);
30022 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30025 ix86_expand_trunc (rtx operand0, rtx operand1)
30027 /* C code for SSE variant we expand below.
30028 double xa = fabs (x), x2;
30029 if (!isless (xa, TWO52))
30031 x2 = (double)(long)x;
30032 if (HONOR_SIGNED_ZEROS (mode))
30033 return copysign (x2, x);
30036 enum machine_mode mode = GET_MODE (operand0);
30037 rtx xa, xi, TWO52, label, res, mask;
30039 TWO52 = ix86_gen_TWO52 (mode);
30041 /* Temporary for holding the result, initialized to the input
30042 operand to ease control flow. */
30043 res = gen_reg_rtx (mode);
30044 emit_move_insn (res, operand1);
30046 /* xa = abs (operand1) */
30047 xa = ix86_expand_sse_fabs (res, &mask);
30049 /* if (!isless (xa, TWO52)) goto label; */
30050 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30052 /* x = (double)(long)x */
30053 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30054 expand_fix (xi, res, 0);
30055 expand_float (res, xi, 0);
30057 if (HONOR_SIGNED_ZEROS (mode))
30058 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
30060 emit_label (label);
30061 LABEL_NUSES (label) = 1;
30063 emit_move_insn (operand0, res);
30066 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30069 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
30071 enum machine_mode mode = GET_MODE (operand0);
30072 rtx xa, mask, TWO52, label, one, res, smask, tmp;
30074 /* C code for SSE variant we expand below.
30075 double xa = fabs (x), x2;
30076 if (!isless (xa, TWO52))
30078 xa2 = xa + TWO52 - TWO52;
30082 x2 = copysign (xa2, x);
30086 TWO52 = ix86_gen_TWO52 (mode);
30088 /* Temporary for holding the result, initialized to the input
30089 operand to ease control flow. */
30090 res = gen_reg_rtx (mode);
30091 emit_move_insn (res, operand1);
30093 /* xa = abs (operand1) */
30094 xa = ix86_expand_sse_fabs (res, &smask);
30096 /* if (!isless (xa, TWO52)) goto label; */
30097 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30099 /* res = xa + TWO52 - TWO52; */
30100 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
30101 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
30102 emit_move_insn (res, tmp);
30105 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
30107 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
30108 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
30109 emit_insn (gen_rtx_SET (VOIDmode, mask,
30110 gen_rtx_AND (mode, mask, one)));
30111 tmp = expand_simple_binop (mode, MINUS,
30112 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
30113 emit_move_insn (res, tmp);
30115 /* res = copysign (res, operand1) */
30116 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
30118 emit_label (label);
30119 LABEL_NUSES (label) = 1;
30121 emit_move_insn (operand0, res);
30124 /* Expand SSE sequence for computing round from OPERAND1 storing
30127 ix86_expand_round (rtx operand0, rtx operand1)
30129 /* C code for the stuff we're doing below:
30130 double xa = fabs (x);
30131 if (!isless (xa, TWO52))
30133 xa = (double)(long)(xa + nextafter (0.5, 0.0));
30134 return copysign (xa, x);
30136 enum machine_mode mode = GET_MODE (operand0);
30137 rtx res, TWO52, xa, label, xi, half, mask;
30138 const struct real_format *fmt;
30139 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
30141 /* Temporary for holding the result, initialized to the input
30142 operand to ease control flow. */
30143 res = gen_reg_rtx (mode);
30144 emit_move_insn (res, operand1);
30146 TWO52 = ix86_gen_TWO52 (mode);
30147 xa = ix86_expand_sse_fabs (res, &mask);
30148 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30150 /* load nextafter (0.5, 0.0) */
30151 fmt = REAL_MODE_FORMAT (mode);
30152 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
30153 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
30155 /* xa = xa + 0.5 */
30156 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
30157 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
30159 /* xa = (double)(int64_t)xa */
30160 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30161 expand_fix (xi, xa, 0);
30162 expand_float (xa, xi, 0);
30164 /* res = copysign (xa, operand1) */
30165 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
30167 emit_label (label);
30168 LABEL_NUSES (label) = 1;
30170 emit_move_insn (operand0, res);
30173 /* Validate whether a FMA4 instruction is valid or not.
30174 OPERANDS is the array of operands.
30175 NUM is the number of operands.
30176 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
30177 NUM_MEMORY is the maximum number of memory operands to accept.
30178 NUM_MEMORY less than zero is a special case to allow an operand
30179 of an instruction to be memory operation.
30180 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
30183 ix86_fma4_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
30184 bool uses_oc0, int num_memory, bool commutative)
30190 /* Count the number of memory arguments */
30193 for (i = 0; i < num; i++)
30195 enum machine_mode mode = GET_MODE (operands[i]);
30196 if (register_operand (operands[i], mode))
30199 else if (memory_operand (operands[i], mode))
30201 mem_mask |= (1 << i);
30207 rtx pattern = PATTERN (insn);
30209 /* allow 0 for pcmov */
30210 if (GET_CODE (pattern) != SET
30211 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
30213 || operands[i] != CONST0_RTX (mode))
30218 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
30219 a memory operation. */
30220 if (num_memory < 0)
30222 num_memory = -num_memory;
30223 if ((mem_mask & (1 << (num-1))) != 0)
30225 mem_mask &= ~(1 << (num-1));
30230 /* If there were no memory operations, allow the insn */
30234 /* Do not allow the destination register to be a memory operand. */
30235 else if (mem_mask & (1 << 0))
30238 /* If there are too many memory operations, disallow the instruction. While
30239 the hardware only allows 1 memory reference, before register allocation
30240 for some insns, we allow two memory operations sometimes in order to allow
30241 code like the following to be optimized:
30243 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
30245 or similar cases that are vectorized into using the vfmaddss
30247 else if (mem_count > num_memory)
30250 /* Don't allow more than one memory operation if not optimizing. */
30251 else if (mem_count > 1 && !optimize)
30254 else if (num == 4 && mem_count == 1)
30256 /* formats (destination is the first argument), example vfmaddss:
30257 xmm1, xmm1, xmm2, xmm3/mem
30258 xmm1, xmm1, xmm2/mem, xmm3
30259 xmm1, xmm2, xmm3/mem, xmm1
30260 xmm1, xmm2/mem, xmm3, xmm1 */
30262 return ((mem_mask == (1 << 1))
30263 || (mem_mask == (1 << 2))
30264 || (mem_mask == (1 << 3)));
30266 /* format, example vpmacsdd:
30267 xmm1, xmm2, xmm3/mem, xmm1 */
30269 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
30271 return (mem_mask == (1 << 2));
30274 else if (num == 4 && num_memory == 2)
30276 /* If there are two memory operations, we can load one of the memory ops
30277 into the destination register. This is for optimizing the
30278 multiply/add ops, which the combiner has optimized both the multiply
30279 and the add insns to have a memory operation. We have to be careful
30280 that the destination doesn't overlap with the inputs. */
30281 rtx op0 = operands[0];
30283 if (reg_mentioned_p (op0, operands[1])
30284 || reg_mentioned_p (op0, operands[2])
30285 || reg_mentioned_p (op0, operands[3]))
30288 /* formats (destination is the first argument), example vfmaddss:
30289 xmm1, xmm1, xmm2, xmm3/mem
30290 xmm1, xmm1, xmm2/mem, xmm3
30291 xmm1, xmm2, xmm3/mem, xmm1
30292 xmm1, xmm2/mem, xmm3, xmm1
30294 For the oc0 case, we will load either operands[1] or operands[3] into
30295 operands[0], so any combination of 2 memory operands is ok. */
30299 /* format, example vpmacsdd:
30300 xmm1, xmm2, xmm3/mem, xmm1
30302 For the integer multiply/add instructions be more restrictive and
30303 require operands[2] and operands[3] to be the memory operands. */
30305 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
30307 return (mem_mask == ((1 << 2) | (1 << 3)));
30310 else if (num == 3 && num_memory == 1)
30312 /* formats, example vprotb:
30313 xmm1, xmm2, xmm3/mem
30314 xmm1, xmm2/mem, xmm3 */
30316 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
30318 /* format, example vpcomeq:
30319 xmm1, xmm2, xmm3/mem */
30321 return (mem_mask == (1 << 2));
30325 gcc_unreachable ();
30331 /* Fixup an FMA4 instruction that has 2 memory input references into a form the
30332 hardware will allow by using the destination register to load one of the
30333 memory operations. Presently this is used by the multiply/add routines to
30334 allow 2 memory references. */
30337 ix86_expand_fma4_multiple_memory (rtx operands[],
30339 enum machine_mode mode)
30341 rtx op0 = operands[0];
30343 || memory_operand (op0, mode)
30344 || reg_mentioned_p (op0, operands[1])
30345 || reg_mentioned_p (op0, operands[2])
30346 || reg_mentioned_p (op0, operands[3]))
30347 gcc_unreachable ();
30349 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
30350 the destination register. */
30351 if (memory_operand (operands[1], mode))
30353 emit_move_insn (op0, operands[1]);
30356 else if (memory_operand (operands[3], mode))
30358 emit_move_insn (op0, operands[3]);
30362 gcc_unreachable ();
30367 /* Table of valid machine attributes. */
30368 static const struct attribute_spec ix86_attribute_table[] =
30370 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
30371 /* Stdcall attribute says callee is responsible for popping arguments
30372 if they are not variable. */
30373 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30374 /* Fastcall attribute says callee is responsible for popping arguments
30375 if they are not variable. */
30376 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30377 /* Cdecl attribute says the callee is a normal C declaration */
30378 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30379 /* Regparm attribute specifies how many integer arguments are to be
30380 passed in registers. */
30381 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
30382 /* Sseregparm attribute says we are using x86_64 calling conventions
30383 for FP arguments. */
30384 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30385 /* force_align_arg_pointer says this function realigns the stack at entry. */
30386 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
30387 false, true, true, ix86_handle_cconv_attribute },
30388 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30389 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
30390 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
30391 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
30393 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30394 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30395 #ifdef SUBTARGET_ATTRIBUTE_TABLE
30396 SUBTARGET_ATTRIBUTE_TABLE,
30398 /* ms_abi and sysv_abi calling convention function attributes. */
30399 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30400 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30401 { "ms_hook_prologue", 0, 0, true, false, false, ix86_handle_fndecl_attribute },
30403 { NULL, 0, 0, false, false, false, NULL }
30406 /* Implement targetm.vectorize.builtin_vectorization_cost. */
30408 x86_builtin_vectorization_cost (bool runtime_test)
30410 /* If the branch of the runtime test is taken - i.e. - the vectorized
30411 version is skipped - this incurs a misprediction cost (because the
30412 vectorized version is expected to be the fall-through). So we subtract
30413 the latency of a mispredicted branch from the costs that are incured
30414 when the vectorized version is executed.
30416 TODO: The values in individual target tables have to be tuned or new
30417 fields may be needed. For eg. on K8, the default branch path is the
30418 not-taken path. If the taken path is predicted correctly, the minimum
30419 penalty of going down the taken-path is 1 cycle. If the taken-path is
30420 not predicted correctly, then the minimum penalty is 10 cycles. */
30424 return (-(ix86_cost->cond_taken_branch_cost));
30430 /* This function returns the calling abi specific va_list type node.
30431 It returns the FNDECL specific va_list type. */
30434 ix86_fn_abi_va_list (tree fndecl)
30437 return va_list_type_node;
30438 gcc_assert (fndecl != NULL_TREE);
30440 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
30441 return ms_va_list_type_node;
30443 return sysv_va_list_type_node;
30446 /* Returns the canonical va_list type specified by TYPE. If there
30447 is no valid TYPE provided, it return NULL_TREE. */
30450 ix86_canonical_va_list_type (tree type)
30454 /* Resolve references and pointers to va_list type. */
30455 if (INDIRECT_REF_P (type))
30456 type = TREE_TYPE (type);
30457 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
30458 type = TREE_TYPE (type);
30462 wtype = va_list_type_node;
30463 gcc_assert (wtype != NULL_TREE);
30465 if (TREE_CODE (wtype) == ARRAY_TYPE)
30467 /* If va_list is an array type, the argument may have decayed
30468 to a pointer type, e.g. by being passed to another function.
30469 In that case, unwrap both types so that we can compare the
30470 underlying records. */
30471 if (TREE_CODE (htype) == ARRAY_TYPE
30472 || POINTER_TYPE_P (htype))
30474 wtype = TREE_TYPE (wtype);
30475 htype = TREE_TYPE (htype);
30478 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30479 return va_list_type_node;
30480 wtype = sysv_va_list_type_node;
30481 gcc_assert (wtype != NULL_TREE);
30483 if (TREE_CODE (wtype) == ARRAY_TYPE)
30485 /* If va_list is an array type, the argument may have decayed
30486 to a pointer type, e.g. by being passed to another function.
30487 In that case, unwrap both types so that we can compare the
30488 underlying records. */
30489 if (TREE_CODE (htype) == ARRAY_TYPE
30490 || POINTER_TYPE_P (htype))
30492 wtype = TREE_TYPE (wtype);
30493 htype = TREE_TYPE (htype);
30496 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30497 return sysv_va_list_type_node;
30498 wtype = ms_va_list_type_node;
30499 gcc_assert (wtype != NULL_TREE);
30501 if (TREE_CODE (wtype) == ARRAY_TYPE)
30503 /* If va_list is an array type, the argument may have decayed
30504 to a pointer type, e.g. by being passed to another function.
30505 In that case, unwrap both types so that we can compare the
30506 underlying records. */
30507 if (TREE_CODE (htype) == ARRAY_TYPE
30508 || POINTER_TYPE_P (htype))
30510 wtype = TREE_TYPE (wtype);
30511 htype = TREE_TYPE (htype);
30514 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30515 return ms_va_list_type_node;
30518 return std_canonical_va_list_type (type);
30521 /* Iterate through the target-specific builtin types for va_list.
30522 IDX denotes the iterator, *PTREE is set to the result type of
30523 the va_list builtin, and *PNAME to its internal type.
30524 Returns zero if there is no element for this index, otherwise
30525 IDX should be increased upon the next call.
30526 Note, do not iterate a base builtin's name like __builtin_va_list.
30527 Used from c_common_nodes_and_builtins. */
30530 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
30536 *ptree = ms_va_list_type_node;
30537 *pname = "__builtin_ms_va_list";
30540 *ptree = sysv_va_list_type_node;
30541 *pname = "__builtin_sysv_va_list";
30549 /* Initialize the GCC target structure. */
30550 #undef TARGET_RETURN_IN_MEMORY
30551 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30553 #undef TARGET_LEGITIMIZE_ADDRESS
30554 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30556 #undef TARGET_ATTRIBUTE_TABLE
30557 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30558 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30559 # undef TARGET_MERGE_DECL_ATTRIBUTES
30560 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30563 #undef TARGET_COMP_TYPE_ATTRIBUTES
30564 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30566 #undef TARGET_INIT_BUILTINS
30567 #define TARGET_INIT_BUILTINS ix86_init_builtins
30568 #undef TARGET_BUILTIN_DECL
30569 #define TARGET_BUILTIN_DECL ix86_builtin_decl
30570 #undef TARGET_EXPAND_BUILTIN
30571 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30573 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30574 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30575 ix86_builtin_vectorized_function
30577 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30578 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30580 #undef TARGET_BUILTIN_RECIPROCAL
30581 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30583 #undef TARGET_ASM_FUNCTION_EPILOGUE
30584 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30586 #undef TARGET_ENCODE_SECTION_INFO
30587 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30588 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30590 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30593 #undef TARGET_ASM_OPEN_PAREN
30594 #define TARGET_ASM_OPEN_PAREN ""
30595 #undef TARGET_ASM_CLOSE_PAREN
30596 #define TARGET_ASM_CLOSE_PAREN ""
30598 #undef TARGET_ASM_BYTE_OP
30599 #define TARGET_ASM_BYTE_OP ASM_BYTE
30601 #undef TARGET_ASM_ALIGNED_HI_OP
30602 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30603 #undef TARGET_ASM_ALIGNED_SI_OP
30604 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30606 #undef TARGET_ASM_ALIGNED_DI_OP
30607 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30610 #undef TARGET_ASM_UNALIGNED_HI_OP
30611 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30612 #undef TARGET_ASM_UNALIGNED_SI_OP
30613 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30614 #undef TARGET_ASM_UNALIGNED_DI_OP
30615 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30617 #undef TARGET_SCHED_ADJUST_COST
30618 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30619 #undef TARGET_SCHED_ISSUE_RATE
30620 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30621 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30622 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30623 ia32_multipass_dfa_lookahead
30625 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30626 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30629 #undef TARGET_HAVE_TLS
30630 #define TARGET_HAVE_TLS true
30632 #undef TARGET_CANNOT_FORCE_CONST_MEM
30633 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30634 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30635 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30637 #undef TARGET_DELEGITIMIZE_ADDRESS
30638 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30640 #undef TARGET_MS_BITFIELD_LAYOUT_P
30641 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30644 #undef TARGET_BINDS_LOCAL_P
30645 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30647 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30648 #undef TARGET_BINDS_LOCAL_P
30649 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30652 #undef TARGET_ASM_OUTPUT_MI_THUNK
30653 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30654 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30655 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30657 #undef TARGET_ASM_FILE_START
30658 #define TARGET_ASM_FILE_START x86_file_start
30660 #undef TARGET_DEFAULT_TARGET_FLAGS
30661 #define TARGET_DEFAULT_TARGET_FLAGS \
30663 | TARGET_SUBTARGET_DEFAULT \
30664 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
30666 #undef TARGET_HANDLE_OPTION
30667 #define TARGET_HANDLE_OPTION ix86_handle_option
30669 #undef TARGET_RTX_COSTS
30670 #define TARGET_RTX_COSTS ix86_rtx_costs
30671 #undef TARGET_ADDRESS_COST
30672 #define TARGET_ADDRESS_COST ix86_address_cost
30674 #undef TARGET_FIXED_CONDITION_CODE_REGS
30675 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30676 #undef TARGET_CC_MODES_COMPATIBLE
30677 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30679 #undef TARGET_MACHINE_DEPENDENT_REORG
30680 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30682 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30683 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30685 #undef TARGET_BUILD_BUILTIN_VA_LIST
30686 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30688 #undef TARGET_FN_ABI_VA_LIST
30689 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30691 #undef TARGET_CANONICAL_VA_LIST_TYPE
30692 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30694 #undef TARGET_EXPAND_BUILTIN_VA_START
30695 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30697 #undef TARGET_MD_ASM_CLOBBERS
30698 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30700 #undef TARGET_PROMOTE_PROTOTYPES
30701 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30702 #undef TARGET_STRUCT_VALUE_RTX
30703 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30704 #undef TARGET_SETUP_INCOMING_VARARGS
30705 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30706 #undef TARGET_MUST_PASS_IN_STACK
30707 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30708 #undef TARGET_PASS_BY_REFERENCE
30709 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30710 #undef TARGET_INTERNAL_ARG_POINTER
30711 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30712 #undef TARGET_UPDATE_STACK_BOUNDARY
30713 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30714 #undef TARGET_GET_DRAP_RTX
30715 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30716 #undef TARGET_STRICT_ARGUMENT_NAMING
30717 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30718 #undef TARGET_STATIC_CHAIN
30719 #define TARGET_STATIC_CHAIN ix86_static_chain
30720 #undef TARGET_TRAMPOLINE_INIT
30721 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
30723 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30724 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30726 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30727 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30729 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30730 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30732 #undef TARGET_C_MODE_FOR_SUFFIX
30733 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30736 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30737 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30740 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30741 #undef TARGET_INSERT_ATTRIBUTES
30742 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30745 #undef TARGET_MANGLE_TYPE
30746 #define TARGET_MANGLE_TYPE ix86_mangle_type
30748 #undef TARGET_STACK_PROTECT_FAIL
30749 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30751 #undef TARGET_FUNCTION_VALUE
30752 #define TARGET_FUNCTION_VALUE ix86_function_value
30754 #undef TARGET_SECONDARY_RELOAD
30755 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30757 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30758 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
30760 #undef TARGET_SET_CURRENT_FUNCTION
30761 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30763 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30764 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30766 #undef TARGET_OPTION_SAVE
30767 #define TARGET_OPTION_SAVE ix86_function_specific_save
30769 #undef TARGET_OPTION_RESTORE
30770 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30772 #undef TARGET_OPTION_PRINT
30773 #define TARGET_OPTION_PRINT ix86_function_specific_print
30775 #undef TARGET_CAN_INLINE_P
30776 #define TARGET_CAN_INLINE_P ix86_can_inline_p
30778 #undef TARGET_EXPAND_TO_RTL_HOOK
30779 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30781 #undef TARGET_LEGITIMATE_ADDRESS_P
30782 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30784 #undef TARGET_IRA_COVER_CLASSES
30785 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
30787 #undef TARGET_FRAME_POINTER_REQUIRED
30788 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
30790 #undef TARGET_CAN_ELIMINATE
30791 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
30793 struct gcc_target targetm = TARGET_INITIALIZER;
30795 #include "gt-i386.h"
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