1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #ifndef CHECK_STACK_LIMIT
54 #define CHECK_STACK_LIMIT (-1)
57 /* Return index of given mode in mult and division cost tables. */
58 #define MODE_INDEX(mode) \
59 ((mode) == QImode ? 0 \
60 : (mode) == HImode ? 1 \
61 : (mode) == SImode ? 2 \
62 : (mode) == DImode ? 3 \
65 /* Processor costs (relative to an add) */
67 struct processor_costs size_cost = { /* costs for tunning for size */
68 2, /* cost of an add instruction */
69 3, /* cost of a lea instruction */
70 2, /* variable shift costs */
71 3, /* constant shift costs */
72 {3, 3, 3, 3, 5}, /* cost of starting a multiply */
73 0, /* cost of multiply per each bit set */
74 {3, 3, 3, 3, 5}, /* cost of a divide/mod */
75 3, /* cost of movsx */
76 3, /* cost of movzx */
79 2, /* cost for loading QImode using movzbl */
80 {2, 2, 2}, /* cost of loading integer registers
81 in QImode, HImode and SImode.
82 Relative to reg-reg move (2). */
83 {2, 2, 2}, /* cost of storing integer registers */
84 2, /* cost of reg,reg fld/fst */
85 {2, 2, 2}, /* cost of loading fp registers
86 in SFmode, DFmode and XFmode */
87 {2, 2, 2}, /* cost of loading integer registers */
88 3, /* cost of moving MMX register */
89 {3, 3}, /* cost of loading MMX registers
90 in SImode and DImode */
91 {3, 3}, /* cost of storing MMX registers
92 in SImode and DImode */
93 3, /* cost of moving SSE register */
94 {3, 3, 3}, /* cost of loading SSE registers
95 in SImode, DImode and TImode */
96 {3, 3, 3}, /* cost of storing SSE registers
97 in SImode, DImode and TImode */
98 3, /* MMX or SSE register to integer */
99 0, /* size of prefetch block */
100 0, /* number of parallel prefetches */
102 2, /* cost of FADD and FSUB insns. */
103 2, /* cost of FMUL instruction. */
104 2, /* cost of FDIV instruction. */
105 2, /* cost of FABS instruction. */
106 2, /* cost of FCHS instruction. */
107 2, /* cost of FSQRT instruction. */
110 /* Processor costs (relative to an add) */
112 struct processor_costs i386_cost = { /* 386 specific costs */
113 1, /* cost of an add instruction */
114 1, /* cost of a lea instruction */
115 3, /* variable shift costs */
116 2, /* constant shift costs */
117 {6, 6, 6, 6, 6}, /* cost of starting a multiply */
118 1, /* cost of multiply per each bit set */
119 {23, 23, 23, 23, 23}, /* cost of a divide/mod */
120 3, /* cost of movsx */
121 2, /* cost of movzx */
122 15, /* "large" insn */
124 4, /* cost for loading QImode using movzbl */
125 {2, 4, 2}, /* cost of loading integer registers
126 in QImode, HImode and SImode.
127 Relative to reg-reg move (2). */
128 {2, 4, 2}, /* cost of storing integer registers */
129 2, /* cost of reg,reg fld/fst */
130 {8, 8, 8}, /* cost of loading fp registers
131 in SFmode, DFmode and XFmode */
132 {8, 8, 8}, /* cost of loading integer registers */
133 2, /* cost of moving MMX register */
134 {4, 8}, /* cost of loading MMX registers
135 in SImode and DImode */
136 {4, 8}, /* cost of storing MMX registers
137 in SImode and DImode */
138 2, /* cost of moving SSE register */
139 {4, 8, 16}, /* cost of loading SSE registers
140 in SImode, DImode and TImode */
141 {4, 8, 16}, /* cost of storing SSE registers
142 in SImode, DImode and TImode */
143 3, /* MMX or SSE register to integer */
144 0, /* size of prefetch block */
145 0, /* number of parallel prefetches */
147 23, /* cost of FADD and FSUB insns. */
148 27, /* cost of FMUL instruction. */
149 88, /* cost of FDIV instruction. */
150 22, /* cost of FABS instruction. */
151 24, /* cost of FCHS instruction. */
152 122, /* cost of FSQRT instruction. */
156 struct processor_costs i486_cost = { /* 486 specific costs */
157 1, /* cost of an add instruction */
158 1, /* cost of a lea instruction */
159 3, /* variable shift costs */
160 2, /* constant shift costs */
161 {12, 12, 12, 12, 12}, /* cost of starting a multiply */
162 1, /* cost of multiply per each bit set */
163 {40, 40, 40, 40, 40}, /* cost of a divide/mod */
164 3, /* cost of movsx */
165 2, /* cost of movzx */
166 15, /* "large" insn */
168 4, /* cost for loading QImode using movzbl */
169 {2, 4, 2}, /* cost of loading integer registers
170 in QImode, HImode and SImode.
171 Relative to reg-reg move (2). */
172 {2, 4, 2}, /* cost of storing integer registers */
173 2, /* cost of reg,reg fld/fst */
174 {8, 8, 8}, /* cost of loading fp registers
175 in SFmode, DFmode and XFmode */
176 {8, 8, 8}, /* cost of loading integer registers */
177 2, /* cost of moving MMX register */
178 {4, 8}, /* cost of loading MMX registers
179 in SImode and DImode */
180 {4, 8}, /* cost of storing MMX registers
181 in SImode and DImode */
182 2, /* cost of moving SSE register */
183 {4, 8, 16}, /* cost of loading SSE registers
184 in SImode, DImode and TImode */
185 {4, 8, 16}, /* cost of storing SSE registers
186 in SImode, DImode and TImode */
187 3, /* MMX or SSE register to integer */
188 0, /* size of prefetch block */
189 0, /* number of parallel prefetches */
191 8, /* cost of FADD and FSUB insns. */
192 16, /* cost of FMUL instruction. */
193 73, /* cost of FDIV instruction. */
194 3, /* cost of FABS instruction. */
195 3, /* cost of FCHS instruction. */
196 83, /* cost of FSQRT instruction. */
200 struct processor_costs pentium_cost = {
201 1, /* cost of an add instruction */
202 1, /* cost of a lea instruction */
203 4, /* variable shift costs */
204 1, /* constant shift costs */
205 {11, 11, 11, 11, 11}, /* cost of starting a multiply */
206 0, /* cost of multiply per each bit set */
207 {25, 25, 25, 25, 25}, /* cost of a divide/mod */
208 3, /* cost of movsx */
209 2, /* cost of movzx */
210 8, /* "large" insn */
212 6, /* cost for loading QImode using movzbl */
213 {2, 4, 2}, /* cost of loading integer registers
214 in QImode, HImode and SImode.
215 Relative to reg-reg move (2). */
216 {2, 4, 2}, /* cost of storing integer registers */
217 2, /* cost of reg,reg fld/fst */
218 {2, 2, 6}, /* cost of loading fp registers
219 in SFmode, DFmode and XFmode */
220 {4, 4, 6}, /* cost of loading integer registers */
221 8, /* cost of moving MMX register */
222 {8, 8}, /* cost of loading MMX registers
223 in SImode and DImode */
224 {8, 8}, /* cost of storing MMX registers
225 in SImode and DImode */
226 2, /* cost of moving SSE register */
227 {4, 8, 16}, /* cost of loading SSE registers
228 in SImode, DImode and TImode */
229 {4, 8, 16}, /* cost of storing SSE registers
230 in SImode, DImode and TImode */
231 3, /* MMX or SSE register to integer */
232 0, /* size of prefetch block */
233 0, /* number of parallel prefetches */
235 3, /* cost of FADD and FSUB insns. */
236 3, /* cost of FMUL instruction. */
237 39, /* cost of FDIV instruction. */
238 1, /* cost of FABS instruction. */
239 1, /* cost of FCHS instruction. */
240 70, /* cost of FSQRT instruction. */
244 struct processor_costs pentiumpro_cost = {
245 1, /* cost of an add instruction */
246 1, /* cost of a lea instruction */
247 1, /* variable shift costs */
248 1, /* constant shift costs */
249 {4, 4, 4, 4, 4}, /* cost of starting a multiply */
250 0, /* cost of multiply per each bit set */
251 {17, 17, 17, 17, 17}, /* cost of a divide/mod */
252 1, /* cost of movsx */
253 1, /* cost of movzx */
254 8, /* "large" insn */
256 2, /* cost for loading QImode using movzbl */
257 {4, 4, 4}, /* cost of loading integer registers
258 in QImode, HImode and SImode.
259 Relative to reg-reg move (2). */
260 {2, 2, 2}, /* cost of storing integer registers */
261 2, /* cost of reg,reg fld/fst */
262 {2, 2, 6}, /* cost of loading fp registers
263 in SFmode, DFmode and XFmode */
264 {4, 4, 6}, /* cost of loading integer registers */
265 2, /* cost of moving MMX register */
266 {2, 2}, /* cost of loading MMX registers
267 in SImode and DImode */
268 {2, 2}, /* cost of storing MMX registers
269 in SImode and DImode */
270 2, /* cost of moving SSE register */
271 {2, 2, 8}, /* cost of loading SSE registers
272 in SImode, DImode and TImode */
273 {2, 2, 8}, /* cost of storing SSE registers
274 in SImode, DImode and TImode */
275 3, /* MMX or SSE register to integer */
276 32, /* size of prefetch block */
277 6, /* number of parallel prefetches */
279 3, /* cost of FADD and FSUB insns. */
280 5, /* cost of FMUL instruction. */
281 56, /* cost of FDIV instruction. */
282 2, /* cost of FABS instruction. */
283 2, /* cost of FCHS instruction. */
284 56, /* cost of FSQRT instruction. */
288 struct processor_costs k6_cost = {
289 1, /* cost of an add instruction */
290 2, /* cost of a lea instruction */
291 1, /* variable shift costs */
292 1, /* constant shift costs */
293 {3, 3, 3, 3, 3}, /* cost of starting a multiply */
294 0, /* cost of multiply per each bit set */
295 {18, 18, 18, 18, 18}, /* cost of a divide/mod */
296 2, /* cost of movsx */
297 2, /* cost of movzx */
298 8, /* "large" insn */
300 3, /* cost for loading QImode using movzbl */
301 {4, 5, 4}, /* cost of loading integer registers
302 in QImode, HImode and SImode.
303 Relative to reg-reg move (2). */
304 {2, 3, 2}, /* cost of storing integer registers */
305 4, /* cost of reg,reg fld/fst */
306 {6, 6, 6}, /* cost of loading fp registers
307 in SFmode, DFmode and XFmode */
308 {4, 4, 4}, /* cost of loading integer registers */
309 2, /* cost of moving MMX register */
310 {2, 2}, /* cost of loading MMX registers
311 in SImode and DImode */
312 {2, 2}, /* cost of storing MMX registers
313 in SImode and DImode */
314 2, /* cost of moving SSE register */
315 {2, 2, 8}, /* cost of loading SSE registers
316 in SImode, DImode and TImode */
317 {2, 2, 8}, /* cost of storing SSE registers
318 in SImode, DImode and TImode */
319 6, /* MMX or SSE register to integer */
320 32, /* size of prefetch block */
321 1, /* number of parallel prefetches */
323 2, /* cost of FADD and FSUB insns. */
324 2, /* cost of FMUL instruction. */
325 56, /* cost of FDIV instruction. */
326 2, /* cost of FABS instruction. */
327 2, /* cost of FCHS instruction. */
328 56, /* cost of FSQRT instruction. */
332 struct processor_costs athlon_cost = {
333 1, /* cost of an add instruction */
334 2, /* cost of a lea instruction */
335 1, /* variable shift costs */
336 1, /* constant shift costs */
337 {5, 5, 5, 5, 5}, /* cost of starting a multiply */
338 0, /* cost of multiply per each bit set */
339 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
340 1, /* cost of movsx */
341 1, /* cost of movzx */
342 8, /* "large" insn */
344 4, /* cost for loading QImode using movzbl */
345 {3, 4, 3}, /* cost of loading integer registers
346 in QImode, HImode and SImode.
347 Relative to reg-reg move (2). */
348 {3, 4, 3}, /* cost of storing integer registers */
349 4, /* cost of reg,reg fld/fst */
350 {4, 4, 12}, /* cost of loading fp registers
351 in SFmode, DFmode and XFmode */
352 {6, 6, 8}, /* cost of loading integer registers */
353 2, /* cost of moving MMX register */
354 {4, 4}, /* cost of loading MMX registers
355 in SImode and DImode */
356 {4, 4}, /* cost of storing MMX registers
357 in SImode and DImode */
358 2, /* cost of moving SSE register */
359 {4, 4, 6}, /* cost of loading SSE registers
360 in SImode, DImode and TImode */
361 {4, 4, 5}, /* cost of storing SSE registers
362 in SImode, DImode and TImode */
363 5, /* MMX or SSE register to integer */
364 64, /* size of prefetch block */
365 6, /* number of parallel prefetches */
367 4, /* cost of FADD and FSUB insns. */
368 4, /* cost of FMUL instruction. */
369 24, /* cost of FDIV instruction. */
370 2, /* cost of FABS instruction. */
371 2, /* cost of FCHS instruction. */
372 35, /* cost of FSQRT instruction. */
376 struct processor_costs k8_cost = {
377 1, /* cost of an add instruction */
378 2, /* cost of a lea instruction */
379 1, /* variable shift costs */
380 1, /* constant shift costs */
381 {3, 4, 3, 4, 5}, /* cost of starting a multiply */
382 0, /* cost of multiply per each bit set */
383 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
384 1, /* cost of movsx */
385 1, /* cost of movzx */
386 8, /* "large" insn */
388 4, /* cost for loading QImode using movzbl */
389 {3, 4, 3}, /* cost of loading integer registers
390 in QImode, HImode and SImode.
391 Relative to reg-reg move (2). */
392 {3, 4, 3}, /* cost of storing integer registers */
393 4, /* cost of reg,reg fld/fst */
394 {4, 4, 12}, /* cost of loading fp registers
395 in SFmode, DFmode and XFmode */
396 {6, 6, 8}, /* cost of loading integer registers */
397 2, /* cost of moving MMX register */
398 {3, 3}, /* cost of loading MMX registers
399 in SImode and DImode */
400 {4, 4}, /* cost of storing MMX registers
401 in SImode and DImode */
402 2, /* cost of moving SSE register */
403 {4, 3, 6}, /* cost of loading SSE registers
404 in SImode, DImode and TImode */
405 {4, 4, 5}, /* cost of storing SSE registers
406 in SImode, DImode and TImode */
407 5, /* MMX or SSE register to integer */
408 64, /* size of prefetch block */
409 6, /* number of parallel prefetches */
411 4, /* cost of FADD and FSUB insns. */
412 4, /* cost of FMUL instruction. */
413 19, /* cost of FDIV instruction. */
414 2, /* cost of FABS instruction. */
415 2, /* cost of FCHS instruction. */
416 35, /* cost of FSQRT instruction. */
420 struct processor_costs pentium4_cost = {
421 1, /* cost of an add instruction */
422 3, /* cost of a lea instruction */
423 4, /* variable shift costs */
424 4, /* constant shift costs */
425 {15, 15, 15, 15, 15}, /* cost of starting a multiply */
426 0, /* cost of multiply per each bit set */
427 {56, 56, 56, 56, 56}, /* cost of a divide/mod */
428 1, /* cost of movsx */
429 1, /* cost of movzx */
430 16, /* "large" insn */
432 2, /* cost for loading QImode using movzbl */
433 {4, 5, 4}, /* cost of loading integer registers
434 in QImode, HImode and SImode.
435 Relative to reg-reg move (2). */
436 {2, 3, 2}, /* cost of storing integer registers */
437 2, /* cost of reg,reg fld/fst */
438 {2, 2, 6}, /* cost of loading fp registers
439 in SFmode, DFmode and XFmode */
440 {4, 4, 6}, /* cost of loading integer registers */
441 2, /* cost of moving MMX register */
442 {2, 2}, /* cost of loading MMX registers
443 in SImode and DImode */
444 {2, 2}, /* cost of storing MMX registers
445 in SImode and DImode */
446 12, /* cost of moving SSE register */
447 {12, 12, 12}, /* cost of loading SSE registers
448 in SImode, DImode and TImode */
449 {2, 2, 8}, /* cost of storing SSE registers
450 in SImode, DImode and TImode */
451 10, /* MMX or SSE register to integer */
452 64, /* size of prefetch block */
453 6, /* number of parallel prefetches */
455 5, /* cost of FADD and FSUB insns. */
456 7, /* cost of FMUL instruction. */
457 43, /* cost of FDIV instruction. */
458 2, /* cost of FABS instruction. */
459 2, /* cost of FCHS instruction. */
460 43, /* cost of FSQRT instruction. */
464 struct processor_costs nocona_cost = {
465 1, /* cost of an add instruction */
466 1, /* cost of a lea instruction */
467 1, /* variable shift costs */
468 1, /* constant shift costs */
469 {10, 10, 10, 10, 10}, /* cost of starting a multiply */
470 0, /* cost of multiply per each bit set */
471 {66, 66, 66, 66, 66}, /* cost of a divide/mod */
472 1, /* cost of movsx */
473 1, /* cost of movzx */
474 16, /* "large" insn */
476 4, /* cost for loading QImode using movzbl */
477 {4, 4, 4}, /* cost of loading integer registers
478 in QImode, HImode and SImode.
479 Relative to reg-reg move (2). */
480 {4, 4, 4}, /* cost of storing integer registers */
481 3, /* cost of reg,reg fld/fst */
482 {12, 12, 12}, /* cost of loading fp registers
483 in SFmode, DFmode and XFmode */
484 {4, 4, 4}, /* cost of loading integer registers */
485 6, /* cost of moving MMX register */
486 {12, 12}, /* cost of loading MMX registers
487 in SImode and DImode */
488 {12, 12}, /* cost of storing MMX registers
489 in SImode and DImode */
490 6, /* cost of moving SSE register */
491 {12, 12, 12}, /* cost of loading SSE registers
492 in SImode, DImode and TImode */
493 {12, 12, 12}, /* cost of storing SSE registers
494 in SImode, DImode and TImode */
495 8, /* MMX or SSE register to integer */
496 128, /* size of prefetch block */
497 8, /* number of parallel prefetches */
499 6, /* cost of FADD and FSUB insns. */
500 8, /* cost of FMUL instruction. */
501 40, /* cost of FDIV instruction. */
502 3, /* cost of FABS instruction. */
503 3, /* cost of FCHS instruction. */
504 44, /* cost of FSQRT instruction. */
507 const struct processor_costs *ix86_cost = &pentium_cost;
509 /* Processor feature/optimization bitmasks. */
510 #define m_386 (1<<PROCESSOR_I386)
511 #define m_486 (1<<PROCESSOR_I486)
512 #define m_PENT (1<<PROCESSOR_PENTIUM)
513 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
514 #define m_K6 (1<<PROCESSOR_K6)
515 #define m_ATHLON (1<<PROCESSOR_ATHLON)
516 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
517 #define m_K8 (1<<PROCESSOR_K8)
518 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
519 #define m_NOCONA (1<<PROCESSOR_NOCONA)
521 const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8;
522 const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
523 const int x86_zero_extend_with_and = m_486 | m_PENT;
524 const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA /* m_386 | m_K6 */;
525 const int x86_double_with_add = ~m_386;
526 const int x86_use_bit_test = m_386;
527 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6;
528 const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
529 const int x86_fisttp = m_NOCONA;
530 const int x86_3dnow_a = m_ATHLON_K8;
531 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
532 /* Branch hints were put in P4 based on simulation result. But
533 after P4 was made, no performance benefit was observed with
534 branch hints. It also increases the code size. As the result,
535 icc never generates branch hints. */
536 const int x86_branch_hints = 0;
537 const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA;
538 const int x86_partial_reg_stall = m_PPRO;
539 const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
540 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT);
541 const int x86_use_mov0 = m_K6;
542 const int x86_use_cltd = ~(m_PENT | m_K6);
543 const int x86_read_modify_write = ~m_PENT;
544 const int x86_read_modify = ~(m_PENT | m_PPRO);
545 const int x86_split_long_moves = m_PPRO;
546 const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8;
547 const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
548 const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
549 const int x86_qimode_math = ~(0);
550 const int x86_promote_qi_regs = 0;
551 const int x86_himode_math = ~(m_PPRO);
552 const int x86_promote_hi_regs = m_PPRO;
553 const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA;
554 const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA;
555 const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA;
556 const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA;
557 const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO);
558 const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
559 const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
560 const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO;
561 const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO;
562 const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO;
563 const int x86_decompose_lea = m_PENT4 | m_NOCONA;
564 const int x86_shift1 = ~m_486;
565 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
566 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO;
567 /* Set for machines where the type and dependencies are resolved on SSE
568 register parts instead of whole registers, so we may maintain just
569 lower part of scalar values in proper format leaving the upper part
571 const int x86_sse_split_regs = m_ATHLON_K8;
572 const int x86_sse_typeless_stores = m_ATHLON_K8;
573 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
574 const int x86_use_ffreep = m_ATHLON_K8;
575 const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
577 /* ??? Allowing interunit moves makes it all too easy for the compiler to put
578 integer data in xmm registers. Which results in pretty abysmal code. */
579 const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
581 const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO;
582 /* Some CPU cores are not able to predict more than 4 branch instructions in
583 the 16 byte window. */
584 const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
585 const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT;
586 const int x86_use_bt = m_ATHLON_K8;
587 /* Compare and exchange was added for 80486. */
588 const int x86_cmpxchg = ~m_386;
589 /* Exchange and add was added for 80486. */
590 const int x86_xadd = ~m_386;
592 /* In case the average insn count for single function invocation is
593 lower than this constant, emit fast (but longer) prologue and
595 #define FAST_PROLOGUE_INSN_COUNT 20
597 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
598 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
599 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
600 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
602 /* Array of the smallest class containing reg number REGNO, indexed by
603 REGNO. Used by REGNO_REG_CLASS in i386.h. */
605 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
608 AREG, DREG, CREG, BREG,
610 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
612 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
613 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
616 /* flags, fpsr, dirflag, frame */
617 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
618 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
620 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
622 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
623 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
624 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
628 /* The "default" register map used in 32bit mode. */
630 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
632 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
633 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
634 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
635 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
636 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
637 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
638 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
641 static int const x86_64_int_parameter_registers[6] =
643 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
644 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
647 static int const x86_64_int_return_registers[4] =
649 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
652 /* The "default" register map used in 64bit mode. */
653 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
655 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
656 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
657 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
658 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
659 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
660 8,9,10,11,12,13,14,15, /* extended integer registers */
661 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
664 /* Define the register numbers to be used in Dwarf debugging information.
665 The SVR4 reference port C compiler uses the following register numbers
666 in its Dwarf output code:
667 0 for %eax (gcc regno = 0)
668 1 for %ecx (gcc regno = 2)
669 2 for %edx (gcc regno = 1)
670 3 for %ebx (gcc regno = 3)
671 4 for %esp (gcc regno = 7)
672 5 for %ebp (gcc regno = 6)
673 6 for %esi (gcc regno = 4)
674 7 for %edi (gcc regno = 5)
675 The following three DWARF register numbers are never generated by
676 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
677 believes these numbers have these meanings.
678 8 for %eip (no gcc equivalent)
679 9 for %eflags (gcc regno = 17)
680 10 for %trapno (no gcc equivalent)
681 It is not at all clear how we should number the FP stack registers
682 for the x86 architecture. If the version of SDB on x86/svr4 were
683 a bit less brain dead with respect to floating-point then we would
684 have a precedent to follow with respect to DWARF register numbers
685 for x86 FP registers, but the SDB on x86/svr4 is so completely
686 broken with respect to FP registers that it is hardly worth thinking
687 of it as something to strive for compatibility with.
688 The version of x86/svr4 SDB I have at the moment does (partially)
689 seem to believe that DWARF register number 11 is associated with
690 the x86 register %st(0), but that's about all. Higher DWARF
691 register numbers don't seem to be associated with anything in
692 particular, and even for DWARF regno 11, SDB only seems to under-
693 stand that it should say that a variable lives in %st(0) (when
694 asked via an `=' command) if we said it was in DWARF regno 11,
695 but SDB still prints garbage when asked for the value of the
696 variable in question (via a `/' command).
697 (Also note that the labels SDB prints for various FP stack regs
698 when doing an `x' command are all wrong.)
699 Note that these problems generally don't affect the native SVR4
700 C compiler because it doesn't allow the use of -O with -g and
701 because when it is *not* optimizing, it allocates a memory
702 location for each floating-point variable, and the memory
703 location is what gets described in the DWARF AT_location
704 attribute for the variable in question.
705 Regardless of the severe mental illness of the x86/svr4 SDB, we
706 do something sensible here and we use the following DWARF
707 register numbers. Note that these are all stack-top-relative
709 11 for %st(0) (gcc regno = 8)
710 12 for %st(1) (gcc regno = 9)
711 13 for %st(2) (gcc regno = 10)
712 14 for %st(3) (gcc regno = 11)
713 15 for %st(4) (gcc regno = 12)
714 16 for %st(5) (gcc regno = 13)
715 17 for %st(6) (gcc regno = 14)
716 18 for %st(7) (gcc regno = 15)
718 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
720 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
721 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
722 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
723 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
724 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
725 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
726 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
729 /* Test and compare insns in i386.md store the information needed to
730 generate branch and scc insns here. */
732 rtx ix86_compare_op0 = NULL_RTX;
733 rtx ix86_compare_op1 = NULL_RTX;
734 rtx ix86_compare_emitted = NULL_RTX;
736 /* Size of the register save area. */
737 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
739 /* Define the structure for the machine field in struct function. */
741 struct stack_local_entry GTY(())
746 struct stack_local_entry *next;
749 /* Structure describing stack frame layout.
750 Stack grows downward:
756 saved frame pointer if frame_pointer_needed
757 <- HARD_FRAME_POINTER
763 > to_allocate <- FRAME_POINTER
775 int outgoing_arguments_size;
778 HOST_WIDE_INT to_allocate;
779 /* The offsets relative to ARG_POINTER. */
780 HOST_WIDE_INT frame_pointer_offset;
781 HOST_WIDE_INT hard_frame_pointer_offset;
782 HOST_WIDE_INT stack_pointer_offset;
784 /* When save_regs_using_mov is set, emit prologue using
785 move instead of push instructions. */
786 bool save_regs_using_mov;
789 /* Code model option. */
790 enum cmodel ix86_cmodel;
792 enum asm_dialect ix86_asm_dialect = ASM_ATT;
794 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
796 /* Which unit we are generating floating point math for. */
797 enum fpmath_unit ix86_fpmath;
799 /* Which cpu are we scheduling for. */
800 enum processor_type ix86_tune;
801 /* Which instruction set architecture to use. */
802 enum processor_type ix86_arch;
804 /* true if sse prefetch instruction is not NOOP. */
805 int x86_prefetch_sse;
807 /* ix86_regparm_string as a number */
808 static int ix86_regparm;
810 /* Preferred alignment for stack boundary in bits. */
811 unsigned int ix86_preferred_stack_boundary;
813 /* Values 1-5: see jump.c */
814 int ix86_branch_cost;
816 /* Variables which are this size or smaller are put in the data/bss
817 or ldata/lbss sections. */
819 int ix86_section_threshold = 65536;
821 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
822 char internal_label_prefix[16];
823 int internal_label_prefix_len;
825 static bool ix86_handle_option (size_t, const char *, int);
826 static void output_pic_addr_const (FILE *, rtx, int);
827 static void put_condition_code (enum rtx_code, enum machine_mode,
829 static const char *get_some_local_dynamic_name (void);
830 static int get_some_local_dynamic_name_1 (rtx *, void *);
831 static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
832 static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
834 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
835 static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
837 static rtx get_thread_pointer (int);
838 static rtx legitimize_tls_address (rtx, enum tls_model, int);
839 static void get_pc_thunk_name (char [32], unsigned int);
840 static rtx gen_push (rtx);
841 static int ix86_flags_dependant (rtx, rtx, enum attr_type);
842 static int ix86_agi_dependant (rtx, rtx, enum attr_type);
843 static struct machine_function * ix86_init_machine_status (void);
844 static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
845 static int ix86_nsaved_regs (void);
846 static void ix86_emit_save_regs (void);
847 static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
848 static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
849 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
850 static HOST_WIDE_INT ix86_GOT_alias_set (void);
851 static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
852 static rtx ix86_expand_aligntest (rtx, int);
853 static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
854 static int ix86_issue_rate (void);
855 static int ix86_adjust_cost (rtx, rtx, rtx, int);
856 static int ia32_multipass_dfa_lookahead (void);
857 static void ix86_init_mmx_sse_builtins (void);
858 static rtx x86_this_parameter (tree);
859 static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
860 HOST_WIDE_INT, tree);
861 static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
862 static void x86_file_start (void);
863 static void ix86_reorg (void);
864 static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
865 static tree ix86_build_builtin_va_list (void);
866 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
868 static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
869 static bool ix86_vector_mode_supported_p (enum machine_mode);
871 static int ix86_address_cost (rtx);
872 static bool ix86_cannot_force_const_mem (rtx);
873 static rtx ix86_delegitimize_address (rtx);
875 static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
877 struct builtin_description;
878 static rtx ix86_expand_sse_comi (const struct builtin_description *,
880 static rtx ix86_expand_sse_compare (const struct builtin_description *,
882 static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
883 static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
884 static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
885 static rtx ix86_expand_store_builtin (enum insn_code, tree);
886 static rtx safe_vector_operand (rtx, enum machine_mode);
887 static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
888 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
889 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
890 static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
891 static int ix86_fp_comparison_cost (enum rtx_code code);
892 static unsigned int ix86_select_alt_pic_regnum (void);
893 static int ix86_save_reg (unsigned int, int);
894 static void ix86_compute_frame_layout (struct ix86_frame *);
895 static int ix86_comp_type_attributes (tree, tree);
896 static int ix86_function_regparm (tree, tree);
897 const struct attribute_spec ix86_attribute_table[];
898 static bool ix86_function_ok_for_sibcall (tree, tree);
899 static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *);
900 static int ix86_value_regno (enum machine_mode, tree, tree);
901 static bool contains_128bit_aligned_vector_p (tree);
902 static rtx ix86_struct_value_rtx (tree, int);
903 static bool ix86_ms_bitfield_layout_p (tree);
904 static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
905 static int extended_reg_mentioned_1 (rtx *, void *);
906 static bool ix86_rtx_costs (rtx, int, int, int *);
907 static int min_insn_size (rtx);
908 static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers);
909 static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
910 static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
912 static void ix86_init_builtins (void);
913 static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
914 static const char *ix86_mangle_fundamental_type (tree);
915 static tree ix86_stack_protect_fail (void);
916 static rtx ix86_internal_arg_pointer (void);
917 static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int);
919 /* This function is only used on Solaris. */
920 static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
923 /* Register class used for passing given 64bit part of the argument.
924 These represent classes as documented by the PS ABI, with the exception
925 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
926 use SF or DFmode move instead of DImode to avoid reformatting penalties.
928 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
929 whenever possible (upper half does contain padding).
931 enum x86_64_reg_class
934 X86_64_INTEGER_CLASS,
935 X86_64_INTEGERSI_CLASS,
942 X86_64_COMPLEX_X87_CLASS,
945 static const char * const x86_64_reg_class_name[] = {
946 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
947 "sseup", "x87", "x87up", "cplx87", "no"
950 #define MAX_CLASSES 4
952 /* Table of constants used by fldpi, fldln2, etc.... */
953 static REAL_VALUE_TYPE ext_80387_constants_table [5];
954 static bool ext_80387_constants_init = 0;
955 static void init_ext_80387_constants (void);
956 static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED;
957 static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
958 static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED;
959 static section *x86_64_elf_select_section (tree decl, int reloc,
960 unsigned HOST_WIDE_INT align)
963 /* Initialize the GCC target structure. */
964 #undef TARGET_ATTRIBUTE_TABLE
965 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
966 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
967 # undef TARGET_MERGE_DECL_ATTRIBUTES
968 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
971 #undef TARGET_COMP_TYPE_ATTRIBUTES
972 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
974 #undef TARGET_INIT_BUILTINS
975 #define TARGET_INIT_BUILTINS ix86_init_builtins
976 #undef TARGET_EXPAND_BUILTIN
977 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
979 #undef TARGET_ASM_FUNCTION_EPILOGUE
980 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
982 #undef TARGET_ENCODE_SECTION_INFO
983 #ifndef SUBTARGET_ENCODE_SECTION_INFO
984 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
986 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
989 #undef TARGET_ASM_OPEN_PAREN
990 #define TARGET_ASM_OPEN_PAREN ""
991 #undef TARGET_ASM_CLOSE_PAREN
992 #define TARGET_ASM_CLOSE_PAREN ""
994 #undef TARGET_ASM_ALIGNED_HI_OP
995 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
996 #undef TARGET_ASM_ALIGNED_SI_OP
997 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
999 #undef TARGET_ASM_ALIGNED_DI_OP
1000 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1003 #undef TARGET_ASM_UNALIGNED_HI_OP
1004 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1005 #undef TARGET_ASM_UNALIGNED_SI_OP
1006 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1007 #undef TARGET_ASM_UNALIGNED_DI_OP
1008 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1010 #undef TARGET_SCHED_ADJUST_COST
1011 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1012 #undef TARGET_SCHED_ISSUE_RATE
1013 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1014 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1015 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1016 ia32_multipass_dfa_lookahead
1018 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1019 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1022 #undef TARGET_HAVE_TLS
1023 #define TARGET_HAVE_TLS true
1025 #undef TARGET_CANNOT_FORCE_CONST_MEM
1026 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1028 #undef TARGET_DELEGITIMIZE_ADDRESS
1029 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1031 #undef TARGET_MS_BITFIELD_LAYOUT_P
1032 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1035 #undef TARGET_BINDS_LOCAL_P
1036 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1039 #undef TARGET_ASM_OUTPUT_MI_THUNK
1040 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1041 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1042 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1044 #undef TARGET_ASM_FILE_START
1045 #define TARGET_ASM_FILE_START x86_file_start
1047 #undef TARGET_DEFAULT_TARGET_FLAGS
1048 #define TARGET_DEFAULT_TARGET_FLAGS \
1050 | TARGET_64BIT_DEFAULT \
1051 | TARGET_SUBTARGET_DEFAULT \
1052 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1054 #undef TARGET_HANDLE_OPTION
1055 #define TARGET_HANDLE_OPTION ix86_handle_option
1057 #undef TARGET_RTX_COSTS
1058 #define TARGET_RTX_COSTS ix86_rtx_costs
1059 #undef TARGET_ADDRESS_COST
1060 #define TARGET_ADDRESS_COST ix86_address_cost
1062 #undef TARGET_FIXED_CONDITION_CODE_REGS
1063 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1064 #undef TARGET_CC_MODES_COMPATIBLE
1065 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1067 #undef TARGET_MACHINE_DEPENDENT_REORG
1068 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1070 #undef TARGET_BUILD_BUILTIN_VA_LIST
1071 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1073 #undef TARGET_MD_ASM_CLOBBERS
1074 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1076 #undef TARGET_PROMOTE_PROTOTYPES
1077 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1078 #undef TARGET_STRUCT_VALUE_RTX
1079 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1080 #undef TARGET_SETUP_INCOMING_VARARGS
1081 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1082 #undef TARGET_MUST_PASS_IN_STACK
1083 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1084 #undef TARGET_PASS_BY_REFERENCE
1085 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1086 #undef TARGET_INTERNAL_ARG_POINTER
1087 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
1088 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
1089 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
1091 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1092 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1094 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1095 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1098 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1099 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1102 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1103 #undef TARGET_INSERT_ATTRIBUTES
1104 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1107 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1108 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1110 #undef TARGET_STACK_PROTECT_FAIL
1111 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1113 #undef TARGET_FUNCTION_VALUE
1114 #define TARGET_FUNCTION_VALUE ix86_function_value
1116 struct gcc_target targetm = TARGET_INITIALIZER;
1119 /* The svr4 ABI for the i386 says that records and unions are returned
1121 #ifndef DEFAULT_PCC_STRUCT_RETURN
1122 #define DEFAULT_PCC_STRUCT_RETURN 1
1125 /* Implement TARGET_HANDLE_OPTION. */
1128 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1135 target_flags &= ~MASK_3DNOW_A;
1136 target_flags_explicit |= MASK_3DNOW_A;
1143 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1144 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1151 target_flags &= ~(MASK_SSE2 | MASK_SSE3);
1152 target_flags_explicit |= MASK_SSE2 | MASK_SSE3;
1159 target_flags &= ~MASK_SSE3;
1160 target_flags_explicit |= MASK_SSE3;
1169 /* Sometimes certain combinations of command options do not make
1170 sense on a particular target machine. You can define a macro
1171 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1172 defined, is executed once just after all the command options have
1175 Don't use this macro to turn on various extra optimizations for
1176 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1179 override_options (void)
1182 int ix86_tune_defaulted = 0;
1184 /* Comes from final.c -- no real reason to change it. */
1185 #define MAX_CODE_ALIGN 16
1189 const struct processor_costs *cost; /* Processor costs */
1190 const int target_enable; /* Target flags to enable. */
1191 const int target_disable; /* Target flags to disable. */
1192 const int align_loop; /* Default alignments. */
1193 const int align_loop_max_skip;
1194 const int align_jump;
1195 const int align_jump_max_skip;
1196 const int align_func;
1198 const processor_target_table[PROCESSOR_max] =
1200 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1201 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1202 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1203 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1204 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1205 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1206 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1207 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1208 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0}
1211 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1214 const char *const name; /* processor name or nickname. */
1215 const enum processor_type processor;
1216 const enum pta_flags
1222 PTA_PREFETCH_SSE = 16,
1228 const processor_alias_table[] =
1230 {"i386", PROCESSOR_I386, 0},
1231 {"i486", PROCESSOR_I486, 0},
1232 {"i586", PROCESSOR_PENTIUM, 0},
1233 {"pentium", PROCESSOR_PENTIUM, 0},
1234 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1235 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1236 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1237 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1238 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1239 {"i686", PROCESSOR_PENTIUMPRO, 0},
1240 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1241 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1242 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1243 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1244 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1245 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1246 | PTA_MMX | PTA_PREFETCH_SSE},
1247 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1248 | PTA_MMX | PTA_PREFETCH_SSE},
1249 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1250 | PTA_MMX | PTA_PREFETCH_SSE},
1251 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1252 | PTA_MMX | PTA_PREFETCH_SSE},
1253 {"k6", PROCESSOR_K6, PTA_MMX},
1254 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1255 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1256 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1258 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1259 | PTA_3DNOW | PTA_3DNOW_A},
1260 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1261 | PTA_3DNOW_A | PTA_SSE},
1262 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1263 | PTA_3DNOW_A | PTA_SSE},
1264 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1265 | PTA_3DNOW_A | PTA_SSE},
1266 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1267 | PTA_SSE | PTA_SSE2 },
1268 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1269 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1270 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1271 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1272 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1273 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1274 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1275 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1278 int const pta_size = ARRAY_SIZE (processor_alias_table);
1280 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1281 SUBTARGET_OVERRIDE_OPTIONS;
1284 /* Set the default values for switches whose default depends on TARGET_64BIT
1285 in case they weren't overwritten by command line options. */
1288 if (flag_omit_frame_pointer == 2)
1289 flag_omit_frame_pointer = 1;
1290 if (flag_asynchronous_unwind_tables == 2)
1291 flag_asynchronous_unwind_tables = 1;
1292 if (flag_pcc_struct_return == 2)
1293 flag_pcc_struct_return = 0;
1297 if (flag_omit_frame_pointer == 2)
1298 flag_omit_frame_pointer = 0;
1299 if (flag_asynchronous_unwind_tables == 2)
1300 flag_asynchronous_unwind_tables = 0;
1301 if (flag_pcc_struct_return == 2)
1302 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1305 if (!ix86_tune_string && ix86_arch_string)
1306 ix86_tune_string = ix86_arch_string;
1307 if (!ix86_tune_string)
1309 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1310 ix86_tune_defaulted = 1;
1312 if (!ix86_arch_string)
1313 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1315 if (ix86_cmodel_string != 0)
1317 if (!strcmp (ix86_cmodel_string, "small"))
1318 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1319 else if (!strcmp (ix86_cmodel_string, "medium"))
1320 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1322 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
1323 else if (!strcmp (ix86_cmodel_string, "32"))
1324 ix86_cmodel = CM_32;
1325 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1326 ix86_cmodel = CM_KERNEL;
1327 else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
1328 ix86_cmodel = CM_LARGE;
1330 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1334 ix86_cmodel = CM_32;
1336 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1338 if (ix86_asm_string != 0)
1341 && !strcmp (ix86_asm_string, "intel"))
1342 ix86_asm_dialect = ASM_INTEL;
1343 else if (!strcmp (ix86_asm_string, "att"))
1344 ix86_asm_dialect = ASM_ATT;
1346 error ("bad value (%s) for -masm= switch", ix86_asm_string);
1348 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
1349 error ("code model %qs not supported in the %s bit mode",
1350 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
1351 if (ix86_cmodel == CM_LARGE)
1352 sorry ("code model %<large%> not supported yet");
1353 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
1354 sorry ("%i-bit mode not compiled in",
1355 (target_flags & MASK_64BIT) ? 64 : 32);
1357 for (i = 0; i < pta_size; i++)
1358 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
1360 ix86_arch = processor_alias_table[i].processor;
1361 /* Default cpu tuning to the architecture. */
1362 ix86_tune = ix86_arch;
1363 if (processor_alias_table[i].flags & PTA_MMX
1364 && !(target_flags_explicit & MASK_MMX))
1365 target_flags |= MASK_MMX;
1366 if (processor_alias_table[i].flags & PTA_3DNOW
1367 && !(target_flags_explicit & MASK_3DNOW))
1368 target_flags |= MASK_3DNOW;
1369 if (processor_alias_table[i].flags & PTA_3DNOW_A
1370 && !(target_flags_explicit & MASK_3DNOW_A))
1371 target_flags |= MASK_3DNOW_A;
1372 if (processor_alias_table[i].flags & PTA_SSE
1373 && !(target_flags_explicit & MASK_SSE))
1374 target_flags |= MASK_SSE;
1375 if (processor_alias_table[i].flags & PTA_SSE2
1376 && !(target_flags_explicit & MASK_SSE2))
1377 target_flags |= MASK_SSE2;
1378 if (processor_alias_table[i].flags & PTA_SSE3
1379 && !(target_flags_explicit & MASK_SSE3))
1380 target_flags |= MASK_SSE3;
1381 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1382 x86_prefetch_sse = true;
1383 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1384 error ("CPU you selected does not support x86-64 "
1390 error ("bad value (%s) for -march= switch", ix86_arch_string);
1392 for (i = 0; i < pta_size; i++)
1393 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
1395 ix86_tune = processor_alias_table[i].processor;
1396 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1398 if (ix86_tune_defaulted)
1400 ix86_tune_string = "x86-64";
1401 for (i = 0; i < pta_size; i++)
1402 if (! strcmp (ix86_tune_string,
1403 processor_alias_table[i].name))
1405 ix86_tune = processor_alias_table[i].processor;
1408 error ("CPU you selected does not support x86-64 "
1411 /* Intel CPUs have always interpreted SSE prefetch instructions as
1412 NOPs; so, we can enable SSE prefetch instructions even when
1413 -mtune (rather than -march) points us to a processor that has them.
1414 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1415 higher processors. */
1416 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
1417 x86_prefetch_sse = true;
1421 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1424 ix86_cost = &size_cost;
1426 ix86_cost = processor_target_table[ix86_tune].cost;
1427 target_flags |= processor_target_table[ix86_tune].target_enable;
1428 target_flags &= ~processor_target_table[ix86_tune].target_disable;
1430 /* Arrange to set up i386_stack_locals for all functions. */
1431 init_machine_status = ix86_init_machine_status;
1433 /* Validate -mregparm= value. */
1434 if (ix86_regparm_string)
1436 i = atoi (ix86_regparm_string);
1437 if (i < 0 || i > REGPARM_MAX)
1438 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
1444 ix86_regparm = REGPARM_MAX;
1446 /* If the user has provided any of the -malign-* options,
1447 warn and use that value only if -falign-* is not set.
1448 Remove this code in GCC 3.2 or later. */
1449 if (ix86_align_loops_string)
1451 warning (0, "-malign-loops is obsolete, use -falign-loops");
1452 if (align_loops == 0)
1454 i = atoi (ix86_align_loops_string);
1455 if (i < 0 || i > MAX_CODE_ALIGN)
1456 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1458 align_loops = 1 << i;
1462 if (ix86_align_jumps_string)
1464 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
1465 if (align_jumps == 0)
1467 i = atoi (ix86_align_jumps_string);
1468 if (i < 0 || i > MAX_CODE_ALIGN)
1469 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1471 align_jumps = 1 << i;
1475 if (ix86_align_funcs_string)
1477 warning (0, "-malign-functions is obsolete, use -falign-functions");
1478 if (align_functions == 0)
1480 i = atoi (ix86_align_funcs_string);
1481 if (i < 0 || i > MAX_CODE_ALIGN)
1482 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1484 align_functions = 1 << i;
1488 /* Default align_* from the processor table. */
1489 if (align_loops == 0)
1491 align_loops = processor_target_table[ix86_tune].align_loop;
1492 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
1494 if (align_jumps == 0)
1496 align_jumps = processor_target_table[ix86_tune].align_jump;
1497 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
1499 if (align_functions == 0)
1501 align_functions = processor_target_table[ix86_tune].align_func;
1504 /* Validate -mpreferred-stack-boundary= value, or provide default.
1505 The default of 128 bits is for Pentium III's SSE __m128, but we
1506 don't want additional code to keep the stack aligned when
1507 optimizing for code size. */
1508 ix86_preferred_stack_boundary = (optimize_size
1509 ? TARGET_64BIT ? 128 : 32
1511 if (ix86_preferred_stack_boundary_string)
1513 i = atoi (ix86_preferred_stack_boundary_string);
1514 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
1515 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
1516 TARGET_64BIT ? 4 : 2);
1518 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
1521 /* Validate -mbranch-cost= value, or provide default. */
1522 ix86_branch_cost = processor_target_table[ix86_tune].cost->branch_cost;
1523 if (ix86_branch_cost_string)
1525 i = atoi (ix86_branch_cost_string);
1527 error ("-mbranch-cost=%d is not between 0 and 5", i);
1529 ix86_branch_cost = i;
1531 if (ix86_section_threshold_string)
1533 i = atoi (ix86_section_threshold_string);
1535 error ("-mlarge-data-threshold=%d is negative", i);
1537 ix86_section_threshold = i;
1540 if (ix86_tls_dialect_string)
1542 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
1543 ix86_tls_dialect = TLS_DIALECT_GNU;
1544 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
1545 ix86_tls_dialect = TLS_DIALECT_SUN;
1547 error ("bad value (%s) for -mtls-dialect= switch",
1548 ix86_tls_dialect_string);
1551 /* Keep nonleaf frame pointers. */
1552 if (flag_omit_frame_pointer)
1553 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
1554 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
1555 flag_omit_frame_pointer = 1;
1557 /* If we're doing fast math, we don't care about comparison order
1558 wrt NaNs. This lets us use a shorter comparison sequence. */
1559 if (flag_unsafe_math_optimizations)
1560 target_flags &= ~MASK_IEEE_FP;
1562 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1563 since the insns won't need emulation. */
1564 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
1565 target_flags &= ~MASK_NO_FANCY_MATH_387;
1567 /* Likewise, if the target doesn't have a 387, or we've specified
1568 software floating point, don't use 387 inline intrinsics. */
1570 target_flags |= MASK_NO_FANCY_MATH_387;
1572 /* Turn on SSE2 builtins for -msse3. */
1574 target_flags |= MASK_SSE2;
1576 /* Turn on SSE builtins for -msse2. */
1578 target_flags |= MASK_SSE;
1580 /* Turn on MMX builtins for -msse. */
1583 target_flags |= MASK_MMX & ~target_flags_explicit;
1584 x86_prefetch_sse = true;
1587 /* Turn on MMX builtins for 3Dnow. */
1589 target_flags |= MASK_MMX;
1593 if (TARGET_ALIGN_DOUBLE)
1594 error ("-malign-double makes no sense in the 64bit mode");
1596 error ("-mrtd calling convention not supported in the 64bit mode");
1598 /* Enable by default the SSE and MMX builtins. Do allow the user to
1599 explicitly disable any of these. In particular, disabling SSE and
1600 MMX for kernel code is extremely useful. */
1602 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
1603 & ~target_flags_explicit);
1607 /* i386 ABI does not specify red zone. It still makes sense to use it
1608 when programmer takes care to stack from being destroyed. */
1609 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
1610 target_flags |= MASK_NO_RED_ZONE;
1613 /* Accept -msseregparm only if at least SSE support is enabled. */
1614 if (TARGET_SSEREGPARM
1616 error ("-msseregparm used without SSE enabled");
1618 ix86_fpmath = TARGET_FPMATH_DEFAULT;
1620 if (ix86_fpmath_string != 0)
1622 if (! strcmp (ix86_fpmath_string, "387"))
1623 ix86_fpmath = FPMATH_387;
1624 else if (! strcmp (ix86_fpmath_string, "sse"))
1628 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1629 ix86_fpmath = FPMATH_387;
1632 ix86_fpmath = FPMATH_SSE;
1634 else if (! strcmp (ix86_fpmath_string, "387,sse")
1635 || ! strcmp (ix86_fpmath_string, "sse,387"))
1639 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1640 ix86_fpmath = FPMATH_387;
1642 else if (!TARGET_80387)
1644 warning (0, "387 instruction set disabled, using SSE arithmetics");
1645 ix86_fpmath = FPMATH_SSE;
1648 ix86_fpmath = FPMATH_SSE | FPMATH_387;
1651 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
1654 /* If the i387 is disabled, then do not return values in it. */
1656 target_flags &= ~MASK_FLOAT_RETURNS;
1658 if ((x86_accumulate_outgoing_args & TUNEMASK)
1659 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1661 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1663 /* ??? Unwind info is not correct around the CFG unless either a frame
1664 pointer is present or M_A_O_A is set. Fixing this requires rewriting
1665 unwind info generation to be aware of the CFG and propagating states
1667 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
1668 || flag_exceptions || flag_non_call_exceptions)
1669 && flag_omit_frame_pointer
1670 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
1672 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1673 warning (0, "unwind tables currently require either a frame pointer "
1674 "or -maccumulate-outgoing-args for correctness");
1675 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1678 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1681 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
1682 p = strchr (internal_label_prefix, 'X');
1683 internal_label_prefix_len = p - internal_label_prefix;
1687 /* When scheduling description is not available, disable scheduler pass
1688 so it won't slow down the compilation and make x87 code slower. */
1689 if (!TARGET_SCHEDULE)
1690 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
1693 /* switch to the appropriate section for output of DECL.
1694 DECL is either a `VAR_DECL' node or a constant of some sort.
1695 RELOC indicates whether forming the initial value of DECL requires
1696 link-time relocations. */
1699 x86_64_elf_select_section (tree decl, int reloc,
1700 unsigned HOST_WIDE_INT align)
1702 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1703 && ix86_in_large_data_p (decl))
1705 const char *sname = NULL;
1706 unsigned int flags = SECTION_WRITE;
1707 switch (categorize_decl_for_section (decl, reloc, flag_pic))
1712 case SECCAT_DATA_REL:
1713 sname = ".ldata.rel";
1715 case SECCAT_DATA_REL_LOCAL:
1716 sname = ".ldata.rel.local";
1718 case SECCAT_DATA_REL_RO:
1719 sname = ".ldata.rel.ro";
1721 case SECCAT_DATA_REL_RO_LOCAL:
1722 sname = ".ldata.rel.ro.local";
1726 flags |= SECTION_BSS;
1729 case SECCAT_RODATA_MERGE_STR:
1730 case SECCAT_RODATA_MERGE_STR_INIT:
1731 case SECCAT_RODATA_MERGE_CONST:
1735 case SECCAT_SRODATA:
1742 /* We don't split these for medium model. Place them into
1743 default sections and hope for best. */
1748 /* We might get called with string constants, but get_named_section
1749 doesn't like them as they are not DECLs. Also, we need to set
1750 flags in that case. */
1752 return get_section (sname, flags, NULL);
1753 return get_named_section (decl, sname, reloc);
1756 return default_elf_select_section (decl, reloc, align);
1759 /* Build up a unique section name, expressed as a
1760 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
1761 RELOC indicates whether the initial value of EXP requires
1762 link-time relocations. */
1765 x86_64_elf_unique_section (tree decl, int reloc)
1767 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1768 && ix86_in_large_data_p (decl))
1770 const char *prefix = NULL;
1771 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
1772 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
1774 switch (categorize_decl_for_section (decl, reloc, flag_pic))
1777 case SECCAT_DATA_REL:
1778 case SECCAT_DATA_REL_LOCAL:
1779 case SECCAT_DATA_REL_RO:
1780 case SECCAT_DATA_REL_RO_LOCAL:
1781 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
1784 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
1787 case SECCAT_RODATA_MERGE_STR:
1788 case SECCAT_RODATA_MERGE_STR_INIT:
1789 case SECCAT_RODATA_MERGE_CONST:
1790 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
1792 case SECCAT_SRODATA:
1799 /* We don't split these for medium model. Place them into
1800 default sections and hope for best. */
1808 plen = strlen (prefix);
1810 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
1811 name = targetm.strip_name_encoding (name);
1812 nlen = strlen (name);
1814 string = alloca (nlen + plen + 1);
1815 memcpy (string, prefix, plen);
1816 memcpy (string + plen, name, nlen + 1);
1818 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
1822 default_unique_section (decl, reloc);
1825 #ifdef COMMON_ASM_OP
1826 /* This says how to output assembler code to declare an
1827 uninitialized external linkage data object.
1829 For medium model x86-64 we need to use .largecomm opcode for
1832 x86_elf_aligned_common (FILE *file,
1833 const char *name, unsigned HOST_WIDE_INT size,
1836 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1837 && size > (unsigned int)ix86_section_threshold)
1838 fprintf (file, ".largecomm\t");
1840 fprintf (file, "%s", COMMON_ASM_OP);
1841 assemble_name (file, name);
1842 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
1843 size, align / BITS_PER_UNIT);
1846 /* Utility function for targets to use in implementing
1847 ASM_OUTPUT_ALIGNED_BSS. */
1850 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
1851 const char *name, unsigned HOST_WIDE_INT size,
1854 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1855 && size > (unsigned int)ix86_section_threshold)
1856 switch_to_section (get_named_section (decl, ".lbss", 0));
1858 switch_to_section (bss_section);
1859 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
1860 #ifdef ASM_DECLARE_OBJECT_NAME
1861 last_assemble_variable_decl = decl;
1862 ASM_DECLARE_OBJECT_NAME (file, name, decl);
1864 /* Standard thing is just output label for the object. */
1865 ASM_OUTPUT_LABEL (file, name);
1866 #endif /* ASM_DECLARE_OBJECT_NAME */
1867 ASM_OUTPUT_SKIP (file, size ? size : 1);
1872 optimization_options (int level, int size ATTRIBUTE_UNUSED)
1874 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
1875 make the problem with not enough registers even worse. */
1876 #ifdef INSN_SCHEDULING
1878 flag_schedule_insns = 0;
1882 /* The Darwin libraries never set errno, so we might as well
1883 avoid calling them when that's the only reason we would. */
1884 flag_errno_math = 0;
1886 /* The default values of these switches depend on the TARGET_64BIT
1887 that is not known at this moment. Mark these values with 2 and
1888 let user the to override these. In case there is no command line option
1889 specifying them, we will set the defaults in override_options. */
1891 flag_omit_frame_pointer = 2;
1892 flag_pcc_struct_return = 2;
1893 flag_asynchronous_unwind_tables = 2;
1894 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1895 SUBTARGET_OPTIMIZATION_OPTIONS;
1899 /* Table of valid machine attributes. */
1900 const struct attribute_spec ix86_attribute_table[] =
1902 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1903 /* Stdcall attribute says callee is responsible for popping arguments
1904 if they are not variable. */
1905 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1906 /* Fastcall attribute says callee is responsible for popping arguments
1907 if they are not variable. */
1908 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1909 /* Cdecl attribute says the callee is a normal C declaration */
1910 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1911 /* Regparm attribute specifies how many integer arguments are to be
1912 passed in registers. */
1913 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
1914 /* Sseregparm attribute says we are using x86_64 calling conventions
1915 for FP arguments. */
1916 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1917 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1918 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
1919 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
1920 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
1922 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
1923 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
1924 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1925 SUBTARGET_ATTRIBUTE_TABLE,
1927 { NULL, 0, 0, false, false, false, NULL }
1930 /* Decide whether we can make a sibling call to a function. DECL is the
1931 declaration of the function being targeted by the call and EXP is the
1932 CALL_EXPR representing the call. */
1935 ix86_function_ok_for_sibcall (tree decl, tree exp)
1940 /* If we are generating position-independent code, we cannot sibcall
1941 optimize any indirect call, or a direct call to a global function,
1942 as the PLT requires %ebx be live. */
1943 if (!TARGET_64BIT && flag_pic && (!decl || TREE_PUBLIC (decl)))
1950 func = TREE_TYPE (TREE_OPERAND (exp, 0));
1951 if (POINTER_TYPE_P (func))
1952 func = TREE_TYPE (func);
1955 /* Check that the return value locations are the same. Like
1956 if we are returning floats on the 80387 register stack, we cannot
1957 make a sibcall from a function that doesn't return a float to a
1958 function that does or, conversely, from a function that does return
1959 a float to a function that doesn't; the necessary stack adjustment
1960 would not be executed. This is also the place we notice
1961 differences in the return value ABI. Note that it is ok for one
1962 of the functions to have void return type as long as the return
1963 value of the other is passed in a register. */
1964 a = ix86_function_value (TREE_TYPE (exp), func, false);
1965 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
1967 if (STACK_REG_P (a) || STACK_REG_P (b))
1969 if (!rtx_equal_p (a, b))
1972 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
1974 else if (!rtx_equal_p (a, b))
1977 /* If this call is indirect, we'll need to be able to use a call-clobbered
1978 register for the address of the target function. Make sure that all
1979 such registers are not used for passing parameters. */
1980 if (!decl && !TARGET_64BIT)
1984 /* We're looking at the CALL_EXPR, we need the type of the function. */
1985 type = TREE_OPERAND (exp, 0); /* pointer expression */
1986 type = TREE_TYPE (type); /* pointer type */
1987 type = TREE_TYPE (type); /* function type */
1989 if (ix86_function_regparm (type, NULL) >= 3)
1991 /* ??? Need to count the actual number of registers to be used,
1992 not the possible number of registers. Fix later. */
1997 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1998 /* Dllimport'd functions are also called indirectly. */
1999 if (decl && DECL_DLLIMPORT_P (decl)
2000 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2004 /* If we forced aligned the stack, then sibcalling would unalign the
2005 stack, which may break the called function. */
2006 if (cfun->machine->force_align_arg_pointer)
2009 /* Otherwise okay. That also includes certain types of indirect calls. */
2013 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2014 calling convention attributes;
2015 arguments as in struct attribute_spec.handler. */
2018 ix86_handle_cconv_attribute (tree *node, tree name,
2020 int flags ATTRIBUTE_UNUSED,
2023 if (TREE_CODE (*node) != FUNCTION_TYPE
2024 && TREE_CODE (*node) != METHOD_TYPE
2025 && TREE_CODE (*node) != FIELD_DECL
2026 && TREE_CODE (*node) != TYPE_DECL)
2028 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2029 IDENTIFIER_POINTER (name));
2030 *no_add_attrs = true;
2034 /* Can combine regparm with all attributes but fastcall. */
2035 if (is_attribute_p ("regparm", name))
2039 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2041 error ("fastcall and regparm attributes are not compatible");
2044 cst = TREE_VALUE (args);
2045 if (TREE_CODE (cst) != INTEGER_CST)
2047 warning (OPT_Wattributes,
2048 "%qs attribute requires an integer constant argument",
2049 IDENTIFIER_POINTER (name));
2050 *no_add_attrs = true;
2052 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2054 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2055 IDENTIFIER_POINTER (name), REGPARM_MAX);
2056 *no_add_attrs = true;
2064 warning (OPT_Wattributes, "%qs attribute ignored",
2065 IDENTIFIER_POINTER (name));
2066 *no_add_attrs = true;
2070 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2071 if (is_attribute_p ("fastcall", name))
2073 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2075 error ("fastcall and cdecl attributes are not compatible");
2077 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2079 error ("fastcall and stdcall attributes are not compatible");
2081 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2083 error ("fastcall and regparm attributes are not compatible");
2087 /* Can combine stdcall with fastcall (redundant), regparm and
2089 else if (is_attribute_p ("stdcall", name))
2091 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2093 error ("stdcall and cdecl attributes are not compatible");
2095 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2097 error ("stdcall and fastcall attributes are not compatible");
2101 /* Can combine cdecl with regparm and sseregparm. */
2102 else if (is_attribute_p ("cdecl", name))
2104 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2106 error ("stdcall and cdecl attributes are not compatible");
2108 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2110 error ("fastcall and cdecl attributes are not compatible");
2114 /* Can combine sseregparm with all attributes. */
2119 /* Return 0 if the attributes for two types are incompatible, 1 if they
2120 are compatible, and 2 if they are nearly compatible (which causes a
2121 warning to be generated). */
2124 ix86_comp_type_attributes (tree type1, tree type2)
2126 /* Check for mismatch of non-default calling convention. */
2127 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2129 if (TREE_CODE (type1) != FUNCTION_TYPE)
2132 /* Check for mismatched fastcall/regparm types. */
2133 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2134 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2135 || (ix86_function_regparm (type1, NULL)
2136 != ix86_function_regparm (type2, NULL)))
2139 /* Check for mismatched sseregparm types. */
2140 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2141 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2144 /* Check for mismatched return types (cdecl vs stdcall). */
2145 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2146 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2152 /* Return the regparm value for a function with the indicated TYPE and DECL.
2153 DECL may be NULL when calling function indirectly
2154 or considering a libcall. */
2157 ix86_function_regparm (tree type, tree decl)
2160 int regparm = ix86_regparm;
2161 bool user_convention = false;
2165 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2168 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2169 user_convention = true;
2172 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2175 user_convention = true;
2178 /* Use register calling convention for local functions when possible. */
2179 if (!TARGET_64BIT && !user_convention && decl
2180 && flag_unit_at_a_time && !profile_flag)
2182 struct cgraph_local_info *i = cgraph_local_info (decl);
2185 int local_regparm, globals = 0, regno;
2187 /* Make sure no regparm register is taken by a global register
2189 for (local_regparm = 0; local_regparm < 3; local_regparm++)
2190 if (global_regs[local_regparm])
2192 /* We can't use regparm(3) for nested functions as these use
2193 static chain pointer in third argument. */
2194 if (local_regparm == 3
2195 && decl_function_context (decl)
2196 && !DECL_NO_STATIC_CHAIN (decl))
2198 /* Each global register variable increases register preassure,
2199 so the more global reg vars there are, the smaller regparm
2200 optimization use, unless requested by the user explicitly. */
2201 for (regno = 0; regno < 6; regno++)
2202 if (global_regs[regno])
2205 = globals < local_regparm ? local_regparm - globals : 0;
2207 if (local_regparm > regparm)
2208 regparm = local_regparm;
2215 /* Return 1 or 2, if we can pass up to 8 SFmode (1) and DFmode (2) arguments
2216 in SSE registers for a function with the indicated TYPE and DECL.
2217 DECL may be NULL when calling function indirectly
2218 or considering a libcall. Otherwise return 0. */
2221 ix86_function_sseregparm (tree type, tree decl)
2223 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2224 by the sseregparm attribute. */
2225 if (TARGET_SSEREGPARM
2227 && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2232 error ("Calling %qD with attribute sseregparm without "
2233 "SSE/SSE2 enabled", decl);
2235 error ("Calling %qT with attribute sseregparm without "
2236 "SSE/SSE2 enabled", type);
2243 /* For local functions, pass SFmode (and DFmode for SSE2) arguments
2244 in SSE registers even for 32-bit mode and not just 3, but up to
2245 8 SSE arguments in registers. */
2246 if (!TARGET_64BIT && decl
2247 && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
2249 struct cgraph_local_info *i = cgraph_local_info (decl);
2251 return TARGET_SSE2 ? 2 : 1;
2257 /* Return true if EAX is live at the start of the function. Used by
2258 ix86_expand_prologue to determine if we need special help before
2259 calling allocate_stack_worker. */
2262 ix86_eax_live_at_start_p (void)
2264 /* Cheat. Don't bother working forward from ix86_function_regparm
2265 to the function type to whether an actual argument is located in
2266 eax. Instead just look at cfg info, which is still close enough
2267 to correct at this point. This gives false positives for broken
2268 functions that might use uninitialized data that happens to be
2269 allocated in eax, but who cares? */
2270 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0);
2273 /* Value is the number of bytes of arguments automatically
2274 popped when returning from a subroutine call.
2275 FUNDECL is the declaration node of the function (as a tree),
2276 FUNTYPE is the data type of the function (as a tree),
2277 or for a library call it is an identifier node for the subroutine name.
2278 SIZE is the number of bytes of arguments passed on the stack.
2280 On the 80386, the RTD insn may be used to pop them if the number
2281 of args is fixed, but if the number is variable then the caller
2282 must pop them all. RTD can't be used for library calls now
2283 because the library is compiled with the Unix compiler.
2284 Use of RTD is a selectable option, since it is incompatible with
2285 standard Unix calling sequences. If the option is not selected,
2286 the caller must always pop the args.
2288 The attribute stdcall is equivalent to RTD on a per module basis. */
2291 ix86_return_pops_args (tree fundecl, tree funtype, int size)
2293 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
2295 /* Cdecl functions override -mrtd, and never pop the stack. */
2296 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
2298 /* Stdcall and fastcall functions will pop the stack if not
2300 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
2301 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
2305 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
2306 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
2307 == void_type_node)))
2311 /* Lose any fake structure return argument if it is passed on the stack. */
2312 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
2314 && !KEEP_AGGREGATE_RETURN_POINTER)
2316 int nregs = ix86_function_regparm (funtype, fundecl);
2319 return GET_MODE_SIZE (Pmode);
2325 /* Argument support functions. */
2327 /* Return true when register may be used to pass function parameters. */
2329 ix86_function_arg_regno_p (int regno)
2333 return (regno < REGPARM_MAX
2334 || (TARGET_MMX && MMX_REGNO_P (regno)
2335 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
2336 || (TARGET_SSE && SSE_REGNO_P (regno)
2337 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
2339 if (TARGET_SSE && SSE_REGNO_P (regno)
2340 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
2342 /* RAX is used as hidden argument to va_arg functions. */
2345 for (i = 0; i < REGPARM_MAX; i++)
2346 if (regno == x86_64_int_parameter_registers[i])
2351 /* Return if we do not know how to pass TYPE solely in registers. */
2354 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
2356 if (must_pass_in_stack_var_size_or_pad (mode, type))
2359 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
2360 The layout_type routine is crafty and tries to trick us into passing
2361 currently unsupported vector types on the stack by using TImode. */
2362 return (!TARGET_64BIT && mode == TImode
2363 && type && TREE_CODE (type) != VECTOR_TYPE);
2366 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2367 for a call to a function whose data type is FNTYPE.
2368 For a library call, FNTYPE is 0. */
2371 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
2372 tree fntype, /* tree ptr for function decl */
2373 rtx libname, /* SYMBOL_REF of library name or 0 */
2376 static CUMULATIVE_ARGS zero_cum;
2377 tree param, next_param;
2379 if (TARGET_DEBUG_ARG)
2381 fprintf (stderr, "\ninit_cumulative_args (");
2383 fprintf (stderr, "fntype code = %s, ret code = %s",
2384 tree_code_name[(int) TREE_CODE (fntype)],
2385 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
2387 fprintf (stderr, "no fntype");
2390 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
2395 /* Set up the number of registers to use for passing arguments. */
2396 cum->nregs = ix86_regparm;
2398 cum->sse_nregs = SSE_REGPARM_MAX;
2400 cum->mmx_nregs = MMX_REGPARM_MAX;
2401 cum->warn_sse = true;
2402 cum->warn_mmx = true;
2403 cum->maybe_vaarg = false;
2405 /* Use ecx and edx registers if function has fastcall attribute,
2406 else look for regparm information. */
2407 if (fntype && !TARGET_64BIT)
2409 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
2415 cum->nregs = ix86_function_regparm (fntype, fndecl);
2418 /* Set up the number of SSE registers used for passing SFmode
2419 and DFmode arguments. Warn for mismatching ABI. */
2420 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
2422 /* Determine if this function has variable arguments. This is
2423 indicated by the last argument being 'void_type_mode' if there
2424 are no variable arguments. If there are variable arguments, then
2425 we won't pass anything in registers in 32-bit mode. */
2427 if (cum->nregs || cum->mmx_nregs || cum->sse_nregs)
2429 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2430 param != 0; param = next_param)
2432 next_param = TREE_CHAIN (param);
2433 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
2443 cum->float_in_sse = 0;
2445 cum->maybe_vaarg = true;
2449 if ((!fntype && !libname)
2450 || (fntype && !TYPE_ARG_TYPES (fntype)))
2451 cum->maybe_vaarg = true;
2453 if (TARGET_DEBUG_ARG)
2454 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
2459 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
2460 But in the case of vector types, it is some vector mode.
2462 When we have only some of our vector isa extensions enabled, then there
2463 are some modes for which vector_mode_supported_p is false. For these
2464 modes, the generic vector support in gcc will choose some non-vector mode
2465 in order to implement the type. By computing the natural mode, we'll
2466 select the proper ABI location for the operand and not depend on whatever
2467 the middle-end decides to do with these vector types. */
2469 static enum machine_mode
2470 type_natural_mode (tree type)
2472 enum machine_mode mode = TYPE_MODE (type);
2474 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
2476 HOST_WIDE_INT size = int_size_in_bytes (type);
2477 if ((size == 8 || size == 16)
2478 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
2479 && TYPE_VECTOR_SUBPARTS (type) > 1)
2481 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
2483 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
2484 mode = MIN_MODE_VECTOR_FLOAT;
2486 mode = MIN_MODE_VECTOR_INT;
2488 /* Get the mode which has this inner mode and number of units. */
2489 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
2490 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
2491 && GET_MODE_INNER (mode) == innermode)
2501 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
2502 this may not agree with the mode that the type system has chosen for the
2503 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
2504 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
2507 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
2512 if (orig_mode != BLKmode)
2513 tmp = gen_rtx_REG (orig_mode, regno);
2516 tmp = gen_rtx_REG (mode, regno);
2517 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
2518 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
2524 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
2525 of this code is to classify each 8bytes of incoming argument by the register
2526 class and assign registers accordingly. */
2528 /* Return the union class of CLASS1 and CLASS2.
2529 See the x86-64 PS ABI for details. */
2531 static enum x86_64_reg_class
2532 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
2534 /* Rule #1: If both classes are equal, this is the resulting class. */
2535 if (class1 == class2)
2538 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
2540 if (class1 == X86_64_NO_CLASS)
2542 if (class2 == X86_64_NO_CLASS)
2545 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
2546 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
2547 return X86_64_MEMORY_CLASS;
2549 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
2550 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
2551 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
2552 return X86_64_INTEGERSI_CLASS;
2553 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
2554 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
2555 return X86_64_INTEGER_CLASS;
2557 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
2559 if (class1 == X86_64_X87_CLASS
2560 || class1 == X86_64_X87UP_CLASS
2561 || class1 == X86_64_COMPLEX_X87_CLASS
2562 || class2 == X86_64_X87_CLASS
2563 || class2 == X86_64_X87UP_CLASS
2564 || class2 == X86_64_COMPLEX_X87_CLASS)
2565 return X86_64_MEMORY_CLASS;
2567 /* Rule #6: Otherwise class SSE is used. */
2568 return X86_64_SSE_CLASS;
2571 /* Classify the argument of type TYPE and mode MODE.
2572 CLASSES will be filled by the register class used to pass each word
2573 of the operand. The number of words is returned. In case the parameter
2574 should be passed in memory, 0 is returned. As a special case for zero
2575 sized containers, classes[0] will be NO_CLASS and 1 is returned.
2577 BIT_OFFSET is used internally for handling records and specifies offset
2578 of the offset in bits modulo 256 to avoid overflow cases.
2580 See the x86-64 PS ABI for details.
2584 classify_argument (enum machine_mode mode, tree type,
2585 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
2587 HOST_WIDE_INT bytes =
2588 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2589 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2591 /* Variable sized entities are always passed/returned in memory. */
2595 if (mode != VOIDmode
2596 && targetm.calls.must_pass_in_stack (mode, type))
2599 if (type && AGGREGATE_TYPE_P (type))
2603 enum x86_64_reg_class subclasses[MAX_CLASSES];
2605 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
2609 for (i = 0; i < words; i++)
2610 classes[i] = X86_64_NO_CLASS;
2612 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
2613 signalize memory class, so handle it as special case. */
2616 classes[0] = X86_64_NO_CLASS;
2620 /* Classify each field of record and merge classes. */
2621 switch (TREE_CODE (type))
2624 /* For classes first merge in the field of the subclasses. */
2625 if (TYPE_BINFO (type))
2627 tree binfo, base_binfo;
2630 for (binfo = TYPE_BINFO (type), basenum = 0;
2631 BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++)
2634 int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8;
2635 tree type = BINFO_TYPE (base_binfo);
2637 num = classify_argument (TYPE_MODE (type),
2639 (offset + bit_offset) % 256);
2642 for (i = 0; i < num; i++)
2644 int pos = (offset + (bit_offset % 64)) / 8 / 8;
2646 merge_classes (subclasses[i], classes[i + pos]);
2650 /* And now merge the fields of structure. */
2651 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2653 if (TREE_CODE (field) == FIELD_DECL)
2657 /* Bitfields are always classified as integer. Handle them
2658 early, since later code would consider them to be
2659 misaligned integers. */
2660 if (DECL_BIT_FIELD (field))
2662 for (i = int_bit_position (field) / 8 / 8;
2663 i < (int_bit_position (field)
2664 + tree_low_cst (DECL_SIZE (field), 0)
2667 merge_classes (X86_64_INTEGER_CLASS,
2672 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2673 TREE_TYPE (field), subclasses,
2674 (int_bit_position (field)
2675 + bit_offset) % 256);
2678 for (i = 0; i < num; i++)
2681 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
2683 merge_classes (subclasses[i], classes[i + pos]);
2691 /* Arrays are handled as small records. */
2694 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
2695 TREE_TYPE (type), subclasses, bit_offset);
2699 /* The partial classes are now full classes. */
2700 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
2701 subclasses[0] = X86_64_SSE_CLASS;
2702 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
2703 subclasses[0] = X86_64_INTEGER_CLASS;
2705 for (i = 0; i < words; i++)
2706 classes[i] = subclasses[i % num];
2711 case QUAL_UNION_TYPE:
2712 /* Unions are similar to RECORD_TYPE but offset is always 0.
2715 /* Unions are not derived. */
2716 gcc_assert (!TYPE_BINFO (type)
2717 || !BINFO_N_BASE_BINFOS (TYPE_BINFO (type)));
2718 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2720 if (TREE_CODE (field) == FIELD_DECL)
2723 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2724 TREE_TYPE (field), subclasses,
2728 for (i = 0; i < num; i++)
2729 classes[i] = merge_classes (subclasses[i], classes[i]);
2738 /* Final merger cleanup. */
2739 for (i = 0; i < words; i++)
2741 /* If one class is MEMORY, everything should be passed in
2743 if (classes[i] == X86_64_MEMORY_CLASS)
2746 /* The X86_64_SSEUP_CLASS should be always preceded by
2747 X86_64_SSE_CLASS. */
2748 if (classes[i] == X86_64_SSEUP_CLASS
2749 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
2750 classes[i] = X86_64_SSE_CLASS;
2752 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
2753 if (classes[i] == X86_64_X87UP_CLASS
2754 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
2755 classes[i] = X86_64_SSE_CLASS;
2760 /* Compute alignment needed. We align all types to natural boundaries with
2761 exception of XFmode that is aligned to 64bits. */
2762 if (mode != VOIDmode && mode != BLKmode)
2764 int mode_alignment = GET_MODE_BITSIZE (mode);
2767 mode_alignment = 128;
2768 else if (mode == XCmode)
2769 mode_alignment = 256;
2770 if (COMPLEX_MODE_P (mode))
2771 mode_alignment /= 2;
2772 /* Misaligned fields are always returned in memory. */
2773 if (bit_offset % mode_alignment)
2777 /* for V1xx modes, just use the base mode */
2778 if (VECTOR_MODE_P (mode)
2779 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
2780 mode = GET_MODE_INNER (mode);
2782 /* Classification of atomic types. */
2792 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
2793 classes[0] = X86_64_INTEGERSI_CLASS;
2795 classes[0] = X86_64_INTEGER_CLASS;
2799 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
2804 if (!(bit_offset % 64))
2805 classes[0] = X86_64_SSESF_CLASS;
2807 classes[0] = X86_64_SSE_CLASS;
2810 classes[0] = X86_64_SSEDF_CLASS;
2813 classes[0] = X86_64_X87_CLASS;
2814 classes[1] = X86_64_X87UP_CLASS;
2817 classes[0] = X86_64_SSE_CLASS;
2818 classes[1] = X86_64_SSEUP_CLASS;
2821 classes[0] = X86_64_SSE_CLASS;
2824 classes[0] = X86_64_SSEDF_CLASS;
2825 classes[1] = X86_64_SSEDF_CLASS;
2828 classes[0] = X86_64_COMPLEX_X87_CLASS;
2831 /* This modes is larger than 16 bytes. */
2839 classes[0] = X86_64_SSE_CLASS;
2840 classes[1] = X86_64_SSEUP_CLASS;
2846 classes[0] = X86_64_SSE_CLASS;
2852 gcc_assert (VECTOR_MODE_P (mode));
2857 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
2859 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
2860 classes[0] = X86_64_INTEGERSI_CLASS;
2862 classes[0] = X86_64_INTEGER_CLASS;
2863 classes[1] = X86_64_INTEGER_CLASS;
2864 return 1 + (bytes > 8);
2868 /* Examine the argument and return set number of register required in each
2869 class. Return 0 iff parameter should be passed in memory. */
2871 examine_argument (enum machine_mode mode, tree type, int in_return,
2872 int *int_nregs, int *sse_nregs)
2874 enum x86_64_reg_class class[MAX_CLASSES];
2875 int n = classify_argument (mode, type, class, 0);
2881 for (n--; n >= 0; n--)
2884 case X86_64_INTEGER_CLASS:
2885 case X86_64_INTEGERSI_CLASS:
2888 case X86_64_SSE_CLASS:
2889 case X86_64_SSESF_CLASS:
2890 case X86_64_SSEDF_CLASS:
2893 case X86_64_NO_CLASS:
2894 case X86_64_SSEUP_CLASS:
2896 case X86_64_X87_CLASS:
2897 case X86_64_X87UP_CLASS:
2901 case X86_64_COMPLEX_X87_CLASS:
2902 return in_return ? 2 : 0;
2903 case X86_64_MEMORY_CLASS:
2909 /* Construct container for the argument used by GCC interface. See
2910 FUNCTION_ARG for the detailed description. */
2913 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
2914 tree type, int in_return, int nintregs, int nsseregs,
2915 const int *intreg, int sse_regno)
2917 enum machine_mode tmpmode;
2919 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2920 enum x86_64_reg_class class[MAX_CLASSES];
2924 int needed_sseregs, needed_intregs;
2925 rtx exp[MAX_CLASSES];
2928 n = classify_argument (mode, type, class, 0);
2929 if (TARGET_DEBUG_ARG)
2932 fprintf (stderr, "Memory class\n");
2935 fprintf (stderr, "Classes:");
2936 for (i = 0; i < n; i++)
2938 fprintf (stderr, " %s", x86_64_reg_class_name[class[i]]);
2940 fprintf (stderr, "\n");
2945 if (!examine_argument (mode, type, in_return, &needed_intregs,
2948 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
2951 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
2952 some less clueful developer tries to use floating-point anyway. */
2953 if (needed_sseregs && !TARGET_SSE)
2955 static bool issued_error;
2958 issued_error = true;
2960 error ("SSE register return with SSE disabled");
2962 error ("SSE register argument with SSE disabled");
2967 /* First construct simple cases. Avoid SCmode, since we want to use
2968 single register to pass this type. */
2969 if (n == 1 && mode != SCmode)
2972 case X86_64_INTEGER_CLASS:
2973 case X86_64_INTEGERSI_CLASS:
2974 return gen_rtx_REG (mode, intreg[0]);
2975 case X86_64_SSE_CLASS:
2976 case X86_64_SSESF_CLASS:
2977 case X86_64_SSEDF_CLASS:
2978 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
2979 case X86_64_X87_CLASS:
2980 case X86_64_COMPLEX_X87_CLASS:
2981 return gen_rtx_REG (mode, FIRST_STACK_REG);
2982 case X86_64_NO_CLASS:
2983 /* Zero sized array, struct or class. */
2988 if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
2990 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
2992 && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
2993 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
2994 if (n == 2 && class[0] == X86_64_INTEGER_CLASS
2995 && class[1] == X86_64_INTEGER_CLASS
2996 && (mode == CDImode || mode == TImode || mode == TFmode)
2997 && intreg[0] + 1 == intreg[1])
2998 return gen_rtx_REG (mode, intreg[0]);
3000 /* Otherwise figure out the entries of the PARALLEL. */
3001 for (i = 0; i < n; i++)
3005 case X86_64_NO_CLASS:
3007 case X86_64_INTEGER_CLASS:
3008 case X86_64_INTEGERSI_CLASS:
3009 /* Merge TImodes on aligned occasions here too. */
3010 if (i * 8 + 8 > bytes)
3011 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
3012 else if (class[i] == X86_64_INTEGERSI_CLASS)
3016 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3017 if (tmpmode == BLKmode)
3019 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3020 gen_rtx_REG (tmpmode, *intreg),
3024 case X86_64_SSESF_CLASS:
3025 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3026 gen_rtx_REG (SFmode,
3027 SSE_REGNO (sse_regno)),
3031 case X86_64_SSEDF_CLASS:
3032 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3033 gen_rtx_REG (DFmode,
3034 SSE_REGNO (sse_regno)),
3038 case X86_64_SSE_CLASS:
3039 if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
3043 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3044 gen_rtx_REG (tmpmode,
3045 SSE_REGNO (sse_regno)),
3047 if (tmpmode == TImode)
3056 /* Empty aligned struct, union or class. */
3060 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3061 for (i = 0; i < nexps; i++)
3062 XVECEXP (ret, 0, i) = exp [i];
3066 /* Update the data in CUM to advance over an argument
3067 of mode MODE and data type TYPE.
3068 (TYPE is null for libcalls where that information may not be available.) */
3071 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3072 tree type, int named)
3075 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3076 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3079 mode = type_natural_mode (type);
3081 if (TARGET_DEBUG_ARG)
3082 fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, "
3083 "mode=%s, named=%d)\n\n",
3084 words, cum->words, cum->nregs, cum->sse_nregs,
3085 GET_MODE_NAME (mode), named);
3089 int int_nregs, sse_nregs;
3090 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3091 cum->words += words;
3092 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3094 cum->nregs -= int_nregs;
3095 cum->sse_nregs -= sse_nregs;
3096 cum->regno += int_nregs;
3097 cum->sse_regno += sse_nregs;
3100 cum->words += words;
3118 cum->words += words;
3119 cum->nregs -= words;
3120 cum->regno += words;
3122 if (cum->nregs <= 0)
3130 if (cum->float_in_sse < 2)
3133 if (cum->float_in_sse < 1)
3144 if (!type || !AGGREGATE_TYPE_P (type))
3146 cum->sse_words += words;
3147 cum->sse_nregs -= 1;
3148 cum->sse_regno += 1;
3149 if (cum->sse_nregs <= 0)
3161 if (!type || !AGGREGATE_TYPE_P (type))
3163 cum->mmx_words += words;
3164 cum->mmx_nregs -= 1;
3165 cum->mmx_regno += 1;
3166 if (cum->mmx_nregs <= 0)
3177 /* Define where to put the arguments to a function.
3178 Value is zero to push the argument on the stack,
3179 or a hard register in which to store the argument.
3181 MODE is the argument's machine mode.
3182 TYPE is the data type of the argument (as a tree).
3183 This is null for libcalls where that information may
3185 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3186 the preceding args and about the function being called.
3187 NAMED is nonzero if this argument is a named parameter
3188 (otherwise it is an extra parameter matching an ellipsis). */
3191 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode,
3192 tree type, int named)
3194 enum machine_mode mode = orig_mode;
3197 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3198 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3199 static bool warnedsse, warnedmmx;
3201 /* To simplify the code below, represent vector types with a vector mode
3202 even if MMX/SSE are not active. */
3203 if (type && TREE_CODE (type) == VECTOR_TYPE)
3204 mode = type_natural_mode (type);
3206 /* Handle a hidden AL argument containing number of registers for varargs
3207 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
3209 if (mode == VOIDmode)
3212 return GEN_INT (cum->maybe_vaarg
3213 ? (cum->sse_nregs < 0
3221 ret = construct_container (mode, orig_mode, type, 0, cum->nregs,
3223 &x86_64_int_parameter_registers [cum->regno],
3228 /* For now, pass fp/complex values on the stack. */
3240 if (words <= cum->nregs)
3242 int regno = cum->regno;
3244 /* Fastcall allocates the first two DWORD (SImode) or
3245 smaller arguments to ECX and EDX. */
3248 if (mode == BLKmode || mode == DImode)
3251 /* ECX not EAX is the first allocated register. */
3255 ret = gen_rtx_REG (mode, regno);
3259 if (cum->float_in_sse < 2)
3262 if (cum->float_in_sse < 1)
3272 if (!type || !AGGREGATE_TYPE_P (type))
3274 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
3277 warning (0, "SSE vector argument without SSE enabled "
3281 ret = gen_reg_or_parallel (mode, orig_mode,
3282 cum->sse_regno + FIRST_SSE_REG);
3289 if (!type || !AGGREGATE_TYPE_P (type))
3291 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
3294 warning (0, "MMX vector argument without MMX enabled "
3298 ret = gen_reg_or_parallel (mode, orig_mode,
3299 cum->mmx_regno + FIRST_MMX_REG);
3304 if (TARGET_DEBUG_ARG)
3307 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
3308 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
3311 print_simple_rtl (stderr, ret);
3313 fprintf (stderr, ", stack");
3315 fprintf (stderr, " )\n");
3321 /* A C expression that indicates when an argument must be passed by
3322 reference. If nonzero for an argument, a copy of that argument is
3323 made in memory and a pointer to the argument is passed instead of
3324 the argument itself. The pointer is passed in whatever way is
3325 appropriate for passing a pointer to that type. */
3328 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3329 enum machine_mode mode ATTRIBUTE_UNUSED,
3330 tree type, bool named ATTRIBUTE_UNUSED)
3335 if (type && int_size_in_bytes (type) == -1)
3337 if (TARGET_DEBUG_ARG)
3338 fprintf (stderr, "function_arg_pass_by_reference\n");
3345 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
3346 ABI. Only called if TARGET_SSE. */
3348 contains_128bit_aligned_vector_p (tree type)
3350 enum machine_mode mode = TYPE_MODE (type);
3351 if (SSE_REG_MODE_P (mode)
3352 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
3354 if (TYPE_ALIGN (type) < 128)
3357 if (AGGREGATE_TYPE_P (type))
3359 /* Walk the aggregates recursively. */
3360 switch (TREE_CODE (type))
3364 case QUAL_UNION_TYPE:
3368 if (TYPE_BINFO (type))
3370 tree binfo, base_binfo;
3373 for (binfo = TYPE_BINFO (type), i = 0;
3374 BINFO_BASE_ITERATE (binfo, i, base_binfo); i++)
3375 if (contains_128bit_aligned_vector_p
3376 (BINFO_TYPE (base_binfo)))
3379 /* And now merge the fields of structure. */
3380 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3382 if (TREE_CODE (field) == FIELD_DECL
3383 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
3390 /* Just for use if some languages passes arrays by value. */
3391 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
3402 /* Gives the alignment boundary, in bits, of an argument with the
3403 specified mode and type. */
3406 ix86_function_arg_boundary (enum machine_mode mode, tree type)
3410 align = TYPE_ALIGN (type);
3412 align = GET_MODE_ALIGNMENT (mode);
3413 if (align < PARM_BOUNDARY)
3414 align = PARM_BOUNDARY;
3417 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
3418 make an exception for SSE modes since these require 128bit
3421 The handling here differs from field_alignment. ICC aligns MMX
3422 arguments to 4 byte boundaries, while structure fields are aligned
3423 to 8 byte boundaries. */
3425 align = PARM_BOUNDARY;
3428 if (!SSE_REG_MODE_P (mode))
3429 align = PARM_BOUNDARY;
3433 if (!contains_128bit_aligned_vector_p (type))
3434 align = PARM_BOUNDARY;
3442 /* Return true if N is a possible register number of function value. */
3444 ix86_function_value_regno_p (int regno)
3447 || (regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)
3448 || (regno == FIRST_SSE_REG && TARGET_SSE))
3452 && (regno == FIRST_MMX_REG && TARGET_MMX))
3458 /* Define how to find the value returned by a function.
3459 VALTYPE is the data type of the value (as a tree).
3460 If the precise function being called is known, FUNC is its FUNCTION_DECL;
3461 otherwise, FUNC is 0. */
3463 ix86_function_value (tree valtype, tree fntype_or_decl,
3464 bool outgoing ATTRIBUTE_UNUSED)
3466 enum machine_mode natmode = type_natural_mode (valtype);
3470 rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype,
3471 1, REGPARM_MAX, SSE_REGPARM_MAX,
3472 x86_64_int_return_registers, 0);
3473 /* For zero sized structures, construct_container return NULL, but we
3474 need to keep rest of compiler happy by returning meaningful value. */
3476 ret = gen_rtx_REG (TYPE_MODE (valtype), 0);
3481 tree fn = NULL_TREE, fntype;
3483 && DECL_P (fntype_or_decl))
3484 fn = fntype_or_decl;
3485 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
3486 return gen_rtx_REG (TYPE_MODE (valtype),
3487 ix86_value_regno (natmode, fn, fntype));
3491 /* Return false iff type is returned in memory. */
3493 ix86_return_in_memory (tree type)
3495 int needed_intregs, needed_sseregs, size;
3496 enum machine_mode mode = type_natural_mode (type);
3499 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
3501 if (mode == BLKmode)
3504 size = int_size_in_bytes (type);
3506 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
3509 if (VECTOR_MODE_P (mode) || mode == TImode)
3511 /* User-created vectors small enough to fit in EAX. */
3515 /* MMX/3dNow values are returned in MM0,
3516 except when it doesn't exits. */
3518 return (TARGET_MMX ? 0 : 1);
3520 /* SSE values are returned in XMM0, except when it doesn't exist. */
3522 return (TARGET_SSE ? 0 : 1);
3533 /* When returning SSE vector types, we have a choice of either
3534 (1) being abi incompatible with a -march switch, or
3535 (2) generating an error.
3536 Given no good solution, I think the safest thing is one warning.
3537 The user won't be able to use -Werror, but....
3539 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
3540 called in response to actually generating a caller or callee that
3541 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
3542 via aggregate_value_p for general type probing from tree-ssa. */
3545 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
3547 static bool warnedsse, warnedmmx;
3551 /* Look at the return type of the function, not the function type. */
3552 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
3554 if (!TARGET_SSE && !warnedsse)
3557 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3560 warning (0, "SSE vector return without SSE enabled "
3565 if (!TARGET_MMX && !warnedmmx)
3567 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
3570 warning (0, "MMX vector return without MMX enabled "
3579 /* Define how to find the value returned by a library function
3580 assuming the value has mode MODE. */
3582 ix86_libcall_value (enum machine_mode mode)
3593 return gen_rtx_REG (mode, FIRST_SSE_REG);
3596 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
3600 return gen_rtx_REG (mode, 0);
3604 return gen_rtx_REG (mode, ix86_value_regno (mode, NULL, NULL));
3607 /* Given a mode, return the register to use for a return value. */
3610 ix86_value_regno (enum machine_mode mode, tree func, tree fntype)
3612 gcc_assert (!TARGET_64BIT);
3614 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
3615 we prevent this case when mmx is not available. */
3616 if ((VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8))
3617 return FIRST_MMX_REG;
3619 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
3620 we prevent this case when sse is not available. */
3621 if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3622 return FIRST_SSE_REG;
3624 /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */
3625 if (!SCALAR_FLOAT_MODE_P (mode) || !TARGET_FLOAT_RETURNS_IN_80387)
3628 /* Floating point return values in %st(0), except for local functions when
3629 SSE math is enabled or for functions with sseregparm attribute. */
3630 if ((func || fntype)
3631 && (mode == SFmode || mode == DFmode))
3633 int sse_level = ix86_function_sseregparm (fntype, func);
3634 if ((sse_level >= 1 && mode == SFmode)
3635 || (sse_level == 2 && mode == DFmode))
3636 return FIRST_SSE_REG;
3639 return FIRST_FLOAT_REG;
3642 /* Create the va_list data type. */
3645 ix86_build_builtin_va_list (void)
3647 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
3649 /* For i386 we use plain pointer to argument area. */
3651 return build_pointer_type (char_type_node);
3653 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3654 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
3656 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
3657 unsigned_type_node);
3658 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
3659 unsigned_type_node);
3660 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
3662 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
3665 va_list_gpr_counter_field = f_gpr;
3666 va_list_fpr_counter_field = f_fpr;
3668 DECL_FIELD_CONTEXT (f_gpr) = record;
3669 DECL_FIELD_CONTEXT (f_fpr) = record;
3670 DECL_FIELD_CONTEXT (f_ovf) = record;
3671 DECL_FIELD_CONTEXT (f_sav) = record;
3673 TREE_CHAIN (record) = type_decl;
3674 TYPE_NAME (record) = type_decl;
3675 TYPE_FIELDS (record) = f_gpr;
3676 TREE_CHAIN (f_gpr) = f_fpr;
3677 TREE_CHAIN (f_fpr) = f_ovf;
3678 TREE_CHAIN (f_ovf) = f_sav;
3680 layout_type (record);
3682 /* The correct type is an array type of one element. */
3683 return build_array_type (record, build_index_type (size_zero_node));
3686 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3689 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3690 tree type, int *pretend_size ATTRIBUTE_UNUSED,
3693 CUMULATIVE_ARGS next_cum;
3694 rtx save_area = NULL_RTX, mem;
3707 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
3710 /* Indicate to allocate space on the stack for varargs save area. */
3711 ix86_save_varrargs_registers = 1;
3713 cfun->stack_alignment_needed = 128;
3715 fntype = TREE_TYPE (current_function_decl);
3716 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
3717 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3718 != void_type_node));
3720 /* For varargs, we do not want to skip the dummy va_dcl argument.
3721 For stdargs, we do want to skip the last named argument. */
3724 function_arg_advance (&next_cum, mode, type, 1);
3727 save_area = frame_pointer_rtx;
3729 set = get_varargs_alias_set ();
3731 for (i = next_cum.regno;
3733 && i < next_cum.regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
3736 mem = gen_rtx_MEM (Pmode,
3737 plus_constant (save_area, i * UNITS_PER_WORD));
3738 MEM_NOTRAP_P (mem) = 1;
3739 set_mem_alias_set (mem, set);
3740 emit_move_insn (mem, gen_rtx_REG (Pmode,
3741 x86_64_int_parameter_registers[i]));
3744 if (next_cum.sse_nregs && cfun->va_list_fpr_size)
3746 /* Now emit code to save SSE registers. The AX parameter contains number
3747 of SSE parameter registers used to call this function. We use
3748 sse_prologue_save insn template that produces computed jump across
3749 SSE saves. We need some preparation work to get this working. */
3751 label = gen_label_rtx ();
3752 label_ref = gen_rtx_LABEL_REF (Pmode, label);
3754 /* Compute address to jump to :
3755 label - 5*eax + nnamed_sse_arguments*5 */
3756 tmp_reg = gen_reg_rtx (Pmode);
3757 nsse_reg = gen_reg_rtx (Pmode);
3758 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
3759 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
3760 gen_rtx_MULT (Pmode, nsse_reg,
3762 if (next_cum.sse_regno)
3765 gen_rtx_CONST (DImode,
3766 gen_rtx_PLUS (DImode,
3768 GEN_INT (next_cum.sse_regno * 4))));
3770 emit_move_insn (nsse_reg, label_ref);
3771 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
3773 /* Compute address of memory block we save into. We always use pointer
3774 pointing 127 bytes after first byte to store - this is needed to keep
3775 instruction size limited by 4 bytes. */
3776 tmp_reg = gen_reg_rtx (Pmode);
3777 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
3778 plus_constant (save_area,
3779 8 * REGPARM_MAX + 127)));
3780 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
3781 MEM_NOTRAP_P (mem) = 1;
3782 set_mem_alias_set (mem, set);
3783 set_mem_align (mem, BITS_PER_WORD);
3785 /* And finally do the dirty job! */
3786 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
3787 GEN_INT (next_cum.sse_regno), label));
3792 /* Implement va_start. */
3795 ix86_va_start (tree valist, rtx nextarg)
3797 HOST_WIDE_INT words, n_gpr, n_fpr;
3798 tree f_gpr, f_fpr, f_ovf, f_sav;
3799 tree gpr, fpr, ovf, sav, t;
3801 /* Only 64bit target needs something special. */
3804 std_expand_builtin_va_start (valist, nextarg);
3808 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3809 f_fpr = TREE_CHAIN (f_gpr);
3810 f_ovf = TREE_CHAIN (f_fpr);
3811 f_sav = TREE_CHAIN (f_ovf);
3813 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
3814 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
3815 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
3816 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
3817 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
3819 /* Count number of gp and fp argument registers used. */
3820 words = current_function_args_info.words;
3821 n_gpr = current_function_args_info.regno;
3822 n_fpr = current_function_args_info.sse_regno;
3824 if (TARGET_DEBUG_ARG)
3825 fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
3826 (int) words, (int) n_gpr, (int) n_fpr);
3828 if (cfun->va_list_gpr_size)
3830 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
3831 build_int_cst (NULL_TREE, n_gpr * 8));
3832 TREE_SIDE_EFFECTS (t) = 1;
3833 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3836 if (cfun->va_list_fpr_size)
3838 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
3839 build_int_cst (NULL_TREE, n_fpr * 16 + 8*REGPARM_MAX));
3840 TREE_SIDE_EFFECTS (t) = 1;
3841 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3844 /* Find the overflow area. */
3845 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
3847 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
3848 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
3849 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
3850 TREE_SIDE_EFFECTS (t) = 1;
3851 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3853 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
3855 /* Find the register save area.
3856 Prologue of the function save it right above stack frame. */
3857 t = make_tree (TREE_TYPE (sav), frame_pointer_rtx);
3858 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
3859 TREE_SIDE_EFFECTS (t) = 1;
3860 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3864 /* Implement va_arg. */
3867 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
3869 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
3870 tree f_gpr, f_fpr, f_ovf, f_sav;
3871 tree gpr, fpr, ovf, sav, t;
3873 tree lab_false, lab_over = NULL_TREE;
3878 enum machine_mode nat_mode;
3880 /* Only 64bit target needs something special. */
3882 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
3884 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3885 f_fpr = TREE_CHAIN (f_gpr);
3886 f_ovf = TREE_CHAIN (f_fpr);
3887 f_sav = TREE_CHAIN (f_ovf);
3889 valist = build_va_arg_indirect_ref (valist);
3890 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
3891 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
3892 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
3893 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
3895 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
3897 type = build_pointer_type (type);
3898 size = int_size_in_bytes (type);
3899 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3901 nat_mode = type_natural_mode (type);
3902 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
3903 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
3905 /* Pull the value out of the saved registers. */
3907 addr = create_tmp_var (ptr_type_node, "addr");
3908 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
3912 int needed_intregs, needed_sseregs;
3914 tree int_addr, sse_addr;
3916 lab_false = create_artificial_label ();
3917 lab_over = create_artificial_label ();
3919 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
3921 need_temp = (!REG_P (container)
3922 && ((needed_intregs && TYPE_ALIGN (type) > 64)
3923 || TYPE_ALIGN (type) > 128));
3925 /* In case we are passing structure, verify that it is consecutive block
3926 on the register save area. If not we need to do moves. */
3927 if (!need_temp && !REG_P (container))
3929 /* Verify that all registers are strictly consecutive */
3930 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
3934 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
3936 rtx slot = XVECEXP (container, 0, i);
3937 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
3938 || INTVAL (XEXP (slot, 1)) != i * 16)
3946 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
3948 rtx slot = XVECEXP (container, 0, i);
3949 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
3950 || INTVAL (XEXP (slot, 1)) != i * 8)
3962 int_addr = create_tmp_var (ptr_type_node, "int_addr");
3963 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
3964 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
3965 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
3968 /* First ensure that we fit completely in registers. */
3971 t = build_int_cst (TREE_TYPE (gpr),
3972 (REGPARM_MAX - needed_intregs + 1) * 8);
3973 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
3974 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
3975 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
3976 gimplify_and_add (t, pre_p);
3980 t = build_int_cst (TREE_TYPE (fpr),
3981 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
3983 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
3984 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
3985 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
3986 gimplify_and_add (t, pre_p);
3989 /* Compute index to start of area used for integer regs. */
3992 /* int_addr = gpr + sav; */
3993 t = fold_convert (ptr_type_node, gpr);
3994 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
3995 t = build2 (MODIFY_EXPR, void_type_node, int_addr, t);
3996 gimplify_and_add (t, pre_p);
4000 /* sse_addr = fpr + sav; */
4001 t = fold_convert (ptr_type_node, fpr);
4002 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4003 t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t);
4004 gimplify_and_add (t, pre_p);
4009 tree temp = create_tmp_var (type, "va_arg_tmp");
4012 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
4013 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
4014 gimplify_and_add (t, pre_p);
4016 for (i = 0; i < XVECLEN (container, 0); i++)
4018 rtx slot = XVECEXP (container, 0, i);
4019 rtx reg = XEXP (slot, 0);
4020 enum machine_mode mode = GET_MODE (reg);
4021 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
4022 tree addr_type = build_pointer_type (piece_type);
4025 tree dest_addr, dest;
4027 if (SSE_REGNO_P (REGNO (reg)))
4029 src_addr = sse_addr;
4030 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
4034 src_addr = int_addr;
4035 src_offset = REGNO (reg) * 8;
4037 src_addr = fold_convert (addr_type, src_addr);
4038 src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr,
4039 size_int (src_offset)));
4040 src = build_va_arg_indirect_ref (src_addr);
4042 dest_addr = fold_convert (addr_type, addr);
4043 dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
4044 size_int (INTVAL (XEXP (slot, 1)))));
4045 dest = build_va_arg_indirect_ref (dest_addr);
4047 t = build2 (MODIFY_EXPR, void_type_node, dest, src);
4048 gimplify_and_add (t, pre_p);
4054 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4055 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
4056 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4057 gimplify_and_add (t, pre_p);
4061 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
4062 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
4063 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
4064 gimplify_and_add (t, pre_p);
4067 t = build1 (GOTO_EXPR, void_type_node, lab_over);
4068 gimplify_and_add (t, pre_p);
4070 t = build1 (LABEL_EXPR, void_type_node, lab_false);
4071 append_to_statement_list (t, pre_p);
4074 /* ... otherwise out of the overflow area. */
4076 /* Care for on-stack alignment if needed. */
4077 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64)
4081 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
4082 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), ovf,
4083 build_int_cst (TREE_TYPE (ovf), align - 1));
4084 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4085 build_int_cst (TREE_TYPE (t), -align));
4087 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
4089 t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
4090 gimplify_and_add (t2, pre_p);
4092 t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
4093 build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
4094 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4095 gimplify_and_add (t, pre_p);
4099 t = build1 (LABEL_EXPR, void_type_node, lab_over);
4100 append_to_statement_list (t, pre_p);
4103 ptrtype = build_pointer_type (type);
4104 addr = fold_convert (ptrtype, addr);
4107 addr = build_va_arg_indirect_ref (addr);
4108 return build_va_arg_indirect_ref (addr);
4111 /* Return nonzero if OPNUM's MEM should be matched
4112 in movabs* patterns. */
4115 ix86_check_movabs (rtx insn, int opnum)
4119 set = PATTERN (insn);
4120 if (GET_CODE (set) == PARALLEL)
4121 set = XVECEXP (set, 0, 0);
4122 gcc_assert (GET_CODE (set) == SET);
4123 mem = XEXP (set, opnum);
4124 while (GET_CODE (mem) == SUBREG)
4125 mem = SUBREG_REG (mem);
4126 gcc_assert (GET_CODE (mem) == MEM);
4127 return (volatile_ok || !MEM_VOLATILE_P (mem));
4130 /* Initialize the table of extra 80387 mathematical constants. */
4133 init_ext_80387_constants (void)
4135 static const char * cst[5] =
4137 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
4138 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
4139 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
4140 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
4141 "3.1415926535897932385128089594061862044", /* 4: fldpi */
4145 for (i = 0; i < 5; i++)
4147 real_from_string (&ext_80387_constants_table[i], cst[i]);
4148 /* Ensure each constant is rounded to XFmode precision. */
4149 real_convert (&ext_80387_constants_table[i],
4150 XFmode, &ext_80387_constants_table[i]);
4153 ext_80387_constants_init = 1;
4156 /* Return true if the constant is something that can be loaded with
4157 a special instruction. */
4160 standard_80387_constant_p (rtx x)
4162 if (GET_CODE (x) != CONST_DOUBLE || !FLOAT_MODE_P (GET_MODE (x)))
4165 if (x == CONST0_RTX (GET_MODE (x)))
4167 if (x == CONST1_RTX (GET_MODE (x)))
4170 /* For XFmode constants, try to find a special 80387 instruction when
4171 optimizing for size or on those CPUs that benefit from them. */
4172 if (GET_MODE (x) == XFmode
4173 && (optimize_size || x86_ext_80387_constants & TUNEMASK))
4178 if (! ext_80387_constants_init)
4179 init_ext_80387_constants ();
4181 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4182 for (i = 0; i < 5; i++)
4183 if (real_identical (&r, &ext_80387_constants_table[i]))
4190 /* Return the opcode of the special instruction to be used to load
4194 standard_80387_constant_opcode (rtx x)
4196 switch (standard_80387_constant_p (x))
4217 /* Return the CONST_DOUBLE representing the 80387 constant that is
4218 loaded by the specified special instruction. The argument IDX
4219 matches the return value from standard_80387_constant_p. */
4222 standard_80387_constant_rtx (int idx)
4226 if (! ext_80387_constants_init)
4227 init_ext_80387_constants ();
4243 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
4247 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
4250 standard_sse_constant_p (rtx x)
4252 if (x == const0_rtx)
4254 return (x == CONST0_RTX (GET_MODE (x)));
4257 /* Returns 1 if OP contains a symbol reference */
4260 symbolic_reference_mentioned_p (rtx op)
4265 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
4268 fmt = GET_RTX_FORMAT (GET_CODE (op));
4269 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
4275 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
4276 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
4280 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
4287 /* Return 1 if it is appropriate to emit `ret' instructions in the
4288 body of a function. Do this only if the epilogue is simple, needing a
4289 couple of insns. Prior to reloading, we can't tell how many registers
4290 must be saved, so return 0 then. Return 0 if there is no frame
4291 marker to de-allocate. */
4294 ix86_can_use_return_insn_p (void)
4296 struct ix86_frame frame;
4298 if (! reload_completed || frame_pointer_needed)
4301 /* Don't allow more than 32 pop, since that's all we can do
4302 with one instruction. */
4303 if (current_function_pops_args
4304 && current_function_args_size >= 32768)
4307 ix86_compute_frame_layout (&frame);
4308 return frame.to_allocate == 0 && frame.nregs == 0;
4311 /* Value should be nonzero if functions must have frame pointers.
4312 Zero means the frame pointer need not be set up (and parms may
4313 be accessed via the stack pointer) in functions that seem suitable. */
4316 ix86_frame_pointer_required (void)
4318 /* If we accessed previous frames, then the generated code expects
4319 to be able to access the saved ebp value in our frame. */
4320 if (cfun->machine->accesses_prev_frame)
4323 /* Several x86 os'es need a frame pointer for other reasons,
4324 usually pertaining to setjmp. */
4325 if (SUBTARGET_FRAME_POINTER_REQUIRED)
4328 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
4329 the frame pointer by default. Turn it back on now if we've not
4330 got a leaf function. */
4331 if (TARGET_OMIT_LEAF_FRAME_POINTER
4332 && (!current_function_is_leaf))
4335 if (current_function_profile)
4341 /* Record that the current function accesses previous call frames. */
4344 ix86_setup_frame_addresses (void)
4346 cfun->machine->accesses_prev_frame = 1;
4349 #if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
4350 # define USE_HIDDEN_LINKONCE 1
4352 # define USE_HIDDEN_LINKONCE 0
4355 static int pic_labels_used;
4357 /* Fills in the label name that should be used for a pc thunk for
4358 the given register. */
4361 get_pc_thunk_name (char name[32], unsigned int regno)
4363 if (USE_HIDDEN_LINKONCE)
4364 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
4366 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
4370 /* This function generates code for -fpic that loads %ebx with
4371 the return address of the caller and then returns. */
4374 ix86_file_end (void)
4379 for (regno = 0; regno < 8; ++regno)
4383 if (! ((pic_labels_used >> regno) & 1))
4386 get_pc_thunk_name (name, regno);
4388 if (USE_HIDDEN_LINKONCE)
4392 decl = build_decl (FUNCTION_DECL, get_identifier (name),
4394 TREE_PUBLIC (decl) = 1;
4395 TREE_STATIC (decl) = 1;
4396 DECL_ONE_ONLY (decl) = 1;
4398 (*targetm.asm_out.unique_section) (decl, 0);
4399 switch_to_section (get_named_section (decl, NULL, 0));
4401 (*targetm.asm_out.globalize_label) (asm_out_file, name);
4402 fputs ("\t.hidden\t", asm_out_file);
4403 assemble_name (asm_out_file, name);
4404 fputc ('\n', asm_out_file);
4405 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
4409 switch_to_section (text_section);
4410 ASM_OUTPUT_LABEL (asm_out_file, name);
4413 xops[0] = gen_rtx_REG (SImode, regno);
4414 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
4415 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
4416 output_asm_insn ("ret", xops);
4419 if (NEED_INDICATE_EXEC_STACK)
4420 file_end_indicate_exec_stack ();
4423 /* Emit code for the SET_GOT patterns. */
4426 output_set_got (rtx dest)
4431 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
4433 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
4435 xops[2] = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
4438 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
4440 output_asm_insn ("call\t%a2", xops);
4443 /* Output the "canonical" label name ("Lxx$pb") here too. This
4444 is what will be referred to by the Mach-O PIC subsystem. */
4445 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
4447 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4448 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
4451 output_asm_insn ("pop{l}\t%0", xops);
4456 get_pc_thunk_name (name, REGNO (dest));
4457 pic_labels_used |= 1 << REGNO (dest);
4459 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4460 xops[2] = gen_rtx_MEM (QImode, xops[2]);
4461 output_asm_insn ("call\t%X2", xops);
4464 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
4465 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
4466 else if (!TARGET_MACHO)
4467 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
4472 /* Generate an "push" pattern for input ARG. */
4477 return gen_rtx_SET (VOIDmode,
4479 gen_rtx_PRE_DEC (Pmode,
4480 stack_pointer_rtx)),
4484 /* Return >= 0 if there is an unused call-clobbered register available
4485 for the entire function. */
4488 ix86_select_alt_pic_regnum (void)
4490 if (current_function_is_leaf && !current_function_profile)
4493 for (i = 2; i >= 0; --i)
4494 if (!regs_ever_live[i])
4498 return INVALID_REGNUM;
4501 /* Return 1 if we need to save REGNO. */
4503 ix86_save_reg (unsigned int regno, int maybe_eh_return)
4505 if (pic_offset_table_rtx
4506 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
4507 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4508 || current_function_profile
4509 || current_function_calls_eh_return
4510 || current_function_uses_const_pool))
4512 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
4517 if (current_function_calls_eh_return && maybe_eh_return)
4522 unsigned test = EH_RETURN_DATA_REGNO (i);
4523 if (test == INVALID_REGNUM)
4530 if (cfun->machine->force_align_arg_pointer
4531 && regno == REGNO (cfun->machine->force_align_arg_pointer))
4534 return (regs_ever_live[regno]
4535 && !call_used_regs[regno]
4536 && !fixed_regs[regno]
4537 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
4540 /* Return number of registers to be saved on the stack. */
4543 ix86_nsaved_regs (void)
4548 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
4549 if (ix86_save_reg (regno, true))
4554 /* Return the offset between two registers, one to be eliminated, and the other
4555 its replacement, at the start of a routine. */
4558 ix86_initial_elimination_offset (int from, int to)
4560 struct ix86_frame frame;
4561 ix86_compute_frame_layout (&frame);
4563 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
4564 return frame.hard_frame_pointer_offset;
4565 else if (from == FRAME_POINTER_REGNUM
4566 && to == HARD_FRAME_POINTER_REGNUM)
4567 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
4570 gcc_assert (to == STACK_POINTER_REGNUM);
4572 if (from == ARG_POINTER_REGNUM)
4573 return frame.stack_pointer_offset;
4575 gcc_assert (from == FRAME_POINTER_REGNUM);
4576 return frame.stack_pointer_offset - frame.frame_pointer_offset;
4580 /* Fill structure ix86_frame about frame of currently computed function. */
4583 ix86_compute_frame_layout (struct ix86_frame *frame)
4585 HOST_WIDE_INT total_size;
4586 unsigned int stack_alignment_needed;
4587 HOST_WIDE_INT offset;
4588 unsigned int preferred_alignment;
4589 HOST_WIDE_INT size = get_frame_size ();
4591 frame->nregs = ix86_nsaved_regs ();
4594 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
4595 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
4597 /* During reload iteration the amount of registers saved can change.
4598 Recompute the value as needed. Do not recompute when amount of registers
4599 didn't change as reload does multiple calls to the function and does not
4600 expect the decision to change within single iteration. */
4602 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
4604 int count = frame->nregs;
4606 cfun->machine->use_fast_prologue_epilogue_nregs = count;
4607 /* The fast prologue uses move instead of push to save registers. This
4608 is significantly longer, but also executes faster as modern hardware
4609 can execute the moves in parallel, but can't do that for push/pop.
4611 Be careful about choosing what prologue to emit: When function takes
4612 many instructions to execute we may use slow version as well as in
4613 case function is known to be outside hot spot (this is known with
4614 feedback only). Weight the size of function by number of registers
4615 to save as it is cheap to use one or two push instructions but very
4616 slow to use many of them. */
4618 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
4619 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
4620 || (flag_branch_probabilities
4621 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
4622 cfun->machine->use_fast_prologue_epilogue = false;
4624 cfun->machine->use_fast_prologue_epilogue
4625 = !expensive_function_p (count);
4627 if (TARGET_PROLOGUE_USING_MOVE
4628 && cfun->machine->use_fast_prologue_epilogue)
4629 frame->save_regs_using_mov = true;
4631 frame->save_regs_using_mov = false;
4634 /* Skip return address and saved base pointer. */
4635 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
4637 frame->hard_frame_pointer_offset = offset;
4639 /* Do some sanity checking of stack_alignment_needed and
4640 preferred_alignment, since i386 port is the only using those features
4641 that may break easily. */
4643 gcc_assert (!size || stack_alignment_needed);
4644 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
4645 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4646 gcc_assert (stack_alignment_needed
4647 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4649 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
4650 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
4652 /* Register save area */
4653 offset += frame->nregs * UNITS_PER_WORD;
4656 if (ix86_save_varrargs_registers)
4658 offset += X86_64_VARARGS_SIZE;
4659 frame->va_arg_size = X86_64_VARARGS_SIZE;
4662 frame->va_arg_size = 0;
4664 /* Align start of frame for local function. */
4665 frame->padding1 = ((offset + stack_alignment_needed - 1)
4666 & -stack_alignment_needed) - offset;
4668 offset += frame->padding1;
4670 /* Frame pointer points here. */
4671 frame->frame_pointer_offset = offset;
4675 /* Add outgoing arguments area. Can be skipped if we eliminated
4676 all the function calls as dead code.
4677 Skipping is however impossible when function calls alloca. Alloca
4678 expander assumes that last current_function_outgoing_args_size
4679 of stack frame are unused. */
4680 if (ACCUMULATE_OUTGOING_ARGS
4681 && (!current_function_is_leaf || current_function_calls_alloca))
4683 offset += current_function_outgoing_args_size;
4684 frame->outgoing_arguments_size = current_function_outgoing_args_size;
4687 frame->outgoing_arguments_size = 0;
4689 /* Align stack boundary. Only needed if we're calling another function
4691 if (!current_function_is_leaf || current_function_calls_alloca)
4692 frame->padding2 = ((offset + preferred_alignment - 1)
4693 & -preferred_alignment) - offset;
4695 frame->padding2 = 0;
4697 offset += frame->padding2;
4699 /* We've reached end of stack frame. */
4700 frame->stack_pointer_offset = offset;
4702 /* Size prologue needs to allocate. */
4703 frame->to_allocate =
4704 (size + frame->padding1 + frame->padding2
4705 + frame->outgoing_arguments_size + frame->va_arg_size);
4707 if ((!frame->to_allocate && frame->nregs <= 1)
4708 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
4709 frame->save_regs_using_mov = false;
4711 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
4712 && current_function_is_leaf)
4714 frame->red_zone_size = frame->to_allocate;
4715 if (frame->save_regs_using_mov)
4716 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
4717 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
4718 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
4721 frame->red_zone_size = 0;
4722 frame->to_allocate -= frame->red_zone_size;
4723 frame->stack_pointer_offset -= frame->red_zone_size;
4725 fprintf (stderr, "nregs: %i\n", frame->nregs);
4726 fprintf (stderr, "size: %i\n", size);
4727 fprintf (stderr, "alignment1: %i\n", stack_alignment_needed);
4728 fprintf (stderr, "padding1: %i\n", frame->padding1);
4729 fprintf (stderr, "va_arg: %i\n", frame->va_arg_size);
4730 fprintf (stderr, "padding2: %i\n", frame->padding2);
4731 fprintf (stderr, "to_allocate: %i\n", frame->to_allocate);
4732 fprintf (stderr, "red_zone_size: %i\n", frame->red_zone_size);
4733 fprintf (stderr, "frame_pointer_offset: %i\n", frame->frame_pointer_offset);
4734 fprintf (stderr, "hard_frame_pointer_offset: %i\n",
4735 frame->hard_frame_pointer_offset);
4736 fprintf (stderr, "stack_pointer_offset: %i\n", frame->stack_pointer_offset);
4740 /* Emit code to save registers in the prologue. */
4743 ix86_emit_save_regs (void)
4748 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
4749 if (ix86_save_reg (regno, true))
4751 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
4752 RTX_FRAME_RELATED_P (insn) = 1;
4756 /* Emit code to save registers using MOV insns. First register
4757 is restored from POINTER + OFFSET. */
4759 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
4764 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4765 if (ix86_save_reg (regno, true))
4767 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
4769 gen_rtx_REG (Pmode, regno));
4770 RTX_FRAME_RELATED_P (insn) = 1;
4771 offset += UNITS_PER_WORD;
4775 /* Expand prologue or epilogue stack adjustment.
4776 The pattern exist to put a dependency on all ebp-based memory accesses.
4777 STYLE should be negative if instructions should be marked as frame related,
4778 zero if %r11 register is live and cannot be freely used and positive
4782 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
4787 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
4788 else if (x86_64_immediate_operand (offset, DImode))
4789 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
4793 /* r11 is used by indirect sibcall return as well, set before the
4794 epilogue and used after the epilogue. ATM indirect sibcall
4795 shouldn't be used together with huge frame sizes in one
4796 function because of the frame_size check in sibcall.c. */
4798 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
4799 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
4801 RTX_FRAME_RELATED_P (insn) = 1;
4802 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
4806 RTX_FRAME_RELATED_P (insn) = 1;
4809 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
4812 ix86_internal_arg_pointer (void)
4814 if (FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
4815 && DECL_NAME (current_function_decl)
4816 && MAIN_NAME_P (DECL_NAME (current_function_decl))
4817 && DECL_FILE_SCOPE_P (current_function_decl))
4819 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, 2);
4820 return copy_to_reg (cfun->machine->force_align_arg_pointer);
4823 return virtual_incoming_args_rtx;
4826 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
4827 This is called from dwarf2out.c to emit call frame instructions
4828 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
4830 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
4832 rtx unspec = SET_SRC (pattern);
4833 gcc_assert (GET_CODE (unspec) == UNSPEC);
4837 case UNSPEC_REG_SAVE:
4838 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
4839 SET_DEST (pattern));
4841 case UNSPEC_DEF_CFA:
4842 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
4843 INTVAL (XVECEXP (unspec, 0, 0)));
4850 /* Expand the prologue into a bunch of separate insns. */
4853 ix86_expand_prologue (void)
4857 struct ix86_frame frame;
4858 HOST_WIDE_INT allocate;
4860 ix86_compute_frame_layout (&frame);
4862 if (cfun->machine->force_align_arg_pointer)
4866 /* Grab the argument pointer. */
4867 x = plus_constant (stack_pointer_rtx, 4);
4868 y = cfun->machine->force_align_arg_pointer;
4869 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
4870 RTX_FRAME_RELATED_P (insn) = 1;
4872 /* The unwind info consists of two parts: install the fafp as the cfa,
4873 and record the fafp as the "save register" of the stack pointer.
4874 The later is there in order that the unwinder can see where it
4875 should restore the stack pointer across the and insn. */
4876 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
4877 x = gen_rtx_SET (VOIDmode, y, x);
4878 RTX_FRAME_RELATED_P (x) = 1;
4879 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
4881 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
4882 RTX_FRAME_RELATED_P (y) = 1;
4883 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
4884 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
4885 REG_NOTES (insn) = x;
4887 /* Align the stack. */
4888 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
4891 /* And here we cheat like madmen with the unwind info. We force the
4892 cfa register back to sp+4, which is exactly what it was at the
4893 start of the function. Re-pushing the return address results in
4894 the return at the same spot relative to the cfa, and thus is
4895 correct wrt the unwind info. */
4896 x = cfun->machine->force_align_arg_pointer;
4897 x = gen_frame_mem (Pmode, plus_constant (x, -4));
4898 insn = emit_insn (gen_push (x));
4899 RTX_FRAME_RELATED_P (insn) = 1;
4902 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
4903 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
4904 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
4905 REG_NOTES (insn) = x;
4908 /* Note: AT&T enter does NOT have reversed args. Enter is probably
4909 slower on all targets. Also sdb doesn't like it. */
4911 if (frame_pointer_needed)
4913 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
4914 RTX_FRAME_RELATED_P (insn) = 1;
4916 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
4917 RTX_FRAME_RELATED_P (insn) = 1;
4920 allocate = frame.to_allocate;
4922 if (!frame.save_regs_using_mov)
4923 ix86_emit_save_regs ();
4925 allocate += frame.nregs * UNITS_PER_WORD;
4927 /* When using red zone we may start register saving before allocating
4928 the stack frame saving one cycle of the prologue. */
4929 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
4930 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
4931 : stack_pointer_rtx,
4932 -frame.nregs * UNITS_PER_WORD);
4936 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
4937 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
4938 GEN_INT (-allocate), -1);
4941 /* Only valid for Win32. */
4942 rtx eax = gen_rtx_REG (SImode, 0);
4943 bool eax_live = ix86_eax_live_at_start_p ();
4946 gcc_assert (!TARGET_64BIT);
4950 emit_insn (gen_push (eax));
4954 emit_move_insn (eax, GEN_INT (allocate));
4956 insn = emit_insn (gen_allocate_stack_worker (eax));
4957 RTX_FRAME_RELATED_P (insn) = 1;
4958 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
4959 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
4960 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4961 t, REG_NOTES (insn));
4965 if (frame_pointer_needed)
4966 t = plus_constant (hard_frame_pointer_rtx,
4969 - frame.nregs * UNITS_PER_WORD);
4971 t = plus_constant (stack_pointer_rtx, allocate);
4972 emit_move_insn (eax, gen_rtx_MEM (SImode, t));
4976 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
4978 if (!frame_pointer_needed || !frame.to_allocate)
4979 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
4981 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
4982 -frame.nregs * UNITS_PER_WORD);
4985 pic_reg_used = false;
4986 if (pic_offset_table_rtx
4987 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4988 || current_function_profile))
4990 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
4992 if (alt_pic_reg_used != INVALID_REGNUM)
4993 REGNO (pic_offset_table_rtx) = alt_pic_reg_used;
4995 pic_reg_used = true;
5001 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
5003 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
5005 /* Even with accurate pre-reload life analysis, we can wind up
5006 deleting all references to the pic register after reload.
5007 Consider if cross-jumping unifies two sides of a branch
5008 controlled by a comparison vs the only read from a global.
5009 In which case, allow the set_got to be deleted, though we're
5010 too late to do anything about the ebx save in the prologue. */
5011 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
5014 /* Prevent function calls from be scheduled before the call to mcount.
5015 In the pic_reg_used case, make sure that the got load isn't deleted. */
5016 if (current_function_profile)
5017 emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
5020 /* Emit code to restore saved registers using MOV insns. First register
5021 is restored from POINTER + OFFSET. */
5023 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
5024 int maybe_eh_return)
5027 rtx base_address = gen_rtx_MEM (Pmode, pointer);
5029 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5030 if (ix86_save_reg (regno, maybe_eh_return))
5032 /* Ensure that adjust_address won't be forced to produce pointer
5033 out of range allowed by x86-64 instruction set. */
5034 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
5038 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
5039 emit_move_insn (r11, GEN_INT (offset));
5040 emit_insn (gen_adddi3 (r11, r11, pointer));
5041 base_address = gen_rtx_MEM (Pmode, r11);
5044 emit_move_insn (gen_rtx_REG (Pmode, regno),
5045 adjust_address (base_address, Pmode, offset));
5046 offset += UNITS_PER_WORD;
5050 /* Restore function stack, frame, and registers. */
5053 ix86_expand_epilogue (int style)
5056 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
5057 struct ix86_frame frame;
5058 HOST_WIDE_INT offset;
5060 ix86_compute_frame_layout (&frame);
5062 /* Calculate start of saved registers relative to ebp. Special care
5063 must be taken for the normal return case of a function using
5064 eh_return: the eax and edx registers are marked as saved, but not
5065 restored along this path. */
5066 offset = frame.nregs;
5067 if (current_function_calls_eh_return && style != 2)
5069 offset *= -UNITS_PER_WORD;
5071 /* If we're only restoring one register and sp is not valid then
5072 using a move instruction to restore the register since it's
5073 less work than reloading sp and popping the register.
5075 The default code result in stack adjustment using add/lea instruction,
5076 while this code results in LEAVE instruction (or discrete equivalent),
5077 so it is profitable in some other cases as well. Especially when there
5078 are no registers to restore. We also use this code when TARGET_USE_LEAVE
5079 and there is exactly one register to pop. This heuristic may need some
5080 tuning in future. */
5081 if ((!sp_valid && frame.nregs <= 1)
5082 || (TARGET_EPILOGUE_USING_MOVE
5083 && cfun->machine->use_fast_prologue_epilogue
5084 && (frame.nregs > 1 || frame.to_allocate))
5085 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
5086 || (frame_pointer_needed && TARGET_USE_LEAVE
5087 && cfun->machine->use_fast_prologue_epilogue
5088 && frame.nregs == 1)
5089 || current_function_calls_eh_return)
5091 /* Restore registers. We can use ebp or esp to address the memory
5092 locations. If both are available, default to ebp, since offsets
5093 are known to be small. Only exception is esp pointing directly to the
5094 end of block of saved registers, where we may simplify addressing
5097 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
5098 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
5099 frame.to_allocate, style == 2);
5101 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
5102 offset, style == 2);
5104 /* eh_return epilogues need %ecx added to the stack pointer. */
5107 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
5109 if (frame_pointer_needed)
5111 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
5112 tmp = plus_constant (tmp, UNITS_PER_WORD);
5113 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
5115 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5116 emit_move_insn (hard_frame_pointer_rtx, tmp);
5118 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
5123 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
5124 tmp = plus_constant (tmp, (frame.to_allocate
5125 + frame.nregs * UNITS_PER_WORD));
5126 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
5129 else if (!frame_pointer_needed)
5130 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5131 GEN_INT (frame.to_allocate
5132 + frame.nregs * UNITS_PER_WORD),
5134 /* If not an i386, mov & pop is faster than "leave". */
5135 else if (TARGET_USE_LEAVE || optimize_size
5136 || !cfun->machine->use_fast_prologue_epilogue)
5137 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5140 pro_epilogue_adjust_stack (stack_pointer_rtx,
5141 hard_frame_pointer_rtx,
5144 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5146 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5151 /* First step is to deallocate the stack frame so that we can
5152 pop the registers. */
5155 gcc_assert (frame_pointer_needed);
5156 pro_epilogue_adjust_stack (stack_pointer_rtx,
5157 hard_frame_pointer_rtx,
5158 GEN_INT (offset), style);
5160 else if (frame.to_allocate)
5161 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5162 GEN_INT (frame.to_allocate), style);
5164 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5165 if (ix86_save_reg (regno, false))
5168 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
5170 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
5172 if (frame_pointer_needed)
5174 /* Leave results in shorter dependency chains on CPUs that are
5175 able to grok it fast. */
5176 if (TARGET_USE_LEAVE)
5177 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5178 else if (TARGET_64BIT)
5179 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5181 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5185 if (cfun->machine->force_align_arg_pointer)
5187 emit_insn (gen_addsi3 (stack_pointer_rtx,
5188 cfun->machine->force_align_arg_pointer,
5192 /* Sibcall epilogues don't want a return instruction. */
5196 if (current_function_pops_args && current_function_args_size)
5198 rtx popc = GEN_INT (current_function_pops_args);
5200 /* i386 can only pop 64K bytes. If asked to pop more, pop
5201 return address, do explicit add, and jump indirectly to the
5204 if (current_function_pops_args >= 65536)
5206 rtx ecx = gen_rtx_REG (SImode, 2);
5208 /* There is no "pascal" calling convention in 64bit ABI. */
5209 gcc_assert (!TARGET_64BIT);
5211 emit_insn (gen_popsi1 (ecx));
5212 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
5213 emit_jump_insn (gen_return_indirect_internal (ecx));
5216 emit_jump_insn (gen_return_pop_internal (popc));
5219 emit_jump_insn (gen_return_internal ());
5222 /* Reset from the function's potential modifications. */
5225 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5226 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5228 if (pic_offset_table_rtx)
5229 REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
5232 /* Extract the parts of an RTL expression that is a valid memory address
5233 for an instruction. Return 0 if the structure of the address is
5234 grossly off. Return -1 if the address contains ASHIFT, so it is not
5235 strictly valid, but still used for computing length of lea instruction. */
5238 ix86_decompose_address (rtx addr, struct ix86_address *out)
5240 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
5241 rtx base_reg, index_reg;
5242 HOST_WIDE_INT scale = 1;
5243 rtx scale_rtx = NULL_RTX;
5245 enum ix86_address_seg seg = SEG_DEFAULT;
5247 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
5249 else if (GET_CODE (addr) == PLUS)
5259 addends[n++] = XEXP (op, 1);
5262 while (GET_CODE (op) == PLUS);
5267 for (i = n; i >= 0; --i)
5270 switch (GET_CODE (op))
5275 index = XEXP (op, 0);
5276 scale_rtx = XEXP (op, 1);
5280 if (XINT (op, 1) == UNSPEC_TP
5281 && TARGET_TLS_DIRECT_SEG_REFS
5282 && seg == SEG_DEFAULT)
5283 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
5312 else if (GET_CODE (addr) == MULT)
5314 index = XEXP (addr, 0); /* index*scale */
5315 scale_rtx = XEXP (addr, 1);
5317 else if (GET_CODE (addr) == ASHIFT)
5321 /* We're called for lea too, which implements ashift on occasion. */
5322 index = XEXP (addr, 0);
5323 tmp = XEXP (addr, 1);
5324 if (GET_CODE (tmp) != CONST_INT)
5326 scale = INTVAL (tmp);
5327 if ((unsigned HOST_WIDE_INT) scale > 3)
5333 disp = addr; /* displacement */
5335 /* Extract the integral value of scale. */
5338 if (GET_CODE (scale_rtx) != CONST_INT)
5340 scale = INTVAL (scale_rtx);
5343 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
5344 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
5346 /* Allow arg pointer and stack pointer as index if there is not scaling. */
5347 if (base_reg && index_reg && scale == 1
5348 && (index_reg == arg_pointer_rtx
5349 || index_reg == frame_pointer_rtx
5350 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
5353 tmp = base, base = index, index = tmp;
5354 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
5357 /* Special case: %ebp cannot be encoded as a base without a displacement. */
5358 if ((base_reg == hard_frame_pointer_rtx
5359 || base_reg == frame_pointer_rtx
5360 || base_reg == arg_pointer_rtx) && !disp)
5363 /* Special case: on K6, [%esi] makes the instruction vector decoded.
5364 Avoid this by transforming to [%esi+0]. */
5365 if (ix86_tune == PROCESSOR_K6 && !optimize_size
5366 && base_reg && !index_reg && !disp
5368 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
5371 /* Special case: encode reg+reg instead of reg*2. */
5372 if (!base && index && scale && scale == 2)
5373 base = index, base_reg = index_reg, scale = 1;
5375 /* Special case: scaling cannot be encoded without base or displacement. */
5376 if (!base && !disp && index && scale != 1)
5388 /* Return cost of the memory address x.
5389 For i386, it is better to use a complex address than let gcc copy
5390 the address into a reg and make a new pseudo. But not if the address
5391 requires to two regs - that would mean more pseudos with longer
5394 ix86_address_cost (rtx x)
5396 struct ix86_address parts;
5398 int ok = ix86_decompose_address (x, &parts);
5402 if (parts.base && GET_CODE (parts.base) == SUBREG)
5403 parts.base = SUBREG_REG (parts.base);
5404 if (parts.index && GET_CODE (parts.index) == SUBREG)
5405 parts.index = SUBREG_REG (parts.index);
5407 /* More complex memory references are better. */
5408 if (parts.disp && parts.disp != const0_rtx)
5410 if (parts.seg != SEG_DEFAULT)
5413 /* Attempt to minimize number of registers in the address. */
5415 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
5417 && (!REG_P (parts.index)
5418 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
5422 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
5424 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
5425 && parts.base != parts.index)
5428 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
5429 since it's predecode logic can't detect the length of instructions
5430 and it degenerates to vector decoded. Increase cost of such
5431 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
5432 to split such addresses or even refuse such addresses at all.
5434 Following addressing modes are affected:
5439 The first and last case may be avoidable by explicitly coding the zero in
5440 memory address, but I don't have AMD-K6 machine handy to check this
5444 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
5445 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
5446 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
5452 /* If X is a machine specific address (i.e. a symbol or label being
5453 referenced as a displacement from the GOT implemented using an
5454 UNSPEC), then return the base term. Otherwise return X. */
5457 ix86_find_base_term (rtx x)
5463 if (GET_CODE (x) != CONST)
5466 if (GET_CODE (term) == PLUS
5467 && (GET_CODE (XEXP (term, 1)) == CONST_INT
5468 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
5469 term = XEXP (term, 0);
5470 if (GET_CODE (term) != UNSPEC
5471 || XINT (term, 1) != UNSPEC_GOTPCREL)
5474 term = XVECEXP (term, 0, 0);
5476 if (GET_CODE (term) != SYMBOL_REF
5477 && GET_CODE (term) != LABEL_REF)
5483 term = ix86_delegitimize_address (x);
5485 if (GET_CODE (term) != SYMBOL_REF
5486 && GET_CODE (term) != LABEL_REF)
5492 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
5493 this is used for to form addresses to local data when -fPIC is in
5497 darwin_local_data_pic (rtx disp)
5499 if (GET_CODE (disp) == MINUS)
5501 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
5502 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
5503 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
5505 const char *sym_name = XSTR (XEXP (disp, 1), 0);
5506 if (! strcmp (sym_name, "<pic base>"))
5514 /* Determine if a given RTX is a valid constant. We already know this
5515 satisfies CONSTANT_P. */
5518 legitimate_constant_p (rtx x)
5520 switch (GET_CODE (x))
5525 if (GET_CODE (x) == PLUS)
5527 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5532 if (TARGET_MACHO && darwin_local_data_pic (x))
5535 /* Only some unspecs are valid as "constants". */
5536 if (GET_CODE (x) == UNSPEC)
5537 switch (XINT (x, 1))
5540 return TARGET_64BIT;
5543 x = XVECEXP (x, 0, 0);
5544 return (GET_CODE (x) == SYMBOL_REF
5545 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
5547 x = XVECEXP (x, 0, 0);
5548 return (GET_CODE (x) == SYMBOL_REF
5549 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
5554 /* We must have drilled down to a symbol. */
5555 if (GET_CODE (x) == LABEL_REF)
5557 if (GET_CODE (x) != SYMBOL_REF)
5562 /* TLS symbols are never valid. */
5563 if (SYMBOL_REF_TLS_MODEL (x))
5571 /* Otherwise we handle everything else in the move patterns. */
5575 /* Determine if it's legal to put X into the constant pool. This
5576 is not possible for the address of thread-local symbols, which
5577 is checked above. */
5580 ix86_cannot_force_const_mem (rtx x)
5582 return !legitimate_constant_p (x);
5585 /* Determine if a given RTX is a valid constant address. */
5588 constant_address_p (rtx x)
5590 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
5593 /* Nonzero if the constant value X is a legitimate general operand
5594 when generating PIC code. It is given that flag_pic is on and
5595 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
5598 legitimate_pic_operand_p (rtx x)
5602 switch (GET_CODE (x))
5605 inner = XEXP (x, 0);
5606 if (GET_CODE (inner) == PLUS
5607 && GET_CODE (XEXP (inner, 1)) == CONST_INT)
5608 inner = XEXP (inner, 0);
5610 /* Only some unspecs are valid as "constants". */
5611 if (GET_CODE (inner) == UNSPEC)
5612 switch (XINT (inner, 1))
5615 return TARGET_64BIT;
5617 x = XVECEXP (inner, 0, 0);
5618 return (GET_CODE (x) == SYMBOL_REF
5619 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
5627 return legitimate_pic_address_disp_p (x);
5634 /* Determine if a given CONST RTX is a valid memory displacement
5638 legitimate_pic_address_disp_p (rtx disp)
5642 /* In 64bit mode we can allow direct addresses of symbols and labels
5643 when they are not dynamic symbols. */
5646 rtx op0 = disp, op1;
5648 switch (GET_CODE (disp))
5654 if (GET_CODE (XEXP (disp, 0)) != PLUS)
5656 op0 = XEXP (XEXP (disp, 0), 0);
5657 op1 = XEXP (XEXP (disp, 0), 1);
5658 if (GET_CODE (op1) != CONST_INT
5659 || INTVAL (op1) >= 16*1024*1024
5660 || INTVAL (op1) < -16*1024*1024)
5662 if (GET_CODE (op0) == LABEL_REF)
5664 if (GET_CODE (op0) != SYMBOL_REF)
5669 /* TLS references should always be enclosed in UNSPEC. */
5670 if (SYMBOL_REF_TLS_MODEL (op0))
5672 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0))
5680 if (GET_CODE (disp) != CONST)
5682 disp = XEXP (disp, 0);
5686 /* We are unsafe to allow PLUS expressions. This limit allowed distance
5687 of GOT tables. We should not need these anyway. */
5688 if (GET_CODE (disp) != UNSPEC
5689 || (XINT (disp, 1) != UNSPEC_GOTPCREL
5690 && XINT (disp, 1) != UNSPEC_GOTOFF))
5693 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
5694 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
5700 if (GET_CODE (disp) == PLUS)
5702 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
5704 disp = XEXP (disp, 0);
5708 if (TARGET_MACHO && darwin_local_data_pic (disp))
5711 if (GET_CODE (disp) != UNSPEC)
5714 switch (XINT (disp, 1))
5719 return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
5721 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
5722 While ABI specify also 32bit relocation but we don't produce it in
5723 small PIC model at all. */
5724 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
5725 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
5727 return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5729 case UNSPEC_GOTTPOFF:
5730 case UNSPEC_GOTNTPOFF:
5731 case UNSPEC_INDNTPOFF:
5734 disp = XVECEXP (disp, 0, 0);
5735 return (GET_CODE (disp) == SYMBOL_REF
5736 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
5738 disp = XVECEXP (disp, 0, 0);
5739 return (GET_CODE (disp) == SYMBOL_REF
5740 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
5742 disp = XVECEXP (disp, 0, 0);
5743 return (GET_CODE (disp) == SYMBOL_REF
5744 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
5750 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
5751 memory address for an instruction. The MODE argument is the machine mode
5752 for the MEM expression that wants to use this address.
5754 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
5755 convert common non-canonical forms to canonical form so that they will
5759 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
5761 struct ix86_address parts;
5762 rtx base, index, disp;
5763 HOST_WIDE_INT scale;
5764 const char *reason = NULL;
5765 rtx reason_rtx = NULL_RTX;
5767 if (TARGET_DEBUG_ADDR)
5770 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
5771 GET_MODE_NAME (mode), strict);
5775 if (ix86_decompose_address (addr, &parts) <= 0)
5777 reason = "decomposition failed";
5782 index = parts.index;
5784 scale = parts.scale;
5786 /* Validate base register.
5788 Don't allow SUBREG's that span more than a word here. It can lead to spill
5789 failures when the base is one word out of a two word structure, which is
5790 represented internally as a DImode int. */
5799 else if (GET_CODE (base) == SUBREG
5800 && REG_P (SUBREG_REG (base))
5801 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
5803 reg = SUBREG_REG (base);
5806 reason = "base is not a register";
5810 if (GET_MODE (base) != Pmode)
5812 reason = "base is not in Pmode";
5816 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
5817 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
5819 reason = "base is not valid";
5824 /* Validate index register.
5826 Don't allow SUBREG's that span more than a word here -- same as above. */
5835 else if (GET_CODE (index) == SUBREG
5836 && REG_P (SUBREG_REG (index))
5837 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
5839 reg = SUBREG_REG (index);
5842 reason = "index is not a register";
5846 if (GET_MODE (index) != Pmode)
5848 reason = "index is not in Pmode";
5852 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
5853 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
5855 reason = "index is not valid";
5860 /* Validate scale factor. */
5863 reason_rtx = GEN_INT (scale);
5866 reason = "scale without index";
5870 if (scale != 2 && scale != 4 && scale != 8)
5872 reason = "scale is not a valid multiplier";
5877 /* Validate displacement. */
5882 if (GET_CODE (disp) == CONST
5883 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
5884 switch (XINT (XEXP (disp, 0), 1))
5886 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
5887 used. While ABI specify also 32bit relocations, we don't produce
5888 them at all and use IP relative instead. */
5891 gcc_assert (flag_pic);
5893 goto is_legitimate_pic;
5894 reason = "64bit address unspec";
5897 case UNSPEC_GOTPCREL:
5898 gcc_assert (flag_pic);
5899 goto is_legitimate_pic;
5901 case UNSPEC_GOTTPOFF:
5902 case UNSPEC_GOTNTPOFF:
5903 case UNSPEC_INDNTPOFF:
5909 reason = "invalid address unspec";
5913 else if (flag_pic && (SYMBOLIC_CONST (disp)
5915 && !machopic_operand_p (disp)
5920 if (TARGET_64BIT && (index || base))
5922 /* foo@dtpoff(%rX) is ok. */
5923 if (GET_CODE (disp) != CONST
5924 || GET_CODE (XEXP (disp, 0)) != PLUS
5925 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
5926 || GET_CODE (XEXP (XEXP (disp, 0), 1)) != CONST_INT
5927 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
5928 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
5930 reason = "non-constant pic memory reference";
5934 else if (! legitimate_pic_address_disp_p (disp))
5936 reason = "displacement is an invalid pic construct";
5940 /* This code used to verify that a symbolic pic displacement
5941 includes the pic_offset_table_rtx register.
5943 While this is good idea, unfortunately these constructs may
5944 be created by "adds using lea" optimization for incorrect
5953 This code is nonsensical, but results in addressing
5954 GOT table with pic_offset_table_rtx base. We can't
5955 just refuse it easily, since it gets matched by
5956 "addsi3" pattern, that later gets split to lea in the
5957 case output register differs from input. While this
5958 can be handled by separate addsi pattern for this case
5959 that never results in lea, this seems to be easier and
5960 correct fix for crash to disable this test. */
5962 else if (GET_CODE (disp) != LABEL_REF
5963 && GET_CODE (disp) != CONST_INT
5964 && (GET_CODE (disp) != CONST
5965 || !legitimate_constant_p (disp))
5966 && (GET_CODE (disp) != SYMBOL_REF
5967 || !legitimate_constant_p (disp)))
5969 reason = "displacement is not constant";
5972 else if (TARGET_64BIT
5973 && !x86_64_immediate_operand (disp, VOIDmode))
5975 reason = "displacement is out of range";
5980 /* Everything looks valid. */
5981 if (TARGET_DEBUG_ADDR)
5982 fprintf (stderr, "Success.\n");
5986 if (TARGET_DEBUG_ADDR)
5988 fprintf (stderr, "Error: %s\n", reason);
5989 debug_rtx (reason_rtx);
5994 /* Return a unique alias set for the GOT. */
5996 static HOST_WIDE_INT
5997 ix86_GOT_alias_set (void)
5999 static HOST_WIDE_INT set = -1;
6001 set = new_alias_set ();
6005 /* Return a legitimate reference for ORIG (an address) using the
6006 register REG. If REG is 0, a new pseudo is generated.
6008 There are two types of references that must be handled:
6010 1. Global data references must load the address from the GOT, via
6011 the PIC reg. An insn is emitted to do this load, and the reg is
6014 2. Static data references, constant pool addresses, and code labels
6015 compute the address as an offset from the GOT, whose base is in
6016 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
6017 differentiate them from global data objects. The returned
6018 address is the PIC reg + an unspec constant.
6020 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
6021 reg also appears in the address. */
6024 legitimize_pic_address (rtx orig, rtx reg)
6032 reg = gen_reg_rtx (Pmode);
6033 /* Use the generic Mach-O PIC machinery. */
6034 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
6037 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
6039 else if (TARGET_64BIT
6040 && ix86_cmodel != CM_SMALL_PIC
6041 && local_symbolic_operand (addr, Pmode))
6044 /* This symbol may be referenced via a displacement from the PIC
6045 base address (@GOTOFF). */
6047 if (reload_in_progress)
6048 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6049 if (GET_CODE (addr) == CONST)
6050 addr = XEXP (addr, 0);
6051 if (GET_CODE (addr) == PLUS)
6053 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6054 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6057 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6058 new = gen_rtx_CONST (Pmode, new);
6060 tmpreg = gen_reg_rtx (Pmode);
6063 emit_move_insn (tmpreg, new);
6067 new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
6068 tmpreg, 1, OPTAB_DIRECT);
6071 else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
6073 else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode))
6075 /* This symbol may be referenced via a displacement from the PIC
6076 base address (@GOTOFF). */
6078 if (reload_in_progress)
6079 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6080 if (GET_CODE (addr) == CONST)
6081 addr = XEXP (addr, 0);
6082 if (GET_CODE (addr) == PLUS)
6084 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6085 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6088 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6089 new = gen_rtx_CONST (Pmode, new);
6090 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6094 emit_move_insn (reg, new);
6098 else if (GET_CODE (addr) == SYMBOL_REF)
6102 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
6103 new = gen_rtx_CONST (Pmode, new);
6104 new = gen_const_mem (Pmode, new);
6105 set_mem_alias_set (new, ix86_GOT_alias_set ());
6108 reg = gen_reg_rtx (Pmode);
6109 /* Use directly gen_movsi, otherwise the address is loaded
6110 into register for CSE. We don't want to CSE this addresses,
6111 instead we CSE addresses from the GOT table, so skip this. */
6112 emit_insn (gen_movsi (reg, new));
6117 /* This symbol must be referenced via a load from the
6118 Global Offset Table (@GOT). */
6120 if (reload_in_progress)
6121 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6122 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
6123 new = gen_rtx_CONST (Pmode, new);
6124 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6125 new = gen_const_mem (Pmode, new);
6126 set_mem_alias_set (new, ix86_GOT_alias_set ());
6129 reg = gen_reg_rtx (Pmode);
6130 emit_move_insn (reg, new);
6136 if (GET_CODE (addr) == CONST_INT
6137 && !x86_64_immediate_operand (addr, VOIDmode))
6141 emit_move_insn (reg, addr);
6145 new = force_reg (Pmode, addr);
6147 else if (GET_CODE (addr) == CONST)
6149 addr = XEXP (addr, 0);
6151 /* We must match stuff we generate before. Assume the only
6152 unspecs that can get here are ours. Not that we could do
6153 anything with them anyway.... */
6154 if (GET_CODE (addr) == UNSPEC
6155 || (GET_CODE (addr) == PLUS
6156 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
6158 gcc_assert (GET_CODE (addr) == PLUS);
6160 if (GET_CODE (addr) == PLUS)
6162 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
6164 /* Check first to see if this is a constant offset from a @GOTOFF
6165 symbol reference. */
6166 if (local_symbolic_operand (op0, Pmode)
6167 && GET_CODE (op1) == CONST_INT)
6171 if (reload_in_progress)
6172 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6173 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
6175 new = gen_rtx_PLUS (Pmode, new, op1);
6176 new = gen_rtx_CONST (Pmode, new);
6177 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6181 emit_move_insn (reg, new);
6187 if (INTVAL (op1) < -16*1024*1024
6188 || INTVAL (op1) >= 16*1024*1024)
6190 if (!x86_64_immediate_operand (op1, Pmode))
6191 op1 = force_reg (Pmode, op1);
6192 new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
6198 base = legitimize_pic_address (XEXP (addr, 0), reg);
6199 new = legitimize_pic_address (XEXP (addr, 1),
6200 base == reg ? NULL_RTX : reg);
6202 if (GET_CODE (new) == CONST_INT)
6203 new = plus_constant (base, INTVAL (new));
6206 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
6208 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
6209 new = XEXP (new, 1);
6211 new = gen_rtx_PLUS (Pmode, base, new);
6219 /* Load the thread pointer. If TO_REG is true, force it into a register. */
6222 get_thread_pointer (int to_reg)
6226 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
6230 reg = gen_reg_rtx (Pmode);
6231 insn = gen_rtx_SET (VOIDmode, reg, tp);
6232 insn = emit_insn (insn);
6237 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
6238 false if we expect this to be used for a memory address and true if
6239 we expect to load the address into a register. */
6242 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
6244 rtx dest, base, off, pic;
6249 case TLS_MODEL_GLOBAL_DYNAMIC:
6250 dest = gen_reg_rtx (Pmode);
6253 rtx rax = gen_rtx_REG (Pmode, 0), insns;
6256 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
6257 insns = get_insns ();
6260 emit_libcall_block (insns, dest, rax, x);
6263 emit_insn (gen_tls_global_dynamic_32 (dest, x));
6266 case TLS_MODEL_LOCAL_DYNAMIC:
6267 base = gen_reg_rtx (Pmode);
6270 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
6273 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
6274 insns = get_insns ();
6277 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
6278 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
6279 emit_libcall_block (insns, base, rax, note);
6282 emit_insn (gen_tls_local_dynamic_base_32 (base));
6284 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
6285 off = gen_rtx_CONST (Pmode, off);
6287 return gen_rtx_PLUS (Pmode, base, off);
6289 case TLS_MODEL_INITIAL_EXEC:
6293 type = UNSPEC_GOTNTPOFF;
6297 if (reload_in_progress)
6298 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6299 pic = pic_offset_table_rtx;
6300 type = TARGET_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
6302 else if (!TARGET_GNU_TLS)
6304 pic = gen_reg_rtx (Pmode);
6305 emit_insn (gen_set_got (pic));
6306 type = UNSPEC_GOTTPOFF;
6311 type = UNSPEC_INDNTPOFF;
6314 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
6315 off = gen_rtx_CONST (Pmode, off);
6317 off = gen_rtx_PLUS (Pmode, pic, off);
6318 off = gen_const_mem (Pmode, off);
6319 set_mem_alias_set (off, ix86_GOT_alias_set ());
6321 if (TARGET_64BIT || TARGET_GNU_TLS)
6323 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6324 off = force_reg (Pmode, off);
6325 return gen_rtx_PLUS (Pmode, base, off);
6329 base = get_thread_pointer (true);
6330 dest = gen_reg_rtx (Pmode);
6331 emit_insn (gen_subsi3 (dest, base, off));
6335 case TLS_MODEL_LOCAL_EXEC:
6336 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
6337 (TARGET_64BIT || TARGET_GNU_TLS)
6338 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
6339 off = gen_rtx_CONST (Pmode, off);
6341 if (TARGET_64BIT || TARGET_GNU_TLS)
6343 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6344 return gen_rtx_PLUS (Pmode, base, off);
6348 base = get_thread_pointer (true);
6349 dest = gen_reg_rtx (Pmode);
6350 emit_insn (gen_subsi3 (dest, base, off));
6361 /* Try machine-dependent ways of modifying an illegitimate address
6362 to be legitimate. If we find one, return the new, valid address.
6363 This macro is used in only one place: `memory_address' in explow.c.
6365 OLDX is the address as it was before break_out_memory_refs was called.
6366 In some cases it is useful to look at this to decide what needs to be done.
6368 MODE and WIN are passed so that this macro can use
6369 GO_IF_LEGITIMATE_ADDRESS.
6371 It is always safe for this macro to do nothing. It exists to recognize
6372 opportunities to optimize the output.
6374 For the 80386, we handle X+REG by loading X into a register R and
6375 using R+REG. R will go in a general reg and indexing will be used.
6376 However, if REG is a broken-out memory address or multiplication,
6377 nothing needs to be done because REG can certainly go in a general reg.
6379 When -fpic is used, special handling is needed for symbolic references.
6380 See comments by legitimize_pic_address in i386.c for details. */
6383 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
6388 if (TARGET_DEBUG_ADDR)
6390 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
6391 GET_MODE_NAME (mode));
6395 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
6397 return legitimize_tls_address (x, log, false);
6398 if (GET_CODE (x) == CONST
6399 && GET_CODE (XEXP (x, 0)) == PLUS
6400 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
6401 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
6403 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
6404 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
6407 if (flag_pic && SYMBOLIC_CONST (x))
6408 return legitimize_pic_address (x, 0);
6410 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
6411 if (GET_CODE (x) == ASHIFT
6412 && GET_CODE (XEXP (x, 1)) == CONST_INT
6413 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
6416 log = INTVAL (XEXP (x, 1));
6417 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
6418 GEN_INT (1 << log));
6421 if (GET_CODE (x) == PLUS)
6423 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
6425 if (GET_CODE (XEXP (x, 0)) == ASHIFT
6426 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6427 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
6430 log = INTVAL (XEXP (XEXP (x, 0), 1));
6431 XEXP (x, 0) = gen_rtx_MULT (Pmode,
6432 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
6433 GEN_INT (1 << log));
6436 if (GET_CODE (XEXP (x, 1)) == ASHIFT
6437 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
6438 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
6441 log = INTVAL (XEXP (XEXP (x, 1), 1));
6442 XEXP (x, 1) = gen_rtx_MULT (Pmode,
6443 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
6444 GEN_INT (1 << log));
6447 /* Put multiply first if it isn't already. */
6448 if (GET_CODE (XEXP (x, 1)) == MULT)
6450 rtx tmp = XEXP (x, 0);
6451 XEXP (x, 0) = XEXP (x, 1);
6456 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
6457 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
6458 created by virtual register instantiation, register elimination, and
6459 similar optimizations. */
6460 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
6463 x = gen_rtx_PLUS (Pmode,
6464 gen_rtx_PLUS (Pmode, XEXP (x, 0),
6465 XEXP (XEXP (x, 1), 0)),
6466 XEXP (XEXP (x, 1), 1));
6470 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
6471 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
6472 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
6473 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
6474 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
6475 && CONSTANT_P (XEXP (x, 1)))
6478 rtx other = NULL_RTX;
6480 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6482 constant = XEXP (x, 1);
6483 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
6485 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
6487 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
6488 other = XEXP (x, 1);
6496 x = gen_rtx_PLUS (Pmode,
6497 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
6498 XEXP (XEXP (XEXP (x, 0), 1), 0)),
6499 plus_constant (other, INTVAL (constant)));
6503 if (changed && legitimate_address_p (mode, x, FALSE))
6506 if (GET_CODE (XEXP (x, 0)) == MULT)
6509 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
6512 if (GET_CODE (XEXP (x, 1)) == MULT)
6515 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
6519 && GET_CODE (XEXP (x, 1)) == REG
6520 && GET_CODE (XEXP (x, 0)) == REG)
6523 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
6526 x = legitimize_pic_address (x, 0);
6529 if (changed && legitimate_address_p (mode, x, FALSE))
6532 if (GET_CODE (XEXP (x, 0)) == REG)
6534 rtx temp = gen_reg_rtx (Pmode);
6535 rtx val = force_operand (XEXP (x, 1), temp);
6537 emit_move_insn (temp, val);
6543 else if (GET_CODE (XEXP (x, 1)) == REG)
6545 rtx temp = gen_reg_rtx (Pmode);
6546 rtx val = force_operand (XEXP (x, 0), temp);
6548 emit_move_insn (temp, val);
6558 /* Print an integer constant expression in assembler syntax. Addition
6559 and subtraction are the only arithmetic that may appear in these
6560 expressions. FILE is the stdio stream to write to, X is the rtx, and
6561 CODE is the operand print code from the output string. */
6564 output_pic_addr_const (FILE *file, rtx x, int code)
6568 switch (GET_CODE (x))
6571 gcc_assert (flag_pic);
6576 assemble_name (file, XSTR (x, 0));
6577 if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
6578 fputs ("@PLT", file);
6585 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
6586 assemble_name (asm_out_file, buf);
6590 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
6594 /* This used to output parentheses around the expression,
6595 but that does not work on the 386 (either ATT or BSD assembler). */
6596 output_pic_addr_const (file, XEXP (x, 0), code);
6600 if (GET_MODE (x) == VOIDmode)
6602 /* We can use %d if the number is <32 bits and positive. */
6603 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
6604 fprintf (file, "0x%lx%08lx",
6605 (unsigned long) CONST_DOUBLE_HIGH (x),
6606 (unsigned long) CONST_DOUBLE_LOW (x));
6608 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
6611 /* We can't handle floating point constants;
6612 PRINT_OPERAND must handle them. */
6613 output_operand_lossage ("floating constant misused");
6617 /* Some assemblers need integer constants to appear first. */
6618 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6620 output_pic_addr_const (file, XEXP (x, 0), code);
6622 output_pic_addr_const (file, XEXP (x, 1), code);
6626 gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
6627 output_pic_addr_const (file, XEXP (x, 1), code);
6629 output_pic_addr_const (file, XEXP (x, 0), code);
6635 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
6636 output_pic_addr_const (file, XEXP (x, 0), code);
6638 output_pic_addr_const (file, XEXP (x, 1), code);
6640 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
6644 gcc_assert (XVECLEN (x, 0) == 1);
6645 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
6646 switch (XINT (x, 1))
6649 fputs ("@GOT", file);
6652 fputs ("@GOTOFF", file);
6654 case UNSPEC_GOTPCREL:
6655 fputs ("@GOTPCREL(%rip)", file);
6657 case UNSPEC_GOTTPOFF:
6658 /* FIXME: This might be @TPOFF in Sun ld too. */
6659 fputs ("@GOTTPOFF", file);
6662 fputs ("@TPOFF", file);
6666 fputs ("@TPOFF", file);
6668 fputs ("@NTPOFF", file);
6671 fputs ("@DTPOFF", file);
6673 case UNSPEC_GOTNTPOFF:
6675 fputs ("@GOTTPOFF(%rip)", file);
6677 fputs ("@GOTNTPOFF", file);
6679 case UNSPEC_INDNTPOFF:
6680 fputs ("@INDNTPOFF", file);
6683 output_operand_lossage ("invalid UNSPEC as operand");
6689 output_operand_lossage ("invalid expression as operand");
6693 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6694 We need to emit DTP-relative relocations. */
6697 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
6699 fputs (ASM_LONG, file);
6700 output_addr_const (file, x);
6701 fputs ("@DTPOFF", file);
6707 fputs (", 0", file);
6714 /* In the name of slightly smaller debug output, and to cater to
6715 general assembler lossage, recognize PIC+GOTOFF and turn it back
6716 into a direct symbol reference. */
6719 ix86_delegitimize_address (rtx orig_x)
6723 if (GET_CODE (x) == MEM)
6728 if (GET_CODE (x) != CONST
6729 || GET_CODE (XEXP (x, 0)) != UNSPEC
6730 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
6731 || GET_CODE (orig_x) != MEM)
6733 return XVECEXP (XEXP (x, 0), 0, 0);
6736 if (GET_CODE (x) != PLUS
6737 || GET_CODE (XEXP (x, 1)) != CONST)
6740 if (GET_CODE (XEXP (x, 0)) == REG
6741 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
6742 /* %ebx + GOT/GOTOFF */
6744 else if (GET_CODE (XEXP (x, 0)) == PLUS)
6746 /* %ebx + %reg * scale + GOT/GOTOFF */
6748 if (GET_CODE (XEXP (y, 0)) == REG
6749 && REGNO (XEXP (y, 0)) == PIC_OFFSET_TABLE_REGNUM)
6751 else if (GET_CODE (XEXP (y, 1)) == REG
6752 && REGNO (XEXP (y, 1)) == PIC_OFFSET_TABLE_REGNUM)
6756 if (GET_CODE (y) != REG
6757 && GET_CODE (y) != MULT
6758 && GET_CODE (y) != ASHIFT)
6764 x = XEXP (XEXP (x, 1), 0);
6765 if (GET_CODE (x) == UNSPEC
6766 && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
6767 || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
6770 return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
6771 return XVECEXP (x, 0, 0);
6774 if (GET_CODE (x) == PLUS
6775 && GET_CODE (XEXP (x, 0)) == UNSPEC
6776 && GET_CODE (XEXP (x, 1)) == CONST_INT
6777 && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
6778 || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF
6779 && GET_CODE (orig_x) != MEM)))
6781 x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
6783 return gen_rtx_PLUS (Pmode, y, x);
6791 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
6796 if (mode == CCFPmode || mode == CCFPUmode)
6798 enum rtx_code second_code, bypass_code;
6799 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
6800 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
6801 code = ix86_fp_compare_code_to_integer (code);
6805 code = reverse_condition (code);
6816 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
6820 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
6821 Those same assemblers have the same but opposite lossage on cmov. */
6822 gcc_assert (mode == CCmode);
6823 suffix = fp ? "nbe" : "a";
6843 gcc_assert (mode == CCmode);
6865 gcc_assert (mode == CCmode);
6866 suffix = fp ? "nb" : "ae";
6869 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
6873 gcc_assert (mode == CCmode);
6877 suffix = fp ? "u" : "p";
6880 suffix = fp ? "nu" : "np";
6885 fputs (suffix, file);
6888 /* Print the name of register X to FILE based on its machine mode and number.
6889 If CODE is 'w', pretend the mode is HImode.
6890 If CODE is 'b', pretend the mode is QImode.
6891 If CODE is 'k', pretend the mode is SImode.
6892 If CODE is 'q', pretend the mode is DImode.
6893 If CODE is 'h', pretend the reg is the 'high' byte register.
6894 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
6897 print_reg (rtx x, int code, FILE *file)
6899 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
6900 && REGNO (x) != FRAME_POINTER_REGNUM
6901 && REGNO (x) != FLAGS_REG
6902 && REGNO (x) != FPSR_REG);
6904 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
6907 if (code == 'w' || MMX_REG_P (x))
6909 else if (code == 'b')
6911 else if (code == 'k')
6913 else if (code == 'q')
6915 else if (code == 'y')
6917 else if (code == 'h')
6920 code = GET_MODE_SIZE (GET_MODE (x));
6922 /* Irritatingly, AMD extended registers use different naming convention
6923 from the normal registers. */
6924 if (REX_INT_REG_P (x))
6926 gcc_assert (TARGET_64BIT);
6930 error ("extended registers have no high halves");
6933 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
6936 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
6939 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
6942 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
6945 error ("unsupported operand size for extended register");
6953 if (STACK_TOP_P (x))
6955 fputs ("st(0)", file);
6962 if (! ANY_FP_REG_P (x))
6963 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
6968 fputs (hi_reg_name[REGNO (x)], file);
6971 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
6973 fputs (qi_reg_name[REGNO (x)], file);
6976 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
6978 fputs (qi_high_reg_name[REGNO (x)], file);
6985 /* Locate some local-dynamic symbol still in use by this function
6986 so that we can print its name in some tls_local_dynamic_base
6990 get_some_local_dynamic_name (void)
6994 if (cfun->machine->some_ld_name)
6995 return cfun->machine->some_ld_name;
6997 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
6999 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
7000 return cfun->machine->some_ld_name;
7006 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
7010 if (GET_CODE (x) == SYMBOL_REF
7011 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
7013 cfun->machine->some_ld_name = XSTR (x, 0);
7021 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
7022 C -- print opcode suffix for set/cmov insn.
7023 c -- like C, but print reversed condition
7024 F,f -- likewise, but for floating-point.
7025 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
7027 R -- print the prefix for register names.
7028 z -- print the opcode suffix for the size of the current operand.
7029 * -- print a star (in certain assembler syntax)
7030 A -- print an absolute memory reference.
7031 w -- print the operand as if it's a "word" (HImode) even if it isn't.
7032 s -- print a shift double count, followed by the assemblers argument
7034 b -- print the QImode name of the register for the indicated operand.
7035 %b0 would print %al if operands[0] is reg 0.
7036 w -- likewise, print the HImode name of the register.
7037 k -- likewise, print the SImode name of the register.
7038 q -- likewise, print the DImode name of the register.
7039 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
7040 y -- print "st(0)" instead of "st" as a register.
7041 D -- print condition for SSE cmp instruction.
7042 P -- if PIC, print an @PLT suffix.
7043 X -- don't print any sort of PIC '@' suffix for a symbol.
7044 & -- print some in-use local-dynamic symbol name.
7045 H -- print a memory address offset by 8; used for sse high-parts
7049 print_operand (FILE *file, rtx x, int code)
7056 if (ASSEMBLER_DIALECT == ASM_ATT)
7061 assemble_name (file, get_some_local_dynamic_name ());
7065 switch (ASSEMBLER_DIALECT)
7072 /* Intel syntax. For absolute addresses, registers should not
7073 be surrounded by braces. */
7074 if (GET_CODE (x) != REG)
7077 PRINT_OPERAND (file, x, 0);
7087 PRINT_OPERAND (file, x, 0);
7092 if (ASSEMBLER_DIALECT == ASM_ATT)
7097 if (ASSEMBLER_DIALECT == ASM_ATT)
7102 if (ASSEMBLER_DIALECT == ASM_ATT)
7107 if (ASSEMBLER_DIALECT == ASM_ATT)
7112 if (ASSEMBLER_DIALECT == ASM_ATT)
7117 if (ASSEMBLER_DIALECT == ASM_ATT)
7122 /* 387 opcodes don't get size suffixes if the operands are
7124 if (STACK_REG_P (x))
7127 /* Likewise if using Intel opcodes. */
7128 if (ASSEMBLER_DIALECT == ASM_INTEL)
7131 /* This is the size of op from size of operand. */
7132 switch (GET_MODE_SIZE (GET_MODE (x)))
7135 #ifdef HAVE_GAS_FILDS_FISTS
7141 if (GET_MODE (x) == SFmode)
7156 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
7158 #ifdef GAS_MNEMONICS
7184 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
7186 PRINT_OPERAND (file, x, 0);
7192 /* Little bit of braindamage here. The SSE compare instructions
7193 does use completely different names for the comparisons that the
7194 fp conditional moves. */
7195 switch (GET_CODE (x))
7210 fputs ("unord", file);
7214 fputs ("neq", file);
7218 fputs ("nlt", file);
7222 fputs ("nle", file);
7225 fputs ("ord", file);
7232 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7233 if (ASSEMBLER_DIALECT == ASM_ATT)
7235 switch (GET_MODE (x))
7237 case HImode: putc ('w', file); break;
7239 case SFmode: putc ('l', file); break;
7241 case DFmode: putc ('q', file); break;
7242 default: gcc_unreachable ();
7249 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
7252 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7253 if (ASSEMBLER_DIALECT == ASM_ATT)
7256 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
7259 /* Like above, but reverse condition */
7261 /* Check to see if argument to %c is really a constant
7262 and not a condition code which needs to be reversed. */
7263 if (!COMPARISON_P (x))
7265 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
7268 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
7271 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7272 if (ASSEMBLER_DIALECT == ASM_ATT)
7275 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
7279 /* It doesn't actually matter what mode we use here, as we're
7280 only going to use this for printing. */
7281 x = adjust_address_nv (x, DImode, 8);
7288 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
7291 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
7294 int pred_val = INTVAL (XEXP (x, 0));
7296 if (pred_val < REG_BR_PROB_BASE * 45 / 100
7297 || pred_val > REG_BR_PROB_BASE * 55 / 100)
7299 int taken = pred_val > REG_BR_PROB_BASE / 2;
7300 int cputaken = final_forward_branch_p (current_output_insn) == 0;
7302 /* Emit hints only in the case default branch prediction
7303 heuristics would fail. */
7304 if (taken != cputaken)
7306 /* We use 3e (DS) prefix for taken branches and
7307 2e (CS) prefix for not taken branches. */
7309 fputs ("ds ; ", file);
7311 fputs ("cs ; ", file);
7318 output_operand_lossage ("invalid operand code '%c'", code);
7322 if (GET_CODE (x) == REG)
7323 print_reg (x, code, file);
7325 else if (GET_CODE (x) == MEM)
7327 /* No `byte ptr' prefix for call instructions. */
7328 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
7331 switch (GET_MODE_SIZE (GET_MODE (x)))
7333 case 1: size = "BYTE"; break;
7334 case 2: size = "WORD"; break;
7335 case 4: size = "DWORD"; break;
7336 case 8: size = "QWORD"; break;
7337 case 12: size = "XWORD"; break;
7338 case 16: size = "XMMWORD"; break;
7343 /* Check for explicit size override (codes 'b', 'w' and 'k') */
7346 else if (code == 'w')
7348 else if (code == 'k')
7352 fputs (" PTR ", file);
7356 /* Avoid (%rip) for call operands. */
7357 if (CONSTANT_ADDRESS_P (x) && code == 'P'
7358 && GET_CODE (x) != CONST_INT)
7359 output_addr_const (file, x);
7360 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
7361 output_operand_lossage ("invalid constraints for operand");
7366 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
7371 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7372 REAL_VALUE_TO_TARGET_SINGLE (r, l);
7374 if (ASSEMBLER_DIALECT == ASM_ATT)
7376 fprintf (file, "0x%08lx", l);
7379 /* These float cases don't actually occur as immediate operands. */
7380 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
7384 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7385 fprintf (file, "%s", dstr);
7388 else if (GET_CODE (x) == CONST_DOUBLE
7389 && GET_MODE (x) == XFmode)
7393 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7394 fprintf (file, "%s", dstr);
7399 /* We have patterns that allow zero sets of memory, for instance.
7400 In 64-bit mode, we should probably support all 8-byte vectors,
7401 since we can in fact encode that into an immediate. */
7402 if (GET_CODE (x) == CONST_VECTOR)
7404 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
7410 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
7412 if (ASSEMBLER_DIALECT == ASM_ATT)
7415 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
7416 || GET_CODE (x) == LABEL_REF)
7418 if (ASSEMBLER_DIALECT == ASM_ATT)
7421 fputs ("OFFSET FLAT:", file);
7424 if (GET_CODE (x) == CONST_INT)
7425 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7427 output_pic_addr_const (file, x, code);
7429 output_addr_const (file, x);
7433 /* Print a memory operand whose address is ADDR. */
7436 print_operand_address (FILE *file, rtx addr)
7438 struct ix86_address parts;
7439 rtx base, index, disp;
7441 int ok = ix86_decompose_address (addr, &parts);
7446 index = parts.index;
7448 scale = parts.scale;
7456 if (USER_LABEL_PREFIX[0] == 0)
7458 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
7464 if (!base && !index)
7466 /* Displacement only requires special attention. */
7468 if (GET_CODE (disp) == CONST_INT)
7470 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
7472 if (USER_LABEL_PREFIX[0] == 0)
7474 fputs ("ds:", file);
7476 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
7479 output_pic_addr_const (file, disp, 0);
7481 output_addr_const (file, disp);
7483 /* Use one byte shorter RIP relative addressing for 64bit mode. */
7486 if (GET_CODE (disp) == CONST
7487 && GET_CODE (XEXP (disp, 0)) == PLUS
7488 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7489 disp = XEXP (XEXP (disp, 0), 0);
7490 if (GET_CODE (disp) == LABEL_REF
7491 || (GET_CODE (disp) == SYMBOL_REF
7492 && SYMBOL_REF_TLS_MODEL (disp) == 0))
7493 fputs ("(%rip)", file);
7498 if (ASSEMBLER_DIALECT == ASM_ATT)
7503 output_pic_addr_const (file, disp, 0);
7504 else if (GET_CODE (disp) == LABEL_REF)
7505 output_asm_label (disp);
7507 output_addr_const (file, disp);
7512 print_reg (base, 0, file);
7516 print_reg (index, 0, file);
7518 fprintf (file, ",%d", scale);
7524 rtx offset = NULL_RTX;
7528 /* Pull out the offset of a symbol; print any symbol itself. */
7529 if (GET_CODE (disp) == CONST
7530 && GET_CODE (XEXP (disp, 0)) == PLUS
7531 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7533 offset = XEXP (XEXP (disp, 0), 1);
7534 disp = gen_rtx_CONST (VOIDmode,
7535 XEXP (XEXP (disp, 0), 0));
7539 output_pic_addr_const (file, disp, 0);
7540 else if (GET_CODE (disp) == LABEL_REF)
7541 output_asm_label (disp);
7542 else if (GET_CODE (disp) == CONST_INT)
7545 output_addr_const (file, disp);
7551 print_reg (base, 0, file);
7554 if (INTVAL (offset) >= 0)
7556 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7560 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7567 print_reg (index, 0, file);
7569 fprintf (file, "*%d", scale);
7577 output_addr_const_extra (FILE *file, rtx x)
7581 if (GET_CODE (x) != UNSPEC)
7584 op = XVECEXP (x, 0, 0);
7585 switch (XINT (x, 1))
7587 case UNSPEC_GOTTPOFF:
7588 output_addr_const (file, op);
7589 /* FIXME: This might be @TPOFF in Sun ld. */
7590 fputs ("@GOTTPOFF", file);
7593 output_addr_const (file, op);
7594 fputs ("@TPOFF", file);
7597 output_addr_const (file, op);
7599 fputs ("@TPOFF", file);
7601 fputs ("@NTPOFF", file);
7604 output_addr_const (file, op);
7605 fputs ("@DTPOFF", file);
7607 case UNSPEC_GOTNTPOFF:
7608 output_addr_const (file, op);
7610 fputs ("@GOTTPOFF(%rip)", file);
7612 fputs ("@GOTNTPOFF", file);
7614 case UNSPEC_INDNTPOFF:
7615 output_addr_const (file, op);
7616 fputs ("@INDNTPOFF", file);
7626 /* Split one or more DImode RTL references into pairs of SImode
7627 references. The RTL can be REG, offsettable MEM, integer constant, or
7628 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
7629 split and "num" is its length. lo_half and hi_half are output arrays
7630 that parallel "operands". */
7633 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
7637 rtx op = operands[num];
7639 /* simplify_subreg refuse to split volatile memory addresses,
7640 but we still have to handle it. */
7641 if (GET_CODE (op) == MEM)
7643 lo_half[num] = adjust_address (op, SImode, 0);
7644 hi_half[num] = adjust_address (op, SImode, 4);
7648 lo_half[num] = simplify_gen_subreg (SImode, op,
7649 GET_MODE (op) == VOIDmode
7650 ? DImode : GET_MODE (op), 0);
7651 hi_half[num] = simplify_gen_subreg (SImode, op,
7652 GET_MODE (op) == VOIDmode
7653 ? DImode : GET_MODE (op), 4);
7657 /* Split one or more TImode RTL references into pairs of DImode
7658 references. The RTL can be REG, offsettable MEM, integer constant, or
7659 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
7660 split and "num" is its length. lo_half and hi_half are output arrays
7661 that parallel "operands". */
7664 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
7668 rtx op = operands[num];
7670 /* simplify_subreg refuse to split volatile memory addresses, but we
7671 still have to handle it. */
7672 if (GET_CODE (op) == MEM)
7674 lo_half[num] = adjust_address (op, DImode, 0);
7675 hi_half[num] = adjust_address (op, DImode, 8);
7679 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
7680 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
7685 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
7686 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
7687 is the expression of the binary operation. The output may either be
7688 emitted here, or returned to the caller, like all output_* functions.
7690 There is no guarantee that the operands are the same mode, as they
7691 might be within FLOAT or FLOAT_EXTEND expressions. */
7693 #ifndef SYSV386_COMPAT
7694 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
7695 wants to fix the assemblers because that causes incompatibility
7696 with gcc. No-one wants to fix gcc because that causes
7697 incompatibility with assemblers... You can use the option of
7698 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
7699 #define SYSV386_COMPAT 1
7703 output_387_binary_op (rtx insn, rtx *operands)
7705 static char buf[30];
7708 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
7710 #ifdef ENABLE_CHECKING
7711 /* Even if we do not want to check the inputs, this documents input
7712 constraints. Which helps in understanding the following code. */
7713 if (STACK_REG_P (operands[0])
7714 && ((REG_P (operands[1])
7715 && REGNO (operands[0]) == REGNO (operands[1])
7716 && (STACK_REG_P (operands[2]) || GET_CODE (operands[2]) == MEM))
7717 || (REG_P (operands[2])
7718 && REGNO (operands[0]) == REGNO (operands[2])
7719 && (STACK_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)))
7720 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
7723 gcc_assert (is_sse);
7726 switch (GET_CODE (operands[3]))
7729 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7730 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7738 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7739 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7747 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7748 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7756 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7757 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7771 if (GET_MODE (operands[0]) == SFmode)
7772 strcat (buf, "ss\t{%2, %0|%0, %2}");
7774 strcat (buf, "sd\t{%2, %0|%0, %2}");
7779 switch (GET_CODE (operands[3]))
7783 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
7785 rtx temp = operands[2];
7786 operands[2] = operands[1];
7790 /* know operands[0] == operands[1]. */
7792 if (GET_CODE (operands[2]) == MEM)
7798 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
7800 if (STACK_TOP_P (operands[0]))
7801 /* How is it that we are storing to a dead operand[2]?
7802 Well, presumably operands[1] is dead too. We can't
7803 store the result to st(0) as st(0) gets popped on this
7804 instruction. Instead store to operands[2] (which I
7805 think has to be st(1)). st(1) will be popped later.
7806 gcc <= 2.8.1 didn't have this check and generated
7807 assembly code that the Unixware assembler rejected. */
7808 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7810 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7814 if (STACK_TOP_P (operands[0]))
7815 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7817 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7822 if (GET_CODE (operands[1]) == MEM)
7828 if (GET_CODE (operands[2]) == MEM)
7834 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
7837 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
7838 derived assemblers, confusingly reverse the direction of
7839 the operation for fsub{r} and fdiv{r} when the
7840 destination register is not st(0). The Intel assembler
7841 doesn't have this brain damage. Read !SYSV386_COMPAT to
7842 figure out what the hardware really does. */
7843 if (STACK_TOP_P (operands[0]))
7844 p = "{p\t%0, %2|rp\t%2, %0}";
7846 p = "{rp\t%2, %0|p\t%0, %2}";
7848 if (STACK_TOP_P (operands[0]))
7849 /* As above for fmul/fadd, we can't store to st(0). */
7850 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7852 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7857 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
7860 if (STACK_TOP_P (operands[0]))
7861 p = "{rp\t%0, %1|p\t%1, %0}";
7863 p = "{p\t%1, %0|rp\t%0, %1}";
7865 if (STACK_TOP_P (operands[0]))
7866 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
7868 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
7873 if (STACK_TOP_P (operands[0]))
7875 if (STACK_TOP_P (operands[1]))
7876 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7878 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
7881 else if (STACK_TOP_P (operands[1]))
7884 p = "{\t%1, %0|r\t%0, %1}";
7886 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
7892 p = "{r\t%2, %0|\t%0, %2}";
7894 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7907 /* Return needed mode for entity in optimize_mode_switching pass. */
7910 ix86_mode_needed (int entity, rtx insn)
7912 enum attr_i387_cw mode;
7914 /* The mode UNINITIALIZED is used to store control word after a
7915 function call or ASM pattern. The mode ANY specify that function
7916 has no requirements on the control word and make no changes in the
7917 bits we are interested in. */
7920 || (NONJUMP_INSN_P (insn)
7921 && (asm_noperands (PATTERN (insn)) >= 0
7922 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
7923 return I387_CW_UNINITIALIZED;
7925 if (recog_memoized (insn) < 0)
7928 mode = get_attr_i387_cw (insn);
7933 if (mode == I387_CW_TRUNC)
7938 if (mode == I387_CW_FLOOR)
7943 if (mode == I387_CW_CEIL)
7948 if (mode == I387_CW_MASK_PM)
7959 /* Output code to initialize control word copies used by trunc?f?i and
7960 rounding patterns. CURRENT_MODE is set to current control word,
7961 while NEW_MODE is set to new control word. */
7964 emit_i387_cw_initialization (int mode)
7966 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
7971 rtx reg = gen_reg_rtx (HImode);
7973 emit_insn (gen_x86_fnstcw_1 (stored_mode));
7974 emit_move_insn (reg, stored_mode);
7976 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
7981 /* round toward zero (truncate) */
7982 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
7983 slot = SLOT_CW_TRUNC;
7987 /* round down toward -oo */
7988 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
7989 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
7990 slot = SLOT_CW_FLOOR;
7994 /* round up toward +oo */
7995 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
7996 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
7997 slot = SLOT_CW_CEIL;
8000 case I387_CW_MASK_PM:
8001 /* mask precision exception for nearbyint() */
8002 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8003 slot = SLOT_CW_MASK_PM;
8015 /* round toward zero (truncate) */
8016 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
8017 slot = SLOT_CW_TRUNC;
8021 /* round down toward -oo */
8022 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
8023 slot = SLOT_CW_FLOOR;
8027 /* round up toward +oo */
8028 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
8029 slot = SLOT_CW_CEIL;
8032 case I387_CW_MASK_PM:
8033 /* mask precision exception for nearbyint() */
8034 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8035 slot = SLOT_CW_MASK_PM;
8043 gcc_assert (slot < MAX_386_STACK_LOCALS);
8045 new_mode = assign_386_stack_local (HImode, slot);
8046 emit_move_insn (new_mode, reg);
8049 /* Output code for INSN to convert a float to a signed int. OPERANDS
8050 are the insn operands. The output may be [HSD]Imode and the input
8051 operand may be [SDX]Fmode. */
8054 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
8056 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
8057 int dimode_p = GET_MODE (operands[0]) == DImode;
8058 int round_mode = get_attr_i387_cw (insn);
8060 /* Jump through a hoop or two for DImode, since the hardware has no
8061 non-popping instruction. We used to do this a different way, but
8062 that was somewhat fragile and broke with post-reload splitters. */
8063 if ((dimode_p || fisttp) && !stack_top_dies)
8064 output_asm_insn ("fld\t%y1", operands);
8066 gcc_assert (STACK_TOP_P (operands[1]));
8067 gcc_assert (GET_CODE (operands[0]) == MEM);
8070 output_asm_insn ("fisttp%z0\t%0", operands);
8073 if (round_mode != I387_CW_ANY)
8074 output_asm_insn ("fldcw\t%3", operands);
8075 if (stack_top_dies || dimode_p)
8076 output_asm_insn ("fistp%z0\t%0", operands);
8078 output_asm_insn ("fist%z0\t%0", operands);
8079 if (round_mode != I387_CW_ANY)
8080 output_asm_insn ("fldcw\t%2", operands);
8086 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
8087 should be used. UNORDERED_P is true when fucom should be used. */
8090 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
8093 rtx cmp_op0, cmp_op1;
8094 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
8098 cmp_op0 = operands[0];
8099 cmp_op1 = operands[1];
8103 cmp_op0 = operands[1];
8104 cmp_op1 = operands[2];
8109 if (GET_MODE (operands[0]) == SFmode)
8111 return "ucomiss\t{%1, %0|%0, %1}";
8113 return "comiss\t{%1, %0|%0, %1}";
8116 return "ucomisd\t{%1, %0|%0, %1}";
8118 return "comisd\t{%1, %0|%0, %1}";
8121 gcc_assert (STACK_TOP_P (cmp_op0));
8123 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
8125 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
8129 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
8130 return TARGET_USE_FFREEP ? "ffreep\t%y1" : "fstp\t%y1";
8133 return "ftst\n\tfnstsw\t%0";
8136 if (STACK_REG_P (cmp_op1)
8138 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
8139 && REGNO (cmp_op1) != FIRST_STACK_REG)
8141 /* If both the top of the 387 stack dies, and the other operand
8142 is also a stack register that dies, then this must be a
8143 `fcompp' float compare */
8147 /* There is no double popping fcomi variant. Fortunately,
8148 eflags is immune from the fstp's cc clobbering. */
8150 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
8152 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
8153 return TARGET_USE_FFREEP ? "ffreep\t%y0" : "fstp\t%y0";
8158 return "fucompp\n\tfnstsw\t%0";
8160 return "fcompp\n\tfnstsw\t%0";
8165 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
8167 static const char * const alt[16] =
8169 "fcom%z2\t%y2\n\tfnstsw\t%0",
8170 "fcomp%z2\t%y2\n\tfnstsw\t%0",
8171 "fucom%z2\t%y2\n\tfnstsw\t%0",
8172 "fucomp%z2\t%y2\n\tfnstsw\t%0",
8174 "ficom%z2\t%y2\n\tfnstsw\t%0",
8175 "ficomp%z2\t%y2\n\tfnstsw\t%0",
8179 "fcomi\t{%y1, %0|%0, %y1}",
8180 "fcomip\t{%y1, %0|%0, %y1}",
8181 "fucomi\t{%y1, %0|%0, %y1}",
8182 "fucomip\t{%y1, %0|%0, %y1}",
8193 mask = eflags_p << 3;
8194 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
8195 mask |= unordered_p << 1;
8196 mask |= stack_top_dies;
8198 gcc_assert (mask < 16);
8207 ix86_output_addr_vec_elt (FILE *file, int value)
8209 const char *directive = ASM_LONG;
8213 directive = ASM_QUAD;
8215 gcc_assert (!TARGET_64BIT);
8218 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
8222 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
8225 fprintf (file, "%s%s%d-%s%d\n",
8226 ASM_LONG, LPREFIX, value, LPREFIX, rel);
8227 else if (HAVE_AS_GOTOFF_IN_DATA)
8228 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
8230 else if (TARGET_MACHO)
8232 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
8233 machopic_output_function_base_name (file);
8234 fprintf(file, "\n");
8238 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
8239 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
8242 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
8246 ix86_expand_clear (rtx dest)
8250 /* We play register width games, which are only valid after reload. */
8251 gcc_assert (reload_completed);
8253 /* Avoid HImode and its attendant prefix byte. */
8254 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
8255 dest = gen_rtx_REG (SImode, REGNO (dest));
8257 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
8259 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
8260 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
8262 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
8263 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
8269 /* X is an unchanging MEM. If it is a constant pool reference, return
8270 the constant pool rtx, else NULL. */
8273 maybe_get_pool_constant (rtx x)
8275 x = ix86_delegitimize_address (XEXP (x, 0));
8277 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
8278 return get_pool_constant (x);
8284 ix86_expand_move (enum machine_mode mode, rtx operands[])
8286 int strict = (reload_in_progress || reload_completed);
8288 enum tls_model model;
8293 if (GET_CODE (op1) == SYMBOL_REF)
8295 model = SYMBOL_REF_TLS_MODEL (op1);
8298 op1 = legitimize_tls_address (op1, model, true);
8299 op1 = force_operand (op1, op0);
8304 else if (GET_CODE (op1) == CONST
8305 && GET_CODE (XEXP (op1, 0)) == PLUS
8306 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
8308 model = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (op1, 0), 0));
8311 rtx addend = XEXP (XEXP (op1, 0), 1);
8312 op1 = legitimize_tls_address (XEXP (XEXP (op1, 0), 0), model, true);
8313 op1 = force_operand (op1, NULL);
8314 op1 = expand_simple_binop (Pmode, PLUS, op1, addend,
8315 op0, 1, OPTAB_DIRECT);
8321 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
8326 rtx temp = ((reload_in_progress
8327 || ((op0 && GET_CODE (op0) == REG)
8329 ? op0 : gen_reg_rtx (Pmode));
8330 op1 = machopic_indirect_data_reference (op1, temp);
8331 op1 = machopic_legitimize_pic_address (op1, mode,
8332 temp == op1 ? 0 : temp);
8334 else if (MACHOPIC_INDIRECT)
8335 op1 = machopic_indirect_data_reference (op1, 0);
8339 if (GET_CODE (op0) == MEM)
8340 op1 = force_reg (Pmode, op1);
8342 op1 = legitimize_address (op1, op1, Pmode);
8343 #endif /* TARGET_MACHO */
8347 if (GET_CODE (op0) == MEM
8348 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
8349 || !push_operand (op0, mode))
8350 && GET_CODE (op1) == MEM)
8351 op1 = force_reg (mode, op1);
8353 if (push_operand (op0, mode)
8354 && ! general_no_elim_operand (op1, mode))
8355 op1 = copy_to_mode_reg (mode, op1);
8357 /* Force large constants in 64bit compilation into register
8358 to get them CSEed. */
8359 if (TARGET_64BIT && mode == DImode
8360 && immediate_operand (op1, mode)
8361 && !x86_64_zext_immediate_operand (op1, VOIDmode)
8362 && !register_operand (op0, mode)
8363 && optimize && !reload_completed && !reload_in_progress)
8364 op1 = copy_to_mode_reg (mode, op1);
8366 if (FLOAT_MODE_P (mode))
8368 /* If we are loading a floating point constant to a register,
8369 force the value to memory now, since we'll get better code
8370 out the back end. */
8374 else if (GET_CODE (op1) == CONST_DOUBLE)
8376 op1 = validize_mem (force_const_mem (mode, op1));
8377 if (!register_operand (op0, mode))
8379 rtx temp = gen_reg_rtx (mode);
8380 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
8381 emit_move_insn (op0, temp);
8388 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8392 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
8394 rtx op0 = operands[0], op1 = operands[1];
8396 /* Force constants other than zero into memory. We do not know how
8397 the instructions used to build constants modify the upper 64 bits
8398 of the register, once we have that information we may be able
8399 to handle some of them more efficiently. */
8400 if ((reload_in_progress | reload_completed) == 0
8401 && register_operand (op0, mode)
8402 && CONSTANT_P (op1) && op1 != CONST0_RTX (mode))
8403 op1 = validize_mem (force_const_mem (mode, op1));
8405 /* Make operand1 a register if it isn't already. */
8407 && !register_operand (op0, mode)
8408 && !register_operand (op1, mode))
8410 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
8414 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8417 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
8418 straight to ix86_expand_vector_move. */
8421 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
8430 /* If we're optimizing for size, movups is the smallest. */
8433 op0 = gen_lowpart (V4SFmode, op0);
8434 op1 = gen_lowpart (V4SFmode, op1);
8435 emit_insn (gen_sse_movups (op0, op1));
8439 /* ??? If we have typed data, then it would appear that using
8440 movdqu is the only way to get unaligned data loaded with
8442 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8444 op0 = gen_lowpart (V16QImode, op0);
8445 op1 = gen_lowpart (V16QImode, op1);
8446 emit_insn (gen_sse2_movdqu (op0, op1));
8450 if (TARGET_SSE2 && mode == V2DFmode)
8454 /* When SSE registers are split into halves, we can avoid
8455 writing to the top half twice. */
8456 if (TARGET_SSE_SPLIT_REGS)
8458 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8463 /* ??? Not sure about the best option for the Intel chips.
8464 The following would seem to satisfy; the register is
8465 entirely cleared, breaking the dependency chain. We
8466 then store to the upper half, with a dependency depth
8467 of one. A rumor has it that Intel recommends two movsd
8468 followed by an unpacklpd, but this is unconfirmed. And
8469 given that the dependency depth of the unpacklpd would
8470 still be one, I'm not sure why this would be better. */
8471 zero = CONST0_RTX (V2DFmode);
8474 m = adjust_address (op1, DFmode, 0);
8475 emit_insn (gen_sse2_loadlpd (op0, zero, m));
8476 m = adjust_address (op1, DFmode, 8);
8477 emit_insn (gen_sse2_loadhpd (op0, op0, m));
8481 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
8482 emit_move_insn (op0, CONST0_RTX (mode));
8484 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8486 if (mode != V4SFmode)
8487 op0 = gen_lowpart (V4SFmode, op0);
8488 m = adjust_address (op1, V2SFmode, 0);
8489 emit_insn (gen_sse_loadlps (op0, op0, m));
8490 m = adjust_address (op1, V2SFmode, 8);
8491 emit_insn (gen_sse_loadhps (op0, op0, m));
8494 else if (MEM_P (op0))
8496 /* If we're optimizing for size, movups is the smallest. */
8499 op0 = gen_lowpart (V4SFmode, op0);
8500 op1 = gen_lowpart (V4SFmode, op1);
8501 emit_insn (gen_sse_movups (op0, op1));
8505 /* ??? Similar to above, only less clear because of quote
8506 typeless stores unquote. */
8507 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
8508 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8510 op0 = gen_lowpart (V16QImode, op0);
8511 op1 = gen_lowpart (V16QImode, op1);
8512 emit_insn (gen_sse2_movdqu (op0, op1));
8516 if (TARGET_SSE2 && mode == V2DFmode)
8518 m = adjust_address (op0, DFmode, 0);
8519 emit_insn (gen_sse2_storelpd (m, op1));
8520 m = adjust_address (op0, DFmode, 8);
8521 emit_insn (gen_sse2_storehpd (m, op1));
8525 if (mode != V4SFmode)
8526 op1 = gen_lowpart (V4SFmode, op1);
8527 m = adjust_address (op0, V2SFmode, 0);
8528 emit_insn (gen_sse_storelps (m, op1));
8529 m = adjust_address (op0, V2SFmode, 8);
8530 emit_insn (gen_sse_storehps (m, op1));
8537 /* Expand a push in MODE. This is some mode for which we do not support
8538 proper push instructions, at least from the registers that we expect
8539 the value to live in. */
8542 ix86_expand_push (enum machine_mode mode, rtx x)
8546 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
8547 GEN_INT (-GET_MODE_SIZE (mode)),
8548 stack_pointer_rtx, 1, OPTAB_DIRECT);
8549 if (tmp != stack_pointer_rtx)
8550 emit_move_insn (stack_pointer_rtx, tmp);
8552 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
8553 emit_move_insn (tmp, x);
8556 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
8557 destination to use for the operation. If different from the true
8558 destination in operands[0], a copy operation will be required. */
8561 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
8564 int matching_memory;
8565 rtx src1, src2, dst;
8571 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
8572 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8573 && (rtx_equal_p (dst, src2)
8574 || immediate_operand (src1, mode)))
8581 /* If the destination is memory, and we do not have matching source
8582 operands, do things in registers. */
8583 matching_memory = 0;
8584 if (GET_CODE (dst) == MEM)
8586 if (rtx_equal_p (dst, src1))
8587 matching_memory = 1;
8588 else if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8589 && rtx_equal_p (dst, src2))
8590 matching_memory = 2;
8592 dst = gen_reg_rtx (mode);
8595 /* Both source operands cannot be in memory. */
8596 if (GET_CODE (src1) == MEM && GET_CODE (src2) == MEM)
8598 if (matching_memory != 2)
8599 src2 = force_reg (mode, src2);
8601 src1 = force_reg (mode, src1);
8604 /* If the operation is not commutable, source 1 cannot be a constant
8605 or non-matching memory. */
8606 if ((CONSTANT_P (src1)
8607 || (!matching_memory && GET_CODE (src1) == MEM))
8608 && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
8609 src1 = force_reg (mode, src1);
8611 src1 = operands[1] = src1;
8612 src2 = operands[2] = src2;
8616 /* Similarly, but assume that the destination has already been
8620 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
8621 enum machine_mode mode, rtx operands[])
8623 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
8624 gcc_assert (dst == operands[0]);
8627 /* Attempt to expand a binary operator. Make the expansion closer to the
8628 actual machine, then just general_operand, which will allow 3 separate
8629 memory references (one output, two input) in a single insn. */
8632 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
8635 rtx src1, src2, dst, op, clob;
8637 dst = ix86_fixup_binary_operands (code, mode, operands);
8641 /* Emit the instruction. */
8643 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
8644 if (reload_in_progress)
8646 /* Reload doesn't know about the flags register, and doesn't know that
8647 it doesn't want to clobber it. We can only do this with PLUS. */
8648 gcc_assert (code == PLUS);
8653 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8654 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
8657 /* Fix up the destination if needed. */
8658 if (dst != operands[0])
8659 emit_move_insn (operands[0], dst);
8662 /* Return TRUE or FALSE depending on whether the binary operator meets the
8663 appropriate constraints. */
8666 ix86_binary_operator_ok (enum rtx_code code,
8667 enum machine_mode mode ATTRIBUTE_UNUSED,
8670 /* Both source operands cannot be in memory. */
8671 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
8673 /* If the operation is not commutable, source 1 cannot be a constant. */
8674 if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
8676 /* If the destination is memory, we must have a matching source operand. */
8677 if (GET_CODE (operands[0]) == MEM
8678 && ! (rtx_equal_p (operands[0], operands[1])
8679 || (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8680 && rtx_equal_p (operands[0], operands[2]))))
8682 /* If the operation is not commutable and the source 1 is memory, we must
8683 have a matching destination. */
8684 if (GET_CODE (operands[1]) == MEM
8685 && GET_RTX_CLASS (code) != RTX_COMM_ARITH
8686 && ! rtx_equal_p (operands[0], operands[1]))
8691 /* Attempt to expand a unary operator. Make the expansion closer to the
8692 actual machine, then just general_operand, which will allow 2 separate
8693 memory references (one output, one input) in a single insn. */
8696 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
8699 int matching_memory;
8700 rtx src, dst, op, clob;
8705 /* If the destination is memory, and we do not have matching source
8706 operands, do things in registers. */
8707 matching_memory = 0;
8710 if (rtx_equal_p (dst, src))
8711 matching_memory = 1;
8713 dst = gen_reg_rtx (mode);
8716 /* When source operand is memory, destination must match. */
8717 if (MEM_P (src) && !matching_memory)
8718 src = force_reg (mode, src);
8720 /* Emit the instruction. */
8722 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
8723 if (reload_in_progress || code == NOT)
8725 /* Reload doesn't know about the flags register, and doesn't know that
8726 it doesn't want to clobber it. */
8727 gcc_assert (code == NOT);
8732 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8733 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
8736 /* Fix up the destination if needed. */
8737 if (dst != operands[0])
8738 emit_move_insn (operands[0], dst);
8741 /* Return TRUE or FALSE depending on whether the unary operator meets the
8742 appropriate constraints. */
8745 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
8746 enum machine_mode mode ATTRIBUTE_UNUSED,
8747 rtx operands[2] ATTRIBUTE_UNUSED)
8749 /* If one of operands is memory, source and destination must match. */
8750 if ((GET_CODE (operands[0]) == MEM
8751 || GET_CODE (operands[1]) == MEM)
8752 && ! rtx_equal_p (operands[0], operands[1]))
8757 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
8758 Create a mask for the sign bit in MODE for an SSE register. If VECT is
8759 true, then replicate the mask for all elements of the vector register.
8760 If INVERT is true, then create a mask excluding the sign bit. */
8763 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
8765 enum machine_mode vec_mode;
8766 HOST_WIDE_INT hi, lo;
8771 /* Find the sign bit, sign extended to 2*HWI. */
8773 lo = 0x80000000, hi = lo < 0;
8774 else if (HOST_BITS_PER_WIDE_INT >= 64)
8775 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
8777 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
8782 /* Force this value into the low part of a fp vector constant. */
8783 mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
8784 mask = gen_lowpart (mode, mask);
8789 v = gen_rtvec (4, mask, mask, mask, mask);
8791 v = gen_rtvec (4, mask, CONST0_RTX (SFmode),
8792 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
8793 vec_mode = V4SFmode;
8798 v = gen_rtvec (2, mask, mask);
8800 v = gen_rtvec (2, mask, CONST0_RTX (DFmode));
8801 vec_mode = V2DFmode;
8804 return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v));
8807 /* Generate code for floating point ABS or NEG. */
8810 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
8813 rtx mask, set, use, clob, dst, src;
8814 bool matching_memory;
8815 bool use_sse = false;
8816 bool vector_mode = VECTOR_MODE_P (mode);
8817 enum machine_mode elt_mode = mode;
8821 elt_mode = GET_MODE_INNER (mode);
8824 else if (TARGET_SSE_MATH)
8825 use_sse = SSE_FLOAT_MODE_P (mode);
8827 /* NEG and ABS performed with SSE use bitwise mask operations.
8828 Create the appropriate mask now. */
8830 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
8833 /* When not using SSE, we don't use the mask, but prefer to keep the
8834 same general form of the insn pattern to reduce duplication when
8835 it comes time to split. */
8842 /* If the destination is memory, and we don't have matching source
8843 operands, do things in registers. */
8844 matching_memory = false;
8847 if (rtx_equal_p (dst, src))
8848 matching_memory = true;
8850 dst = gen_reg_rtx (mode);
8852 if (MEM_P (src) && !matching_memory)
8853 src = force_reg (mode, src);
8857 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
8858 set = gen_rtx_SET (VOIDmode, dst, set);
8863 set = gen_rtx_fmt_e (code, mode, src);
8864 set = gen_rtx_SET (VOIDmode, dst, set);
8865 use = gen_rtx_USE (VOIDmode, mask);
8866 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8867 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, set, use, clob)));
8870 if (dst != operands[0])
8871 emit_move_insn (operands[0], dst);
8874 /* Expand a copysign operation. Special case operand 0 being a constant. */
8877 ix86_expand_copysign (rtx operands[])
8879 enum machine_mode mode, vmode;
8880 rtx dest, op0, op1, mask, nmask;
8886 mode = GET_MODE (dest);
8887 vmode = mode == SFmode ? V4SFmode : V2DFmode;
8889 if (GET_CODE (op0) == CONST_DOUBLE)
8893 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
8894 op0 = simplify_unary_operation (ABS, mode, op0, mode);
8896 if (op0 == CONST0_RTX (mode))
8897 op0 = CONST0_RTX (vmode);
8901 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
8902 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
8904 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
8905 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
8908 mask = ix86_build_signbit_mask (mode, 0, 0);
8911 emit_insn (gen_copysignsf3_const (dest, op0, op1, mask));
8913 emit_insn (gen_copysigndf3_const (dest, op0, op1, mask));
8917 nmask = ix86_build_signbit_mask (mode, 0, 1);
8918 mask = ix86_build_signbit_mask (mode, 0, 0);
8921 emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask));
8923 emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask));
8927 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
8928 be a constant, and so has already been expanded into a vector constant. */
8931 ix86_split_copysign_const (rtx operands[])
8933 enum machine_mode mode, vmode;
8934 rtx dest, op0, op1, mask, x;
8941 mode = GET_MODE (dest);
8942 vmode = GET_MODE (mask);
8944 dest = simplify_gen_subreg (vmode, dest, mode, 0);
8945 x = gen_rtx_AND (vmode, dest, mask);
8946 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8948 if (op0 != CONST0_RTX (vmode))
8950 x = gen_rtx_IOR (vmode, dest, op0);
8951 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8955 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
8956 so we have to do two masks. */
8959 ix86_split_copysign_var (rtx operands[])
8961 enum machine_mode mode, vmode;
8962 rtx dest, scratch, op0, op1, mask, nmask, x;
8965 scratch = operands[1];
8968 nmask = operands[4];
8971 mode = GET_MODE (dest);
8972 vmode = GET_MODE (mask);
8974 if (rtx_equal_p (op0, op1))
8976 /* Shouldn't happen often (it's useless, obviously), but when it does
8977 we'd generate incorrect code if we continue below. */
8978 emit_move_insn (dest, op0);
8982 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
8984 gcc_assert (REGNO (op1) == REGNO (scratch));
8986 x = gen_rtx_AND (vmode, scratch, mask);
8987 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
8990 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
8991 x = gen_rtx_NOT (vmode, dest);
8992 x = gen_rtx_AND (vmode, x, op0);
8993 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8997 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
8999 x = gen_rtx_AND (vmode, scratch, mask);
9001 else /* alternative 2,4 */
9003 gcc_assert (REGNO (mask) == REGNO (scratch));
9004 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
9005 x = gen_rtx_AND (vmode, scratch, op1);
9007 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
9009 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
9011 dest = simplify_gen_subreg (vmode, op0, mode, 0);
9012 x = gen_rtx_AND (vmode, dest, nmask);
9014 else /* alternative 3,4 */
9016 gcc_assert (REGNO (nmask) == REGNO (dest));
9018 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
9019 x = gen_rtx_AND (vmode, dest, op0);
9021 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9024 x = gen_rtx_IOR (vmode, dest, scratch);
9025 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9028 /* Return TRUE or FALSE depending on whether the first SET in INSN
9029 has source and destination with matching CC modes, and that the
9030 CC mode is at least as constrained as REQ_MODE. */
9033 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
9036 enum machine_mode set_mode;
9038 set = PATTERN (insn);
9039 if (GET_CODE (set) == PARALLEL)
9040 set = XVECEXP (set, 0, 0);
9041 gcc_assert (GET_CODE (set) == SET);
9042 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
9044 set_mode = GET_MODE (SET_DEST (set));
9048 if (req_mode != CCNOmode
9049 && (req_mode != CCmode
9050 || XEXP (SET_SRC (set), 1) != const0_rtx))
9054 if (req_mode == CCGCmode)
9058 if (req_mode == CCGOCmode || req_mode == CCNOmode)
9062 if (req_mode == CCZmode)
9072 return (GET_MODE (SET_SRC (set)) == set_mode);
9075 /* Generate insn patterns to do an integer compare of OPERANDS. */
9078 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
9080 enum machine_mode cmpmode;
9083 cmpmode = SELECT_CC_MODE (code, op0, op1);
9084 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
9086 /* This is very simple, but making the interface the same as in the
9087 FP case makes the rest of the code easier. */
9088 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
9089 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
9091 /* Return the test that should be put into the flags user, i.e.
9092 the bcc, scc, or cmov instruction. */
9093 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
9096 /* Figure out whether to use ordered or unordered fp comparisons.
9097 Return the appropriate mode to use. */
9100 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
9102 /* ??? In order to make all comparisons reversible, we do all comparisons
9103 non-trapping when compiling for IEEE. Once gcc is able to distinguish
9104 all forms trapping and nontrapping comparisons, we can make inequality
9105 comparisons trapping again, since it results in better code when using
9106 FCOM based compares. */
9107 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
9111 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
9113 if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
9114 return ix86_fp_compare_mode (code);
9117 /* Only zero flag is needed. */
9119 case NE: /* ZF!=0 */
9121 /* Codes needing carry flag. */
9122 case GEU: /* CF=0 */
9123 case GTU: /* CF=0 & ZF=0 */
9124 case LTU: /* CF=1 */
9125 case LEU: /* CF=1 | ZF=1 */
9127 /* Codes possibly doable only with sign flag when
9128 comparing against zero. */
9129 case GE: /* SF=OF or SF=0 */
9130 case LT: /* SF<>OF or SF=1 */
9131 if (op1 == const0_rtx)
9134 /* For other cases Carry flag is not required. */
9136 /* Codes doable only with sign flag when comparing
9137 against zero, but we miss jump instruction for it
9138 so we need to use relational tests against overflow
9139 that thus needs to be zero. */
9140 case GT: /* ZF=0 & SF=OF */
9141 case LE: /* ZF=1 | SF<>OF */
9142 if (op1 == const0_rtx)
9146 /* strcmp pattern do (use flags) and combine may ask us for proper
9155 /* Return the fixed registers used for condition codes. */
9158 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9165 /* If two condition code modes are compatible, return a condition code
9166 mode which is compatible with both. Otherwise, return
9169 static enum machine_mode
9170 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
9175 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
9178 if ((m1 == CCGCmode && m2 == CCGOCmode)
9179 || (m1 == CCGOCmode && m2 == CCGCmode))
9207 /* These are only compatible with themselves, which we already
9213 /* Return true if we should use an FCOMI instruction for this fp comparison. */
9216 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
9218 enum rtx_code swapped_code = swap_condition (code);
9219 return ((ix86_fp_comparison_cost (code) == ix86_fp_comparison_fcomi_cost (code))
9220 || (ix86_fp_comparison_cost (swapped_code)
9221 == ix86_fp_comparison_fcomi_cost (swapped_code)));
9224 /* Swap, force into registers, or otherwise massage the two operands
9225 to a fp comparison. The operands are updated in place; the new
9226 comparison code is returned. */
9228 static enum rtx_code
9229 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
9231 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
9232 rtx op0 = *pop0, op1 = *pop1;
9233 enum machine_mode op_mode = GET_MODE (op0);
9234 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
9236 /* All of the unordered compare instructions only work on registers.
9237 The same is true of the fcomi compare instructions. The XFmode
9238 compare instructions require registers except when comparing
9239 against zero or when converting operand 1 from fixed point to
9243 && (fpcmp_mode == CCFPUmode
9244 || (op_mode == XFmode
9245 && ! (standard_80387_constant_p (op0) == 1
9246 || standard_80387_constant_p (op1) == 1)
9247 && GET_CODE (op1) != FLOAT)
9248 || ix86_use_fcomi_compare (code)))
9250 op0 = force_reg (op_mode, op0);
9251 op1 = force_reg (op_mode, op1);
9255 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
9256 things around if they appear profitable, otherwise force op0
9259 if (standard_80387_constant_p (op0) == 0
9260 || (GET_CODE (op0) == MEM
9261 && ! (standard_80387_constant_p (op1) == 0
9262 || GET_CODE (op1) == MEM)))
9265 tmp = op0, op0 = op1, op1 = tmp;
9266 code = swap_condition (code);
9269 if (GET_CODE (op0) != REG)
9270 op0 = force_reg (op_mode, op0);
9272 if (CONSTANT_P (op1))
9274 int tmp = standard_80387_constant_p (op1);
9276 op1 = validize_mem (force_const_mem (op_mode, op1));
9280 op1 = force_reg (op_mode, op1);
9283 op1 = force_reg (op_mode, op1);
9287 /* Try to rearrange the comparison to make it cheaper. */
9288 if (ix86_fp_comparison_cost (code)
9289 > ix86_fp_comparison_cost (swap_condition (code))
9290 && (GET_CODE (op1) == REG || !no_new_pseudos))
9293 tmp = op0, op0 = op1, op1 = tmp;
9294 code = swap_condition (code);
9295 if (GET_CODE (op0) != REG)
9296 op0 = force_reg (op_mode, op0);
9304 /* Convert comparison codes we use to represent FP comparison to integer
9305 code that will result in proper branch. Return UNKNOWN if no such code
9309 ix86_fp_compare_code_to_integer (enum rtx_code code)
9338 /* Split comparison code CODE into comparisons we can do using branch
9339 instructions. BYPASS_CODE is comparison code for branch that will
9340 branch around FIRST_CODE and SECOND_CODE. If some of branches
9341 is not required, set value to UNKNOWN.
9342 We never require more than two branches. */
9345 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
9346 enum rtx_code *first_code,
9347 enum rtx_code *second_code)
9350 *bypass_code = UNKNOWN;
9351 *second_code = UNKNOWN;
9353 /* The fcomi comparison sets flags as follows:
9363 case GT: /* GTU - CF=0 & ZF=0 */
9364 case GE: /* GEU - CF=0 */
9365 case ORDERED: /* PF=0 */
9366 case UNORDERED: /* PF=1 */
9367 case UNEQ: /* EQ - ZF=1 */
9368 case UNLT: /* LTU - CF=1 */
9369 case UNLE: /* LEU - CF=1 | ZF=1 */
9370 case LTGT: /* EQ - ZF=0 */
9372 case LT: /* LTU - CF=1 - fails on unordered */
9374 *bypass_code = UNORDERED;
9376 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
9378 *bypass_code = UNORDERED;
9380 case EQ: /* EQ - ZF=1 - fails on unordered */
9382 *bypass_code = UNORDERED;
9384 case NE: /* NE - ZF=0 - fails on unordered */
9386 *second_code = UNORDERED;
9388 case UNGE: /* GEU - CF=0 - fails on unordered */
9390 *second_code = UNORDERED;
9392 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
9394 *second_code = UNORDERED;
9399 if (!TARGET_IEEE_FP)
9401 *second_code = UNKNOWN;
9402 *bypass_code = UNKNOWN;
9406 /* Return cost of comparison done fcom + arithmetics operations on AX.
9407 All following functions do use number of instructions as a cost metrics.
9408 In future this should be tweaked to compute bytes for optimize_size and
9409 take into account performance of various instructions on various CPUs. */
9411 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
9413 if (!TARGET_IEEE_FP)
9415 /* The cost of code output by ix86_expand_fp_compare. */
9443 /* Return cost of comparison done using fcomi operation.
9444 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9446 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
9448 enum rtx_code bypass_code, first_code, second_code;
9449 /* Return arbitrarily high cost when instruction is not supported - this
9450 prevents gcc from using it. */
9453 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9454 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
9457 /* Return cost of comparison done using sahf operation.
9458 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9460 ix86_fp_comparison_sahf_cost (enum rtx_code code)
9462 enum rtx_code bypass_code, first_code, second_code;
9463 /* Return arbitrarily high cost when instruction is not preferred - this
9464 avoids gcc from using it. */
9465 if (!TARGET_USE_SAHF && !optimize_size)
9467 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9468 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
9471 /* Compute cost of the comparison done using any method.
9472 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9474 ix86_fp_comparison_cost (enum rtx_code code)
9476 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
9479 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
9480 sahf_cost = ix86_fp_comparison_sahf_cost (code);
9482 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
9483 if (min > sahf_cost)
9485 if (min > fcomi_cost)
9490 /* Generate insn patterns to do a floating point compare of OPERANDS. */
9493 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
9494 rtx *second_test, rtx *bypass_test)
9496 enum machine_mode fpcmp_mode, intcmp_mode;
9498 int cost = ix86_fp_comparison_cost (code);
9499 enum rtx_code bypass_code, first_code, second_code;
9501 fpcmp_mode = ix86_fp_compare_mode (code);
9502 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
9505 *second_test = NULL_RTX;
9507 *bypass_test = NULL_RTX;
9509 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9511 /* Do fcomi/sahf based test when profitable. */
9512 if ((bypass_code == UNKNOWN || bypass_test)
9513 && (second_code == UNKNOWN || second_test)
9514 && ix86_fp_comparison_arithmetics_cost (code) > cost)
9518 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9519 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
9525 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9526 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9528 scratch = gen_reg_rtx (HImode);
9529 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9530 emit_insn (gen_x86_sahf_1 (scratch));
9533 /* The FP codes work out to act like unsigned. */
9534 intcmp_mode = fpcmp_mode;
9536 if (bypass_code != UNKNOWN)
9537 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
9538 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9540 if (second_code != UNKNOWN)
9541 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
9542 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9547 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
9548 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9549 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9551 scratch = gen_reg_rtx (HImode);
9552 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9554 /* In the unordered case, we have to check C2 for NaN's, which
9555 doesn't happen to work out to anything nice combination-wise.
9556 So do some bit twiddling on the value we've got in AH to come
9557 up with an appropriate set of condition codes. */
9559 intcmp_mode = CCNOmode;
9564 if (code == GT || !TARGET_IEEE_FP)
9566 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
9571 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9572 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9573 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
9574 intcmp_mode = CCmode;
9580 if (code == LT && TARGET_IEEE_FP)
9582 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9583 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
9584 intcmp_mode = CCmode;
9589 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
9595 if (code == GE || !TARGET_IEEE_FP)
9597 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
9602 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9603 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
9610 if (code == LE && TARGET_IEEE_FP)
9612 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9613 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9614 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
9615 intcmp_mode = CCmode;
9620 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
9626 if (code == EQ && TARGET_IEEE_FP)
9628 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9629 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
9630 intcmp_mode = CCmode;
9635 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
9642 if (code == NE && TARGET_IEEE_FP)
9644 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9645 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
9651 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
9657 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
9661 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
9670 /* Return the test that should be put into the flags user, i.e.
9671 the bcc, scc, or cmov instruction. */
9672 return gen_rtx_fmt_ee (code, VOIDmode,
9673 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9678 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
9681 op0 = ix86_compare_op0;
9682 op1 = ix86_compare_op1;
9685 *second_test = NULL_RTX;
9687 *bypass_test = NULL_RTX;
9689 if (ix86_compare_emitted)
9691 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
9692 ix86_compare_emitted = NULL_RTX;
9694 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
9695 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
9696 second_test, bypass_test);
9698 ret = ix86_expand_int_compare (code, op0, op1);
9703 /* Return true if the CODE will result in nontrivial jump sequence. */
9705 ix86_fp_jump_nontrivial_p (enum rtx_code code)
9707 enum rtx_code bypass_code, first_code, second_code;
9710 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9711 return bypass_code != UNKNOWN || second_code != UNKNOWN;
9715 ix86_expand_branch (enum rtx_code code, rtx label)
9719 switch (GET_MODE (ix86_compare_op0))
9725 tmp = ix86_expand_compare (code, NULL, NULL);
9726 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9727 gen_rtx_LABEL_REF (VOIDmode, label),
9729 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
9738 enum rtx_code bypass_code, first_code, second_code;
9740 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
9743 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9745 /* Check whether we will use the natural sequence with one jump. If
9746 so, we can expand jump early. Otherwise delay expansion by
9747 creating compound insn to not confuse optimizers. */
9748 if (bypass_code == UNKNOWN && second_code == UNKNOWN
9751 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
9752 gen_rtx_LABEL_REF (VOIDmode, label),
9753 pc_rtx, NULL_RTX, NULL_RTX);
9757 tmp = gen_rtx_fmt_ee (code, VOIDmode,
9758 ix86_compare_op0, ix86_compare_op1);
9759 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9760 gen_rtx_LABEL_REF (VOIDmode, label),
9762 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
9764 use_fcomi = ix86_use_fcomi_compare (code);
9765 vec = rtvec_alloc (3 + !use_fcomi);
9766 RTVEC_ELT (vec, 0) = tmp;
9768 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
9770 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
9773 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
9775 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
9784 /* Expand DImode branch into multiple compare+branch. */
9786 rtx lo[2], hi[2], label2;
9787 enum rtx_code code1, code2, code3;
9788 enum machine_mode submode;
9790 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
9792 tmp = ix86_compare_op0;
9793 ix86_compare_op0 = ix86_compare_op1;
9794 ix86_compare_op1 = tmp;
9795 code = swap_condition (code);
9797 if (GET_MODE (ix86_compare_op0) == DImode)
9799 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
9800 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
9805 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
9806 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
9810 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
9811 avoid two branches. This costs one extra insn, so disable when
9812 optimizing for size. */
9814 if ((code == EQ || code == NE)
9816 || hi[1] == const0_rtx || lo[1] == const0_rtx))
9821 if (hi[1] != const0_rtx)
9822 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
9823 NULL_RTX, 0, OPTAB_WIDEN);
9826 if (lo[1] != const0_rtx)
9827 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
9828 NULL_RTX, 0, OPTAB_WIDEN);
9830 tmp = expand_binop (submode, ior_optab, xor1, xor0,
9831 NULL_RTX, 0, OPTAB_WIDEN);
9833 ix86_compare_op0 = tmp;
9834 ix86_compare_op1 = const0_rtx;
9835 ix86_expand_branch (code, label);
9839 /* Otherwise, if we are doing less-than or greater-or-equal-than,
9840 op1 is a constant and the low word is zero, then we can just
9841 examine the high word. */
9843 if (GET_CODE (hi[1]) == CONST_INT && lo[1] == const0_rtx)
9846 case LT: case LTU: case GE: case GEU:
9847 ix86_compare_op0 = hi[0];
9848 ix86_compare_op1 = hi[1];
9849 ix86_expand_branch (code, label);
9855 /* Otherwise, we need two or three jumps. */
9857 label2 = gen_label_rtx ();
9860 code2 = swap_condition (code);
9861 code3 = unsigned_condition (code);
9865 case LT: case GT: case LTU: case GTU:
9868 case LE: code1 = LT; code2 = GT; break;
9869 case GE: code1 = GT; code2 = LT; break;
9870 case LEU: code1 = LTU; code2 = GTU; break;
9871 case GEU: code1 = GTU; code2 = LTU; break;
9873 case EQ: code1 = UNKNOWN; code2 = NE; break;
9874 case NE: code2 = UNKNOWN; break;
9882 * if (hi(a) < hi(b)) goto true;
9883 * if (hi(a) > hi(b)) goto false;
9884 * if (lo(a) < lo(b)) goto true;
9888 ix86_compare_op0 = hi[0];
9889 ix86_compare_op1 = hi[1];
9891 if (code1 != UNKNOWN)
9892 ix86_expand_branch (code1, label);
9893 if (code2 != UNKNOWN)
9894 ix86_expand_branch (code2, label2);
9896 ix86_compare_op0 = lo[0];
9897 ix86_compare_op1 = lo[1];
9898 ix86_expand_branch (code3, label);
9900 if (code2 != UNKNOWN)
9901 emit_label (label2);
9910 /* Split branch based on floating point condition. */
9912 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
9913 rtx target1, rtx target2, rtx tmp, rtx pushed)
9916 rtx label = NULL_RTX;
9918 int bypass_probability = -1, second_probability = -1, probability = -1;
9921 if (target2 != pc_rtx)
9924 code = reverse_condition_maybe_unordered (code);
9929 condition = ix86_expand_fp_compare (code, op1, op2,
9930 tmp, &second, &bypass);
9932 /* Remove pushed operand from stack. */
9934 ix86_free_from_memory (GET_MODE (pushed));
9936 if (split_branch_probability >= 0)
9938 /* Distribute the probabilities across the jumps.
9939 Assume the BYPASS and SECOND to be always test
9941 probability = split_branch_probability;
9943 /* Value of 1 is low enough to make no need for probability
9944 to be updated. Later we may run some experiments and see
9945 if unordered values are more frequent in practice. */
9947 bypass_probability = 1;
9949 second_probability = 1;
9951 if (bypass != NULL_RTX)
9953 label = gen_label_rtx ();
9954 i = emit_jump_insn (gen_rtx_SET
9956 gen_rtx_IF_THEN_ELSE (VOIDmode,
9958 gen_rtx_LABEL_REF (VOIDmode,
9961 if (bypass_probability >= 0)
9963 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9964 GEN_INT (bypass_probability),
9967 i = emit_jump_insn (gen_rtx_SET
9969 gen_rtx_IF_THEN_ELSE (VOIDmode,
9970 condition, target1, target2)));
9971 if (probability >= 0)
9973 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9974 GEN_INT (probability),
9976 if (second != NULL_RTX)
9978 i = emit_jump_insn (gen_rtx_SET
9980 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
9982 if (second_probability >= 0)
9984 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9985 GEN_INT (second_probability),
9988 if (label != NULL_RTX)
9993 ix86_expand_setcc (enum rtx_code code, rtx dest)
9995 rtx ret, tmp, tmpreg, equiv;
9996 rtx second_test, bypass_test;
9998 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
9999 return 0; /* FAIL */
10001 gcc_assert (GET_MODE (dest) == QImode);
10003 ret = ix86_expand_compare (code, &second_test, &bypass_test);
10004 PUT_MODE (ret, QImode);
10009 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
10010 if (bypass_test || second_test)
10012 rtx test = second_test;
10014 rtx tmp2 = gen_reg_rtx (QImode);
10017 gcc_assert (!second_test);
10018 test = bypass_test;
10020 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
10022 PUT_MODE (test, QImode);
10023 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
10026 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
10028 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
10031 /* Attach a REG_EQUAL note describing the comparison result. */
10032 if (ix86_compare_op0 && ix86_compare_op1)
10034 equiv = simplify_gen_relational (code, QImode,
10035 GET_MODE (ix86_compare_op0),
10036 ix86_compare_op0, ix86_compare_op1);
10037 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
10040 return 1; /* DONE */
10043 /* Expand comparison setting or clearing carry flag. Return true when
10044 successful and set pop for the operation. */
10046 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
10048 enum machine_mode mode =
10049 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
10051 /* Do not handle DImode compares that go trought special path. Also we can't
10052 deal with FP compares yet. This is possible to add. */
10053 if (mode == (TARGET_64BIT ? TImode : DImode))
10055 if (FLOAT_MODE_P (mode))
10057 rtx second_test = NULL, bypass_test = NULL;
10058 rtx compare_op, compare_seq;
10060 /* Shortcut: following common codes never translate into carry flag compares. */
10061 if (code == EQ || code == NE || code == UNEQ || code == LTGT
10062 || code == ORDERED || code == UNORDERED)
10065 /* These comparisons require zero flag; swap operands so they won't. */
10066 if ((code == GT || code == UNLE || code == LE || code == UNGT)
10067 && !TARGET_IEEE_FP)
10072 code = swap_condition (code);
10075 /* Try to expand the comparison and verify that we end up with carry flag
10076 based comparison. This is fails to be true only when we decide to expand
10077 comparison using arithmetic that is not too common scenario. */
10079 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
10080 &second_test, &bypass_test);
10081 compare_seq = get_insns ();
10084 if (second_test || bypass_test)
10086 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10087 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10088 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
10090 code = GET_CODE (compare_op);
10091 if (code != LTU && code != GEU)
10093 emit_insn (compare_seq);
10097 if (!INTEGRAL_MODE_P (mode))
10105 /* Convert a==0 into (unsigned)a<1. */
10108 if (op1 != const0_rtx)
10111 code = (code == EQ ? LTU : GEU);
10114 /* Convert a>b into b<a or a>=b-1. */
10117 if (GET_CODE (op1) == CONST_INT)
10119 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
10120 /* Bail out on overflow. We still can swap operands but that
10121 would force loading of the constant into register. */
10122 if (op1 == const0_rtx
10123 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
10125 code = (code == GTU ? GEU : LTU);
10132 code = (code == GTU ? LTU : GEU);
10136 /* Convert a>=0 into (unsigned)a<0x80000000. */
10139 if (mode == DImode || op1 != const0_rtx)
10141 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
10142 code = (code == LT ? GEU : LTU);
10146 if (mode == DImode || op1 != constm1_rtx)
10148 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
10149 code = (code == LE ? GEU : LTU);
10155 /* Swapping operands may cause constant to appear as first operand. */
10156 if (!nonimmediate_operand (op0, VOIDmode))
10158 if (no_new_pseudos)
10160 op0 = force_reg (mode, op0);
10162 ix86_compare_op0 = op0;
10163 ix86_compare_op1 = op1;
10164 *pop = ix86_expand_compare (code, NULL, NULL);
10165 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
10170 ix86_expand_int_movcc (rtx operands[])
10172 enum rtx_code code = GET_CODE (operands[1]), compare_code;
10173 rtx compare_seq, compare_op;
10174 rtx second_test, bypass_test;
10175 enum machine_mode mode = GET_MODE (operands[0]);
10176 bool sign_bit_compare_p = false;;
10179 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10180 compare_seq = get_insns ();
10183 compare_code = GET_CODE (compare_op);
10185 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
10186 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
10187 sign_bit_compare_p = true;
10189 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
10190 HImode insns, we'd be swallowed in word prefix ops. */
10192 if ((mode != HImode || TARGET_FAST_PREFIX)
10193 && (mode != (TARGET_64BIT ? TImode : DImode))
10194 && GET_CODE (operands[2]) == CONST_INT
10195 && GET_CODE (operands[3]) == CONST_INT)
10197 rtx out = operands[0];
10198 HOST_WIDE_INT ct = INTVAL (operands[2]);
10199 HOST_WIDE_INT cf = INTVAL (operands[3]);
10200 HOST_WIDE_INT diff;
10203 /* Sign bit compares are better done using shifts than we do by using
10205 if (sign_bit_compare_p
10206 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
10207 ix86_compare_op1, &compare_op))
10209 /* Detect overlap between destination and compare sources. */
10212 if (!sign_bit_compare_p)
10214 bool fpcmp = false;
10216 compare_code = GET_CODE (compare_op);
10218 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10219 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10222 compare_code = ix86_fp_compare_code_to_integer (compare_code);
10225 /* To simplify rest of code, restrict to the GEU case. */
10226 if (compare_code == LTU)
10228 HOST_WIDE_INT tmp = ct;
10231 compare_code = reverse_condition (compare_code);
10232 code = reverse_condition (code);
10237 PUT_CODE (compare_op,
10238 reverse_condition_maybe_unordered
10239 (GET_CODE (compare_op)));
10241 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
10245 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
10246 || reg_overlap_mentioned_p (out, ix86_compare_op1))
10247 tmp = gen_reg_rtx (mode);
10249 if (mode == DImode)
10250 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
10252 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
10256 if (code == GT || code == GE)
10257 code = reverse_condition (code);
10260 HOST_WIDE_INT tmp = ct;
10265 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
10266 ix86_compare_op1, VOIDmode, 0, -1);
10279 tmp = expand_simple_binop (mode, PLUS,
10281 copy_rtx (tmp), 1, OPTAB_DIRECT);
10292 tmp = expand_simple_binop (mode, IOR,
10294 copy_rtx (tmp), 1, OPTAB_DIRECT);
10296 else if (diff == -1 && ct)
10306 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10308 tmp = expand_simple_binop (mode, PLUS,
10309 copy_rtx (tmp), GEN_INT (cf),
10310 copy_rtx (tmp), 1, OPTAB_DIRECT);
10318 * andl cf - ct, dest
10328 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10331 tmp = expand_simple_binop (mode, AND,
10333 gen_int_mode (cf - ct, mode),
10334 copy_rtx (tmp), 1, OPTAB_DIRECT);
10336 tmp = expand_simple_binop (mode, PLUS,
10337 copy_rtx (tmp), GEN_INT (ct),
10338 copy_rtx (tmp), 1, OPTAB_DIRECT);
10341 if (!rtx_equal_p (tmp, out))
10342 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
10344 return 1; /* DONE */
10350 tmp = ct, ct = cf, cf = tmp;
10352 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10354 /* We may be reversing unordered compare to normal compare, that
10355 is not valid in general (we may convert non-trapping condition
10356 to trapping one), however on i386 we currently emit all
10357 comparisons unordered. */
10358 compare_code = reverse_condition_maybe_unordered (compare_code);
10359 code = reverse_condition_maybe_unordered (code);
10363 compare_code = reverse_condition (compare_code);
10364 code = reverse_condition (code);
10368 compare_code = UNKNOWN;
10369 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
10370 && GET_CODE (ix86_compare_op1) == CONST_INT)
10372 if (ix86_compare_op1 == const0_rtx
10373 && (code == LT || code == GE))
10374 compare_code = code;
10375 else if (ix86_compare_op1 == constm1_rtx)
10379 else if (code == GT)
10384 /* Optimize dest = (op0 < 0) ? -1 : cf. */
10385 if (compare_code != UNKNOWN
10386 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
10387 && (cf == -1 || ct == -1))
10389 /* If lea code below could be used, only optimize
10390 if it results in a 2 insn sequence. */
10392 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
10393 || diff == 3 || diff == 5 || diff == 9)
10394 || (compare_code == LT && ct == -1)
10395 || (compare_code == GE && cf == -1))
10398 * notl op1 (if necessary)
10406 code = reverse_condition (code);
10409 out = emit_store_flag (out, code, ix86_compare_op0,
10410 ix86_compare_op1, VOIDmode, 0, -1);
10412 out = expand_simple_binop (mode, IOR,
10414 out, 1, OPTAB_DIRECT);
10415 if (out != operands[0])
10416 emit_move_insn (operands[0], out);
10418 return 1; /* DONE */
10423 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
10424 || diff == 3 || diff == 5 || diff == 9)
10425 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
10427 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
10433 * lea cf(dest*(ct-cf)),dest
10437 * This also catches the degenerate setcc-only case.
10443 out = emit_store_flag (out, code, ix86_compare_op0,
10444 ix86_compare_op1, VOIDmode, 0, 1);
10447 /* On x86_64 the lea instruction operates on Pmode, so we need
10448 to get arithmetics done in proper mode to match. */
10450 tmp = copy_rtx (out);
10454 out1 = copy_rtx (out);
10455 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
10459 tmp = gen_rtx_PLUS (mode, tmp, out1);
10465 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
10468 if (!rtx_equal_p (tmp, out))
10471 out = force_operand (tmp, copy_rtx (out));
10473 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
10475 if (!rtx_equal_p (out, operands[0]))
10476 emit_move_insn (operands[0], copy_rtx (out));
10478 return 1; /* DONE */
10482 * General case: Jumpful:
10483 * xorl dest,dest cmpl op1, op2
10484 * cmpl op1, op2 movl ct, dest
10485 * setcc dest jcc 1f
10486 * decl dest movl cf, dest
10487 * andl (cf-ct),dest 1:
10490 * Size 20. Size 14.
10492 * This is reasonably steep, but branch mispredict costs are
10493 * high on modern cpus, so consider failing only if optimizing
10497 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10498 && BRANCH_COST >= 2)
10504 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10505 /* We may be reversing unordered compare to normal compare,
10506 that is not valid in general (we may convert non-trapping
10507 condition to trapping one), however on i386 we currently
10508 emit all comparisons unordered. */
10509 code = reverse_condition_maybe_unordered (code);
10512 code = reverse_condition (code);
10513 if (compare_code != UNKNOWN)
10514 compare_code = reverse_condition (compare_code);
10518 if (compare_code != UNKNOWN)
10520 /* notl op1 (if needed)
10525 For x < 0 (resp. x <= -1) there will be no notl,
10526 so if possible swap the constants to get rid of the
10528 True/false will be -1/0 while code below (store flag
10529 followed by decrement) is 0/-1, so the constants need
10530 to be exchanged once more. */
10532 if (compare_code == GE || !cf)
10534 code = reverse_condition (code);
10539 HOST_WIDE_INT tmp = cf;
10544 out = emit_store_flag (out, code, ix86_compare_op0,
10545 ix86_compare_op1, VOIDmode, 0, -1);
10549 out = emit_store_flag (out, code, ix86_compare_op0,
10550 ix86_compare_op1, VOIDmode, 0, 1);
10552 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
10553 copy_rtx (out), 1, OPTAB_DIRECT);
10556 out = expand_simple_binop (mode, AND, copy_rtx (out),
10557 gen_int_mode (cf - ct, mode),
10558 copy_rtx (out), 1, OPTAB_DIRECT);
10560 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
10561 copy_rtx (out), 1, OPTAB_DIRECT);
10562 if (!rtx_equal_p (out, operands[0]))
10563 emit_move_insn (operands[0], copy_rtx (out));
10565 return 1; /* DONE */
10569 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10571 /* Try a few things more with specific constants and a variable. */
10574 rtx var, orig_out, out, tmp;
10576 if (BRANCH_COST <= 2)
10577 return 0; /* FAIL */
10579 /* If one of the two operands is an interesting constant, load a
10580 constant with the above and mask it in with a logical operation. */
10582 if (GET_CODE (operands[2]) == CONST_INT)
10585 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
10586 operands[3] = constm1_rtx, op = and_optab;
10587 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
10588 operands[3] = const0_rtx, op = ior_optab;
10590 return 0; /* FAIL */
10592 else if (GET_CODE (operands[3]) == CONST_INT)
10595 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
10596 operands[2] = constm1_rtx, op = and_optab;
10597 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
10598 operands[2] = const0_rtx, op = ior_optab;
10600 return 0; /* FAIL */
10603 return 0; /* FAIL */
10605 orig_out = operands[0];
10606 tmp = gen_reg_rtx (mode);
10609 /* Recurse to get the constant loaded. */
10610 if (ix86_expand_int_movcc (operands) == 0)
10611 return 0; /* FAIL */
10613 /* Mask in the interesting variable. */
10614 out = expand_binop (mode, op, var, tmp, orig_out, 0,
10616 if (!rtx_equal_p (out, orig_out))
10617 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
10619 return 1; /* DONE */
10623 * For comparison with above,
10633 if (! nonimmediate_operand (operands[2], mode))
10634 operands[2] = force_reg (mode, operands[2]);
10635 if (! nonimmediate_operand (operands[3], mode))
10636 operands[3] = force_reg (mode, operands[3]);
10638 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
10640 rtx tmp = gen_reg_rtx (mode);
10641 emit_move_insn (tmp, operands[3]);
10644 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
10646 rtx tmp = gen_reg_rtx (mode);
10647 emit_move_insn (tmp, operands[2]);
10651 if (! register_operand (operands[2], VOIDmode)
10653 || ! register_operand (operands[3], VOIDmode)))
10654 operands[2] = force_reg (mode, operands[2]);
10657 && ! register_operand (operands[3], VOIDmode))
10658 operands[3] = force_reg (mode, operands[3]);
10660 emit_insn (compare_seq);
10661 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10662 gen_rtx_IF_THEN_ELSE (mode,
10663 compare_op, operands[2],
10666 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
10667 gen_rtx_IF_THEN_ELSE (mode,
10669 copy_rtx (operands[3]),
10670 copy_rtx (operands[0]))));
10672 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
10673 gen_rtx_IF_THEN_ELSE (mode,
10675 copy_rtx (operands[2]),
10676 copy_rtx (operands[0]))));
10678 return 1; /* DONE */
10681 /* Swap, force into registers, or otherwise massage the two operands
10682 to an sse comparison with a mask result. Thus we differ a bit from
10683 ix86_prepare_fp_compare_args which expects to produce a flags result.
10685 The DEST operand exists to help determine whether to commute commutative
10686 operators. The POP0/POP1 operands are updated in place. The new
10687 comparison code is returned, or UNKNOWN if not implementable. */
10689 static enum rtx_code
10690 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
10691 rtx *pop0, rtx *pop1)
10699 /* We have no LTGT as an operator. We could implement it with
10700 NE & ORDERED, but this requires an extra temporary. It's
10701 not clear that it's worth it. */
10708 /* These are supported directly. */
10715 /* For commutative operators, try to canonicalize the destination
10716 operand to be first in the comparison - this helps reload to
10717 avoid extra moves. */
10718 if (!dest || !rtx_equal_p (dest, *pop1))
10726 /* These are not supported directly. Swap the comparison operands
10727 to transform into something that is supported. */
10731 code = swap_condition (code);
10735 gcc_unreachable ();
10741 /* Detect conditional moves that exactly match min/max operational
10742 semantics. Note that this is IEEE safe, as long as we don't
10743 interchange the operands.
10745 Returns FALSE if this conditional move doesn't match a MIN/MAX,
10746 and TRUE if the operation is successful and instructions are emitted. */
10749 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
10750 rtx cmp_op1, rtx if_true, rtx if_false)
10752 enum machine_mode mode;
10758 else if (code == UNGE)
10761 if_true = if_false;
10767 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
10769 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
10774 mode = GET_MODE (dest);
10776 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
10777 but MODE may be a vector mode and thus not appropriate. */
10778 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
10780 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
10783 if_true = force_reg (mode, if_true);
10784 v = gen_rtvec (2, if_true, if_false);
10785 tmp = gen_rtx_UNSPEC (mode, v, u);
10789 code = is_min ? SMIN : SMAX;
10790 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
10793 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
10797 /* Expand an sse vector comparison. Return the register with the result. */
10800 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
10801 rtx op_true, rtx op_false)
10803 enum machine_mode mode = GET_MODE (dest);
10806 cmp_op0 = force_reg (mode, cmp_op0);
10807 if (!nonimmediate_operand (cmp_op1, mode))
10808 cmp_op1 = force_reg (mode, cmp_op1);
10811 || reg_overlap_mentioned_p (dest, op_true)
10812 || reg_overlap_mentioned_p (dest, op_false))
10813 dest = gen_reg_rtx (mode);
10815 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
10816 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10821 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
10822 operations. This is used for both scalar and vector conditional moves. */
10825 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
10827 enum machine_mode mode = GET_MODE (dest);
10830 if (op_false == CONST0_RTX (mode))
10832 op_true = force_reg (mode, op_true);
10833 x = gen_rtx_AND (mode, cmp, op_true);
10834 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10836 else if (op_true == CONST0_RTX (mode))
10838 op_false = force_reg (mode, op_false);
10839 x = gen_rtx_NOT (mode, cmp);
10840 x = gen_rtx_AND (mode, x, op_false);
10841 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10845 op_true = force_reg (mode, op_true);
10846 op_false = force_reg (mode, op_false);
10848 t2 = gen_reg_rtx (mode);
10850 t3 = gen_reg_rtx (mode);
10854 x = gen_rtx_AND (mode, op_true, cmp);
10855 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
10857 x = gen_rtx_NOT (mode, cmp);
10858 x = gen_rtx_AND (mode, x, op_false);
10859 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
10861 x = gen_rtx_IOR (mode, t3, t2);
10862 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10866 /* Expand a floating-point conditional move. Return true if successful. */
10869 ix86_expand_fp_movcc (rtx operands[])
10871 enum machine_mode mode = GET_MODE (operands[0]);
10872 enum rtx_code code = GET_CODE (operands[1]);
10873 rtx tmp, compare_op, second_test, bypass_test;
10875 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
10877 enum machine_mode cmode;
10879 /* Since we've no cmove for sse registers, don't force bad register
10880 allocation just to gain access to it. Deny movcc when the
10881 comparison mode doesn't match the move mode. */
10882 cmode = GET_MODE (ix86_compare_op0);
10883 if (cmode == VOIDmode)
10884 cmode = GET_MODE (ix86_compare_op1);
10888 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
10890 &ix86_compare_op1);
10891 if (code == UNKNOWN)
10894 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
10895 ix86_compare_op1, operands[2],
10899 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
10900 ix86_compare_op1, operands[2], operands[3]);
10901 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
10905 /* The floating point conditional move instructions don't directly
10906 support conditions resulting from a signed integer comparison. */
10908 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10910 /* The floating point conditional move instructions don't directly
10911 support signed integer comparisons. */
10913 if (!fcmov_comparison_operator (compare_op, VOIDmode))
10915 gcc_assert (!second_test && !bypass_test);
10916 tmp = gen_reg_rtx (QImode);
10917 ix86_expand_setcc (code, tmp);
10919 ix86_compare_op0 = tmp;
10920 ix86_compare_op1 = const0_rtx;
10921 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10923 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
10925 tmp = gen_reg_rtx (mode);
10926 emit_move_insn (tmp, operands[3]);
10929 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
10931 tmp = gen_reg_rtx (mode);
10932 emit_move_insn (tmp, operands[2]);
10936 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10937 gen_rtx_IF_THEN_ELSE (mode, compare_op,
10938 operands[2], operands[3])));
10940 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10941 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
10942 operands[3], operands[0])));
10944 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10945 gen_rtx_IF_THEN_ELSE (mode, second_test,
10946 operands[2], operands[0])));
10951 /* Expand a floating-point vector conditional move; a vcond operation
10952 rather than a movcc operation. */
10955 ix86_expand_fp_vcond (rtx operands[])
10957 enum rtx_code code = GET_CODE (operands[3]);
10960 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
10961 &operands[4], &operands[5]);
10962 if (code == UNKNOWN)
10965 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
10966 operands[5], operands[1], operands[2]))
10969 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
10970 operands[1], operands[2]);
10971 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
10975 /* Expand a signed integral vector conditional move. */
10978 ix86_expand_int_vcond (rtx operands[])
10980 enum machine_mode mode = GET_MODE (operands[0]);
10981 enum rtx_code code = GET_CODE (operands[3]);
10982 bool negate = false;
10985 cop0 = operands[4];
10986 cop1 = operands[5];
10988 /* Canonicalize the comparison to EQ, GT, GTU. */
10999 code = reverse_condition (code);
11005 code = reverse_condition (code);
11011 code = swap_condition (code);
11012 x = cop0, cop0 = cop1, cop1 = x;
11016 gcc_unreachable ();
11019 /* Unsigned parallel compare is not supported by the hardware. Play some
11020 tricks to turn this into a signed comparison against 0. */
11029 /* Perform a parallel modulo subtraction. */
11030 t1 = gen_reg_rtx (mode);
11031 emit_insn (gen_subv4si3 (t1, cop0, cop1));
11033 /* Extract the original sign bit of op0. */
11034 mask = GEN_INT (-0x80000000);
11035 mask = gen_rtx_CONST_VECTOR (mode,
11036 gen_rtvec (4, mask, mask, mask, mask));
11037 mask = force_reg (mode, mask);
11038 t2 = gen_reg_rtx (mode);
11039 emit_insn (gen_andv4si3 (t2, cop0, mask));
11041 /* XOR it back into the result of the subtraction. This results
11042 in the sign bit set iff we saw unsigned underflow. */
11043 x = gen_reg_rtx (mode);
11044 emit_insn (gen_xorv4si3 (x, t1, t2));
11052 /* Perform a parallel unsigned saturating subtraction. */
11053 x = gen_reg_rtx (mode);
11054 emit_insn (gen_rtx_SET (VOIDmode, x,
11055 gen_rtx_US_MINUS (mode, cop0, cop1)));
11062 gcc_unreachable ();
11066 cop1 = CONST0_RTX (mode);
11069 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
11070 operands[1+negate], operands[2-negate]);
11072 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
11073 operands[2-negate]);
11077 /* Expand conditional increment or decrement using adb/sbb instructions.
11078 The default case using setcc followed by the conditional move can be
11079 done by generic code. */
11081 ix86_expand_int_addcc (rtx operands[])
11083 enum rtx_code code = GET_CODE (operands[1]);
11085 rtx val = const0_rtx;
11086 bool fpcmp = false;
11087 enum machine_mode mode = GET_MODE (operands[0]);
11089 if (operands[3] != const1_rtx
11090 && operands[3] != constm1_rtx)
11092 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
11093 ix86_compare_op1, &compare_op))
11095 code = GET_CODE (compare_op);
11097 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11098 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11101 code = ix86_fp_compare_code_to_integer (code);
11108 PUT_CODE (compare_op,
11109 reverse_condition_maybe_unordered
11110 (GET_CODE (compare_op)));
11112 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
11114 PUT_MODE (compare_op, mode);
11116 /* Construct either adc or sbb insn. */
11117 if ((code == LTU) == (operands[3] == constm1_rtx))
11119 switch (GET_MODE (operands[0]))
11122 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
11125 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
11128 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
11131 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
11134 gcc_unreachable ();
11139 switch (GET_MODE (operands[0]))
11142 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
11145 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
11148 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
11151 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
11154 gcc_unreachable ();
11157 return 1; /* DONE */
11161 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
11162 works for floating pointer parameters and nonoffsetable memories.
11163 For pushes, it returns just stack offsets; the values will be saved
11164 in the right order. Maximally three parts are generated. */
11167 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
11172 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
11174 size = (GET_MODE_SIZE (mode) + 4) / 8;
11176 gcc_assert (GET_CODE (operand) != REG || !MMX_REGNO_P (REGNO (operand)));
11177 gcc_assert (size >= 2 && size <= 3);
11179 /* Optimize constant pool reference to immediates. This is used by fp
11180 moves, that force all constants to memory to allow combining. */
11181 if (GET_CODE (operand) == MEM && MEM_READONLY_P (operand))
11183 rtx tmp = maybe_get_pool_constant (operand);
11188 if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand))
11190 /* The only non-offsetable memories we handle are pushes. */
11191 int ok = push_operand (operand, VOIDmode);
11195 operand = copy_rtx (operand);
11196 PUT_MODE (operand, Pmode);
11197 parts[0] = parts[1] = parts[2] = operand;
11201 if (GET_CODE (operand) == CONST_VECTOR)
11203 enum machine_mode imode = int_mode_for_mode (mode);
11204 /* Caution: if we looked through a constant pool memory above,
11205 the operand may actually have a different mode now. That's
11206 ok, since we want to pun this all the way back to an integer. */
11207 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
11208 gcc_assert (operand != NULL);
11214 if (mode == DImode)
11215 split_di (&operand, 1, &parts[0], &parts[1]);
11218 if (REG_P (operand))
11220 gcc_assert (reload_completed);
11221 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
11222 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
11224 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
11226 else if (offsettable_memref_p (operand))
11228 operand = adjust_address (operand, SImode, 0);
11229 parts[0] = operand;
11230 parts[1] = adjust_address (operand, SImode, 4);
11232 parts[2] = adjust_address (operand, SImode, 8);
11234 else if (GET_CODE (operand) == CONST_DOUBLE)
11239 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11243 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
11244 parts[2] = gen_int_mode (l[2], SImode);
11247 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
11250 gcc_unreachable ();
11252 parts[1] = gen_int_mode (l[1], SImode);
11253 parts[0] = gen_int_mode (l[0], SImode);
11256 gcc_unreachable ();
11261 if (mode == TImode)
11262 split_ti (&operand, 1, &parts[0], &parts[1]);
11263 if (mode == XFmode || mode == TFmode)
11265 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
11266 if (REG_P (operand))
11268 gcc_assert (reload_completed);
11269 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
11270 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
11272 else if (offsettable_memref_p (operand))
11274 operand = adjust_address (operand, DImode, 0);
11275 parts[0] = operand;
11276 parts[1] = adjust_address (operand, upper_mode, 8);
11278 else if (GET_CODE (operand) == CONST_DOUBLE)
11283 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11284 real_to_target (l, &r, mode);
11286 /* Do not use shift by 32 to avoid warning on 32bit systems. */
11287 if (HOST_BITS_PER_WIDE_INT >= 64)
11290 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
11291 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
11294 parts[0] = immed_double_const (l[0], l[1], DImode);
11296 if (upper_mode == SImode)
11297 parts[1] = gen_int_mode (l[2], SImode);
11298 else if (HOST_BITS_PER_WIDE_INT >= 64)
11301 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
11302 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
11305 parts[1] = immed_double_const (l[2], l[3], DImode);
11308 gcc_unreachable ();
11315 /* Emit insns to perform a move or push of DI, DF, and XF values.
11316 Return false when normal moves are needed; true when all required
11317 insns have been emitted. Operands 2-4 contain the input values
11318 int the correct order; operands 5-7 contain the output values. */
11321 ix86_split_long_move (rtx operands[])
11326 int collisions = 0;
11327 enum machine_mode mode = GET_MODE (operands[0]);
11329 /* The DFmode expanders may ask us to move double.
11330 For 64bit target this is single move. By hiding the fact
11331 here we simplify i386.md splitters. */
11332 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
11334 /* Optimize constant pool reference to immediates. This is used by
11335 fp moves, that force all constants to memory to allow combining. */
11337 if (GET_CODE (operands[1]) == MEM
11338 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
11339 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
11340 operands[1] = get_pool_constant (XEXP (operands[1], 0));
11341 if (push_operand (operands[0], VOIDmode))
11343 operands[0] = copy_rtx (operands[0]);
11344 PUT_MODE (operands[0], Pmode);
11347 operands[0] = gen_lowpart (DImode, operands[0]);
11348 operands[1] = gen_lowpart (DImode, operands[1]);
11349 emit_move_insn (operands[0], operands[1]);
11353 /* The only non-offsettable memory we handle is push. */
11354 if (push_operand (operands[0], VOIDmode))
11357 gcc_assert (GET_CODE (operands[0]) != MEM
11358 || offsettable_memref_p (operands[0]));
11360 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
11361 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
11363 /* When emitting push, take care for source operands on the stack. */
11364 if (push && GET_CODE (operands[1]) == MEM
11365 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
11368 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
11369 XEXP (part[1][2], 0));
11370 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
11371 XEXP (part[1][1], 0));
11374 /* We need to do copy in the right order in case an address register
11375 of the source overlaps the destination. */
11376 if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM)
11378 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
11380 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11383 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
11386 /* Collision in the middle part can be handled by reordering. */
11387 if (collisions == 1 && nparts == 3
11388 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11391 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
11392 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
11395 /* If there are more collisions, we can't handle it by reordering.
11396 Do an lea to the last part and use only one colliding move. */
11397 else if (collisions > 1)
11403 base = part[0][nparts - 1];
11405 /* Handle the case when the last part isn't valid for lea.
11406 Happens in 64-bit mode storing the 12-byte XFmode. */
11407 if (GET_MODE (base) != Pmode)
11408 base = gen_rtx_REG (Pmode, REGNO (base));
11410 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
11411 part[1][0] = replace_equiv_address (part[1][0], base);
11412 part[1][1] = replace_equiv_address (part[1][1],
11413 plus_constant (base, UNITS_PER_WORD));
11415 part[1][2] = replace_equiv_address (part[1][2],
11416 plus_constant (base, 8));
11426 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
11427 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
11428 emit_move_insn (part[0][2], part[1][2]);
11433 /* In 64bit mode we don't have 32bit push available. In case this is
11434 register, it is OK - we will just use larger counterpart. We also
11435 retype memory - these comes from attempt to avoid REX prefix on
11436 moving of second half of TFmode value. */
11437 if (GET_MODE (part[1][1]) == SImode)
11439 switch (GET_CODE (part[1][1]))
11442 part[1][1] = adjust_address (part[1][1], DImode, 0);
11446 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
11450 gcc_unreachable ();
11453 if (GET_MODE (part[1][0]) == SImode)
11454 part[1][0] = part[1][1];
11457 emit_move_insn (part[0][1], part[1][1]);
11458 emit_move_insn (part[0][0], part[1][0]);
11462 /* Choose correct order to not overwrite the source before it is copied. */
11463 if ((REG_P (part[0][0])
11464 && REG_P (part[1][1])
11465 && (REGNO (part[0][0]) == REGNO (part[1][1])
11467 && REGNO (part[0][0]) == REGNO (part[1][2]))))
11469 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
11473 operands[2] = part[0][2];
11474 operands[3] = part[0][1];
11475 operands[4] = part[0][0];
11476 operands[5] = part[1][2];
11477 operands[6] = part[1][1];
11478 operands[7] = part[1][0];
11482 operands[2] = part[0][1];
11483 operands[3] = part[0][0];
11484 operands[5] = part[1][1];
11485 operands[6] = part[1][0];
11492 operands[2] = part[0][0];
11493 operands[3] = part[0][1];
11494 operands[4] = part[0][2];
11495 operands[5] = part[1][0];
11496 operands[6] = part[1][1];
11497 operands[7] = part[1][2];
11501 operands[2] = part[0][0];
11502 operands[3] = part[0][1];
11503 operands[5] = part[1][0];
11504 operands[6] = part[1][1];
11508 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
11511 if (GET_CODE (operands[5]) == CONST_INT
11512 && operands[5] != const0_rtx
11513 && REG_P (operands[2]))
11515 if (GET_CODE (operands[6]) == CONST_INT
11516 && INTVAL (operands[6]) == INTVAL (operands[5]))
11517 operands[6] = operands[2];
11520 && GET_CODE (operands[7]) == CONST_INT
11521 && INTVAL (operands[7]) == INTVAL (operands[5]))
11522 operands[7] = operands[2];
11526 && GET_CODE (operands[6]) == CONST_INT
11527 && operands[6] != const0_rtx
11528 && REG_P (operands[3])
11529 && GET_CODE (operands[7]) == CONST_INT
11530 && INTVAL (operands[7]) == INTVAL (operands[6]))
11531 operands[7] = operands[3];
11534 emit_move_insn (operands[2], operands[5]);
11535 emit_move_insn (operands[3], operands[6]);
11537 emit_move_insn (operands[4], operands[7]);
11542 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
11543 left shift by a constant, either using a single shift or
11544 a sequence of add instructions. */
11547 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
11551 emit_insn ((mode == DImode
11553 : gen_adddi3) (operand, operand, operand));
11555 else if (!optimize_size
11556 && count * ix86_cost->add <= ix86_cost->shift_const)
11559 for (i=0; i<count; i++)
11561 emit_insn ((mode == DImode
11563 : gen_adddi3) (operand, operand, operand));
11567 emit_insn ((mode == DImode
11569 : gen_ashldi3) (operand, operand, GEN_INT (count)));
11573 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
11575 rtx low[2], high[2];
11577 const int single_width = mode == DImode ? 32 : 64;
11579 if (GET_CODE (operands[2]) == CONST_INT)
11581 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11582 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11584 if (count >= single_width)
11586 emit_move_insn (high[0], low[1]);
11587 emit_move_insn (low[0], const0_rtx);
11589 if (count > single_width)
11590 ix86_expand_ashl_const (high[0], count - single_width, mode);
11594 if (!rtx_equal_p (operands[0], operands[1]))
11595 emit_move_insn (operands[0], operands[1]);
11596 emit_insn ((mode == DImode
11598 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
11599 ix86_expand_ashl_const (low[0], count, mode);
11604 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11606 if (operands[1] == const1_rtx)
11608 /* Assuming we've chosen a QImode capable registers, then 1 << N
11609 can be done with two 32/64-bit shifts, no branches, no cmoves. */
11610 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
11612 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
11614 ix86_expand_clear (low[0]);
11615 ix86_expand_clear (high[0]);
11616 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
11618 d = gen_lowpart (QImode, low[0]);
11619 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
11620 s = gen_rtx_EQ (QImode, flags, const0_rtx);
11621 emit_insn (gen_rtx_SET (VOIDmode, d, s));
11623 d = gen_lowpart (QImode, high[0]);
11624 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
11625 s = gen_rtx_NE (QImode, flags, const0_rtx);
11626 emit_insn (gen_rtx_SET (VOIDmode, d, s));
11629 /* Otherwise, we can get the same results by manually performing
11630 a bit extract operation on bit 5/6, and then performing the two
11631 shifts. The two methods of getting 0/1 into low/high are exactly
11632 the same size. Avoiding the shift in the bit extract case helps
11633 pentium4 a bit; no one else seems to care much either way. */
11638 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
11639 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
11641 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
11642 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
11644 emit_insn ((mode == DImode
11646 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
11647 emit_insn ((mode == DImode
11649 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
11650 emit_move_insn (low[0], high[0]);
11651 emit_insn ((mode == DImode
11653 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
11656 emit_insn ((mode == DImode
11658 : gen_ashldi3) (low[0], low[0], operands[2]));
11659 emit_insn ((mode == DImode
11661 : gen_ashldi3) (high[0], high[0], operands[2]));
11665 if (operands[1] == constm1_rtx)
11667 /* For -1 << N, we can avoid the shld instruction, because we
11668 know that we're shifting 0...31/63 ones into a -1. */
11669 emit_move_insn (low[0], constm1_rtx);
11671 emit_move_insn (high[0], low[0]);
11673 emit_move_insn (high[0], constm1_rtx);
11677 if (!rtx_equal_p (operands[0], operands[1]))
11678 emit_move_insn (operands[0], operands[1]);
11680 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11681 emit_insn ((mode == DImode
11683 : gen_x86_64_shld) (high[0], low[0], operands[2]));
11686 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
11688 if (TARGET_CMOVE && scratch)
11690 ix86_expand_clear (scratch);
11691 emit_insn ((mode == DImode
11692 ? gen_x86_shift_adj_1
11693 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
11696 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
11700 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
11702 rtx low[2], high[2];
11704 const int single_width = mode == DImode ? 32 : 64;
11706 if (GET_CODE (operands[2]) == CONST_INT)
11708 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11709 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11711 if (count == single_width * 2 - 1)
11713 emit_move_insn (high[0], high[1]);
11714 emit_insn ((mode == DImode
11716 : gen_ashrdi3) (high[0], high[0],
11717 GEN_INT (single_width - 1)));
11718 emit_move_insn (low[0], high[0]);
11721 else if (count >= single_width)
11723 emit_move_insn (low[0], high[1]);
11724 emit_move_insn (high[0], low[0]);
11725 emit_insn ((mode == DImode
11727 : gen_ashrdi3) (high[0], high[0],
11728 GEN_INT (single_width - 1)));
11729 if (count > single_width)
11730 emit_insn ((mode == DImode
11732 : gen_ashrdi3) (low[0], low[0],
11733 GEN_INT (count - single_width)));
11737 if (!rtx_equal_p (operands[0], operands[1]))
11738 emit_move_insn (operands[0], operands[1]);
11739 emit_insn ((mode == DImode
11741 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
11742 emit_insn ((mode == DImode
11744 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
11749 if (!rtx_equal_p (operands[0], operands[1]))
11750 emit_move_insn (operands[0], operands[1]);
11752 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11754 emit_insn ((mode == DImode
11756 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
11757 emit_insn ((mode == DImode
11759 : gen_ashrdi3) (high[0], high[0], operands[2]));
11761 if (TARGET_CMOVE && scratch)
11763 emit_move_insn (scratch, high[0]);
11764 emit_insn ((mode == DImode
11766 : gen_ashrdi3) (scratch, scratch,
11767 GEN_INT (single_width - 1)));
11768 emit_insn ((mode == DImode
11769 ? gen_x86_shift_adj_1
11770 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
11774 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
11779 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
11781 rtx low[2], high[2];
11783 const int single_width = mode == DImode ? 32 : 64;
11785 if (GET_CODE (operands[2]) == CONST_INT)
11787 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11788 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11790 if (count >= single_width)
11792 emit_move_insn (low[0], high[1]);
11793 ix86_expand_clear (high[0]);
11795 if (count > single_width)
11796 emit_insn ((mode == DImode
11798 : gen_lshrdi3) (low[0], low[0],
11799 GEN_INT (count - single_width)));
11803 if (!rtx_equal_p (operands[0], operands[1]))
11804 emit_move_insn (operands[0], operands[1]);
11805 emit_insn ((mode == DImode
11807 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
11808 emit_insn ((mode == DImode
11810 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
11815 if (!rtx_equal_p (operands[0], operands[1]))
11816 emit_move_insn (operands[0], operands[1]);
11818 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11820 emit_insn ((mode == DImode
11822 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
11823 emit_insn ((mode == DImode
11825 : gen_lshrdi3) (high[0], high[0], operands[2]));
11827 /* Heh. By reversing the arguments, we can reuse this pattern. */
11828 if (TARGET_CMOVE && scratch)
11830 ix86_expand_clear (scratch);
11831 emit_insn ((mode == DImode
11832 ? gen_x86_shift_adj_1
11833 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
11837 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
11841 /* Helper function for the string operations below. Dest VARIABLE whether
11842 it is aligned to VALUE bytes. If true, jump to the label. */
11844 ix86_expand_aligntest (rtx variable, int value)
11846 rtx label = gen_label_rtx ();
11847 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
11848 if (GET_MODE (variable) == DImode)
11849 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
11851 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
11852 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
11857 /* Adjust COUNTER by the VALUE. */
11859 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
11861 if (GET_MODE (countreg) == DImode)
11862 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
11864 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
11867 /* Zero extend possibly SImode EXP to Pmode register. */
11869 ix86_zero_extend_to_Pmode (rtx exp)
11872 if (GET_MODE (exp) == VOIDmode)
11873 return force_reg (Pmode, exp);
11874 if (GET_MODE (exp) == Pmode)
11875 return copy_to_mode_reg (Pmode, exp);
11876 r = gen_reg_rtx (Pmode);
11877 emit_insn (gen_zero_extendsidi2 (r, exp));
11881 /* Expand string move (memcpy) operation. Use i386 string operations when
11882 profitable. expand_clrmem contains similar code. */
11884 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
11886 rtx srcreg, destreg, countreg, srcexp, destexp;
11887 enum machine_mode counter_mode;
11888 HOST_WIDE_INT align = 0;
11889 unsigned HOST_WIDE_INT count = 0;
11891 if (GET_CODE (align_exp) == CONST_INT)
11892 align = INTVAL (align_exp);
11894 /* Can't use any of this if the user has appropriated esi or edi. */
11895 if (global_regs[4] || global_regs[5])
11898 /* This simple hack avoids all inlining code and simplifies code below. */
11899 if (!TARGET_ALIGN_STRINGOPS)
11902 if (GET_CODE (count_exp) == CONST_INT)
11904 count = INTVAL (count_exp);
11905 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
11909 /* Figure out proper mode for counter. For 32bits it is always SImode,
11910 for 64bits use SImode when possible, otherwise DImode.
11911 Set count to number of bytes copied when known at compile time. */
11913 || GET_MODE (count_exp) == SImode
11914 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
11915 counter_mode = SImode;
11917 counter_mode = DImode;
11919 gcc_assert (counter_mode == SImode || counter_mode == DImode);
11921 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
11922 if (destreg != XEXP (dst, 0))
11923 dst = replace_equiv_address_nv (dst, destreg);
11924 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
11925 if (srcreg != XEXP (src, 0))
11926 src = replace_equiv_address_nv (src, srcreg);
11928 /* When optimizing for size emit simple rep ; movsb instruction for
11929 counts not divisible by 4, except when (movsl;)*(movsw;)?(movsb;)?
11930 sequence is shorter than mov{b,l} $count, %{ecx,cl}; rep; movsb.
11931 Sice of (movsl;)*(movsw;)?(movsb;)? sequence is
11932 count / 4 + (count & 3), the other sequence is either 4 or 7 bytes,
11933 but we don't know whether upper 24 (resp. 56) bits of %ecx will be
11934 known to be zero or not. The rep; movsb sequence causes higher
11935 register pressure though, so take that into account. */
11937 if ((!optimize || optimize_size)
11942 || (count & 3) + count / 4 > 6))))
11944 emit_insn (gen_cld ());
11945 countreg = ix86_zero_extend_to_Pmode (count_exp);
11946 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
11947 srcexp = gen_rtx_PLUS (Pmode, srcreg, countreg);
11948 emit_insn (gen_rep_mov (destreg, dst, srcreg, src, countreg,
11952 /* For constant aligned (or small unaligned) copies use rep movsl
11953 followed by code copying the rest. For PentiumPro ensure 8 byte
11954 alignment to allow rep movsl acceleration. */
11956 else if (count != 0
11958 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
11959 || optimize_size || count < (unsigned int) 64))
11961 unsigned HOST_WIDE_INT offset = 0;
11962 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
11963 rtx srcmem, dstmem;
11965 emit_insn (gen_cld ());
11966 if (count & ~(size - 1))
11968 if ((TARGET_SINGLE_STRINGOP || optimize_size) && count < 5 * 4)
11970 enum machine_mode movs_mode = size == 4 ? SImode : DImode;
11972 while (offset < (count & ~(size - 1)))
11974 srcmem = adjust_automodify_address_nv (src, movs_mode,
11976 dstmem = adjust_automodify_address_nv (dst, movs_mode,
11978 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11984 countreg = GEN_INT ((count >> (size == 4 ? 2 : 3))
11985 & (TARGET_64BIT ? -1 : 0x3fffffff));
11986 countreg = copy_to_mode_reg (counter_mode, countreg);
11987 countreg = ix86_zero_extend_to_Pmode (countreg);
11989 destexp = gen_rtx_ASHIFT (Pmode, countreg,
11990 GEN_INT (size == 4 ? 2 : 3));
11991 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
11992 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
11994 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
11995 countreg, destexp, srcexp));
11996 offset = count & ~(size - 1);
11999 if (size == 8 && (count & 0x04))
12001 srcmem = adjust_automodify_address_nv (src, SImode, srcreg,
12003 dstmem = adjust_automodify_address_nv (dst, SImode, destreg,
12005 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12010 srcmem = adjust_automodify_address_nv (src, HImode, srcreg,
12012 dstmem = adjust_automodify_address_nv (dst, HImode, destreg,
12014 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12019 srcmem = adjust_automodify_address_nv (src, QImode, srcreg,
12021 dstmem = adjust_automodify_address_nv (dst, QImode, destreg,
12023 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12026 /* The generic code based on the glibc implementation:
12027 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
12028 allowing accelerated copying there)
12029 - copy the data using rep movsl
12030 - copy the rest. */
12035 rtx srcmem, dstmem;
12036 int desired_alignment = (TARGET_PENTIUMPRO
12037 && (count == 0 || count >= (unsigned int) 260)
12038 ? 8 : UNITS_PER_WORD);
12039 /* Get rid of MEM_OFFSETs, they won't be accurate. */
12040 dst = change_address (dst, BLKmode, destreg);
12041 src = change_address (src, BLKmode, srcreg);
12043 /* In case we don't know anything about the alignment, default to
12044 library version, since it is usually equally fast and result in
12047 Also emit call when we know that the count is large and call overhead
12048 will not be important. */
12049 if (!TARGET_INLINE_ALL_STRINGOPS
12050 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12053 if (TARGET_SINGLE_STRINGOP)
12054 emit_insn (gen_cld ());
12056 countreg2 = gen_reg_rtx (Pmode);
12057 countreg = copy_to_mode_reg (counter_mode, count_exp);
12059 /* We don't use loops to align destination and to copy parts smaller
12060 than 4 bytes, because gcc is able to optimize such code better (in
12061 the case the destination or the count really is aligned, gcc is often
12062 able to predict the branches) and also it is friendlier to the
12063 hardware branch prediction.
12065 Using loops is beneficial for generic case, because we can
12066 handle small counts using the loops. Many CPUs (such as Athlon)
12067 have large REP prefix setup costs.
12069 This is quite costly. Maybe we can revisit this decision later or
12070 add some customizability to this code. */
12072 if (count == 0 && align < desired_alignment)
12074 label = gen_label_rtx ();
12075 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12076 LEU, 0, counter_mode, 1, label);
12080 rtx label = ix86_expand_aligntest (destreg, 1);
12081 srcmem = change_address (src, QImode, srcreg);
12082 dstmem = change_address (dst, QImode, destreg);
12083 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12084 ix86_adjust_counter (countreg, 1);
12085 emit_label (label);
12086 LABEL_NUSES (label) = 1;
12090 rtx label = ix86_expand_aligntest (destreg, 2);
12091 srcmem = change_address (src, HImode, srcreg);
12092 dstmem = change_address (dst, HImode, destreg);
12093 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12094 ix86_adjust_counter (countreg, 2);
12095 emit_label (label);
12096 LABEL_NUSES (label) = 1;
12098 if (align <= 4 && desired_alignment > 4)
12100 rtx label = ix86_expand_aligntest (destreg, 4);
12101 srcmem = change_address (src, SImode, srcreg);
12102 dstmem = change_address (dst, SImode, destreg);
12103 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12104 ix86_adjust_counter (countreg, 4);
12105 emit_label (label);
12106 LABEL_NUSES (label) = 1;
12109 if (label && desired_alignment > 4 && !TARGET_64BIT)
12111 emit_label (label);
12112 LABEL_NUSES (label) = 1;
12115 if (!TARGET_SINGLE_STRINGOP)
12116 emit_insn (gen_cld ());
12119 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12121 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12125 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12126 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12128 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
12129 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12130 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
12131 countreg2, destexp, srcexp));
12135 emit_label (label);
12136 LABEL_NUSES (label) = 1;
12138 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12140 srcmem = change_address (src, SImode, srcreg);
12141 dstmem = change_address (dst, SImode, destreg);
12142 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12144 if ((align <= 4 || count == 0) && TARGET_64BIT)
12146 rtx label = ix86_expand_aligntest (countreg, 4);
12147 srcmem = change_address (src, SImode, srcreg);
12148 dstmem = change_address (dst, SImode, destreg);
12149 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12150 emit_label (label);
12151 LABEL_NUSES (label) = 1;
12153 if (align > 2 && count != 0 && (count & 2))
12155 srcmem = change_address (src, HImode, srcreg);
12156 dstmem = change_address (dst, HImode, destreg);
12157 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12159 if (align <= 2 || count == 0)
12161 rtx label = ix86_expand_aligntest (countreg, 2);
12162 srcmem = change_address (src, HImode, srcreg);
12163 dstmem = change_address (dst, HImode, destreg);
12164 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12165 emit_label (label);
12166 LABEL_NUSES (label) = 1;
12168 if (align > 1 && count != 0 && (count & 1))
12170 srcmem = change_address (src, QImode, srcreg);
12171 dstmem = change_address (dst, QImode, destreg);
12172 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12174 if (align <= 1 || count == 0)
12176 rtx label = ix86_expand_aligntest (countreg, 1);
12177 srcmem = change_address (src, QImode, srcreg);
12178 dstmem = change_address (dst, QImode, destreg);
12179 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12180 emit_label (label);
12181 LABEL_NUSES (label) = 1;
12188 /* Expand string clear operation (bzero). Use i386 string operations when
12189 profitable. expand_movmem contains similar code. */
12191 ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp)
12193 rtx destreg, zeroreg, countreg, destexp;
12194 enum machine_mode counter_mode;
12195 HOST_WIDE_INT align = 0;
12196 unsigned HOST_WIDE_INT count = 0;
12198 if (GET_CODE (align_exp) == CONST_INT)
12199 align = INTVAL (align_exp);
12201 /* Can't use any of this if the user has appropriated esi. */
12202 if (global_regs[4])
12205 /* This simple hack avoids all inlining code and simplifies code below. */
12206 if (!TARGET_ALIGN_STRINGOPS)
12209 if (GET_CODE (count_exp) == CONST_INT)
12211 count = INTVAL (count_exp);
12212 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
12215 /* Figure out proper mode for counter. For 32bits it is always SImode,
12216 for 64bits use SImode when possible, otherwise DImode.
12217 Set count to number of bytes copied when known at compile time. */
12219 || GET_MODE (count_exp) == SImode
12220 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
12221 counter_mode = SImode;
12223 counter_mode = DImode;
12225 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
12226 if (destreg != XEXP (dst, 0))
12227 dst = replace_equiv_address_nv (dst, destreg);
12230 /* When optimizing for size emit simple rep ; movsb instruction for
12231 counts not divisible by 4. The movl $N, %ecx; rep; stosb
12232 sequence is 7 bytes long, so if optimizing for size and count is
12233 small enough that some stosl, stosw and stosb instructions without
12234 rep are shorter, fall back into the next if. */
12236 if ((!optimize || optimize_size)
12239 && (!optimize_size || (count & 0x03) + (count >> 2) > 7))))
12241 emit_insn (gen_cld ());
12243 countreg = ix86_zero_extend_to_Pmode (count_exp);
12244 zeroreg = copy_to_mode_reg (QImode, const0_rtx);
12245 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
12246 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg, destexp));
12248 else if (count != 0
12250 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
12251 || optimize_size || count < (unsigned int) 64))
12253 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
12254 unsigned HOST_WIDE_INT offset = 0;
12256 emit_insn (gen_cld ());
12258 zeroreg = copy_to_mode_reg (size == 4 ? SImode : DImode, const0_rtx);
12259 if (count & ~(size - 1))
12261 unsigned HOST_WIDE_INT repcount;
12262 unsigned int max_nonrep;
12264 repcount = count >> (size == 4 ? 2 : 3);
12266 repcount &= 0x3fffffff;
12268 /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes.
12269 movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN
12270 bytes. In both cases the latter seems to be faster for small
12272 max_nonrep = size == 4 ? 7 : 4;
12273 if (!optimize_size)
12276 case PROCESSOR_PENTIUM4:
12277 case PROCESSOR_NOCONA:
12284 if (repcount <= max_nonrep)
12285 while (repcount-- > 0)
12287 rtx mem = adjust_automodify_address_nv (dst,
12288 GET_MODE (zeroreg),
12290 emit_insn (gen_strset (destreg, mem, zeroreg));
12295 countreg = copy_to_mode_reg (counter_mode, GEN_INT (repcount));
12296 countreg = ix86_zero_extend_to_Pmode (countreg);
12297 destexp = gen_rtx_ASHIFT (Pmode, countreg,
12298 GEN_INT (size == 4 ? 2 : 3));
12299 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12300 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg,
12302 offset = count & ~(size - 1);
12305 if (size == 8 && (count & 0x04))
12307 rtx mem = adjust_automodify_address_nv (dst, SImode, destreg,
12309 emit_insn (gen_strset (destreg, mem,
12310 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12315 rtx mem = adjust_automodify_address_nv (dst, HImode, destreg,
12317 emit_insn (gen_strset (destreg, mem,
12318 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12323 rtx mem = adjust_automodify_address_nv (dst, QImode, destreg,
12325 emit_insn (gen_strset (destreg, mem,
12326 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12333 /* Compute desired alignment of the string operation. */
12334 int desired_alignment = (TARGET_PENTIUMPRO
12335 && (count == 0 || count >= (unsigned int) 260)
12336 ? 8 : UNITS_PER_WORD);
12338 /* In case we don't know anything about the alignment, default to
12339 library version, since it is usually equally fast and result in
12342 Also emit call when we know that the count is large and call overhead
12343 will not be important. */
12344 if (!TARGET_INLINE_ALL_STRINGOPS
12345 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12348 if (TARGET_SINGLE_STRINGOP)
12349 emit_insn (gen_cld ());
12351 countreg2 = gen_reg_rtx (Pmode);
12352 countreg = copy_to_mode_reg (counter_mode, count_exp);
12353 zeroreg = copy_to_mode_reg (Pmode, const0_rtx);
12354 /* Get rid of MEM_OFFSET, it won't be accurate. */
12355 dst = change_address (dst, BLKmode, destreg);
12357 if (count == 0 && align < desired_alignment)
12359 label = gen_label_rtx ();
12360 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12361 LEU, 0, counter_mode, 1, label);
12365 rtx label = ix86_expand_aligntest (destreg, 1);
12366 emit_insn (gen_strset (destreg, dst,
12367 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12368 ix86_adjust_counter (countreg, 1);
12369 emit_label (label);
12370 LABEL_NUSES (label) = 1;
12374 rtx label = ix86_expand_aligntest (destreg, 2);
12375 emit_insn (gen_strset (destreg, dst,
12376 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12377 ix86_adjust_counter (countreg, 2);
12378 emit_label (label);
12379 LABEL_NUSES (label) = 1;
12381 if (align <= 4 && desired_alignment > 4)
12383 rtx label = ix86_expand_aligntest (destreg, 4);
12384 emit_insn (gen_strset (destreg, dst,
12386 ? gen_rtx_SUBREG (SImode, zeroreg, 0)
12388 ix86_adjust_counter (countreg, 4);
12389 emit_label (label);
12390 LABEL_NUSES (label) = 1;
12393 if (label && desired_alignment > 4 && !TARGET_64BIT)
12395 emit_label (label);
12396 LABEL_NUSES (label) = 1;
12400 if (!TARGET_SINGLE_STRINGOP)
12401 emit_insn (gen_cld ());
12404 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12406 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12410 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12411 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12413 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12414 emit_insn (gen_rep_stos (destreg, countreg2, dst, zeroreg, destexp));
12418 emit_label (label);
12419 LABEL_NUSES (label) = 1;
12422 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12423 emit_insn (gen_strset (destreg, dst,
12424 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12425 if (TARGET_64BIT && (align <= 4 || count == 0))
12427 rtx label = ix86_expand_aligntest (countreg, 4);
12428 emit_insn (gen_strset (destreg, dst,
12429 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12430 emit_label (label);
12431 LABEL_NUSES (label) = 1;
12433 if (align > 2 && count != 0 && (count & 2))
12434 emit_insn (gen_strset (destreg, dst,
12435 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12436 if (align <= 2 || count == 0)
12438 rtx label = ix86_expand_aligntest (countreg, 2);
12439 emit_insn (gen_strset (destreg, dst,
12440 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12441 emit_label (label);
12442 LABEL_NUSES (label) = 1;
12444 if (align > 1 && count != 0 && (count & 1))
12445 emit_insn (gen_strset (destreg, dst,
12446 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12447 if (align <= 1 || count == 0)
12449 rtx label = ix86_expand_aligntest (countreg, 1);
12450 emit_insn (gen_strset (destreg, dst,
12451 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12452 emit_label (label);
12453 LABEL_NUSES (label) = 1;
12459 /* Expand strlen. */
12461 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
12463 rtx addr, scratch1, scratch2, scratch3, scratch4;
12465 /* The generic case of strlen expander is long. Avoid it's
12466 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
12468 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12469 && !TARGET_INLINE_ALL_STRINGOPS
12471 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
12474 addr = force_reg (Pmode, XEXP (src, 0));
12475 scratch1 = gen_reg_rtx (Pmode);
12477 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12480 /* Well it seems that some optimizer does not combine a call like
12481 foo(strlen(bar), strlen(bar));
12482 when the move and the subtraction is done here. It does calculate
12483 the length just once when these instructions are done inside of
12484 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
12485 often used and I use one fewer register for the lifetime of
12486 output_strlen_unroll() this is better. */
12488 emit_move_insn (out, addr);
12490 ix86_expand_strlensi_unroll_1 (out, src, align);
12492 /* strlensi_unroll_1 returns the address of the zero at the end of
12493 the string, like memchr(), so compute the length by subtracting
12494 the start address. */
12496 emit_insn (gen_subdi3 (out, out, addr));
12498 emit_insn (gen_subsi3 (out, out, addr));
12503 scratch2 = gen_reg_rtx (Pmode);
12504 scratch3 = gen_reg_rtx (Pmode);
12505 scratch4 = force_reg (Pmode, constm1_rtx);
12507 emit_move_insn (scratch3, addr);
12508 eoschar = force_reg (QImode, eoschar);
12510 emit_insn (gen_cld ());
12511 src = replace_equiv_address_nv (src, scratch3);
12513 /* If .md starts supporting :P, this can be done in .md. */
12514 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
12515 scratch4), UNSPEC_SCAS);
12516 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
12519 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
12520 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
12524 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
12525 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
12531 /* Expand the appropriate insns for doing strlen if not just doing
12534 out = result, initialized with the start address
12535 align_rtx = alignment of the address.
12536 scratch = scratch register, initialized with the startaddress when
12537 not aligned, otherwise undefined
12539 This is just the body. It needs the initializations mentioned above and
12540 some address computing at the end. These things are done in i386.md. */
12543 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
12547 rtx align_2_label = NULL_RTX;
12548 rtx align_3_label = NULL_RTX;
12549 rtx align_4_label = gen_label_rtx ();
12550 rtx end_0_label = gen_label_rtx ();
12552 rtx tmpreg = gen_reg_rtx (SImode);
12553 rtx scratch = gen_reg_rtx (SImode);
12557 if (GET_CODE (align_rtx) == CONST_INT)
12558 align = INTVAL (align_rtx);
12560 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
12562 /* Is there a known alignment and is it less than 4? */
12565 rtx scratch1 = gen_reg_rtx (Pmode);
12566 emit_move_insn (scratch1, out);
12567 /* Is there a known alignment and is it not 2? */
12570 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
12571 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
12573 /* Leave just the 3 lower bits. */
12574 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
12575 NULL_RTX, 0, OPTAB_WIDEN);
12577 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12578 Pmode, 1, align_4_label);
12579 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
12580 Pmode, 1, align_2_label);
12581 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
12582 Pmode, 1, align_3_label);
12586 /* Since the alignment is 2, we have to check 2 or 0 bytes;
12587 check if is aligned to 4 - byte. */
12589 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
12590 NULL_RTX, 0, OPTAB_WIDEN);
12592 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12593 Pmode, 1, align_4_label);
12596 mem = change_address (src, QImode, out);
12598 /* Now compare the bytes. */
12600 /* Compare the first n unaligned byte on a byte per byte basis. */
12601 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
12602 QImode, 1, end_0_label);
12604 /* Increment the address. */
12606 emit_insn (gen_adddi3 (out, out, const1_rtx));
12608 emit_insn (gen_addsi3 (out, out, const1_rtx));
12610 /* Not needed with an alignment of 2 */
12613 emit_label (align_2_label);
12615 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
12619 emit_insn (gen_adddi3 (out, out, const1_rtx));
12621 emit_insn (gen_addsi3 (out, out, const1_rtx));
12623 emit_label (align_3_label);
12626 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
12630 emit_insn (gen_adddi3 (out, out, const1_rtx));
12632 emit_insn (gen_addsi3 (out, out, const1_rtx));
12635 /* Generate loop to check 4 bytes at a time. It is not a good idea to
12636 align this loop. It gives only huge programs, but does not help to
12638 emit_label (align_4_label);
12640 mem = change_address (src, SImode, out);
12641 emit_move_insn (scratch, mem);
12643 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
12645 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
12647 /* This formula yields a nonzero result iff one of the bytes is zero.
12648 This saves three branches inside loop and many cycles. */
12650 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
12651 emit_insn (gen_one_cmplsi2 (scratch, scratch));
12652 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
12653 emit_insn (gen_andsi3 (tmpreg, tmpreg,
12654 gen_int_mode (0x80808080, SImode)));
12655 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
12660 rtx reg = gen_reg_rtx (SImode);
12661 rtx reg2 = gen_reg_rtx (Pmode);
12662 emit_move_insn (reg, tmpreg);
12663 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
12665 /* If zero is not in the first two bytes, move two bytes forward. */
12666 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
12667 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12668 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
12669 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
12670 gen_rtx_IF_THEN_ELSE (SImode, tmp,
12673 /* Emit lea manually to avoid clobbering of flags. */
12674 emit_insn (gen_rtx_SET (SImode, reg2,
12675 gen_rtx_PLUS (Pmode, out, const2_rtx)));
12677 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12678 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
12679 emit_insn (gen_rtx_SET (VOIDmode, out,
12680 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
12687 rtx end_2_label = gen_label_rtx ();
12688 /* Is zero in the first two bytes? */
12690 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
12691 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12692 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
12693 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12694 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
12696 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12697 JUMP_LABEL (tmp) = end_2_label;
12699 /* Not in the first two. Move two bytes forward. */
12700 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
12702 emit_insn (gen_adddi3 (out, out, const2_rtx));
12704 emit_insn (gen_addsi3 (out, out, const2_rtx));
12706 emit_label (end_2_label);
12710 /* Avoid branch in fixing the byte. */
12711 tmpreg = gen_lowpart (QImode, tmpreg);
12712 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
12713 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
12715 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
12717 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
12719 emit_label (end_0_label);
12723 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
12724 rtx callarg2 ATTRIBUTE_UNUSED,
12725 rtx pop, int sibcall)
12727 rtx use = NULL, call;
12729 if (pop == const0_rtx)
12731 gcc_assert (!TARGET_64BIT || !pop);
12734 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
12735 fnaddr = machopic_indirect_call_target (fnaddr);
12737 /* Static functions and indirect calls don't need the pic register. */
12738 if (! TARGET_64BIT && flag_pic
12739 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
12740 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
12741 use_reg (&use, pic_offset_table_rtx);
12743 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
12745 rtx al = gen_rtx_REG (QImode, 0);
12746 emit_move_insn (al, callarg2);
12747 use_reg (&use, al);
12749 #endif /* TARGET_MACHO */
12751 if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
12753 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
12754 fnaddr = gen_rtx_MEM (QImode, fnaddr);
12756 if (sibcall && TARGET_64BIT
12757 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
12760 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
12761 fnaddr = gen_rtx_REG (Pmode, FIRST_REX_INT_REG + 3 /* R11 */);
12762 emit_move_insn (fnaddr, addr);
12763 fnaddr = gen_rtx_MEM (QImode, fnaddr);
12766 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
12768 call = gen_rtx_SET (VOIDmode, retval, call);
12771 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
12772 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
12773 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
12776 call = emit_call_insn (call);
12778 CALL_INSN_FUNCTION_USAGE (call) = use;
12782 /* Clear stack slot assignments remembered from previous functions.
12783 This is called from INIT_EXPANDERS once before RTL is emitted for each
12786 static struct machine_function *
12787 ix86_init_machine_status (void)
12789 struct machine_function *f;
12791 f = ggc_alloc_cleared (sizeof (struct machine_function));
12792 f->use_fast_prologue_epilogue_nregs = -1;
12797 /* Return a MEM corresponding to a stack slot with mode MODE.
12798 Allocate a new slot if necessary.
12800 The RTL for a function can have several slots available: N is
12801 which slot to use. */
12804 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
12806 struct stack_local_entry *s;
12808 gcc_assert (n < MAX_386_STACK_LOCALS);
12810 for (s = ix86_stack_locals; s; s = s->next)
12811 if (s->mode == mode && s->n == n)
12814 s = (struct stack_local_entry *)
12815 ggc_alloc (sizeof (struct stack_local_entry));
12818 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
12820 s->next = ix86_stack_locals;
12821 ix86_stack_locals = s;
12825 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12827 static GTY(()) rtx ix86_tls_symbol;
12829 ix86_tls_get_addr (void)
12832 if (!ix86_tls_symbol)
12834 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
12835 (TARGET_GNU_TLS && !TARGET_64BIT)
12836 ? "___tls_get_addr"
12837 : "__tls_get_addr");
12840 return ix86_tls_symbol;
12843 /* Calculate the length of the memory address in the instruction
12844 encoding. Does not include the one-byte modrm, opcode, or prefix. */
12847 memory_address_length (rtx addr)
12849 struct ix86_address parts;
12850 rtx base, index, disp;
12854 if (GET_CODE (addr) == PRE_DEC
12855 || GET_CODE (addr) == POST_INC
12856 || GET_CODE (addr) == PRE_MODIFY
12857 || GET_CODE (addr) == POST_MODIFY)
12860 ok = ix86_decompose_address (addr, &parts);
12863 if (parts.base && GET_CODE (parts.base) == SUBREG)
12864 parts.base = SUBREG_REG (parts.base);
12865 if (parts.index && GET_CODE (parts.index) == SUBREG)
12866 parts.index = SUBREG_REG (parts.index);
12869 index = parts.index;
12874 - esp as the base always wants an index,
12875 - ebp as the base always wants a displacement. */
12877 /* Register Indirect. */
12878 if (base && !index && !disp)
12880 /* esp (for its index) and ebp (for its displacement) need
12881 the two-byte modrm form. */
12882 if (addr == stack_pointer_rtx
12883 || addr == arg_pointer_rtx
12884 || addr == frame_pointer_rtx
12885 || addr == hard_frame_pointer_rtx)
12889 /* Direct Addressing. */
12890 else if (disp && !base && !index)
12895 /* Find the length of the displacement constant. */
12898 if (GET_CODE (disp) == CONST_INT
12899 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K')
12905 /* ebp always wants a displacement. */
12906 else if (base == hard_frame_pointer_rtx)
12909 /* An index requires the two-byte modrm form.... */
12911 /* ...like esp, which always wants an index. */
12912 || base == stack_pointer_rtx
12913 || base == arg_pointer_rtx
12914 || base == frame_pointer_rtx)
12921 /* Compute default value for "length_immediate" attribute. When SHORTFORM
12922 is set, expect that insn have 8bit immediate alternative. */
12924 ix86_attr_length_immediate_default (rtx insn, int shortform)
12928 extract_insn_cached (insn);
12929 for (i = recog_data.n_operands - 1; i >= 0; --i)
12930 if (CONSTANT_P (recog_data.operand[i]))
12934 && GET_CODE (recog_data.operand[i]) == CONST_INT
12935 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data.operand[i]), 'K'))
12939 switch (get_attr_mode (insn))
12950 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
12955 fatal_insn ("unknown insn mode", insn);
12961 /* Compute default value for "length_address" attribute. */
12963 ix86_attr_length_address_default (rtx insn)
12967 if (get_attr_type (insn) == TYPE_LEA)
12969 rtx set = PATTERN (insn);
12971 if (GET_CODE (set) == PARALLEL)
12972 set = XVECEXP (set, 0, 0);
12974 gcc_assert (GET_CODE (set) == SET);
12976 return memory_address_length (SET_SRC (set));
12979 extract_insn_cached (insn);
12980 for (i = recog_data.n_operands - 1; i >= 0; --i)
12981 if (GET_CODE (recog_data.operand[i]) == MEM)
12983 return memory_address_length (XEXP (recog_data.operand[i], 0));
12989 /* Return the maximum number of instructions a cpu can issue. */
12992 ix86_issue_rate (void)
12996 case PROCESSOR_PENTIUM:
13000 case PROCESSOR_PENTIUMPRO:
13001 case PROCESSOR_PENTIUM4:
13002 case PROCESSOR_ATHLON:
13004 case PROCESSOR_NOCONA:
13012 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
13013 by DEP_INSN and nothing set by DEP_INSN. */
13016 ix86_flags_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
13020 /* Simplify the test for uninteresting insns. */
13021 if (insn_type != TYPE_SETCC
13022 && insn_type != TYPE_ICMOV
13023 && insn_type != TYPE_FCMOV
13024 && insn_type != TYPE_IBR)
13027 if ((set = single_set (dep_insn)) != 0)
13029 set = SET_DEST (set);
13032 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
13033 && XVECLEN (PATTERN (dep_insn), 0) == 2
13034 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
13035 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
13037 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
13038 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
13043 if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG)
13046 /* This test is true if the dependent insn reads the flags but
13047 not any other potentially set register. */
13048 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
13051 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
13057 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
13058 address with operands set by DEP_INSN. */
13061 ix86_agi_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
13065 if (insn_type == TYPE_LEA
13068 addr = PATTERN (insn);
13070 if (GET_CODE (addr) == PARALLEL)
13071 addr = XVECEXP (addr, 0, 0);
13073 gcc_assert (GET_CODE (addr) == SET);
13075 addr = SET_SRC (addr);
13080 extract_insn_cached (insn);
13081 for (i = recog_data.n_operands - 1; i >= 0; --i)
13082 if (GET_CODE (recog_data.operand[i]) == MEM)
13084 addr = XEXP (recog_data.operand[i], 0);
13091 return modified_in_p (addr, dep_insn);
13095 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
13097 enum attr_type insn_type, dep_insn_type;
13098 enum attr_memory memory;
13100 int dep_insn_code_number;
13102 /* Anti and output dependencies have zero cost on all CPUs. */
13103 if (REG_NOTE_KIND (link) != 0)
13106 dep_insn_code_number = recog_memoized (dep_insn);
13108 /* If we can't recognize the insns, we can't really do anything. */
13109 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
13112 insn_type = get_attr_type (insn);
13113 dep_insn_type = get_attr_type (dep_insn);
13117 case PROCESSOR_PENTIUM:
13118 /* Address Generation Interlock adds a cycle of latency. */
13119 if (ix86_agi_dependant (insn, dep_insn, insn_type))
13122 /* ??? Compares pair with jump/setcc. */
13123 if (ix86_flags_dependant (insn, dep_insn, insn_type))
13126 /* Floating point stores require value to be ready one cycle earlier. */
13127 if (insn_type == TYPE_FMOV
13128 && get_attr_memory (insn) == MEMORY_STORE
13129 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13133 case PROCESSOR_PENTIUMPRO:
13134 memory = get_attr_memory (insn);
13136 /* INT->FP conversion is expensive. */
13137 if (get_attr_fp_int_src (dep_insn))
13140 /* There is one cycle extra latency between an FP op and a store. */
13141 if (insn_type == TYPE_FMOV
13142 && (set = single_set (dep_insn)) != NULL_RTX
13143 && (set2 = single_set (insn)) != NULL_RTX
13144 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
13145 && GET_CODE (SET_DEST (set2)) == MEM)
13148 /* Show ability of reorder buffer to hide latency of load by executing
13149 in parallel with previous instruction in case
13150 previous instruction is not needed to compute the address. */
13151 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13152 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13154 /* Claim moves to take one cycle, as core can issue one load
13155 at time and the next load can start cycle later. */
13156 if (dep_insn_type == TYPE_IMOV
13157 || dep_insn_type == TYPE_FMOV)
13165 memory = get_attr_memory (insn);
13167 /* The esp dependency is resolved before the instruction is really
13169 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
13170 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
13173 /* INT->FP conversion is expensive. */
13174 if (get_attr_fp_int_src (dep_insn))
13177 /* Show ability of reorder buffer to hide latency of load by executing
13178 in parallel with previous instruction in case
13179 previous instruction is not needed to compute the address. */
13180 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13181 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13183 /* Claim moves to take one cycle, as core can issue one load
13184 at time and the next load can start cycle later. */
13185 if (dep_insn_type == TYPE_IMOV
13186 || dep_insn_type == TYPE_FMOV)
13195 case PROCESSOR_ATHLON:
13197 memory = get_attr_memory (insn);
13199 /* Show ability of reorder buffer to hide latency of load by executing
13200 in parallel with previous instruction in case
13201 previous instruction is not needed to compute the address. */
13202 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13203 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13205 enum attr_unit unit = get_attr_unit (insn);
13208 /* Because of the difference between the length of integer and
13209 floating unit pipeline preparation stages, the memory operands
13210 for floating point are cheaper.
13212 ??? For Athlon it the difference is most probably 2. */
13213 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
13216 loadcost = TARGET_ATHLON ? 2 : 0;
13218 if (cost >= loadcost)
13231 /* How many alternative schedules to try. This should be as wide as the
13232 scheduling freedom in the DFA, but no wider. Making this value too
13233 large results extra work for the scheduler. */
13236 ia32_multipass_dfa_lookahead (void)
13238 if (ix86_tune == PROCESSOR_PENTIUM)
13241 if (ix86_tune == PROCESSOR_PENTIUMPRO
13242 || ix86_tune == PROCESSOR_K6)
13250 /* Compute the alignment given to a constant that is being placed in memory.
13251 EXP is the constant and ALIGN is the alignment that the object would
13253 The value of this function is used instead of that alignment to align
13257 ix86_constant_alignment (tree exp, int align)
13259 if (TREE_CODE (exp) == REAL_CST)
13261 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
13263 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
13266 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
13267 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
13268 return BITS_PER_WORD;
13273 /* Compute the alignment for a static variable.
13274 TYPE is the data type, and ALIGN is the alignment that
13275 the object would ordinarily have. The value of this function is used
13276 instead of that alignment to align the object. */
13279 ix86_data_alignment (tree type, int align)
13281 if (AGGREGATE_TYPE_P (type)
13282 && TYPE_SIZE (type)
13283 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13284 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 256
13285 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 256)
13288 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13289 to 16byte boundary. */
13292 if (AGGREGATE_TYPE_P (type)
13293 && TYPE_SIZE (type)
13294 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13295 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
13296 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13300 if (TREE_CODE (type) == ARRAY_TYPE)
13302 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13304 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13307 else if (TREE_CODE (type) == COMPLEX_TYPE)
13310 if (TYPE_MODE (type) == DCmode && align < 64)
13312 if (TYPE_MODE (type) == XCmode && align < 128)
13315 else if ((TREE_CODE (type) == RECORD_TYPE
13316 || TREE_CODE (type) == UNION_TYPE
13317 || TREE_CODE (type) == QUAL_UNION_TYPE)
13318 && TYPE_FIELDS (type))
13320 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13322 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13325 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13326 || TREE_CODE (type) == INTEGER_TYPE)
13328 if (TYPE_MODE (type) == DFmode && align < 64)
13330 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13337 /* Compute the alignment for a local variable.
13338 TYPE is the data type, and ALIGN is the alignment that
13339 the object would ordinarily have. The value of this macro is used
13340 instead of that alignment to align the object. */
13343 ix86_local_alignment (tree type, int align)
13345 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13346 to 16byte boundary. */
13349 if (AGGREGATE_TYPE_P (type)
13350 && TYPE_SIZE (type)
13351 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13352 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
13353 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13356 if (TREE_CODE (type) == ARRAY_TYPE)
13358 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13360 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13363 else if (TREE_CODE (type) == COMPLEX_TYPE)
13365 if (TYPE_MODE (type) == DCmode && align < 64)
13367 if (TYPE_MODE (type) == XCmode && align < 128)
13370 else if ((TREE_CODE (type) == RECORD_TYPE
13371 || TREE_CODE (type) == UNION_TYPE
13372 || TREE_CODE (type) == QUAL_UNION_TYPE)
13373 && TYPE_FIELDS (type))
13375 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13377 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13380 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13381 || TREE_CODE (type) == INTEGER_TYPE)
13384 if (TYPE_MODE (type) == DFmode && align < 64)
13386 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13392 /* Emit RTL insns to initialize the variable parts of a trampoline.
13393 FNADDR is an RTX for the address of the function's pure code.
13394 CXT is an RTX for the static chain value for the function. */
13396 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
13400 /* Compute offset from the end of the jmp to the target function. */
13401 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
13402 plus_constant (tramp, 10),
13403 NULL_RTX, 1, OPTAB_DIRECT);
13404 emit_move_insn (gen_rtx_MEM (QImode, tramp),
13405 gen_int_mode (0xb9, QImode));
13406 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
13407 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
13408 gen_int_mode (0xe9, QImode));
13409 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
13414 /* Try to load address using shorter movl instead of movabs.
13415 We may want to support movq for kernel mode, but kernel does not use
13416 trampolines at the moment. */
13417 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
13419 fnaddr = copy_to_mode_reg (DImode, fnaddr);
13420 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13421 gen_int_mode (0xbb41, HImode));
13422 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
13423 gen_lowpart (SImode, fnaddr));
13428 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13429 gen_int_mode (0xbb49, HImode));
13430 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13434 /* Load static chain using movabs to r10. */
13435 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13436 gen_int_mode (0xba49, HImode));
13437 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13440 /* Jump to the r11 */
13441 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13442 gen_int_mode (0xff49, HImode));
13443 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
13444 gen_int_mode (0xe3, QImode));
13446 gcc_assert (offset <= TRAMPOLINE_SIZE);
13449 #ifdef ENABLE_EXECUTE_STACK
13450 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
13451 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
13455 /* Codes for all the SSE/MMX builtins. */
13458 IX86_BUILTIN_ADDPS,
13459 IX86_BUILTIN_ADDSS,
13460 IX86_BUILTIN_DIVPS,
13461 IX86_BUILTIN_DIVSS,
13462 IX86_BUILTIN_MULPS,
13463 IX86_BUILTIN_MULSS,
13464 IX86_BUILTIN_SUBPS,
13465 IX86_BUILTIN_SUBSS,
13467 IX86_BUILTIN_CMPEQPS,
13468 IX86_BUILTIN_CMPLTPS,
13469 IX86_BUILTIN_CMPLEPS,
13470 IX86_BUILTIN_CMPGTPS,
13471 IX86_BUILTIN_CMPGEPS,
13472 IX86_BUILTIN_CMPNEQPS,
13473 IX86_BUILTIN_CMPNLTPS,
13474 IX86_BUILTIN_CMPNLEPS,
13475 IX86_BUILTIN_CMPNGTPS,
13476 IX86_BUILTIN_CMPNGEPS,
13477 IX86_BUILTIN_CMPORDPS,
13478 IX86_BUILTIN_CMPUNORDPS,
13479 IX86_BUILTIN_CMPEQSS,
13480 IX86_BUILTIN_CMPLTSS,
13481 IX86_BUILTIN_CMPLESS,
13482 IX86_BUILTIN_CMPNEQSS,
13483 IX86_BUILTIN_CMPNLTSS,
13484 IX86_BUILTIN_CMPNLESS,
13485 IX86_BUILTIN_CMPNGTSS,
13486 IX86_BUILTIN_CMPNGESS,
13487 IX86_BUILTIN_CMPORDSS,
13488 IX86_BUILTIN_CMPUNORDSS,
13490 IX86_BUILTIN_COMIEQSS,
13491 IX86_BUILTIN_COMILTSS,
13492 IX86_BUILTIN_COMILESS,
13493 IX86_BUILTIN_COMIGTSS,
13494 IX86_BUILTIN_COMIGESS,
13495 IX86_BUILTIN_COMINEQSS,
13496 IX86_BUILTIN_UCOMIEQSS,
13497 IX86_BUILTIN_UCOMILTSS,
13498 IX86_BUILTIN_UCOMILESS,
13499 IX86_BUILTIN_UCOMIGTSS,
13500 IX86_BUILTIN_UCOMIGESS,
13501 IX86_BUILTIN_UCOMINEQSS,
13503 IX86_BUILTIN_CVTPI2PS,
13504 IX86_BUILTIN_CVTPS2PI,
13505 IX86_BUILTIN_CVTSI2SS,
13506 IX86_BUILTIN_CVTSI642SS,
13507 IX86_BUILTIN_CVTSS2SI,
13508 IX86_BUILTIN_CVTSS2SI64,
13509 IX86_BUILTIN_CVTTPS2PI,
13510 IX86_BUILTIN_CVTTSS2SI,
13511 IX86_BUILTIN_CVTTSS2SI64,
13513 IX86_BUILTIN_MAXPS,
13514 IX86_BUILTIN_MAXSS,
13515 IX86_BUILTIN_MINPS,
13516 IX86_BUILTIN_MINSS,
13518 IX86_BUILTIN_LOADUPS,
13519 IX86_BUILTIN_STOREUPS,
13520 IX86_BUILTIN_MOVSS,
13522 IX86_BUILTIN_MOVHLPS,
13523 IX86_BUILTIN_MOVLHPS,
13524 IX86_BUILTIN_LOADHPS,
13525 IX86_BUILTIN_LOADLPS,
13526 IX86_BUILTIN_STOREHPS,
13527 IX86_BUILTIN_STORELPS,
13529 IX86_BUILTIN_MASKMOVQ,
13530 IX86_BUILTIN_MOVMSKPS,
13531 IX86_BUILTIN_PMOVMSKB,
13533 IX86_BUILTIN_MOVNTPS,
13534 IX86_BUILTIN_MOVNTQ,
13536 IX86_BUILTIN_LOADDQU,
13537 IX86_BUILTIN_STOREDQU,
13539 IX86_BUILTIN_PACKSSWB,
13540 IX86_BUILTIN_PACKSSDW,
13541 IX86_BUILTIN_PACKUSWB,
13543 IX86_BUILTIN_PADDB,
13544 IX86_BUILTIN_PADDW,
13545 IX86_BUILTIN_PADDD,
13546 IX86_BUILTIN_PADDQ,
13547 IX86_BUILTIN_PADDSB,
13548 IX86_BUILTIN_PADDSW,
13549 IX86_BUILTIN_PADDUSB,
13550 IX86_BUILTIN_PADDUSW,
13551 IX86_BUILTIN_PSUBB,
13552 IX86_BUILTIN_PSUBW,
13553 IX86_BUILTIN_PSUBD,
13554 IX86_BUILTIN_PSUBQ,
13555 IX86_BUILTIN_PSUBSB,
13556 IX86_BUILTIN_PSUBSW,
13557 IX86_BUILTIN_PSUBUSB,
13558 IX86_BUILTIN_PSUBUSW,
13561 IX86_BUILTIN_PANDN,
13565 IX86_BUILTIN_PAVGB,
13566 IX86_BUILTIN_PAVGW,
13568 IX86_BUILTIN_PCMPEQB,
13569 IX86_BUILTIN_PCMPEQW,
13570 IX86_BUILTIN_PCMPEQD,
13571 IX86_BUILTIN_PCMPGTB,
13572 IX86_BUILTIN_PCMPGTW,
13573 IX86_BUILTIN_PCMPGTD,
13575 IX86_BUILTIN_PMADDWD,
13577 IX86_BUILTIN_PMAXSW,
13578 IX86_BUILTIN_PMAXUB,
13579 IX86_BUILTIN_PMINSW,
13580 IX86_BUILTIN_PMINUB,
13582 IX86_BUILTIN_PMULHUW,
13583 IX86_BUILTIN_PMULHW,
13584 IX86_BUILTIN_PMULLW,
13586 IX86_BUILTIN_PSADBW,
13587 IX86_BUILTIN_PSHUFW,
13589 IX86_BUILTIN_PSLLW,
13590 IX86_BUILTIN_PSLLD,
13591 IX86_BUILTIN_PSLLQ,
13592 IX86_BUILTIN_PSRAW,
13593 IX86_BUILTIN_PSRAD,
13594 IX86_BUILTIN_PSRLW,
13595 IX86_BUILTIN_PSRLD,
13596 IX86_BUILTIN_PSRLQ,
13597 IX86_BUILTIN_PSLLWI,
13598 IX86_BUILTIN_PSLLDI,
13599 IX86_BUILTIN_PSLLQI,
13600 IX86_BUILTIN_PSRAWI,
13601 IX86_BUILTIN_PSRADI,
13602 IX86_BUILTIN_PSRLWI,
13603 IX86_BUILTIN_PSRLDI,
13604 IX86_BUILTIN_PSRLQI,
13606 IX86_BUILTIN_PUNPCKHBW,
13607 IX86_BUILTIN_PUNPCKHWD,
13608 IX86_BUILTIN_PUNPCKHDQ,
13609 IX86_BUILTIN_PUNPCKLBW,
13610 IX86_BUILTIN_PUNPCKLWD,
13611 IX86_BUILTIN_PUNPCKLDQ,
13613 IX86_BUILTIN_SHUFPS,
13615 IX86_BUILTIN_RCPPS,
13616 IX86_BUILTIN_RCPSS,
13617 IX86_BUILTIN_RSQRTPS,
13618 IX86_BUILTIN_RSQRTSS,
13619 IX86_BUILTIN_SQRTPS,
13620 IX86_BUILTIN_SQRTSS,
13622 IX86_BUILTIN_UNPCKHPS,
13623 IX86_BUILTIN_UNPCKLPS,
13625 IX86_BUILTIN_ANDPS,
13626 IX86_BUILTIN_ANDNPS,
13628 IX86_BUILTIN_XORPS,
13631 IX86_BUILTIN_LDMXCSR,
13632 IX86_BUILTIN_STMXCSR,
13633 IX86_BUILTIN_SFENCE,
13635 /* 3DNow! Original */
13636 IX86_BUILTIN_FEMMS,
13637 IX86_BUILTIN_PAVGUSB,
13638 IX86_BUILTIN_PF2ID,
13639 IX86_BUILTIN_PFACC,
13640 IX86_BUILTIN_PFADD,
13641 IX86_BUILTIN_PFCMPEQ,
13642 IX86_BUILTIN_PFCMPGE,
13643 IX86_BUILTIN_PFCMPGT,
13644 IX86_BUILTIN_PFMAX,
13645 IX86_BUILTIN_PFMIN,
13646 IX86_BUILTIN_PFMUL,
13647 IX86_BUILTIN_PFRCP,
13648 IX86_BUILTIN_PFRCPIT1,
13649 IX86_BUILTIN_PFRCPIT2,
13650 IX86_BUILTIN_PFRSQIT1,
13651 IX86_BUILTIN_PFRSQRT,
13652 IX86_BUILTIN_PFSUB,
13653 IX86_BUILTIN_PFSUBR,
13654 IX86_BUILTIN_PI2FD,
13655 IX86_BUILTIN_PMULHRW,
13657 /* 3DNow! Athlon Extensions */
13658 IX86_BUILTIN_PF2IW,
13659 IX86_BUILTIN_PFNACC,
13660 IX86_BUILTIN_PFPNACC,
13661 IX86_BUILTIN_PI2FW,
13662 IX86_BUILTIN_PSWAPDSI,
13663 IX86_BUILTIN_PSWAPDSF,
13666 IX86_BUILTIN_ADDPD,
13667 IX86_BUILTIN_ADDSD,
13668 IX86_BUILTIN_DIVPD,
13669 IX86_BUILTIN_DIVSD,
13670 IX86_BUILTIN_MULPD,
13671 IX86_BUILTIN_MULSD,
13672 IX86_BUILTIN_SUBPD,
13673 IX86_BUILTIN_SUBSD,
13675 IX86_BUILTIN_CMPEQPD,
13676 IX86_BUILTIN_CMPLTPD,
13677 IX86_BUILTIN_CMPLEPD,
13678 IX86_BUILTIN_CMPGTPD,
13679 IX86_BUILTIN_CMPGEPD,
13680 IX86_BUILTIN_CMPNEQPD,
13681 IX86_BUILTIN_CMPNLTPD,
13682 IX86_BUILTIN_CMPNLEPD,
13683 IX86_BUILTIN_CMPNGTPD,
13684 IX86_BUILTIN_CMPNGEPD,
13685 IX86_BUILTIN_CMPORDPD,
13686 IX86_BUILTIN_CMPUNORDPD,
13687 IX86_BUILTIN_CMPNEPD,
13688 IX86_BUILTIN_CMPEQSD,
13689 IX86_BUILTIN_CMPLTSD,
13690 IX86_BUILTIN_CMPLESD,
13691 IX86_BUILTIN_CMPNEQSD,
13692 IX86_BUILTIN_CMPNLTSD,
13693 IX86_BUILTIN_CMPNLESD,
13694 IX86_BUILTIN_CMPORDSD,
13695 IX86_BUILTIN_CMPUNORDSD,
13696 IX86_BUILTIN_CMPNESD,
13698 IX86_BUILTIN_COMIEQSD,
13699 IX86_BUILTIN_COMILTSD,
13700 IX86_BUILTIN_COMILESD,
13701 IX86_BUILTIN_COMIGTSD,
13702 IX86_BUILTIN_COMIGESD,
13703 IX86_BUILTIN_COMINEQSD,
13704 IX86_BUILTIN_UCOMIEQSD,
13705 IX86_BUILTIN_UCOMILTSD,
13706 IX86_BUILTIN_UCOMILESD,
13707 IX86_BUILTIN_UCOMIGTSD,
13708 IX86_BUILTIN_UCOMIGESD,
13709 IX86_BUILTIN_UCOMINEQSD,
13711 IX86_BUILTIN_MAXPD,
13712 IX86_BUILTIN_MAXSD,
13713 IX86_BUILTIN_MINPD,
13714 IX86_BUILTIN_MINSD,
13716 IX86_BUILTIN_ANDPD,
13717 IX86_BUILTIN_ANDNPD,
13719 IX86_BUILTIN_XORPD,
13721 IX86_BUILTIN_SQRTPD,
13722 IX86_BUILTIN_SQRTSD,
13724 IX86_BUILTIN_UNPCKHPD,
13725 IX86_BUILTIN_UNPCKLPD,
13727 IX86_BUILTIN_SHUFPD,
13729 IX86_BUILTIN_LOADUPD,
13730 IX86_BUILTIN_STOREUPD,
13731 IX86_BUILTIN_MOVSD,
13733 IX86_BUILTIN_LOADHPD,
13734 IX86_BUILTIN_LOADLPD,
13736 IX86_BUILTIN_CVTDQ2PD,
13737 IX86_BUILTIN_CVTDQ2PS,
13739 IX86_BUILTIN_CVTPD2DQ,
13740 IX86_BUILTIN_CVTPD2PI,
13741 IX86_BUILTIN_CVTPD2PS,
13742 IX86_BUILTIN_CVTTPD2DQ,
13743 IX86_BUILTIN_CVTTPD2PI,
13745 IX86_BUILTIN_CVTPI2PD,
13746 IX86_BUILTIN_CVTSI2SD,
13747 IX86_BUILTIN_CVTSI642SD,
13749 IX86_BUILTIN_CVTSD2SI,
13750 IX86_BUILTIN_CVTSD2SI64,
13751 IX86_BUILTIN_CVTSD2SS,
13752 IX86_BUILTIN_CVTSS2SD,
13753 IX86_BUILTIN_CVTTSD2SI,
13754 IX86_BUILTIN_CVTTSD2SI64,
13756 IX86_BUILTIN_CVTPS2DQ,
13757 IX86_BUILTIN_CVTPS2PD,
13758 IX86_BUILTIN_CVTTPS2DQ,
13760 IX86_BUILTIN_MOVNTI,
13761 IX86_BUILTIN_MOVNTPD,
13762 IX86_BUILTIN_MOVNTDQ,
13765 IX86_BUILTIN_MASKMOVDQU,
13766 IX86_BUILTIN_MOVMSKPD,
13767 IX86_BUILTIN_PMOVMSKB128,
13769 IX86_BUILTIN_PACKSSWB128,
13770 IX86_BUILTIN_PACKSSDW128,
13771 IX86_BUILTIN_PACKUSWB128,
13773 IX86_BUILTIN_PADDB128,
13774 IX86_BUILTIN_PADDW128,
13775 IX86_BUILTIN_PADDD128,
13776 IX86_BUILTIN_PADDQ128,
13777 IX86_BUILTIN_PADDSB128,
13778 IX86_BUILTIN_PADDSW128,
13779 IX86_BUILTIN_PADDUSB128,
13780 IX86_BUILTIN_PADDUSW128,
13781 IX86_BUILTIN_PSUBB128,
13782 IX86_BUILTIN_PSUBW128,
13783 IX86_BUILTIN_PSUBD128,
13784 IX86_BUILTIN_PSUBQ128,
13785 IX86_BUILTIN_PSUBSB128,
13786 IX86_BUILTIN_PSUBSW128,
13787 IX86_BUILTIN_PSUBUSB128,
13788 IX86_BUILTIN_PSUBUSW128,
13790 IX86_BUILTIN_PAND128,
13791 IX86_BUILTIN_PANDN128,
13792 IX86_BUILTIN_POR128,
13793 IX86_BUILTIN_PXOR128,
13795 IX86_BUILTIN_PAVGB128,
13796 IX86_BUILTIN_PAVGW128,
13798 IX86_BUILTIN_PCMPEQB128,
13799 IX86_BUILTIN_PCMPEQW128,
13800 IX86_BUILTIN_PCMPEQD128,
13801 IX86_BUILTIN_PCMPGTB128,
13802 IX86_BUILTIN_PCMPGTW128,
13803 IX86_BUILTIN_PCMPGTD128,
13805 IX86_BUILTIN_PMADDWD128,
13807 IX86_BUILTIN_PMAXSW128,
13808 IX86_BUILTIN_PMAXUB128,
13809 IX86_BUILTIN_PMINSW128,
13810 IX86_BUILTIN_PMINUB128,
13812 IX86_BUILTIN_PMULUDQ,
13813 IX86_BUILTIN_PMULUDQ128,
13814 IX86_BUILTIN_PMULHUW128,
13815 IX86_BUILTIN_PMULHW128,
13816 IX86_BUILTIN_PMULLW128,
13818 IX86_BUILTIN_PSADBW128,
13819 IX86_BUILTIN_PSHUFHW,
13820 IX86_BUILTIN_PSHUFLW,
13821 IX86_BUILTIN_PSHUFD,
13823 IX86_BUILTIN_PSLLW128,
13824 IX86_BUILTIN_PSLLD128,
13825 IX86_BUILTIN_PSLLQ128,
13826 IX86_BUILTIN_PSRAW128,
13827 IX86_BUILTIN_PSRAD128,
13828 IX86_BUILTIN_PSRLW128,
13829 IX86_BUILTIN_PSRLD128,
13830 IX86_BUILTIN_PSRLQ128,
13831 IX86_BUILTIN_PSLLDQI128,
13832 IX86_BUILTIN_PSLLWI128,
13833 IX86_BUILTIN_PSLLDI128,
13834 IX86_BUILTIN_PSLLQI128,
13835 IX86_BUILTIN_PSRAWI128,
13836 IX86_BUILTIN_PSRADI128,
13837 IX86_BUILTIN_PSRLDQI128,
13838 IX86_BUILTIN_PSRLWI128,
13839 IX86_BUILTIN_PSRLDI128,
13840 IX86_BUILTIN_PSRLQI128,
13842 IX86_BUILTIN_PUNPCKHBW128,
13843 IX86_BUILTIN_PUNPCKHWD128,
13844 IX86_BUILTIN_PUNPCKHDQ128,
13845 IX86_BUILTIN_PUNPCKHQDQ128,
13846 IX86_BUILTIN_PUNPCKLBW128,
13847 IX86_BUILTIN_PUNPCKLWD128,
13848 IX86_BUILTIN_PUNPCKLDQ128,
13849 IX86_BUILTIN_PUNPCKLQDQ128,
13851 IX86_BUILTIN_CLFLUSH,
13852 IX86_BUILTIN_MFENCE,
13853 IX86_BUILTIN_LFENCE,
13855 /* Prescott New Instructions. */
13856 IX86_BUILTIN_ADDSUBPS,
13857 IX86_BUILTIN_HADDPS,
13858 IX86_BUILTIN_HSUBPS,
13859 IX86_BUILTIN_MOVSHDUP,
13860 IX86_BUILTIN_MOVSLDUP,
13861 IX86_BUILTIN_ADDSUBPD,
13862 IX86_BUILTIN_HADDPD,
13863 IX86_BUILTIN_HSUBPD,
13864 IX86_BUILTIN_LDDQU,
13866 IX86_BUILTIN_MONITOR,
13867 IX86_BUILTIN_MWAIT,
13869 IX86_BUILTIN_VEC_INIT_V2SI,
13870 IX86_BUILTIN_VEC_INIT_V4HI,
13871 IX86_BUILTIN_VEC_INIT_V8QI,
13872 IX86_BUILTIN_VEC_EXT_V2DF,
13873 IX86_BUILTIN_VEC_EXT_V2DI,
13874 IX86_BUILTIN_VEC_EXT_V4SF,
13875 IX86_BUILTIN_VEC_EXT_V4SI,
13876 IX86_BUILTIN_VEC_EXT_V8HI,
13877 IX86_BUILTIN_VEC_EXT_V2SI,
13878 IX86_BUILTIN_VEC_EXT_V4HI,
13879 IX86_BUILTIN_VEC_SET_V8HI,
13880 IX86_BUILTIN_VEC_SET_V4HI,
13885 #define def_builtin(MASK, NAME, TYPE, CODE) \
13887 if ((MASK) & target_flags \
13888 && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \
13889 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
13890 NULL, NULL_TREE); \
13893 /* Bits for builtin_description.flag. */
13895 /* Set when we don't support the comparison natively, and should
13896 swap_comparison in order to support it. */
13897 #define BUILTIN_DESC_SWAP_OPERANDS 1
13899 struct builtin_description
13901 const unsigned int mask;
13902 const enum insn_code icode;
13903 const char *const name;
13904 const enum ix86_builtins code;
13905 const enum rtx_code comparison;
13906 const unsigned int flag;
13909 static const struct builtin_description bdesc_comi[] =
13911 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
13912 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
13913 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
13914 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
13915 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
13916 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
13917 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
13918 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
13919 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
13920 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
13921 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
13922 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
13923 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
13924 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
13925 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
13926 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
13927 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
13928 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
13929 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
13930 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
13931 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
13932 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
13933 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
13934 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
13937 static const struct builtin_description bdesc_2arg[] =
13940 { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 },
13941 { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 },
13942 { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 },
13943 { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 },
13944 { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 },
13945 { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 },
13946 { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 },
13947 { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 },
13949 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
13950 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
13951 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
13952 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
13953 BUILTIN_DESC_SWAP_OPERANDS },
13954 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
13955 BUILTIN_DESC_SWAP_OPERANDS },
13956 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
13957 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
13958 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
13959 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
13960 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
13961 BUILTIN_DESC_SWAP_OPERANDS },
13962 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
13963 BUILTIN_DESC_SWAP_OPERANDS },
13964 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
13965 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
13966 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
13967 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
13968 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
13969 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
13970 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
13971 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
13972 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
13973 BUILTIN_DESC_SWAP_OPERANDS },
13974 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
13975 BUILTIN_DESC_SWAP_OPERANDS },
13976 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
13978 { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
13979 { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 },
13980 { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 },
13981 { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 },
13983 { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 },
13984 { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 },
13985 { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 },
13986 { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 },
13988 { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 },
13989 { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 },
13990 { MASK_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, 0, 0 },
13991 { MASK_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, 0, 0 },
13992 { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 },
13995 { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
13996 { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
13997 { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
13998 { MASK_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
13999 { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
14000 { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
14001 { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
14002 { MASK_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
14004 { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
14005 { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
14006 { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 },
14007 { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 },
14008 { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 },
14009 { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 },
14010 { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 },
14011 { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 },
14013 { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 },
14014 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
14015 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
14017 { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 },
14018 { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 },
14019 { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 },
14020 { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 },
14022 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
14023 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
14025 { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 },
14026 { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 },
14027 { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 },
14028 { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 },
14029 { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 },
14030 { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 },
14032 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
14033 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
14034 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
14035 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
14037 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
14038 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
14039 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
14040 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
14041 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
14042 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
14045 { MASK_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, 0, 0 },
14046 { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 },
14047 { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 },
14049 { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 },
14050 { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 },
14051 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 },
14053 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 },
14054 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 },
14055 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 },
14056 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 },
14057 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 },
14058 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 },
14060 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 },
14061 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 },
14062 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 },
14063 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 },
14064 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 },
14065 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 },
14067 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 },
14068 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 },
14069 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 },
14070 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 },
14072 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 },
14073 { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 },
14076 { MASK_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, 0, 0 },
14077 { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 },
14078 { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 },
14079 { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 },
14080 { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 },
14081 { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 },
14082 { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 },
14083 { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 },
14085 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
14086 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
14087 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
14088 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
14089 BUILTIN_DESC_SWAP_OPERANDS },
14090 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
14091 BUILTIN_DESC_SWAP_OPERANDS },
14092 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
14093 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
14094 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
14095 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
14096 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
14097 BUILTIN_DESC_SWAP_OPERANDS },
14098 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
14099 BUILTIN_DESC_SWAP_OPERANDS },
14100 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
14101 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
14102 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
14103 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
14104 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
14105 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
14106 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
14107 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
14108 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
14110 { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 },
14111 { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 },
14112 { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 },
14113 { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 },
14115 { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 },
14116 { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 },
14117 { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 },
14118 { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 },
14120 { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 },
14121 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
14122 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
14125 { MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
14126 { MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
14127 { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
14128 { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
14129 { MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
14130 { MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
14131 { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
14132 { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
14134 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
14135 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
14136 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
14137 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
14138 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
14139 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
14140 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
14141 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
14143 { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 },
14144 { MASK_SSE2, CODE_FOR_sse2_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
14146 { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 },
14147 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
14148 { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 },
14149 { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 },
14151 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
14152 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
14154 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
14155 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
14156 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
14157 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
14158 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
14159 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
14161 { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 },
14162 { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 },
14163 { MASK_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, 0, 0 },
14164 { MASK_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, 0, 0 },
14166 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
14167 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
14168 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
14169 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
14170 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
14171 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
14172 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
14173 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
14175 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
14176 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
14177 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
14179 { MASK_SSE2, CODE_FOR_sse2_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
14180 { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 },
14182 { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 },
14183 { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 },
14185 { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 },
14186 { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 },
14187 { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 },
14189 { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 },
14190 { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 },
14191 { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 },
14193 { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 },
14194 { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 },
14196 { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 },
14198 { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
14199 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
14200 { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
14201 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
14204 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
14205 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
14206 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
14207 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
14208 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
14209 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
14212 static const struct builtin_description bdesc_1arg[] =
14214 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
14215 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
14217 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },
14218 { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 },
14219 { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 },
14221 { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 },
14222 { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 },
14223 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 },
14224 { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 },
14225 { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 },
14226 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 },
14228 { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 },
14229 { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 },
14231 { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 },
14233 { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 },
14234 { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 },
14236 { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 },
14237 { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 },
14238 { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 },
14239 { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 },
14240 { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 },
14242 { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 },
14244 { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 },
14245 { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 },
14246 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 },
14247 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 },
14249 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
14250 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
14251 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
14254 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
14255 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
14259 ix86_init_builtins (void)
14262 ix86_init_mmx_sse_builtins ();
14265 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
14266 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
14269 ix86_init_mmx_sse_builtins (void)
14271 const struct builtin_description * d;
14274 tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
14275 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
14276 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
14277 tree V2DI_type_node
14278 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
14279 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
14280 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
14281 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
14282 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
14283 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
14284 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
14286 tree pchar_type_node = build_pointer_type (char_type_node);
14287 tree pcchar_type_node = build_pointer_type (
14288 build_type_variant (char_type_node, 1, 0));
14289 tree pfloat_type_node = build_pointer_type (float_type_node);
14290 tree pcfloat_type_node = build_pointer_type (
14291 build_type_variant (float_type_node, 1, 0));
14292 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
14293 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
14294 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
14297 tree int_ftype_v4sf_v4sf
14298 = build_function_type_list (integer_type_node,
14299 V4SF_type_node, V4SF_type_node, NULL_TREE);
14300 tree v4si_ftype_v4sf_v4sf
14301 = build_function_type_list (V4SI_type_node,
14302 V4SF_type_node, V4SF_type_node, NULL_TREE);
14303 /* MMX/SSE/integer conversions. */
14304 tree int_ftype_v4sf
14305 = build_function_type_list (integer_type_node,
14306 V4SF_type_node, NULL_TREE);
14307 tree int64_ftype_v4sf
14308 = build_function_type_list (long_long_integer_type_node,
14309 V4SF_type_node, NULL_TREE);
14310 tree int_ftype_v8qi
14311 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
14312 tree v4sf_ftype_v4sf_int
14313 = build_function_type_list (V4SF_type_node,
14314 V4SF_type_node, integer_type_node, NULL_TREE);
14315 tree v4sf_ftype_v4sf_int64
14316 = build_function_type_list (V4SF_type_node,
14317 V4SF_type_node, long_long_integer_type_node,
14319 tree v4sf_ftype_v4sf_v2si
14320 = build_function_type_list (V4SF_type_node,
14321 V4SF_type_node, V2SI_type_node, NULL_TREE);
14323 /* Miscellaneous. */
14324 tree v8qi_ftype_v4hi_v4hi
14325 = build_function_type_list (V8QI_type_node,
14326 V4HI_type_node, V4HI_type_node, NULL_TREE);
14327 tree v4hi_ftype_v2si_v2si
14328 = build_function_type_list (V4HI_type_node,
14329 V2SI_type_node, V2SI_type_node, NULL_TREE);
14330 tree v4sf_ftype_v4sf_v4sf_int
14331 = build_function_type_list (V4SF_type_node,
14332 V4SF_type_node, V4SF_type_node,
14333 integer_type_node, NULL_TREE);
14334 tree v2si_ftype_v4hi_v4hi
14335 = build_function_type_list (V2SI_type_node,
14336 V4HI_type_node, V4HI_type_node, NULL_TREE);
14337 tree v4hi_ftype_v4hi_int
14338 = build_function_type_list (V4HI_type_node,
14339 V4HI_type_node, integer_type_node, NULL_TREE);
14340 tree v4hi_ftype_v4hi_di
14341 = build_function_type_list (V4HI_type_node,
14342 V4HI_type_node, long_long_unsigned_type_node,
14344 tree v2si_ftype_v2si_di
14345 = build_function_type_list (V2SI_type_node,
14346 V2SI_type_node, long_long_unsigned_type_node,
14348 tree void_ftype_void
14349 = build_function_type (void_type_node, void_list_node);
14350 tree void_ftype_unsigned
14351 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
14352 tree void_ftype_unsigned_unsigned
14353 = build_function_type_list (void_type_node, unsigned_type_node,
14354 unsigned_type_node, NULL_TREE);
14355 tree void_ftype_pcvoid_unsigned_unsigned
14356 = build_function_type_list (void_type_node, const_ptr_type_node,
14357 unsigned_type_node, unsigned_type_node,
14359 tree unsigned_ftype_void
14360 = build_function_type (unsigned_type_node, void_list_node);
14361 tree v2si_ftype_v4sf
14362 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
14363 /* Loads/stores. */
14364 tree void_ftype_v8qi_v8qi_pchar
14365 = build_function_type_list (void_type_node,
14366 V8QI_type_node, V8QI_type_node,
14367 pchar_type_node, NULL_TREE);
14368 tree v4sf_ftype_pcfloat
14369 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
14370 /* @@@ the type is bogus */
14371 tree v4sf_ftype_v4sf_pv2si
14372 = build_function_type_list (V4SF_type_node,
14373 V4SF_type_node, pv2si_type_node, NULL_TREE);
14374 tree void_ftype_pv2si_v4sf
14375 = build_function_type_list (void_type_node,
14376 pv2si_type_node, V4SF_type_node, NULL_TREE);
14377 tree void_ftype_pfloat_v4sf
14378 = build_function_type_list (void_type_node,
14379 pfloat_type_node, V4SF_type_node, NULL_TREE);
14380 tree void_ftype_pdi_di
14381 = build_function_type_list (void_type_node,
14382 pdi_type_node, long_long_unsigned_type_node,
14384 tree void_ftype_pv2di_v2di
14385 = build_function_type_list (void_type_node,
14386 pv2di_type_node, V2DI_type_node, NULL_TREE);
14387 /* Normal vector unops. */
14388 tree v4sf_ftype_v4sf
14389 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
14391 /* Normal vector binops. */
14392 tree v4sf_ftype_v4sf_v4sf
14393 = build_function_type_list (V4SF_type_node,
14394 V4SF_type_node, V4SF_type_node, NULL_TREE);
14395 tree v8qi_ftype_v8qi_v8qi
14396 = build_function_type_list (V8QI_type_node,
14397 V8QI_type_node, V8QI_type_node, NULL_TREE);
14398 tree v4hi_ftype_v4hi_v4hi
14399 = build_function_type_list (V4HI_type_node,
14400 V4HI_type_node, V4HI_type_node, NULL_TREE);
14401 tree v2si_ftype_v2si_v2si
14402 = build_function_type_list (V2SI_type_node,
14403 V2SI_type_node, V2SI_type_node, NULL_TREE);
14404 tree di_ftype_di_di
14405 = build_function_type_list (long_long_unsigned_type_node,
14406 long_long_unsigned_type_node,
14407 long_long_unsigned_type_node, NULL_TREE);
14409 tree v2si_ftype_v2sf
14410 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
14411 tree v2sf_ftype_v2si
14412 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
14413 tree v2si_ftype_v2si
14414 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
14415 tree v2sf_ftype_v2sf
14416 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
14417 tree v2sf_ftype_v2sf_v2sf
14418 = build_function_type_list (V2SF_type_node,
14419 V2SF_type_node, V2SF_type_node, NULL_TREE);
14420 tree v2si_ftype_v2sf_v2sf
14421 = build_function_type_list (V2SI_type_node,
14422 V2SF_type_node, V2SF_type_node, NULL_TREE);
14423 tree pint_type_node = build_pointer_type (integer_type_node);
14424 tree pdouble_type_node = build_pointer_type (double_type_node);
14425 tree pcdouble_type_node = build_pointer_type (
14426 build_type_variant (double_type_node, 1, 0));
14427 tree int_ftype_v2df_v2df
14428 = build_function_type_list (integer_type_node,
14429 V2DF_type_node, V2DF_type_node, NULL_TREE);
14431 tree void_ftype_pcvoid
14432 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
14433 tree v4sf_ftype_v4si
14434 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
14435 tree v4si_ftype_v4sf
14436 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
14437 tree v2df_ftype_v4si
14438 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
14439 tree v4si_ftype_v2df
14440 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
14441 tree v2si_ftype_v2df
14442 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
14443 tree v4sf_ftype_v2df
14444 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
14445 tree v2df_ftype_v2si
14446 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
14447 tree v2df_ftype_v4sf
14448 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
14449 tree int_ftype_v2df
14450 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
14451 tree int64_ftype_v2df
14452 = build_function_type_list (long_long_integer_type_node,
14453 V2DF_type_node, NULL_TREE);
14454 tree v2df_ftype_v2df_int
14455 = build_function_type_list (V2DF_type_node,
14456 V2DF_type_node, integer_type_node, NULL_TREE);
14457 tree v2df_ftype_v2df_int64
14458 = build_function_type_list (V2DF_type_node,
14459 V2DF_type_node, long_long_integer_type_node,
14461 tree v4sf_ftype_v4sf_v2df
14462 = build_function_type_list (V4SF_type_node,
14463 V4SF_type_node, V2DF_type_node, NULL_TREE);
14464 tree v2df_ftype_v2df_v4sf
14465 = build_function_type_list (V2DF_type_node,
14466 V2DF_type_node, V4SF_type_node, NULL_TREE);
14467 tree v2df_ftype_v2df_v2df_int
14468 = build_function_type_list (V2DF_type_node,
14469 V2DF_type_node, V2DF_type_node,
14472 tree v2df_ftype_v2df_pcdouble
14473 = build_function_type_list (V2DF_type_node,
14474 V2DF_type_node, pcdouble_type_node, NULL_TREE);
14475 tree void_ftype_pdouble_v2df
14476 = build_function_type_list (void_type_node,
14477 pdouble_type_node, V2DF_type_node, NULL_TREE);
14478 tree void_ftype_pint_int
14479 = build_function_type_list (void_type_node,
14480 pint_type_node, integer_type_node, NULL_TREE);
14481 tree void_ftype_v16qi_v16qi_pchar
14482 = build_function_type_list (void_type_node,
14483 V16QI_type_node, V16QI_type_node,
14484 pchar_type_node, NULL_TREE);
14485 tree v2df_ftype_pcdouble
14486 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
14487 tree v2df_ftype_v2df_v2df
14488 = build_function_type_list (V2DF_type_node,
14489 V2DF_type_node, V2DF_type_node, NULL_TREE);
14490 tree v16qi_ftype_v16qi_v16qi
14491 = build_function_type_list (V16QI_type_node,
14492 V16QI_type_node, V16QI_type_node, NULL_TREE);
14493 tree v8hi_ftype_v8hi_v8hi
14494 = build_function_type_list (V8HI_type_node,
14495 V8HI_type_node, V8HI_type_node, NULL_TREE);
14496 tree v4si_ftype_v4si_v4si
14497 = build_function_type_list (V4SI_type_node,
14498 V4SI_type_node, V4SI_type_node, NULL_TREE);
14499 tree v2di_ftype_v2di_v2di
14500 = build_function_type_list (V2DI_type_node,
14501 V2DI_type_node, V2DI_type_node, NULL_TREE);
14502 tree v2di_ftype_v2df_v2df
14503 = build_function_type_list (V2DI_type_node,
14504 V2DF_type_node, V2DF_type_node, NULL_TREE);
14505 tree v2df_ftype_v2df
14506 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
14507 tree v2di_ftype_v2di_int
14508 = build_function_type_list (V2DI_type_node,
14509 V2DI_type_node, integer_type_node, NULL_TREE);
14510 tree v4si_ftype_v4si_int
14511 = build_function_type_list (V4SI_type_node,
14512 V4SI_type_node, integer_type_node, NULL_TREE);
14513 tree v8hi_ftype_v8hi_int
14514 = build_function_type_list (V8HI_type_node,
14515 V8HI_type_node, integer_type_node, NULL_TREE);
14516 tree v8hi_ftype_v8hi_v2di
14517 = build_function_type_list (V8HI_type_node,
14518 V8HI_type_node, V2DI_type_node, NULL_TREE);
14519 tree v4si_ftype_v4si_v2di
14520 = build_function_type_list (V4SI_type_node,
14521 V4SI_type_node, V2DI_type_node, NULL_TREE);
14522 tree v4si_ftype_v8hi_v8hi
14523 = build_function_type_list (V4SI_type_node,
14524 V8HI_type_node, V8HI_type_node, NULL_TREE);
14525 tree di_ftype_v8qi_v8qi
14526 = build_function_type_list (long_long_unsigned_type_node,
14527 V8QI_type_node, V8QI_type_node, NULL_TREE);
14528 tree di_ftype_v2si_v2si
14529 = build_function_type_list (long_long_unsigned_type_node,
14530 V2SI_type_node, V2SI_type_node, NULL_TREE);
14531 tree v2di_ftype_v16qi_v16qi
14532 = build_function_type_list (V2DI_type_node,
14533 V16QI_type_node, V16QI_type_node, NULL_TREE);
14534 tree v2di_ftype_v4si_v4si
14535 = build_function_type_list (V2DI_type_node,
14536 V4SI_type_node, V4SI_type_node, NULL_TREE);
14537 tree int_ftype_v16qi
14538 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
14539 tree v16qi_ftype_pcchar
14540 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
14541 tree void_ftype_pchar_v16qi
14542 = build_function_type_list (void_type_node,
14543 pchar_type_node, V16QI_type_node, NULL_TREE);
14546 tree float128_type;
14549 /* The __float80 type. */
14550 if (TYPE_MODE (long_double_type_node) == XFmode)
14551 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
14555 /* The __float80 type. */
14556 float80_type = make_node (REAL_TYPE);
14557 TYPE_PRECISION (float80_type) = 80;
14558 layout_type (float80_type);
14559 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
14562 float128_type = make_node (REAL_TYPE);
14563 TYPE_PRECISION (float128_type) = 128;
14564 layout_type (float128_type);
14565 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
14567 /* Add all builtins that are more or less simple operations on two
14569 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
14571 /* Use one of the operands; the target can have a different mode for
14572 mask-generating compares. */
14573 enum machine_mode mode;
14578 mode = insn_data[d->icode].operand[1].mode;
14583 type = v16qi_ftype_v16qi_v16qi;
14586 type = v8hi_ftype_v8hi_v8hi;
14589 type = v4si_ftype_v4si_v4si;
14592 type = v2di_ftype_v2di_v2di;
14595 type = v2df_ftype_v2df_v2df;
14598 type = v4sf_ftype_v4sf_v4sf;
14601 type = v8qi_ftype_v8qi_v8qi;
14604 type = v4hi_ftype_v4hi_v4hi;
14607 type = v2si_ftype_v2si_v2si;
14610 type = di_ftype_di_di;
14614 gcc_unreachable ();
14617 /* Override for comparisons. */
14618 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
14619 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
14620 type = v4si_ftype_v4sf_v4sf;
14622 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
14623 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
14624 type = v2di_ftype_v2df_v2df;
14626 def_builtin (d->mask, d->name, type, d->code);
14629 /* Add the remaining MMX insns with somewhat more complicated types. */
14630 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
14631 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
14632 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
14633 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
14635 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
14636 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
14637 def_builtin (MASK_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
14639 def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
14640 def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
14642 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
14643 def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
14645 /* comi/ucomi insns. */
14646 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
14647 if (d->mask == MASK_SSE2)
14648 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
14650 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
14652 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
14653 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
14654 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
14656 def_builtin (MASK_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
14657 def_builtin (MASK_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
14658 def_builtin (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
14659 def_builtin (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
14660 def_builtin (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
14661 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
14662 def_builtin (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
14663 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
14664 def_builtin (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
14665 def_builtin (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
14666 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
14668 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
14670 def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
14671 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
14673 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
14674 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
14675 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
14676 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
14678 def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
14679 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
14680 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
14681 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
14683 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
14685 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
14687 def_builtin (MASK_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
14688 def_builtin (MASK_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
14689 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
14690 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
14691 def_builtin (MASK_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
14692 def_builtin (MASK_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
14694 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
14696 /* Original 3DNow! */
14697 def_builtin (MASK_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
14698 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
14699 def_builtin (MASK_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
14700 def_builtin (MASK_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
14701 def_builtin (MASK_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
14702 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
14703 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
14704 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
14705 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
14706 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
14707 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
14708 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
14709 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
14710 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
14711 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
14712 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
14713 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
14714 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
14715 def_builtin (MASK_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
14716 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
14718 /* 3DNow! extension as used in the Athlon CPU. */
14719 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
14720 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
14721 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
14722 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
14723 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
14724 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
14727 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
14729 def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
14730 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
14732 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
14733 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
14735 def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
14736 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
14737 def_builtin (MASK_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
14738 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
14739 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
14741 def_builtin (MASK_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
14742 def_builtin (MASK_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
14743 def_builtin (MASK_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
14744 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
14746 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
14747 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
14749 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
14751 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
14752 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
14754 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
14755 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
14756 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
14757 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
14758 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
14760 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
14762 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
14763 def_builtin (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
14764 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
14765 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
14767 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
14768 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
14769 def_builtin (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
14771 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
14772 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
14773 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
14774 def_builtin (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
14776 def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
14777 def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
14778 def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
14780 def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
14781 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
14783 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
14784 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
14786 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128);
14787 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128);
14788 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
14790 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128);
14791 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128);
14792 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
14794 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128);
14795 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128);
14797 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
14798 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
14799 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
14800 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
14802 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
14803 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
14804 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
14805 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
14807 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
14808 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
14810 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
14812 /* Prescott New Instructions. */
14813 def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
14814 void_ftype_pcvoid_unsigned_unsigned,
14815 IX86_BUILTIN_MONITOR);
14816 def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
14817 void_ftype_unsigned_unsigned,
14818 IX86_BUILTIN_MWAIT);
14819 def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
14821 IX86_BUILTIN_MOVSHDUP);
14822 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
14824 IX86_BUILTIN_MOVSLDUP);
14825 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
14826 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
14828 /* Access to the vec_init patterns. */
14829 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
14830 integer_type_node, NULL_TREE);
14831 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
14832 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
14834 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
14835 short_integer_type_node,
14836 short_integer_type_node,
14837 short_integer_type_node, NULL_TREE);
14838 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi",
14839 ftype, IX86_BUILTIN_VEC_INIT_V4HI);
14841 ftype = build_function_type_list (V8QI_type_node, char_type_node,
14842 char_type_node, char_type_node,
14843 char_type_node, char_type_node,
14844 char_type_node, char_type_node,
14845 char_type_node, NULL_TREE);
14846 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi",
14847 ftype, IX86_BUILTIN_VEC_INIT_V8QI);
14849 /* Access to the vec_extract patterns. */
14850 ftype = build_function_type_list (double_type_node, V2DF_type_node,
14851 integer_type_node, NULL_TREE);
14852 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df",
14853 ftype, IX86_BUILTIN_VEC_EXT_V2DF);
14855 ftype = build_function_type_list (long_long_integer_type_node,
14856 V2DI_type_node, integer_type_node,
14858 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di",
14859 ftype, IX86_BUILTIN_VEC_EXT_V2DI);
14861 ftype = build_function_type_list (float_type_node, V4SF_type_node,
14862 integer_type_node, NULL_TREE);
14863 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
14864 ftype, IX86_BUILTIN_VEC_EXT_V4SF);
14866 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
14867 integer_type_node, NULL_TREE);
14868 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
14869 ftype, IX86_BUILTIN_VEC_EXT_V4SI);
14871 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
14872 integer_type_node, NULL_TREE);
14873 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
14874 ftype, IX86_BUILTIN_VEC_EXT_V8HI);
14876 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
14877 integer_type_node, NULL_TREE);
14878 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi",
14879 ftype, IX86_BUILTIN_VEC_EXT_V4HI);
14881 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
14882 integer_type_node, NULL_TREE);
14883 def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
14884 ftype, IX86_BUILTIN_VEC_EXT_V2SI);
14886 /* Access to the vec_set patterns. */
14887 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
14889 integer_type_node, NULL_TREE);
14890 def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi",
14891 ftype, IX86_BUILTIN_VEC_SET_V8HI);
14893 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
14895 integer_type_node, NULL_TREE);
14896 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi",
14897 ftype, IX86_BUILTIN_VEC_SET_V4HI);
14900 /* Errors in the source file can cause expand_expr to return const0_rtx
14901 where we expect a vector. To avoid crashing, use one of the vector
14902 clear instructions. */
14904 safe_vector_operand (rtx x, enum machine_mode mode)
14906 if (x == const0_rtx)
14907 x = CONST0_RTX (mode);
14911 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
14914 ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
14917 tree arg0 = TREE_VALUE (arglist);
14918 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14919 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14920 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14921 enum machine_mode tmode = insn_data[icode].operand[0].mode;
14922 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
14923 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
14925 if (VECTOR_MODE_P (mode0))
14926 op0 = safe_vector_operand (op0, mode0);
14927 if (VECTOR_MODE_P (mode1))
14928 op1 = safe_vector_operand (op1, mode1);
14930 if (optimize || !target
14931 || GET_MODE (target) != tmode
14932 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14933 target = gen_reg_rtx (tmode);
14935 if (GET_MODE (op1) == SImode && mode1 == TImode)
14937 rtx x = gen_reg_rtx (V4SImode);
14938 emit_insn (gen_sse2_loadd (x, op1));
14939 op1 = gen_lowpart (TImode, x);
14942 /* The insn must want input operands in the same modes as the
14944 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
14945 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
14947 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
14948 op0 = copy_to_mode_reg (mode0, op0);
14949 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
14950 op1 = copy_to_mode_reg (mode1, op1);
14952 /* ??? Using ix86_fixup_binary_operands is problematic when
14953 we've got mismatched modes. Fake it. */
14959 if (tmode == mode0 && tmode == mode1)
14961 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
14965 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
14967 op0 = force_reg (mode0, op0);
14968 op1 = force_reg (mode1, op1);
14969 target = gen_reg_rtx (tmode);
14972 pat = GEN_FCN (icode) (target, op0, op1);
14979 /* Subroutine of ix86_expand_builtin to take care of stores. */
14982 ix86_expand_store_builtin (enum insn_code icode, tree arglist)
14985 tree arg0 = TREE_VALUE (arglist);
14986 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14987 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14988 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14989 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
14990 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
14992 if (VECTOR_MODE_P (mode1))
14993 op1 = safe_vector_operand (op1, mode1);
14995 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
14996 op1 = copy_to_mode_reg (mode1, op1);
14998 pat = GEN_FCN (icode) (op0, op1);
15004 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
15007 ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
15008 rtx target, int do_load)
15011 tree arg0 = TREE_VALUE (arglist);
15012 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15013 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15014 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15016 if (optimize || !target
15017 || GET_MODE (target) != tmode
15018 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15019 target = gen_reg_rtx (tmode);
15021 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15024 if (VECTOR_MODE_P (mode0))
15025 op0 = safe_vector_operand (op0, mode0);
15027 if ((optimize && !register_operand (op0, mode0))
15028 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15029 op0 = copy_to_mode_reg (mode0, op0);
15032 pat = GEN_FCN (icode) (target, op0);
15039 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
15040 sqrtss, rsqrtss, rcpss. */
15043 ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
15046 tree arg0 = TREE_VALUE (arglist);
15047 rtx op1, op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15048 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15049 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15051 if (optimize || !target
15052 || GET_MODE (target) != tmode
15053 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15054 target = gen_reg_rtx (tmode);
15056 if (VECTOR_MODE_P (mode0))
15057 op0 = safe_vector_operand (op0, mode0);
15059 if ((optimize && !register_operand (op0, mode0))
15060 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15061 op0 = copy_to_mode_reg (mode0, op0);
15064 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
15065 op1 = copy_to_mode_reg (mode0, op1);
15067 pat = GEN_FCN (icode) (target, op0, op1);
15074 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
15077 ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
15081 tree arg0 = TREE_VALUE (arglist);
15082 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15083 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15084 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15086 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
15087 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
15088 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
15089 enum rtx_code comparison = d->comparison;
15091 if (VECTOR_MODE_P (mode0))
15092 op0 = safe_vector_operand (op0, mode0);
15093 if (VECTOR_MODE_P (mode1))
15094 op1 = safe_vector_operand (op1, mode1);
15096 /* Swap operands if we have a comparison that isn't available in
15098 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
15100 rtx tmp = gen_reg_rtx (mode1);
15101 emit_move_insn (tmp, op1);
15106 if (optimize || !target
15107 || GET_MODE (target) != tmode
15108 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
15109 target = gen_reg_rtx (tmode);
15111 if ((optimize && !register_operand (op0, mode0))
15112 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
15113 op0 = copy_to_mode_reg (mode0, op0);
15114 if ((optimize && !register_operand (op1, mode1))
15115 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
15116 op1 = copy_to_mode_reg (mode1, op1);
15118 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
15119 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
15126 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
15129 ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
15133 tree arg0 = TREE_VALUE (arglist);
15134 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15135 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15136 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15138 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
15139 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
15140 enum rtx_code comparison = d->comparison;
15142 if (VECTOR_MODE_P (mode0))
15143 op0 = safe_vector_operand (op0, mode0);
15144 if (VECTOR_MODE_P (mode1))
15145 op1 = safe_vector_operand (op1, mode1);
15147 /* Swap operands if we have a comparison that isn't available in
15149 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
15156 target = gen_reg_rtx (SImode);
15157 emit_move_insn (target, const0_rtx);
15158 target = gen_rtx_SUBREG (QImode, target, 0);
15160 if ((optimize && !register_operand (op0, mode0))
15161 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15162 op0 = copy_to_mode_reg (mode0, op0);
15163 if ((optimize && !register_operand (op1, mode1))
15164 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15165 op1 = copy_to_mode_reg (mode1, op1);
15167 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
15168 pat = GEN_FCN (d->icode) (op0, op1);
15172 emit_insn (gen_rtx_SET (VOIDmode,
15173 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
15174 gen_rtx_fmt_ee (comparison, QImode,
15178 return SUBREG_REG (target);
15181 /* Return the integer constant in ARG. Constrain it to be in the range
15182 of the subparts of VEC_TYPE; issue an error if not. */
15185 get_element_number (tree vec_type, tree arg)
15187 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15189 if (!host_integerp (arg, 1)
15190 || (elt = tree_low_cst (arg, 1), elt > max))
15192 error ("selector must be an integer constant in the range 0..%wi", max);
15199 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15200 ix86_expand_vector_init. We DO have language-level syntax for this, in
15201 the form of (type){ init-list }. Except that since we can't place emms
15202 instructions from inside the compiler, we can't allow the use of MMX
15203 registers unless the user explicitly asks for it. So we do *not* define
15204 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
15205 we have builtins invoked by mmintrin.h that gives us license to emit
15206 these sorts of instructions. */
15209 ix86_expand_vec_init_builtin (tree type, tree arglist, rtx target)
15211 enum machine_mode tmode = TYPE_MODE (type);
15212 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
15213 int i, n_elt = GET_MODE_NUNITS (tmode);
15214 rtvec v = rtvec_alloc (n_elt);
15216 gcc_assert (VECTOR_MODE_P (tmode));
15218 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
15220 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
15221 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15224 gcc_assert (arglist == NULL);
15226 if (!target || !register_operand (target, tmode))
15227 target = gen_reg_rtx (tmode);
15229 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
15233 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15234 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
15235 had a language-level syntax for referencing vector elements. */
15238 ix86_expand_vec_ext_builtin (tree arglist, rtx target)
15240 enum machine_mode tmode, mode0;
15245 arg0 = TREE_VALUE (arglist);
15246 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15248 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15249 elt = get_element_number (TREE_TYPE (arg0), arg1);
15251 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15252 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15253 gcc_assert (VECTOR_MODE_P (mode0));
15255 op0 = force_reg (mode0, op0);
15257 if (optimize || !target || !register_operand (target, tmode))
15258 target = gen_reg_rtx (tmode);
15260 ix86_expand_vector_extract (true, target, op0, elt);
15265 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15266 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
15267 a language-level syntax for referencing vector elements. */
15270 ix86_expand_vec_set_builtin (tree arglist)
15272 enum machine_mode tmode, mode1;
15273 tree arg0, arg1, arg2;
15277 arg0 = TREE_VALUE (arglist);
15278 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15279 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15281 tmode = TYPE_MODE (TREE_TYPE (arg0));
15282 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15283 gcc_assert (VECTOR_MODE_P (tmode));
15285 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
15286 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
15287 elt = get_element_number (TREE_TYPE (arg0), arg2);
15289 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15290 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15292 op0 = force_reg (tmode, op0);
15293 op1 = force_reg (mode1, op1);
15295 ix86_expand_vector_set (true, op0, op1, elt);
15300 /* Expand an expression EXP that calls a built-in function,
15301 with result going to TARGET if that's convenient
15302 (and in mode MODE if that's convenient).
15303 SUBTARGET may be used as the target for computing one of EXP's operands.
15304 IGNORE is nonzero if the value is to be ignored. */
15307 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15308 enum machine_mode mode ATTRIBUTE_UNUSED,
15309 int ignore ATTRIBUTE_UNUSED)
15311 const struct builtin_description *d;
15313 enum insn_code icode;
15314 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
15315 tree arglist = TREE_OPERAND (exp, 1);
15316 tree arg0, arg1, arg2;
15317 rtx op0, op1, op2, pat;
15318 enum machine_mode tmode, mode0, mode1, mode2;
15319 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15323 case IX86_BUILTIN_EMMS:
15324 emit_insn (gen_mmx_emms ());
15327 case IX86_BUILTIN_SFENCE:
15328 emit_insn (gen_sse_sfence ());
15331 case IX86_BUILTIN_MASKMOVQ:
15332 case IX86_BUILTIN_MASKMOVDQU:
15333 icode = (fcode == IX86_BUILTIN_MASKMOVQ
15334 ? CODE_FOR_mmx_maskmovq
15335 : CODE_FOR_sse2_maskmovdqu);
15336 /* Note the arg order is different from the operand order. */
15337 arg1 = TREE_VALUE (arglist);
15338 arg2 = TREE_VALUE (TREE_CHAIN (arglist));
15339 arg0 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15340 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15341 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15342 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15343 mode0 = insn_data[icode].operand[0].mode;
15344 mode1 = insn_data[icode].operand[1].mode;
15345 mode2 = insn_data[icode].operand[2].mode;
15347 op0 = force_reg (Pmode, op0);
15348 op0 = gen_rtx_MEM (mode1, op0);
15350 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15351 op0 = copy_to_mode_reg (mode0, op0);
15352 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15353 op1 = copy_to_mode_reg (mode1, op1);
15354 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
15355 op2 = copy_to_mode_reg (mode2, op2);
15356 pat = GEN_FCN (icode) (op0, op1, op2);
15362 case IX86_BUILTIN_SQRTSS:
15363 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, arglist, target);
15364 case IX86_BUILTIN_RSQRTSS:
15365 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, arglist, target);
15366 case IX86_BUILTIN_RCPSS:
15367 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, arglist, target);
15369 case IX86_BUILTIN_LOADUPS:
15370 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, arglist, target, 1);
15372 case IX86_BUILTIN_STOREUPS:
15373 return ix86_expand_store_builtin (CODE_FOR_sse_movups, arglist);
15375 case IX86_BUILTIN_LOADHPS:
15376 case IX86_BUILTIN_LOADLPS:
15377 case IX86_BUILTIN_LOADHPD:
15378 case IX86_BUILTIN_LOADLPD:
15379 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
15380 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
15381 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
15382 : CODE_FOR_sse2_loadlpd);
15383 arg0 = TREE_VALUE (arglist);
15384 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15385 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15386 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15387 tmode = insn_data[icode].operand[0].mode;
15388 mode0 = insn_data[icode].operand[1].mode;
15389 mode1 = insn_data[icode].operand[2].mode;
15391 op0 = force_reg (mode0, op0);
15392 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
15393 if (optimize || target == 0
15394 || GET_MODE (target) != tmode
15395 || !register_operand (target, tmode))
15396 target = gen_reg_rtx (tmode);
15397 pat = GEN_FCN (icode) (target, op0, op1);
15403 case IX86_BUILTIN_STOREHPS:
15404 case IX86_BUILTIN_STORELPS:
15405 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
15406 : CODE_FOR_sse_storelps);
15407 arg0 = TREE_VALUE (arglist);
15408 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15409 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15410 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15411 mode0 = insn_data[icode].operand[0].mode;
15412 mode1 = insn_data[icode].operand[1].mode;
15414 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15415 op1 = force_reg (mode1, op1);
15417 pat = GEN_FCN (icode) (op0, op1);
15423 case IX86_BUILTIN_MOVNTPS:
15424 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, arglist);
15425 case IX86_BUILTIN_MOVNTQ:
15426 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, arglist);
15428 case IX86_BUILTIN_LDMXCSR:
15429 op0 = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
15430 target = assign_386_stack_local (SImode, SLOT_TEMP);
15431 emit_move_insn (target, op0);
15432 emit_insn (gen_sse_ldmxcsr (target));
15435 case IX86_BUILTIN_STMXCSR:
15436 target = assign_386_stack_local (SImode, SLOT_TEMP);
15437 emit_insn (gen_sse_stmxcsr (target));
15438 return copy_to_mode_reg (SImode, target);
15440 case IX86_BUILTIN_SHUFPS:
15441 case IX86_BUILTIN_SHUFPD:
15442 icode = (fcode == IX86_BUILTIN_SHUFPS
15443 ? CODE_FOR_sse_shufps
15444 : CODE_FOR_sse2_shufpd);
15445 arg0 = TREE_VALUE (arglist);
15446 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15447 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15448 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15449 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15450 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15451 tmode = insn_data[icode].operand[0].mode;
15452 mode0 = insn_data[icode].operand[1].mode;
15453 mode1 = insn_data[icode].operand[2].mode;
15454 mode2 = insn_data[icode].operand[3].mode;
15456 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15457 op0 = copy_to_mode_reg (mode0, op0);
15458 if ((optimize && !register_operand (op1, mode1))
15459 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
15460 op1 = copy_to_mode_reg (mode1, op1);
15461 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15463 /* @@@ better error message */
15464 error ("mask must be an immediate");
15465 return gen_reg_rtx (tmode);
15467 if (optimize || target == 0
15468 || GET_MODE (target) != tmode
15469 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15470 target = gen_reg_rtx (tmode);
15471 pat = GEN_FCN (icode) (target, op0, op1, op2);
15477 case IX86_BUILTIN_PSHUFW:
15478 case IX86_BUILTIN_PSHUFD:
15479 case IX86_BUILTIN_PSHUFHW:
15480 case IX86_BUILTIN_PSHUFLW:
15481 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
15482 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
15483 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
15484 : CODE_FOR_mmx_pshufw);
15485 arg0 = TREE_VALUE (arglist);
15486 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15487 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15488 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15489 tmode = insn_data[icode].operand[0].mode;
15490 mode1 = insn_data[icode].operand[1].mode;
15491 mode2 = insn_data[icode].operand[2].mode;
15493 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15494 op0 = copy_to_mode_reg (mode1, op0);
15495 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15497 /* @@@ better error message */
15498 error ("mask must be an immediate");
15502 || GET_MODE (target) != tmode
15503 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15504 target = gen_reg_rtx (tmode);
15505 pat = GEN_FCN (icode) (target, op0, op1);
15511 case IX86_BUILTIN_PSLLDQI128:
15512 case IX86_BUILTIN_PSRLDQI128:
15513 icode = ( fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
15514 : CODE_FOR_sse2_lshrti3);
15515 arg0 = TREE_VALUE (arglist);
15516 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15517 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15518 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15519 tmode = insn_data[icode].operand[0].mode;
15520 mode1 = insn_data[icode].operand[1].mode;
15521 mode2 = insn_data[icode].operand[2].mode;
15523 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15525 op0 = copy_to_reg (op0);
15526 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
15528 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15530 error ("shift must be an immediate");
15533 target = gen_reg_rtx (V2DImode);
15534 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), op0, op1);
15540 case IX86_BUILTIN_FEMMS:
15541 emit_insn (gen_mmx_femms ());
15544 case IX86_BUILTIN_PAVGUSB:
15545 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, arglist, target);
15547 case IX86_BUILTIN_PF2ID:
15548 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, arglist, target, 0);
15550 case IX86_BUILTIN_PFACC:
15551 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, arglist, target);
15553 case IX86_BUILTIN_PFADD:
15554 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, arglist, target);
15556 case IX86_BUILTIN_PFCMPEQ:
15557 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, arglist, target);
15559 case IX86_BUILTIN_PFCMPGE:
15560 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, arglist, target);
15562 case IX86_BUILTIN_PFCMPGT:
15563 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, arglist, target);
15565 case IX86_BUILTIN_PFMAX:
15566 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, arglist, target);
15568 case IX86_BUILTIN_PFMIN:
15569 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, arglist, target);
15571 case IX86_BUILTIN_PFMUL:
15572 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, arglist, target);
15574 case IX86_BUILTIN_PFRCP:
15575 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, arglist, target, 0);
15577 case IX86_BUILTIN_PFRCPIT1:
15578 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, arglist, target);
15580 case IX86_BUILTIN_PFRCPIT2:
15581 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, arglist, target);
15583 case IX86_BUILTIN_PFRSQIT1:
15584 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, arglist, target);
15586 case IX86_BUILTIN_PFRSQRT:
15587 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, arglist, target, 0);
15589 case IX86_BUILTIN_PFSUB:
15590 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, arglist, target);
15592 case IX86_BUILTIN_PFSUBR:
15593 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, arglist, target);
15595 case IX86_BUILTIN_PI2FD:
15596 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, arglist, target, 0);
15598 case IX86_BUILTIN_PMULHRW:
15599 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, arglist, target);
15601 case IX86_BUILTIN_PF2IW:
15602 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, arglist, target, 0);
15604 case IX86_BUILTIN_PFNACC:
15605 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, arglist, target);
15607 case IX86_BUILTIN_PFPNACC:
15608 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, arglist, target);
15610 case IX86_BUILTIN_PI2FW:
15611 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, arglist, target, 0);
15613 case IX86_BUILTIN_PSWAPDSI:
15614 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, arglist, target, 0);
15616 case IX86_BUILTIN_PSWAPDSF:
15617 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, arglist, target, 0);
15619 case IX86_BUILTIN_SQRTSD:
15620 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, arglist, target);
15621 case IX86_BUILTIN_LOADUPD:
15622 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, arglist, target, 1);
15623 case IX86_BUILTIN_STOREUPD:
15624 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, arglist);
15626 case IX86_BUILTIN_MFENCE:
15627 emit_insn (gen_sse2_mfence ());
15629 case IX86_BUILTIN_LFENCE:
15630 emit_insn (gen_sse2_lfence ());
15633 case IX86_BUILTIN_CLFLUSH:
15634 arg0 = TREE_VALUE (arglist);
15635 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15636 icode = CODE_FOR_sse2_clflush;
15637 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
15638 op0 = copy_to_mode_reg (Pmode, op0);
15640 emit_insn (gen_sse2_clflush (op0));
15643 case IX86_BUILTIN_MOVNTPD:
15644 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, arglist);
15645 case IX86_BUILTIN_MOVNTDQ:
15646 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, arglist);
15647 case IX86_BUILTIN_MOVNTI:
15648 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, arglist);
15650 case IX86_BUILTIN_LOADDQU:
15651 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1);
15652 case IX86_BUILTIN_STOREDQU:
15653 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist);
15655 case IX86_BUILTIN_MONITOR:
15656 arg0 = TREE_VALUE (arglist);
15657 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15658 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15659 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15660 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15661 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15663 op0 = copy_to_mode_reg (SImode, op0);
15665 op1 = copy_to_mode_reg (SImode, op1);
15667 op2 = copy_to_mode_reg (SImode, op2);
15668 emit_insn (gen_sse3_monitor (op0, op1, op2));
15671 case IX86_BUILTIN_MWAIT:
15672 arg0 = TREE_VALUE (arglist);
15673 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15674 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15675 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15677 op0 = copy_to_mode_reg (SImode, op0);
15679 op1 = copy_to_mode_reg (SImode, op1);
15680 emit_insn (gen_sse3_mwait (op0, op1));
15683 case IX86_BUILTIN_LDDQU:
15684 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
15687 case IX86_BUILTIN_VEC_INIT_V2SI:
15688 case IX86_BUILTIN_VEC_INIT_V4HI:
15689 case IX86_BUILTIN_VEC_INIT_V8QI:
15690 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
15692 case IX86_BUILTIN_VEC_EXT_V2DF:
15693 case IX86_BUILTIN_VEC_EXT_V2DI:
15694 case IX86_BUILTIN_VEC_EXT_V4SF:
15695 case IX86_BUILTIN_VEC_EXT_V4SI:
15696 case IX86_BUILTIN_VEC_EXT_V8HI:
15697 case IX86_BUILTIN_VEC_EXT_V2SI:
15698 case IX86_BUILTIN_VEC_EXT_V4HI:
15699 return ix86_expand_vec_ext_builtin (arglist, target);
15701 case IX86_BUILTIN_VEC_SET_V8HI:
15702 case IX86_BUILTIN_VEC_SET_V4HI:
15703 return ix86_expand_vec_set_builtin (arglist);
15709 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
15710 if (d->code == fcode)
15712 /* Compares are treated specially. */
15713 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
15714 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
15715 || d->icode == CODE_FOR_sse2_maskcmpv2df3
15716 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
15717 return ix86_expand_sse_compare (d, arglist, target);
15719 return ix86_expand_binop_builtin (d->icode, arglist, target);
15722 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
15723 if (d->code == fcode)
15724 return ix86_expand_unop_builtin (d->icode, arglist, target, 0);
15726 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
15727 if (d->code == fcode)
15728 return ix86_expand_sse_comi (d, arglist, target);
15730 gcc_unreachable ();
15733 /* Store OPERAND to the memory after reload is completed. This means
15734 that we can't easily use assign_stack_local. */
15736 ix86_force_to_memory (enum machine_mode mode, rtx operand)
15740 gcc_assert (reload_completed);
15741 if (TARGET_RED_ZONE)
15743 result = gen_rtx_MEM (mode,
15744 gen_rtx_PLUS (Pmode,
15746 GEN_INT (-RED_ZONE_SIZE)));
15747 emit_move_insn (result, operand);
15749 else if (!TARGET_RED_ZONE && TARGET_64BIT)
15755 operand = gen_lowpart (DImode, operand);
15759 gen_rtx_SET (VOIDmode,
15760 gen_rtx_MEM (DImode,
15761 gen_rtx_PRE_DEC (DImode,
15762 stack_pointer_rtx)),
15766 gcc_unreachable ();
15768 result = gen_rtx_MEM (mode, stack_pointer_rtx);
15777 split_di (&operand, 1, operands, operands + 1);
15779 gen_rtx_SET (VOIDmode,
15780 gen_rtx_MEM (SImode,
15781 gen_rtx_PRE_DEC (Pmode,
15782 stack_pointer_rtx)),
15785 gen_rtx_SET (VOIDmode,
15786 gen_rtx_MEM (SImode,
15787 gen_rtx_PRE_DEC (Pmode,
15788 stack_pointer_rtx)),
15793 /* Store HImodes as SImodes. */
15794 operand = gen_lowpart (SImode, operand);
15798 gen_rtx_SET (VOIDmode,
15799 gen_rtx_MEM (GET_MODE (operand),
15800 gen_rtx_PRE_DEC (SImode,
15801 stack_pointer_rtx)),
15805 gcc_unreachable ();
15807 result = gen_rtx_MEM (mode, stack_pointer_rtx);
15812 /* Free operand from the memory. */
15814 ix86_free_from_memory (enum machine_mode mode)
15816 if (!TARGET_RED_ZONE)
15820 if (mode == DImode || TARGET_64BIT)
15824 /* Use LEA to deallocate stack space. In peephole2 it will be converted
15825 to pop or add instruction if registers are available. */
15826 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
15827 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
15832 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
15833 QImode must go into class Q_REGS.
15834 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
15835 movdf to do mem-to-mem moves through integer regs. */
15837 ix86_preferred_reload_class (rtx x, enum reg_class class)
15839 /* We're only allowed to return a subclass of CLASS. Many of the
15840 following checks fail for NO_REGS, so eliminate that early. */
15841 if (class == NO_REGS)
15844 /* All classes can load zeros. */
15845 if (x == CONST0_RTX (GET_MODE (x)))
15848 /* Floating-point constants need more complex checks. */
15849 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
15851 /* General regs can load everything. */
15852 if (reg_class_subset_p (class, GENERAL_REGS))
15855 /* Floats can load 0 and 1 plus some others. Note that we eliminated
15856 zero above. We only want to wind up preferring 80387 registers if
15857 we plan on doing computation with them. */
15859 && (TARGET_MIX_SSE_I387
15860 || !(TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (x))))
15861 && standard_80387_constant_p (x))
15863 /* Limit class to non-sse. */
15864 if (class == FLOAT_SSE_REGS)
15866 if (class == FP_TOP_SSE_REGS)
15868 if (class == FP_SECOND_SSE_REGS)
15869 return FP_SECOND_REG;
15870 if (class == FLOAT_INT_REGS || class == FLOAT_REGS)
15876 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x))
15878 if (MAYBE_SSE_CLASS_P (class) && CONSTANT_P (x))
15881 /* Generally when we see PLUS here, it's the function invariant
15882 (plus soft-fp const_int). Which can only be computed into general
15884 if (GET_CODE (x) == PLUS)
15885 return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS;
15887 /* QImode constants are easy to load, but non-constant QImode data
15888 must go into Q_REGS. */
15889 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
15891 if (reg_class_subset_p (class, Q_REGS))
15893 if (reg_class_subset_p (Q_REGS, class))
15901 /* If we are copying between general and FP registers, we need a memory
15902 location. The same is true for SSE and MMX registers.
15904 The macro can't work reliably when one of the CLASSES is class containing
15905 registers from multiple units (SSE, MMX, integer). We avoid this by never
15906 combining those units in single alternative in the machine description.
15907 Ensure that this constraint holds to avoid unexpected surprises.
15909 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
15910 enforce these sanity checks. */
15913 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
15914 enum machine_mode mode, int strict)
15916 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
15917 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
15918 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
15919 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
15920 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
15921 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
15923 gcc_assert (!strict);
15927 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
15930 /* ??? This is a lie. We do have moves between mmx/general, and for
15931 mmx/sse2. But by saying we need secondary memory we discourage the
15932 register allocator from using the mmx registers unless needed. */
15933 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
15936 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
15938 /* SSE1 doesn't have any direct moves from other classes. */
15942 /* If the target says that inter-unit moves are more expensive
15943 than moving through memory, then don't generate them. */
15944 if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
15947 /* Between SSE and general, we have moves no larger than word size. */
15948 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
15951 /* ??? For the cost of one register reformat penalty, we could use
15952 the same instructions to move SFmode and DFmode data, but the
15953 relevant move patterns don't support those alternatives. */
15954 if (mode == SFmode || mode == DFmode)
15961 /* Return true if the registers in CLASS cannot represent the change from
15962 modes FROM to TO. */
15965 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
15966 enum reg_class class)
15971 /* x87 registers can't do subreg at all, as all values are reformatted
15972 to extended precision. */
15973 if (MAYBE_FLOAT_CLASS_P (class))
15976 if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class))
15978 /* Vector registers do not support QI or HImode loads. If we don't
15979 disallow a change to these modes, reload will assume it's ok to
15980 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
15981 the vec_dupv4hi pattern. */
15982 if (GET_MODE_SIZE (from) < 4)
15985 /* Vector registers do not support subreg with nonzero offsets, which
15986 are otherwise valid for integer registers. Since we can't see
15987 whether we have a nonzero offset from here, prohibit all
15988 nonparadoxical subregs changing size. */
15989 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
15996 /* Return the cost of moving data from a register in class CLASS1 to
15997 one in class CLASS2.
15999 It is not required that the cost always equal 2 when FROM is the same as TO;
16000 on some machines it is expensive to move between registers if they are not
16001 general registers. */
16004 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
16005 enum reg_class class2)
16007 /* In case we require secondary memory, compute cost of the store followed
16008 by load. In order to avoid bad register allocation choices, we need
16009 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
16011 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
16015 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
16016 MEMORY_MOVE_COST (mode, class1, 1));
16017 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
16018 MEMORY_MOVE_COST (mode, class2, 1));
16020 /* In case of copying from general_purpose_register we may emit multiple
16021 stores followed by single load causing memory size mismatch stall.
16022 Count this as arbitrarily high cost of 20. */
16023 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
16026 /* In the case of FP/MMX moves, the registers actually overlap, and we
16027 have to switch modes in order to treat them differently. */
16028 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
16029 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
16035 /* Moves between SSE/MMX and integer unit are expensive. */
16036 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
16037 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
16038 return ix86_cost->mmxsse_to_integer;
16039 if (MAYBE_FLOAT_CLASS_P (class1))
16040 return ix86_cost->fp_move;
16041 if (MAYBE_SSE_CLASS_P (class1))
16042 return ix86_cost->sse_move;
16043 if (MAYBE_MMX_CLASS_P (class1))
16044 return ix86_cost->mmx_move;
16048 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
16051 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
16053 /* Flags and only flags can only hold CCmode values. */
16054 if (CC_REGNO_P (regno))
16055 return GET_MODE_CLASS (mode) == MODE_CC;
16056 if (GET_MODE_CLASS (mode) == MODE_CC
16057 || GET_MODE_CLASS (mode) == MODE_RANDOM
16058 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
16060 if (FP_REGNO_P (regno))
16061 return VALID_FP_MODE_P (mode);
16062 if (SSE_REGNO_P (regno))
16064 /* We implement the move patterns for all vector modes into and
16065 out of SSE registers, even when no operation instructions
16067 return (VALID_SSE_REG_MODE (mode)
16068 || VALID_SSE2_REG_MODE (mode)
16069 || VALID_MMX_REG_MODE (mode)
16070 || VALID_MMX_REG_MODE_3DNOW (mode));
16072 if (MMX_REGNO_P (regno))
16074 /* We implement the move patterns for 3DNOW modes even in MMX mode,
16075 so if the register is available at all, then we can move data of
16076 the given mode into or out of it. */
16077 return (VALID_MMX_REG_MODE (mode)
16078 || VALID_MMX_REG_MODE_3DNOW (mode));
16081 if (mode == QImode)
16083 /* Take care for QImode values - they can be in non-QI regs,
16084 but then they do cause partial register stalls. */
16085 if (regno < 4 || TARGET_64BIT)
16087 if (!TARGET_PARTIAL_REG_STALL)
16089 return reload_in_progress || reload_completed;
16091 /* We handle both integer and floats in the general purpose registers. */
16092 else if (VALID_INT_MODE_P (mode))
16094 else if (VALID_FP_MODE_P (mode))
16096 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
16097 on to use that value in smaller contexts, this can easily force a
16098 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
16099 supporting DImode, allow it. */
16100 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
16106 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
16107 tieable integer mode. */
16110 ix86_tieable_integer_mode_p (enum machine_mode mode)
16119 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
16122 return TARGET_64BIT;
16129 /* Return true if MODE1 is accessible in a register that can hold MODE2
16130 without copying. That is, all register classes that can hold MODE2
16131 can also hold MODE1. */
16134 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
16136 if (mode1 == mode2)
16139 if (ix86_tieable_integer_mode_p (mode1)
16140 && ix86_tieable_integer_mode_p (mode2))
16143 /* MODE2 being XFmode implies fp stack or general regs, which means we
16144 can tie any smaller floating point modes to it. Note that we do not
16145 tie this with TFmode. */
16146 if (mode2 == XFmode)
16147 return mode1 == SFmode || mode1 == DFmode;
16149 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
16150 that we can tie it with SFmode. */
16151 if (mode2 == DFmode)
16152 return mode1 == SFmode;
16154 /* If MODE2 is only appropriate for an SSE register, then tie with
16155 any other mode acceptable to SSE registers. */
16156 if (GET_MODE_SIZE (mode2) >= 8
16157 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
16158 return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1);
16160 /* If MODE2 is appropriate for an MMX (or SSE) register, then tie
16161 with any other mode acceptable to MMX registers. */
16162 if (GET_MODE_SIZE (mode2) == 8
16163 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
16164 return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1);
16169 /* Return the cost of moving data of mode M between a
16170 register and memory. A value of 2 is the default; this cost is
16171 relative to those in `REGISTER_MOVE_COST'.
16173 If moving between registers and memory is more expensive than
16174 between two registers, you should define this macro to express the
16177 Model also increased moving costs of QImode registers in non
16181 ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
16183 if (FLOAT_CLASS_P (class))
16200 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
16202 if (SSE_CLASS_P (class))
16205 switch (GET_MODE_SIZE (mode))
16219 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
16221 if (MMX_CLASS_P (class))
16224 switch (GET_MODE_SIZE (mode))
16235 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
16237 switch (GET_MODE_SIZE (mode))
16241 return (Q_CLASS_P (class) ? ix86_cost->int_load[0]
16242 : ix86_cost->movzbl_load);
16244 return (Q_CLASS_P (class) ? ix86_cost->int_store[0]
16245 : ix86_cost->int_store[0] + 4);
16248 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
16250 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
16251 if (mode == TFmode)
16253 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
16254 * (((int) GET_MODE_SIZE (mode)
16255 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
16259 /* Compute a (partial) cost for rtx X. Return true if the complete
16260 cost has been computed, and false if subexpressions should be
16261 scanned. In either case, *TOTAL contains the cost result. */
16264 ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
16266 enum machine_mode mode = GET_MODE (x);
16274 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
16276 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
16278 else if (flag_pic && SYMBOLIC_CONST (x)
16280 || (!GET_CODE (x) != LABEL_REF
16281 && (GET_CODE (x) != SYMBOL_REF
16282 || !SYMBOL_REF_LOCAL_P (x)))))
16289 if (mode == VOIDmode)
16292 switch (standard_80387_constant_p (x))
16297 default: /* Other constants */
16302 /* Start with (MEM (SYMBOL_REF)), since that's where
16303 it'll probably end up. Add a penalty for size. */
16304 *total = (COSTS_N_INSNS (1)
16305 + (flag_pic != 0 && !TARGET_64BIT)
16306 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
16312 /* The zero extensions is often completely free on x86_64, so make
16313 it as cheap as possible. */
16314 if (TARGET_64BIT && mode == DImode
16315 && GET_MODE (XEXP (x, 0)) == SImode)
16317 else if (TARGET_ZERO_EXTEND_WITH_AND)
16318 *total = COSTS_N_INSNS (ix86_cost->add);
16320 *total = COSTS_N_INSNS (ix86_cost->movzx);
16324 *total = COSTS_N_INSNS (ix86_cost->movsx);
16328 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16329 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
16331 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16334 *total = COSTS_N_INSNS (ix86_cost->add);
16337 if ((value == 2 || value == 3)
16338 && ix86_cost->lea <= ix86_cost->shift_const)
16340 *total = COSTS_N_INSNS (ix86_cost->lea);
16350 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
16352 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16354 if (INTVAL (XEXP (x, 1)) > 32)
16355 *total = COSTS_N_INSNS(ix86_cost->shift_const + 2);
16357 *total = COSTS_N_INSNS(ix86_cost->shift_const * 2);
16361 if (GET_CODE (XEXP (x, 1)) == AND)
16362 *total = COSTS_N_INSNS(ix86_cost->shift_var * 2);
16364 *total = COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2);
16369 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16370 *total = COSTS_N_INSNS (ix86_cost->shift_const);
16372 *total = COSTS_N_INSNS (ix86_cost->shift_var);
16377 if (FLOAT_MODE_P (mode))
16379 *total = COSTS_N_INSNS (ix86_cost->fmul);
16384 rtx op0 = XEXP (x, 0);
16385 rtx op1 = XEXP (x, 1);
16387 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16389 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16390 for (nbits = 0; value != 0; value &= value - 1)
16394 /* This is arbitrary. */
16397 /* Compute costs correctly for widening multiplication. */
16398 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
16399 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
16400 == GET_MODE_SIZE (mode))
16402 int is_mulwiden = 0;
16403 enum machine_mode inner_mode = GET_MODE (op0);
16405 if (GET_CODE (op0) == GET_CODE (op1))
16406 is_mulwiden = 1, op1 = XEXP (op1, 0);
16407 else if (GET_CODE (op1) == CONST_INT)
16409 if (GET_CODE (op0) == SIGN_EXTEND)
16410 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
16413 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
16417 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
16420 *total = COSTS_N_INSNS (ix86_cost->mult_init[MODE_INDEX (mode)]
16421 + nbits * ix86_cost->mult_bit)
16422 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code);
16431 if (FLOAT_MODE_P (mode))
16432 *total = COSTS_N_INSNS (ix86_cost->fdiv);
16434 *total = COSTS_N_INSNS (ix86_cost->divide[MODE_INDEX (mode)]);
16438 if (FLOAT_MODE_P (mode))
16439 *total = COSTS_N_INSNS (ix86_cost->fadd);
16440 else if (GET_MODE_CLASS (mode) == MODE_INT
16441 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
16443 if (GET_CODE (XEXP (x, 0)) == PLUS
16444 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
16445 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
16446 && CONSTANT_P (XEXP (x, 1)))
16448 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
16449 if (val == 2 || val == 4 || val == 8)
16451 *total = COSTS_N_INSNS (ix86_cost->lea);
16452 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16453 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
16455 *total += rtx_cost (XEXP (x, 1), outer_code);
16459 else if (GET_CODE (XEXP (x, 0)) == MULT
16460 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
16462 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
16463 if (val == 2 || val == 4 || val == 8)
16465 *total = COSTS_N_INSNS (ix86_cost->lea);
16466 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16467 *total += rtx_cost (XEXP (x, 1), outer_code);
16471 else if (GET_CODE (XEXP (x, 0)) == PLUS)
16473 *total = COSTS_N_INSNS (ix86_cost->lea);
16474 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16475 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16476 *total += rtx_cost (XEXP (x, 1), outer_code);
16483 if (FLOAT_MODE_P (mode))
16485 *total = COSTS_N_INSNS (ix86_cost->fadd);
16493 if (!TARGET_64BIT && mode == DImode)
16495 *total = (COSTS_N_INSNS (ix86_cost->add) * 2
16496 + (rtx_cost (XEXP (x, 0), outer_code)
16497 << (GET_MODE (XEXP (x, 0)) != DImode))
16498 + (rtx_cost (XEXP (x, 1), outer_code)
16499 << (GET_MODE (XEXP (x, 1)) != DImode)));
16505 if (FLOAT_MODE_P (mode))
16507 *total = COSTS_N_INSNS (ix86_cost->fchs);
16513 if (!TARGET_64BIT && mode == DImode)
16514 *total = COSTS_N_INSNS (ix86_cost->add * 2);
16516 *total = COSTS_N_INSNS (ix86_cost->add);
16520 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
16521 && XEXP (XEXP (x, 0), 1) == const1_rtx
16522 && GET_CODE (XEXP (XEXP (x, 0), 2)) == CONST_INT
16523 && XEXP (x, 1) == const0_rtx)
16525 /* This kind of construct is implemented using test[bwl].
16526 Treat it as if we had an AND. */
16527 *total = (COSTS_N_INSNS (ix86_cost->add)
16528 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
16529 + rtx_cost (const1_rtx, outer_code));
16535 if (!TARGET_SSE_MATH
16537 || (mode == DFmode && !TARGET_SSE2))
16542 if (FLOAT_MODE_P (mode))
16543 *total = COSTS_N_INSNS (ix86_cost->fabs);
16547 if (FLOAT_MODE_P (mode))
16548 *total = COSTS_N_INSNS (ix86_cost->fsqrt);
16552 if (XINT (x, 1) == UNSPEC_TP)
16563 static int current_machopic_label_num;
16565 /* Given a symbol name and its associated stub, write out the
16566 definition of the stub. */
16569 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16571 unsigned int length;
16572 char *binder_name, *symbol_name, lazy_ptr_name[32];
16573 int label = ++current_machopic_label_num;
16575 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16576 symb = (*targetm.strip_name_encoding) (symb);
16578 length = strlen (stub);
16579 binder_name = alloca (length + 32);
16580 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
16582 length = strlen (symb);
16583 symbol_name = alloca (length + 32);
16584 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16586 sprintf (lazy_ptr_name, "L%d$lz", label);
16589 switch_to_section (machopic_picsymbol_stub_section);
16591 switch_to_section (machopic_symbol_stub_section);
16593 fprintf (file, "%s:\n", stub);
16594 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16598 fprintf (file, "\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n", label, label);
16599 fprintf (file, "\tmovl %s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
16600 fprintf (file, "\tjmp %%edx\n");
16603 fprintf (file, "\tjmp *%s\n", lazy_ptr_name);
16605 fprintf (file, "%s:\n", binder_name);
16609 fprintf (file, "\tlea %s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
16610 fprintf (file, "\tpushl %%eax\n");
16613 fprintf (file, "\t pushl $%s\n", lazy_ptr_name);
16615 fprintf (file, "\tjmp dyld_stub_binding_helper\n");
16617 switch_to_section (machopic_lazy_symbol_ptr_section);
16618 fprintf (file, "%s:\n", lazy_ptr_name);
16619 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16620 fprintf (file, "\t.long %s\n", binder_name);
16622 #endif /* TARGET_MACHO */
16624 /* Order the registers for register allocator. */
16627 x86_order_regs_for_local_alloc (void)
16632 /* First allocate the local general purpose registers. */
16633 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16634 if (GENERAL_REGNO_P (i) && call_used_regs[i])
16635 reg_alloc_order [pos++] = i;
16637 /* Global general purpose registers. */
16638 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16639 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
16640 reg_alloc_order [pos++] = i;
16642 /* x87 registers come first in case we are doing FP math
16644 if (!TARGET_SSE_MATH)
16645 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
16646 reg_alloc_order [pos++] = i;
16648 /* SSE registers. */
16649 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
16650 reg_alloc_order [pos++] = i;
16651 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
16652 reg_alloc_order [pos++] = i;
16654 /* x87 registers. */
16655 if (TARGET_SSE_MATH)
16656 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
16657 reg_alloc_order [pos++] = i;
16659 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
16660 reg_alloc_order [pos++] = i;
16662 /* Initialize the rest of array as we do not allocate some registers
16664 while (pos < FIRST_PSEUDO_REGISTER)
16665 reg_alloc_order [pos++] = 0;
16668 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
16669 struct attribute_spec.handler. */
16671 ix86_handle_struct_attribute (tree *node, tree name,
16672 tree args ATTRIBUTE_UNUSED,
16673 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
16676 if (DECL_P (*node))
16678 if (TREE_CODE (*node) == TYPE_DECL)
16679 type = &TREE_TYPE (*node);
16684 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
16685 || TREE_CODE (*type) == UNION_TYPE)))
16687 warning (OPT_Wattributes, "%qs attribute ignored",
16688 IDENTIFIER_POINTER (name));
16689 *no_add_attrs = true;
16692 else if ((is_attribute_p ("ms_struct", name)
16693 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
16694 || ((is_attribute_p ("gcc_struct", name)
16695 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
16697 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
16698 IDENTIFIER_POINTER (name));
16699 *no_add_attrs = true;
16706 ix86_ms_bitfield_layout_p (tree record_type)
16708 return (TARGET_MS_BITFIELD_LAYOUT &&
16709 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
16710 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
16713 /* Returns an expression indicating where the this parameter is
16714 located on entry to the FUNCTION. */
16717 x86_this_parameter (tree function)
16719 tree type = TREE_TYPE (function);
16723 int n = aggregate_value_p (TREE_TYPE (type), type) != 0;
16724 return gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
16727 if (ix86_function_regparm (type, function) > 0)
16731 parm = TYPE_ARG_TYPES (type);
16732 /* Figure out whether or not the function has a variable number of
16734 for (; parm; parm = TREE_CHAIN (parm))
16735 if (TREE_VALUE (parm) == void_type_node)
16737 /* If not, the this parameter is in the first argument. */
16741 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
16743 return gen_rtx_REG (SImode, regno);
16747 if (aggregate_value_p (TREE_TYPE (type), type))
16748 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
16750 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
16753 /* Determine whether x86_output_mi_thunk can succeed. */
16756 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
16757 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
16758 HOST_WIDE_INT vcall_offset, tree function)
16760 /* 64-bit can handle anything. */
16764 /* For 32-bit, everything's fine if we have one free register. */
16765 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
16768 /* Need a free register for vcall_offset. */
16772 /* Need a free register for GOT references. */
16773 if (flag_pic && !(*targetm.binds_local_p) (function))
16776 /* Otherwise ok. */
16780 /* Output the assembler code for a thunk function. THUNK_DECL is the
16781 declaration for the thunk function itself, FUNCTION is the decl for
16782 the target function. DELTA is an immediate constant offset to be
16783 added to THIS. If VCALL_OFFSET is nonzero, the word at
16784 *(*this + vcall_offset) should be added to THIS. */
16787 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
16788 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
16789 HOST_WIDE_INT vcall_offset, tree function)
16792 rtx this = x86_this_parameter (function);
16795 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
16796 pull it in now and let DELTA benefit. */
16799 else if (vcall_offset)
16801 /* Put the this parameter into %eax. */
16803 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
16804 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16807 this_reg = NULL_RTX;
16809 /* Adjust the this parameter by a fixed constant. */
16812 xops[0] = GEN_INT (delta);
16813 xops[1] = this_reg ? this_reg : this;
16816 if (!x86_64_general_operand (xops[0], DImode))
16818 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
16820 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
16824 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
16827 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
16830 /* Adjust the this parameter by a value stored in the vtable. */
16834 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
16837 int tmp_regno = 2 /* ECX */;
16838 if (lookup_attribute ("fastcall",
16839 TYPE_ATTRIBUTES (TREE_TYPE (function))))
16840 tmp_regno = 0 /* EAX */;
16841 tmp = gen_rtx_REG (SImode, tmp_regno);
16844 xops[0] = gen_rtx_MEM (Pmode, this_reg);
16847 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
16849 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16851 /* Adjust the this parameter. */
16852 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
16853 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
16855 rtx tmp2 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
16856 xops[0] = GEN_INT (vcall_offset);
16858 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
16859 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
16861 xops[1] = this_reg;
16863 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
16865 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
16868 /* If necessary, drop THIS back to its stack slot. */
16869 if (this_reg && this_reg != this)
16871 xops[0] = this_reg;
16873 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16876 xops[0] = XEXP (DECL_RTL (function), 0);
16879 if (!flag_pic || (*targetm.binds_local_p) (function))
16880 output_asm_insn ("jmp\t%P0", xops);
16883 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
16884 tmp = gen_rtx_CONST (Pmode, tmp);
16885 tmp = gen_rtx_MEM (QImode, tmp);
16887 output_asm_insn ("jmp\t%A0", xops);
16892 if (!flag_pic || (*targetm.binds_local_p) (function))
16893 output_asm_insn ("jmp\t%P0", xops);
16898 rtx sym_ref = XEXP (DECL_RTL (function), 0);
16899 tmp = (gen_rtx_SYMBOL_REF
16901 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
16902 tmp = gen_rtx_MEM (QImode, tmp);
16904 output_asm_insn ("jmp\t%0", xops);
16907 #endif /* TARGET_MACHO */
16909 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
16910 output_set_got (tmp);
16913 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
16914 output_asm_insn ("jmp\t{*}%1", xops);
16920 x86_file_start (void)
16922 default_file_start ();
16923 if (X86_FILE_START_VERSION_DIRECTIVE)
16924 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
16925 if (X86_FILE_START_FLTUSED)
16926 fputs ("\t.global\t__fltused\n", asm_out_file);
16927 if (ix86_asm_dialect == ASM_INTEL)
16928 fputs ("\t.intel_syntax\n", asm_out_file);
16932 x86_field_alignment (tree field, int computed)
16934 enum machine_mode mode;
16935 tree type = TREE_TYPE (field);
16937 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
16939 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
16940 ? get_inner_array_type (type) : type);
16941 if (mode == DFmode || mode == DCmode
16942 || GET_MODE_CLASS (mode) == MODE_INT
16943 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
16944 return MIN (32, computed);
16948 /* Output assembler code to FILE to increment profiler label # LABELNO
16949 for profiling a function entry. */
16951 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
16956 #ifndef NO_PROFILE_COUNTERS
16957 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
16959 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
16963 #ifndef NO_PROFILE_COUNTERS
16964 fprintf (file, "\tmovq\t$%sP%d,%%r11\n", LPREFIX, labelno);
16966 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
16970 #ifndef NO_PROFILE_COUNTERS
16971 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
16972 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
16974 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
16978 #ifndef NO_PROFILE_COUNTERS
16979 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
16980 PROFILE_COUNT_REGISTER);
16982 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
16986 /* We don't have exact information about the insn sizes, but we may assume
16987 quite safely that we are informed about all 1 byte insns and memory
16988 address sizes. This is enough to eliminate unnecessary padding in
16992 min_insn_size (rtx insn)
16996 if (!INSN_P (insn) || !active_insn_p (insn))
16999 /* Discard alignments we've emit and jump instructions. */
17000 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
17001 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
17003 if (GET_CODE (insn) == JUMP_INSN
17004 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
17005 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
17008 /* Important case - calls are always 5 bytes.
17009 It is common to have many calls in the row. */
17010 if (GET_CODE (insn) == CALL_INSN
17011 && symbolic_reference_mentioned_p (PATTERN (insn))
17012 && !SIBLING_CALL_P (insn))
17014 if (get_attr_length (insn) <= 1)
17017 /* For normal instructions we may rely on the sizes of addresses
17018 and the presence of symbol to require 4 bytes of encoding.
17019 This is not the case for jumps where references are PC relative. */
17020 if (GET_CODE (insn) != JUMP_INSN)
17022 l = get_attr_length_address (insn);
17023 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
17032 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
17036 ix86_avoid_jump_misspredicts (void)
17038 rtx insn, start = get_insns ();
17039 int nbytes = 0, njumps = 0;
17042 /* Look for all minimal intervals of instructions containing 4 jumps.
17043 The intervals are bounded by START and INSN. NBYTES is the total
17044 size of instructions in the interval including INSN and not including
17045 START. When the NBYTES is smaller than 16 bytes, it is possible
17046 that the end of START and INSN ends up in the same 16byte page.
17048 The smallest offset in the page INSN can start is the case where START
17049 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
17050 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
17052 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
17055 nbytes += min_insn_size (insn);
17057 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
17058 INSN_UID (insn), min_insn_size (insn));
17059 if ((GET_CODE (insn) == JUMP_INSN
17060 && GET_CODE (PATTERN (insn)) != ADDR_VEC
17061 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
17062 || GET_CODE (insn) == CALL_INSN)
17069 start = NEXT_INSN (start);
17070 if ((GET_CODE (start) == JUMP_INSN
17071 && GET_CODE (PATTERN (start)) != ADDR_VEC
17072 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
17073 || GET_CODE (start) == CALL_INSN)
17074 njumps--, isjump = 1;
17077 nbytes -= min_insn_size (start);
17079 gcc_assert (njumps >= 0);
17081 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
17082 INSN_UID (start), INSN_UID (insn), nbytes);
17084 if (njumps == 3 && isjump && nbytes < 16)
17086 int padsize = 15 - nbytes + min_insn_size (insn);
17089 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
17090 INSN_UID (insn), padsize);
17091 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
17096 /* AMD Athlon works faster
17097 when RET is not destination of conditional jump or directly preceded
17098 by other jump instruction. We avoid the penalty by inserting NOP just
17099 before the RET instructions in such cases. */
17101 ix86_pad_returns (void)
17106 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
17108 basic_block bb = e->src;
17109 rtx ret = BB_END (bb);
17111 bool replace = false;
17113 if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN
17114 || !maybe_hot_bb_p (bb))
17116 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
17117 if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL)
17119 if (prev && GET_CODE (prev) == CODE_LABEL)
17124 FOR_EACH_EDGE (e, ei, bb->preds)
17125 if (EDGE_FREQUENCY (e) && e->src->index >= 0
17126 && !(e->flags & EDGE_FALLTHRU))
17131 prev = prev_active_insn (ret);
17133 && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
17134 || GET_CODE (prev) == CALL_INSN))
17136 /* Empty functions get branch mispredict even when the jump destination
17137 is not visible to us. */
17138 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
17143 emit_insn_before (gen_return_internal_long (), ret);
17149 /* Implement machine specific optimizations. We implement padding of returns
17150 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
17154 if (TARGET_ATHLON_K8 && optimize && !optimize_size)
17155 ix86_pad_returns ();
17156 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
17157 ix86_avoid_jump_misspredicts ();
17160 /* Return nonzero when QImode register that must be represented via REX prefix
17163 x86_extended_QIreg_mentioned_p (rtx insn)
17166 extract_insn_cached (insn);
17167 for (i = 0; i < recog_data.n_operands; i++)
17168 if (REG_P (recog_data.operand[i])
17169 && REGNO (recog_data.operand[i]) >= 4)
17174 /* Return nonzero when P points to register encoded via REX prefix.
17175 Called via for_each_rtx. */
17177 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
17179 unsigned int regno;
17182 regno = REGNO (*p);
17183 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
17186 /* Return true when INSN mentions register that must be encoded using REX
17189 x86_extended_reg_mentioned_p (rtx insn)
17191 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
17194 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
17195 optabs would emit if we didn't have TFmode patterns. */
17198 x86_emit_floatuns (rtx operands[2])
17200 rtx neglab, donelab, i0, i1, f0, in, out;
17201 enum machine_mode mode, inmode;
17203 inmode = GET_MODE (operands[1]);
17204 gcc_assert (inmode == SImode || inmode == DImode);
17207 in = force_reg (inmode, operands[1]);
17208 mode = GET_MODE (out);
17209 neglab = gen_label_rtx ();
17210 donelab = gen_label_rtx ();
17211 i1 = gen_reg_rtx (Pmode);
17212 f0 = gen_reg_rtx (mode);
17214 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, Pmode, 0, neglab);
17216 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
17217 emit_jump_insn (gen_jump (donelab));
17220 emit_label (neglab);
17222 i0 = expand_simple_binop (Pmode, LSHIFTRT, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17223 i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17224 i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
17225 expand_float (f0, i0, 0);
17226 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
17228 emit_label (donelab);
17231 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17232 with all elements equal to VAR. Return true if successful. */
17235 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
17236 rtx target, rtx val)
17238 enum machine_mode smode, wsmode, wvmode;
17245 if (!mmx_ok && !TARGET_SSE)
17253 val = force_reg (GET_MODE_INNER (mode), val);
17254 x = gen_rtx_VEC_DUPLICATE (mode, val);
17255 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17261 if (TARGET_SSE || TARGET_3DNOW_A)
17263 val = gen_lowpart (SImode, val);
17264 x = gen_rtx_TRUNCATE (HImode, val);
17265 x = gen_rtx_VEC_DUPLICATE (mode, x);
17266 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17295 /* Replicate the value once into the next wider mode and recurse. */
17296 val = convert_modes (wsmode, smode, val, true);
17297 x = expand_simple_binop (wsmode, ASHIFT, val,
17298 GEN_INT (GET_MODE_BITSIZE (smode)),
17299 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17300 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
17302 x = gen_reg_rtx (wvmode);
17303 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
17304 gcc_unreachable ();
17305 emit_move_insn (target, gen_lowpart (mode, x));
17313 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17314 whose low element is VAR, and other elements are zero. Return true
17318 ix86_expand_vector_init_low_nonzero (bool mmx_ok, enum machine_mode mode,
17319 rtx target, rtx var)
17321 enum machine_mode vsimode;
17328 if (!mmx_ok && !TARGET_SSE)
17334 var = force_reg (GET_MODE_INNER (mode), var);
17335 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
17336 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17341 var = force_reg (GET_MODE_INNER (mode), var);
17342 x = gen_rtx_VEC_DUPLICATE (mode, var);
17343 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
17344 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17349 vsimode = V4SImode;
17355 vsimode = V2SImode;
17358 /* Zero extend the variable element to SImode and recurse. */
17359 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
17361 x = gen_reg_rtx (vsimode);
17362 if (!ix86_expand_vector_init_low_nonzero (mmx_ok, vsimode, x, var))
17363 gcc_unreachable ();
17365 emit_move_insn (target, gen_lowpart (mode, x));
17373 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17374 consisting of the values in VALS. It is known that all elements
17375 except ONE_VAR are constants. Return true if successful. */
17378 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
17379 rtx target, rtx vals, int one_var)
17381 rtx var = XVECEXP (vals, 0, one_var);
17382 enum machine_mode wmode;
17385 const_vec = copy_rtx (vals);
17386 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
17387 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
17395 /* For the two element vectors, it's just as easy to use
17396 the general case. */
17412 /* There's no way to set one QImode entry easily. Combine
17413 the variable value with its adjacent constant value, and
17414 promote to an HImode set. */
17415 x = XVECEXP (vals, 0, one_var ^ 1);
17418 var = convert_modes (HImode, QImode, var, true);
17419 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
17420 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17421 x = GEN_INT (INTVAL (x) & 0xff);
17425 var = convert_modes (HImode, QImode, var, true);
17426 x = gen_int_mode (INTVAL (x) << 8, HImode);
17428 if (x != const0_rtx)
17429 var = expand_simple_binop (HImode, IOR, var, x, var,
17430 1, OPTAB_LIB_WIDEN);
17432 x = gen_reg_rtx (wmode);
17433 emit_move_insn (x, gen_lowpart (wmode, const_vec));
17434 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
17436 emit_move_insn (target, gen_lowpart (mode, x));
17443 emit_move_insn (target, const_vec);
17444 ix86_expand_vector_set (mmx_ok, target, var, one_var);
17448 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
17449 all values variable, and none identical. */
17452 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
17453 rtx target, rtx vals)
17455 enum machine_mode half_mode = GET_MODE_INNER (mode);
17456 rtx op0 = NULL, op1 = NULL;
17457 bool use_vec_concat = false;
17463 if (!mmx_ok && !TARGET_SSE)
17469 /* For the two element vectors, we always implement VEC_CONCAT. */
17470 op0 = XVECEXP (vals, 0, 0);
17471 op1 = XVECEXP (vals, 0, 1);
17472 use_vec_concat = true;
17476 half_mode = V2SFmode;
17479 half_mode = V2SImode;
17485 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
17486 Recurse to load the two halves. */
17488 op0 = gen_reg_rtx (half_mode);
17489 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
17490 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
17492 op1 = gen_reg_rtx (half_mode);
17493 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
17494 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
17496 use_vec_concat = true;
17507 gcc_unreachable ();
17510 if (use_vec_concat)
17512 if (!register_operand (op0, half_mode))
17513 op0 = force_reg (half_mode, op0);
17514 if (!register_operand (op1, half_mode))
17515 op1 = force_reg (half_mode, op1);
17517 emit_insn (gen_rtx_SET (VOIDmode, target,
17518 gen_rtx_VEC_CONCAT (mode, op0, op1)));
17522 int i, j, n_elts, n_words, n_elt_per_word;
17523 enum machine_mode inner_mode;
17524 rtx words[4], shift;
17526 inner_mode = GET_MODE_INNER (mode);
17527 n_elts = GET_MODE_NUNITS (mode);
17528 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
17529 n_elt_per_word = n_elts / n_words;
17530 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
17532 for (i = 0; i < n_words; ++i)
17534 rtx word = NULL_RTX;
17536 for (j = 0; j < n_elt_per_word; ++j)
17538 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
17539 elt = convert_modes (word_mode, inner_mode, elt, true);
17545 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
17546 word, 1, OPTAB_LIB_WIDEN);
17547 word = expand_simple_binop (word_mode, IOR, word, elt,
17548 word, 1, OPTAB_LIB_WIDEN);
17556 emit_move_insn (target, gen_lowpart (mode, words[0]));
17557 else if (n_words == 2)
17559 rtx tmp = gen_reg_rtx (mode);
17560 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
17561 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
17562 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
17563 emit_move_insn (target, tmp);
17565 else if (n_words == 4)
17567 rtx tmp = gen_reg_rtx (V4SImode);
17568 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
17569 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
17570 emit_move_insn (target, gen_lowpart (mode, tmp));
17573 gcc_unreachable ();
17577 /* Initialize vector TARGET via VALS. Suppress the use of MMX
17578 instructions unless MMX_OK is true. */
17581 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
17583 enum machine_mode mode = GET_MODE (target);
17584 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17585 int n_elts = GET_MODE_NUNITS (mode);
17586 int n_var = 0, one_var = -1;
17587 bool all_same = true, all_const_zero = true;
17591 for (i = 0; i < n_elts; ++i)
17593 x = XVECEXP (vals, 0, i);
17594 if (!CONSTANT_P (x))
17595 n_var++, one_var = i;
17596 else if (x != CONST0_RTX (inner_mode))
17597 all_const_zero = false;
17598 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17602 /* Constants are best loaded from the constant pool. */
17605 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
17609 /* If all values are identical, broadcast the value. */
17611 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
17612 XVECEXP (vals, 0, 0)))
17615 /* Values where only one field is non-constant are best loaded from
17616 the pool and overwritten via move later. */
17619 if (all_const_zero && one_var == 0
17620 && ix86_expand_vector_init_low_nonzero (mmx_ok, mode, target,
17621 XVECEXP (vals, 0, 0)))
17624 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
17628 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
17632 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
17634 enum machine_mode mode = GET_MODE (target);
17635 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17636 bool use_vec_merge = false;
17645 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
17646 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
17648 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
17650 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
17651 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17661 /* For the two element vectors, we implement a VEC_CONCAT with
17662 the extraction of the other element. */
17664 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
17665 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
17668 op0 = val, op1 = tmp;
17670 op0 = tmp, op1 = val;
17672 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
17673 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17681 use_vec_merge = true;
17685 /* tmp = target = A B C D */
17686 tmp = copy_to_reg (target);
17687 /* target = A A B B */
17688 emit_insn (gen_sse_unpcklps (target, target, target));
17689 /* target = X A B B */
17690 ix86_expand_vector_set (false, target, val, 0);
17691 /* target = A X C D */
17692 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17693 GEN_INT (1), GEN_INT (0),
17694 GEN_INT (2+4), GEN_INT (3+4)));
17698 /* tmp = target = A B C D */
17699 tmp = copy_to_reg (target);
17700 /* tmp = X B C D */
17701 ix86_expand_vector_set (false, tmp, val, 0);
17702 /* target = A B X D */
17703 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17704 GEN_INT (0), GEN_INT (1),
17705 GEN_INT (0+4), GEN_INT (3+4)));
17709 /* tmp = target = A B C D */
17710 tmp = copy_to_reg (target);
17711 /* tmp = X B C D */
17712 ix86_expand_vector_set (false, tmp, val, 0);
17713 /* target = A B X D */
17714 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17715 GEN_INT (0), GEN_INT (1),
17716 GEN_INT (2+4), GEN_INT (0+4)));
17720 gcc_unreachable ();
17725 /* Element 0 handled by vec_merge below. */
17728 use_vec_merge = true;
17734 /* With SSE2, use integer shuffles to swap element 0 and ELT,
17735 store into element 0, then shuffle them back. */
17739 order[0] = GEN_INT (elt);
17740 order[1] = const1_rtx;
17741 order[2] = const2_rtx;
17742 order[3] = GEN_INT (3);
17743 order[elt] = const0_rtx;
17745 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
17746 order[1], order[2], order[3]));
17748 ix86_expand_vector_set (false, target, val, 0);
17750 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
17751 order[1], order[2], order[3]));
17755 /* For SSE1, we have to reuse the V4SF code. */
17756 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
17757 gen_lowpart (SFmode, val), elt);
17762 use_vec_merge = TARGET_SSE2;
17765 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
17776 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
17777 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
17778 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17782 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
17784 emit_move_insn (mem, target);
17786 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
17787 emit_move_insn (tmp, val);
17789 emit_move_insn (target, mem);
17794 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
17796 enum machine_mode mode = GET_MODE (vec);
17797 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17798 bool use_vec_extr = false;
17811 use_vec_extr = true;
17823 tmp = gen_reg_rtx (mode);
17824 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
17825 GEN_INT (elt), GEN_INT (elt),
17826 GEN_INT (elt+4), GEN_INT (elt+4)));
17830 tmp = gen_reg_rtx (mode);
17831 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
17835 gcc_unreachable ();
17838 use_vec_extr = true;
17853 tmp = gen_reg_rtx (mode);
17854 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
17855 GEN_INT (elt), GEN_INT (elt),
17856 GEN_INT (elt), GEN_INT (elt)));
17860 tmp = gen_reg_rtx (mode);
17861 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
17865 gcc_unreachable ();
17868 use_vec_extr = true;
17873 /* For SSE1, we have to reuse the V4SF code. */
17874 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
17875 gen_lowpart (V4SFmode, vec), elt);
17881 use_vec_extr = TARGET_SSE2;
17884 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
17889 /* ??? Could extract the appropriate HImode element and shift. */
17896 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
17897 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
17899 /* Let the rtl optimizers know about the zero extension performed. */
17900 if (inner_mode == HImode)
17902 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
17903 target = gen_lowpart (SImode, target);
17906 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17910 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
17912 emit_move_insn (mem, vec);
17914 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
17915 emit_move_insn (target, tmp);
17919 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
17920 pattern to reduce; DEST is the destination; IN is the input vector. */
17923 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
17925 rtx tmp1, tmp2, tmp3;
17927 tmp1 = gen_reg_rtx (V4SFmode);
17928 tmp2 = gen_reg_rtx (V4SFmode);
17929 tmp3 = gen_reg_rtx (V4SFmode);
17931 emit_insn (gen_sse_movhlps (tmp1, in, in));
17932 emit_insn (fn (tmp2, tmp1, in));
17934 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
17935 GEN_INT (1), GEN_INT (1),
17936 GEN_INT (1+4), GEN_INT (1+4)));
17937 emit_insn (fn (dest, tmp2, tmp3));
17940 /* Implements target hook vector_mode_supported_p. */
17942 ix86_vector_mode_supported_p (enum machine_mode mode)
17944 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
17946 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
17948 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
17950 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
17955 /* Worker function for TARGET_MD_ASM_CLOBBERS.
17957 We do this in the new i386 backend to maintain source compatibility
17958 with the old cc0-based compiler. */
17961 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
17962 tree inputs ATTRIBUTE_UNUSED,
17965 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
17967 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
17969 clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"),
17974 /* Return true if this goes in small data/bss. */
17977 ix86_in_large_data_p (tree exp)
17979 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
17982 /* Functions are never large data. */
17983 if (TREE_CODE (exp) == FUNCTION_DECL)
17986 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
17988 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
17989 if (strcmp (section, ".ldata") == 0
17990 || strcmp (section, ".lbss") == 0)
17996 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
17998 /* If this is an incomplete type with size 0, then we can't put it
17999 in data because it might be too big when completed. */
18000 if (!size || size > ix86_section_threshold)
18007 ix86_encode_section_info (tree decl, rtx rtl, int first)
18009 default_encode_section_info (decl, rtl, first);
18011 if (TREE_CODE (decl) == VAR_DECL
18012 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
18013 && ix86_in_large_data_p (decl))
18014 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
18017 /* Worker function for REVERSE_CONDITION. */
18020 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
18022 return (mode != CCFPmode && mode != CCFPUmode
18023 ? reverse_condition (code)
18024 : reverse_condition_maybe_unordered (code));
18027 /* Output code to perform an x87 FP register move, from OPERANDS[1]
18031 output_387_reg_move (rtx insn, rtx *operands)
18033 if (REG_P (operands[1])
18034 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
18036 if (REGNO (operands[0]) == FIRST_STACK_REG
18037 && TARGET_USE_FFREEP)
18038 return "ffreep\t%y0";
18039 return "fstp\t%y0";
18041 if (STACK_TOP_P (operands[0]))
18042 return "fld%z1\t%y1";
18046 /* Output code to perform a conditional jump to LABEL, if C2 flag in
18047 FP status register is set. */
18050 ix86_emit_fp_unordered_jump (rtx label)
18052 rtx reg = gen_reg_rtx (HImode);
18055 emit_insn (gen_x86_fnstsw_1 (reg));
18057 if (TARGET_USE_SAHF)
18059 emit_insn (gen_x86_sahf_1 (reg));
18061 temp = gen_rtx_REG (CCmode, FLAGS_REG);
18062 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
18066 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
18068 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18069 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
18072 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
18073 gen_rtx_LABEL_REF (VOIDmode, label),
18075 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
18076 emit_jump_insn (temp);
18079 /* Output code to perform a log1p XFmode calculation. */
18081 void ix86_emit_i387_log1p (rtx op0, rtx op1)
18083 rtx label1 = gen_label_rtx ();
18084 rtx label2 = gen_label_rtx ();
18086 rtx tmp = gen_reg_rtx (XFmode);
18087 rtx tmp2 = gen_reg_rtx (XFmode);
18089 emit_insn (gen_absxf2 (tmp, op1));
18090 emit_insn (gen_cmpxf (tmp,
18091 CONST_DOUBLE_FROM_REAL_VALUE (
18092 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
18094 emit_jump_insn (gen_bge (label1));
18096 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
18097 emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1));
18098 emit_jump (label2);
18100 emit_label (label1);
18101 emit_move_insn (tmp, CONST1_RTX (XFmode));
18102 emit_insn (gen_addxf3 (tmp, op1, tmp));
18103 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
18104 emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp));
18106 emit_label (label2);
18109 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
18112 i386_solaris_elf_named_section (const char *name, unsigned int flags,
18115 /* With Binutils 2.15, the "@unwind" marker must be specified on
18116 every occurrence of the ".eh_frame" section, not just the first
18119 && strcmp (name, ".eh_frame") == 0)
18121 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
18122 flags & SECTION_WRITE ? "aw" : "a");
18125 default_elf_asm_named_section (name, flags, decl);
18128 /* Return the mangling of TYPE if it is an extended fundamental type. */
18130 static const char *
18131 ix86_mangle_fundamental_type (tree type)
18133 switch (TYPE_MODE (type))
18136 /* __float128 is "g". */
18139 /* "long double" or __float80 is "e". */
18146 /* For 32-bit code we can save PIC register setup by using
18147 __stack_chk_fail_local hidden function instead of calling
18148 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
18149 register, so it is better to call __stack_chk_fail directly. */
18152 ix86_stack_protect_fail (void)
18154 return TARGET_64BIT
18155 ? default_external_stack_protect_fail ()
18156 : default_hidden_stack_protect_fail ();
18159 /* Select a format to encode pointers in exception handling data. CODE
18160 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
18161 true if the symbol may be affected by dynamic relocations.
18163 ??? All x86 object file formats are capable of representing this.
18164 After all, the relocation needed is the same as for the call insn.
18165 Whether or not a particular assembler allows us to enter such, I
18166 guess we'll have to see. */
18168 asm_preferred_eh_data_format (int code, int global)
18172 int type = DW_EH_PE_sdata8;
18174 || ix86_cmodel == CM_SMALL_PIC
18175 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
18176 type = DW_EH_PE_sdata4;
18177 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
18179 if (ix86_cmodel == CM_SMALL
18180 || (ix86_cmodel == CM_MEDIUM && code))
18181 return DW_EH_PE_udata4;
18182 return DW_EH_PE_absptr;
18185 #include "gt-i386.h"